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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_SYMBOL_V
`define SKY130_FD_SC_MS__A2BB2OI_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_SYMBOL_V
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "distributed" *) module CvtColor_1_sectorncg_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 2;
parameter AWIDTH = 3;
parameter MEM_SIZE = 6;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./CvtColor_1_sectorncg_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module CvtColor_1_sectorncg(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd6;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
CvtColor_1_sectorncg_rom CvtColor_1_sectorncg_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
/*
This block handles the autoincrement needed for bursting and detects
read responses
*/
`include "elink_regmap.v"
module erx_protocol (/*AUTOARG*/
// Outputs
erx_rdwr_access, erx_rr_access, erx_packet,
// Inputs
reset, rx_enable, clk, rx_packet, rx_burst, rx_access
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h800; //link id
// System reset input
input reset;
input rx_enable;//Enables receiver
// Parallel interface, 8 eLink bytes at a time
input clk;
input [PW-1:0] rx_packet;
input rx_burst;
input rx_access;
// Output to MMU / filter
output erx_rdwr_access;
output erx_rr_access;
output [PW-1:0] erx_packet;
//wires
reg [31:0] dstaddr_reg;
wire [31:0] dstaddr_next;
wire [31:0] dstaddr_mux;
reg erx_rdwr_access;
reg erx_rr_access;
reg [PW-1:0] erx_packet;
wire [11:0] myid;
wire [31:0] rx_addr;
wire read_response;
//parsing inputs
assign myid[11:0] = ID;
assign rx_addr[31:0] = rx_packet[39:8];
//Address generator for bursting
always @ (posedge clk)
if(rx_access)
dstaddr_reg[31:0] <= dstaddr_mux[31:0];
assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4'b1000;
assign dstaddr_mux[31:0] = rx_burst ? dstaddr_next[31:0] :
rx_addr[31:0];
//Read response detector
assign read_response = (rx_addr[31:20] == myid[11:0]) &
(rx_addr[19:16] == `EGROUP_RR);
//Pipeline stage and decode
always @ (posedge clk)
begin
//Write/read request
erx_rdwr_access <= rx_access & ~read_response;
//Read response
erx_rr_access <= rx_access & read_response;
//Common packet
erx_packet[PW-1:0] <= {rx_packet[PW-1:40],
dstaddr_mux[31:0],
rx_packet[7:0]
};
end
endmodule // erx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
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#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; cout << ((n % 2) ? black : white n1 2 n ) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int q; cin >> q; for (int k = 0; k < q; ++k) { string s, t; cin >> s >> t; vector<bool> a(26), b(26); for (int i = 0; i < s.size(); ++i) { a[s[i] - a ] = true; b[t[i] - a ] = true; } bool flag = false; for (int i = 0; i < 26; ++i) { if (a[i] && b[i]) { flag = true; break; } } if (flag) cout << YES n ; else cout << NO n ; } return 0; }
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/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define low_pos(x,y) `high_pos(x,y) - 63
`define high_pos(x,y) 1599 - 64*(5*y+x)
`define add_1(x) (x == 4 ? 0 : x + 1)
`define add_2(x) (x == 3 ? 0 : x == 4 ? 1 : x + 2)
`define sub_1(x) (x == 0 ? 4 : x - 1)
`define rot_up(in, n) {in[63-n:0], in[63:63-n+1]}
`define rot_up_1(in) {in[62:0], in[63]}
module round(in, round_const, out);
input [1599:0] in;
input [63:0] round_const;
output [1599:0] out;
wire [63:0] a[4:0][4:0];
wire [63:0] b[4:0];
wire [63:0] c[4:0][4:0], d[4:0][4:0], e[4:0][4:0], f[4:0][4:0], g[4:0][4:0];
genvar x, y;
/* assign "a[x][y][z] == in[w(5y+x)+z]" */
generate
for(y=0; y<5; y=y+1)
begin : L0
for(x=0; x<5; x=x+1)
begin : L1
assign a[x][y] = in[`high_pos(x,y) : `low_pos(x,y)];
end
end
endgenerate
/* calc "b[x] == a[x][0] ^ a[x][1] ^ ... ^ a[x][4]" */
generate
for(x=0; x<5; x=x+1)
begin : L2
assign b[x] = a[x][0] ^ a[x][1] ^ a[x][2] ^ a[x][3] ^ a[x][4];
end
endgenerate
/* calc "c == theta(a)" */
generate
for(y=0; y<5; y=y+1)
begin : L3
for(x=0; x<5; x=x+1)
begin : L4
assign c[x][y] = a[x][y] ^ b[`sub_1(x)] ^ `rot_up_1(b[`add_1(x)]);
end
end
endgenerate
/* calc "d == rho(c)" */
assign d[0][0] = c[0][0];
assign d[1][0] = `rot_up_1(c[1][0]);
assign d[2][0] = `rot_up(c[2][0], 62);
assign d[3][0] = `rot_up(c[3][0], 28);
assign d[4][0] = `rot_up(c[4][0], 27);
assign d[0][1] = `rot_up(c[0][1], 36);
assign d[1][1] = `rot_up(c[1][1], 44);
assign d[2][1] = `rot_up(c[2][1], 6);
assign d[3][1] = `rot_up(c[3][1], 55);
assign d[4][1] = `rot_up(c[4][1], 20);
assign d[0][2] = `rot_up(c[0][2], 3);
assign d[1][2] = `rot_up(c[1][2], 10);
assign d[2][2] = `rot_up(c[2][2], 43);
assign d[3][2] = `rot_up(c[3][2], 25);
assign d[4][2] = `rot_up(c[4][2], 39);
assign d[0][3] = `rot_up(c[0][3], 41);
assign d[1][3] = `rot_up(c[1][3], 45);
assign d[2][3] = `rot_up(c[2][3], 15);
assign d[3][3] = `rot_up(c[3][3], 21);
assign d[4][3] = `rot_up(c[4][3], 8);
assign d[0][4] = `rot_up(c[0][4], 18);
assign d[1][4] = `rot_up(c[1][4], 2);
assign d[2][4] = `rot_up(c[2][4], 61);
assign d[3][4] = `rot_up(c[3][4], 56);
assign d[4][4] = `rot_up(c[4][4], 14);
/* calc "e == pi(d)" */
assign e[0][0] = d[0][0];
assign e[0][2] = d[1][0];
assign e[0][4] = d[2][0];
assign e[0][1] = d[3][0];
assign e[0][3] = d[4][0];
assign e[1][3] = d[0][1];
assign e[1][0] = d[1][1];
assign e[1][2] = d[2][1];
assign e[1][4] = d[3][1];
assign e[1][1] = d[4][1];
assign e[2][1] = d[0][2];
assign e[2][3] = d[1][2];
assign e[2][0] = d[2][2];
assign e[2][2] = d[3][2];
assign e[2][4] = d[4][2];
assign e[3][4] = d[0][3];
assign e[3][1] = d[1][3];
assign e[3][3] = d[2][3];
assign e[3][0] = d[3][3];
assign e[3][2] = d[4][3];
assign e[4][2] = d[0][4];
assign e[4][4] = d[1][4];
assign e[4][1] = d[2][4];
assign e[4][3] = d[3][4];
assign e[4][0] = d[4][4];
/* calc "f = chi(e)" */
generate
for(y=0; y<5; y=y+1)
begin : L5
for(x=0; x<5; x=x+1)
begin : L6
assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]);
end
end
endgenerate
/* calc "g = iota(f)" */
generate
for(x=0; x<64; x=x+1)
begin : L60
if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63)
assign g[0][0][x] = f[0][0][x] ^ round_const[x];
else
assign g[0][0][x] = f[0][0][x];
end
endgenerate
generate
for(y=0; y<5; y=y+1)
begin : L7
for(x=0; x<5; x=x+1)
begin : L8
if(x!=0 || y!=0)
assign g[x][y] = f[x][y];
end
end
endgenerate
/* assign "out[w(5y+x)+z] == out_var[x][y][z]" */
generate
for(y=0; y<5; y=y+1)
begin : L99
for(x=0; x<5; x=x+1)
begin : L100
assign out[`high_pos(x,y) : `low_pos(x,y)] = g[x][y];
end
end
endgenerate
endmodule
`undef low_pos
`undef high_pos
`undef add_1
`undef add_2
`undef sub_1
`undef rot_up
`undef rot_up_1
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#include <bits/stdc++.h> using namespace std; int k, l; int main() { int i, n; scanf( %d , &n); getchar(); char ch[1000]; scanf( %s , ch); for (i = 0; i < n; ++i) { if (ch[i] == 0 ) k++; else l++; } if (n % 2 == 1 || k != l) { printf( 1 n%s n , ch); return 0; } cout << 2 << endl; for (i = 0; i < n; ++i) { printf( %c , ch[i]); if (ch[i] == 0 ) k--; else l--; if (k == 0 || l == 0) break; } i++; cout << ; for (int j = i; j < n; ++j) printf( %c , ch[j]); cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { char a; int b; scanf( %c%d , &a, &b); if ((a == a || a == h ) && (b == 1 || b == 8)) printf( 3 n ); else if (a == a || a == h || b == 1 || b == 8) printf( 5 n ); else printf( 8 n ); }
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#include <bits/stdc++.h> using namespace std; int main() { int s, v1, v2, p1, p2; scanf( %d%d%d%d%d , &s, &v1, &v2, &p1, &p2); if (v1 * s + p1 * 2 < v2 * s + p2 * 2) printf( First n ); if (v1 * s + p1 * 2 > v2 * s + p2 * 2) printf( Second n ); if (v1 * s + p1 * 2 == v2 * s + p2 * 2) printf( Friendship n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 300005; int n, m, q; struct Graph { struct Edge { int to, next; } edge[N << 1]; int head[N], cnt; Graph() { memset(head, 0, sizeof(head)); cnt = 1; return; } void add_edge(int u, int v) { if (u == 0 || v == 0) return; cnt++; edge[cnt].to = v; edge[cnt].next = head[u]; head[u] = cnt; return; } }; Graph G1; int dfn1[N], low1[N], Index1; stack<int> s1; int bel1[N], tot1; void tarjan1(int u, int pre) { dfn1[u] = low1[u] = ++Index1; s1.push(u); for (int i = G1.head[u]; i; i = G1.edge[i].next) { int v = G1.edge[i].to; if ((i ^ 1) == pre) continue; if (!dfn1[v]) { tarjan1(v, i); low1[u] = min(low1[u], low1[v]); } else low1[u] = min(low1[u], dfn1[v]); } if (dfn1[u] == low1[u]) { tot1++; while (s1.top() != u) { bel1[s1.top()] = tot1; s1.pop(); } bel1[u] = tot1; s1.pop(); return; } return; } vector<int> G[N]; int f[N][20], dep[N]; int dfn[N], Index; void dfs(int u, int father) { dfn[u] = ++Index; dep[u] = dep[father] + 1; f[u][0] = father; for (int i = 1; (1 << i) <= n; i++) f[u][i] = f[f[u][i - 1]][i - 1]; for (int v : G[u]) { if (v == father) continue; dfs(v, u); } return; } int LCA(int u, int v) { if (dep[u] < dep[v]) swap(u, v); for (int i = log2(n); i >= 0; i--) if (dep[f[u][i]] >= dep[v]) u = f[u][i]; if (u == v) return u; for (int i = log2(n); i >= 0; i--) if (f[u][i] != f[v][i]) u = f[u][i], v = f[v][i]; return f[u][0]; } int s[N << 1], top; Graph G2; vector<int> pos; void ins(int u) { int z = LCA(u, s[top]); pos.push_back(u); if (z == s[top]) s[++top] = u; else { pos.push_back(z); while (top >= 2 && dep[s[top - 1]] > dep[z]) { if (s[top - 1] != s[top]) G2.add_edge(s[top - 1], s[top]), G2.add_edge(s[top], s[top - 1]); top--; } if (top) { if (z != s[top]) G2.add_edge(z, s[top]), G2.add_edge(s[top], z); top--; } s[++top] = z; s[++top] = u; } return; } bool cmp(int a, int b) { return dfn[a] < dfn[b]; } void build(vector<int>& k) { sort(k.begin(), k.end()); k.erase(unique(k.begin(), k.end()), k.end()); sort(k.begin(), k.end(), cmp); top = 0; s[++top] = 0; for (int x : k) if (x != 0) ins(x); while (top >= 2) { if (s[top - 1] != s[top]) G2.add_edge(s[top - 1], s[top]), G2.add_edge(s[top], s[top - 1]); top--; } sort(pos.begin(), pos.end()); pos.erase(unique(pos.begin(), pos.end()), pos.end()); return; } int dfn2[N], low2[N], Index2; stack<int> s2; int bel2[N], tot2; void tarjan2(int u, int pre) { dfn2[u] = low2[u] = ++Index2; s2.push(u); for (int i = G2.head[u]; i; i = G2.edge[i].next) { int v = G2.edge[i].to; if ((i ^ 1) == pre) continue; if (!dfn2[v]) { tarjan2(v, i); low2[u] = min(low2[u], low2[v]); } else low2[u] = min(low2[u], dfn2[v]); } if (dfn2[u] == low2[u]) { tot2++; while (s2.top() != u) { bel2[s2.top()] = tot2; s2.pop(); } bel2[u] = tot2; s2.pop(); return; } return; } int x[N]; long long R; int rotate(int element) { element = (element + R) % n; if (element == 0) { element = n; } return element; } void clear() { for (int u : pos) { G2.head[u] = 0; dfn2[u] = low2[u] = 0; bel2[u] = 0; } pos.clear(); return; } int Case = 0; void solve() { Case++; int ni, mi; scanf( %d%d , &ni, &mi); vector<int> k; for (int i = 1; i <= ni; i++) { scanf( %d , &x[i]); x[i] = rotate(x[i]); x[i] = bel1[x[i]]; k.push_back(x[i]); } G2.cnt = 1; for (int i = 1; i <= mi; i++) { int x, y; scanf( %d%d , &x, &y); x = rotate(x), y = rotate(y); x = bel1[x], y = bel1[y]; if (x == y) continue; G2.add_edge(x, y); G2.add_edge(y, x); k.push_back(x), k.push_back(y); } build(k); Index2 = tot2 = 0; while (!s2.empty()) s2.pop(); for (int u : pos) if (!dfn2[u]) tarjan2(u, 0); for (int i = 2; i <= ni; i++) if (bel2[x[i]] != bel2[x[i - 1]]) { printf( NO n ); clear(); return; } printf( YES n ); R += Case; clear(); return; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); G1.add_edge(x, y); G1.add_edge(y, x); } for (int i = 1; i <= n; i++) if (!dfn1[i]) tarjan1(i, 0); for (int u = 1; u <= n; u++) for (int i = G1.head[u]; i; i = G1.edge[i].next) { int v = G1.edge[i].to; int x = bel1[u], y = bel1[v]; if (x < y) G[x].push_back(y), G[y].push_back(x); } for (int i = 1; i <= tot1; i++) if (!dep[i]) dfs(i, 0); while (q--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int NMAX = 1e5; int v[NMAX + 5], ans[NMAX + 5]; inline void GenerateAnswer(int n) { int i, state = 1, st = 1, dr = n, dim = 0; sort(v + 1, v + n + 1); while (st <= dr) { if (st != dr) { if (state == 1) ans[++dim] = v[st], ans[++dim] = v[dr]; else ans[++dim] = v[dr], ans[++dim] = v[st]; } else ans[++dim] = v[st]; ++st; --dr; } } int main() { int t, n, i, j; scanf( %d , &t); for (j = 1; j <= t; ++j) { scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &v[i]); GenerateAnswer(n); for (i = n; i >= 1; --i) printf( %d , ans[i]); printf( n ); } return 0; }
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module RS232TX (
input clk,
input Tx_start,
input [23:0] dbuffer,
output Tx,
output Tx_busy
);
wire bittick;
wire[7:0] Tx_data = dbuffer[7:0];
RS232Baud baud(
.clk(clk),
.enable(Tx_busy),
.tick(bittick)
);
reg[3:0] Tx_state = 0;
wire Tx_ready = (Tx_state==0);
assign Tx_busy = ~Tx_ready;
reg[7:0] Tx_shift = 0;
always @(posedge clk)
begin
if (Tx_ready & Tx_start)
Tx_shift <= Tx_data;
else
if (Tx_state[3] & bittick)
Tx_shift <= (Tx_shift >> 1);
case(Tx_state)
4'b0000: if(Tx_start) Tx_state <= 4'b0100; // waiting?
4'b0100: if (bittick) Tx_state <= 4'b1000; //start bit
4'b1000: if (bittick) Tx_state <= 4'b1001; // bit 0
4'b1001: if (bittick) Tx_state <= 4'b1010; // bit 1
4'b1010: if (bittick) Tx_state <= 4'b1011; // bit 2
4'b1011: if (bittick) Tx_state <= 4'b1100; // bit 3
4'b1100: if (bittick) Tx_state <= 4'b1101; // bit 4
4'b1101: if (bittick) Tx_state <= 4'b1110; // bit 5
4'b1110: if (bittick) Tx_state <= 4'b1111; // bit 6
4'b1111: if (bittick) Tx_state <= 4'b0010; // bit 7
4'b0010: if (bittick) Tx_state <= 4'b0011; // stop1
4'b0011: if (bittick) Tx_state <= 4'b0000; // stop2
default: if (bittick) Tx_state <= 4'b0000;
endcase
end
assign Tx = (Tx_state < 4) | (Tx_state[3] & Tx_shift[0]);
endmodule
module RS232Baud(
input clk,
input enable,
output tick
);
parameter ClkFrequency = 50000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void read(vector<T> &a, long long n) { T x; a.clear(); for (long long i = 0; i < n; i++) { cin >> x; a.push_back(x); } } template <class T> void write(vector<T> &a) { for (T x : a) cout << x << ; cout << endl; } int main() { ios_base::sync_with_stdio(0); int T; cin >> T; while (T--) { int n, m; vector<int> a, b; cin >> n >> n >> m; read(a, n); read(b, m); sort(a.begin(), a.end()); sort(b.begin(), b.end()); if (a.back() > b.back()) cout << YES << endl; else cout << NO << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_SYMBOL_V
`define SKY130_FD_SC_HD__SDFRTN_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 16:06:27 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_internoc_ni_axi_master_0_0_stub.v
// Design : DemoInterconnect_internoc_ni_axi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "internoc_ni_axi_master_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(if00_data_in, if00_load_in, if00_data_out,
if00_load_out, if00_send_done, if00_send_busy, m00_axi_awaddr, m00_axi_awprot,
m00_axi_awvalid, m00_axi_awready, m00_axi_wdata, m00_axi_wstrb, m00_axi_wvalid,
m00_axi_wready, m00_axi_bresp, m00_axi_bvalid, m00_axi_bready, m00_axi_araddr,
m00_axi_arprot, m00_axi_arvalid, m00_axi_arready, m00_axi_rdata, m00_axi_rresp,
m00_axi_rvalid, m00_axi_rready, m00_axi_aclk, m00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="if00_data_in[7:0],if00_load_in,if00_data_out[7:0],if00_load_out,if00_send_done,if00_send_busy,m00_axi_awaddr[31:0],m00_axi_awprot[2:0],m00_axi_awvalid,m00_axi_awready,m00_axi_wdata[31:0],m00_axi_wstrb[3:0],m00_axi_wvalid,m00_axi_wready,m00_axi_bresp[1:0],m00_axi_bvalid,m00_axi_bready,m00_axi_araddr[31:0],m00_axi_arprot[2:0],m00_axi_arvalid,m00_axi_arready,m00_axi_rdata[31:0],m00_axi_rresp[1:0],m00_axi_rvalid,m00_axi_rready,m00_axi_aclk,m00_axi_aresetn" */;
input [7:0]if00_data_in;
input if00_load_in;
output [7:0]if00_data_out;
output if00_load_out;
input if00_send_done;
input if00_send_busy;
output [31:0]m00_axi_awaddr;
output [2:0]m00_axi_awprot;
output m00_axi_awvalid;
input m00_axi_awready;
output [31:0]m00_axi_wdata;
output [3:0]m00_axi_wstrb;
output m00_axi_wvalid;
input m00_axi_wready;
input [1:0]m00_axi_bresp;
input m00_axi_bvalid;
output m00_axi_bready;
output [31:0]m00_axi_araddr;
output [2:0]m00_axi_arprot;
output m00_axi_arvalid;
input m00_axi_arready;
input [31:0]m00_axi_rdata;
input [1:0]m00_axi_rresp;
input m00_axi_rvalid;
output m00_axi_rready;
input m00_axi_aclk;
input m00_axi_aresetn;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 26869 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w128,
w129,
w2064,
w2065,
w8260,
w10325,
w16512,
w26837,
w32,
w26869;
assign w1 = i_data0;
assign w10325 = w2065 + w8260;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w16512 = w129 << 7;
assign w2064 = w129 << 4;
assign w2065 = w1 + w2064;
assign w26837 = w10325 + w16512;
assign w26869 = w26837 + w32;
assign w32 = w1 << 5;
assign w8260 = w2065 << 2;
assign o_data0 = w26869;
//multiplier_block area estimate = 8671.92501534265;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; scanf( %d %d %d , &a, &b, &c); double rez = 1.0 * a * a * a * 1.41421356237309 / 12.0; rez += 1.0 * b * b * b * 1.41421356237309 / 6.0; rez += 1.0 * c * c * c * 7.23606797749978 / 24.0; printf( %.10lf n , rez); return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module store and retrieves video frames to and from memory. *
* *
******************************************************************************/
`undef USE_TO_MEMORY
`define USE_32BIT_MASTER
module Raster_Laser_Projector_Video_In_video_dma_controller_0 (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
// Bidirectional
// Outputs
stream_ready,
master_address,
master_write,
master_writedata,
slave_readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 7; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter WIDTH = 640; // Frame's width in pixels
parameter HEIGHT = 480; // Frame's height in lines
parameter AW = 18; // Frame's address width
parameter WW = 9; // Frame width's address width
parameter HW = 8; // Frame height's address width
parameter MDW = 7; // Avalon master's datawidth
parameter DEFAULT_BUFFER_ADDRESS = 32'd9437184;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd0;
parameter ADDRESSING_BITS = 16'd19;
parameter COLOR_BITS = 4'd7;
parameter COLOR_PLANES = 2'd0;
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
// Bidirectional
// Outputs
output stream_ready;
output [31: 0] master_address;
output master_write;
output [MDW:0] master_writedata;
output [31: 0] slave_readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire inc_address;
wire reset_address;
wire [31: 0] buffer_start_address;
wire dma_enabled;
// Internal Registers
reg [AW: 0] pixel_address;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset | ~dma_enabled)
pixel_address <= 'h0;
else if (reset_address)
pixel_address <= 'h0;
else if (inc_address)
pixel_address <= pixel_address + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
pixel_address;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_dma_control_slave DMA_Control_Slave (
// Inputs
.clk (clk),
.reset (reset),
.address (slave_address),
.byteenable (slave_byteenable),
.read (slave_read),
.write (slave_write),
.writedata (slave_writedata),
.swap_addresses_enable (reset_address),
// Bi-Directional
// Outputs
.readdata (slave_readdata),
.current_start_address (buffer_start_address),
.dma_enabled (dma_enabled)
);
defparam
DMA_Control_Slave.DEFAULT_BUFFER_ADDRESS = DEFAULT_BUFFER_ADDRESS,
DMA_Control_Slave.DEFAULT_BACK_BUF_ADDRESS = DEFAULT_BACK_BUF_ADDRESS,
DMA_Control_Slave.WIDTH = WIDTH,
DMA_Control_Slave.HEIGHT = HEIGHT,
DMA_Control_Slave.ADDRESSING_BITS = ADDRESSING_BITS,
DMA_Control_Slave.COLOR_BITS = COLOR_BITS,
DMA_Control_Slave.COLOR_PLANES = COLOR_PLANES,
DMA_Control_Slave.ADDRESSING_MODE = 1'b1,
DMA_Control_Slave.DEFAULT_DMA_ENABLED = DEFAULT_DMA_ENABLED;
altera_up_video_dma_to_memory From_Stream_to_Memory (
// Inputs
.clk (clk),
.reset (reset | ~dma_enabled),
.stream_data (stream_data),
.stream_startofpacket (stream_startofpacket),
.stream_endofpacket (stream_endofpacket),
.stream_empty (stream_empty),
.stream_valid (stream_valid),
.master_waitrequest (master_waitrequest),
// Bidirectional
// Outputs
.stream_ready (stream_ready),
.master_write (master_write),
.master_writedata (master_writedata),
.inc_address (inc_address),
.reset_address (reset_address)
);
defparam
From_Stream_to_Memory.DW = DW,
From_Stream_to_Memory.EW = EW,
From_Stream_to_Memory.MDW = MDW;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool jolmetsz(long long a, long long b, long long c, long long x1, long long y1, long long x2, long long y2) { return -c - a * x1 < b * y1 && -c - a * x2 > b * y2; } int main() { long long x1, x2, y1, y2, n, db = 0; cin >> x1 >> y1 >> x2 >> y2 >> n; if (y2 < y1) { swap(y1, y2); swap(x1, x2); } int lep = 0; for (int i = 0; i < n; i++) { long long a, b, c; cin >> a >> b >> c; if (jolmetsz(a, b, c, x1, y1, x2, y2) || jolmetsz(a, b, c, x2, y2, x1, y1)) db++; } cout << db << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:19:54 04/26/2017
// Design Name:
// Module Name: decrypt_dumb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt_dumb(
input [63:0] message,
input [63:0] DESkey,
output reg [63:0] decrypted,
output done,
input clk,
input reset,
input enable,
input ack
);
// 8 of 8 bits
reg [63:0] rand;
initial begin
rand = {8'd238, 8'd107, 8'd12, 8'd79, 8'd36, 8'd116, 8'd4, 8'd112};
end
reg [7:0] firstBit, secondBit, thirdBit;
// 8 of 3 bits
reg [23:0] randIdx;
reg [2:0] state;
localparam
INITIAL = 3'd1,
DECRYPT = 3'd2,
DONE = 3'd4;
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
state <= INITIAL;
randIdx = 24'd0;
end
else
begin
case (state)
INITIAL:
begin : STATE_INITIAL
if (enable)
state <= DECRYPT;
end
DECRYPT:
begin: STATE_DECRYPT
integer i;
for (i = 0; i < 8; i = i + 1) begin
firstBit[i] = (DESkey[8*i+2 +: 2] ^ DESkey[8*i+6 +: 2]) > 2'd1;
secondBit[i] = (DESkey[8*i +: 2] ^ DESkey[8*i+4 +: 2]) > 2'd1;
thirdBit[i] = (DESkey[8*i +: 4] ^ DESkey[8*i+4 +: 4]) > 3'd3;
randIdx[3 * i +: 3] = {firstBit[i], secondBit[i], thirdBit[i]};
decrypted[8 * i +: 8] <= message[8 * i +: 8] ^ rand[randIdx[3 * i +: 3] +: 8];
end
state <= DONE;
end
DONE:
begin: STATE_DONE
if (ack)
state <= INITIAL;
end
endcase
end
end
assign done = state == DONE;
endmodule
|
//
// Author: Pawel Szostek ()
// Date: 01.08.2011
`timescale 1ns/1ps
module stimulus (output reg [7:0] a);
parameter S = 20000;
int unsigned j,i;
initial begin
for(i=0; i<S; i=i+1) begin
#10;
a[7] <= inject();
a[6] <= inject();
a[5] <= inject();
a[4] <= inject();
a[3] <= inject();
a[2] <= inject();
a[1] <= inject();
a[0] <= inject();
end
end
function inject();
reg ret;
reg unsigned [3:0] temp;
temp[3:0] = $random % 16;
begin
if(temp >= 10)
ret = 1'b1;
else if(temp >= 4)
ret = 1'b0;
else if(temp >= 2)
ret = 1'bx;
else
ret = 1'b0;
inject = ret;
end
endfunction
endmodule
module main;
wire [7:0] i, o;
wire [0:7] o_vl;
dummy dummy_vhdl(o, i);
stimulus stim(i);
assign o_vl = i;
always @(i) begin
#1;
if(o !== o_vl) begin
$display("OUTPUT: ", o);
$display("INPUT: ", i);
$display("CORRECT: ", o_vl);
end
end
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
module SystolicDataSetupRow #(
parameter DATA_BITS = 8,
parameter MATRIX_SIZE = 256,
parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1
) (
input clock,
input reset,
input [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:MATRIX_SIZE-1],
output [DATA_BITS-1:0] data_out[0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1]
);
integer i;
integer j;
always @ (posedge clock or posedge reset) begin
if (reset) begin
for( i = 0; i < MATRIX_SIZE; i++ )
for (j=0;j< OUTPUT_SIZE;j++)
data_out[i][j] = 8'h00;
end else begin
$display ("New Iteration");
for( i = 0; i < MATRIX_SIZE; i++ ) begin
for( j = 0; j < OUTPUT_SIZE; j++ ) begin
if (j<i) begin
data_out[i][j]=8'h00;
$display("value of data_out[%d][%d] is 0 : 1",i,j);
end
else if (j > (i+MATRIX_SIZE-1)) begin
data_out[i][j]=8'h00;
$display("value of data_out[%d][%d] is 0 : 2",i,j);
end
else begin
data_out[i][j] = data_in[i][i+j];
$display ("value of data_out[%d][%d] is data_in[%d][%d]",i,j,i,i+j );
end
end
end
$display ("End Iteration");
$display("\n");
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int compare(const void *a, const void *b) { int *p = (int *)a; int *q = (int *)b; if (p[0] == q[0]) return p[1] - q[1]; return p[0] - q[0]; } int main() { int n, m, c = 0, t, i, x; scanf( %d%d , &n, &m); ; t = 0; for (i = 0; i < n; i++) { scanf( %d , &x); ; if (x > t) { c++; t = m - x; } else t -= x; } printf( %d n , c); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(T x) { return x * x; } const double EPS = 1e-6; const int INF = 0x3fffffff; const long long LINF = INF * 1ll * INF; const double PI = acos(-1.0); using namespace std; struct PointSet { char val; int num; } ps[1000005]; char s[1000005]; int len; void unionPoint() { int cnt = 0; for (int i = 1; i <= len; i++) { if (ps[i].num > 0) { if (ps[i].val == ps[cnt].val) ps[cnt].num += ps[i].num; else ps[++cnt] = ps[i]; } } len = cnt; } int main() { scanf( %s , s + 1); len = strlen(s + 1); ps[0] = { # , 0}; for (int i = 1; i <= len; i++) { ps[i].val = s[i]; ps[i].num = 1; } unionPoint(); int ans = 0; while (len > 1) { ans++; for (int i = 1; i <= len; i++) { if (i == 1 || i == len) ps[i].num--; else ps[i].num -= 2; } unionPoint(); } printf( %d n , ans); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but ensures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long A, B, n; cin >> A >> B >> n; long long i, j; if (A == 0) { if (B == 0) { cout << 0; } else cout << No solution ; return 0; } if (B % A) { cout << No solution ; return 0; } long long rez = B / A; if (rez == 1) { cout << 1; return 0; } if (B == 0) { cout << 0; return 0; } for (long long i = -1002; i <= 1002; i++) { long long cur = i; for (j = 2; j <= n; j++) { cur *= i; if (abs(cur) > 1000000000) break; } if (cur == rez) { cout << i; return 0; } } cout << No solution ; return 0; }
|
//Define 32 to 16 multiplexer
module mux32to16(out , in1 , in2 ,control);
// I/O port declaration
output [31:0] out;
input [31:0] in1,in2;
input control;
//internal nets
wire control_not;
wire [31:0] anded_out_1,anded_out_2;
//internal gate circuitry
not (control_not,control);
and (anded_out_1[0] , control_not , in1[0]);
and (anded_out_1[1] , control_not , in1[1]);
and (anded_out_1[2] , control_not , in1[2]);
and (anded_out_1[3] , control_not , in1[3]);
and (anded_out_1[4] , control_not , in1[4]);
and (anded_out_1[5] , control_not , in1[5]);
and (anded_out_1[6] , control_not , in1[6]);
and (anded_out_1[7] , control_not , in1[7]);
and (anded_out_1[8] , control_not , in1[8]);
and (anded_out_1[9] , control_not , in1[9]);
and (anded_out_1[10] , control_not , in1[10]);
and (anded_out_1[11] , control_not , in1[11]);
and (anded_out_1[12] , control_not , in1[12]);
and (anded_out_1[13] , control_not , in1[13]);
and (anded_out_1[14] , control_not , in1[14]);
and (anded_out_1[15] , control_not , in1[15]);
and (anded_out_1[16] , control_not , in1[16]);
and (anded_out_1[17] , control_not , in1[17]);
and (anded_out_1[18] , control_not , in1[18]);
and (anded_out_1[19] , control_not , in1[19]);
and (anded_out_1[20] , control_not , in1[20]);
and (anded_out_1[21] , control_not , in1[21]);
and (anded_out_1[22] , control_not , in1[22]);
and (anded_out_1[23] , control_not , in1[23]);
and (anded_out_1[24] , control_not , in1[24]);
and (anded_out_1[25] , control_not , in1[25]);
and (anded_out_1[26] , control_not , in1[26]);
and (anded_out_1[27] , control_not , in1[27]);
and (anded_out_1[28] , control_not , in1[28]);
and (anded_out_1[29] , control_not , in1[29]);
and (anded_out_1[30] , control_not , in1[30]);
and (anded_out_1[31] , control_not , in1[31]);
and (anded_out_2[0] , control , in2[0]);
and (anded_out_2[1] , control , in2[1]);
and (anded_out_2[2] , control , in2[2]);
and (anded_out_2[3] , control , in2[3]);
and (anded_out_2[4] , control , in2[4]);
and (anded_out_2[5] , control , in2[5]);
and (anded_out_2[6] , control , in2[6]);
and (anded_out_2[7] , control , in2[7]);
and (anded_out_2[8] , control , in2[8]);
and (anded_out_2[9] , control , in2[9]);
and (anded_out_2[10] , control , in2[10]);
and (anded_out_2[11] , control , in2[11]);
and (anded_out_2[12] , control , in2[12]);
and (anded_out_2[13] , control , in2[13]);
and (anded_out_2[14] , control , in2[14]);
and (anded_out_2[15] , control , in2[15]);
and (anded_out_2[16] , control , in2[16]);
and (anded_out_2[17] , control , in2[17]);
and (anded_out_2[18] , control , in2[18]);
and (anded_out_2[19] , control , in2[19]);
and (anded_out_2[20] , control , in2[20]);
and (anded_out_2[21] , control , in2[21]);
and (anded_out_2[22] , control , in2[22]);
and (anded_out_2[23] , control , in2[23]);
and (anded_out_2[24] , control , in2[24]);
and (anded_out_2[25] , control , in2[25]);
and (anded_out_2[26] , control , in2[26]);
and (anded_out_2[27] , control , in2[27]);
and (anded_out_2[28] , control , in2[28]);
and (anded_out_2[29] , control , in2[29]);
and (anded_out_2[30] , control , in2[30]);
and (anded_out_2[31] , control , in2[31]);
or (out[0] , anded_out_1[0] , anded_out_2[0]);
or (out[1] , anded_out_1[1] , anded_out_2[1]);
or (out[2] , anded_out_1[2] , anded_out_2[2]);
or (out[3] , anded_out_1[3] , anded_out_2[3]);
or (out[4] , anded_out_1[4] , anded_out_2[4]);
or (out[5] , anded_out_1[5] , anded_out_2[5]);
or (out[6] , anded_out_1[6] , anded_out_2[6]);
or (out[7] , anded_out_1[7] , anded_out_2[7]);
or (out[8] , anded_out_1[8] , anded_out_2[8]);
or (out[9] , anded_out_1[9] , anded_out_2[9]);
or (out[10] , anded_out_1[10] , anded_out_2[10]);
or (out[11] , anded_out_1[11] , anded_out_2[11]);
or (out[12] , anded_out_1[12] , anded_out_2[12]);
or (out[13] , anded_out_1[13] , anded_out_2[13]);
or (out[14] , anded_out_1[14] , anded_out_2[14]);
or (out[15] , anded_out_1[15] , anded_out_2[15]);
or (out[16] , anded_out_1[16] , anded_out_2[16]);
or (out[17] , anded_out_1[17] , anded_out_2[17]);
or (out[18] , anded_out_1[18] , anded_out_2[18]);
or (out[19] , anded_out_1[19] , anded_out_2[19]);
or (out[20] , anded_out_1[20] , anded_out_2[20]);
or (out[21] , anded_out_1[21] , anded_out_2[21]);
or (out[22] , anded_out_1[22] , anded_out_2[22]);
or (out[23] , anded_out_1[23] , anded_out_2[23]);
or (out[24] , anded_out_1[24] , anded_out_2[24]);
or (out[25] , anded_out_1[25] , anded_out_2[25]);
or (out[26] , anded_out_1[26] , anded_out_2[26]);
or (out[27] , anded_out_1[27] , anded_out_2[27]);
or (out[28] , anded_out_1[28] , anded_out_2[28]);
or (out[29] , anded_out_1[29] , anded_out_2[29]);
or (out[30] , anded_out_1[30] , anded_out_2[30]);
or (out[31] , anded_out_1[31] , anded_out_2[31]);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:45:17 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/arthas/git/SHD/SHD.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_stub.v
// Design : shd_pe_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3" *)
module shd_pe_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[7:0],wr_en,rd_en,dout[7:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [7:0]din;
input wr_en;
input rd_en;
output [7:0]dout;
output full;
output empty;
endmodule
|
`timescale 1ns/1ps
module tb_cocotb #(
//parameter CONSOLE_DEPTH = 12,
parameter CONSOLE_DEPTH = 5,
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter AXIS_STROBE_WIDTH = (AXIS_WIDTH / 8),
parameter BUFFER_DEPTH = 8,
parameter IMAGE_WIDTH = 30,
parameter IMAGE_HEIGHT = 24,
parameter PIXEL_WIDTH = 24
)(
input clk,
input rst,
//Write Address Channel
input AXIML_AWVALID,
input [ADDR_WIDTH - 1: 0] AXIML_AWADDR,
output AXIML_AWREADY,
//Write Data Channel
input AXIML_WVALID,
output AXIML_WREADY,
input [STROBE_WIDTH - 1:0] AXIML_WSTRB,
input [DATA_WIDTH - 1: 0] AXIML_WDATA,
//Write Response Channel
output AXIML_BVALID,
input AXIML_BREADY,
output [1:0] AXIML_BRESP,
//Read Address Channel
input AXIML_ARVALID,
output AXIML_ARREADY,
input [ADDR_WIDTH - 1: 0] AXIML_ARADDR,
//Read Data Channel
output AXIML_RVALID,
input AXIML_RREADY,
output [1:0] AXIML_RRESP,
output [DATA_WIDTH - 1: 0] AXIML_RDATA,
output [AXIS_WIDTH - 1:0] AXISS_TDATA,
input AXISS_TREADY,
output AXISS_TVALID,
output AXISS_TLAST,
output [AXIS_STROBE_WIDTH - 1: 0] AXISS_TKEEP,
output [AXIS_STROBE_WIDTH - 1: 0] AXISS_TSTRB,
output [3:0] AXISS_TID,
output [31:0] AXISS_TDEST,
output [3:0] AXISS_TUSER
);
//Local Parameters
//Registers
reg r_rst;
reg r_axiss_tready;
always @ (*) r_rst = rst;
always @ (*) r_axiss_tready = AXISS_TREADY;
reg [3:0] test_id = 0;
//submodules
axi_on_screen_display #(
.CONSOLE_DEPTH (CONSOLE_DEPTH ),
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH ),
.AXIS_WIDTH (AXIS_WIDTH ),
.INVERT_AXI_RESET (0 ),
.INVERT_AXIS_RESET (0 ),
.IMAGE_WIDTH (IMAGE_WIDTH ),
.IMAGE_HEIGHT (IMAGE_HEIGHT ),
.PIXEL_WIDTH (PIXEL_WIDTH ),
.BUFFER_DEPTH (BUFFER_DEPTH ),
.FOREGROUND_COLOR (24'hFFFFFF ),
.BACKGROUND_COLOR (24'h000000 )
) dut (
.clk (clk ),
.rst (r_rst ),
//AXI Lite Interface
.i_awvalid (AXIML_AWVALID ),
.i_awaddr (AXIML_AWADDR ),
.o_awready (AXIML_AWREADY ),
.i_wvalid (AXIML_WVALID ),
.o_wready (AXIML_WREADY ),
.i_wstrb (AXIML_WSTRB ),
.i_wdata (AXIML_WDATA ),
.o_bvalid (AXIML_BVALID ),
.i_bready (AXIML_BREADY ),
.o_bresp (AXIML_BRESP ),
.i_arvalid (AXIML_ARVALID ),
.o_arready (AXIML_ARREADY ),
.i_araddr (AXIML_ARADDR ),
.o_rvalid (AXIML_RVALID ),
.i_rready (AXIML_RREADY ),
.o_rresp (AXIML_RRESP ),
.o_rdata (AXIML_RDATA ),
//AXI Stream
.i_axis_clk (clk ),
.i_axis_rst (r_rst ),
.o_axis_user (AXISS_TUSER ),
.i_axis_ready (r_axiss_tready ),
.o_axis_data (AXISS_TDATA ),
.o_axis_last (AXISS_TLAST ),
.o_axis_valid (AXISS_TVALID )
);
//asynchronus logic
//synchronous logic
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int M = 1005; int n, m, x[N], s; double p[N * M], tmp[N * M]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , &x[i]); for (int i = 1; i <= n; ++i) s += x[i]; if (m == 1) { puts( 1.0000000000 ); return 0; } p[0] = 1; for (int i = 1; i <= n; ++i) { double now = 0; for (int j = 1; j < s; ++j) { now += p[j - 1]; if (x[i] <= j) now -= p[j - x[i]]; if (x[i] < j) now += p[j - x[i] - 1]; if (m < j) now -= p[j - m - 1]; tmp[j] = now / (m - 1); } for (int j = 0; j <= s; ++j) p[j] = tmp[j]; copy(tmp, tmp + s, p); } double ans = 0; for (int i = 1; i <= s; ++i) ans += p[i]; ans = ans * (m - 1) + 1; printf( %.10f n , ans); return 0; }
|
//
//////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////////
//
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 2.10
// \ \ Filename: uart_tx.v
// / / Date Last Modified: March 19 2010
// /___/ /\ Date Created: October 14 2002
// \ \ / \
// \___\/\___\
//
// Device: Xilinx
// Purpose: UART Transmitter with integral 16 byte FIFO buffer
// 8 bit, no parity, 1 stop bit
//
// This module was made for use with Spartan-3 Generation Devices and is also ideally
// suited for use with Virtex-II(PRO) and Virtex-4 devices. Will also work in Virtex-5,
// Virtex-6 and Spartan-6 devices but it is not specifically optimised for these
// architectures.
//
//
// Contact: e-mail
//
//
// Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, October 14 2002.
// Rev 1.01 - sus - Converted to verilog, August 4 2004.
// Rev 1.02 - njs - Converted to verilog 2001, February 10 2006.
// Rev 1.03 - kc - Minor format changes, January 17 2007.
// Rev 2.10 - njs - March 19 2010.
// Format and text changes consistent with sub-modules.
// No functional changes.
//
//////////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ps / 1ps
module uart_tx (
input [7:0] data_in,
input write_buffer,
input reset_buffer,
input en_16_x_baud,
output serial_out,
output buffer_full,
output buffer_half_full,
input clk);
//
//////////////////////////////////////////////////////////////////////////////////
//
// Signals used in UART_TX
//
//////////////////////////////////////////////////////////////////////////////////
//
wire [7:0] fifo_data_out;
wire fifo_data_present;
wire fifo_read;
//
//////////////////////////////////////////////////////////////////////////////////
//
// Start of UART_TX circuit description
//
//////////////////////////////////////////////////////////////////////////////////
//
kcuart_tx kcuart (
.data_in (fifo_data_out),
.send_character (fifo_data_present),
.en_16_x_baud (en_16_x_baud),
.serial_out (serial_out),
.Tx_complete (fifo_read),
.clk (clk));
bbfifo_16x8 buf_0 (
.data_in (data_in),
.data_out (fifo_data_out),
.reset (reset_buffer),
.write (write_buffer),
.read (fifo_read),
.full (buffer_full),
.half_full (buffer_half_full),
.data_present (fifo_data_present),
.clk (clk));
endmodule
//
//////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE UART_TX.V
//
//////////////////////////////////////////////////////////////////////////////////
//
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MSPAC_ROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("MSPAC_ROM.mif"),
.C_INIT_FILE("MSPAC_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(16384),
.C_READ_DEPTH_A(16384),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(16384),
.C_READ_DEPTH_B(16384),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sum = 0; for (int i = 0; i < n; i++) { int x1, x2, y1, y2; cin >> x1 >> x2 >> y1 >> y2; sum += (max(x1, y1) - min(x1, y1) + 1) * (max(x2, y2) - min(x2, y2) + 1); } cout << sum << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = 0; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); return f ? x : -x; } long long n, m, ans, s = 1, num; bool exia[20][20], exib[20][20], s1[20][20], s2[20][20]; signed main() { n = read(), m = read(); for (long long i = 1; i <= n; i++) { long long x = read(), y = read(); exia[x][y] = exia[y][x] = 1; } for (long long i = 1; i <= m; i++) { long long x = read(), y = read(); exib[x][y] = exib[y][x] = 1; } for (long long i = 1; i <= 9; i++) { for (long long j = 1; j <= 9; j++) { if (i == j) continue; for (long long k = 1; k <= 9; k++) { if (i == k || j == k) continue; if (exia[i][j] && exib[i][k]) { s1[i][j] = s2[i][k] = 1; ans = i; if (num && num != i) s = 0; num = i; } } } } if (s) printf( %lld , ans); else { ans = 0; for (long long i = 1; i <= 9; i++) { for (long long j = 1; j <= 9; j++) { if (i == j) continue; if (s1[i][j] && s1[j][i]) { ans = -1; break; } if (s2[i][j] && s2[j][i]) { ans = -1; break; } } } printf( %lld , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t, i, j, k, z, x, num[2]; string s; cin >> t; while (t--) { cin >> s; memset(num, 0, sizeof(num)); for (i = 0; i < s.size(); i++) { if (s[i] == 1 ) num[1]++; else num[0]++; } z = min(num[0], num[1]); if (z % 2) cout << DA n ; else cout << NET n ; } return 0; }
|
`timescale 1 ns / 1 ps
`include "../verilog/greycount.v"
module top;
reg clk = 1'b0;
integer t = 0;
reg [15:0] wd = 16'b1;
wire [15:0] rd;
reg we = 1'b1;
reg move = 1'b1;
reg pop = 1'b0;
reg twe = 1'b1;
reg tmove = 1'b1;
reg tpop = 1'b0;
stack2pipe4 #(.DEPTH(4)) dstack_(.clk(clk), .rd(rd), .we(we), .wd(wd), .delta({pop,move}));
// delta[0] is 'move\freeze'
// delta[1] is 'pop\push'
reg [1:0] state = 2'b00;
wire [1:0] last,next;
greycount gc_(.last(last), .next(next));
assign last = state;
always @(posedge clk or negedge clk) begin
if (!clk) begin
state <= next;
wd <= wd + 1;
end
t = t + 1;
end
always @(posedge clk) begin
case (state)
2'b10: begin
{we, move, pop} <= {twe, tmove, tpop};
end
default: begin
{we, move, pop} <= (t<9)? 3'b110 : 3'b000;
end
endcase
end
initial
begin
$display("Stack2pipe4 testbench.\n t, clk, state, we, move\\freeze, pop\\push, wd, rd");
end
always @* begin
if (t==64) {twe, tmove, tpop} <= 3'b011; //
if (t==64) {twe, tmove, tpop} <= 3'b011; // start popping out data.
clk <= !clk;
$display(t, " ", clk, " S:", state, ," ", we, move, pop, wd, rd);
if (t>128) $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void reshenie() { int n, m; cin >> n >> m; int a[n][n]; for (int i = 0; i < n; ++i) { for (int j = i; j < n; ++j) { a[i][j] = a[j][i] = 0; } } while (m--) { int u, v; cin >> u >> v; --u, --v; a[u][v] = a[v][u] = 1; } if (n == 1) { cout << Yes na << endl; return; } string s(n, * ); for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (a[i][j]) { s[i] = s[j] = b ; } } } for (int i = 0; i < n; ++i) { if (accumulate(a[i], a[i] + n, 0) != n - 1) { if (s[i] != c ) { s[i] = a ; for (int j = i + 1; j < n; ++j) { if (!a[i][j]) { s[j] = c ; } } } else { s[i] = c ; for (int j = i + 1; j < n; ++j) { if (!a[i][j]) { s[j] = a ; } } } } } for (int i = 0; i < n; ++i) { if (s[i] == * ) { cout << No << endl; return; } for (int j = i + 1; j < n; ++j) { if (a[i][j] && abs(s[i] - s[j]) <= 1) continue; if (!a[i][j] && abs(s[i] - s[j]) > 1) continue; cout << No << endl; return; } } cout << Yes n << s << endl; } int main() { reshenie(); return 1 - 1 + 2 - 2 + 3 - 3 + 4 - 4 + 5 - 5; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x7fffffff; const int maxn = 2e5 + 5; int bit[2][maxn], num[maxn]; int n, k, a, b, q; void update(int id, int x, int v) { while (x <= n) { bit[id][x] += v; x += (x & -x); } } int sum(int id, int x) { int ans = 0; while (x) { ans += bit[id][x]; x -= x & -x; } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k >> a >> b >> q; int x, y, z; while (q--) { cin >> x; if (x == 1) { cin >> y >> z; if (num[y] + z < b) { update(0, y, z); update(1, y, z); } else if (num[y] + z < a) { if (num[y] < b) update(0, y, b - num[y]); update(1, y, z); } else { if (num[y] < b) update(0, y, b - num[y]); if (num[y] < a) update(1, y, a - num[y]); } num[y] += z; } else { cin >> y; int ans = sum(0, y - 1) + sum(1, n) - sum(1, y + k - 1); cout << ans << endl; } } return 0; }
|
/*
* Copyright (c) 2001 Philip Blundell
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
primitive p (Q, D);
input D;
output Q;
reg Q;
initial Q = 1'b0;
table
0 : ? : 0;
1 : ? : 1;
endtable
endprimitive
module m;
reg D;
wire Q;
reg A;
wire QQ;
p(Q, D);
buf(QQ, Q);
initial
begin
// The #1 is needed here to allow the initial values to
// settle. Without it, there is a time-0 race.
#1 $display(QQ, Q);
#10
D = 0;
#15
$display(QQ, Q);
#20
D = 1;
#25
$display(QQ, Q);
$finish(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct union_find { vector<int> uf; vector<int> num_segments; vector<bool> used; union_find(int n) { uf.assign(n, -1); num_segments.assign(n, 0); used.assign(n, false); for (int i = 0; i < n; ++i) { if (i % 2 == 0) num_segments[i] = 1; } } int find(int i) { if (uf[i] < 0) return i; else return uf[i] = find(uf[i]); } bool merge(int a, int b) { a = find(a); b = find(b); if (a == b) return false; if (uf[a] <= uf[b]) { uf[b] = a; if (uf[a] == uf[b]) { uf[a]--; } num_segments[a] = min(num_segments[a] + num_segments[b], 2 * (int)uf.size()); used[a] = used[a] || used[b]; } else if (uf[b] < uf[a]) { uf[a] = b; num_segments[b] = min(num_segments[a] + num_segments[b], 2 * (int)uf.size()); used[b] = used[a] || used[b]; } return true; } }; int main() { ios::sync_with_stdio(false); cin.tie(0); int N, K; cin >> N >> K; string s; cin >> s; vector<vector<int>> groups(K); vector<vector<int>> groups_for_bit(N); for (int i = 0; i < K; ++i) { int k; cin >> k; groups[i].resize(k); for (int j = 0; j < k; ++j) { cin >> groups[i][j]; groups[i][j]--; groups_for_bit[groups[i][j]].push_back(i); } } auto inverse = [](int x) { return x ^ 1; }; union_find uf(2 * K); int num_segments = 0; auto unset = [&](int i) { if (uf.used[i]) { uf.used[i] = false; num_segments -= uf.num_segments[i]; ; } }; auto set = [&](int i) { assert(!uf.used[i]); uf.used[i] = true; num_segments += uf.num_segments[i]; ; }; for (int i = 0; i < N; ++i) { ; int g = -1; if (groups_for_bit[i].size() == 0) { ; } else if (groups_for_bit[i].size() == 1) { g = uf.find(2 * groups_for_bit[i][0]); int ig = uf.find(inverse(g)); ; unset(g); unset(ig); if (s[i] == 0 ) { uf.num_segments[ig] = N * 3; } else { uf.num_segments[g] = N * 3; } } else { g = uf.find(2 * groups_for_bit[i][0]); int h = uf.find(2 * groups_for_bit[i][1]); int ig = uf.find(inverse(g)); int ih = uf.find(inverse(h)); ; ; unset(g); unset(ig); unset(h); unset(ih); if (s[i] == 0 ) { uf.merge(ig, h); uf.merge(g, ih); } else { uf.merge(g, h); uf.merge(ig, ih); } } if (g >= 0) { g = uf.find(g); int ig = uf.find(inverse(g)); set(uf.num_segments[g] <= uf.num_segments[ig] ? g : ig); } cout << num_segments << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, cv; long long level[3501]; long long vis[3501] = {}; vector<long long> graph[3501]; vector<long long> cycles[3501]; vector<long long> z; void dfs_cycle(long long u, long long p, long long color[], long long mark[], long long par[], long long& cyclenumber) { if (color[u] == 2) { return; } if (color[u] == 1) { cyclenumber++; long long cur = p; mark[cur] = cyclenumber; while (cur != u) { cur = par[cur]; mark[cur] = cyclenumber; } return; } par[u] = p; color[u] = 1; for (long long v : graph[u]) { if (v == par[u]) { continue; } dfs_cycle(v, u, color, mark, par, cyclenumber); } color[u] = 2; } void printCycles(long long edges, long long mark[], long long& cyclenumber) { for (long long i = 1; i <= edges; i++) { if (mark[i] != 0) cycles[mark[i]].push_back(i); } for (long long i = 1; i <= cyclenumber; i++) { for (long long x : cycles[i]) z.push_back(x); } } void bfs(long long s) { queue<long long> q; q.push(s); level[s] = 0; vis[s] = 1; while (!q.empty()) { long long p = q.front(); q.pop(); for (long long i = 0; i < graph[p].size(); i++) { if (vis[graph[p][i]] == 0) { level[graph[p][i]] = min(level[graph[p][i]], level[p] + 1); q.push(graph[p][i]); vis[graph[p][i]] = 1; } } } } void quickly_quickly_kro() { cin >> n; for (long long i = 1; i < n + 1; i++) { long long a, b; cin >> a >> b; graph[a].push_back(b); graph[b].push_back(a); } long long color[3501]; long long par[3501]; long long mark[3501]; long long cyclenumber = 0; long long edges = n; dfs_cycle(1, 0, color, mark, par, cyclenumber); printCycles(edges, mark, cyclenumber); for (long long i = 1; i < n + 1; i++) level[i] = (long long)2e18; for (auto k : z) { for (long long i = 1; i < n + 1; i++) { vis[i] = 0; } bfs(k); } for (long long i = 1; i < n + 1; i++) { cout << level[i] << ; } } signed main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) { quickly_quickly_kro(); cout << n ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// BCHDecoderCommandReception for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder command reception controller
// Module Name: BCHDecoderCommandReception
// File Name: BCHDecoderCommandReception.v
//
// Version: v1.0.0
//
// Description: BCH decoder command reception
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
module BCHDecoderCommandReception
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter ThisID = 2
)
(
iClock ,
iReset ,
iSrcOpcode ,
iSrcTargetID ,
iSrcSourceID ,
iSrcAddress ,
iSrcLength ,
iSrcCmdValid ,
oSrcCmdReady ,
oQueuedCmdType ,
oQueuedCmdSourceID ,
oQueuedCmdTargetID ,
oQueuedCmdOpcode ,
oQueuedCmdAddress ,
oQueuedCmdLength ,
oQueuedCmdValid ,
iQueuedCmdReady
);
input iClock ;
input iReset ;
input [5:0] iSrcOpcode ;
input [4:0] iSrcTargetID ;
input [4:0] iSrcSourceID ;
input [AddressWidth - 1:0] iSrcAddress ;
input [InnerIFLengthWidth - 1:0] iSrcLength ;
input iSrcCmdValid ;
output oSrcCmdReady ;
output [1:0] oQueuedCmdType ;
output [4:0] oQueuedCmdSourceID ;
output [4:0] oQueuedCmdTargetID ;
output [5:0] oQueuedCmdOpcode ;
output [AddressWidth - 1:0] oQueuedCmdAddress ;
output [InnerIFLengthWidth - 1:0] oQueuedCmdLength ;
output oQueuedCmdValid ;
input iQueuedCmdReady ;
reg [1:0] rCmdType ;
reg [4:0] rCmdSourceID ;
reg [4:0] rCmdTargetID ;
reg [5:0] rCmdOpcode ;
reg [AddressWidth - 1:0] rCmdAddress ;
reg [InnerIFLengthWidth - 1:0] rCmdLength ;
wire wJobQueuePushSignal ;
wire wJobQueuePopSignal ;
wire wJobQueueFull ;
wire wJobQueueEmpty ;
parameter DispatchCmd_PageWriteToRAM = 6'b000001 ;
parameter DispatchCmd_SpareWriteToRAM = 6'b000010 ;
parameter ECCCtrlCmdType_Bypass = 2'b00 ;
parameter ECCCtrlCmdType_PageDecode = 2'b01 ;
parameter ECCCtrlCmdType_SpareDecode = 2'b10 ;
parameter ECCCtrlCmdType_ErrcntReport = 2'b11 ;
localparam State_Idle = 1'b0 ;
localparam State_PushCmdJob = 1'b1 ;
reg rCurState ;
reg rNextState ;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
if (iSrcCmdValid)
rNextState <= State_PushCmdJob;
else
rNextState <= State_Idle;
State_PushCmdJob:
rNextState <= (!wJobQueueFull)?State_Idle:State_PushCmdJob;
default:
rNextState <= State_Idle;
endcase
assign oSrcCmdReady = (rCurState == State_Idle);
always @ (posedge iClock)
if (iReset)
rCmdType <= 2'b0;
else
if (iSrcCmdValid && rCurState == State_Idle)
begin
if (iSrcTargetID == ThisID)
rCmdType <= ECCCtrlCmdType_ErrcntReport;
else if (iSrcTargetID == 0 && iSrcOpcode == DispatchCmd_PageWriteToRAM)
rCmdType <= ECCCtrlCmdType_PageDecode;
else if (iSrcTargetID == 0 && iSrcOpcode == DispatchCmd_SpareWriteToRAM)
rCmdType <= ECCCtrlCmdType_SpareDecode;
else
rCmdType <= ECCCtrlCmdType_Bypass;
end
always @ (posedge iClock)
if (iReset)
begin
rCmdSourceID <= 5'b0;
rCmdTargetID <= 5'b0;
rCmdOpcode <= 6'b0;
rCmdAddress <= {(AddressWidth){1'b0}};
rCmdLength <= {(InnerIFLengthWidth){1'b0}};
end
else
if (iSrcCmdValid && rCurState == State_Idle)
begin
rCmdSourceID <= iSrcSourceID ;
rCmdTargetID <= iSrcTargetID ;
rCmdOpcode <= iSrcOpcode ;
rCmdAddress <= iSrcAddress ;
rCmdLength <= iSrcLength ;
end
assign wJobQueuePushSignal = (rCurState == State_PushCmdJob) && !wJobQueueFull;
AutoFIFOPopControl
Inst_JobQueueAutoPopControl
(
.iClock (iClock ),
.iReset (iReset ),
.oPopSignal (wJobQueuePopSignal ),
.iEmpty (wJobQueueEmpty ),
.oValid (oQueuedCmdValid ),
.iReady (iQueuedCmdReady )
);
SCFIFO_128x64_withCount
Inst_JobQueue
(
.iClock (iClock ),
.iReset (iReset ),
.iPushData (
{
rCmdAddress,
rCmdLength,
rCmdOpcode,
rCmdSourceID,
rCmdTargetID,
rCmdType
}
),
.iPushEnable (wJobQueuePushSignal ),
.oIsFull (wJobQueueFull ),
.oPopData (
{
oQueuedCmdAddress,
oQueuedCmdLength,
oQueuedCmdOpcode,
oQueuedCmdSourceID,
oQueuedCmdTargetID,
oQueuedCmdType
}
),
.iPopEnable (wJobQueuePopSignal ),
.oIsEmpty (wJobQueueEmpty ),
.oDataCount ( )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; int a = 1; int b = N; for (int i = 2; N / i >= i; i++) if (N % i == 0) a = i, b = N / i; cout << a << << b << n ; }
|
`timescale 1ns / 1ps
module dewater_mode
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 2)
(
input dewater_start, input start, input power, input [31:0]clk,
input [2:0]weight,
output reg dewater_end_sign,
//light
output reg dewatering_light,output reg water_out_light,
output [2:0]water_level, output reg [31:0]dewater_count
);
reg [1:0]state, nextstate;
reg water_out_start, dewatering_start; // control sbumodules' running
wire [31:0]dewatering_count; // dewatering time
wire [2:0]water_level_dewater; // dewater water level
wire water_out_end_sign, water_in_end_sign, dewatering_end_sign; // end sign return to controller
parameter water_out_state = 0, dewatering_state = 1, dewater_end_state = 2;
initial begin
state = water_out_state;
nextstate = water_out_state;
water_out_light = 1'b0;
dewatering_light = 1'b1; // light on when module start
water_out_start = 1'b0;
dewatering_start = 1'b0;
dewater_count = {32{1'b0}};
dewater_end_sign = 1'b0;
end
assign water_level = (state == water_out_state) ? water_level_dewater : 3'b000;
// water_let mode run when start sign nd power are both true
water_let_mode #(WIDTH, CLK_CH, TIME_SCORE) WATER_OUT_MODE (.water_out_end_sign(water_out_end_sign),
.water_in_end_sign(water_in_end_sign),
.water_out_start(water_out_start),
.water_in_start(1'b0),
.clk(clk),
.power(power),
.max_water_level(weight),
.start(start),
.water_level(water_level_dewater)
);
// count time
timer #(WIDTH, CLK_CH, TIME_SCORE) TIMER_WASH (.clk_src(clk),
.switch_power(power),
.switch_en(start),
.sum_count({{29{1'b0}},weight}),
.count_start_flag(dewatering_start),
.count_end_flag(dewatering_end_sign),
.count(dewatering_count)
);
// change state
always @(posedge clk[0])
begin
if(power & dewater_start & start) state <= nextstate;
else if(!(power & dewater_start)) begin
state <= water_out_state;
end
end
// control light
always @(posedge clk[CLK_CH])
if(dewater_start & power)
begin
case(state)
water_out_state: begin water_out_light = ~water_out_light; dewatering_light = 1'b1; end
dewatering_state: begin water_out_light = 1'b0; dewatering_light = ~dewatering_light; end
dewater_end_state: begin dewatering_light = 1'b0; end
endcase
end
else begin
water_out_light = 1'b0; dewatering_light = 1'b1;
end
// control time
always @(posedge clk[0])
begin
if(dewater_start & power) begin
case(state)
water_out_state: begin dewater_count = {{29{1'b0}},weight} + {{29{1'b0}},water_level}; dewater_end_sign = 1'b0; end
dewatering_state: dewater_count = dewatering_count;
dewater_end_state: begin dewater_count = 0; dewater_end_sign = 1'b1; end
endcase
end else begin
dewater_count = 0; dewater_end_sign = 1'b0;
end
end
// control submodule start
always @(state or power or dewater_start or start)
if(dewater_start & power & start) begin
case(state)
water_out_state: begin water_out_start = 1'b1; dewatering_start = 1'b0; end
dewatering_state: begin water_out_start = 1'b0; dewatering_start = 1'b1; end
dewater_end_state: begin dewatering_start = 1'b0; water_out_start = 1'b0; end
endcase
end
else if(!(dewater_start & power)) begin
water_out_start = 1'b0; dewatering_start = 1'b0;
end
// change nextstate
always @(water_out_end_sign or dewatering_end_sign or dewater_start or power)
if(power & dewater_start)
begin
case(state)
water_out_state:begin
if(water_out_end_sign)
nextstate = dewatering_state;
else nextstate = water_out_state;
end
dewatering_state: begin
if(dewatering_end_sign)
nextstate = dewater_end_state;
else nextstate = dewatering_state;
end
dewater_end_state: begin
nextstate = dewater_end_state;
end
endcase
end else begin
nextstate = water_out_state;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long double sq(long double a) { return a * a; } long double dist(pair<long double, long double> a, pair<long double, long double> b) { return sqrt((long double)(sq(a.second - b.second) + sq(a.first - b.first))); } long double mandist(pair<long long, long long> a, pair<long long, long long> b) { return abs(a.second - b.second) + abs(a.first - b.first); } long long a, b, c; pair<long long, long long> p1, p2; int main() { scanf( %lld%lld%lld , &a, &b, &c); scanf( %lld%lld%lld%lld , &p1.first, &p1.second, &p2.first, &p2.second); if (a == 0 || b == 0) printf( %.20Lf n , mandist(p1, p2)); else { long double res = mandist(p1, p2); long double interhoriz1 = ((long double)(-c - a * p1.first)) / ((long double)b); long double interhoriz2 = ((long double)(-c - a * p2.first)) / ((long double)b); long double intervert1 = ((long double)(-c - b * p1.second)) / ((long double)a); long double intervert2 = ((long double)(-c - b * p2.second)) / ((long double)a); res = min(res, abs((long double)p1.second - interhoriz1) + abs((long double)p2.second - interhoriz2) + dist(make_pair((long double)p1.first, interhoriz1), make_pair((long double)p2.first, interhoriz2))); res = min(res, abs((long double)p1.second - interhoriz1) + abs((long double)p2.first - intervert2) + dist(make_pair((long double)p1.first, interhoriz1), make_pair(intervert2, (long double)p2.second))); res = min(res, abs((long double)p1.first - intervert1) + abs((long double)p2.first - intervert2) + dist(make_pair(intervert1, (long double)p1.second), make_pair(intervert2, (long double)p2.second))); res = min(res, abs((long double)p1.first - intervert1) + abs((long double)p2.second - interhoriz2) + dist(make_pair(intervert1, (long double)p1.second), make_pair((long double)p2.first, interhoriz2))); printf( %.20Lf n , res); } }
|
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; using namespace std; int v[5005]; int main() { int t1; cin >> t1; for (int t = 1; t <= t1; t++) { int n, d; cin >> n >> d; memset(v, 0, sizeof(v)); int l = 1, nr = n - 1; v[0] = 1; for (; nr >= v[l - 1] * 2; l++) { v[l] = v[l - 1] * 2; d -= v[l] * l; nr -= v[l]; } if (nr == 0) l--; else d -= nr * l, v[l] = nr; if (d < 0) { cout << NO n ; continue; } int l2; for (l2 = l; d > 0 && l >= 1; l--) { if (v[l] == 1) continue; if (l2 + 1 - l > d) { v[l]--; v[l + d]++; d = 0; break; } v[++l2] = 1; d -= l2 - l; v[l]--; l++; } if (d == 0) { cout << YES n ; queue<int> p[5005]; p[0].push(1); p[0].push(1); for (int i = 1, node = 2; i <= l2; i++) if (v[i] > 0) { cout << p[i - 1].front() << ; p[i - 1].pop(); p[i].push(node); p[i].push(node); v[i--]--; node++; } cout << n ; } else { cout << NO n ; } } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// GLOBAL_LOGIC
//
// Description: The GLOBAL_LOGIC module handles channel bonding, channel error manangement
// and channel bond block code generation.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_GLOBAL_LOGIC #
(
parameter INTER_CB_GAP = 5'd9
)
(
// GTX Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
CHAN_BOND_RESET,
// Aurora Lane Interface
LANE_UP,
HARD_ERR,
GEN_NA_IDLES,
GEN_CH_BOND,
RESET_LANES,
GOT_NA_IDLES,
GOT_CCS,
REMOTE_READY,
GOT_CBS,
GOT_IDLES,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP_RX_IF,
CHANNEL_UP_TX_IF,
CHANNEL_HARD_ERR,
TXDATAVALID_IN
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTX Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
output CHAN_BOND_RESET;
// Aurora Lane Interface
input LANE_UP;
input HARD_ERR;
input GOT_NA_IDLES;
input GOT_CCS;
input REMOTE_READY;
input GOT_CBS;
input GOT_IDLES;
output GEN_NA_IDLES;
output GEN_CH_BOND;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input TXDATAVALID_IN;
output CHANNEL_UP_RX_IF;
output CHANNEL_UP_TX_IF;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire reset_channel_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_64b66b_25p4G_CHANNEL_INIT_SM channel_init_sm_i
(
// GTX Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
.CHAN_BOND_RESET(CHAN_BOND_RESET),
// Aurora Lane Interface
.GEN_NA_IDLES(GEN_NA_IDLES),
.RX_NA_IDLES(GOT_NA_IDLES),
.RX_CC(GOT_CCS),
.REMOTE_READY(REMOTE_READY),
.RX_CB(GOT_CBS),
.RX_IDLES(GOT_IDLES),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.LANE_UP(LANE_UP),
.CHANNEL_UP_TX_IF(CHANNEL_UP_TX_IF),
.CHANNEL_UP_RX_IF(CHANNEL_UP_RX_IF)
);
// Idle and verification sequence generator module.
aurora_64b66b_25p4G_CHANNEL_BOND_GEN #
(
.INTER_CB_GAP (INTER_CB_GAP)
)channel_bond_gen_i
(
// Channel Init SM Interface
.CHANNEL_UP(CHANNEL_UP_TX_IF),
// Aurora Lane Interface
.GEN_CH_BOND(GEN_CH_BOND),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.TXDATAVALID_IN(TXDATAVALID_IN)
);
// Channel Error Management module.
aurora_64b66b_25p4G_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR)
);
endmodule
|
module top;
typedef reg [4:0] T1;
typedef T1 [7:0] T2;
T2 q_tst [$];
T2 q_tmp [$];
T2 elem;
integer idx;
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1'b0;
end
endtask
task automatic check_idx_value(integer idx,
T2 expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != %0d (%0d)",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1'b0;
end
endtask
initial begin
passed = 1'b1;
q_tst.delete(0); // Warning: skip delete on an empty queue
check_size(0, `__FILE__, `__LINE__);
check_idx_value(0, 0, `__FILE__, `__LINE__);
elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue
if (elem !== 'X) begin
$display("Failed: pop_front() != 'X (%0d)", elem);
passed = 1'b0;
end
elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue
if (elem !== 'X) begin
$display("Failed: pop_back() != 'X (%0d)", elem);
passed = 1'b0;
end
q_tst.push_back(2);
q_tst.push_front(1);
q_tst.push_back(3);
q_tst.push_back(100);
q_tst.delete(3); // Should $ work here?
q_tst.delete(3); // Warning: skip an out of range delete()
q_tst.delete(-1); // Warning: skip delete with negative index
q_tst.delete('X); // Warning: skip delete with undefined index
check_size(3, `__FILE__, `__LINE__);
if (q_tst[0] !== 1) begin
$display("Failed: element [0] != 1 (%0d)", q_tst[0]);
passed = 1'b0;
end
if (q_tst[1] !== 2) begin
$display("Failed: element [1] != 2 (%0d)", q_tst[1]);
passed = 1'b0;
end
if (q_tst[2] !== 3) begin
$display("Failed: element [2] != 3 (%0d)", q_tst[2]);
passed = 1'b0;
end
if (q_tst[3] !== 'X) begin
$display("Failed: element [3] != 'X (%0d)", q_tst[3]);
passed = 1'b0;
end
if (q_tst[-1] !== 'X) begin
$display("Failed: element [-1] != 'X (%0d)", q_tst[-1]);
passed = 1'b0;
end
if (q_tst['X] !== 'X) begin
$display("Failed: element ['X] != 'X (%0d)", q_tst['X]);
passed = 1'b0;
end
check_idx_value(-1, 0.0, `__FILE__, `__LINE__);
check_idx_value('X, 0.0, `__FILE__, `__LINE__);
elem = q_tst.pop_front();
if (elem !== 1) begin
$display("Failed: element pop_front() != 1 (%0d)", elem);
passed = 1'b0;
end
elem = q_tst.pop_back();
if (elem !== 3) begin
$display("Failed: element pop_back() != 3 (%0d)", elem);
passed = 1'b0;
end
check_size(1, `__FILE__, `__LINE__);
if ((q_tst[0] !== q_tst[$]) || (q_tst[0] !== 2)) begin
$display("Failed: q_tst[0](%0d) != q_tst[$](%0d) != 2",
q_tst[0], q_tst[$]);
passed = 1'b0;
end
q_tst.delete();
check_size(0, `__FILE__, `__LINE__);
q_tst.push_front(5);
q_tst.push_front(100);
q_tst.push_back(100);
elem = q_tst.pop_back;
elem = q_tst.pop_front;
check_size(1, `__FILE__, `__LINE__);
check_idx_value(0, 5, `__FILE__, `__LINE__);
q_tst[0] = 1;
q_tst[1] = 3;
q_tst[1] = 2;
q_tst[2] = 3;
q_tst[-1] = 10; // Warning: will not be added (negative index)
q_tst['X] = 10; // Warning: will not be added (undefined index)
q_tst[4] = 10; // Warning: will not be added (out of range index)
idx = -1;
q_tst[idx] = 10; // Warning: will not be added (negative index)
idx = 3'b0x1;
q_tst[idx] = 10; // Warning: will not be added (undefined index)
idx = 4;
q_tst[idx] = 10; // Warning: will not be added (out of range index)
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tst.delete();
q_tst[0] = 2;
q_tst.insert(1, 4);
q_tst.insert(0, 1);
q_tst.insert(2, 3);
q_tst.insert(-1, 10); // Warning: will not be added (negative index)
q_tst.insert('X, 10); // Warning: will not be added (undefined index)
q_tst.insert(5, 10); // Warning: will not be added (out of range index)
check_size(4, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
check_idx_value(3, 4, `__FILE__, `__LINE__);
q_tst = '{3, 2, 1};
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 3, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 1, `__FILE__, `__LINE__);
q_tmp = '{1, 2};
q_tst = q_tmp;
q_tmp[0] = 3;
q_tmp[2] = 1;
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
q_tst[2] = 3;
check_size(3, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tst = {1, 2};
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
q_tst = '{};
check_size(0, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
#include <bits/stdc++.h> using std::cin; using std::cout; using std::endl; using std::ifstream; using std::max; using std::min; using std::ofstream; using std::string; int dp[2204][2204]; int vec[21][2]; int x, y, vec_num_n, max_dist_d; int dfs(int ori_x, int ori_y, int off_x, int off_y) { if (dp[off_x][off_y] >= 0) { return dp[off_x][off_y]; } int cur_x = ori_x + off_x; int cur_y = ori_y + off_y; if (cur_x * cur_x + cur_y * cur_y > max_dist_d * max_dist_d) { return dp[off_x][off_y] = 0; } for (int vec_i = 0; vec_i < vec_num_n; ++vec_i) { int next_x = vec[vec_i][0] + off_x; int next_y = vec[vec_i][1] + off_y; if (dfs(ori_x, ori_y, next_x, next_y)) { return dp[off_x][off_y] = 0; } } return dp[off_x][off_y] = 1; } int main() { cin >> x >> y >> vec_num_n >> max_dist_d; for (int vec_i = 0; vec_i < vec_num_n; ++vec_i) { cin >> vec[vec_i][0] >> vec[vec_i][1]; } memset(dp, -1, sizeof(dp)); if (!dfs(x, y, 0, 0)) { cout << Anton << endl; } else { cout << Dasha << endl; } return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_0_4 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:59 09/20/2015
// Design Name:
// Module Name: Gato_Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Gato_Top(
input clk , reset_all, //Entradas de reloj y reset
input reset_game, //Resetea el juego
input boton_arriba, //Botones
input boton_abajo,
input boton_izq,
input boton_der,
input boton_elige,
output hsync,vsync, //Salidas VGA
output [2:0] rgb, //Salidas VGA
output [3:0] cuadro
);
//Reloj del sincronizador, FSM y demas modulos
wire clk_sys;
//Cables para conectar modulos
wire [3:0] cuadro;
wire [1:0] vertical;
wire [1:0] horizontal;
wire [1:0] cruzada;
wire [2:0] state;
wire turno_p1_wire;
wire turno_p2_wire;
wire win_game;
wire loss_game;
wire tie_game;
wire [1:0]
c1,
c2,
c3,
c4,
c5,
c6,
c7,
c8,
c9;
//Se;ales de botones sincronizadas
wire boton_arriba_sync;
wire boton_abajo_sync;
wire boton_izq_sync;
wire boton_der_sync;
wire boton_elige_sync;
//Cables de modulo VGA
wire[10:0] pix_x, pix_y;
wire video_on;
wire clk_VGA;
wire hsync_out;
wire vsync_out;
assign hsync = ~hsync_out;
assign vsync = ~vsync_out;
Sincronizador debouncer (
._clk_(clk_sys),
.boton_arriba_in(boton_arriba),
.boton_abajo_in(boton_abajo),
.boton_izq_in(boton_izq),
.boton_der_in(boton_der),
.boton_elige_in(boton_elige),
.boton_arriba_out(boton_arriba_sync),
.boton_abajo_out(boton_abajo_sync),
.boton_izq_out(boton_izq_sync),
.boton_der_out(boton_der_sync),
.boton_elige_out(boton_elige_sync)
);
Controlador_Gato controlador_juego (
.clk(clk_sys),
.reset_all(reset_all),
.reset_game(reset_game),
.cuadro(cuadro),
.vertical(vertical),
.horizontal(horizontal),
.cruzada(cruzada),
.state(state),
.c1_out_registro(c1),
.c2_out_registro(c2),
.c3_out_registro(c3),
.c4_out_registro(c4),
.c5_out_registro(c5),
.c6_out_registro(c6),
.c7_out_registro(c7),
.c8_out_registro(c8),
.c9_out_registro(c9),
.boton_arriba_reg(boton_arriba_sync),
.boton_abajo_reg(boton_abajo_sync),
.boton_izq_reg(boton_izq_sync),
.boton_der_reg(boton_der_sync),
.boton_elige_reg(boton_elige_sync),
.turno_p1_wire(turno_p1_wire),
.turno_p2_wire(turno_p2_wire),
.win_game_wire(win_game),
.loss_game_wire(loss_game),
.tie_game_wire(tie_game)
);
//Se inicializa el sincronizador VGA
VGA_Controlador vsync_unit (
._clk_(clk_VGA),
._reset_(reset),
.hsync(hsync_out),
.vsync(vsync_out),
.PixelX(pix_x),
.PixelY(pix_y),
.video_encendido(video_on));
//Se inicializa el generador de graficos
figuras_Gato graficos(
.video_mostrar(video_on),
.selector_entrada(cuadro),
.c1_in(c1),
.c2_in(c2),
.c3_in(c3),
.c4_in(c4),
.c5_in(c5),
.c6_in(c6),
.c7_in(c8),
.c8_in(c7),
.c9_in(c9),
.pixel_x(pix_x),
.pixel_y(pix_y),
.salida_rgb(rgb)
);
//Reloj de 25Mhz
CLK_25Mhz clock25 (.CLK_IN(clk), .CLK_OUT(clk_VGA), .CLK_OUTSYS(clk_sys));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, now, p[20000], p_, g[10], ans; int xx[10]; int tmp[10000]; int yoo[2][10000][10], f[1000][1000]; void dfs(int k) { int tmp = 0; for (int i = 1; i < k; ++i) tmp = tmp * 10 + xx[i] / g[k + 1] % 10; if (k == n) { ans += ::tmp[tmp]; return; } for (int v = yoo[0][tmp][n - k + 1]; v <= yoo[1][tmp][n - k + 1]; v++) { xx[k] = p[v]; dfs(k + 1); } } int dfss(int k) { int tmp = 0; for (int i = 1; i < k; ++i) tmp = tmp * 10 + xx[i] / g[k + 1] % 10; if (k == n - 1) { int ppp = 0; for (int i = 1; i < k; ++i) ppp = ppp * 10 + xx[i] / g[k + 2] % 10; if (f[tmp][ppp] != -1) { ans += f[tmp][ppp]; return 0; } f[tmp][ppp] = 0; for (int v = yoo[0][tmp][n - k + 1]; v <= yoo[1][tmp][n - k + 1]; v++) { xx[k] = p[v]; f[tmp][ppp] += dfss(k + 1); } return 0; } if (k == n) { ans += ::tmp[tmp]; return ::tmp[tmp]; } for (int v = yoo[0][tmp][n - k + 1]; v <= yoo[1][tmp][n - k + 1]; v++) { xx[k] = p[v]; dfss(k + 1); } } int main() { int test; cin >> test; for (int i = 2; i <= 99999; ++i) { bool can = 1; for (int j = 0; j < p_; ++j) if (i % p[j] == 0) { can = 0; break; } if (can) p[p_++] = i; } g[0] = 100000; g[1] = 10000; g[2] = 1000; g[3] = 100; g[4] = 10; g[5] = 1; memset(yoo[1], -1, sizeof yoo[1]); memset(yoo[0], 63, sizeof yoo[0]); memset(f, -1, sizeof f); for (int i = 0; i < p_; ++i) for (int j = 0; j < 5; ++j) if (4 == j) tmp[p[i] / g[j]]++; else yoo[0][p[i] / g[j + 1]][4 - j] = min(yoo[0][p[i] / g[j + 1]][4 - j], i), yoo[1][p[i] / g[j + 1]][4 - j] = max(yoo[1][p[i] / g[j + 1]][4 - j], i); for (; test--;) { ans = 0; cin >> now; ans = 0; n = 0; for (int i = now; i; i /= 10) n++; g[n + 1] = 1; for (int i = 0; i < n; ++i) g[n - i] = g[n - i + 1] * 10; xx[1] = now; if (n < 5) dfs(2); else dfss(2); cout << ans << endl; } return 0; }
|
//
// xc3s500e_godil.v - SPI loader for GODIL with XC3S500E
//
// Copied from bscan_s3e_starter.v.
// Then the starter specific signals removed.
// Top level module renamed from top to xc3s500e_godil.
// Use with a .ucf file with the right PIN assignments.
//
module xc3s500e_godil
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
// output wire dac_cs,
// output wire amp_cs,
// output wire ad_conv,
// output wire sf_ce0,
// output wire fpga_init_b,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
// assign dac_cs = 1;
// assign amp_cs = 1;
// assign ad_conv = 0;
// assign sf_ce0 = 1;
// assign fpga_init_b = 1;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TDI(TDI),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1'b0)
);
`include "bscan_common.v"
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v; int n, i, j, k, value; cin >> n; int x = n; while (x--) { cin >> value; v.push_back(value); } for (i = 0; i < n; i++) for (j = 0; j < n; j++) { if (i == j) j++; for (k = j + 1; k <= n - 1; k++) { if (k == i) k++; if (k == n) break; if (v[i] == v[j] + v[k]) { cout << i + 1 << << k + 1 << << j + 1; return 0; } } } cout << -1 ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A311OI_BEHAVIORAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_MS__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, dd, hh, mm, t; int sep[16]; char buf[80]; vector<string> todo; map<string, int> cost; vector<pair<int, int> > time; vector<vector<pair<int, bool> > > dp; vector<pair<pair<int, int>, pair<int, int> > > job; scanf( %d%d%d , &n, &m, &dd); for (int i = 0; i < n; ++i) { scanf( %s , buf); todo.push_back(buf); } for (int i = 0; i < n; ++i) { scanf( %d , &cost[todo[i]]); } for (int i = 0; i < 8; ++i) { scanf( %*[^0-9]%d:%d , &hh, &mm); sep[i] = hh * 60 + mm; } for (int i = 1, k = 0; i <= dd; ++i) { for (int j = 0; j < 24 * 60; ++j) { if (k % 2 == 0 && j == sep[k]) { k = (k + 1) % 8; } if (k % 2 == 0) { time.push_back(make_pair(i, j)); } if (k % 2 != 0 && j == sep[k]) { k = (k + 1) % 8; } } } for (int i = 0; i < m; ++i) { scanf( %s%d%d:%d%d , buf, &dd, &hh, &mm, &t); if (cost.count(buf) == 0) { continue; } job.push_back(make_pair(make_pair(lower_bound(time.begin(), time.end(), make_pair(dd, hh * 60 + mm)) - time.begin(), i), make_pair(cost[buf], t))); } sort(job.begin(), job.end()); reverse(job.begin(), job.end()); n = time.size(); m = job.size(); dp = vector<vector<pair<int, bool> > >(1, vector<pair<int, bool> >(n + 1)); for (int i = 0; i < m; ++i) { t = job[i].second.first; dp.push_back(dp.back()); for (int j = 0; j <= n; ++j) { dp[i + 1][j].second = false; } for (int j = t; j <= job[i].first.first; ++j) { if (dp[i + 1][j - t].first < dp[i][j].first + job[i].second.second) { dp[i + 1][j - t].first = dp[i][j].first + job[i].second.second; dp[i + 1][j - t].second = true; } } } printf( %d n , dp[m][0].first); todo.clear(); for (int i = m - 1, j = 0; i >= 0; --i) { if (dp[i + 1][j].second) { t = j + job[i].second.first - 1; sprintf(buf, %d %d %02d:%02d %d %02d:%02d , job[i].first.second + 1, time[j].first, time[j].second / 60, time[j].second % 60, time[t].first, time[t].second / 60, time[t].second % 60); todo.push_back(buf); j = t + 1; } } printf( %d n , todo.size()); for (int i = 0; i < (int)todo.size(); ++i) { puts(todo[i].c_str()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> using vv = vector<vector<T>>; template <class T> inline bool MX(T &l, const T &r) { return l < r ? l = r, 1 : 0; } template <class T> inline bool MN(T &l, const T &r) { return l > r ? l = r, 1 : 0; } const long long MOD = 1e9 + 7; int N; long long C[114514]; long long T[114514]; vector<long long> ds, es; int main() { scanf( %d , &N); for (int(i) = 0; (i) < (N); ++(i)) { scanf( %lld , &C[i]); if (i > 0) ds.emplace_back(C[i] - C[i - 1]); } for (int(i) = 0; (i) < (N); ++(i)) { scanf( %lld , &T[i]); if (i > 0) es.emplace_back(T[i] - T[i - 1]); } sort((ds).begin(), (ds).end()); sort((es).begin(), (es).end()); if (C[0] != T[0]) { puts( No ); return 0; } assert((int)ds.size() == N - 1); assert((int)es.size() == N - 1); for (int(i) = 0; (i) < (N - 1); ++(i)) { if (ds[i] != es[i]) { puts( No ); return 0; } } puts( Yes ); }
|
#include <bits/stdc++.h> using namespace std; const int _ = 600 + 7; const int __ = 1e5 + 7; const int S = 601, T = 602; const int inf = 0x3f3f3f3f; int n; int lst[_], nxt[__], to[__], cap[__], tot = 1; long long ans; int gi() { int x = 0; bool f = 0; char c = getchar(); while (!isdigit(c) and c != - ) c = getchar(); if (c == - ) f = 1, c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); return f ? -x : x; } void Add(int x, int y, int c) { nxt[++tot] = lst[x]; to[tot] = y; cap[tot] = c; lst[x] = tot; nxt[++tot] = lst[y]; to[tot] = x; cap[tot] = 0; lst[y] = tot; } void Init() { n = gi(); for (int i = 1; i <= n; ++i) { int m = gi(); for (int j = 1; j <= m; ++j) Add(i, gi() + n, inf); } for (int i = 1; i <= n; ++i) { int v = gi(); ans -= v; Add(S, i, inf - v), Add(i + n, T, inf); } } int d[_], cur[_]; queue<int> q; bool Bfs() { memset(d, -1, sizeof d); while (!q.empty()) q.pop(); d[S] = 0, q.push(S); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = lst[u]; i; i = nxt[i]) if (cap[i] and d[to[i]] == -1) { d[to[i]] = d[u] + 1, q.push(to[i]); if (to[i] == T) return 1; } } return 0; } int Dfs(int u, int flow) { if (u == T) return flow; int res = flow; for (int &i = cur[u]; i; i = nxt[i]) if (cap[i] and d[to[i]] == d[u] + 1) { int tmp = Dfs(to[i], min(res, cap[i])); cap[i] -= tmp, cap[i ^ 1] += tmp; res -= tmp; if (!res) return flow; } return flow - res; } void Run() { long long maxFlow = -1ll * n * inf; int flow; while (Bfs()) { memcpy(cur, lst, sizeof cur); do { flow = Dfs(S, inf); maxFlow += flow; } while (flow); } cout << min(0ll, -(ans - maxFlow)) << endl; } int main() { Init(); Run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> MP1, MP2; map<int, int>::iterator it; const int N = 300100; const long long INF = 3000 * 1000 * 1000LL; vector<int> v; int a[N]; long long ps[N]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, l, r; long long ans = -INF; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; if (!MP1.count(a[i])) MP1[a[i]] = i; MP2[a[i]] = i; ps[i] += ps[i - 1]; if (a[i] > 0) ps[i] += a[i]; } for (it = MP1.begin(); it != MP1.end(); it++) { if (MP2[it->first] != it->second) { long long t = ps[MP2[it->first]] - ps[it->second] + it->first; if (it->first < 0) t += it->first; if (t > ans) { ans = t; l = it->second; r = MP2[it->first]; } } } for (int i = 1; i <= n; i++) if ((i != l && i != r && a[i] < 0) || (i < l || i > r)) v.push_back(i); cout << ans << << v.size() << endl; for (int u : v) cout << u << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> #define pb push_back using namespace std; const int N = 3e5 + 5; vector<int> G[N], G0[N]; long long day; int cur, n, pv, pt, a[N], fa[N], dep[N]; int prv[N], pst[N], np[N], bp[N], ep[N]; void Build(int u) { for(int v : G0[u]) { if(v == fa[u]) continue; fa[v] = u; dep[v] = dep[u] + 1; Build(v); G[u].pb(v); } sort(G[u].begin(), G[u].end(), [](int x, int y){ return a[x] < a[y]; }); } void Dfs1(int u) { for(int v : G[u]) Dfs1(v); pst[u] = ++pt; ep[pt] = u; } bool Find(int u, int v) { if(u == v) return true; if(u == 1) return false; return Find(fa[u], v); } void Back(int u) { if(u == 1) return; swap(a[u], a[fa[u]]); day++; Back(fa[u]); } void Dfs2(int u) { if(a[u] < cur) return; prv[u] = pv; bp[pv++] = u; for(int v : G[u]) Dfs2(v); } void Dfs3(int u) { prv[u] = ++pv; for(int v : G[u]) Dfs3(v); } int main() { ios::sync_with_stdio(false); cin >> n; for(int i = 1; i <= n; i++) { cin >> a[i]; np[a[i]] = i; } for(int i = 1; i < n; i++) { int u, v; cin >> u >> v; G0[u].pb(v); G0[v].pb(u); } Build(1); Dfs1(1); if(a[1] == 1) { Dfs3(1); for(int i = 1; i <= n; i++) { if(prv[i] != a[i]) { cout << NO n ; return 0; } } cout << YES n0 n ; for(int i = 1; i <= n; i++) cout << prv[i] << ; return 0; } cur = a[1] - 1; if(!Find(ep[cur], np[cur])) { cout << NO n ; return 0; } Back(np[cur]); for(int i = 1; i <= n; i++) np[a[i]] = i; for(int i = 1; i < cur; i++) { if(np[i] != ep[i]) { cout << NO n ; return 0; } } pv = cur; Dfs2(1); for(int i = cur; i <= n; i++) { if(np[i] != bp[i]) { cout << NO n ; return 0; } } cout << YES n ; for(int i = 1; i < cur; i++) day += dep[np[i]]; cout << day << endl; pv = 0; Dfs3(1); for(int i = 1; i <= n; i++) cout << prv[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INFLL = 1e18; const int MAXN = 1e6 + 100; const long long INF = 1e9; const long long mod1 = 1e9 + 7; const long long mod2 = 2e9 + 11; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { long long a, b; cin >> a >> b; if (a == b) cout << 0 << n ; else { if (b < a) { if ((a - b) % 2 == 0) cout << 1 << n ; else cout << 2 << n ; } else { if ((a - b) % 2 == 0) cout << 2 << n ; else cout << 1 << n ; } } } }
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#include <bits/stdc++.h> using namespace std; const int INFTY = 20000000; const int MAX = 500100; const int MOD = 10000000; void coutTab(int* tab, int n) { for (int i = 0; i < n; i++) { cout << tab[i] << ; } cout << n ; } string create(int a, int b, int x, int start) { if (start == 0) a--; else b--; string s; s.push_back(start + 0 ); char l; for (int i = 0; i < x - 1; i++) { l = s[s.size() - 1]; if (l == 1 ) { s.push_back( 0 ); a--; } else { s.push_back( 1 ); b--; } } l = s[s.size() - 1]; if (l == 0 ) { while (a--) s.push_back( 0 ); while (b--) s.push_back( 1 ); } else { while (b--) s.push_back( 1 ); while (a--) s.push_back( 0 ); } return s; } bool check(string s, int x) { int j = 0; for (int i = 1; i < s.size(); i++) { if (s[i - 1] != s[i]) j++; } return x == j; } int main() { ios_base::sync_with_stdio(0); int a, b, x; cin >> a >> b >> x; string res = create(a, b, x, 0); if (!check(res, x)) res = create(a, b, x, 1); cout << res << n ; }
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#include <bits/stdc++.h> const int Maxn = 50005; int N, A[Maxn]; double L[Maxn], P[Maxn], Sum[Maxn], Ans; using namespace std; bool Cmp(const int &i, const int &j) { return (L[i] * P[i] * (1 - P[j] / 100)) > (L[j] * P[j] * (1 - P[i] / 100)); } int main() { scanf( %d , &N); for (int i = 1; i <= N; ++i) { scanf( %lf%lf , &L[i], &P[i]); A[i] = i; } sort(A + 1, A + 1 + N, Cmp); for (int i = 1; i <= N; ++i) Sum[i] = Sum[i - 1] + L[A[i]] * P[A[i]]; for (int i = 1; i <= N; ++i) Ans += L[i] * 10000; for (int i = 2; i <= N; ++i) Ans += (100 - P[A[i]]) * Sum[i - 1]; cout << setprecision(12) << setiosflags(ios ::fixed) << Ans / 10000 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int getint() { unsigned int c; int x = 0; while (((c = getchar()) - 0 ) >= 10) { if (c == - ) return -getint(); if (!~c) exit(0); } do { x = (x << 3) + (x << 1) + (c - 0 ); } while (((c = getchar()) - 0 ) < 10); return x; } char a1[] = ### ..# .#. #.. ; char a2[] = .#. ### .#. ### ; char a3[] = .#. ..# ### #.. ; vector<int> px[4], py[4]; int n, m, grid[10][10], mx, res[10][10]; void solve(int x, int y, int curr) { if (y >= m) { solve(x + 1, 0, curr); return; } if (x >= n) { if (curr > mx) mx = curr, memcpy(res, grid, sizeof(res)); return; } int i, j, k, d, tmp[10][10], nx, ny; int mxPossible = 0; for (i = y; i < m; i++) if (grid[x][i] == 0) mxPossible++; for (i = x; i < n; i++) for (j = 0; j < m; j++) if (grid[i][j] == 0) mxPossible++; mxPossible /= 5; if (mxPossible + curr <= mx) return; memcpy(tmp, grid, sizeof(tmp)); for (d = 0; d < 4; d++) { bool canPlace = 1; memcpy(grid, tmp, sizeof(tmp)); for (i = 0; i < px[d].size(); i++) { nx = x + px[d][i]; ny = y + py[d][i]; if (nx >= n or ny >= m or grid[nx][ny]) { canPlace = 0; break; } grid[nx][ny] = curr + 1; } if (canPlace) { solve(x, y + 1, curr + 1); } } memcpy(grid, tmp, sizeof(tmp)); solve(x, y + 1, curr); } int main() { int i, j, tcc, tc = 1 << 28; for (i = 0; i < 4; i++) { for (j = 0; j < 3; j++) if (a1[i * 4 + j] == # ) px[i].push_back(0), py[i].push_back(j); for (j = 0; j < 3; j++) if (a2[i * 4 + j] == # ) px[i].push_back(1), py[i].push_back(j); for (j = 0; j < 3; j++) if (a3[i * 4 + j] == # ) px[i].push_back(2), py[i].push_back(j); } for (tcc = 0; tcc < tc; tcc++) { n = getint(), m = getint(), mx = 0; if (n == 9 and m == 9) { puts( 13 ); puts( AAA.BCCC. n.ABBB.CD. n.AE.BFCD. nEEEFFFDDD nG.E.HFIII nGGGJHHHI. nGK.JHL.IM n.KJJJLMMM nKKK.LLL.M n ); continue; } memset(res, 0, sizeof(res)); memset(grid, 0, sizeof(grid)); solve(0, 0, 0); printf( %d n , mx); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (res[i][j] == 0) putchar( . ); else putchar( A + res[i][j] - 1); } puts( ); } puts( ); } return 0; }
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#include <bits/stdc++.h> using namespace std; void scan() {} template <typename F, typename... R> void scan(F &f, R &...r) { cin >> f; scan(r...); } int di_; string dnms_, co_ = , ; void debug_() { cout << endl; } template <typename F, typename... R> void debug_(F f, R... r) { while (dnms_[di_] != , ) cout << dnms_[di_++]; di_++; cout << : << f << , ; debug_(r...); } const int MAX = 200001; int n, __ptr = 0, arr[MAX]; inline int top() { return arr[__ptr]; } inline int pop() { return arr[__ptr++]; } inline bool empty() { return __ptr >= n; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); scan(n); for (int i = 0; i < n; ++i) scan(arr[i]); sort(arr, arr + n); int best = 0; for (int i = 1;; i++) { while (!empty() && top() < i) pop(); if (empty()) break; else pop(); best = max(best, i); } printf( %d n , best); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_1_V
`define SKY130_FD_SC_HD__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-8; const double PI = acos(-1); int n; long long h[N], dp[N][2]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &h[i]), h[i]--; h[n + 1] = inf; dp[1][0] = h[1]; dp[1][1] = min(h[1], h[2]); long long ans = dp[1][0]; for (int i = 2; i <= n; i++) { dp[i][0] = (dp[i - 1][1] * min(h[i - 1], h[i]) + h[i]) % mod; dp[i][1] = ((dp[i - 1][1] * min(h[i - 1], min(h[i], h[i + 1])) % mod) + min(h[i], h[i + 1])) % mod; ans = (ans + dp[i][0]) % mod; } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline long long read() { long long x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long a) { if (a < 0) { a = -a; putchar( - ); } if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void wri(long long a) { write(a); putchar( ); } inline void writeln(long long a) { write(a); puts( ); } const int N = 1 << 17 | 2, mod = 998244353; int sum, A[N], B[N], C[N], f[N]; long long ksm(long long a, int b) { a %= mod; int ans = 1; for (; b; b >>= 1) { if (b & 1) ans = ans * a % mod; a = a * a % mod; } return ans; } void FWT(int *a, int n) { for (int i = 0; i < n; i++) { for (int j = 0; j < (1 << n); j++) if (j >> i & 1) { int x = a[j]; a[j] = a[j ^ (1 << i)] >= x ? a[j ^ (1 << i)] - x : a[j ^ (1 << i)] - x + mod; a[j ^ (1 << i)] = a[j ^ (1 << i)] + x >= mod ? a[j ^ (1 << i)] + x - mod : a[j ^ (1 << i)] + x; } } } void ba(int &a) { if (a > mod / 2) a = a - mod; } signed main() { int n = read(), k = read(); int x = read(), y = read(), z = read(); for (int i = 0; i < n; i++) { int a = read(), b = read() ^ a, c = read() ^ a; sum ^= a; A[b]++; B[c]++; C[b ^ c]++; } FWT(A, k); FWT(B, k); FWT(C, k); for (int i = 0; i < (1 << k); i++) { int t1 = n, t2 = A[i], t3 = B[i], t4 = C[i]; ba(t2); ba(t3); ba(t4); f[i] = ksm((long long)x + y + z, (t1 + t2 + t3 + t4) / 4) * ksm((long long)x + y - z, (t1 + t2 - t3 - t4) / 4) % mod * ksm((long long)x - y + z, (t1 - t2 + t3 - t4) / 4) % mod * ksm((long long)x - y - z, (t1 - t2 - t3 + t4) / 4) % mod; f[i] = (f[i] + mod) % mod; } FWT(f, k); long long in = ksm(1 << k, mod - 2); for (int i = 0; i < (1 << k); i++) f[i] = f[i] * in % mod; for (int i = 0; i < (1 << k); i++) { wri(f[i ^ sum]); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:31:33 05/12/2015
// Design Name:
// Module Name: sbox3
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sbox3(
Bin,
BSout
);
input [6:1] Bin;
output reg [4:1] BSout;
wire [6:1] offset;
assign offset = {Bin[6], Bin[1], Bin[5 : 2]};
always @(offset)
begin
case (offset)
6'b000000: BSout <= 4'd10;
6'b000001: BSout <= 4'd0;
6'b000010: BSout <= 4'd9;
6'b000011: BSout <= 4'd14;
6'b000100: BSout <= 4'd6;
6'b000101: BSout <= 4'd3;
6'b000110: BSout <= 4'd15;
6'b000111: BSout <= 4'd5;
6'b001000: BSout <= 4'd1;
6'b001001: BSout <= 4'd13;
6'b001010: BSout <= 4'd12;
6'b001011: BSout <= 4'd7;
6'b001100: BSout <= 4'd11;
6'b001101: BSout <= 4'd4;
6'b001110: BSout <= 4'd2;
6'b001111: BSout <= 4'd8;
6'b010000: BSout <= 4'd13;
6'b010001: BSout <= 4'd7;
6'b010010: BSout <= 4'd0;
6'b010011: BSout <= 4'd9;
6'b010100: BSout <= 4'd3;
6'b010101: BSout <= 4'd4;
6'b010110: BSout <= 4'd6;
6'b010111: BSout <= 4'd10;
6'b011000: BSout <= 4'd2;
6'b011001: BSout <= 4'd8;
6'b011010: BSout <= 4'd5;
6'b011011: BSout <= 4'd14;
6'b011100: BSout <= 4'd12;
6'b011101: BSout <= 4'd11;
6'b011110: BSout <= 4'd15;
6'b011111: BSout <= 4'd1;
6'b100000: BSout <= 4'd13;
6'b100001: BSout <= 4'd6;
6'b100010: BSout <= 4'd4;
6'b100011: BSout <= 4'd9;
6'b100100: BSout <= 4'd8;
6'b100101: BSout <= 4'd15;
6'b100110: BSout <= 4'd3;
6'b100111: BSout <= 4'd0;
6'b101000: BSout <= 4'd11;
6'b101001: BSout <= 4'd1;
6'b101010: BSout <= 4'd2;
6'b101011: BSout <= 4'd12;
6'b101100: BSout <= 4'd5;
6'b101101: BSout <= 4'd10;
6'b101110: BSout <= 4'd14;
6'b101111: BSout <= 4'd7;
6'b110000: BSout <= 4'd1;
6'b110001: BSout <= 4'd10;
6'b110010: BSout <= 4'd13;
6'b110011: BSout <= 4'd0;
6'b110100: BSout <= 4'd6;
6'b110101: BSout <= 4'd9;
6'b110110: BSout <= 4'd8;
6'b110111: BSout <= 4'd7;
6'b111000: BSout <= 4'd4;
6'b111001: BSout <= 4'd15;
6'b111010: BSout <= 4'd14;
6'b111011: BSout <= 4'd3;
6'b111100: BSout <= 4'd11;
6'b111101: BSout <= 4'd5;
6'b111110: BSout <= 4'd2;
6'b111111: BSout <= 4'd12;
default: BSout <= 4'd0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long INF = 9999999999; double EPSILON = 0.00000001; int sint(string s) { int num = 0; istringstream myStream(s); (myStream >> num); return num; } string str(int num) { ostringstream oss; oss << num; return oss.str(); } vector<string> split(string s) { vector<string> tokens; stringstream os(s); string temp; while (os >> temp) { tokens.push_back(temp); } return tokens; } int maxv(vector<int> v) { int m = -9999999; for (int i = 0; i < v.size(); i++) m = max(m, v[i]); return m; } int minv(vector<int> v) { int m = 9999999; for (int i = 0; i < v.size(); i++) m = min(m, v[i]); return m; } int main() { long long n; cin >> n; long long s = 0; while (n != 1) { s += n; long long root = sqrt(n); bool found = false; for (long long r = 2; r <= root; r++) { if (n % r == 0) { n /= r; found = true; break; } } if (not found) n = 1; } cout << s + 1 << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int k = 1; k <= n / 3; k++) { if (n % k == 0) { for (int p = 0; p < k; p++) { int sum = 0; for (int v = p; v < n; v += k) { if (a[v] == 1) sum++; } if (sum == n / k) { cout << YES n ; return 0; } } } } cout << NO n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const double eps = 1e-9; double mi[N], ma[N]; double pre1[N], pre2[N]; double ans1[N], ans2[N]; int main() { int n; scanf( %d , &n); for (int i = (1); i <= (n); i++) cin >> ma[i]; for (int i = (1); i <= (n); i++) cin >> mi[i]; for (int i = (1); i <= (n); i++) pre1[i] = pre1[i - 1] + ma[i]; for (int i = n; i >= 1; i--) pre2[i] = pre2[i + 1] + mi[i]; for (int i = (1); i <= (n); i++) { double t1 = pre2[i + 1] - pre1[i] - 1.0; double t3 = t1 * t1 - 4.0 * pre1[i]; if (t3 < eps) t3 = 0.0; t3 = sqrt(t3); ans1[i] = 0.5 * (-t1 + t3); ans2[i] = 0.5 * (-t1 - t3); } for (int i = (1); i <= (n); i++) printf( %.9lf , ans1[i] - ans1[i - 1]); puts( ); for (int i = (1); i <= (n); i++) printf( %.9lf , ans2[i] - ans2[i - 1]); return 0; }
|
module nh_lcd #(
parameter DATAS_WIDTH = 24,
parameter BUFFER_SIZE = 12
)(
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_enable,
input i_reset_display,
input i_cmd_mode,
input i_enable_tearing,
input i_cmd_parameter,
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output [7:0] o_cmd_data,
output o_cmd_finished,
input i_write_override,
input i_chip_select,
input [31:0] i_image_width,
input [31:0] i_image_height,
//FIFO Signals
input i_fifo_clk,
input i_fifo_rst,
output [1:0] o_fifo_rdy,
input [1:0] i_fifo_act,
input i_fifo_stb,
output [23:0] o_fifo_size,
input [DATAS_WIDTH:0] i_fifo_data,
//Physical Signals
output o_read_en,
output o_register_data_sel,
output o_write_n,
output o_read_n,
input [7:0] i_data,
output [7:0] o_data,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
input i_tp_red,
input i_tp_green,
input i_tp_blue
);
//Local Parameters
//Registers/Wires
wire [7:0] w_data_out;
wire w_cmd_write;
wire w_cmd_read;
wire [7:0] w_cmd_data;
wire w_cmd_cmd_mode;
wire w_cmd_data_out_en;
wire w_data_cmd_mode;
wire [7:0] w_data_data;
wire w_data_write;
wire w_data_read;
wire w_data_data_out_en;
//Submodules
nh_lcd_command lcd_commander (
.rst (rst ),
.clk (clk ),
// .debug (debug ),
.i_enable (i_enable ),
.i_cmd_parameter (i_cmd_parameter ),
.i_cmd_write_stb (i_cmd_write_stb ),
.i_cmd_read_stb (i_cmd_read_stb ),
.i_cmd_data (i_cmd_data ),
.o_cmd_data (o_cmd_data ),
//Control Signals
.o_data_out_en (w_cmd_data_out_en ),
.o_cmd_finished (o_cmd_finished ),
.o_cmd_mode (w_cmd_cmd_mode ),
.o_write (w_cmd_write ),
.o_read (w_cmd_read ),
.o_data_out (w_cmd_data ),
.i_data_in (i_data )
);
nh_lcd_data_writer #(
.DATAS_WIDTH (DATAS_WIDTH ),
.BUFFER_SIZE (BUFFER_SIZE )
)lcd_data_writer(
.rst (rst ),
.clk (clk ),
.debug (debug ),
.i_enable (i_enable ),
.i_enable_tearing (i_enable_tearing ),
.i_image_width (i_image_width ),
.i_image_height (i_image_height ),
.i_fifo_clk (i_fifo_clk ),
.i_fifo_rst (i_fifo_rst ),
.o_fifo_rdy (o_fifo_rdy ),
.i_fifo_act (i_fifo_act ),
.i_fifo_stb (i_fifo_stb ),
.o_fifo_size (o_fifo_size ),
.i_fifo_data (i_fifo_data ),
.o_cmd_mode (w_data_cmd_mode ),
.o_data_out (w_data_data ),
.i_data_in (i_data ),
.o_write (w_data_write ),
.o_read (w_data_read ),
.o_data_out_en (w_data_data_out_en ),
.i_tearing_effect (i_tearing_effect ),
//Test Generator
.i_tp_red (i_tp_red ),
.i_tp_blue (i_tp_blue ),
.i_tp_green (i_tp_green )
);
//Asynchronous Logic
assign o_reset_n = ~i_reset_display;
assign o_cs_n = ~i_chip_select;
//Select control between the Command controller and the Data Controller
assign o_register_data_sel = (i_cmd_mode) ? w_cmd_cmd_mode : w_data_cmd_mode;
assign o_write_n = (i_cmd_mode) ? ~w_cmd_write : ~w_data_write;
assign o_read_n = (i_cmd_mode) ? ~w_cmd_read : ~w_data_read;
assign o_read_en = (i_cmd_mode) ? w_cmd_data_out_en : w_data_data_out_en;
assign o_data = (i_cmd_mode) ? w_cmd_data : w_data_data;
//Synchronous Logic
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_SN_TB_V
/**
* udp_dlatch$PR_pp$PKG$sN: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_SN_TB_V
|
module conware #(
parameter DWIDTH = 32,
parameter WIDTH = 8,
parameter HEIGHT = 1
)(
// Color conversion signals
// alive_color,
// dead_color,
// Clock and Reset
ACLK,
ARESETN,
// Input AXI stream ports
S_AXIS_TVALID,
S_AXIS_TREADY,
S_AXIS_TDATA,
S_AXIS_TLAST,
// Output AXI stream ports
M_AXIS_TVALID,
M_AXIS_TREADY,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TKEEP,
M_AXIS_TSTRB,
in_states,
out_states,
num_reads,
num_writes,
read_ctr,
write_ctr
);
input ACLK;
input ARESETN;
// input [DWIDTH-1:0] alive_color;
// input [DWIDTH-1:0] dead_color;
input [DWIDTH-1:0] S_AXIS_TDATA;
input S_AXIS_TVALID;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output [DWIDTH-1:0] M_AXIS_TDATA;
output M_AXIS_TVALID;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
output [3:0] M_AXIS_TKEEP; // TODO: This needs to change with DWIDTH
output [3:0] M_AXIS_TSTRB;
output wire [WIDTH-1:0] in_states;
output wire [WIDTH-1:0] out_states;
output wire [31:0] num_reads;
output wire [31:0] num_writes;
output wire [7:0] read_ctr;
output wire [7:0] write_ctr;
// Signals to handle internal handshake between in-buffer and out-buffer
wire pvalid;
wire pready;
wire shredder_en;
// We want to pull the data into the shredders when both the in buffer and
// out buffer are ready to move data one step through the pipeline
assign shredder_en = pvalid & pready;
axis2buffer #(DWIDTH, WIDTH) a2b(
.clk(ACLK),
.rstn(ARESETN),
.alive_color('hFFFFFFFF),
.dead_color('h00000000),
.S_AXIS_TVALID(S_AXIS_TVALID),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TLAST(S_AXIS_TLAST),
.out_data(in_states),
.out_valid(pvalid),
.out_ready(pready),
.num_reads(num_reads),
.counter(read_ctr)
);
shredder_array #(WIDTH) shredders(
.clk(ACLK),
.rstn(ARESETN),
.enable(shredder_en),
.in_data(in_states),
.out_data(out_states)
);
buffer2axis #(DWIDTH, WIDTH) b2a(
.clk(ACLK),
.rstn(ARESETN),
.alive_color('hFFFFFFFF),
.dead_color('h00000000),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TLAST(M_AXIS_TLAST),
.M_AXIS_TKEEP(M_AXIS_TKEEP),
.M_AXIS_TSTRB(M_AXIS_TSTRB),
.in_data(out_states),
.in_valid(pvalid),
.in_ready(pready),
.num_writes(num_writes),
.counter(write_ctr)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; const long long int MOD = 1000000007; const long long int MAXN = 1000005; const long long int INF = 100000000000005; void solve() { long long int n; cin >> n; vector<long long int> a(n), pos, neg; for (long long int i = 0; i < n; ++i) cin >> a[i]; long long int ans = 1; if (n == 5) { for (long long int i = 0; i < n; ++i) { ans = ans * a[i]; } cout << ans << endl; return; } for (auto itr : a) { if (itr < 0) { neg.push_back(itr); } else { pos.push_back(itr); } } if (pos.size() == 0 and neg.size() == 0) { ans = 0; } else if (pos.size() == 0) { sort(neg.begin(), neg.end()); reverse(neg.begin(), neg.end()); if (neg.size() < 5) { ans = 0; } else { for (long long int i = 0; i < 5; ++i) { ans = ans * neg[i]; } } } else if (neg.size() == 0) { sort(pos.begin(), pos.end()); reverse(pos.begin(), pos.end()); if (pos.size() < 5) { ans = 0; } else { for (long long int i = 0; i < 5; ++i) { ans = ans * pos[i]; } } } else { sort(pos.begin(), pos.end()); sort(neg.begin(), neg.end()); long long int si_pos = pos.size(), si_neg = neg.size(), res = -INF; if (si_neg + si_pos < 5) { ans = 0; } else { if (si_pos >= 5) { res = max(res, pos[si_pos - 1] * pos[si_pos - 2] * pos[si_pos - 3] * pos[si_pos - 4] * pos[si_pos - 5]); } if (si_pos >= 3 and si_neg >= 2) { res = max(res, pos[si_pos - 1] * pos[si_pos - 2] * pos[si_pos - 3] * neg[0] * neg[1]); } if (si_pos >= 1 and si_neg >= 4) { res = max(res, pos[si_pos - 1] * neg[2] * neg[3] * neg[0] * neg[1]); } ans = res; } } cout << ans << endl; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) solve(); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_maccontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_maccontrol.v,v $
// Revision 1.7 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.6 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.5 2002/11/21 00:14:39 mohor
// TxDone and TxAbort changed so they're not propagated to the wishbone
// module when control frame is transmitted.
//
// Revision 1.4 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
`include "timescale.v"
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= #Tp 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= #Tp 1'b0;
TxDoneInLatched <= #Tp 1'b0;
end
else
begin
TxAbortInLatched <= #Tp TxAbortIn;
TxDoneInLatched <= #Tp TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= #Tp 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= #Tp 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= #Tp 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= #Tp 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char buf[256]; signed main() { long long n; scanf( %lld , &n); stack<long long> cur; set<long long> si; long long tmp = 1, ans = 0; for (long long i = 0; i < n * 2; i++) { scanf( %s , buf); string s(buf); if (s == add ) { long long x; scanf( %lld , &x); cur.push(x); } if (s == remove ) { if (cur.empty() || cur.top() == tmp) { if (!cur.empty()) cur.pop(); tmp++; } else { while (!cur.empty()) { si.insert(cur.top()); cur.pop(); } si.erase(tmp); tmp++; ans++; } } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> int main() { int i, j, l, n, k, good; static int a[6][1001], dp0[1001], dp1[1001], pp[6][1001]; scanf( %d%d , &n, &k); for (i = 1; i <= k; i++) for (j = 1; j <= n; j++) { scanf( %d , &a[i][j]); if (i == 1) pp[1][a[i][j]] = j; else { a[i][j] = pp[1][a[i][j]]; pp[i][a[i][j]] = j; } } dp0[1] = 0; dp1[1] = 1; for (i = 2; i <= n; i++) { dp0[i] = dp0[i - 1] > dp1[i - 1] ? dp0[i - 1] : dp1[i - 1]; dp1[i] = 1; for (j = 0; j < i; j++) { good = 1; for (l = 2; l <= k; l++) if (pp[l][j] > pp[l][i]) { good = 0; break; } if (good && dp1[i] < dp1[j] + 1) dp1[i] = dp1[j] + 1; } } printf( %d n , dp0[n] > dp1[n] ? dp0[n] : dp1[n]); return 0; }
|
`timescale 1 ns / 1 ps
module axi_cfg_register #
(
parameter integer CFG_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
// Configuration bits
output wire [CFG_DATA_WIDTH-1:0] cfg_data,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready // AXI4-Lite slave: Read data ready
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
localparam integer CFG_SIZE = CFG_DATA_WIDTH/AXI_DATA_WIDTH;
localparam integer CFG_WIDTH = CFG_SIZE > 1 ? clogb2(CFG_SIZE-1) : 1;
reg [AXI_ADDR_WIDTH-1:0] int_awaddr_reg, int_awaddr_next;
reg int_awready_reg, int_awready_next;
reg [AXI_DATA_WIDTH-1:0] int_wdata_reg, int_wdata_next;
reg [AXI_DATA_WIDTH/8-1:0] int_wstrb_reg, int_wstrb_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
reg [AXI_ADDR_WIDTH-1:0] int_araddr_reg, int_araddr_next;
reg int_arready_reg, int_arready_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
reg int_rvalid_reg, int_rvalid_next;
wire int_awdone_wire, int_wdone_wire, int_bdone_wire;
wire [AXI_ADDR_WIDTH-1:0] int_awaddr_wire;
wire [AXI_DATA_WIDTH-1:0] int_wdata_wire;
wire [AXI_DATA_WIDTH/8-1:0] int_wstrb_wire;
wire int_ardone_wire, int_rdone_wire;
wire [AXI_ADDR_WIDTH-1:0] int_araddr_wire;
wire [AXI_DATA_WIDTH-1:0] int_data_mux [CFG_SIZE-1:0];
wire [CFG_DATA_WIDTH-1:0] int_data_wire;
wire [CFG_SIZE-1:0] int_ce_wire;
genvar j, k;
generate
for(j = 0; j < CFG_SIZE; j = j + 1)
begin : WORDS
assign int_data_mux[j] = int_data_wire[j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1:j*AXI_DATA_WIDTH];
assign int_ce_wire[j] = int_awdone_wire & int_wdone_wire & int_bdone_wire & (int_awaddr_wire[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB] == j);
for(k = 0; k < AXI_DATA_WIDTH; k = k + 1)
begin : BITS
FDRE #(
.INIT(1'b0)
) FDRE_inst (
.CE(int_ce_wire[j] & int_wstrb_wire[k/8]),
.C(aclk),
.R(~aresetn),
.D(int_wdata_wire[k]),
.Q(int_data_wire[j*AXI_DATA_WIDTH + k])
);
end
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awaddr_reg <= {(AXI_ADDR_WIDTH){1'b0}};
int_awready_reg <= 1'b1;
int_wdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
int_wstrb_reg <= {(AXI_DATA_WIDTH/8){1'b0}};
int_wready_reg <= 1'b1;
int_bvalid_reg <= 1'b0;
end
else
begin
int_awaddr_reg <= int_awaddr_next;
int_awready_reg <= int_awready_next;
int_wdata_reg <= int_wdata_next;
int_wstrb_reg <= int_wstrb_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
end
end
assign int_awdone_wire = ~int_awready_reg | s_axi_awvalid;
assign int_wdone_wire = ~int_wready_reg | s_axi_wvalid;
assign int_bdone_wire = ~int_bvalid_reg | s_axi_bready;
assign int_awaddr_wire = int_awready_reg ? s_axi_awaddr : int_awaddr_reg;
assign int_wdata_wire = int_wready_reg ? s_axi_wdata : int_wdata_reg;
assign int_wstrb_wire = int_wready_reg ? s_axi_wstrb : int_wstrb_reg;
always @*
begin
int_awaddr_next = int_awaddr_reg;
int_awready_next = ~int_awdone_wire | (int_wdone_wire & int_bdone_wire);
int_wdata_next = int_wdata_reg;
int_wstrb_next = int_wstrb_reg;
int_wready_next = ~int_wdone_wire | (int_awdone_wire & int_bdone_wire);
int_bvalid_next = ~int_bdone_wire | (int_awdone_wire & int_wdone_wire);
if(int_awready_reg)
begin
int_awaddr_next = s_axi_awaddr;
end
if(int_wready_reg)
begin
int_wdata_next = s_axi_wdata;
int_wstrb_next = s_axi_wstrb;
end
end
always @(posedge aclk)
begin
if(~aresetn)
begin
int_araddr_reg <= {(AXI_ADDR_WIDTH){1'b0}};
int_arready_reg <= 1'b1;
int_rdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
int_rvalid_reg <= 1'b0;
end
else
begin
int_araddr_reg <= int_araddr_next;
int_arready_reg <= int_arready_next;
int_rdata_reg <= int_rdata_next;
int_rvalid_reg <= int_rvalid_next;
end
end
assign int_ardone_wire = ~int_arready_reg | s_axi_arvalid;
assign int_rdone_wire = ~int_rvalid_reg | s_axi_rready;
assign int_araddr_wire = int_arready_reg ? s_axi_araddr : int_araddr_reg;
always @*
begin
int_araddr_next = int_araddr_reg;
int_arready_next = ~int_ardone_wire | int_rdone_wire;
int_rdata_next = int_rdata_reg;
int_rvalid_next = ~int_rdone_wire | int_ardone_wire;
if(int_arready_reg)
begin
int_araddr_next = s_axi_araddr;
end
if(int_ardone_wire & int_rdone_wire)
begin
int_rdata_next = int_data_mux[int_araddr_wire[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB]];
end
end
assign cfg_data = int_data_wire;
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bresp = 2'd0;
assign s_axi_bvalid = int_bvalid_reg;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rresp = 2'd0;
assign s_axi_rvalid = int_rvalid_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e3 + 100; struct node { int a, b, c; } p[N]; int nex[N]; vector<int> pre[N]; int dp[N][N]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); int sum = k; for (int i = 1; i <= n; ++i) scanf( %d %d %d , &p[i].a, &p[i].b, &p[i].c), sum += p[i].b; for (int i = 1; i <= n; ++i) nex[i] = i; for (int i = 1; i <= m; ++i) { int u, v; scanf( %d %d , &u, &v); nex[v] = max(nex[v], u); } for (int i = 1; i <= n; ++i) { pre[nex[i]].push_back(p[i].c); } memset(dp, -0x3f3f3f3f, sizeof(dp)); dp[1][k] = 0; for (int i = 1; i <= n; ++i) { for (int j = p[i].a; j <= 5000; ++j) { int nj = j + p[i].b; if (dp[i][j] >= 0) dp[i + 1][nj] = max(dp[i + 1][nj], dp[i][j]); } for (int k = 0; k < pre[i].size(); ++k) { int x = pre[i][k]; for (int j = 0; j <= 5000; ++j) { dp[i + 1][j] = max(dp[i + 1][j], dp[i + 1][j + 1] + x); } } } int ans = -1; for (int i = 0; i <= sum; ++i) ans = max(ans, dp[n + 1][i]); printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAX_N = 3e5 + 7; const long long MOD = 998244353; long long n; long long deg[MAX_N], fac[MAX_N]; long long f_pow(long long base, long long b, long long mod) { long long res = 1; while (b) { if (b & 1) res = res * base % mod; base = base * base % mod; b >>= 1; } return res; } namespace NTT { const long long MAX_N = 3e6 + 7; const long long MOD = 998244353; const long long G = 3; long long rev[MAX_N]; long long f[MAX_N], g[MAX_N]; long long n, m; vector<vector<long long>> p; struct Poly { long long n; vector<long long> p; Poly(vector<long long> _p = {}, long long _n = 0) : n(_n) { n = _p.size(); p.resize(n); for (long long i = 0; i < n; ++i) p[i] = _p[i]; } bool operator<(const Poly &a) const { return n > a.n; } }; void ntt(long long *a, long long n, long long dft) { for (long long i = 0; i < n; i++) { if (i < rev[i]) swap(a[i], a[rev[i]]); } for (long long i = 1; i < n; i <<= 1) { long long wn = f_pow(G, (MOD - 1) / (i << 1), MOD); if (dft < 0) wn = f_pow(wn, MOD - 2, MOD); for (long long j = 0; j < n; j += (i << 1)) { long long wnk = 1; for (long long k = j; k < j + i; k++) { long long a1 = a[k], a2 = a[k + i]; a[k] = (a1 + wnk * a2 % MOD) % MOD; a[k + i] = (a1 - wnk * a2 % MOD) % MOD; wnk = wnk * wn % MOD; } } } if (dft == -1) { long long inv = f_pow(n, MOD - 2, MOD); for (long long i = 0; i < n; i++) a[i] = a[i] * inv % MOD; } } vector<long long> merge(const vector<long long> &F, const vector<long long> &G) { n = F.size() - 1, m = G.size() - 1; long long N = 1, p = 0; while (N < (m + n + 1)) N <<= 1, ++p; for (long long i = 0; i < N; ++i) rev[i] = f[i] = g[i] = 0; for (long long i = 0; i < N; ++i) rev[i] = ((rev[i >> 1] >> 1) | ((i & 1) << (p - 1))); for (long long i = 0; i <= n; ++i) f[i] = F[i]; for (long long i = 0; i <= m; ++i) g[i] = G[i]; ntt(f, N, 1), ntt(g, N, 1); for (long long i = 0; i < N; ++i) f[i] = f[i] * g[i] % MOD; ntt(f, N, -1); vector<long long> res(m + n + 1); for (long long i = 0; i <= n + m; ++i) res[i] = (f[i] + MOD) % MOD; return res; } vector<long long> div_ntt(long long l, long long r) { if (l == r) return p[l]; long long mid = (l + r) >> 1; vector<long long> F = div_ntt(l, mid), G = div_ntt(mid + 1, r); return merge(F, G); } void merge(long long idx_f, long long idx_g) { vector<long long> &F = p[idx_f]; vector<long long> &G = p[idx_g]; n = F.size() - 1, m = G.size() - 1; long long N = 1, p = 0; while (N < (m + n + 1)) N <<= 1, p++; for (long long i = 0; i < N; ++i) rev[i] = f[i] = g[i] = 0; for (long long i = 0; i < N; i++) rev[i] = ((rev[i >> 1] >> 1) | ((i & 1) << (p - 1))); for (long long i = 0; i <= n; i++) f[i] = F[i]; for (long long i = 0; i <= m; i++) g[i] = G[i]; ntt(f, N, 1); ntt(g, N, 1); for (long long i = 0; i < N; i++) { f[i] = f[i] * g[i] % MOD; } ntt(f, N, -1); F.resize(m + n + 1); for (long long i = 0; i <= (n + m); ++i) F[i] = (f[i] + MOD) % MOD; } vector<long long> solve() { priority_queue<Poly> q; for (long long i = 0; i < p.size(); ++i) q.push(Poly(p[i])); while (q.size() > 1) { vector<long long> F = q.top().p; q.pop(); vector<long long> G = q.top().p; q.pop(); q.push(Poly(merge(F, G))); } return q.top().p; } vector<long long> solve(long long l, long long r) { return div_ntt(l, r); } } // namespace NTT signed main() { scanf( %lld , &n); for (long long i = 1; i < n; ++i) { long long x, y; scanf( %lld%lld , &x, &y); ++deg[x], ++deg[y]; } for (long long i = 2; i <= n; ++i) --deg[i]; for (long long i = 1; i <= n; ++i) { vector<long long> t; t.push_back(1ll); if (deg[i]) t.push_back(deg[i]); NTT::p.push_back(t); } vector<long long> F = NTT::solve(); long long ans = 0, flag = 1; fac[0] = 1; for (long long i = 1; i <= n; ++i) fac[i] = fac[i - 1] * i % MOD; for (long long i = 0; i < n && i < F.size(); ++i) { ans = (ans + flag * F[i] * fac[n - i] % MOD) % MOD; flag = -flag; } printf( %lld n , (ans + MOD) % MOD); return 0; }
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#include <bits/stdc++.h> using namespace std; const int oo = 1e9; const int maxc = 77; struct thang { int X, B; }; thang A[1010]; double f[1010]; int trace[1010], st[1010]; int N, L; void nhap() { scanf( %d%d , &N, &L); for (int i = 1; i <= N; i++) scanf( %d%d , &A[i].X, &A[i].B); A[0].X = 0; } void solve(double mid) { for (int i = 1; i <= N; i++) f[i] = oo; f[0] = 0; for (int i = 1; i <= N; i++) { int vt = 0; double t = oo; for (int j = i - 1; j >= 0; j--) if (f[j] + sqrt(abs((A[i].X - A[j].X) - L * 1.0)) - mid * 1.0 * A[i].B < t) { vt = j; t = f[j] + sqrt(abs((A[i].X - A[j].X) - L * 1.0)) - mid * 1.0 * A[i].B; } f[i] = t; trace[i] = vt; } } void chat() { double l = 0, r = oo; for (int i = 1; i <= maxc; i++) { double mid = (l + r) / 2; solve(mid); if (f[N] <= 0) r = mid; else l = mid; } int top = 0, i = N; while (i != 0) { st[++top] = i; i = trace[i]; } while (top > 0) printf( %d , st[top--]); } int main() { nhap(); chat(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[100][100]; struct point { public: int f, t; point() {} point(int a, int b) { f = a, t = b; } }; int main() { int X, k; cin >> X >> k; int val, sum = 0; vector<pair<int, int>> a, b; for (int i = 0; i < (X); i++) { cin >> val; sum += val; a.push_back(make_pair(val, i + 1)); } sort((a).begin(), (a).end()); int cnt = 0; while (k--) { int di = a[X - 1].first - a[0].first; if (di > 1) { a[X - 1].first--; a[0].first++; b.push_back(make_pair(a[X - 1].second, a[0].second)); sort((a).begin(), (a).end()); cnt++; } else break; } cout << a[X - 1].first - a[0].first << << cnt << endl; for (int j = 0; j < (cnt); j++) cout << b[j].first << << b[j].second << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_4_V
`define SKY130_FD_SC_LP__FILL_4_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_TB_V
`define SKY130_FD_SC_LP__NAND4BB_TB_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_lp__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EDFXBP_BEHAVIORAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_BEHAVIORAL_PP_V
|
// ghrd_10as066n2_dipsw_pio.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_dipsw_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.export
output wire irq, // irq.irq
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq dipsw_pio (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.address (address), // input, width = 2, s1.address
.write_n (write_n), // input, width = 1, .write_n
.writedata (writedata), // input, width = 32, .writedata
.chipselect (chipselect), // input, width = 1, .chipselect
.readdata (readdata), // output, width = 32, .readdata
.in_port (in_port), // input, width = 4, external_connection.export
.irq (irq) // output, width = 1, irq.irq
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int *tree; void buildTree(int node, int arr[], int start, int end) { if (start == end) { tree[node] = arr[start]; return; } int mid = (start + end) / 2; buildTree(2 * node + 1, arr, start, mid); buildTree(2 * node + 2, arr, mid + 1, end); tree[node] = min(tree[2 * node + 1], tree[2 * node + 2]); } int query(int node, int start, int end, int L, int R) { if (L <= start && R >= end) return tree[node]; else if (L > end || R < start) return INT32_MAX; else { int mid = (start + end) / 2; int c1 = query(2 * node + 1, start, mid, L, R); int c2 = query(2 * node + 2, mid + 1, end, L, R); return min(c1, c2); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n, x; cin >> n >> x; x--; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } tree = new int[4 * n]; buildTree(0, a, 0, n - 1); int i = n - 1; bool ans = false; while (i >= 0) { long long y = a[i]; if (x > i) { long long p = y * n + x - i; int h1 = query(0, 0, n - 1, i + 1, x); int h2 = -1; if (x + 1 < n) h2 = query(0, 0, n - 1, x + 1, n - 1); int h3 = query(0, 0, n - 1, 0, i - 1); bool cond = true; if (h1 < y + 1) cond = false; if (h2 != -1 && h2 < y) cond = false; if (h3 < y) cond = false; if (cond) { long long b[n]; b[i] = p; for (int j = i + 1; j < x + 1; j++) { b[j] = a[j] - (y + 1); } for (int j = x + 1; j < n; j++) { b[j] = a[j] - y; } for (int j = 0; j < i; j++) { b[j] = a[j] - y; } for (auto e : b) { cout << e << ; } cout << endl; break; } } else if (x < i) { long long p = y * n + n - i - 1 + x + 1; int h1 = query(0, 0, n - 1, i + 1, n - 1); int h3 = query(0, 0, n - 1, 0, x); int h2 = query(0, 0, n - 1, x + 1, i - 1); bool cond = true; if (h1 < y + 1) cond = false; if (h2 < y) cond = false; if (h3 < y + 1) cond = false; if (cond) { long long b[n]; b[i] = p; for (int j = i + 1; j < n; j++) { b[j] = a[j] - (y + 1); } for (int j = 0; j < x + 1; j++) { b[j] = a[j] - (y + 1); } for (int j = x + 1; j < i; j++) { b[j] = a[j] - y; } for (auto e : b) { cout << e << ; } cout << endl; break; } } else { long long p = y * n; int h1 = -1; if (i + 1 < n) { h1 = query(0, 0, n - 1, i + 1, n - 1); } int h3 = -1; if (x - 1 >= 0) { h3 = query(0, 0, n - 1, 0, x - 1); } bool cond = true; if (h1 != -1 && h1 < y) cond = false; if (h3 != -1 && h3 < y) cond = false; if (cond) { long long b[n]; b[i] = p; for (int j = i + 1; j < n; j++) { b[j] = a[j] - (y); } for (int j = 0; j < x; j++) { b[j] = a[j] - (y); } for (auto e : b) { cout << e << ; } cout << endl; break; } } i--; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFXBP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000006; int t, n, m, x, y; stack<int> s; int rg[N], rs[N], ls[N], lg[N], a[N]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } a[0] = a[n + 1] = 0; for (int i = 1; i <= n + 1; i++) { while (!s.empty() && a[s.top()] > a[i]) { t = s.top(); s.pop(); rs[t] = i - 1; } s.push(i); } s.pop(); for (int i = n; i >= 0; i--) { while (!s.empty() && a[s.top()] >= a[i]) { t = s.top(); s.pop(); ls[t] = i + 1; } s.push(i); } s.pop(); a[0] = a[n + 1] = INT_MAX; for (int i = 1; i <= n + 1; i++) { while (!s.empty() && a[s.top()] < a[i]) { t = s.top(); s.pop(); rg[t] = i - 1; } s.push(i); } s.pop(); for (int i = n; i >= 0; i--) { while (!s.empty() && a[s.top()] <= a[i]) { t = s.top(); s.pop(); lg[t] = i + 1; } s.push(i); } s.pop(); long long ans = 0; for (int i = 1; i <= n; i++) { ans += 1LL * ((rg[i] - lg[i]) + 1LL * (rg[i] - i) * (i - lg[i])) * a[i]; ans -= 1LL * ((rs[i] - ls[i]) + 1LL * (rs[i] - i) * (i - ls[i])) * a[i]; } cout << ans; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] rd0; // From test of Test.v
wire [31:0] rd1; // From test of Test.v
// End of automatics
wire rden0 = crc[0];
wire rden1 = crc[1];
wire [4:0] raddr0 = crc[20:16];
wire [4:0] raddr1 = crc[28:24];
Test test(/*AUTOINST*/
// Outputs
.rd0 (rd0[31:0]),
.rd1 (rd1[31:0]),
// Inputs
.clk (clk),
.raddr0 (raddr0[4:0]),
.raddr1 (raddr1[4:0]),
.rden0 (rden0),
.rden1 (rden1));
// Aggregate outputs into a single result vector
wire [63:0] result = {rd1, rd0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdc97b141ac5d6d7d
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
rd0, rd1,
// Inputs
clk, raddr0, raddr1, rden0, rden1
);
input clk;
input [4:0] raddr0;
input [4:0] raddr1;
input rden0;
input rden1;
output reg [31:0] rd0;
output reg [31:0] rd1;
reg [31:0] gpr [31:1];
initial begin
for (int j=1; j<32; j++ ) begin
gpr[j] = {8'(j), 8'(j), 8'(j), 8'(j)};
end
end
always_comb begin
rd0[31:0] = 32'b0;
rd1[31:0] = 32'b0;
// Future optimization:
// Multiple assignments to same variable with OR between them
// ASSIGN(a, OR(a, aq)), ASSIGN(a, OR(a, bq)) -> ASSIGN(a, OR(a, OR(aq, bq))
// Skip if we're not const'ing an entire module (IE doing only one assign, etc)
for (int j=1; j<32; j++ ) begin
rd0[31:0] |= ({32{rden0 & (raddr0[4:0]== 5'(j))}} & gpr[j][31:0]);
rd1[31:0] |= ({32{rden1 & (raddr1[4:0]== 5'(j))}} & gpr[j][31:0]);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFBBN_FUNCTIONAL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ms__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_FUNCTIONAL_V
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[3]),
.D (sw[14]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[2]),
.D (sw[13]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram1 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[1]),
.D (sw[12]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram2 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[0]),
.D (sw[11]),
.WE (sw[15])
);
assign led[15:4] = sw[15:4];
assign tx = rx;
endmodule
|
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