text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; int main() { int res; cin >> res; if (res % 2 == 0) { cout << Mahmoud ; } else { cout << Ehab ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_FUNCTIONAL_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__inputisolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, SLEEP_B );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> t, a, b; vector<pair<int, int>> p; void push(int v) { if (t[v] != -1) { t[v * 2] = t[v * 2 + 1] = t[v]; t[v] = -1; } } void update(int v, int l, int r, int vl, int vr, int color) { if (vl > vr) return; if (l == vl && r == vr) t[v] = color; else { push(v); int m = (l + r) / 2; update(v * 2, l, m, vl, min(vr, m), color); update(v * 2 + 1, m + 1, r, max(vl, m + 1), vr, color); } } int get(int v, int l, int r, int pos) { if (l == r) return t[v]; push(v); int m = (l + r) / 2; if (m >= pos) return get(v * 2, l, m, pos); else return get(v * 2 + 1, m + 1, r, pos); } int main() { cin >> n >> m; a.resize(n); b.resize(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; int bin = 1; while (bin < n) bin *= 2; n = bin; t.assign(n * 2, -1); for (int i = 0; i < m; ++i) { int type; cin >> type; if (type == 1) { int l, q, k; cin >> l >> q >> k; update(1, 0, n - 1, q - 1, q + k - 2, p.size()); p.push_back({l, q}); } else { int x, y = -1; cin >> x; y = get(1, 0, n - 1, x - 1); if (y == -1) cout << b[x - 1] << n ; else cout << a[p[y].first + x - p[y].second - 1] << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 10000010; int p[N], num, last[N]; bool flag[N]; int cnt[N], n, m; void make_prime() { for (int i = 2; i < N; ++i) if (!flag[i]) { p[num++] = i; last[i] = i; for (int j = i + i; j < N; j += i) flag[j] = true, last[j] = i; } } int main() { make_prime(); scanf( %d , &n); for (int i = 0, x; i < n; ++i) { scanf( %d , &x); int s = -1; while (x != 1) { if (last[x] != s) cnt[last[x]]++; s = last[x]; x /= last[x]; } } for (int i = 1; i < N; ++i) cnt[i] += cnt[i - 1]; scanf( %d , &m); for (int i = 0, x, y; i < m; ++i) { scanf( %d %d , &x, &y); if (x >= N) puts( 0 ); else { y = min(y, N - 1); printf( %d n , cnt[y] - cnt[x - 1]); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: clock_generator_pll_s8_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: PLL Based clock generator. Takes in a differential clock and multiplies it
// by the amount specified. Instantiates a BUFIO2, BUFPLL and a PLL using
// INTERNAL feedback
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module clock_generator_pll_s8_diff (clkin_p, clkin_n, ioclk, serdesstrobe, reset, gclk, bufpll_lckd) ;
parameter integer S = 8 ; // Parameter to set the serdes factor 1..8
parameter integer PLLX = 2 ; // Parameter to set the multiplication factor in the PLL
parameter integer PLLD = 1 ; // Parameter to set the division factor in the PLL
parameter real CLKIN_PERIOD = 6.000 ; // clock period (ns) of input clock on clkin_p
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input reset ; // reset (active high)
input clkin_p, clkin_n ; // differential clock inputs
output ioclk ; // ioclock from BUFPLL
output serdesstrobe ; // serdes strobe from BUFPLL
output gclk ; // global clock output from BUFG
output bufpll_lckd ; // Locked output from BUFPLL
wire clkint ; // clock input from pin
wire pllout_x1 ; // pll generated x1 clock
wire pllout_xn ; // pll generated xn clock
wire dummy ; // feedback net
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
clk_iob_in (
.I (clkin_p),
.IB (clkin_n),
.O (clkint));
BUFIO2 #(
.DIVIDE (1), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("TRUE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst (
.I (clkint), // Input source clock 0 degrees
.IOCLK (), // Output Clock for IO
.DIVCLK (clkintb), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
PLL_ADV #(
.BANDWIDTH ("OPTIMIZED"), // "high", "low" or "optimized"
.CLKFBOUT_MULT (PLLX), // multiplication factor for all output clocks
.CLKFBOUT_PHASE (0.0), // phase shift (degrees) of all output clocks
.CLKIN1_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin1
.CLKIN2_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin2
.CLKOUT0_DIVIDE (1), // division factor for clkout0 (1 to 128)
.CLKOUT0_DUTY_CYCLE (0.5), // duty cycle for clkout0 (0.01 to 0.99)
.CLKOUT0_PHASE (0.0), // phase shift (degrees) for clkout0 (0.0 to 360.0)
.CLKOUT1_DIVIDE (1), // division factor for clkout1 (1 to 128)
.CLKOUT1_DUTY_CYCLE (0.5), // duty cycle for clkout1 (0.01 to 0.99)
.CLKOUT1_PHASE (0.0), // phase shift (degrees) for clkout1 (0.0 to 360.0)
.CLKOUT2_DIVIDE (S), // division factor for clkout2 (1 to 128)
.CLKOUT2_DUTY_CYCLE (0.5), // duty cycle for clkout2 (0.01 to 0.99)
.CLKOUT2_PHASE (0.0), // phase shift (degrees) for clkout2 (0.0 to 360.0)
.CLKOUT3_DIVIDE (8), // division factor for clkout3 (1 to 128)
.CLKOUT3_DUTY_CYCLE (0.5), // duty cycle for clkout3 (0.01 to 0.99)
.CLKOUT3_PHASE (0.0), // phase shift (degrees) for clkout3 (0.0 to 360.0)
.CLKOUT4_DIVIDE (8), // division factor for clkout4 (1 to 128)
.CLKOUT4_DUTY_CYCLE (0.5), // duty cycle for clkout4 (0.01 to 0.99)
.CLKOUT4_PHASE (0.0), // phase shift (degrees) for clkout4 (0.0 to 360.0)
.CLKOUT5_DIVIDE (8), // division factor for clkout5 (1 to 128)
.CLKOUT5_DUTY_CYCLE (0.5), // duty cycle for clkout5 (0.01 to 0.99)
.CLKOUT5_PHASE (0.0), // phase shift (degrees) for clkout5 (0.0 to 360.0)
.COMPENSATION ("INTERNAL"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE (PLLD), // division factor for all clocks (1 to 52)
.REF_JITTER (0.100)) // input reference jitter (0.000 to 0.999 ui%)
tx_pll_adv_inst (
.CLKFBDCM (), // output feedback signal used when pll feeds a dcm
.CLKFBOUT (dummy), // general output feedback signal
.CLKOUT0 (pllout_xn), // x7 clock for transmitter
.CLKOUT1 (), //
.CLKOUT2 (pllout_x1), // x1 clock for BUFG
.CLKOUT3 (), // one of six general clock output signals
.CLKOUT4 (), // one of six general clock output signals
.CLKOUT5 (), // one of six general clock output signals
.CLKOUTDCM0 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM1 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM2 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM3 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM4 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM5 (), // one of six clock outputs to connect to the dcm
.DO (), // dynamic reconfig data output (16-bits)
.DRDY (), // dynamic reconfig ready output
.LOCKED (pll_lckd), // active high pll lock signal
.CLKFBIN (dummy), // clock feedback input
.CLKIN1 (clkintb), // primary clock input
.CLKIN2 (1'b0), // secondary clock input
.CLKINSEL (1'b1), // selects '1' = clkin1, '0' = clkin2
.DADDR (5'b00000), // dynamic reconfig address input (5-bits)
.DCLK (1'b0), // dynamic reconfig clock input
.DEN (1'b0), // dynamic reconfig enable input
.DI (16'h0000), // dynamic reconfig data input (16-bits)
.DWE (1'b0), // dynamic reconfig write enable input
.RST (reset), // asynchronous pll reset
.REL (1'b0)) ; // used to force the state of the PFD outputs (test only)
BUFG bufg_tx (.I(pllout_x1), .O(gclk) ) ;
BUFPLL #(
.DIVIDE (S)) // PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
tx_bufpll_inst (
.PLLIN (pllout_xn), // PLL Clock input
.GCLK (gclk), // Global Clock input
.LOCKED (pll_lckd), // Clock0 locked input
.IOCLK (ioclk), // Output PLL Clock
.LOCK (buf_pll_lckd), // BUFPLL Clock and strobe locked
.SERDESSTROBE (serdesstrobe)) ; // Output SERDES strobe
assign bufpll_lckd = buf_pll_lckd & pll_lckd ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& s, vector<T>& v) { s << { ; for (int i = 0; i < int(v.size()); i++) s << (i ? , : ) << v[i]; return s << } ; } template <typename S, typename T> ostream& operator<<(ostream& s, pair<S, T> const& p) { return s << ( << p.first << , << p.second << ) ; } const long long INV2 = 500000004; const long long INV3 = 333333336; const long long MOD = 1000000007; long long modexp(long long x, long long n) { long long result = 1; while (n) { if (n % 2) { result = (result * x) % MOD; n--; } x = (x * x) % MOD; n /= 2; } return result; } int main() { int K; bool even = false; scanf( %d , &K); long long sm = 2; for (int k = 0; k < int(K); k++) { long long a; scanf( %lld , &a); if (a % 2 == 0) even = true; sm = modexp(sm, a); } sm = (sm * INV2) % MOD; long long denom = (sm + MOD) % MOD; if (even) sm++; else sm--; sm = (sm * INV3) % MOD; sm = (sm + MOD) % MOD; printf( %lld/%lld n , sm, denom); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; int C[N][N], dp[N][N]; int main() { int m, x[110], y[110], sum[110]; sum[0] = 0; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d , x + i); sum[i] = sum[i - 1] + x[i]; } for (int i = 1; i <= m; i++) { scanf( %d , y + i); } C[0][0] = 1; for (int i = 1; i <= sum[m]; i++) { C[i][0] = C[i][i] = 1; for (int j = 1; j < i; j++) { C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % 1000000007; } } dp[0][0] = 1; for (int i = 1; i <= m; i++) { for (int j = 0; j <= sum[i]; j++) { for (int k = 0; k <= min(y[i], j); k++) { dp[i][j] = (dp[i][j] + (long long)dp[i - 1][j - k] * C[sum[i] - (j - k)][k]) % 1000000007; } } } long long ans = dp[m][sum[m]] % 1000000007; for (int i = 1; i <= m; i++) { ans = (long long)(ans * C[sum[m] - sum[i - 1]][x[i]]) % 1000000007; } printf( %d n , ans); return 0; }
|
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans % m; } int main() { string s; cin >> s; int n; cin >> n; int from[n]; char s1, s2; string to[n]; long long a[10], b[10]; for (int i = 0; i < n; i++) { cin >> from[i] >> to[i]; } for (int i = 0; i < n; i++) { to[i] = to[i].substr(2); } for (int i = 0; i < 10; i++) { a[i] = 10; b[i] = i; } for (int i = n - 1; i >= 0; i--) { long long p = 1, q = 0; for (int j = 0; j < to[i].length(); j++) { int c = to[i][j] - 0 ; long long p2 = (a[c] * p) % 1000000007; long long q2 = (a[c] * q + b[c]) % 1000000007; p = p2; q = q2; } a[from[i]] = p; b[from[i]] = q; } long long ans = 0; for (int i = 0; i < s.length(); i++) { int c = s[i] - 0 ; ans = (ans * a[c] + b[c]) % 1000000007; } cout << ans; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 1e2 + 5, M = 1e5 + 5; int lim = (1 << 10) - 1; bool vis[M]; vector<int> primes; int idx[M]; void pre() { for (int i = 2; primes.size() < 110; ++i) { if (vis[i]) continue; primes.emplace_back(i); for (int j = i; j < M; j += i) vis[j] = true; } for (int i = 0; i < 110; ++i) idx[primes[i]] = i; } vector<int> tmp; void fac(int x) { tmp.clear(); for (int i = 2; i * i <= x; ++i) { if (x % i) continue; tmp.emplace_back(idx[i]); while (x % i == 0) x /= i; } if (x > 1) tmp.emplace_back(idx[x]); } int n, a[N]; int dp[N][1 << 10][N + 10]; int solve(int i, int msk, int j) { if (i == n) return 0; if (msk == lim && j == 110) return (int)1e7; int &ret = dp[i][msk][j]; if (~ret) return ret; ret = (int)1e7; if (j < 110 && a[i] > primes[j]) cout << yala n2fl ya 3mna kda mb2tsh nf3a << endl; if (j < 110) ret = min(ret, solve(i + 1, msk, j + 1) - a[i] + primes[j]); for (int f = 0; f < 10; ++f) { if ((msk & (1 << f))) continue; int nw = primes[f]; for (int k = 0; k <= 15 && (int)1e7 / nw >= primes[f]; ++k, nw *= primes[f]) ret = min(ret, solve(i + 1, (msk | (1 << f)), j) + abs(a[i] - nw)); } for (int hna = 1; hna <= 30; ++hna) { bool baz = false; int nmsk = msk; fac(hna); for (auto f : tmp) { nmsk |= (1 << f); baz |= ((msk & (1 << f)) > 0); } if (baz) continue; ret = min(ret, solve(i + 1, nmsk, j) + abs(a[i] - hna)); } return ret; } vector<int> out; void build(int i, int msk, int j) { if (i == n) { for (auto x : out) printf( %d%c , x, n [&x == &out.back()]); exit(0); } if (msk == lim && j == 110) return; int m3lsh = solve(i, msk, j); if (j < 110 && m3lsh == solve(i + 1, msk, j + 1) - a[i] + primes[j]) { out.emplace_back(primes[j]); build(i + 1, msk, j + 1); return; } for (int f = 0; f < 10; ++f) { if ((msk & (1 << f))) continue; int nw = primes[f]; for (int k = 0; k <= 15 && (int)1e7 / nw >= primes[f]; ++k, nw *= primes[f]) { if (m3lsh == solve(i + 1, (msk | (1 << f)), j) + abs(a[i] - nw)) { out.emplace_back(nw); build(i + 1, (msk | (1 << f)), j); return; } } } for (int hna = 1; hna <= 30; ++hna) { bool baz = false; int nmsk = msk; fac(hna); for (auto f : tmp) { nmsk |= (1 << f); baz |= (msk & (1 << f)); } if (baz) continue; if (m3lsh == solve(i + 1, nmsk, j) + abs(a[i] - hna)) { out.emplace_back(hna); build(i + 1, nmsk, j); return; } } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; pre(); scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); memset(dp, -1, sizeof dp); solve(0, 0, 10); build(0, 0, 10); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__FAH_BEHAVIORAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_BEHAVIORAL_PP_V
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
/*
* Arbitrary width and addressing depth dual port ram
*/
module dualportram #(
// Default parameters. These can be overrriden
parameter WIDTH = 64,
parameter DEPTH = 6
) (
// Port A
input wire clk_a,
input wire we_a,
input wire [DEPTH-1:0] addr_a,
input wire [WIDTH-1:0] din_a,
output reg [WIDTH-1:0] dout_a,
// Port B
input wire clk_b,
input wire we_b,
input wire [DEPTH-1:0] addr_b,
input wire [WIDTH-1:0] din_b,
output reg [WIDTH-1:0] dout_b
);
// Shared memory array
reg [WIDTH-1:0] memarray [(2**DEPTH)-1:0];
// Port A
always @(posedge clk_a) begin
// Always load the output register
dout_a <= memarray[addr_a];
if(we_a) begin // Write enable?
dout_a <= din_a;
memarray[addr_a] <= din_a;
end
end
// Port B
always @(posedge clk_b) begin
// Always load the output register
dout_b <= memarray[addr_b];
if(we_b) begin // Write enable?
dout_b <= din_b;
memarray[addr_b] <= din_b;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 999999999; const long long INFL = 99999999999999999LL; const double EPSILON = 0.00000001; const long long MOD = 1000000007; long long a[100005]; int32_t main() { long long n, t; scanf( %I64d , &n); ; scanf( %I64d , &t); ; for (long long i = 0; i < n; i++) scanf( %I64d , &a[i]); ; long long ans = 0; long long l = 0, r = 0; long long cur = 0; long long s = 0; while (l < n) { while (r < n and s + a[r] <= t) { s += a[r]; r++; cur++; ans = ((ans) > (cur) ? (ans) : (cur)); } l++; if (l > r) r++; else { s -= a[l - 1]; cur--; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int Res[2][7010], N[2][7010], Loss[2][7010]; int n, m, k, OpN[2]; queue<pair<int, int> > Q; int main() { srand((unsigned)time(0)); ios::sync_with_stdio(false); cin.tie(0); cin >> n; cin.get(); for (int i = 0; i < 2; i++) { cin >> m; OpN[i] = m; for (int j = 0; j < m; j++) { cin >> k; N[i][j] = k; Res[i][n + 1 - k] = 1; Q.push({i, n + 1 - k}); } } pair<int, int>* P; while (!Q.empty()) { P = &Q.front(); int k = !P->first, i = P->second; Q.pop(); for (int j = 0; j < OpN[k]; j++) { int h = N[k][j], l = ((i - h < 1) ? (i - h + n) : (i - h)); if (Res[k][l] == 0) { Loss[k][l]++; } } for (int i = 2; i < n + 1; i++) { if (Res[k][i] == 0) { if (Loss[k][i] == OpN[k]) { Res[k][i] = 2; for (int t = 0; t < OpN[!k]; t++) { int h = N[!k][t], l = ((i - h < 1) ? (i - h + n) : (i - h)); if (Res[!k][l] == 0) { Res[!k][l] = 1; Q.push({!k, l}); } } } } } } string Out[3] = { Loop , Win , Lose }; for (int k = 0; k < 2; k++) { for (int i = 2; i < n + 1; i++) { cout << Out[Res[k][i]].c_str() << ; } cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int MX = 1e6 + 42; int k; int f[6]; long long dp[MX]; long long eval(int val) { long long ret = 0; for (int dig = 0; dig < 6; dig++) { int d = val % 10; if (d % 3 == 0) ret = ret + 1LL * d / 3 * f[dig]; val = val / 10; } return ret; } void push(long long object, long long gain) { if (object >= MX) return; for (int i = MX - 1; i >= object; i--) dp[i] = max(dp[i], dp[i - object] + gain); } void prec() { for (int i = 0; i < MX; i++) dp[i] = -1e18; dp[0] = 0; for (int dig = 0; dig < 6; dig++) { int mult = 1; for (int t = 0; t < dig; t++) mult = mult * 10; mult = mult * 3; long long remain = 3 * (k - 1), object = mult, gain = f[dig]; while (remain) { if (remain % 2 == 0) { push(object, gain); remain--; } if (remain % 2 == 1) { push(object, gain); remain--; } object = object * 2; gain = gain * 2; remain = remain / 2; } } } long long solve(int cur) { long long ret = 0; for (int i = 0; i <= cur; i++) ret = max(ret, dp[i] + eval(cur - i)); return ret; } int main() { scanf( %i , &k); for (int i = 0; i < 6; i++) scanf( %i , &f[i]); prec(); int q; scanf( %i , &q); for (int i = 1; i <= q; i++) { int val; scanf( %i , &val); printf( %lld n , solve(val)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long C[2333][2333]; int d, MOD, p = 0; long long co[23333]; vector<int> operator-(vector<int> a, vector<int> b) { vector<int> s; int u = max(a.size(), b.size()); a.resize(u); b.resize(u); for (int i = 0; i < u; ++i) s.push_back((a[i] - b[i]) % MOD); return s; } long long qp(long long a, long long b) { long long x = 1; a %= MOD; while (b) { if (b & 1) x = x * a % MOD; a = a * a % MOD; b >>= 1; } return x; } int add(int a, int b) { ++p; cout << + << a << << b << << p << endl; co[p] = (co[a] + co[b]) % MOD; return p; } int po(int a) { ++p; cout << ^ << a << << p << endl; co[p] = qp(co[a], d); return p; } int mul(int a, int k) { k = (k % MOD + MOD) % MOD; if (!k) k += MOD; int s = a; --k; while (k) { if (k & 1) s = add(s, a); a = add(a, a); k >>= 1; } return s; } int neg(int a) { return mul(a, MOD - 1); } int minus_(int a, int b) { return add(a, neg(b)); } void op(int a) { cout << f << a << endl; cerr << co[a] << endl; } int l = 3, z; long long show(vector<int>& v, long long t) { long long x = 1, s = 0; for (int i = 0; i < v.size(); ++i) s += x * v[i] % MOD, s %= MOD, x = x * t % MOD; return (s % MOD + MOD) % MOD; } int p2(int a) { if (d == 2) return po(a); int n = d + 1; static vector<int> u[233], ss[233]; static int w[233], ww[233]; ww[0] = a; for (int i = 1; i <= n; ++i) { u[i].clear(); ss[i].clear(); for (int w = 0; w <= d; ++w) u[i].push_back(C[d][w] * qp(i, d - w) % MOD); ww[i] = add(ww[i - 1], l); w[i] = po(ww[i]); ss[i].resize(n + 1); ss[i][i] = 1; } for (int s = 0; s <= d; ++s) { long long x = u[s + 1][s] % MOD; if (!x) { for (int q = s + 2; q <= n; ++q) if (u[q][s] % MOD) { x = u[q][s] % MOD; for (int i = 1; i <= n; ++i) swap(ss[i][s + 1], ss[i][q]); swap(u[s + 1], u[q]); break; } } if (!x) throw GG ; long long rv = qp(x, MOD - 2); for (auto& w : u[s + 1]) w = w % MOD * rv % MOD; for (auto& w : ss[s + 1]) w = w % MOD * rv % MOD; for (int q = 1; q <= n; ++q) if (q != s + 1 && u[q][s] % MOD) { long long v = u[q][s] % MOD; for (int e = 1; e <= n; ++e) ss[q][e] = (ss[q][e] - ss[s + 1][e] * v) % MOD; for (int e = 0; e <= d; ++e) u[q][e] = (u[q][e] - u[s + 1][e] * v) % MOD; } } int aa = z; for (int i = 1; i <= n; ++i) if (ss[3][i]) aa = add(aa, mul(w[i], ss[3][i])); return aa; } int main() { cin >> d >> MOD; p = 4; for (int i = 0; i < 23333; ++i) co[i] = 1; for (int i = 0; i < 2333; ++i) { C[i][0] = 1; for (int j = 1; j <= i; ++j) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } co[1] = 5; co[2] = 3; z = minus_(l, l); op(mul(minus_(minus_(p2(add(1, 2)), p2(1)), p2(2)), (MOD + 1) / 2)); }
|
#include <bits/stdc++.h> using namespace std; int main() { map<pair<long long, long long>, long long> m; vector<long long> p1, p2; long long n, s, i, j, k, a, u, v, w, l, k1, k2; cin >> n; while (n--) { cin >> a; if (a == 1) { cin >> u >> v >> w; j = u; k1 = 0, k2 = 0; p1.push_back(j); while (j != 1) { j = j / 2; p1.push_back(j); } j = v; p2.push_back(j); while (j != 1) { j = j / 2; p2.push_back(j); } for (i = 0; i < p1.size(); i++) { int t = 1; for (j = 0; j < p2.size(); j++) { if (p1[i] == p2[j]) { k1 = i; k2 = j; t = 0; break; } } if (t == 0) break; } for (i = 0; i < k1; i++) { m[make_pair(p1[i], p1[i + 1])] += w; } for (i = 0; i < k2; i++) { m[make_pair(p2[i], p2[i + 1])] += w; } p1.clear(); p2.clear(); } else { s = 0; cin >> u >> v; j = u; k1 = k2 = 0; p1.push_back(j); while (j != 1) { j = j / 2; p1.push_back(j); } j = v; p2.push_back(j); while (j != 1) { j = j / 2; p2.push_back(j); } for (i = 0; i < p1.size(); i++) { int t = 1; for (j = 0; j < p2.size(); j++) { if (p1[i] == p2[j]) { k1 = i; k2 = j; t = 0; break; } } if (t == 0) break; } for (i = 0; i < k1; i++) { s += m[make_pair(p1[i], p1[i + 1])]; } for (i = 0; i < k2; i++) { s += m[make_pair(p2[i], p2[i + 1])]; } p1.clear(); p2.clear(); cout << s << endl; } } }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: whoosh_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module whoosh_new (
address,
clock,
q);
input [12:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../audio_mifs/whoosh_new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../audio_mifs/whoosh_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../audio_mifs/whoosh_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL whoosh_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { long long x, d, k = 1; cin >> x >> d; vector<long long> ans; while (x) { long long rem = 0; for (int i = 31; i >= 0; --i) { if (x >> i & 1) { long long tmp = i; if (i == 0) { ans.push_back(k); rem--; } while (tmp--) ans.push_back(k); k += d; rem++; } } x = rem; } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) cout << ans[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int printx(int x, int a, int b, int c) { if (x == 0) return a; else if (x == 1) return b; else return c; } int main() { long long n; int x; cin >> n >> x; n %= 6; switch (n) { case 0: x = printx(x, 0, 1, 2); break; case 1: x = printx(x, 1, 0, 2); break; case 2: x = printx(x, 1, 2, 0); break; case 3: x = printx(x, 2, 1, 0); break; case 4: x = printx(x, 2, 0, 1); break; case 5: x = printx(x, 0, 2, 1); break; } cout << x << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ls__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int ts = 1, cs = 1; cin >> ts; while (ts--) { int n, m; cin >> n >> m; pair<int, int> vec[m + 2]; for (int i = 1; i <= m; i++) { cin >> vec[i].first; vec[i].second = i; } sort(vec + 1, vec + m + 1); long long ans = 0; for (int i = 1; i <= m; i++) { for (int j = 1; j <= m; j++) { if (vec[i].second > vec[j].second && vec[i].first > vec[j].first) ans++; } } cout << ans << endl; } }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES Key Expand Block (for 128 bit keys) ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_key_expand_128.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $
//
// $Date: 2002/11/09 11:22:38 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_key_expand_128.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:38 rudi
// Initial Checkin
//
//
//
//
//
//
`timescale 1ns / 10ps
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
input clk;
input kld;
input [127:0] key;
output [31:0] wo_0, wo_1, wo_2, wo_3;
reg [31:0] w[3:0];
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign wo_0 = w[0];
assign wo_1 = w[1];
assign wo_2 = w[2];
assign wo_3 = w[3];
always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
endmodule
|
module first_nns_comb_td
#
(
parameter W = 15,
parameter N = 32
)
(
g_input,
e_input,
o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value;
for (log2=0; temp>0; log2=log2+1)
temp = temp>>1;
end
endfunction
localparam LOGW = log2(W);
input [2*W-1:0] g_input;
input [2*W*N-1:0] e_input;
output [2*W-1:0] o;
wire [W-1:0] x1[N-1:0];
wire [W-1:0] y1[N-1:0];
wire [W-1:0] x2, y2;
wire [2*W-1:0] min_val_out;
assign x2 = g_input[2*W-1:W];
assign y2 = g_input[W-1:0];
assign min_val_out = o;
//wire [2*W-1:0] DBi[N-1:0];
wire [W+1:0] dist[N-1:0];
wire [W-1:0] min_val_x[N-1:0];
wire [W-1:0] min_val_y[N-1:0];
wire [W+1:0] min_dist[N-1:0];
wire gt_dist[N-1:1];
genvar i;
generate
for (i=0;i<N;i=i+1)
begin:D_ASN
//assign DBi[i] = e_input[2*W*(i+1)-1:2*W*i];
assign x1[i] = e_input[2*W*(i+1)-1:2*W*(i+1)-W];
assign y1[i] = e_input[2*W*(i+1)-W-1:2*W*i];
end
endgenerate
generate
for (i=0;i<N;i=i+1)
begin:dist_inst
taxicab_distance
#(
.N(W)
)
taxicab_distance_
(
.x1(x1[i]), .y1(y1[i]), .x2(x2), .y2(y2),
.dist(dist[i])
);
end
endgenerate
assign min_val_x[0] = x1[0];
assign min_val_y[0] = y1[0];
assign min_dist[0] = dist[0];
generate
for (i=1;i<N;i=i+1)
begin:comp_inst
COMP
#(
.N(W+2)
)
COMP_
(
.A(min_dist[i-1]),
.B(dist[i]),
.O(gt_dist[i])
);
end
endgenerate
generate
for (i=1;i<N;i=i+1)
begin:mux_inst
MUX
#(
.N(2*W)
)
MUX_1
(
//.A(DBi[i]),
.A({x1[i], y1[i]}),
.B({min_val_x[i-1], min_val_y[i-1]}),
.S(gt_dist[i]),
.O({min_val_x[i], min_val_y[i]})
);
MUX
#(
.N(W+2)
)
MUX_2
(
.A(dist[i]),
.B(min_dist[i-1]),
.S(gt_dist[i]),
.O(min_dist[i])
);
//assign min_val[i] = (gt_dist[i])? DBi[i] :min_val[i-1];
//assign min_dist[i] = (gt_dist[i])? dist[i] :min_dist[i-1];
end
endgenerate
assign o = {min_val_x[N-1], min_val_y[N-1]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <class T> T gi() { T x = 0; bool f = 0; char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); if (c == - ) f = 1, c = getchar(); while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return f ? -x : x; } const int N = 2e5 + 10; struct node { int to, nxt, w; } g[N << 1]; int lst[N], gl, w[N]; void add(int z, int y, int x) { g[++gl] = (node){y, lst[x], z}; lst[x] = gl; g[++gl] = (node){x, lst[y], z}; lst[y] = gl; } int ans1; double ans2; int siz[N], mx, rt, sum; bool vis[N]; void getroot(int u, int ff) { siz[u] = 1; int s = 0; for (int i = lst[u]; i; i = g[i].nxt) { int v = g[i].to; if (v == ff || vis[v]) continue; getroot(v, u); siz[u] += siz[v]; s = max(s, siz[v]); } s = max(s, sum - siz[u]); if (s < mx) mx = s, rt = u; } double sd[N], sumd, ans; void dfs(int u, int ff, int tp, int dep) { ans += pow(dep, 1.5) * w[u]; sumd += 1.5 * sqrt(dep) * w[u]; sd[tp] += 1.5 * sqrt(dep) * w[u]; for (int i = lst[u]; i; i = g[i].nxt) { int v = g[i].to; if (v == ff) continue; dfs(v, u, tp, dep + g[i].w); } } void solve(int u) { vis[u] = 1; ans = sumd = 0; for (int i = lst[u]; i; i = g[i].nxt) sd[g[i].to] = 0, dfs(g[i].to, u, g[i].to, g[i].w); if (ans2 > ans) ans1 = u, ans2 = ans; for (int i = lst[u]; i; i = g[i].nxt) { int v = g[i].to; if (vis[v]) continue; if (sumd - sd[v] > sd[v]) continue; mx = sum = siz[v]; getroot(v, u); solve(rt); } } int main() { int n = gi<int>(); for (int i = 1; i <= n; i++) w[i] = gi<int>(); for (int i = 1; i < n; i++) add(gi<int>(), gi<int>(), gi<int>()); ans2 = 1e20; mx = sum = n; getroot(1, 0); solve(rt); printf( %d %.10lf n , ans1, ans2); return 0; }
|
/* HW4, Problem 16 */
module ct4(output reg [3:0] count, output reg carry_out, input enable_l, clk_l, reset, load, input [3:0] data);
always @(negedge clk_l)
if (reset) count <= 0;
else if (load) count <= data;
else if (!enable_l) count <= count + 1;
always @(count)
if (count == 'b1111) carry_out <= 1;
else carry_out <= 0;
endmodule
module ct8(output [7:0] count, output carry_out, input enable_l, clk_l, reset, load, input [7:0] data);
wire carry_out_inter;
ct4 dev1(count[3:0], carry_out_inter, enable_l, clk_l , reset, load, data[3:0]);
ct4 dev2(count[7:4], carry_out , enable_l, carry_out_inter, reset, load, data[7:4]);
endmodule
module tb_p16();
reg enable_l, clk_l, reset, load;
reg [7:0] data;
wire [7:0] count;
wire carry_out;
ct4 dev1(count[3:0], carry_out, enable_l, clk_l , reset, load, data[3:0]);
ct4 dev2(count[7:4], _ , enable_l, carry_out, reset, load, data[7:4]);
initial begin
clk_l = 0;
forever #5 clk_l = ~clk_l;
end
initial begin
enable_l = 1;
reset = 0;
load = 0;
data = 200;
reset = 1;
#5 reset = 0;
$dumpfile("p16.vcd");
$dumpvars(0, tb_p16);
fork
#100 enable_l = 1;
#120 load = 1;
#130 load = 0;
#150 enable_l = 0;
#200 load = 1;
#240 load = 0;
#300 reset = 1;
#320 reset = 0;
#500 $finish;
join
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e6 + 7; const int mod = 1e9 + 7; int a[N]; int l[N]; int c[N]; int f[N]; int binpow(int a, int b) { int ret = 1; while (b) { if (b & 1) { ret = (ret * 1LL * a) % mod; --b; } a = (a * 1LL * a) % mod; b >>= 1; } return ret; } int main() { f[0] = 1; for (int i = 1; i < N; ++i) f[i] = (f[i - 1] * 1LL * i) % mod; int n; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); sort(a, a + n); c[0] = 1; for (int i = 1; i < n; ++i) { l[i] = a[i] == a[i - 1] ? l[i - 1] : l[i - 1] + c[i - 1]; c[i] = a[i] == a[i - 1] ? c[i - 1] + 1 : 1; } int res = 0; for (int i = 0; i < n; ++i) { if (a[i] == a[n - 1]) break; int v = (a[i] * 1LL * f[l[i]]) % mod; v = (v * 1LL * f[n - l[i] - 1]) % mod; v = (v * 1LL * f[n]) % mod; v = (v * 1LL * binpow((f[n - l[i]] * 1LL * f[l[i]]) % mod, mod - 2)) % mod; res = (res + v) % mod; } printf( %d n , res); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize -O3 using namespace std; const int MAXN = 2100; int n, m; long long a[MAXN]; long long aa[MAXN]; long long b[MAXN]; long long bb[MAXN]; long long x; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < n; ++i) cin >> a[i]; for (int j = 0; j < m; ++j) cin >> b[j]; cin >> x; for (int i = 1; i <= n; ++i) aa[i] = x + 1; for (int i = 1; i <= m; ++i) bb[i] = x + 1; for (int i = 0; i < n; ++i) { long long sum = 0; for (int j = i; j < n; ++j) { sum += a[j]; aa[j - i + 1] = min(aa[j - i + 1], sum); } } for (int i = 0; i < m; ++i) { long long sum = 0; for (int j = i; j < m; ++j) { sum += b[j]; bb[j - i + 1] = min(bb[j - i + 1], sum); } } int ans = 0; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) { if (aa[i] * bb[j] <= x) ans = max(ans, i * j); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> long long n, m, a, d, t[100007], old, ans, aind, firstA, stepD; int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); std::cout.tie(0); std::cin >> n >> m >> a >> d; for (int i = 0; i < m; ++i) std::cin >> t[i]; aind = d / a * a + a; for (int i = 0; i < m; ++i) { if (t[i] <= old) continue; if (t[i] <= n * a) { firstA = (old / a + 1) * a; if (t[i] <= firstA) { ++ans; old = t[i] + d; } else { stepD = (t[i] - firstA) / aind + ((t[i] - firstA) % aind ? 1 : 0); ans += stepD; old = firstA + stepD * aind - (a - d % a); if (old < t[i]) { ++ans; firstA = (old / a + 1) * a; old = std::min(t[i], firstA) + d; } } } else { if (old < n * a) { firstA = (old / a + 1) * a; stepD = (n * a - firstA) / aind + ((n * a - firstA) % aind ? 1 : 0); ans += stepD; old = firstA + stepD * aind - (a - d % a); if (old < n * a) { ++ans; firstA = (old / a + 1) * a; old = firstA + d; } } if (old < t[i]) { ++ans; old = t[i] + d; } } } if (old < a * n) { firstA = (old / a + 1) * a; stepD = (a * n - firstA) / aind + ((a * n - firstA) % aind ? 1 : 0); ans += stepD; old = firstA + stepD * aind - (a - d % a); if (old < a * n) { ++ans; } } std::cout << ans; }
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Core
-- Description: Nucleo de encriptacion DES. El bloque trabaja con un
bloque de datos a encriptar de 64 bits denominado
'plaintext' y una llave de encriptacion de 64 bits
llamada 'key'.
El proceso de encriptacion tiene una duracion de 16
ciclos de reloj.
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_core
(
input wire clk,
input wire reset,
// -- input -------------------------------------------------- >>>>>
input wire start_strobe_din,
input wire [0:63] plaintext_din,
input wire [0:63] key_din,
// -- output ------------------------------------------------- >>>>>
output wire done_strobe_dout,
output wire active_des_engine_dout,
output wire parity_check_dout,
output wire [0:63] ciphertext_dout
);
// -- Declaracion temprana de señales ---------------------------- >>>>>
wire enable;
wire source;
wire round_shift;
wire [0:47] round_key;
wire [0:63] ciphertext;
// -- Parity Drop ------------------------------------------------ >>>>>
/*
-- Nota: La llave de DES esta formada por 64 bits. Sin embargo,
los datos utilizados de manera efectiva son 56. Este
paso elimina los bits de paridad de toda la llave,
dejando atras solo datos efectivos.
*/
wire [0:55] parity_drop_key;
wire parity_check;
assign parity_drop_key[0 +: 8] = {
key_din[56],
key_din[48],
key_din[40],
key_din[32],
key_din[24],
key_din[16],
key_din[8],
key_din[0]
};
assign parity_drop_key[8 +: 8] = {
key_din[57],
key_din[49],
key_din[41],
key_din[33],
key_din[25],
key_din[17],
key_din[9],
key_din[1]
};
assign parity_drop_key[16 +: 8] = {
key_din[58],
key_din[50],
key_din[42],
key_din[34],
key_din[26],
key_din[18],
key_din[10],
key_din[2]
};
assign parity_drop_key[24 +: 8] = {
key_din[59],
key_din[51],
key_din[43],
key_din[35],
key_din[62],
key_din[54],
key_din[46],
key_din[38]
};
assign parity_drop_key[32 +: 8] = {
key_din[30],
key_din[22],
key_din[14],
key_din[6],
key_din[61],
key_din[53],
key_din[45],
key_din[37]
};
assign parity_drop_key[40 +: 8] = {
key_din[29],
key_din[21],
key_din[13],
key_din[5],
key_din[60],
key_din[52],
key_din[44],
key_din[36]
};
assign parity_drop_key[48 +: 8] = {
key_din[28],
key_din[20],
key_din[12],
key_din[4],
key_din[27],
key_din[19],
key_din[11],
key_din[3]
};
assign parity_check_dout = key_din[7] ^
key_din[15] ^
key_din[23] ^
key_din[31] ^
key_din[39] ^
key_din[47] ^
key_din[55] ^
key_din[63];
// -- Unidad de Control ------------------------------------------ >>>>>
des_control unidad_control
(
.clk (clk),
.reset (reset),
// -- input ---------------------------------------------- >>>>>
.start_strobe_din (start_strobe_din),
// -- output --------------------------------------------- >>>>>
.enable_dout (enable),
.source_dout (source),
.active_dout (active_des_engine_dout),
.round_shift_dout (round_shift),
.done_strobe_dout (done_strobe_dout)
);
// -- Camino de datos de nucleo DES ------------------------------ >>>>>
// -- Generador de Round keys ------------------------------- >>>>>>
des_key_generator key_generator
(
.clk (clk),
.reset (reset),
// -- input ------------------------------------------ >>>>>
.enable_din (enable),
.source_sel_din (source),
.round_shift_din (round_shift),
.parity_drop_key_din(parity_drop_key),
// -- output ----------------------------------------- >>>>>
.round_key_dout (round_key)
);
// -- Rondas de encriptacion --------------------------------- >>>>>
des_datapath cipher_rounds
(
.clk (clk),
.reset (reset),
// -- inputs ----------------------------------------- >>>>>
.enable (enable),
.source_sel (source),
.plaintext_din (plaintext_din),
.round_key_din (round_key),
// -- outputs ---------------------------------------- >>>>>
.ciphertext_dout(ciphertext)
);
// -- logica de salida --------------------------------------- >>>>>
assign ciphertext_dout = ciphertext;
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
des_core des_engine
(
.clk(clk),
.reset(reset),
// -- input -------------------------------------------------- >>>>>
.start_strobe_din (start_strobe_din),
.plaintext_din (plaintext_din),
.key_din (key_din),
// -- output ------------------------------------------------- >>>>>
.done_strobe_dout (done_strobe_dout),
.active_des_engine_dout (active_des_engine_dout),
.parity_check_dout (parity_check_dout),
.ciphertext_dout (ciphertext_dout)
);
*/
|
#include <bits/stdc++.h> using namespace std; const int N = 255; int parent[N]; int ra[N]; void make_set(int v) { parent[v] = v; ra[v] = 0; } int find_set(int v) { if (v == parent[v]) return v; return parent[v] = find_set(parent[v]); } void union_sets(int a, int b) { a = find_set(a); b = find_set(b); if (a != b) { if (ra[a] < ra[b]) swap(a, b); parent[b] = a; if (ra[a] == ra[b]) ++ra[a]; } } string s[N]; int main() { cout.sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> s[i]; } for (int i = 0; i < n; i++) make_set(i); for (int j = 0; j < m; j++) make_set(100 + j); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == # ) { union_sets(i, 100 + j); } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == # && find_set(i) != find_set(100 + j)) { cout << No ; return 0; } if (s[i][j] != # && find_set(i) == find_set(100 + j)) { cout << No ; return 0; } } } cout << Yes ; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define ll long long #define ld long double #define For(i,x,y) for(ll i = (x);i <= (y);++i) #define FOr(i,x,y) for(ll i = (x);i >= (y);--i) #define fi first #define se second #define pa pair<ll,ll> #define mk make_pair #define pb push_back #define clr(a,b) memset(a,b,sizeof(a)) #define cpy(a,b) memcpy(a,b,sizeof(b)) #define y1 y11111111111111111111 #define debug puts( @@@@@@@@@@@@@@@@@@@@ ) #define NO puts( NO ) #define YES puts( YES ) #define Yes puts( Yes ) #define No puts( No ) inline ll read() { ll x = 0,f = 1;char ch = getchar(); while(ch < 0 || ch > 9 ){if(ch == - )f = -1;ch = getchar();} while(ch >= 0 && ch <= 9 ){x = x*10+ch- 0 ;ch = getchar();} return x*f; } char s[999]; int main() { while (scanf( %s ,s)!=EOF) { if (s[1]== s ) puts( NO ),fflush(stdout); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_2_V
`define SKY130_FD_SC_HS__A222OI_2_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222oi_2 (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_2_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Resistor to GND
// /___/ /\ Filename : PULLDOWN.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module PULLDOWN (O);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
wire A;
pulldown (A);
buf (weak0,weak1) #(100,100) (O,A);
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int read() { int xx = 0, ff = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) ff = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { xx = xx * 10 + ch - 0 ; ch = getchar(); } return xx * ff; } int N, K, f[110][100010]; struct Segment { int L, R; } S[110]; int q[100010], head, tail; int main() { N = read(), K = read(); for (int i = 1; i <= K; i++) S[i].L = read(), S[i].R = read(); for (int j = 0; j <= N; j++) f[0][j] = (1 << 29); f[0][0] = 0; for (int i = 1; i <= K; i++) { for (int j = 0; j <= N; j++) f[i][j] = f[i - 1][j]; head = 1, tail = 0; for (int j = 0; j <= S[i].R; j++) { if (j <= N) { while (head <= tail && f[i - 1][j] <= f[i - 1][q[tail]]) tail--; q[++tail] = j; } while (head <= tail && q[head] <= j - (S[i].R - S[i].L + 1)) head++; if (head <= tail) f[i][j] = min(f[i][j], f[i - 1][q[head]] + 2); } head = 1, tail = 0; for (int j = S[i].R; j >= 0; j--) { if (S[i].R - j <= N) { while (head <= tail && f[i - 1][S[i].R - j] <= f[i - 1][q[tail]]) tail--; q[++tail] = S[i].R - j; } while (head <= tail && q[head] <= S[i].L - (j + 1)) head++; if (head <= tail) f[i][j] = min(f[i][j], f[i][q[head]] + 1); } } if (f[K][N] >= (1 << 29)) puts( Hungry ); else { puts( Full ); printf( %d n , f[K][N]); } return 0; }
|
module basic_FuncLED(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-MM LED Control.
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
//Avalon-ST LED Control.
input [23:0] asi_ledf_data,
input asi_ledf_valid,
//LED pin-out.
output coe_LED_R,
output coe_LED_G,
output coe_LED_B
);
assign avs_ctrl_readdata = {led_asi_en, 7'b0, led_r_data, led_g_data, led_b_data};
assign avs_ctrl_waitrequest = 1'b0;
reg [7:0] led_r_data, led_g_data, led_b_data;
reg [7:0] led_r_cnt, led_g_cnt, led_b_cnt;
reg led_r, led_g, led_b;
reg led_asi_en;
assign coe_LED_R = led_r;
assign coe_LED_G = led_g;
assign coe_LED_B = led_b;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
led_r_data <= 0;
led_g_data <= 0;
led_b_data <= 0;
led_asi_en <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) led_asi_en <= avs_ctrl_writedata[31];
end
if(led_asi_en) begin
if(asi_ledf_valid) begin
led_r_data <= asi_ledf_data[23:16];
led_g_data <= asi_ledf_data[15:8];
led_b_data <= asi_ledf_data[7:0];
end
end
else if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[2]) led_r_data <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) led_g_data <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) led_b_data <= avs_ctrl_writedata[7:0];
end
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
led_r_cnt <= 0;
led_g_cnt <= 0;
led_b_cnt <= 0;
led_r <= 1'b1;
led_g <= 1'b1;
led_b <= 1'b1;
end
else begin
led_r_cnt <= led_r_cnt + 1;
led_g_cnt <= led_g_cnt + 1;
led_b_cnt <= led_b_cnt + 1;
if(led_r_cnt < led_r_data) led_r <= 1'b0; else led_r <= 1'b1;
if(led_g_cnt < led_g_data) led_g <= 1'b0; else led_g <= 1'b1;
if(led_b_cnt < led_b_data) led_b <= 1'b0; else led_b <= 1'b1;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// rstgen.v: reset generator, based on lfsr counter //
// //
// Ameer M.S. Abdelhadi (; ), May 2012 //
////////////////////////////////////////////////////////////////////////////////////
`include "math.v"
module rstgen
#( parameter WID = 16 ) // LOG2 reset cycles
( input clk , // input clock
input rsti , // input reset; pass 1'b0 if not required
output rsto ); // output reset
// lfsr count output
reg [WID-1:0] cnt;
// lfst feedback function
wire fb;
lfsr_fb #( .WID(WID) ) // integer: register width, up to 168.
lfsr_fb_inst ( .cnt(cnt) , // input clock
.fb (fb ) ); // output random count number
localparam LASTCNT = {1'b1,{(WID-1){1'b0}}}; // last lfsr number before rolling back to all 0's
wire is_last = (cnt == LASTCNT) ; // last lfsr number reached
always @(posedge clk or posedge rsti)
if (rsti ) cnt <= {WID{1'b0}} ;
else if (is_last) cnt <= LASTCNT ;
else cnt <= {cnt[WID-2:0],fb};
reg is_last_rh;
always @(posedge clk or posedge rsti)
if (rsti) is_last_rh <= 1'b0 ;
else is_last_rh <= is_last;
//reg is_last_rl;
//always @(negedge clk or posedge rsti)
// if (rsti) is_last_rl <= 1'b0 ;
// else is_last_rl <= is_last_rh;
assign rsto = !is_last_rh;
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:20000000 ) string problem_name = a ; void init() { freopen((problem_name + .in ).c_str(), rt , stdin); } long long res = 0; int ms[300100]; int len; void mul(int val) { int p = 0; for (int i = 0; i < 300000; i++) { p += ms[i] *= val; ms[i] = p % 10; p /= 10; } } int main() { string s; cin >> s; vector<int> u(255, 0); res = 1; int zero = 0; long long col = 10; int c = 0; int c2 = 0; for (int i = 0; i < int((s).size()); i++) { if (s[i] == ? ) { c++; } else if (isalpha(s[i])) { if (u[s[i]]) continue; u[s[i]] = 1; if (col <= 0) { res = 0; zero = 1; break; } c2++; col--; } } if (zero) { cout << 0; return 0; } if (c) { if (s[0] == ? ) ms[c - 1] = 9; else ms[c] = 1; } else ms[0] = 1; if (c2) { for (int i = 10; i > 10 - c2; i--) { if (i == 10 && isalpha(s[0])) mul(9); else mul(i); } } int len = 300000; while (!ms[len]) len--; for (int i = len; i >= 0; i--) printf( %d , ms[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> v; for (int i = 0; i < n; i++) { int num; cin >> num; v.push_back(num); } vector<pair<int, int> > vp; int x, y; for (int i = 0; i < n; i++) { if (i == 0) { x = v[i + 1] - v[i]; y = v[n - 1] - v[i]; } else if (i == n - 1) { x = v[i] - v[i - 1]; y = v[i] - v[0]; } else { x = min(v[i] - v[i - 1], v[i + 1] - v[i]); y = max(v[i] - v[0], v[n - 1] - v[i]); } vp.push_back(make_pair(x, y)); } for (auto &i : vp) { cout << i.first << << i.second << endl; } return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 20; const int V = (1 << 20) + 10; const int P = 1000000007; int Pow(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = (long long)ret * x % P; x = (long long)x * x % P; y /= 2; } return ret; } void utf(int *a, int l, int r) { if (l + 1 != r) { int mid = (l + r) / 2; for (int i = 0; i < mid - l; i++) { a[l + i] -= a[mid + i]; if (a[l + i] < 0) a[l + i] += P; } utf(a, l, mid); utf(a, mid, r); } } void tf(int *a, int l, int r) { if (l + 1 != r) { int mid = (l + r) / 2; tf(a, l, mid); tf(a, mid, r); for (int i = 0; i < mid - l; i++) { if (((l + i) & (mid + i)) != (l + i)) while (1) ; a[l + i] += a[mid + i]; if (a[l + i] >= P) a[i + l] -= P; } } } int cnt[V], q[V]; int n, x, pro[V]; int pt[V]; int main() { pt[0] = 1; for (int i = 1; i < (1 << N); i++) pt[i] = pt[i - 1] * 2 % P; while (~scanf( %d , &n)) { memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < n; i++) { scanf( %d , &x); cnt[x]++; } tf(cnt, 0, (1 << N)); for (int i = 0; i < (1 << N); i++) pro[i] = pt[cnt[i]]; utf(pro, 0, (1 << N)); printf( %d n , pro[0]); } return 0; }
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define SGB_HOOK
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
//input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
//input [23:0] SAVERAM_MASK,
//input [23:0] ROM_MASK,
output msu_enable,
//output srtc_enable,
output sgb_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output button_enable,
output button_addr
);
/* feature bits. see src/fpga_spi.c for mapping */
parameter [2:0]
FEAT_DSPX = 0,
FEAT_ST0010 = 1,
FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
- LoROM
*/
assign IS_ROM = ~SNES_ROMSEL;
// Original SGB SNES code does not enable SaveRAM. If a SD2SNES feature is added to support this
// the firmware will need a way to back it up. Also SNES access to PSRAM will create bus
// contention with the GB. A better solution is to have the GB code use its SaveRAM.
assign IS_SAVERAM = 0;
// LoROM: A23 = r03/r04 A22 = r06 A21 = r05 A20 = 0 A19 = d/c
assign IS_WRITABLE = IS_SAVERAM;
// Only a LOROM image of up to 512KB is supported. MAPPER, ROMMASK, and RAMMASK have been repurposed for GB.
assign SRAM_SNES_ADDR = {5'h00, SNES_ADDR[19:16], SNES_ADDR[14:0]};
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign sgb_enable = !SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hf808) == 16'h6000 || (SNES_ADDR[15:0] & 16'hf80F) == 16'h600F || (SNES_ADDR[15:0] & 16'hf000) == 16'h7000); // 6000/2/8-F -67FF, 7000-7FFF -> 6000/2/8-F, 7000-700F, 7800 unique
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
// Simplified button snooping for SGB hook code. See cheats.v for more details.
// $010F11 <- $4218
// $010F12 <- $4219
assign button_enable = {SNES_ADDR[23:2],2'b00} == {24'h010F10} && SNES_ADDR[1] != SNES_ADDR[0];
assign button_addr = ~SNES_ADDR[0];
endmodule
|
// $Id: vcr_comb_alloc_mac.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// combined VC and switch allocator for VC router
module vcr_comb_alloc_mac
(clk, reset, route_port_ip_ivc, inc_rc_ip_ivc, elig_op_ovc, vc_req_ip_ivc,
vc_gnt_ip_ivc, vc_gnt_ip_ivc_ovc, vc_gnt_op_ovc, vc_gnt_op_ovc_ip,
vc_gnt_op_ovc_ivc, sw_req_ip_ivc, sw_gnt_ip_ivc, sw_gnt_op_ip);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// number of input and output ports on router
parameter num_ports = 5;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// select implementation variant for switch allocator
parameter allocator_type = `SW_ALLOC_TYPE_SEP_IF;
// select implementation variant for wavefront allocator
// (note: only valid for SW_ALLOC_TYPE_WF_BASE+x
localparam wf_alloc_type = allocator_type-`SW_ALLOC_TYPE_WF_BASE;
// select which arbiter type to use in allocator
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// destination port selects
input [0:num_ports*num_vcs*port_idx_width-1] route_port_ip_ivc;
// transition to next resource class
input [0:num_ports*num_vcs-1] inc_rc_ip_ivc;
// output VC is eligible for allocation (i.e., not currently allocated)
input [0:num_ports*num_vcs-1] elig_op_ovc;
// VC requests
input [0:num_ports*num_vcs-1] vc_req_ip_ivc;
// granted output VC (to input controller)
output [0:num_ports*num_vcs*num_vcs-1] vc_gnt_ip_ivc_ovc;
wire [0:num_ports*num_vcs*num_vcs-1] vc_gnt_ip_ivc_ovc;
// VC grants (to input controller)
output [0:num_ports*num_vcs-1] vc_gnt_ip_ivc;
wire [0:num_ports*num_vcs-1] vc_gnt_ip_ivc;
// output VC was granted (to output controller)
output [0:num_ports*num_vcs-1] vc_gnt_op_ovc;
wire [0:num_ports*num_vcs-1] vc_gnt_op_ovc;
// input port that each output VC was granted to
output [0:num_ports*num_vcs*num_ports-1] vc_gnt_op_ovc_ip;
wire [0:num_ports*num_vcs*num_ports-1] vc_gnt_op_ovc_ip;
// input VC that each output VC was granted to
output [0:num_ports*num_vcs*num_vcs-1] vc_gnt_op_ovc_ivc;
wire [0:num_ports*num_vcs*num_vcs-1] vc_gnt_op_ovc_ivc;
// switch requests
input [0:num_ports*num_vcs-1] sw_req_ip_ivc;
// switch grants (to input controller)
output [0:num_ports*num_vcs-1] sw_gnt_ip_ivc;
wire [0:num_ports*num_vcs-1] sw_gnt_ip_ivc;
// crossbar control signals
output [0:num_ports*num_ports-1] sw_gnt_op_ip;
wire [0:num_ports*num_ports-1] sw_gnt_op_ip;
generate
case(allocator_type)
`SW_ALLOC_TYPE_SEP_IF:
begin
vcr_comb_alloc_sep_if
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.arbiter_type(arbiter_type),
.reset_type(reset_type))
core_sep_if
(.clk(clk),
.reset(reset),
.route_port_ip_ivc(route_port_ip_ivc),
.inc_rc_ip_ivc(inc_rc_ip_ivc),
.elig_op_ovc(elig_op_ovc),
.vc_req_ip_ivc(vc_req_ip_ivc),
.vc_gnt_ip_ivc(vc_gnt_ip_ivc),
.vc_gnt_ip_ivc_ovc(vc_gnt_ip_ivc_ovc),
.vc_gnt_op_ovc(vc_gnt_op_ovc),
.vc_gnt_op_ovc_ip(vc_gnt_op_ovc_ip),
.vc_gnt_op_ovc_ivc(vc_gnt_op_ovc_ivc),
.sw_req_ip_ivc(sw_req_ip_ivc),
.sw_gnt_ip_ivc(sw_gnt_ip_ivc),
.sw_gnt_op_ip(sw_gnt_op_ip));
end
/*`SW_ALLOC_TYPE_SEP_OF:
begin
vcr_comb_alloc_sep_of
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.arbiter_type(arbiter_type),
.reset_type(reset_type))
core_sep_of
(.clk(clk),
.reset(reset),
.route_port_ip_ivc(route_port_ip_ivc),
.inc_rc_ip_ivc(inc_rc_ip_ivc),
.elig_op_ovc(elig_op_ovc),
.vc_req_ip_ivc(vc_req_ip_ivc),
.vc_gnt_ip_ivc(vc_gnt_ip_ivc),
.vc_gnt_ip_ivc_ovc(vc_gnt_ip_ivc_ovc),
.vc_gnt_op_ovc(vc_gnt_op_ovc),
.vc_gnt_op_ovc_ip(vc_gnt_op_ovc_ip),
.vc_gnt_op_ovc_ivc(vc_gnt_op_ovc_ivc),
.sw_req_ip_ivc(sw_req_ip_ivc),
.sw_gnt_ip_ivc(sw_gnt_ip_ivc),
.sw_gnt_op_ip(sw_gnt_op_ip));
end*/
endcase
/*if(allocator_type >= `SW_ALLOC_TYPE_WF_BASE)
begin
vcr_comb_alloc_wf
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.wf_alloc_type(wf_alloc_type),
.arbiter_type(arbiter_type),
.reset_type(reset_type))
core_wf
(.clk(clk),
.reset(reset),
.route_port_ip_ivc(route_port_ip_ivc),
.inc_rc_ip_ivc(inc_rc_ip_ivc),
.elig_op_ovc(elig_op_ovc),
.vc_req_ip_ivc(vc_req_ip_ivc),
.vc_gnt_ip_ivc(vc_gnt_ip_ivc),
.vc_gnt_ip_ivc_ovc(vc_gnt_ip_ivc_ovc),
.vc_gnt_op_ovc(vc_gnt_op_ovc),
.vc_gnt_op_ovc_ip(vc_gnt_op_ovc_ip),
.vc_gnt_op_ovc_ivc(vc_gnt_op_ovc_ivc),
.sw_req_ip_ivc(sw_req_ip_ivc),
.sw_gnt_ip_ivc(sw_gnt_ip_ivc),
.sw_gnt_op_ip(sw_gnt_op_ip));
end*/
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b); long long int gcd(long long int a, long long int b); int prime(int n); long long int lcm(long long int a, long long int b) { return (a * b) / gcd(a, b); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; cin >> t; while (t--) { string a; cin >> a; long long int n = a.size(); long long int k = 0; for (int i = 0; i < n; i++) { if (a[i] != 0 ) k++; } cout << k << endl; for (int i = 0; i < n; i++) { if (a[i] != 0 ) { cout << a[i]; for (int j = i + 1; j < n; j++) cout << 0 ; cout << ; } } cout << endl; } } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } int prime(int n) { int flag = 1; for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { flag = 0; break; } } return flag; }
|
#include <bits/stdc++.h> int main() { int num; int count = 0, i; int digitos[10]; scanf( %d , &num); int aux = num; for (i = 0; i < 10; i++) digitos[i] = 0; while (aux != 0) { digitos[aux % 10] = 1; aux = aux / 10; } if (num == 1) { printf( 1 n ); return 0; } for (i = 1; i * i <= num; i++) { if (num % i == 0) { aux = i; while (aux != 0) { if (digitos[aux % 10] == 1) { count++; break; } aux = aux / 10; } aux = num / i; if (aux != i) while (aux != 0) { if (digitos[aux % 10] == 1) { count++; break; } aux = aux / 10; } } } printf( %d n , count); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 6; int n, m; int a[200]; bool check() { if (*max_element(a, a + n) != 0) { return false; } return true; } void solve() { int k; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } if (k == 1) { if ((count(a, a + n, *max_element(a, a + n))) != n) { cout << -1 << n ; return; } else { cout << 1 << n ; return; } } m = 0; while (!check()) { int tmp = k; m++; std::vector<int> b(n); for (int i = 0; i < n; i++) { if (i == 0) { tmp--; } else { if (a[i] != a[i - 1]) { if (tmp == 0) break; else { tmp--; } } } b.push_back(i); } for (auto j : b) { a[j] = 0; } } cout << m << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int T; cin >> T; while (T--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> A(n + 10, 0); for (int i = 0; i < n; i++) cin >> A[i]; unordered_map<long long, int> fir, sec; fir[A[0]] = 1; for (int i = 1; i < n; i++) sec[A[i]]++; long long S = 0; for (int i = 0; i < n; i++) S += A[i]; long long sdash = 0; if (S & 1) { cout << NO << endl; return 0; } for (int i = 0; i < n; i++) { sdash += A[i]; if (sdash == S / 2) { cout << YES ; return 0; } if (sdash < S / 2) { long long x = S / 2 - sdash; if (sec[x] > 0) { cout << YES ; return 0; } } else { long long y = sdash - S / 2; if (fir[y] > 0) { cout << YES ; return 0; } } fir[A[i + 1]]++; sec[A[i + 1]]--; } cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMD64E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/21/12 - CR649330 - Add RAM_ADDRESS_MASK to allow floating WADR6/7.
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMD64E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [1:0] RAM_ADDRESS_MASK = 2'b00,
parameter [1:0] RAM_ADDRESS_SPACE = 2'b00
)(
output O,
input CLK,
input I,
input RADR0,
input RADR1,
input RADR2,
input RADR3,
input RADR4,
input RADR5,
input WADR0,
input WADR1,
input WADR2,
input WADR3,
input WADR4,
input WADR5,
input WADR6,
input WADR7,
input WE
);
reg [63:0] mem;
wire [5:0] ADR_dly, ADR_in;
wire [5:0] radr;
wire CLK_dly, I_dly;
wire CLK_in, I_in;
wire [1:0] WADR_dly, WADR_in;
wire WE_dly, WE_in;
localparam MODULE_NAME = "RAMD64E";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
assign radr[5:0] = {RADR5, RADR4, RADR3, RADR2, RADR1, RADR0};
always @(posedge CLK_in)
if (WE_in == 1'b1 &&
(RAM_ADDRESS_MASK[1] || WADR_in[1] == RAM_ADDRESS_SPACE[1]) &&
(RAM_ADDRESS_MASK[0] || WADR_in[0] == RAM_ADDRESS_SPACE[0]) )
mem[ADR_in] <= #100 I_in;
assign O = mem[radr];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_in] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {WADR5, WADR4, WADR3, WADR2, WADR1, WADR0};
assign WADR_dly = {WADR7, WADR6};
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
assign WE_in = WE_dly;
assign I_in = I_dly;
assign ADR_in = ADR_dly;
assign WADR_in = WADR_dly;
`ifdef XIL_TIMING
specify
(CLK => O) = (0:0:0, 0:0:0);
(RADR0 => O) = (0:0:0, 0:0:0);
(RADR1 => O) = (0:0:0, 0:0:0);
(RADR2 => O) = (0:0:0, 0:0:0);
(RADR3 => O) = (0:0:0, 0:0:0);
(RADR4 => O) = (0:0:0, 0:0:0);
(RADR5 => O) = (0:0:0, 0:0:0);
$period (negedge CLK &&& WE, 0:0:0, notifier);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/** * created: 25/03/2021, 15:47:17 * pause: 16:11 - 16:18 **/ #include <bits/stdc++.h> using namespace std; const int max_n = 200222, inf = 1000111222; const int max_x = 2 * max_n; vector<long long> all; struct node { int cnt; long long sum, sum_l, sum_r; friend ostream& operator << (ostream &os, const node &nd) { os << (cnt = << nd.cnt << , s = << nd.sum << , sl = << nd.sum_l << , sr = << nd.sum_r << ) ; return os; } }; node combine(const node &a, const node &b) { return {a.cnt + b.cnt, a.sum + b.sum, a.sum_l + b.sum_l + a.sum * b.cnt, a.sum_r + b.sum_r + b.sum * a.cnt}; } struct segment_tree { node a[4 * max_x]; void build(int v, int l, int r, int cnt[]) { if (l == r) { a[v] = {cnt[l], cnt[l] * all[l], cnt[l] * all[l], cnt[l] * all[l]}; //cout << v << : [ << l << << r << ], nd = << a[v] << endl; return; } int mid = (l + r) / 2; build(2 * v, l, mid, cnt); build(2 * v + 1, mid + 1, r, cnt); a[v] = combine(a[2 * v], a[2 * v + 1]); //cout << v << : [ << l << << r << ], nd = << a[v] << endl; } void update(int v, int l, int r, int x, int value) { if (l == r) { a[v] = {value, value * all[l], value * all[l], value * all[l]}; return; } int mid = (l + r) / 2; if (x <= mid) { update(2 * v, l, mid, x, value); } else { update(2 * v + 1, mid + 1, r, x, value); } a[v] = combine(a[2 * v], a[2 * v + 1]); } node get_sum(int v, int tl, int tr, int l, int r) { if (tl == l && tr == r) { return a[v]; } int mid = (tl + tr) / 2; if (r <= mid) { return get_sum(2 * v, tl, mid, l, r); } else if (l > mid) { return get_sum(2 * v + 1, mid + 1, tr, l, r); } return combine(get_sum(2 * v, tl, mid, l, mid), get_sum(2 * v + 1, mid + 1, tr, mid + 1, r)); } long long get_sum_left(int v, int tl, int tr, int k) { if (tl == tr) { if (k == 1) { return a[v].sum; } return 0; } int mid = (tl + tr) / 2; if (k <= a[2 * v].cnt) { return get_sum_left(2 * v, tl, mid, k); } return a[2 * v].sum + get_sum_left(2 * v + 1, mid + 1, tr, k - a[2 * v].cnt); } long long get_sum_right(int v, int tl, int tr, int k) { if (tl == tr) { if (k == 1) { return a[v].sum; } return 0; } int mid = (tl + tr) / 2; if (k <= a[2 * v + 1].cnt) { return get_sum_right(2 * v + 1, mid + 1, tr, k); } return a[2 * v + 1].sum + get_sum_right(2 * v, tl, mid, k - a[2 * v + 1].cnt); } node get_node_left(int v, int tl, int tr, int k) { if (tl == tr) { return a[v]; } int mid = (tl + tr) / 2; if (k <= a[2 * v].cnt) { return get_node_left(2 * v, tl, mid, k); } return combine(a[2 * v], get_node_left(2 * v + 1, mid + 1, tr, k - a[2 * v].cnt)); } node get_node_right(int v, int tl, int tr, int k) { if (tl == tr) { return a[v]; } int mid = (tl + tr) / 2; if (k <= a[2 * v + 1].cnt) { return get_node_right(2 * v + 1, mid + 1, tr, k); } return combine(get_node_right(2 * v, tl, mid, k - a[2 * v + 1].cnt), a[2 * v + 1]); } }; int n, q, tp[max_n], cnt[max_x]; long long a[max_n], b[max_n]; segment_tree st; int compress(long long x) { return lower_bound(all.begin(), all.end(), x) - all.begin(); } long long solve() { //cout << # << st.a[1] << endl; long long res = st.a[1].sum_r - st.a[1].sum_l; const int k = st.a[1].cnt; if (k >= 3) { int pos = (k + 1) / 2 - 2; long long sr = st.get_sum_right(1, 0, all.size() - 1, pos + 1); long long sl = st.get_sum_left(1, 0, all.size() - 1, pos + 2); if (sr > sl) { int l = pos, r = k - 1; while (r - l > 1) { int mid = (l + r) / 2; long long sr = st.get_sum_right(1, 0, all.size() - 1, mid + 1); long long sl = st.get_sum_left(1, 0, all.size() - 1, mid + 2); if (sr > sl) { l = mid; } else { r = mid; } } int to = l; l = -1; r = pos; while (r - l > 1) { int mid = (l + r) / 2; long long sr = st.get_sum_right(1, 0, all.size() - 1, mid + 1); long long sl = st.get_sum_left(1, 0, all.size() - 1, mid + 2); if (sr > sl) { r = mid; } else { l = mid; } } int from = r; res -= st.get_node_right(1, 0, all.size() - 1, to + 1).sum_r; if (from) { res += st.get_node_right(1, 0, all.size() - 1, from).sum_r; } res += st.get_node_left(1, 0, all.size() - 1, to + 2).sum_l; res -= st.get_node_left(1, 0, all.size() - 1, from + 1).sum_l; /*for (int i = from; i <= to; ++i) { //res -= st.get_sum_right(1, 0, all.size() - 1, i + 1) - st.get_sum_left(1, 0, all.size() - 1, i + 2); res += st.get_sum_left(1, 0, all.size() - 1, i + 2); }*/ } } return res; } int main() { //freopen( input.txt , r , stdin); //freopen( output.txt , w , stdout); scanf( %d%d , &n, &q); for (int i = 0; i < n; ++i) { scanf( %lld , &a[i]); } for (int i = 0; i < q; ++i) { scanf( %d%lld , &tp[i], &b[i]); } for (int i = 0; i < n; ++i) { all.push_back(a[i]); } for (int i = 0; i < q; ++i) { all.push_back(b[i]); } sort(all.begin(), all.end()); all.erase(unique(all.begin(), all.end()), all.end()); for (int i = 0; i < n; ++i) { cnt[compress(a[i])] = 1; } st.build(1, 0, all.size() - 1, cnt); printf( %lld n , solve()); for (int i = 0; i < q; ++i) { if (tp[i] == 1) { st.update(1, 0, all.size() - 1, compress(b[i]), 1); } else { st.update(1, 0, all.size() - 1, compress(b[i]), 0); } printf( %lld n , solve()); } return 0; }
|
// -*- Mode: Verilog -*-
// Filename : test_00.v
// Description : Simple ADXL362 Test Case to bring environment to life
// Author : Philip Tracton
// Created On : Thu Jun 23 11:36:12 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 11:36:12 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
`include "simulation_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "boot_rom";
parameter number_of_tests = 0;
`include "setup.v"
reg err;
reg [31:0] data_out;
integer i;
initial begin
$display("Boot Case");
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
`UART_CONFIG;
// #300;
// `TEST_COMPLETE;
`UART_READ_CHAR(8'h30);
`UART_READ_CHAR(8'h31);
`UART_READ_CHAR(8'h32);
`UART_READ_CHAR(8'h33);
repeat(100) @(posedge `WB_CLK);
`UART_WRITE_CHAR("A");
`UART_READ_CHAR("A");
`UART_WRITE_CHAR("B");
`UART_READ_CHAR("B");
`UART_WRITE_CHAR("C");
`UART_READ_CHAR("C");
#10000;
`TEST_COMPLETE;
end
endmodule // test_case
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; int n; int m; int t[4 * N]; void upd(int l, int r, int v = 1, int tl = 1, int tr = N) { if (l > r) return; if (l <= tl && tr <= r) { t[v]++; return; } int tm = (tl + tr) / 2; upd(l, min(tm, r), v * 2, tl, tm); upd(max(tm + 1, l), r, v * 2 + 1, tm + 1, tr); } int get(int pos, int v = 1, int tl = 1, int tr = N) { if (tl == tr) return t[v]; int tm = (tl + tr) / 2; if (pos <= tm) return t[v] + get(pos, v * 2, tl, tm); else return t[v] + get(pos, v * 2 + 1, tm + 1, tr); } int main() { ios_base::sync_with_stdio(false); cin >> n >> m; long long res = 1; vector<pair<int, int>> left; vector<pair<int, int>> right; for (int i = 1; i <= n; i++) { int y, l, r; cin >> y >> l >> r; if (l == 0 && r == N) res++; if (l == 0) left.push_back({y, r}); else right.push_back({y, l}); } sort(left.begin(), left.end()); sort(right.begin(), right.end()); vector<pair<int, int>> top; vector<pair<int, int>> bottom; for (int i = 1; i <= m; i++) { int x, l, r; cin >> x >> l >> r; if (l == 0 && r == N) res++; if (l == 0) bottom.push_back({r, x}); else top.push_back({l, x}); } sort(bottom.begin(), bottom.end()); int i1 = 0, i2 = 0; for (int i = 0; i < (int)bottom.size(); i++) { while (i1 < (int)left.size() && left[i1].first <= bottom[i].first) { upd(0, left[i1].second); i1++; } while (i2 < (int)right.size() && right[i2].first <= bottom[i].first) { upd(right[i2].second, N); i2++; } res += get(bottom[i].second); } memset(t, 0, sizeof t); sort(top.rbegin(), top.rend()); reverse(left.begin(), left.end()); reverse(right.begin(), right.end()); i1 = 0, i2 = 0; for (int i = 0; i < (int)top.size(); i++) { while (i1 < (int)left.size() && left[i1].first >= top[i].first) { upd(0, left[i1].second); i1++; } while (i2 < (int)right.size() && right[i2].first >= top[i].first) { upd(right[i2].second, N); i2++; } res += get(top[i].second); } cout << res << n ; }
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* the module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const (clk, addr, out, effective);
input clk;
input [5:0] addr;
output reg [197:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
1: out <= 198'd0;
2: out <= 198'd1;
4: out <= {6'b000101, 192'd0};
8: out <= {6'b001001, 192'd0};
16: out <= {6'b010101, 192'd0};
default:
begin out <= 198'd0; effective <= 0; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m1, q; int m[102][102]; struct query { int t; int a; int b; int c; }; void rote(int type, int val) { if (type == 1) { int aux = m[val][m1]; for (int i = m1 - 1; i >= 1; i--) m[val][i + 1] = m[val][i]; m[val][1] = aux; } else { int aux = m[n][val]; for (int i = n - 1; i >= 1; i--) m[i + 1][val] = m[i][val]; m[1][val] = aux; } } int main() { cin >> n >> m1 >> q; stack<query> st; for (int i = 0; i < q; i++) { int in; cin >> in; if (in == 3) { int a, b, c; cin >> a >> b >> c; query qu; qu.t = in; qu.a = a; qu.b = b; qu.c = c; st.push(qu); } else { int a; cin >> a; query qu; qu.t = in; qu.a = a; st.push(qu); } } memset(m, 0, sizeof(m)); while (!st.empty()) { int type = st.top().t; if (type == 3) { int x, y, v; x = st.top().b; y = st.top().a; v = st.top().c; st.pop(); m[y][x] = v; } else { int a = st.top().a; st.pop(); rote(type, a); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m1; j++) cout << m[i][j] << ; cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_TB_V
`define SKY130_FD_SC_HD__NAND4B_TB_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hd__nand4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_TB_V
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [2:-1] vec;
integer idx;
initial begin
pass = 1'b1;
idx = 'bx;
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx] <= 1'b1;
`endif
#1 if (vec !== 4'bxxx) begin
$display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
vec[idx] <= 1'b1;
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx:0] <= 1'b1;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[0:1'bx] <= 1'b1;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx:1'bx] <= 1'b1;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx+:1] <= 1'b1;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx+:2] <= 2'b01;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx-:1] <= 1'b1;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1'bx-:2] <= 2'b01;
`endif
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
vec[idx+:1] <= 1'b1;
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[idx+:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
vec[idx+:2] <= 2'b01;
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[idx+:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
vec[idx-:1] <= 1'b1;
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[idx-:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
vec = 4'bxxxx;
vec[idx-:2] <= 2'b01;
#1 if (vec !== 4'bxxxx) begin
$display("Failed vec[idx-:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module ram0(
// Write port
input wrclk,
input [7:0] di,
input wren,
input [5:0] wraddr,
// Read port
input rdclk,
input rden,
input [5:0] rdaddr,
output reg [7:0] do);
(* syn_ramstyle = "block_ram" *) reg [7:0] ram[0:63];
initial begin
ram[0] = 8'b00000001;
ram[1] = 8'b10101010;
ram[2] = 8'b01010101;
ram[3] = 8'b11111111;
ram[4] = 8'b11110000;
ram[5] = 8'b00001111;
ram[6] = 8'b11001100;
ram[7] = 8'b00110011;
ram[8] = 8'b00000010;
ram[9] = 8'b00000100;
end
always @ (posedge wrclk) begin
if(wren == 1) begin
ram[wraddr] <= di;
end
end
always @ (posedge rdclk) begin
if(rden == 1) begin
do <= ram[rdaddr];
end
end
endmodule
module top (
input wire clk,
input wire pb0,
input wire pb1,
input wire [7:0] sw,
output wire [13:0] led
);
wire bufclk;
DCC gbuf_i(.CLKI(clk), .CLKO(bufclk));
wire rden;
reg wren;
wire [5:0] rdaddr;
wire [5:0] wraddr;
wire [7:0] di;
wire [7:0] do;
ram0 ram(
.wrclk(bufclk),
.di(di),
.wren(wren),
.wraddr(wraddr),
.rdclk(bufclk),
.rden(rden),
.rdaddr(rdaddr),
.do(do)
);
reg [5:0] address_reg;
reg [7:0] data_reg;
reg [7:0] out_reg;
assign rdaddr = address_reg;
assign wraddr = address_reg;
// input_mode == 00 -> in[3:0] -> address_reg
// input_mode == 01 -> in[3:0] -> data_reg[3:0]
// input_mode == 10 -> in[3:0] -> data_reg[7:4]
// input_mode == 11 -> data_reg -> ram[address_reg]
wire [1:0] input_mode;
// WE == 0 -> address_reg and data_reg unchanged.
// WE == 1 -> address_reg or data_reg is updated because on input_mode.
wire we;
assign input_mode[0] = ~sw[6];
assign input_mode[1] = ~sw[7];
assign we = ~pb0;
assign led = ~{address_reg, out_reg};
assign di = data_reg;
assign rden = 1;
initial begin
wren = 1'b0;
address_reg = 10'b0;
data_reg = 16'b0;
out_reg = 16'b0;
end
always @ (posedge bufclk) begin
out_reg <= do;
if(we == 1) begin
if(input_mode == 0) begin
address_reg <= ~sw[5:0];
wren <= 0;
end else if(input_mode == 1) begin
data_reg[3:0] <= ~sw[3:0];
wren <= 0;
end else if(input_mode == 2) begin
data_reg[7:4] <= ~sw[3:0];
wren <= 0;
end else if(input_mode == 3) begin
wren <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int num; int num_num; } num[105]; int main() { int N, M; scanf( %d%d , &N, &M); num[0].num = 0; num[0].num_num = 0; for (int i = 1; i <= N; i++) { int flag; scanf( %d , &flag); num[i].num = num[i - 1].num + flag; num[i].num_num = 0; } while (M--) { int left, right; scanf( %d%d , &left, &right); if (left == right && num[left].num - num[left - 1].num > 0) num[left].num_num++; else if (left < right && num[right].num - num[left - 1].num >= 0) { for (int i = left; i <= right; i++) num[i].num_num++; } } long long int sum = 0; for (int i = 1; i <= N; i++) { sum += (num[i].num - num[i - 1].num) * num[i].num_num; } printf( %I64d n , sum); return 0; }
|
#include <bits/stdc++.h> using namespace std; int true_mod(int A, int N) { A %= N; if (A < 0) A += N; return A; } const long long MOD = 1000LL * 1000LL * 1000LL + 7LL; const int MX = 109; struct matrix { long long A[MX][MX]; }; int x; void output(const matrix& A) { for (int i = 0; i < x; i++) { for (int j = 0; j < x; j++) cout << A.A[i][j] << ; cout << endl; } } matrix operator*(const matrix& A, const matrix& B) { matrix R; for (int i = 0; i < x; i++) { for (int k = 0; k < x; k++) { long long t = 0; for (int j = 0; j < x; j++) t += A.A[i][j] * B.A[j][k] % MOD; R.A[i][k] = t % MOD; } } return R; } matrix unity() { matrix R; for (int i = 0; i < x; i++) for (int j = 0; j < x; j++) R.A[i][j] = (i == j ? 1 : 0); return R; } matrix power(const matrix& A, int N) { matrix R = unity(), A_pow = A; while (N != 0) { if (N % 2 == 1) R = R * A_pow; A_pow = A_pow * A_pow; N /= 2; } return R; } int n, b, k; const long long B = 10; int cnt_D[MX] = {0}; matrix get_A() { matrix R; for (int i = 0; i < x; i++) { for (int j = 0; j < x; j++) { int smth = true_mod(j - 10 * i, x); R.A[i][j] = cnt_D[smth]; } } return R; } int main() { cin >> n >> b >> k >> x; for (int i = 0; i < n; i++) { int a; cin >> a; cnt_D[a % x]++; } matrix A = get_A(); matrix A_pow = power(A, b); cout << A_pow.A[0][k]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<string> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int j = 0; j < m; ++j) { vector<int> indx; for (int i = 0; i < n; ++i) { if (a[i][j] == # ) indx.push_back(i); } for (int i = 1; i < indx.size(); ++i) { if (a[indx[i]] != a[indx[0]]) { cout << No ; return 0; } } } cout << Yes ; return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; const int infinity = (int)1e9 + 42; const int64_t llInfinity = (int64_t)1e18 + 256; const int module = (int)1e9 + 7; const long double eps = 1e-8; mt19937_64 randGen(system_clock().now().time_since_epoch().count()); inline void raiseError(string errorCode) { cerr << Error : << errorCode << endl; exit(42); } signed main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; vector<vector<int> > g(n); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; g[a].push_back(b); g[b].push_back(a); } vector<int> d(n, INT_MAX); vector<int> p(n, -1); queue<int> q; q.push(0); d[0] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (int to : g[v]) { if (d[to] == INT_MAX) { d[to] = d[v] + 1; p[to] = v; q.push(to); } } } int ans1 = d[n - 1]; int idx2 = -1; for (int i = 0; i < n; i++) { if (d[i] == 2) { idx2 = i; break; } } if (ans1 > 4 && idx2 >= 0) { cout << 4 << endl; cout << 1 << << p[idx2] + 1 << << idx2 + 1 << << 1 << << n << endl; return 0; } if (ans1 > 5) { vector<char> used(n, false); vector<vector<int> > komps; vector<int> kompId(n, -1); used[0] = true; function<void(int)> dfs = [&](int v) { if (used[v]) { return; } used[v] = true; kompId[v] = (int)komps.size() - 1; komps.back().push_back(v); for (int to : g[v]) { dfs(to); } }; for (int i : g[0]) { if (!used[i]) { komps.emplace_back(); dfs(i); } } for (int i = 0; i < n; i++) { sort(g[i].begin(), g[i].end()); } for (auto &komp : komps) { sort(komp.begin(), komp.end()); bool klika = true; int ngsz = (int)komp.size(); int x = -1, y = -1; for (int i : komp) { if ((int)g[i].size() == ngsz) { continue; } for (int j : komp) { if (i == j) { continue; } if (!binary_search(g[i].begin(), g[i].end(), j)) { x = i; y = j; break; } } if (x < 0 || y < 0) { for (;;) ; } klika = false; break; } if (klika) { continue; } int z = -1; vector<int> xReach; for (int i = 1; i < n; i++) { if (i == x || i == y) { continue; } bool findX = binary_search(g[i].begin(), g[i].end(), x); bool findY = binary_search(g[i].begin(), g[i].end(), y); if (findX && findY) { z = i; break; } else if (findX) { xReach.push_back(i); } } if (z < 0) { z = -1; for (int i : xReach) { for (int j : g[i]) { if (j == x || j == 0 || binary_search(xReach.begin(), xReach.end(), j)) { continue; } y = j; z = i; break; } if (z >= 0) { break; } } assert(z >= 0); } cout << 5 << endl; cout << 1 << << x + 1 << << z + 1 << << y + 1 << << x + 1 << << n << endl; return 0; } } if (ans1 == INT_MAX) { cout << -1 << endl; return 0; } cout << ans1 << endl; vector<int> res; int kur = n - 1; while (kur >= 0) { res.push_back(kur + 1); kur = p[kur]; } reverse(res.begin(), res.end()); for (int i : res) { cout << i << ; } cout << endl; return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Parameter LE tells us if we are little-endian.
// Little-endian means send lower 16 bits first.
// Default is big endian (network order), send upper bits first.
module fifo19_to_fifo36
#(parameter LE=0)
(input clk, input reset, input clear,
input [18:0] f19_datain,
input f19_src_rdy_i,
output f19_dst_rdy_o,
output [35:0] f36_dataout,
output f36_src_rdy_o,
input f36_dst_rdy_i,
output [31:0] debug
);
// Shortfifo on input to guarantee no deadlock
wire [18:0] f19_data_int;
wire f19_src_rdy_int, f19_dst_rdy_int;
fifo_short #(.WIDTH(19)) head_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o),
.dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int),
.space(),.occupied() );
// Actual f19 to f36 which could deadlock if not connected to shortfifos
reg f36_sof_int, f36_eof_int;
reg [1:0] f36_occ_int;
wire [35:0] f36_data_int;
wire f36_src_rdy_int, f36_dst_rdy_int;
reg [1:0] state;
reg [15:0] dat0, dat1;
wire f19_sof_int = f19_data_int[16];
wire f19_eof_int = f19_data_int[17];
wire f19_occ_int = f19_data_int[18];
wire xfer_out = f36_src_rdy_int & f36_dst_rdy_int;
always @(posedge clk)
if(f19_src_rdy_int & ((state==0)|xfer_out))
f36_sof_int <= f19_sof_int;
always @(posedge clk)
if(f19_src_rdy_int & ((state != 2)|xfer_out))
f36_eof_int <= f19_eof_int;
always @(posedge clk)
if(reset)
begin
state <= 0;
f36_occ_int <= 0;
end
else
if(f19_src_rdy_int)
case(state)
0 :
begin
dat0 <= f19_data_int;
if(f19_eof_int)
begin
state <= 2;
f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
end
else
state <= 1;
end
1 :
begin
dat1 <= f19_data_int;
state <= 2;
if(f19_eof_int)
f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00;
end
2 :
if(xfer_out)
begin
dat0 <= f19_data_int;
if(f19_eof_int) // remain in state 2 if we are at eof
f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
else
state <= 1;
end
endcase // case(state)
else
if(xfer_out)
begin
state <= 0;
f36_occ_int <= 0;
end
assign f19_dst_rdy_int = xfer_out | (state != 2);
assign f36_data_int = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} :
{f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1};
assign f36_src_rdy_int = (state == 2);
assign debug = state;
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(36)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
.dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
.space(),.occupied() );
endmodule // fifo19_to_fifo36
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`ifdef VERILATOR
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
`else
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [60:0] p;
reg [60:0] a;
reg [20:0] b;
reg [60:0] shifted;
always @* begin
p = a[60:0] ** b[20:0];
shifted = 2 ** b[20:0];
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%0x %x %x\n", cyc, p, shifted);
`endif
// Constant versions
`checkh(61'h1 ** 21'h31, 61'h1);
`checkh(61'h2 ** 21'h10, 61'h10000);
`checkh(61'd10 ** 21'h3, 61'h3e8);
`checkh(61'h3 ** 21'h7, 61'h88b);
`ifndef VCS
`checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81);
`endif
if (cyc==1) begin
a <= 61'h0;
b <= 21'h0;
end
if (cyc==2) begin
a <= 61'h0;
b <= 21'h3;
end
if (cyc==3) begin
a <= 61'h1;
b <= 21'h31;
end
if (cyc==4) begin
a <= 61'h2;
b <= 21'h10;
end
if (cyc==5) begin
a <= 61'd10;
b <= 21'd3;
end
if (cyc==6) begin
a <= 61'd3;
b <= 21'd7;
end
if (cyc==7) begin
a <= 61'h7ab3811219;
b <= 21'ha6e30;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
case (cyc)
32'd00: ;
32'd01: ;
32'd02: ; // 0^x is indeterminate
32'd03: ; // 0^x is indeterminate
32'd04: `checkh(p, 61'h1);
32'd05: `checkh(p, 61'h10000);
32'd06: `checkh(p, 61'h3e8);
32'd07: `checkh(p, 61'h88b);
32'd08: `checkh(p, 61'h01ea58c703687e81);
32'd09: `checkh(p, 61'h01ea58c703687e81);
default: $stop;
endcase
case (cyc)
32'd00: ;
32'd01: ;
32'd02: `checkh(shifted, 61'h0000000000000001);
32'd03: `checkh(shifted, 61'h0000000000000008);
32'd04: `checkh(shifted, 61'h0002000000000000);
32'd05: `checkh(shifted, 61'h0000000000010000);
32'd06: `checkh(shifted, 61'h0000000000000008);
32'd07: `checkh(shifted, 61'h0000000000000080);
32'd08: `checkh(shifted, 61'h0000000000000000);
32'd09: `checkh(shifted, 61'h0000000000000000);
default: $stop;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); string s; cin >> s; s = 0 + s; vector<int> v(int(s.size()), 0); for (int i = int(s.size()) - 1; i >= 0; i--) { if (s[i] == 1 ) { v[i] = -1; while (s[i] != 0 ) i--; v[i] = 1; } } for (int i = 1; i < int(v.size()); i++) { if (v[i] == -1 and v[i - 1] == 1) { v[i - 1] = 0; v[i] = 1; } else if (v[i] == 1 and v[i - 1] == -1) { v[i - 1] = 0; v[i] = -1; } } int count = 0; for (int i = 0; i < int(v.size()); i++) if (v[i] != 0) count++; cout << count << endl; }
|
#include <bits/stdc++.h> const int maxn = 60; int mtx[maxn][maxn]; int n, m; bool col_ok(int a, int b) { for (int i = 0; i < n; i++) { if (mtx[i][a] != mtx[i][b]) return 0; } return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %c , &mtx[i][j]); for (int i = 0; i < n; i++) { int cmp = -1; for (int j = 0; j < m; j++) { if (mtx[i][j] == # ) { if (cmp == -1) { cmp = j; } else { if (!col_ok(cmp, j)) { printf( No n ); return 0; } } } } } printf( Yes n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; string w; for (int i = 0; i <= 2 * n - 2; i = i + 2) { w = w + s[i]; } cout << w << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O41AI_PP_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_PP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// ii2dcam.v: indirectly-indexed 2D BCAM (II2DCAM) top hierarchy //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// include config file for synthesis mode
`ifndef SIM
`include "config.vh"
`endif
module ii2dcam
#( parameter CDEP = `CDEP , // CAM depth (k-entries, power of 2)
parameter PWID = `PWID , // pattern width (9-bits multiply)
parameter PIPE = `PIPE , // pipelined?
parameter REGI = `REGI , // register inputs?
parameter REGO = `REGO ) // register outputs?
( input clk , // clock
input rst , // global reset
input wEnb , // write enable
input [`log2(CDEP)+9:0] wAddr , // write address
input [PWID*9-1:0] mPatt , // match pattern
input [PWID*9-1:0] wPatt , // write pattern
output match , // match
output [`log2(CDEP)+9:0] mAddr ); // match indicators
// register inputs
reg wEnbR ;
reg [`log2(CDEP)+9:0] wAddrR;
reg [PWID*9-1:0] mPattR;
reg [PWID*9-1:0] wPattR;
wire wEnbI ;
wire [`log2(CDEP)+9:0] wAddrI;
wire [PWID*9-1:0] mPattI;
wire [PWID*9-1:0] wPattI;
always @(posedge clk, posedge rst)
if (rst) {wEnbR,wAddrR,mPattR,wPattR} <= {(`log2(CDEP)+18*PWID+11){1'b0}};
else {wEnbR,wAddrR,mPattR,wPattR} <=
{wEnb ,wAddr ,mPatt ,wPatt } ;
assign {wEnbI,wAddrI,mPattI,wPattI} = REGI ?
{wEnbR,wAddrR,mPattR,wPattR} :
{wEnb ,wAddr ,mPatt ,wPatt } ;
// register outputs
reg matchR;
reg [`log2(CDEP)+9:0] mAddrR;
wire matchI;
wire [`log2(CDEP)+9:0] mAddrI;
always @(posedge clk, posedge rst)
if (rst) {matchR,mAddrR} <= {(`log2(CDEP)+11){1'b0}};
else {matchR,mAddrR} <=
{matchI,mAddrI} ;
assign {match ,mAddr } = REGO ?
{matchR,mAddrR} :
{matchI,mAddrI} ;
// instantiate slices of ii2dcam9b for each 9-bits of pattern
wire [CDEP*1024-1:0] mIndc_i [PWID-1:0];
genvar gi;
generate
for (gi=0 ; gi<PWID ; gi=gi+1) begin: STG
// instantiate ii2dcam9b
ii2dcam9b #( .CDEP (CDEP ), // depth (k-entries)
.PIPE (PIPE )) // pipelined?
ii2dcam9bi ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnbI ), // write enable // input
.wAddr(wAddrI ), // write address // input [`log2(DEP)+9:0]
.mPatt(mPattI[gi*9 +: 9]), // match pattern // input [8 :0]
.wPatt(wPattI[gi*9 +: 9]), // write pattern // input [8 :0]
.mIndc(mIndc_i[gi] )); // match indicators // output [DEP*1024-1:0]
end
endgenerate
// cascading by AND'ing matches
integer i;
reg [CDEP*1024-1:0] mIndc; // match one-hot
always @(*) begin
mIndc = {(CDEP*1024){1'b1}};
for (i=0; i<PWID; i=i+1)
mIndc = mIndc & mIndc_i[i];
end
// binary match (priority encoded) with CDEPx1k width
`ifdef SIM
pe_bhv #( .OHW(CDEP*1024) ) // behavioural priority encoder
`else
pe_cam // generated automatically by ./pe script
`endif
pe_cam_inst (
.clk(clk ), // clock for pipelined priority encoder
.rst(rst ), // registers reset for pipelined priority encoder
.oht(mIndc ), // one-hot match input / in : [ CDEP -1:0]
.bin(mAddrI), // first match index / out: [`log2(CDEP)-1:0]
.vld(matchI) // match indicator / out
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_4_V
`define SKY130_FD_SC_LS__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_4_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
// Internal 125 MHz clock
wire clk_dcm_out;
wire clk_int;
wire rst_int;
wire dcm_rst;
wire [7:0] dcm_status;
wire dcm_locked;
wire dcm_clkfx_stopped = dcm_status[2];
assign dcm_rst = ~reset_n | (dcm_clkfx_stopped & ~dcm_locked);
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
DCM_SP #(
.CLKIN_PERIOD(10),
.CLK_FEEDBACK("NONE"),
.CLKDV_DIVIDE(2.0),
.CLKFX_MULTIPLY(5.0),
.CLKFX_DIVIDE(4.0),
.PHASE_SHIFT(0),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.STARTUP_WAIT("FALSE"),
.CLKIN_DIVIDE_BY_2("FALSE")
)
clk_dcm_inst (
.CLKIN(clk_ibufg),
.CLKFB(1'b0),
.RST(dcm_rst),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_dcm_out),
.CLKFX180(),
.STATUS(dcm_status),
.LOCKED(dcm_locked),
.PSDONE()
);
BUFG
clk_bufg_inst (
.I(clk_dcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~dcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
/*module MUX8_1(Sel,S0,S1,S2,S3,S4,S5,S6,S7,out);
input [2:0] Sel;
input [7:0] S0,S1,S2,S3,S4,S5,S6,S7;
output [7:0]out;
assign out = (Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module MUX4_1(Sel,S0,S1,S2,S3,out);
input [1:0] Sel;
input [7:0] S0,S1,S2,S3;
output [7:0]out;
assign out = (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
*/
module Register_ShiftOutput(
input [31:0] Rt_out,
input [1:0] Mem_addr_in,
input [31:26] IR,
output [31:0] Mem_data_shift
);
wire [2:0] Rt_out_shift_ctr;
wire [31:0] Rt_out_l,Rt_out_r,Rt_out_shift;
assign Rt_out_shift_ctr[2] = (IR[31])&(!IR[30])&(IR[29])&(((!IR[28])&(IR[27])) | ((IR[27])&(!IR[26])) );
assign Rt_out_shift_ctr[1] = (IR[31])&(!IR[30])&(IR[29])&(((!IR[28])&(!IR[27])&(IR[26])) | ((IR[28])&(IR[27])&(!IR[26])));//xor better
assign Rt_out_shift_ctr[0] = (IR[31])&(!IR[30])&(IR[29])&(!IR[28])&(IR[27])&(!IR[26]);
MUX4_1 mux4_1_0(Mem_addr_in[1:0],Rt_out[31:24],8'b0,8'b0,8'b0,Rt_out_l[31:24]);
MUX4_1 mux4_1_1(Mem_addr_in[1:0],Rt_out[23:16],Rt_out[31:24],8'b0,8'b0,Rt_out_l[23:16]);
MUX4_1 mux4_1_2(Mem_addr_in[1:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],8'b0,Rt_out_l[15:8]);
MUX4_1 mux4_1_3(Mem_addr_in[1:0],Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],Rt_out_l[7:0]);
MUX4_1 mux4_1_4(Mem_addr_in[1:0],Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],Rt_out_r[31:24]);
MUX4_1 mux4_1_5(Mem_addr_in[1:0],8'b0,Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out_r[23:16]);
MUX4_1 mux4_1_6(Mem_addr_in[1:0],8'b0,8'b0,Rt_out[7:0],Rt_out[15:8],Rt_out_r[15:8]);
MUX4_1 mux4_1_7(Mem_addr_in[1:0],8'b0,8'b0,8'b0,Rt_out[7:0],Rt_out_r[7:0]);
MUX8_1 mux8_1_0(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[15:8],8'b0,Rt_out_l[31:24],Rt_out_l[31:24],Rt_out_r[31:24],8'b0,Mem_data_shift[31:24]);
MUX8_1 mux8_1_1(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[7:0],8'b0,Rt_out_l[23:16],Rt_out_l[23:16],Rt_out_r[23:16],8'b0,Mem_data_shift[23:16]);
MUX8_1 mux8_1_2(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[15:8],8'b0,Rt_out_l[15:8],Rt_out_l[15:8],Rt_out_r[15:8],8'b0,Mem_data_shift[15:8]);
MUX8_1 mux8_1_3(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[7:0],8'b0,Rt_out_l[7:0],Rt_out_l[7:0],Rt_out_r[7:0],8'b0,Mem_data_shift[7:0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { long long n, q; cin >> n >> q; while (q--) { long long x; cin >> x; long long c = 1; for (long long int i = 0; i < 63; i++) if ((x + c - 2 * n) % (2 * c) == 0) { cout << ((x + c - 2 * n) / (2 * c)) + n << n ; break; } else c *= 2; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int kocka[25] = {}; for (int i = 1; i <= 24; i++) cin >> kocka[i]; if (kocka[1] == kocka[2] && kocka[2] == kocka[3] && kocka[3] == kocka[4] && kocka[17] == kocka[18] && kocka[18] == kocka[7] && kocka[7] == kocka[8] && kocka[21] == kocka[22] && kocka[22] == kocka[19] && kocka[19] == kocka[20]) { cout << YES ; exit(0); } if (kocka[1] == kocka[2] && kocka[2] == kocka[3] && kocka[3] == kocka[4] && kocka[13] == kocka[14] && kocka[14] == kocka[7] && kocka[7] == kocka[8] && kocka[5] == kocka[6] && kocka[6] == kocka[19] && kocka[19] == kocka[20]) { cout << YES ; exit(0); } if (kocka[1] == kocka[2] && kocka[2] == kocka[17] && kocka[17] == kocka[19] && kocka[5] == kocka[6] && kocka[6] == kocka[7] && kocka[7] == kocka[8] && kocka[10] == kocka[18] && kocka[18] == kocka[9] && kocka[9] == kocka[20]) { cout << YES ; exit(0); } if (kocka[1] == kocka[2] && kocka[2] == kocka[16] && kocka[16] == kocka[14] && kocka[5] == kocka[6] && kocka[6] == kocka[7] && kocka[7] == kocka[8] && kocka[3] == kocka[18] && kocka[18] == kocka[4] && kocka[4] == kocka[20]) { cout << YES ; exit(0); } if (kocka[5] == kocka[2] && kocka[2] == kocka[7] && kocka[7] == kocka[4] && kocka[9] == kocka[6] && kocka[6] == kocka[11] && kocka[11] == kocka[8] && kocka[17] == kocka[18] && kocka[18] == kocka[19] && kocka[19] == kocka[20]) { cout << YES ; exit(0); } if (kocka[24] == kocka[2] && kocka[2] == kocka[22] && kocka[22] == kocka[4] && kocka[1] == kocka[6] && kocka[6] == kocka[3] && kocka[3] == kocka[8] && kocka[17] == kocka[18] && kocka[18] == kocka[19] && kocka[19] == kocka[20]) { cout << YES ; exit(0); } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long tests, t, qq, q, i, j, bb[200000], s1, ans[2100][2100]; long long a, b; long solve(long long a, long long b) { if (a < b) swap(a, b); if (a == 0 || b == 0) return 0; if (solve(a % b, b) == 0) return 1; t = a / b; if (b % 2 == 1) return 1 - t % 2; t %= (b + 1); if (t % 2 == 1) return 0; return 1; } int main() { long s = 0; cin >> tests; for (; tests; --tests) { cin >> a >> b; if (solve(a, b)) cout << First << endl; else cout << Second << endl; } cin.get(); cin.get(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A222OI_BEHAVIORAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire B2 nand2_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& p) { in >> p.first >> p.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> p) { out << { << p.first << , << p.second << } ; return out; } template <typename T> istream& operator>>(istream& in, vector<T>& arr) { for (auto& i : arr) { in >> i; } return in; } template <typename T> ostream& operator<<(ostream& out, vector<T> arr) { for (int64_t i = 0; i < (int64_t)arr.size() - 1; ++i) out << arr[i] << ; if (arr.size()) out << arr.back(); out << n ; return out; } int64_t get(int64_t n, int64_t k) { if (n >= 0) { return -n / k; } else { return abs(n) / k + (n % k != 0) * 1; } } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int64_t p, k; cin >> p >> k; if (p < k) { cout << 1 << n ; cout << p << n ; return 0; } vector<int64_t> ans(500000); ans[0] = -p / k; for (int64_t i = 1; i < 500000; ++i) { ans[i] = get(ans[i - 1], k); } if (ans.back() != 0) { cout << -1 << n ; return 0; } while (ans.back() == 0) ans.pop_back(); vector<int64_t> ans2(ans.size() + 1); ans2[0] = ans[0] * k + p; for (int64_t i = 1; i < ans.size(); ++i) { ans2[i] = ans[i] * k + ans[i - 1]; } ans2[ans.size()] = ans.back(); cout << ans2.size() << n ; cout << ans2 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int l1, r1, l2, r2, ans; int min(int a, int b) { return a < b ? a : b; } int max(int a, int b) { return a > b ? a : b; } int check(int a) { if (a > ans) ans = a; return a; } int solve(int l1, int r1, int l2, int r2, int k) { if (l1 == l2 && r1 == r2) { if (r1 - l1 + 1 > ans) ans = r1 - l1 + 1; return r1 - l1 + 1; } if (r1 - l1 + 1 <= ans || r2 - l2 + 1 <= ans) return 0; if (k == 0) return 0; int mid = (1 << k); if (r1 < mid && r2 < mid) return check(solve(l1, r1, l2, r2, k - 1)); if (l1 > mid && l2 > mid) return check(solve(l1 - mid, r1 - mid, l2 - mid, r2 - mid, k - 1)); if (r1 < mid && l2 > mid) return check(solve(l1, r1, l2 - mid, r2 - mid, k - 1)); if (r2 < mid && l1 > mid) return check(solve(l1 - mid, r1 - mid, l2, r2, k - 1)); if (l1 <= mid && r1 >= mid) { if (r2 < mid) return check(max(solve(l1, mid - 1, l2, r2, k - 1), solve(1, r1 - mid, l2, r2, k - 1))); if (l2 > mid) return check(max(solve(l1, mid - 1, l2 - mid, r2 - mid, k - 1), solve(1, r1 - mid, l2 - mid, r2 - mid, k - 1))); int ret = min(r1, r2) - max(l1, l2) + 1; ret = max(ret, solve(l1, mid - 1, 1, r2 - mid, k - 1)); ret = max(ret, solve(1, r1 - mid, l2, mid - 1, k - 1)); return check(ret); } if (l2 <= mid && r2 >= mid) { if (r1 < mid) return check(max(solve(l1, r1, l2, mid - 1, k - 1), solve(l1, r1, 1, r2 - mid, k - 1))); if (l1 > mid) return check(max(solve(l1 - mid, r1 - mid, l2, mid - 1, k - 1), solve(l1 - mid, r1 - mid, 1, r2 - mid, k - 1))); int ret = min(r1, r2) - max(l1, l2) + 1; ret = max(ret, solve(l1, mid - 1, 1, r2 - mid, k - 1)); ret = max(ret, solve(1, r1 - mid, l2, mid - 1, k - 1)); return check(ret); } } int main() { cin >> l1 >> r1 >> l2 >> r2; cout << solve(l1, r1, l2, r2, 29) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[5010]; int main() { scanf( %s , s); int n = (int)strlen(s); int res = 0; for (int i = 0; i < n; i++) { int mn = 0, mx = 0; for (int j = i; j < n; j++) { if (s[j] == ( ) { mn++, mx++; } else if (s[j] == ) ) { mn--, mx--; } else if (s[j] == ? ) { mn--, mx++; } if (mx < 0) break; if (mn < 0 && mn < mx) mn += 2; if (mn == 0) res++; } } printf( %d , res); return 0; }
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
/*
* the module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const_ (clk, addr, out, effective);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101, 1182'd0};
8: out <= {6'b001001, 1182'd0};
16: out <= {6'b010101, 1182'd0};
default:
begin out <= 0; effective <= 0; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_1_V
`define SKY130_FD_SC_LP__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_1_V
|
/* 2013-08-11 10:03:33.914034 */#include<iostream> #include<cstdio> #include<cstdlib> #include<ctime> #include<cmath> #include<cctype> #include<cstring> #include<algorithm> #include<map> #include<set> #include<vector> #include<string> #include<queue> using namespace std; char s[1011][1011]; bool u[1011][1011]; char c[1011][1011]; int n,m; const int dx[]={1,0,-1,0}; const int dy[]={0,1,0,-1}; inline bool fitr(int x,int y){ return s[x][y+1]== b &&s[x][y+2]== w &&!u[x][y+1]&&!u[x][y+2]; } inline bool fitc(int x,int y){ return s[x+1][y]== b &&s[x+2][y]== w &&!u[x+1][y]&&!u[x+2][y]; } char choosec(int a,int b,int ax,int ay){ int opt=0; for(int i=0;i<3;++i) { for(int k=0;k<4;++k) { int nx=a+dx[k],ny=b+dy[k]; if(nx>0&&nx<=n&&ny>0&&ny<=m) { if(c[nx][ny]!= . ) opt|=1<<(c[nx][ny]- a ); } } a+=ax,b+=ay; } for(int i=0;;++i) { if(((1<<i)&opt)==0) return i+ a ; } } int main(){ scanf( %d%d ,&n,&m); for(int i=1;i<=n;++i) { scanf( %s ,s[i]+1); for(int j=1;j<=m;++j) c[i][j]= . ; } for(int i=1;i<=n;++i) for(int j=1;j<=m;++j) if(!u[i][j]&&s[i][j]!= . ) { if(s[i][j]== b ) { printf( NO n ); return 0; } else { if(fitr(i,j)) { u[i][j]=u[i][j+1]=u[i][j+2]=1; char co=choosec(i,j,0,1); c[i][j]=c[i][j+1]=c[i][j+2]=co; } else { if(fitc(i,j)) { u[i][j]=u[i+1][j]=u[i+2][j]=1; char co=choosec(i,j,1,0); c[i][j]=c[i+1][j]=c[i+2][j]=co; } else { printf( NO n ); return 0; } } } } printf( YES n ); for(int i=1;i<=n;++i) printf( %s n ,c[i]+1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n + 5]; for (int i = 1; i <= n; i++) cin >> a[i]; int m = 1; for (int i = 2; i < n; i++) { if (abs(a[i] - a[i + 1]) < abs(a[m] - a[m + 1])) m = i; } if (abs(a[n] - a[1]) < abs(a[m] - a[m + 1])) { cout << n << << 1; } else cout << m << << m + 1 << endl; }
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct P { int x, y; bool operator<(const P &p) { if (x != p.x) return x < p.x; else return y < p.y; } }; int main() { int T; cin >> T; for (int t = 0; t < T; ++t) { int n; cin >> n; int bsz = n / 3; vector<int> buf(bsz); for (int i = 0; i < n / 3; ++i) { cout << ? << 3 * i + 1 << << 3 * i + 2 << << 3 * i + 3 << endl; cout.flush(); cin >> buf[i]; if (buf[i] == -1) { break; } } int ind0, ind1; for (int i = 0; i < bsz; ++i) { int indl = i; int indr = (i + 1) % bsz; if (buf[indl] != buf[indr]) { vector<int> tbuf(6); tbuf[0] = buf[indl]; for (int j = 1; j <= 5; ++j) { int v1 = (3 * indl + j) % n + 1; int v2 = (3 * indl + j + 1) % n + 1; int v3 = (3 * indl + j + 2) % n + 1; cout << ? << v1 << << v2 << << v3 << endl; cout.flush(); cin >> tbuf[j]; if (tbuf[j] == -1) { break; } if (tbuf[j - 1] != tbuf[j]) { if (tbuf[j - 1] == 0) { ind0 = (3 * indl + j - 1) % n + 1; ind1 = v3; } else { ind1 = (3 * indl + j - 1) % n + 1; ind0 = v3; } break; } } break; } } vector<int> mapping(n); mapping[ind1 - 1] = 1; int tmp; for (int i = 0; i < bsz; ++i) { int v1 = 3 * i + 1; int v2 = 3 * i + 2; int v3 = 3 * i + 3; if (buf[i] == 0) { if (v1 == ind1) { cout << ? << ind1 << << ind0 << << v2 << endl; } else if (v2 == ind1) { cout << ? << ind1 << << v1 << << ind0 << endl; } else { cout << ? << ind1 << << v1 << << v2 << endl; } cout.flush(); cin >> tmp; if (tmp == 0) { mapping[v1 - 1] = 0; mapping[v2 - 1] = 0; if (v3 == ind0) { tmp = 0; } else if (v3 == ind1) { tmp = 1; } else { cout << ? << ind0 << << ind1 << << v3 << endl; cout.flush(); cin >> tmp; } mapping[v3 - 1] = tmp; } else { mapping[v3 - 1] = 0; if (ind0 == v1) { tmp = 0; } else if (ind1 == v1) { tmp = 1; } else { cout << ? << ind0 << << ind1 << << v1 << endl; cout.flush(); cin >> tmp; } mapping[v1 - 1] = tmp; mapping[v2 - 1] = 1 - tmp; } } else { if (v1 == ind0) { cout << ? << ind0 << << ind1 << << v2 << endl; } else if (v2 == ind0) { cout << ? << ind0 << << v1 << << ind1 << endl; } else { cout << ? << ind0 << << v1 << << v2 << endl; } cout.flush(); cin >> tmp; if (tmp == 1) { mapping[v1 - 1] = 1; mapping[v2 - 1] = 1; if (v3 == ind0) { tmp = 0; } else if (v3 == ind1) { tmp = 1; } else { cout << ? << ind0 << << ind1 << << v3 << endl; cout.flush(); cin >> tmp; } mapping[v3 - 1] = tmp; } else { mapping[v3 - 1] = 1; if (v1 == ind0) { tmp = 0; } else if (v1 == ind1) { tmp = 1; } else { cout << ? << ind0 << << ind1 << << v1 << endl; cout.flush(); cin >> tmp; } mapping[v1 - 1] = tmp; mapping[v2 - 1] = 1 - tmp; } } } vector<int> fake; for (int i = 0; i < n; ++i) { if (mapping[i] == 0) { fake.push_back(i + 1); } } cout << ! << fake.size(); for (int i = 0; i < fake.size(); ++i) { cout << << fake[i]; } cout << endl; cout.flush(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; cin >> t; while (t--) { int n; cin >> n; for (long long int i = (long long int)0; i < (long long int)n; i++) cout << i + 1 << n [i == n - 1]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 500010; bool f[MAXN]; int main() { int n, d; scanf( %d %d , &n, &d); f[0] = 1; for (int i = 0; i < n; i++) { int x; scanf( %d , &x); for (int j = MAXN - 1 - x; j >= 0; --j) f[j + x] |= f[j]; } int r = 1, sum = 0, ans = 0; while (r < MAXN) { int next = -1; while (r <= sum + d && r < MAXN) { if (f[r]) next = r; r++; } if (next == -1) break; sum = next; ans++; } printf( %d %d n , sum, ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.12.2015 18:04:09
// Design Name:
// Module Name: product_sat
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_product_sat
#( parameter BITS_IN1 = 50,
parameter BITS_IN2 = 50,
parameter BITS_OUT = 50,
parameter SHIFT = 10
)
(
input signed [BITS_IN1-1:0] factor1_i,
input signed [BITS_IN2-1:0] factor2_i,
output signed [BITS_OUT-1:0] product_o,
output overflow
);
wire signed [BITS_IN1+BITS_IN2-1:0] product;
//assign product = factor1_i*factor2_i;
// simple saturation added:
assign product = factor1_i*factor2_i + $signed(1 <<(SHIFT-1));
assign {product_o,overflow} = ( {product[BITS_IN1+BITS_IN2-1],|product[BITS_IN1+BITS_IN2-2:SHIFT+BITS_OUT-1]} ==2'b01) ? {{1'b0,{BITS_OUT-1{1'b1}}},1'b1} : //positive overflow
( {product[BITS_IN1+BITS_IN2-1],&product[BITS_IN1+BITS_IN2-2:SHIFT+BITS_OUT-1]} ==2'b10) ? {{1'b1,{BITS_OUT-1{1'b0}}},1'b1} : //negative overflow
{product[SHIFT+BITS_OUT-1:SHIFT],1'b0} ; //correct value
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void smn(T &a, const T &b) { if (b < a) a = b; } template <class T> inline void smx(T &a, const T &b) { if (b > a) a = b; } template <class T> inline T rev(const T &a) { T _ = a; reverse(_.begin(), _.end()); return _; } const double eps = 1e-9; const long double leps = 1e-14; const int MN = 5000 + 100, MOD = 1000 * 1000 * 1000 + 7; vector<int> dis; int n; int dt[MN][MN]; pair<int, int> point[MN]; int mk = 1, now; int mark[MN]; int v[MN]; int d(pair<int, int> a, pair<int, int> b) { return abs(a.first - b.first) + abs(a.second - b.second); } void dfs(int a) { mark[a] = mk; for (int i = 0; i < n; i++) if (dt[a][i] > now && mark[i] != mk) v[i] = 1 - v[a], dfs(i); } bool av(int a) { now = a; for (int i = 0; i < n; i++) if (mark[i] != mk) v[i] = 0, dfs(i); mk++; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (dt[i][j] > now && v[i] == v[j]) return 0; return 1; } int main(int argc, char *argv[]) { ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> point[i].first >> point[i].second; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) dt[i][j] = d(point[i], point[j]); int s = 0, e = 10000; int res = 10000; while (s <= e) { int m = (s + e) / 2; if (av(m)) smn(res, m), e = m - 1; else s = m + 1; } now = res; cout << now << n ; int rn = 1; for (int i = 0; i < n; i++) if (mark[i] != mk) dfs(i), rn = (2LL * rn) % MOD; cout << rn << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, j, i, l, r, ans = 0, x, y, minimum; scanf( %d , &n); scanf( %d , &k); int count_a[n], count_b[n]; char str[n + 1], ch; scanf( %s , str); for (i = 0; i < n; i++) { count_a[i] = 0; count_b[i] = 0; } for (i = 0; i < n; i++) { if (str[i] == a ) count_a[i]++; if (str[i] == b ) count_b[i]++; } for (i = 1; i < n; i++) { count_a[i] += count_a[i - 1]; count_b[i] += count_b[i - 1]; } l = 0; r = 0; while (r < n) { if (l == 0) { x = count_a[r]; y = count_b[r]; } else { x = count_a[r] - count_a[l - 1]; y = count_b[r] - count_b[l - 1]; } minimum = min(x, y); if (k >= minimum) { ans = max(ans, r - l + 1); r++; } else l++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { string s; cin >> s; int i, k, cnt = 0; for (i = 0; i < s.length(); i++) if (s[i] != 0 ) break; k = i; for (i; i < s.length(); i++) if (s[i] == 0 ) cnt++; for (int j = s.length(); j >= k; j--) { if (s[j] == 0 ) cnt--; else if (s[j] == 1 ) break; } cout << cnt << endl; } return 0; }
|
#include<bits/stdc++.h> using namespace std; #define l1 long long void solve() { int n; cin>>n; vector<int> v(n); for(auto &i:v) cin>>i; l1 sum = 0; l1 need = 0; for(int i=0;i<n;i++) { sum+=v[i]; need+=i; if(sum<need) {cout<< NO <<endl; return;} } cout<< YES <<endl; } int main() { int t; cin>>t; while(t--) { solve(); } }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_count_to_16x(
input clk,
input rst,
input count,
output [3:0] counter_value
);
//This module counts from 0 to 16
//input clk, rst, count;
//output [3:0] counter_value;
reg [3:0] counter_value_preserver;
//assign counter_value = (count) ? counter_value_preserver + 1 : counter_value_preserver;
assign counter_value = counter_value_preserver;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
counter_value_preserver = 4'h0;
end else if ( count == 1'b1 ) begin
counter_value_preserver = counter_value_preserver + 1;
end else begin
counter_value_preserver = counter_value;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int flag[3000500]; int dp[200050]; int maxx[200050]; int ans[200050]; stack<int> st; int main() { string s; cin >> s; int n = s.size(); for (int i = 0; i < n; i++) { ans[i] = 0; if (s[i] == 1 ) st.push(i); if (s[i - 1] == 1 && s[i] == 0 ) { int j = i; while (!st.empty() && s[j] == 0 && j < n) { int temp = st.top(); st.pop(); ans[temp] = 1; j++; i = j - 1; } } } for (int i = 0; i < n; i++) cout << ans[i]; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.07.2017 13:29:14
// Design Name:
// Module Name: t_mem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_mem;
// Inputs
reg [31:0] writedata, aluresultin, pcbranch1;
reg [4:0] writereg1;
reg branch, memwrite, memtoreg1, regwrite1, zerowire, clk;
// Outputs
wire [31:0] readdata, aluresultout, pcbranch2;
wire [4:0] writereg2;
wire regwrite2, memtoreg2, pcsrc;
// Instantiate the Unit Under Test
memoryaccess uut (
.ReadDataM( readdata ), .ALUResultOut( aluresultout ), .PCBranchM2( pcbranch2 ),
.WriteRegM2( writereg2 ),
.RegWriteM2( regwrite2 ), .MemToRegM2( memtoreg2 ), .PCSrcM( pcsrc ),
.WriteDataM( writedata ), .ALUResultIn( aluresultin ), .PCBranchM1( pcbranch1 ),
.WriteRegM1( writereg1 ),
.BranchM( branch ), .MemWriteM( memwrite ), .MemToRegM1( memtoreg1 ),
.RegWriteM1( regwrite1 ),
.ZerowireM( zerowire ), .clk( clk )
);
// Intialise the clock
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
// Initialise inputs
writedata = 0; aluresultin = 0; pcbranch1 = 0;
writereg1 = 0;
branch = 0; memwrite = 0; memtoreg1 = 0; regwrite1 = 0; zerowire = 0; clk = 0;
// Wait 100 ns for global resets
#100;
// Test zerowire + branch and PCBranch
#10 zerowire = 0; branch = 0; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 0; branch = 1; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 1; branch = 0; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 1; branch = 1; pcbranch1 = 32'h00000008; //expected output pcsrc = 1; pcbranch2 = 32'h00000008;
// Test ALUResultIn for when MemWrite = 0 and MemWrite = 1;
#20 aluresultin = 32'h00000001; memwrite = 1; writedata = 32'hFFFFFFFF;
// expected output aluresultout = 32'h00000001; dmem stores value FFFFFFFF into address 32'h00000001
#20 aluresultin = 32'h00000001; memwrite = 0; writedata = 32'hAAAAAAAA; // expected output aluresultout = 32'h00000001; readdata = 32'hFFFFFFFF;
// Test read function of dmem
// Test follow-through signals
#20 writereg1 = 5'b01000; memtoreg1 = 1; regwrite1 = 1; // expected output writereg2 = 5'b01000; memtoreg2 = 1; regwrite2 = 1;
#20 writereg1 = 5'b01001; memtoreg1 = 0; regwrite1 = 0; // expected output writereg2 = 5'b01001; memtoreg2 = 0; regwrite2 = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e6; const int inf = (int)2e9; const double eps = 1e-9; const int mod = (int)1e9 + 7; int n, l, x, y, a[maxn], ok1, ok2; map<int, int> was; bool check(int v) { if (v >= 0 && v <= l && (was.count(v - x) || was.count(v + x) || ok1) && (ok2 || was.count(v - y) || was.count(v + y))) return true; return false; } int main() { scanf( %d%d%d%d , &n, &l, &x, &y); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); if (was.count(a[i] - x)) ok1 = true; if (was.count(a[i] - y)) ok2 = true; was[a[i]] = true; } if (ok1 && ok2) { puts( 0 ); return 0; } for (int i = 1; i <= n; ++i) { if (check(a[i] - x)) { puts( 1 ); cout << a[i] - x << n ; return 0; } if (check(a[i] - y)) { puts( 1 ); cout << a[i] - y << n ; return 0; } if (check(a[i] + x)) { puts( 1 ); cout << a[i] + x << n ; return 0; } if (check(a[i] + y)) { puts( 1 ); cout << a[i] + y << n ; return 0; } } puts( 2 ); cout << x << << y << n ; return 0; }
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
input din_update,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
miso_d = data_q[7];
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (din_update) begin
data_d = din;
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.