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#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); } map<int, int> mpi; map<string, int> mps; map<int, vector<int> > path; map<int, int> visited; set<int> st; vector<int> v; map<int, int>::iterator iti; map<string, int>::iterator its; set<int>::iterator sit; vector<int>::iterator itv; void fresh() { mpi.clear(); mps.clear(); st.clear(); v.clear(); path.clear(); visited.clear(); } int main() { fast(); int n, a, b, c, d, x1, x2, y1, y2; int tst; cin >> tst; while (tst--) { cin >> n >> a >> b >> c >> d; bool flag = false; for (int i = c - d; i <= c + d; i++) { if ((i / n) >= (a - b) && (i / n) <= (a + b)) { int x = ceil((float)i / (float)n); if (x >= (a - b) && x <= (a + b)) { flag = true; break; } } } if (flag) { cout << YES << endl; ; } else cout << NO << endl; ; } return 0; }
|
module salu_tb();
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value;
reg[5:0] issue_wfid;
reg[11:0] issue_source_reg1, issue_source_reg2, issue_dest_reg;
reg[15:0] issue_imm_value;
reg[31:0] exec_rd_m0_value, issue_instr_pc, issue_opcode;
reg[63:0] sgpr_source2_data, sgpr_source1_data,
exec_rd_exec_value, exec_rd_vcc_value;
wire exec_wr_exec_en, exec_wr_vcc_en, exec_wr_m0_en, exec_wr_scc_en,
exec_wr_scc_value, exec_rd_en, issue_alu_ready, sgpr_instr_done,
fetchwaveissue_branch_en, fetchwaveissue_branch_taken,
tracemon_exec_word_sel, tracemon_vcc_word_sel;
wire [1:0] sgpr_dest_wr_en;
wire[5:0] exec_wr_wfid, exec_rd_wfid, sgpr_instr_done_wfid,
fetchwaveissue_branch_wfid;
wire[8:0] sgpr_dest_addr, sgpr_source2_addr, sgpr_source1_addr;
wire[31:0] exec_wr_m0_value, fetch_branch_pc_value, tracemon_retire_pc;
wire[63:0] exec_wr_exec_value, exec_wr_vcc_value, sgpr_dest_data;
salu salu_dut(
issue_source_reg1,
issue_source_reg2,
issue_dest_reg,
issue_imm_value,
issue_opcode,
issue_wfid,
issue_alu_select,
exec_rd_exec_value,
exec_rd_vcc_value,
exec_rd_m0_value,
exec_rd_scc_value,
sgpr_source2_data,
sgpr_source1_data,
issue_instr_pc,
exec_wr_exec_en,
exec_wr_vcc_en,
exec_wr_m0_en,
exec_wr_scc_en,
exec_wr_exec_value,
exec_wr_vcc_value,
exec_wr_m0_value,
exec_wr_scc_value,
exec_wr_wfid,
exec_rd_en,
exec_rd_wfid,
sgpr_dest_data,
sgpr_dest_addr,
sgpr_dest_wr_en,
sgpr_source2_addr,
sgpr_source1_addr,
issue_alu_ready,
sgpr_instr_done_wfid,
sgpr_instr_done,
fetchwaveissue_branch_wfid,
fetchwaveissue_branch_en,
fetchwaveissue_branch_taken,
fetch_branch_pc_value,
tracemon_retire_pc,
tracemon_exec_word_sel,
tracemon_vcc_word_sel,
clk,
rst
);
initial
begin
clk = 0;
#1 rst = 1;
#30 rst = 0;
end
initial begin
while (1) begin
#5;
clk = ~clk;
end
end
initial begin
issue_alu_select = 1'b0;
issue_source_reg1 = 12'd0;
issue_source_reg2 = 12'd0;
issue_dest_reg = 12'd0;
issue_imm_value = 16'd0;
issue_opcode = 16'd0;
issue_wfid = 6'd0;
exec_rd_exec_value = 64'd0;
exec_rd_vcc_value = 64'd0;
sgpr_source2_data = 32'd0;
sgpr_source1_data = 32'd0;
issue_instr_pc = 32'd0;
// salu 32 op with reg
#40;
issue_source_reg1 = 12'b110000000001;
issue_source_reg2 = 12'b110000000010;
issue_dest_reg = 12'b110000000110;
issue_imm_value = 16'd0;
issue_opcode = 32'h08000002;
issue_wfid = 6'd2;
issue_alu_select = 1'b1;
exec_rd_exec_value = 64'h8888888844444444;
exec_rd_vcc_value = 64'h2222222211111111;
sgpr_source2_data = 64'hxxxxxxxx00001106;
sgpr_source1_data = 64'hxxxxxxxx00000102;
issue_instr_pc = 32'd64;
// salu 64 op with reg
#10;
issue_source_reg1 = 12'b110000000001;
issue_source_reg2 = 12'b110000000010;
issue_dest_reg = 12'b110000000110;
issue_imm_value = 16'd0;
issue_opcode = 32'h0800000F;
issue_wfid = 6'd2;
issue_alu_select = 1'b1;
exec_rd_exec_value = 64'h8888888844444444;
exec_rd_vcc_value = 64'h2222222211111111;
sgpr_source2_data = 64'h7777777700001106;
sgpr_source1_data = 64'h6666666600000102;
issue_instr_pc = 32'd64;
// salu op with exec and vcc
#10;
issue_source_reg1 = 12'b111000000001;
issue_source_reg2 = 12'b111000000010;
issue_dest_reg = 12'b111000001000;
issue_imm_value = 16'd0;
issue_opcode = 32'h08000007;
issue_wfid = 6'd2;
issue_alu_select = 1'b1;
exec_rd_exec_value = 64'h8888888844444444;
exec_rd_vcc_value = 64'h2222222211111111;
sgpr_source2_data = 64'h7777777700001106;
sgpr_source1_data = 64'h6666666600000102;
issue_instr_pc = 32'd64;
// branch
#10;
issue_source_reg1 = 12'b111000000001;
issue_source_reg2 = 12'b111000000010;
issue_dest_reg = 12'b011000001000;
issue_imm_value = 16'd10;
issue_opcode = 32'h01000002;
issue_wfid = 6'd2;
issue_alu_select = 1'b1;
exec_rd_exec_value = 64'h8888888844444444;
exec_rd_vcc_value = 64'h2222222211111111;
sgpr_source2_data = 64'h7777777700001106;
sgpr_source1_data = 64'h6666666600000102;
issue_instr_pc = 32'd64;
// branch on vccz
#10;
issue_source_reg1 = 12'b111000000001;
issue_source_reg2 = 12'b111000000010;
issue_dest_reg = 12'b011000001000;
issue_imm_value = 16'd10;
issue_opcode = 32'h01000006;
issue_wfid = 6'd2;
issue_alu_select = 1'b1;
exec_rd_exec_value = 64'h8888888844444444;
exec_rd_vcc_value = 64'h0000000000000000;
sgpr_source2_data = 64'h7777777700001106;
sgpr_source1_data = 64'h6666666600000102;
issue_instr_pc = 32'd64;
#10;
issue_alu_select = 1'b0;
end
initial begin
#150;
$finish;
end
always@(posedge clk)
begin
if(sgpr_dest_wr_en)
$display("SGPR: TIME: %g SGPR_DEST_EN = %b SGPR_DONE_WFID: %h SGPR_DST_REG: %h SGPR_DST_DATA: %h RETIRE_PC: %h",
$time, sgpr_dest_wr_en, sgpr_instr_done_wfid,
sgpr_dest_addr, sgpr_dest_data, tracemon_retire_pc);
if(exec_wr_scc_en)
$display("SCC : TIME: %g SCC_WR_EN = %b SCC_WR_WFID: %h SCC_VALUE: %b RETIRE_PC: %h",
$time, exec_wr_scc_en, exec_wr_wfid,
exec_wr_scc_value, tracemon_retire_pc);
if(exec_wr_exec_en)
$display("EXEC: TIME: %g EXEC_WR_EN = %b EXEC_WR_WFID: %h EXEC_VALUE: %h RETIRE_PC: %h",
$time, exec_wr_exec_en, exec_wr_wfid,
exec_wr_exec_value, tracemon_retire_pc);
if(exec_wr_vcc_en)
$display("VCC : TIME: %g VCC_WR_EN = %b VCC_WR_WFID: %h VCC_VALUE: %h RETIRE_PC: %h",
$time, exec_wr_vcc_en, exec_wr_wfid,
exec_wr_vcc_value, tracemon_retire_pc);
if(fetchwaveissue_branch_en)
$display("BRH : TIME: %g BRANCH_EN = %b BRANCH_TK = %b BRANCH_WFID: %h NEW_PC: %h RETIRE_PC: %h",
$time, fetchwaveissue_branch_en, fetchwaveissue_branch_taken,
fetchwaveissue_branch_wfid, fetch_branch_pc_value, tracemon_retire_pc);
if(sgpr_dest_wr_en | exec_wr_scc_en | exec_wr_exec_en |
exec_wr_vcc_en | fetchwaveissue_branch_en)
$display("");
end
endmodule
|
`timescale 1ns/1ns
module sigma_delta
(input c_mod, // modulation clock
input mod_bit, // data bit from the modulator
input c, // the clock for the rest of the chip
input invert,
output [15:0] raw_d, // raw ADC word
output raw_dv,
output [15:0] d, // filtered ADC word (dumb for now)
output dv);
wire mod_bit_s; // synchronized modulator bit
sync mod_sync(.in(mod_bit), .clk(c_mod), .out(mod_bit_s));
wire invert_modclk;
sync invert_sync(.in(invert), .clk(c_mod), .out(invert_modclk));
// let's use a decimation ratio of 32 for now. This will give 11.4 ENOB
// and a settling time of 2.4 usec.
localparam W = 16;
localparam DECIM = 32;
wire [W-1:0] i0, i1, i2; // integrators
r #(W) int_0(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i0 + mod_bit_s), .q(i0));
r #(W) int_1(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i0 + i1), .q(i1));
r #(W) int_2(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i1 + i2), .q(i2));
wire dec_match;
wire [7:0] dec_cnt;
r #(8) dec_cnt_r
(.c(c_mod), .rst(dec_match), .en(1'b1), .d(dec_cnt + 1'b1), .q(dec_cnt));
assign dec_match = dec_cnt == DECIM-1; //8'd3; //8'd31; // decimate by 32
wire [W-1:0] decim; // the simplest decimator possible
r #(W) decim_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(i2), .q(decim));
// now the differentiators
wire [W-1:0] d0, d1, d2;
wire [W-1:0] diff_0 = decim - d0;
wire [W-1:0] diff_1 = diff_0 - d1;
wire [W-1:0] diff_2 = diff_1 - d2;
r #(W) d0_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(decim), .q(d0));
r #(W) d1_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(diff_0), .q(d1));
r #(W) d2_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(diff_1), .q(d2));
wire raw_dv_d1;
d1 raw_dv_d1_r(.c(c_mod), .d(dec_match), .q(raw_dv_d1));
// delay things one clock cycle in order to meet timing
wire [15:0] raw_d_modclk; // data word, in the modulation-clock domain
wire raw_dv_modclk;
d1 #(16) raw_d_d1_r(.c(c_mod),
.d(invert_modclk ? 16'd32767 - diff_2 : diff_2),
.q(raw_d_modclk));
d1 raw_dv_d2_r(.c(c_mod), .d(raw_dv_d1), .q(raw_dv_modclk));
// clock it up to the rest of the logic speed
sync #(16) raw_d_s(.in(raw_d_modclk), .clk(c), .out(raw_d));
wire raw_dv_slow; // this signal will be synchronized to "c" but is high too long
sync #(.W(1), .S(3)) raw_dv_s(.in(raw_dv_modclk), .clk(c), .out(raw_dv_slow));
wire raw_dv_slow_d1;
d1 raw_dv_slow_d1_r(.c(c), .d(raw_dv_slow), .q(raw_dv_slow_d1));
assign raw_dv = raw_dv_slow & ~raw_dv_slow_d1; // high for only one cycle
//////////////////////////////////////
// now, implement a dumb placeholder filter. maybe in the future do something
// more sophisticated, but for now just average x32 to make a 19.531 kHz
// stream for feeding PWM
wire [4:0] sample_cnt;
r #(5) sample_cnt_r
(.c(c_mod), .en(raw_dv_modclk), .rst(1'b0),
.d(sample_cnt + 1'b1), .q(sample_cnt));
wire raw_dv_modclk_d1;
d1 raw_dv_modclk_d1_r(.c(c_mod), .d(raw_dv_modclk), .q(raw_dv_modclk_d1));
wire [21:0] accum_d, accum;
wire accum_en, accum_rst;
r #(22) accum_r
(.c(c_mod), .d(accum_d), .rst(accum_rst), .en(raw_dv_modclk), .q(accum));
assign accum_d = accum + {5'h0, raw_d};
assign accum_rst = sample_cnt == 5'h00 & raw_dv_modclk_d1;
wire [21:0] last_accum;
r #(22) last_accum_r
(.c(c_mod), .rst(1'b0), .en(accum_rst), .d(accum), .q(last_accum));
wire [15:0] filtered_modclk = last_accum[20:5]; // in the c_mod domain
wire filtered_dv_modclk;
d1 filtered_dv_d1_r(.c(c_mod), .d(accum_rst), .q(filtered_dv_modclk));
// clock it up to the rest of the logic speed
sync #(16) d_s(.in(filtered_modclk), .clk(c), .out(d));
wire dv_slow; // this signal will be synchronized to "c" but is high too long
sync #(.W(1), .S(3)) dv_s(.in(filtered_dv_modclk), .clk(c), .out(dv_slow));
wire dv_slow_d1;
d1 dv_slow_d1_r(.c(c), .d(dv_slow), .q(dv_slow_d1));
assign dv = dv_slow & ~dv_slow_d1; // high for only one cycle
endmodule
`ifdef test_sigma_delta
module sigma_delta_tb();
wire c, c_mod;
sim_clk #(20) clk_20(c_mod);
sim_clk #(125) clk_125(c);
wire [2:0] hi, lo;
wire [15:0] sd_d;
reg [1:0] all_bits [3999:0];
wire sd_dv;
reg mod_bit;
reg invert;
sigma_delta sd_inst
(.c_mod(c_mod), .c(c), .invert(invert), .mod_bit(mod_bit), .d(sd_d), .dv(sd_dv));
integer i;
initial begin
$readmemh("sigma_delta_test_data.txt", all_bits, 0, 3999);
$dumpfile("sigma_delta.lxt");
$dumpvars();
mod_bit = 1'b0;
invert = 1'b0;
for (i = 0; i < 4000; i = i + 1) begin
wait(c_mod);
wait(~c_mod);
mod_bit = all_bits[i][0];
end
$finish();
end
endmodule
`endif
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: phd_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module phd_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/phd_new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/phd_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/phd_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module nh_lcd_command (
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output reg [7:0] o_cmd_data,
input i_enable,
input i_cmd_parameter,
output reg o_cmd_finished,
//Physical Signals
output o_cmd_mode,
output reg o_write,
output reg o_read,
output reg [7:0] o_data_out,
input [7:0] i_data_in,
output reg o_data_out_en
);
//Local Parameters
localparam IDLE = 4'h0;
localparam READ_WAIT = 4'h1;
localparam FINISHED = 4'h2;
//Registers/Wires
reg [3:0] state;
//Submodules
//Asynchronous Logic
assign o_cmd_mode = i_cmd_parameter;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_data_out_en <= 0;
o_data_out <= 0;
o_cmd_finished <= 0;
o_cmd_data <= 0;
o_write <= 0;
o_read <= 0;
end
else begin
//Strobes
o_cmd_finished <= 0;
//State Machine
case (state)
IDLE: begin
o_write <= 0;
o_read <= 0;
o_data_out_en <= 0;
if (i_cmd_write_stb) begin
//Change the bus to an output
o_data_out_en <= 1;
//Put the data on the bus
o_data_out <= i_cmd_data;
o_write <= 1;
state <= FINISHED;
end
else if (i_cmd_read_stb) begin
//Change the bus to an input
o_data_out_en <= 0;
o_read <= 1;
state <= READ_WAIT;
end
end
READ_WAIT: begin
state <= FINISHED;
end
FINISHED: begin
o_write <= 0;
o_read <= 0;
if (!o_data_out_en) begin
//XXX: The appliction note doesn't describe how to explicitly read
//and the protocol is different from the 8080 MCU interface
o_cmd_data <= i_data_in;
end
o_cmd_finished <= 1;
state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300010; int t, n, x[N], y[N]; long long a[N], val[N]; int main() { cin >> t; while (t--) { scanf( %d , &n); long long sum = 0; for (int i = 1; i <= n; ++i) { scanf( %lld , a + i); sum += a[i]; } if (sum % n) { puts( -1 ); continue; } sum /= n; int m = 0; for (int i = 2; i <= n; ++i) { long long req = a[i] % i; if (req) { req = i - req, ++m; x[m] = 1, y[m] = i, val[m] = req; a[1] -= req, a[i] += req; } ++m; x[m] = i, y[m] = 1, val[m] = a[i] / i; a[1] += a[i], a[i] = 0; } for (int i = 2; i <= n; ++i) { ++m; x[m] = 1, y[m] = i, val[m] = sum; a[1] -= sum, a[i] += sum; } printf( %d n , m); for (int i = 1; i <= m; ++i) printf( %d %d %lld n , x[i], y[i], val[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 105; int v[N], ans[N]; int main() { cin.tie(0), ios_base::sync_with_stdio(false); int n, k, s = 0; cin >> n >> k; for (int i = 0; i < n; i++) cin >> v[i], s += v[i], ans[i % k] += v[i]; int tans = 0; for (int i = 0; i < k; i++) tans = max(tans, abs(s - ans[i])); cout << tans << n ; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:15:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_0/system_auto_us_0_stub.v
// Design : system_auto_us_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen,
m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion,
m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp,
m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long p, long long n) { if (n == 0) return 1; if (n % 2 == 1) return (p * powmod(p, n - 1)) % 1000000007; long long z = powmod(p, n / 2); return (z * z) % 1000000007; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long x, n; cin >> x >> n; set<long long> P; for (long long i = 2; i < 100000 && x > 1; ++i) { while (x % i == 0) { P.insert(i); x /= i; } } if (x > 1) P.insert(x); long long ans = 1; for (long long p : P) { long long a = 0; long long b = n; while (b) { b /= p; a += b; a %= (1000000007 - 1); } ans *= powmod(p, a); ans %= 1000000007; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k; long long num[5005], sum[5005], dp[5005][5005]; int main() { int i, j; while (scanf( %d%d%d , &n, &m, &k) != EOF) { for (i = 0; i < n; i++) { scanf( %I64d , &num[i]); } memset(sum, 0, sizeof(sum)); for (i = 0; i <= m - 1; i++) { sum[0] += num[i]; } for (i = 1; i + m <= n; i++) { sum[i] = sum[i - 1]; sum[i] -= num[i - 1]; sum[i] += num[i + m - 1]; } memset(dp, 0, sizeof(dp)); for (j = 1; j <= k; j++) { for (i = n - m * j; i >= 0; i--) { dp[i][j] = max(dp[i + 1][j], dp[i + m][j - 1] + sum[i]); } } long long res = 0; for (i = 0; i <= n - m * k; i++) { res = max(dp[i][k], res); } cout << res << endl; } return 0; }
|
`default_nettype none
module main (input sysclk,
input clk,
input rst,
output c0,
output c1,
output c2,
output c3,
output c4,
output c5,
output c6,
output c7);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(clk),
.D_IN_0(clk2)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(rst),
.D_IN_0(rst2)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign rst_in = ~rst2;
assign sw = ~clk2;
debounce d1 (
.clk(sysclk),
.sw_in(sw),
.sw_out(clk_in)
);
//-- Counter with asynchronous reset
reg [7:0] counter;
always @(posedge clk_in or posedge rst_in) begin
if (rst_in==1'b1)
counter <= 7'b0;
else
counter <= counter + 1;
end
//-- Output the counter's bits
assign c0 = counter[0];
assign c1 = counter[1];
assign c2 = counter[2];
assign c3 = counter[3];
assign c4 = counter[4];
assign c5 = counter[5];
assign c6 = counter[6];
assign c7 = counter[7];
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1e5 + 9, maxV = 536, MOD = 1e9 + 7, AND = (1 << 20) - 1, lg = 21; vector<int> farg[maxN], adj[maxN], adjc[maxN], elems[maxN]; int incom[maxN], comp[maxN], idx; set<pair<int, int> > mys; stack<int> stc; bool vi[maxN]; void dfs(int nd) { if (vi[nd]) return; vi[nd] = 1; for (int sn : adj[nd]) dfs(sn); stc.push(nd); } void sfd(int nd) { if (vi[nd]) return; vi[nd] = 1; for (int sn : farg[nd]) sfd(sn); comp[nd] = idx; elems[idx].push_back(nd); } bool makeQuery(int a, int b) { cout << ? << a + 1 << << b + 1 << n ; cout.flush(); int ans; cin >> ans; return ans == 1; } void procesavec(vector<int> &one, vector<int> &two) { while (one.size() && two.size()) { if (makeQuery(one.back(), two.back())) { two.pop_back(); } else { one.pop_back(); } } } int n, m; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int u, v, i = 0; i < m; i++) { cin >> u >> v; u--; v--; adj[u].push_back(v); farg[v].push_back(u); } for (int i = 0; i < n; i++) dfs(i); memset(vi, 0, sizeof vi); while (stc.size()) { while (stc.size() && vi[stc.top()]) stc.pop(); if (stc.empty()) break; sfd(stc.top()); idx++; } for (int i = 0; i < n; i++) { for (int to : adj[i]) { if (comp[to] == comp[i]) continue; incom[comp[to]]++; adjc[comp[i]].push_back(comp[to]); } } for (int i = 0; i < idx; i++) { mys.insert(pair<int, int>(incom[i], i)); } int nd = mys.begin()->second; mys.erase(mys.begin()); while (mys.size() && mys.begin()->first == 0) { int frontup = mys.begin()->second; mys.erase(pair<int, int>(incom[frontup], frontup)); procesavec(elems[nd], elems[frontup]); if (elems[nd].empty()) swap(nd, frontup); for (int cmp : adjc[frontup]) { mys.erase(pair<int, int>(incom[cmp]--, cmp)); mys.insert(pair<int, int>(incom[cmp], cmp)); } } cout << ! << elems[nd].back() + 1 << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_LP_V
`define SKY130_FD_SC_LP__EINVP_LP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_lp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_lp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_LP_V
|
/*
* Front-end instruction pre-fetch unit with umi master interface
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_front_prefetch_umi (
// common signals
input clk,
input rst,
// UMI master interface - fetch
output [19:0] umi_adr_o,
input [15:0] umi_dat_i,
output reg umi_stb_o,
output umi_by_o,
input umi_ack_i,
// Invalidate current fetch cycle
input flush,
// Address stearing from back-end
input load_cs_ip,
input [15:0] requested_cs,
input [15:0] requested_ip,
// Output to instruction fifo stage
output reg [15:0] cs,
output reg [15:0] ip,
output reg [15:0] fifo_dat_o,
output reg wr_fifo,
input fifo_full
);
// Registers and nets
wire stalled;
// Continuous assignments
// The flush, load_cs_ip and fifo_full signals will cause the fetch to be stalled
// Any other time, it should be ok to start another fetch cycle
assign stalled = flush || load_cs_ip || fifo_full;
// Calculate address for wb_adr_o
assign umi_adr_o = (cs << 4) + ip;
// We are always fetching two bytes at a time
assign umi_by_o = 1'b0;
// behaviour
// cs and ip logic
always @(posedge clk)
if (rst) begin
cs <= 16'hf000;
ip <= 16'hfff0;
end
else begin
if (flush) begin
cs <= requested_cs;
ip <= requested_ip;
end
else if (load_cs_ip) begin
cs <= requested_cs;
ip <= requested_ip;
end
else if (!stalled & umi_ack_i)
ip <= ip + 2;
end
// wb_stb_o
// When a stall condition is encountered at or during wb strobe,
// follow through until wishbone cycle completes. This essentially forces one
// complete wb cycle before the stall condition is acknowledge.
always @(posedge clk)
if (rst) umi_stb_o <= 1'b0;
else umi_stb_o <= !stalled ? 1'b1 : (umi_ack_i ? 1'b0 : umi_stb_o);
// write fifo
always @(posedge clk)
if (rst) wr_fifo <= 1'b0;
else wr_fifo <= (!stalled & umi_ack_i);
// Pass wishbone data to fifo
always @(posedge clk)
if (rst) wr_fifo <= 1'b0;
else fifo_dat_o <= umi_dat_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 55; const int maxm = 2e4 + 5; int a[maxn][maxm], dp[maxm], nxt[maxm], sum[maxn][maxm]; int pre[maxm], suff[maxm]; int n, m, k; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m >> k; for (int i = 0; i <= n - 1; i++) for (int j = 0; j <= m - 1; j++) cin >> a[i][j]; for (int i = 0; i <= n - 1; i++) for (int j = 0; j <= k - 1; j++) sum[i][0] += a[i][j]; for (int i = 0; i <= n - 1; i++) for (int j = 1; j <= m - k; j++) sum[i][j] = sum[i][j - 1] + a[i][j + k - 1] - a[i][j - 1]; for (int i = 0; i <= m - k; i++) nxt[i] = sum[0][i] + sum[1][i]; for (int i = 1; i <= n - 1; i++) { for (int j = 0; j <= m - k; j++) dp[j] = nxt[j], nxt[j] = 0; pre[0] = dp[0]; for (int i = 1; i <= m - k; i++) pre[i] = max(pre[i - 1], dp[i]); suff[m - k] = dp[m - k]; for (int i = m - k - 1; i >= 0; i--) suff[i] = max(suff[i + 1], dp[i]); for (int j = 0; j <= m - k; j++) { if (j - k >= 0) nxt[j] = max(pre[j - k], nxt[j]); if (j + k <= m - k) nxt[j] = max(suff[j + k], nxt[j]); } int tmp = 0; deque<pair<int, int> > que; for (int j = 0; j <= m - k; j++) { int now = dp[j] - tmp - sum[i][j]; while (que.size() && que.front().first < now) que.pop_front(); que.push_front(pair<int, int>(now, j)); if (j - k >= 0 && que.size() && que.back().second == j - k) que.pop_back(); nxt[j] = max(nxt[j], que.back().first + tmp); tmp += a[i][j]; } tmp = 0; que.clear(); for (int j = m - k; j >= 0; j--) { int now = dp[j] - tmp - sum[i][j]; while (que.size() && que.front().first < now) que.pop_front(); que.push_front(pair<int, int>(now, j)); if (j + k <= m - k && que.size() && que.back().second == j + k) que.pop_back(); nxt[j] = max(nxt[j], que.back().first + tmp); tmp += a[i][j + k - 1]; } for (int j = 0; j <= m - k; j++) nxt[j] += sum[i][j] + sum[i + 1][j]; } int res = 0; for (int i = 0; i <= m - k; i++) res = max(res, nxt[i]); cout << res << n ; }
|
// -*- Mode: Verilog -*-
// Filename : wb_ram_xilinx_bank.v
// Description : Bank of Xilinx BRAMs
// Author : Philip Tracton
// Created On : Tue Jan 3 15:24:54 2017
// Last Modified By: Philip Tracton
// Last Modified On: Tue Jan 3 15:24:54 2017
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_ram_xilinx_bank (/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rst, we, din, waddr, raddr, bank_select
) ;
input clk;
input rst;
input [3:0] we;
input [31:0] din;
input [15:0] waddr;
input [15:0] raddr;
input wire bank_select;
output wire [31:0] dout;
//
// Select the correct address, any write means use waddr
//
wire [14:0] address = (|we & bank_select) ? waddr : raddr;
//
// RAMS always enabled
//
wire [3:0] enable = {4{bank_select}};
`ifndef XILINX_RAMB16_S9
//
// RAMS -- the RAMB16_S9 is lifted from ISE
//
RAMB16_S9 ram0(
.DO(dout[7:0]),
.DOP(),
.ADDR(address[10:0]),
.CLK(clk),
.DI(din[7:0]),
.DIP(1'b0),
.EN(enable[0]),
.SSR(rst),
.WE(we[0])
);
RAMB16_S9 ram1(
.DO(dout[15:8]),
.DOP(),
.ADDR(address[10:0]),
.CLK(clk),
.DI(din[15:8]),
.DIP(1'b0),
.EN(enable[1]),
.SSR(rst),
.WE(we[1])
);
RAMB16_S9 ram2(
.DO(dout[23:16]),
.DOP(),
.ADDR(address[10:0]),
.CLK(clk),
.DI(din[23:16]),
.DIP(1'b0),
.EN(enable[2]),
.SSR(rst),
.WE(we[2])
);
RAMB16_S9 ram3(
.DO(dout[31:24]),
.DOP(),
.ADDR(address[10:0]),
.CLK(clk),
.DI(din[31:24]),
.DIP(1'b0),
.EN(enable[3]),
.SSR(rst),
.WE(we[3])
);
`else // !`ifdef XILINX_RAMB16_S9
wire VSS = 1'b0;
wire VDD = 1'b1;
RAMB36E1 #(.READ_WIDTH_A(36), .RAM_MODE(SDP))
ram0(
.CASCADEOUTA(),
.CASCADEOUTB(),
.DBITERR(VSS),
.DOADO(dout),
.DOBDO(),
.DOPADOP(),
.DOPBDOP(),
.ECCPARITY(),
.RDADDRECC(),
.SBITERR(),
.ADDRARDADDR(),
.ADDRBWRADDR(),
.CASCADEINA(),
.CASCADEINB(),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DIADI(din),
.DIBDI(),
.DIPADIP(),
.DIPBDIP(),
.ENARDEN(VDD),
.ENBWREN(VSS),
.INJECTDBITERR(VSS),
.INJECTSBITERR(VSS),
.REGCEAREGCE(VSS),
.REGCEB(VSS),
.RSTRAMARSTRAM(rst),
.RSTRAMB(rst),
.RSTREGARSTREG(rst),
.RSTREGB(rst),
.WEA(we),
.WEBWE({8{VSS}})
);
`endif // !`ifdef XILINX_RAMB16_S9
endmodule // wb_ram_xilinx_bank
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, k, p, x, y; cin >> n >> k >> p >> x >> y; vector<int> a(n); int sum = 0; for (int i = 0; i < k; i++) { cin >> a[i]; sum += a[i]; } if (sum + n - k > x) { cout << -1 << n ; exit(0); } x -= sum; for (int i = k; i < n; i++) { if (y + n - 1 - i <= x) { a[i] = y; x -= y; } else { a[i] = 1; x -= 1; } } vector<int> b = a; sort(b.begin(), b.end()); if (b[n >> 1] >= y) { for (int i = k; i < n; i++) { cout << a[i] << ; } cout << n ; } else { cout << -1 << n ; } return 0; }
|
module dispatcher_wrapper (/*AUTOARG*/
// Outputs
dispatch2cu_wf_dispatch, dispatch2cu_wg_wf_count,
dispatch2cu_wf_size_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_vgpr_base_dispatch, dispatch2cu_wf_tag_dispatch,
dispatch2cu_lds_base_dispatch, dispatch2cu_start_pc_dispatch,
ldssize_out, vregsize_out, sregsize_out,
// Inputs
cu2dispatch_wf_done, cu2dispatch_wf_tag_done, clk, rst
) ;
parameter NUMOFCU = 1;
localparam CU_ID_WIDTH = 2;
output [(NUMOFCU-1):0] dispatch2cu_wf_dispatch;
output [3:0] dispatch2cu_wg_wf_count;
output [5:0] dispatch2cu_wf_size_dispatch;
output [8:0] dispatch2cu_sgpr_base_dispatch;
output [9:0] dispatch2cu_vgpr_base_dispatch;
output [14:0] dispatch2cu_wf_tag_dispatch;
output [15:0] dispatch2cu_lds_base_dispatch;
output [31:0] dispatch2cu_start_pc_dispatch;
output [15:0] ldssize_out;
output [9:0] vregsize_out;
output [8:0] sregsize_out;
input [NUMOFCU-1:0] cu2dispatch_wf_done;
input [NUMOFCU*15 - 1:0] cu2dispatch_wf_tag_done;
input clk,rst;
`ifdef HARD_DISPATCHER
localparam NUMBER_CU = NUMOFCU;
localparam WG_ID_WIDTH = 6;
localparam WG_SLOT_ID_WIDTH = 6;
localparam NUMBER_WF_SLOTS = 40;
localparam WF_COUNT_WIDTH = 4;
localparam WAVE_ITEM_WIDTH = 6;
localparam VGPR_ID_WIDTH = 8;
localparam NUMBER_VGPR_SLOTS = 256;
localparam SGPR_ID_WIDTH = 4;
localparam NUMBER_SGPR_SLOTS = 13;
localparam LDS_ID_WIDTH = 8;
localparam NUMBER_LDS_SLOTS = 256;
localparam GDS_ID_WIDTH = 14;
localparam GDS_SIZE = 16384;
localparam TAG_WIDTH = 15;
localparam MEM_ADDR_WIDTH = 32;
// Dispatcher internal localparams
localparam RES_TABLE_ADDR_WIDTH = 1;
localparam ENTRY_ADDR_WIDTH = 6;
localparam NUMBER_ENTRIES = 64;
localparam CU_VGPR_ID_WIDTH = 10;
localparam CU_SGPR_ID_WIDTH = 9;
localparam CU_LDS_ID_WIDTH = 16;
localparam CU_GDS_ID_WIDTH = 16;
dispatcher_hard
#(/*AUTOINSTPARAM*/
// Parameters
.NUMBER_CU (NUMBER_CU),
.CU_ID_WIDTH (CU_ID_WIDTH),
.WG_ID_WIDTH (WG_ID_WIDTH),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS (NUMBER_WF_SLOTS),
.WF_COUNT_WIDTH (WF_COUNT_WIDTH),
.WAVE_ITEM_WIDTH (WAVE_ITEM_WIDTH),
.VGPR_ID_WIDTH (VGPR_ID_WIDTH),
.NUMBER_VGPR_SLOTS (NUMBER_VGPR_SLOTS),
.SGPR_ID_WIDTH (SGPR_ID_WIDTH),
.NUMBER_SGPR_SLOTS (NUMBER_SGPR_SLOTS),
.LDS_ID_WIDTH (LDS_ID_WIDTH),
.NUMBER_LDS_SLOTS (NUMBER_LDS_SLOTS),
.GDS_ID_WIDTH (GDS_ID_WIDTH),
.GDS_SIZE (GDS_SIZE),
.TAG_WIDTH (TAG_WIDTH),
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH),
.RES_TABLE_ADDR_WIDTH (RES_TABLE_ADDR_WIDTH),
.ENTRY_ADDR_WIDTH (ENTRY_ADDR_WIDTH),
.NUMBER_ENTRIES (NUMBER_ENTRIES),
.CU_VGPR_ID_WIDTH (CU_VGPR_ID_WIDTH),
.CU_SGPR_ID_WIDTH (CU_SGPR_ID_WIDTH),
.CU_LDS_ID_WIDTH (CU_LDS_ID_WIDTH),
.CU_GDS_ID_WIDTH (CU_GDS_ID_WIDTH))
DISPATCHER
(/*AUTOINST*/
// Outputs
.ldssize_out (ldssize_out[15:0]),
.vregsize_out (vregsize_out[9:0]),
.sregsize_out (sregsize_out[8:0]),
.dispatch2cu_lds_base_dispatch (dispatch2cu_lds_base_dispatch[CU_LDS_ID_WIDTH-1:0]),
.dispatch2cu_sgpr_base_dispatch (dispatch2cu_sgpr_base_dispatch[CU_SGPR_ID_WIDTH-1:0]),
.dispatch2cu_start_pc_dispatch (dispatch2cu_start_pc_dispatch[MEM_ADDR_WIDTH-1:0]),
.dispatch2cu_vgpr_base_dispatch (dispatch2cu_vgpr_base_dispatch[CU_VGPR_ID_WIDTH-1:0]),
.dispatch2cu_wf_dispatch (dispatch2cu_wf_dispatch[NUMBER_CU-1:0]),
.dispatch2cu_wf_size_dispatch (dispatch2cu_wf_size_dispatch[WAVE_ITEM_WIDTH-1:0]),
.dispatch2cu_wf_tag_dispatch (dispatch2cu_wf_tag_dispatch[TAG_WIDTH-1:0]),
.dispatch2cu_wg_wf_count (dispatch2cu_wg_wf_count[WF_COUNT_WIDTH-1:0]),
// Inputs
.clk (clk),
.cu2dispatch_wf_done (cu2dispatch_wf_done[NUMBER_CU-1:0]),
.cu2dispatch_wf_tag_done (cu2dispatch_wf_tag_done[NUMBER_CU*TAG_WIDTH-1:0]),
.rst (rst));
`endif
`ifndef HARD_DISPATCHER
dispatcher_soft
#(/*AUTOINSTPARAM*/
// Parameters
.NUMOFCU (NUMOFCU))
DISPATCHER
(/*AUTOINST*/
// Outputs
.dispatch2cu_wf_dispatch (dispatch2cu_wf_dispatch[(NUMOFCU-1):0]),
.dispatch2cu_wg_wf_count (dispatch2cu_wg_wf_count[3:0]),
.dispatch2cu_wf_size_dispatch (dispatch2cu_wf_size_dispatch[5:0]),
.dispatch2cu_sgpr_base_dispatch (dispatch2cu_sgpr_base_dispatch[8:0]),
.dispatch2cu_vgpr_base_dispatch (dispatch2cu_vgpr_base_dispatch[9:0]),
.dispatch2cu_wf_tag_dispatch (dispatch2cu_wf_tag_dispatch[14:0]),
.dispatch2cu_lds_base_dispatch (dispatch2cu_lds_base_dispatch[15:0]),
.dispatch2cu_start_pc_dispatch (dispatch2cu_start_pc_dispatch[31:0]),
.ldssize_out (ldssize_out[15:0]),
.vregsize_out (vregsize_out[9:0]),
.sregsize_out (sregsize_out[8:0]),
// Inputs
.cu2dispatch_wf_done (cu2dispatch_wf_done[NUMOFCU-1:0]),
.cu2dispatch_wf_tag_done (cu2dispatch_wf_tag_done[NUMOFCU*15-1:0]),
.rst (rst),
.clk (clk));
`endif
endmodule // dispatcher_wrapper
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file data_ram.v when simulating
// the core, data_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module data_ram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [3 : 0] wea;
input [7 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input [3 : 0] web;
input [7 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long power(long long a, long long b) { long long x = 1; a = a % 1000000007ULL; while (b) { if (b & 1) x = (x * a) % 1000000007ULL; a = (a * a) % 1000000007ULL; b >>= 1; } return x; } inline long long inv(long long a) { return power(a, 1000000007ULL - 2); } long long gcd(long long a, long long b) { return a ? gcd(b % a, a) : b; } const int N = 1e5 + 5; string s; vector<int> v[12]; int n; int main() { ios_base::sync_with_stdio(false); cin >> s; n = s.size(); for (int i = 0; i < n; i++) { v[s[i] - 0 ].push_back(i); } if (n < 2) { cout << -1 n ; return 0; } if (n == 2) { if (v[0].size() > 0 && v[5].size() > 0) { if (s[0] == 5 ) cout << 0 n ; else cout << 1 n ; return 0; } if (v[2].size() > 0 && v[5].size() > 0) { if (s[0] == 2 ) cout << 0 n ; else cout << 1 n ; return 0; } if (v[7].size() > 0 && v[5].size() > 0) { if (s[0] == 7 ) cout << 0 n ; else cout << 1 n ; return 0; } cout << -1 n ; return 0; } int ans = 10000; if (v[0].size() > 1) { int x = v[0].size(); ans = min(ans, abs(n - 1 - v[0][x - 1]) + abs(n - 2 - v[0][x - 2])); } if (v[2].size() > 0 && v[5].size() > 0) { int x = v[2].size(); int y = v[5].size(); x = v[2][x - 1]; y = v[5][y - 1]; if (n != 3 || v[0].size() == 0) { int tmp = 0; string sss = s; for (int i = y; i < n - 1; i++) { sss[i] = sss[i + 1]; tmp++; } sss[n - 1] = 5 ; for (int j = n - 2; j > -1; j--) { if (sss[j] == 2 ) { x = j; break; } } for (int i = x; i < n - 2; i++) { sss[i] = sss[i + 1]; tmp++; } sss[n - 2] = 2 ; if (sss[0] == 0 ) { for (int j = 0; j < n; j++) { if (sss[j] == 0 ) tmp++; } } ans = min(tmp, ans); } } if (v[7].size() > 0 && v[5].size() > 0) { int x = v[7].size(); int y = v[5].size(); x = v[7][x - 1]; y = v[5][y - 1]; if (n != 3 || v[0].size() == 0) { int tmp = 0; string sss = s; for (int i = y; i < n - 1; i++) { sss[i] = sss[i + 1]; tmp++; } sss[n - 1] = 5 ; for (int j = n - 2; j > -1; j--) { if (sss[j] == 7 ) { x = j; break; } } for (int i = x; i < n - 2; i++) { sss[i] = sss[i + 1]; tmp++; } sss[n - 2] = 7 ; if (sss[0] == 0 ) { for (int j = 0; j < n; j++) { if (sss[j] == 0 ) tmp++; } } ans = min(tmp, ans); } } if (v[5].size() > 0 && v[0].size() > 0) { int x = v[5].size(); int y = v[0].size(); x = v[5][x - 1]; y = v[0][y - 1]; if (n != 3 || v[0].size() == 1) { int tmp = 0; string sss = s; for (int i = y; i < n - 1; i++) { sss[i] = sss[i + 1]; tmp++; } sss[n - 1] = 0 ; for (int j = n - 2; j > -1; j--) { if (sss[j] == 5 ) { x = j; break; } } for (int i = x; i < n - 2; i++) { sss[i] = sss[i + 1]; tmp++; } sss[n - 2] = 5 ; if (sss[0] == 0 ) { for (int j = 0; j < n; j++) { if (sss[j] == 0 ) tmp++; } } ans = min(tmp, ans); } } if (ans == 10000) { cout << -1 n ; return 0; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void warp() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); } long long get(vector<long long> &a, vector<long long> &b) { long long ans = 0; long long all = 0; long long n = a.size(); for (long long i = 0; i < n; i++) all += b[i]; long long cur = b[0], tar = 0; while (cur < all - cur) { tar++; cur += b[tar]; } for (long long i = 0; i < n; i++) { ans += b[i] * abs(a[i] - a[tar]); } return ans; } long long check(long long need, vector<long long> a) { long long ans = 0; long long n = a.size(); vector<long long> cur; vector<long long> b; long long s = 0; for (long long i = 0; i < n; i++) { a[i] %= need; if (a[i]) { cur.push_back(i); b.push_back(a[i]); } s += a[i]; if (s >= need && b.size()) { b.back() -= (s - need); ans += get(cur, b); cur.clear(); b.clear(); s -= need; if (s == 0) continue; cur.push_back(i); b.push_back(s); } } return ans; } long long solve(long long n, vector<long long> a) { long long cnt = 0; for (long long i = 0; i < n; i++) cnt += a[i]; if (cnt == 1) { return -1; } long long ans = check(cnt, a); vector<bool> prime(1e6 + 1, true); for (long long i = 2; i * i <= cnt; i++) { if (cnt % i) continue; while (cnt % i == 0) cnt /= i; ans = min(ans, check(i, a)); } if (cnt > 1) ans = min(ans, check(cnt, a)); return ans; } const long long maxn = 1e6; void gen(vector<long long> &a) { long long n = a.size(); for (long long i = 0; i < n; i++) a[i] = rand() % 20; long long s = 0; for (long long i = 0; i < n; i++) s += a[i]; if (s == 0) a[0] = 1; } signed main() { warp(); long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } cout << solve(n, a) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[100005]; int reduce(int n) { while (n % 2 == 0) n /= 2; while (n % 3 == 0) n /= 3; return n; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); } int r = reduce(arr[0]); bool ok = true; for (int i = 1; i < n; i++) { if (reduce(arr[i]) != r) { ok = false; break; } } if (ok) printf( Yes n ); else printf( No n ); return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_phy_ctl_io.v
// /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:00 $
// \ \ / \ Date Created: Thu Aug 24 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module puts the memory control signals like address, bank address,
// row address strobe, column address strobe, write enable and clock enable
// in the IOBs.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_ctl_io #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2,
parameter CKE_WIDTH = 1,
parameter COL_WIDTH = 10,
parameter CS_NUM = 1,
parameter TWO_T_TIME_EN = 0,
parameter CS_WIDTH = 1,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 14,
parameter DDR_TYPE = 1
)
(
input clk0,
input clk90,
input rst0,
input rst90,
input [ROW_WIDTH-1:0] ctrl_addr,
input [BANK_WIDTH-1:0] ctrl_ba,
input ctrl_ras_n,
input ctrl_cas_n,
input ctrl_we_n,
input [CS_NUM-1:0] ctrl_cs_n,
input [ROW_WIDTH-1:0] phy_init_addr,
input [BANK_WIDTH-1:0] phy_init_ba,
input phy_init_ras_n,
input phy_init_cas_n,
input phy_init_we_n,
input [CS_NUM-1:0] phy_init_cs_n,
input [CKE_WIDTH-1:0] phy_init_cke,
input phy_init_data_sel,
input [CS_NUM-1:0] odt,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH-1:0] ddr_cs_n,
output [ODT_WIDTH-1:0] ddr_odt
);
reg [ROW_WIDTH-1:0] addr_mux;
reg [BANK_WIDTH-1:0] ba_mux;
reg cas_n_mux;
reg [CS_NUM-1:0] cs_n_mux;
reg ras_n_mux;
reg we_n_mux;
//***************************************************************************
// MUX to choose from either PHY or controller for SDRAM control
generate // in 2t timing mode the extra register stage cannot be used.
if(TWO_T_TIME_EN) begin // the control signals are asserted for two cycles
always @(*)begin
if (phy_init_data_sel) begin
addr_mux = ctrl_addr;
ba_mux = ctrl_ba;
cas_n_mux = ctrl_cas_n;
cs_n_mux = ctrl_cs_n;
ras_n_mux = ctrl_ras_n;
we_n_mux = ctrl_we_n;
end else begin
addr_mux = phy_init_addr;
ba_mux = phy_init_ba;
cas_n_mux = phy_init_cas_n;
cs_n_mux = phy_init_cs_n;
ras_n_mux = phy_init_ras_n;
we_n_mux = phy_init_we_n;
end
end
end else begin
always @(posedge clk0)begin // register the signals in non 2t mode
if (phy_init_data_sel) begin
addr_mux <= ctrl_addr;
ba_mux <= ctrl_ba;
cas_n_mux <= ctrl_cas_n;
cs_n_mux <= ctrl_cs_n;
ras_n_mux <= ctrl_ras_n;
we_n_mux <= ctrl_we_n;
end else begin
addr_mux <= phy_init_addr;
ba_mux <= phy_init_ba;
cas_n_mux <= phy_init_cas_n;
cs_n_mux <= phy_init_cs_n;
ras_n_mux <= phy_init_ras_n;
we_n_mux <= phy_init_we_n;
end
end
end
endgenerate
//***************************************************************************
// Output flop instantiation
// NOTE: Make sure all control/address flops are placed in IOBs
//***************************************************************************
// RAS: = 1 at reset
(* IOB = "FORCE" *) FDCPE u_ff_ras_n
(
.Q (ddr_ras_n),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (ras_n_mux),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
// CAS: = 1 at reset
(* IOB = "FORCE" *) FDCPE u_ff_cas_n
(
.Q (ddr_cas_n),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (cas_n_mux),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
// WE: = 1 at reset
(* IOB = "FORCE" *) FDCPE u_ff_we_n
(
.Q (ddr_we_n),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (we_n_mux),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
// CKE: = 0 at reset
genvar cke_i;
generate
for (cke_i = 0; cke_i < CKE_WIDTH; cke_i = cke_i + 1) begin: gen_cke
(* IOB = "FORCE" *) FDCPE u_ff_cke
(
.Q (ddr_cke[cke_i]),
.C (clk0),
.CE (1'b1),
.CLR (rst0),
.D (phy_init_cke[cke_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
// chip select: = 1 at reset
// For unbuffered dimms the loading will be high. The chip select
// can be asserted early if the loading is very high. The
// code as is uses clock 0. If needed clock 270 can be used to
// toggle chip select 1/4 clock cycle early. The code has
// the clock 90 input for the early assertion of chip select.
genvar cs_i;
generate
for(cs_i = 0; cs_i < CS_WIDTH; cs_i = cs_i + 1) begin: gen_cs_n
if(TWO_T_TIME_EN) begin
(* IOB = "FORCE" *) FDCPE u_ff_cs_n
(
.Q (ddr_cs_n[cs_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
end else begin // if (TWO_T_TIME_EN)
(* IOB = "FORCE" *) FDCPE u_ff_cs_n
(
.Q (ddr_cs_n[cs_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
end // else: !if(TWO_T_TIME_EN)
end
endgenerate
// address: = X at reset
genvar addr_i;
generate
for (addr_i = 0; addr_i < ROW_WIDTH; addr_i = addr_i + 1) begin: gen_addr
(* IOB = "FORCE" *) FDCPE u_ff_addr
(
.Q (ddr_addr[addr_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (addr_mux[addr_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
// bank address = X at reset
genvar ba_i;
generate
for (ba_i = 0; ba_i < BANK_WIDTH; ba_i = ba_i + 1) begin: gen_ba
(* IOB = "FORCE" *) FDCPE u_ff_ba
(
.Q (ddr_ba[ba_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (ba_mux[ba_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
// ODT control = 0 at reset
genvar odt_i;
generate
if (DDR_TYPE > 0) begin: gen_odt_ddr2
for (odt_i = 0; odt_i < ODT_WIDTH; odt_i = odt_i + 1) begin: gen_odt
(* IOB = "FORCE" *) FDCPE u_ff_odt
(
.Q (ddr_odt[odt_i]),
.C (clk0),
.CE (1'b1),
.CLR (rst0),
.D (odt[(odt_i*CS_NUM)/ODT_WIDTH]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ls__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long linf = 1e18 + 5; const int mod = (int)1e9 + 7; const int logN = 17; const int inf = 1e9; const int N = 2e5 + 5; int temp[1 << 7][1 << 7], res[1 << 7][1 << 7], cur[1 << 7][1 << 7], x; void mul(int res[][1 << 7], int cur[][1 << 7], int t) { t = 1 << t; --t; memset(temp, 0, sizeof temp); for (int i = 0; i <= t; i++) for (int j = 0; j <= t; j++) for (int k = 0; k <= t; k++) temp[i][j] = (temp[i][j] + res[i][k] * (long long)cur[k][j] % mod) % mod; memcpy(res, temp, sizeof temp); } int main() { for (int i = 0; i <= (1 << 7) - 1; i++) res[i][i] = 1; for (int i = 1; i <= 7; i++) { scanf( %d , &x); for (int a = 0; a <= (1 << i) - 1; a++) for (int b = 0; b <= (1 << i) - 1; b++) { cur[a][b] = 0; for (int poke = 0; poke <= (1 << i + 1) - 1; poke++) { if ((poke & 1) || (poke & (1 << i))) continue; if ((((a | b | poke | (poke >> 1)) & ((1 << i) - 1))) == (1 << i) - 1) cur[a][b]++; } } while (x) { if (x & 1) mul(res, cur, i); x >>= 1; mul(cur, cur, i); } } cout << res[0][0] << n ; return 0; }
|
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMR.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMR (
O,
I
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n; cin >> s; int count = 0; for (int i = 0; i < n; i++) { if (s[i] == 8 ) { count++; } } int a = n / 11; if (count >= a) { cout << a; } else { cout << count; } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_eth_tx
*/
module test_ip_eth_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_ip_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [15:0] s_ip_identification = 0;
reg [2:0] s_ip_flags = 0;
reg [12:0] s_ip_fragment_offset = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [7:0] s_ip_payload_axis_tdata = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [7:0] m_eth_payload_axis_tdata;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
wire error_payload_early_termination;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
busy,
error_payload_early_termination
);
// dump file
$dumpfile("test_ip_eth_tx.lxt");
$dumpvars(0, test_ip_eth_tx);
end
ip_eth_tx
UUT (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy),
.error_payload_early_termination(error_payload_early_termination)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_TB_V
`define SKY130_FD_SC_LP__DFSTP_TB_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfstp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__dfstp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 500008; int n, m, cnt; int day[] = {0, 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int get(int x) { int ret = 0; for (int i = 0; i < x; ++i) ret += day[i]; return ret; } struct Node { int year, month, date; int hour, minute, second; int dis; Node() {} Node(int Y, int M, int D, int H, int Mi, int S) { year = Y, month = M, date = D; hour = H, minute = Mi, second = S; dis = second + minute * 60 + hour * 3600; if (date - 1 == 0) { dis += day[month - 1] * 24 * 3600 + get(month - 1) * 24 * 3600; } else dis += (date - 1) * 24 * 3600 + get(month) * 24 * 3600; }; } node[maxn]; int main() { cin >> n >> m; string str; cnt = 0; while (cin >> str) { int y = 2012, m = (str[5] - 0 ) * 10 + str[6] - 0 , d = (str[8] - 0 ) * 10 + str[9] - 0 ; cin >> str; int h = (str[0] - 0 ) * 10 + str[1] - 0 , mi = (str[3] - 0 ) * 10 + str[4] - 0 , s = (str[6] - 0 ) * 10 + str[7] - 0 ; node[++cnt] = Node(y, m, d, h, mi, s); getline(cin, str, n ); } bool ff = 0; int i; for (i = m; i <= cnt; ++i) { if (node[i].dis - node[i - m + 1].dis + 1 <= n) { ff = 1; break; } } if (ff) { printf( %02d-%02d-%02d , node[i].year, node[i].month, node[i].date); printf( %02d:%02d:%02d n , node[i].hour, node[i].minute, node[i].second); } else puts( -1 ); }
|
#include <bits/stdc++.h> using namespace std; int N; int main() { cin >> N; int dec[2 * N]; int all_round_down = 0; int z = 0; for (int i = 0; i < 2 * N; i++) { double x; cin >> x; dec[i] = int((x + 0.0005 - int(x + 0.0005)) * 1000); all_round_down += dec[i]; if (dec[i] == 0) z++; } int mi = max(0, N - z); int ma = min(N, 2 * N - z); int best = (all_round_down + 500) / 1000; int ans; if (best >= mi && best <= ma) ans = abs(all_round_down - 1000 * best); else ans = min(abs(all_round_down - 1000 * mi), abs(all_round_down - 1000 * ma)); cout << ans / 1000 << . << (ans % 1000) / 100 << (ans % 100) / 10 << ans % 10; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 11; const long long MOD0 = 1e9 + 7; const long long P0 = 37; const long long MOD1 = 1e9 + 9; const long long P1 = 49; long long a[N], b[N]; long long h1[2][N], h2[2][N], s[2][N]; long long m, n; map<int, bool> ans; int getnext(int pos) { if (pos > a[n]) return 1e9; int l = 1, r = n; while (r - l > 1) { int mid = (l + r) / 2; if (a[mid] >= pos) r = mid; else l = mid; } if (a[l] >= pos) return l; return r; } int getprev(int pos) { if (pos < a[1]) return -1e9; int l = 1, r = n; while (r - l > 1) { int mid = (l + r) / 2; if (a[mid] <= pos) l = mid; else r = mid; } if (a[r] <= pos) return r; return l; } bool good0(int l, int r) { long long hash1 = h1[0][r] - h1[0][l - 1] + MOD0; hash1 *= s[0][n - r]; hash1 %= MOD0; long long hash2 = h2[0][l] - h2[0][r + 1] + MOD0; hash2 *= s[0][l]; hash2 %= MOD0; if (hash1 == hash2) return true; return false; } bool good1(int l, int r) { long long hash1 = h1[1][r] - h1[1][l - 1] + MOD1; hash1 *= s[1][n - r]; hash1 %= MOD1; long long hash2 = h2[1][l] - h2[1][r + 1] + MOD1; hash2 *= s[1][l]; hash2 %= MOD1; if (hash1 == hash2) return true; return false; } bool good(long long x, long long y) { if (x > y) return true; if (y < a[1]) return true; int l = getnext(x), r = getprev(y); if (l > r) return true; if (a[l] - x != y - a[r]) return false; if (l == r) return true; if (good1(l, r - 1) && good0(l, r - 1)) return true; return false; } bool good(long long p) { if (ans[p]) return false; ans[p] = 1; if (good(0, p) && good(p + 1, m - 1)) return true; return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i < n; i++) b[i] = a[i + 1] - a[i]; s[0][0] = 1; s[1][0] = 1; for (int i = 1; i <= n * 2; i++) { s[0][i] = (s[0][i - 1] * P0) % MOD0; s[1][i] = (s[1][i - 1] * P1) % MOD1; } for (int i = 1; i < n; i++) { h1[0][i] = (h1[0][i - 1] + b[i] * s[0][i]) % MOD0; h1[1][i] = (h1[1][i - 1] + b[i] * s[1][i]) % MOD1; } for (int i = n - 1; i >= 1; i--) { h2[0][i] = (h2[0][i + 1] + b[i] * s[0][n - i]) % MOD0; h2[1][i] = (h2[1][i + 1] + b[i] * s[1][n - i]) % MOD1; } vector<int> vv; for (int i = 1; i <= n; i++) { long long x = (a[1] + a[i]) % m; if (good(x)) vv.push_back(x); } sort(vv.begin(), vv.end()); cout << vv.size() << endl; for (int j = 0; j < vv.size(); j++) cout << vv[j] << ; }
|
#include <bits/stdc++.h> using namespace std; struct sgmnt { long long L, R; int mxL, mxR, w; sgmnt() {} sgmnt(long long L, int mxL, long long R, int mxR, int w) : L(L), mxL(mxL), R(R), mxR(mxR), w(w) {} }; const int MAXN = 3 * 1000 * 100 + 10; long long arr[MAXN]; sgmnt seg[MAXN * 4]; sgmnt merge(sgmnt a, sgmnt b, int s, int m, int e) { sgmnt c = sgmnt(a.L, a.mxL, b.R, b.mxR, max(a.w, b.w)); if ((a.R > 0 && b.L != 0) || (a.R < 0 && b.L < 0)) { if (a.mxL == m - s) c.mxL = a.mxL + b.mxL; if (b.mxR == e - m) c.mxR = b.mxR + a.mxR; c.w = max(c.w, a.mxR + b.mxL); } c.w = max({c.w, c.mxR, c.mxL}); return c; } void add(int p, int v, int s, int e) { if (e - s <= 1) { seg[v] = sgmnt(arr[s], 1, arr[s], 1, 1); return; } int m = (s + e) / 2; if (p < m) add(p, v * 2, s, m); else add(p, v * 2 + 1, m, e); seg[v] = merge(seg[v * 2], seg[v * 2 + 1], s, m, e); } int main() { int n, b; scanf( %d %d , &n, &b); n--; for (int i = 0; i < n; i++) { int a; scanf( %d , &a); arr[i] = a - b; add(i, 1, 0, n); b = a; } int q; scanf( %d , &q); while (q--) { int l, r, d; scanf( %d %d %d , &l, &r, &d); l--; if (!n) { cout << 1 << endl; continue; } if (l != 0) { arr[l - 1] += d; add(l - 1, 1, 0, n); } if (r != n + 1) { arr[r - 1] -= d; add(r - 1, 1, 0, n); } printf( %d n , seg[1].w + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, h; cin >> n; int a[n]; cin >> a[0]; h = a[0]; for (int i = 1; i < n; i++) { cin >> a[i]; h = h + abs(a[i] - a[i - 1]) + 1; } cout << h + n; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) using namespace std; bool is_prime(long long n) { for (long long i = 2; i * i <= n; ++i) { if (n % i == 0) { return false; } } return true; } vector<long long> fact(long long n) { vector<long long> ans; for (int i = 2; i * i <= n; i++) { if (n % i == 0) { ans.push_back(i); while (n % i == 0) { n /= i; } } } if (n > 1) ans.push_back(n); return ans; } long long getPow(long long a, long long b) { long long res = 1ll, tp = a; while (b) { if (b & 1ll) { res *= tp; } tp *= tp; b >>= 1ll; } return res; } long long vec_mult(long long x1, long long y1, long long x2, long long y2, long long x3, long long y3) { return abs((x2 - x1) * (y3 - y1) - (y2 - y1) * (x3 - x1)); } void ok() { cout << YES << endl; exit(0); } void no() { cout << NO << endl; exit(0); } inline long long nxt() { long long x; cin >> x; return x; } const long long N = 3000 + 5, inf = 2e16; int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); long long n = nxt(), m = nxt(), k = nxt(); vector<long long> used(n, 1); for (int i = 0; i < m; i++) { long long x = nxt(); used[x] = 0; } vector<long long> a(k); for (int i = 0; i < k; i++) { a[i] = nxt(); } if (!used[0]) { return cout << -1, 0; } vector<long long> pos; for (int i = 0; i < n; i++) { if (used[i]) pos.push_back(i); } auto get = [&](long long l) { long long ct = 0; long long start = 0; long long ind = 0; if (!pos.size()) return inf; while (true) { ct++; long long cur = start + l; if (cur >= n) { start = cur; break; } long long cur_ind = (upper_bound(pos.begin(), pos.end(), cur)) - pos.begin(); if (cur_ind == pos.size()) cur_ind--; else if (pos[cur_ind] > cur) { cur_ind--; } if (pos[cur_ind] == start) break; if (cur < n) { start = pos[cur_ind]; } else { start = cur; break; } } if (start >= n) return ct; else return inf; }; long long ans = inf; for (int i = 0; i < k; i++) { long long ct = get(i + 1); if (ct == inf) continue; ans = min(ans, ct * a[i]); } if (ans >= inf) cout << -1; else cout << ans; return 0; }
|
/*
* ALU.
*
* AI and BI are 8 bit inputs. Result in OUT.
* CI is Carry In.
* CO is Carry Out.
*
* op[3:0] is defined as follows:
*
* 0011 AI + BI
* 0111 AI - BI
* 1011 AI + AI
* 1100 AI | BI
* 1101 AI & BI
* 1110 AI ^ BI
* 1111 AI
*
*/
`timescale 1ns / 1ps
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, x, y, z, k, w, ans; int A[400], B[400]; char c[2]; int main() { scanf( %d , &n); for (int i = (0); i < (n); i++) { scanf( %s%d%d , &c, &x, &y); if (c[0] == M ) { for (int j = (x); j <= (y); j++) A[j]++; } else { for (int j = (x); j <= (y); j++) B[j]++; } } for (int i = (1); i <= (366); i++) ans = max(ans, min(A[i], B[i])); printf( %d n , ans * 2); return 0; }
|
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_fifo_progfull, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input wr_clk;
input [AW:0] wr_rd_gray_pointer;//synced from read domain
input wr_write;
//###########
//# OUTPUTS
//###########
output wr_fifo_full;
output wr_fifo_progfull;//TODO: hack!, fix this properly
//also make, programmable
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
//#########
//# REGS
//#########
reg [AW:0] wr_gray_pointer;
reg [AW:0] wr_binary_pointer;
reg wr_fifo_full;
//##########
//# WIRES
//##########
wire wr_fifo_full_next;
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
wire wr_fifo_progfull_next;
reg wr_fifo_progfull;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
begin
wr_binary_pointer[AW:0] <= {(AW+1){1'b0}};
wr_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(wr_write)
begin
wr_binary_pointer[AW:0] <= wr_binary_next[AW:0];
wr_gray_pointer[AW:0] <= wr_gray_next[AW:0];
end
//Write Address
assign wr_addr[AW-1:0] = wr_binary_pointer[AW-1:0];
//Updating binary pointer
assign wr_binary_next[AW:0] = wr_binary_pointer[AW:0] +
{{(AW){1'b0}},wr_write};
//Gray Pointer Conversion (for more reliable synchronization)!
assign wr_gray_next[AW:0] = {1'b0,wr_binary_next[AW:1]} ^
wr_binary_next[AW:0];
//FIFO full indication
assign wr_fifo_full_next =
(wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
//FIFO almost full
assign wr_fifo_progfull_next =
(wr_gray_next[AW-3:0] == wr_rd_gray_pointer[AW-3:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]) &
(wr_gray_next[AW-2] ^ wr_rd_gray_pointer[AW-2]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
else
wr_fifo_full <=wr_fifo_full_next;
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_progfull <= 1'b0;
else
wr_fifo_progfull <=wr_fifo_progfull_next;
endmodule // fifo_full_block
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
`include "project_defines.v"
module seeed_tft #(
parameter BUFFER_SIZE = 12
)(
input rst,
input clk,
output [31:0] debug,
input i_soft_tearing,
input [7:0] i_tearing_reg,
input [31:0] i_tearing_value,
input [31:0] i_tearing_count,
input [7:0] i_mem_write_cmd,
input i_tearing_polarity,
//Control Signals
input i_enable,
input i_reset_display,
input i_data_command_mode,
input i_enable_tearing,
input i_cmd_rs,
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output [7:0] o_cmd_data,
output o_cmd_finished,
input i_backlight_enable,
input i_chip_select,
input [31:0] i_num_pixels,
//FIFO Signals
output [1:0] o_fifo_rdy,
input [1:0] i_fifo_act,
input i_fifo_stb,
output [23:0] o_fifo_size,
input [31:0] i_fifo_data,
//Physical Signals
output o_backlight_enable,
output o_register_data_sel,
output o_write_n,
output o_read_n,
inout [7:0] io_data,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
output o_display_on
);
//Local Parameters
//Registers/Wires
wire [7:0] w_data_out;
wire [7:0] w_data_in;
wire w_cmd_write;
wire w_cmd_read;
wire [7:0] w_cmd_data;
wire w_cmd_cmd_mode;
wire w_cmd_data_out_en;
wire w_data_dir;
wire w_data_chip_select;
wire w_data_cmd_mode;
wire [7:0] w_data_data;
wire w_data_write;
wire w_data_read;
wire w_data_data_out_en;
//Submodules
seeed_tft_command lcd_commander (
.rst (rst ),
.clk (clk ),
// .debug (debug ),
.i_enable (i_enable ),
.i_cmd_rs (i_cmd_rs ),
.i_cmd_write_stb (i_cmd_write_stb ),
.i_cmd_read_stb (i_cmd_read_stb ),
.i_cmd_data (i_cmd_data ),
.o_cmd_data (o_cmd_data ),
//Control Signals
.o_data_out_en (w_cmd_data_out_en ),
.o_cmd_finished (o_cmd_finished ),
.o_cmd_mode (w_cmd_cmd_mode ),
.o_write (w_cmd_write ),
.o_read (w_cmd_read ),
.o_data_out (w_cmd_data ),
.i_data_in (w_data_in )
);
seeed_tft_data_writer #(
.BUFFER_SIZE (BUFFER_SIZE )
)lcd_data_writer(
.rst (rst ),
.clk (clk ),
.debug (debug ),
.i_soft_tearing (i_soft_tearing ),
.i_tearing_reg (i_tearing_reg ),
.i_tearing_value (i_tearing_value ),
.i_tearing_count (i_tearing_count ),
.i_mem_write_cmd (i_mem_write_cmd ),
.i_tearing_polarity (i_tearing_polarity ),
.i_enable (i_enable ),
.i_enable_tearing (i_enable_tearing ),
.i_num_pixels (i_num_pixels ),
.o_fifo_rdy (o_fifo_rdy ),
.i_fifo_act (i_fifo_act ),
.i_fifo_stb (i_fifo_stb ),
.o_fifo_size (o_fifo_size ),
.i_fifo_data (i_fifo_data ),
.i_tearing_effect (i_tearing_effect ),
.o_chip_select (w_data_chip_select ),
.o_cmd_mode (w_data_cmd_mode ),
.o_data_out (w_data_data ),
.i_data_in (w_data_in ),
.o_write (w_data_write ),
.o_read (w_data_read ),
.o_data_out_en (w_data_data_out_en )
);
//Asynchronous Logic
assign o_backlight_enable = i_backlight_enable;
assign o_display_on = i_enable;
assign o_reset_n = ~i_reset_display;
assign w_data_in = io_data;
//Select control between the Command controller and the Data Controller
assign o_cs_n = (i_data_command_mode) ? ~w_data_chip_select : ~i_chip_select;
assign o_register_data_sel = (i_data_command_mode) ? w_data_cmd_mode : w_cmd_cmd_mode;
assign o_write_n = (i_data_command_mode) ? ~w_data_write : ~w_cmd_write;
assign o_read_n = (i_data_command_mode) ? ~w_data_read : ~w_cmd_read;
assign w_data_dir = (i_data_command_mode) ? w_data_data_out_en : w_cmd_data_out_en;
assign io_data = (w_data_dir) ? (i_data_command_mode) ?
w_data_data : w_cmd_data :
8'hZZ;
//Synchronous Logic
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_tx_addr_add.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:18 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module MAC_tx_addr_add (
Reset ,
Clk ,
MAC_tx_addr_init ,
MAC_tx_addr_rd ,
MAC_tx_addr_data ,
//CPU ,
MAC_add_prom_data ,
MAC_add_prom_add ,
MAC_add_prom_wr
);
input Reset ;
input Clk ;
input MAC_tx_addr_rd ;
input MAC_tx_addr_init ;
output [7:0] MAC_tx_addr_data ;
//CPU ;
input [7:0] MAC_add_prom_data ;
input [2:0] MAC_add_prom_add ;
input MAC_add_prom_wr ;
//******************************************************************************
//internal signals
//******************************************************************************
reg [2:0] add_rd;
wire[2:0] add_wr;
wire[7:0] din;
wire[7:0] dout;
wire wr_en;
reg MAC_add_prom_wr_dl1;
reg MAC_add_prom_wr_dl2;
//******************************************************************************
//write data from cpu to prom
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
MAC_add_prom_wr_dl1 <=0;
MAC_add_prom_wr_dl2 <=0;
end
else
begin
MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
end
assign # 2 wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
assign # 2 add_wr =MAC_add_prom_add;
assign # 2 din =MAC_add_prom_data;
//******************************************************************************
//read data from cpu to prom
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
add_rd <=0;
else if (MAC_tx_addr_init)
add_rd <=0;
else if (MAC_tx_addr_rd)
add_rd <=add_rd + 1;
assign MAC_tx_addr_data=dout;
//******************************************************************************
//b port for read ,a port for write .
//******************************************************************************
duram #(8,3,"M512","DUAL_PORT") U_duram(
.data_a (din ),
.wren_a (wr_en ),
.address_a (add_wr ),
.address_b (add_rd ),
.clock_a (Clk ),
.clock_b (Clk ),
.q_b (dout ));
endmodule
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: usint_div.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module usint_div (
denom,
numer,
quotient,
remain);
input [15:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [15:0] remain;
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] quotient = sub_wire0[15:0];
wire [15:0] remain = sub_wire1[15:0];
lpm_divide LPM_DIVIDE_component (
.denom (denom),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 16,
LPM_DIVIDE_component.lpm_widthn = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "16"
// Retrieval info: USED_PORT: denom 0 0 16 0 INPUT NODEFVAL "denom[15..0]"
// Retrieval info: USED_PORT: numer 0 0 16 0 INPUT NODEFVAL "numer[15..0]"
// Retrieval info: USED_PORT: quotient 0 0 16 0 OUTPUT NODEFVAL "quotient[15..0]"
// Retrieval info: USED_PORT: remain 0 0 16 0 OUTPUT NODEFVAL "remain[15..0]"
// Retrieval info: CONNECT: @denom 0 0 16 0 denom 0 0 16 0
// Retrieval info: CONNECT: @numer 0 0 16 0 numer 0 0 16 0
// Retrieval info: CONNECT: quotient 0 0 16 0 @quotient 0 0 16 0
// Retrieval info: CONNECT: remain 0 0 16 0 @remain 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL usint_div.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL usint_div.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usint_div.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usint_div.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usint_div_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usint_div_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_1_V
`define SKY130_FD_SC_LS__A32OI_1_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32oi_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_1_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::high_resolution_clock::now().time_since_epoch().count()); long long power(long long b, long long e, long long m) { if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } long long power(long long b, long long e) { if (e == 0) return 1; if (e & 1) return b * power(b * b, e / 2); return power(b * b, e / 2); } template <typename T, typename U> static inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> static inline void amax(T &x, U y) { if (x < y) x = y; } int n; const int N = 300005; vector<int> v[N]; bool vis[N]; int val[N]; int dp[N][2], ans = 0; void dfs(int s) { vis[s] = true; for (auto j : v[s]) { if (!vis[j]) { dfs(j); dp[s][0] += dp[j][0]; dp[s][1] += dp[j][1]; } } if (val[s]) ++dp[s][val[s] - 1]; } void dfs2(int s = 1) { vis[s] = true; for (auto j : v[s]) { if (!vis[j]) { int k = (dp[j][0] > 0); if ((k > 0 && dp[j][1] == 0) || (k == 0 && dp[j][1] >= 0)) { int z = ((dp[1][0] - dp[j][0]) > 0); if ((z > 0 && dp[1][1] - dp[j][1] == 0) || (z == 0 && dp[1][1] - dp[j][1] >= 0)) ++ans; } dfs2(j); } } } int _runtimeTerror_() { int i; cin >> n; for (i = 1; i <= n; ++i) cin >> val[i]; for (i = 0; i < n - 1; ++i) { int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } dfs(1); memset(vis, false, sizeof(vis)); dfs2(); cout << ans << n ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) _runtimeTerror_(); cerr << n << 1.0 * clock() / CLOCKS_PER_SEC; return 0; }
|
module test #(
parameter integer i1 = 1.0, i2 = 2,
parameter [7:0] v1 = 3.0, v2 = 4,
parameter real r1 = 5.0, r2 = 6,
parameter u1 = 7.0, u2 = 8'd8
)(
);
parameter integer i3 = 1.0, i4 = 2;
parameter [7:0] v3 = 3.0, v4 = 4;
parameter real r3 = 5.0, r4 = 6;
parameter u3 = 7.0, u4 = 8'd8;
localparam integer i5 = 1.0, i6 = 2;
localparam [7:0] v5 = 3.0, v6 = 4;
localparam real r5 = 5.0, r6 = 6;
localparam u5 = 7.0, u6 = 8'd8;
reg failed = 0;
initial begin
$display("%b", i1);
$display("%b", i2);
$display("%b", v1);
$display("%b", v2);
$display("%f", r1);
$display("%f", r2);
$display("%f", u1);
$display("%b", u2);
if (i1 !== 32'd1) failed = 1;
if (i2 !== 32'd2) failed = 1;
if (v1 !== 8'd3) failed = 1;
if (v2 !== 8'd4) failed = 1;
if (r1 != 5.0) failed = 1;
if (r2 != 6.0) failed = 1;
if (u1 != 7.0) failed = 1;
if (u2 !== 8'd8) failed = 1;
$display("%b", i3);
$display("%b", i4);
$display("%b", v3);
$display("%b", v4);
$display("%f", r3);
$display("%f", r4);
$display("%f", u3);
$display("%b", u4);
if (i3 !== 32'd1) failed = 1;
if (i4 !== 32'd2) failed = 1;
if (v3 !== 8'd3) failed = 1;
if (v4 !== 8'd4) failed = 1;
if (r3 != 5.0) failed = 1;
if (r4 != 6.0) failed = 1;
if (u3 != 7.0) failed = 1;
if (u4 !== 8'd8) failed = 1;
$display("%b", i5);
$display("%b", i6);
$display("%b", v5);
$display("%b", v6);
$display("%f", r5);
$display("%f", r6);
$display("%f", u5);
$display("%b", u6);
if (i5 !== 32'd1) failed = 1;
if (i6 !== 32'd2) failed = 1;
if (v5 !== 8'd3) failed = 1;
if (v6 !== 8'd4) failed = 1;
if (r5 != 5.0) failed = 1;
if (r6 != 6.0) failed = 1;
if (u5 != 7.0) failed = 1;
if (u6 !== 8'd8) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
ui32ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 5, 11)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui32ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 8, 24)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui32ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 11, 53)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui32ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 15, 113)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui64ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 5, 11)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui64ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 8, 24)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui64ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 11, 53)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
ui64ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 15, 113)
iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);
endmodule
module
i32ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 5, 11)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i32ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 8, 24)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i32ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 11, 53)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i32ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [31:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(32, 15, 113)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i64ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 5, 11)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i64ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 8, 24)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i64ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 11, 53)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
module
i64ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [63:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
iNToRecFN#(64, 15, 113)
iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("loop.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 1;
reg [ MEM_ADDR:0] pc = 17;
reg [STACK_DEPTH:0] index = 1;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("loop_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
#247
`assert(result, 3);
`assert(result_empty, 0);
$finish;
end
endmodule
|
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
#(PER1*50);
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 305; int n, m; inline int gi() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); int sum = 0; while ( 0 <= c && c <= 9 ) sum = sum * 10 + c - 48, c = getchar(); return sum; } const int Maxn = 605, Maxm = Maxn * Maxn; const long long Inf = 1ll << 60, zero = 5000000; long long ans; struct edge { int to, next; long long cap; } e[Maxm]; int h[Maxn], tot, s, t; inline void add(int u, int v, long long w) { e[++tot] = (edge){v, h[u], w}; h[u] = tot; e[++tot] = (edge){u, h[v], 0}; h[v] = tot; } bool vis[Maxn]; int l, r, que[Maxn], d[Maxn], cur[Maxn]; inline bool bfs() { l = 0; r = 1; que[r] = s; vis[s] = true; do { int u = que[++l]; for (int i = h[u], v; ~i; i = e[i].next) if (e[i].cap && !vis[v = e[i].to]) { vis[v] = true; d[v] = d[u] + 1; que[++r] = v; } } while (l < r); return vis[t]; } long long dfs(int u, long long a) { if (u == t || a == 0) return a; long long f, flow = 0; for (int &i = cur[u], v; ~i; i = e[i].next) { if (d[u] + 1 == d[v = e[i].to] && (f = dfs(v, min(a, e[i].cap)))) { e[i].cap -= f; e[i ^ 1].cap += f; flow += f; a -= f; if (a == 0) break; } } return flow; } int main() { memset(h, -1, sizeof(h)); tot = -1; n = gi(); s = n * 2 + 1; t = s + 1; for (int t, i = 1; i <= n; ++i) { t = gi(); while (t--) add(i, gi() + n, Inf); } for (int i = 1; i <= n; ++i) add(i + n, t, zero); for (int p, i = 1; i <= n; ++i) { scanf( %d , &p); add(s, i, zero - p); ans -= zero - p; } while (bfs()) { memset(vis, 0, sizeof(bool) * (t + 1)); memcpy(cur, h, sizeof(int) * (t + 1)); ans += dfs(s, Inf); } printf( %lld n , ans); return 0; }
|
`timescale 1ns / 1ps
`define intN 32
`define addrN 4
`include "primitives.v"
`include "tests_stream_compute_fn.v"
`include "array.v"
module tests_stream_compute_fn_tb;
localparam N = 16;
`wire(Array, (`addrN, `intN), arr);
wire `intT res;
integer write_seed = 21;
integer read_seed = 42;
`reg(stream, `intN, sRA);
`wire(stream, `intN, sR);
`reg(stream, `intN, sWA);
`reg(stream, `intN, sW);
`wire(stream, 1, sB);
`wire(stream, 1, sC);
assign sR_ready = out_ready;
assign sB_ready = out_ready;
assign sC_ready = out_ready;
integer counter = 0;
`testbench(tests_stream_compute_fn_tb, 15.45)
// Use bit 31 to indicate that data is invalid
array #(.N(N), .INIT_ADDR(0), .INIT(0))
array(.clk(clk),
`out(Array, 0, arr));
`in_ready(inst);
`inst_sync(tests_stream_compute_fn, inst, #())(
`sync(in_valid, out_ready),
`in(Array, 0, arr),
`in(stream, 1, sRA),
`in(stream, 2, sWA),
`in(stream, 3, sW),
`out(stream, 0, sR),
`out(null_stream, 1, sB),
`out(null_stream, 2, sC));
integer i;
integer start_time = 0;
integer max_time = 0;
integer write_time = 0;
integer max_addr = 0;
initial begin
sRA = 0;
sRA_valid = `false;
sWA = 0;
sWA_valid = `false;
sW = 0;
sW_valid = `false;
`start;
// write some data
for(i = 0; i < N; i = i + 1) begin
start_time = counter;
sWA = i;
sWA_valid = `true;
sW = i + 1;
sW_valid = `true;
`wait_for(sWA_ready && sW_ready);
write_time = counter - start_time;
if(write_time > max_time) begin
max_time = write_time;
max_addr = i;
end
if($random(write_seed) & 1) begin
sWA_valid = `false;
sW_valid = `false;
@(posedge clk);
sWA_valid = `true;
sW_valid = `true;
end
end
sWA_valid = `false;
sW_valid = `false;
`wait_for(sRA >= N-1 && sR_valid);
nrst = `false;
#2;
$display("done @ %d", counter);
$display("max write time = %d @ %d", max_time, max_addr);
$finish;
end
always @(posedge clk) begin
counter <= counter + 1;
if(sRA_ready) begin
sRA_valid <= $random(read_seed);
end
if(sR_valid & sR[31]) begin
$display("arr(%d) = %d", sRA, sR[30:0]);
sRA <= sRA + 1;
end
end
endmodule // tests_stream_compute_fn_tb
|
module brush_motor_driver(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [2:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
//brush_moter_interface
output HX,
output HY
);
//Qsys controller
reg forward_back;
reg on_off;
reg [31:0] PWM_width;
reg [31:0] PWM_frequent;
reg [31:0] read_data;
assign avs_ctrl_readdata = read_data;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else if(avs_ctrl_write)
begin
case(avs_ctrl_address)
1: begin
if(avs_ctrl_byteenable[3]) PWM_frequent[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_frequent[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_frequent[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_frequent[7:0] <= avs_ctrl_writedata[7:0];
end
2: begin
if(avs_ctrl_byteenable[3]) PWM_width[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width[7:0] <= avs_ctrl_writedata[7:0];
end
3: on_off <= avs_ctrl_writedata[0];
4: forward_back <= avs_ctrl_writedata[0];
default:;
endcase
end
else begin
case(avs_ctrl_address)
0: read_data <= 32'hEA680003;
1: read_data <= PWM_frequent;
2: read_data <= PWM_width;
3: read_data <= {31'b0,on_off};
4: read_data <= {31'b0,forward_back};
default: read_data <= 32'b0;
endcase
end
end
//PWM controller
reg [31:0] PWM;
reg PWM_out;
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM <= 32'b0;
else
begin
PWM <= PWM + PWM_frequent;
PWM_out <=(PWM > PWM_width) ? 1'b0:1'b1;
end
end
//Output
wire X, Y;
assign X = forward_back?PWM_out:0;
assign Y = forward_back?0:PWM_out;
assign HX = on_off?X:0;
assign HY = on_off?Y:0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 5; int n, m; vector<vector<pair<int, int>>> adj; vector<int> dist, color; void bfs(int v) { queue<int> q; q.push(v); while (!q.empty()) { int u = q.front(); q.pop(); for (auto it : adj[u]) { int to = it.first; if (color[to] == -1) { color[to] = (it.second == 1) ? 0 : 1; } else { if (dist[to] == INF && color[to] == it.second) { dist[to] = dist[u] + 1; q.push(to); } } } } } int main() { cin >> n >> m; dist.assign(n, INF); adj.resize(n); color.assign(n, -1); dist[n - 1] = 0; for (int i = 0; i < m; ++i) { int u, v, t; cin >> u >> v >> t; u--; v--; adj[v].push_back({u, t}); } bfs(n - 1); if (dist[0] == INF) { cout << -1 << n ; } else { cout << dist[0] << n ; } for (int i = 0; i < n; ++i) { if (color[i] == -1) cout << 0; else cout << color[i]; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A2BB2OI_PP_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`timescale 1ns / 1ps
module t_chg (/*AUTOARG*/
// Outputs
passed,
// Inputs
clk, fastclk
);
input clk;
input fastclk; // surefire lint_off_line UDDIXN
output passed; reg passed; initial passed = 0;
integer _mode; initial _mode=0;
reg [31:0] ord1; initial ord1 = 32'h1111;
wire [31:0] ord2;
reg [31:0] ord3;
wire [31:0] ord4;
wire [31:0] ord5;
wire [31:0] ord6;
wire [31:0] ord7;
// verilator lint_off UNOPT
t_chg_a a (
.a(ord1), .a_p1(ord2),
.b(ord4), .b_p1(ord5),
.c(ord3), .c_p1(ord4),
.d(ord6), .d_p1(ord7)
);
// surefire lint_off ASWEMB
assign ord6 = ord5 + 1;
// verilator lint_on UNOPT
always @ (/*AS*/ord2) ord3 = ord2 + 1;
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
if (_mode==1) begin
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
//if (ord2 == 2 && ord7 != 7) $stop;
end
end
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_chg: Running\n", $time);
_mode<=1;
ord1 <= 1;
end
else if (_mode==1) begin
_mode<=2;
if (ord7 !== 7) $stop;
$write("[%0t] t_chg: Passed\n", $time);
passed <= 1'b1;
end
end
endmodule
module t_chg_a (/*AUTOARG*/
// Outputs
a_p1, b_p1, c_p1, d_p1,
// Inputs
a, b, c, d
);
input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1;
input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1;
input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1;
input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long; using LD = long double; using ULL = unsigned long long; template <class T1, class T2> using P = pair<T1, T2>; using PII = P<int, int>; using PLL = P<LL, LL>; using PLD = P<LD, LD>; template <class T> using V = vector<T>; using VI = V<int>; using VLL = V<LL>; using VLD = V<LD>; using VB = V<bool>; using VS = V<string>; template <class T, class Comp = greater<T>> using PQ = priority_queue<T, V<T>, Comp>; template <class T> int sz(const T& x) { return (int)size(x); } template <class T> bool amin(T& a, const T& b) { if (b < a) { a = b; return true; } return false; } template <class T> bool amax(T& a, const T& b) { if (b > a) { a = b; return true; } return false; } const size_t rseed = std::chrono::high_resolution_clock::now().time_since_epoch().count(); mt19937 rnd(rseed); int randint(int lo, int hi) { return uniform_int_distribution<int>{lo, hi}(rnd); } int main() { int T; scanf( %d , &T); for (int t = (1); t <= (T); t++) { int n; scanf( %d , &n); string s(n + 1, ); scanf( %s , &s[0]); string a(n, ), b(n, ); bool f = false; for (int i = (0); i <= (n - 1); i++) { if (f) { a[i] = 0 ; b[i] = s[i]; } else { if (s[i] == 1 ) { f = true; a[i] = 1 ; b[i] = 0 ; } else if (s[i] == 2 ) a[i] = b[i] = 1 ; else a[i] = b[i] = 0 ; } } printf( %s n%s n , a.c_str(), b.c_str()); } }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:12:55 07/16/2013
// Design Name:
// Module Name: fpga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fpga(
input wire input_clk,
input wire [7:0] sw,
input wire [4:0] btn,
output wire [7:0] led,
output wire [7:0] seg,
output wire [3:0] an,
output wire RsTx,
input wire RsRx
);
wire clk; // 10MHz clock
dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk)); // 100MHz -> 10MHz DCM
//assign led = sw;
// button synchronizer:
reg [4:0] btn_sync, btn_sync2;
always @(posedge clk) begin
{btn_sync, btn_sync2} <= {btn, btn_sync};
end
wire [4:0] btn_debounced;
genvar idx;
generate
for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
end
endgenerate
reg [15:0] ctr;
reg [4:0] btn_prev;
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
/*
Baud rates:
@10MHz:
115,200: 87 cycles
*/
wire uart_tx_req, uart_tx_ready;
wire [31:0] uart_rx_data;
wire uart_rx_valid;
assign uart_tx_req = uart_rx_valid;
uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbtx(.clk(clk), .data(uart_rx_data), .req(uart_tx_req), .uart_tx(RsTx));
// Input synchronizer:
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
uart_multibyte_receiver #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b1), .uart_rx(RsRx2));
always @(posedge clk) begin
if (btn_debounced[0] && !btn_prev[0]) ctr <= ctr + 1'b1;
if (btn_debounced[2] && !btn_prev[2]) ctr <= 0;
if (uart_rx_valid) begin
ctr <= uart_rx_data[15:0];
end
btn_prev <= btn_debounced;
end
endmodule
|
module TOP(CLK, RST, IN, IN2, reg1, OUT);
input CLK, RST, IN, IN2;
reg reg1,reg2,reg3;
output reg1,OUT;
wire in1;
wire OUT;
wire IN;
wire IN2;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else begin
reg1 <= IN;
end
end
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg2 <= 1'b0;
end else begin
reg2 <= func1(reg1);
end
end
SUB sub(CLK,RST,in1,OUT);
SUB2 ccc(CLK,RST,in1);
function func1;
input bit1;
if(bit1)
func1 = !bit1;
else
func1 = bit1;
endfunction
endmodule
module SUB(CLK,RST,IN, OUT);
input CLK, RST, IN;
output OUT;
reg reg1;
wire IN;
wire OUT = reg1;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else begin
reg1 <= 1'b1;
end
end
endmodule
module SUB2(input CLK,input RST,input IN, output OUT);
reg reg1;
wire IN;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else if(IN) begin
reg1 <= 1'b0;
end else begin
reg1 <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long k, b, n; long long z = 1, t; cin >> k >> b >> n >> t; for (int i = 0; i < n; i++) { if (z > t) { cout << n - i + 1 << endl; return 0; } z = z * k + b; } if (z <= t) cout << 0 << endl; else cout << 1 << endl; }
|
/*
* Copyright (c) 2000 Chris Lattner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
reg [3:0] val, y;
initial begin
val = 2;
y = !{!val};
if (y !== 4'b0001) begin
$display("FAILED -- !!4'b%b --> 4'b%b", val, y);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline void chkmin(T1 &first, T2 second) { if (first > second) first = second; } template <typename T1, typename T2> inline void chkmax(T1 &first, T2 second) { if (first < second) first = second; } const string FileName = input ; const int MAXN = 3e5 + 100; int n, k, b, c; vector<int> arr; vector<int> event[5]; long long sum, mod, ans = 1e18; multiset<long long> que; long long f(long long s, long long t) { return ((t - s) / 5) * b + ((t - s) % 5) * c; } int main(int argc, char const *argv[]) { srand(time(0)); ios::sync_with_stdio(0); cin >> n >> k >> b >> c; arr.resize(n); b = min(b, c * 5); for (int i = 0; i < n; ++i) { cin >> arr[i]; } sort(arr.begin(), arr.end()); for (int i = 0; i < n; ++i) { for (int j = 0; j < 5; ++j) { event[(((arr[i] + j) % 5) + 5) % 5].push_back(arr[i] + j); } } for (int j = 0; j < 5; ++j) { int L = 0; sum = 0, mod = 0; que.clear(); for (int i = 0; i < n; ++i) { while (L < n && arr[L] <= event[j][i]) { que.insert(-f(arr[L], event[j][i]) - mod); sum += f(arr[L], event[j][i]); ++L; } while (que.size() > k) { sum += *que.begin() + mod; que.erase(que.begin()); } if (que.size() == k) { ans = min(ans, sum); } if (i != n - 1) { assert(event[j][i] <= event[j][i + 1]); mod -= f(event[j][i], event[j][i + 1]); sum += f(event[j][i], event[j][i + 1]) * que.size(); } } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long pow2(long long n) { long long x = 1; for (long long i = 1; i <= n; i++) { x *= 2; } return x; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; cout << 2 * (n - 1) + 1 << 2 << endl; cout << 1 2 << endl; }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Computer_System_SDRAM_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 15: 0] q;
input [ 15: 0] data;
input [ 24: 0] rdaddress;
input rdclken;
input [ 24: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array [33554431: 0];
wire [ 15: 0] q;
reg [ 24: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("Computer_System_SDRAM_test_component.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 25,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Computer_System_SDRAM_test_component (
// inputs:
clk,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dqm,
zs_ras_n,
zs_we_n,
// outputs:
zs_dq
)
;
inout [ 15: 0] zs_dq;
input clk;
input [ 12: 0] zs_addr;
input [ 1: 0] zs_ba;
input zs_cas_n;
input zs_cke;
input zs_cs_n;
input [ 1: 0] zs_dqm;
input zs_ras_n;
input zs_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
wire [ 9: 0] addr_col;
reg [ 14: 0] addr_crb;
wire [ 1: 0] ba;
wire cas_n;
wire cke;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 1: 0] dqm;
wire [ 2: 0] index;
reg [ 2: 0] latency;
wire [ 1: 0] mask;
wire [ 15: 0] mem_bytes;
wire ras_n;
reg [ 24: 0] rd_addr_pipe_0;
reg [ 24: 0] rd_addr_pipe_1;
reg [ 24: 0] rd_addr_pipe_2;
reg [ 1: 0] rd_mask_pipe_0;
reg [ 1: 0] rd_mask_pipe_1;
reg [ 1: 0] rd_mask_pipe_2;
reg [ 2: 0] rd_valid_pipe;
wire [ 24: 0] read_addr;
wire [ 15: 0] read_data;
wire [ 1: 0] read_mask;
wire [ 15: 0] read_temp;
wire read_valid;
wire [ 15: 0] rmw_temp;
wire [ 24: 0] test_addr;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 15: 0] zs_dq;
initial
begin
$write("\n");
$write("************************************************************\n");
$write("This testbench includes an SOPC Builder Generated Altera model:\n");
$write("'Computer_System_SDRAM_test_component.v', to simulate accesses to SDRAM.\n");
$write("Initial contents are loaded from the file: 'Computer_System_SDRAM_test_component.dat'.\n");
$write("************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
Computer_System_SDRAM_test_component_ram_module Computer_System_SDRAM_test_component_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress ((CODE == 24'h205752) ? test_addr : read_addr),
.rdclken (1'b1),
.wraddress (test_addr),
.wrclock (clk),
.wren (CODE == 24'h205752)
);
assign cke = zs_cke;
assign cs_n = zs_cs_n;
assign ras_n = zs_ras_n;
assign cas_n = zs_cas_n;
assign we_n = zs_we_n;
assign dqm = zs_dqm;
assign ba = zs_ba;
assign a = zs_addr;
assign cmd_code = {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 0];
assign test_addr = {addr_crb, addr_col};
assign mem_bytes = read_data;
assign rmw_temp[7 : 0] = dqm[0] ? mem_bytes[7 : 0] : zs_dq[7 : 0];
assign rmw_temp[15 : 8] = dqm[1] ? mem_bytes[15 : 8] : zs_dq[15 : 8];
// Handle Input.
always @(posedge clk)
begin
// No Activity of Clock Disabled
if (cke)
begin
// LMR: Get CAS_Latency.
if (CODE == 24'h4c4d52)
latency <= a[6 : 4];
// ACT: Get Row/Bank Address.
if (CODE == 24'h414354)
addr_crb <= {ba[1], a, ba[0]};
rd_valid_pipe[2] <= rd_valid_pipe[1];
rd_valid_pipe[1] <= rd_valid_pipe[0];
rd_valid_pipe[0] <= CODE == 24'h205244;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_addr_pipe_0 <= test_addr;
rd_mask_pipe_2 <= rd_mask_pipe_1;
rd_mask_pipe_1 <= rd_mask_pipe_0;
rd_mask_pipe_0 <= dqm;
end
end
assign read_temp[7 : 0] = mask[0] ? 8'bz : read_data[7 : 0];
assign read_temp[15 : 8] = mask[1] ? 8'bz : read_data[15 : 8];
//use index to select which pipeline stage drives addr
assign read_addr = (index == 0)? rd_addr_pipe_0 :
(index == 1)? rd_addr_pipe_1 :
rd_addr_pipe_2;
//use index to select which pipeline stage drives mask
assign read_mask = (index == 0)? rd_mask_pipe_0 :
(index == 1)? rd_mask_pipe_1 :
rd_mask_pipe_2;
//use index to select which pipeline stage drives valid
assign read_valid = (index == 0)? rd_valid_pipe[0] :
(index == 1)? rd_valid_pipe[1] :
rd_valid_pipe[2];
assign index = latency - 1'b1;
assign mask = read_mask;
assign zs_dq = read_valid ? read_temp : {16{1'bz}};
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2015 12:30:30
// Design Name:
// Module Name: testcase_basic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
module testcase_basic();
harness harness();
data_memory memoria();
parameter KEY = "01234567";
parameter ROWS = 133;
parameter COLS = 200;
parameter Taddress = (ROWS * COLS) / 8;
initial
begin: injector
integer index;
harness.sync_reset();
for (index = 0; index < Taddress; index = index + 1)
begin
memoria.read(index);
harness.source.encrypt(memoria.memory_data, KEY);
end
//harness.source.encrypt("memories", "slipknot");
repeat(50)
@(posedge harness.clk);
$fclose(harness.sink.fp);
$finish;
end
endmodule // testcase_basic
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; long long gcd(long long a, long long b) { if (b == 0) { return a; } else { return gcd(b, a % b); } } void change(map<long long, long long> &m, long long n) { long long i; for (long long i = 1; i < n + 1; i++) { if (m[i] == 1) m.erase(i); else m[i]--; } return; } void solve() { long long n, i, l, t; cin >> n >> t; string ans = ; map<long long, long long> m; for (long long i = 0; i < t; i++) { cin >> l; m[l]++; if ((long long)m.size() == n) { ans += 1 ; change(m, n); } else { ans += 0 ; } } cout << ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t = 1; while (t--) { solve(); cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_4_V
`define SKY130_FD_SC_MS__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_4_V
|
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: timer.v
// Description: Wishbone based Timer
// Phase accumulator clock:
// Fo = Fc * N / 2^bits
// here N: 12507 and bits: 33
// it gives a frequency of 18.200080376 Hz
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module timer #(
parameter res = 33, // bit resolution (default: 33 bits)
parameter phase = 12507 // phase value for the counter
)
(
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
output reg wb_tgc_o // Interrupt output
);
reg [res-1:0] cnt;
reg old_clk2;
wire clk2;
// Continuous assignments
assign clk2 = cnt[res-1];
// Behaviour
always @(posedge wb_clk_i)
cnt <= wb_rst_i ? 0 : (cnt + phase);
always @(posedge wb_clk_i)
old_clk2 <= wb_rst_i ? 1'b0 : clk2;
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0 : (!old_clk2 & clk2);
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long dp[100050][205]; int redpac[100050][4]; int e[100050]; bool cmp(int x, int y) { return redpac[x][0] < redpac[y][0]; } int main() { int n, m, k, cur = 0; long long ans = -1; priority_queue<pair<int, pair<int, int> > > availablepackets; scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < k; i++) { scanf( %d%d%d%d , &redpac[i][0], &redpac[i][1], &redpac[i][2], &redpac[i][3]); e[i] = i; } sort(e, e + k, cmp); memset(dp, -1, sizeof(dp)); dp[1][0] = 0; for (int i = 1; i <= n; i++) { if (availablepackets.size() > 0) { while (availablepackets.top().second.second < i) { availablepackets.pop(); if (availablepackets.size() == 0) break; } } while (cur < k && redpac[e[cur]][0] <= i) { availablepackets.push(make_pair( redpac[e[cur]][3], make_pair(redpac[e[cur]][2], redpac[e[cur]][1]))); cur++; } for (int j = 0; j < m + 1; j++) { if (dp[i][j] == -1) continue; if (j < m && (dp[i + 1][j + 1] > dp[i][j] || dp[i + 1][j + 1] == -1)) { dp[i + 1][j + 1] = dp[i][j]; } if (availablepackets.size() > 0) { if (dp[availablepackets.top().second.first + 1][j] > dp[i][j] + availablepackets.top().first || dp[availablepackets.top().second.first + 1][j] == -1) { dp[availablepackets.top().second.first + 1][j] = dp[i][j] + availablepackets.top().first; } } else { if (dp[i + 1][j] == -1 || dp[i + 1][j] > dp[i][j]) { dp[i + 1][j] = dp[i][j]; } } } } for (int i = 0; i < m + 1; i++) { if (dp[n + 1][i] != -1 && (ans > dp[n + 1][i] || ans == -1)) { ans = dp[n + 1][i]; } } printf( %lld , ans); }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module altera_mem_if_ddr3_phy_0001_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
reset_request_n,
ctl_reset_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
input csr_soft_reset_req;
output reset_request_n;
output ctl_reset_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign reset_request_n = pll_locked;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n & (!csr_soft_reset_req);
altera_mem_if_ddr3_phy_0001_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 5;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
altera_mem_if_ddr3_phy_0001_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (ctl_reset_n)
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 5;
altera_mem_if_ddr3_phy_0001_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
altera_mem_if_ddr3_phy_0001_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
altera_mem_if_ddr3_phy_0001_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
altera_mem_if_ddr3_phy_0001_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
altera_mem_if_ddr3_phy_0001_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
altera_mem_if_ddr3_phy_0001_reset_sync ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
module stimulus (output reg A, B);
initial begin
{A, B} = 2'b00;
#10 {A, B} = 2'b01;
#10 {A, B} = 2'b10;
#10 {A, B} = 2'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
2'b00: gate_output = 1;
2'b01: gate_output = 1;
2'b10: gate_output = 1;
2'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in NAND operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
nand_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#100;
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long inf = 1e14; long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, ans = 0; cin >> n; for (long long i = 2; i <= n; i++) { for (long long j = i + i; j <= n; j += i) { ans += (j / i); } } cout << ans * 4; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v; int main(void) { int n, m, a, b; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &a, &b); v.push_back(make_pair(b, a)); } sort(v.rbegin(), v.rend()); long long ans = 0; int i = 0; while (n) { int del = min(n, v[i].second); ans += (long long)del * v[i].first; n -= del; i++; if (i == v.size()) break; } printf( %lld n , ans); }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module vita_rx_control
#(parameter BASE=0,
parameter WIDTH=32)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [63:0] vita_time,
output overrun,
// To vita_rx_framer
output [5+64+WIDTH-1:0] sample_fifo_o,
output sample_fifo_src_rdy_o,
input sample_fifo_dst_rdy_i,
// From DSP Core
input [WIDTH-1:0] sample,
output run,
input strobe,
output [31:0] debug_rx
);
// FIXME add TX Interruption (halt, pause, continue) functionality
wire [63:0] new_time;
wire [31:0] new_command;
wire sc_pre1;
wire [63:0] rcvtime_pre;
reg [63:0] rcvtime;
wire [27:0] numlines_pre;
wire send_imm_pre, chain_pre, reload_pre, stop_pre;
reg send_imm, chain, reload;
wire read_ctrl, not_empty_ctrl, write_ctrl;
reg sc_pre2;
wire [33:0] fifo_line;
reg [27:0] lines_left, lines_total;
reg [2:0] ibs_state;
wire now, early, late;
wire sample_fifo_in_rdy;
setting_reg #(.my_addr(BASE)) sr_cmd
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(new_command),.changed());
setting_reg #(.my_addr(BASE+1)) sr_time_h
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(new_time[63:32]),.changed());
setting_reg #(.my_addr(BASE+2)) sr_time_l
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
// FIFO to store commands sent from the settings bus
always @(posedge clk)
if(reset | clear)
sc_pre2 <= 0;
else
sc_pre2 <= sc_pre1;
assign write_ctrl = sc_pre1 & ~sc_pre2;
wire [4:0] command_queue_len;
fifo_short #(.WIDTH(96)) commandfifo
(.clk(clk),.reset(reset),.clear(clear),
.datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(),
.dataout({send_imm_pre,chain_pre,reload_pre,stop_pre,numlines_pre,rcvtime_pre}),
.src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl),
.occupied(command_queue_len), .space() );
reg [33:0] pkt_fifo_line;
localparam IBS_IDLE = 0;
localparam IBS_WAITING = 1;
localparam IBS_RUNNING = 2;
localparam IBS_OVERRUN = 4;
localparam IBS_BROKENCHAIN = 5;
localparam IBS_LATECMD = 6;
localparam IBS_ZEROLEN = 7;
wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & stop_pre));
wire signal_overrun = (ibs_state == IBS_OVERRUN);
wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN);
wire signal_latecmd = (ibs_state == IBS_LATECMD);
wire signal_zerolen = (ibs_state == IBS_ZEROLEN);
// Buffer of samples for while we're writing the packet headers
wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
wire attempt_sample_write = ((run & strobe) | (ibs_state==IBS_OVERRUN) |
(ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) |
(ibs_state==IBS_ZEROLEN));
fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy),
.dataout(sample_fifo_o),
.src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
.space(), .occupied() );
// Inband Signalling State Machine
time_compare
time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late));
wire go_now = now | send_imm;
wire full = ~sample_fifo_in_rdy;
reg too_late;
always @(posedge clk)
if(reset | clear)
too_late <= 0;
else
too_late <= late & ~send_imm;
reg late_valid;
always @(posedge clk)
if(reset | clear)
begin
ibs_state <= IBS_IDLE;
lines_left <= 0;
lines_total <= 0;
rcvtime <= 0;
send_imm <= 0;
chain <= 0;
reload <= 0;
late_valid <= 0;
end
else
case(ibs_state)
IBS_IDLE :
if(not_empty_ctrl)
begin
lines_left <= numlines_pre;
lines_total <= numlines_pre;
rcvtime <= rcvtime_pre;
late_valid <= 0;
if(stop_pre)
ibs_state <= IBS_ZEROLEN;
else
ibs_state <= IBS_WAITING;
send_imm <= send_imm_pre;
chain <= chain_pre;
reload <= reload_pre;
end
IBS_WAITING :
begin
late_valid <= 1;
if(late_valid)
if(go_now)
ibs_state <= IBS_RUNNING;
else if(too_late)
ibs_state <= IBS_LATECMD;
end
IBS_RUNNING :
if(strobe)
if(full)
ibs_state <= IBS_OVERRUN;
else
begin
lines_left <= lines_left - 1;
if(lines_left == 1)
if(~chain)
ibs_state <= IBS_IDLE;
else if(~not_empty_ctrl & reload)
begin
ibs_state <= IBS_RUNNING;
lines_left <= lines_total;
end
else if(~not_empty_ctrl)
ibs_state <= IBS_BROKENCHAIN;
else
begin
lines_left <= numlines_pre;
lines_total <= numlines_pre;
rcvtime <= rcvtime_pre;
send_imm <= send_imm_pre;
chain <= chain_pre;
reload <= reload_pre;
if(stop_pre) // If we are told to stop here
ibs_state <= IBS_IDLE;
else
ibs_state <= IBS_RUNNING;
end
end // else: !if(full)
IBS_OVERRUN :
if(sample_fifo_in_rdy)
ibs_state <= IBS_IDLE;
IBS_LATECMD :
if(sample_fifo_in_rdy)
ibs_state <= IBS_IDLE;
IBS_BROKENCHAIN :
if(sample_fifo_in_rdy)
ibs_state <= IBS_IDLE;
IBS_ZEROLEN :
if(sample_fifo_in_rdy)
ibs_state <= IBS_IDLE;
endcase // case(ibs_state)
assign overrun = (ibs_state == IBS_OVERRUN);
assign run = (ibs_state == IBS_RUNNING);
assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
& not_empty_ctrl;
assign debug_rx = { { ibs_state[2:0], command_queue_len },
{ 8'd0 },
{ go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl },
{ 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
endmodule // vita_rx_control
|
#include <bits/stdc++.h> using namespace std; template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcounll(s); } template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } int k, n, m; int a[200005], b[200005]; vector<pair<int, int> > V[200005]; vector<pair<int, int> > VV; int M[200005], vt[200005]; vector<pair<long double, int> > T[200005]; vector<pair<long double, int> > TT; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); memset(M, -1, sizeof(M)); memset(vt, -1, sizeof(vt)); cin >> k >> n >> m; for (int i = (1); i <= (k); ++i) { cin >> a[i]; } for (int run = 0; run < (n); ++run) { int id, u, v; cin >> id >> u >> v; b[run + 1] = id; if (id == 1) { if (M[u] < v) { M[u] = v; vt[u] = run + 1; } } else if (id == 2) { V[u].push_back(make_pair(v, run + 1)); } else { VV.push_back(make_pair(v, run + 1)); } } sort((VV).begin(), (VV).end()); priority_queue<pair<pair<long double, int>, pair<int, int> > > que; for (int i = (1); i <= (k); ++i) { if (M[i] > a[i]) { V[i].push_back(make_pair(M[i] - a[i], vt[i])); } sort((V[i]).begin(), (V[i]).end()); long long run = a[i], temp; for (int j = ((int)(V[i]).size()) - 1; j >= 0; j--) { temp = run + V[i][j].first; T[i].push_back(make_pair(log(temp) - log(run), V[i][j].second)); run = temp; } if (((int)(V[i]).size())) { que.push( make_pair(make_pair(T[i][0].first, T[i][0].second), make_pair(i, 0))); } } long double RR = 0; while (!que.empty()) { pair<long double, int> PP = que.top().first; long double x = PP.first; int t = PP.second; pair<int, int> P = que.top().second; int u = P.first, v = P.second; que.pop(); if (((int)(T[u]).size()) >= v + 2) { que.push(make_pair(make_pair(T[u][v + 1].first, T[u][v + 1].second), make_pair(u, v + 1))); } RR += x; TT.push_back(make_pair(RR, t)); } RR = 0; long double MAX = -1; int vt = -1; for (int i = 0; i <= ((int)(VV).size()); i++) { if (i > m) break; int u = min(m - i, ((int)(TT).size())); u--; long double x; if (u >= 0) x = TT[u].first; else x = 0; if (MAX < x + RR) { MAX = x + RR; vt = i; } if (i < ((int)(VV).size())) RR += log(VV[((int)(VV).size()) - i - 1].first); } int u = min(m - vt, ((int)(TT).size())); cout << u + vt << endl; vector<pair<int, int> > res; for (int i = 1; i <= vt; i++) res.push_back(make_pair(b[VV[((int)(VV).size()) - i].second], VV[((int)(VV).size()) - i].second)); for (int i = 0; i < u; i++) res.push_back(make_pair(b[TT[i].second], TT[i].second)); sort((res).begin(), (res).end()); for (int i = 0; i < (((int)(res).size())); ++i) cout << res[i].second << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> edge[110000]; vector<pair<int, int> > R; set<int> N; int find(int rt, int to) { int i; for (i = 0; i < edge[rt].size(); i++) { if (edge[rt][i] == to) return 1; } return 0; } int dfs(int rt) { if (R.size() == m || R.size() == n - 1) return 1; N.erase(rt); set<int>::iterator it; for (it = N.begin(); it != N.end(); it++) { if (find(rt, *it)) continue; R.push_back(make_pair(rt, *it)); if (dfs(*it)) return 1; R.pop_back(); it = N.find(*it); } N.insert(rt); return 0; } int main() { int a, b, i; scanf( %d%d , &n, &m); for (i = 1; i <= m; i++) { scanf( %d%d , &a, &b); edge[a].push_back(b); edge[b].push_back(a); } for (i = 1; i <= n; i++) { N.insert(i); } for (i = 1; i <= n; i++) { if (dfs(i)) { if (n == m) R.push_back(make_pair(R[0].first, R[R.size() - 1].second)); for (i = 0; i < m; i++) printf( %d %d n , R[i].first, R[i].second); return 0; } } puts( -1 ); return 0; }
|
module rf(clk,p0_addr,p1_addr,p0,p1,re0,re1,dst_addr,dst,we,hlt);
//////////////////////////////////////////////////////////////////
// Triple ported register file. Two read ports (p0 & p1), and //
// one write port (dst). Data is written on clock high, and //
// read on clock low //////////////////////////////////////////
//////////////////////
input clk;
input [3:0] p0_addr, p1_addr; // two read port addresses
input re0,re1; // read enables (power not functionality)
input [3:0] dst_addr; // write address
input [15:0] dst; // dst bus
input we; // write enable
input hlt; // not a functional input. Used to dump register contents when
// test is halted.
output reg [15:0] p0,p1; //output read ports
integer indx;
reg [15:0]mem[0:15];
/*
reg [3:0] dst_addr_lat; // have to capture dst_addr from previous cycle
reg [15:0] dst_lat; // have to capture write data from previous cycle
reg we_lat; // have to capture we from previous cycle
*/
//////////////////////////////////////////////////////////
// Register file will come up uninitialized except for //
// register zero which is hardwired to be zero. //
///////////////////////////////////////////////////////
initial begin
mem[0] = 16'h0000; // reg0 is always 0,
end
/*
//////////////////////////////////////////////////
// dst_addr, dst, & we all need to be latched //
// on clock low of previous cycle to maintain //
// in clock high write of next cycle. //
//////////////////////////////////////////////
always @(clk,dst_addr,dst,we)
if (~clk)
begin
dst_addr_lat <= dst_addr;
dst_lat <= dst;
we_lat <= we;
end
*/
//////////////////////////////////
// RF is written on clock high //
////////////////////////////////
always @(clk,we,dst_addr,dst)
if (clk && we && |dst_addr)
mem[dst_addr] <= dst;
//////////////////////////////
// RF is read on clock low //
////////////////////////////
always @(clk,re0,p0_addr)
if (~clk && re0)
p0 <= mem[p0_addr];
//////////////////////////////
// RF is read on clock low //
////////////////////////////
always @(clk,re1,p1_addr)
if (~clk && re1)
p1 <= mem[p1_addr];
////////////////////////////////////////
// Dump register contents at program //
// halt for debug purposes //
/////////////////////////////////////
always @(posedge hlt)
for(indx=1; indx<16; indx = indx+1)
$display("R%1h = %h",indx,mem[indx]);
endmodule
|
module sm (/*AUTOARG*/);
//==================== Constant declarations ==============
`include "autoasciienum_param.v"
//==================== Intermediate Variables =============
reg [3:0] /* synopsys enum En_C14ChipNum */ chip_r;
//==================== DEBUG ASCII CODE =========================
/*AUTOASCIIENUM("chip_r", "chip_r__ascii","Ep_C14ChipNum_")*/
// Beginning of automatic ASCII enum decoding
reg [31:0] chip_r__ascii; // Decode of chip_r
always @(chip_r) begin
case ({chip_r})
EP_C14ChipNum_RNP: chip_r__ascii = "rnp ";
EP_C14ChipNum_SPP: chip_r__ascii = "spp ";
EP_C14ChipNum_SRP: chip_r__ascii = "srp ";
EP_C14ChipNum_SMM2: chip_r__ascii = "smm2";
EP_C14ChipNum_SMM: chip_r__ascii = "smm ";
EP_C14ChipNum_TTE: chip_r__ascii = "tte ";
EP_C14ChipNum_DLE: chip_r__ascii = "dle ";
EP_C14ChipNum_OASP: chip_r__ascii = "oasp";
default: chip_r__ascii = "%Err";
endcase
end
// End of automatics
endmodule
//==== Emacs verilog-mode controls ====
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
`ifdef POWER_GATING
`undef POWER_GATING
`endif
module mbus_general_layer_wrapper(
input CLK_EXT,
input MASTER_EN,
input mbus_snoop_enabled,
input [19:0] ADDRESS,
input [`DYNA_WIDTH-1:0] ASSIGNED_ADDR_IN,
output [`DYNA_WIDTH-1:0] ASSIGNED_ADDR_OUT,
input ASSIGNED_ADDR_VALID,
output ASSIGNED_ADDR_WRITE,
output ASSIGNED_ADDR_INVALIDn,
input CLKIN,
output CLKOUT,
input RESETn,
input DIN,
output DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
input TX_PRIORITY,
output TX_ACK,
output [`ADDR_WIDTH-1:0] RX_ADDR,
output [`DATA_WIDTH-1:0] RX_DATA,
output RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output RX_FAIL,
output RX_PEND,
output [1:0] ice_export_control_bits,
output TX_FAIL,
output TX_SUCC,
input TX_RESP_ACK
`ifdef POWER_GATING
// power gated signals from sleep controller
input MBC_RESET,
// power gated signals to layer controller
output LRC_SLEEP,
output LRC_CLKENB,
output LRC_RESET,
output LRC_ISOLATE,
// wake up bus controller
input EXTERNAL_INT,
output CLR_EXT_INT,
output CLR_BUSY,
// wake up processor
output reg SLEEP_REQUEST_TO_SLEEP_CTRL,
`endif
);
parameter THRESHOLD = 20'h05fff;
wire CLK_CTRL_TO_NODE;
wire DOUT_CTRL_TO_NODE;
wire NODE_RX_REQ;
wire NODE_RX_ACK;
`ifdef POWER_GATING
wire SLEEP_REQ;
`endif
reg ctrl_addr_match, ctrl_rx_ack;
`ifdef POWER_GATING
wire RESETn_local = (RESETn & (~MBC_RESET) & MASTER_EN);
`else
wire RESETn_local = RESETn & MASTER_EN;
`endif
wire dout_from_bus, clkout_from_bus;
wire clkin = (MASTER_EN==1'b1)? CLK_CTRL_TO_NODE : CLKIN;
wire din = (MASTER_EN==1'b1)? DOUT_CTRL_TO_NODE : DIN;
always @ *
begin
if ((RX_BROADCAST) && (RX_ADDR[`FUNC_WIDTH-1:0]==`CHANNEL_CTRL))
ctrl_addr_match = 1;
else
ctrl_addr_match = 0;
end
assign RX_REQ = (ctrl_addr_match & MASTER_EN)? 1'b0 : NODE_RX_REQ;
always @ (posedge CLK_EXT or negedge RESETn_local)
begin
if (~RESETn_local)
begin
ctrl_rx_ack <= 0;
`ifdef POWER_GATING
SLEEP_REQUEST_TO_SLEEP_CTRL <= 0;
`endif
end
else
begin
if (ctrl_addr_match & NODE_RX_REQ)
begin
ctrl_rx_ack <= 1;
end
if (ctrl_rx_ack & (~NODE_RX_REQ))
ctrl_rx_ack <= 0;
`ifdef POWER_GATING
// delay 1 cycle
SLEEP_REQUEST_TO_SLEEP_CTRL <= SLEEP_REQ;
`endif
end
end
assign NODE_RX_ACK = (RX_ACK | ctrl_rx_ack);
mbus_ctrl ctrl0(
.CLK_EXT(CLK_EXT),
.RESETn(RESETn_local),
.CLKIN(CLKIN),
.CLKOUT(CLK_CTRL_TO_NODE),
.DIN(DIN),
.DOUT(DOUT_CTRL_TO_NODE),
.THRESHOLD(THRESHOLD)
);
mbus_node node0(
.CLKIN(clkin),
.RESETn(RESETn),
.DIN(din),
.CLKOUT(clkout_from_bus),
.DOUT(dout_from_bus),
.TX_ADDR(TX_ADDR),
.TX_DATA(TX_DATA),
.TX_PEND(TX_PEND),
.TX_REQ(TX_REQ),
.TX_PRIORITY(TX_PRIORITY),
.TX_ACK(TX_ACK),
.RX_ADDR(RX_ADDR),
.RX_DATA(RX_DATA),
.RX_REQ(NODE_RX_REQ),
.RX_ACK(NODE_RX_ACK),
.RX_BROADCAST(RX_BROADCAST),
.RX_FAIL(RX_FAIL),
.RX_PEND(RX_PEND),
.ice_export_control_bits(ice_export_control_bits),
.TX_FAIL(TX_FAIL),
.TX_SUCC(TX_SUCC),
.TX_RESP_ACK(TX_RESP_ACK),
`ifdef POWER_GATING
.MBC_RESET(MBC_RESET),
.LRC_SLEEP(LRC_SLEEP),
.LRC_CLKENB(LRC_CLKENB),
.LRC_RESET(LRC_RESET),
.LRC_ISOLATE(LRC_ISOLATE),
.SLEEP_REQUEST_TO_SLEEP_CTRL(SLEEP_REQ),
.EXTERNAL_INT(EXTERNAL_INT),
.CLR_EXT_INT(CLR_EXT_INT),
.CLR_BUSY(CLR_BUSY),
`endif
.ASSIGNED_ADDR_IN(ASSIGNED_ADDR_IN),
.ASSIGNED_ADDR_OUT(ASSIGNED_ADDR_OUT),
.ASSIGNED_ADDR_VALID(ASSIGNED_ADDR_VALID),
.ASSIGNED_ADDR_WRITE(ASSIGNED_ADDR_WRITE),
.ASSIGNED_ADDR_INVALIDn(ASSIGNED_ADDR_INVALIDn),
.MASTER_EN(MASTER_EN),
.mbus_snoop_enabled(mbus_snoop_enabled),
.ADDRESS(ADDRESS)
);
mbus_wire_ctrl wc0(
.RESETn(RESETn),
.DOUT_FROM_BUS(dout_from_bus),
.CLKOUT_FROM_BUS(clkout_from_bus),
.DOUT(DOUT),
.CLKOUT(CLKOUT)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 301; int main() { int n; scanf( %d , &n); vector<map<int, int> > rank(n); for (int i = 0; i < (n); ++i) { for (int j = 0; j < (n); ++j) { int a; scanf( %d , &a); --a; rank[i][a] = j; } } vector<int> my(n); for (int i = 0; i < (n); ++i) { scanf( %d , &my[i]); --my[i]; } vector<int> ans(n), val(n); fill(val.begin(), val.end(), n); for (int i = 0; i < (n); ++i) { int tar = -1; for (int j = 0; j < (n); ++j) if (my[j] <= i) { tar = my[j]; break; } for (int j = 0; j < (n); ++j) { if (j == tar) continue; int r = rank[j][tar]; if (val[j] > r) { val[j] = r; ans[j] = i; } } for (int j = 0; j < (n); ++j) if (my[j] != tar && my[j] <= i) { int k = my[j]; int r = rank[tar][k]; if (val[tar] > r) { val[tar] = r; ans[tar] = i; } break; } } for (int i = 0; i < (n); ++i) { printf( %d , ans[i] + 1); if (i < n - 1) putchar( ); else putchar( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class _T> inline _T sqr(const _T &first) { return first * first; } template <class _T> inline string tostr(const _T &a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795L; const long double EPS = 1e-9; char TEMPORARY_CHAR; const int INF = 1e9; inline void fft(vector<complex<long double> > &a, bool invert) { int n = (int)a.size(); for (int i = 1, j = 0; i < n; ++i) { int bit = n >> 1; for (; j >= bit; bit >>= 1) j -= bit; j += bit; if (i < j) swap(a[i], a[j]); } for (int len = 2; len <= n; len <<= 1) { long double ang = 2 * PI / len * (invert ? -1 : 1); complex<long double> wlen(cos(ang), sin(ang)); for (int i = 0; i < n; i += len) { complex<long double> w(1); for (int j = 0; j < len / 2; ++j) { complex<long double> u = a[i + j], v = a[i + j + len / 2] * w; a[i + j] = u + v; a[i + j + len / 2] = u - v; w *= wlen; } } } if (invert) for (int i = 0; i < n; ++i) a[i] /= n; } inline void input(int &a) { a = 0; while (((TEMPORARY_CHAR = getchar()) > 9 || TEMPORARY_CHAR < 0 ) && (TEMPORARY_CHAR != - )) { } char neg = 0; if (TEMPORARY_CHAR == - ) { neg = 1; TEMPORARY_CHAR = getchar(); } while (TEMPORARY_CHAR <= 9 && TEMPORARY_CHAR >= 0 ) { a = (a << 3) + (a << 1) + TEMPORARY_CHAR - 0 ; TEMPORARY_CHAR = getchar(); } if (neg) a = -a; } inline void out(long long a) { if (!a) putchar( 0 ); if (a < 0) { putchar( - ); a = -a; } char s[20]; int i; for (i = 0; a; ++i) { s[i] = 0 + a % 10; a /= 10; } for (int j = (i)-1; j >= 0; j--) putchar(s[j]); } inline int nxt() { int(ret); input((ret)); ; return ret; } struct lnum { vector<int> a; int base; lnum(int num = 0, int base = 1000000000) : base(base) { if (!num) a.resize(1); while (num) { a.push_back(num % base); num /= base; } } inline int len() const { return a.size(); } lnum &operator=(const lnum &l) { if (this != &l) { a = l.a; base = l.base; } return *this; } inline friend lnum operator+(const lnum &l, const lnum &r) { lnum ret(0, l.base); int base = l.base; int ln = l.len(), rn = r.len(); int n = max(ln, rn); ret.a.resize(n); int o = 0; for (int i = 0; i < n; ++i) { int s = o; if (i < ln) s += l.a[i]; if (i < rn) s += r.a[i]; o = s >= base; if (o) s -= base; ret.a[i] = s; } if (o) ret.a.push_back(1); return ret; } inline friend lnum operator-(const lnum &l, const lnum &r) { lnum ret(0, l.base); int base = l.base; int n = l.len(); int rn = r.len(); ret.a.resize(n); int o = 0; for (int i = 0; i < n; ++i) { int s = l.a[i] - o; if (i < rn) s -= r.a[i]; o = s < 0; if (o) s += base; ret.a[i] = s; } if (ret.len() > 1 && !ret.a.back()) ret.a.pop_back(); return ret; } inline friend lnum operator*(const lnum &l, const lnum &r) { lnum ret(0, l.base); int base = l.base; if (l.len() * r.len() > 1000000) { vector<complex<long double> > fa(l.a.begin(), l.a.end()), fb(r.a.begin(), r.a.end()); int n = 1; while (n < max(l.len(), r.len())) n <<= 1; n <<= 1; fa.resize(n), fb.resize(n); fft(fa, false), fft(fb, false); for (int i = 0; i < n; ++i) fa[i] *= fb[i]; fft(fa, true); ret.a.resize(n); for (int i = 0; i < n; ++i) ret.a[i] = int(fa[i].real() + 0.5); int carry = 0; for (int i = 0; i < n; ++i) { ret.a[i] += carry; carry = ret.a[i] / base; ret.a[i] %= base; } } else { ret.a.resize(l.len() + r.len()); for (int i = 0; i < l.len(); ++i) for (int j = 0, carry = 0; j < r.len() || carry; ++j) { long long cur = ret.a[i + j] + (long long)l.a[i] * (j < r.len() ? r.a[j] : 0) + carry; ret.a[i + j] = cur % base; carry = cur / base; } } while (ret.len() > 1 && !ret.a.back()) ret.a.pop_back(); return ret; } inline friend lnum operator/(const lnum &l, const int &r) { lnum ret(0, l.base); ret.a.resize(l.len()); int carry = 0; for (int i = l.len() - 1; i >= 0; --i) { long long cur = l.a[i] + (long long)carry * l.base; ret.a[i] = cur / r; carry = cur % r; } while (ret.len() > 1 && ret.a.back() == 0) ret.a.pop_back(); return ret; } inline friend bool operator<(const lnum &l, const lnum &r) { if (l.len() < r.len()) return true; if (l.len() > r.len()) return false; int n = l.len(); for (int i = n - 1; i >= 0; --i) { if (l.a[i] < r.a[i]) return true; if (l.a[i] > r.a[i]) return false; } return false; } inline friend bool operator>(const lnum &l, const lnum &r) { return r < l; } inline friend bool operator==(const lnum &l, const lnum &r) { if (l.len() != r.len()) return false; int n = l.len(); for (int i = n - 1; i; --i) { if (l.a[i] != r.a[i]) return false; } return true; } inline friend bool operator!=(const lnum &l, const lnum &r) { return !(l == r); } inline void print() { if (base == 1000000000) { printf( %d , a.back()); for (int i = a.size() - 2; i >= 0; --i) printf( %09d , a[i]); } else { for (int i = a.size() - 1; i >= 0; --i) printf( %d , a[i]); } } }; int main() { string s; cin >> s; int n = s.length(); int ans[n][n]; memset((ans), 0, sizeof(ans)); for (int i = 0; i < n; ++i) for (int j = i; j < n; ++j) for (int k = 0; k < (j - i + 1) / 2; ++k) if (s[i + k] != s[j - k]) ++ans[i][j]; int(k); input((k)); ; int dp[n + 1][k + 1]; int p[n + 1][k + 1]; for (int i = 0; i <= n; ++i) for (int j = 0; j <= k; ++j) dp[i][j] = 1e9; dp[0][0] = 0; for (int i = 0; i < n; ++i) for (int j = 1; j <= k; ++j) for (int l = 0; l <= i; ++l) if (dp[i + 1][j] > dp[l][j - 1] + ans[l][i]) { dp[i + 1][j] = dp[l][j - 1] + ans[l][i]; p[i + 1][j] = l; } int best = 1; for (int i = 1; i <= k; ++i) if (dp[n][i] < dp[n][best]) best = i; cout << dp[n][best] << endl; vector<string> t; int cur = n; while (best) { t.push_back(s.substr(p[cur][best], cur - p[cur][best])); cur = p[cur][best]; --best; } reverse((t).begin(), (t).end()); for (int i = 0; i < t.size(); ++i) { if (i) cout << + ; for (int j = 0; j < t[i].length(); ++j) if (t[i][j] != t[i][t[i].length() - 1 - j]) t[i][j] = t[i][t[i].length() - 1 - j]; cout << t[i]; } cout << endl; }
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "../../vtr/dff/dff.sim.v"
`include "../dsp_combinational/dsp_combinational.sim.v"
/* DSP Block with register on all inputs */
module DSP_IN_REGISTERED (clk, a, b, m, out);
localparam DATA_WIDTH = 4;
input wire clk;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
output wire [DATA_WIDTH-1:0] out;
/* Input registers */
(* pack="DFF2DSP" *)
wire [DATA_WIDTH/2-1:0] q_a;
(* pack="DFF2DSP" *)
wire [DATA_WIDTH/2-1:0] q_b;
(* pack="DFF2DSP" *)
wire q_m;
genvar i;
for (i=0; i<DATA_WIDTH/2; i=i+1) begin
DFF q_a_ff(.D(a[i]), .Q(q_a[i]), .CLK(clk));
DFF q_b_ff(.D(b[i]), .Q(q_b[i]), .CLK(clk));
end
DFF m_ff(.D(m), .Q(q_m), .CLK(clk));
/* Combinational Logic */
DSP_COMBINATIONAL comb (.a(q_a), .b(q_b), .m(q_m), .out(out));
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; long long n; bool len(char x) { return x == a || x == e || x == i || x == o || x == u || x == y ; } int main() { cin >> n; cin >> s; cout << s[0]; for (int i = 1; i < n; i++) { if (len(s[i]) && len(s[i - 1])) continue; cout << s[i]; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T_container, typename T = typename enable_if< !is_same<T_container, string>::value, typename T_container::value_type>::type> ostream &operator<<(ostream &os, const T_container &v) { os << [ ; string sep; for (const T &x : v) os << sep << x, sep = , ; return os << ] ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } void run_case() { int N; cin >> N; vector<int> A(N); for (int &a : A) cin >> a; int MX = *max_element(A.begin(), A.end()) / 3 + 100; int best = MX; for (int ones = 0; ones <= 2; ++ones) for (int twos = 0; twos <= 2; ++twos) { int threes = 0; for (int a : A) { int least = MX; for (int one = 0; one <= ones; ++one) for (int two = 0; two <= twos; ++two) { int want = a - two * 2 - one; if (want % 3 != 0 || want < 0) continue; least = min(least, want / 3); } threes = max(threes, least); } best = min(best, ones + twos + threes); } cout << best << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int tests; cin >> tests; while (tests--) run_case(); }
|
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } const int N = 1e5 + 7; const int xinc[] = {0, 0, 1, -1}; const int yinc[] = {1, -1, 0, 0}; const long double PI = acos(-1.0); const double EPS = 1e-9; string s; long long a, n, sum[4007], ans; map<long long, long long> m; void solve() { cin >> a >> s; n = s.size(); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + s[i - 1] - 0 ; long long t = 0; for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) { long long psum = sum[j] - sum[i - 1]; m[psum]++; t++; } for (auto i : m) { long long psum = i.first; if (psum != 0 && a != 0 && a % psum == 0) { long long cur = m[a / psum] * i.second; ans += cur; } if (a == 0) { if (psum == 0) ans += m[psum] * t; else ans += m[psum] * m[0]; } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int nmax = 100005; const long long inf = 1e9; const double eps = 1e-6; long long dp[1005][1005]; long long gp[1005][1005]; long long a[1005][1005]; long long rdp[1005][1005]; long long rgp[1005][1005]; int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> a[i][j]; } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { dp[i][j] = max(dp[i - 1][j], dp[i][j - 1]) + a[i][j]; } } for (int i = n; i; --i) { for (int j = m; j; --j) { rdp[i][j] = max(rdp[i][j + 1], rdp[i + 1][j]) + a[i][j]; } } for (int i = n; i; --i) { for (int j = 1; j <= m; ++j) { gp[i][j] = max(gp[i + 1][j], gp[i][j - 1]) + a[i][j]; } } for (int i = 1; i <= n; ++i) { for (int j = m; j; --j) { rgp[i][j] = max(rgp[i - 1][j], rgp[i][j + 1]) + a[i][j]; } } long long ans = 0; for (int i = 2; i < n; ++i) { for (int j = 2; j < m; ++j) { ans = max(ans, dp[i][j - 1] + rdp[i][j + 1] + gp[i + 1][j] + rgp[i - 1][j]); ans = max(ans, dp[i - 1][j] + rdp[i + 1][j] + gp[i][j - 1] + rgp[i][j + 1]); } } cout << ans << n ; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 6-Bit Look-Up Table with Two Outputs
// /___/ /\ Filename : LUT6_2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 08/08/06 - Initial version.
// 06/04/07 - Change timescale form 100ps/10ps to 1ps/1ps.
// Add wire definition.
// 06/19/07 - 441956 - Add LOC Parameter
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 09/12/16 - ANSI ports, speed improvements
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module LUT6_2 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000
)(
output O5,
output O6,
input I0,
input I1,
input I2,
input I3,
input I4,
input I5
);
// define constants
localparam MODULE_NAME = "LUT6_2";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "LUT6_2_dr.v"
`else
reg [63:0] INIT_REG = INIT;
`endif
// begin behavioral model
reg O5_out;
reg O6_out;
assign O5 = O5_out;
assign O6 = O6_out;
function lut_mux4_f;
input [3:0] d;
input [1:0] s;
begin
if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0))
lut_mux4_f = d[s];
else if ( ~(|d) || &d)
lut_mux4_f = d[0];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}]))
lut_mux4_f = d[{1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}]))
lut_mux4_f = d[{s[1],1'b0}];
else
lut_mux4_f = 1'bx;
end
endfunction
function lut_mux8_f;
input [7:0] d;
input [2:0] s;
begin
if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0))
lut_mux8_f = d[s];
else if ( ~(|d) || &d)
lut_mux8_f = d[0];
else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) &&
(d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}]))
lut_mux8_f = d[{1'b0,s[1:0]}];
else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) &&
(d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}]))
lut_mux8_f = d[{s[2],1'b0,s[0]}];
else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) &&
(d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}]))
lut_mux8_f = d[{s[2:1],1'b0}];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}]))
lut_mux8_f = d[{1'b0,1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}]))
lut_mux8_f = d[{1'b0,s[1],1'b0}];
else if (((s[2] === 1'b1) || (s[2] === 1'b0)) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}]))
lut_mux8_f = d[{s[2],1'b0,1'b0}];
else
lut_mux8_f = 1'bx;
end
endfunction
always @(I0 or I1 or I2 or I3 or I4) begin
if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b1)
O5_out = INIT_REG[{I4, I3, I2, I1, I0}];
else if ( ~(|INIT_REG[31:0]) || &INIT_REG[31:0] )
O5_out = INIT_REG[0];
else
O5_out = lut_mux4_f ({lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}),
lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I4, I3});
end
always @(I0 or I1 or I2 or I3 or I4 or I5) begin
if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b1)
O6_out = INIT_REG[{I5, I4, I3, I2, I1, I0}];
else if ( ~(|INIT_REG) || &INIT_REG )
O6_out = INIT_REG[0];
else
O6_out = lut_mux8_f ({lut_mux8_f (INIT_REG[63:56], {I2, I1, I0}),
lut_mux8_f (INIT_REG[55:48], {I2, I1, I0}),
lut_mux8_f (INIT_REG[47:40], {I2, I1, I0}),
lut_mux8_f (INIT_REG[39:32], {I2, I1, I0}),
lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}),
lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I5, I4, I3});
end
// end behavioral model
`ifdef XIL_TIMING
specify
(I0 => O5) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I4 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
(I5 => O6) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; bool check(int a, int b) { bool dig[10] = {0}; while (a > 0) { dig[a % 10] = true; a /= 10; } while (b > 0) { if (dig[b % 10]) { return true; } b /= 10; } return false; } int main() { int a; cin >> a; int i, s = 0; for (i = 1; i * i <= a; i++) { if (a % i == 0) { if (check(a, i)) { s++; } if (i != a / i && check(a, a / i)) { s++; } } } cout << s << endl; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cclk_inv_64x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_cclk_inv_64x.behV
// --------------------------------------------------
//
module bw_clk_cclk_inv_64x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; const int M = 1e4 + 5; int n, m, w, vis[N], l[N], r[N]; long long a[N], ans[N], s; int main() { cin >> n >> s; long long sum = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; } if (sum < s) { cout << -1 << endl; return 0; } else if (sum == s) { cout << 0 << endl; return 0; } sort(a + 1, a + 1 + n); int now = 1; sum = s; while (a[now] == a[1]) { now++; } for (int i = n; i >= now; i--) { sum -= (a[i] - a[1]); } if (sum) { int cnt = 0; while (sum > 0) { sum -= n; cnt++; } cout << a[1] - cnt << endl; } else { cout << a[1] << endl; } return 0; }
|
`timescale 1ns/1ns
/*
* Trial test bench for clock switching between two asynchronous clocks
*
* Enable the `define STOP_IN_PHI1_D to stop the clocks low for the handover, and omit it to stop in PHI2.
*
* When stopping in PHI1 the clock selection signal must only change in PHI1. Similarly if stopping in PHI2 the
* selection signal must change only in PHI2.
*
* ie for Beeb816 there's not much time to detect whether to switch to the low speed clock when running in a
* high speed mode if STOP_ON_PHI1 is selected - this is probably why we defaulted to stopping in PHI2 instead.
*
*/
//`define STOP_IN_PHI1_D 1
`ifdef STOP_IN_PHI1_D
// to stop in PHI1 enable must be asserted with clock low
`define CHANGEDGE negedge
`else
// to stop in PHI2 enable must be asserted with clock high
`define CHANGEDGE posedge
`endif
`define LSCLK_HALF_CYCLE 500
`define HSCLK_HALF_CYCLE 30
module retimer(clk, din, rst_b, dout);
input din;
input clk;
input rst_b;
output dout;
reg r1_q, r2_q;
assign dout = r2_q & din;
always @ ( `CHANGEDGE clk or negedge rst_b )
if ( !rst_b)
{ r1_q, r2_q} <= 0;
else
{ r1_q, r2_q} <= {din, r1_q};
endmodule
module clkctrl_tb ;
reg reset_b_r;
reg hsclk_by2_r;
reg hsclk_by4_r;
reg lsclk_r;
reg hsclk_r;
reg hienable_r;
wire clkout;
wire loselect_w;
wire hiselect_w;
wire cpuclk_w;
`ifdef STOP_IN_PHI1_D
assign clkout = (hiselect_w & hienable_r & hsclk_by4_r ) | (!hienable_r & loselect_w & lsclk_r);
`else
assign clkout = (!hiselect_w | !hienable_r | hsclk_by4_r ) & (hienable_r | !loselect_w | lsclk_r);
`endif
initial
begin
$dumpvars();
reset_b_r = 0;
lsclk_r = 0;
hsclk_r = 0;
hienable_r = 0;
#500 reset_b_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#10 hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#10 hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#25 hienable_r = 1;
#10000 $finish();
end
always
#`LSCLK_HALF_CYCLE lsclk_r = !lsclk_r ;
always
#`HSCLK_HALF_CYCLE hsclk_r = !hsclk_r ;
always @ (negedge reset_b_r or posedge hsclk_r )
if ( !reset_b_r)
{ hsclk_by2_r, hsclk_by4_r } <= 0;
else
begin
hsclk_by2_r <= !hsclk_by2_r;
hsclk_by4_r <= hsclk_by2_r ^ hsclk_by4_r;
end
retimer ls_retime ( lsclk_r, !hienable_r & !hiselect_w, reset_b_r, loselect_w);
retimer hs_retime ( hsclk_by4_r, hienable_r & !loselect_w, reset_b_r, hiselect_w);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(const T &a) { return a * a; } int x, k, timer, n[3], t[3], y[3], head[3], tail[3]; pair<int, int> z[3][100000]; int main() { scanf( %d%d%d%d%d%d%d , &k, &n[0], &n[1], &n[2], &t[0], &t[1], &t[2]); while (1) { timer++; if (timer >= t[0] + t[1] + t[2]) { for (int i = 0; i < (int)3; i++) if (z[i][tail[i]].first == timer) y[i] -= z[i][tail[i]].second, tail[i]++; x = min(n[2] - y[2], min(n[1] - y[1], n[0] - y[0])); if (x) { k -= x; y[2] += x, y[1] += x, y[0] += x; z[0][head[0]++] = make_pair(timer + t[0], x); z[1][head[1]++] = make_pair(timer + t[1], x); z[2][head[2]++] = make_pair(timer + t[2], x); } if (k <= 0) { printf( %d n , timer); return 0; } } } }
|
#include <bits/stdc++.h> using namespace std; long long int f1(long int x, long int a) { if ((x < 0 && x > (-1 * ((double)a) / 2)) || (x > 0 && x < ((double)a) / 2) || x == 0) return 1; else return 0; } long long int f2(long long int x, long long int a) { if ((x < 0 && x > (-1 * ((double)a))) || (x > 0 && x < ((double)a))) return 1; else return 0; } int main() { long long int x, y, a, num, p, flag = 1, ans; cin >> a >> x >> y; num = (y - a) % (2 * a); ans = (y - a - num) / a; ans = 1 + (ans / 2) * 3; p = num / a; if (p * a == num) flag = 0; else { if (y < a) { if (!f1(x, a)) flag = 0; } else { if (p < 1) { if (f1(x, a)) ans += 1; else flag = 0; } else { if (f2(x, a)) { if (x < 0) ans += 2; else ans += 3; } else flag = 0; } } } if (flag) cout << ans; else cout << -1; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; const int maxn = 1e6 + 100; const double EPS = 1e-12; struct point { double x, y; }; string a[11] = { zero , one , two , three , four , five , six , seven , eight , nine , ten }; string b[11] = { , , twen , thir , for , fif , six , seven , eigh , nine }; string c[11] = { , , , thir , four , fif , six , seven , eigh , nine }; int n; int main() { cin >> n; if (n <= 10) { cout << a[n] << endl; return 0; } if (n < 20) { if (n == 11) cout << eleven << endl; else if (n == 12) cout << twelve << endl; else cout << c[n % 10] << teen << endl; return 0; } if (n % 10 == 0) { cout << b[n / 10] << ty << endl; return 0; } cout << b[n / 10] << ty- << a[n % 10] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; bool flag = 1; int c = 0, a[] = {5, 7, 5}, k = 0; map<char, bool> m{{ a , 1}, { e , 1}, { o , 1}, { u , 1}, { i , 1}}; while (getline(cin, s)) { c = 0; for (int i = 0; i < s.size(); i++) c += m[s[i]]; if (c != a[k]) flag = 0; k++; } if (flag == 1) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 100 * 1000 + 5; const int lim = 1000 * 1000 * 1000; const int inf = 1000 * 1000 * 1000 + 5; int f[3 * maxN]; vector<pair<int, string> > a[maxN]; string t; int ans; void dfs(int v, int F) { for (auto u : a[v]) { int tmp = F; string s = u.second; for (int i = 0; i < s.size(); i++) { while (tmp && (tmp == t.size() || t[tmp] != s[i])) tmp = f[tmp - 1]; if (t[tmp] == s[i]) tmp++; if (tmp == t.size()) ans++; } dfs(u.first, tmp); } } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 1; i < n; i++) { int par; string s; cin >> par >> s; par--; a[par].push_back(make_pair(i, s)); } cin >> t; int tmp = 0; for (int i = 1; i < t.size(); i++) { while (tmp && t[tmp] != t[i]) tmp = f[tmp - 1]; if (t[tmp] == t[i]) tmp++; f[i] = tmp; } dfs(0, 0); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[1000001]; int b[1000001], ans[1000001]; int main() { int n, h; cin >> n >> h; for (int i = 0; i < n; i++) { int c; cin >> c; a[i] = make_pair(c, i + 1); } sort(a, a + n); for (int i = 0; i < n; i++) b[i] = a[i].first; int diff = b[n - 1] + b[n - 2] - b[0] - b[1]; int km = 0; for (int k = 1; k < n; k++) { int other; int small = int(1e9); if (k >= 2) { other = b[1] + b[2]; if (other < small) small = other; } other = b[0] + b[1] + h; if (other < small) small = other; if (k < n - 1) { other = b[0] + b[k + 1]; if (other < small) small = other; } int big = b[n - 1] + h; if (k == n - 1) big += b[0]; else big += b[k]; other = b[n - 1] + b[n - 2]; if (other > big) big = other; if (big - small < diff) { diff = big - small; km = k; } } cout << diff << endl; for (int i = 1; i <= n; i++) ans[i] = 1; for (int i = 1; i <= km; i++) ans[a[i].second] = 2; for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_1_V
`define SKY130_FD_SC_LP__A21BOI_1_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_1_V
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// mix up border and pixels, add palette and blanks
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module video_palframe(
input wire clk, // 28MHz clock
input wire hpix,
input wire vpix,
input wire hblank,
input wire vblank,
input wire hsync_start,
input wire vsync,
input wire [ 3:0] pixels,
input wire [ 3:0] border,
input wire border_sync,
input wire border_sync_ena,
// ulaplus related
input wire [ 1:0] up_palsel,
input wire [ 2:0] up_paper,
input wire [ 2:0] up_ink,
input wire up_pixel,
input wire up_ena,
input wire up_palwr,
input wire [ 5:0] up_paladdr,
input wire [ 7:0] up_paldata,
input wire atm_palwr,
input wire [ 5:0] atm_paldata,
output wire [ 5:0] palcolor, // just for palette readback
output wire [ 5:0] color
);
reg [7:0] palette_read;
wire [ 3:0] zxcolor;
wire [ 5:0] up_color;
wire [ 8:0] palette_color;
reg [3:0] synced_border;
reg vsync_r;
reg [1:0] ctr_14;
reg ctr_h;
reg ctr_v;
always @(posedge clk)
if( border_sync )
synced_border <= border;
assign zxcolor = (hpix&vpix) ? pixels : (border_sync_ena ? synced_border : border);
assign up_color = (hpix&vpix) ? {up_palsel,~up_pixel,up_pixel?up_ink:up_paper} : {3'd0,border[2:0]};
assign palette_color = up_ena ? {3'b100,up_color} : {5'd0,zxcolor};
// palette
reg [7:0] palette [0:511]; // let quartus instantiate it as RAM
always @(posedge clk)
begin
if( atm_palwr || up_palwr )
begin : palette_write
reg [8:0] pal_addr;
pal_addr = atm_palwr ? { 5'd0, zxcolor } : { 3'b100, up_paladdr };
palette[pal_addr] <= atm_palwr ? {atm_paldata[3:2],1'b0,atm_paldata[5:4],1'b0,atm_paldata[1:0]} : up_paldata;
end
palette_read <= palette[palette_color];
end
assign palcolor = {palette_read[4:3],palette_read[7:6], palette_read[1:0]};
// make 3bit palette
always @(posedge clk)
vsync_r <= vsync;
//
wire vsync_start = vsync && !vsync_r;
//
initial ctr_14 = 2'b00;
always @(posedge clk)
ctr_14 <= ctr_14+2'b01;
//
initial ctr_h = 1'b0;
always @(posedge clk) if( hsync_start )
ctr_h <= ~ctr_h;
//
initial ctr_v = 1'b0;
always @(posedge clk) if( vsync_start )
ctr_v <= ~ctr_v;
wire plus1 = ctr_14[1] ^ ctr_h ^ ctr_v;
wire [1:0] red;
wire [1:0] grn;
wire [1:0] blu;
video_palframe_mk3bit red_color
(
.plus1 (plus1 ),
.color_in (palette_read[7:5]),
.color_out(red )
);
//
video_palframe_mk3bit grn_color
(
.plus1 (plus1 ),
.color_in (palette_read[4:2]),
.color_out(grn )
);
//
assign blu = palette_read[1:0];
assign color = (hblank | vblank) ? 6'd0 : {grn,red,blu};
endmodule
module video_palframe_mk3bit
(
input wire plus1,
input wire [2:0] color_in,
output reg [1:0] color_out
);
always @*
case( color_in )
3'b000: color_out <= 2'b00;
3'b001: color_out <= plus1 ? 2'b01 : 2'b00;
3'b010: color_out <= 2'b01;
3'b011: color_out <= plus1 ? 2'b10 : 2'b01;
3'b100: color_out <= 2'b10;
3'b101: color_out <= plus1 ? 2'b11 : 2'b10;
default: color_out <= 2'b11;
endcase
endmodule
|
#include <bits/stdc++.h> const int maxn = 1e6 + 20; const int maxm = 1e5 + 10; const long long int mod = 998244353; const long long int INF = 1e18 + 100; const int inf = 0x3f3f3f3f; const double pi = acos(-1.0); const double eps = 1e-8; using namespace std; int a[50][50]; int num[200], c[200]; int main() { int _; for (scanf( %d , &_); _; _--) { memset(num, 0, sizeof num); memset(c, 0, sizeof c); memset(a, 0, sizeof a); int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); if (n == 2 && m == 2) { if (a[0][0] != a[1][1]) puts( 1 ); else puts( 0 ); } else { n--; m--; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { c[i + j]++; num[i + j] += a[i][j]; } } int ans = 0; if ((n + m) % 2 == 1) { for (int i = 0; i < (n + m) / 2; i++) { ans += min(num[i] + num[n + m - i], (c[i] + c[n + m - i]) - (num[i] + num[n + m - i])); } int i = (n + m) / 2; ans += min(num[i] + num[n + m - i], (c[i] + c[n + m - i]) - (num[i] + num[n + m - i])); } else { for (int i = 0; i < (n + m) / 2; i++) { ans += min(num[i] + num[n + m - i], (c[i] + c[n + m - i]) - (num[i] + num[n + m - i])); } } printf( %d n , ans); } } }
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#include <bits/stdc++.h> using namespace std; void solve() { int i, ar[3]; cin >> ar[0] >> ar[1] >> ar[2]; int person = 0; for (i = 0; i < 3; i++) if (ar[i] > 0) { ar[i]--; person++; } sort(ar, ar + 3); if (ar[0] > 0 && ar[2] > 0) { person++; ar[0]--; ar[2]--; } if (ar[1] > 0 && ar[2] > 0) { person++; ar[2]--; ar[1]--; } if (ar[0] > 0 && ar[1] > 0) { person++; ar[0]--; ar[1]--; } if (ar[0] && ar[1] && ar[2]) { person++; } cout << person << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int T = 1; cin >> T; while (T--) solve(); return 0; }
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