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#include <bits/stdc++.h> int cicle[300] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}; int main() { int n; scanf( %d , &n); if (n == 1) { int b; scanf( %d , &b); if (b == 15) printf( DOWN n ); else if (b == 0) { printf( UP n ); } else printf( -1 n ); return 0; } int a[n]; for (int i = 0; i < n; ++i) { scanf( %d , a + i); } for (int i = 0; i < 100; ++i) { if (a[n - 1] == cicle[i + 1] && a[n - 2] == cicle[i]) { if (cicle[i + 2] > cicle[i + 1]) printf( UP n ); else printf( DOWN n ); return 0; } } return 0; }
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#include <bits/stdc++.h> static inline void setio(void); int main(void) { setio(); long long n; std::cin >> n; std::vector<long long> vec(n); std::vector<char> neg(n); for (long long i = 0; i < n; ++i) { std::cin >> vec[i]; if (vec[i] < 0) { neg[i] = true; vec[i] = -vec[i]; } } std::vector<long long> primes; std::vector<char> sieve(1000000, true); for (long long i = 2; i < sieve.size(); ++i) { if (!sieve[i]) continue; primes.push_back(i * i); if (primes.back() > 100000001LL) break; for (long long j = i + i; j < sieve.size(); j += i) sieve[j] = false; } for (auto& num : vec) { for (const auto& p : primes) { if (p > num) break; while (num % p == 0) num /= p; } } for (long long i = 0; i < n; ++i) if (neg[i]) vec[i] = -vec[i]; std::vector<long long> cnts(n + 1, 0); std::vector<long long> last_time(n); std::map<long long, long long> bleh; for (long long i = 0; i < n; ++i) { last_time[i] = bleh[vec[i]] - 1; bleh[vec[i]] = i + 1; } bool seen_zero; for (long long i = 0; i < n; ++i) { long long count = 0; seen_zero = false; for (long long j = i; j < n; ++j) { count += last_time[j] < i; seen_zero = seen_zero || vec[j] == 0; if (count == 1 && seen_zero) cnts[count]++; else if (count > 0) cnts[count - (seen_zero)]++; } } for (long long i = 1; i <= n; ++i) std::cout << cnts[i] << ; std::cout << n ; return 0; } static inline void setio(void) { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.precision(10); std::cout << std::fixed; }
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// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
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#include <bits/stdc++.h> using namespace std; const int INF = (int)2e9; const long long INFL = (long long)9e18; const int MAXINT = ((~0) ^ (1 << 31)); const long long MAXLL = ((~0) ^ ((long long)1 << 63)); template <class T> inline T pow2(T a) { return a * a; } template <class T> inline bool mineq(T& a, T b) { return (a > b) ? (a = b, true) : false; } template <class T> inline bool maxeq(T& a, T b) { return (a < b) ? (a = b, true) : false; } const int maxn = (int)1111; ; int n; struct human { int h, w; void input() { cin >> w >> h; } bool operator<(const human& a) const { return h - w < a.h - a.w; } } num[maxn]; bool used[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < (int)(n); i++) num[i].input(); sort(num, num + n); long long ans = INF; for (int maxh = 1; maxh < (int)(maxn); maxh++) { fill(used, used + n, false); long long cnt = 0, width = 0, f = 1; for (int i = 0; i < (int)(n); i++) { if (num[i].h > maxh && num[i].w > maxh) f = false; if (num[i].h > maxh) { used[i] = true; cnt++; } } for (int i = 0; i < (int)(n); i++) { if (!used[i] && cnt + 1 <= n / 2 && num[i].h < num[i].w && num[i].w <= maxh) { used[i] = true; cnt++; } if (used[i]) width += num[i].h; else width += num[i].w; } if (f && cnt <= n / 2) mineq(ans, maxh * width); } cout << ans; }
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//--------------------------------------------------------------------------------
// controller.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Controls the capturing & readback operation.
//
// If no other operation has been activated, the controller samples data
// into the memory. When the run signal is received, it continues to do so
// for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
// This allows to capture data from before the trigger match which is a nice
// feature.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module controller(
clock, reset, run,
wrSize, config_data,
validIn, dataIn, busy, arm,
// outputs...
send, memoryWrData, memoryRead,
memoryWrite, memoryLastWrite);
input clock;
input reset;
input run;
input wrSize;
input [31:0] config_data;
input validIn;
input [31:0] dataIn;
input busy;
input arm;
output send;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
reg [15:0] fwd, next_fwd; // Config registers...
reg [15:0] bwd, next_bwd;
reg send, next_send;
reg memoryRead, next_memoryRead;
reg memoryWrite, next_memoryWrite;
reg memoryLastWrite, next_memoryLastWrite;
reg [17:0] counter, next_counter;
wire [17:0] counter_inc = counter+1'b1;
reg [31:0] memoryWrData, next_memoryWrData;
always @(posedge clock)
begin
memoryWrData = next_memoryWrData;
end
always @*
begin
#1; next_memoryWrData = dataIn;
end
//
// Control FSM...
//
parameter [2:0]
IDLE = 3'h0,
SAMPLE = 3'h1,
DELAY = 3'h2,
READ = 3'h3,
READWAIT = 3'h4;
reg [2:0] state, next_state;
initial state = IDLE;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
state = IDLE;
memoryWrite = 1'b0;
memoryLastWrite = 1'b0;
memoryRead = 1'b0;
end
else
begin
state = next_state;
memoryWrite = next_memoryWrite;
memoryLastWrite = next_memoryLastWrite;
memoryRead = next_memoryRead;
end
end
always @(posedge clock)
begin
counter = next_counter;
send = next_send;
end
// FSM to control the controller action
always @*
begin
#1;
next_state = state;
next_counter = counter;
next_memoryWrite = 1'b0;
next_memoryLastWrite = 1'b0;
next_memoryRead = 1'b0;
next_send = 1'b0;
case(state)
IDLE :
begin
next_counter = 0;
next_memoryWrite = 1;
if (run) next_state = DELAY;
else if (arm) next_state = SAMPLE;
end
// default mode: write data samples to memory
SAMPLE :
begin
next_counter = 0;
next_memoryWrite = validIn;
if (run) next_state = DELAY;
end
// keep sampling for 4 * fwd + 4 samples after run condition
DELAY :
begin
if (validIn)
begin
next_memoryWrite = 1'b1;
next_counter = counter_inc;
if (counter == {fwd,2'b11}) // IED - Evaluate only on validIn to make behavior
begin // match between sampling on all-clocks verses occasionally.
next_memoryLastWrite = 1'b1; // Added LastWrite flag to simplify write->read memory handling.
next_counter = 0;
next_state = READ;
end
end
end
// read back 4 * bwd + 4 samples after DELAY
// go into wait state after each sample to give transmitter time
READ :
begin
next_memoryRead = 1'b1;
next_send = 1'b1;
if (counter == {bwd,2'b11})
begin
next_counter = 0;
next_state = IDLE;
end
else
begin
next_counter = counter_inc;
next_state = READWAIT;
end
end
// wait for the transmitter to become ready again
READWAIT :
begin
if (!busy && !send) next_state = READ;
end
endcase
end
//
// Set speed and size registers if indicated...
//
always @(posedge clock)
begin
fwd = next_fwd;
bwd = next_bwd;
end
always @*
begin
#1;
next_fwd = fwd;
next_bwd = bwd;
if (wrSize)
begin
next_fwd = config_data[31:16];
next_bwd = config_data[15:0];
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; using ld = long double; using ll = long long; void solve() { int n; cin >> n; vector<int> v(n); vector<pair<int, int>> a(n); for (int i = 0; i < n; i++) { cin >> v[i]; a[i] = {v[i], i}; } sort(a.begin(), a.end()); vector<int> p(n); int j = 0; unordered_multiset<int> next; for (int i = 0; i < n; i++) { if (i > 0 && a[i].first != a[i - 1].first) { j++; } p[a[i].second] = j; next.insert(j); } unordered_map<int, int> d; vector<int> dp1(n), dp2(n), dp3(n), cnt(n); for (int i = 0; i < n; i++) { if (next.count(p[i])) { next.erase(next.find(p[i])); } if (d.count(p[i] - 1)) { if (!d.count(p[i])) { dp2[i] = max(dp2[i], dp1[d[p[i] - 1]] + 1); if (!next.count(p[i] - 1)) { dp2[i] = max(dp2[i], dp2[d[p[i] - 1]] + 1); } } if (!next.count(p[i] - 1)) { dp3[i] = max(dp3[i], dp2[d[p[i] - 1]] + 1); } dp3[i] = max(dp3[i], dp1[d[p[i] - 1]] + 1); } if (d.count(p[i])) { dp3[i] = max(dp3[i], dp3[d[p[i]]] + 1); dp2[i] = max(dp2[i], dp2[d[p[i]]] + 1); dp1[i] = dp1[d[p[i]]] + 1; } else { dp1[i] = 1; } dp2[i] = max(dp2[i], dp1[i]); dp3[i] = max(dp3[i], dp2[i]); d[p[i]] = i; } cout << n - *max_element(dp3.begin(), dp3.end()) << n ; } int main() { int n; cin >> n; while (n--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int maxn = 2e3 + 1; const int maxm = 2e3 + 1; char a[maxn], b[maxn]; int num[maxn]; int m, d; long long dp[maxn][maxm]; int len; int judge(const char* s, int lena) { int mod = 0; for (int i = 1; i <= lena; i++) { mod = (mod * 10 + s[i]) % m; if ((i & 1) == 0 && s[i] != d) { return 0; } if ((i & 1) && s[i] == d) return 0; } return (mod == 0); } int val[maxn]; long long dfs(int pos, int mod, bool limit) { if (pos == len + 1) { return mod == 0; } if (!limit && dp[pos][mod] != -1) return dp[pos][mod]; int up = (limit ? num[pos] : 9); long long res = 0; for (int i = 0; i <= up; i++) { int tmod = (mod * 10 + i) % m; if ((pos & 1) && (i == d)) continue; if (!(pos & 1) && (i != d)) continue; res = (res + dfs(pos + 1, tmod, limit && i == up)) % MOD; } if (!limit) dp[pos][mod] = res; return res; } long long solve(const char* s, int lena) { for (int i = 1; i <= lena; i++) num[i] = s[i]; len = lena; memset(dp, -1, sizeof(dp)); return dfs(1, 0, true) % MOD; } int main() { cin >> m >> d; cin >> (a + 1); cin >> (b + 1); int lena = strlen(a + 1), lenb = strlen(b + 1); for (int i = 1; i <= lena; i++) a[i] -= 0 ; for (int i = 1; i <= lenb; i++) b[i] -= 0 ; cout << ((solve(b, lenb) - solve(a, lena) + judge(a, lena)) % MOD + MOD) % MOD << endl; return 0; }
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module FrameTrans(Reset,Clock100M,Mode,Clock,DataIn);
input Reset;
input Clock100M;
input [1:0] Mode;
output Clock;
output reg DataIn;
reg [31:0] Counter;
reg Clk_10ms;
reg [7:0] StateCnt256;
reg [1:0] FrameCnt4;
reg FrameStart;
reg ScrambEn;
wire ScrambOut;
parameter DELAY_NUM = 100000;
parameter FRAMEHEAD = 8'b1001_1011;
parameter FRAMEHEAD_WRONG = 8'b1000_1001;
assign Clock = Clk_10ms;
// Generate Clk_400ms Signal;
always@(negedge Reset or posedge Clock100M)
begin
if(Reset == 1'b0)
begin
Counter <= 0;
Clk_10ms <= 0;
end
else
begin
Counter <= Counter + 1;
if(Counter == DELAY_NUM)
begin
Counter <= 0;
Clk_10ms <= ~Clk_10ms;
end
end
end
// Transmission Control
always@(negedge Reset or posedge Clk_10ms)
begin
if(Reset == 1'b0)
begin
StateCnt256 <= 0;
DataIn <= 0;
FrameStart <= 0;
ScrambEn <= 0;
FrameCnt4 <= 0;
end
else if(Mode > 0)
begin
FrameStart <= 0;
StateCnt256 <= StateCnt256 + 1;
if(StateCnt256)
FrameCnt4 <= FrameCnt4 + 1;
if(StateCnt256 < 8)
begin
ScrambEn <= 0;
if(Mode == 3 && FrameCnt4 == 2)
DataIn <= FRAMEHEAD_WRONG>>(7 - StateCnt256);
else
DataIn <= FRAMEHEAD>>(7 - StateCnt256);
if(StateCnt256 == 5)
FrameStart<=1;
else if (StateCnt256 > 5)
ScrambEn <= 1;
end
else
begin
DataIn <= ScrambOut;
if(StateCnt256 == 255 && Mode == 1)
begin
StateCnt256 <= 255;
ScrambEn <= 0;
DataIn <= 0;
end
end
end
else
begin
StateCnt256 <= 0;
DataIn <= 0;
FrameStart <= 0;
ScrambEn <= 0;
FrameCnt4 <= 0;
end
end
scrambler U1(.clk(Clk_10ms),
.rst(Reset),
.frame_start(FrameStart),
.scramb_en(ScrambEn),
.din(0),
.dout(ScrambOut),
.scramb_out_en());
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; string s; cin >> s; for (int cnt1 = 0; cnt1 <= n / a; ++cnt1) { for (int cnt2 = 0; cnt2 <= n / b; ++cnt2) if (a * cnt1 + b * cnt2 == n) { cout << cnt1 + cnt2 << endl; for (int i = 0; i < cnt1; ++i) { for (int j = 0; j < a; ++j) cout << s[j]; cout << endl; s.erase(0, a); } for (int i = 0; i < cnt2; ++i) { for (int j = 0; j < b; ++j) cout << s[j]; cout << endl; s.erase(0, b); } return 0; } } cout << -1 << endl; return 0; }
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///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $
//
// Module: fallthrough_small_fifo.v
// Project: utils
// Description: small fifo with fallthrough i.e. data valid when rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 2/11/09 -- jnaous: Rewrote to make much more efficient.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module fallthrough_small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output reg empty,
output [MAX_DEPTH_BITS:0] data_count,
input reset,
input clk
);
reg fifo_rd_en, empty_nxt;
small_fifo
#(.WIDTH (WIDTH),
.MAX_DEPTH_BITS (MAX_DEPTH_BITS),
.PROG_FULL_THRESHOLD (PROG_FULL_THRESHOLD))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (fifo_rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (fifo_empty),
.data_count (data_count),
.reset (reset),
.clk (clk)
);
always @(*) begin
empty_nxt = empty;
fifo_rd_en = 0;
case (empty)
1'b1: begin
if(!fifo_empty) begin
fifo_rd_en = 1;
empty_nxt = 0;
end
end
1'b0: begin
if(rd_en) begin
if(fifo_empty) begin
empty_nxt = 1;
end
else begin
fifo_rd_en = 1;
end
end
end
endcase // case(empty)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
empty <= 1'b1;
end
else begin
empty <= empty_nxt;
end
end
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && full) begin
$display("%t ERROR: Attempt to write to full FIFO: %m", $time);
end
if (rd_en && empty) begin
$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
end
end // always @ (posedge clk)
// synthesis translate_on
endmodule // fallthrough_small_fifo_v2
// synthesis translate_off
module fallthrough_small_fifo_tester();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer count = 0;
always #8 clk = ~clk;
fallthrough_small_fifo
#(.WIDTH (32),
.MAX_DEPTH_BITS (3),
.PROG_FULL_THRESHOLD (4))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (empty),
.reset (reset),
.clk (clk)
);
always @(posedge clk) begin
count <= count + 1;
reset <= 0;
wr_en <= 0;
rd_en <= 0;
if(count < 2) begin
reset <= 1'b1;
end
else if(count < 2 + 9) begin
wr_en <= 1;
din <= din + 1'b1;
end
else if(count < 2 + 8 + 4) begin
rd_en <= 1;
end
else if(count < 2 + 8 + 4 + 2) begin
din <= din + 1'b1;
wr_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4) begin
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
end // always @ (posedge clk)
endmodule // fallthrough_small_fifo_tester
// synthesis translate_on
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; pair<int, int> p[n]; int t = 0; for (int i = 0; i < n; i++) { cin >> p[i].first >> p[i].second; } sort(p, p + n); int start = 0, l = 0, r = 0, s = 0; for (int i = 0; i < 2 * n; i++) { if (i < n && p[i].first > 0) { start = 1; } if (start) { l = i - 1; r = i; while (1) { if (l < 0 && r == n) break; if (l < 0) { s += p[r].second; break; } else if (r == n) { s += p[l].second; break; } s += p[l--].second + p[r++].second; } return cout << s, 0; } } cout << p[n - 1].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, arr[1042], cc[1042]; vector<pair<int, int> > path; vector<pair<int, int> > ans; map<pair<long long, long long>, pair<int, int> > m; long long base = 1031, mod = 1000000007LL, mod2 = 1000000009LL; long long pows[1042] = {1}; pair<long long, long long> h(int a[]) { long long ret = 0, ret2 = 0; for (int i = 0; i < n; i++) { ret *= base; ret2 *= base; ret += a[i]; ret2 += a[i]; ret %= mod; ret2 %= mod2; } return make_pair(ret, ret2); } bool ok() { if (m.find(h(arr)) != m.end()) { return 1; } return 0; for (int i = 1; i <= n; i++) { if (arr[i - 1] != i) { return 0; } } return 1; } bool f = 0; void get(int ck) { if (ans.size()) { return; } if (ck == 2) { if (ok()) { ans = path; ans.push_back(m[h(arr)]); } return; } for (int s = 0; s < n; s++) { if (s != 0 && abs(arr[s] - arr[s - 1]) == 1 && s != 1 && abs(arr[s - 2] - arr[s - 1]) == 1) { continue; } for (int f = s; f < n; f++) { if (f != n - 1 && abs(arr[f] - arr[f + 1]) == 1 && f != n - 2 && abs(arr[f + 1] - arr[f + 2]) == 1) { continue; } path.push_back(make_pair(s, f)); reverse(arr + s, arr + f + 1); get(ck + 1); reverse(arr + s, arr + f + 1); path.pop_back(); if (ans.size()) { return; } } } } long long ss[1042], ff[1042], revHs[1042][1042]; long long ss2[1042], ff2[1042], revHs2[1042][1042]; long long pows2[1042]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n; pows[0] = 1; pows2[0] = 1; for (int i = 1; i <= n; i++) { pows[i] = pows[i - 1] * base % mod; pows2[i] = pows2[i - 1] * base % mod2; } for (int i = 0; i < n; i++) { cin >> arr[i]; cc[i] = i + 1; } ss[0] = 0; ss2[0] = 0; for (int i = 1; i <= n; i++) { ss[i] = ss[i - 1] + i * pows[n - i]; ss2[i] = ss2[i - 1] + i * pows2[n - i]; ss[i] %= mod; ss2[i] %= mod2; } ff[n - 1] = 0; ff2[n - 1] = 0; for (int i = n - 2; i >= 0; i--) { ff[i] = ff[i + 1] + (i + 2) * pows[n - i - 2]; ff2[i] = ff2[i + 1] + (i + 2) * pows2[n - i - 2]; ff[i] %= mod; ff2[i] %= mod2; } for (int s = 0; s < n; s++) { revHs[s][s] = s + 1; revHs2[s][s] = s + 1; for (int f = s + 1; f < n; f++) { revHs[s][f] = revHs[s][f - 1] + (f + 1) * pows[f - s]; revHs2[s][f] = revHs2[s][f - 1] + (f + 1) * pows2[f - s]; revHs[s][f] %= mod; revHs2[s][f] %= mod2; } } for (int s = 0; s < n; s++) { for (int f = s; f < n; f++) { long long c = ss[s] + revHs[s][f] * pows[n - f - 1] + ff[f]; long long c2 = ss2[s] + revHs2[s][f] * pows2[n - f - 1] + ff2[f]; c %= mod; c2 %= mod2; m[make_pair(c, c2)] = make_pair(s, f); } } get(0); reverse(ans.begin(), ans.end()); path = ans; int kk = 0; for (int j = 0; j < path.size(); j++) { if (path[j].first == path[j].second) { continue; } kk++; } cout << kk << n ; for (int j = 0; j < path.size(); j++) { if (path[j].first == path[j].second) { continue; } cout << path[j].first + 1 << << path[j].second + 1 << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A32O_PP_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; long long n, m, l, r; long long binpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res % mod; } long long inv(long long a) { return binpow(a, mod - 2); } int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); cin >> n >> m >> l >> r; long long sz = n * m; if (sz & 1) { cout << binpow(r - l + 1, sz); } else { cout << (inv(2) * (binpow(r - l + 1, sz) + (((r - l + 1) % 2) ? 1 : 0))) % mod; } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_data_mover (
input clk,
input resetn,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
input enable,
output reg enabled,
output s_axi_ready,
input s_axi_valid,
input [C_DATA_WIDTH-1:0] s_axi_data,
input m_axi_ready,
output m_axi_valid,
output [C_DATA_WIDTH-1:0] m_axi_data,
output m_axi_last,
input req_valid,
output reg req_ready,
input [3:0] req_last_burst_length
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_DISABLE_WAIT_FOR_ID = 1;
`include "inc_id.v"
reg [3:0] last_burst_length;
reg [C_ID_WIDTH-1:0] id = 'h00;
reg [C_ID_WIDTH-1:0] id_next;
reg [3:0] beat_counter = 'h00;
wire [3:0] beat_counter_next;
wire last;
reg pending_burst;
assign response_id = id;
assign beat_counter_next = s_axi_ready && s_axi_valid ? beat_counter + 1'b1 : beat_counter;
assign last = beat_counter == (eot ? last_burst_length : 4'hf);
assign s_axi_ready = m_axi_ready & pending_burst & ~req_ready;
assign m_axi_valid = s_axi_valid & pending_burst & ~req_ready;
assign m_axi_data = s_axi_data;
assign m_axi_last = last;
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable) begin
enabled <= 1'b1;
end else begin
if (C_DISABLE_WAIT_FOR_ID == 0) begin
// We are not allowed to just deassert valid, so wait until the
// current beat has been accepted
if (~s_axi_valid || m_axi_ready)
enabled <= 1'b0;
end else begin
// For memory mapped AXI busses we have to complete all pending
// burst requests before we can disable the data mover.
if (response_id == request_id)
enabled <= 1'b0;
end
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
beat_counter <= 'h0;
req_ready <= 1'b1;
end else begin
if (~enabled) begin
req_ready <= 1'b1;
end else if (req_ready) begin
if (req_valid && enabled) begin
last_burst_length <= req_last_burst_length;
req_ready <= 1'b0;
beat_counter <= 'h0;
end
end else if (s_axi_ready && s_axi_valid) begin
if (last && eot)
req_ready <= 1'b1;
beat_counter <= beat_counter + 1'b1;
end
end
end
always @(*)
begin
if ((s_axi_ready && s_axi_valid && last) ||
(sync_id && id != request_id))
id_next <= inc_id(id);
else
id_next <= id;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
id <= id_next;
pending_burst <= id_next != request_id;
end
end
endmodule
|
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_mul_hc(
// this interface matches what hdlgen expects
input logic clock,
input logic resetn,
input logic valid_in,
input logic stall_in,
output logic valid_out,
output logic stall_out,
input logic [31:0] dataa,
input logic [31:0] datab,
output logic [31:0] result
);
acl_fp_custom_mul_hc_core #(
.HIGH_CAPACITY(1)
)
core(
.clock(clock),
.resetn(resetn),
.valid_in(valid_in),
.stall_in(stall_in),
.valid_out(valid_out),
.stall_out(stall_out),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_PP_BLACKBOX_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } template <typename T, size_t size> ostream &operator<<(ostream &os, const array<T, size> &arr) { os << { ; string sep; for (const auto &x : arr) os << sep << x, sep = , ; return os << } ; } template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename A, typename B> ostream &operator<<(ostream &os, const map<A, B> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } mt19937 mt_rng(chrono::steady_clock::now().time_since_epoch().count()); long long rand(long long a, long long b) { return uniform_int_distribution<long long>(a, b)(mt_rng); } template <long long D, typename T> struct vec : public vector<vec<D - 1, T>> { static_assert(D >= 1, Dimensions invalid ); template <typename... Args> vec(long long n = 0, Args... args) : vector<vec<D - 1, T>>(n, vec<D - 1, T>(args...)) {} }; template <typename T> struct vec<1, T> : public vector<T> { vec(long long n = 0, const T &val = T()) : vector<T>(n, val) {} }; template <class T> bool cmin(T &a, const T &b) { return b < a ? a = b, 1 : 0; } template <class T> bool cmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const long long N = 2e5 + 5, inf = 1e18; struct Point { long long x, y; Point operator-(Point p) { return {x - p.x, y - p.y}; } long long dist() { return x * x + y * y; } }; bool by_x(Point &a, Point &b) { return a.x < b.x; } bool by_y(Point &a, Point &b) { return a.y < b.y; } long long n, ans = 1e18; long long a[N], pref[N]; Point pt[N]; long long solve(long long L, long long R) { if (L == R) return 1e18; long long M = (L + R) / 2; sort(pt + L, pt + R + 1, by_x); long long d = min(solve(L, M), solve(M + 1, R)); long long midx = pt[L + (R - L + 1) / 2].x; vector<Point> v; for (long long i = L; i <= R; i++) { if (Point{pt[i].x - midx, 0}.dist() < d) { v.push_back(pt[i]); } } sort(v.begin(), v.end(), by_y); for (long long i = 0; i < v.size(); i++) { for (long long j = i + 1; j < v.size(); j++) { if (Point{0, v[i].y - v[j].y}.dist() > d) break; d = min(d, (v[i] - v[j]).dist()); } } return d; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; long long sum = 0; for (long long i = 1, u; i <= n; i++) { cin >> u; sum += u; pt[i].x = i; pt[i].y = sum; } cout << solve(1, n) << n ; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_sc_0_rep2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_sc_0_rep2(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_buf, dram_scbuf_ecc_r2_buf,
scbuf_dram_wr_data_r5_buf, scbuf_dram_data_vld_r5_buf,
scbuf_dram_data_mecc_r5_buf, sctag_dram_rd_req_buf,
sctag_dram_rd_dummy_req_buf, sctag_dram_rd_req_id_buf,
sctag_dram_addr_buf, sctag_dram_wr_req_buf, dram_sctag_rd_ack_buf,
dram_sctag_wr_ack_buf, dram_sctag_chunk_id_r0_buf,
dram_sctag_data_vld_r0_buf, dram_sctag_rd_req_id_r0_buf,
dram_sctag_secc_err_r2_buf, dram_sctag_mecc_err_r2_buf,
dram_sctag_scb_mecc_err_buf, dram_sctag_scb_secc_err_buf,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_buf;
output [27:0] dram_scbuf_ecc_r2_buf;
// scbuf to dram TOp
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// BOTTOM
output [63:0] scbuf_dram_wr_data_r5_buf;
output scbuf_dram_data_vld_r5_buf;
output scbuf_dram_data_mecc_r5_buf;
// sctag_dramsctag signals INputs
// @ the TOp.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
// sctag_dram BOTTOM
output sctag_dram_rd_req_buf;
output sctag_dram_rd_dummy_req_buf;
output [2:0] sctag_dram_rd_req_id_buf;
output [39:5] sctag_dram_addr_buf;
output sctag_dram_wr_req_buf;
// Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
// outputs BOTTOM
output dram_sctag_rd_ack_buf;
output dram_sctag_wr_ack_buf;
output [1:0] dram_sctag_chunk_id_r0_buf;
output dram_sctag_data_vld_r0_buf;
output [2:0] dram_sctag_rd_req_id_r0_buf;
output dram_sctag_secc_err_r2_buf ;
output dram_sctag_mecc_err_r2_buf ;
output dram_sctag_scb_mecc_err_buf;
output dram_sctag_scb_secc_err_buf;
// The placement of pins on the top and bottom should be identical to
// the placement of the data column of pins in dram_l2_buf1.v
assign dram_scbuf_data_r2_buf = dram_scbuf_data_r2 ;
assign dram_scbuf_ecc_r2_buf = dram_scbuf_ecc_r2 ;
assign scbuf_dram_wr_data_r5_buf = scbuf_dram_wr_data_r5 ;
assign scbuf_dram_data_vld_r5_buf = scbuf_dram_data_vld_r5 ;
assign scbuf_dram_data_mecc_r5_buf = scbuf_dram_data_mecc_r5 ;
assign dram_sctag_rd_ack_buf = dram_sctag_rd_ack ;
assign dram_sctag_wr_ack_buf = dram_sctag_wr_ack ;
assign dram_sctag_chunk_id_r0_buf = dram_sctag_chunk_id_r0 ;
assign dram_sctag_data_vld_r0_buf = dram_sctag_data_vld_r0;
assign dram_sctag_rd_req_id_r0_buf = dram_sctag_rd_req_id_r0;
assign dram_sctag_secc_err_r2_buf = dram_sctag_secc_err_r2;
assign dram_sctag_mecc_err_r2_buf = dram_sctag_mecc_err_r2;
assign dram_sctag_scb_mecc_err_buf = dram_sctag_scb_mecc_err;
assign dram_sctag_scb_secc_err_buf = dram_sctag_scb_secc_err;
assign sctag_dram_rd_req_buf = sctag_dram_rd_req ;
assign sctag_dram_rd_dummy_req_buf = sctag_dram_rd_dummy_req ;
assign sctag_dram_rd_req_id_buf = sctag_dram_rd_req_id ;
assign sctag_dram_addr_buf = sctag_dram_addr ;
assign sctag_dram_wr_req_buf = sctag_dram_wr_req ;
endmodule
|
// Build a test bench to test the design
module testBench;
wire [12:0] pc; // connect the pc
wire clock; // connect the clock
hal1 aComputer (clock, pc); // build an instance of the computer
test_it aTester(clock, pc); // build a tester
initial
begin
$dumpfile("hal1.vcd");
$dumpvars(1,aComputer);
end
endmodule
// The Computer - HAL1
module hal1 (clock, pc);
// declare the parameters
input clock;
output [12:0] pc;
reg [31:0] m [7:0]; // 8 x 32 bit memory
reg [12:0] pc; // 13 bit program counter
reg [31:0] acc; // 32 bit accumulator
reg [15:0] ir; // 16 bit instruction register
reg [31:0] r[7:0]; // 16 x 32 value
initial // initialize the pc and the accumulator
begin // define the instruction rom
pc = 0;
acc = 0;
$display("\nInitize acc with 0", acc);
m[0] = 'h0000; // these are for illustration
m[1] = 'h2001;
m[2] = 'h4002;
m[3] = 'h6003;
m[4] = 'ha004;
m[5] = 'hc005;
m[6] = 'h6206;
m[7] = 'h8007;
r[0] = 'h0; // these are for illustration
r[1] = 'h1;
r[2] = 'h2;
r[3] = 'h3;
r[4] = 'h4;
r[5] = 'h5;
r[6] = 'h6;
r[7] = 'h7;
end
always
begin
@(posedge clock)
ir = m [pc]; // fetch an instruction
if (ir[15:13] == 3'b000) // begin decoding
pc = m [ir [12:0]]; // and executing
else if (ir[15:13] == 3'b001)
pc = pc + m [ir [12:0]];
else if (ir[15:13] == 3'b010)
acc = m [ir [12:0]];
else if (ir[15:13] == 3'b011)
m [ir [12:0]] = acc;
else if ((ir[15:13] == 3'b101) || (ir[15:13] == 3'b100))
acc = acc - m [ir [12:0]];
else if (ir[15:13] == 3'b110)
begin
acc = -m [ir [12:0]];
pc = pc+1;
acc = r[(ir[12:10])]+r[(ir[3:0])];
end
pc = (pc + 1)%8; //increment program
// counter
end
endmodule
// Test module
module test_it(clock, pc);
// declare the parameters
input [12:0] pc;
output clock;
reg clock; // system clock
parameter period = 1;
initial
clock = 0;
// manage the clock
always
begin
#(period) clock = ~clock;
end
// manage the display
always @(posedge clock)
begin
$strobe ($time,, "pc = %d", pc); // record every time tick
// look for changes
$monitor ($time,, "pc = %d", pc); // record only changes
#(30*period); // let clock cycle a couple of times
#(period); // needed to see END of a simulation
$finish; // return to dos
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class temp> inline void Rd(temp &p) { p = 0; char c; while (c = getchar(), c < 48) ; do p = p * 10 + (c & 15); while (c = getchar(), c > 47); } int pow(int n, int m) { int ans = 1; while (m) { if (m & 1) ans = 1ll * ans * n % 1000000007; m >>= 1; n = 1ll * n * n % 1000000007; } return ans; } int head[100005], tot = 0; struct eg { int v, col, nxt; } E[100005 << 1]; void add_edge(int u, int v, int w) { E[++tot] = (eg){v, w, head[u]}; head[u] = tot; E[++tot] = (eg){u, w, head[v]}; head[v] = tot; } int col[100005]; bool dfs(int u) { for (int j = head[u]; j; j = E[j].nxt) { int v = E[j].v, c = E[j].col; if (!~col[v]) { col[v] = col[u] ^ c ^ 1; if (!dfs(v)) return false; } else { if ((col[u] ^ c ^ 1) != col[v]) return false; } } return true; } int main() { int n, m; Rd(n), Rd(m); for (int i = 1; i <= m; i++) { int u, v, w; Rd(u), Rd(v), Rd(w); add_edge(u, v, w); } memset(col, -1, sizeof(col)); int sz = 0; for (int i = 1; i <= n; i++) if (!~col[i]) { col[i] = 0; if (!dfs(i)) { puts( 0 ); return 0; } ++sz; } printf( %d n , pow(2, sz - 1)); }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<ll, ll>; const ll MOD = 1e9 + 7, N = 1e5 + 10; void test() { ll n; cin >> n; vector<ll> a(n); for (ll i = 0; i < n; i++) { cin >> a[i]; } vector<ll> ans; sort(a.begin(), a.end()); ll l = 0, h = n - 1; while (l < h) { ans.push_back(a[l]); ans.push_back(a[h]); l++, h--; } if (l == h) ans.push_back(a[l]); reverse(ans.begin(), ans.end()); for (ll i = 0; i < n; i++) { cout << ans[i] << n [i == n - 1]; } return; } int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); ll tt = 1; cin >> tt; for (ll i = 0; i < tt; i++) test(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1000000; const int MAX_N = 50000; const int oo = 1e9; const int LOGN = 20; const int Z = 230; int f[MAX + 1], n, m, a[MAX_N], ans[MAX_N]; struct node { int nxt[2], val; multiset<int> mst; node() { memset(nxt, -1, sizeof nxt); val = oo; } }; struct query { int l, r, idx; query(int _l, int _r, int _idx) { l = _l, r = _r, idx = _idx; } bool operator<(const query &rhs) const { return r < rhs.r; } }; vector<query> q[Z]; struct honey { vector<node> trie; int ty; honey(int _ty) { ty = _ty; } void insert(int u, int depth, int first, int ax, bool add) { if (!trie.size()) trie.push_back(node()); if (depth == -1) { if (add) trie[u].mst.insert(ax); else trie[u].mst.erase(trie[u].mst.find(ax)); if (ty == 0) { trie[u].val = trie[u].mst.size() ? *trie[u].mst.begin() : oo; } else { trie[u].val = trie[u].mst.size() ? *--trie[u].mst.end() : -oo; } return; } bool bt = (first >> depth) & 1; if (trie[u].nxt[bt] == -1) { trie[u].nxt[bt] = trie.size(); trie.push_back(node()); } insert(trie[u].nxt[bt], depth - 1, first, ax, add); trie[u].val = (!ty ? oo : -oo); if (trie[u].nxt[bt] != -1) trie[u].val = trie[trie[u].nxt[bt]].val; if (trie[u].nxt[bt ^ 1] != -1) { if (!ty) trie[u].val = min(trie[u].val, trie[trie[u].nxt[bt ^ 1]].val); else trie[u].val = max(trie[u].val, trie[trie[u].nxt[bt ^ 1]].val); } } int search(int u, int depth, int first, int ax) { if (depth == -1 || u == -1 || (ty == 0 ? trie[u].val > ax : trie[u].val < ax)) return 0; bool bt = (first >> depth) & 1; if (trie[u].nxt[bt ^ 1] != -1 && (ty == 0 ? trie[trie[u].nxt[bt ^ 1]].val <= ax : trie[trie[u].nxt[bt ^ 1]].val >= ax)) return (1 << depth) + search(trie[u].nxt[bt ^ 1], depth - 1, first, ax); return search(trie[u].nxt[bt], depth - 1, first, ax); } void clear() { trie.clear(); } }; honey lv[2] = {honey(0), honey(1)}; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); for (int i = 0, l, r; i < m; ++i) { scanf( %d%d , &l, &r); --l, --r; q[l / Z].push_back(query(l, r, i)); } for (int i = 1; i <= MAX; ++i) f[i] = i ^ f[i - 1]; for (int bucket = 0; bucket < Z; ++bucket) { if (q[bucket].size() == 0) continue; sort(q[bucket].begin(), q[bucket].end()); int idx = bucket * Z + Z; int ed = min(n - 1, bucket * Z + Z - 1); lv[0].clear(); lv[1].clear(); int mx = 0; for (int j = 0; j < q[bucket].size(); ++j) { query &sh = q[bucket][j]; while (idx <= sh.r) { lv[0].insert(0, LOGN, f[a[idx] - 1], a[idx], 1); mx = max(mx, lv[0].search(0, LOGN, f[a[idx]], a[idx])); lv[1].insert(0, LOGN, f[a[idx]], a[idx], 1); mx = max(mx, lv[1].search(0, LOGN, f[a[idx] - 1], a[idx])); idx++; } ans[sh.idx] = mx; int lf = sh.l, rf = min(ed, sh.r); for (int p = lf; p <= rf; ++p) { lv[0].insert(0, LOGN, f[a[p] - 1], a[p], 1); lv[1].insert(0, LOGN, f[a[p]], a[p], 1); } for (int p = lf; p <= rf; ++p) { ans[sh.idx] = max(ans[sh.idx], lv[0].search(0, LOGN, f[a[p]], a[p])); ans[sh.idx] = max(ans[sh.idx], lv[1].search(0, LOGN, f[a[p] - 1], a[p])); } for (int p = lf; p <= rf; ++p) { lv[0].insert(0, LOGN, f[a[p] - 1], a[p], 0); lv[1].insert(0, LOGN, f[a[p]], a[p], 0); } } } for (int i = 0; i < m; ++i) { printf( %d n , ans[i]); } return 0; }
|
// -*- Mode: Verilog -*-
// Filename : system_controller_altera.v
// Description : System Controller for Altera FPGA
// Author : Philip Tracton
// Created On : Sat Jan 7 21:51:18 2017
// Last Modified By: Philip Tracton
// Last Modified On: Sat Jan 7 21:51:18 2017
// Update Count : 0
// Status : Unknown, Use with caution!
module system_controller_altera (/*AUTOARG*/
// Outputs
clk_i, rst_i, nrst_i,
// Inputs
clk_sys_i, rst_sys_i
) ;
input wire clk_sys_i;
input wire rst_sys_i;
output wire clk_i;
output reg rst_i;
output wire nrst_i;
wire LOCKED;
altera_syscon_pll pll(
.areset(rst_sys_i),
.inclk0(clk_sys_i),
.c0(clk_i),
.locked(LOCKED)
);
//
// RESET Logic
//
reg [3:0] rst_count;
//
// Inverted reset signal since some 3rd party blocks use an active low reset
//
assign nrst_i = ~rst_i;
//
// If input rst_sys_i or we are NOT locked, keep rst_i high for rest of system
// Once LOCKED is asserted, count down the rst_count number of clocks to make sure all
// synchronous reset blocks get a few clocks and can reset correctly. Once the count reaches 0
// release reset and let the sytem run
//
always @(posedge clk_sys_i)
if (rst_sys_i | ~LOCKED) begin
rst_i <= 1;
rst_count <= 4'hF;
end else begin
if (LOCKED) begin
if (rst_count) begin
rst_count <= rst_count - 1;
end else begin
rst_i <= 0;
end
end
end // else: !if(rst_sys_i | ~LOCKED)
endmodule // system_controller_altera
|
#include <bits/stdc++.h> using namespace std; long long n, x, a, s; vector<pair<int, long long> > v, u; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x >> a; if (x < 0) v.push_back(make_pair(-x, a)); else u.push_back(make_pair(x, a)); s += a; } sort(v.begin(), v.end()); sort(u.begin(), u.end()); if ((int)v.size() - (int)u.size() <= 1 && (int)u.size() - (int)v.size() <= 1) { cout << s << endl; return 0; } if (v.size() > u.size()) { for (int i = u.size() + 1; i < v.size(); i++) s -= v[i].second; cout << s << endl; return 0; } for (int i = v.size() + 1; i < u.size(); i++) s -= u[i].second; cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int max_n = 100; int a[max_n], tmp[max_n]; bool vis[max_n]; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int main() { int n; cin >> n; for (int i = 0; i < (n); i++) { cin >> a[i]; a[i]--; tmp[i] = a[i]; } sort(tmp, tmp + n); for (int i = 0; i < (n); i++) if (i != tmp[i]) { cout << -1 << endl; return 0; } long long ans = 1; memset(vis, false, sizeof vis); for (int i = 0; i < (n); i++) if (!vis[i]) { int cnt = 0; for (int k = i; !vis[k]; k = a[k]) { vis[k] = true; cnt++; } if (cnt % 2 == 0) cnt /= 2; ans *= cnt / gcd(ans, cnt); } cout << ans << endl; return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_39x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_39x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [38:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [38:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [38:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [38:0] q = sub_wire2[38:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 39,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "39"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "39"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "39"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 39 0 INPUT NODEFVAL data[38..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL q[38..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 39 0 data 0 0 39 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
`define OP_SPECIAL 6'b000000
`define OP_SPECIAL2 6'b011100
`define OP_ADDI 6'b001000 // addi rt, rs, imm ; rt = rs + imm
`define OP_ADDIU 6'b001001 // addiu rt, rs, imm ; rt = rs + imm
`define OP_ANDI 6'b001100 // andi rt, rs, imm ; rt = rs & imm
`define OP_ORI 6'b001101
`define OP_XORI 6'b001110
`define OP_SLTI 6'b001010
`define OP_SLTIU 6'b001011
`define OP_LB 6'b100000
`define OP_LH 6'b100001
`define OP_LBU 6'b100100
`define OP_LHU 6'b100101
`define OP_LW 6'b100011 // lw rt, imm(rs) ; rt = [rs+imm]
`define OP_SW 6'b101011 // sw rt, imm(rs) ; [rs + imm] = rt
// Special 0
`define FUNCT_ADD 6'b100000
`define FUNCT_ADDU 6'b100001
`define FUNCT_AND 6'b100100
`define FUNCT_DIV 6'b011010
`define FUNCT_DIVU 6'b011011
`define FUNCT_MULT 6'b011000
`define FUNCT_MULTU 6'b011001
`define FUNCT_NOR 6'b100111
`define FUNCT_OR 6'b100101
`define FUNCT_SLT 6'b101010
`define FUNCT_SUB 6'b100010
`define FUNCT_SUBU 6'b100011
`define FUNCT_XOR 6'b100110
// Special 2
//`define FUNCT_CLO 6'b100001
//`define FUNCT_CLZ 6'b100000
//`define FUNCT_MADD 6'b000000
//`define FUNCT_MADDU 6'b000001
//`define FUNCT_MSUB 6'b000100
//`define FUNCT_MSUBU 6'b000101
//`define FUNCT_MUL 6'b000010
`include "defines.v"
module qm_control(
/// Instruction from the decode stage
input wire [5:0] i_Opcode,
input wire [5:0] i_Function,
/// Control lines to the pipeline stages
// Mux selecting the destination register for the register writeback
// 0 - RT
// 1 - RD
output reg co_RegDest,
// Mux selecting the source of the ALU B operand
// 0 - Value of RT register
// 1 - instruction Imediate part
output reg co_ALUSource,
// ALU Control signal, select ALU operation
output reg [3:0] co_ALUControl,
// Memory write enable signal
output reg co_MemWrite,
// Mux selecting the source of the data for the register writeback
// 0 - output of ALU
// 1 - data read from memory
output reg co_RegWSource,
// Register writeback enable signal
output reg co_RegWrite,
// Unused...
output reg co_Branch
);
always @(i_Opcode, i_Function) begin
case (i_Opcode)
`OP_SPECIAL: begin
co_RegDest = 1;
co_ALUSource = 0;
co_MemWrite = 0;
co_RegWSource = 0;
co_RegWrite = 1;
co_Branch = 0;
case (i_Function)
`FUNCT_ADD: co_ALUControl = `ALU_ADD;
`FUNCT_ADDU: co_ALUControl = `ALU_ADD;
`FUNCT_AND: co_ALUControl = `ALU_AND;
`FUNCT_DIV: co_ALUControl = `ALU_DIV;
`FUNCT_DIVU: co_ALUControl = `ALU_DIV;
`FUNCT_MULT: co_ALUControl = `ALU_MUL;
`FUNCT_MULTU: co_ALUControl = `ALU_MUL;
`FUNCT_NOR: co_ALUControl = `ALU_NOR;
`FUNCT_OR: co_ALUControl = `ALU_OR;
`FUNCT_SLT: co_ALUControl = `ALU_SLT;
`FUNCT_SUB: co_ALUControl = `ALU_SUB;
`FUNCT_SUBU: co_ALUControl = `ALU_SUB;
`FUNCT_XOR: co_ALUControl = `ALU_XOR;
endcase
end
`OP_LW: begin
co_RegDest = 0;
co_ALUSource = 1;
co_ALUControl = 0;
co_MemWrite = 0;
co_RegWSource = 1;
co_RegWrite = 1;
co_Branch = 0;
end
`OP_SW: begin
co_RegDest = 0;
co_ALUSource = 1;
co_ALUControl = 0;
co_MemWrite = 1;
co_RegWSource = 0;
co_RegWrite = 0;
co_Branch = 0;
end
6'b001???: // all immediate arith/logic
begin
co_RegDest = 0;
co_ALUSource = 1;
co_MemWrite = 0;
co_RegWSource = 0;
co_RegWrite = 1;
co_Branch = 0;
case (i_Opcode)
`OP_ADDI: co_ALUControl = `ALU_ADD;
`OP_ADDIU: co_ALUControl = `ALU_ADD;
`OP_ANDI: co_ALUControl = `ALU_AND;
`OP_ORI: co_ALUControl = `ALU_OR;
`OP_XORI: co_ALUControl = `ALU_XOR;
`OP_SLTI: co_ALUControl = `ALU_SLT;
`OP_SLTIU: co_ALUControl = `ALU_SLT;
endcase
end
default: begin
co_RegDest = 0;
co_ALUSource = 1;
co_MemWrite = 0;
co_RegWSource = 0;
co_RegWrite = 0;
co_Branch = 0;
co_ALUControl = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, j, k, e, x, l[7], r[7]; double p, c, res, f[7][7][3]; int main() { scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d%d , &l[i], &r[i]); for (i = 1; i <= 10000; i++) { memset(f, 0, sizeof(f)); f[0][0][0] = 1; for (j = 0; j < n; j++) { p = 1. / (r[j] - l[j] + 1.); for (k = 0; k <= j; k++) for (e = 0; e < 2; e++) if (f[j][k][e]) { x = min(r[j] + 1, i) - l[j]; if (x > 0) f[j + 1][k][e] += f[j][k][e] * x * p; if (i >= l[j] && i <= r[j]) f[j + 1][k + 1][e] += f[j][k][e] * p; x = r[j] - max(l[j] - 1, i); if (x > 0) f[j + 1][k][e + 1] += f[j][k][e] * x * p; } } for (c = 0, k = 1; k <= j; k++) for (e = 0; e < 2; e++) if ((k > 1 && e == 0) || e == 1) c += f[n][k][e]; res += c * i; } printf( %.15lf n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T load() { T r; cin >> r; return r; } template <typename T> vector<T> loadMany(int n) { vector<T> rs(n); generate(rs.begin(), rs.end(), &load<T>); return rs; } struct StrInt { StrInt(const string& ref) : ref(ref) {} int operator[](int i) const { return ref[i] - a ; } int size() const { return (int)ref.size(); } const string& ref; }; struct Trans { explicit Trans(int k) : k(k), tab(k, -1), rev(k, -1) {} Trans() : tab() {} void add(int from, int to) { tab[from] = to; rev[to] = from; } int get(int i) { return tab[i]; } bool loose(int i) { return tab[i] == -1; } bool free(int j) { return rev[j] == -1; } bool anyRangeFree(int j1, int j2) { for (auto j = j1; j <= j2; ++j) if (free(j)) return true; return false; } int findRangeFree(int j1, int j2) { for (auto j = j1; j <= j2; ++j) if (free(j)) return j; return -1; } bool defined() { return not tab.empty(); } void fillWithAny() { auto j = 0; for (auto i = 0; i < k; ++i) if (loose(i)) { while (not free(j)) ++j; add(i, j); } } void print() { for (auto i = 0; i < k; ++i) cout << (char)( a + tab[i]); } int k; vector<int> tab; vector<int> rev; }; Trans solveA(int i, int k, StrInt s, StrInt a, Trans&& trans) { auto n = (int)s.size(); if (trans.loose(s[i]) and trans.free(a[i])) trans.add(s[i], a[i]); else if (trans.loose(s[i])) return {}; ++i; for (; i < n; ++i) if (trans.loose(s[i]) and trans.anyRangeFree(a[i] + 1, k - 1)) return trans.add(s[i], trans.findRangeFree(a[i] + 1, k - 1)), move(trans); else if (trans.loose(s[i]) and trans.free(a[i])) trans.add(s[i], a[i]); else if (trans.loose(s[i])) return {}; else if (trans.get(s[i]) > a[i]) return move(trans); else if (trans.get(s[i]) < a[i]) return {}; return move(trans); } Trans solveB(int i, int, StrInt s, StrInt b, Trans&& trans) { auto n = (int)s.size(); if (trans.loose(s[i]) and trans.free(b[i])) trans.add(s[i], b[i]); else if (trans.loose(s[i])) return {}; ++i; for (; i < n; ++i) if (trans.loose(s[i]) and trans.anyRangeFree(0, b[i] - 1)) return trans.add(s[i], trans.findRangeFree(0, b[i] - 1)), move(trans); else if (trans.loose(s[i]) and trans.free(b[i])) trans.add(s[i], b[i]); else if (trans.loose(s[i])) return {}; else if (trans.get(s[i]) < b[i]) return move(trans); else if (trans.get(s[i]) > b[i]) return {}; return move(trans); } Trans solve(int k, StrInt s, StrInt a, StrInt b) { auto n = s.size(); auto trans = Trans(k); auto i = 0; for (; i < n; ++i) if (a[i] != b[i] and trans.loose(s[i])) break; else if (a[i] != b[i] and (a[i] < trans.get(s[i]) and trans.get(s[i]) < b[i])) return trans; else if (a[i] != b[i] and a[i] == trans.get(s[i])) return solveA(i, k, s, a, move(trans)); else if (a[i] != b[i] and b[i] == trans.get(s[i])) return solveB(i, k, s, b, move(trans)); else if (trans.loose(s[i]) and trans.free(a[i])) trans.add(s[i], a[i]); else if (trans.loose(s[i])) return {}; else if (not(a[i] <= trans.get(s[i]) and trans.get(s[i]) <= b[i])) return {}; if (i == n) return trans; if (trans.anyRangeFree(a[i] + 1, b[i] - 1)) return trans.add(s[i], trans.findRangeFree(a[i] + 1, b[i] - 1)), move(trans); auto ans1 = solveA(i, k, s, a, Trans(trans)); if (ans1.defined()) return ans1; auto ans2 = solveB(i, k, s, b, move(trans)); return ans2; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); auto t = load<int>(); while (t-- > 0) { auto k = load<int>(); auto s = load<string>(); auto a = load<string>(); auto b = load<string>(); auto ans = solve(k, s, a, b); if (ans.defined()) { ans.fillWithAny(); cout << YES n ; ans.print(); cout << n ; } else cout << NO n ; } }
|
#include <bits/stdc++.h> using namespace std; int n, m; int visited[200001]; int colour[200001]; vector<int> adj_list[200001]; int* graph[1000001]; int* finalcolour[1000001]; int size[1000001]; int check; int count1 = 0; int k[9]; int l[9]; int dp[9][1001]; int A[9][11]; int c[9][10]; bool pairCompare(const pair<int, int>& firstElem, const pair<int, int>& secondElem) { return firstElem.first > secondElem.first; } int solve(int cards, int coins) { int i; if (cards <= 0) return 0; if (dp[cards][coins] != -1) return dp[cards][coins]; int ret = A[cards][l[cards]] + solve(cards - 1, coins); int use = 0; int coins_left = coins; for (i = l[cards] + 1; i <= k[cards]; i++) { coins_left = coins_left - c[cards][i - 1]; if (coins_left >= 0) ret = max(ret, A[cards][i] + solve(cards - 1, coins_left)); else break; } dp[cards][coins] = ret; return ret; } long long powe(long long a, long long b, long long k) { if (b == 0) return 1; long long temp = powe(a, b / 2, k); temp *= temp; if (temp >= k) temp %= k; if (b % 2 == 1) temp *= a; if (temp >= k) temp %= k; return temp; } void dfs(int x) { int i; visited[x] = 1; for (i = 0; i < adj_list[x].size(); i++) { if (visited[adj_list[x][i]] == 0) { printf( %d , x); if (colour[x] == -1) { colour[x] = 1; } else { colour[x] = -1; } dfs(adj_list[x][i]); if (colour[adj_list[x][i]] == -1) { printf( %d %d , x, adj_list[x][i]); colour[adj_list[x][i]] = 1; if (colour[x] == -1) { colour[x] = 1; } else { colour[x] = -1; } } } } printf( %d , x); if (colour[x] == -1) { colour[x] = 1; } else { colour[x] = -1; } } int main() { int n, i, count = 0; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &colour[i]); visited[i] = 0; if (colour[i] == 1) count++; } for (i = 1; i < n; i++) { int x, y; scanf( %d %d , &x, &y); adj_list[x].push_back(y); adj_list[y].push_back(x); } if (count == n) { printf( 1 n ); return 0; } if (colour[1] == -1) colour[1] = 1; else colour[1] = -1; dfs(1); if (colour[1] == -1) { printf( %d 1 %d , adj_list[1][0], adj_list[1][0]); } return 0; }
|
// Author: Adam Nunez,
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module PulseCounter(
input Reset,
input Clock,
input In,
output [3:0] Out
);
reg [3:0] Counter;
reg toggle;
// This module takes a bit input
// and returns the number of times
// that input has been pulsed.
// It has an active low reset.
always @(posedge Clock, negedge Reset) begin
if ( Reset == 0 )
Counter <= 4'b0000;
else begin
if ((In==1) & (toggle==0)) begin
Counter <= Counter + 1'b1;
toggle <= 1;
end
else if (In==0) begin
toggle <= 0;
end
end
end
assign Out = Counter;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e7 + 10; int n; vector<string> a; vector<pair<pair<int, int>, int> > pos; char s[N]; int main() { scanf( %d , &n); for (int i = (0); i < (n); i++) { int m; string t; cin >> t; a.push_back(t); scanf( %d , &m); for (int j = (0); j < (m); j++) { int at; scanf( %d , &at); at--; pos.push_back(make_pair(make_pair(at, -(int)a[i].size()), i)); } } sort(pos.begin(), pos.end()); int p = 0; for (int i = (0); i < ((int)pos.size()); i++) { int at = pos[i].first.first, len = -pos[i].first.second, id = pos[i].second; while (p < at) s[p++] = a ; if (p >= at && p < at + len) { for (int j = (p - at); j < (len); j++) s[p++] = a[id][j]; } } printf( %s n , s); return 0; }
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
/*
* This is the top level or 'root' of the design.
*
* This level should contain device-specific changes, signal inversions,
* tri-state and testability logic.
*
* For example, PLL's and other device specific things would
* be instantiated at this level.
*
*
* Modules further down in the heirarchy should be generic so that
* different FPGA's can be retargeted with minimal fuss.
*
*/
module root(clk, rstn, datain_ch0, datain_ch1, datain_ch2, datain_ch3, serialout, testout0, testout1, testout2, testout3);
input clk;
input rstn;
input datain_ch0;
input datain_ch1;
input datain_ch2;
input datain_ch3;
output serialout;
output testout0;
output testout1;
output testout2;
output testout3;
system sys0(
.clk(clk),
.rstn(rstn),
.datain_ch0(datain_ch0),
.datain_ch1(datain_ch1),
.datain_ch2(datain_ch2),
.datain_ch3(datain_ch3),
.serialout(serialout),
.testout0(testout0),
.testout1(testout1),
.testout2(testout2),
.testout3(testout3)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_2_V
`define SKY130_FD_SC_MS__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_2_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 40,
NUM_STAGE = 8,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_6_max_dsp_32 convolve_kernel_ap_fmul_6_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @ (posedge clk) begin
ce_r <= ce;
end
always @ (posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r?dout_i:dout_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<string> v; vector<int> vn; for (int i = 0; i < n; i++) { string a; cin >> a; bool cn = false; int y = 0; for (int j = 0; j < v.size(); j++) { if (a == v[j]) { y = j; cn = true; break; } } if (cn) { vn[y]++; } else { v.push_back(a); vn.push_back(1); } } int rpta = vn[0]; for (int i = 1; i < vn.size(); i++) { rpta = max(rpta, vn[i]); } cout << rpta << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class node> struct link_cut_tree { bool connected(node* u, node* v) { return lca(u, v) != NULL; } int depth(node* u) { access(u); return get_sz(u->ch[0]); } node* get_root(node* u) { access(u); while (u->ch[0]) u = u->ch[0], u->push(); return access(u), u; } node* ancestor(node* u, int k) { k = depth(u) - k; for (;; u->push()) { int sz = get_sz(u->ch[0]); if (sz == k) return access(u), u; if (sz < k) k -= sz + 1, u = u->ch[1]; else u = u->ch[0]; } } node* lca(node* u, node* v) { if (u == v) return u; access(u); access(v); if (!u->p) return NULL; u->splay(); return u->p ?: u; } void link(node* u, node* v) { make_root(v); access(u); set_link(v, u, 0); v->update(); } void cut(node* u) { access(u); u->ch[0]->p = NULL; u->ch[0] = NULL; u->update(); } void cut(node* u, node* v) { cut(depth(u) > depth(v) ? u : v); } void make_root(node* u) { access(u); u->rev ^= 1; access(u); } void access(node* u) { for (node *v = u, *pre = NULL; v; v = v->p) { v->splay(); if (pre) v->update_vsub(pre, false); if (v->ch[1]) v->update_vsub(v->ch[1], true); v->ch[1] = pre; v->update(); pre = v; } u->splay(); } node* operator[](int i) { return &data[i]; } int operator[](node* i) { return i - &data[0]; } vector<node> data; link_cut_tree(int n) : data(n) {} }; template <typename pnode> struct splay_tree { pnode ch[2], p; bool rev; int sz; splay_tree() { ch[0] = ch[1] = p = NULL; rev = 0; sz = 1; } friend int get_sz(pnode u) { return u ? u->sz : 0; } virtual void update() { if (ch[0]) ch[0]->push(); if (ch[1]) ch[1]->push(); sz = 1 + get_sz(ch[0]) + get_sz(ch[1]); } virtual void push() { if (rev) { if (ch[0]) ch[0]->rev ^= 1; if (ch[1]) ch[1]->rev ^= 1; swap(ch[0], ch[1]); rev = 0; } } int dir() { if (!p) return -2; if (p->ch[0] == this) return 0; if (p->ch[1] == this) return 1; return -1; } bool is_root() { return dir() < 0; } friend void set_link(pnode u, pnode v, int d) { if (v) v->p = u; if (d >= 0) u->ch[d] = v; } void rotate() { int x = dir(); pnode g = p; set_link(g->p, static_cast<pnode>(this), g->dir()); set_link(g, ch[x ^ 1], x); set_link(static_cast<pnode>(this), g, x ^ 1); g->update(); update(); } void splay() { while (!is_root() && !p->is_root()) { p->p->push(), p->push(), push(); dir() == p->dir() ? p->rotate() : rotate(); rotate(); } if (!is_root()) p->push(), push(), rotate(); push(); } }; struct node; node* root; bool capture; vector<pair<int, int>> vec; struct node : splay_tree<node*> { using splay_tree::ch; int val, lazy; node() : splay_tree() { val = -1e9; lazy = -1; } void update() override { splay_tree::update(); } void update_vsub(node* v, bool add) { if (!add && capture) vec.push_back({this - root, val}); } void push() override { splay_tree::push(); if (lazy != -1) { val = lazy; if (ch[0]) ch[0]->lazy = lazy; if (ch[1]) ch[1]->lazy = lazy; lazy = -1; } } }; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; vector<vector<pair<int, int>>> adj(n); for (int i = 1, u, v, w; i < n; ++i) { cin >> u >> v >> w; --u, --v; adj[u].push_back({v, w}); } vector<long long> dist(n); vec.reserve(n); link_cut_tree<node> lct(n); function<void(int)> dfs_access = [&](int u) { for (auto v : adj[u]) { dist[v.first] = dist[u] + v.second; lct.link(lct[u], lct[v.first]); dfs_access(v.first); } }; dfs_access(0); root = lct[0]; vector<pair<long long, long long>> s; for (int i = 0, d, t; i < m; ++i) { cin >> d >> t; --d; auto u = lct[d], v = u; while (!v->is_root()) v = v->p, v->push(); while (v->ch[1]) v = v->ch[1], v->push(); vec.clear(); capture = true; lct.access(u); capture = false; for (auto x : vec) s.push_back({dist[x.first] + x.second, dist[x.first] + t}); int val = u->val; u->lazy = t; u->push(); u->val = val; lct.access(v); } long long explosion = -1, changes = s.size(); sort(s.begin(), s.end()); priority_queue<long long, vector<long long>, greater<long long>> pq; for (long long t = 1, i = 0; i < s.size() || !pq.empty();) { if (pq.empty() && t <= s[i].first) t = s[i].first + 1; while (i < s.size() && s[i].first < t) pq.push(s[i].second), ++i; if (t > pq.top()) { explosion = t - 1; break; } pq.pop(); ++t; } if (explosion != -1) changes -= count_if(s.begin(), s.end(), [&](pair<long long, long long> x) { return x.second >= explosion; }); cout << explosion << << changes << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, x, p, q, ans = 0, cnt = 0; ; cin >> n >> k >> x; int a[n + 5]; for (int i = 1; i <= n; i++) { cin >> a[i]; } if (n == 1) { cout << x << endl; return 0; } for (int i = n; i > 1; i--) { if (a[i] >= a[i - 1] && cnt < k) { cnt++; ans += x; } else ans += a[i]; } if (cnt < k && a[1] <= a[2]) ans += x; else ans += a[1]; cout << ans << endl; }
|
module RM_ctrl (
input rst,
input[`ByteSlctWidth-1:0] byte_slct,
input[`OpcodeWidth-1:0] opcode,
input[`RegDataWidth-1:0] raw_mem_data,
output reg[`RegDataWidth-1:0] data_to_reg
);
reg[`ByteBus] read_byte;
reg[`HalfWordBus] read_half_word;
always @(*) begin : proc_read_byte
case (byte_slct)
4'b1000 : read_byte <= raw_mem_data[31:24];
4'b0100 : read_byte <= raw_mem_data[23:16];
4'b0010 : read_byte <= raw_mem_data[15:8];
4'b0001 : read_byte <= raw_mem_data[7:0];
default : read_byte <= `ZeroWord;
endcase
end
always @(*) begin : proc_read_half_word
case (byte_slct)
4'b1100 : read_half_word <= raw_mem_data[31:16];
4'b0011 : read_half_word <= raw_mem_data[15:0];
default : read_half_word <= `ZeroWord;
endcase
end
always @(*) begin : proc_read_mem_control
if (rst == ~`RstEnable) begin
case (opcode)
`mips_lb : data_to_reg <= {{24{read_byte[7]}}, read_byte};
`mips_lh : data_to_reg <= {{16{read_half_word[15]}}, read_half_word};
`mips_lw : data_to_reg <= raw_mem_data;
`mips_lbu : data_to_reg <= {24'b0, read_byte};
`mips_lhu : data_to_reg <= {16'b0, read_half_word};
default : data_to_reg <= `ZeroWord;
endcase
end
else data_to_reg <= `ZeroWord;
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 1 14:04:03 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_adc/clk_adc_stub.v
// Design : clk_adc
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_adc(clk_in1_p, clk_in1_n, clk_250Mhz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1_p,clk_in1_n,clk_250Mhz,locked" */;
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9680_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [55:0] adc_data_a;
output [55:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s3_s;
wire [15:0] adc_data_a_s2_s;
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s3_s;
wire [15:0] adc_data_b_s2_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0],
adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0],
adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
// data multiplex
assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]};
assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]};
assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]};
assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]};
assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]};
assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]};
assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]};
assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int n; string s; int main() { cin >> n; cin >> s; bool tmp = false; for (int i = 0; i <= s.size() - 1; i++) { if (s[i] > s[i + 1]) { tmp = true; s.erase(i, 1); break; } } if (!tmp) s.erase(s.size() - 1, 1); cout << s; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T mod_v(T num) { if (num >= 0) return num % 1000000007; else return (num % 1000000007 + 1000000007) % 1000000007; } template <class T> inline T gcd(T a, T b) { a = abs(a); b = abs(b); while (b) { a = a % b; swap(a, b); } return a; } template <class T> T fast_pow(T n, T p) { if (p == 0) return 1; if (p % 2) { T g = mod_v(mod_v(n) * mod_v(fast_pow(n, p - 1))); return g; } else { T g = fast_pow(n, p / 2); g = mod_v(mod_v(g) * mod_v(g)); return g; } } template <class T> inline T modInverse(T n) { return fast_pow(n, 1000000007 - 2); } template <class T> inline void debug(string S1, T S2, string S3) { cout << S1 << S2 << S3; } template <class T> inline T in() { register char c = 0; register T num = 0; bool n = false; while (c < 33) c = getchar(); while (c > 33) { if (c == - ) n = true; else num = num * 10 + c - 0 ; c = getchar(); } return n ? -num : num; } class data { public: int t, w; }; int dp[108][208][208]; int n; data ara[108]; vector<int> ans; int re(int p, int s, int u) { if (p == n) { return s; return ((s >= u) ? s : 100000000); } if (dp[p][s][u] != -1) return dp[p][s][u]; dp[p][s][u] = 1 << 30; if (u - ara[p].w - ara[p].t >= 0) { dp[p][s][u] = min(dp[p][s][u], re(p + 1, s - ara[p].t, u - ara[p].t - ara[p].w)); } ans.push_back(p + 1); dp[p][s][u] = min(dp[p][s][u], re(p + 1, s, u)); ans.pop_back(); return dp[p][s][u]; } int main() { n = in<int>(); int t = 0, w = 0; for (int i = 0; i < n; i++) { scanf( %d %d , &ara[i].t, &ara[i].w); t += ara[i].t; } memset(dp, -1, sizeof(dp)); ; printf( %d n , re(0, t, t)); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1, ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { write(x); puts( ); } const long long N = 5e5 + 5; long long q, sum[N], a[N], cnt; inline double f(long long x) { return (double)a[cnt] - (sum[x] + a[cnt]) / (double)(x + 1); } signed main() { q = read(); for (long long i = 1; i <= q; i++) { long long l, r, opt = read(); if (opt == 1) { a[++cnt] = read(); sum[cnt] = sum[cnt - 1] + a[cnt]; } else { l = 1, r = cnt - 1; while (l < r - 2) { long long k = (r - l) / 3; long long lmid = l + k, rmid = r - k; if (f(lmid) > f(rmid)) { r = rmid; } else { if (f(lmid) < f(rmid)) { l = lmid; } else { l = lmid; r = rmid; } } } double ans = 0; for (long long j = l; j <= r; j++) ans = max(ans, f(j)); printf( %.8lf n , ans); } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg b;
wire vconst1 = 1'b0;
wire vconst2 = !(vconst1);
wire vconst3 = !vconst2;
wire vconst = vconst3;
wire qa;
wire qb;
wire qc;
wire qd;
wire qe;
ta ta (.b(b), .vconst(vconst), .q(qa));
tb tb (.clk(clk), .vconst(vconst), .q(qb));
tc tc (.b(b), .vconst(vconst), .q(qc));
td td (.b(b), .vconst(vconst), .q(qd));
te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$display("%b",{qa,qb,qc,qd,qe});
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
b <= 1'b1;
end
if (cyc==2) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
b <= 1'b0;
end
if (cyc==3) begin
if (qa!=1'b0) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b0) $stop;
b <= 1'b1;
end
if (cyc==4) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b1) $stop;
b <= 1'b0;
end
if (cyc==5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module ta (
input vconst,
input b,
output reg q);
always @ (/*AS*/b or vconst) begin
q = vconst | b;
end
endmodule
module tb (
input vconst,
input clk,
output reg q);
always @ (posedge clk) begin
q <= vconst;
end
endmodule
module tc (
input vconst,
input b,
output reg q);
always @ (posedge vconst) begin
q <= b;
$stop;
end
endmodule
module td (
input vconst,
input b,
output reg q);
always @ (/*AS*/vconst) begin
q = vconst;
end
endmodule
module te (
input clk,
input vconst,
input b,
output reg q);
reg qmid;
always @ (posedge vconst or posedge clk) begin
qmid <= b;
end
always @ (posedge clk or posedge vconst) begin
q <= qmid;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<bool> visited; vector<vector<long long> > adj; vector<vector<long long> > rev; vector<long long> order; vector<char> col; void dfs1(long long x) { visited[x] = true; for (auto y : adj[x]) { if (!visited[y]) dfs1(y); } order.push_back(x); } void dfs2(long long x, char colour) { visited[x] = true; col[x] = colour; for (auto y : rev[x]) { if (!visited[y]) { dfs2(y, colour); } } } int32_t main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j; long long n, k; cin >> n >> k; adj.resize(n); rev.resize(n); long long p[n]; for (i = 0; i < n; i++) cin >> p[i]; for (i = 0; i < n - 1; i++) { long long u = p[i + 1] - 1; long long v = p[i] - 1; adj[v].push_back(u); rev[u].push_back(v); } for (i = 0; i < n; i++) cin >> p[i]; for (i = 0; i < n - 1; i++) { long long u = p[i + 1] - 1; long long v = p[i] - 1; adj[v].push_back(u); rev[u].push_back(v); } visited.assign(n, false); for (long long i = 0; i < n; i++) { if (!visited[i]) dfs1(i); } visited.assign(n, false); reverse(order.begin(), order.end()); vector<long long> condensed[n]; char colour = a ; col.resize(n); for (i = 0; i < n; i++) { long long v = order[i]; if (!visited[v]) { dfs2(v, colour); if (colour != z ) ++colour; } } set<long long> numCols; for (i = 0; i < n; i++) { numCols.insert(col[i]); } if (numCols.size() >= k) cout << YES << n ; else { cout << NO << n ; return 0; } for (auto ch : col) cout << ch; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T, class L> bool smax(T &x, L y) { return x < y ? (x = y, 1) : 0; } template <class T, class L> bool smin(T &x, L y) { return y < x ? (x = y, 1) : 0; } const int maxn = 20, maxm = 1e5 + 17; char c[maxm]; int n, m, col[maxm]; int dp[maxn + 1][1 << maxn], ans[1 << maxn]; int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) { cin >> c; for (int j = 0; j < m; j++) col[j] |= c[j] - 0 << i; } for (int i = 0; i < m; i++) dp[0][col[i]]++; for (int i = 0; i < n; i++) for (int k = n; k; k--) for (int mask = 0; mask < 1 << n; mask++) dp[k][mask] += dp[k - 1][mask ^ (1 << i)]; int po = 1 << n; for (int i = 0; i <= n; i++) { int x = min(i, n - i); for (int mask = 0; mask < po; mask++) ans[mask] += x * dp[i][mask]; } cout << *min_element(ans, ans + po) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mxn(3e5 + 10), mxm(4e5 + 10); const long long modl(998244353); int nm, n, m, p, t, k; int ans; int a[mxn], b[mxn], c[mxn]; int main() { ios_base::sync_with_stdio(false); cin >> nm; while (cin >> n >> m) { ans = max(0, n + m - 3) / m + 1; cout << ans; cout << endl; } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
phy_reset_n,
phy_mdc,
phy_mdio,
phy_tx_clk,
phy_tx_ctrl,
phy_tx_data,
phy_rx_clk,
phy_rx_ctrl,
phy_rx_data,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
output phy_reset_n;
output phy_mdc;
inout phy_mdio;
output phy_tx_clk;
output phy_tx_ctrl;
output [ 3:0] phy_tx_data;
input phy_rx_clk;
input phy_rx_ctrl;
input [ 3:0] phy_rx_data;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [12:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// default logic
assign mgt_clk_sel = 2'd0;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
.dio_t (gpio_t[12:0]),
.dio_i (gpio_o[12:0]),
.dio_o (gpio_i[12:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.hdmi_24_data (hdmi_data),
.hdmi_24_data_e (hdmi_data_e),
.hdmi_24_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_24_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_06 (1'b0),
.mb_intr_12 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_io (phy_mdio),
.mdio_mdc (phy_mdc),
.phy_rst_n (phy_reset_n),
.rgmii_rd (phy_rx_data),
.rgmii_rx_ctl (phy_rx_ctrl),
.rgmii_rxc (phy_rx_clk),
.rgmii_td (phy_tx_data),
.rgmii_tx_ctl (phy_tx_ctrl),
.rgmii_txc (phy_tx_clk),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long resp, n, m, tt; int main() { cin >> n >> m; if (m % 2 == 0) { tt = m / 2; tt = tt * (tt + 1) - tt; } else { tt = m / 2; tt = tt * (tt + 1); } for (long long i = 2; i <= n; i += 2) { resp += tt * (n - i + 1); } cout << resp; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1005; const int INF = 0x3f3f3f3f; int a[MAXN]; int book[MAXN * 2]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int tmp; scanf( %d , &tmp); a[tmp] = 1; } queue<int> Q; memset(book, 0x3f, sizeof(book)); for (int i = 0; i <= 1000; i++) { if (a[i]) { book[i - n + MAXN] = 1; Q.push(i - n + MAXN); } } while (!Q.empty()) { if (book[MAXN] != INF) { return 0 * printf( %d n , book[MAXN]); } int now = Q.front(); Q.pop(); for (int i = 0; i <= 1000; i++) { if (!a[i]) continue; int co = i - n; int nxt = now + co; if (nxt < 0 || nxt > 2005) continue; if (book[nxt] > book[now] + 1) { Q.push(nxt); book[nxt] = book[now] + 1; } } } printf( -1 n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { double a, b, m, vx, vy, vz; cin >> a >> b >> m >> vx >> vy >> vz; double X = a / 2 - m / vy * vx; double Z = -m / vy * vz; while (X < 0 || X > a) if (X > a) X = 2 * a - X; else X = -X; while (Z < 0 || Z > b) if (Z > b) Z = 2 * b - Z; else Z = -Z; printf( %.9lf %.9lf , X, Z); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[2000006], pp[2000006]; long long first[2000006], cur = 0, w[2000006], n, m, i, xx, second, d, h, ans, w1, p, tt, o, temp, t; void dfs(long long node, long long l) { if (node > n) return; long long i, j; first[node] = l; v[node].push_back(l); dfs(2 * node, l + w[2 * node]); dfs(2 * node + 1, l + w[2 * node + 1]); for (j = 0; j < v[2 * node].size(); ++j) v[node].push_back(v[2 * node][j]); for (j = 0; j < v[2 * node + 1].size(); ++j) v[node].push_back(v[2 * node + 1][j]); sort(v[node].begin(), v[node].end()); pp[node].resize(v[node].size()); pp[node][0] = v[node][0]; for (i = 1; i < v[node].size(); ++i) pp[node][i] = v[node][i] + pp[node][i - 1]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (i = 2; i <= n; ++i) cin >> w[i]; dfs(1, 0); for (i = 0; i < m; ++i) { ans = 0; cin >> d >> h; t = upper_bound(v[d].begin(), v[d].end(), h + first[d]) - v[d].begin(); if (t) ans = (h + first[d]) * t - pp[d][t - 1]; while (d != 1) { w1 = w[d]; p = d / 2; if (h > w1) ans += h - w1; o = d - (d % 2) + !(d % 2); if (o <= n) { temp = h - (w[o] + w1) + first[o]; tt = upper_bound(v[o].begin(), v[o].end(), temp) - v[o].begin(); if (tt) ans += tt * temp - pp[o][tt - 1]; } h -= w[d]; d >>= 1; } cout << ans << n ; } return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 15199 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16384,
w16383,
w32,
w16351,
w8,
w9,
w1152,
w15199;
assign w1 = i_data0;
assign w1152 = w9 << 7;
assign w15199 = w16351 - w1152;
assign w16351 = w16383 - w32;
assign w16383 = w16384 - w1;
assign w16384 = w1 << 14;
assign w32 = w1 << 5;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign o_data0 = w15199;
//multiplier_block area estimate = 6732.63349485736;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_1_V
`define SKY130_FD_SC_LP__SRDLRTP_1_V
/**
* srdlrtp: ????.
*
* Verilog wrapper for srdlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srdlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srdlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srdlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srdlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srdlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_1_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 300 * 1000 + 10; long long dist[MAX_N], dist1[MAX_N]; vector<pair<int, int>> adj[MAX_N]; set<pair<long long, int>> s; bool inPath[MAX_N]; pair<int, int> mx; int nxt[MAX_N]; bool dfs_path(int u, int par = -1) { for (auto x : adj[u]) { int v = x.first; if (v != par && dfs_path(v, u)) inPath[u] = true, nxt[u] = v; } return inPath[u]; } long long dfs_dist(int u, int par = -1) { if (inPath[u]) for (auto x : adj[u]) { int v = x.first, w = x.second; if (v == nxt[u]) dist1[v] = dist1[u] + w, dist[u] = dfs_dist(v, u) + w; } for (auto x : adj[u]) { int v = x.first, w = x.second; if (v != par && !inPath[v]) dist1[v] = dist1[u] + w, dist[v] = dist[u] + w, dfs_dist(v, u); } return dist[u]; } bool cmp(pair<int, int> a, pair<int, int> b) { if (min(a.first, b.first) < 0) return a.first < 0 ? true : false; return dist1[a.first] + dist[a.second] < dist1[b.first] + dist[b.second]; } void rem_block(int u, int par = -1) { s.erase({dist[u], u}); for (auto x : adj[u]) { int v = x.first; if (v != par) rem_block(v, u); } } void add_block(int u, int par = -1) { s.insert({dist[u], u}); for (auto x : adj[u]) { int v = x.first; if (v != par) add_block(v, u); } } void dfs(int u, int par = -1) { if (inPath[u]) { s.erase({dist[u], u}); for (auto x : adj[u]) { int v = x.first; if (v != par && v != nxt[u]) rem_block(v, u), dfs(v, u), add_block(v, u); } for (auto x : adj[u]) { int v = x.first; if (v != par && v != nxt[u]) rem_block(v, u); } for (auto it = s.rbegin(); it != s.rend(); it++) if (it->second != nxt[u]) { mx = max(make_pair(u, it->second), mx, cmp); break; } if (nxt[u] != u) dfs(nxt[u], u); } else if (!s.empty()) { mx = max(make_pair(u, (*s.rbegin()).second), mx, cmp); for (auto x : adj[u]) { int v = x.first; if (v != par) dfs(v, u); } } } int main() { ios_base ::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n, m; cin >> n >> m; for (int i = 1; i < n; i++) { int u, v, w; cin >> u >> v >> w; u--, v--; adj[u].push_back({v, w}); adj[v].push_back({u, w}); } inPath[n - 1] = true, nxt[n - 1] = n - 1, mx = {-1, -1}; dfs_path(0), dfs_dist(0), add_block(0), dfs(0); for (int i = 0; i < m; i++) { int x; cin >> x; cout << min(dist1[mx.first] + dist[mx.second] + x, dist[0]) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int setbit(int n, int pos) { return n = n | (1 << pos); } int resetbit(int n, int pos) { return n = n & ~(1 << pos); } bool checkbit(int n, int pos) { return (bool)(n & (1 << pos)); } template <typename T> T modMul(T x, T y, T mod = 1e9 + 7) { x %= mod; y %= mod; return (x * y) % mod; } template <typename T> T modAdd(T x, T y, T mod = 1e9 + 7) { x %= mod; y %= mod; return (x + y) % mod; } template <typename T> T ext_gcd(T num1, T num2, T &X, T &Y) { T r2, r1, q2, q1, x2, x1, y2, y1, x, y, r; x2 = 1; y2 = 0; x1 = 0; y1 = 1; for (r2 = num1, r1 = num2; r1 != 0; y2 = y1, y1 = y, x2 = x1, x1 = x, r2 = r1, r1 = r) { q1 = r2 / r1; x = x2 - q1 * x1; y = y2 - q1 * y1; r = r2 % r1; } X = x2; Y = y2; return r2; } template <typename T> void print(const T &v) { cerr << v << ; } template <typename T1, typename... T2> void print(const T1 &first, const T2 &...rest) { print(first); print(rest...); } template <class T> string to_str(T t) { stringstream second; second << t; return second.str(); } template <typename T> T modPow(T x, T k, T mod = 1e9 + 7) { if (k == 0) return (T)1; if (k & 1) { return ((x % mod) * modPow(x, k - 1, mod) % mod) % mod; } else { T ret = modPow(x, k / 2, mod); ret %= mod; return (ret * ret) % mod; } } template <typename T> T modInv(T x, T m) { return modPow(x, m - 2, m); } template <typename T> void dbg_a(T a[], int n = 10) { cerr << [ ; for (int i = 0; i < n; i++) cerr << a[i] << ; cerr << ] << n ; } template <typename F, typename S> ostream &operator<<(ostream &os, const pair<F, S> &p) { return os << [ << p.first << , << p.second << ] ; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << [ ; for (int i = 0; i < v.size(); i++) os << v[i] << ; return os << ] n ; } template <typename T> ostream &operator<<(ostream &os, const map<T, T> &Map) { os << [ ; for (__typeof((Map).begin()) it = (Map).begin(); it != (Map).end(); ++it) os << [ << (*it).first << << (*it).second << ] ; return os << ] n ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &Set) { os << [ ; for (__typeof((Set).begin()) it = (Set).begin(); it != (Set).end(); ++it) os << *it << ; return os << ] n ; } const int maxn = (int)2e6 + 123; const int inf = 0x3f; const long long mod = (long long)1e9 + 7LL; int a[maxn]; void solve() { int n, q, cnt = 0, ans = 0, magic = 0; vector<int> even, odd; string s; cin >> s; for (int i = 0; i < s.size(); i++) { int x = s[i] - 0 ; if (x & 1) odd.push_back(x); else even.push_back(x); } reverse(odd.begin(), odd.end()); reverse(even.begin(), even.end()); for (int i = 0; i < s.size(); i++) { if (odd.size() == 0) { cout << even.back(); even.pop_back(); } else if (even.size() == 0) { cout << odd.back(); odd.pop_back(); } else { if (even.back() < odd.back()) { cout << even.back(); even.pop_back(); } else { cout << odd.back(); odd.pop_back(); } } } cout << n ; } int main() { ios ::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1, c = 0; cin >> t; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_2_V
`define SKY130_FD_SC_HDLL__O22AI_2_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22ai_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; string s; cin >> s; int cnt = 0; for (int i = 0; i < n; i++) { int up = 0, le = 0; for (int j = i; j < n; j++) { if (s[j] == U ) up++; if (s[j] == D ) up--; if (s[j] == L ) le++; if (s[j] == R ) le--; if (up == 0 && le == 0) cnt++; } } cout << cnt << endl; }
|
#include <bits/stdc++.h> using namespace std; const int C = 10005, N = 1005; int n, w, b, x, c[N], cost[N]; long long dp[2][C]; template <class T> void maxz(T &a, T b) { if (a < b) a = b; } int main() { int i, j, k, ub; long long mn; scanf( %d%d%d%d , &n, &w, &b, &x); for (i = 1; i <= n; i++) scanf( %d , c + i); for (i = 1; i <= n; i++) scanf( %d , cost + i); memset(dp[0], -1, sizeof(dp[0])); ub = 1; dp[0][0] = w; for (i = 1; i <= n; i++) { memset(dp[i & 1], -1, sizeof(dp[0])); for (j = 0; j < ub; j++) if (dp[~i & 1][j] >= 0) { mn = min(dp[~i & 1][j] + x, w + (long long)b * j); for (k = 0; k <= c[i] && mn >= 0; k++) { maxz(dp[i & 1][j + k], mn); mn -= cost[i]; } maxz(ub, j + k); } } printf( %d , ub - 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int P = 1e9 + 7; int p[11]; vector<int> operator*(const vector<int> &lhs, const vector<int> &rhs) { vector<int> ret; ret.resize(lhs.size() + rhs.size() - 1, 0); for (int i = 0; i < lhs.size(); i++) { for (int j = 0; j < rhs.size(); j++) { ret[i + j] = (ret[i + j] + lhs[i] * 1LL * rhs[j]) % P; } } return ret; } vector<int> operator+(const vector<int> &lhs, const vector<int> &rhs) { vector<int> ret; ret.resize(max(lhs.size(), rhs.size()), 0); for (int i = 0; i < ret.size(); i++) ret[i] = ((i < lhs.size() ? lhs[i] : 0) + (i < rhs.size() ? rhs[i] : 0)) % P; return ret; } vector<int> modExp(vector<int> &a, long long m, vector<int> &c) { int n = a.size(); vector<int> ret(n, 0); ret[0] = 1; if (m == 0) return ret; for (int i = 63 - __builtin_clz(m); i >= 0; i--) { ret = ret * ret; if (m >> i & 1) ret = ret * a; for (int i = (int)ret.size() - 1; i >= n; i--) if (ret[i]) { for (int j = 0; j < n; j++) if (c[j]) ret[i - j - 1] = (ret[i - j - 1] + ret[i] * 1LL * c[j]) % P; } ret.resize(n); } return ret; } int main() { int F, B; long long N; cin >> F >> B >> N; for (int i = 1; i <= F; i++) cin >> p[i]; vector<int> a(250, 0), b(250, 0), c(250, 0); for (int i = 1; i <= B; i++) { int x; cin >> x; c[x - 1]++; } b[0] = 1; for (int i = 1; i < 250; i++) { for (int j = 0; j < i; j++) b[i] = (b[i] + b[i - j - 1] * 1LL * c[j]) % P; } a[1] = 1; vector<int> d(250, 0); for (int i = 1; i <= F; i++) d = d + modExp(a, p[i], c); d = modExp(d, N, c); int ans = 0; for (int i = 0; i < 250; i++) ans = (ans + d[i] * 1LL * b[i]) % P; cout << ans << endl; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_uart_transceiver_0_0 -prefix
// DemoInterconnect_uart_transceiver_0_0_ DemoInterconnect_uart_transceiver_0_0_stub.v
// Design : DemoInterconnect_uart_transceiver_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uart_top,Vivado 2017.3" *)
module DemoInterconnect_uart_transceiver_0_0(i_Clk, i_RX_Serial, o_RX_Done, o_RX_Byte,
i_TX_Load, i_TX_Byte, o_TX_Active, o_TX_Serial, o_TX_Done)
/* synthesis syn_black_box black_box_pad_pin="i_Clk,i_RX_Serial,o_RX_Done,o_RX_Byte[7:0],i_TX_Load,i_TX_Byte[7:0],o_TX_Active,o_TX_Serial,o_TX_Done" */;
input i_Clk;
input i_RX_Serial;
output o_RX_Done;
output [7:0]o_RX_Byte;
input i_TX_Load;
input [7:0]i_TX_Byte;
output o_TX_Active;
output o_TX_Serial;
output o_TX_Done;
endmodule
|
/*
* Wishbone Flash RAM core with delayed ack for Altera DE0 board
* Copyright (C) 2010 Donna Polehn <>
* delayed ack added 2014 by Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module flash16_dack #(
parameter delayed = 4
)
(
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_we_i,
input wb_adr_i, // Wishbone address line
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Pad signals
output [21:0] flash_addr_,
input [15:0] flash_data_,
output flash_we_n_,
output flash_oe_n_,
output flash_ce_n_,
output flash_rst_n_
);
// Registers and nets
wire op;
wire wr_command;
reg [21:0] address;
reg [delayed-1:0] delay;
// Combinatorial logic
assign op = wb_stb_i & wb_cyc_i;
assign flash_rst_n_ = 1'b1;
assign flash_we_n_ = 1'b1;
assign flash_oe_n_ = !op;
assign flash_ce_n_ = !op;
assign flash_addr_ = address;
assign wr_command = op & wb_we_i; // Wishbone write access Signal
assign wb_ack_o = delay[delayed-1];
assign wb_dat_o = flash_data_;
// behaviour
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define FLASH_ALO 1'h0 // Lower 16 bits of address lines
`define FLASH_AHI 1'h1 // Upper 6 bits of address lines
always @(posedge wb_clk_i) // Synchrounous
if(wb_rst_i)
address <= 22'h000000; // Interupt Enable default
else
if(wr_command) // If a write was requested
case(wb_adr_i) // Determine which register was writen to
`FLASH_ALO: address[15: 0] <= wb_dat_i;
`FLASH_AHI: address[21:16] <= wb_dat_i[5:0];
default: ; // Default
endcase // End of case
// delay shift register
always @(posedge wb_clk_i)
delay <= wb_rst_i ? 1'd0
: (op & delay==1'd0 ? 1'd1 : { delay[delayed-2:0], 1'b0 });
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module zbroji_top (
aclk,
aresetn,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB,
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY,
interrupt
);
parameter C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH = 6;
parameter C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH = 32;
input aclk ;
input aresetn ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH/8 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY ;
output [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY ;
input [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY ;
output [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA ;
output [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP ;
output s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID ;
input s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY ;
output interrupt ;
wire aclk;
wire aresetn;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH/8 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY;
wire [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY;
wire [C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA;
wire [2 - 1:0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID;
wire s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY;
wire interrupt;
wire [32 - 1:0] sig_zbroji_a;
wire [32 - 1:0] sig_zbroji_b;
wire sig_zbroji_ap_start;
wire sig_zbroji_ap_ready;
wire sig_zbroji_ap_done;
wire sig_zbroji_ap_idle;
wire [32 - 1:0] sig_zbroji_ap_return;
zbroji zbroji_U(
.a(sig_zbroji_a),
.b(sig_zbroji_b),
.ap_start(sig_zbroji_ap_start),
.ap_ready(sig_zbroji_ap_ready),
.ap_done(sig_zbroji_ap_done),
.ap_idle(sig_zbroji_ap_idle),
.ap_return(sig_zbroji_ap_return)
);
zbroji_HLS_ZBROJI_PERIPH_BUS_if #(
.C_ADDR_WIDTH(C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH),
.C_DATA_WIDTH(C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH))
zbroji_HLS_ZBROJI_PERIPH_BUS_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.I_a(sig_zbroji_a),
.I_b(sig_zbroji_b),
.I_ap_start(sig_zbroji_ap_start),
.O_ap_ready(sig_zbroji_ap_ready),
.O_ap_done(sig_zbroji_ap_done),
.O_ap_idle(sig_zbroji_ap_idle),
.O_ap_return(sig_zbroji_ap_return),
.AWADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR),
.AWVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID),
.AWREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY),
.WDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA),
.WSTRB(s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB),
.WVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID),
.WREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY),
.BRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP),
.BVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID),
.BREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY),
.ARADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR),
.ARVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID),
.ARREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY),
.RDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA),
.RRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP),
.RVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID),
.RREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY),
.interrupt(interrupt));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j, k, n, m, ans = 0, sum = 0, a[100005] = {0}, mn = 2e9, mx = 0, x, y, z, cnt = 0; string s; set<long long> zero, one; set<long long>::iterator it, it1; vector<long long> v[200005]; cin >> s; for (i = 0; i < s.size(); i++) { if (s[i] == 0 ) { zero.insert(i); } else { one.insert(i); } } while (one.size()) { i = -1; if (zero.size() == 0) { cout << -1; return 0; } it = zero.lower_bound(i); i = *it; zero.erase(i); v[ans].push_back(i); while (one.size()) { it = one.lower_bound(i); if (it == one.end()) { break; } i = *it; one.erase(i); v[ans].push_back(i); it = zero.lower_bound(i); if (it == zero.end()) { cout << -1; return 0; } i = *it; zero.erase(i); v[ans].push_back(i); } ans++; } k = ans + zero.size(); cout << k << endl; for (i = 0; i < ans; i++) { for (j = 0; j < v[i].size(); j++) { if (j == 0) { cout << v[i].size() << ; } cout << v[i][j] + 1 << ; } cout << endl; } while (zero.size()) { it = zero.begin(); cout << 1 << << *it + 1 << endl; zero.erase(it); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { while (b) { a %= b; swap(a, b); } return a; } template <class T> inline T lcm(T a, T b) { return a / gcd(a, b) * b; } inline int nxt() { int wow; scanf( %d , &wow); return wow; } inline long long int lxt() { long long int wow; scanf( %lld , &wow); return wow; } inline double dxt() { double wow; scanf( %lf , &wow); return wow; } long long int dp[2][5002]; int main() { int n = nxt(), p = 0, c = 1; long long int a[5002], b[5002]; for (int i = 1; i <= n; i++) b[i] = a[i] = lxt() - i; sort(b + 1, b + n + 1); dp[1][0] = (long long int)1e17; for (int j = 1; j <= n; j++) dp[c][j] = min(dp[c][j - 1], abs(b[j] - a[1])); for (int i = 2; i <= n; i++) { swap(c, p); dp[c][0] = (long long int)1e17; for (int j = 1; j <= n; j++) dp[c][j] = min(dp[c][j - 1], abs(b[j] - a[i]) + dp[p][j]); } cout << dp[c][n] << endl; return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller Reset Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_rst.v,v 1.1 2001/08/03 06:54:50 rudi Exp $
//
// $Date: 2001/08/03 06:54:50 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_rst.v,v $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:19 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_);
input clk, rst;
input rst_force;
output ps_ce;
output ac97_rst_;
reg ac97_rst_;
reg [2:0] cnt;
wire ce;
wire to;
reg [5:0] ps_cnt;
wire ps_ce;
always @(posedge clk or negedge rst)
if(!rst) ac97_rst_ <= #1 0;
else
if(rst_force) ac97_rst_ <= #1 0;
else
if(to) ac97_rst_ <= #1 1;
assign to = (cnt == `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 0;
else
if(rst_force) cnt <= #1 0;
else
if(ce) cnt <= #1 cnt + 1;
assign ce = ps_ce & (cnt != `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) ps_cnt <= #1 0;
else
if(ps_ce | rst_force) ps_cnt <= #1 0;
else ps_cnt <= #1 ps_cnt + 1;
assign ps_ce = (ps_cnt == `AC97_250_PS);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 200000; int n; string s1, s2; int main() { cin >> n >> s1 >> s2; int K = 7; long long H = 0, HH = 0, D = 1; n--; for (int(i) = (1); i < (n + 1); ++(i)) { int p = 0, pp = 0; if (s1[n - i] == N ) p = 1; if (s1[n - i] == S ) p = 4; if (s1[n - i] == E ) p = 2; if (s1[n - i] == W ) p = 3; H = H * K + p; if (s2[n - i] == N ) pp = 4; if (s2[n - i] == S ) pp = 1; if (s2[n - i] == E ) pp = 3; if (s2[n - i] == W ) pp = 2; HH += D * (pp); D *= 7; if (H == HH) { cout << NO ; return 0; } } cout << YES ; }
|
#include <bits/stdc++.h> using namespace std; inline void intialize() { cin.tie(0); ios_base::sync_with_stdio(0); cout.tie(0); } void clearArr(int arr[], int n); bool arr[105][105]; bool farr[105]; queue<int> q; queue<int> done; int main() { intialize(); string ans[2] = { No , Yes }; string s; cin >> s; int ss = s.length(), i; stack<int> st; int t = 0; for (i = 0; i < ss; ++i) { if (st.empty()) st.push(s[i]); else { if (s[i] == st.top()) { t = (t + 1) % 2; st.pop(); } else { st.push(s[i]); } } } cout << ans[t] << endl; } void clearArr(int arr[], int n) { for (int i = 0; i < n; ++i) arr[i] = 0; }
|
#include <bits/stdc++.h> const int maxn = 200001, maxf = 19; const long long INF = 0x3f3f3f3f3f3f3f3fLL; int n, q, tot, lnk[maxn], dep[maxn], fa[maxn][maxf]; struct Edge { int v, nxt; } e[maxn << 1]; template <class T> void swap(T& x, T& y) { const T t = x; x = y; y = t; } template <class T> const T& min(const T& x, const T& y) { return x < y ? x : y; } void dfs(int u) { for (int it = lnk[u]; it; it = e[it].nxt) { int& v = e[it].v; if (v == fa[u][0]) continue; dep[v] = dep[u] + 1; fa[v][0] = u; for (int i = 1; fa[v][i - 1]; ++i) fa[v][i] = fa[fa[v][i - 1]][i - 1]; dfs(v); } } int deeper(int u, int v) { return dep[u] < dep[v] ? v : u; } int lca(int u, int v) { if (dep[u] > dep[v]) swap(u, v); for (int i = 0, j = dep[v] - dep[u]; j; ++i, j >>= 1) if (j & 1) v = fa[v][i]; if (u == v) return u; for (int i = maxf - 1; i >= 0; --i) if (fa[u][i] != fa[v][i]) { u = fa[u][i]; v = fa[v][i]; } return fa[u][0]; } int dist(int u, int v) { return dep[u] + dep[v] - (dep[lca(u, v)] << 1); } int gcd(int x, int y) { return y ? gcd(y, x % y) : x; } void exgcd(int a, int b, int& x, int& y) { if (!b) { x = 1; y = 0; return; } exgcd(b, a % b, y, x); y -= x * (a / b); } long long Case1(int t1, int d1, int t2, int d2) { int g = gcd(t1, t2), r = (d2 - d1) % t2; if (r < 0) r += t2; if (r % g != 0) return INF; int x, y; t1 /= g; t2 /= g; r /= g; exgcd(t1, t2, x, y); if (x < 0) x += t2; x = (long long)x * r % t2; return (long long)x * t1 * g + d1; } long long AMAC(int m, int d, int l, int r) { if (l % d == 0) return l / d; if (l / d != r / d) return l / d + 1; int g = gcd(m, d); if (l % g != 0 && l / g == r / g) return -1; long long res = AMAC(d, m % d, -r % d + d, -l % d + d); if (res == -1) return -1; return (res * m + l - 1) / d + 1; } long long Case2(int t1, int d1, int t2, int d2, int dd) { int m = t2, d = t1, l = (d2 - d1 - dd) % t2, r = (d2 - d1 + dd) % t2; if (l < 0) l += t2; if (r < 0) r += t2; if (l & 1) return INF; if (t2 == dd * 2 || l > r || l == 0) return d1 + r / 2; if (!(d %= m)) return INF; long long res = AMAC(m, d, l, r); if (res == -1) return INF; return t1 * res + d1 + dd - (t1 * res % t2 - l) / 2; return t1 * res + d1 + (((-t1 * res + d2 + dd - d1) / 2) % t2 + t2) % t2; } int main() { scanf( %d , &n); for (int i = 1, u, v; i < n; ++i) { scanf( %d%d , &u, &v); e[++tot] = (Edge){v, lnk[u]}; lnk[u] = tot; e[++tot] = (Edge){u, lnk[v]}; lnk[v] = tot; } dfs(1); scanf( %d , &q); while (q--) { int u, v, x, y; scanf( %d%d%d%d , &u, &v, &x, &y); int px = deeper(lca(u, x), lca(v, x)); int py = deeper(lca(u, y), lca(v, y)); int pp = deeper(lca(u, v), lca(x, y)); if (dep[px] < dep[pp] && dep[py] < dep[pp]) { puts( -1 ); continue; } if (dep[px] < dep[pp]) px = pp; else if (dep[py] < dep[pp]) py = pp; int f1 = dist(u, v) << 1, f2 = dist(x, y) << 1, d = dist(px, py); int t1 = dist(u, px), t2 = dist(u, py), t3 = dist(x, px), t4 = dist(x, py); if (t1 <= t2) t2 = f1 - t2; else t1 = f1 - t1; if (t3 <= t4) t4 = f2 - t4; else t3 = f2 - t3; long long ans = min(min(Case1(f1, t1, f2, t3), Case2(f1, t1, f2, t4, d)), min(Case1(f1, t2, f2, t4), Case2(f1, t2, f2, t3, d))); if (ans == INF) puts( -1 ); else printf( %I64d n , ans); } return 0; }
|
`timescale 1ns / 1ps
`define clkperiodby2 10
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/04/2015 02:52:37 PM
// Design Name:
// Module Name: tb_mult
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_mult;
// Inputs
reg clk;
reg [15 : 0] A, B;
// Outputs
wire [31 : 0] P;
// Instantiate the Unit Under Test (UUT)
MULT multiplier (
.clk(clk), // input clk
.a(A), // input [15 : 0] a
.b(B), // input [15 : 0] b
.p(P) // output [31 : 0] p
);
initial begin
// Initialize Inputs
clk = 0;
A = 0;
B = 0;
#300
A = -2;
B = 15;
#20
A = 3.1;
B = 4;
#20
A = 6;
B = 7;
#20
A = 4;
B = 15;
#20
A = 8;
B = 9;
#20
#100
$stop;
end
always
#`clkperiodby2 clk <= ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; string s; int main() { cin >> n >> s; int sol = n; for (int i = 1; i < n; i++) { if (s[i] != s[i - 1] and s[i - 1] != D ) { sol--; s[i] = D ; } } cout << sol << endl; }
|
#include <bits/stdc++.h> const int inf = (1ll << 30) - 1; const int maxn = (int)1e5 + 10; using namespace std; int dp[150][(1 << 16) + 100]; int c[111]; int r[111]; int b[111]; char temp[111]; int cntR[(1 << 16) + 10]; int cntB[(1 << 16) + 10]; int n; void solve() { memset(dp, -1, sizeof dp); queue<pair<pair<int, int>, int> > pq; scanf( %d , &n); int xx = 0; for (int i = 0; i < n; i++) { scanf( %s%d%d , temp, &r[i], &b[i]); c[i] = temp[0] == R ? 1 : 0; xx += c[i]; } for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < n; j++) { if (i & (1 << j)) { if (c[j]) cntR[i]++; else cntB[i]++; } } } dp[0][0] = 0; pq.push(make_pair(make_pair(0, 0), 0)); while (pq.size() > 0) { int x = pq.front().first.first; int y = pq.front().first.second; int mask = pq.front().second; pq.pop(); if (dp[x][mask] < y) continue; for (int i = 0; i < n; i++) { if (mask & (1 << i)) continue; int nmask = mask | (1 << i); int X = x, Y = y; if (r[i] >= cntR[mask]) { X += cntR[mask]; } else X += r[i]; if (b[i] >= cntB[mask]) { Y += cntB[mask]; } else Y += b[i]; if (dp[X][nmask] == -1 || dp[X][nmask] < Y) { dp[X][nmask] = Y; pq.push(make_pair(make_pair(X, Y), nmask)); } } } int sumA = 0, sumB = 0; for (int i = 0; i < n; i++) { sumA += r[i]; sumB += b[i]; } int ans = inf; for (int i = 0; i < 144; i++) { if (dp[i][(1 << n) - 1] == -1) continue; ans = min(ans, max(sumA - i, sumB - dp[i][(1 << n) - 1])); } printf( %d n , ans + n); } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int A[10010] = {0}; int D; int N, M, P; int g; int fact[20010] = {0}; int fp = 0; int Hash[20010] = {0}; int place[10010] = {0}; int F[20010] = {0}; long long power(long long a, long long k, long long Mod) { long long o = 1; for (; k > 0; k >>= 1) { if (k & 1) o = o * a % Mod; a = a * a % Mod; } return o; } int gcd(int a, int b) { return a % b == 0 ? b : gcd(b, a % b); } int getplace(int k) { for (int l = 1, r = fp; l <= r;) { int mid = (l + r) >> 1; if (fact[mid] == k) return mid; if (fact[mid] > k) r = mid - 1; else l = mid + 1; } return 0; } int main() { cin >> N >> M >> P; for (int i = 1; i * i <= P - 1; i++) { if ((P - 1) % i != 0) continue; fact[++fp] = i; if (i * i != (P - 1)) fact[++fp] = (P - 1) / i; } sort(fact + 1, fact + fp + 1); for (int i = 1; i <= N; i++) { scanf( %d , &A[i]); A[i] %= P; for (int j = 1; j <= fp; j++) { if (power(A[i], fact[j], P) == 1) { A[i] = (P - 1) / fact[j]; break; } } } D = P - 1; for (int i = 1; i <= M; i++) { int B; scanf( %d , &B); D = gcd(D, B); } P = (P - 1) / D; fp = 0; for (int i = 1; i * i <= P; i++) { if (P % i != 0) continue; fact[++fp] = i; if (i * i != P) fact[++fp] = P / i; } sort(fact + 1, fact + fp + 1); int Ans = 0; for (int i = 1; i <= N; i++) { A[i] = gcd(A[i], P); int place = getplace(A[i]); if (Hash[place] == 0) Ans += P / fact[place]; F[place] = 1; Hash[place] = 1; } for (int i = fp; i >= 1; i--) { for (int j = i + 1; j <= fp; j++) { if (fact[j] % fact[i] == 0) F[j] += F[i]; } } for (int i = 1; i <= fp; i++) { if (Hash[i] == 1) { int Need = -(F[i] - 1); Ans += Need * (P / fact[i]); for (int j = i + 1; j <= fp; j++) if (fact[j] % fact[i] == 0) { Hash[j] = 1; F[j] += Need; } } } cout << Ans << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// bug998
interface intf
#(parameter PARAM = 0)
();
logic val;
function integer func (); return 5; endfunction
endinterface
module t1(intf mod_intf);
initial begin
$display("%m %d", mod_intf.val);
end
endmodule
module t();
intf #(.PARAM(1)) my_intf [1:0] ();
generate
genvar the_genvar;
begin
for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf
begin
assign my_intf[the_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_genvar]));
end
end
end
endgenerate
generate
genvar the_second_genvar;
begin
intf #(.PARAM(1)) my_intf [1:0] ();
for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf
begin
assign my_intf[the_second_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_second_genvar]));
end
end
end
endgenerate
generate
genvar the_third_genvar;
begin
for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf
begin
intf #(.PARAM(1)) my_intf [1:0] ();
assign my_intf[the_third_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_third_genvar]));
end
end
end
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
`include "../lib/mux32bits_32to1.v"
module test;
reg [4:0] s;
reg [31:0] i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16;
reg [31:0] i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0;
wire [31:0] z;
reg [31:0] val, expect;
mux32bits_32to1 mux(
.s (s ),
.i31(i31),
.i30(i30),
.i29(i29),
.i28(i28),
.i27(i27),
.i26(i26),
.i25(i25),
.i24(i24),
.i23(i23),
.i22(i22),
.i21(i21),
.i20(i20),
.i19(i19),
.i18(i18),
.i17(i17),
.i16(i16),
.i15(i15),
.i14(i14),
.i13(i13),
.i12(i12),
.i11(i11),
.i10(i10),
.i9 (i9 ),
.i8 (i8 ),
.i7 (i7 ),
.i6 (i6 ),
.i5 (i5 ),
.i4 (i4 ),
.i3 (i3 ),
.i2 (i2 ),
.i1 (i1 ),
.i0 (i0 ),
.z (z ));
initial begin
$monitor($time, ": val=%d expect=%d", val, expect);
#5 i31 = 5 ; val = i31; s = 5'b11111; expect = 5 ;
#5 i25 = 345; val = i25; s = 5'b11001; expect = 345;
#5 i6 = 35 ; val = i6 ; s = 5'b00110; expect = 35 ;
#5 i16 = 276; val = i16; s = 5'b10000; expect = 276;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3fffffff; const int maxn = 100000 + 5, maxh = 800; int n, k; int f[maxh], g[maxh]; vector<int> P[maxn]; int main() { scanf( %d%d , &n, &k); for (int i = 1, iend = k; i <= iend; ++i) { int x, y; scanf( %d%d , &x, &y); P[y].push_back(n - x + 1); } for (int i = 1, iend = n; i <= iend; ++i) sort(P[i].begin(), P[i].end()); int hgt = sqrt(6 * k) + 5; memset(f, 0x3f, sizeof f); f[0] = 0; for (int i = 1, iend = n; i <= iend; ++i) { memcpy(g, f, sizeof f); memset(f, 0x3f, sizeof f); int minf = 0, pt = 0; for (int j = 0, jend = hgt; j <= jend; ++j) { if (pt < P[i].size() && P[i][pt] == j) pt++; if (g[j] < g[minf]) minf = j; f[j] = min(g[j + 1], g[minf] + (j ? j * (j + 1) / 2 + 2 : 0)) + (P[i].size() - pt) * 3; } } int ans = inf; for (int i = 0, iend = hgt; i <= iend; ++i) ans = min(ans, f[i]); printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, i, p[202020], ki[202020], ka[202020], ta, tb, taa, tbb, nx[202020]; void gab(long long aa, long long bb) { nx[ka[aa]] = ki[bb]; ka[aa] = ka[bb]; ki[bb] = ki[aa]; p[aa] = bb; } long long car(long long aa) { if (p[aa] == aa) return aa; else return p[aa] = car(p[aa]); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (i = 1; i <= n; i++) p[i] = i; for (i = 1; i <= n; i++) ki[i] = i; for (i = 1; i <= n; i++) ka[i] = i; for (i = 1; i < n; i++) { cin >> ta >> tb; taa = car(ta); tbb = car(tb); gab(taa, tbb); } long long tem = ki[car(1)]; for (i = 1; i <= n; i++) { cout << tem; tem = nx[tem]; if (i < n) cout << ; else cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long a, b; cin >> a >> b; long long sum = 0; long long notes = 0; while (sum + notes + 1 <= a + b) { ++notes; sum += notes; } set<int> possible; for (int i = 1; i <= notes; ++i) possible.insert(i); vector<int> read_a; while (a && possible.size()) { if (*possible.rbegin() < a) { int take = *possible.rbegin(); a -= take; possible.erase(take); read_a.push_back(take); } else { possible.erase(a); read_a.push_back(a); a = 0; } } cout << read_a.size() << n ; for (int x : read_a) cout << x << ; cout << n ; cout << possible.size() << n ; for (int x : possible) cout << x << ; cout << n ; }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// Filename: afi_mux.v
// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
// During calibration, mux_sel = 1, sequencer AFI signals are selected
// After calibration is succesfu, mux_sel = 0, controller AFI signals are selected
// ********************************************************************************************************************************
module altera_mem_if_ddr3_phy_0001_afi_mux(
mux_sel,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
seq_mux_address,
seq_mux_bank,
seq_mux_cs_n,
seq_mux_cke,
seq_mux_odt,
seq_mux_ras_n,
seq_mux_cas_n,
seq_mux_we_n,
seq_mux_reset_n,
seq_mux_dqs_en,
seq_mux_wdata,
seq_mux_wdata_valid,
seq_mux_dm,
seq_mux_rdata_en,
mux_seq_rdata,
mux_seq_read_fifo_q,
mux_seq_rdata_valid,
mux_phy_address,
mux_phy_bank,
mux_phy_cs_n,
mux_phy_cke,
mux_phy_odt,
mux_phy_ras_n,
mux_phy_cas_n,
mux_phy_we_n,
mux_phy_reset_n,
mux_phy_dqs_en,
mux_phy_wdata,
mux_phy_wdata_valid,
mux_phy_dm,
mux_phy_rdata_en,
mux_phy_rdata_en_full,
phy_mux_rdata,
phy_mux_read_fifo_q,
phy_mux_rdata_valid
);
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
input mux_sel;
// AFI inputs from the controller
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
input [AFI_DQS_WIDTH-1:0] afi_dqs_burst;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
input afi_rdata_en;
input afi_rdata_en_full;
output [AFI_DATA_WIDTH-1:0] afi_rdata;
output afi_rdata_valid;
// AFI inputs from the sequencer
input [AFI_ADDRESS_WIDTH-1:0] seq_mux_address;
input [AFI_BANK_WIDTH-1:0] seq_mux_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] seq_mux_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke;
input [AFI_ODT_WIDTH-1:0] seq_mux_odt;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_reset_n;
input [AFI_DQS_WIDTH-1:0] seq_mux_dqs_en;
input [AFI_DATA_WIDTH-1:0] seq_mux_wdata;
input [AFI_DQS_WIDTH-1:0] seq_mux_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] seq_mux_dm;
input seq_mux_rdata_en;
output [AFI_DATA_WIDTH-1:0] mux_seq_rdata;
output [AFI_DATA_WIDTH-1:0] mux_seq_read_fifo_q;
output mux_seq_rdata_valid;
// Mux output to the rest of the PHY logic
output [AFI_ADDRESS_WIDTH-1:0] mux_phy_address;
output [AFI_BANK_WIDTH-1:0] mux_phy_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] mux_phy_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] mux_phy_cke;
output [AFI_ODT_WIDTH-1:0] mux_phy_odt;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_ras_n;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_cas_n;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_we_n;
output [AFI_CONTROL_WIDTH-1:0] mux_phy_reset_n;
output [AFI_DQS_WIDTH-1:0] mux_phy_dqs_en;
output [AFI_DATA_WIDTH-1:0] mux_phy_wdata;
output [AFI_DQS_WIDTH-1:0] mux_phy_wdata_valid;
output [AFI_DATA_MASK_WIDTH-1:0] mux_phy_dm;
output mux_phy_rdata_en;
output mux_phy_rdata_en_full;
input [AFI_DATA_WIDTH-1:0] phy_mux_rdata;
input [AFI_DATA_WIDTH-1:0] phy_mux_read_fifo_q;
input phy_mux_rdata_valid;
assign afi_rdata = phy_mux_rdata;
assign afi_rdata_valid = mux_sel ? 1'b0 : phy_mux_rdata_valid;
assign mux_seq_rdata = phy_mux_rdata;
assign mux_seq_read_fifo_q = phy_mux_read_fifo_q;
assign mux_seq_rdata_valid = phy_mux_rdata_valid;
assign mux_phy_address = mux_sel ? seq_mux_address : afi_address;
assign mux_phy_bank = mux_sel ? seq_mux_bank : afi_bank;
assign mux_phy_cs_n = mux_sel ? seq_mux_cs_n : afi_cs_n;
assign mux_phy_cke = mux_sel ? seq_mux_cke : afi_cke;
assign mux_phy_odt = mux_sel ? seq_mux_odt : afi_odt;
assign mux_phy_ras_n = mux_sel ? seq_mux_ras_n : afi_ras_n;
assign mux_phy_cas_n = mux_sel ? seq_mux_cas_n : afi_cas_n;
assign mux_phy_we_n = mux_sel ? seq_mux_we_n : afi_we_n;
assign mux_phy_reset_n = mux_sel ? seq_mux_reset_n : afi_rst_n;
assign mux_phy_dqs_en = mux_sel ? seq_mux_dqs_en : afi_dqs_burst;
assign mux_phy_wdata = mux_sel ? seq_mux_wdata : afi_wdata;
assign mux_phy_wdata_valid = mux_sel ? seq_mux_wdata_valid : afi_wdata_valid;
assign mux_phy_dm = mux_sel ? seq_mux_dm : afi_dm;
assign mux_phy_rdata_en = mux_sel ? seq_mux_rdata_en : afi_rdata_en;
assign mux_phy_rdata_en_full = mux_sel ? seq_mux_rdata_en : afi_rdata_en_full;
endmodule
|
#include <bits/stdc++.h> using namespace std; double p[8][10020]; int main() { int n; int l[8], r[8]; scanf( %d , &n); double ex = 0; double all = 1.0; for (int i = 0; i < n; i++) { scanf( %d %d , &l[i], &r[i]); all *= (r[i] - l[i] + 1); } for (int i = 1; i <= 10000; ++i) { double cr = 0; for (int j = 0; j < n; ++j) { if (r[j] < i || l[j] > i) continue; for (int k = 0; k < n; ++k) { if (k == j) continue; double t = 1.0; if (k < j) { if (r[k] < i) continue; t *= (r[k] - max(i, l[k]) + 1); } else { if (r[k] <= i) continue; t *= (r[k] - max(i + 1, l[k]) + 1); } for (int s = 0; s < n; ++s) { if (s == j || s == k) continue; if (s < j) { if (l[s] >= i) { t = 0; break; } t *= (min(r[s], i - 1) - l[s] + 1); } else { if (l[s] > i) { t = 0; break; } t *= (min(r[s], i) - l[s] + 1); } } if (t != 0) { } cr += t; } } ex += cr / all * i; } printf( %.15lf n , ex); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; double memo[105][105][105]; double dp(int R, int S, int P) { if (R == 0) return 0; if (S + P == 0) return 1; double& ret = memo[R][S][P]; if (memo[R][S][P] >= 0) return ret; ret = 0; if (R && S) ret += dp(R, S - 1, P) * R * S; if (S && P) ret += dp(R, S, P - 1) * S * P; if (R && P) ret += dp(R - 1, S, P) * R * P; ret /= (R * S + S * P + R * P); return ret; } int main() { std::ios_base::sync_with_stdio(0); int x, y, z; for (int x = 0; x < 105; x++) for (int y = 0; y < 105; y++) for (int i = 0; i < 105; i++) memo[x][y][i] = -1; cin >> x >> y >> z; cout << fixed; cout << setprecision(10); cout << dp(x, y, z) << << dp(y, z, x) << << dp(z, x, y) << endl; ; return 0; }
|
#include <bits/stdc++.h> const int maxnm = 9 + 2; int n, m; char map[maxnm][maxnm], best[maxnm][maxnm]; bool shape[4][3][3] = {{{1, 1, 1}, {0, 1, 0}, {0, 1, 0}}, {{0, 1, 0}, {0, 1, 0}, {1, 1, 1}}, {{1, 0, 0}, {1, 1, 1}, {1, 0, 0}}, {{0, 0, 1}, {1, 1, 1}, {0, 0, 1}}}; inline bool valid(int x, int y, int k) { if (x < 1 || x + 2 > n || y < 1 || y + 2 > m) return false; for (int i = 0; i <= 2; ++i) for (int j = 0; j <= 2; ++j) { if (shape[k][i][j] && map[x + i][y + j] != . ) return false; } return true; } inline void set(int x, int y, int k, char c) { for (int i = 0; i <= 2; ++i) for (int j = 0; j <= 2; ++j) { if (shape[k][i][j]) map[x + i][y + j] = c; } } int ans; void dfs(int x, int y, int now) { if (now + ((n - x - 1) * m + m - y + 1) / 5 <= ans) return; if (y > m) return dfs(x + 1, 1, now); if (x <= n) { for (int i = x; i <= n; ++i) for (int j = (i == x ? y : 1); j <= m; ++j) { for (int k = 0; k < 4; ++k) { if (!valid(i, j, k)) continue; set(i, j, k, A + now); dfs(i, j + 1, now + 1); set(i, j, k, . ); } } } if (now > ans) { ans = now; memcpy(best, map, sizeof(map)); } } int main() { int a; a = 1; a = 0; a = (a == 1); scanf( %d%d , &n, &m); memset(map, . , sizeof(map)); memset(best, . , sizeof(best)); dfs(1, 1, 0); printf( %d n , ans); for (int i = 1; i <= n; ++i, putchar( n )) for (int j = 1; j <= m; ++j) { putchar(best[i][j]); } return 0; }
|
module data_test2 (
input rst, //reset
input clk,
output reg din_stb,
input [1:0] din_ready,
output reg [1:0] din_activate,
output reg [31:0] din,
input [23:0] din_size,
input dout_ready,
output reg dout_activate,
input [31:0] dout,
output reg dout_stb,
input [23:0] dout_size,
output reg count_error,
output reg incorrect_data,
output reg [23:0] count_detected,
output reg [31:0] detected_value
);
//Parameters
//Registers/Wires
reg [31:0] write_count;
reg [31:0] read_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
din_stb <= 0;
din_activate <= 0;
din <= 0;
write_count <= 0;
dout_activate <= 0;
dout_stb <= 0;
read_count <= 0;
count_error <= 0;
incorrect_data <= 0;
detected_value <= 0;
count_detected <= 0;
end
else begin
din_stb <= 0;
dout_stb <= 0;
count_error <= 0;
incorrect_data <= 0;
if ((din_ready > 0) && (din_activate == 0)) begin
write_count <= 0;
din <= 0;
if (din_ready[0]) begin
din_activate[0] <= 1;
end
else begin
din_activate[1] <= 1;
end
end
else if (din_activate != 0) begin
if (write_count < din_size) begin
din_stb <= 1;
din <= write_count;
write_count <= write_count + 1;
end
else begin
din_activate <= 0;
end
end
if (dout_ready && !dout_activate) begin
read_count <= 0;
dout_activate <= 1;
if (dout_size != 24'h0800) begin
count_error <= 1;
count_detected <= dout_size;
end
end
else if (dout_activate) begin
if (read_count < dout_size) begin
dout_stb <= 1;
read_count <= read_count + 1;
end
else begin
dout_activate <= 0;
end
//Error Detection
if (read_count > 0) begin
if (dout != read_count - 1) begin
incorrect_data <= 1;
count_detected <= read_count[23:0];
detected_value <= dout;
end
end
else begin
if (dout != 0) begin
incorrect_data <= 1;
count_detected <= read_count[23:0];
detected_value <= dout;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 0x3f3f3f3f; const int N = 3e5 + 10; const long long mod = 1e9 + 7; const double PI = acos(-1); inline long long mm(long long x, long long p) { return x >= p ? x -= p : ((x < 0) ? x += p : x); } inline long long ab(long long x) { return x < 0 ? -x : x; } char s[N]; int main() { int n, x, y; long long cnt = 0; scanf( %d%d%d , &n, &x, &y); scanf( %s , s); bool flag = true; for (int i = 0; i < n; ++i) { if (s[i] == 1 ) flag = true; else { if (flag) cnt++; flag = false; } } if (cnt) printf( %lld n , min(cnt * y, (cnt - 1) * x + y)); else puts( 0 ); return 0; }
|
//I ll always miss you like a darling. #include <bits/stdc++.h> using namespace std; #define LL long long #define LD long double #define ull unsigned long long #define x first #define y second #define pb push_back #define pf push_front #define mp make_pair #define Pair pair<int,int> #define pLL pair<LL,LL> #define pii pair<double,double> #define LOWBIT(x) x & (-x) #define rep(i,a,b) for (int i=a;i<=b;i++) #define REP(i,a,b) for (int i=a;i>=b;i--) const int INF=2e9; const LL LINF=2e16; const int magic=348; const int MOD=1e9+7; const double eps=1e-10; const double pi=acos(-1); struct fastio { static const int S=1e7; char rbuf[S+48],wbuf[S+48];int rpos,wpos,len; fastio() {rpos=len=wpos=0;} inline char Getchar() { if (rpos==len) rpos=0,len=fread(rbuf,1,S,stdin); if (!len) return EOF; return rbuf[rpos++]; } template <class T> inline void Get(T &x) { char ch;bool f;T res; while (!isdigit(ch=Getchar()) && ch!= - ) {} if (ch== - ) f=false,res=0; else f=true,res=ch- 0 ; while (isdigit(ch=Getchar())) res=res*10+ch- 0 ; x=(f?res:-res); } inline void getstring(char *s) { char ch; while ((ch=Getchar())<=32) {} for (;ch>32;ch=Getchar()) *s++=ch; *s= 0 ; } inline void flush() {fwrite(wbuf,1,wpos,stdout);fflush(stdout);wpos=0;} inline void Writechar(char ch) { if (wpos==S) flush(); wbuf[wpos++]=ch; } template <class T> inline void Print(T x,char ch) { char s[20];int pt=0; if (x==0) s[++pt]= 0 ; else { if (x<0) Writechar( - ),x=-x; while (x) s[++pt]= 0 +x%10,x/=10; } while (pt) Writechar(s[pt--]); Writechar(ch); } inline void printstring(char *s) { int pt=1; while (s[pt]!= 0 ) Writechar(s[pt++]); } }io; template<typename T> inline void check_max(T &x,T cmp) {x=max(x,cmp);} template<typename T> inline void check_min(T &x,T cmp) {x=min(x,cmp);} template<typename T> inline T myabs(T x) {return x>=0?x:-x;} template<typename T> inline T mygcd(T x,T y) {return y==0?x:mygcd(y,x%y);} inline int add(int x) {if (x>=MOD) x-=MOD;return x;} inline int add(int x,int MO) {if (x>=MO) x-=MO;return x;} inline int sub(int x) {if (x<0) x+=MOD;return x;} inline int sub(int x,int MO) {if (x<0) x+=MO;return x;} inline void Add(int &x,int y) {x=add(x+y);} inline void Add(int &x,int y,int MO) {x=add(x+y,MO);} inline void Sub(int &x,int y) {x=sub(x-y);} inline void Sub(int &x,int y,int MO) {x=sub(x-y,MO);} template<typename T> inline int quick_pow(int x,T y) {int res=1;while (y) {if (y&1) res=1ll*res*x%MOD;x=1ll*x*x%MOD;y>>=1;}return res;} template<typename T> inline int quick_pow(int x,T y,int MO) {int res=1;while (y) {if (y&1) res=1ll*res*x%MO;x=1ll*x*x%MO;y>>=1;}return res;} int print(int l,int r) { printf( ? %d %d n ,l,r); fflush(stdout); int res;scanf( %d ,&res);return res; } int main () { #ifndef ONLINE_JUDGE double TIME=clock(); cerr<< Running... <<endl; #endif int n;scanf( %d ,&n); int pos=print(1,n);int l=1,r=n; while (r-l+1>=4) { int mid=(l+r)>>1; if (l<=pos && pos<=r) { if (pos<=mid) { int res=print(l,mid); if (res==pos) r=mid; else l=mid+1; } else { int res=print(mid+1,r); if (res==pos) l=mid+1; else r=mid; } } else { if (pos<l) { int res=print(pos,mid); if (res==pos) r=mid; else l=mid+1; } else { int res=print(mid+1,pos); if (res==pos) l=mid+1; else r=mid; } } } if (l==r) printf( ! %d n ,l); else if (l+1==r) { int res=print(l,r),ans=l+r-res; printf( ! %d n ,ans); } else { int res=print(l,r); if (res==l) { int rres=print(l+1,r),ans=l+1+r-rres; printf( ! %d n ,ans); } else if (res==r) { int rres=print(l,r-1),ans=l+r-1-rres; printf( ! %d n ,ans); } else { int rres=print(l,r-1); if (rres==r-1) printf( ! %d n ,l); else printf( ! %d n ,r); } } #ifndef ONLINE_JUDGE cerr<< Exec Time: <<(clock()-TIME)/CLOCKS_PER_SEC<<endl; #endif return 0; }
|
`include "CLA.v"
module tb4CLA;
wire C_OUT;
wire [15:0] SUM;
reg C_IN;
reg [15:0] A, B;
CLA CLA00 (A, B, C_IN, SUM, C_OUT);
initial
begin
C_IN = 1'd1;
A = 16'd21;
B = 16'd56;
#5
C_IN = 1'd0;
A = 16'd23;
B = 16'd198;
#5
C_IN = 1'd1;
A = 16'd423;
B = 16'd345;
#5
C_IN = 1'd0;
A = 16'd999;
B = 16'd0;
#5
C_IN = 1'd1;
A = 16'd5435;
B = 16'd3456;
#5
C_IN = 1'd1;
A = 16'd2454;
B = 16'd9867;
#5
C_IN = 1'd1;
A = 16'd62551;
B = 16'd15456;
#5
C_IN = 1'd1;
A = 16'd2315;
B = 16'd4548;
#5
C_IN = 1'd1;
A = 16'd54544;
B = 16'd64545;
#5
C_IN = 1'd1;
A = 16'd15478;
B = 16'd63265;
#5
C_IN = 1'd1;
A = 16'd6152;
B = 16'd65210;
#5
C_IN = 1'd1;
A = 16'd1;
B = 16'd1;
#5
C_IN = 1'd1;
A = 16'd45944;
B = 16'd9545;
#5
C_IN = 1'd1;
A = 16'd1234;
B = 16'd65531;
#5
C_IN = 1'd1;
A = 16'd17832;
B = 16'd64512;
#5
C_IN = 1'd1;
A = 16'd54581;
B = 16'd64259;
#5
C_IN = 1'd1;
A = 16'd2;
B = 16'd6;
#5
C_IN = 1'd1;
A = 16'd4;
B = 16'd6;
#5
C_IN = 1'd1;
A = 16'd12345;
B = 16'd1;
#5
C_IN = 1'd1;
A = 16'd5;
B = 16'd65537;
#5
C_IN = 1'd1;
A = 16'd54;
B = 16'd45;
#5
$stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
integer status;
wire a, b, x;
A mod_a(/*AUTOINST*/
// Outputs
.x (x),
// Inputs
.clk (clk),
.a (a),
.b (b));
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
module A(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a, b
);
input clk;
input a, b;
output x;
wire y, c;
B mod_b(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.b (b),
.c (c));
C \mod_c. (/*AUTOINST*/
// Outputs
.x (x),
// Inputs
.clk (clk),
.a (a),
.y (y));
endmodule : A
module B(/*AUTOARG*/
// Outputs
y,
// Inputs
b, c
); /*verilator public_module*/
input b, c;
output reg y;
always @(*) begin : myproc
y = b ^ c;
end
endmodule
module C(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a, y
);
input clk;
input a, y;
output reg x /* verilator public_flat_rw */;
always @(posedge clk) begin
x <= a & y;
end
endmodule
|
/* wb_upsizer_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_upsizer_tb
(input wb_clk_i,
input wb_rst_i,
output done);
localparam aw = 32;
localparam MEMORY_SIZE_WORDS = 2**10;
localparam DW_IN = 32;
localparam SCALE = 2;
localparam DW_OUT = DW_IN * SCALE;
wire [aw-1:0] wbm_m2s_adr;
wire [DW_IN-1:0] wbm_m2s_dat;
wire [DW_IN/8-1:0] wbm_m2s_sel;
wire wbm_m2s_we ;
wire wbm_m2s_cyc;
wire wbm_m2s_stb;
wire [2:0] wbm_m2s_cti;
wire [1:0] wbm_m2s_bte;
wire [DW_IN-1:0] wbm_s2m_dat;
wire wbm_s2m_ack;
wire wbm_s2m_err;
wire wbm_s2m_rty;
wire [aw-1:0] wbs_m2s_adr;
wire [DW_OUT-1:0] wbs_m2s_dat;
wire [DW_OUT/8-1:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [2:0] wbs_m2s_cti;
wire [1:0] wbs_m2s_bte;
wire [DW_OUT-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire wbs_s2m_err;
wire wbs_s2m_rty;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wb_bfm_transactor
#(.MEM_HIGH(MEMORY_SIZE_WORDS-1),
.MEM_LOW (0),
.VERBOSE (0))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we ),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (wbm_m2s_cti),
.wb_bte_o (wbm_m2s_bte),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (wbm_s2m_err),
.wb_rty_i (wbm_s2m_rty),
//Test Control
.done(done));
integer idx;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
$display("Master : %f", ack_delay/num_transactions);
$display("%0d : All tests passed!", $time);
end
end
wb_upsizer
#(.DW_IN (DW_IN),
.SCALE (SCALE))
dut
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbs_adr_i (wbm_m2s_adr),
.wbs_dat_i (wbm_m2s_dat),
.wbs_sel_i (wbm_m2s_sel),
.wbs_we_i (wbm_m2s_we ),
.wbs_cyc_i (wbm_m2s_cyc),
.wbs_stb_i (wbm_m2s_stb),
.wbs_cti_i (wbm_m2s_cti),
.wbs_bte_i (wbm_m2s_bte),
.wbs_dat_o (wbm_s2m_dat),
.wbs_ack_o (wbm_s2m_ack),
.wbs_err_o (wbm_s2m_err),
.wbs_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbm_adr_o (wbs_m2s_adr),
.wbm_dat_o (wbs_m2s_dat),
.wbm_sel_o (wbs_m2s_sel),
.wbm_we_o (wbs_m2s_we),
.wbm_cyc_o (wbs_m2s_cyc),
.wbm_stb_o (wbs_m2s_stb),
.wbm_cti_o (wbs_m2s_cti),
.wbm_bte_o (wbs_m2s_bte),
.wbm_dat_i (wbs_s2m_dat),
.wbm_ack_i (wbs_s2m_ack),
.wbm_err_i (wbs_s2m_err),
.wbm_rty_i (wbs_s2m_rty));
assign slave_writes = mem.writes;
assign slave_reads = mem.reads;
time start_time;
time ack_delay;
integer num_transactions;
initial begin
ack_delay = 0;
num_transactions = 0;
while(1) begin
@(posedge wbm_m2s_cyc);
start_time = $time;
@(posedge wbm_s2m_ack);
ack_delay = ack_delay + $time-start_time;
num_transactions = num_transactions+1;
end
end
wb_bfm_memory #(.DEBUG (0),
.dw (DW_OUT),
.mem_size_bytes(MEMORY_SIZE_WORDS*(DW_IN/8)))
mem
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 11:45:21 03/21/2016
// Design Name:
// Module Name: timing_generator_VGA
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timing_generator_VGA
(
input wire clk,reset,
output wire hsync,vsync,video_on,p_tick,
output wire [9:0] pixel_x, pixel_y
);
//Declaración de constantes
//Parámetros para VGA 640x480
localparam HD = 640;//área de despliegue horizontal
localparam HF = 48;// borde izquierdo horizontal
localparam HB = 16;//borde derecho horizontal(16)
localparam HR = 96;//retraso horizontal
localparam VD = 480;//área de despliegue vertical
localparam VF = 10;//borde superior vertical
localparam VB = 33;//borde inferior vertical
localparam VR = 2;//retraso vertical
//Contadores
//Contador para la división de frecuencia (100 MHz a 25 MHz)
//reg mod2_reg;
//wire mod2_next;
reg cuenta, CV;
//Contadores de "timing" vertical y horizontal
reg[9:0] h_count_reg, h_count_next;
reg[9:0] v_count_reg, v_count_next;
reg h_sync_reg, v_sync_reg;
wire h_sync_next, v_sync_next;
//Señales de status
wire h_end, v_end;
wire pixel_tick;
//Definición de comportamiento
//Registros
always @(posedge clk, posedge reset)
begin
if(reset)
begin
//mod2_reg <= 1'b0;
h_count_reg <= 0;
v_count_reg <= 0;
h_sync_reg <= 1'b0;
v_sync_reg <= 1'b0;
end
else
begin
//mod2_reg <= mod2_next;
h_count_reg <= h_count_next;
v_count_reg <= v_count_next;
h_sync_reg <= h_sync_next;
v_sync_reg <= v_sync_next;
end
end
//Para generar 25 MHz
always@(posedge clk, posedge reset)
begin
if(reset)
begin
cuenta <= 0;
CV <= 0;
end
else
begin
if (cuenta == 1'b1)
begin
cuenta <= 0;
CV <= ~CV;
end
else
cuenta <= cuenta + 1'b1;
end
end
//assign mod2_next = ~mod2_reg;
assign pixel_tick = CV;
//Definición señales de status
//Final del contador horizontal (799)
assign h_end = (h_count_reg == (HD+HF+HB+HR-1));
//Final contador vertical (524)
assign v_end = (v_count_reg == (VD+VF+VB+VR-1));
//Lógicas de estado siguiente de los contadores
//Contador horizontal
always@(negedge pixel_tick)
begin
//if(pixel_tick) //pulso de 25 MHz
if(h_end)
h_count_next = 0;
else
h_count_next = h_count_reg + 1'b1;
/* else
h_count_next = h_count_reg; //Mantiene la cuenta*/
end
//Contador vertical
always@(negedge pixel_tick)
begin
//if(pixel_tick & h_end) //pulso de 25 MHz y final de fila
if(h_end) //pulso de 25 MHz y final de fila
if(v_end)
v_count_next = 0;
else
v_count_next = v_count_reg + 1'b1;
else
v_count_next = v_count_reg; //Mantiene la cuenta
end
/*h_sync_next puesto en bajo para generar retraso
entre la cuentas 656 y 751*/
assign h_sync_next = (h_count_reg >= (HD+HB)&&
h_count_reg <=(HD+HB+HR-1));
/*v_sync_next puesto en bajo para generar retraso
entre la cuentas 490 y 491*/
assign v_sync_next = (v_count_reg >= (VD+VB)&&
v_count_reg <=(VD+VB+VR-1));
//Asignación de salidas
//Para generar señal video on/off
assign video_on = (h_count_reg < HD) && (v_count_reg < VD); //Para mantener una forma de saber si el pixel está en la región visible
assign hsync = ~h_sync_reg;
assign vsync = ~v_sync_reg;
assign pixel_x = h_count_reg; //Coordenada x
assign pixel_y = v_count_reg; //Coordenada y
assign p_tick = pixel_tick; //Ayuda a coordinar la creación de imágenes (módulo de generación de píxeles)
endmodule
/*Notas:
1. La frecuencia del "timing" vertical
define el tiempo de refresco de la pantalla
(30 fps, 60 fps,etc)
2. 25 MHz es la frecuencia de escritura de cada
píxel (pixel_clk)
3.video_on debe tener un período igual al que corresponde escribir sobre la región visible*/
|
#include <bits/stdc++.h> using namespace std; int a[100010]; int b[100010]; int ans[100010]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; b[a[i]] = i; } ans[b[n]] = 0; for (int i = n - 1; i >= 1; i--) { int idx = b[i]; int flag = 0; for (int j = idx + i; j <= n; j += i) { if (a[j] > i && ans[j] == 0) { flag = 1; break; } } for (int j = idx - i; j >= 1; j -= i) { if (a[j] > i && ans[j] == 0) { flag = 1; break; } } if (flag == 1) { ans[idx] = 1; } else { ans[idx] = 0; } } for (int i = 1; i <= n; i++) { if (ans[i]) { cout << A ; } else { cout << B ; } } }
|
/*
* Copyright (c) 2013, Stefan Kristiansson <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module wb_to_avalon_bridge #(
parameter DW = 32, // Data width
parameter AW = 32, // Address width
parameter BURST_SUPPORT = 0
)(
input clk,
input rst,
// Wishbone Master Input
input [AW-1:0] wbm_adr_i,
input [DW-1:0] wbm_dat_i,
input [DW/8-1:0] wbm_sel_i,
input wbm_we_i,
input wbm_cyc_i,
input wbm_stb_i,
input [2:0] wbm_cti_i,
input [1:0] wbm_bte_i,
output [DW-1:0] wbm_dat_o,
output wbm_ack_o,
output wbm_err_o,
output wbm_rty_o,
// Avalon Master Output
output [AW-1:0] avm_address_o,
output [DW/8-1:0] avm_byteenable_o,
output avm_read_o,
input [DW-1:0] avm_readdata_i,
output [7:0] avm_burstcount_o,
output avm_write_o,
output [DW-1:0] avm_writedata_o,
input avm_waitrequest_i,
input avm_readdatavalid_i
);
wire cycstb = wbm_cyc_i & wbm_stb_i;
generate if (BURST_SUPPORT == 1) begin : burst_enable
localparam IDLE = 3'd0;
localparam READ = 3'd1;
localparam WRITE = 3'd2;
localparam BURST = 3'd3;
localparam FLUSH_PIPE = 3'd4;
localparam CLASSIC = 3'b000;
localparam CONST_BURST = 3'b001;
localparam INC_BURST = 3'b010;
localparam END_BURST = 3'b111;
localparam LINEAR_BURST = 2'b00;
localparam WRAP4_BURST = 2'b01;
localparam WRAP8_BURST = 2'b10;
localparam WRAP16_BURST = 2'b11;
reg [2:0] state;
reg [3:0] pending_reads;
reg [3:0] reads_left;
reg [AW-1:0] adr;
wire [AW-1:0] curr_adr;
wire [AW-1:0] next_adr;
reg read_req;
wire [AW-1:0] wb_burst_req;
//
// Avalon bursts can be either linear or wrapped, but that is a synthesis,
// not a runtime option.
// We have no way to know what kind of bursts are supported by the slaves we
// connect to, so instead of doing real bursts, we pipeline (up to) the number
// of reads that the wishbone side have requested in the burst.
// For linear bursts, 8 accesses are pipelined.
// This implies that only bursted reads are curently supported,
// A future improvement would be to let the user choose one of the burst
// modes by parameters and handle those as proper bursts.
//
assign curr_adr = (state == IDLE) ? wbm_adr_i : adr;
assign next_adr = (wbm_bte_i == LINEAR_BURST) ?
(curr_adr[AW-1:0] + 32'd4) :
(wbm_bte_i == WRAP4_BURST ) ?
{curr_adr[AW-1:4], curr_adr[3:0] + 4'd4} :
(wbm_bte_i == WRAP8_BURST ) ?
{curr_adr[AW-1:5], curr_adr[4:0] + 5'd4} :
/*(wbm_bte_i == WRAP16_BURST) ?*/
{curr_adr[AW-1:6], curr_adr[5:0] + 6'd4};
assign wb_burst_req = cycstb & (wbm_cti_i == INC_BURST);
always @(posedge clk) begin
read_req <= 0;
case (state)
IDLE: begin
pending_reads <= 0;
adr <= wbm_adr_i;
if (cycstb & !avm_waitrequest_i) begin
if (wbm_we_i)
state <= WRITE;
else if (wb_burst_req) begin
// Set counter for number of reads left,
// calculated by the burst count minus one
// for the current read (performed by the
// bypass) and one for the read initiated
// here.
case (wbm_bte_i)
WRAP4_BURST:
reads_left <= 4 - 2;
LINEAR_BURST,
WRAP8_BURST:
reads_left <= 8 - 2;
WRAP16_BURST:
reads_left <= 16 - 2;
endcase
pending_reads <= 1;
read_req <= 1;
adr <= next_adr;
state <= BURST;
end else
state <= READ;
end
end
READ: begin
if (avm_readdatavalid_i)
state <= IDLE;
end
BURST: begin
// Pipeline remaining reads.
// pending_reads increase when a new read is pipelined and
// decrease when a pending read is acknowledged.
// On cycles where both a read is pipelined and a pending read
// is acked, pending_reads do not change.
read_req <= 1;
if (avm_readdatavalid_i)
pending_reads <= pending_reads - 1;
if (!avm_waitrequest_i && reads_left != 0) begin
pending_reads <= pending_reads + 1;
if (avm_readdatavalid_i)
pending_reads <= pending_reads;
reads_left <= reads_left - 1;
adr <= next_adr;
end
// All reads pipelined?
if (reads_left == 0 && !(avm_waitrequest_i & read_req)) begin
read_req <= 0;
// Last transaction done, go back to IDLE
if (avm_readdatavalid_i && pending_reads == 0)
state <= IDLE;
end
// If the burst ends prematurely, we have to wait out the
// already pipelined reads before we can accept new requests.
if (avm_readdatavalid_i & !wb_burst_req & pending_reads != 0)
state <= FLUSH_PIPE;
end
FLUSH_PIPE: begin
if (avm_readdatavalid_i) begin
if (pending_reads == 0)
state <= IDLE;
pending_reads <= pending_reads - 1;
end
end
WRITE: begin
state <= IDLE;
end
default:
state <= IDLE;
endcase
if (rst) begin
read_req <= 0;
state <= IDLE;
end
end
assign avm_address_o = curr_adr;
assign avm_read_o = cycstb & !wbm_we_i & (state == IDLE) | read_req;
assign avm_write_o = cycstb & wbm_we_i & (state == IDLE);
assign wbm_ack_o = avm_readdatavalid_i & (state != FLUSH_PIPE) |
(state == WRITE);
end else begin : burst_disable
reg cycstb_r;
wire req;
reg write_ack;
always @(posedge clk)
cycstb_r <= cycstb & !wbm_ack_o;
assign req = cycstb & (!cycstb_r | avm_waitrequest_i);
always @(posedge clk)
write_ack <= cycstb & wbm_we_i & !avm_waitrequest_i & !wbm_ack_o;
assign avm_address_o = wbm_adr_i;
assign avm_write_o = req & wbm_we_i;
assign avm_read_o = req & !wbm_we_i;
assign wbm_ack_o = write_ack | avm_readdatavalid_i;
end
endgenerate
assign avm_burstcount_o = 8'h1;
assign avm_writedata_o = wbm_dat_i;
assign avm_byteenable_o = wbm_sel_i;
assign wbm_dat_o = avm_readdata_i;
assign wbm_err_o = 0;
assign wbm_rty_o = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; long long n_r, n_g, n_b, r[maxn], g[maxn], b[maxn], ans; void cal(long long n_r, long long n_g, long long n_b, long long r[], long long g[], long long b[]) { long long x, y, z, i, j = 1, k = 1; for (i = 1; i <= n_g; ++i) { y = g[i]; while (r[j] <= y && j <= n_r) ++j; if (j == 1) continue; --j; x = r[j]; while (b[k] < y) ++k; if (k > n_b) break; z = b[k]; ans = min(ans, (x - y) * (x - y) + (y - z) * (y - z) + (z - x) * (z - x)); } } void solve() { ans = 0x7fffffffffffffff; cal(n_r, n_g, n_b, r, g, b); cal(n_r, n_b, n_g, r, b, g); cal(n_g, n_r, n_b, g, r, b); cal(n_g, n_b, n_r, g, b, r); cal(n_b, n_g, n_r, b, g, r); cal(n_b, n_r, n_g, b, r, g); cout << ans << n ; } int main() { int t, i, j; ios::sync_with_stdio(false); cin >> t; while (t--) { cin >> n_r >> n_g >> n_b; for (i = 1; i <= n_r; ++i) cin >> r[i]; for (i = 1; i <= n_g; ++i) cin >> g[i]; for (i = 1; i <= n_b; ++i) cin >> b[i]; sort(r + 1, r + 1 + n_r); sort(g + 1, g + 1 + n_g); sort(b + 1, b + 1 + n_b); solve(); } return 0; }
|
module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED);
input clk_i;
input nrst_i;
input [24:1] wb_adr_i;
output [15:0] wb_dat_o;
input [15:0] wb_dat_i;
input [1:0] wb_sel_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output wb_ack_o;
output wb_err_o;
output wb_int_o;
output reg [3:0] DISP_SEL;
output reg [6:0] DISP_LED;
reg [15:0] data_reg;
reg [6:0] disp_cnt;
reg [3:0] disp_data;
wire [6:0] disp_data_led;
reg [3:0] disp_pos;
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
data_reg <= 16'hABCD;
else
if (wb_stb_i && wb_we_i)
data_reg <= wb_dat_i;
end
assign wb_ack_o = wb_stb_i;
assign wb_err_o = 1'b0;
assign wb_int_o = 1'b0;
assign wb_dat_o = data_reg;
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
disp_cnt <= 7'b0000000;
else
disp_cnt <= disp_cnt + 1;
end
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
disp_pos <= 4'b0010;
else
if (disp_cnt == 7'b1111111)
disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]};
end
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
disp_data <= 4'b0000;
else
case (DISP_SEL)
4'b1000: disp_data <= data_reg[3:0];
4'b0100: disp_data <= data_reg[7:4];
4'b0010: disp_data <= data_reg[11:8];
4'b0001: disp_data <= data_reg[15:12];
endcase
end
disp_dec u0 (disp_data, disp_data_led);
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
DISP_LED <= 7'b0000000;
else
DISP_LED <= disp_data_led;
end
always @(posedge clk_i or negedge nrst_i)
begin
if (nrst_i == 0)
DISP_SEL <= 0;
else
DISP_SEL <= disp_pos;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf(101010101010101010LL); int n; struct uf { int par[1005]; uf() { for (int i(0); i < (n); i++) par[i] = i; } int ff(int x) { return par[x] == x ? x : par[x] = ff(par[x]); } void uu(int x, int y) { x = ff(x), y = ff(y); if (x - y) par[x] = y; } }; vector<pair<int, int> > edges; vector<int> eA, eB; char col[20]; int main() { cin >> n; int m; cin >> m; edges.resize(m); uf fA, fB; for (int id(0); id < (m); id++) { int x, y; scanf( %d%d%s , &x, &y, col); x--, y--; edges[id] = make_pair(x, y); if (col[0] == S ) { if (fA.ff(x) == fA.ff(y)) continue; eA.push_back(id), fA.uu(x, y); } else { if (fB.ff(x) == fB.ff(y)) continue; eB.push_back(id), fB.uu(x, y); } } uf fAB_1; for (__typeof((eA).end()) it((eA).begin()); it != (eA).end(); ++it) { int id(*it), x(edges[id].first), y(edges[id].second); fAB_1.uu(x, y); } vector<int> eB_selected; for (__typeof((eB).end()) it((eB).begin()); it != (eB).end(); ++it) { int id(*it), x(edges[id].first), y(edges[id].second); if (fAB_1.ff(x) != fAB_1.ff(y)) { eB_selected.push_back(id); fAB_1.uu(x, y); } } uf fAB_2; int nA(0), nB(((int)(eB_selected).size())); for (__typeof((eB_selected).end()) it((eB_selected).begin()); it != (eB_selected).end(); ++it) { int id(*it), x(edges[id].first), y(edges[id].second); fAB_2.uu(x, y); } for (__typeof((eB).end()) it((eB).begin()); it != (eB).end(); ++it) if (nB < (n - 1) / 2) { int id(*it), x(edges[id].first), y(edges[id].second); if (fAB_2.ff(x) != fAB_2.ff(y)) { eB_selected.push_back(id); fAB_2.uu(x, y); nB++; } } vector<int> eA_selected; for (__typeof((eA).end()) it((eA).begin()); it != (eA).end(); ++it) { int id(*it), x(edges[id].first), y(edges[id].second); if (fAB_2.ff(x) != fAB_2.ff(y)) { eA_selected.push_back(id); fAB_2.uu(x, y); nA++; } } if (nA != (n - 1) / 2 || nB != (n - 1) / 2) { puts( -1 ); return 0; } cout << (n - 1) << endl; vector<int> selected; for (__typeof((eA_selected).end()) it((eA_selected).begin()); it != (eA_selected).end(); ++it) selected.push_back(*it); for (__typeof((eB_selected).end()) it((eB_selected).begin()); it != (eB_selected).end(); ++it) selected.push_back(*it); for (__typeof((selected).end()) it((selected).begin()); it != (selected).end(); ++it) { if (it != (selected).begin()) cout << ; cout << (*it) + 1; } cout << endl; }
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module testbench;
reg clk, reset;
always
#100 clk =~clk;
initial begin
clk = 1'b0;
reset = 1'b1;
end
mips_single A1(clk, reset);
//always @(negedge clk)
// reset = 1'b0;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 18:24:55 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_stub.v
// Design : mig_wrap_proc_sys_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module mig_wrap_proc_sys_reset_0_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
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