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#include <bits/stdc++.h> using namespace std; #define int long long #define double long double #define FOR(i, n) for (signed i = 0; i < n; ++i) #define ALL(x) x.begin(), x.end() #define RALL(x) x.rbegin(), x.rend() #define VI vector<int> #define VII vector<VI> #define PII pair<int, int> #define PPII pair<int, PII> #define make(type, x) type x; cin >> x #define makev(x, n) VI x(n); FOR(I, n) cin >> x[I] #define repeat(n) for(int J = n; J; --J) #define M7 1000000007LL #define M9 1000000009LL #define MFFT 998244353LL #define INF 2000000000000000000LL void solveForSet() { make(int, n); map<int, VI> indices; VI a; for (int i = 0; i < n; ++i) { make(int, t); indices[t].push_back(i + 1); a.push_back(t); } VI answers; for (const auto &x: indices.rbegin()->second) { answers.push_back(x); } sort(ALL(a)); VI pref(n + 1); for (int i = 0; i < n; ++i) { pref[i + 1] = pref[i] + a[i]; } for (int i = n - 1; i > 0; --i) { while (a[i - 1] == a[i]) --i; if (i > 0 && pref[i] < a[i]) { break; } for (const auto &x: indices[a[i - 1]]) { answers.push_back(x); } } sort(ALL(answers)); cout << answers.size() << n ; for (const auto &x: answers) { cout << x << ; } cout << n ; } void solve() { make(int, t); while (t--) { solveForSet(); } } signed main(signed argc, char **argv) { ios_base::sync_with_stdio(false); cin.tie(nullptr); if (argc > 1 && (string) argv[1] == local ) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); solve(); while (cin.peek() != EOF) { if (isspace(cin.peek())) cin.get(); else { cout << n ; solve(); } } } else { solve(); } }
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 // IP Revision: 5 `timescale 1ns/1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module ball_small ( clka, wea, addra, dina, douta ); (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input wire clka; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input wire [0 : 0] wea; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input wire [9 : 0] addra; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input wire [11 : 0] dina; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output wire [11 : 0] douta; blk_mem_gen_v8_3_5 #( .C_FAMILY("artix7"), .C_XDEVICEFAMILY("artix7"), .C_ELABORATION_DIR("./"), .C_INTERFACE_TYPE(0), .C_AXI_TYPE(1), .C_AXI_SLAVE_TYPE(0), .C_USE_BRAM_BLOCK(0), .C_ENABLE_32BIT_ADDRESS(0), .C_CTRL_ECC_ALGO("NONE"), .C_HAS_AXI_ID(0), .C_AXI_ID_WIDTH(4), .C_MEM_TYPE(0), .C_BYTE_SIZE(9), .C_ALGORITHM(1), .C_PRIM_TYPE(1), .C_LOAD_INIT_FILE(1), .C_INIT_FILE_NAME("ball_small.mif"), .C_INIT_FILE("ball_small.mem"), .C_USE_DEFAULT_DATA(0), .C_DEFAULT_DATA("0"), .C_HAS_RSTA(0), .C_RST_PRIORITY_A("CE"), .C_RSTRAM_A(0), .C_INITA_VAL("0"), .C_HAS_ENA(0), .C_HAS_REGCEA(0), .C_USE_BYTE_WEA(0), .C_WEA_WIDTH(1), .C_WRITE_MODE_A("WRITE_FIRST"), .C_WRITE_WIDTH_A(12), .C_READ_WIDTH_A(12), .C_WRITE_DEPTH_A(900), .C_READ_DEPTH_A(900), .C_ADDRA_WIDTH(10), .C_HAS_RSTB(0), .C_RST_PRIORITY_B("CE"), .C_RSTRAM_B(0), .C_INITB_VAL("0"), .C_HAS_ENB(0), .C_HAS_REGCEB(0), .C_USE_BYTE_WEB(0), .C_WEB_WIDTH(1), .C_WRITE_MODE_B("WRITE_FIRST"), .C_WRITE_WIDTH_B(12), .C_READ_WIDTH_B(12), .C_WRITE_DEPTH_B(900), .C_READ_DEPTH_B(900), .C_ADDRB_WIDTH(10), .C_HAS_MEM_OUTPUT_REGS_A(1), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_MUX_PIPELINE_STAGES(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_USE_SOFTECC(0), .C_USE_ECC(0), .C_EN_ECC_PIPE(0), .C_HAS_INJECTERR(0), .C_SIM_COLLISION_CHECK("ALL"), .C_COMMON_CLK(0), .C_DISABLE_WARN_BHV_COLL(0), .C_EN_SLEEP_PIN(0), .C_USE_URAM(0), .C_EN_RDADDRA_CHG(0), .C_EN_RDADDRB_CHG(0), .C_EN_DEEPSLEEP_PIN(0), .C_EN_SHUTDOWN_PIN(0), .C_EN_SAFETY_CKT(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_COUNT_36K_BRAM("0"), .C_COUNT_18K_BRAM("1"), .C_EST_POWER_SUMMARY("Estimated Power for IP : 1.43485 mW") ) inst ( .clka(clka), .rsta(1'D0), .ena(1'D0), .regcea(1'D0), .wea(wea), .addra(addra), .dina(dina), .douta(douta), .clkb(1'D0), .rstb(1'D0), .enb(1'D0), .regceb(1'D0), .web(1'B0), .addrb(10'B0), .dinb(12'B0), .doutb(), .injectsbiterr(1'D0), .injectdbiterr(1'D0), .eccpipece(1'D0), .sbiterr(), .dbiterr(), .rdaddrecc(), .sleep(1'D0), .deepsleep(1'D0), .shutdown(1'D0), .rsta_busy(), .rstb_busy(), .s_aclk(1'H0), .s_aresetn(1'D0), .s_axi_awid(4'B0), .s_axi_awaddr(32'B0), .s_axi_awlen(8'B0), .s_axi_awsize(3'B0), .s_axi_awburst(2'B0), .s_axi_awvalid(1'D0), .s_axi_awready(), .s_axi_wdata(12'B0), .s_axi_wstrb(1'B0), .s_axi_wlast(1'D0), .s_axi_wvalid(1'D0), .s_axi_wready(), .s_axi_bid(), .s_axi_bresp(), .s_axi_bvalid(), .s_axi_bready(1'D0), .s_axi_arid(4'B0), .s_axi_araddr(32'B0), .s_axi_arlen(8'B0), .s_axi_arsize(3'B0), .s_axi_arburst(2'B0), .s_axi_arvalid(1'D0), .s_axi_arready(), .s_axi_rid(), .s_axi_rdata(), .s_axi_rresp(), .s_axi_rlast(), .s_axi_rvalid(), .s_axi_rready(1'D0), .s_axi_injectsbiterr(1'D0), .s_axi_injectdbiterr(1'D0), .s_axi_sbiterr(), .s_axi_dbiterr(), .s_axi_rdaddrecc() ); endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__A21OI_PP_BLACKBOX_V `define SKY130_FD_SC_HD__A21OI_PP_BLACKBOX_V /** * a21oi: 2-input AND into first input of 2-input NOR. * * Y = !((A1 & A2) | B1) * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hd__a21oi ( Y , A1 , A2 , B1 , VPWR, VGND, VPB , VNB ); output Y ; input A1 ; input A2 ; input B1 ; input VPWR; input VGND; input VPB ; input VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__A21OI_PP_BLACKBOX_V
#include <bits/stdc++.h> template <class T> std::vector<T> ReadVector(size_t size) { std::vector<T> vector(size); for (auto& element : vector) { std::cin >> element; } return vector; } int64_t divisor(int64_t x) { for (int64_t d = 2; d * d <= x; ++d) { while (x % d == 0) { x /= d; return d; } } return x; } void YES(bool yes) { if (yes) { std::cout << YES n ; } else { std::cout << NO n ; } } class Solver { public: Solver() {} void solve() { int t; std::cin >> t; while (t--) { one(); } } int lo(int& a, int& d) { if (a + d == 0) return 0; int losers = 0; if (d > a) { int m = std::max(0, a); losers += m; d -= m; a -= m; } else if (d < a) { int m = std::max(0, d - 1); losers += m; a -= m; d -= m; } else { losers += d - 1; d = 1; a = 1; } return losers; } int wi(int& a, int& d) { int winners = 0; if (d > a) { int m = a; winners += m; d -= m; a = 0; } else if (d < a) { int m = d; winners += m; a -= m; d = 0; } else { winners += d; d = 0; a = 0; } return winners; } void one() { int n, x, y; std::cin >> n >> x >> y; if (x > y) std::swap(x, y); int a = x - 1; int b = n - x; int c = y - 1; int d = n - y; int losers = 0; losers += lo(a, d); losers += lo(c, b); losers += std::min(b, d); a = x - 1; b = n - x; c = y - 1; d = n - y; int winners = 1; winners += wi(a, d); winners += wi(c, b); winners += std::min(a, c); std::cout << n - losers << << winners << std::endl; } }; int main() { Solver solver; solver.solve(); return 0; }
#include <bits/stdc++.h> using namespace std; template <class T> void chmin(T& a, const T& b) { if (a > b) a = b; } template <class T> void chmax(T& a, const T& b) { if (a < b) a = b; } tuple<long long, long long, long long> adj[400001]; long long cnt; long long nm; int main() { long long k, a, x, y, m, n; cin >> n; for (long long i = 1; i <= n; i++) { cin >> k >> a >> x >> y >> m; long long t = 0; for (long long j = 1; j <= k; j++, adj[nm++] = make_tuple(t, a, i), (a > ((a * x + y) % m) && j != k + 1) ? t++ : t, a = (a * x + y) % m) ; cnt = max(cnt, t); } cout << cnt << n ; sort(adj, adj + nm); for (long long i = 0; i < nm; i++) cout << get<1>(adj[i]) << << get<2>(adj[i]) << n ; }
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,tune=native ) #pragma GCC optimize( unroll-loops ) using namespace std; template <typename T, typename U> inline ostream &operator<<(ostream &_out, const pair<T, U> &_p) { _out << _p.first << << _p.second; return _out; } template <typename T, typename U> inline istream &operator>>(istream &_in, pair<T, U> &_p) { _in >> _p.first >> _p.second; return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const vector<T> &_v) { if (_v.empty()) { return _out; } _out << _v.front(); for (auto _it = ++_v.begin(); _it != _v.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline istream &operator>>(istream &_in, vector<T> &_v) { for (auto &_i : _v) { _in >> _i; } return _in; } const long long MAXN = 3604; const long long MAXM = MAXN / 2; const long long INF = 1e9; const long long MOD = 998244353; long long sum(long long a, long long b) { if (a + b >= MOD) { return a + b - MOD; } return a + b; } long long mul(long long a, long long b) { if (a * b >= MOD) { return (a * b) % MOD; } return a * b; } long long sqr(long long a) { return (a * a) % MOD; } long long bin_pow(long long a, long long b) { if (b == 0) { return 1; } if (b % 2) { return mul(a, bin_pow(a, b - 1)); } return sqr(bin_pow(a, b / 2)); } long long fact[MAXN]; long long rfact[MAXN]; long long dp[2][MAXM][MAXN]; bool connected[MAXN]; long long dp1[MAXM]; long long dp2[MAXN][MAXM]; inline long long c(long long n, long long k) { return mul(fact[n], mul(rfact[k], rfact[n - k])); } class FSbalansirovannieRaspolozheniyaDomino { public: void solve(std::istream &in, std::ostream &out) { fact[0] = 1; for (long long i = 1; i < MAXN; i++) { fact[i] = mul(i, fact[i - 1]); } rfact[MAXN - 1] = bin_pow(fact[MAXN - 1], MOD - 2); for (long long j = MAXN - 1; j >= 1; j--) { rfact[j - 1] = mul(rfact[j], j); } long long h, w; in >> h >> w; long long n; in >> n; vector<pair<pair<long long, long long>, pair<long long, long long>>> a(n); in >> a; { for (long long i = 0; i <= h; i++) { for (long long j = 0; j < MAXM; j++) { dp2[i][j] = 0; dp[0][j][i] = 0; } connected[i] = 0; } for (long long j = 0; j < MAXM; j++) { dp1[j] = 0; } for (auto v : a) { connected[v.first.first - 1] = 1; connected[v.second.first - 1] = 1; } long long counts = 0; for (long long j = 0; j < h; j++) { counts += !connected[j]; } dp1[0] = 1; for (long long i = 0; i <= h; i++) { for (long long j = 0; j < MAXM; j++) { dp1[j] = sum(dp1[j], dp2[i][j]); } if (i + 1 < h && connected[i] == 0 && connected[i + 1] == 0) { for (long long j = 0; j + 1 < MAXM; j++) { dp2[i + 2][j + 1] = dp1[j]; } } } for (long long i = 0; i < MAXM; i++) { for (long long j = 0; j <= counts - 2 * i; j++) { dp[0][i][j] = mul(dp1[i], mul(fact[counts - 2 * i], mul(fact[i], rfact[counts - 2 * i - j]))); } } } { for (long long i = 0; i <= w; i++) { for (long long j = 0; j < MAXM; j++) { dp2[i][j] = 0; dp[1][j][i] = 0; } connected[i] = 0; } for (long long j = 0; j < MAXM; j++) { dp1[j] = 0; } for (auto v : a) { connected[v.first.second - 1] = 1; connected[v.second.second - 1] = 1; } long long counts = 0; for (long long j = 0; j < w; j++) { counts += !connected[j]; } dp1[0] = 1; for (long long i = 0; i <= w; i++) { for (long long j = 0; j < MAXM; j++) { dp1[j] = sum(dp1[j], dp2[i][j]); } if (i + 1 < w && connected[i] == 0 && connected[i + 1] == 0) { for (long long j = 0; j + 1 < MAXM; j++) { dp2[i + 2][j + 1] = dp1[j]; } } } for (long long i = 0; i < MAXM; i++) { for (long long j = 0; j <= counts - 2 * i; j++) { dp[1][i][j] = mul(dp1[i], c(counts - 2 * i, j)); } } } long long ans = 0; for (long long i = 0; 2 * i <= h; i++) { for (long long j = 0; 2 * j <= w; j++) { ans += dp[0][i][j] * dp[1][j][i]; if (ans >= MOD * MOD) { ans -= MOD * MOD; } } } ans %= MOD; out << ans; } }; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); FSbalansirovannieRaspolozheniyaDomino solver; std::istream &in(std::cin); std::ostream &out(std::cout); solver.solve(in, out); return 0; }
#include <bits/stdc++.h> using namespace std; bool f[110][110][2][60]; int main() { string str; cin >> str; int n = str.size(); int m; cin >> m; memset(f, 0, sizeof(f)); f[0][0][1][0] = 1; for (int i = 0; i < n; i++) { char ch = str[i]; for (int dist = 0; dist <= n; dist++) for (int dir = 0; dir <= 1; dir++) for (int opr = 0; opr <= m; opr++) if (f[i][dist][dir][opr]) if (ch == F ) { int delta = dir ? 1 : -1; if (dist == 0) f[i + 1][1][1][opr] = 1; else f[i + 1][dist + delta][dir][opr] = 1; f[i + 1][dist][1 - dir][opr + 1] = 1; } else { f[i + 1][dist][1 - dir][opr] = 1; int delta = dir ? 1 : -1; if (dist == 0) f[i + 1][1][1][opr + 1] = 1; else f[i + 1][dist + delta][dir][opr + 1] = 1; } } int ans = 0; for (int dist = 0; dist <= n; dist++) for (int dir = 0; dir <= 1; dir++) for (int opr = m; opr >= 0; opr -= 2) if (f[n][dist][dir][opr]) ans = ((ans) > (dist) ? (ans) : (dist)); cout << ans << endl; }
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; int n, q, k; vector<pair<int, int> > tree[N << 2]; int ask[N], ans[N]; struct que { int x, y, times, l; }; queue<que> Q; int fa[N], h[N], siz[N]; int find(int o) { if (o != fa[o]) { return find(fa[o]); } return o; } struct gu { int first, second, val; }; gu merge(int x, int y) { x = find(x); y = find(y); gu re; re.val = -1; if (x == y) return re; if (h[x] > h[y]) swap(x, y); fa[x] = y; siz[y] += siz[x]; re.val = h[x] == h[y]; h[y] += h[x] == h[y]; re.first = x; re.second = y; return re; } void del(int x, int y, int val) { h[y] -= val; siz[y] -= siz[x]; fa[x] = x; } void add(int o, int l, int r, int L, int R, pair<int, int> x) { if (l >= L && r <= R) { tree[o].push_back(x); return; } int mid = (l + r) >> 1; if (mid >= L) add(o << 1, l, mid, L, R, x); if (mid < R) add(o << 1 | 1, mid + 1, r, L, R, x); } int tp; gu s[1000100]; void qu(int o, int l, int r) { int now = tp, sf = 0; for (int i = 0; i < tree[o].size(); ++i) { pair<int, int> now = tree[o][i]; s[++tp] = merge(now.first, now.second); } if (l == r) { ans[l] = siz[find(ask[l])]; } else { int mid = (l + r) >> 1; qu(o << 1, l, mid); qu(o << 1 | 1, mid + 1, r); } while (tp != now) { if (s[tp].val != -1) del(s[tp].first, s[tp].second, s[tp].val); --tp; } } int main() { scanf( %d%d%d , &n, &q, &k); for (int i = 1; i <= n; ++i) fa[i] = i, siz[i] = 1, h[i] = 1; int days = 1; for (int i = 1; i <= q; ++i) { int op; scanf( %d , &op); if (op == 1) { int x, y; scanf( %d%d , &x, &y); Q.push((que){x, y, days, i}); } if (op == 2) { int o; scanf( %d , &o); ask[i] = o; } if (op == 3) { ++days; while (!Q.empty() && Q.front().times <= days - k) { add(1, 1, q, Q.front().l, i - 1, make_pair(Q.front().x, Q.front().y)); Q.pop(); } } } while (!Q.empty()) { add(1, 1, q, Q.front().l, q, make_pair(Q.front().x, Q.front().y)); Q.pop(); } qu(1, 1, q); for (int i = 1; i <= q; ++i) { if (ask[i]) printf( %d n , ans[i]); } }
#include <bits/stdc++.h> using namespace std; int T, n, k, l, a[300010], lst; bool flag = 0; int main() { scanf( %d , &T); while (T--) { flag = 0; lst = 0; scanf( %d%d%d , &n, &k, &l); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] > l) flag = 1; else if (a[i] + k <= l) lst = 0; else if (lst < k) lst = max(lst + 1, k + a[i] - l); else { if (lst + 1 + a[i] <= l + k) lst++; else flag = 1; } } if (flag) printf( No n ); else printf( Yes n ); } }
#include <bits/stdc++.h> using namespace std; #define ll long long #define mp make_pair #define rep(i,a,b) for( i=a;i<b;++i) #define repr(i,a,b) for( i=a;i>=b;i--) #define up upper_bound #define lb lower_bound #define t() int test;cin>>test;while(test--) #define IOS ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); #define TRACE #ifdef TRACE #define trace(...) __f(#__VA_ARGS__, __VA_ARGS__) template <typename Arg1> void __f(const char* name, Arg1&& arg1){ cout << name << : << arg1 << endl; //use cerr if u want to display at the bottom } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args){ const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1<< | ;__f(comma+1, args...); } #else #define trace(...) #endif bool cmp(pair<ll,ll> a,pair<ll,ll> b){ if(a.first != b.first){ return a.first < b.first; }else{ return a.second < b.second; } } int main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif IOS; ll t; cin >> t; while(t--){ ll n; cin >> n; vector<string> s(n); for(ll i = 0;i < n;i++){ cin >> s[i]; } ll k= 0; for(ll i = 0;i < n;i++){ for(ll j = 0;j < n;j++){ if (s[i][j] != . ){ k++; } } } bool flag = true; for(ll x = 0;x < 3;x++){ for(ll y = 0;y < 3;y++){ if(x == y){ continue; }else{ ll count = 0; for(ll i = 0;i < n;i++){ for(ll j= 0;j < n;j++){ if(s[i][j] == X && (i + j)%3 == x){ count++; }else if(s[i][j] == O && (i + j)%3 == y){ count++; } } } if(count <= k/3){ for(ll i = 0;i < n;i++){ for(ll j= 0;j < n;j++){ if(s[i][j] == X && (i + j)%3 == x){ s[i][j] = O ; }else if(s[i][j] == O && (i + j)%3 == y){ s[i][j] = X ; } } } for(auto it : s){ cout << it << n ; } flag = false; break; } } } if(!flag){ break; } } } return 0; }
#include <bits/stdc++.h> using namespace std; int main() { long long n, m = 1, a, t1 = 1, tong = 0; cin >> n; while (1) { tong += t1; if (tong > n) { cout << --m; return 0; } t1 += ++m; } return 0; }
#include <bits/stdc++.h> using namespace std; string a[200009]; int pre[1 << 20][22], cost[200009], n, m, dp[200009]; int compute(string suf, string pre) { for (int k = int(0); k <= int(m - 1); k++) { int j = k, i = 0; while (j < m) { if (suf[j] == pre[i]) { j++; i++; } else break; } if (j == m) return k; } return m; } int calmask(string str, int len) { int mask = 0; for (int i = int(m - len); i <= int(m - 1); i++) { mask = mask * 2; if (str[i] == 1 ) mask++; } return mask; } int calmask2(string str, int len) { int mask = 0; for (int i = int(0); i <= int(len - 1); i++) { mask = mask * 2; if (str[i] == 1 ) mask++; } return mask; } int main() { std::ios::sync_with_stdio(false); int ans; cin >> n; for (int i = int(1); i <= int(n); i++) cin >> a[i]; m = a[1].length(); for (int i = int(0); i <= int((1 << m) - 1); i++) for (int j = int(0); j <= int(m); j++) pre[i][j] = 2000000000; cost[0] = 0; for (int i = int(1); i <= int(n - 1); i++) cost[i] = cost[i - 1] + compute(a[i], a[i + 1]); pre[0][0] = cost[n - 1]; ans = 2000000000; for (int i = int(n); i >= int(1); i--) { int mini = 2000000000; int mask = 0; for (int j = int(0); j <= int(m); j++) { if (i == 1 && j > 0) break; mini = min(mini, pre[mask][j] + m - j); if (m - j - 1 >= 0 && a[i - 1][m - j - 1] == 1 ) mask |= (1 << j); } mini = mini - cost[i - 1]; dp[i] = mini; if (i - 2 >= 0) { mask = 0; for (int j = int(0); j <= int(m); j++) { pre[mask][j] = min(pre[mask][j], mini + cost[i - 2]); mask *= 2; if (j < m && a[i][j] == 1 ) mask++; } } } cout << dp[1] << endl; return 0; }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__AND2B_BLACKBOX_V `define SKY130_FD_SC_HDLL__AND2B_BLACKBOX_V /** * and2b: 2-input AND, first input inverted. * * Verilog stub definition (black box without power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hdll__and2b ( X , A_N, B ); output X ; input A_N; input B ; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HDLL__AND2B_BLACKBOX_V
// Icarus 0.6, snapshot 20020907 // ================================================== // -- confused by disables from within a fork -- vvp fails // // -- to run, incant // iverilog tt.v // vvp a.out module top; integer simple_fail, loop_fail, fork_fail, tlp_fail, tfk_fail; integer loop_cntr, tlp_cntr; reg fred, abort; initial begin #1; simple_fail = 0; loop_fail = 0; fork_fail = 0; tlp_fail = 0; tfk_fail = 0; fred = 0; abort = 1; #4; fred = 1; #4 if(simple_fail) $display("\n***** simple block disable FAILED *****"); else $display("\n***** simple block disable PASSED *****"); if(loop_fail) $display("***** block with loop disable FAILED *****"); else $display("***** block with loop disable PASSED *****"); if(fork_fail) $display("***** forked block disable FAILED *****"); else $display("***** forked block disable PASSED *****"); if(tlp_fail) $display("***** task with loop disable FAILED *****"); else $display("***** task with loop disable PASSED *****"); if(tfk_fail) $display("***** task with forked block disable FAILED ****\n"); else $display("***** task with forked block disable PASSED ****\n"); $finish; end // simple block disable initial begin: block_name #2; disable block_name; simple_fail = 1; end // more complex: block disable inside for-loop initial begin #2; begin: configloop for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin wait (fred); if (abort) begin disable configloop; end loop_fail = 1; end end // configloop block if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr); end // still more complex: disable from within a forked block initial begin #2; begin: forked_tasks fork begin #5; fork_fail = 1; end begin @(fred); disable forked_tasks; fork_fail = 1; end join fork_fail = 1; end //forked_tasks end // disables inside tasks initial begin task_with_loop; end initial begin task_with_fork; end task task_with_loop; begin #2; begin: configtlp for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin wait (fred); if (abort) begin disable configtlp; end tlp_fail = 1; end end // configloop block end endtask // task_with_loop task task_with_fork; begin #2; begin: forked_tasks_in_task fork begin #5; tfk_fail = 1; end begin @(fred); disable forked_tasks_in_task; tfk_fail = 1; end join tfk_fail = 1; end //forked_tasks_in_task end endtask // task_with_fork endmodule
/****************************************************************************** * License Agreement * * * * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * * All rights reserved. * * * * Any megafunction design, and related net list (encrypted or decrypted), * * support information, device programming or simulation file, and any other * * associated documentation or information provided by Altera or a partner * * under Altera's Megafunction Partnership Program may be used only to * * program PLD devices (but not masked PLD devices) from Altera. Any other * * use of such megafunction design, net list, support information, device * * programming or simulation file, or any other related documentation or * * information is prohibited for any other purpose, including, but not * * limited to modification, reverse engineering, de-compiling, or use with * * any other silicon devices, unless such use is explicitly licensed under * * a separate agreement with Altera or a megafunction partner. Title to * * the intellectual property, including patents, copyrights, trademarks, * * trade secrets, or maskworks, embodied in any such megafunction design, * * net list, support information, device programming or simulation file, or * * any other related documentation or information provided by Altera or a * * megafunction partner, remains with Altera, the megafunction partner, or * * their respective licensors. No other licenses, including any licenses * * needed under any third party's intellectual property, are provided herein.* * Copying or modifying any file, or portion thereof, to which this notice * * is attached violates this copyright. * * * * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * * IN THIS FILE. * * * * This agreement shall be governed in all respects by the laws of the State * * of California and by the laws of the United States of America. * * * ******************************************************************************/ /****************************************************************************** * * * This module runs through the 16x2 Character LCD initialization * * commands for the DE2 Board. * * * ******************************************************************************/ module altera_up_character_lcd_initialization ( // Inputs clk, reset, initialize_LCD_display, command_was_sent, // Bidirectionals // Outputs done_initialization, send_command, the_command ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter CURSOR_ON = 1'b1; parameter BLINKING_ON = 1'b1; // Timing info for waiting for power up // when using a 50MHz system clock parameter CLOCK_CYCLES_FOR_15MS = 750000; parameter W15 = 20; // Counter width required for 15ms parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001; // Timing info for waiting between commands // when using a 50MHz system clock parameter CLOCK_CYCLES_FOR_5MS = 250000; parameter W5 = 18; // Counter width required for 5ms parameter COUNTER_INCREMENT_FOR_5MS = 18'h00001; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input initialize_LCD_display; input command_was_sent; // Bidirectionals // Outputs output done_initialization; output send_command; output reg [ 8: 0] the_command; /***************************************************************************** * Constant Declarations * *****************************************************************************/ // States localparam LCD_INIT_STATE_0_WAIT_POWER_UP = 2'h0, LCD_INIT_STATE_1_SEND_COMMAND = 2'h1, LCD_INIT_STATE_2_CHECK_DONE = 2'h2, LCD_INIT_STATE_3_DONE = 2'h3; localparam AUTO_INIT_LENGTH = 4'h8; /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires reg [ 8: 0] command_rom; // Internal Registers reg [W15: 1] waiting_power_up; reg [W5: 1] waiting_to_send; reg [ 3: 0] command_counter; // State Machine Registers reg [ 1: 0] ns_lcd_initialize; reg [ 1: 0] s_lcd_initialize; /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ always @(posedge clk) begin if (reset) s_lcd_initialize <= LCD_INIT_STATE_0_WAIT_POWER_UP; else s_lcd_initialize <= ns_lcd_initialize; end always @(*) begin // Defaults ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP; case (s_lcd_initialize) LCD_INIT_STATE_0_WAIT_POWER_UP: begin if ((waiting_power_up == CLOCK_CYCLES_FOR_15MS) & (initialize_LCD_display)) ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND; else ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP; end LCD_INIT_STATE_1_SEND_COMMAND: begin if (command_was_sent) ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE; else ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND; end LCD_INIT_STATE_2_CHECK_DONE: begin if (command_counter == AUTO_INIT_LENGTH) ns_lcd_initialize = LCD_INIT_STATE_3_DONE; else if (waiting_to_send == CLOCK_CYCLES_FOR_5MS) ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND; else ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE; end LCD_INIT_STATE_3_DONE: begin if (initialize_LCD_display) ns_lcd_initialize = LCD_INIT_STATE_3_DONE; else ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP; end default: begin ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP; end endcase end /***************************************************************************** * Sequential Logic * *****************************************************************************/ // Output Registers always @(posedge clk) begin if (reset) the_command <= 9'h000; else the_command <= command_rom; end // Internal Registers always @(posedge clk) begin if (reset) waiting_power_up <= {W15{1'b0}}; else if ((s_lcd_initialize == LCD_INIT_STATE_0_WAIT_POWER_UP) && (waiting_power_up != CLOCK_CYCLES_FOR_15MS)) waiting_power_up <= waiting_power_up + COUNTER_INCREMENT_FOR_15MS; end always @(posedge clk) begin if (reset) waiting_to_send <= {W5{1'b0}}; else if (s_lcd_initialize == LCD_INIT_STATE_2_CHECK_DONE) begin if (waiting_to_send != CLOCK_CYCLES_FOR_5MS) waiting_to_send <= waiting_to_send + COUNTER_INCREMENT_FOR_5MS; end else waiting_to_send <= {W5{1'b0}}; end always @(posedge clk) begin if (reset) command_counter <= 4'h0; else if (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND) begin if (command_was_sent) command_counter <= command_counter + 4'h1; end else if (s_lcd_initialize == LCD_INIT_STATE_3_DONE) command_counter <= 4'h5; end /***************************************************************************** * Combinational Logic * *****************************************************************************/ // Output Assignments assign send_command = (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND); assign done_initialization = (s_lcd_initialize == LCD_INIT_STATE_3_DONE); // Internal Assignments always @(*) begin case (command_counter) 0 : command_rom <= 9'h030; 1 : command_rom <= 9'h030; 2 : command_rom <= 9'h030; 3 : command_rom <= 9'h03C; 4 : command_rom <= 9'h008; 5 : command_rom <= 9'h001; 6 : command_rom <= 9'h006; 7 : command_rom <= {7'h03, CURSOR_ON, BLINKING_ON}; default : command_rom <= 9'h000; endcase end /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule
`timescale 1ns / 1ps module LowPassFilter(clk, new_sample, input_sample, output_sample); input clk; input new_sample; reg enable_systolic; wire clk_systolic; input [15:0] input_sample; output [15:0] output_sample; reg [2:0] state; localparam IDLE = 3'd0, CLK_A = 3'd1, CLK_B = 3'd2, CLK_C = 3'd3, CLK_D = 3'd4; initial begin state <= IDLE; enable_systolic <= 1'b0; end always @ (posedge clk) begin case(state) IDLE: begin if(new_sample) state <= CLK_A; else state <= IDLE; end CLK_A: begin enable_systolic <= 1'b1; state <= CLK_B; end CLK_B: begin enable_systolic <= 1'b1; state <= CLK_C; end CLK_C: begin enable_systolic <= 1'b0; state <= IDLE; end endcase end localparam NUM_COEFFS = 99; // 57 localparam BITS_COEFF = 8; localparam NUM_COEFFS_BITS = NUM_COEFFS * BITS_COEFF; /* // Simulator coefficients localparam [NUM_COEFFS_BITS-1:0] COEFFS = { 8'sd1, 8'sd1, 8'sd1, -8'sd1 }; */ /* // Low pass coefficients localparam [NUM_COEFFS_BITS-1:0] COEFFS = { 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd2, 6'd3, 6'd5, 6'd7, 6'd10, 6'd12, 6'd15, 6'd19, 6'd22, 6'd25, 6'd28, 6'd31, 6'd33, 6'd34, 6'd34, 6'd34, 6'd33, 6'd31, 6'd28, 6'd25, 6'd22, 6'd19, 6'd15, 6'd12, 6'd10, 6'd7, 6'd5, 6'd3, 6'd2, 6'd1, 6'd1, 6'd0, 6'd0, 6'd0 }; */ // low pass 99 coeff, 100 Hz stop freq, 60 dB attenuate, 48 khz sampling freq, multiplier: 4926 localparam [NUM_COEFFS_BITS-1:0] COEFFS = { 8'sd0, 8'sd1, 8'sd1, 8'sd1, 8'sd1, 8'sd1, 8'sd2, 8'sd2, 8'sd2, 8'sd2, 8'sd3, 8'sd3, 8'sd4, 8'sd4, 8'sd4, 8'sd5, 8'sd5, 8'sd6, 8'sd6, 8'sd7, 8'sd8, 8'sd8, 8'sd9, 8'sd9, 8'sd10, 8'sd11, 8'sd11, 8'sd12, 8'sd12, 8'sd13, 8'sd14, 8'sd14, 8'sd15, 8'sd15, 8'sd16, 8'sd16, 8'sd17, 8'sd17, 8'sd18, 8'sd18, 8'sd19, 8'sd19, 8'sd19, 8'sd20, 8'sd20, 8'sd20, 8'sd20, 8'sd20, 8'sd21, 8'sd21, 8'sd21, 8'sd20, 8'sd20, 8'sd20, 8'sd20, 8'sd20, 8'sd19, 8'sd19, 8'sd19, 8'sd18, 8'sd18, 8'sd17, 8'sd17, 8'sd16, 8'sd16, 8'sd15, 8'sd15, 8'sd14, 8'sd14, 8'sd13, 8'sd12, 8'sd12, 8'sd11, 8'sd11, 8'sd10, 8'sd9, 8'sd9, 8'sd8, 8'sd8, 8'sd7, 8'sd6, 8'sd6, 8'sd5, 8'sd5, 8'sd4, 8'sd4, 8'sd4, 8'sd3, 8'sd3, 8'sd2, 8'sd2, 8'sd2, 8'sd2, 8'sd1, 8'sd1, 8'sd1, 8'sd1, 8'sd1, 8'sd0 }; wire [31:0] a_out [0:NUM_COEFFS]; wire [31:0] b_out [0:NUM_COEFFS]; genvar j; generate for(j = 0; j < NUM_COEFFS; j = j+1) begin: GEN processingUnit #(COEFFS[NUM_COEFFS_BITS-1-(j*BITS_COEFF):NUM_COEFFS_BITS-(j*BITS_COEFF)-BITS_COEFF]) gen_proc( .clk(clk), .a_in(a_out[j]), .a_out(a_out[j+1]), .b_out(b_out[j]), .b_in(b_out[j+1]), .enable(enable_systolic) ); end endgenerate assign a_out[0] = {{16{input_sample[15]}}, input_sample}; // sign extend to 32 bits assign b_out[NUM_COEFFS] = 32'h0; assign output_sample = b_out[0][26:10]; // divide by 1024 endmodule /* processingUnit #(1) p00 (clk, systolic_input, a_out[0], systolic_output, b_out[17], enable_systolic); processingUnit #(3) p01 (clk, a_out[0], a_out[1], b_out[17], b_out[16], enable_systolic); processingUnit #(5) p02 (clk, a_out[1], a_out[2], b_out[16], b_out[15], enable_systolic); processingUnit #(7) p03 (clk, a_out[2], a_out[3], b_out[15], b_out[14], enable_systolic); processingUnit #(11)p04 (clk, a_out[3], a_out[4], b_out[14], b_out[13], enable_systolic); processingUnit #(13)p05 (clk, a_out[4], a_out[5], b_out[13], b_out[12], enable_systolic); processingUnit #(16)p06 (clk, a_out[5], a_out[6], b_out[12], b_out[11], enable_systolic); processingUnit #(19)p07 (clk, a_out[6], a_out[7], b_out[11], b_out[10], enable_systolic); processingUnit #(20)p08 (clk, a_out[7], a_out[8], b_out[10], b_out[9], enable_systolic); processingUnit #(21)p09 (clk, a_out[8], a_out[9], b_out[9], b_out[8], enable_systolic); processingUnit #(20)p10 (clk, a_out[9], a_out[10], b_out[8], b_out[7], enable_systolic); processingUnit #(19)p11 (clk, a_out[10], a_out[11], b_out[7], b_out[6], enable_systolic); processingUnit #(16)p12 (clk, a_out[11], a_out[12], b_out[6], b_out[5], enable_systolic); processingUnit #(13)p13 (clk, a_out[12], a_out[13], b_out[5], b_out[4], enable_systolic); processingUnit #(11)p14 (clk, a_out[13], a_out[14], b_out[4], b_out[3], enable_systolic); processingUnit #(7) p15 (clk, a_out[14], a_out[15], b_out[3], b_out[2], enable_systolic); processingUnit #(5) p16 (clk, a_out[15], a_out[16], b_out[2], b_out[1], enable_systolic); processingUnit #(3) p17 (clk, a_out[16], a_out[17], b_out[1], b_out[0], enable_systolic); processingUnit #(1) p18 (clk, a_out[17], , b_out[0], 32'h0, enable_systolic);*/
// Identifies the sequence 11101 // includes a overlap bit sequence as well module jfsmMooreWithOverlap(dataout, clock, reset, datain); output reg dataout; input clock, reset, datain; reg[2:0] cs, ns; parameter a = 3'b000; parameter b = 3'b001; parameter c = 3'b010; parameter d = 3'b011; parameter e = 3'b100; parameter f = 3'b101; always @(posedge clock) begin if(reset) cs <= a; else cs <= ns; end always @(cs, datain) begin case(cs) a: begin if(datain) ns <= b; else ns <= a; end b: begin if(datain) ns <= c; else ns <= b; end c: begin if(datain) ns <= d; else ns <= a; end d: begin if(datain) ns <= d; else ns <= e; end e: begin if(datain) ns <= f; else ns <= a; end f: begin if(datain) ns <= c; // This has to be ns <= a; if we have to consider with overlap else ns <= a; end endcase end // This will assign the correct status to the dataout bit always @(cs, datain) begin if ( cs == e && datain == 1 ) dataout <= 1; else dataout <= 0; end endmodule
/******************************************************************************* * This file is owned and controlled by Xilinx and must be used solely * * for design, simulation, implementation and creation of design files * * limited to Xilinx devices or technologies. Use with non-Xilinx * * devices or technologies is expressly prohibited and immediately * * terminates your license. * * * * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * * PARTICULAR PURPOSE. * * * * Xilinx products are not intended for use in life support appliances, * * devices, or systems. Use in such applications are expressly * * prohibited. * * * * (c) Copyright 1995-2015 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // You must compile the wrapper file RAM_4K.v when simulating // the core, RAM_4K. When compiling the wrapper file, be sure to // reference the XilinxCoreLib Verilog simulation library. For detailed // instructions, please refer to the "CORE Generator Help". // The synthesis directives "translate_off/translate_on" specified below are // supported by Xilinx, Mentor Graphics and Synplicity synthesis // tools. Ensure they are correct for your synthesis tool(s). `timescale 1ns/1ps module RAM_4K( clka, ena, wea, addra, dina, douta ); input clka; input ena; input [0 : 0] wea; input [11 : 0] addra; input [15 : 0] dina; output [15 : 0] douta; // synthesis translate_off BLK_MEM_GEN_V6_2 #( .C_ADDRA_WIDTH(12), .C_ADDRB_WIDTH(12), .C_ALGORITHM(1), .C_AXI_ID_WIDTH(4), .C_AXI_SLAVE_TYPE(0), .C_AXI_TYPE(1), .C_BYTE_SIZE(9), .C_COMMON_CLK(0), .C_DEFAULT_DATA("0"), .C_DISABLE_WARN_BHV_COLL(1), .C_DISABLE_WARN_BHV_RANGE(1), .C_FAMILY("spartan6"), .C_HAS_AXI_ID(0), .C_HAS_ENA(1), .C_HAS_ENB(0), .C_HAS_INJECTERR(0), .C_HAS_MEM_OUTPUT_REGS_A(0), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_HAS_REGCEA(0), .C_HAS_REGCEB(0), .C_HAS_RSTA(0), .C_HAS_RSTB(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_INIT_FILE_NAME("RAM_4K.mif"), .C_INITA_VAL("0"), .C_INITB_VAL("0"), .C_INTERFACE_TYPE(0), .C_LOAD_INIT_FILE(1), .C_MEM_TYPE(0), .C_MUX_PIPELINE_STAGES(0), .C_PRIM_TYPE(1), .C_READ_DEPTH_A(4096), .C_READ_DEPTH_B(4096), .C_READ_WIDTH_A(16), .C_READ_WIDTH_B(16), .C_RST_PRIORITY_A("CE"), .C_RST_PRIORITY_B("CE"), .C_RST_TYPE("SYNC"), .C_RSTRAM_A(0), .C_RSTRAM_B(0), .C_SIM_COLLISION_CHECK("ALL"), .C_USE_BYTE_WEA(0), .C_USE_BYTE_WEB(0), .C_USE_DEFAULT_DATA(1), .C_USE_ECC(0), .C_USE_SOFTECC(0), .C_WEA_WIDTH(1), .C_WEB_WIDTH(1), .C_WRITE_DEPTH_A(4096), .C_WRITE_DEPTH_B(4096), .C_WRITE_MODE_A("WRITE_FIRST"), .C_WRITE_MODE_B("WRITE_FIRST"), .C_WRITE_WIDTH_A(16), .C_WRITE_WIDTH_B(16), .C_XDEVICEFAMILY("spartan6") ) inst ( .CLKA(clka), .ENA(ena), .WEA(wea), .ADDRA(addra), .DINA(dina), .DOUTA(douta), .RSTA(), .REGCEA(), .CLKB(), .RSTB(), .ENB(), .REGCEB(), .WEB(), .ADDRB(), .DINB(), .DOUTB(), .INJECTSBITERR(), .INJECTDBITERR(), .SBITERR(), .DBITERR(), .RDADDRECC(), .S_ACLK(), .S_ARESETN(), .S_AXI_AWID(), .S_AXI_AWADDR(), .S_AXI_AWLEN(), .S_AXI_AWSIZE(), .S_AXI_AWBURST(), .S_AXI_AWVALID(), .S_AXI_AWREADY(), .S_AXI_WDATA(), .S_AXI_WSTRB(), .S_AXI_WLAST(), .S_AXI_WVALID(), .S_AXI_WREADY(), .S_AXI_BID(), .S_AXI_BRESP(), .S_AXI_BVALID(), .S_AXI_BREADY(), .S_AXI_ARID(), .S_AXI_ARADDR(), .S_AXI_ARLEN(), .S_AXI_ARSIZE(), .S_AXI_ARBURST(), .S_AXI_ARVALID(), .S_AXI_ARREADY(), .S_AXI_RID(), .S_AXI_RDATA(), .S_AXI_RRESP(), .S_AXI_RLAST(), .S_AXI_RVALID(), .S_AXI_RREADY(), .S_AXI_INJECTSBITERR(), .S_AXI_INJECTDBITERR(), .S_AXI_SBITERR(), .S_AXI_DBITERR(), .S_AXI_RDADDRECC() ); // synthesis translate_on endmodule
#include<bits/stdc++.h> #define fre(x) freopen(#x .in , r ,stdin);freopen(#x .out , w ,stdout) #define ll long long using namespace std; inline int read(){ int x=0,f=1;char c=getchar(); while(c< 0 ||c> 9 ) { if(c== - ) f=-1;c=getchar(); } while(c>= 0 &&c<= 9 ) x=(x<<3)+(x<<1)+(c^ 0 ),c=getchar(); return x*f; } const int N=1e5+5; int n,l[N],r[N]; ll f[N][2]; vector<int>e[N]; void dfs(int x,int fa){ f[x][0]=f[x][1]=0; for(auto y:e[x]) if(y^fa){ dfs(y,x); f[x][0]+=max(f[y][0]+abs(l[x]-l[y]),f[y][1]+abs(l[x]-r[y])); f[x][1]+=max(f[y][0]+abs(r[x]-l[y]),f[y][1]+abs(r[x]-r[y])); } } inline void solve(){ n=read(); for(int i=1;i<=n;i++) l[i]=read(),r[i]=read(),e[i].clear(); for(int i=1;i<n;i++){ int x=read(),y=read(); e[x].push_back(y); e[y].push_back(x); } dfs(1,0); printf( %lld n ,max(f[1][0],f[1][1])); } int main(){ int T=read(); while(T--) solve(); return 0; }
#include <bits/stdc++.h> using namespace std; clock_t timeStart, timeFinish; void timeBegin() { timeStart = clock(); } void timeEnd() { timeFinish = clock(); } void timeDuration() { timeEnd(); double time_taken = double(timeFinish - timeStart) / double(CLOCKS_PER_SEC); cout << Time taken by program is : << fixed << time_taken << setprecision(5); cout << sec << endl; } class InputReader { public: InputReader() { input_file = stdin; cursor = 0; fread(buffer, SIZE, 1, input_file); } InputReader(const char *file_name) { input_file = fopen(file_name, r ); cursor = 0; fread(buffer, SIZE, 1, input_file); } inline InputReader &operator>>(int &n) { while ((buffer[cursor] < 0 || buffer[cursor] > 9 ) && buffer[cursor] != - ) { advance(); } int sign = 1; if (buffer[cursor] == - ) { sign = -1; advance(); } n = 0; while ( 0 <= buffer[cursor] && buffer[cursor] <= 9 ) { n = n * 10 + buffer[cursor] - 0 ; advance(); } n *= sign; return *this; } private: FILE *input_file; static const int SIZE = 1 << 17; int cursor; char buffer[SIZE]; inline void advance() { ++cursor; if (cursor == SIZE) { cursor = 0; fread(buffer, SIZE, 1, input_file); } } }; const int MAXN = 200000; const int MAXLOG = 18; const int INF = 1000000000; vector<int> g[1 + MAXN]; vector<pair<int, int> > t[1 + MAXN]; int dad[1 + MAXLOG][1 + MAXN], answer[1 + MAXN], virusId[1 + MAXN]; int counter = 0, start[1 + MAXN], finish[1 + MAXN], depth[1 + MAXN]; int speed[1 + MAXN], id[1 + MAXN], virus[1 + MAXN], city[1 + MAXN], st[1 + MAXN]; void DFS(int node, int father) { dad[0][node] = father; depth[node] = depth[father] + 1; for (int i = 1; (1 << i) < depth[node]; i++) { dad[i][node] = dad[i - 1][dad[i - 1][node]]; } start[node] = ++counter; for (auto son : g[node]) { if (son != father) { DFS(son, node); } } finish[node] = counter; } int raise(int node, int delta) { for (int i = 0; i < MAXLOG; i++) { if ((delta >> i) & 1) { node = dad[i][node]; } } return node; } bool isParent(int a, int b) { return start[a] <= start[b] && finish[b] <= finish[a]; } int lca(int a, int b) { if (depth[a] < depth[b]) { swap(a, b); } a = raise(a, depth[a] - depth[b]); for (int i = MAXLOG - 1; i >= 0; i--) { if (dad[i][a] != dad[i][b]) { a = dad[i][a]; b = dad[i][b]; } } if (a != b) { a = dad[0][a]; b = dad[0][b]; } return a; } inline bool compareStart(const int &a, const int &b) { return start[a] < start[b]; } void sortUnique(vector<int> &v) { sort(v.begin(), v.end(), compareStart); v.resize(unique(v.begin(), v.end()) - v.begin()); } pair<int, int> d[1 + MAXN]; bool isSmaller(int c1, int s1, int c2, int s2) { int t1 = (c1 == 0 ? 0 : (c1 - 1) / speed[s1] + 1); int t2 = (c2 == 0 ? 0 : (c2 - 1) / speed[s2] + 1); return make_pair(t1, virusId[s1]) < make_pair(t2, virusId[s2]); } bool seen[1 + MAXN]; void dijkstra(vector<int> &v) { priority_queue<pair<pair<int, int>, pair<int, int> >, vector<pair<pair<int, int>, pair<int, int> > >, greater<pair<pair<int, int>, pair<int, int> > > > h; for (auto node : v) { if (virusId[node] != 0) { d[node] = {0, virusId[node]}; h.push({{0, virusId[node]}, {node, 0}}); } else { d[node] = {INF, 0}; } } while (!h.empty()) { int r = h.top().first.first, s = h.top().first.second, node = h.top().second.first, c = h.top().second.second; h.pop(); if (seen[node]) { continue; } seen[node] = true; for (auto it : t[node]) { int other = it.first, l = it.second; int r0 = (c + l - 1) / speed[s] + 1, s0 = s; if (make_pair(r0, s0) < d[other]) { d[other] = {r0, s0}; h.push({{r0, s0}, {other, c + l}}); } } } } void solve(int k, int m) { vector<int> v; for (int i = 1; i <= k; i++) { v.push_back(virus[i]); } for (int i = 1; i <= m; i++) { v.push_back(city[i]); } sortUnique(v); int x = v.size(); for (int i = 0; i + 1 < x; i++) { v.push_back(lca(v[i], v[i + 1])); } sortUnique(v); int top = 1; st[top] = v[0]; for (int i = 1; i < v.size(); i++) { int node = v[i]; while (!isParent(st[top], node)) { top--; } int l = depth[node] - depth[st[top]]; t[st[top]].push_back({node, l}); t[node].push_back({st[top], l}); top++; st[top] = node; } dijkstra(v); for (auto node : v) { seen[node] = false; t[node].clear(); if (id[node] != 0) { answer[id[node]] = d[node].second; } } } int main() { timeBegin(); ios_base::sync_with_stdio(false); cin.tie(0); speed[0] = 1; int n; cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } DFS(1, 0); int q; cin >> q; for (int i = 1; i <= q; i++) { int k, m; cin >> k >> m; for (int i = 1; i <= k; i++) { cin >> virus[i] >> speed[i]; virusId[virus[i]] = i; } for (int i = 1; i <= m; i++) { cin >> city[i]; id[city[i]] = i; } solve(k, m); for (int i = 1; i <= m; i++) { cout << answer[i] << ; } cout << n ; for (int i = 1; i <= k; i++) { virusId[virus[i]] = 0; } for (int i = 1; i <= m; i++) { id[city[i]] = 0; } } return 0; }
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_solo_nios2_gen2_0_cpu_debug_slave_wrapper ( // inputs: MonDReg, break_readreg, clk, dbrk_hit0_latch, dbrk_hit1_latch, dbrk_hit2_latch, dbrk_hit3_latch, debugack, monitor_error, monitor_ready, reset_n, resetlatch, tracemem_on, tracemem_trcdata, tracemem_tw, trc_im_addr, trc_on, trc_wrap, trigbrktype, trigger_state_1, // outputs: jdo, jrst_n, st_ready_test_idle, take_action_break_a, take_action_break_b, take_action_break_c, take_action_ocimem_a, take_action_ocimem_b, take_action_tracectrl, take_no_action_break_a, take_no_action_break_b, take_no_action_break_c, take_no_action_ocimem_a ) ; output [ 37: 0] jdo; output jrst_n; output st_ready_test_idle; output take_action_break_a; output take_action_break_b; output take_action_break_c; output take_action_ocimem_a; output take_action_ocimem_b; output take_action_tracectrl; output take_no_action_break_a; output take_no_action_break_b; output take_no_action_break_c; output take_no_action_ocimem_a; input [ 31: 0] MonDReg; input [ 31: 0] break_readreg; input clk; input dbrk_hit0_latch; input dbrk_hit1_latch; input dbrk_hit2_latch; input dbrk_hit3_latch; input debugack; input monitor_error; input monitor_ready; input reset_n; input resetlatch; input tracemem_on; input [ 35: 0] tracemem_trcdata; input tracemem_tw; input [ 6: 0] trc_im_addr; input trc_on; input trc_wrap; input trigbrktype; input trigger_state_1; wire [ 37: 0] jdo; wire jrst_n; wire [ 37: 0] sr; wire st_ready_test_idle; wire take_action_break_a; wire take_action_break_b; wire take_action_break_c; wire take_action_ocimem_a; wire take_action_ocimem_b; wire take_action_tracectrl; wire take_no_action_break_a; wire take_no_action_break_b; wire take_no_action_break_c; wire take_no_action_ocimem_a; wire vji_cdr; wire [ 1: 0] vji_ir_in; wire [ 1: 0] vji_ir_out; wire vji_rti; wire vji_sdr; wire vji_tck; wire vji_tdi; wire vji_tdo; wire vji_udr; wire vji_uir; //Change the sld_virtual_jtag_basic's defparams to //switch between a regular Nios II or an internally embedded Nios II. //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. nios_solo_nios2_gen2_0_cpu_debug_slave_tck the_nios_solo_nios2_gen2_0_cpu_debug_slave_tck ( .MonDReg (MonDReg), .break_readreg (break_readreg), .dbrk_hit0_latch (dbrk_hit0_latch), .dbrk_hit1_latch (dbrk_hit1_latch), .dbrk_hit2_latch (dbrk_hit2_latch), .dbrk_hit3_latch (dbrk_hit3_latch), .debugack (debugack), .ir_in (vji_ir_in), .ir_out (vji_ir_out), .jrst_n (jrst_n), .jtag_state_rti (vji_rti), .monitor_error (monitor_error), .monitor_ready (monitor_ready), .reset_n (reset_n), .resetlatch (resetlatch), .sr (sr), .st_ready_test_idle (st_ready_test_idle), .tck (vji_tck), .tdi (vji_tdi), .tdo (vji_tdo), .tracemem_on (tracemem_on), .tracemem_trcdata (tracemem_trcdata), .tracemem_tw (tracemem_tw), .trc_im_addr (trc_im_addr), .trc_on (trc_on), .trc_wrap (trc_wrap), .trigbrktype (trigbrktype), .trigger_state_1 (trigger_state_1), .vs_cdr (vji_cdr), .vs_sdr (vji_sdr), .vs_uir (vji_uir) ); nios_solo_nios2_gen2_0_cpu_debug_slave_sysclk the_nios_solo_nios2_gen2_0_cpu_debug_slave_sysclk ( .clk (clk), .ir_in (vji_ir_in), .jdo (jdo), .sr (sr), .take_action_break_a (take_action_break_a), .take_action_break_b (take_action_break_b), .take_action_break_c (take_action_break_c), .take_action_ocimem_a (take_action_ocimem_a), .take_action_ocimem_b (take_action_ocimem_b), .take_action_tracectrl (take_action_tracectrl), .take_no_action_break_a (take_no_action_break_a), .take_no_action_break_b (take_no_action_break_b), .take_no_action_break_c (take_no_action_break_c), .take_no_action_ocimem_a (take_no_action_ocimem_a), .vs_udr (vji_udr), .vs_uir (vji_uir) ); //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS assign vji_tck = 1'b0; assign vji_tdi = 1'b0; assign vji_sdr = 1'b0; assign vji_cdr = 1'b0; assign vji_rti = 1'b0; assign vji_uir = 1'b0; assign vji_udr = 1'b0; assign vji_ir_in = 2'b0; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // sld_virtual_jtag_basic nios_solo_nios2_gen2_0_cpu_debug_slave_phy // ( // .ir_in (vji_ir_in), // .ir_out (vji_ir_out), // .jtag_state_rti (vji_rti), // .tck (vji_tck), // .tdi (vji_tdi), // .tdo (vji_tdo), // .virtual_state_cdr (vji_cdr), // .virtual_state_sdr (vji_sdr), // .virtual_state_udr (vji_udr), // .virtual_state_uir (vji_uir) // ); // // defparam nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES", // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0, // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2, // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70, // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "", // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0, // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0, // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34, // nios_solo_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3; // //synthesis read_comments_as_HDL off endmodule
// ============================================================== // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC // Version: 2015.4 // Copyright (C) 2015 Xilinx Inc. All rights reserved. // // ============================================================== `timescale 1ns/1ps module feedforward_fpext_32ns_64_1 #(parameter ID = 4, NUM_STAGE = 1, din0_WIDTH = 32, dout_WIDTH = 64 )( input wire [din0_WIDTH-1:0] din0, output wire [dout_WIDTH-1:0] dout ); //------------------------Local signal------------------- wire a_tvalid; wire [31:0] a_tdata; wire r_tvalid; wire [63:0] r_tdata; //------------------------Instantiation------------------ feedforward_ap_fpext_0_no_dsp_32 feedforward_ap_fpext_0_no_dsp_32_u ( .s_axis_a_tvalid ( a_tvalid ), .s_axis_a_tdata ( a_tdata ), .m_axis_result_tvalid ( r_tvalid ), .m_axis_result_tdata ( r_tdata ) ); //------------------------Body--------------------------- assign a_tvalid = 1'b1; assign a_tdata = din0==='bx ? 'b0 : din0; assign dout = r_tdata; endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__OR4BB_PP_BLACKBOX_V `define SKY130_FD_SC_LP__OR4BB_PP_BLACKBOX_V /** * or4bb: 4-input OR, first two inputs inverted. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__or4bb ( X , A , B , C_N , D_N , VPWR, VGND, VPB , VNB ); output X ; input A ; input B ; input C_N ; input D_N ; input VPWR; input VGND; input VPB ; input VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__OR4BB_PP_BLACKBOX_V
#include <bits/stdc++.h> using namespace std; long long i, j, k, l, n, a, b, ans = 0; int gcd(int a, int b) { if (a < b) swap(a, b); return (b == 0) ? a : gcd(b, a % b); } struct st { int first; long double second; }; int main() { std::ios_base::sync_with_stdio(0); string s; cin >> s; n = s.size(); list<int> left, right; j = 0; for (auto i : s) { if (i == l ) { left.push_front(++j); } else { right.push_front(++j); } } reverse(right.begin(), right.end()); for (auto i : right) cout << i << n ; for (auto i : left) cout << i << n ; fflush(stdin); return 0; }
/****************************************************************************** * License Agreement * * * * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * * All rights reserved. * * * * Any megafunction design, and related net list (encrypted or decrypted), * * support information, device programming or simulation file, and any other * * associated documentation or information provided by Altera or a partner * * under Altera's Megafunction Partnership Program may be used only to * * program PLD devices (but not masked PLD devices) from Altera. Any other * * use of such megafunction design, net list, support information, device * * programming or simulation file, or any other related documentation or * * information is prohibited for any other purpose, including, but not * * limited to modification, reverse engineering, de-compiling, or use with * * any other silicon devices, unless such use is explicitly licensed under * * a separate agreement with Altera or a megafunction partner. Title to * * the intellectual property, including patents, copyrights, trademarks, * * trade secrets, or maskworks, embodied in any such megafunction design, * * net list, support information, device programming or simulation file, or * * any other related documentation or information provided by Altera or a * * megafunction partner, remains with Altera, the megafunction partner, or * * their respective licensors. No other licenses, including any licenses * * needed under any third party's intellectual property, are provided herein.* * Copying or modifying any file, or portion thereof, to which this notice * * is attached violates this copyright. * * * * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * * IN THIS FILE. * * * * This agreement shall be governed in all respects by the laws of the State * * of California and by the laws of the United States of America. * * * ******************************************************************************/ /****************************************************************************** * * * This module scales video streams on the DE boards. * * * ******************************************************************************/ module niosII_system_video_scaler_0 ( // Inputs clk, reset, stream_in_data, stream_in_startofpacket, stream_in_endofpacket, stream_in_empty, stream_in_valid, stream_out_ready, // Bidirectional // Outputs stream_in_ready, stream_out_data, stream_out_startofpacket, stream_out_endofpacket, stream_out_empty, stream_out_valid ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter DW = 29; // Frame's Data Width parameter EW = 1; // Frame's Empty Width parameter WIW = 8; // Incoming frame's width's address width parameter HIW = 7; // Incoming frame's height's address width parameter WIDTH_IN = 320; parameter WIDTH_DROP_MASK = 4'b0000; parameter HEIGHT_DROP_MASK = 4'b0000; parameter MH_WW = 8; // Multiply height's incoming width's address width parameter MH_WIDTH_IN = 320; // Multiply height's incoming width parameter MH_CW = 0; // Multiply height's counter width parameter MW_CW = 0; // Multiply width's counter width /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input [DW: 0] stream_in_data; input stream_in_startofpacket; input stream_in_endofpacket; input [EW: 0] stream_in_empty; input stream_in_valid; input stream_out_ready; // Bidirectional // Outputs output stream_in_ready; output [DW: 0] stream_out_data; output stream_out_startofpacket; output stream_out_endofpacket; output [EW: 0] stream_out_empty; output stream_out_valid; /***************************************************************************** * Constant Declarations * *****************************************************************************/ /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires wire [DW: 0] internal_data; wire internal_startofpacket; wire internal_endofpacket; wire internal_valid; wire internal_ready; // Internal Registers // State Machine Registers // Integers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential Logic * *****************************************************************************/ // Output Registers // Internal Registers /***************************************************************************** * Combinational Logic * *****************************************************************************/ // Output Assignments assign stream_out_empty = 'h0; // Internal Assignments /***************************************************************************** * Internal Modules * *****************************************************************************/ altera_up_video_scaler_multiply_height Multiply_Height ( // Inputs .clk (clk), .reset (reset), .stream_in_data (stream_in_data), .stream_in_startofpacket (stream_in_startofpacket), .stream_in_endofpacket (stream_in_endofpacket), .stream_in_valid (stream_in_valid), .stream_out_ready (internal_ready), // Bi-Directional // Outputs .stream_in_ready (stream_in_ready), .stream_out_data (internal_data), .stream_out_startofpacket (internal_startofpacket), .stream_out_endofpacket (internal_endofpacket), .stream_out_valid (internal_valid) ); defparam Multiply_Height.DW = DW, Multiply_Height.WW = MH_WW, Multiply_Height.WIDTH = MH_WIDTH_IN, Multiply_Height.CW = MH_CW; altera_up_video_scaler_multiply_width Multiply_Width ( // Inputs .clk (clk), .reset (reset), .stream_in_data (internal_data), .stream_in_startofpacket (internal_startofpacket), .stream_in_endofpacket (internal_endofpacket), .stream_in_valid (internal_valid), .stream_out_ready (stream_out_ready), // Bi-Directional // Outputs .stream_in_ready (internal_ready), .stream_out_data (stream_out_data), .stream_out_startofpacket (stream_out_startofpacket), .stream_out_endofpacket (stream_out_endofpacket), .stream_out_valid (stream_out_valid) ); defparam Multiply_Width.DW = DW, Multiply_Width.CW = MW_CW; endmodule
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module soc_system_led_pio ( // inputs: address, chipselect, clk, reset_n, write_n, writedata, // outputs: out_port, readdata ) ; output [ 9: 0] out_port; output [ 31: 0] readdata; input [ 1: 0] address; input chipselect; input clk; input reset_n; input write_n; input [ 31: 0] writedata; wire clk_en; reg [ 9: 0] data_out; wire [ 9: 0] out_port; wire [ 9: 0] read_mux_out; wire [ 31: 0] readdata; assign clk_en = 1; //s1, which is an e_avalon_slave assign read_mux_out = {10 {(address == 0)}} & data_out; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) data_out <= 0; else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[9 : 0]; end assign readdata = {32'b0 | read_mux_out}; assign out_port = data_out; endmodule
//*******************************************************************************************************************************************************/ // Module Name: user_interface // Module Type: User Interface and External Communications Module // Author: Shreyas Vinod // Purpose: User Interface and External Communications Module for Neptune I v3.0 // Description: A simplistic User Interface and Front Panel Communications and Translation Module that takes a small number of inputs from Neptune I's // Front Panel and converts it into a multitude of signals to communicate in perfect harmony with Neptune I's Control Matrix. It's able // to request for IO and Bus Access as well. It is also capable of driving two sets of five 7-segment displays with binary outputs that // can later be externally decoded into BCD or hexadecimal. //*******************************************************************************************************************************************************/ module user_interface(clk, rst, dma_req, dma_appr, wr, add_wr, incr_add, clk_sel, entity_sel, pc_rd, mar_rd, rf_rd1, rf_rd2, ram_rd, stk_rd, alu_rd, data_in, sys_clk, sys_rst, sys_hrd_rst, sys_dma_req, mar_incr, we_out, d_out, add_out, data_out); // Parameter Definitions parameter width = 'd16; // Data Width parameter add_width = 'd13; // Address Width parameter disp_output_width = 'd20; // Display Driver Data Width // Inputs input wire clk /* External Clock */, rst /* External Reset Request */, dma_req /* External Direct Memory Access (DMA) Request */; // Management Interfaces input wire dma_appr /* External Direct Memory Access (DMA) Request Approval Notification */; // Notification Interfaces input wire wr /* External Write Request */, add_wr /* External Address Write Request */; input wire incr_add /* Increment Address Request */, clk_sel /* Clock Select Toggle */; input wire [2:0] entity_sel /* Read/Write Processor Entity Select */; input wire [add_width-1:0] mar_rd /* Memory Address Register (MAR) Read */; input wire [width-1:0] pc_rd /* Program Counter (PC) Read */, rf_rd1 /* Register File Port (RF) I Read */, rf_rd2 /* Register File (RF) Port II Read */, ram_rd /* Random Access Memory (RAM) Read */; input wire [width-1:0] stk_rd /* Stack Read */, alu_rd /* ALU Result Read */; input wire [width-1:0] data_in /* External Data Input Port */; // Outputs output wire sys_clk /* System Clock Output */, sys_rst /* System Reset Output */, sys_hrd_rst /* System Hard Reset Output */, sys_dma_req /* Request Direct Memory Access (DMA) from System */; output wire mar_incr /* Increment MAR Request */; output wire [2:0] we_out /* Control Matrix Write Enable Request */; output wire [width-1:0] d_out /* Data Output for Direct Memory Access (DMA) Write Requests */; output wire [disp_output_width-1:0] add_out /* External Address Output Port */; output wire [disp_output_width:0] data_out /* External Data Output Port */; // Internals reg sclk /* Slow Clock Driver */, rst_buf /* External Reset Request Buffer */, dma_req_buf /* External Direct Memory Access (DMA) Request Buffer */, wr_buf /* External Write Request Buffer */; reg add_wr_buf /* External Address Write Request Buffer */, incr_add_buf /* Increment Address Request Buffer */, incr_c /* Incrementation Complete Notification */; reg [2:0] entity_sel_buf /* Read/Write Processor Entity Select Buffer */, entity_sel_buf_t /* True Entity Select Buffer */; reg [3:0] stclk /* Reset LED State Clock */; reg [width-1:0] data_in_buf /* Data Input Buffer */, data_conv_buf /* Hex Conversion Data Buffer */; reg [disp_output_width:0] a_bus_disp; // Binary to Hex (Extended Binary, decoded by Display Driver) converted Address Output signal. Extra bit ignored. reg [disp_output_width:0] d_bus_disp; // Binary to Hex (Extended Binary, decoded by Display Driver) converted Data Output signals. One extra bit for sign notation. reg [23:0] counter /* Slow Clock Driver Counter */; // Initialization initial begin sclk <= 1'b0; stclk [3;0] <= 4'b0; counter [23:0] <= 24'b0; end // Slow Clock Driver Block always@(posedge clk) begin if(counter [23:0] < ) counter [23:0] <= counter [23:0] + 1'b1; else begin sclk <= !sclk; counter [23:0] <= 24'b0; end end // Write Request assign we_out [2:0] = (wr_buf && dma_appr)?entity_sel_buf [2:0]:3'b0; // Output Logic assign sys_clk = (clk_sel)?sclk:clk; // System Clock Select assign sys_rst = (rst_buf)?1'b1:1'b0; // Reset Enable assign sys_hrd_rst = (rst_buf && wr_buf && add_wr_buf && incr_add_buf && (entity_sel_buf == 3'b0))?1'b1:1'b0; // Hard Reset Enable Logic assign sys_dma_req = dma_req_buf; // Request Direct Memory Access (DMA) from Control Matrix assign mar_incr = incr_add_buf; // Increment MAR contents. assign d_out [width-1:0] = data_in_buf [width-1:0]; // Assigns the Direct Memory Access (DMA) Write Request Data Line based on input. assign add_out [disp_output_width-1:0] = a_bus_disp [disp_output_width-1:0]; // Assigns the Address Output Port the value of the Address Output buffer. assign data_out [disp_output_width:0] = d_bus_disp [disp_output_width:0]; // Assigns the Data Output Port the value of the Data Output buffer. // Buffer Logic always@(posedge sclk) begin rst_buf <= rst; // External Reset Request Buffer dma_req_buf <= dma_req; // External Direct Memory Access (DMA) Request Buffer wr_buf <= wr; // External Write Request Buffer add_wr_buf <= add_wr; // External Address Write Request Buffer data_in_buf <= data_in; // External Data Input Buffer // Entity Select entity_sel_buf_t [2:0] <= entity_sel [2:0]; // True Entity Select Buffer based on input. if(add_wr_buf) entity_sel_buf [2:0] <= 3'b101; // Select MAR to write address. else entity_sel_buf [2:0] <= entity_sel [2:0]; // Select Entity based on input. end // Data Conversion Buffer always@(entity_sel_buf_t, rf_rd1, rf_rd2, ram_rd, pc_rd, mar_rd, stk_rd, alu_rd) begin case(entity_sel_buf_t) // synthesis parallel_case 3'b000: data_conv_buf [width-1:0] = {width{1'b0}}; 3'b001: data_conv_buf [width-1:0] = rf_rd1 [width-1:0]; 3'b010: data_conv_buf [width-1:0] = rf_rd2 [width-1:0]; 3'b011: data_conv_buf [width-1:0] = ram_rd [width-1:0]; 3'b100: data_conv_buf [width-1:0] = pc_rd [width-1:0]; 3'b101: data_conv_buf [width-1:0] = {{width-add_width{1'b0}}, mar_rd [add_width-1:0]}; 3'b110: data_conv_buf [width-1:0] = stk_rd [width-1:0]; 3'b111: data_conv_buf [width-1:0] = alu_rd [width-1:0]; default: data_conv_buf [width-1:0] = {width{1'b0}}; endcase end // Incrementation Logic and signal buffer // This block ensures that incrementation takes place only once for every increment request by using the 'Incrementation Complete (incr_c)' notification. always@(posedge sclk) begin if(!incr_add_buf && incr_add && !incr_c) incr_add_buf <= 1'b1; else if(incr_add_buf && incr_add) begin incr_add_buf <= 1'b0; incr_c <= 1'b1; end else if(!incr_add) begin incr_add_buf <= 1'b0; incr_c <= 1'b0; end end // Binary to Hex (Extended Binary, decoded by Display Driver) Conversion Block // Address Bus always@(mar_rd) begin a_bus_disp [disp_output_width:0] = {7'b0, mar_rd [add_width-1:0]}; end // Data Bus always@(data_conv_buf) begin d_bus_disp [disp_output_width:0] = {data_conv_buf[width-1], 4'b0, data_conv_buf [width-2:0]}; end endmodule
#include <bits/stdc++.h> using namespace std; bool s[100005]; int main() { int n; cin >> n; n *= 2; int ans = 0, rst = 0; ; while (n--) { int tmp; cin >> tmp; if (s[tmp]) ans -= 1; else s[tmp] = 1, ans++; rst = max(rst, ans); } cout << rst << endl; return 0; }
#include <bits/stdc++.h> using namespace std; const int N = 356438; int from[N], to[N], limL, nextp[N], headp[N], p[N], Lcnt[N], chcnt[N], num, a[N], b[N], sz, c[N]; bool taboo[N], boo[N]; long long limW, W[N], Wcnt[N], ans; inline int lowbit(int x) { return x & (-x); } inline int ask(int x) { int ans = 0; while (x) { ans += c[x]; x -= lowbit(x); } return ans; } inline void add(int x, int y) { while (x < N) { c[x] += y; x += lowbit(x); } } inline void addedge(int x, int y, long long z, int &tot) { from[tot] = x; to[tot] = y; W[tot] = z; nextp[tot] = headp[x]; headp[x] = tot; ++tot; } void dfs(int x) { a[sz] = x; ++sz; chcnt[x] = 1; for (int i = headp[x]; i != -1; i = nextp[i]) { if (taboo[i]) continue; int y = to[i]; if (p[x] != -1 && from[p[x]] == y) continue; p[y] = i; dfs(y); chcnt[x] += chcnt[y]; } } void dfs2(int x, bool b) { boo[x] = b; for (int i = headp[x]; i != -1; i = nextp[i]) { if (taboo[i]) continue; int y = to[i]; if (p[x] != -1 && from[p[x]] == y) continue; p[y] = i; Lcnt[y] = Lcnt[x] + 1; Wcnt[y] = Wcnt[x] + W[i]; dfs2(y, b); } } inline bool cmpb(int x, int y) { if (Wcnt[x] != Wcnt[y]) return Wcnt[x] < Wcnt[y]; if (Lcnt[x] != Lcnt[y]) return Lcnt[x] < Lcnt[y]; return boo[x] < boo[y]; } void work(int root) { p[root] = -1; Lcnt[root] = 0; Wcnt[root] = 0; sz = 0; dfs(root); if (sz == 1) return; int tempsz = 0, tempedge = -1; for (int i = 1; i < sz; ++i) { int x = a[i]; if (min(chcnt[x], sz - chcnt[x]) > tempsz) { tempsz = min(chcnt[x], sz - chcnt[x]); tempedge = p[x]; } } taboo[tempedge] = taboo[tempedge ^ 1] = true; Lcnt[from[tempedge]] = 0; Wcnt[from[tempedge]] = 0; p[from[tempedge]] = -1; dfs2(from[tempedge], true); Lcnt[to[tempedge]] = 0; Wcnt[to[tempedge]] = 0; p[to[tempedge]] = -1; dfs2(to[tempedge], false); for (int i = 0; i < sz; ++i) { int x = a[i]; if (boo[x]) { Lcnt[x] = limL - Lcnt[x] - 1; Wcnt[x] = limW - Wcnt[x] - W[tempedge]; } b[i] = x; } sort(b, b + sz, cmpb); for (int i = 0; i < sz; ++i) { int x = b[i]; if (boo[x]) { if (Lcnt[x] < 0) continue; ans += ask(Lcnt[x] + 1); } else { add(Lcnt[x] + 1, 1); } } for (int i = 0; i < sz; ++i) { int x = b[i]; if (boo[x]) { } else { add(Lcnt[x] + 1, -1); } } work(to[tempedge]); work(from[tempedge]); } int main() { int n; scanf( %d%d%I64d , &n, &limL, &limW); int tot = 0; memset(headp, -1, sizeof(headp)); for (int i = 2; i <= n; ++i) { int j; long long temp; scanf( %d %I64d , &j, &temp); addedge(i, j, temp, tot); addedge(j, i, temp, tot); } work(1); printf( %I64d n , ans); }
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0, ways = 0; int c[100]; cin >> n; for (int i = 0; i < n; ++i) { cin >> c[i]; sum = sum + c[i]; } for (int i = 0; i < n; ++i) { if ((sum - c[i]) % 2 == 0) ways++; } cout << ways << endl; return 0; }
`define WIDTH_P 3 `define CASE_P 1 // XOR:1, AND:2, OR:3 /**************************** TEST RATIONALE ******************************* 1. STATE SPACE This module tests hi_to_lo and lo_to_hi simultaneously by instantiating two DUTs, DUT_hilo and DUT_lohi. Each unit is tested for entire state space of a binary number of WIDTH_P. 2. PARAMETERIZATION DUT's implementation is not much influenced by WIDTH_P. CASE_P can have only one of the three values 100, 010 and 001. So a minimum set of test might be WIDTH_P = 1,2,3,4 and CASE_P = 100,010,001. Tests with a large WIDTH_P take long to finish because the number of test inputs grow exponentially with WIDTH_P. ***************************************************************************/ module test_bsg #( parameter cycle_time_p = 20, parameter width_p = `WIDTH_P, // width of test input parameter xor_p = (`CASE_P==1), parameter and_p = (`CASE_P==2), parameter or_p = (`CASE_P==3), parameter reset_cycles_lo_p=0, parameter reset_cycles_hi_p=5 ); wire clk; wire reset; bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p) ) clock_gen ( .o(clk) ); bsg_nonsynth_reset_gen #( .num_clocks_p (1) , .reset_cycles_lo_p(reset_cycles_lo_p) , .reset_cycles_hi_p(reset_cycles_hi_p) ) reset_gen ( .clk_i (clk) , .async_reset_o(reset) ); initial begin $display("\n\n\n"); $display("==========================================================="); $display("testing with ..."); $display("WIDTH_P: %d", `WIDTH_P); $display("CASE_P : %d\n", `CASE_P); end logic [width_p-1:0] test_input, test_output_hilo, test_output_lohi; logic [width_p-1:0] ref_test_output_hilo, ref_test_output_lohi; logic finish_r; always_comb begin // hi to lo if(xor_p == 1) begin ref_test_output_hilo[width_p-1] = 0 ^ test_input[width_p-1]; for(int i=width_p-2; i>=0; --i) ref_test_output_hilo[i] = ref_test_output_hilo[i+1] ^ test_input[i]; end else if(and_p == 1) begin ref_test_output_hilo[width_p-1] = 1 & test_input[width_p-1]; for(int i=width_p-2; i>=0; --i) ref_test_output_hilo[i] = ref_test_output_hilo[i+1] & test_input[i]; end else if(or_p == 1) begin ref_test_output_hilo[width_p-1] = 0 | test_input[width_p-1]; for(int i=width_p-2; i>=0; --i) ref_test_output_hilo[i] = ref_test_output_hilo[i+1] | test_input[i]; end // lo to hi if(xor_p == 1) begin ref_test_output_lohi[0] = 0 ^ test_input[0]; for(int i=1; i<width_p; ++i) ref_test_output_lohi[i] = ref_test_output_lohi[i-1] ^ test_input[i]; end else if(and_p == 1) begin ref_test_output_lohi[0] = 1 & test_input[0]; for(int i=1; i<width_p; ++i) ref_test_output_lohi[i] = ref_test_output_lohi[i-1] & test_input[i]; end else if(or_p == 1) begin ref_test_output_lohi[0] = 0 | test_input[0]; for(int i=1; i<width_p; ++i) ref_test_output_lohi[i] = ref_test_output_lohi[i-1] | test_input[i]; end end always_ff @(posedge clk) begin if(reset) begin test_input <= 0; finish_r <= 1'b0; end else test_input <= test_input+1; if(&test_input) finish_r <= 1'b1; end always_ff @(posedge clk) begin /*$display("test_input: %b, test_output_hilo: %b, test_output_lohi: %b" , test_input, test_output_hilo, test_output_lohi);*/ if(!reset) begin assert (ref_test_output_hilo == test_output_hilo) else $error("hi_to_lo_scan: mismatch on input %x; expected output: %x; " , test_input, ref_test_output_hilo, "test output: %x", test_output_hilo); assert (ref_test_output_lohi == test_output_lohi) else $error("lo_to_hi_scan: mismatch on input %x; expected output: %x; " , test_input, ref_test_output_lohi, "test output: %x", test_output_lohi); end if(finish_r) begin $display("==============================================================\n"); $finish; end end bsg_scan #( .width_p (width_p) , .xor_p (xor_p) , .and_p (and_p) , .or_p (or_p) , .lo_to_hi_p(0) ) DUT_hilo ( .i(test_input) , .o(test_output_hilo) ); bsg_scan #( .width_p (width_p) , .xor_p (xor_p) , .and_p (and_p) , .or_p (or_p) , .lo_to_hi_p(1) ) DUT_lohi ( .i(test_input) , .o(test_output_lohi) ); /*logic [(5*width_p)-1:0] log; assign log = {test_output_lohi, test_output_hilo, ref_test_output_lohi , ref_test_output_hilo, test_input}; bsg_nonsynth_ascii_writer #( .width_p (width_p) , .values_p (5) , .filename_p ("output.log") , .fopen_param_p("a+") , .format_p ("%b") ) ascii_writer( .clk (clk) , .reset_i(reset) , .valid_i(1'b1) , .data_i (log) );*/ endmodule
/* * Milkymist VJ SoC * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 3 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ module hpdmc_ddrio( input sys_clk, input sys_clk_n, input dqs_clk, input dqs_clk_n, input direction, input direction_r, input [7:0] mo, input [63:0] do, output [63:0] di, output [3:0] sdram_dqm, inout [31:0] sdram_dq, inout [3:0] sdram_dqs, input idelay_rst, input idelay_ce, input idelay_inc ); /******/ /* DQ */ /******/ wire [31:0] sdram_dq_t; wire [31:0] sdram_dq_out; wire [31:0] sdram_dq_in; hpdmc_iobuf32 iobuf_dq( .T(sdram_dq_t), .I(sdram_dq_out), .O(sdram_dq_in), .IO(sdram_dq) ); hpdmc_oddr32 oddr_dq_t( .Q(sdram_dq_t), .C0(sys_clk), .C1(sys_clk_n), .CE(1'b1), .D0({32{~direction_r}}), .D1({32{~direction_r}}), .R(1'b0), .S(1'b0) ); hpdmc_oddr32 oddr_dq( .Q(sdram_dq_out), .C0(sys_clk), .C1(sys_clk_n), .CE(1'b1), .D0(do[31:0]), .D1(do[63:32]), .R(1'b0), .S(1'b0) ); hpdmc_iddr32 iddr_dq( .Q0(di[31:0]), .Q1(di[63:32]), .C0(sys_clk), .C1(sys_clk_n), .CE(1'b1), .D(sdram_dq_in), .R(1'b0), .S(1'b0) ); /*******/ /* DQM */ /*******/ hpdmc_oddr4 oddr_dqm( .Q(sdram_dqm), .C0(sys_clk), .C1(sys_clk_n), .CE(1'b1), .D0(mo[7:4]), .D1(mo[3:0]), .R(1'b0), .S(1'b0) ); /*******/ /* DQS */ /*******/ wire [3:0] sdram_dqs_t; wire [3:0] sdram_dqs_out; hpdmc_obuft4 obuft_dqs( .T(sdram_dqs_t), .I(sdram_dqs_out), .O(sdram_dqs) ); hpdmc_oddr4 oddr_dqs_t( .Q(sdram_dqs_t), .C0(dqs_clk), .C1(dqs_clk_n), .CE(1'b1), .D0({4{~direction_r}}), .D1({4{~direction_r}}), .R(1'b0), .S(1'b0) ); hpdmc_oddr4 oddr_dqs( .Q(sdram_dqs_out), .C0(dqs_clk), .C1(dqs_clk_n), .CE(1'b1), .D0(4'hf), .D1(4'h0), .R(1'b0), .S(1'b0) ); endmodule
#include <bits/stdc++.h> using namespace std; int main() { int n, x, e_min = INT_MAX, e_max = INT_MIN; list<int> l; cin >> n; for (int i = 1; i <= n; ++i) { cin >> x; if (x < e_min) e_min = x; if (x > e_max) e_max = x; l.push_back(x); } l.remove_if( [e_min, e_max](int it) { return (it == e_min) || (it == e_max); }); cout << l.size(); }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_SYMBOL_V `define SKY130_FD_SC_HS__DLYMETAL6S4S_SYMBOL_V /** * dlymetal6s4s: 6-inverter delay with output from 4th inverter on * horizontal route. * * Verilog stub (without power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hs__dlymetal6s4s ( //# {{data|Data Signals}} input A, output X ); // Voltage supply signals supply1 VPWR; supply0 VGND; endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__DLYMETAL6S4S_SYMBOL_V
#include <bits/stdc++.h> using namespace std; struct hh { int num; int c; }; bool cmp(const hh p, const hh q) { return p.c < q.c; } int main() { int n, k; scanf( %d%d , &n, &k); hh a[1010], b[1010]; int i; int p = 0, q = 0; vector<int> ss[1010]; for (i = 0; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); if (y == 1) { a[p].num = i + 1; a[p++].c = x; } else { b[q].num = i + 1; b[q++].c = x; } } sort(a, a + p, cmp); sort(b, b + q, cmp); double ans = 0; if (p >= k) { for (i = 1; i < k; ++i) { ans += a[p - i].c * 1.0 / 2; ss[i].push_back(a[p - i].num); } if (q > 0) { if (a[0].c > b[0].c) { ans += b[0].c * 1.0 / 2; ans += a[0].c; } else { ans += a[0].c * 1.0 / 2; ans += b[0].c; } ss[k].push_back(b[0].num); } else ans += a[0].c * 1.0 / 2; ss[k].push_back(a[0].num); for (i = 1; i < q; ++i) { ss[k].push_back(b[i].num); ans += b[i].c; } for (i = p - k; i > 0; --i) { ss[k].push_back(a[i].num); ans += a[i].c; } } else { for (i = 1; i <= p; ++i) { ss[i].push_back(a[i - 1].num); ans += a[i - 1].c * 1.0 / 2; } int e = 0; for (i = p + 1; i <= k; ++i) { ss[i].push_back(b[e].num); ans += b[e++].c; } for (i = e; i < q; ++i) { ss[k].push_back(b[i].num); ans += b[i].c; } } printf( %.1f n , ans); int j; for (i = 1; i <= k; ++i) { printf( %d , ss[i].size()); for (j = 0; j < ss[i].size(); ++j) printf( %d , ss[i][j]); printf( n ); } return 0; }
`timescale 1ns / 1ps //********************************************************************** // File: spi_master.v // Module:spi_master // by Robin zhang //********************************************************************** module spi_master( clk,rst_n, spi_miso,spi_mosi,spi_clk, spi_tx_en,spi_rx_en,spi_over,mode_select_CPHA,mode_select_CPOL,receive_status ); input clk; input rst_n; input spi_miso; output spi_mosi; output spi_clk; input spi_tx_en; output spi_over; output receive_status; input spi_rx_en; input mode_select_CPHA; input mode_select_CPOL; reg[7:0] data_count; reg[7:0] recv_detect; reg[7:0] spi_tx_db; reg[4:0] cnt8; reg spi_clkr; reg spi_mosir; reg spi_mosir1; reg receive_status; reg[7:0] spi_rx_dbr; reg[7:0] spi_rx_dbr1; wire[7:0] spi_rx_db; wire[4:0] mode_reg; wire[4:0] start_reg; /*********************************************************************** *detect spi mode ***********************************************************************/ assign mode_reg = mode_select_CPHA ? 5'd18 : 5'd17; assign start_reg = mode_select_CPHA ? 5'd1 : 5'd0; /*********************************************************************** *control the spi timimg ***********************************************************************/ always @(posedge clk or negedge rst_n) begin if(!rst_n) begin cnt8 <= 5'd0; data_count <= 8'h0; spi_tx_db <= 8'h0; recv_detect <= 8'h0; end else if((spi_tx_en || spi_rx_en) && ((data_count < 8'd64) )) begin if(cnt8 < mode_reg) cnt8 <= cnt8+1'b1; else begin if(spi_tx_en && spi_rx_en && delay_flag == 1'b1) begin cnt8 <= 5'd0; data_count <= data_count + 1'b1; spi_tx_db <= spi_tx_db + 1'b1; recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect; end else begin if(spi_tx_en && delay_flag == 1'b1) begin cnt8 <= 5'd0; data_count <= data_count + 1'b1; spi_tx_db <= spi_tx_db + 1'b1; end else if(delay_flag == 1'b1)begin cnt8 <= 5'd0; data_count <= data_count + 1'b1; recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect; end end end end else begin cnt8 <= 5'd0; data_count <= data_count; end end /*********************************************************************** *generate spi clk ***********************************************************************/ always @(posedge clk or negedge rst_n) begin if(!rst_n) spi_clkr <= mode_select_CPOL ? 1'b1 : 1'b0; else if(cnt8 > start_reg && cnt8 < mode_reg) spi_clkr <= ~spi_clkr; else spi_clkr <= spi_clkr; end assign spi_clk = spi_clkr; /*********************************************************************** *spi master output data ***********************************************************************/ always @(posedge clk or negedge rst_n) begin if(!rst_n) spi_mosir <= 1'b1; else if(spi_tx_en) begin case(cnt8[4:1]) 4'd0: spi_mosir <= spi_tx_db[7]; 4'd1: spi_mosir <= spi_tx_db[6]; 4'd2: spi_mosir <= spi_tx_db[5]; 4'd3: spi_mosir <= spi_tx_db[4]; 4'd4: spi_mosir <= spi_tx_db[3]; 4'd5: spi_mosir <= spi_tx_db[2]; 4'd6: spi_mosir <= spi_tx_db[1]; 4'd7: spi_mosir <= spi_tx_db[0]; default: spi_mosir <= 1'b1; endcase end else spi_mosir <= 1'b1; end always @(posedge clk or negedge rst_n) begin if(!rst_n) spi_mosir1 <= 1'b1; else if(spi_tx_en) begin case(cnt8[4:1]) 4'd1: spi_mosir1 <= spi_tx_db[7]; 4'd2: spi_mosir1 <= spi_tx_db[6]; 4'd3: spi_mosir1 <= spi_tx_db[5]; 4'd4: spi_mosir1 <= spi_tx_db[4]; 4'd5: spi_mosir1 <= spi_tx_db[3]; 4'd6: spi_mosir1 <= spi_tx_db[2]; 4'd7: spi_mosir1 <= spi_tx_db[1]; 4'd8: spi_mosir1 <= spi_tx_db[0]; default: spi_mosir1 <= 1'b1; endcase end else spi_mosir1 <= 1'b1; end assign spi_mosi = mode_select_CPHA ? spi_mosir1 : spi_mosir; /*********************************************************************** *spi master input data ***********************************************************************/ always @(posedge clk or negedge rst_n) begin if(!rst_n) spi_rx_dbr <= 8'hff; else if(spi_rx_en) begin case(cnt8) 5'd1: spi_rx_dbr[7] <= spi_miso; 5'd3: spi_rx_dbr[6] <= spi_miso; 5'd5: spi_rx_dbr[5] <= spi_miso; 5'd7: spi_rx_dbr[4] <= spi_miso; 5'd9: spi_rx_dbr[3] <= spi_miso; 5'd11: spi_rx_dbr[2] <= spi_miso; 5'd13: spi_rx_dbr[1] <= spi_miso; 5'd15: spi_rx_dbr[0] <= spi_miso; default: spi_rx_dbr <= spi_rx_dbr; endcase end end always @(posedge clk or negedge rst_n) begin if(!rst_n) spi_rx_dbr1 <= 8'hff; else if(spi_rx_en) begin case(cnt8) 5'd3: spi_rx_dbr1[7] <= spi_miso; 5'd5: spi_rx_dbr1[6] <= spi_miso; 5'd7: spi_rx_dbr1[5] <= spi_miso; 5'd9: spi_rx_dbr1[4] <= spi_miso; 5'd11: spi_rx_dbr1[3] <= spi_miso; 5'd13: spi_rx_dbr1[2] <= spi_miso; 5'd15: spi_rx_dbr1[1] <= spi_miso; 5'd17: spi_rx_dbr1[0] <= spi_miso; default: spi_rx_dbr1 <= spi_rx_dbr1; endcase end end assign spi_rx_db = mode_select_CPHA ? spi_rx_dbr1 : spi_rx_dbr; assign spi_over = (data_count == 8'd64) ? 1'b1 :1'b0; always @(posedge clk or negedge rst_n) begin if(!rst_n) receive_status <= 1'b0; else receive_status <= (recv_detect == 8'd64) ? 1'b1 : 1'b0; end /*********************************************************************** *spi master delay ***********************************************************************/ reg delay_flag; reg [31:0] delay_cnt; always@(posedge clk or negedge rst_n)begin if(!rst_n)begin delay_flag <= 1'b1; delay_cnt <= 'h0; end else if(delay_cnt == 'hF && cnt8 == mode_reg)begin delay_cnt <= 'h0; delay_flag <= 1'b1; end else begin delay_cnt <= (cnt8 == mode_reg) ? (delay_cnt + 1'b1) : 'h0; delay_flag <= 1'b0; end end endmodule
#include <bits/stdc++.h> using namespace std; using ll = long long; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <class T> T rand(T a, T b) { return uniform_int_distribution<T>(a, b)(rng); } template <class T> T rand() { return uniform_int_distribution<T>()(rng); } const ll INF = (ll)1e18 + 7; const int N = 2 * (int)1e5; const int Q = 1e5; const int K = 100; const int D = 20; int col[N]; ll ans[4 * Q]; vector<pair<pair<int, int>, int>> itvs[4 * Q]; ll adjs[N][D][4]; void placeSegs( int i, int a, int b, const vector<pair<pair<int, int>, pair<pair<int, int>, int>>>& segs) { vector<pair<pair<int, int>, pair<pair<int, int>, int>>> ch; for (auto pr : segs) { if (pr.first.first <= a && b <= pr.first.second) { itvs[i].push_back(pr.second); } else if (a <= pr.first.second && pr.first.first <= b) { ch.push_back(pr); } } if (a != b) { int im = (a + b) >> 1; placeSegs(2 * i, a, im, ch); placeSegs(2 * i + 1, im + 1, b, ch); } } void recSolve(int i, int ia, int ib, ll zeros, ll ones) { for (auto pr : itvs[i]) { int a = pr.first.first; int b = pr.first.second; ll w = pr.second; if (col[a] == col[b]) { if (col[a] == 0) zeros = min(zeros, w); else ones = min(ones, w); } } if (ia == ib) ans[i] = min(ans[i], zeros + ones); else { int im = (ia + ib) >> 1; recSolve(2 * i, ia, im, zeros, ones); recSolve(2 * i + 1, im + 1, ib, zeros, ones); } } ll offerEdge(int i, ll w, int d, int ind) { if (adjs[i][d][3] != ind) { for (int si = (ind >> 1), sd = d - 1;; si >>= 1, --sd) { if (adjs[i][sd][3] == si) { for (int it = 0; it < 3; ++it) adjs[i][d][it] = adjs[i][sd][it]; break; } } adjs[i][d][3] = ind; } ll off = 0; for (int it = 0; it < 3; ++it) { if (w < adjs[i][d][it]) swap(w, adjs[i][d][it]); off += adjs[i][d][it]; } return off; } void solveAdjs(int i, int ia, int ib, int d, ll res) { for (auto pr : itvs[i]) { int a = pr.first.first; int b = pr.first.second; ll w = pr.second; res = min(res, offerEdge(a, w, d, i)); res = min(res, offerEdge(b, w, d, i)); } if (ia == ib) ans[i] = min(ans[i], res); else { int im = (ia + ib) >> 1; solveAdjs(2 * i, ia, im, d + 1, res); solveAdjs(2 * i + 1, im + 1, ib, d + 1, res); } } void solve() { int n, m; cin >> n >> m; vector<array<int, 4>> evs; for (int i = 0; i < m; ++i) { int a, b, w; cin >> a >> b >> w; if (a > b) swap(a, b); array<int, 4> ev; ev[0] = a - 1; ev[1] = b - 1; ev[2] = 0; ev[3] = w; evs.push_back(ev); } int q; cin >> q; for (int qi = 0; qi < q; ++qi) { int t; cin >> t; if (t == 0) { int a, b; cin >> a >> b; if (a > b) swap(a, b); array<int, 4> ev; ev[0] = a - 1; ev[1] = b - 1; ev[2] = qi + 1; ev[3] = -1; evs.push_back(ev); } else { int a, b, w; cin >> a >> b >> w; if (a > b) swap(a, b); array<int, 4> ev; ev[0] = a - 1; ev[1] = b - 1; ev[2] = qi + 1; ev[3] = w; evs.push_back(ev); } } sort(evs.begin(), evs.end()); vector<pair<pair<int, int>, pair<pair<int, int>, int>>> segs; for (int i = 0; i < evs.size(); ++i) { int a = evs[i][0]; int b = evs[i][1]; pair<pair<int, int>, int> ed = {{a, b}, evs[i][3]}; if (i + 1 >= evs.size() || evs[i + 1][0] != a || evs[i + 1][1] != b) { segs.emplace_back(make_pair(evs[i][2], q), ed); } else { segs.emplace_back(make_pair(evs[i][2], evs[i + 1][2] - 1), ed); ++i; } } int h = 1; while (h <= q) h *= 2; placeSegs(1, 0, h - 1, segs); for (int i = h; i <= h + q; ++i) ans[i] = INF; for (int j = 0; j < K; ++j) { for (int i = 0; i < n; ++i) col[i] = rand(0, 1); recSolve(1, 0, h - 1, INF, INF); } for (int i = 0; i < n; ++i) { adjs[i][0][0] = INF; adjs[i][0][1] = INF; adjs[i][0][2] = INF; adjs[i][0][3] = 0; } solveAdjs(1, 0, h - 1, 1, INF); for (int i = h; i <= h + q; ++i) cout << ans[i] << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); }
#include <bits/stdc++.h> using namespace std; long long int n; string s; vector<long long int> ss; inline bool check(long long int lim) { long long int sum = 0, cnt = 0; for (long long int i = 0; i < ss.size(); i++) { if (sum + ss[i] <= lim) { sum += ss[i]; } else { cnt++; sum = ss[i]; } } cnt++; if (cnt <= n) return true; return false; } int main() { cin >> n; cin.ignore(); getline(cin, s); long long int pos = 0; for (long long int i = 0; i < s.length(); i++) { if (s[i] == - || s[i] == ) { ss.push_back(i - pos + 1); pos = i + 1; } } ss.push_back(s.length() - pos); long long int low, high, mid; high = s.length(); low = -1; for (long long int i = 0; i < ss.size(); i++) low = max(low, ss[i]); long long int ans = high; while (low <= high) { mid = (low + high) / 2; if (check(mid)) { high = mid - 1; ans = min(ans, mid); } else low = mid + 1; } cout << ans; return 0; }
#include <bits/stdc++.h> using namespace std; const int N_MAX = 1005, M_MAX = 100005; struct union_find { int rank[N_MAX], parent[N_MAX]; union_find() { for (int i = 0; i < N_MAX; i++) { rank[i] = 0; parent[i] = i; } } int find(int x) { return x == parent[x] ? x : parent[x] = find(parent[x]); } bool join(int x, int y) { x = find(x); y = find(y); if (x == y) return false; if (rank[x] >= rank[y]) { parent[y] = x; if (rank[x] == rank[y]) rank[x]++; } else parent[x] = y; return true; } }; struct edge { int a, b; char who; }; int N, M, H; edge edges[M_MAX]; union_find S_UF, M_UF; int impossible() { puts( -1 ); return 0; } int main() { scanf( %d %d , &N, &M); if (N % 2 == 0) return impossible(); H = (N - 1) / 2; for (int i = 0; i < M; i++) { scanf( %d %d %c , &edges[i].a, &edges[i].b, &edges[i].who); edges[i].a--; edges[i].b--; } int S = 0; for (int i = 0; i < M; i++) if (edges[i].who == S ) if (S_UF.join(edges[i].a, edges[i].b)) S++; if (S < H) return impossible(); int components = N - S; vector<int> answer; for (int i = 0; i < M && (int)answer.size() < H - (components - 1); i++) if (edges[i].who == M ) if (S_UF.find(edges[i].a) == S_UF.find(edges[i].b)) if (M_UF.join(edges[i].a, edges[i].b)) answer.push_back(i); assert((int)answer.size() <= H - (components - 1)); if ((int)answer.size() != H - (components - 1)) return impossible(); for (int i = 0; i < M; i++) if (edges[i].who == M ) if (S_UF.join(edges[i].a, edges[i].b)) { assert(M_UF.join(edges[i].a, edges[i].b)); answer.push_back(i); } assert((int)answer.size() <= H); if ((int)answer.size() != H) return impossible(); for (int i = 0; i < M; i++) if (edges[i].who == S ) if (M_UF.join(edges[i].a, edges[i].b)) answer.push_back(i); assert((int)answer.size() == N - 1); printf( %d n , (int)answer.size()); for (int i = 0; i < (int)answer.size(); i++) printf( %d%c , answer[i] + 1, i < (int)answer.size() - 1 ? : n ); return 0; }
// *************************************************************************** // *************************************************************************** // Copyright 2013(c) Analog Devices, Inc. // Author: Lars-Peter Clausen <> // // All rights reserved. // // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in // the documentation and/or other materials provided with the // distribution. // - Neither the name of Analog Devices, Inc. nor the names of its // contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // - The use of this software may or may not infringe the patent rights // of one or more patent holders. This license does not release you // from the requirement that you obtain separate licenses from these // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. // // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** module dmac_src_fifo_inf ( input clk, input resetn, input enable, output enabled, input sync_id, output sync_id_ret, input [C_ID_WIDTH-1:0] request_id, output [C_ID_WIDTH-1:0] response_id, input eot, input en, input [C_DATA_WIDTH-1:0] din, output reg overflow, input sync, output xfer_req, input fifo_ready, output fifo_valid, output [C_DATA_WIDTH-1:0] fifo_data, input req_valid, output req_ready, input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input req_sync_transfer_start ); parameter C_ID_WIDTH = 3; parameter C_DATA_WIDTH = 64; parameter C_BEATS_PER_BURST_WIDTH = 4; wire ready; reg needs_sync = 1'b0; wire has_sync = ~needs_sync | sync; wire sync_valid = en & ready & has_sync; always @(posedge clk) begin if (resetn == 1'b0) begin needs_sync <= 1'b0; end else begin if (ready && en && sync) begin needs_sync <= 1'b0; end else if (req_valid && req_ready) begin needs_sync <= req_sync_transfer_start; end end end always @(posedge clk) begin if (resetn == 1'b0) begin overflow <= 1'b0; end else begin if (enable) begin overflow <= en & ~ready; end else begin overflow <= en; end end end assign sync_id_ret = sync_id; dmac_data_mover # ( .C_ID_WIDTH(C_ID_WIDTH), .C_DATA_WIDTH(C_DATA_WIDTH), .C_DISABLE_WAIT_FOR_ID(0), .C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH) ) i_data_mover ( .clk(clk), .resetn(resetn), .enable(enable), .enabled(enabled), .sync_id(sync_id), .xfer_req(xfer_req), .request_id(request_id), .response_id(response_id), .eot(eot), .req_valid(req_valid), .req_ready(req_ready), .req_last_burst_length(req_last_burst_length), .s_axi_ready(ready), .s_axi_valid(sync_valid), .s_axi_data(din), .m_axi_ready(fifo_ready), .m_axi_valid(fifo_valid), .m_axi_data(fifo_data), .m_axi_last() ); endmodule
#include <bits/stdc++.h> using namespace std; int n, t, a[110]; int main() { scanf( %d%d , &n, &t); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= n; i++) { t = t - 86400 + a[i]; if (t <= 0) { printf( %d , i); break; } } return 0; }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__NAND2_SYMBOL_V `define SKY130_FD_SC_LP__NAND2_SYMBOL_V /** * nand2: 2-input NAND. * * Verilog stub (without power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__nand2 ( //# {{data|Data Signals}} input A, input B, output Y ); // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__NAND2_SYMBOL_V
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; long long cal(long long x) { return (x + 1) * x / 2; } int main() { std::ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n; cin >> n; long long l = 0, r = 1e8, ans = -1; while (l <= r) { long long mid = (l + r) >> 1; if (cal(mid) < n) l = mid + 1, ans = mid; else r = mid - 1; } cout << n - cal(ans) << n ; return 0; }
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a; int sum = 0; for (int i = 0; i < n; i++) { cin >> a; sum += a; } cout << (sum % n == 0 ? n : n - 1) << endl; return 0; }
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n; long long A[N]; map<long long, long long> MP; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &A[i]); MP.insert({A[1] - 1, 0}); for (int i = 2; i <= n; i++) { long long B = -1; while (MP.rbegin()->first >= A[i]) { long long a = MP.rbegin()->first; long long b = MP.rbegin()->second; MP[a % A[i]] = max(MP[a % A[i]], b + a / A[i] * A[i] * (i - 1)); B = max(B, b + (a / A[i] - 1) * A[i] * (i - 1)); MP.erase(a); } if (B >= 0) MP[A[i] - 1] = max(MP[A[i] - 1], B); } long long MX = 0; for (auto X : MP) MX = max(MX, X.first * n + X.second); return !printf( %lld n , MX); }
//Integer to IEEE Floating Point Converter (Single Precision) //Copyright (C) Jonathan P Dawson 2013 //2013-12-12 module int_to_float( input_a, input_a_stb, output_z_ack, clk, rst, output_z, output_z_stb, input_a_ack); input clk; input rst; input [31:0] input_a; input input_a_stb; output input_a_ack; output [31:0] output_z; output output_z_stb; input output_z_ack; reg s_output_z_stb; reg [31:0] s_output_z; reg s_input_a_ack; reg s_input_b_ack; reg [2:0] state; parameter get_a = 3'd0, convert_0 = 3'd1, convert_1 = 3'd2, convert_2 = 3'd3, round = 3'd4, pack = 3'd5, put_z = 3'd6; reg [31:0] a, z, value; reg [23:0] z_m; reg [7:0] z_r; reg [7:0] z_e; reg z_s; reg guard, round_bit, sticky; always @(posedge clk) begin case(state) get_a: begin s_input_a_ack <= 1; if (s_input_a_ack && input_a_stb) begin a <= input_a; s_input_a_ack <= 0; state <= convert_0; end end convert_0: begin if ( a == 0 ) begin z_s <= 0; z_m <= 0; z_e <= -127; state <= pack; end else begin value <= a[31] ? -a : a; z_s <= a[31]; state <= convert_1; end end convert_1: begin z_e <= 31; z_m <= value[31:8]; z_r <= value[7:0]; state <= convert_2; end convert_2: begin if (!z_m[23]) begin z_e <= z_e - 1; z_m <= z_m << 1; z_m[0] <= z_r[7]; z_r <= z_r << 1; end else begin guard <= z_r[7]; round_bit <= z_r[6]; sticky <= z_r[5:0] != 0; state <= round; end end round: begin if (guard && (round_bit || sticky || z_m[0])) begin z_m <= z_m + 1; if (z_m == 24'hffffff) begin z_e <=z_e + 1; end end state <= pack; end pack: begin z[22 : 0] <= z_m[22:0]; z[30 : 23] <= z_e + 127; z[31] <= z_s; state <= put_z; end put_z: begin s_output_z_stb <= 1; s_output_z <= z; if (s_output_z_stb && output_z_ack) begin s_output_z_stb <= 0; state <= get_a; end end endcase if (rst == 1) begin state <= get_a; s_input_a_ack <= 0; s_output_z_stb <= 0; end end assign input_a_ack = s_input_a_ack; assign output_z_stb = s_output_z_stb; assign output_z = s_output_z; endmodule
// This tests SystemVerilog casting support // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // Extended by Maciej Suminski // Copied and modified by Martin Whitaker // Copied and modified again by Lars-Peter Clausen module test(); typedef logic [7:0] pa08; typedef pa08 [1:0] pa16; typedef pa16 [1:0] pa32; typedef pa32 [1:0] pa64; // variables used in casting pa08 var_08; pa16 var_16; pa32 var_32; pa64 var_64; real var_real; // error counter bit err = 0; initial begin var_08 = pa08'(4'h5); if (var_08 !== 8'h05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end var_16 = pa16'(var_08); if (var_16 !== 16'h05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end var_32 = pa32'(var_16); if (var_32 !== 32'h05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end var_64 = pa64'(var_32); if (var_64 !== 64'h05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end var_real = 13.4; var_08 = pa08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end var_real = 14.5; var_16 = pa16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end var_real = 15.6; var_32 = pa32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end var_real = -15.6; var_64 = pa64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end var_08 = pa08'(4'hf); if (var_08 !== 8'h0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end var_16 = pa08'(16'h0f0f); if (var_16 !== 16'h0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end if (!err) $display("PASSED"); end endmodule // test
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int inf = (int)1e9; struct vert { int to, z, num; }; struct ans { int x, y, z; }; const int N = (int)(1e5) + 5; int n, m; vector<vert> g[N]; vector<int> d(N, inf); vector<int> dp(N, inf); vector<int> pr(N, -1); vector<bool> road(N); void go() { queue<int> q; q.push(0); d[0] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].to; if (d[to] == inf) { d[to] = d[v] + 1; q.push(to); } } } } void getAns() { queue<int> q; q.push(n - 1); dp[n - 1] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].to; int z = 1 - g[v][i].z; if (d[to] + 1 == d[v]) { if (dp[to] > dp[v] + z) { dp[to] = dp[v] + z; pr[to] = v; } q.push(to); } } } } int main() { cin >> n >> m; vert p; int kol = 0; for (int i = 0; i < m; ++i) { int x, y, z; scanf( %d %d %d , &x, &y, &z); --x; --y; p.z = z; p.num = i; if (z == 0) { ++kol; } p.to = y; g[x].push_back(p); p.to = x; g[y].push_back(p); } go(); getAns(); vector<ans> out; ans a; int v = 0; for (int to = pr[0]; to != -1; to = pr[to]) { vert now; for (int k = 0; k < g[v].size(); ++k) { if (g[v][k].to == to) { now = g[v][k]; break; } } road[now.num] = true; if (now.z == 0) { a.x = v + 1; a.y = to + 1; a.z = 1; out.push_back(a); } v = to; } for (int i = 0; i < n; ++i) { for (int j = 0; j < (int)g[i].size(); ++j) { if (road[g[i][j].num]) { continue; } if (g[i][j].z == 1) { a.x = i + 1; a.y = g[i][j].to + 1; a.z = 0; road[g[i][j].num] = true; out.push_back(a); } } } cout << out.size() << n ; for (int i = 0; i < out.size(); ++i) { cout << out[i].x << << out[i].y << << out[i].z << n ; } return 0; }
#include <bits/stdc++.h> using namespace std; int nx[1000514 * 2][26], spt; int fl[1000514 * 2], ll[1000514 * 2], lp[1000514 * 2]; int newnode() { memset(nx[spt], 0, sizeof(nx[spt])); fl[spt] = ll[spt] = lp[spt] = 0; return spt++; } void add(int root, int& last, char A) { int a = A - a ; int p = last; int np = last = newnode(); ll[np] = ll[p] + 1; lp[np] = 0; for (; p && nx[p][a] == 0; p = fl[p]) nx[p][a] = np; int q = nx[p][a]; if (p == 0) fl[np] = root; else if (ll[q] == ll[p] + 1) fl[np] = q; else { int nq = spt++; memcpy(nx[nq], nx[q], sizeof(nx[q])); fl[nq] = fl[q]; ll[nq] = ll[p] + 1; lp[nq] = lp[q] + ll[q] - 1 - ll[p]; fl[q] = fl[np] = nq; for (; p && nx[p][a] == q; p = fl[p]) nx[p][a] = nq; } } char s[1000514], r[1000514 * 2]; vector<int> bk[1000514]; int dp[1000514 * 2]; int vs[1000514 * 2], vt; void make_z(int* z, char* s, int l) { int j = z[0] = 0; for (int i = 1; i < l; i++) { z[i] = (i > j + z[j] - 1) ? 0 : min(z[i - j], j + z[j] - i); for (; i + z[i] < l && s[z[i]] == s[i + z[i]]; z[i]++) ; if (i + z[i] > j + z[j]) j = i; } } int z[1000514 * 2]; void sol() { spt = 1; int last; int root = last = newnode(); int sl = 0; for (; s[sl]; sl++) ; for (int i = 0; i < sl; i++) add(root, last, s[i]); for (int i = 1; i < spt; i++) { bk[ll[i]].push_back(i); } for (int p = last; p; p = fl[p]) { dp[p] = 1; } for (int i = sl; i >= 0; i--) { int sz = (int)bk[i].size(); for (int j = 0; j < sz; j++) { int w = bk[i][j]; for (int k = 0; k < 26; k++) { int t = nx[w][k]; if (t) dp[w] += dp[t]; } } } int Q; scanf( %d , &Q); for (int T = 0; T < Q; T++) { scanf( %s , r); int rl = 0; for (; r[rl]; rl++) ; for (int i = 0; i < rl; i++) r[rl + i] = r[i]; r[rl + rl] = 0; make_z(z, r, rl * 2); int t = 0; for (int i = 1; i <= rl; i++) { if (rl % i) continue; int flag = 0; for (int j = i; j < rl; j += i) { if (z[j] < rl / i) { flag = 1; } } if (flag) continue; t = i; break; } int p = root; int l = 0; for (int i = 0; i < rl; i++) { int a = r[i] - a ; for (; p && nx[p][a] == 0; p = fl[p]) ; if (p == 0) { l = 0; p = root; } else { l = min(l, ll[p]) + 1; p = nx[p][a]; } } vt++; int ans = 0; if (l >= rl && vs[p] != vt) { vs[p] = vt; ans += dp[p]; } for (int i = 0; i < rl - 1; i++) { int a = r[i] - a ; for (; p && nx[p][a] == 0; p = fl[p]) ; if (p == 0) { l = 0; p = root; } else { l = min(l, ll[p]) + 1; p = nx[p][a]; } for (; p && ll[fl[p]] >= rl; p = fl[p]) ; l = min(l, ll[p]); if (l >= rl && vs[p] != vt) { vs[p] = vt; ans += dp[p]; } } printf( %d n , (int)ans); } } int main() { scanf( %s , s); sol(); }
#include <bits/stdc++.h> using namespace std; string s; char zh[125], ch, sw; int n, m; int main() { cin >> n >> m >> s; for (int i = 97; i <= 122; i += 1) { zh[i] = i; } for (int i = 1; i <= m; i += 1) { cin >> ch >> sw; for (int j = 97; j <= 122; j += 1) { if (zh[j] == ch) { zh[j] = sw; } else { if (zh[j] == sw) { zh[j] = ch; } } } } for (int i = 0; i <= n - 1; i += 1) { cout << zh[s[i]]; } return 0; }
#include <bits/stdc++.h> using namespace std; void _dbg(string) { cout << endl; } template <class H, class... T> void _dbg(string s, H h, T... t) { int l = s.find( , ); cout << s.substr(0, l) << = << h << , ; _dbg(s.substr(l + 1), t...); } template <class T, class U> ostream& operator<<(ostream& o, const pair<T, U>& p) { o << ( << p.first << , << p.second << ) ; return o; } template <class T> ostream& operator<<(ostream& o, const vector<T>& v) { o << [ ; for (T t : v) { o << t << , ; } o << ] ; return o; } const int N = 100000; int n, m; bool used[N + 5]; char s[N + 5]; int hoge(char c) { int crnt = 0; int last = -1; int ret = 0; for (int i = (int)(0); i < (int)(n); i++) { crnt++; if (s[i] == c) last = i; if (used[i]) crnt = 0; if (crnt == m) { if (i - last >= m) return -1; crnt = i - last; used[last] = true; ret++; } } return ret; } int main() { cin >> m >> s; n = strlen(s); for (int i = (int)(0); i < (int)(26); i++) { char c = i + a ; int r = hoge(c); if (r == -1) { r = 0; for (int j = (int)(0); j < (int)(n); j++) if (s[j] == c) { r++; used[j] = true; } } else { i = 100; } for (int j = (int)(0); j < (int)(r); j++) printf( %c , c); } cout << endl; return 0; }
#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; if (n == 1) cout << -1 ; else cout << n << << n + 1 << << n * n + n; return 0; }
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long N = 1e5 + 1; const long long mod = 1e9 + 7; const long double eps = 1E-7; vector<int> a[N]; int n, k, x, ans; int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= k; i++) cin >> x, a[x].push_back(i); for (int i = 1; i <= n; i++) { if (a[i].size() == 0) ans += 1 + (i != 1) + (i != n); else { x = a[i][0]; if (i != 1) if (upper_bound(a[i - 1].begin(), a[i - 1].end(), x) == a[i - 1].end()) ans++; if (i != n) if (upper_bound(a[i + 1].begin(), a[i + 1].end(), x) == a[i + 1].end()) ans++; } } cout << ans << endl; }
module bit_reversal #(parameter dat_w=5) ( input wire [dat_w-1:0] dat_i, input wire [2:0] bitrev, output reg [dat_w-1:0] dat_o); integer i; always@* begin dat_o = dat_i; //Always keep LSB casex(bitrev) 3'b000: //Reverse 6 bits (keep LSB) for(i=1;i<7;i=i+1) dat_o[i] = dat_i[7-i]; 3'b001: //Reverse 7 bits (keep LSB) for(i=1;i<8;i=i+1) dat_o[i] = dat_i[8-i]; 3'b010: //Reverse 8 bits (keep LSB) for(i=1;i<9;i=i+1) dat_o[i] = dat_i[9-i]; 3'b011: //Reverse 9 bits (keep LSB) for(i=1;i<10;i=i+1) dat_o[i] = dat_i[10-i]; 3'b100: //Reverse 10 bits (keep LSB) for(i=1;i<11;i=i+1) dat_o[i] = dat_i[11-i]; 3'b101: //Reverse 11 bits (keep LSB) for(i=1;i<12;i=i+1) dat_o[i] = dat_i[12-i]; 3'b110: //Reverse 12 bits (keep LSB) for(i=1;i<13;i=i+1) dat_o[i] = dat_i[13-i]; 3'b111: //Reverse 13 bits (keep LSB) for(i=1;i<14;i=i+1) dat_o[i] = dat_i[14-i]; endcase end endmodule // bit_reversal
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V `define SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V /** * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage, * isolated well on input buffer, double height cell. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_hvl__lsbuflv2hv ( X, A ); // Module ports output X; input A; // Name Output Other arguments buf buf0 (X , A ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, i, j, k, x, MOD = 1000000007, ans, a1, a2, b1, b2, a, b; string s1, s2; cin >> n >> s1 >> s2; vector<vector<long long>> dp(n + 1, vector<long long>(4, 0)); dp[0][0] = 1; for (i = 0; i < n; i++) { for (j = 0; j < 4; j++) { if (s1[i] == ? ) a1 = 0, a2 = 9; else a1 = s1[i] - 0 , a2 = a1; if (s2[i] == ? ) b1 = 0, b2 = 9; else b1 = s2[i] - 0 , b2 = b1; for (a = a1; a <= a2; a++) { for (b = b1; b <= b2; b++) { x = j; if (a < b) x |= 1; else if (a > b) x |= 2; dp[i + 1][x] = (dp[i + 1][x] + dp[i][j]) % MOD; } } } } ans = dp[n][3]; cout << ans << n ; return 0; }
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); double l, x, v1, v2, k; cin >> l >> x >> v1 >> v2 >> k; double n = ceil(l / k); double t2, t1; t2 = x / (v2 * (n * ((v1 + v2) / (v2 - v1)) - (n - 1))); t1 = t2 * (v1 + v2) / (v2 - v1); double odp = t1 * n + t2 * (n - 1); cout << setprecision(8) << odp; }
#include <bits/stdc++.h> using namespace std; const int i32INF = 1 << 30; const long long i64INF = 1LL << 60; const double mINF = 1e100; const double EPS = 1e-9; int nextint() { int a; scanf( %d , &a); return a; } int n; vector<int> v; int difs[23][23]; bool isGood[1 << 23]; bool solveIsGood(int mask) { int id = n; while ((mask & (1 << (id - 1))) == 0) id--; for (int i = 0; i < n; i++) if (mask & (1 << i) && mask & difs[id][i]) return true; return false; } int dp[1 << 23]; int main() { n = nextint(); v.resize(n); for (int i = 0; i < n; i++) v[i] = nextint(); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (i != j) for (int k = 0; k < n; k++) if (v[i] - v[j] == v[k]) difs[i][j] |= (1 << k); isGood[0] = 1; for (int mask = 1; mask < (1 << (n - 1)); mask++) isGood[mask] = solveIsGood(mask); fill(dp, dp + (1 << n), 1024); dp[1] = 1; for (int i = 1; i < n; i++) { for (int j = 0; j < (1 << (i - 1)); j++) { int jj = j | (1 << (i - 1)); if (isGood[jj]) { int cr = dp[jj]; jj |= 1 << i; dp[jj] = min(dp[jj], cr + 1); for (int k = 0; k < i; k++) if (jj & (1 << k)) dp[jj & (~(1 << k))] = min(dp[jj & (~(1 << k))], cr); } } } int res = 1024; for (int mask = 0; mask < (1 << (n - 1)); mask++) res = min(res, dp[mask | (1 << (n - 1))]); if (res == 1024) res = -1; cout << res << endl; return 0; }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__A32O_2_V `define SKY130_FD_SC_LP__A32O_2_V /** * a32o: 3-input AND into first input, and 2-input AND into * 2nd input of 2-input OR. * * X = ((A1 & A2 & A3) | (B1 & B2)) * * Verilog wrapper for a32o with size of 2 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_lp__a32o.v" `ifdef USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_lp__a32o_2 ( X , A1 , A2 , A3 , B1 , B2 , VPWR, VGND, VPB , VNB ); output X ; input A1 ; input A2 ; input A3 ; input B1 ; input B2 ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_lp__a32o base ( .X(X), .A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*********************************************************/ `else // If not USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_lp__a32o_2 ( X , A1, A2, A3, B1, B2 ); output X ; input A1; input A2; input A3; input B1; input B2; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_lp__a32o base ( .X(X), .A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2) ); endmodule `endcelldefine /*********************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_LP__A32O_2_V
#include <bits/stdc++.h> using namespace std; long long int n; map<pair<long long int, long long int>, long long int> val; long long int get_lca(long long int x, long long int y) { vector<long long int> a, b; a.clear(); b.clear(); while (x > 0) { a.push_back(x); x >>= 1; } while (y > 0) { b.push_back(y); y >>= 1; } reverse(a.begin(), a.end()); reverse(b.begin(), b.end()); long long int j = 0; for (j = 0; j < a.size() && j < b.size(); j++) { if (a[j] != b[j]) break; } return a[j - 1]; } void upd(long long int x, long long int l, long long int w) { long long int y = x % 2; x >>= 1; while (x > 0) { val[{x, y}] += w; y = x % 2; x >>= 1; } y = l % 2; l >>= 1; while (l > 0) { val[{l, y}] -= w; y = l % 2; l >>= 1; } } long long int get(long long int x, long long int l) { long long int an = 0; long long int y = x % 2; x >>= 1; while (x > 0 && x >= l) { an += val[{x, y}]; y = x % 2; x >>= 1; } return an; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { long long int t, u, v, w; cin >> t >> u >> v; if (t == 1) { cin >> w; long long int l = get_lca(u, v); upd(u, l, w); upd(v, l, w); } else { long long int l = get_lca(u, v); long long int an = get(u, l) + get(v, l); cout << an << n ; } } return 0; }
module FpuFpF_Add( /* verilator lint_off UNUSED */ clk, isen, doSub, srca, srcb, dst ); input clk; input isen; input doSub; input[31:0] srca; input[31:0] srcb; output[31:0] dst; reg sgna; reg sgnb; reg sgnc; reg[9:0] exa; reg[9:0] exb; reg[9:0] exc; reg[9:0] exm; reg[31:0] tFracA; reg[31:0] tFracB; reg[31:0] tFracC; // reg[22:0] tFracC; reg[31:0] tFracA1; reg[31:0] tFracB1; reg[31:0] tFracC1; // reg[31:0] tFracA2; // reg[31:0] tFracB2; reg[31:0] tFracC2; reg[31:0] tFracC2_A; //16 reg[31:0] tFracC2_B; //8 reg[31:0] tFracC2_C; //4 reg[31:0] tFracC2_D; //2 reg[9:0] tExc_A; reg[9:0] tExc_B; reg[9:0] tExc_C; reg[9:0] tExc_D; always @ (clk) begin sgna=srca[31]; sgnb=srcb[31]; exa[7:0]=srca[30:23]; exb[7:0]=srcb[30:23]; exa[9:8]=0; exb[9:8]=0; exm=(exa>=exb)?exa:exb; if(sgna) begin tFracA[31:23]=~(9'h1); tFracA[22:0]=~(srca[22:0]); end else begin tFracA[31:23]=9'h1; tFracA[22:0]=srca[22:0]; end if(sgnb^doSub) begin tFracB[31:23]=~(9'h1); tFracB[22:0]=~(srcb[22:0]); end else begin tFracB[31:23]=9'h1; tFracB[22:0]=srcb[22:0]; end tFracA1=tFracA>>>(exm-exa); tFracB1=tFracB>>>(exm-exb); tFracC1=tFracA1+tFracB1; if(tFracC1[31]) begin sgnc=1; tFracC2=~tFracC1; end else begin sgnc=0; tFracC2=tFracC1; end if(tFracC2[23:0]==0) begin sgnc=0; tFracC=0; exc=0; end else if(tFracC2[24:23]==0) begin if(tFracC2[23:8]==0) begin tFracC2_A=tFracC2<<16; tExc_A=exm-16; end else begin tFracC2_A=tFracC2; tExc_A=exm; end if(tFracC2_A[23:16]==0) begin tFracC2_B=tFracC2_A<<8; tExc_B=tExc_A-8; end else begin tFracC2_B=tFracC2_A; tExc_B=tExc_A; end if(tFracC2_B[23:20]==0) begin tFracC2_C=tFracC2_B<<4; tExc_C=tExc_B-4; end else begin tFracC2_C=tFracC2_B; tExc_C=tExc_B; end if(tFracC2_C[23:22]==0) begin tFracC2_D=tFracC2_C<<2; tExc_D=tExc_C-2; end else begin tFracC2_D=tFracC2_C; tExc_D=tExc_C; end if(tFracC2_D[23]==0) begin tFracC=tFracC2_D<<1; exc=tExc_D-1; end else begin tFracC=tFracC2_D; exc=tExc_D; end end else begin if(tFracC2[24]) begin tFracC=tFracC2>>1; exc=exm+1; end else begin tFracC=tFracC2; exc=exm; end end if(exc[9]) begin dst[31:0]=32'h0; end else if(exc[8]) begin dst[31]=sgnc; dst[30:0]=31'h7F80_0000; end else begin dst[31]=sgnc; dst[30:23]=exc[7:0]; dst[22:0]=tFracC[22:0]; end end endmodule
#include <iostream> using namespace std; int main() { int n,q, l,r; cin>>n>>q; string s; cin>>s; int arr[n]; arr[0]=s[0]- a +1; for(int i=1;i<n;i++){ arr[i]=arr[i-1]+s[i]- a +1; } while(q--){ cin>>l>>r; cout<<(arr[r-1]-((l==1)?0:arr[l-2]))<< n ; } return 0; }
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_PP_V `define SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_PP_V /** * nor4: 4-input NOR. * * Y = !(A | B | C | D) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_hdll__nor4 ( Y , A , B , C , D , VPWR, VGND, VPB , VNB ); // Module ports output Y ; input A ; input B ; input C ; input D ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire nor0_out_Y ; wire pwrgood_pp0_out_Y; // Name Output Other arguments nor nor0 (nor0_out_Y , A, B, C, D ); sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND); buf buf0 (Y , pwrgood_pp0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_PP_V
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k, x, s = 0; cin >> n >> k; map<long long, long long> m; queue<long long> q; for (long long i = 0; 0 < n ? i < n : i > n; 0 < n ? i += 1 : i -= 1) { cin >> x; q.push(x); m[x] = 0; } while (1) { x = q.front(); q.pop(); if (!m.count(x + 1)) { q.push(x + 1); m[x + 1] = m[x] + 1; } if (m.size() >= n + k) break; if (!m.count(x - 1)) { q.push(x - 1); m[x - 1] = m[x] + 1; } if (m.size() >= n + k) break; } for (auto i : m) s += i.second; cout << s << n ; for (auto i : m) if (i.second != 0) cout << i.first << ; }
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = (int)1e5 + 5; int _ = 1; int n, q; int a[N], pos[N]; int nex[N], blo; int calc(int x) { for (int i = 1; i <= blo; i++) x = a[x]; return x; } void work() { scanf( %d%d , &n, &q); blo = sqrt(n) + 1; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) pos[a[i]] = i; for (int i = 1; i <= n; i++) nex[i] = calc(i); while (q--) { int op; scanf( %d , &op); if (op == 1) { int x, y; scanf( %d%d , &x, &y); swap(pos[a[x]], pos[a[y]]); swap(a[x], a[y]); nex[x] = calc(x); nex[y] = calc(y); for (int i = 1; i <= blo; i++) { x = pos[x]; y = pos[y]; } int ex = calc(x), ey = calc(y); for (int i = 1; i <= blo; i++) { nex[x] = ex; nex[y] = ey; x = a[x]; y = a[y]; ex = a[ex]; ey = a[ey]; } } else { int x, y; scanf( %d%d , &x, &y); while (y >= blo) { x = nex[x]; y -= blo; } while (y) { x = a[x]; y--; } printf( %d n , x); } } } int main() { while (_--) { work(); } return 0; }
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LS__O21AI_FUNCTIONAL_PP_V `define SKY130_FD_SC_LS__O21AI_FUNCTIONAL_PP_V /** * o21ai: 2-input OR into first input of 2-input NAND. * * Y = !((A1 | A2) & B1) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_ls__o21ai ( Y , A1 , A2 , B1 , VPWR, VGND, VPB , VNB ); // Module ports output Y ; input A1 ; input A2 ; input B1 ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire or0_out ; wire nand0_out_Y ; wire pwrgood_pp0_out_Y; // Name Output Other arguments or or0 (or0_out , A2, A1 ); nand nand0 (nand0_out_Y , B1, or0_out ); sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND); buf buf0 (Y , pwrgood_pp0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LS__O21AI_FUNCTIONAL_PP_V
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int i = 0; i < q; i++) { int n; cin >> n; int ans = 0; int ct_4 = n / 4; int rem = n % 4; if (rem == 1) { ct_4 -= 2; ans = ct_4 + 1; } else if (rem == 2) { ct_4 -= 1; ans = ct_4 + 1; } else if (rem == 3) { ct_4 -= 3; ans = ct_4 + 2; } else { ans = ct_4; } if (ct_4 < 0) { cout << -1 << endl; } else { cout << ans << endl; } } return 0; }
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T a) { return a * a; } int n; int a[21000]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int best = -1000000000; for (int i = 3; i <= n; i++) if (n % i == 0) { int g = n / i; for (int j = 0; j < g; j++) { int cur = 0; for (int k = j; k < n; k += g) cur += a[k]; best = max(cur, best); } } cout << best; return 0; }
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; char ch = getchar(), flag = 0; while ((ch > 9 || ch < 0 ) && ch != - ) ch = getchar(); if (ch == - ) flag = 1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); if (flag) x = -x; } inline void read(int &x, int &y) { read(x), read(y); } inline void read(int &x, int &y, int &z) { read(x), read(y), read(z); } const int N = 20005, inf = 1e9 + 7, mod = 20000; int n, m, up[N], cup[N], cnt, si[N], num[N], dep[N], use[N]; vector<int> g[N], f[N], s[N]; bool vis[N]; struct node { int to, next, v; } p[N << 4]; int S, T, head[N], st[N], tot, ans; inline void add(int x, int y, int z) { p[tot].to = y; p[tot].next = head[x]; p[tot].v = z; head[x] = tot++; p[tot].to = x; p[tot].next = head[y]; p[tot].v = 0; head[y] = tot++; } queue<int> q; inline bool bfs(int x) { memset(st, 0, sizeof(st)); st[x] = 1; q.push(x); while (!q.empty()) { int x = q.front(); q.pop(); for (int i = head[x]; ~i; i = p[i].next) { int y = p[i].to, v = p[i].v; if (!v || st[y]) continue; st[y] = st[x] + 1; q.push(y); } } return st[T] > 0; } inline int dfs(int x, int f) { int r = 0; if (x == T) return f; for (int i = head[x]; ~i; i = p[i].next) { int y = p[i].to, v = p[i].v, tmp; if (!v || st[y] != st[x] + 1) continue; tmp = dfs(y, min(f - r, v)); r += tmp; p[i].v -= tmp; p[i ^ 1].v += tmp; if (r == f) break; } if (!r) st[x] = -1; return r; } inline void dinic() { int t; while (bfs(S)) while (t = dfs(S, inf)) ans += t; printf( %d n , ans); } inline void Add(int x, int y, int z) { g[x].push_back(y); f[x].push_back(z); g[y].push_back(x); f[y].push_back(z); vis[x] = vis[y] = 1; } inline void Dfs(int x, int fa) { vis[x] = 1; for (int i = 0; i < g[x].size(); i++) { int y = g[x][i], z = f[x][i]; if (y == fa) continue; if (vis[y] && dep[y] < dep[x]) { cnt++; s[cnt].push_back(z); si[z]--; int k = x, o = 0; while (k != y) { si[cup[k]]--; s[cnt].push_back(cup[k]); k = up[k]; } continue; } if (vis[y]) continue; cup[y] = z; up[y] = x; dep[y] = dep[x] + 1; Dfs(y, x); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); Add(x, y, z); si[z]++; use[z]++; } for (int i = 1; i <= n; i++) if (vis[i]) { memset(vis, 0, sizeof(vis)); Dfs(i, -1); break; } memset(head, -1, sizeof(head)); S = 0; T = cnt + 1; for (int i = 1; i <= m; i++) if (!si[i] && use[i]) T++; else if (use[i]) ans++; int CNT = cnt; for (int i = 1; i <= m; i++) if (!si[i] && use[i]) add(num[i] = ++CNT, T, 1); for (int i = 1; i <= cnt; i++) { bool isok = 1; for (int j = 0; j < s[i].size(); j++) if (si[s[i][j]]) isok = 0; add(S, i, s[i].size() - 1); for (int j = 0; j < s[i].size(); j++) if (num[s[i][j]]) add(i, num[s[i][j]], 1); } dinic(); return 0; }
#include<bits/stdc++.h> using namespace std; #define INF 1234567890 #define ll long long int T; int N, K; int A[200201]; int main() { //ios::sync_with_stdio(0); cin.tie(0); scanf( %d , &T); while(T--) { scanf( %d %d , &N, &K); for(int i=1; i<=N; i++) { if (i <= K) A[i] = i; else A[i] = K-(i-K); } // for(int i=1; i<=N; i++) // printf( %d , A[i]); // printf( n ); int cnt = A[N]-1; // prefix for(int i=1; i<=cnt; i++) printf( %d , i); for(int i=cnt+1; i<=K; i++) printf( %d , cnt+1+K-i); printf( n ); } return 0; }
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_V `define SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_V /** * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted * clock, complementary outputs. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import sub cells. `include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v" `include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v" `celldefine module sky130_fd_sc_hs__sdfbbp ( Q , Q_N , D , SCD , SCE , CLK , SET_B , RESET_B, VPWR , VGND ); // Module ports output Q ; output Q_N ; input D ; input SCD ; input SCE ; input CLK ; input SET_B ; input RESET_B; input VPWR ; input VGND ; // Local signals wire RESET ; wire SET ; wire buf_Q ; wire mux_out; // Delay Name Output Other arguments not not0 (RESET , RESET_B ); not not1 (SET , SET_B ); sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE ); sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, mux_out, VPWR, VGND); buf buf0 (Q , buf_Q ); not not2 (Q_N , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_V
#include <bits/stdc++.h> using namespace std; long long int n, k, a, b; vector<long long int> arr; long long int rec(long long int l, long long int r) { long long int i = lower_bound(arr.begin(), arr.end(), l) - arr.begin(); long long int j = upper_bound(arr.begin(), arr.end(), r) - arr.begin(); long long int x = j - i; long long int val; if (x == 0) { val = a; } else { val = b * x * (r - l + 1); } if (l == r || x == 0) { return val; } long long int mid = (l + r) / 2; return min(val, rec(l, mid) + rec(mid + 1, r)); } int main() { cin >> n >> k >> a >> b; for (int i = 0; i < k; i++) { int x; cin >> x; arr.push_back(x); } sort(arr.begin(), arr.end()); long long int start = 1; long long int end = pow(2, n); cout << rec(start, end) << endl; }
#include <bits/stdc++.h> using namespace std; int fr[200004]; struct cmp { bool operator()(int a, int b) const { return a > b; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; auto make = [](vector<int>& a, int pos) { swap(a[pos + 2], a[pos + 1]); swap(a[pos + 1], a[pos]); }; int t; cin >> t; while (t--) { int n, i, j, k, l; cin >> n; vector<int> v(n); vector<pair<int, int>> p(n); for (i = 0; i < n; i++) { cin >> v[i]; p[i] = {v[i], i}; } sort(p.begin(), p.end()); for (i = 0; i < n; i++) v[p[i].second] = i; int cnt = 0; for (i = 0; i < n - 1; i++) { for (j = i + 1; j < n; j++) if (v[j] < v[i]) cnt++; } if (cnt & 1) { for (i = 0; i < n - 1; i++) if (p[i].first == p[i + 1].first) { swap(v[p[i].second], v[p[i + 1].second]); break; } } vector<int> ans; for (i = 0; i < n - 2; i++) { int pos = min_element(v.begin() + i, v.end()) - v.begin(); while (pos > i + 1) { make(v, pos - 2); ans.push_back(pos - 2); pos = pos - 2; } if (pos != i) { make(v, i); make(v, i); ans.push_back(i); ans.push_back(i); pos = i; } } for (i = 0; i < 3; i++) { if (is_sorted(v.begin(), v.end())) { break; } make(v, n - 3); ans.push_back(n - 3); } if (!is_sorted(v.begin(), v.end())) { cout << -1 << n ; continue; } cout << ans.size() << n ; for (int x : ans) cout << x + 1 << ; cout << n ; } }
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 5; int n; pair<int, int> a[MAX]; struct par { int a, b; par(int a, int b) : a(a), b(b) {} bool operator<(const par &p) const { return b < p.b; } }; multiset<par> s; multiset<int> sizes; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i].first); a[i].second = i; } sort(a + 1, a + n + 1); int best = 1, opt = a[n].first + 1; for (int i = 1; i <= n; i++) { if (!sizes.empty()) { auto x = sizes.begin(); auto y = sizes.rbegin(); int v = a[i - 1].first + 1; if (*x == *y) { if ((int)sizes.size() > best) { best = sizes.size(); opt = v; } else if ((int)sizes.size() == best && a[i].first < opt) opt = v; } } auto u = s.upper_bound(par(0, a[i].second)); par intervalo = par(a[i].second, a[i].second); vector<par> del; if (u != s.end()) { auto o = *u; if (o.a - 1 == a[i].second) { del.push_back(o); intervalo.b = o.b; } } if (u != s.begin()) { u--; auto o = *u; if (o.b + 1 == a[i].second) { del.push_back(o); intervalo.a = o.a; } } for (auto o : del) { s.erase(s.find(o)); int sz = o.b - o.a + 1; sizes.erase(sizes.find(sz)); } s.insert(intervalo); sizes.insert(intervalo.b - intervalo.a + 1); } printf( %d n , opt); return 0; }
// nios_tester_audio_out_dma.v // This file was auto-generated from altera_msgdma_hw.tcl. If you edit it your changes // will probably be lost. // // Generated using ACDS version 18.1 625 `timescale 1 ps / 1 ps module nios_tester_audio_out_dma ( output wire [25:0] mm_read_address, // mm_read.address output wire mm_read_read, // .read output wire [3:0] mm_read_byteenable, // .byteenable input wire [31:0] mm_read_readdata, // .readdata input wire mm_read_waitrequest, // .waitrequest input wire mm_read_readdatavalid, // .readdatavalid input wire clock_clk, // clock.clk input wire reset_n_reset_n, // reset_n.reset_n input wire [31:0] csr_writedata, // csr.writedata input wire csr_write, // .write input wire [3:0] csr_byteenable, // .byteenable output wire [31:0] csr_readdata, // .readdata input wire csr_read, // .read input wire [2:0] csr_address, // .address input wire descriptor_slave_write, // descriptor_slave.write output wire descriptor_slave_waitrequest, // .waitrequest input wire [127:0] descriptor_slave_writedata, // .writedata input wire [15:0] descriptor_slave_byteenable, // .byteenable output wire csr_irq_irq, // csr_irq.irq output wire [31:0] st_source_data, // st_source.data output wire st_source_valid, // .valid input wire st_source_ready // .ready ); wire dispatcher_internal_read_command_source_valid; // dispatcher_internal:src_read_master_valid -> read_mstr_internal:snk_command_valid wire [255:0] dispatcher_internal_read_command_source_data; // dispatcher_internal:src_read_master_data -> read_mstr_internal:snk_command_data wire dispatcher_internal_read_command_source_ready; // read_mstr_internal:snk_command_ready -> dispatcher_internal:src_read_master_ready wire read_mstr_internal_response_source_valid; // read_mstr_internal:src_response_valid -> dispatcher_internal:snk_read_master_valid wire [255:0] read_mstr_internal_response_source_data; // read_mstr_internal:src_response_data -> dispatcher_internal:snk_read_master_data wire read_mstr_internal_response_source_ready; // dispatcher_internal:snk_read_master_ready -> read_mstr_internal:src_response_ready dispatcher #( .MODE (1), .RESPONSE_PORT (2), .DESCRIPTOR_INTERFACE (0), .DESCRIPTOR_FIFO_DEPTH (8), .ENHANCED_FEATURES (0), .DESCRIPTOR_WIDTH (128), .DESCRIPTOR_BYTEENABLE_WIDTH (16) ) dispatcher_internal ( .clk (clock_clk), // clock.clk .reset (~reset_n_reset_n), // clock_reset.reset .csr_writedata (csr_writedata), // CSR.writedata .csr_write (csr_write), // .write .csr_byteenable (csr_byteenable), // .byteenable .csr_readdata (csr_readdata), // .readdata .csr_read (csr_read), // .read .csr_address (csr_address), // .address .descriptor_write (descriptor_slave_write), // Descriptor_Slave.write .descriptor_waitrequest (descriptor_slave_waitrequest), // .waitrequest .descriptor_writedata (descriptor_slave_writedata), // .writedata .descriptor_byteenable (descriptor_slave_byteenable), // .byteenable .src_read_master_data (dispatcher_internal_read_command_source_data), // Read_Command_Source.data .src_read_master_valid (dispatcher_internal_read_command_source_valid), // .valid .src_read_master_ready (dispatcher_internal_read_command_source_ready), // .ready .snk_read_master_data (read_mstr_internal_response_source_data), // Read_Response_Sink.data .snk_read_master_valid (read_mstr_internal_response_source_valid), // .valid .snk_read_master_ready (read_mstr_internal_response_source_ready), // .ready .csr_irq (csr_irq_irq), // csr_irq.irq .src_response_data (), // (terminated) .src_response_valid (), // (terminated) .src_response_ready (1'b0), // (terminated) .snk_descriptor_data (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .snk_descriptor_valid (1'b0), // (terminated) .snk_descriptor_ready (), // (terminated) .mm_response_waitrequest (), // (terminated) .mm_response_byteenable (4'b0000), // (terminated) .mm_response_address (1'b0), // (terminated) .mm_response_readdata (), // (terminated) .mm_response_read (1'b0), // (terminated) .src_write_master_data (), // (terminated) .src_write_master_valid (), // (terminated) .src_write_master_ready (1'b0), // (terminated) .snk_write_master_data (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .snk_write_master_valid (1'b0), // (terminated) .snk_write_master_ready () // (terminated) ); read_master #( .DATA_WIDTH (32), .LENGTH_WIDTH (21), .FIFO_DEPTH (256), .STRIDE_ENABLE (0), .BURST_ENABLE (0), .PACKET_ENABLE (0), .ERROR_ENABLE (0), .ERROR_WIDTH (8), .CHANNEL_ENABLE (0), .CHANNEL_WIDTH (8), .BYTE_ENABLE_WIDTH (4), .BYTE_ENABLE_WIDTH_LOG2 (2), .ADDRESS_WIDTH (26), .FIFO_DEPTH_LOG2 (8), .SYMBOL_WIDTH (8), .NUMBER_OF_SYMBOLS (4), .NUMBER_OF_SYMBOLS_LOG2 (2), .MAX_BURST_COUNT_WIDTH (1), .UNALIGNED_ACCESSES_ENABLE (0), .ONLY_FULL_ACCESS_ENABLE (1), .BURST_WRAPPING_SUPPORT (0), .PROGRAMMABLE_BURST_ENABLE (0), .MAX_BURST_COUNT (1), .FIFO_SPEED_OPTIMIZATION (1), .STRIDE_WIDTH (1) ) read_mstr_internal ( .clk (clock_clk), // Clock.clk .reset (~reset_n_reset_n), // Clock_reset.reset .master_address (mm_read_address), // Data_Read_Master.address .master_read (mm_read_read), // .read .master_byteenable (mm_read_byteenable), // .byteenable .master_readdata (mm_read_readdata), // .readdata .master_waitrequest (mm_read_waitrequest), // .waitrequest .master_readdatavalid (mm_read_readdatavalid), // .readdatavalid .src_data (st_source_data), // Data_Source.data .src_valid (st_source_valid), // .valid .src_ready (st_source_ready), // .ready .snk_command_data (dispatcher_internal_read_command_source_data), // Command_Sink.data .snk_command_valid (dispatcher_internal_read_command_source_valid), // .valid .snk_command_ready (dispatcher_internal_read_command_source_ready), // .ready .src_response_data (read_mstr_internal_response_source_data), // Response_Source.data .src_response_valid (read_mstr_internal_response_source_valid), // .valid .src_response_ready (read_mstr_internal_response_source_ready), // .ready .master_burstcount (), // (terminated) .src_sop (), // (terminated) .src_eop (), // (terminated) .src_empty (), // (terminated) .src_error (), // (terminated) .src_channel () // (terminated) ); endmodule
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int N = 1e6 + 5; const int inf = 1 << 30; const long long llf = 9e18; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } struct node { int x, y, time; friend bool operator<(const node &a, const node &b) { return a.time > b.time; } }; bool cmp(int x, int y) { return x < y; } int pic[1010][1010]; int book[1010][1010]; int dx[4] = {0, 0, 1, -1}; int dy[4] = {1, -1, 0, 0}; int n, m, t; bool check(int x, int y) { bool f1 = false; bool f2 = false; for (register int i = 0; i <= 3; ++i) { if (x + dx[i] < 0 || x + dx[i] > n - 1 || y + dy[i] < 0 || y + dy[i] > m - 1) continue; if (pic[x + dx[i]][y + dy[i]] != pic[x][y]) { f2 = true; } else { f1 = true; book[x][y] = 0; } } if (f1 && !f2) return false; if (f1 && f2) return true; if (!f1 && f2) return false; } int main() { cin >> n >> m >> t; string s; for (register int i = 0; i <= n - 1; ++i) { cin >> s; for (register int j = 0; j <= m - 1; ++j) { pic[i][j] = s[j] - 0 ; } } node now, re; priority_queue<node> q; for (register int i = 0; i <= n - 1; ++i) { for (register int j = 0; j <= m - 1; ++j) { book[i][j] = inf; if (check(i, j)) { now.x = i; now.y = j; now.time = 0; q.push(now); } } } while (!q.empty()) { re = q.top(); q.pop(); int x = re.x, y = re.y; for (register int i = 0; i <= 3; ++i) { if (x + dx[i] < 0 || x + dx[i] > n - 1 || y + dy[i] < 0 || y + dy[i] > m - 1) continue; if (pic[x + dx[i]][y + dy[i]] != pic[x][y]) { now.x = x + dx[i]; now.y = y + dy[i]; now.time = re.time + 1; if (book[now.x][now.y] > now.time) { book[now.x][now.y] = now.time; q.push(now); } } } } long long x, y, p; for (register int i = 1; i <= t; ++i) { cin >> x >> y >> p; x--; y--; if (p < book[x][y] || book[x][y] == inf) cout << pic[x][y] << endl; else cout << (pic[x][y] + (p - 1ll * book[x][y]) % 2) % 2 << endl; } }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__O2111A_SYMBOL_V `define SKY130_FD_SC_MS__O2111A_SYMBOL_V /** * o2111a: 2-input OR into first input of 4-input AND. * * X = ((A1 | A2) & B1 & C1 & D1) * * Verilog stub (without power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_ms__o2111a ( //# {{data|Data Signals}} input A1, input A2, input B1, input C1, input D1, output X ); // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_MS__O2111A_SYMBOL_V
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; using ld = long double; using pi = pair<int, int>; using pl = pair<ll, ll>; using vi = vector<int>; using vl = vector<ll>; using vpi = vector<pi>; using si = set<int>; using sl = set<ll>; using qi = queue<int>; using ql = queue<ll>; template <class T> bool uin(T& a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T& a, T b) { return a < b ? (a = b, true) : false; } template <class T> bool uin(T& u, T& v, T a, T b) { return v - u > b - a ? (u = a, v = b, true) : false; } template <class T> bool uax(T& u, T& v, T a, T b) { return v - u < b - a ? (u = a, v = b, true) : false; } namespace input { template <class T> void re(complex<T>& x); template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } void re(ld& x) { string t; re(t); x = stold(t); } template <class T, class... Ts> void re(T& t, Ts&... ts) { re(t); re(ts...); } template <class T> void re(complex<T>& x) { T a, b; re(a, b); x = cd(a, b); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.f, p.s); } template <class T> void re(vector<T>& a) { for (int i = 0; i < (((int)(a).size())); ++i) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = 0; i < (SZ); ++i) re(a[i]); } } // namespace input using namespace input; namespace output { void pr(int x) { cout << x; } void pr(long x) { cout << x; } void pr(ll x) { cout << x; } void pr(unsigned x) { cout << x; } void pr(unsigned long x) { cout << x; } void pr(unsigned long long x) { cout << x; } void pr(float x) { cout << x; } void pr(double x) { cout << x; } void pr(ld x) { cout << x; } void pr(char x) { cout << x; } void pr(const char* x) { cout << x; } void pr(const string& x) { cout << x; } void pr(bool x) { pr(x ? true : false ); } template <class T> void pr(const complex<T>& x) { cout << x; } template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T> void pr(const T& x); template <class T, class... Ts> void pr(const T& t, const Ts&... ts) { pr(t); pr(ts...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.f, , , x.s, } ); } template <class T> void pr(const T& x) { pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } void ps() { pr( n ); } template <class T, class... Ts> void ps(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( ); ps(ts...); } void pc() { pr( ] n ); } template <class T, class... Ts> void pc(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( , ); pc(ts...); } } // namespace output using namespace output; inline int bs(bool (*valid)(int), int l, int r, bool order) { l--, r++; if (!order) swap(l, r); while (abs(r - l) > 1) { int mid = (l + r) >> 1; if (valid(mid)) r = mid; else l = mid; } valid(r); return r; } struct dsu { vector<int> p; dsu(int n) { p.resize(n + 1); } inline int get(int x) { return p[x] ? p[x] = get(p[x]) : x; } inline bool mrg(int x, int y) { return get(x) == get(y) ? false : p[get(x)] = get(y); } }; const int M = 1e9 + 7; const ll lnf = 1e18 + 3; const int inf = 1e9 + 3; const int nax = 2e5 + 5; typedef decay<decltype(M)>::type T; struct mi { T val; explicit operator T() const { return val; } mi() { val = 0; } mi(const ll& v) { val = (-M <= v && v <= M) ? v : v % M; if (val < 0) val += M; } friend void pr(const mi& a) { pr(a.val); } friend void re(mi& a) { ll x; re(x); a = mi(x); } friend bool operator==(const mi& a, const mi& b) { return a.val == b.val; } friend bool operator!=(const mi& a, const mi& b) { return !(a == b); } friend bool operator<(const mi& a, const mi& b) { return a.val < b.val; } mi operator-() const { return mi(-val); } mi& operator+=(const mi& m) { if ((val += m.val) >= M) val -= M; return *this; } mi& operator-=(const mi& m) { if ((val -= m.val) < 0) val += M; return *this; } mi& operator*=(const mi& m) { val = (ll)val * m.val % M; return *this; } friend mi pow(mi a, ll p) { mi ans = 1; assert(p >= 0); for (; p; p /= 2, a *= a) if (p & 1) ans *= a; return ans; } friend mi inv(const mi& a) { assert(a != 0); return pow(a, M - 2); } mi& operator/=(const mi& m) { return (*this) *= inv(m); } friend mi operator+(mi a, const mi& b) { return a += b; } friend mi operator-(mi a, const mi& b) { return a -= b; } friend mi operator*(mi a, const mi& b) { return a *= b; } friend mi operator/(mi a, const mi& b) { return a /= b; } }; vi invs, fac, ifac; void genFac(int SZ) { invs.resize(SZ), fac.resize(SZ), ifac.resize(SZ); invs[1] = fac[0] = ifac[0] = 1; for (int i = (2); i <= (SZ - 1); ++i) invs[i] = M - (ll)M / i * invs[M % i] % M; for (int i = (1); i <= (SZ - 1); ++i) { fac[i] = (ll)fac[i - 1] * i % M; ifac[i] = (ll)ifac[i - 1] * invs[i] % M; } } ll comb(int a, int b) { if (a < b || b < 0) return 0; return (ll)fac[a] * ifac[b] % M * ifac[a - b] % M; } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int test_case; cin >> test_case; while (test_case--) { int n; re(n); vi a(n, 0); re(a); int q = 0, p = n - 1; while (a[q] >= q) q++; while (a[p] >= n - 1 - p) p--; ps(q > p + 1 ? YES : NO ); } }
#include <bits/stdc++.h> using namespace std; string str; set<string> vis; int main() { int n; scanf( %d , &n); vis.clear(); for (int i = 0; i < n; ++i) { cin >> str; if (vis.find(str) != vis.end()) cout << YES << endl; else cout << NO << endl; vis.insert(str); } return 0; }
#include <bits/stdc++.h> using namespace std; int main() { int numRows, numCols; scanf( %d %d n , &numRows, &numCols); bool *rowArray = new bool[numRows]; for (int k = 0; k < numRows; k++) { rowArray[k] = 1; } bool *colArray = new bool[numCols]; for (int k = 0; k < numCols; k++) { colArray[k] = 1; } char temp; for (int row = 0; row < numRows; row++) { for (int col = 0; col < numCols; col++) { scanf( %c , &temp); if (temp == S ) { rowArray[row] = 0; colArray[col] = 0; } } scanf( n ); } int freeRows(0), freeCols(0); for (int k = 0; k < numRows; k++) { if (rowArray[k]) { ++freeRows; } } for (int k = 0; k < numCols; k++) { if (colArray[k]) { ++freeCols; } } printf( %d n , freeRows * numCols + freeCols * numRows - freeRows * freeCols); return 0; }
#include <bits/stdc++.h> using namespace std; int N, M; int A[50050], X[50500]; int L[50050], R[50500]; int XX[1010101]; int ma[50505]; int ret[50505]; signed long long xorxor(signed long long val) { int i; signed long long ret = ((val + 1) / 2) % 2; for (i = 0; i <= 29; i++) if ((val >> i) % 2) ret |= (1 ^ (val % 2)) << i; return ret; } void solve() { int i, j, k, l, r, x, y; string s; for (i = 1; i <= 1000000; i++) XX[i] = XX[i - 1] ^ i; cin >> N >> M; for (i = 0; i < (N); i++) cin >> A[i], X[i] = XX[A[i]]; for (i = 0; i < (M); i++) cin >> L[i] >> R[i], L[i]--, R[i]--; for (x = 0; x < (N); x++) { ma[x - 1] = 0; for (y = x; y < N; y++) ma[y] = max(ma[y - 1], X[x] ^ X[y] ^ ((A[x] > A[y]) ? A[y] : A[x])); for (i = 0; i < (M); i++) if (L[i] <= x) ret[i] = max(ret[i], ma[R[i]]); } for (i = 0; i < (M); i++) cout << ret[i] << endl; } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false); for (i = 0; i < (argc - 1); i++) s += argv[i + 1], s += n ; for (i = 0; i < (s.size()); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__DLXTN_4_V `define SKY130_FD_SC_HDLL__DLXTN_4_V /** * dlxtn: Delay latch, inverted enable, single output. * * Verilog wrapper for dlxtn with size of 4 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hdll__dlxtn.v" `ifdef USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_hdll__dlxtn_4 ( Q , D , GATE_N, VPWR , VGND , VPB , VNB ); output Q ; input D ; input GATE_N; input VPWR ; input VGND ; input VPB ; input VNB ; sky130_fd_sc_hdll__dlxtn base ( .Q(Q), .D(D), .GATE_N(GATE_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*********************************************************/ `else // If not USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_hdll__dlxtn_4 ( Q , D , GATE_N ); output Q ; input D ; input GATE_N; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hdll__dlxtn base ( .Q(Q), .D(D), .GATE_N(GATE_N) ); endmodule `endcelldefine /*********************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_HDLL__DLXTN_4_V
// dig /* ------------------------------------------------------------------------------- Copyright 2014 Parallax Inc. This file is part of the hardware description for the Propeller 1 Design. The Propeller 1 Design is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. The Propeller 1 Design is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- */ `include "cog.v" // cog logic and memory (8 instances) `include "hub.v" // hub logic and memory module dig ( input nres, // reset input (active low) output [7:0] cfg, // configuration output (set by clkset instruction) input clk_cog, // cog clock input input clk_pll, // pll simulator clock input (2x cog clock) input [31:0] pin_in, // pin state inputs output [31:0] pin_out, // pin state outputs output [31:0] pin_dir, // pin direction outputs output [7:0] cog_led // led outputs to show which cogs are active ); // cnt reg [31:0] cnt; always @(posedge clk_cog) if (nres) cnt <= cnt + 1'b1; // bus enable reg ena_bus; always @(posedge clk_cog or negedge nres) if (!nres) ena_bus <= 1'b0; else ena_bus <= !ena_bus; // bus select reg [7:0] bus_sel; always @(posedge clk_cog or negedge nres) if (!nres) bus_sel <= 8'b0; else if (ena_bus) bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]}; // cogs wire [7:0] bus_r; wire [7:0] bus_e; wire [7:0] bus_w; wire [7:0] [1:0] bus_s; wire [7:0] [15:0] bus_a; wire [7:0] [31:0] bus_d; wire [7:0] pll; wire [7:0] [31:0] outx; wire [7:0] [31:0] dirx; genvar i; generate for (i=0; i<8; i++) begin : coggen cog cog_( .nres (nres), .clk_cog (clk_cog), .clk_pll (clk_pll), .ena_bus (ena_bus), .ptr_w (ptr_w[i]), .ptr_d (ptr_d), .ena (cog_ena[i]), .bus_sel (bus_sel[i]), .bus_r (bus_r[i]), .bus_e (bus_e[i]), .bus_w (bus_w[i]), .bus_s (bus_s[i]), .bus_a (bus_a[i]), .bus_d (bus_d[i]), .bus_q (bus_q), .bus_c (bus_c), .bus_ack (bus_ack[i]), .cnt (cnt), .pll_in (pll), .pll_out (pll[i]), .pin_in (pin_in), .pin_out (outx[i]), .pin_dir (dirx[i]) ); end endgenerate // hub wire hub_bus_r = |bus_r; wire hub_bus_e = |bus_e; wire hub_bus_w = |bus_w; wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0]; wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0]; wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0]; wire [31:0] bus_q; wire bus_c; wire [7:0] bus_ack; wire [7:0] cog_ena; wire [7:0] ptr_w; wire [27:0] ptr_d; hub hub_ ( .clk_cog (clk_cog), .ena_bus (ena_bus), .nres (nres), .bus_sel (bus_sel), .bus_r (hub_bus_r), .bus_e (hub_bus_e), .bus_w (hub_bus_w), .bus_s (hub_bus_s), .bus_a (hub_bus_a), .bus_d (hub_bus_d), .bus_q (bus_q), .bus_c (bus_c), .bus_ack (bus_ack), .cog_ena (cog_ena), .ptr_w (ptr_w), .ptr_d (ptr_d), .cfg (cfg) ); // pins assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0]; assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0]; // cog leds assign cog_led = cog_ena; endmodule
#include <bits/stdc++.h> int main(void) { int n, w; int el[(4 * 100 * 1000)], be[(4 * 100 * 1000)]; int k[(4 * 100 * 1000)]; int i, j, z; scanf( %d %d , &n, &w); if (w == 1) { printf( %d n , n); return 0; } n--; for (i = 0; i <= n; i++) { if (i == 0) { scanf( %d , &z); } else { scanf( %d , &j); be[i - 1] = j - z; z = j; } } w--; for (i = 0; i <= w; i++) { if (i == 0) { scanf( %d , &z); } else { scanf( %d , &j); el[i - 1] = j - z; z = j; } } i = 0; j = -1; k[0] = -1; while (i < w) { while (j >= 0 && el[i] != el[j]) j = k[j]; i++; j++; k[i] = j; } i = 0; j = 0; z = 0; while (i < n) { while (j >= 0 && be[i] != el[j]) j = k[j]; i++; j++; if (j == w) { z++; j = k[j]; } } printf( %d n , z); return 0; }
/***************************************************************************** * * * Module: Altera_UP_RS232_Counters * * Description: * * This module reads and writes data to the RS232 connector on Altera's * * DE1 and DE2 Development and Education Boards. * * * *****************************************************************************/ module Altera_UP_RS232_Counters ( // Inputs clk, reset, reset_counters, // Bidirectionals // Outputs baud_clock_rising_edge, baud_clock_falling_edge, all_bits_transmitted ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input reset_counters; // Bidirectionals // Outputs output reg baud_clock_rising_edge; output reg baud_clock_falling_edge; output reg all_bits_transmitted; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter; reg [3:0] bit_counter; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (reset_counters) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (baud_counter == BAUD_TICK_COUNT) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else baud_counter <= baud_counter + BAUD_TICK_INCREMENT; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_rising_edge <= 1'b0; else if (baud_counter == BAUD_TICK_COUNT) baud_clock_rising_edge <= 1'b1; else baud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_falling_edge <= 1'b0; else if (baud_counter == HALF_BAUD_TICK_COUNT) baud_clock_falling_edge <= 1'b1; else baud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) bit_counter <= 4'h0; else if (reset_counters) bit_counter <= 4'h0; else if (bit_counter == TOTAL_DATA_WIDTH) bit_counter <= 4'h0; else if (baud_counter == BAUD_TICK_COUNT) bit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin if (reset == 1'b1) all_bits_transmitted <= 1'b0; else if (bit_counter == TOTAL_DATA_WIDTH) all_bits_transmitted <= 1'b1; else all_bits_transmitted <= 1'b0; end /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule
// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: bw_clk_gclk_inv_224x.v // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ // -------------------------------------------------- // File: bw_clk_gclk_inv_224x.behV // -------------------------------------------------- // module bw_clk_gclk_inv_224x ( clkout, clkin ); output clkout; input clkin; assign clkout = ~( clkin ); endmodule
// (C) 1992-2014 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. module acl_fp_ln_double_s5 ( enable, resetn, clock, dataa, result); input enable, resetn; input clock; input [63:0] dataa; output [63:0] result; wire [63:0] sub_wire0; wire [63:0] result = sub_wire0[63:0]; fp_ln_double_s5 inst ( .clk(clock), .areset(1'b0), .en(enable), .a(dataa), .q(sub_wire0)); endmodule
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014 // // Z80 clocking module, also contains some wait-stating when 14MHz /* This file is part of ZX-Evo Base Configuration firmware. ZX-Evo Base Configuration firmware is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. ZX-Evo Base Configuration firmware is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with ZX-Evo Base Configuration firmware. If not, see <http://www.gnu.org/licenses/>. */ // // IDEAL: // fclk _/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\ // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // zclk /```\___/```\___/```\___/```````\_______/```````\_______/```````````````\_______________/```````````````\_______________/` // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // zpos `\___/```\___/```\___/```\___________/```\___________/```\___________________________/```\___________________________/```\ // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________ // clock phasing: // cend must be zpos for 7mhz, therefore post_cbeg - zneg // for 3.5 mhz, cend is both zpos and zneg (alternating) // 14MHz rulez: // 1. do variable stalls for memory access. // 2. do fallback on 7mhz for external IO accesses // 3. clock switch 14-7-3.5 only at RFSH `include "../include/tune.v" module zclock( input wire fclk, input wire rst_n, input wire zclk, // Z80 clock, buffered via act04 and returned back to the FPGA input wire [15:0] a, // for contention input wire [ 1:0] modes_raster, input wire mode_contend_type, input wire mode_contend_ena, input wire [ 2:0] mode_7ffd_bits, // low 3 bits of 7FFD for 128k contention input wire contend, input wire mreq_n, input wire iorq_n, input wire m1_n, input wire rfsh_n, // switch turbo modes in RFSH part of m1 output reg zclk_out, // generated Z80 clock - passed through inverter externally! output reg zpos, output reg zneg, input wire zclk_stall, input wire [ 1:0] turbo, // 2'b00 - 3.5 MHz // 2'b01 - 7.0 MHz // 2'b1x - 14.0 MHz output reg [ 1:0] int_turbo, // internal turbo, switched on /RFSH // input signals for 14MHz external IORQ waits input wire external_port, input wire cbeg, input wire pre_cend // syncing signals, taken from arbiter.v and dram.v ); reg precend_cnt; wire h_precend_1; // to take every other pulse of pre_cend wire h_precend_2; // to take every other pulse of pre_cend reg [2:0] zcount; // counter for generating 3.5 and 7 MHz z80 clocks reg old_rfsh_n; wire stall; reg clk14_src; // source for 14MHz clock wire pre_zpos_35, pre_zneg_35; wire pre_zpos_70, pre_zneg_70; wire pre_zpos_140, pre_zneg_140; reg r_mreq_n; wire iorq_n_a; reg r_iorq_n_a; wire contend_wait; wire contend_mem; wire contend_io; wire contend_addr; reg [2:0] p7ffd; // resync to 14MHz `ifdef SIMULATE initial // simulation... begin precend_cnt = 1'b0; int_turbo = 2'b00; old_rfsh_n = 1'b1; clk14_src = 1'b0; zclk_out = 1'b0; end `endif // switch clock only at predefined time always @(posedge fclk) if(zpos) begin old_rfsh_n <= rfsh_n; if( old_rfsh_n && !rfsh_n ) int_turbo <= turbo; end // resync p7ffd always @(posedge fclk) p7ffd <= mode_7ffd_bits; // make 14MHz iorq wait reg [3:0] io_wait_cnt; reg io_wait; wire io; reg io_r; assign io = (~iorq_n) & m1_n & external_port; always @(posedge fclk) if( zpos ) io_r <= io; always @(posedge fclk, negedge rst_n) if( ~rst_n ) io_wait_cnt <= 4'd0; else if( io && (!io_r) && zpos && int_turbo[1] ) io_wait_cnt[3] <= 1'b1; else if( io_wait_cnt[3] ) io_wait_cnt <= io_wait_cnt + 4'd1; always @(posedge fclk) case( io_wait_cnt ) 4'b1000: io_wait <= 1'b1; 4'b1001: io_wait <= 1'b1; 4'b1010: io_wait <= 1'b1; 4'b1011: io_wait <= 1'b1; 4'b1100: io_wait <= 1'b1; 4'b1101: io_wait <= 1'b0; 4'b1110: io_wait <= 1'b1; 4'b1111: io_wait <= 1'b0; default: io_wait <= 1'b0; endcase assign stall = zclk_stall | io_wait | contend_wait; // 14MHz clocking always @(posedge fclk) if( !stall ) clk14_src <= ~clk14_src; // assign pre_zpos_140 = clk14_src ; assign pre_zneg_140 = (~clk14_src); // take every other pulse of pre_cend (make half pre_cend) always @(posedge fclk) if( pre_cend ) precend_cnt <= ~precend_cnt; assign h_precend_1 = precend_cnt && pre_cend; assign h_precend_2 = !precend_cnt && pre_cend; assign pre_zpos_35 = h_precend_2; assign pre_zneg_35 = h_precend_1; assign pre_zpos_70 = pre_cend; assign pre_zneg_70 = cbeg; assign pre_zpos = int_turbo[1] ? pre_zpos_140 : ( int_turbo[0] ? pre_zpos_70 : pre_zpos_35 ); assign pre_zneg = int_turbo[1] ? pre_zneg_140 : ( int_turbo[0] ? pre_zneg_70 : pre_zneg_35 ); always @(posedge fclk) begin zpos <= (~stall) & pre_zpos & zclk_out; end always @(posedge fclk) begin zneg <= (~stall) & pre_zneg & (~zclk_out); end // make Z80 clock: account for external inversion and make some leading of clock // 9.5 ns propagation delay: from fclk posedge to zclk returned back any edge // (1/28)/2=17.9ns half a clock lead // 2.6ns lag because of non-output register emitting of zclk_out // total: 5.8 ns lead of any edge of zclk relative to posedge of fclk => ACCOUNT FOR THIS WHEN DOING INTER-CLOCK DATA TRANSFERS // always @(negedge fclk) begin if( zpos ) zclk_out <= 1'b0; if( zneg ) zclk_out <= 1'b1; end // contention emulation -- only 48k by now, TODO 128k pages and +2a/+3! // assign iorq_n_a = iorq_n || (a[0]==1'b1); // always @(posedge fclk) if( zpos ) begin r_mreq_n <= mreq_n; r_iorq_n_a <= iorq_n_a; end // assign contend_addr = (modes_raster[0]==1'b0) ? ( a[15:14]==2'b01 ) : // 48k mode ( a[15:14]==2'b01 || (a[15:14]==2'b11 && p7ffd[0]) ) ; // 128k mode (yet only 128/+2) // assign contend_mem = contend_addr && r_mreq_n; assign contend_io = !iorq_n_a && r_iorq_n_a; // assign contend_wait = contend && (contend_mem || contend_io) && !int_turbo && modes_raster[1] && mode_contend_ena; // // TODO: contend is 28MHz signal, while we'd better have here // 3.5MHz-synced r_contend signal, which should be synced // to free-running 3.5MHz zpos/zneg sequence (not affected by stall) endmodule
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , unroll-loops , omit-frame-pointer , inline ) #pragma GCC option( arch=native , tune=native , no-zero-upper ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) using namespace std; int n, q, fa[66666], aa[66666], kh[66666], a[66666], p[66666], fp[66666], siz[66666], ck, pa[66666]; vector<int> edge[66666]; int dd[66666]; void dfs(int u) { siz[u] = 1; p[++ck] = u; fp[u] = ck; pa[ck] = fp[fa[u]]; dd[ck] = dd[pa[ck]] + 1; for (auto v : edge[u]) { dfs(v); siz[u] += siz[v]; } } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) { scanf( %d , aa + i); } for (int i = 2; i <= n; ++i) { scanf( %d , fa + i); edge[fa[i]].push_back(i); } dfs(1); for (int i = 1; i <= n; ++i) { a[fp[i]] = aa[i]; kh[i] = -50001; } for (int i = 1; i <= q; ++i) { int x; scanf( %d , &x); int y = siz[x]; x = fp[x]; int pp = i + 1, *jj = kh + x, *diao = dd + x, *aa = a + x; int ans = 0, cnt = 0; for (int j = 0; j < y; ++j) { if (jj[j] + aa[j] < pp) { jj[j] = i; ans += diao[j]; cnt++; } } ans = ans - cnt * dd[x]; printf( %d %d n , ans, cnt); } }
#include <bits/stdc++.h> using namespace std; const int N = 200010; vector<int> e[N]; set<int> l[N]; int n; void exitno() { printf( -1 n ); exit(0); } int exitans(int x) { while (x % 2 == 0) x /= 2; printf( %d n , x); exit(0); } void _dfs(int p, int fa) { if (fa && e[p].size() == 1) l[p].insert(0); for (int i = 0; i < e[p].size(); i++) { int x = e[p][i]; if (x == fa) continue; _dfs(x, p); for (auto j : l[x]) l[p].insert(j + 1); } if (l[p].size() >= 3) exitno(); } void work(int p) { for (int i = 1; i <= n; i++) l[i].clear(); _dfs(p, 0); int x = 0; for (auto i : l[p]) x += i; exitans(x); } void dfs(int p = 1, int fa = 0) { if (fa && e[p].size() == 1) l[p].insert(0); for (int i = 0; i < e[p].size(); i++) { int x = e[p][i]; if (x == fa) continue; dfs(x, p); for (auto j : l[x]) l[p].insert(j + 1); } if (l[p].size() >= 3) exitno(); if (l[p].size() == 2) work(p); } int main() { cin >> n; for (int i = 1; i <= n - 1; i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } dfs(); exitans(*l[1].begin()); return 0; }
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; bool f = 0; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = 1; for (; isdigit(c); c = getchar()) x = x * 10 + (c ^ 48); if (f) x = -x; } template <typename T> inline void Mx(T &x, T y) { x < y && (x = y); } template <typename T> inline void Mn(T &x, T y) { x > y && (x = y); } long long T, n, l, r; int main() { read(T); while (T--) { read(n), read(l), read(r); if (n == 2) { } long long sum = 0, pre = 0; for (int i = 1; i < n; i++) { sum += (n - i) * 2; if (l < sum) { long long t = l - pre; long long x = (t & 1) ? i : (t / 2) + i, y = (t / 2) + i; while (l < sum && l <= r) { printf( %lld , x); x == i ? y++, x = y : x = i; l++; } } if (l == sum && l <= r) printf( %lld , n), l++; pre = sum; if (l > r) break; } if (l <= r) printf( 1 ); puts( ); } return 0; }
#include <bits/stdc++.h> using namespace std; int n, k, s = 0, a; int sg(int x) { if (x == 0 || x == 1) return x; if (k % 2 == 0) { if (x == 2) return 2; if (x % 2 == 0) return 1; else return 0; } else { if (x == 2) return 0; if (x == 3) return 1; if (x == 4) return 2; if (x % 2 == 0) { int cnt = 0; while (x % 2 == 0) x /= 2, cnt++; if (x == 3) cnt++; if (cnt % 2) return 1; else return 2; } else return 0; } } int main(void) { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a; s ^= sg(a); } if (s == 0) cout << Nicky n ; else cout << Kevin n ; }
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: testIm_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 14.0.0 Build 200 06/17/2014 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, the Altera Quartus II License Agreement, //the Altera MegaCore Function License Agreement, or other //applicable license agreement, including, without limitation, //that your use is for the sole purpose of programming logic //devices manufactured by Altera and sold by Altera or its //authorized distributors. Please refer to the applicable //agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module testIm_rom ( address, clock, q); input [9:0] address; input clock; output [8:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [8:0] sub_wire0; wire [8:0] q = sub_wire0[8:0]; altsyncram altsyncram_component ( .address_a (address), .clock0 (clock), .q_a (sub_wire0), .aclr0 (1'b0), .aclr1 (1'b0), .address_b (1'b1), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), .clocken0 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .data_a ({9{1'b1}}), .data_b (1'b1), .eccstatus (), .q_b (), .rden_a (1'b1), .rden_b (1'b1), .wren_a (1'b0), .wren_b (1'b0)); defparam altsyncram_component.address_aclr_a = "NONE", altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.init_file = "../Software/testIm6.mif", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 1024, altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.widthad_a = 10, altsyncram_component.width_a = 9, altsyncram_component.width_byteena_a = 1; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "../Software/testIm.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "10" // Retrieval info: PRIVATE: WidthData NUMERIC "9" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "../Software/testIm.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" // Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0 // Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 5; const long long linf = 1e18 + 5; const int N = 3000 + 5; int n, x, y, all, up[N], down[N], w[N]; vector<pair<int, int> > v[N]; void dfs(int root, int x, int w, int up, int down) { ::up[x] = up; ::down[x] = down; ::w[x] = w; for (__typeof(v[x].begin()) it = v[x].begin(); it != v[x].end(); it++) if (it->first != root) { all += it->second; dfs(x, it->first, w, up + it->second, down + !it->second); } } int solve(int x) { all = 0; w[x] = 0; up[x] = 0; down[x] = 0; for (__typeof(v[x].begin()) it = v[x].begin(); it != v[x].end(); it++) { all += it->second; dfs(x, it->first, it->first, it->second, !it->second); } int ans = all, mni = -1; for (int i = 1; i <= n; i++) { if (all - up[i] + down[i] < ans) { ans = all - up[i] + down[i]; mni = w[i]; } } int ans2 = ans; for (int i = 1; i <= n; i++) { if (w[i] != mni and ans - up[i] + down[i] < ans2) { ans2 = ans - up[i] + down[i]; } } return ans2; } int main() { ios ::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n - 1; i++) { cin >> x >> y; v[x].push_back(make_pair(y, 0)); v[y].push_back(make_pair(x, 1)); } int ans = inf; for (int i = 1; i <= n; i++) ans = min(ans, solve(i)); cout << ans << n ; return 0; }
#include <bits/stdc++.h> using namespace std; mt19937 rd(chrono ::steady_clock ::now().time_since_epoch().count()); long long Rand(long long l, long long h) { return l + rd() % (h - l + 1); } template <typename T> inline void read(T &x) { register char c; bool sign = 0; for (c = getchar(); !isdigit(c); c = getchar()) if (c == - ) sign = !sign; x = c - 0 ; for (c = getchar(); isdigit(c); c = getchar()) x = x * 10 + c - 0 ; if (sign) x = -x; } template <typename T> inline bool mini(T &x, T y) { if (x > y) x = y; else return 0; return 1; } template <typename T> inline bool maxi(T &x, T y) { if (x < y) x = y; else return 0; return 1; } template <typename T> inline void _abs(T &x) { if (x < 0) x = -x; return; } const int N = 1003; int a[N]; int d[2]; int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; d[0] = d[1] = 0; for (int i = 1; i <= n; ++i) d[a[i]]++; bool t; if (d[0] < d[1]) t = 1; else t = 0; vector<int> res; for (int i = 1; i <= n; ++i) if (a[i] == t) res.push_back(t); if (t && (int)(res.size()) % 2) res.pop_back(); cout << res.size() << n ; for (int x : res) cout << x << ; cout << n ; } return 0; }
#include <bits/stdc++.h> using namespace std; int main() { int n, q, i; cin >> q; for (i = 0; i < q; i++) { cin >> n; if (n == 2) { cout << 2 << endl; } else if (n % 2 == 1) { cout << 1 << endl; } else if (n != 2 && n % 2 == 0) { cout << 0 << endl; } } }
module arbiter( input wire clk, input wire reset, // Slave 0 input wire [17:0] s0_address, input wire s0_write, input wire s0_read, input wire [35:0] s0_writedata, output reg [35:0] s0_readdata, output reg s0_waitrequest, // Slave 1 input wire [17:0] s1_address, input wire s1_write, input wire s1_read, input wire [35:0] s1_writedata, output reg [35:0] s1_readdata, output reg s1_waitrequest, // Master output reg [17:0] m_address, output reg m_write, output reg m_read, output reg [35:0] m_writedata, input wire [35:0] m_readdata, input wire m_waitrequest ); wire cyc0 = s0_read | s0_write; wire cyc1 = s1_read | s1_write; reg sel0, sel1; wire connected = sel0 | sel1; always @(posedge clk or negedge reset) begin if(~reset) begin sel0 <= 0; sel1 <= 0; end else begin if(sel0 & ~cyc0 | sel1 & ~cyc1) begin // disconnect if cycle is done sel0 <= 0; sel1 <= 0; end else if(~connected) begin // connect to master 0 or 1 if(cyc0) sel0 <= 1; else if(cyc1) sel1 <= 1; end end end // Do the connection always @(*) begin if(sel0) begin m_address <= s0_address; m_write <= s0_write; m_read <= s0_read; m_writedata <= s0_writedata; s0_readdata <= m_readdata; s0_waitrequest <= m_waitrequest; s1_readdata <= 0; s1_waitrequest <= 1; end else if(sel1) begin m_address <= s1_address; m_write <= s1_write; m_read <= s1_read; m_writedata <= s1_writedata; s1_readdata <= m_readdata; s1_waitrequest <= m_waitrequest; s0_readdata <= 0; s0_waitrequest <= 1; end else begin m_address <= 0; m_write <= 0; m_read <= 0; m_writedata <= 0; s0_readdata <= 0; s0_waitrequest <= 1; s1_readdata <= 0; s1_waitrequest <= 1; end end endmodule
#include <bits/stdc++.h> int n; int main() { int i; scanf( %d , &n); for (i = 20; i >= 0; i--) { if (n & (1 << i)) printf( %d , i + 1); } return 0; }
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V `define SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V /** * dfsbp: Delay flop, inverted set, complementary outputs. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hs__dfsbp ( CLK , D , Q , Q_N , SET_B, VPWR , VGND ); input CLK ; input D ; output Q ; output Q_N ; input SET_B; input VPWR ; input VGND ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int MAXN = 1e3 + 10; inline long long in() { long long x = 0, flag = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) flag = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + (ch ^ 48), ch = getchar(); return x * flag; } int T; int n, m; long long ans; long long fac[MAXN]; long long c[MAXN << 1][MAXN << 1]; long long dp[52][MAXN]; void prework() { fac[0] = 1; for (int i = 1; i <= 1000; i++) fac[i] = fac[i - 1] * 1LL * i % MOD; c[0][0] = 1; for (int i = 1; i <= 2000; i++) { c[i][0] = 1; for (int j = 1; j <= i; j++) (c[i][j] = c[i - 1][j - 1] + c[i - 1][j]) %= MOD; } dp[0][0] = 1; for (int i = 0; i <= 50; i++) { for (int j = i * (i + 1) / 2; j <= 1000; j++) { if (j + i <= 1000 && i != 0) (dp[i][j + i] += dp[i][j]) %= MOD; if (j + i + 1 <= 1000) (dp[i + 1][j + i + 1] += dp[i][j]) %= MOD; } } } int main() { T = in(); prework(); while (T--) { ans = 0; n = in(), m = in(); for (int i = m * (m + 1) / 2; i <= n; i++) { if (dp[m][i] == 0) continue; int res = n - i; (ans += c[res + m][m] * fac[m] % MOD * dp[m][i] % MOD) %= MOD; } printf( %lld n , ans); } return 0; }