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// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Fri May 20 15:50:56 2016
// Module Declaration
module main_module
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
clock, output
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input clock;
output output;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
endmodule
|
// Q: пограничные условия - входы выходы триггеров,
// значения регисторов
// ch2.
module mult8(
output [7:0] product,
input [7:0] A,
input [7:0] B,
input clk );
reg [15:0] prod16;
assign product = prod16[15:8];
always @(posedge clk) begin
prod16 <= A * B;
end
endmodule
module mult8_rollup(
output reg [7:0] product,
output done,
input [7:0] A,
input [7:0] B,
input clk,
input start );
reg [4:0] multcounter;
reg [7:0] shiftA;
reg [7:0] shiftB;
wire adden;
assign adden = shiftB[7] & !done;
assign done = multcounter[3];
always @(posedge clk) begin
if( start )
multcounter <= 0;
else if( !done ) begin
multcounter <= multcounter + 1;
end
if( start )
shiftB <= B;
else
shiftB[7:0] <= { shiftB[6:0], 1'b0 };
if( start )
shiftA <= A;
else
shiftA <= { shiftA[7], shiftA[7:1] };
if( start )
product <= 0;
else if( adden )
product <= product + shiftA;
end
endmodule
// к железу все равно близко!
// 2.2
module lowpassfir(
output reg [7:0] filtout,
output reg done,
input clk,
input [7:0] datain,
input datavalid,
input [7:0] coeffA, coeffB, coeffC);
reg [7:0] X0, X1, X2;
reg multdonedelay;
reg multstart;
reg [7:0] multdat;
reg [7:0] multcoeff;
reg [2:0] state;
reg [7:0] accum;
reg clearaccum;
reg [7:0] accumsum;
wire multdone;
wire [7:0] multout;
//.... mult instance
mult8x8 mult8x8(.clk(clk), .dat1(multdat),
.dat2(multcoeff), .start(multstart),
.done(multdone), .multout(multout));
// комбинация seq and comb logic
always @( posedge clk ) begin
multdonedelay <= multdone;
accumsum <= accum + multout[7:0];
if( clearaccum)
accum <= 0;
else if ( multdonedelay ) // почему задерж?
accum <= accumsum;
case( state )
0: begin
if( datavalid ) begin
X0 <= datain;
X1 <= X0;
X2 <= X1;
multdat <= datain; // load mult
multcoeff <= coeffA;
multstart <= 1;
clearaccum <= 1;
state <= 1;
end
else begin
multstart <= 0;
clearaccum <= 0;
done <= 0;
end
end
1: begin
if( multdonedelay ) begin
multdat <= X1;
multcoeff <= coeffB;
multstart <= 1;
state <= 2;
end
else begin
multstart <= 0;
clearaccum <= 0;
done <= 0;
end
end
2: begin
if( multdonedelay ) begin
multdat <= X2;
multcoeff <= coeffC;
multstart <= 0;
state <= 3;
end
else begin
multstart <= 0;
clearaccum <= 0;
done <= 0;
end
end
3: begin
if( multdonedelay ) begin
filtout <= accumsum;
done <= 1;
state <= 0;
end
else begin
multstart <= 0;
clearaccum <= 0;
done <= 0;
end
end
default
state <= 0;
endcase
end
endmodule
// reset troubles
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; int m; cin >> n >> m >> k; set<long long> removal; for (int i = 0; i < m; i++) { long long x; cin >> x; removal.insert(x); } long long total = 0; long long offset = 0; set<long long>::iterator itr = removal.begin(); while (itr != removal.end()) { auto num = *itr; auto cur_offset = offset; auto a = num - offset; auto r = a % k, d = a / k; long long K = 0; if (r == 0) { K = a; } else { K = k * (d + 1); } total++; do { offset++; itr++; } while (itr != removal.end() && *itr - cur_offset <= K); } cout << total << endl; ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000005, md = 998244353; int n, i, j, k, e, p[N], lmt, len, rt[N], ome[N], rome[N], g[N], h[N], w1[N], w2[N], inv[N]; long long a[N], b[N], w, xxj[65]; inline void Read(long long &x) { char c; while ((c = getchar()) < 0 || c > 9 ) ; x = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; } void ntt(int a[N], bool t) { for (int i = 0; i < len; ++i) if (i < rt[i]) swap(a[i], a[rt[i]]); for (int l = 2; l <= len; l <<= 1) { int m = l >> 1; for (int i = 0; i < len; i += l) for (int j = 0; j < m; ++j) { int w = 1ll * (t ? ome[len / l * j] : rome[len / l * j]) * a[i + j + m] % md; a[i + j + m] = (a[i + j] - w + md) % md; a[i + j] = (a[i + j] + w) % md; } } if (!t) for (int i = 0; i < len; ++i) a[i] = 1ll * a[i] * inv[len] % md; } void merge(int l, int r) { if (l == r) { p[l] = 2; return; } int mid = (l + r) / 2, i; merge(l, mid); merge(mid + 1, r); lmt = 0; while ((1 << lmt) <= r - l + 1) ++lmt; len = 1 << lmt; ome[0] = rome[0] = 1; for (i = 1; i < len; ++i) { rt[i] = 0; for (j = 0; j < lmt; ++j) if ((1 << j) & i) rt[i] |= 1 << (lmt - j - 1); ome[i] = 1ll * ome[i - 1] * w1[len] % md, rome[i] = 1ll * rome[i - 1] * w2[len] % md; } for (i = 0; i < len; ++i) g[i] = h[i] = 0; for (i = l; i <= mid; ++i) g[i - l] = p[i]; for (i = mid + 1; i <= r; ++i) h[i - mid - 1] = p[i]; ntt(g, true); ntt(h, true); for (i = 0; i < len; ++i) g[i] = 1ll * g[i] * h[i] % md; ntt(g, false); for (i = 0; i < len; ++i) { g[i + 1] += g[i] / 10; g[i] %= 10; } for (i = l; i <= r; ++i) p[i] = g[i - l]; } inline int pw(int a, int b) { int rtn = 1; while (b) { if (b & 1) rtn = 1ll * rtn * a % md; a = 1ll * a * a % md; b >>= 1; } return rtn; } int main() { scanf( %d , &n); for (i = 1; i <= n; ++i) { Read(a[i]); Read(b[i]); b[i] ^= a[i]; w ^= a[i]; } e = 0; for (i = 1; i <= n; ++i) { for (j = 60; j >= 0; --j) if ((1ll << j) & b[i]) { if (!xxj[j]) { xxj[j] = b[i]; break; } b[i] ^= xxj[j]; } if (b[i] == 0) ++e; } for (j = 60; j >= 0; --j) if ((1ll << j) & w) { if (!xxj[j]) { printf( 1/1 ); return 0; } w ^= xxj[j]; } if (n - e == 0) { printf( 0/1 ); return 0; } for (i = 1; i <= 2 * (n - e); ++i) { w1[i] = pw(3, (md - 1) / i), w2[i] = pw(w1[i], md - 2); if (i == 1) inv[i] = 1; else inv[i] = 1ll * inv[md % i] * (md - md / i) % md; } merge(1, n - e); for (i = n - e; p[i] == 0; --i) ; for (; i >= 2; --i) printf( %d , p[i]); printf( %d/ , p[i] - 1); for (i = n - e; p[i] == 0; --i) ; for (; i >= 1; --i) printf( %d , p[i]); return 0; }
|
// OPED.v - OpenCPI PCIe Endpoint with DMA
// Copyright (c) 2010,2011 Atomic Rules LLC - ALL RIGHTS RESERVED
//
// This is the top-level port signature of the OPED sub-system
// The signals are grouped functionally as indicated by their prefix
// + The PCIE_ signals must connect directly to their IOBs with no intermediate logic.
// + The ACLK and ARESETN outputs are the clock and reset for all other port groups
// + The M_AXI_ signal group is a AXI4-Lite Master with a 4GB address space
// + The M_AXIS group is the AXI4-Stream channel providing ingress data from PCIe->FPGA
// + The S_AXIS group is the AXI4-Stream channel supplying egress data from FPGA->PCIe
// + The ERR channel has zero bits of data. An error is indicated by TVALID assertion
// + The DEBUG signals contain up to 32 "interesting" bits of status
//
// + The 128b of TUSER are assigned as follows:
// TUSER[15:0] Transfer Length in Bytes (provided by OPED AXIS Master; ignored by OPED AXIS Slave since TLAST implicit length)
// TUSER[23:16] Source Port (SPT) (provided by OPED AXIS Master from DP0 opcode; ignored by OPED AXIS Slave)
// TUSER[31:24] Destination Port (DPT) (driven to 8'h01 by OPED AXIS Master; used by OPED AXIS Slave to make DP1 opcode)
// TUSER[127:32] User metadata bits, un-used by OPED. driven to 0 by OPED AXIS master; un-used by OPED AXIS slave
//
// Note that OPED is "port-encoding-agnostic" with respect to the values on SPT and DPT:
// a. In the case of packets moving downstream from host to NF10, OPED places DP0 opcode metadata on SPT
// b. In the case of packets moving upstream from NF10 to host, OPED captures DPT and places it in DP1 opcode
// The value 8'h01 is placed as a constant in the DPT output of the OPED AXIS Master
// Note that OPED does nothing with the TUSER[127:32] user metadata bits.
// a. It drives them to 0 on the AXIS Master
// b. it ignores them on the the AXIS Slave
module OPED #
( // OPED accepts the MPD-named paramater specifications...
parameter C_M_AXIS_DATA_WIDTH = 32,
parameter C_S_AXIS_DATA_WIDTH = 32,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter HAS_DEBUG_LOGIC = 0) // 0 = no debug logic, 1= debug logic
( // OPED uses the MPD-specified signal names for the AXI user-facing ports...
input PCIE_CLKP, // PCIe connections...
input PCIE_CLKN,
input PCIE_RSTN,
input [7:0] PCIE_RXP,
input [7:0] PCIE_RXN,
output [7:0] PCIE_TXP,
output [7:0] PCIE_TXN,
output ACLK, // Clock (125 MHz) (BUFG driven)
output ARESETN, // Synchronous Reset, Active-Low
output [31:0] M_AXI_AWADDR, // AXI4-Lite Write-Address channel..
output [2:0] M_AXI_AWPROT,
output M_AXI_AWVALID,
input M_AXI_AWREADY,
output [31:0] M_AXI_WDATA, // AXI4-Lite Write-Data channel...
output [3:0] M_AXI_WSTRB,
output M_AXI_WVALID,
input M_AXI_WREADY,
input [1:0] M_AXI_BRESP, // AXI4-Lite Write-Response channel...
input M_AXI_BVALID,
output M_AXI_BREADY,
output [31:0] M_AXI_ARADDR, // AXI4-Lite Read-Address channel...
output [2:0] M_AXI_ARPROT,
output M_AXI_ARVALID,
input M_AXI_ARREADY,
input [31:0] M_AXI_RDATA, // AXI4-Lite Read-Data channel...
input [1:0] M_AXI_RRESP,
input M_AXI_RVALID,
output M_AXI_RREADY,
output [C_M_AXIS_DATA_WIDTH-1:0] M_AXIS_DAT_TDATA, // AXI4-Stream (Ingress from PCIe) Master-Producer...
output [C_M_AXIS_DATA_WIDTH/8-1:0] M_AXIS_DAT_TSTRB,
output [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_DAT_TUSER,
output M_AXIS_DAT_TLAST,
output M_AXIS_DAT_TVALID,
input M_AXIS_DAT_TREADY,
input [C_S_AXIS_DATA_WIDTH-1:0] S_AXIS_DAT_TDATA, // AXI4-Stream (Egress to PCIe) Slave-Consumer...
input [C_S_AXIS_DATA_WIDTH/8-1:0] S_AXIS_DAT_TSTRB,
input [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_DAT_TUSER,
input S_AXIS_DAT_TLAST,
input S_AXIS_DAT_TVALID,
output S_AXIS_DAT_TREADY,
output [31:0] DEBUG // 32b of OPED debug information
);
// The code that follows is the "impedance-matching" to the underlying OPED core logic
// This code, and the the submodules it instantiates, are intended to be functionally opaque
// Here we instance mkOPED, which is the name of the BSV OPED implementation.
// Alternately, future OPED implementations may be adapted and placed here, if desired.
// This adaptation layer may be removed at a later date when it is clear it is not needed
//
// Compile time check for expected paramaters...
initial begin
if (C_M_AXIS_DATA_WIDTH != 32) begin $display("Unsupported M_AXIS_DATA width"); $finish; end
if (C_S_AXIS_DATA_WIDTH != 32) begin $display("Unsupported S_AXIS_DATA width"); $finish; end
if (C_M_AXIS_TUSER_WIDTH != 128) begin $display("Unsupported M_AXIS_TUSER width"); $finish; end
if (C_S_AXIS_TUSER_WIDTH != 128) begin $display("Unsupported S_AXIS_TUSER width"); $finish; end
end
mkOPED_v5 # (
.hasDebugLogic (HAS_DEBUG_LOGIC) // Set to 0 for no debug logic; Set to 1 for debug logic
)
oped
(
.pci0_clkp (PCIE_CLKP),
.pci0_clkn (PCIE_CLKN),
.RST_N_pci0_rstn (PCIE_RSTN),
.pcie_rxp_i (PCIE_RXP),
.pcie_rxn_i (PCIE_RXN),
.pcie_txp (PCIE_TXP),
.pcie_txn (PCIE_TXN),
.p125clk (ACLK),
.CLK_GATE_p125clk (),
.RST_N_p125rst (ARESETN),
.axi4m_AWADDR (M_AXI_AWADDR),
.axi4m_AWPROT (M_AXI_AWPROT),
.axi4m_AWVALID (M_AXI_AWVALID),
.axi4m_AWREADY (M_AXI_AWREADY),
.axi4m_WDATA (M_AXI_WDATA),
.axi4m_WSTRB (M_AXI_WSTRB),
.axi4m_WVALID (M_AXI_WVALID),
.axi4m_WREADY (M_AXI_WREADY),
.axi4m_BRESP (M_AXI_BRESP),
.axi4m_BVALID (M_AXI_BVALID),
.axi4m_BREADY (M_AXI_BREADY),
.axi4m_ARADDR (M_AXI_ARADDR),
.axi4m_ARPROT (M_AXI_ARPROT),
.axi4m_ARVALID (M_AXI_ARVALID),
.axi4m_ARREADY (M_AXI_ARREADY),
.axi4m_RDATA (M_AXI_RDATA),
.axi4m_RRESP (M_AXI_RRESP),
.axi4m_RVALID (M_AXI_RVALID),
.axi4m_RREADY (M_AXI_RREADY),
.axisM_TDATA (M_AXIS_DAT_TDATA),
.axisM_TVALID (M_AXIS_DAT_TVALID),
.axisM_TSTRB (M_AXIS_DAT_TSTRB),
.axisM_TUSER (M_AXIS_DAT_TUSER),
.axisM_TLAST (M_AXIS_DAT_TLAST),
.axisM_TREADY (M_AXIS_DAT_TREADY),
.axisS_TDATA (S_AXIS_DAT_TDATA),
.axisS_TVALID (S_AXIS_DAT_TVALID),
.axisS_TSTRB (S_AXIS_DAT_TSTRB),
.axisS_TUSER (S_AXIS_DAT_TUSER),
.axisS_TLAST (S_AXIS_DAT_TLAST),
.axisS_TREADY (S_AXIS_DAT_TREADY),
.debug (DEBUG)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFSBP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_TB_V
`define SKY130_FD_SC_MS__O31AI_TB_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_TB_V
|
`timescale 1ns/10ps
`define CYCLE_PERIOD 4.0
module PATTERN(
input [10:0] out,
input out_valid,
output reg [3:0] in,
output reg [1:0] mode,
output reg in_valid,
output reg clk,
output reg rst_n
);
parameter CYCLE = `CYCLE_PERIOD;
parameter PATTERN_NUM = 1000;
reg [7:0] times[0:8];
reg [2:0] mode_t;
reg [7:0] length,wait_clk,i,k,l;
reg [4:0] t1,t2,t3,t4,t5,t6,t7,t8,t9;
integer latency, total_latency;
integer pattern_num, j;
integer max,min,gold;
initial begin
total_latency = 0;
end
initial begin
clk = 0;
#10;
$display("before clk");
forever #(CYCLE/2) clk = ~clk;
end
initial begin
in <= 'dx;
mode <= 'dx;
in_valid <= 'bx;
rst_n <= 1'b1;
mode<='dx;
$display("before reset");
#2;
rst_n <= 1'b0;
#4;
rst_n <= 1'b1;
check_rst;
in_valid <= 'b0;
@(negedge clk);
pattern_num=0;
input_task1;
ans_calc;
wait_out;
check_ans;
for(pattern_num=1;pattern_num<PATTERN_NUM;pattern_num=pattern_num+1) begin
input_task;
ans_calc;
wait_out;
check_ans;
end
@(negedge clk);
$display ("--------------------------------------------------------------------");
$display (" Congratulations ! ");
$display (" You have passed all patterns ! ");
$display (" Your total latency is %6d ! ", total_latency);
$display ("--------------------------------------------------------------------");
@(negedge clk);
$finish;
end
task check_rst;
if(out !== 'd0 || out_valid !== 1'b0) begin
$display("");
$display("=================================================");
$display(" Output should be reset !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
endtask
task check_out_vaild;
if(out_valid !== 1'b0) begin
$display("");
$display("=================================================");
$display(" Out_valid should not be HIGH while in_valid is HIGH !!!!");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
endtask
task input_task1;begin
for(i=0;i<9;i=i+1) begin
times[i] = 0;
end
length={$random()}%'d10+1;
mode_t=2;
max=0;
i=0;
while (i<9)begin
while (length>0 && times[8]<31)begin
in_valid <= 1'b1;
in <= i+1;
times[i]=times[i]+1;
if (times[i]>max) max=times[i];
if (times[i]==31) i=i+1;
length<=length-1;
check_out_vaild;
t1=times[0]; t2=times[1]; t3=times[2]; t4=times[3]; t5=times[4];
t6=times[5]; t7=times[6]; t8=times[7]; t9=times[8];
@(negedge clk);
end
in <= 'dx;
in_valid <= 1'b0;
wait_clk={$random()}%'d20;
repeat(wait_clk)@(negedge clk);
length={$random()}%'d10+1;
k=k-1;
end
in <= 0;
in_valid <= 1'b1;
@(negedge clk);
in <= 'dx;
in_valid <= 1'b0;
mode<=mode_t;
@(negedge clk);
mode<='dx;
end endtask
task input_task;begin
for(i=0;i<9;i=i+1) begin
times[i] = 0;
end
k={$random()}%'d31+1;
length={$random()}%'d10+1;
mode_t={$random()}%'d3;
max=0;
while (k>0 && max<31)begin
while (length>0 && max<31)begin
i={$random()}%'d9;
in_valid <= 1'b1;
in <= i+1;
times[i]=times[i]+1;
if (times[i]>max) max=times[i];
length<=length-1;
check_out_vaild;
t1=times[0]; t2=times[1]; t3=times[2]; t4=times[3]; t5=times[4];
t6=times[5]; t7=times[6]; t8=times[7]; t9=times[8];
@(negedge clk);
end
in <= 'dx;
in_valid <= 1'b0;
wait_clk={$random()}%'d20;
repeat(wait_clk)@(negedge clk);
length={$random()}%'d10+1;
k=k-1;
end
in <= 0;
in_valid <= 1'b1;
@(negedge clk);
in <= 'dx;
in_valid <= 1'b0;
mode<=mode_t;
@(negedge clk);
mode<='dx;
end endtask
task ans_calc;begin
min=33;
gold=0;
case (mode_t)
2'd0:gold=max;
2'd1:begin
for (i=0;i<9;i=i+1)begin
if (times[i]<min) min=times[i];
end
gold=min;
end
2'd2:begin
for (i=0;i<9;i=i+1)begin
gold=gold+(i+1)*times[i];
end
end
default:gold=0;
endcase
end endtask
task wait_out;begin
latency = -1;
while(!(out_valid === 1'b1)) begin
if(latency > 100) begin
$display("");
$display("=================================================");
$display(" Latency too more !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
latency = latency + 1;
total_latency = total_latency + 1;
@(negedge clk);
end
end endtask
task check_ans;begin
i=0;
while(out_valid) begin
if(out !== gold) begin
$display("");
$display("=================================================");
$display(" Failed!! PATTERN %4d is wrong! ", pattern_num+1);
$display(" mode=%d gold=%d your ans=%d ",mode_t,gold,out);
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
if(i>=1)
begin
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" Outvalid is more than 1 cycles ");
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(9) @(negedge clk);
$finish;
end
i=i+1;
@(negedge clk);
end
$display("");
$display(" Pass pattern %3d ", pattern_num+1);
@(negedge clk);
end endtask
endmodule
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#include <bits/stdc++.h> using namespace std; bool used[10000001]; int n, m, second = 0, ds[1000001], ans[1000001], str[1000001], sv[1000001]; struct o { int x, i, j; }; o d[1000001]; vector<vector<int> > a; bool comp(o a, o b) { if (a.x == b.x) return a.i < b.i; return a.x < b.x; } bool fcomp(o a, o b) { if (a.x == b.x) return a.j < b.j; return a.x < b.x; } int FS(int v) { if (ds[v] == v) return v; return ds[v] = FS(ds[v]); } void US(int a, int b) { a = FS(a); b = FS(b); ds[a] = ds[b]; return; } vector<pair<int, int> > tt[1000001]; pair<int, int> dd(int v) { int i = (v - 1) / m; ++i; int j = v % m; if (j == 0) j = m; return {i, j}; } int main() { cin >> n >> m; a.resize(n + 1); for (int k = 1; k <= n; ++k) { a[k].resize(m + 1); } for (int k = 1; k <= n; ++k) for (int i = 1; i <= m; ++i) { cin >> a[k][i]; ds[(k - 1) * m + i] = (k - 1) * m + i; o w; w.x = a[k][i]; w.i = k; w.j = i; d[++second] = w; } sort(d + 1, d + second + 1, comp); for (int k = 1; k < second; ++k) if (d[k].x == d[k + 1].x) { if (d[k].i == d[k + 1].i) US((d[k].i - 1) * m + d[k].j, (d[k + 1].i - 1) * m + d[k + 1].j); } sort(d + 1, d + second + 1, fcomp); for (int k = 1; k < second; ++k) if (d[k].x == d[k + 1].x) { if (d[k].j == d[k + 1].j) { US((d[k].i - 1) * m + d[k].j, (d[k + 1].i - 1) * m + d[k + 1].j); } } for (int k = 1; k <= n * m; ++k) tt[FS(ds[k])].push_back(dd(k)); for (int k = 1; k <= second; ++k) { int i = d[k].i; int j = d[k].j; if (used[(i * m - m) + j]) continue; int cm = FS(ds[(i * m - m) + j]); int cnt = 0; for (int i = 0; i < tt[cm].size(); ++i) { int ii = tt[cm][i].first; int jj = tt[cm][i].second; used[ii * (m)-m + jj] = 1; cnt = max(str[ii], cnt); cnt = max(sv[jj], cnt); } for (int i = 0; i < tt[cm].size(); ++i) { int ii = tt[cm][i].first; int jj = tt[cm][i].second; ans[ii * (m)-m + jj] = cnt + 1; sv[jj] = max(cnt + 1, sv[jj]); str[ii] = max(cnt + 1, str[ii]); } } for (int k = 1; k <= n; ++k) { for (int i = 1; i <= m; ++i) cout << ans[(k - 1) * m + i] << ; cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long power(long long b, long long e) { long long p = 1; while (e > 0) { if (e & 1) { p = (p * b) % 1000000007; } e = e >> 1; b = (b * b) % 1000000007; } return p; } vector<string> num; string s, s1; int main() { long long n, i, t, x = 0, j, m, c, q, ans = 0, l; scanf( %lld , &n); cin >> s; for (i = 0; i < 10; i++) { for (j = 0; j < n; j++) { s1 = s; for (l = 0; l < n; l++) { s1[l] = (char)((s[(l + j) % n] - 48 + i) % 10 + 48); } num.push_back(s1); } } sort((num).begin(), (num).end()); cout << num[0] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(); cin.tie(); cout.tie(); int n; cin >> n; int weight[n]; for (int i = 0; i < n; ++i) cin >> weight[i]; int p; cin >> p; vector<pair<pair<int, int>, int> > data; for (int i = 0; i < p; ++i) { int a, b; cin >> a >> b; --a; data.push_back({{b, a}, i}); } sort(data.begin(), data.end()); vector<pair<int, long long> > answer; long long dp[n]; int prev = -1; for (int i = 0; i < p; ++i) { int b = data[i].first.first, a = data[i].first.second; if (b >= 500) { long long sum = 0; for (; a < n; a += b) sum += weight[a]; answer.push_back({data[i].second, sum}); prev = -1; continue; } if (prev == -1 || b != prev) { for (int j = n - 1; j >= 0; --j) { if (j + b > n - 1) dp[j] = weight[j]; else dp[j] = weight[j] + dp[j + b]; } } answer.push_back({data[i].second, dp[a]}); prev = b; } sort(answer.begin(), answer.end()); for (int i = 0; i < p; ++i) cout << answer[i].second << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> a(n); int prev = -1; bool invalid = false; for (int i = 0; i < n; i++) { cin >> a[i]; invalid = (prev > a[i]) || (a[i] > i + 1); prev = a[i]; } if (invalid) { cout << -1 << endl; return; } int mex = a.back(); vector<int> ans(n); bool first = true; for (int i = 0, cnt = 0; i < n; i++) { if (first && i == mex) { first = false; cnt++; } ans[i] = cnt++; } for (int i = n - 1; ~i; i--) { if (ans[a[i]] == a[i]) { swap(ans[a[i]], ans[i + 1]); } } for (int i = 0; i < n; i++) { cout << ans[i] << n [i + 1 == n]; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; long long fac[100001]; long long inv_fac[100001]; int val[100001]; vector<int> cnt(53, 0); int l[100001]; int r[100001]; long long keep[53][53]; long long dp[54][100001]; long long dp1[54][100001]; long long mod = 1e9 + 7; inline void add(long long &a, long long b) { a += b; if (a >= mod) a -= mod; } inline void sub(long long &a, long long b) { a -= b; if (a < 0) a += mod; } long long pw(long long x, int p) { if (p == 0) return 1; if (p == 1) return x % mod; long long temp = pw(x, p / 2); temp = (temp * temp) % mod; if (p % 2 == 0) return temp; temp = (x * temp) % mod; return temp; } void calc() { fac[0] = fac[1] = 1; inv_fac[0] = inv_fac[1] = 1; for (int i = 2; i <= 100000; i++) { fac[i] = (i * fac[i - 1]) % mod; inv_fac[i] = pw(fac[i], mod - 2); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s; cin >> s; int q; cin >> q; for (int i = 0; i < q; i++) cin >> l[i] >> r[i]; int n = s.size(); int mx = n / 2; calc(); for (int i = 0; i < n; i++) { if (s[i] >= a && s[i] <= z ) { val[i + 1] = int(s[i] - a ) + 1; cnt[int(s[i] - a ) + 1]++; } else { val[i + 1] = 26 + int(s[i] - A ) + 1; cnt[26 + int(s[i] - A ) + 1]++; } } for (int i = 1; i <= 52; i++) { int temp = cnt[i]; if (temp > n / 2 || cnt[i] == 0) { continue; } temp = n / 2 - temp; for (int w = 0; w <= mx; w++) dp[0][w] = dp1[53][w] = 0; dp[0][0] = dp1[53][0] = 1; for (int k = 1; k <= 52; k++) { if (k == i || cnt[k] == 0) { for (int w = 0; w <= mx; w++) dp[k][w] = dp[k - 1][w]; continue; } for (int w = 0; w <= mx; w++) { dp[k][w] = dp[k - 1][w]; if (w >= cnt[k]) add(dp[k][w], dp[k - 1][w - cnt[k]]); } } for (int k = 52; k >= 1; k--) { if (k == i || cnt[k] == 0) { for (int w = 0; w <= mx; w++) dp1[k][w] = dp1[k + 1][w]; continue; } for (int w = 0; w <= mx; w++) { dp1[k][w] = dp1[k + 1][w]; if (w >= cnt[k]) add(dp1[k][w], dp1[k + 1][w - cnt[k]]); } } for (int k = i; k <= 52; k++) { if (k == i) { keep[k][i] = dp[52][temp]; continue; } long long t1 = 0; int rem = temp - cnt[k]; if (rem < 0) { keep[k][i] = keep[i][k] = 0; continue; } for (int w = 0; w <= rem; w++) { long long t2 = (dp[k - 1][w] * dp1[k + 1][rem - w]) % mod; add(t1, t2); } keep[i][k] = keep[k][i] = t1; } } long long ans = (fac[n / 2] * fac[n / 2]) % mod; for (int i = 1; i <= 52; i++) ans = (ans * inv_fac[cnt[i]]) % mod; ans = (2 * ans) % mod; for (int i = 0; i < q; i++) { int x = val[l[i]]; int y = val[r[i]]; long long temp = ans; temp = (temp * keep[x][y]) % mod; cout << temp << endl; } }
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#include <bits/stdc++.h> using namespace std; long long arr[500005]; map<long long, int> mm; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &arr[i]); for (int i = 1; i <= n - 1; i++) arr[i] += arr[i - 1]; for (int i = 0; i < n; i++) mm[arr[i]]++; int mx = -1; map<long long, int>::iterator it; for (it = mm.begin(); it != mm.end(); it++) { mx = max(mx, it->second); } printf( %d n , n - mx); return 0; }
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#include <bits/stdc++.h> using namespace std; double px[1005], py[1005]; double tx, ty; int sum; int pnpoly(int nvert, double *vertx, double *verty, double testx, double testy) { int i, j, c = 0; for (i = 0, j = nvert - 1; i < nvert; j = i++) { if (((verty[i] > testy) != (verty[j] > testy)) && (testx < (vertx[j] - vertx[i]) * (testy - verty[i]) / (verty[j] - verty[i]) + vertx[i])) c = !c; } return c; } int main() { ios::sync_with_stdio(false); int n; while (cin >> n) { sum = 0; memset(px, 0, sizeof(px)); memset(py, 0, sizeof(py)); for (int i = 0; i <= n; i++) { cin >> px[i] >> py[i]; } for (int i = 1; i < n; i++) { if (px[i] - px[i - 1] == 0) { tx = px[i]; ty = abs(py[i] - py[i - 1]) / (py[i] - py[i - 1]) * 0.1 + py[i]; } else if (py[i] - py[i - 1] == 0) { ty = py[i]; tx = abs(px[i] - px[i - 1]) / (px[i] - px[i - 1]) * 0.1 + px[i]; } if (pnpoly(n, px, py, tx, ty)) { sum++; } } cout << sum << endl; } return 0; }
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#include<bits/stdc++.h> using namespace std; typedef double db; typedef uint32_t u32; typedef uint64_t u64; typedef pair<int, int> pii; typedef pair<int, int> point; #define fi first #define se second #define pb(x) push_back(x) #define SZ(x) ((int) (x).size()) #define all(x) (x).begin(), (x).end() #define rep(i, l, r) for(int i = l; i < r; i++) typedef long long ll; const int mod = 998244353; int main() { #ifdef local freopen( in.txt , r , stdin); #endif ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); const int mod = 1e9 + 7; int n; cin >> n; vector<int> a(n); ll tot = 0; for(auto &e : a) { cin >> e; tot += e; } if(tot % n) { cout << 0 n ; return 0; } vector<int> fac(n + 1, 1); vector<int> ifac(n + 1, 1); for(int i = 2; i <= n; i++) { fac[i] = (ll) fac[i - 1] * i % mod; ifac[i] = (ll) ifac[mod % i] * (mod - mod / i) % mod; } for(int i = 2; i <= n; i++) { ifac[i] = (ll) ifac[i] * ifac[i - 1] % mod; } auto C = [&](int n, int m) { if(n < m || m < 0) return 0ll; return (ll) fac[n] * ifac[m] % mod * ifac[n - m] % mod; }; ll avg = tot / n; vector<int> l, r; int eq = 0; for(auto &e : a) { if(e > avg) { r.push_back(e); } else if(e < avg) { l.push_back(e); } else { eq++; } } int ans = 1; if(l.size() > 1 && r.size() > 1) { ans = 2; } if(l.size() == 1) { r.push_back(l[0]); l.clear(); } if(r.size() == 1) { l.push_back(r[0]); r.clear(); } sort(all(l)); sort(all(r)); int a1 = fac[l.size()]; int a2 = fac[r.size()]; for(int i = 0, j = 0; i < (int) l.size(); i = j) { while(j < (int) l.size() && l[j] == l[i]) { j++; } a1 = (ll) a1 * ifac[j - i] % mod; } for(int i = 0, j = 0; i < (int) r.size(); i = j) { while(j < (int) r.size() && r[j] == r[i]) { j++; } a2 = (ll) a2 * ifac[j - i] % mod; } int a3 = C(n, eq); ans = (ll) ans * a1 % mod; ans = (ll) ans * a2 % mod; ans = (ll) ans * a3 % mod; cout << ans << n ; return 0; }
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/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output irq,
/* Wishbone DMA master (write only, sel=1111) */
output [31:0] wbm_dat_o,
output [31:0] wbm_adr_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i
);
wire alu_rst;
wire [31:0] a;
wire [31:0] b;
wire ifb;
wire [3:0] opcode;
wire [31:0] r;
wire r_valid;
wire dma_en;
wire err_collision;
pfpu_alu alu(
.sys_clk(sys_clk),
.alu_rst(alu_rst), /* < from sequencer */
.a(a), /* < from register file */
.b(b), /* < from register file */
.ifb(ifb), /* < from register file */
.opcode(opcode), /* < from program memory */
.r(r), /* < to register file */
.r_valid(r_valid), /* < to register file */
.dma_en(dma_en), /* < to DMA engine and sequencer */
.err_collision(err_collision) /* < to control interface */
);
wire c_en;
wire [6:0] a_addr;
wire [6:0] b_addr;
wire [6:0] w_addr;
wire [6:0] cr_addr;
wire [31:0] cr_dr;
wire [31:0] cr_dw;
wire cr_w_en;
wire [31:0] r0;
wire [31:0] r1;
wire err_stray;
pfpu_regf regf(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ifb(ifb), /* < to ALU */
.a(a), /* < to ALU */
.b(b), /* < to ALU */
.r(r), /* < to ALU */
.w_en(r_valid), /* < from ALU */
.a_addr(a_addr), /* < from program memory */
.b_addr(b_addr), /* < from program memory */
.w_addr(w_addr), /* < from program memory */
.c_en(c_en), /* < from sequencer */
.c_addr(cr_addr), /* < from control interface */
.c_do(cr_dr), /* < to control interface */
.c_di(cr_dw), /* < from control interface */
.c_w_en(cr_w_en), /* < from control interface */
.r0(r0), /* < from counters */
.r1(r1), /* < from counters */
.err_stray(err_stray) /* < to control interface */
);
wire [28:0] dma_base;
wire dma_busy;
wire dma_ack;
pfpu_dma dma(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.dma_en(dma_en), /* < from ALU */
.dma_base(dma_base), /* < from control interface */
.x(r0[6:0]), /* < from counters */
.y(r1[6:0]), /* < from counters */
.dma_d1(a), /* < from register file */
.dma_d2(b), /* < from register file */
.busy(dma_busy), /* < to sequencer */
.ack(dma_ack), /* < to sequencer */
.wbm_dat_o(wbm_dat_o),
.wbm_adr_o(wbm_adr_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i)
);
wire vfirst;
wire vnext;
wire [6:0] hmesh_last;
wire [6:0] vmesh_last;
wire vlast;
pfpu_counters counters(
.sys_clk(sys_clk),
.first(vfirst), /* < from sequencer */
.next(vnext), /* < from sequencer */
.hmesh_last(hmesh_last), /* < from control interface */
.vmesh_last(vmesh_last), /* < from control interface */
.r0(r0), /* < to register file */
.r1(r1), /* < to register file */
.last(vlast) /* < to sequencer */
);
wire pcount_rst;
wire [1:0] cp_page;
wire [8:0] cp_offset;
wire [31:0] cp_dr;
wire [31:0] cp_dw;
wire cp_w_en;
wire [10:0] pc;
pfpu_prog prog(
.sys_clk(sys_clk),
.count_rst(pcount_rst), /* < from sequencer */
.a_addr(a_addr), /* < to ALU */
.b_addr(b_addr), /* < to ALU */
.opcode(opcode), /* < to ALU */
.w_addr(w_addr), /* < to ALU */
.c_en(c_en), /* < from sequencer */
.c_page(cp_page), /* < from control interface */
.c_offset(cp_offset), /* < from control interface */
.c_do(cp_dr), /* < to control interface */
.c_di(cp_dw), /* < from control interface */
.c_w_en(cp_w_en), /* < from control interface */
.pc(pc) /* < to control interface */
);
wire start;
wire busy;
pfpu_seq seq(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.alu_rst(alu_rst), /* < to ALU */
.dma_en(dma_en), /* < from ALU */
.dma_busy(dma_busy), /* < from DMA engine */
.dma_ack(dma_ack), /* < from DMA engine */
.vfirst(vfirst), /* < to counters */
.vnext(vnext), /* < to counters and control interface */
.vlast(vlast), /* < from counters */
.pcount_rst(pcount_rst), /* < to program memory */
.c_en(c_en), /* < to register file and program memory */
.start(start), /* < from control interface */
.busy(busy) /* < to control interface */
);
pfpu_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.start(start), /* < to sequencer */
.busy(busy), /* < from sequencer */
.dma_base(dma_base), /* < to DMA engine */
.hmesh_last(hmesh_last), /* < to counters */
.vmesh_last(vmesh_last), /* < to counters */
.cr_addr(cr_addr), /* < to register file */
.cr_di(cr_dr), /* < from register file */
.cr_do(cr_dw), /* < to register file */
.cr_w_en(cr_w_en), /* < to register file */
.cp_page(cp_page), /* < to program memory */
.cp_offset(cp_offset), /* < to program memory */
.cp_di(cp_dr), /* < from program memory */
.cp_do(cp_dw), /* < to program memory */
.cp_w_en(cp_w_en), /* < to program memory */
.vnext(vnext), /* < from sequencer */
.err_collision(err_collision), /* < from ALU */
.err_stray(err_stray), /* < from register file */
.pc(pc), /* < from program memory */
.wbm_adr_o(wbm_adr_o), /* < from DMA engine */
.wbm_ack_i(wbm_ack_i) /* < from DMA engine */
);
endmodule
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#include <bits/stdc++.h> // #include <ext/pb_ds/assoc_container.hpp> // #include <ext/pb_ds/tree_policy.hpp> using namespace std; // using namespace __gnu_pbds; #define lli long long int #define llu unsigned long long int #define pb push_back #define rt return 0 #define endln n #define all(x) x.begin(), x.end() #define sz(x) (lli)(x.size()) const lli MOD = 1e9 + 7; const double PI = 2 * acos(0.0); // cout << fixed << setprecision(0) << pi <<endl; // typedef tree<int, null_type, less<int>, rb_tree_tag, // tree_order_statistics_node_update> // new_data_set; // for multiset // typedef tree<int, null_type, less_equal<int>, rb_tree_tag, // tree_order_statistics_node_update> // new_data_set; // order_of_key(val): returns the number of values less than val // find_by_order(k): returns an iterator to the kth largest element (0-based) void solve() { lli n, a; cin >> n >> a; cout << n - 1 << << a << endl; } int main(void) { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); lli t; cin >> t; while (t--) solve(); rt; }
|
`timescale 1ns / 1ps
module spi_trx_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg sck;
parameter TCLK_SCK = 55;
reg mosi;
reg ss;
reg [7:0] data_i;
reg ack_i;
spi_trx uut(
.clk(clk),
.sck(sck),
.mosi(mosi),
.ss(ss),
.data_i(data_i),
.ack_i(ack_i));
task spi_cycle;
input wire [7:0] data;
begin
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
end
endtask
initial begin
$dumpfile("spi_trx_t.lxt");
$dumpvars(0, spi_trx_t);
sck = 0;
mosi = 0;
ss = 1;
ack_i = 0;
#(TCLK*3);
data_i = 8'b10101011;
ack_i = 1;
#(TCLK);
ack_i = 0;
#(TCLK);
ss = 0;
spi_cycle(8'hab);
spi_cycle(8'hcd);
spi_cycle(8'hef);
#(TCLK*3);
$finish(2);
end
always @(posedge clk) begin
if(uut.ack_pop_o)
$display("uut.data_o: %x", uut.data_o);
end
endmodule
|
module ALU_bit_tb;
reg [8:0]test_vector;
// all input signals will be mapped to the test_vector reg
// thus the DUT input signals themselves will just be wires
wire [4:0]FS;
wire A, B, C_in, A_from_next_bit;
wire not_A, not_B;
// not_A and not_B required for arithmetic functions because behavioral Verilog
// can promote the bit width of an operator before using it thus (~A) could be
// promoted to two bits and become 11 (if A is 0) instead of 01
// However, not_A in the case above would be 1 so when it is promoted it becomes 01.
// This all happens because Verilog promotes the bit width of all operators to match
// the destination (an for the arithmetic cases the destination is two bits in this testbench)
assign not_A = ~A;
assign not_B = ~B;
// define DUT outputs as wires
wire F;
wire C_out;
// Since the test vector is 9 bits we have 512 possible input scenarios to test
// manually checking all 512 scenarios will be tedious so instead we will
// create a better test bench which can check each scenario automatically
// and just notify us of the scenarios which produce "unexpected" results
// define expected value registers
reg F_exp, C_out_exp;
// map the 9 test_vector bits to the 9 input bits
assign {FS, A, B, C_in, A_from_next_bit} = test_vector;
// reminder: {a, b, c} is the syntax for concatinating signals together
// create an instance of the Design Under Test
//ALU_bit (S, A, B, F, C_in, A_from_next_bit, C_out)
ALU_Cell_1bit dut (
.FS (FS),
.A (A),
.B (B),
.F (F),
.C_out (C_out),
.C_in (C_in),
.A_from_next_bit (A_from_next_bit)
);
// If a DUT error is detected it is important to analize whether the expected value
// or the actual value is wrong as it is possible that your test bench is incorrect
initial
begin
// initialize the test_vector to 0
test_vector = 9'b0;
forever
begin
// increment the test_vector
#1 test_vector = test_vector + 9'b1;
// do nothing for one tic
#1 test_vector <= test_vector; // the purpose of this is so we end up checking the expected vs. actual in the middle of the 4 tic period
// check if the ALU expected output matches the actual output
if(F_exp != F) begin
$display("DUT error at time %d", $time);
$display("Expected F = %b, actual = %b, inputs FS=%b,A=%b,B=%b,C_in=%b,A_from_next_bit=%b",
F_exp, F, FS, A, B, C_in, A_from_next_bit);
end
// if the Function Select is arithmetic/shift then check if the actual C_out matches the expected value
if(FS[4]) begin
if(C_out_exp != C_out) begin
$display("DUT error at time %d", $time);
$display("Expected C_out = %b, actual = %b, inputs FS=%b,A=%b,B=%b,C_in=%b,A_from_next_bit=%b",
C_out_exp, C_out, FS, A, B, C_in, A_from_next_bit);
end
end
// do nothing for two more tics before going to the next test case
#2 test_vector <= test_vector;
end
end
// use behavioral Verilog to calculate the expected values for F and C_out
always @(test_vector) begin
// casex treats x as don't care instead of looking for the input to the case to have an actual x value
casex(FS)
5'b00000: F_exp <= 4'b0;
5'b00001: F_exp <= (~A)&(~B);
5'b00010: F_exp <= ~A & B;
5'b00011: F_exp <= ~A;
5'b00100: F_exp <= A & ~B;
5'b00101: F_exp <= ~B;
5'b00110: F_exp <= A^B;
5'b00111: F_exp <= ~(A & B);
5'b01000: F_exp <= A&B;
5'b01001: F_exp <= ~(A^B);
5'b01010: F_exp <= B;
5'b01011: F_exp <= ~A | B;
5'b01100: F_exp <= A;
5'b01101: F_exp <= A | ~B;
5'b01110: F_exp <= A|B;
5'b01111: F_exp <= 4'b1;
// for the arithmetic operations the result will be two bits so map it to {C_out_exp, F_exp}
5'b10000: {C_out_exp, F_exp} <= {A & C_in, A+C_in};
5'b10001: {C_out_exp, F_exp} <= {not_A & C_in, not_A+C_in}; // not_A must be used instead of ~A because A gets promoted to 2 bits so if A=0 then ~A is 11 instead of 01 as desired
5'b10010: {C_out_exp, F_exp} <= {A |C_in, A + C_in + 4'b1};//LAB fill in the behavioral arithmetic equations for the expected F value
5'b10011: {C_out_exp, F_exp} <= {~A | C_in, not_A + C_in + 4'b1};
5'b10100: {C_out_exp, F_exp} <= {A&(C_in | B) | B&C_in, A + B + C_in};
5'b10101: {C_out_exp, F_exp} <= {not_A&(C_in | B) | B&C_in, not_A + B + C_in};
5'b10110: {C_out_exp, F_exp} <= {A&(not_B|C_in) | not_B&C_in, A + not_B + C_in};
5'b10111: {C_out_exp, F_exp} <= {not_A&(not_B|C_in) | not_B&C_in, not_A + not_B + C_in}; // USELESS
5'b11xx0: {C_out_exp, F_exp} <= {A, C_in};
5'b11xx1: {C_out_exp, F_exp} <= {A, A_from_next_bit};//LAB use a concatination as above to implement
endcase
end
// after (period)*(num test cases) every input scenario will have been tested
initial
#2048 $finish;
endmodule
|
#include <bits/stdc++.h> int II() { int n; scanf( %d , &n); return n; } void II(int n) { printf( %d , n); } void IIn(int n) { printf( %d n , n); } void IIb(int n) { printf( %d , n); } long long int LL() { long long int n; scanf( %lld , &n); return n; } void LL(long long int n) { printf( %lld , n); } void LLn(long long int n) { printf( %lld n , n); } void LLb(long long int n) { printf( %lld , n); } char CC() { return getchar(); } char CCa() { char c = getchar(); while (c <= 32) c = getchar(); return c; } void CC(char c) { putchar(c); } void CCn(char c) { putchar(c); putchar(10); } void CCb(char c) { putchar(c); putchar(32); } void CCn() { putchar(10); } void CCb() { putchar(32); } void SS(char *s) { scanf( %s , s); } void SSb(const char *s) { printf( %s , s); } void SSn(const char *s) { printf( %s n , s); } float FF() { float n; scanf( %f , &n); return n; } void FF(float n) { printf( %f , n); } void FFn(float n) { printf( %f n , n); } void FFb(float n) { printf( %f , n); } void FF(double n, int prec) { std::cout << std::setprecision(prec) << n; } void FFn(double n, int prec) { std::cout << std::setprecision(prec) << n; putchar(10); } void FFb(double n, int prec) { std::cout << std::setprecision(prec) << n; putchar(32); } struct node { int val; int prio; int subsize; bool flagrotate; node *left, *right; node() { prio = rand(); subsize = 1; flagrotate = false; left = right = NULL; } void clean() { if (flagrotate) { flagrotate = false; std::swap(left, right); if (left) left->flagrotate ^= 1; if (right) right->flagrotate ^= 1; } } void assest() { subsize = 1 + (left ? left->subsize : 0) + (right ? right->subsize : 0); } }; typedef node *tree; tree merge(tree A, tree B) { if (!A) return B; if (!B) return A; A->clean(); B->clean(); if (A->prio > B->prio) { A->right = merge(A->right, B); A->assest(); return A; } else { B->left = merge(A, B->left); B->assest(); return B; } } void print(tree x, int d = 0) { if (!x) return; x->clean(); print(x->left, d + 1); IIb(x->val); print(x->right, d + 1); } std::pair<tree, tree> split(tree x, int k) { if (!x) return {NULL, NULL}; x->clean(); int sl = x->left ? x->left->subsize : 0; if (k <= sl) { std::pair<tree, tree> r = split(x->left, k); x->left = r.second; x->assest(); return {r.first, x}; } k -= sl; --k; std::pair<tree, tree> r = split(x->right, k); x->right = r.first; x->assest(); return {x, r.second}; } int nth(tree x, int p) { x->clean(); int sl = x->left ? x->left->subsize : 0; if (sl == p) return x->val; if (sl > p) return nth(x->left, p); return nth(x->right, p - sl - 1); } constexpr int MAXN = 200000; node V[MAXN]; int main() { int N = II(), Q = II(), M = II(); for (int x = 0; x < N; x++) V[x].val = II(); tree T = NULL; for (int x = 0; x < N; x++) T = merge(T, V + x); while (Q--) { if (II() == 1) { int l = II() - 1, r = II(); std::pair<tree, tree> A = split(T, r); std::pair<tree, tree> B = split(A.first, l); std::pair<tree, tree> C = split(B.second, B.second->subsize - 1); T = merge(merge(B.first, C.second), merge(C.first, A.second)); } else { int l = II() - 1, r = II(); std::pair<tree, tree> A = split(T, r); std::pair<tree, tree> B = split(A.first, l); B.second->flagrotate ^= 1; T = merge(merge(B.first, B.second), A.second); } } while (M--) IIb(nth(T, II() - 1)); CCn(); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T; cin >> T; while (T-- > 0) { long long n, k; cin >> n >> k; int m; for (m = 2; m <= n; m++) { if (n % m == 0) break; } long long ans = n + m + (k - 1) * 2; cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long in() { int32_t x; scanf( %d , &x); return x; } inline long long lin() { long long x; scanf( %lld , &x); return x; } inline string get() { char ch[2000010]; scanf( %s , ch); return ch; } inline void read(long long *a, long long n) { for (long long i = 0; i < n; i++) a[i] = in(); } template <class blank> inline void out(blank x) { cout << x << n ; exit(0); } const long long maxn = 1e5 + 10; const long long maxm = 1e6 + 10; const long long maxlg = 20; const long long base = 29; const long long base2 = 31; const long long mod2 = 1e9 + 9; const long long mod = 1e9 + 7; const long long INF = 1e18 + 10; const long long SQ = 317 + 5; vector<pair<long long, long long> > g[maxn]; bool mark[maxn]; long long where[maxn]; long long cur = 1; long long n, m; vector<long long> adj[maxn]; vector<long long> vertices[maxn]; long long cnt[maxn], has[maxn]; long long root[maxn][maxlg]; bool cut[maxn]; long long h[maxn], l[maxn]; long long pre[maxn]; inline void tarjan(long long node, long long fa = 0) { h[node] = l[node] = (fa ? h[fa] + 1 : 0); pre[node] = fa; mark[node] = true; for (auto u : g[node]) { if (!mark[u.first]) { tarjan(u.first, node); l[node] = min(l[node], l[u.first]); if (l[u.first] > h[node]) cut[u.second] = true; } else if (u.first != fa && h[u.first] < h[node]) { for (long long V = node; V != pre[u.first]; V = pre[V]) { vertices[cur].push_back(V); where[V] = cur + n; } cur++; } if (u.first != fa) { l[node] = min(l[node], h[u.first]); if (l[u.first] > h[node]) cut[u.second] = true; } } } inline void dfs(long long node, long long fa = 0) { cnt[node] += cnt[fa]; root[node][0] = fa; for (long long i = 1; i < maxlg; i++) root[node][i] = root[root[node][i - 1]][i - 1]; for (auto u : adj[node]) { if (u - fa) { h[u] = h[node] + 1; dfs(u, node); } } } long long pr[maxn]; inline long long Root(long long v) { return pr[v] == v ? v : pr[v] = Root(pr[v]); } inline void merge(long long v, long long u) { v = Root(v), u = Root(u); pr[v] = u; } inline long long lca(long long p, long long q) { if (h[p] < h[q]) swap(p, q); for (long long i = maxlg - 1; i >= 0; i--) if (h[p] - (1 << i) >= h[q]) p = root[p][i]; if (p == q) return p; for (long long i = maxlg - 1; i >= 0; i--) if (root[p][i] != root[q][i]) p = root[p][i], q = root[q][i]; return root[p][0]; } inline long long CNT(long long v, long long u) { long long LCA = lca(v, u); return cnt[v] + cnt[u] - 2 * cnt[LCA] + has[LCA]; } long long pw[maxn]; pair<long long, long long> e[maxn]; int32_t main() { pw[0] = 1; for (long long i = 1; i < maxn; i++) pw[i] = pw[i - 1] * 2 % mod; n = in(), m = in(); for (long long i = 1; i <= n; i++) pr[i] = where[i] = i; for (long long i = 0; i < m; i++) { long long v = in(), u = in(); g[v].push_back({u, i}); g[u].push_back({v, i}); merge(v, u); e[i] = {v, u}; } tarjan(1); memset(h, 0, sizeof h); for (long long i = 0; i < m; i++) if (cut[i]) { adj[where[e[i].first]].push_back(where[e[i].second]), adj[where[e[i].second]].push_back(where[e[i].first]); } for (long long i = 1; i < cur; i++) { for (auto v : vertices[i]) adj[v].push_back(i + n), adj[i + n].push_back(v); } for (long long i = 1; i < cur; i++) cnt[i + n] = 1, has[i + n] = true; dfs(1); long long q = in(); while (q--) { long long v = in(), u = in(); cout << pw[CNT(v, u)] << n ; } }
|
/* -----------------------------------------------------------------------
*
* Copyright 2004,2007 Tommy Thorn - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
* Bostom MA 02111-1307, USA; either version 2 of the License, or
* (at your option) any later version; incorporated herein by reference.
*
* -----------------------------------------------------------------------
*
*
* Block ram controller
*/
`timescale 1ns/10ps
`include "pipeconnect.h"
module blockram
(input wire clock
,input wire rst
,output mem_waitrequest
,input [1:0] mem_id
,input [29:0] mem_address
,input mem_read
,input mem_write
,input [31:0] mem_writedata
,input [3:0] mem_writedatamask
,output [31:0] mem_readdata
,output reg [1:0] mem_readdataid = 0
);
parameter burst_bits = 2;
parameter size = 18; // 4 * 2^18 = 1 MiB
parameter INIT_FILE = "";
parameter burst_length = 1 << burst_bits;
wire sel = mem_address[29:26] == 'h4;
reg [burst_bits:0] cnt = ~0;
reg [size-1:0] read_address = 0;
assign mem_waitrequest = !cnt[burst_bits];
dpram memory(.clock(clock),
.address_a(mem_waitrequest
? read_address
: mem_address[size-1:0]),
.byteena_a(mem_writedatamask),
.wrdata_a(mem_writedata),
.wren_a(!mem_waitrequest & sel & mem_write),
.rddata_a(mem_readdata),
.address_b(0),
.byteena_b(0),
.wrdata_b(0),
.wren_b(0),
.rddata_b());
defparam
memory.DATA_WIDTH = 32,
memory.ADDR_WIDTH = size,
memory.INIT_FILE = INIT_FILE;
always @(posedge clock)
if (mem_waitrequest) begin
cnt <= cnt - 1;
read_address <= read_address + 1;
end else begin
mem_readdataid <= 0;
if (sel & mem_read) begin
read_address <= mem_address[size-1:0] + 1;
mem_readdataid <= mem_id;
cnt <= burst_length - 2;
end
end
`define DEBUG_BLOCKRAM 1
`ifdef DEBUG_BLOCKRAM
always @(posedge clock) begin
if (!mem_waitrequest & sel & mem_read)
$display("%05d blockram[%x] -> ? for %d", $time,
{mem_address,2'd0}, mem_id);
if (!mem_waitrequest & sel & mem_write)
$display("%05d blockram[%x] <- %8x/%x", $time,
{mem_address,2'd0}, mem_writedata, mem_writedatamask);
if (mem_readdataid)
$display("%05d blockram[%x] -> %8x for %d", $time,
32'h3fff_fffc + (read_address << 2), mem_readdata, mem_readdataid);
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, j, k, n, m, an; int f[(1 << 20)], h[(1 << 20)]; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &k), f[k]++; m = (1 << 20) - 1; for (i = 0; i <= 19; i++) for (j = 0; j <= m; j++) if (!(j & (1 << i))) f[j] += f[j | (1 << i)]; h[0] = 1; for (i = 1; i <= (1 << 20) - 1; i++) h[i] = h[i - 1] * 2 % 1000000007; for (i = 0; i <= m; i++) { int s = 0; for (j = 0; j <= 19; j++) s += i >> j & 1; if (f[i]) an = ((s & 1 ? -1 : 1) * (h[f[i]] - 1) + an) % 1000000007; } if (an < 0) an += 1000000007; printf( %d n , an); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char arr[4][4], a; for (int i = 0; i < 4; i++) { for (int j = 0; j < 4; j++) { cin >> a; arr[i][j] = a; } } for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { if (arr[i][j] == # && arr[i][1 + j] == # && (arr[1 + i][j] == # || arr[i + 1][1 + j] == # ) || (arr[i][j] == # || arr[i][1 + j] == # ) && arr[1 + i][j] == # && arr[i + 1][1 + j] == # ) { cout << YES ; return 0; } else if (arr[i][j] == . && arr[i][1 + j] == . && (arr[1 + i][j] == . || arr[i + 1][1 + j] == . ) || (arr[i][j] == . || arr[i][1 + j] == . ) && arr[1 + i][j] == . && arr[i + 1][1 + j] == . ) { cout << YES ; return 0; } } } cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long INF = 9e18; const int inf = 2147483647; long long phi(long long n) { long long ans = n; for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { ans = ans / i * (i - 1); while (n % i == 0) n /= i; } } if (n > 1) ans = ans / n * (n - 1); return ans; } long long qpow(long long a, long long b, long long mod) { long long r = 1; for (; b; b >>= 1) { if (b & 1) r = (r * a) % mod; a = (a * a) % mod; } return r; } long long C(int n, int m) { if (m < n - m) m = n - m; long long ans = 1; for (int i = m + 1; i <= n; i++) ans *= i; for (int i = 1; i <= n - m; i++) ans /= i; return ans; } const int N = 2e5 + 5; int look(int a, int x) { int q = sqrt(x + 0.5); int ans = inf; for (int i = 2; i <= q; i++) { if (x % i == 0) { int j = x / i; if (abs(i - a) < abs(j - a)) { if (abs(ans - a) > abs(i - a)) { ans = i; } } else { if (abs(ans - a) > abs(j - a)) { ans = j; } } } } if (ans >= inf) { if (abs(1 - a) < abs(x - a)) { ans = 1; } else { ans = x; } } else { if (abs(ans - a) > abs(1 - a)) { ans = 1; } if (abs(ans - a) > abs(x - a)) { ans = x; } } return ans; } void work() { int t; scanf( %d , &t); while (t--) { int a, b, c; scanf( %d%d%d , &a, &b, &c); int ta, tc; int ans = inf; int as[5]; for (int i = 1; i <= (int)2e4; i++) { int tb = i; if (tb > a) { ta = look(a, tb); } else { ta = tb; } if (c > tb) { int t1 = c / tb; int xc = t1 * tb, dc = (t1 + 1) * tb; if (abs(c - xc) < abs(c - dc)) { tc = xc; } else { tc = dc; } } else { tc = tb; } int cnt1 = abs(a - ta), cnt2 = abs(b - tb), cnt3 = abs(c - tc); if (cnt1 + cnt2 + cnt3 < ans) { ans = cnt1 + cnt2 + cnt3; as[0] = ta, as[1] = tb, as[2] = tc; } } printf( %d n , ans); for (int i = 0; i < 3; ++i) { printf( %d , as[i]); } puts( ); } } int main() { work(); return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON128_NEXT 5'b0_0001
`define S_TXPORTMON128_TXN 5'b0_0010
`define S_TXPORTMON128_READ 5'b0_0100
`define S_TXPORTMON128_END_0 5'b0_1000
`define S_TXPORTMON128_END_1 5'b1_0000
`timescale 1ns/1ns
module tx_port_monitor_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [4:0] rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE4Lo=0, _rLenLE4Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON128_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON128_READ
assign TXN = rState[1]; // S_TXPORTMON128_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[2]; // !S_TXPORTMON128_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON128_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_TXN;
end
`S_TXPORTMON128_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON128_END_0 : `S_TXPORTMON128_READ);
end
`S_TXPORTMON128_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON128_END_0;
end
`S_TXPORTMON128_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
end
`S_TXPORTMON128_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_NEXT;
end
default: begin
_rState = `S_TXPORTMON128_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE4Lo <= #1 _rLenLE4Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[63:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 4, we want to trigger the almost all received flag
_rLenLE4Lo = (LEN[15:0] <= 16'd4);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<2));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<2));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({201'd0,
rWordsRecvd, // 32
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 129
rState}) // 5
);
*/
endmodule
|
// Single-bit clock-domain crossing synchronizer
//
// Notes:
// A synchronizer is a device that takes an asynchronous
// input and produces an output signal that transitions
// synchronous to a sample clock
//
// The single-bit clock domain synchronizer safely
// transfers the output from clock domain A to
// clock domain B. Without the synchronizer, the
// input of the receiving clock domain can go
// metastable at the first register stage of the
// sampling domain. A good synchronizer
// removes the probability of input going metastable
// by moving the input through register stages in
// the target clock domain
//
// Mean Time Between Failures defines the probability
// of the o/p of the sampling domain going metastable.
// MTBF = 1/(freq of sampling * freq of data change *X)
// Higher MTBF, the better
// As freq of sampling increases, probability of metastability
// is higher (lower MTBF)
//
// It is generally recommended that the output of the
// launching clock domain is registered before synchronizing.
// Consider the case where a signal is derived through some
// combinational logic before getting transfered from clock
// domain A to B. The probability of glitching after the
// combinational logic is very high, which in turn increases
// probability of metastability at the latching clock domain.
//
// The synchronizer may be used in different scenarios
// - Case 1: Transfer from slow clock domain to fast
// - Case 2: Transfer from fast clock domain to slow
// - Case 3: Transfer b/w unrelated clocks with same frequency,
//
// Case 1 is the most straightforward. A CDC with >=2 stages is
// sufficient. Case 2 is tricky because the launch data can
// change multiple times before capturing in the latching domain.
// In this situation, it is recommended that either the launch clock
// hold the data for at-least 3 clock cycles of the latch
// clock domain (open-loop solution) or hold the data until
// the latch domain sends back an acknowledgment (closed-loop
// solution).
//
module single_bit_cdc_synchronizer #(
parameter NUM_STAGES = 3 // minimum 2 stages, recommended 3 stages
// probability of metastability decreases
// exponentially with #stages
) (
input clk, //latch clock
input d_in,
output q_out;
);
reg[NUM_STAGES-1:0] r;
assign q_out=r[NUM_STAGES-1];
integer i;
always@(posedge latch_clk)
begin
for(i=1; i<NUM_STAGES; i=i+1) begin
r[i] <= r[i-1];
end
end
endmodule
|
`timescale 1ns/1ps
`default_nettype none
module test;
localparam NUM_FF = 4;
`include "../../../../library/tbassert.v"
reg clk = 0;
reg rx = 1;
reg [13:0] sw = 0;
reg ce = 0;
reg sr = 0;
wire tx;
wire [15:0] led;
// clock generation
always #1 clk=~clk;
top unt(
.clk(clk),
.rx(rx),
.tx(tx),
.sw({sr, ce, sw}),
.led(led)
);
wire [4*NUM_FF-1:0] D;
wire [NUM_FF-1:0] Q_vcc_gnd;
wire [NUM_FF-1:0] Q_s_gnd;
wire [NUM_FF-1:0] Q_s_s;
wire [NUM_FF-1:0] Q_vcc_s;
assign Q_vcc_gnd[0] = led[0];
assign Q_s_gnd[0] = led[1];
assign Q_s_s[0] = led[2];
assign Q_vcc_s[0] = led[3];
assign Q_vcc_gnd[1] = led[4];
assign Q_vcc_gnd[NUM_FF-1] = led[5];
assign Q_s_gnd[NUM_FF-1] = led[6];
assign Q_s_s[NUM_FF-1] = led[7];
assign Q_vcc_s[NUM_FF-1] = led[8];
wire xorQ = led[9];
wire orQ = led[10];
wire andQ = led[11];
genvar i;
generate for(i = 0; i < NUM_FF; i=i+1) begin:ff
assign D[4*i+0] = sw[(4*i+0) % 14];
assign D[4*i+1] = sw[(4*i+1) % 14];
assign D[4*i+2] = sw[(4*i+2) % 14];
assign D[4*i+3] = sw[(4*i+3) % 14];
end endgenerate
wire xorD = ^D;
wire orD = |D;
wire andD = &D;
always begin
#1
$monitor("1:%d %d %d %d %d %d %d %d %d %d %d %d %d", $time, clk, sw[14], led[0], led[1], led[2], led[3], led[9], xorD, led[10], orD, led[11], andD);
end
initial begin
$dumpfile("testbench_ff_ce_sr_4_tb.vcd");
$dumpvars;
#1.1 // 1
tbassert(clk, "Clock!");
tbassert(!Q_vcc_gnd[0], "!Q_vcc_gnd[0]");
tbassert(!Q_s_gnd[0], "!Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(!xorQ, "^Q == 0");
tbassert(!orQ, "|Q == 0");
tbassert(!andQ, "&Q == 0");
tbassert(xorQ == xorD, "^Q == xorD");
// Test CE
#1 // 2
tbassert(!clk, "Clock!");
sw[0] = 1;
sw[1] = 1;
sw[2] = 1;
sw[3] = 1;
#1 // 3
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(!Q_s_gnd[0], "!Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 4
ce = 1;
#1 // 5
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 6
ce = 0;
sw[0] = 0;
sw[1] = 0;
sw[2] = 0;
sw[3] = 0;
#1 // 7
tbassert(!Q_vcc_gnd[0], "!Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 8
ce = 1;
#1 // 9
tbassert(!Q_vcc_gnd[0], "!Q_vcc_gnd[0]");
tbassert(!Q_s_gnd[0], "!Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(!orQ, "|Q == 0");
tbassert(!andQ, "&Q == 0");
// Test SR
#1 // 10
sw[0] = 1;
sw[1] = 1;
sw[2] = 1;
sw[3] = 1;
#1 // 11
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 12
sr = 1;
#1 // 13
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 14
ce = 0;
sr = 0;
#1 // 15
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 16
ce = 1;
#1 // 17
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 18
sw[13:0] = 14'b11_1111_1111_1111;
#1 // 19
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(Q_vcc_gnd[1], "Q_vcc_gnd[1]");
tbassert(Q_vcc_gnd[NUM_FF-1], "Q_vcc_gnd[-1]");
tbassert(Q_s_gnd[NUM_FF-1], "Q_s_gnd[-1]");
tbassert(Q_s_s[NUM_FF-1], "Q_s_s[-1]");
tbassert(Q_vcc_s[NUM_FF-1], "Q_vcc_s[-1]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(andQ, "&Q == 1");
#1 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int dig(long long int n) { long long int r = 0; while (n) { ++r; n = n / 10; } return (r - 1); } long long int func(long long int n) { if (n <= 9) return (n + 1); long long int lt = dig(n); lt = pow(10, lt); long long int ret = lt - 1; long long int mul = ret / 10; long long int mid = (n % lt) / 10; lt = n / lt; long long int rt = n % 10; if (rt >= lt) { return (lt * (mul + 1) + func(ret)); } else { return (lt * (mul + 1) + func(ret)); } } long long int fun(long long int n) { if (n <= 9) return (n + 1); long long int lt = dig(n); lt = pow(10, lt); long long int ret = lt - 1; long long int mul = ret / 10; long long int mid = (n % lt) / 10; lt = n / lt; long long int rt = n % 10; if (rt >= lt) { return ((mid + 1) + (lt - 1) * (mul + 1) + func(ret)); } else { return (mid + (lt - 1) * (mul + 1) + func(ret)); } } int main() { long long int l, r; cin >> l >> r; cout << fun(r) - fun(l - 1); return 0; }
|
`timescale 1ns / 1ps
module pixelGeneration(clk, rst, push, switch, pixel_x, pixel_y, video_on, rgb);
input clk, rst;
input [3:0] push;
input [2:0] switch;
input [9:0] pixel_x, pixel_y;
input video_on;
output reg [2:0] rgb;
wire square_on, refr_tick;
//define screen size max values.
localparam MAX_X = 640;
localparam MAX_Y = 480;
//define square size and square velocity
localparam SQUARE_SIZE = 40;
localparam SQUARE_VEL = 5;
//boundaries of the square
wire [9:0] square_x_left, square_x_right, square_y_top, square_y_bottom;
reg [9:0] square_y_reg, square_y_next;
reg [9:0] square_x_reg, square_x_next;
//registers
always @(posedge clk) begin
if(rst) begin
square_y_reg <= 240;
square_x_reg <= 320;
end
else begin
square_y_reg <= square_y_next;
square_x_reg <= square_x_next;
end
end
//check screen refresh
assign refr_tick = (pixel_y ==481) && (pixel_x ==0);
//boundary circuit: assign stored values of y_top and x_left and calculate the y_bottom and x_right values by adding square size.
assign square_y_top = square_y_reg;
assign square_x_left = square_x_reg;
assign square_y_bottom = square_y_top + SQUARE_SIZE - 1;
assign square_x_right = square_x_left + SQUARE_SIZE - 1;
//rgb circuit
always @(*) begin
rgb = 3'b000;
if(video_on) begin
if(square_on)
rgb = switch;
else
rgb = 3'b110;
end
end
assign square_on = ((pixel_x > square_x_left) && (pixel_x < square_x_right)) && ((pixel_y > square_y_top) && (pixel_y < square_y_bottom));
//object animation circuit
always @(*) begin
square_y_next = square_y_reg;
square_x_next = square_x_reg;
if(refr_tick) begin
if (push[0] && (square_x_right < MAX_X - 1)) begin // make sure that it stays on the screen
square_x_next = square_x_reg + SQUARE_VEL; // right
end
else if (push[1] && (square_x_left > 1 )) begin
square_x_next = square_x_reg - SQUARE_VEL; // left
end
else if (push[2] && (square_y_bottom < MAX_Y - 1 )) begin
square_y_next = square_y_reg + SQUARE_VEL; // down
end
else if (push[3] && (square_y_top > 1)) begin
square_y_next = square_y_reg - SQUARE_VEL; // up
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; const int MOD = (int)1e9 + 7; const int N = (int)1e6 + 7; int n, k; int a[N], bit[N]; map<int, int> cnt[11]; long long dp[N][11]; void Init() { for (int i = (1); i < (11); ++i) cnt[i].clear(); for (int i = (0); i < (n); ++i) scanf( %d , a + i); for (int i = (0); i < (n); ++i) { int x = a[i]; bit[i] = 0; while (x) { bit[i]++; x /= 10; } } } int Solve() { for (int i = (0); i < (n); ++i) { cnt[bit[i]][a[i] % k]++; dp[i][0] = a[i] % k; for (int j = (1); j < (11); ++j) dp[i][j] = dp[i][j - 1] * 10 % k; } long long ans = 0; for (int i = (0); i < (n); ++i) { for (int j = (1); j < (11); ++j) { if (bit[i] == j && (dp[i][j] + a[i]) % k == 0) --ans; int t = k - dp[i][j] != k ? k - dp[i][j] : 0; if (cnt[j].count(t)) ans += cnt[j][t]; } } return !printf( %lld n , ans); } int main() { while (~scanf( %d%d , &n, &k)) { Init(); Solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int tree[500000]; int a[100000], pos[100001]; void update(int node, int l, int r, int pos, int u) { if (l == r) { tree[node] += u; return; } int mid = (l + r) / 2; if (pos <= mid) update(2 * node, l, mid, pos, u); else update(2 * node + 1, mid + 1, r, pos, u); tree[node] = tree[2 * node] + tree[2 * node + 1]; } int query(int node, int l, int r, int ql, int qr) { if (ql > r || qr < l) return 0; if (ql <= l && qr >= r) return tree[node]; int mid = (l + r) / 2; return query(2 * node, l, mid, ql, qr) + query(2 * node + 1, mid + 1, r, ql, qr); } int main() { int i, j, k; int n, res = 0; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < n; i++) { scanf( %d , &j); pos[j] = i; } for (i = 0; i < n; i++) { if (query(1, 0, n, pos[a[i]] + 1, n)) res++; update(1, 0, n, pos[a[i]], 1); } printf( %d , res); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_SYMBOL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s25 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 2 * 1e6 + 10; long long a[maxn], b[maxn], q[maxn], sz[maxn], n; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return x * f; } long long b1, b2, n1; signed main() { n = read(); long long p = 0; for (long long i = 1; i <= n; i++) { a[i] = read(); if (a[i] > a[p]) p = i; if (a[i] > b1) b2 = b1, b1 = a[i], n1 = 1; else if (a[i] == b1) n1++; else if (a[i] > b2) b2 = a[i]; } for (long long i = 1; i <= n; i++) b[i] = a[(i + p - 1) % n + 1]; long long l = 1, r = 0, ans = 0; for (long long i = 1; i <= n; i++) { while (l <= r && b[i] > b[q[r]]) r--, ans++; if (r >= l) { if (b[i] == b[q[r]]) ans += min(r, sz[r] + 1); else ans++; } q[++r] = i; if (b[i] == b[q[r - 1]]) sz[r] = sz[r - 1] + 1; else sz[r] = 1; } p = 0; for (long long i = 1; i < n; i++) if (b[i] >= b[p]) { p = i; if (n1 > 1 && b[p] == b1) ; else if (n1 == 1 && b[p] == b2) ; else ans++; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int n, t, sz[200010], cen; vector<int> g[200010], v; bool mark[200010]; int dfs(int pos, int par) { sz[pos] = (int)mark[pos]; bool ok = true; for (int i = 0; i < g[pos].size(); i++) if (g[pos][i] != par) { sz[pos] += dfs(g[pos][i], pos); if (sz[g[pos][i]] > t) ok = false; } if (ok && sz[pos] >= t) cen = pos; return sz[pos]; } void dfs2(int pos, int par) { if (mark[pos]) v.push_back(pos); for (int i = 0; i < g[pos].size(); i++) if (g[pos][i] != par) dfs2(g[pos][i], pos); } int main() { cin >> n >> t; int x, y; for (int i = 0; i < n - 1; i++) { scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } for (int i = 0; i < t + t; i++) { scanf( %d , &x); mark[x] = true; } dfs(1, 0); for (int i = 0; i < g[cen].size(); i++) dfs2(g[cen][i], cen); if (mark[cen]) v.push_back(cen); cout << 1 << endl << cen << endl; for (int i = 0; i < t; i++) printf( %d %d %d n , v[i], v[i + t], cen); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, s, q, nr = 0; scanf( %d%d%d , &t, &s, &q); while (s < t) { nr++; s += s * (q - 1); } printf( %d , nr); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 11:25:26
// Design Name:
// Module Name: lab5_2_1_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_2_1_tb(
);
reg [1:0] ain;
reg clk,reset;
wire yout;
lab5_2_1 dut(ain,clk,reset,yout);
initial
begin
for(clk = 0;clk >= 0;clk = clk + 1)
begin
#5;
end
end
initial
begin
ain = 0;reset = 1;
#20 reset = 0;
#20 ain = 3;
#10 ain = 2;
#10 ain = 0;
#20 ain = 2;
#10 ain = 0;
#10 ain = 3;
#10 ain = 0;
#10 ain = 1;
#10 ain = 0;
#10 ain = 2;
#10 ain = 3;
#10 ain = 0;
#10 reset = 1;
#10 reset = 0;
#10 ain = 2;
end
endmodule
|
/**
* bsg_lru_pseudo_tree_encode.v
*
* Pseudo-Tree-LRU encode unit.
* Given the LRU bits, traverses the pseudo-LRU tree and returns the
* LRU way_id.
* Only for power-of-2 ways.
*
* --------------------
* Example (ways_p=8)
* --------------------
* lru_i way_id_o
* ----- --------
* xxx_0x00 0
* xxx_1x00 1
* xx0 xx10 2
* xx1 xx10 3
* x0x x0x1 4
* x1x x0x1 5
* 0xx x1x1 6
* 1xx x1x1 7
* --------------------
* 'x' means don't care.
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_lru_pseudo_tree_encode
#(parameter `BSG_INV_PARAM(ways_p)
, parameter lg_ways_lp = `BSG_SAFE_CLOG2(ways_p)
)
(
input [`BSG_SAFE_MINUS(ways_p, 2):0] lru_i
, output logic [lg_ways_lp-1:0] way_id_o
);
if (ways_p == 1) begin: no_lru
assign way_id_o = 1'b0;
end
else begin: lru
for (genvar i = 0; i < lg_ways_lp; i++) begin: rank
if (i == 0) begin: z
// top way_id_o bit is just the lowest LRU bit
assign way_id_o[lg_ways_lp-1] = lru_i[0]; // root
end
else begin: nz
// each output way_id_o bit uses *all* of the way_id_o bits above it in the way_id_o vector
// as the select to a mux which has as input an exponentially growing (2^i) collection of unique LRU bits
bsg_mux #(
.width_p(1)
,.els_p(2**i)
) mux (
.data_i(lru_i[((2**i)-1)+:(2**i)])
,.sel_i(way_id_o[lg_ways_lp-1-:i])
,.data_o(way_id_o[lg_ways_lp-1-i])
);
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_lru_psuedo_tree_encode)
|
#include <bits/stdc++.h> using namespace std; signed main() { long long V; cin >> V; while (V--) { double a[250]; for (long long i = 0; i < 250; i++) cin >> a[i]; double exp = 0; for (long long i = 0; i < 250; i++) exp += a[i]; exp /= 250; double var = 0; for (long long i = 0; i < 250; i++) var += (a[i] - exp) * (a[i] - exp); var /= 250; double k = exp / var; double err = 0.60; if (1.0 - err <= k && k <= 1.0 + err) cout << poisson << endl; else cout << uniform << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<vector<int>> a(n, vector<int>(m)); map<int, vector<int>> raws; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } raws[a[i][0]] = a[i]; } for (int j = 0; j < m; j++) { for (int i = 0; i < n; i++) { cin >> a[i][j]; } if (raws.find(a[0][j]) != raws.end()) { for (int i = 0; i < n; i++) { for (int x : raws[a[i][j]]) { cout << x << ; } cout << n ; } } } } return 0; }
|
/**
* Embedded System in Soongsil University
* Author : Namyun Kim, Hanter Jung
* Date : 19. June. 2014
**/
module ElevatorSimulator(clk,push_btns,motor_out,dot_col,dot_row);
input clk;
input [8:0] push_btns;
output [3:0] motor_out;
output [11:0] dot_col, dot_row;
reg [3:0] motor_out;
reg motor_count;
reg motor_dir;
reg motor_power;
// About elevator control
reg [8:0] ready_queue [2:0];
reg [1:0] current;
reg [1:0] direction;
reg input_status;
// Initialize variables
initial
begin
// Motor
motor_count = 0;
motor_dir = 0;
motor_power = 0;
motor_out = 0;
ready_queue[0] = 8'd1; // Located at 1st floor at first time
ready_queue[1] = 8'd1; // Located at 1st floor at first time
current = 0;
direction = 0;
input_status = 0;
end
// Push buttons
always@(posedge push_btns[0])
begin
if(input_status == 0)
begin
input_status = 1;
end
else if(input_status == 1)
begin
input_status = 0;
end
end
// Motor Control
always@(posedge clk)
begin
if(motor_power == 0)
begin
if(motor_count == 30'd960000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b1001; end
1'b1: begin motor_out = 4'b0101; end
endcase
motor_count = 0;
end
else if(motor_count == 30'd240000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b1010; end
1'b1: begin motor_out = 4'b0110; end
endcase
motor_count = motor_count + 1;
end
else if(motor_count == 30'd480000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b0110; end
1'b1: begin motor_out = 4'b1010; end
endcase
motor_count = motor_count + 1;
end
else if(motor_count == 30'd720000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b0101; end
1'b1: begin motor_out = 4'b1001; end
endcase
motor_count = motor_count + 1;
end
else
begin
motor_count = motor_count + 1;
end
end
end
// Elevator Schduling Algorithm
function schedule;
input current;
input destination;
begin
reg min = minimum((destination-current[0]),(destination-current[1]));
// Check same direction
// Check ready queue
end
endfunction
// Get Ready Queue Status
function get_ready_status;
input elevator;
begin
reg ready_count = 0, i;
for(i = 0; i < 10; i = i+1)
begin
if(ready_queue[elevator][i] == 1)
begin
ready_count = ready_count + 1;
end
end
end
endfunction
// Get minimum
function minimum;
input a,b;
begin
minimum = (a<=b)?0:1;
end
endfunction
endmodule
|
/* Title: seven_seg_decoder.v
* Author: Sergiy Kolodyazhnyy <>
* Date: March 9, 2017
* Purpose: Data-flow code for simple binary to hex display driver
* Developed on: Ubuntu 16.04 LTS , Quartus Prime Lite 16.1
* Tested on: DE1-SoC , Cyclone V , 5CSEMA5F31
*/
module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
/* A => bin_in[3]
* B => bin_in[2]
* C => bin_in[1]
* D => bin_in[0]
*/
// note: tmp variables use implicit nets
//led_out[6] = A’B’C’ + A’BCD + ABC’D’
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
//led_out[5] = A’B’D + A’B’C + A’CD +ABC’D
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[4] = A’D + B’C’D + A’BC’
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
//led_out[3] = B’C’D + BCD + A’BC’D’ + AB’CD’
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[2] = ABD’ + ABC + A’B’CD’
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[1] = BCD’ + ACD + ABD’ + A’BC’D
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[0] = A’B’C’D + A’BC’D’ + AB’CD + ABC’D
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule
module stimulus_seven_seg;
reg [3:0] bin_in = 0000;
wire [6:0] led_out;
reg clk;
// instantiate the seven segment decoder
seven_seg_decoder s1(led_out,bin_in);
// We'll make a counter that counts from 00 to 1111
// In order to do that, we'll need a clock
initial
clk = 1'b0;
always
#5 clk = ~clk; //toggle clock every 5 time units
always @(posedge clk)
bin_in = bin_in + 1;
initial
begin
$monitor("At time",$time,"binary input=%b and hex output=%h\n",bin_in,led_out);
#160 $stop;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_8_V
`define SKY130_FD_SC_HDLL__MUX2_8_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_8 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_8 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_8_V
|
#include <bits/stdc++.h> using namespace std; double PI = 3.141592653589793238462643383279; const double EPS = 1e-9; const long long MOD = 1000000007; const int inf = 1 << 30; const long long linf = 1LL << 60; int n; int a[100]; vector<pair<vector<int>, int> > v1, v2; int main() { scanf( %d , &n); for (int i = 0; i < (int)n; i++) scanf( %d , a + i); for (int i = 0; i < (int)(1 << 15); i++) { { int pre = __builtin_popcount((a[0] ^ i) & ((1 << 15) - 1)); vector<int> tmp; for (int k = 1; k < n; k++) { int now = __builtin_popcount((a[k] ^ i) & ((1 << 15) - 1)); tmp.push_back(pre - now); pre = now; } v1.push_back(pair<vector<int>, int>(tmp, i)); if (i == 3) { } } { int pre = __builtin_popcount((a[0] >> 15) ^ i); vector<int> tmp2; for (int k = 1; k < n; k++) { int now = __builtin_popcount((a[k] >> 15) ^ i); tmp2.push_back(now - pre); pre = now; } v2.push_back(pair<vector<int>, int>(tmp2, i * (1 << 15))); } } sort(v1.begin(), v1.end(), [](const pair<vector<int>, int>& l, const pair<vector<int>, int>& r) { for (int i = 0; i < (int)n - 1; i++) { if (l.first[i] < r.first[i]) return true; if (l.first[i] > r.first[i]) return false; } return l.second < r.second; }); sort(v2.begin(), v2.end(), [](const pair<vector<int>, int>& l, const pair<vector<int>, int>& r) { for (int i = 0; i < (int)n - 1; i++) { if (l.first[i] < r.first[i]) return true; if (l.first[i] > r.first[i]) return false; } return l.second < r.second; }); int pos = 0; for (pair<vector<int>, int>& p : v1) { while (pos < (int)v2.size()) { pair<vector<int>, int>& q = v2[pos]; bool ok = true; bool con = false; for (int i = 0; i < (int)n - 1; i++) { if (q.first[i] < p.first[i]) { pos++; ok = false; con = true; break; } if (q.first[i] > p.first[i]) { ok = false; break; } } if (ok) { printf( %d n , p.second + q.second); return 0; } if (!con) break; } } puts( -1 ); }
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 5; const int MACX = (int)1e9 + 7; const int dx[] = {1, -1, 0, 0}; const int dy[] = {0, 0, 1, -1}; long long n, a[N], b[N], c[N]; multiset<long long> ms, ms2; int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; ms.insert(a[i]); } for (int i = 1; i < n; i++) { cin >> b[i]; ms.erase(ms.find(b[i])); ms2.insert(b[i]); } for (int i = 1; i < n - 1; i++) { cin >> c[i]; ms2.erase(ms2.find(c[i])); } cout << *ms.begin() << << *ms2.begin(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; long long n, a, d[MAXN], v[MAXN], P[MAXN]; vector<pair<int, long long> > vc; long long ans; int main() { cin >> n >> a; vc.push_back({0, 0}); P[0] = -1e18; for (int i = 0; i < n; i++) { cin >> d[i] >> v[i]; ans = max(ans, a - v[i]); v[i] -= a; if (i == 0) continue; v[i] += v[i - 1]; long long mn; if (i >= 2) mn = v[i - 2]; else mn = 0; while (!vc.empty() && vc.back().first <= d[i] - d[i - 1]) mn = max(mn, vc.back().second), vc.pop_back(); vc.push_back({d[i] - d[i - 1], mn}); mn -= (d[i] - d[i - 1]) * (d[i] - d[i - 1]); P[vc.size()] = max(P[vc.size() - 1], mn); ans = max(ans, -v[i] + P[vc.size()]); } cout << ans; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_hd__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> a(n), b(n); pair<int, int> p; vector<pair<int, int> > v; for (int i = 0; i < n; i++) { cin >> a[i]; } iota(b.begin(), b.end(), 0); sort(b.begin(), b.end(), [&](int x, int y) { if (a[x] != a[y]) { return a[x] < a[y]; } return x < y; }); for (int i = n - 1; i >= 0; i--) { int it = 0; for (auto j = b.begin(); j != b.end(); j++) { if (*j == i) { b.erase(j); break; } it++; } for (int j = it; j < b.size(); j++) { p.first = b[j]; p.second = i; v.emplace_back(p); } } cout << v.size() << n ; for (auto i : v) { cout << i.first + 1 << << i.second + 1 << n ; } } int main() { solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; struct edge { int to, next; } e[400005]; int n, k, num, head[200005], a[200005], f[200005], g[200005], h[200005], g_node[200005], ans, maxa, size[200005]; bool ok[200005]; inline void insert(int u, int v) { e[++num].to = v; e[num].next = head[u]; head[u] = num; e[++num].to = u; e[num].next = head[v]; head[v] = num; } void dfs(int now, int fa) { size[now] = 1; int s = 0, maxc = 0, secc = 0, id = 0; for (int i = head[now]; i; i = e[i].next) if (e[i].to != fa) { dfs(e[i].to, now); size[now] += size[e[i].to]; if (ok[e[i].to]) { int ch = f[e[i].to] + g[e[i].to] + 1; if (ch == size[e[i].to]) s += ch; else if (ch > maxc) secc = maxc, maxc = ch, id = e[i].to; else if (ch > secc) secc = ch; } } if (ok[now]) { f[now] = s; g[now] = maxc; h[now] = secc; g_node[now] = id; } } void work(int now, int fa, int out) { if (ok[now]) { if (out == n - size[now]) f[now] += out; else { if (out > g[now]) h[now] = g[now], g[now] = out, g_node[now] = fa; else if (out > h[now]) h[now] = out; } num = max(num, f[now] + g[now] + 1); if (num >= k) return; } for (int i = head[now]; i; i = e[i].next) if (e[i].to != fa) { if (!ok[now]) work(e[i].to, now, 0); else { if (ok[e[i].to] && f[e[i].to] + g[e[i].to] + 1 == size[e[i].to]) work(e[i].to, now, f[now] - size[e[i].to] + g[now] + 1); else if (e[i].to == g_node[now]) work(e[i].to, now, f[now] + h[now] + 1); else work(e[i].to, now, f[now] + g[now] + 1); } } } inline bool check(int x) { for (int i = 1; i <= n; i++) ok[i] = a[i] >= x; memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); memset(h, 0, sizeof(h)); dfs(1, 0); num = 0; work(1, 0, 0); return num >= k; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); maxa = max(maxa, a[i]); } for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); insert(u, v); } int l = 1, r = maxa; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) ans = mid, l = mid + 1; else r = mid - 1; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; scanf( %d%d , &a, &b); if (b > a) { printf( -1 n ); } else if (a == b) { printf( %d.000000000 n , a); } else { int k((a - b) / b); if (k & 1) { k--; } double ans1(1. * (a - b) / k); k = (a + b) / b; if (k & 1) { k--; } double ans2(1. * (a + b) / k); printf( %.9f n , min(ans1, ans2)); } }
|
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (5),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file lut_xilinx.v when simulating
// the core, lut_xilinx. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
ZUMA_LUT_SIZE
`timescale 1ns/1ps
module lut_xilinx(
a,
d,
dpra,
clk,
we,
dpo);
input [ZUMA_LUT_SIZE-1 : 0] a;
input [0 : 0] d;
input [ZUMA_LUT_SIZE-1 : 0] dpra;
input clk;
input we;
output [0 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V6_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("virtex5"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(0),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("no_coe_file_loaded"),
.C_MEM_TYPE(4),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(0),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(1))
inst (
.A(a),
.D(d),
.DPRA(dpra),
.CLK(clk),
.WE(we),
.DPO(dpo),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.SPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int i, j, n, m; cin >> n; vector<int> vec(n); vector<int> ans; int count = 1; for (int i = 0; i < n; i++) { cin >> vec[i]; } for (int i = 0; i < n; i++) { count = 1; for (int j = 0; j < n; j++) { if (vec[i] < vec[j]) { count++; } } ans.push_back(count); } for (auto x : ans) { if (x > 1) cout << x << ; else cout << 1 << ; } cout << n ; } int32_t main() { int T = 1; while (T--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; int main() { long long n, res = 0, i; cin >> n; long long ans = (n * (n + 1)) / 2; if (ans % 2 == 0) cout << 0 << endl; else cout << 1 << endl; ans = ans / 2; for (i = n; i >= 1; i--) { res += i; if (res > ans) break; v.push_back(i); } res -= i; if (res < ans) v.push_back(ans - res); int sz = v.size(); cout << sz << ; for (int i = 0; i < sz; i++) cout << v[i] << ; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or ~^(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = ~^(vect);
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xnor ~^(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xnor ~^(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary xnor ~^(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int T; int main() { cin.tie(0); ios_base::sync_with_stdio(0); cin >> T; for (int i = 0; i < T; i++) { int n, oneCnt = 0, zeroCnt = 0; cin >> n; string str; for (int j = 0; j < n; j++) { char ch; cin >> ch; str.push_back(ch); if (ch == 1 ) oneCnt++; } if (oneCnt == 1) { cout << 0 << n ; continue; }; int len = str.length(); int start = 0, end = 0; for (int j = 0; j < len; j++) { if (str[j] == 1 ) { start = j; break; } } for (int j = len - 1; j > -1; j--) { if (str[j] == 1 ) { end = j; break; } } for (int j = start; j <= end; j++) { if (str[j] == 0 ) zeroCnt++; } cout << zeroCnt << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int R[N], czy[N], dp[N], siz[N]; pair<int, int> E[N], E2[N]; int M; pair<int, int> Find(int x) { if (x == R[x]) return {x, 0}; pair<int, int> a = Find(R[x]); a.second ^= czy[x]; return a; } void Union(int a, int b) { if (a == b) return; if (siz[a] > siz[b]) swap(a, b); siz[b] += siz[a]; R[a] = b; czy[a] ^= 1 ^ czy[b]; czy[b] = 0; } void sep(int a, int b) { if (a == b) return; czy[a] = 0; czy[b] = 0; if (siz[a] > siz[b]) swap(a, b); siz[b] -= siz[a]; R[a] = a; } void solve(int l, int r, int a, int b) { if (l > r) return; int m = (l + r) >> 1; dp[m] = N; for (int i = l; i < m; i++) { pair<int, int> A = Find(E[i].first), B = Find(E[i].second); E2[i] = {A.first, B.first}; if (A.first == B.first && (A.second ^ B.second ^ 1)) { dp[m] = i; break; } if (A.first != B.first) { czy[A.first] = A.second; czy[B.first] = B.second; } Union(A.first, B.first); } if (dp[m] < m) { for (int i = dp[m] - 1; i >= l; i--) sep(E2[i].first, E2[i].second); solve(l, dp[m], a, b); for (int i = dp[m] + 1; i <= r; i++) dp[i] = b; return; } for (int i = b; i >= a; i--) { if (i < m) { dp[m] = m - 1; break; } pair<int, int> A = Find(E[i].first), B = Find(E[i].second); E2[i] = {A.first, B.first}; if (A.first == B.first && (A.second ^ B.second ^ 1)) { dp[m] = i; break; } if (A.first != B.first) { czy[A.first] = A.second; czy[B.first] = B.second; } Union(A.first, B.first); } for (int i = dp[m] + 1; i <= b; i++) sep(E2[i].first, E2[i].second); pair<int, int> A = Find(E[m].first), B = Find(E[m].second); if (A.first == B.first && (A.second ^ B.second ^ 1)) { for (int i = m + 1; i <= r; i++) dp[i] = b; } else { if (A.first != B.first) { czy[A.first] = A.second; czy[B.first] = B.second; } Union(A.first, B.first); solve(m + 1, r, dp[m], b); sep(A.first, B.first); } for (int i = m - 1; i >= l; i--) { sep(E2[i].first, E2[i].second); } for (int i = b; i > dp[m]; i--) { A = Find(E[i].first), B = Find(E[i].second); E2[i] = {A.first, B.first}; if (A.first != B.first) { czy[A.first] = A.second; czy[B.first] = B.second; } Union(A.first, B.first); } solve(l, m - 1, a, dp[m]); for (int i = dp[m] + 1; i <= b; i++) sep(E2[i].first, E2[i].second); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, q; cin >> n >> m >> q; M = m; for (int i = 1; i <= n + 2; i++) { R[i] = i; siz[i] = 1; } for (int i = 1; i <= m; i++) { cin >> E[i].first >> E[i].second; } E[m + 1] = {n + 1, n + 2}; solve(1, m, 0, m + 1); while (q--) { int l, r; cin >> l >> r; if (r >= dp[l]) cout << NO n ; else cout << YES n ; } }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; const int LG = 27; const int INF = 1e9 + 7; pair<int, int> seg[LG][N]; int mx[LG][N]; int r[N], a[N], sol[N]; pair<int, int> p[N]; int n, k; void build(int l = 0, int r = n, int d = 0) { if (r - l == 1) { seg[d][l] = make_pair(p[l].second, l); mx[d][l] = sol[l]; return; } int mid = (l + r) / 2; build(l, mid, d + 1); build(mid, r, d + 1); merge(seg[d + 1] + l, seg[d + 1] + mid, seg[d + 1] + mid, seg[d + 1] + r, seg[d] + l); int out = 0; for (int i = r - 1; i >= l; i--) { out = max(out, sol[seg[d][i].second]); mx[d][i] = out; } } pair<int, int> get(int l, int r, int val, int s = 0, int e = n, int d = 0) { if (l >= e || r <= s) return make_pair(0, 0); if (l <= s && e <= r) { int pos = lower_bound(seg[d] + s, seg[d] + e, make_pair(val, 0)) - seg[d]; int pos2 = lower_bound(seg[d] + s, seg[d] + e, make_pair(val + 1, 0)) - seg[d]; int ans1 = 0; if (pos < e) ans1 = mx[d][pos]; return make_pair(ans1, pos2 - s); } int mid = (s + e) / 2; pair<int, int> a = get(l, r, val, s, mid, d + 1); pair<int, int> b = get(l, r, val, mid, e, d + 1); return make_pair(max(a.first, b.first), a.second + b.second); } int main() { scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &r[i]); p[i].second = r[i]; } for (int i = 0; i < n; i++) { scanf( %d , &a[i]); p[i].first = a[i]; } sort(p, p + n); build(); int L = 0, R = 0; for (int i = 0; i < n; i++) { while (L < n && p[L].first + k < p[i].first) L++; while (R < n && p[i].first + k >= p[R].first) R++; sol[i] = get(L, R, p[i].second).second; } build(); int m; cin >> m; while (m--) { int x, y; scanf( %d %d , &x, &y); x--, y--; if (a[x] > a[y]) swap(x, y); int L = lower_bound(p, p + n, make_pair(a[y] - k, 0)) - p; int R = lower_bound(p, p + n, make_pair(a[x] + k + 1, 0)) - p; int ans = get(L, R, max(r[x], r[y])).first; if (ans < 2) printf( -1 n ); else printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int maxim = 0, sum = 0, a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; maxim = max(maxim, a[i]); sum += a[i]; } if (maxim > sum / 2) { cout << T n ; continue; } if (sum % 2 == 0) cout << HL n ; else cout << T n ; } return 0; }
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#include <bits/stdc++.h> int main() { int a, b, r; scanf( %d %d %d , &a, &b, &r); r *= 2; if (r > a || r > b) { printf( Second n ); return 0; } printf( First n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int a[5]; int kiemtra(int x, int y, int z) { if (x < y + z && y < z + x && z < x + y) return 1; if (x == y + z || y == x + z || z == x + y) return 2; return 0; } void solve() { int i, j, k, x, gan; gan = 0; for (i = 0; i < 4; i++) for (j = 0; j < 4; j++) for (k = 0; k < 4; k++) if (i != j && j != k && i != k) { x = kiemtra(a[i], a[j], a[k]); if (x == 1) { cout << TRIANGLE n ; return; } if (x == 2) gan = 1; } if (gan == 1) { cout << SEGMENT n ; return; } cout << IMPOSSIBLE n ; } void input() { int i; while (cin >> a[0] >> a[1] >> a[2] >> a[3]) { solve(); } } int main() { input(); return 0; }
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//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_pio_2 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 19: 0] in_port;
input reset_n;
wire clk_en;
wire [ 19: 0] data_in;
wire [ 19: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {20 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class T> using pq = priority_queue<T>; template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; int scan() { return getchar(); } void scan(int& a) { cin >> a; } void scan(long long& a) { cin >> a; } void scan(char& a) { cin >> a; } void scan(double& a) { cin >> a; } void scan(long double& a) { cin >> a; } void scan(char a[]) { scanf( %s , a); } void scan(string& a) { cin >> a; } template <class T> void scan(vector<T>&); template <class T, size_t size> void scan(array<T, size>&); template <class T, class L> void scan(pair<T, L>&); template <class T, size_t size> void scan(T (&)[size]); template <class T> void scan(vector<T>& a) { for (auto& i : a) scan(i); } template <class T> void scan(deque<T>& a) { for (auto& i : a) scan(i); } template <class T, size_t size> void scan(array<T, size>& a) { for (auto& i : a) scan(i); } template <class T, class L> void scan(pair<T, L>& p) { scan(p.first); scan(p.second); } template <class T, size_t size> void scan(T (&a)[size]) { for (auto& i : a) scan(i); } template <class T> void scan(T& a) { cin >> a; } void IN() {} template <class Head, class... Tail> void IN(Head& head, Tail&... tail) { scan(head); IN(tail...); } string stin() { string s; cin >> s; return s; } template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } vector<int> iota(int n) { vector<int> a(n); iota(begin(a), end(a), 0); return a; } template <class T> void UNIQUE(vector<T>& x) { sort(begin(x), end(x)); x.erase(unique(begin(x), end(x)), x.end()); } int in() { int x; cin >> x; return x; } long long lin() { unsigned long long x; cin >> x; return x; } void print() { putchar( ); } void print(bool a) { cout << a; } void print(int a) { cout << a; } void print(long long a) { cout << a; } void print(char a) { cout << a; } void print(string& a) { cout << a; } void print(double a) { cout << a; } template <class T> void print(const vector<T>&); template <class T, size_t size> void print(const array<T, size>&); template <class T, class L> void print(const pair<T, L>& p); template <class T, size_t size> void print(const T (&)[size]); template <class T> void print(const vector<T>& a) { if (a.empty()) return; print(a[0]); for (auto i = a.begin(); ++i != a.end();) { cout << ; print(*i); } cout << endl; } template <class T> void print(const deque<T>& a) { if (a.empty()) return; print(a[0]); for (auto i = a.begin(); ++i != a.end();) { cout << ; print(*i); } } template <class T, size_t size> void print(const array<T, size>& a) { print(a[0]); for (auto i = a.begin(); ++i != a.end();) { cout << ; print(*i); } } template <class T, class L> void print(const pair<T, L>& p) { cout << ( ; print(p.first); cout << , ; print(p.second); cout << ) ; } template <class T> void print(set<T>& x) { for (auto e : x) print(e), cout << ; cout << endl; } template <class T, size_t size> void print(const T (&a)[size]) { print(a[0]); for (auto i = a; ++i != end(a);) { cout << ; print(*i); } } template <class T> void print(const T& a) { cout << a; } int out() { putchar( n ); return 0; } template <class T> int out(const T& t) { print(t); putchar( n ); return 0; } template <class Head, class... Tail> int out(const Head& head, const Tail&... tail) { print(head); putchar( ); out(tail...); return 0; } long long gcd(long long a, long long b) { while (b) { long long c = b; b = a % b; a = c; } return a; } long long lcm(long long a, long long b) { if (!a || !b) return 0; return a * b / gcd(a, b); } vector<pair<long long, long long>> factor(long long x) { vector<pair<long long, long long>> ans; for (long long i = 2; i * i <= x; i++) if (x % i == 0) { ans.push_back({i, 1}); while ((x /= i) % i == 0) ans.back().second++; } if (x != 1) ans.push_back({x, 1}); return ans; } vector<int> divisor(int x) { vector<int> ans; for (int i = 1; i * i <= x; i++) if (x % i == 0) { ans.push_back(i); if (i * i != x) ans.push_back(x / i); } return ans; } int popcount(long long x) { return __builtin_popcountll(x); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int rnd(int n) { return uniform_int_distribution<int>(0, n - 1)(rng); } template <class... T> void err(const T&...) {} struct Setup_io { Setup_io() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout << fixed << setprecision(15); } } setup_io; double d(long long x, long long y) { return sqrt((long double)x * (long double)x + (long double)y * (long double)y); } double d(pair<int, int> x) { return d(x.first, x.second); } int main() { int n, k; IN(n, k); map<pair<int, int>, vector<pair<int, int>>> mp; for (long long i = 0; i < n; ++i) { long long a, b; IN(a, b); if (!a and !b) continue; if (b < 0 or (b == 0 and a <= 0)) { long long g = gcd(a, b); g = abs(g); mp[{a / g, b / g}].emplace_back(abs(a), abs(b)); } else { long long g = gcd(a, b); g = abs(g); mp[{a / g, b / g}].emplace_back(abs(a), abs(b)); } } vector<long double> ans{0}; bool flag = false; for (auto [e, v] : mp) { sort(begin(v), end(v), greater<pair<int, int>>()); if (v.size() > k / 2) { for (long long i = 0; i < k / 2; ++i) { long double D = d(v[i]); ans.emplace_back(D * (k - 1 - i * 2)); } int c = k / 2; long double dist = 0; for (long long i = v.size() - 1; i >= c; --i) { long double D = d(v[i]); ans.emplace_back(D * (k - 1 - c * 2) - dist); dist += D * 2; } } else for (long long i = 0; i < v.size(); ++i) { long double D = d(v[i]); ans.emplace_back(D * (k - 1 - i * 2)); } } sort(begin(ans), end(ans), greater<long double>()); long double sum = 0; for (long long i = 0; i < k; ++i) sum += ans[i]; cout << sum << n ; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MAXN = 1000010; int prime[5005]; long long f[MAXN][22]; void getPrime() { for (int i = 2; i <= 5000; i++) { if (!prime[i]) prime[++prime[0]] = i; for (int j = 1; j <= prime[0] && prime[j] <= 5000 / i; j++) { prime[prime[j] * i] = 1; if (i % prime[j] == 0) break; } } } void init() { f[0][0] = 1; for (int i = 1; i <= 20; ++i) { f[0][i] = 2; } for (int i = 1; i <= 1000000; ++i) { f[i][0] = 1; for (int j = 1; j <= 20; ++j) { f[i][j] = (f[i][j - 1] + f[i - 1][j]) % MOD; } } } int q, r, n; int main() { init(); getPrime(); scanf( %d , &q); while (q--) { scanf( %d%d , &r, &n); long long ans = 1; int cnt = 0; for (int i = 1, tmp; prime[i] * prime[i] <= n && i <= prime[0]; ++i) { tmp = prime[i]; if (n == 1) break; if (n % tmp == 0) { while (n % tmp == 0) { n /= tmp; cnt++; } } ans = ans * f[r][cnt] % MOD; cnt = 0; } if (n > 1) { ans = ans * (long long)f[r][1] % MOD; } printf( %I64d n , ans); } return 0; }
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#include<stdio.h> #include<bits/stdc++.h> typedef long long ll; using namespace std; int main() { ll deva; cin>>deva; for(ll ol=0;ol<deva;ol++) { int n; cin>>n; string s; cin>>s; int a[26]={0}; int flag=1; a[s[0]- A ]+=1; for(int i=1;i<n;i++) { if(a[s[i]- A ]>0 && s[i]!=s[i-1]) { flag=0; break; } a[s[i]- A ]+=1; } if(flag) cout<< YES <<endl; else cout<< NO <<endl; } return 0; }
|
//
// Copyright (c) 1999 Thomas Coonan ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// Integer Multicycle Divide circuit (divide a 16-bit number by a 16-bit number in 16 cycles).
//
// a / b = q with remainder r
//
// Where a is 16-bits,
// Where b is 16 bits
//
// Module is actually parameterized if you want other widths.
//
// *** Test the ranges of values for which you'll use this. For example, you
// can't divide FFFF by FF without underflow (overflow?). Mess with
// the testbench. You may need to widen some thing. ***
//
// The answer is 16-bits and the remainder is also 16-bits.
// After the start pulse, the module requires 16 cycles to complete.
// The q/r outputs stay the same until next start pulse.
// Start pulse should be a single cycle.
// Division by zero results in a quotient equal to FFFF and remainder equal to 'a'.
//
//
// Written by tom coonan.
//
// Notes:
// - This ain't fancy. I wanted something straight-forward quickly. Go study
// more elaborate algorithms if you want to optimize area or speed. If you
// have an isolated divide and can spare N cycles for N bits; this may meet your needs.
// - You might want to think more about the sizes of things. I wanted a basic estimate
// of gates plus I specifically needed to divide 16-bits (not even full range)
// by 8-bits.
// - Handle divide by zero at higher level..
// - I needed a remainder so I could easily to truncate and rounding stuff,
// but remove this to save gates if you don't need a remainder.
// - This is about 800 asic gates (0.25um, Standard Cell, 27Mhz). 27Mhz
// is my system clock and NOT the maximum it can go..
// - I tried to keep everything parameterized by N, but I only worked through
// the N=16 case because that's what I needed...
//
module div16 (clk, resetb, start, a, b, q, r, done);
parameter N = 16; // a/b = q remainder r, where all operands are N wide.
input clk;
input resetb; // Asynchronous, active low reset.
input start; // Pulse this to start the division.
input [N-1:0] a; // This is the number we are dividing (the dividend)
input [N-1:0] b; // This is the 'divisor'
output [N-1:0] q; // This is the 'quotient'
output [N-1:0] r; // Here is the remainder.
output done; // Will be asserted when q and r are available.
// Registered q
reg [N-1:0] q;
reg done;
// Power is the current 2^n bit we are considering. Power is a shifting
// '1' that starts at the highest power of 2 and goes all the way down
// to ...00001 Shift this until it is zero at which point we stop.
//
reg [N-1:0] power;
// This is the accumulator. We are start with the accumulator set to 'a' (the dividend).
// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) from the accumulator.
// We subtract these terms as long as adding in the term doesn't cause the accumulator
// to exceed a. When we are done, whatever is left in the accumulator is the remainder.
//
reg [N-1:0] accum;
// This is the divisor*2^N term. Essentually, we are taking the divisor ('b'), initially
// shifting it all the way to the left, and shifting it 1 bit at a time to the right.
//
reg [(2*N-1):0] bpower;
// Remainder will be whatever is left in the accumulator.
assign r = accum;
// Do this addition here for resource sharing.
// ** Note that 'accum' is N bits wide, but bpower is 2*N-1 bits wide **
//
wire [2*N-1:0] accum_minus_bpower = accum - bpower;
always @(posedge clk or negedge resetb) begin
if (~resetb) begin
q <= 0;
accum <= 0;
power <= 0;
bpower <= 0;
done <= 0;
end
else begin
if (start) begin
// Reinitialize the divide circuit.
q <= 0;
accum <= a; // Accumulator initially gets the dividend.
power[N-1] <= 1'b1; // We start with highest power of 2 (which is a '1' in MSB)
bpower <= b << N-1; // Start with highest bpower, which is (divisor * 2^(N-1))
done <= 0;
end
else begin
// Go until power is zero.
//
if (power != 0) begin
//
// Can we add this divisor*2^(power) to the accumulator without going negative?
// Just test the MSB of the subtraction. If it is '1', then it must be negative.
//
if ( ~accum_minus_bpower[2*N-1]) begin
// Yes! Set this power of 2 in the quotieny and
// then actually comitt to the subtraction from our accumulator.
//
q <= q | power;
accum <= accum_minus_bpower;
end
// Regardless, always go to next lower power of 2.
//
power <= power >> 1;
bpower <= bpower >> 1;
end
else begin
// We're done. Set done flag.
done <= 1;
end
end
end
end
endmodule
// synopsys translate_off
module test_div16;
reg clk;
reg resetb;
reg start;
reg [15:0] a;
reg [15:0] b;
wire [15:0] q;
wire [15:0] r;
wire done;
integer num_errors;
div16 div16 (
.clk(clk),
.resetb(resetb),
.start(start),
.a(a),
.b(b),
.q(q),
.r(r),
.done(done)
);
initial begin
num_errors = 0;
start = 0;
// Wait till reset is completely over.
#200;
// Do some divisions where divisor is constrained to 8-bits and dividend is 16-bits
$display ("16-bit Dividend, 8-bit divisor");
repeat (25) begin
do_divide ($random, $random & 255);
end
// Do some divisions where divisor is constrained to 12-bits and dividend is 16-bits
$display ("\n16-bit Dividend, 12-bit divisor");
repeat (25) begin
do_divide ($random, $random & 4095);
end
// Do some divisions where both divisor and dividend is 16-bits
$display ("\n16-bit Dividend, 16-bit divisor");
repeat (25) begin
do_divide ($random, $random);
end
// Special cases
$display ("\nSpecial Cases:");
do_divide (16'hFFFF, 16'hFFFF); // largest possible quotient
do_divide (312, 1); // divide by 1
do_divide ( 0, 42); // divide 0 by something else
do_divide (312, 0); // divide by zero
// That's all. Summarize the test.
if (num_errors === 0) begin
$display ("\n\nPASSED");
end
else begin
$display ("\n\nFAILED - There were %0d Errors.", num_errors);
end
$finish;
end
task do_divide;
input [15:0] arga;
input [15:0] argb;
begin
a = arga;
b = argb;
@(posedge clk);
#1 start = 1;
@(posedge clk);
#1 start = 0;
while (~done) @(posedge clk);
#1;
$display ("Circuit: %0d / %0d = %0d, rem = %0d\t\t......... Reality: %0d, rem = %0d", arga, argb, q, r, a/b, a%b);
if (b !== 0) begin
if (q !== a/b) begin
$display (" Error! Unexpected Quotient\n\n");
num_errors = num_errors + 1;
end
if (r !== a % b) begin
$display (" Error! Unexpected Remainder\n\n");
num_errors = num_errors + 1;
end
end
end
endtask
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
resetb = 0;
#133 resetb = 1;
end
//initial begin
// $dumpfile ("test_div16.vcd");
// $dumpvars (0,test_div16);
//end
endmodule
|
#include <bits/stdc++.h> using namespace std; string str; int ss; int par[10001]; int ans[2][10001]; int root(int x) { if (par[x] != x) par[x] = root(par[x]); return par[x]; } map<string, int> m; int main() { while (getline(cin, str)) { char ty = str[0]; int k = 2; int z = 0; int p = 0; string tt = ; tt += ty; tt += ; while (k < str.size()) { tt += ; string t = ; k++; while (k < str.size() && str[k] != ) t += str[k], k++; tt += t; z++; if (k < str.size()) { if (!m.count(tt)) { m[tt] = ++ss; par[m[tt]] = m[tt]; } if (z > 1) { int xx = root(m[tt]); int yy = root(p); if (xx != yy) { par[xx] = yy; ans[0][yy]++; } } p = m[tt]; } else { ans[1][root(p)]++; } } } int mx1 = 0, mx2 = 0; for (map<string, int>::iterator it = m.begin(); it != m.end(); it++) { mx1 = max(mx1, ans[0][it->second]); mx2 = max(mx2, ans[1][it->second]); } cout << mx1 << << mx2; return 0; }
|
`timescale 1 ns/1 ps
module someTwoPortVendorMem_128_8_0 (QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB);
output [7:0] QA;
input CLKA;
input CENA;
input WENA;
input [6:0] AA;
input [7:0] DA;
input OENA;
output [7:0] QB;
input CLKB;
input CENB;
input WENB;
input [6:0] AB;
input [7:0] DB;
input OENB;
reg [7:0] mem [127:0];
reg [7:0] QA,QB;
initial
begin
$display("%m : someTwoPortVendorMem_128_8_0 instantiated.");
end
always @(posedge CLKA)
begin
if((CENA == 0)&&(WENA==0))
begin
mem[AA] <= DA;
end
else if((CENA == 0)&&(WENA==1))
begin
QA <=mem[AA];
end
end
always @(posedge CLKB)
begin
if((CENB == 0)&&(WENB==0))
begin
mem[AB] <= DB;
end
else if((CENB == 0)&&(WENB==1))
begin
QB <=mem[AB];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, ans = 0; const long long maxn = 1e6 + 5; long long p[maxn]; int main() { cin >> a >> b >> c >> d; long long mx = min(b - a, c - b) + 1; for (long long i = a + b, t = 1; i <= b + c; ++i) { p[i] = t; t = min(t + 1, mx); } for (long long i = b + c - mx + 1, t = mx; i <= b + c; ++i) { p[i] = t; --t; } for (long long i = a + b; i <= b + c; ++i) { p[i] = p[i - 1] + p[i]; } ans = p[b + c] * (d - c + 1); for (long long i = c; i <= d; ++i) { long long ind = min(b + c, i); ans -= p[ind]; } cout << ans << endl; }
|
#include <bits/stdc++.h> char a[200005], b[200005], c[200005]; int v[200005], n, m; bool verif(int poz) { int i, j; for (i = 1; i <= n; i++) c[i] = a[i]; for (i = 1; i <= poz; i++) c[v[i]] = 0; for (i = 1, j = 1; i <= n && j <= m; i++) if (c[i] == b[j]) j++; if (j == m + 1) return true; return false; } int main() { int i, st, dr, mij, rasp = 0; char ch; ch = fgetc(stdin); while (ch >= a && ch <= z ) { n++; a[n] = ch; ch = fgetc(stdin); } ch = fgetc(stdin); while (ch >= a && ch <= z ) { m++; b[m] = ch; ch = fgetc(stdin); } for (i = 1; i <= n; i++) fscanf(stdin, %d , &v[i]); st = 1; dr = n; while (st <= dr) { mij = (st + dr) / 2; if (verif(mij) == true) { rasp = mij; st = mij + 1; } else { dr = mij - 1; } } fprintf(stdout, %d , rasp); fclose(stdin); fclose(stdout); return 0; }
|
#include <bits/stdc++.h> int main() { long n(0); scanf( %ld , &n); long currentDiv = 2, total = 1; while (n > 1) { if (currentDiv * currentDiv > n) { total += n; break; } else if (n % currentDiv == 0) { total += n; n /= currentDiv; } else { ++currentDiv; } } printf( %ld n , total); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKBUF_BEHAVIORAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; char buf[1 << 21], *p1 = buf, *p2 = buf; inline long long qread() { register char c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); register long long x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 48; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } return x * f; } inline long long Abs(const long long& x) { return (x > 0 ? x : -x); } inline long long Max(const long long& x, const long long& y) { return (x > y ? x : y); } inline long long Min(const long long& x, const long long& y) { return (x < y ? x : y); } long long n, l, wmax; vector<long long> ml, mr; inline long long Div(long long x, long long y) { if (!y) { if (x > 0) return 2147483647; else return -2147483647; } if (x % y < 0) x -= (y + x % y); return x / y; } inline void Read() { n = qread(); l = qread(); wmax = qread(); for (register long long i = 1; i <= n; i++) { register long long x = qread(), v = qread(); if (v == 1) mr.push_back(x); else ml.push_back(x); } } inline void Solve() { register long long siz = ml.size(); register long long ans = 0; for (register long long i = 0; i < siz; i++) { auto lmost = lower_bound(mr.begin(), mr.end(), -ml[i] - l); ans += upper_bound( mr.begin(), lmost, Min(Div((ml[i] + l) * (wmax + 1) - 1, wmax - 1), -ml[i] - l)) - mr.begin(); ans += upper_bound(lmost, mr.end(), Min(Div((ml[i] + l) * (wmax - 1) - 1, wmax + 1), ml[i])) - lmost; } printf( %lld , ans); } signed main() { Read(); sort(ml.begin(), ml.end()); sort(mr.begin(), mr.end()); Solve(); return 0; }
|
`timescale 1ns/10ps
module usb_121pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("20.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("60.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("60.000000 MHz"),
.phase_shift1("8333 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int kN = 1e5 + 10; const int MOD = 1e9 + 7; int N, M; int power(int d, int k) { int ret = 1, tmp = d; while (k) { if (k & 1) { ret = 1ll * ret * tmp % MOD; } tmp = 1ll * tmp * tmp % MOD; k >>= 1; } return ret; } void cant() { printf( 0 ); exit(0); } struct Edge { int u, v; bool diff; } es[kN]; struct UFS { int fa[kN]; int lowbit(int i) { return i & -i; } void init() { for (int i = 0; i < kN; i++) fa[i] = i; } int getFa(int i) { if (fa[i] != i) fa[i] = getFa(fa[i]); return fa[i]; } bool isSameFa(int u, int v) { int uf = getFa(u); int vf = getFa(v); return uf == vf; } void link(int u, int v) { int uf = getFa(u); int vf = getFa(v); fa[uf] = vf; } } ufs; int col[kN]; vector<int> G[kN]; void dfs(int u, int c) { if (col[u]) { if (col[u] != c) cant(); return; } col[u] = c; c = c == 1 ? 2 : 1; for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; dfs(v, c); } } int main() { scanf( %d %d , &N, &M); for (int i = 1; i <= M; i++) { int op, u, v; scanf( %d %d %d , &u, &v, &op); if (u > v) swap(u, v); es[i].u = u, es[i].v = v, es[i].diff = !op; } ufs.init(); for (int i = 1; i <= M; i++) { if (es[i].diff == false) { ufs.link(es[i].u, es[i].v); } } for (int i = 1; i <= M; i++) { if (es[i].diff) { int uf = ufs.getFa(es[i].u); int vf = ufs.getFa(es[i].v); G[uf].push_back(vf); G[vf].push_back(uf); } } int cnt = 0; for (int i = 1; i <= N; i++) if (ufs.getFa(i) == i && !col[i]) { dfs(i, 1); cnt++; } int ans = power(2, cnt - 1); printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, cnt = 0; long long sum = 0; bool flag = false; struct Node { int num; int pos; } a[200005]; bool cmp(const Node &a, const Node &b) { return a.num < b.num; } vector<int> v; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].num; a[i].pos = i; sum += a[i].num; } sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n - 1; i++) { if (sum - a[i].num == 2 * a[n].num) { cnt++; v.push_back(a[i].pos); } } if (sum - a[n].num == 2 * a[n - 1].num) { v.push_back(a[n].pos); cnt++; } if (cnt == 0) { cout << 0 << endl; return 0; } cout << cnt << endl; for (int i = 0; i < v.size(); i++) { cout << v[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; template <class T> void dbs(string str, T t) { cerr << str << : << t << n ; } template <class T, class... second> void dbs(string str, T t, second... s) { int idx = str.find( , ); cerr << str.substr(0, idx) << : << t << , ; dbs(str.substr(idx + 1), s...); } template <class second, class T> ostream& operator<<(ostream& os, const pair<second, T>& p) { return os << ( << p.first << , << p.second << ) ; } template <class T> void prc(T a, T b) { cerr << [ ; for (T i = a; i != b; ++i) { if (i != a) cerr << , ; cerr << *i; } cerr << ] n ; } const int N = 2020; long long first[N][N]; long long G[N][N]; string s; long long g(int n, int k); long long f(int n, int k) { if (k < 0) return 0; if (n == 0) return k == 0; long long& ans = first[n][k]; if (ans != -1) return ans; ans = 0; int ch = s[int(s.size()) - n] - a ; ans = ch * f(n - 1, k) + (25 - ch) * f(n - 1, k - n) + g(n - 1, k) + (k == 0); int nk = k; for (int i = 1; i <= n - 1; ++i) { int ch = s[int(s.size()) - n + i] - a ; nk = k - (i + 1) * (n - i); if (nk < 0) { for (int i = n - 1; i >= 1; --i) { int ch = s[int(s.size()) - n + i] - a ; nk = k - (i + 1) * (n - i); if (nk < 0) break; ans += (25 - ch) * f(n - i - 1, nk); ans %= inf; } break; } ans += (25 - ch) * f(n - i - 1, nk); ans %= inf; } ans %= inf; return ans; } long long g(int n, int k) { if (k < 0) return 0; if (n == 0) return 0; long long& ans = G[n][k]; if (ans != -1) return ans; int ch = s[int(s.size()) - n] - a ; ans = ch * f(n - 1, k) + g(n - 1, k); ans %= inf; return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; memset(first, -1, sizeof first); memset(G, -1, sizeof G); cin >> s; cout << f(n, k) << n ; return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; const long long MOD = 1e9 + 7; const long long MODD = 1e9 + 1; const long long MODL = 998244353; const long long N = 200005; const long long INF = 1e18; const long long mx = 1e5 + 1; long long Power(long long x, long long y) { long long r = 1; while (y) { if (y & 1) r = 1ll * r * x % MOD; x = 1ll * x * x % MOD, y >>= 1; } return r; } bool sortbysec(const pair<int, int>& a, const pair<int, int>& b) { return (a.second < b.second); } bool sortstring(const string& a, const string& b) { return a + b < b + a; } long long GCD(long long a, long long b) { if (b == 0) return a; a %= b; return GCD(b, a); } bool isZero(int i) { return i == 0; } int ce(int n, int m) { int ans = 0; if (n % m == 0) ans = n / m; else ans = n / m + 1; return ans; } int solve(int n) { int m, k; cin >> m >> k; int p = 0; int q = 0, qq = 0; int r = 0; int x = ce(n, m); int s = 0; if (n % m != 0) { for (int i = n - 1; i >= 0; i--) { if (i % x == 0 && (n - i) % (n / m) == 0 && (i / x + (n - i) / (n / m) == m)) { s = i; break; } } } s = (n - s) / (n / m); for (int i = 0; i < k; i++) { for (int j = 0; j < m - s; j++) { cout << x << ; r = j * x + p; for (int k = 0; k < x; k++) { cout << r % n + 1 << ; q = r % n; r++; } cout << n ; } qq = q; for (int j = 0; j < s; j++) { cout << n / m << ; r = q + 1; for (int k = 0; k < n / m; k++) { cout << r % n + 1 << ; q = r % n; r++; } cout << n ; } p = qq + 1; } cout << n ; return 0; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; int n = 0; cin >> t; while (t--) { cin >> n; solve(n); } return 0; }
|
//...START BY DOING WHAT IS NECESSARY, THEN WHAT IS POSSIBLE AND SUDDENLY YOU ARE DOING THE IMPOSSIBLE... #include <bits/stdc++.h> using namespace std; #define FAST_FURIER ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); #define pb push_back #define mk make_pair #define rep(i,a,N) for(ll i=a;i<N;i++) #define rrep(i,a,N) for(ll i=a;i>N;i--) typedef long long ll; #define M 1000000007 bool comp(int x,int y) { return x > y; } /*..............................code starts here........................*/ // C is first won in M int main() { FAST_FURIER; int tt=1; cin >> tt; ll m,d,k; //ll a,b,c; while(tt--) { cin >> d >> k; ll x = 0,y = 0; int f = 0; while(true){ ll d1 = pow(x+k,2)+pow(y,2), d2 = pow(x,2)+pow(y+k,2); f = abs(f-1); if(d1 < d2 and d1 <= d*d){ x += k; } else if(d2 <= d1 and d2 <= d*d) y += k; else break; } if(f) cout << Utkarsh ; else cout << Ashish ; cout << endl; } } // Author : shivam_123 // g++ -std=c++17
|
//-----------------------------------------------------------------------------
// File : TestInitializer.v
// Creation date : 10.05.2017
// Creation time : 16:20:32
// Description : A bare bones verilog test bench, which is used to assert reset, generate clock, give start signal and finally check after WAIT_TIME, if the done is asserted.
// Created by : TermosPullo
// Tool : Kactus2 3.4.107 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:other.subsystem.test:wb_example.bench:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/other.subsystem.test/wb_example.bench/1.0/wb_example.bench.1.0.xml
//-----------------------------------------------------------------------------
module TestInitializer #(
parameter WAIT_TIME = 100, // How long to wait after reset is deassereted.
parameter V_WAIT_TIME = WAIT_TIME // How long to wait after reset is deassereted.
) (
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous logic.
input done, // Output used to signal that the masters are done sending.
input rst_i, // The mandatory reset, as this is synchronous logic.
output reg start // Input used to signal that is is ok to start the masters.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
initial begin
start = 0;
@(posedge rst_i); // wait for reset
start = 1;
@(posedge clk_i);
@(posedge clk_i);
@(posedge clk_i);
start =0; // generate the falling edge
#V_WAIT_TIME
if ( done == 1'b0 )
$display("not done!");
else
$display("done high");
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; set<int> s; while (1) { int k = s.size(); s.insert(n); int m = s.size(); if (k == m) break; n = n + 1; while (n % 10 == 0) { n = n / 10; } } cout << s.size() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a, b; double gia[n]; for (int i = 0; i < n; i++) { cin >> a >> b; gia[i] = (double)a / b; } double kq = gia[0]; for (int i = 1; i < n; i++) { if (kq > gia[i]) kq = gia[i]; } cout << setprecision(8) << kq * m; }
|
#include <bits/stdc++.h> using namespace std; void c_p_c() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } bool prime(long long c) { for (long long i = 2; i * i <= c; i++) { if (c % i == 0) return 0; } return 1; } int32_t main() { c_p_c(); long long n; cin >> n; while (n--) { long long a, b, s = 0; cin >> a >> b; while (a > 0 && b > 0) { if (a > b) { s += (a / b); a -= (a / b) * b; } else { s += (b / a); b -= (b / a) * a; } } cout << s << n ; } return 0; }
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#include <bits/stdc++.h> long long int n, m; long long int pow(long long int k) { long long int a = 1, t = 3; for (; k; k /= 2) { if (k & 1) a = (a * t) % m; t = t * t % m; } return a; } void suru() { scanf( %I64d %I64d , &n, &m); } void truli() {} void sutru() { printf( %I64d n , (pow(n) - 1 + m) % m); } int main() { suru(); truli(); sutru(); return 0; }
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#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; using namespace std; int a[105], n, dp[105][105][2], cnt = 0; int main() { scanf( %d , &n); cnt = (n + 1) / 2; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); if (a[i]) { if (a[i] & 1) --cnt; } } memset(dp, INF, sizeof(dp)); dp[0][0][0] = 0; dp[0][0][1] = 0; for (int i = 1; i <= n; ++i) { if (a[i]) { int t = a[i] & 1; for (int j = 0; j <= min(cnt, i - 1); ++j) dp[i][j][t] = min(dp[i - 1][j][t], dp[i - 1][j][1 - t] + 1); } else { for (int j = 1; j <= min(cnt, i); ++j) dp[i][j][1] = min(dp[i - 1][j - 1][1], dp[i - 1][j - 1][0] + 1); for (int j = 0; j <= min(cnt, i - 1); ++j) dp[i][j][0] = min(dp[i - 1][j][1] + 1, dp[i - 1][j][0]); } } printf( %d n , min(dp[n][cnt][0], dp[n][cnt][1])); }
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#include <bits/stdc++.h> using namespace std; int main() { unsigned long long int n, sum = 0, pos = 0, ans1 = 0, ans2 = 0; cin >> n; vector<unsigned long long int> vect; vect.resize(n); for (unsigned long long int i = 0; i < n; i++) { cin >> vect[i]; sum += vect[i]; } if (sum % n == 0) { pos = sum / n; for (unsigned long long int i = 0; i < n; i++) { if (vect[i] > pos) { ans1 += vect[i] - pos; } } cout << ans1 << endl; } else { pos = (sum / n) + 1; for (unsigned long long int i = 0; i < n; i++) { if (vect[i] > pos) { ans1 += vect[i] - pos; } else if (vect[i] < pos - 1) { ans2 += pos - 1 - vect[i]; } } cout << max(ans1, ans2) << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); long long n; cin >> n; vector<int> v(n); for (int i = (0); i < (n); ++i) cin >> v[i]; sort(v.begin(), v.end()); vector<int> res = {v[0]}; for (int i = (0); i < (n); ++i) for (int j = (0); j < (31); ++j) { int lx = v[i] - (1 << j); int rx = v[i] + (1 << j); bool isl = binary_search(v.begin(), v.end(), lx); bool isr = binary_search(v.begin(), v.end(), rx); if (isl && isr && int(res.size()) < 3) { res = {lx, v[i], rx}; } if (isl && int((int)res.size()) < 2) { res = {lx, v[i]}; } } cout << (int)res.size() << endl; for (auto it : res) cout << it << ; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:52 06/07/2015
// Design Name:
// Module Name: UART_LOOPBACK
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_LOOPBACK(
// UART USB ports
input sys_clk, // 27 MHZ on SP605
output CTS,// I am ready to receive data
input RTS, // USB Clear to send
output TX, // Output to USB
input RX, // Input to USB
output [3:0] leds
);
// LOOPBACK WIRES
wire [7:0] TxD_par;
wire TxD_ready;
assign leds = {CTS,RTS,TxD_par[1:0]};
UART_IP uartip(
// UART USB ports
.sys_clk(sys_clk), // 27 MHZ on SP605
.RTS(RTS),// I am ready to receive data
.CTS(CTS), // USB Clear to send
.TX(TX), // Output to USB
.RX(RX), // Input to USB
// FPGA
.TxD_par(TxD_par),
.TxD_ready(TxD_ready),
.RxD_par(TxD_par),
.RxD_start(TxD_ready)
);
endmodule
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#include <bits/stdc++.h> using namespace std; bool valid(string s) { int start = 0, end = s.length() - 1; while (start < end) { if (s[start] == a && s[end] == a ) { start++; end--; } else if (s[start] == a && s[end] == z ) { return false; } else if (s[start] == z && s[end] == a ) { return false; } else if (s[start] == z && s[end] == z ) { start++; end--; } else if (s[start] == z ) { if (abs(s[start] - s[end]) == 2 || abs(s[start] - s[end]) == 0) { start++; end--; } else { return false; } } else if (s[start] == a ) { if (abs(s[start] - s[end]) == 2 || abs(s[start] - s[end]) == 0) { start++; end--; } else { return false; } } else if (s[end] == a ) { if (abs(s[start] - s[end]) == 2 || abs(s[start] - s[end]) == 0) { start++; end--; } else { return false; } } else if (s[end] == z ) { if (abs(s[start] - s[end]) == 2 || abs(s[start] - s[end]) == 0) { start++; end--; } else { return false; } } else { if (abs(s[start] - s[end]) == 2 || abs(s[start] - s[end]) == 0) { start++; end--; } else { return false; } } } } int main() { int n, t; string s; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &t); cin >> s; if (valid(s)) cout << YES << endl; else cout << NO << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = (int)15e4 + 10, M = 310; int n, m, d; long long a[N], b[N], t[N], tmp[N], dp[2][N]; inline void f(int j) { long long k = 1ll * (t[j] - t[j - 1]) * d; int r = j % 2; deque<int> deq; for (int i = 0; i < n; i++) { while (deq.size() && dp[!r][deq.back()] <= dp[!r][i]) deq.pop_back(); deq.push_back(i); while (deq.front() < i - k) deq.pop_front(); tmp[i] = dp[!r][deq.front()]; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> d; for (int i = 0; i < m; i++) { cin >> a[i] >> b[i] >> t[i]; a[i]--; } for (int i = 0; i < n; i++) dp[0][i] = b[0] - abs(a[0] - i); for (int j = 1; j < m; j++) { int r = j % 2; f(j); for (int i = 0; i < n; i++) dp[r][i] = tmp[i]; reverse(dp[!r], dp[!r] + n); f(j); for (int i = 0; i < n; i++) dp[r][i] = max(dp[r][i], tmp[n - 1 - i]); for (int i = 0; i < n; i++) dp[r][i] += b[j] - abs(a[j] - i); } m--; cout << *max_element(dp[m % 2], dp[m % 2] + n); return 0; }
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#include <bits/stdc++.h> using std::cin; using std::string; string x; int a, b, c; int main() { cin >> x; switch (x[0]) { case r : a = 0; break; case s : a = 2; break; case p : a = 5; break; } cin >> x; switch (x[0]) { case r : b = 0; break; case s : b = 2; break; case p : b = 5; break; } cin >> x; switch (x[0]) { case r : c = 0; break; case s : c = 2; break; case p : c = 5; break; } if (a == b && ((c == 0 && a == 2) || (c == 2 && a == 5) || (c == 5 && a == 0))) printf( S ); else if (b == c && ((a == 0 && b == 2) || (a == 2 && b == 5) || (a == 5 && b == 0))) printf( F ); else if (a == c && ((b == 0 && a == 2) || (b == 2 && a == 5) || (b == 5 && a == 0))) printf( M ); else printf( ? ); }
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#include <bits/stdc++.h> using namespace std; multiset<pair<int, int> > st; int main() { int n, k; cin >> n >> k; int cnt = 0; for (int i = 0; i < n; i++) { int num; cin >> num; cnt += num / 10; if (num < 100) st.insert(make_pair(num % 10, num)); } while (st.size() > 0 && (*st.rbegin()).first != 0 && k > 0) { pair<int, int> num = *st.rbegin(); st.erase(st.find(num)); num.first++; num.second++; if (num.first == 10) cnt++; num.first %= 10; if (num.second < 100) st.insert(num); k--; } while (st.size() > 0) { pair<int, int> num = *st.begin(); st.erase(st.find(num)); while (num.second < 100 && k > 0) { k--; num.second++; num.first = (num.first + 1) % 10; if (num.first == 0) cnt++; } } cout << cnt << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, aa, bb; cin >> a >> b; a += 100; b += 100; cin >> aa >> bb; aa += 100; bb += 100; if (aa != a && bb != b) { int tmp = (abs(a - aa)); int tmp2 = (abs(b - bb)); cout << 2 * abs(tmp2 + tmp) + 4; } else cout << max(8, (6 + (abs(a - aa) + abs(b - bb)) * 2)); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; while (a > 0) { if (2 * a <= b && 4 * a <= c) { cout << 7 * a; return 0; } else { a--; } } cout << 0 ; return 0; }
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