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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n <= 6) { cout << m << endl; return 0; } int mark[8][8] = {0}, i, j, deg[8] = {0}, a, k; for (i = 0; i < m; i++) { int x, y; cin >> x >> y; mark[x][y] = 1; mark[y][x] = 1; deg[x]++; deg[y]++; } int max = INT_MIN; for (i = 1; i <= 7; i++) { int v[8] = {0}, c = 0, count = 0; count = m - deg[i]; for (j = 1; j <= 7; j++) { if (j == i) continue; for (k = 1; k <= 7; k++) { if (k == i) continue; if (mark[j][k] == 0 && mark[j][i] == 1) v[k]++; } } sort(v, v + 8); for (j = 1; j <= 7; j++) { if (mark[i][j] == 1) c++; } if (c < v[7]) count += c; else count += v[7]; if (count > max) max = count; } cout << max << endl; return 0; }
|
`timescale 1ns/1ps
module tb;
reg E;
wire Y;
wire clk;
parameter NAND2_DEFAULT_DELAY = 1;
/* chip AUTO_TEMPLATE(
.notE(!E),
.G(clk),
); */
chip #(.NAND2_DELAY(NAND2_DEFAULT_DELAY))
U_CHIP
(
/*AUTOINST*/
// Outputs
.Y (Y),
// Inputs
.notE (!E), // Templated
.G (clk)); // Templated
clock_gen #(.period(20)) U_CLK_GEN (
/*AUTOINST*/
// Outputs
.clk (clk));
// Dump all nets to a vcd file called tb.vcd
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
E = 0;
#100;
E=1;
#205;
E=0;
#10;
E=1;
#194;
E=0;
// @(posedge done_r); // wait for done signal to rise
#1;
@(posedge clk);
@(posedge clk);
$display("-I- Done !");
#1;
$finish;
end
endmodule // tb
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_FUNCTIONAL_PP_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_39x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_39x256 (
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [38:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [38:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire [38:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [7:0] usedw = sub_wire1[7:0];
wire empty = sub_wire2;
wire [38:0] q = sub_wire3[38:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 240,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 39,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "39"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "39"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "39"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 39 0 INPUT NODEFVAL data[38..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL q[38..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 39 0 data 0 0 39 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_39x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: demux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple demultiplexer
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module demux
#(
parameter C_OUTPUTS = 12,
parameter C_WIDTH = 1
)
(
input [C_WIDTH-1:0] WR_DATA,// Inputs
input [clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector
output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs
);
genvar i;
reg [C_OUTPUTS*C_WIDTH-1:0] _rOut;
assign RD_DATA = _rOut;
always @(*) begin
_rOut = 0;
_rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9; const long long N = 1e5 + 10; const long long bits = 30; const long long mod = 1e9 + 7; const long double pi = 3.14159265358979323846; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; std::cout << std::fixed << std::setprecision(20); ; long double n; cin >> n; long double ans = 0; for (long double i = 1; i <= n; i++) { ans += (long double)1.0 / i; } cout << ans << n ; }
|
// ======================================================================
// Design01.v generated from TopDesign.cysch
// 09/05/2015 at 17:07
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_GEN4 2
`define CYDEV_CHIP_REV_GEN4_PRODUCTION 17
`define CYDEV_CHIP_REV_GEN4_ES 17
`define CYDEV_CHIP_REV_GEN4_ES2 33
`define CYDEV_CHIP_DIE_PSOC4A 3
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_PANTHER 5
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 4
`define CYDEV_CHIP_REV_EXPECT 0
`define CYDEV_CHIP_DIE_ACTUAL 4
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 4
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 5
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 6
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 7
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_MEMBER_4F 8
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_MEMBER_4M 9
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 10
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 11
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 12
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 13
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 3
`define CYDEV_CHIP_MEMBER_USED 12
`define CYDEV_CHIP_REVISION_USED 0
// Component: STC_Datapath16_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "..\STC_Datapath16_v1_0"
`include "..\STC_Datapath16_v1_0\STC_Datapath16_v1_0.v"
`else
`define CY_BLK_DIR "Z:\scottcarlson On My Mac\Code\PSoC_Creator\Design01\Design01.cydsn\Design01.cydsn\STC_Datapath16_v1_0"
`include "Z:\scottcarlson On My Mac\Code\PSoC_Creator\Design01\Design01.cydsn\Design01.cydsn\STC_Datapath16_v1_0\STC_Datapath16_v1_0.v"
`endif
// Component: CyStatusReg_v1_90
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyStatusReg_v1_90"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyStatusReg_v1_90\CyStatusReg_v1_90.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyStatusReg_v1_90"
`include "C:\Program Files\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyStatusReg_v1_90\CyStatusReg_v1_90.v"
`endif
// top
module top ;
wire [7:0] Net_57;
wire Net_56;
wire Net_55;
wire Net_54;
wire Net_53;
wire Net_52;
wire Net_50;
wire Net_45;
wire Net_44;
wire Net_43;
wire Net_42;
wire Net_49;
wire Net_48;
wire Net_47;
wire Net_46;
wire Net_36;
STC_Datapath16_v1_0 STC_Datapath16_v1_00 (
.Clock(Net_36),
.Reset(1'b0),
.State_0(Net_47),
.State_1(Net_48),
.State_2(Net_49));
defparam STC_Datapath16_v1_00.A0_init_a = 0;
defparam STC_Datapath16_v1_00.A0_init_b = 0;
defparam STC_Datapath16_v1_00.A1_init_a = 0;
defparam STC_Datapath16_v1_00.A1_init_b = 0;
defparam STC_Datapath16_v1_00.D0_init_a = 0;
defparam STC_Datapath16_v1_00.D0_init_b = 0;
defparam STC_Datapath16_v1_00.D1_init_a = 0;
defparam STC_Datapath16_v1_00.D1_init_b = 0;
cy_clock_v1_0
#(.id("b4b5e17f-634b-4c3d-aaa4-f65d9e49df2e"),
.source_clock_id(""),
.divisor(0),
.period("83333333."),
.is_direct(0),
.is_digital(1))
Clock_1
(.clock_out(Net_36));
cy_dma_v1_0
#(.drq_type(2'b10))
DMA_1
(.drq(1'b0),
.trq(1'b0),
.nrq(Net_45));
CyStatusReg_v1_90 Status_Reg_1 (
.status_0(Net_47),
.status_1(Net_48),
.status_2(Net_49),
.status_3(1'b0),
.clock(Net_36),
.status_4(1'b0),
.status_5(1'b0),
.status_6(1'b0),
.status_7(1'b0),
.intr(Net_56),
.status_bus(8'b0));
defparam Status_Reg_1.Bit0Mode = 0;
defparam Status_Reg_1.Bit1Mode = 0;
defparam Status_Reg_1.Bit2Mode = 0;
defparam Status_Reg_1.Bit3Mode = 0;
defparam Status_Reg_1.Bit4Mode = 0;
defparam Status_Reg_1.Bit5Mode = 0;
defparam Status_Reg_1.Bit6Mode = 0;
defparam Status_Reg_1.Bit7Mode = 0;
defparam Status_Reg_1.BusDisplay = 0;
defparam Status_Reg_1.Interrupt = 0;
defparam Status_Reg_1.MaskValue = 0;
defparam Status_Reg_1.NumInputs = 8;
endmodule
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
`define low_pos(w,b) ((w)*64 + (b)*8)
`define low_pos2(w,b) `low_pos(w,7-b)
`define high_pos(w,b) (`low_pos(w,b) + 7)
`define high_pos2(w,b) (`low_pos2(w,b) + 7)
module keccak(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output [511:0] out;
output reg out_ready;
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
wire [575:0] padder_out,
padder_out_1; /* before reorder byte */
wire padder_out_ready;
wire f_ack;
wire [1599:0] f_out;
wire f_out_ready;
wire [511:0] out1; /* before reorder byte */
reg [22:0] i; /* gen "out_ready" */
genvar w, b;
assign out1 = f_out[1599:1599-511];
always @ (posedge clk)
if (reset)
i <= 0;
else
i <= {i[21:0], state & f_ack};
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
/* reorder byte ~ ~ */
generate
for(w=0; w<8; w=w+1)
begin : L0
for(b=0; b<8; b=b+1)
begin : L1
assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
/* reorder byte ~ ~ */
generate
for(w=0; w<9; w=w+1)
begin : L2
for(b=0; b<8; b=b+1)
begin : L3
assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (i[22])
out_ready <= 1;
padder
padder_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack);
f_permutation
f_permutation_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready);
endmodule
`undef low_pos
`undef low_pos2
`undef high_pos
`undef high_pos2
|
#include <bits/stdc++.h> using namespace std; int how_many(string s, vector<string>& deleted) { int res = 0; for (auto i : deleted) for (int j = 0; j < s.size(); j++) { if (i[j] != s[j]) break; if (j == s.size() - 1) res++; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<string> deleted(n); for (int i = 0; i < n; i++) cin >> deleted[i]; string res = ; long long curr = ((1LL << m) + 1 - n) / 2; for (int i = 0; i < m; i++) { long long x = (1LL << (m - i - 1)) - how_many(res + 0 , deleted); if (x >= curr) res.push_back( 0 ); else { res.push_back( 1 ); curr -= x; } } cout << res << n ; } return 0; }
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module pulse_synchronizer
( input pulse_in_clkA,
input clkA,
output pulse_out_clkB,
input clkB,
input reset_clkA,
input reset_clkB
);
reg ackA;
reg ackB;
reg ackA_synch;
reg ackA_clkB;
reg ackB_synch;
reg ackB_clkA;
reg pulse_in_clkA_d1;
reg ackA_clkB_d1;
reg ackB_d1;
/* detect rising edges in clkA domain, set the ackA signal
* until the pulse is acked from the other domain */
always @(posedge clkA) begin
if(reset_clkA) begin
ackA <= 0;
end
else if(!pulse_in_clkA_d1 & pulse_in_clkA) begin
ackA <= 1;
end
else if(ackB_clkA) begin
ackA <= 0;
end
end // always @ (posedge clkA)
/* detect the rising edge of ackA and set ackB until ackA falls */
always @(posedge clkB) begin
if(reset_clkB) begin
ackB <= 0;
end
else if(!ackA_clkB_d1 & ackA_clkB) begin
ackB <= 1;
end
else if(!ackA_clkB) begin
ackB <= 0;
end
end // always @ (posedge clkB)
/* detect rising edge of ackB and send pulse */
assign pulse_out_clkB = ackB & !ackB_d1;
/* synchronize the ack signals */
always @(posedge clkA) begin
if(reset_clkA) begin
pulse_in_clkA_d1 <= 0;
ackB_synch <= 0;
ackB_clkA <= 0;
end
else begin
pulse_in_clkA_d1 <= pulse_in_clkA;
ackB_synch <= ackB;
ackB_clkA <= ackB_synch;
end
end
/* synchronize the ack signals */
always @(posedge clkB) begin
if(reset_clkB) begin
ackB_d1 <= 0;
ackA_synch <= 0;
ackA_clkB <= 0;
ackA_clkB_d1 <= 0;
end
else begin
ackB_d1 <= ackB;
ackA_synch <= ackA;
ackA_clkB <= ackA_synch;
ackA_clkB_d1 <= ackA_clkB;
end
end
endmodule // pulse_synchronizer
|
/*
* Generate a combinational adder of any width. The width parameter can
* be any integer value >0. The A and B inputs have WID bits, and the Q
* output has WID+1 bits to include the overflow.
*/
module addN
#(parameter WID = 4)
(input wire [WID-1:0] A,
input wire [WID-1:0] B,
output wire [WID:0] Q
/* */);
wire [WID-1:0] Cout;
/* The least significant slice has no Cin */
add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0]));
/* Generate all the remaining slices */
genvar i;
for (i = 1 ; i < WID ; i = i+1) begin : U
add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i]));
end
assign Q[WID] = Cout[WID-1];
endmodule // add
/*
* This is a single-bit combinational adder used by the addH module
* above.
*/
module add1(input A, input B, input Cin, output Q, output Cout);
assign Q = A ^ B ^ Cin;
assign Cout = A&B | A&Cin | B&Cin;
endmodule // hadd
`ifdef TEST_BENCH
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire [WID:0] Q;
addN #(.WID(WID)) usum (.A(A), .B(B), .Q(Q));
int adx;
int bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
A <= adx[WID-1:0];
B <= bdx[WID-1:0];
#1 if (Q !== (adx+bdx)) begin
$display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
$finish;
end
end
end
$display("PASSED");
end
endmodule // main
`endif
|
#include <bits/stdc++.h> int main() { int x, y; scanf( %d%d , &x, &y); int i = 1; while (1) { if (y < 2 || ((100 * x) + (10 * y)) < 220) { if (i & 1 == 1) printf( Hanako ); else printf( Ciel ); return 0; } if (i & 1 == 1) { if (x >= 2) { x -= 2; y -= 2; } else { y -= ((220 - (100 * x))) / 10; x = 0; } } else { if (y >= 22) y -= 22; else if (y >= 12) { x--; y -= 12; } else { x -= 2; y -= 2; } } i++; } return 0; }
|
#include <bits/stdc++.h> template <typename T> T inline SQR(const T &a) { return a * a; } template <typename T> T inline ABS(const T &a) { return a < 0 ? -a : a; } template <typename T> T inline MIN(const T &a, const T &b) { if (a < b) return a; return b; } template <typename T> T inline MAX(const T &a, const T &b) { if (a > b) return a; return b; } const double EPS = 1e-9; inline int sgn(double a) { return a > EPS ? 1 : (a < -EPS ? -1 : 0); } inline int cmp(double a, double b) { return sgn(a - b); } using namespace std; struct orientacao_t { char f, c; char v[4]; orientacao_t() {} orientacao_t(char frente, char costas, char vizinhos[]) : f(frente), c(costas) { for (int i = 0; i < 4; i++) v[i] = vizinhos[i]; } bool operator==(const orientacao_t &o) const { if (f == o.f && c == o.c) { if (v[0] == o.v[0] && v[1] == o.v[1] && v[2] == o.v[2] && v[3] == o.v[3]) return true; if (v[0] == o.v[1] && v[1] == o.v[2] && v[2] == o.v[3] && v[3] == o.v[0]) return true; if (v[0] == o.v[2] && v[1] == o.v[3] && v[2] == o.v[0] && v[3] == o.v[1]) return true; if (v[0] == o.v[3] && v[1] == o.v[0] && v[2] == o.v[1] && v[3] == o.v[2]) return true; } if (f == o.c && c == o.f) { if (v[2] == o.v[0] && v[1] == o.v[1] && v[0] == o.v[2] && v[3] == o.v[3]) return true; if (v[2] == o.v[1] && v[1] == o.v[2] && v[0] == o.v[3] && v[3] == o.v[0]) return true; if (v[2] == o.v[2] && v[1] == o.v[3] && v[0] == o.v[0] && v[3] == o.v[1]) return true; if (v[2] == o.v[3] && v[1] == o.v[0] && v[0] == o.v[1] && v[3] == o.v[2]) return true; } return false; } void operator=(const orientacao_t &o) { f = o.f; c = o.c; for (int i = 0; i < 4; i++) v[i] = o.v[i]; } }; struct cubo_t { orientacao_t orientacao[3]; cubo_t() {} cubo_t(char a, char b, char c, char d, char e, char f) { char v[4]; v[0] = e; v[1] = d; v[2] = c; v[3] = b; orientacao[0] = orientacao_t(a, f, v); v[0] = e; v[1] = a; v[2] = c; v[3] = f; orientacao[1] = orientacao_t(b, d, v); v[0] = d; v[1] = a; v[2] = b; v[3] = f; orientacao[2] = orientacao_t(e, c, v); } bool operator==(const cubo_t &c) const { for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) if (orientacao[i] == c.orientacao[j]) return true; return false; } void operator=(const cubo_t &c) { orientacao[0] = c.orientacao[0]; orientacao[1] = c.orientacao[1]; orientacao[2] = c.orientacao[2]; } }; int main(int argc, char *argv[]) { ios::sync_with_stdio(false); string s; cin >> s; sort(s.begin(), s.end()); vector<cubo_t> cubes; int eq = 0; do { cubo_t aux = cubo_t(s[0], s[1], s[2], s[3], s[4], s[5]); for (int i = 0; i < int((cubes).size()); ++i) if (aux == cubes[i]) goto hell; cubes.push_back(aux); hell: eq++; } while (next_permutation(s.begin(), s.end())); cout << int((cubes).size()) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXK = 3000; struct Update { int cost; long long profit; }; struct CommutativeUndoableDS { vector<array<long long, MAXK + 1> > dp; CommutativeUndoableDS() { dp.emplace_back(); fill(dp.back().begin(), dp.back().end(), 0); } void addUpdate(Update u) { int sz = dp.size(); dp.push_back(dp.back()); for (int i = MAXK; i >= u.cost; i--) { dp[sz][i] = max(dp[sz][i], dp[sz - 1][i - u.cost] + u.profit); } } void undoLastUpdate() { dp.pop_back(); assert(!dp.empty()); } long long operator[](int i) { return dp.back()[i]; } }; struct QueueUndoDS { vector<pair<Update, int> > qyu; CommutativeUndoableDS ds; int rem_a; QueueUndoDS() { rem_a = 0; } void pushBack(pair<Update, int> u) { ds.addUpdate(u.first); qyu.emplace_back(u); } void pushBack(Update u) { pushBack(pair<Update, int>(u, 1)); } void popFront() { assert(!qyu.empty()); if (rem_a == 0) { rem_a = qyu.size(); for (int i = 0; i < rem_a; i++) ds.undoLastUpdate(); reverse(qyu.begin(), qyu.end()); for (pair<Update, int> &u : qyu) { u.second = 0; ds.addUpdate(u.first); } } vector<pair<Update, int> > popped[2]; while (qyu.back().second == 1) { popped[1].push_back(qyu.back()); qyu.pop_back(); ds.undoLastUpdate(); } int sz = rem_a & (-rem_a); for (int i = 0; i < sz; i++) { assert(qyu.back().second == 0); popped[0].push_back(qyu.back()); qyu.pop_back(); ds.undoLastUpdate(); } for (int z : {1, 0}) { reverse(popped[z].begin(), popped[z].end()); for (pair<Update, int> &u : popped[z]) pushBack(u); } assert(qyu.back().second == 0); ds.undoLastUpdate(); qyu.pop_back(); rem_a--; } }; vector<long long> a[MAXK]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; QueueUndoDS qds; for (int i = 1; i <= n; i++) { int sz; cin >> sz; a[i].resize(sz + 1); for (int j = 1; j <= sz; j++) { cin >> a[i][j]; a[i][j] += a[i][j - 1]; } if (sz > k) a[i].resize(k + 1); qds.pushBack({(int)a[i].size() - 1, a[i].back()}); } long long ans = -1; for (int i = 1; i <= n; i++) { qds.popFront(); for (int j = 0; j < a[i].size(); j++) { ans = max(ans, a[i][j] + qds.ds[k - j]); } qds.pushBack({(int)a[i].size() - 1, a[i].back()}); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxx = 1e5 + 7; const int Inf = 1 << 30; const long long INF = 1ll << 60; int n; int a[maxx]; vector<int> vec; int pos[maxx]; map<int, int> mp; int ans; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; int cnt = 0; int t = 0; bool flg = 0; for (int i = 1; i <= n; i++) { if (a[i] == 1) { if (!flg) pos[++t] = i; flg = 1; cnt++; } else { if (cnt) vec.push_back(cnt); cnt = 0; flg = 0; } if (i == n && a[i] == 1) vec.push_back(cnt); } for (int i = 0; i < vec.size(); i++) mp[pos[i + 1]] = vec[i]; int pp = pos[1] - 1; int minx = min(pp, mp[pos[1]]); ans = max(ans, 2 * minx); for (int i = 1; i <= t; i++) { int tmp; if (i == 1) tmp = minx; else tmp = pos[i] - (pos[i - 1] + mp[pos[i - 1]]); int min1 = min(tmp, mp[pos[i]]); int min2 = min(tmp, mp[pos[i - 1]]); int minT = max(min1, min2); ans = max(ans, 2 * minT); } int dd = n - (pos[t] + mp[pos[t]] - 1); int min0 = min(dd, mp[pos[t]]); ans = max(ans, 2 * min0); cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; void optimise() { ios_base::sync_with_stdio(false); cin.tie(NULL); } long long int mod = 1e9 + 7; void normalize(long long int &a) { a = (a + mod) % mod; } long long int modmul(long long int a, long long int b) { a = a % mod; b = b % mod; normalize(a); normalize(b); return (a * b) % mod; } long long int modadd(long long int a, long long int b) { a = a % mod; b = b % mod; normalize(a); normalize(b); return (a + b) % mod; } long long int modsub(long long int a, long long int b) { a = a % mod; b = b % mod; normalize(a); normalize(b); return (a - b + mod) % mod; } long long int me(long long int x, long long int n) { x %= mod; if (n == 0) return 1; long long int u = me(x, n / 2) % mod; u = (u * u) % mod; if (n % 2) u = (u * x) % mod; return u; } long long int me1(long long int x, long long int n) { if (n == 0) return 1; long long int u = me1(x, n / 2); u = u * u; if (n % 2) u = u * x; return u; } inline long long int modInv(long long int a) { return me(a, mod - 2); } inline long long int modDiv(long long int a, long long int b) { return modmul(a, modInv(b)); } float power(float x, long long int y) { float temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp; else { if (y > 0) return x * temp * temp; else return (temp * temp) / x; } } long long int __gcd(long long int a, long long int b) { if (b == 0) return a; else return __gcd(b, a % b); } pair<long long int, long long int> operator+( pair<long long int, long long int> a, pair<long long int, long long int> b) { return {a.first + b.first, a.second + b.second}; } pair<long long int, long long int> operator-( pair<long long int, long long int> a, pair<long long int, long long int> b) { return {a.first - b.first, a.second - b.second}; } pair<long long int, long long int> operator*( pair<long long int, long long int> a, pair<long long int, long long int> b) { return {a.first * b.first, a.second * b.second}; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { for (auto it : v) os << it << ; return os; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (long long int i = 0; i < v.size(); ++i) os << v[i] << ; return os; } bool compare(string s1, string s2) { return s1.size() < s2.size(); } void solve() { long long int n, k; cin >> n >> k; vector<pair<long long int, long long int> > v; if (n > k * (k - 1)) { cout << No ; return; } cout << Yes << n ; for (long long int i = 0; i < k; i++) { for (long long int j = i + 1; j < k; j++) { n--; cout << i + 1 << << j + 1 << n ; if (n == 0) return; n--; cout << j + 1 << << i + 1 << n ; if (n == 0) return; } } } signed main() { optimise(); long long int t; t = 1; cout << fixed << setprecision(5); while (t--) { solve(); cout << n ; } cerr << n << Time Elasped : << 1.0 * clock() / CLOCKS_PER_SEC << n ; }
|
#include <bits/stdc++.h> using namespace std; string s[105]; int main() { int n, m, cnt = 0, t, tt, temp, dis = 0, ans = 0, len; int row = 0, rowup = 2e9, rowdn = -1, col = 0, collft = 2e9, colrt = -1; int rowupcol, rowdncol, collftrow, colrtrow; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == B ) { cnt++; if (i < rowup) { rowup = i; rowupcol = j; } if (rowdn < i) { rowdn = i; rowdncol = j; } if (j < collft) { collft = j; collftrow = i; } if (colrt < j) { colrt = j; colrtrow = i; } } } } if (!cnt) printf( 1 n ); else if (cnt == 1) printf( 0 n ); else { len = max(rowdn - rowup + 1, colrt - collft + 1); if (len > n || len > m) printf( -1 n ); else printf( %d n , (len * len) - cnt); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4B_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int M = 220000; vector<int> e1[M], e2[M]; int p[M], dis[M]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; e1[u].push_back(v); e2[v].push_back(u); } int k; cin >> k; for (int i = 0; i < k; i++) cin >> p[i]; queue<int> q; q.push(p[k - 1]); dis[p[k - 1]] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int v : e2[u]) { if (dis[v] == 0) { dis[v] = dis[u] + 1; q.push(v); } } } int mi = 0, mx = 0; for (int i = 0; i < k - 1; i++) { if (dis[p[i]] != dis[p[i + 1]] + 1) ++mi; for (int v : e1[p[i]]) { if (v != p[i + 1] && dis[p[i]] == dis[v] + 1) { ++mx; break; } } } cout << mi << << mx << endl; return 0; }
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: SEG7_LUT
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module SEG7_LUT ( oSEG,iDIG );
input [3:0] iDIG;
output [6:0] oSEG;
reg [6:0] oSEG;
always @(iDIG)
begin
case(iDIG)
4'h1: oSEG = 7'b1111001; // ---t----
4'h2: oSEG = 7'b0100100; // | |
4'h3: oSEG = 7'b0110000; // lt rt
4'h4: oSEG = 7'b0011001; // | |
4'h5: oSEG = 7'b0010010; // ---m----
4'h6: oSEG = 7'b0000010; // | |
4'h7: oSEG = 7'b1111000; // lb rb
4'h8: oSEG = 7'b0000000; // | |
4'h9: oSEG = 7'b0011000; // ---b----
4'ha: oSEG = 7'b0001000;
4'hb: oSEG = 7'b0000011;
4'hc: oSEG = 7'b1000110;
4'hd: oSEG = 7'b0100001;
4'he: oSEG = 7'b0000110;
4'hf: oSEG = 7'b0001110;
4'h0: oSEG = 7'b1000000;
endcase
end
endmodule
|
`define ADDER_WIDTH 023
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O41AI_PP_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-3; const int SZ = 4000050, INF = 0x7FFFFFFF; const double PI = acos(-1); struct nd { double a, b, c, d, e; nd(double _a = 0, double _b = 0, double _c = 0, double _d = 0, double _e = 0) : a(_a), b(_b), c(_c), d(_d), e(_e) {} nd operator-(nd &rbs) { return nd(a - rbs.a, b - rbs.b, c - rbs.c, d - rbs.d, e - rbs.e); } }; double len(nd &x) { double res = sqrt(x.a * x.a + x.b * x.b + x.c * x.c + x.d * x.d + x.e * x.e); return res; } double Dot(nd &x, nd &y) { return (x.a * y.a + x.b * y.b + x.c * y.c + x.d * y.d + x.e * y.e) / len(x) / len(y); } bool test(nd &x, nd &y) { double ang = acos(Dot(x, y)); return ang < (PI / 2) && fabs(ang - (PI / 2)) > EPS; } int main() { int pnum; cin >> pnum; vector<nd> vct; if (pnum > 11) { cout << 0 << endl; return 0; } for (int i = 0; i < pnum; ++i) { nd tmp; cin >> tmp.a >> tmp.b >> tmp.c >> tmp.d >> tmp.e; vct.push_back(tmp); } vector<int> res; for (int i = 0; i < pnum; ++i) { bool ok = 1; for (int j = 0; j < pnum; ++j) { if (j == i) continue; for (int k = 0; k < pnum; ++k) { if (k == j) continue; nd ac = vct[j] - vct[i]; nd bc = vct[k] - vct[i]; if (test(ac, bc)) ok = 0; } } if (ok) { res.push_back(i + 1); } } cout << res.size() << endl; for (int i = 0; i < res.size(); ++i) { cout << res[i] << endl; } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:58:27 12/03/2015
// Design Name: div_64
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/Div64b/Div_tst.v
// Project Name: Div64b
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: div_64
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Div_tst;
// Inputs
reg clk;
reg rst;
reg init_in;
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [63:0] Result;
wire busy;
// Instantiate the Unit Under Test (UUT)
div_64 uut (
.clk(clk),
.rst(rst),
.init_in(init_in),
.A(A),
.B(B),
.Result(Result),
.busy(busy)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
init_in = 0;
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
#100;
A = 64'd8835 << 32;
B = 64'd100000000;
#20 init_in = 1;
#40 init_in = 0;
while(busy)#10;
#50;
A = 64'd289505280 << 32;
B = 64'd100000000;
#20 init_in = 1;
#40 init_in = 0;
end
always #5 clk = !clk;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_i2f(
input sys_clk,
input alu_rst,
input [31:0] a,
input valid_i,
output [31:0] r,
output valid_o
);
/* Stage 1 */
reg s1_valid;
reg s1_sign;
reg [30:0] s1_abs;
reg s1_zero;
always @(posedge sys_clk) begin
if(alu_rst)
s1_valid <= 1'b0;
else
s1_valid <= valid_i;
s1_sign <= a[31];
if(a[31])
s1_abs <= 31'd0 - a[30:0];
else
s1_abs <= a[30:0];
s1_zero <= a == 32'd0;
end
/* Stage 2 */
wire [4:0] s1_clz;
pfpu_clz32 clz32(
.d({s1_abs, 1'bx}),
.clz(s1_clz)
);
reg s2_valid;
reg s2_sign;
reg [7:0] s2_expn;
reg [30:0] s2_mant;
always @(posedge sys_clk) begin
if(alu_rst)
s2_valid <= 1'b0;
else
s2_valid <= s1_valid;
s2_sign <= s1_sign;
s2_mant <= s1_abs << s1_clz;
if(s1_zero)
s2_expn <= 8'd0;
else
s2_expn <= 8'd157 - {4'd0, s1_clz};
end
assign r = {s2_sign, s2_expn, s2_mant[29:7]};
assign valid_o = s2_valid;
endmodule
|
// $Id: c_fbmult.v 1836 2010-03-23 02:35:46Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic feedback multiplier for multi-input LFSRs
module c_fbmult
(feedback, complete, data_in, data_out);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// how many iterations to perform at once
parameter iterations = 1;
// feedback polynomial(s)
input [0:width-1] feedback;
// include all-zeros state in state sequence
input complete;
// data input
input [0:width-1] data_in;
// data output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [0:width-1] feedback_seeds;
wire [0:width*width-1] iter_matrix_noshift_transposed;
generate
if(width == 1)
begin
assign feedback_seeds = complete ^ data_in;
assign iter_matrix_noshift_transposed = feedback;
end
else
begin
assign feedback_seeds[0:(width-1)-1] = data_in[0:(width-1)-1];
assign feedback_seeds[width-1]
= (~|data_in[0:(width-1)-1] & complete) ^ data_in[width-1];
assign iter_matrix_noshift_transposed
= {{((width-1)*width){1'b0}}, feedback};
end
endgenerate
wire [0:width*width-1] iter_matrix_noshift;
c_interleaver
#(.width(width*width),
.num_blocks(width))
iter_matrix_noshift_intl
(.data_in(iter_matrix_noshift_transposed),
.data_out(iter_matrix_noshift));
wire [0:width*width-1] initial_matrix;
wire [0:(iterations+1)*width*width-1] matrices;
assign matrices[0:width*width-1] = initial_matrix;
wire [0:width*width-1] feedback_matrix;
assign feedback_matrix
= matrices[iterations*width*width:(iterations+1)*width*width-1];
wire [0:width*width-1] iter_matrix;
wire [0:width*width-1] feedback_matrix_noshift;
generate
genvar row;
for(row = 0; row < width; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < width; col = col + 1)
begin:cols
wire invert;
assign invert = (row == (col + 1));
assign iter_matrix[row*width+col]
= iter_matrix_noshift[row*width+col] ^ invert;
assign feedback_matrix_noshift[row*width+col]
= feedback_matrix[row*width+col] ^ invert;
wire sethi;
assign sethi = (row == col);
assign initial_matrix[row*width+col] = sethi;
end
end
genvar iter;
for(iter = 0; iter < iterations; iter = iter+1)
begin:iters
wire [0:width*width-1] in_matrix;
assign in_matrix = matrices[iter*width*width:(iter+1)*width*width-1];
wire [0:width*width-1] out_matrix;
c_mat_mult
#(.dim1_width(width),
.dim2_width(width),
.dim3_width(width))
out_matrix_mmult
(.input_a(iter_matrix),
.input_b(in_matrix),
.result(out_matrix));
assign matrices[(iter+1)*width*width:(iter+2)*width*width-1]
= out_matrix;
end
endgenerate
wire [0:width-1] feedback_sum;
c_mat_mult
#(.dim1_width(width),
.dim2_width(width),
.dim3_width(1))
feedback_sum_mmult
(.input_a(feedback_matrix_noshift),
.input_b(feedback_seeds),
.result(feedback_sum));
assign data_out = feedback_sum;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433832795l; template <typename T> inline auto sqr(T x) -> decltype(x * x) { return x * x; } template <typename T1, typename T2> inline bool umx(T1& a, T2 b) { if (a < b) { a = b; return 1; } return 0; } template <typename T1, typename T2> inline bool umn(T1& a, T2 b) { if (b < a) { a = b; return 1; } return 0; } struct Input { int n, k; bool read() { if (!(cin >> n >> k)) { return false; } return true; } void init(const Input& input) { *this = input; } }; struct Data : Input { long long ans; void write() { cout << ans << n ; } virtual void solve() {} virtual void clear() { *this = Data(); } }; struct Solution : Data { void solve() { ans = 0; while (n > 1 && k > 0) { ans += 2 * (n - 1) - 1; n -= 2; --k; } } void clear() { *this = Solution(); } }; Solution sol; int main() { cout.setf(ios::showpoint | ios::fixed); cout.precision(20); sol.read(); sol.solve(); sol.write(); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool check[100]; int main() { int n; string s; cin >> n; cin >> s; int ans = 0; for (int x = 0; x < s.size(); ++x) { if (!check[s[x] - a ]) { ans++; check[s[x] - a ] = 1; } } cout << ((ans >= n) ? YES : NO ) << endl; if (ans >= n) { for (int x = 0; x < s.size(); ++x) { if (n) { if (check[s[x] - a ]) { if (x) cout << endl; cout << s[x]; check[s[x] - a ] = 0; n--; } else { cout << s[x]; } } else cout << s[x]; } cout << endl; } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; pair<int, int> p[10][10]; int nom[4]; bool cmp(int a, int b) { if (p[a][0] != p[b][0]) return (p[a][0] < p[b][0]); else return (p[a][1] < p[b][1]); } int main() { for (int i = (0); i < (4); i++) { for (int j = (0); j < (2); j++) { scanf( %d%d , &p[i][j].first, &p[i][j].second); } if (p[i][0].first == p[i][1].first) { if (p[i][0].second > p[i][1].second) swap(p[i][0], p[i][1]); } else { if (p[i][0].first > p[i][1].first) swap(p[i][0], p[i][1]); } } for (int i = (0); i < (4); i++) nom[i] = i; sort(nom, nom + 4, &cmp); if (p[nom[1]][0].second == p[nom[1]][1].second && p[nom[1]][0].first != p[nom[1]][1].first) { if (p[nom[0]][0].first == p[nom[0]][1].first && p[nom[0]][0].second != p[nom[0]][1].second) { if (p[nom[2]][0].second == p[nom[2]][1].second && p[nom[2]][0].first != p[nom[2]][1].first) { if (p[nom[3]][0].first == p[nom[3]][1].first && p[nom[3]][0].second != p[nom[3]][1].second) { if (p[nom[0]][0] == p[nom[1]][0] && p[nom[0]][1] == p[nom[2]][0] && p[nom[2]][1] == p[nom[3]][1] && p[nom[3]][0] == p[nom[1]][1]) { printf( YES n ); return 0; } } } } } printf( NO n ); return 0; }
|
#include <bits/stdc++.h> #define int long long using namespace std; signed main(){ int t; cin >> t; while(t--){ int k, n, m; cin >> k >> n >> m; int a[n + 1], b[m + 1]; for(int i = 0;i < n;i++){ cin >> a[i]; } for(int i = 0;i < m;i++){ cin >> b[i]; } a[n] = 0x3f3f3f3f, b[m] = 0x3f3f3f3f; vector<int> ans; //答案序列 int l = k, ai = 0, bi = 0; //ai，bi分别表示两个数组分别删到了哪里，l为行数 bool flag = false; while(ans.size() < n + m){ if(a[ai] == 0){ ai++, ans.push_back(0); l++; continue; } else if(b[bi] == 0){ bi++, ans.push_back(0); l++; continue; } int p = min(a[ai], b[bi]); if(p == a[ai]){ ai++; } else{ bi++; } if(p > l){ flag = true; break; } ans.push_back(p); } if(flag){ cout << -1 << endl; } else{ for(int i = 0;i < ans.size();i++){ cout << ans[i] << ; //输出答案序列 } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; string g[51]; int pre[52][52]; int dp[51][51][51][51]; bool chk(int x1, int x2, int y1, int y2) { int r = pre[x2][y2] - pre[x1][y1 - 1] - pre[x1 - 1][y1] + pre[x1 - 1][y1 - 1]; if (r >= 1) return true; return false; } int fun(int r1, int r2, int c1, int c2) { if (chk(r1, r2, c1, c2) == false) return 0; if (dp[r1][r2][c1][c2] != -1) return dp[r1][r2][c1][c2]; int ans = max((r2 - r1 + 1), (c2 - c1 + 1)); for (int i = r1; i < r2; i++) ans = min(ans, fun(r1, i, c1, c2) + fun(i + 1, r2, c1, c2)); for (int j = c1; j < c2; j++) { ans = min(ans, fun(r1, r2, c1, j) + fun(r1, r2, j + 1, c2)); } return dp[r1][r2][c1][c2] = ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; memset(dp, -1, sizeof(dp)); for (int i = 0; i < n; i += 1) cin >> g[i]; pre[0][0] = 1; for (int i = 0; i < n; i++) { pre[i][0] = pre[0][i] = 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (g[i][j] == # ) pre[i + 1][j + 1] = 1; pre[i + 1][j + 1] += (pre[i][j + 1] + pre[i + 1][j] - pre[i][j]); } } int ans = fun(1, n, 1, n); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, l, r, shag = 0; cin >> n; l = 1; r = n; while (l <= r) { if (shag % 2 == 0) cout << l++ << ; else cout << r-- << ; shag++; } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_l2d_rep_bot.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_r_l2d_rep_bot (/*AUTOARG*/
// Outputs
fuse_l2d_rden_buf, fuse_l2d_wren_buf, si_buf, arst_l_buf, se_buf,
sehold_buf, fuse_l2d_rid_buf, fuse_read_data_in_buf,
fuse_l2d_data_in_buf, word_en_l, col_offset_l, set_l, wr_en_l,
way_sel_l, decc_in_l, scbuf_scdata_fbdecc_top_buf,
scbuf_scdata_fbdecc_bot_buf, sbdt_l, sbdb_l, fuse_clk1_buf,
fuse_clk2_buf, mem_write_disable_buf,
// Inputs
fuse_l2d_rden, fuse_l2d_wren, si, arst_l, se, sehold,
fuse_l2d_rid, fuse_read_data_in, fuse_l2d_data_in, word_en,
col_offset, set, wr_en, way_sel, decc_in, fbdt_l, fbdb_l,
scdata_scbuf_decc_top, scdata_scbuf_decc_bot,
efc_scdata_fuse_clk1, efc_scdata_fuse_clk2, mem_write_disable
);
input fuse_l2d_rden;
input [5:0] fuse_l2d_wren;
input si;
input arst_l;
input se;
input sehold;
input [2:0] fuse_l2d_rid;
input fuse_read_data_in;
input fuse_l2d_data_in;
input [3:0] word_en;
input col_offset;
input [9:0] set;
input wr_en;
input [11:0] way_sel;
input [155:0] decc_in;
input [155:0] fbdt_l;
input [155:0] fbdb_l;
input [155:0] scdata_scbuf_decc_top;
input [155:0] scdata_scbuf_decc_bot;
input efc_scdata_fuse_clk1;
input efc_scdata_fuse_clk2;
input mem_write_disable;
output fuse_l2d_rden_buf;
output [5:0] fuse_l2d_wren_buf;
output si_buf;
output arst_l_buf;
output se_buf;
output sehold_buf;
output [2:0] fuse_l2d_rid_buf;
output fuse_read_data_in_buf;
output fuse_l2d_data_in_buf;
output [3:0] word_en_l;
output col_offset_l;
output [9:0] set_l;
output wr_en_l;
output [11:0] way_sel_l;
output [155:0] decc_in_l;
output [155:0] scbuf_scdata_fbdecc_top_buf;
output [155:0] scbuf_scdata_fbdecc_bot_buf;
output [155:0] sbdt_l;
output [155:0] sbdb_l;
output fuse_clk1_buf;
output fuse_clk2_buf;
output mem_write_disable_buf;
///////////////////////////////////////////////////////////////////////
// Non-inverting Buffers
///////////////////////////////////////////////////////////////////////
assign fuse_l2d_rden_buf = fuse_l2d_rden;
assign fuse_l2d_wren_buf[5:0] = fuse_l2d_wren[5:0];
assign si_buf = si;
assign arst_l_buf = arst_l;
assign se_buf = se;
assign sehold_buf = sehold;
assign fuse_l2d_rid_buf[2:0] = fuse_l2d_rid[2:0];
assign fuse_read_data_in_buf = fuse_read_data_in;
assign fuse_l2d_data_in_buf = fuse_l2d_data_in;
assign fuse_clk1_buf = efc_scdata_fuse_clk1;
assign fuse_clk2_buf = efc_scdata_fuse_clk2;
assign mem_write_disable_buf = mem_write_disable;
///////////////////////////////////////////////////////////////////////
// Inverting Buffers
///////////////////////////////////////////////////////////////////////
assign word_en_l[3:0] = ~word_en[3:0];
assign col_offset_l = ~col_offset;
assign set_l[9:0] = ~set[9:0];
assign wr_en_l = ~wr_en;
assign way_sel_l = ~way_sel;
assign decc_in_l[155:0] = ~decc_in[155:0];
assign scbuf_scdata_fbdecc_top_buf[155:0] = ~fbdt_l[155:0];
assign scbuf_scdata_fbdecc_bot_buf[155:0] = ~fbdb_l[155:0];
assign sbdt_l[155:0] = ~scdata_scbuf_decc_top[155:0];
assign sbdb_l[155:0] = ~scdata_scbuf_decc_bot[155:0];
endmodule // bw_r_l2d_rep_bot
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:04:44 02/23/2015
// Design Name:
// Module Name: Descale_pipeline
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Descale_pipeline(
input [31:0] x_scale,
input [31:0] y_scale,
input [31:0] z_scale,
input [31:0] k_in,
input [7:0] InsTagScaleOut,
input ScaleValid,
input NatLogFlagScaleOut,
input reset,
input clock,
output [31:0] x_out,
output [31:0] y_out,
output [31:0] z_out,
output done,
output [7:0] InsTagFinal
);
wire doneSpare;
wire [7:0] InsTagFinalSpare;
wire [31:0] z_outSpare;
mult_descale_pipeline DescalePipe_x (
.a_multiplicand(x_scale),
.b_multiplier(k_in),
.z_scale(z_scale),
.InsTagScaleOut(InsTagScaleOut),
.ScaleValid(ScaleValid),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.reset(reset),
.clock(clock),
.FinalProduct(x_out),
.done(done),
.InsTagDescale(InsTagFinal),
.z_out(z_out)
);
mult_descale_pipeline DescalePipe_y (
.a_multiplicand(y_scale),
.b_multiplier(k_in),
.z_scale(z_scale),
.InsTagScaleOut(InsTagScaleOut),
.ScaleValid(ScaleValid),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.reset(reset),
.clock(clock),
.FinalProduct(y_out),
.done(doneSpare),
.InsTagDescale(InsTagFinalSpare),
.z_out(z_outSpare)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[8000]; char s[8000]; int main() { scanf( %s , s); int n = strlen(s), m = n; if (s[0] == * || s[0] == / ) { puts( 0 ); return 0; } f[m] = 1; for (int i = 0; i < n; i++) if (!isdigit(s[i])) if (s[i + 1] == * || s[i + 1] == / || i == n - 1) { puts( 0 ); return 0; } else m--; else if (!isdigit(s[i + 1])) for (int j = m + n; j > m; j--) f[j - 1] = (f[j - 1] + f[j]) % 1000003; printf( %d n , f[m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[5050][505]; pair<long long, long long> pre[5050][505]; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long d, s; cin >> d >> s; queue<pair<long long, long long>> q; for (long long i = 1; i < 10; i++) { dp[i][i % d] = 1; q.push({i, i % d}); } while (q.size()) { pair<long long, long long> curr = q.front(); q.pop(); long long sum = curr.first; long long div = curr.second; for (long long i = 0; i <= 9; i++) { long long curr_sum = sum + i; long long curr_div = (div * 10 + i) % d; if (curr_sum <= s and !dp[curr_sum][curr_div]) { dp[curr_sum][curr_div] = dp[sum][div] + 1; q.push({curr_sum, curr_div}); pre[curr_sum][curr_div] = {sum, div}; } } } if (!dp[s][0]) { cout << -1; } else { vector<long long> ans; long long sum = s, div = 0; while (true) { if (dp[sum][div] == 1) { ans.push_back(sum); break; } else { pair<long long, long long> curr = pre[sum][div]; ans.push_back(sum - curr.first); sum = curr.first; div = curr.second; } } reverse(ans.begin(), ans.end()); for (auto x : ans) { cout << x; } } }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 1: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] d1_data_in;
reg [ 1: 0] d2_data_in;
wire [ 1: 0] data_in;
reg [ 1: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 1: 0] edge_detect;
wire irq;
reg [ 1: 0] irq_mask;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({2 {(address == 0)}} & data_in) |
({2 {(address == 2)}} & irq_mask) |
({2 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[1 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int size = 3111; long long mod = 200000007; double p; int x, k, tmpx, a, m, b; double dp[2][1 << 9][2][255]; int main() { cin >> x >> k >> p; tmpx = x; p /= 100; int cur, nxt; m = (1 << 9) - 1; int res = (x & m); x >>= 9; if (x & 1) { a = 0; while (x & 1) { a++; x >>= 1; } dp[0][res][1][a] = 1; } else { a = 0; while (x > 0 && !(x & 1)) { a++; x >>= 1; } dp[0][res][0][a] = 1; } x = tmpx; for (int i = 0; i < k; i++) { cur = i % 2; nxt = (i + 1) % 2; for (int i = 0; i < (1 << 9); i++) { if (i + 1 <= m) { for (int k = 0; k < 250; k++) { dp[nxt][i + 1][0][k] += (1 - p) * dp[cur][i][0][k]; dp[nxt][i + 1][1][k] += (1 - p) * dp[cur][i][1][k]; } } else { for (int k = 0; k < 250; k++) { dp[nxt][0][1][1] += (1 - p) * dp[cur][i][0][k]; dp[nxt][0][0][k] += (1 - p) * dp[cur][i][1][k]; } } if (i * 2 <= m) { for (int k = 0; k < 250; k++) { dp[nxt][i * 2][0][1] += p * dp[cur][i][1][k]; dp[nxt][i * 2][0][k + 1] += p * dp[cur][i][0][k]; } } else { a = i * 2; a &= m; for (int k = 0; k < 250; k++) { dp[nxt][a][1][1] += p * dp[cur][i][0][k]; dp[nxt][a][1][k + 1] += p * dp[cur][i][1][k]; } } } for (int i = 0; i <= m; i++) for (int k = 0; k < 250; k++) dp[cur][i][0][k] = dp[cur][i][1][k] = 0; } double ans = 0; for (int i = 1; i <= m; i++) { a = 0; b = i; while (!(b & 1)) { b >>= 1; a++; } for (int k = 0; k < 250; k++) ans += (dp[nxt][i][0][k] + dp[nxt][i][1][k]) * a; } for (int k = 0; k < 250; k++) { ans += dp[nxt][0][0][k] * (k + 9); ans += dp[nxt][0][1][k] * 9; } printf( %.8lf n , ans); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; inline int sgn(int x) { if (x > -eps || x < eps) return 0; if (x > 0) return 1; else return -1; } struct point { double x, y; point(double a = 0, double b = 0) { x = a; y = b; } point operator+(const point &b) const { return point(x + b.x, y + b.y); } point operator-(const point &b) const { return point(x - b.x, y - b.y); } point operator*(const double &t) const { return point(x * t, y * t); } }; struct circle { point o; double r; }; inline double sqr(double x) { return x * x; } inline double det(const point &a, const point &b) { return a.x * b.y - b.x * a.y; } inline double dist(const point &a, const point &b) { return sqrt(sqr(a.x - b.x) + sqr(a.y - b.y)); } inline double mysqrt(double x) { return sqrt(max(0.0, x)); } inline circle inversion(circle a, point p, double R) { circle res; double d1 = dist(p, a.o); res.r = a.r * R * R / (sqr(d1) - sqr(a.r)); double d2 = R * R / (d1 - a.r) - res.r; res.o = p + (a.o - p) * (d2 / d1); return res; } circle a, b; int k; double R, r, ans; inline void prework() { scanf( %lf%lf%d , &R, &r, &k); } inline void mainwork() { double lx = R * 2, rx = sqr(R * 2) / (2 * r); a.o = point(2 * r + (R - r), 0); a.r = R - r; a = inversion(a, point(0, 0), 2 * R); b.o = point(a.o.x, a.o.y + k * (rx - lx)); b.r = (rx - lx) / 2; b = inversion(b, point(0, 0), 2 * R); ans = b.r; } inline void print() { printf( %.8f n , ans); } int main() { int t; scanf( %d , &t); for (int i = 1; i <= t; i++) { prework(); mainwork(); print(); } return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: async_fifo_fwft.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An asynchronous capable parameterized FIFO. As with all
// first word fall through FIFOs, the RD_DATA will be valid when RD_EMPTY is
// low. Asserting RD_EN will consume the current RD_DATA value and cause the
// next value (if it exists) to appear on RD_DATA on the following cycle. Be sure
// to check if RD_EMPTY is low each cycle to determine if RD_DATA is valid.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module async_fifo_fwft #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
`include "functions.vh"
reg [C_WIDTH-1:0] rData=0;
reg [C_WIDTH-1:0] rCache=0;
reg [1:0] rCount=0;
reg rFifoDataValid=0;
reg rDataValid=0;
reg rCacheValid=0;
wire [C_WIDTH-1:0] wData;
wire wEmpty;
wire wRen = RD_EN || (rCount < 2'd2);
assign RD_DATA = rData;
assign RD_EMPTY = !rDataValid;
// Wrapped non-FWFT FIFO (synthesis attributes applied to this module will
// determine the memory option).
async_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.WR_FULL(WR_FULL),
.RD_EN(wRen),
.RD_DATA(wData),
.RD_EMPTY(wEmpty)
);
always @ (posedge RD_CLK) begin
if (RD_RST) begin
rCount <= #1 0;
rDataValid <= #1 0;
rCacheValid <= #1 0;
rFifoDataValid <= #1 0;
end
else begin
// Keep track of the count
rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);
// Signals when wData from FIFO is valid
rFifoDataValid <= #1 (wRen & !wEmpty);
// Keep rData up to date
if (rFifoDataValid) begin
if (RD_EN | !rDataValid) begin
rData <= #1 wData;
rDataValid <= #1 1'd1;
rCacheValid <= #1 1'd0;
end
else begin
rCacheValid <= #1 1'd1;
end
rCache <= #1 wData;
end
else begin
if (RD_EN | !rDataValid) begin
rData <= #1 rCache;
rDataValid <= #1 rCacheValid;
rCacheValid <= #1 1'd0;
end
end
end
end
endmodule
|
/* Data read from RAM and displayed on one LED while others are a
* binary counter
*/
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
parameter LOG2RAMDELAY = 20;
localparam BITS = 4;
localparam LOG2DELAY = LOG2RAMDELAY + 7;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
wire bout;
reg enable = 0;
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
enable <= counter[LOG2RAMDELAY];
end
memory m1 (clk, enable, bout);
assign LED1 = bout;
assign {LED2, LED3, LED4, LED5} = outcnt;
endmodule
module memory (
input clk,
input inc,
output bout
);
localparam DEPTH = 6;
localparam LEN = 1<<(DEPTH-1);
wire [15:0] data;
reg [DEPTH-1:0] cnt = 0;
// Morse code for "hello"
SB_RAM40_4K #(
.INIT_0(256'h0000000100000000000000010000000000000001000000010000000100000001),
.INIT_1(256'h0000000100010001000000010000000000000001000000010000000100010001),
.INIT_2(256'h0001000100000001000100010000000100010001000000000000000100000001),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000001),
.INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.READ_MODE(2'b01),
.WRITE_MODE(2'b01)
)
mem
(
.RADDR({ 5'b0, cnt}),
.RCLK(clk),
.RCLKE(1'b1),
.RDATA(data),
.RE(1'b1),
.WCLK(clk),
.WCLKE(1'b0)
);
always @(posedge inc) begin
cnt <= cnt + 1;
end
assign bout = data[0];
endmodule // memory
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; long long mod = 1000000007; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void init() {} void solve() { long long x, y, n, i, j; cin >> n; vector<pair<long long, long long> > adj(n - 1); vector<long long> deg(n + 1, 0); for (i = 0; i < n - 1; i++) { cin >> x >> y; deg[x]++; deg[y]++; adj[i] = {x, y}; } vector<long long> edge; for (i = 0; i < n + 1; i++) { if (deg[i] == 1) { edge.push_back(i); } } if ((int)edge.size() == 2) { for (i = 0; i < n - 1; i++) { cout << i << endl; } } else { long long ep = 0, elp = 3; for (i = 0; i < n - 1; i++) { bool flag = false; for (j = 0; j < 3; j++) { if (edge[j] == adj[i].first or edge[j] == adj[i].second) { flag = true; } } if (flag) { cout << ep << endl; ep++; } else { cout << elp << endl; elp++; } } } } int main() { init(); auto start = high_resolution_clock::now(); int T = 1; while (T--) { solve(); } auto stop = high_resolution_clock::now(); auto duration = duration_cast<milliseconds>(stop - start); }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 502; long long c[maxN][maxN]; long long a[maxN]; int n, m, b, md; int main() { cin >> n >> m >> b >> md; for (int i = 1; i <= n; i++) cin >> a[i]; c[0][0] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j < m; j++) for (int t = 0; t <= b - a[i]; t++) if (c[j][t] > 0) { c[j + 1][t + a[i]] = (c[j + 1][t + a[i]] + c[j][t]) % md; } long long ans = 0; for (int i = 0; i <= b; i++) ans = (ans + c[m][i]) % md; cout << ans << endl; return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 27178 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w5,
w128,
w127,
w20,
w107,
w13696,
w13589,
w27178;
assign w1 = i_data0;
assign w107 = w127 - w20;
assign w127 = w128 - w1;
assign w128 = w1 << 7;
assign w13589 = w13696 - w107;
assign w13696 = w107 << 7;
assign w20 = w5 << 2;
assign w27178 = w13589 << 1;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign o_data0 = w27178;
//multiplier_block area estimate = 6057.37431490147;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long qpow(long long x, long long y) { long long re = 1, base = x % mod; while (y) { if (y & 1) re = (re * base) % mod; base = (base * base) % mod; y >>= 1; } return re; } struct node { int to, w; node(int to, int w) : to(to), w(w) {} }; int n, k; vector<node> e[100050]; int deep[100050], f[100050], anc[100050][25]; int up[100050], cnt[2][100050]; void init() { for (int i = 0; i <= n; i++) e[i].clear(); memset(f, 0, sizeof(f)), memset(anc, 0, sizeof(anc)), memset(deep, 0, sizeof(deep)); memset(up, 0, sizeof(up)), memset(cnt, 0, sizeof(cnt)); deep[1] = 1; } void dfs1(int x, int fa) { anc[x][0] = f[x]; for (int i = 1; i <= 20; i++) anc[x][i] = anc[anc[x][i - 1]][i - 1]; for (int i = 0; i < e[x].size(); i++) { int next = e[x][i].to; if (next != fa) { f[next] = x; deep[next] = deep[x] + 1; up[next] = -e[x][i].w; dfs1(next, x); } } } int lca(int x, int y) { if (deep[x] < deep[y]) swap(x, y); for (int i = 20; i >= 0; i--) if (deep[anc[x][i]] >= deep[y]) x = anc[x][i]; if (x == y) return x; for (int i = 20; i >= 0; i--) if (anc[x][i] != anc[y][i]) x = anc[x][i], y = anc[y][i]; return f[x]; } void dfs2(int x) { for (int i = 0; i < e[x].size(); i++) { int next = e[x][i].to; if (next == anc[x][0]) continue; dfs2(next); for (int j = 0; j < 2; j++) cnt[j][x] += cnt[j][next]; } } int main() { scanf( %d , &n); init(); for (int i = 1; i < n; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); if (w == 0) { e[u].push_back(node(v, 0)); e[v].push_back(node(u, 0)); } else { e[u].push_back(node(v, 1)); e[v].push_back(node(u, -1)); } } dfs1(1, 0); scanf( %d , &k); int pre = 1, now; while (k--) { scanf( %d , &now); int x = lca(pre, now); cnt[0][pre]++; cnt[0][x]--; cnt[1][now]++; cnt[1][x]--; pre = now; } dfs2(1); int ans = 0; for (int i = 1; i <= n; i++) { if (!up[i]) continue; if (up[i] == -1) ans = (ans + qpow(2, cnt[0][i]) - 1) % mod; else ans = (ans + qpow(2, cnt[1][i]) - 1) % mod; } ans = (ans + mod) % mod; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> int main() { int s; scanf( %d , &s); char t[s]; scanf( %s , t); int i, count = 0; for (i = 0; i < s; ++i) { if (t[i] == t[i + 1]) ++count; } printf( %d , count); }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler and Nick Desaulniers
//
// Create Date: 11:36:45 04/07/2011
// Design Name: instruction_decode
// Module Name: instruction_decode
// Project Name: Omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: Instruction Decode stage of pipeline
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Added reg_block, need to fix instruction bits (CRC)
// Revision 2.00 - Fixed instruction bits (CRC)
// Revision 3.00 - Changed names on outputs from if -> id (CRC)
// Revision 4.00 - Changed wb_reg_load -> wb_reg_wea, fixed names (CRC)
// Revision 5.00 - Removed sign extend of address and changed size to 7 bits (CRC)
// Revision 6.00 - Removed id_regx_addr, added id_dest_reg_addr (CRC)
// Revision 7.00 - Changed ISA for register destination
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module instruction_decode(
input clk_n,
input [6:0] if_next_addr,
input [15:0] if_curr_inst,
input wb_reg_wea,
input [15:0] wb_reg_wdata,
input [2:0] wb_reg_waddr,
output [3:0] id_opcode, // [15:12]
output [6:0] id_next_addr,
output [15:0] id_register1_data,
output [15:0] id_register2_data,
output [6:0] id_sign_ext_addr, // [6:0]
output [2:0] id_dest_reg_addr // [8:6]
);
assign id_next_addr = if_next_addr;
assign id_opcode = if_curr_inst[15:12];
assign id_dest_reg_addr = if_curr_inst[8:6];
assign id_sign_ext_addr = if_curr_inst[6:0];
reg_block i_reg_block(
.clk_n(clk_n),
.wea(wb_reg_wea),
.raddr1(if_curr_inst[11:9]),
.raddr2(if_curr_inst[5:3]),
.waddr(wb_reg_waddr[2:0]),
.wdata(wb_reg_wdata[15:0]),
.rdata1(id_register1_data[15:0]),
.rdata2(id_register2_data[15:0])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, i; int digits(int n) { int d = 0; while (n) { n /= 10; d++; } return d; } int main() { cin >> a >> b; c = a; d = digits(b); for (i = 1; b; i++) { c += (b % 10) * (int)floor(pow((double)10, (double)d - i)); b /= 10; } cout << c; }
|
//==================================================================================================
// Filename : musoc.v
// Created On : 2015-01-10 21:18:59
// Last Modified : 2015-05-28 09:43:30
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Implementation of the SoC:
// - Core
// - XBAR
// - RAM
// - GPIO
// - UART/Bootloader
//==================================================================================================
module musoc#(
parameter SIM_MODE = "NONE", // Simulation Mode. "SIM" = simulation. "NONE": synthesis mode.
// Core configuration
parameter ENABLE_HW_MULT = 0, // Implement the multiplier
parameter ENABLE_HW_DIV = 0, // Implement the divider
parameter ENABLE_HW_CLO_Z = 0, // Enable CLO/CLZ instructions
// UARTboot
parameter BUS_FREQ = 50, // Bus frequency
// Memory
parameter MEM_ADDR_WIDTH = 12 // 16 KB/4 KW of internal memory
)(
input clk,
input rst,
output halted,
// GPIO
inout [31:0] gpio_a_inout,
// UART
input uart_rx,
output uart_tx
);
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
// master
wire [31:0] master0_address;
wire [3:0] master0_wr;
wire master0_enable;
wire master0_ready;
wire master0_error;
wire [31:0] master1_address;
wire [31:0] master1_data_i;
wire [3:0] master1_wr;
wire master1_enable;
wire master1_ready;
wire master1_error;
wire [31:0] master2_address;
wire [31:0] master2_data_i;
wire [3:0] master2_wr;
wire master2_enable;
wire master2_ready;
wire master2_error; // unused (Bootloader)
wire [31:0] master_data_o;
// slaves
wire [31:0] slave0_data_i;
wire [31:0] slave1_data_i;
wire [31:0] slave2_data_i;
wire slave0_enable;
wire slave1_enable;
wire slave2_enable;
wire slave0_ready;
wire slave1_ready;
wire slave2_ready;
wire [31:0] slave_address;
wire [31:0] slave_data_o;
wire [3:0] slave_wr;
wire [31:0] ms_address;
wire [31:0] ms_data_oi;
wire [31:0] ms_data_io;
wire [3:0] ms_wr;
wire ms_enable;
wire ms_ready;
wire ms_error;
wire [3:0] gpio_interrupt;
wire uart_rx_ready_int;
wire bootloader_reset_core;
wire rst_module;
wire clk_core;
wire clk_bus;
//--------------------------------------------------------------------------
// Clock frequency generator.
//--------------------------------------------------------------------------
clk_generator clock_manager(
.clk_i ( clk ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus )
);
//--------------------------------------------------------------------------
// Reset Manager
// Hold reset for 8 cycles
//--------------------------------------------------------------------------
rst_generator reset_manager(
.clk ( clk_core ),
.rst_i ( rst ),
.rst_o ( rst_module )
);
//--------------------------------------------------------------------------
// MIPS CORE
//--------------------------------------------------------------------------
musb_core #(
.ENABLE_HW_MULT ( ENABLE_HW_MULT ),
.ENABLE_HW_DIV ( ENABLE_HW_DIV ),
.ENABLE_HW_CLO_Z ( ENABLE_HW_CLO_Z )
)
musb_core0(/*AUTOINST*/
.halted ( halted ),
.iport_address ( master0_address[31:0] ),
.iport_wr ( master0_wr[3:0] ),
.iport_enable ( master0_enable ),
.dport_address ( master1_address[31:0] ),
.dport_data_o ( master1_data_i[31:0] ),
.dport_wr ( master1_wr[3:0] ),
.dport_enable ( master1_enable ),
.clk ( clk_core ),
.rst ( rst_module | bootloader_reset_core ),
.interrupts ( {uart_rx_ready_int, gpio_interrupt[3:0]} ),
.nmi ( 1'b0 ),
.iport_data_i ( master_data_o[31:0] ),
.iport_ready ( master0_ready ),
.iport_error ( master0_error ),
.dport_data_i ( master_data_o[31:0] ),
.dport_ready ( master1_ready ),
.dport_error ( master1_error )
);
//--------------------------------------------------------------------------
// XBAR
//--------------------------------------------------------------------------
arbiter #(
.nmasters(3)
)
arbiter0(/*autoinst*/
.clk ( clk_bus ),
.rst ( rst_module ),
.master_address ( {master2_address[31:0], master1_address[31:0], master0_address[31:0]} ),
.master_data_i ( {master2_data_i[31:0], master1_data_i[31:0], 32'hDEAD_C0DE} ),
.master_wr ( {master2_wr[3:0], master1_wr[3:0], master0_wr[3:0]} ),
.master_enable ( {master2_enable, master1_enable ,master0_enable} ),
.master_data_o ( master_data_o[31:0] ),
.master_ready ( {master2_ready, master1_ready, master0_ready} ),
.master_error ( {master2_error, master1_error, master0_error} ),
.slave_data_i ( ms_data_io[31:0] ),
.slave_ready ( ms_ready ),
.slave_error ( ms_error ),
.slave_address ( ms_address[31:0] ),
.slave_data_o ( ms_data_oi[31:0] ),
.slave_wr ( ms_wr[3:0] ),
.slave_enable ( ms_enable )
);
mux_switch #(
.nslaves (3),
// Slaves
// To generate the mask (easy way): (32'hFFFF_FFFF << N-bits).
// TODO: find a way to get "N-bits" (non-magical way).
// UART GPIO Internal Memory
// 3-bits 5-bits (MEM_ADDR_WIDTH)-bits
.MATCH_ADDR ({32'h1100_0000, 32'h1000_0000, 32'h0000_0000}), // Adjust the mask to avoid address aliasing.
.MATCH_MASK ({32'hFFFF_FFF8, 32'hFFFF_FFE0, 32'hFFFF_0000}) // Adjust the mask to avoid address aliasing.
)
mux_switch0(
.clk ( clk_bus ),
.master_address ( ms_address[31:0] ),
.master_data_i ( ms_data_oi[31:0] ),
.master_wr ( ms_wr[3:0] ),
.master_enable ( ms_enable ),
.master_data_o ( ms_data_io[31:0] ),
.master_ready ( ms_ready ),
.master_error ( ms_error ),
.slave_data_i ( {slave2_data_i[31:0], slave1_data_i[31:0], slave0_data_i[31:0]} ),
.slave_ready ( {slave2_ready, slave1_ready, slave0_ready} ),
.slave_address ( slave_address[31:0] ),
.slave_data_o ( slave_data_o[31:0] ),
.slave_wr ( slave_wr[3:0] ),
.slave_enable ( {slave2_enable, slave1_enable, slave0_enable} )
);
//--------------------------------------------------------------------------
// Internal memory
//--------------------------------------------------------------------------
memory #(
.addr_size( MEM_ADDR_WIDTH ) // Memory size
)
memory0(
.clk ( clk_bus ),
.rst ( rst_module ),
.a_addr ( slave_address[2 +: MEM_ADDR_WIDTH] ), // MEM_ADDR_WIDTH bits address.
.a_din ( slave_data_o[31:0] ),
.a_wr ( slave_wr[3:0] ),
.a_enable ( slave0_enable ),
.a_dout ( slave0_data_i[31:0] ),
.a_ready ( slave0_ready ),
.b_addr ( ), // DO NOT CONNECT
.b_din ( ), // DO NOT CONNECT
.b_wr ( ), // DO NOT CONNECT
.b_enable ( ), // DO NOT CONNECT
.b_dout ( ), // DO NOT CONNECT
.b_ready ( ) // DO NOT CONNECT
);
//--------------------------------------------------------------------------
// I/O
//--------------------------------------------------------------------------
gpio gpio0(/*autoinst*/
.gpio_inout ( gpio_a_inout[31:0] ),
.gpio_data_o ( slave1_data_i[31:0] ),
.gpio_ready ( slave1_ready ),
.gpio_interrupt ( gpio_interrupt[3:0] ),
.clk ( clk_bus ),
.rst ( rst_module ),
.gpio_address ( slave_address[4:0] ),
.gpio_data_i ( slave_data_o[31:0] ),
.gpio_wr ( slave_wr[3:0] ),
.gpio_enable ( slave1_enable )
);
uart_bootloader #(
.SIM_MODE ( SIM_MODE ), // Simulation Mode
.BUS_FREQ ( BUS_FREQ ) // Bus frequency
)
uart_bootloader0(
.clk ( clk_bus ),
.rst ( rst_module ),
.uart_address ( slave_address[2:0] ),
.uart_data_i ( slave_data_o[7:0] ),
.uart_wr ( slave_wr[0] ),
.uart_enable ( slave2_enable ),
.uart_data_o ( slave2_data_i[31:0] ),
.uart_ready ( slave2_ready ),
.boot_master_data_i ( master_data_o[31:0] ),
.boot_master_ready ( master2_ready ),
.boot_master_address ( master2_address[31:0] ),
.boot_master_data_o ( master2_data_i[31:0] ),
.boot_master_wr ( master2_wr[3:0] ),
.boot_master_enable ( master2_enable ),
.uart_rx_ready_int ( uart_rx_ready_int ), // unused.
.uart_rx_full_int ( ), // unused.
.bootloader_reset_core ( bootloader_reset_core ),
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
module flt_fx_24p8
(
input [31:0] fp_in, // Floating point in IEEE fmt
output reg [31:0] int_out // Fixed point integer out
);
//
// 24.8, Z.
//
wire [7:0] bias_exp; /* Real exponent -127 - 128 */
wire [7:0] bias_exp2; /* Real exponent 2's comp */
wire [39:0] fixed_out2; /* 2's complement of fixed out */
wire [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
assign bias_mant = {25'h0001, fp_in[22:0]};
assign bias_exp = fp_in[30:23] - 8'd127;
assign bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
always @* begin
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[46:15];
int_out = (fp_in[31]) ? ~fixed_out + 1 : fixed_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> a >> b; long long ans = 0; while (true) { long long x = max(a, b); long long y = min(a, b); if (x == 0 || y == 0) break; long long n = x / y; ans += n; x -= n * y; a = x; b = y; } cout << ans; return 0; }
|
#include <bits/stdc++.h> long long gcdfun(long long x, long long y) { if (y == 0) return x; else return gcdfun(y, x % y); } using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, k = 1, flag = 0, ans = 0; cin >> n; vector<int> a(n), b(n); for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a.begin(), a.end()); int p = *max_element(a.begin(), a.end()); while (k <= 1024) { flag = 0; for (int i = 0; i < n; i++) { b[i] = (a[i] ^ k); } sort(b.begin(), b.end()); for (int i = 0; i < n; i++) { if (a[i] != b[i]) { flag = 1; break; } } if (flag == 1) k++; else { cout << k << n ; ans = 1; break; } } if (ans == 0) cout << -1 << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, d, t, result, stored = 0; cin >> n >> d; for (int i = 0; i < n; i++) { cin >> t; stored += t; } d -= (n - 1) * 10; if (d - stored >= 0) { cout << (n - 1) * 2 + (d - stored) / 5; } else cout << -1; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> #pragma optimize( TKACHENKO-GORYACHENKO ) using namespace std; const int maxn = 11e5; const int inf = 1e18; int n, m, k; int A[maxn]; int B[maxn]; int C[maxn]; int V[4 * maxn]; int T[4 * maxn]; inline void push(int v, int tl, int tr) { if (T[v] == 0) { return; } V[v] += T[v]; if (tl != tr) { T[2 * v] += T[v]; T[2 * v + 1] += T[v]; } T[v] = 0; } inline void build(int v, int tl, int tr) { if (tl == tr) { V[v] = C[tl]; return; } int tm = (tl + tr) / 2; build(2 * v, tl, tm); build(2 * v + 1, tm + 1, tr); V[v] = min(V[2 * v], V[2 * v + 1]); } inline void update(int v, int tl, int tr, int l, int r, int color) { push(v, tl, tr); if (l > r || tl > r || l > tr) { return; } if (tl == l && tr == r) { T[v] += color; push(v, tl, tr); return; } int tm = (tl + tr) / 2; update(2 * v, tl, tm, l, min(r, tm), color); update(2 * v + 1, tm + 1, tr, max(l, tm + 1), r, color); V[v] = min(V[2 * v], V[2 * v + 1]); } inline void changea(int i, int j) { if (j >= i) { update(1, 0, maxn - 1, i + 1, j, -1); } else { update(1, 0, maxn - 1, j + 1, i, 1); } } inline void changeb(int i, int j) { if (j >= i) { update(1, 0, maxn - 1, i + 1, j, 1); } else { update(1, 0, maxn - 1, j + 1, i, -1); } } inline int getans(int v, int tl, int tr) { push(v, tl, tr); int tm = (tl + tr) / 2; if (tl != tr) { push(2 * v, tl, tm); push(2 * v + 1, tm + 1, tr); } if (V[v] >= 0) { return -1; } if (tl == tr) { return tl; } if (V[2 * v + 1] < 0) { return getans(2 * v + 1, tm + 1, tr); } if (V[2 * v] < 0) { return getans(2 * v, tl, tm); } } int main() { int q, w, e, a, b, f; ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (q = 0; q < n; q++) { cin >> A[q]; C[A[q]]--; } for (q = 0; q < m; q++) { cin >> B[q]; C[B[q]]++; } cin >> k; for (q = maxn - 2; q >= 0; q--) { C[q] += C[q + 1]; } build(1, 0, maxn - 1); for (e = 0; e < k; e++) { int i, x, comm; cin >> comm >> i >> x; i--; if (comm == 1) { changea(A[i], x); A[i] = x; } else { changeb(B[i], x); B[i] = x; } cout << getans(1, 0, maxn - 1) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, k, m, n, a[100400], t, w, q, sum = 0; char s[105000]; long double x, y; cin >> q; for (j = 0; j < q; j++) { cin >> n; cin >> s; if (n > 2) { cout << YES << endl; cout << 2 << endl; cout << s[0] << ; for (i = 1; i < n; i++) cout << s[i]; cout << endl; } else { if (s[0] - 0 < s[1] - 0 ) { cout << YES << endl; cout << 2 << endl; cout << s[0] << << s[1] << endl; } else cout << NO << endl; } } return 0; }
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module ym_timer #(parameter cnt_width = 8, mult_width = 1) (
input CLK,
input TICK_144,
input nRESET,
input [cnt_width-1:0] LOAD_VALUE,
input LOAD,
input CLR_FLAG,
input SET_RUN,
input CLR_RUN,
output reg OVF_FLAG,
output reg OVF
);
reg RUN;
reg [mult_width-1:0] MULT;
reg [cnt_width-1:0] CNT;
reg [mult_width+cnt_width-1:0] NEXT, INIT;
always @(posedge CLK)
begin
if (CLR_RUN || !nRESET)
RUN <= 0;
else if (SET_RUN || LOAD)
RUN <= 1;
if (CLR_FLAG || !nRESET)
OVF_FLAG <= 0;
else if (OVF)
OVF_FLAG <= 1;
if (TICK_144)
begin
if (LOAD)
begin
MULT <= { (mult_width){1'b0} };
CNT <= LOAD_VALUE;
end
else if (RUN)
{ CNT, MULT } <= OVF ? INIT : NEXT;
end
end
always @(*)
begin
{ OVF, NEXT } <= { 1'b0, CNT, MULT } + 1'b1;
INIT <= { LOAD_VALUE, { (mult_width){1'b0} } };
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module sysctl #(
parameter csr_addr = 4'h0,
parameter ninputs = 16,
parameter noutputs = 16,
parameter systemid = 32'habadface
) (
input sys_clk,
input sys_rst,
/* Interrupts */
output reg gpio_irq,
output reg timer0_irq,
output reg timer1_irq,
/* CSR bus interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
/* GPIO */
input [ninputs-1:0] gpio_inputs,
output reg [noutputs-1:0] gpio_outputs,
input [31:0] capabilities,
output reg hard_reset
);
/*
* GPIO
*/
/* Synchronize the input */
reg [ninputs-1:0] gpio_in0;
reg [ninputs-1:0] gpio_in;
always @(posedge sys_clk) begin
gpio_in0 <= gpio_inputs;
gpio_in <= gpio_in0;
end
/* Detect level changes and generate IRQs */
reg [ninputs-1:0] gpio_inbefore;
always @(posedge sys_clk) gpio_inbefore <= gpio_in;
wire [ninputs-1:0] gpio_diff = gpio_inbefore ^ gpio_in;
reg [ninputs-1:0] gpio_irqen;
always @(posedge sys_clk) begin
if(sys_rst)
gpio_irq <= 1'b0;
else
gpio_irq <= |(gpio_diff & gpio_irqen);
end
/*
* Dual timer
*/
reg en0, en1;
reg ar0, ar1;
reg [31:0] counter0, counter1;
reg [31:0] compare0, compare1;
wire match0 = (counter0 == compare0);
wire match1 = (counter1 == compare1);
/*
* Logic and CSR interface
*/
wire csr_selected = csr_a[13:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
timer0_irq <= 1'b0;
timer1_irq <= 1'b0;
gpio_outputs <= {noutputs{1'b0}};
gpio_irqen <= {ninputs{1'b0}};
en0 <= 1'b0;
en1 <= 1'b0;
ar0 <= 1'b0;
ar1 <= 1'b0;
counter0 <= 32'd0;
counter1 <= 32'd0;
compare0 <= 32'hFFFFFFFF;
compare1 <= 32'hFFFFFFFF;
hard_reset <= 1'b0;
end else begin
timer0_irq <= 1'b0;
timer1_irq <= 1'b0;
/* Handle timer 0 */
if( en0 & ~match0) counter0 <= counter0 + 32'd1;
if( en0 & match0) timer0_irq <= 1'b1;
if( ar0 & match0) counter0 <= 32'd1;
if(~ar0 & match0) en0 <= 1'b0;
/* Handle timer 1 */
if( en1 & ~match1) counter1 <= counter1 + 32'd1;
if( en1 & match1) timer1_irq <= 1'b1;
if( ar1 & match1) counter1 <= 32'd1;
if(~ar1 & match1) en1 <= 1'b0;
csr_do <= 32'd0;
if(csr_selected) begin
/* CSR Writes */
if(csr_we) begin
case(csr_a[3:0])
/* GPIO registers */
// 0000 is GPIO IN and is read-only
4'b0001: gpio_outputs <= csr_di[noutputs-1:0];
4'b0010: gpio_irqen <= csr_di[ninputs-1:0];
/* Timer 0 registers */
4'b0100: begin
en0 <= csr_di[0];
ar0 <= csr_di[1];
end
4'b0101: compare0 <= csr_di;
4'b0110: counter0 <= csr_di;
/* Timer 1 registers */
4'b1000: begin
en1 <= csr_di[0];
ar1 <= csr_di[1];
end
4'b1001: compare1 <= csr_di;
4'b1010: counter1 <= csr_di;
4'b1111: hard_reset <= 1'b1;
endcase
end
/* CSR Reads */
case(csr_a[3:0])
/* GPIO registers */
4'b0000: csr_do <= gpio_in;
4'b0001: csr_do <= gpio_outputs;
4'b0010: csr_do <= gpio_irqen;
/* Timer 0 registers */
4'b0100: csr_do <= {ar0, en0};
4'b0101: csr_do <= compare0;
4'b0110: csr_do <= counter0;
/* Timer 1 registers */
4'b1000: csr_do <= {ar1, en1};
4'b1001: csr_do <= compare1;
4'b1010: csr_do <= counter1;
4'b1110: csr_do <= capabilities;
4'b1111: csr_do <= systemid;
endcase
end
end
end
endmodule
|
#include<bits/stdc++.h> using namespace std; #define ll long long #define endl n #define pb push_back const ll INF=1e18+10; void solve() { ll n,m; cin>>n>>m; string s; cin>>s; string p=s; while(m--) { s=p; for(ll i=0;i<n;i++) { if(p[i]== 1 ) continue; else{ if(i==0) { // cout<< YES <<endl; if(s[i+1]== 1 ) p[i]= 1 ; else p[i]= 0 ; //cout<<p[i]<<endl; } else if(i==n-1) { if(s[i-1]== 1 ) p[i]= 1 ; else p[i]= 0 ; } else { if((s[i-1]== 1 &&s[i+1]== 0 )||(s[i+1]== 1 &&s[i-1]== 0 )) p[i]= 1 ; else p[i]= 0 ; } } } if(p==s) break; } cout<<p<<endl; // cout<<p[0]<<endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); ll t; t=1; cin>>t; while(t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; typedef struct { int pre[maxn]; void init(int n) { for (int i = 0; i <= n + 1; ++i) pre[i] = i; } int find(int x) { if (x == pre[x]) return x; return pre[x] = find(pre[x]); } void merge(int x, int y) { pre[find(x)] = find(y); } } DS; DS lds, rds; int n, m, q; int M[maxn][maxn]; int D[maxn][maxn]; int U[maxn][maxn]; int L[maxn][maxn]; int R[maxn][maxn]; int a[maxn]; int id[maxn]; bool comp(int x, int y) { return a[x] < a[y]; } int getMax(int n, int x) { int ret = 0; int l, r; int i; for (i = 1; i <= n; ++i) id[i] = i; lds.init(n); rds.init(n); sort(id + 1, id + 1 + n, comp); for (i = n; i > 0; --i) { l = lds.find(id[i] - 1) + 1; r = rds.find(id[i] + 1) - 1; if (l <= x && x <= r) ret = max(ret, (r - l + 1) * a[id[i]]); lds.merge(id[i], id[i] - 1); rds.merge(id[i], id[i] + 1); } return ret; } void printMat(int x[][maxn]) { int i, j; for (i = 1; i <= n; ++i) { for (j = 1; j <= m; ++j) printf( %d , x[i][j]); putchar( n ); } } int main() { int i, j, k; int ans; int op, x, y; scanf( %d %d %d , &n, &m, &q); for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) scanf( %d , &M[i][j]); memset(D, 0, sizeof(D)); memset(U, 0, sizeof(U)); memset(L, 0, sizeof(L)); memset(R, 0, sizeof(R)); for (i = 1; i <= n; ++i) { for (j = 1; j <= m; ++j) { if (M[i][j]) { U[i][j] = U[i - 1][j] + 1; L[i][j] = L[i][j - 1] + 1; } } } for (i = n; i > 0; --i) { for (j = m; j > 0; --j) { if (M[i][j]) { D[i][j] = D[i + 1][j] + 1; R[i][j] = R[i][j + 1] + 1; } } } while (q--) { scanf( %d %d %d , &op, &x, &y); if (op == 1) { M[x][y] = !M[x][y]; for (j = y; j <= m; ++j) L[x][j] = M[x][j] ? L[x][j - 1] + 1 : 0; for (i = x; i <= n; ++i) U[i][y] = M[i][y] ? U[i - 1][y] + 1 : 0; for (j = y; j > 0; --j) R[x][j] = M[x][j] ? R[x][j + 1] + 1 : 0; for (i = x; i > 0; --i) D[i][y] = M[i][y] ? D[i + 1][y] + 1 : 0; } else { ans = 0; for (i = 1; i <= n; ++i) a[i] = L[i][y]; ans = max(ans, getMax(n, x)); for (i = 1; i <= n; ++i) a[i] = R[i][y]; ans = max(ans, getMax(n, x)); for (i = 1; i <= m; ++i) a[i] = U[x][i]; ans = max(ans, getMax(m, y)); for (i = 1; i <= m; ++i) a[i] = D[x][i]; ans = max(ans, getMax(m, y)); printf( %d n , ans); } } return 0; }
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-25 00:55:26
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-2){1'b0}};; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-1){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin : GENSTOP
always @* begin : STOP1
sgf_result_o <= Data_A_i * Data_B_i;
end
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [2*(SW/2+2)-1:0] S_B;
always@(posedge clk) begin : EVEN12
Q_middle <= result_A_adder * result_B_adder;
Q_left [SW-1:0] <= Data_A_i[(SW-1) -: SW/2] * Data_B_i[(SW-1) -: SW/2];
Q_right[SW-1:0] <= Data_A_i[((SW/2)-1):0] * Data_B_i[((SW/2)-1):0];
end
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - (Q_left + {zero1,Q_right}));
sgf_result_o[2*SW-1:0] <= {S_B[2*(SW/2)+1:0],rightside1} + {Q_left,Q_right[2*(SW/2)-1:0]};
//sgf_result_o[2*SW-1:0] <= Result[2*SW-1:0];
end
//assign sgf_result_o = Result[4*(SW/2)-1:0];
end
1:begin : ODD1
always@(posedge clk) begin : ODD12
Q_middle <= result_A_adder * result_B_adder;
Q_left <= Data_A_i[SW-1:SW/2+1] * Data_B_i[SW-1:SW/2+1];
Q_right <= Data_A_i[SW/2:0] * Data_B_i[SW/2:0];
end
always @* begin : ODD
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [2*(SW/2+2)-1:0] S_B;
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - (Q_left + Q_right));
sgf_result_o<= {S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
//assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
`default_nettype none
module serial_wb_mcu(
// System signals
clk_i, rst_i,
// Program memory address, instruction from program memory
pm_addr_o, pm_insn_i,
// Data port 0 and 1 (out)
port0_o,
port1_o,
strobe1_o,
// Data port 0 and 1 (in)
port2_i,
strobe2_o
);
input clk_i;
input rst_i;
output [9:0] pm_addr_o;
input [15:0] pm_insn_i;
output reg [7:0] port0_o;
output reg [7:0] port1_o;
output strobe1_o;
input wire [7:0] port2_i;
output strobe2_o;
wire clk_i;
wire rst_i;
reg [9:0] pm_addr_o;
wire [15:0] pm_insn_i;
reg strobe1_o;
reg strobe2_o;
reg [7:0] port2_r;
reg [15:0] insnreg;
// Internal registers and wires:
//
// Register file (16x8 bit registers)
reg [7:0] regfile[15:0];
reg [7:0] rf_op_a;
reg [7:0] rf_op_b;
reg rf_w; // Writeback enable
reg [7:0] rf_result; // Writeback input
reg [3:0] rf_index_r; // Writeback register
// ALU
reg [8:0] alu_result;
reg alu_flag_z;
reg alu_flag_c;
// Program counter
reg [8:0] pc;
// 2 slot stack for PC
reg [8:0] returnpc_0; // Return address from a jsr
reg [8:0] next_returnpc_0;
reg [8:0] returnpc_1; // Return address from a jsr
reg [8:0] next_returnpc_1;
// Instructions ( *tested means that it is tested in the testbench)
// Register modification group
// 0x0000ddddssssSSSS Rd = Rs + RS (set flags)
// 0x0001ddddssssSSSS Rd = Rs ^ RS (set flags)
// 0x0010ddddssssSSSS Rd = Rs & RS (set flags)
// 0x0011ddddssssSSSS Rd = Rs | RS (set flags)
// 0x0100ddddiiiiiiii Rd = immediate
// 0x0101dddd00000000 Rd = Port 2
// 0x0110dddd00000000 Rd = Address[port0+768]
// 0x0111ddddssss0000 Rd = Swap nibbles(Rs)
// Jump/misc group
// 0x1000000aaaaaaaaa Jump to address a
// 0x1000001aaaaaaaaa Jump to address a if zero
// 0x1000010aaaaaaaaa Jump to address a if carry
// 0x1000011aaaaaaaaa Jump to subroutine
// 0x1000100000000000 Return from subroutine
// 0x10010000ssss0000 Port 0 = Rs
// 0x10010001ssss0000 Port 1 = Rs
always @(posedge clk_i) begin
port2_r <= port2_i;
end
reg [7:0] from_pm_r;
always @(posedge clk_i) begin
if(!rf_op_b[0]) begin
from_pm_r <= pm_insn_i[15:8];
end else begin
from_pm_r <= pm_insn_i[7:0];
end
end
// Writeback
always @(posedge clk_i)
if(rst_i) begin
end else begin
if(rf_w)
regfile[rf_index_r] <= rf_result;
end
wire [7:0] rf_output;
// Decode operands
assign rf_output = regfile[rf_index_r];
localparam [1:0] FETCH = 2'd0; // Fetch INSN && Writeback
localparam [1:0] DECODE1 = 2'd1; // Fetch OP1
localparam [1:0] DECODE2 = 2'd2; // Fetch OP2
localparam [1:0] EXECUTE = 2'd3; // Execute
reg [1:0] state_r;
always @(posedge clk_i)
if(rst_i) begin
$display("In reset");
state_r <= FETCH;
end else begin
case(state_r)
FETCH: state_r <= DECODE1;
DECODE1: state_r <= DECODE2;
DECODE2: state_r <= EXECUTE;
EXECUTE: state_r <= FETCH;
endcase // case(state_r)
end
always @(posedge clk_i)
if(rst_i) begin
insnreg <= 16'hffff;
end else begin
if(state_r == FETCH) begin
insnreg <= pm_insn_i;
if(pm_insn_i == 16'hfffe) begin
$display("Breakpoint!");
$stop;
end
end
end
always @*
case(state_r)
FETCH: rf_index_r = insnreg[11:8];
DECODE1: rf_index_r = insnreg[7:4];
DECODE2: rf_index_r = insnreg[3:0];
default: rf_index_r = insnreg[3:0];
endcase // case(state_r)
always @(posedge clk_i) begin
if(state_r == DECODE1) rf_op_a <= rf_output;
if(state_r == DECODE2) rf_op_b <= rf_output;
end
always @* begin
if(state_r == DECODE1) begin
pm_addr_o = {rf_op_a[2:0],rf_op_b[7:1]};
// pm_addr_o = {2'b11, port0_o[7:1]};
end else begin
pm_addr_o = pc;
end
end // UNMATCHED !!
always @(posedge clk_i)
if(rst_i) begin
pc <= 0;
returnpc_0 <= 0;
returnpc_1 <= 0;
end else begin
if(state_r == FETCH) begin
pc <= pc + 1;
end else if(state_r == DECODE1) begin
if(insnreg[15:12] == 4'b1000) begin
case(insnreg[11:9])
3'b000:
pc <= insnreg[8:0];
3'b001:
if(alu_flag_z)
pc <= insnreg[8:0];
3'b010:
if(alu_flag_c)
pc <= insnreg[8:0];
3'b011: begin
pc <= insnreg[8:0];
returnpc_0 <= pc;
returnpc_1 <= returnpc_0;
end
default: begin
pc <= returnpc_0;
returnpc_0 <= returnpc_1;
end
endcase // case(insnreg[11:9])
end // if (insnreg[15:12] == 4'b1000)
end
end // else: !if(rst_i)
// Output ports:
always @(posedge clk_i)
if(rst_i) begin
port0_o <= 0;
port1_o <= 0;
strobe1_o <= 0;
end else begin
strobe1_o <= 0;
if(state_r == EXECUTE) begin
if(insnreg[15:12] == 4'b1001) begin
if(insnreg[8] == 0) begin
port0_o <= rf_op_a;
end else begin
strobe1_o <= 1;
port1_o <= rf_op_a;
end
end
end
end // else: !if(rst_i)
reg [7:0] alu_result_r;
// ALU
always @*
case(insnreg[13:12])
2'b00: alu_result = { 1'b0 , rf_op_a} + {1'b0, rf_op_b};
2'b01: alu_result = rf_op_a ^ rf_op_b;
2'b10: alu_result = rf_op_a & rf_op_b;
default: alu_result = rf_op_a | rf_op_b;
endcase // case(pm_insn[13:12])
// Flag generation
always @(posedge clk_i)
if(rst_i) begin
alu_result_r <= 8'b0;
end else begin
alu_result_r <= alu_result;
// Check to see if it is an ALU op
end // else: !if(rst_i)
always @(posedge clk_i)
if(rst_i) begin
alu_flag_c <= 0;
alu_flag_z <= 0;
strobe2_o <= 1'b0;
rf_w <= 0;
end else begin
strobe2_o <= 1'b0;
rf_w <= 0;
if(state_r == DECODE1) begin
if(insnreg[15:12] == 4'b0101) begin
strobe2_o <= 1'b1;
end
end else if(state_r == EXECUTE) begin
case(insnreg[15:14])
2'b00: begin // ALU operation
rf_result <= alu_result;
rf_w <= 1;
alu_flag_c <= alu_result[8];
if(alu_result[7:0] == 0) // Don't need ALU_flags just now...
alu_flag_z <= 1;
else
alu_flag_z <= 0;
end
2'b01: begin
rf_w <= 1;
case(insnreg[13:12])
2'b00: begin
rf_result <= insnreg[7:0];
end
2'b01: begin
rf_result <= port2_r;
end
2'b10: begin
rf_result <= from_pm_r;
end
default: begin
rf_result <= {rf_op_a[3:0], rf_op_a[7:4]};
end
endcase // case(insnreg[13:12])
end
default: begin
rf_w <= 0;
end
endcase // case(insnreg[15:14])
end
end
endmodule // mcu
|
#include <bits/stdc++.h> using namespace std; int n, ans = 0; int main() { cin >> n; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { int x; cin >> x; if (i == j || (i + j) == (n + 1) || i == (n + 1) / 2 || j == (n + 1) / 2) ans += x; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #include <stdio.h> using namespace std; typedef long long ll; typedef unsigned long long ul; #define len (int)1e5+5 #define mod (ll)(1e9+7) #define pq(a) priority_queue< a > #define pqd(b) priority_queue< b , vector< b > , greater< b >> #define MP make_pair #define v(i) vector<i> #define p(aa,bb) pair< aa,bb> #define pb push_back #define pp pop_back #define clr(a) memset((a),0,sizeof((a))) #define rep(i,a,b) for(int i=(a);i<=(b);i++) #define repd(i,a,b) for(ll i=(a);i>=(b);i--) #define all(a) (a).begin(),(a).end() #define F first #define S second #define ln length() #define INF (1LL<<61) #define co cout<< #define ci cin>> #define sc(a,b) scanf( %(a) ,&(b)) #define nl n #define fio(a,b) freopen( a , r ,stdin); freopen( b , w ,stdout); #define ios ios::sync_with_stdio(0); cin.tie(0); ul modpow(ul x,ul n,ul m){ if(n==0) return 1UL%m; ul u=modpow(x,n/2,m); u = (u*u)%m; if(n%2==1) u = (u*x)%m; return u; } bool prm[len]; v(int) prm_no; void make_prm(){ prm[0]=prm[1]=true; for(int first=2;first<=len;first++){ if(!prm[first]){ prm_no.pb(first); for(int second=2*first;second<=len;second+=first)prm[second]=true; } } } v(int) factor; void make_factor(int n) { for(int i=1;i*i<=n;i++){ if(n%i==0){ factor.pb(i);factor.pb(n/i); if(i*i==n)factor.pp(); } } } ul pascal_tri[2][(int)105]; void make_pascalTri(int n){ bool f=0;clr(pascal_tri); for(int i=0;i<=n;i++){ pascal_tri[f][0]=1; for(int j=1;j<=i;j++){ pascal_tri[f][j]=pascal_tri[!f][j]+pascal_tri[!f][j-1]; } f=!f; } } int prm_div[len]; void make_prm_div(){ for(auto u:prm_no){ for(int i=u;i<=len;i+=u)prm_div[i]++; } } ll gcd(ll a, ll b) { if (b == 0) return a; return gcd(b, a % b); } ll give_floor(ll n,ll a) { if(n%a==0)return n/a; else{ return n/a+1; } } bool is_perfect(ll n) { ll i; for(i=1;i*i<n;i++); return i*i==n; } int n,k; void solve(){ ci n>>k; string s;ci s; int cnt=0; for(int i=1;i<=(n-i);i++){ if(s[i-1]==s[n-i])cnt++; else break; } if(cnt>=k and n>=2*k+1)co YES n ; else co NO n ; } signed main(){ //ios int t;//=1; ci t; while(t--){ solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; char s[N]; int a[N], sta[N], tp; int main() { scanf( %s , s + 1); int n = strlen(s + 1); for (int i = 1; i <= n; ++i) if (s[i] == 0 ) { if (tp) a[sta[tp--]] = 1; } else sta[++tp] = i; for (int i = 1; i <= n; ++i) printf( %d , a[i]); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult16_12.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mult16_12 (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_wave*.jpg FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int A[n + 1], S[n + 1], S1[n + 3]; A[0] = 0; for (int i = 1; i <= n; i++) { cin >> A[i]; } S[0] = 0; for (int i = 1; i <= n; i++) { S[i] = S[i - 1] + A[i]; } string st; cin >> st; S1[n + 1] = 0; S1[n + 2] = 0; for (int i = n; i > 0; i--) { S1[i] = S1[i + 1] + (st[i - 1] - 0 ) * A[i]; } int ans = -1; for (int i = n; i > 0; i--) { int aux; if (st[i - 1] == 1 ) { ans = max(ans, S1[i + 1] + S[i - 1]); } } cout << max(ans, S1[1]) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, ans, l; bool flag = 0; inline long long getLen(long long x) { long long cnt = 0; while (x) { cnt++; x /= 10; } return cnt; } inline long long getSum(long long x) { long long cnt = 0; while (x) { cnt += x % 10; x /= 10; } return cnt; } int main() { cin >> n; long long sqn = sqrt(n); for (l = sqn; l > 0; l--) { if (l * l + 9 * l * getLen(l) < n) break; } for (ans = l; ans <= sqn; ans++) { if (ans * ans + ans * getSum(ans) == n) { flag = 1; break; } } printf( %lld n , flag ? ans : -1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long LL_INF = (long long)2e18 + 5; struct point { long long x, y; point() : x(0), y(0) {} point(long long _x, long long _y) : x(_x), y(_y) {} }; struct reverse_monotonic_dp_hull { vector<point> points; int size() const { return (int)points.size(); } void clear() { points.clear(); prev_x = LL_INF; } static long long floor_div(long long a, long long b) { return a / b - ((a ^ b) < 0 && a % b != 0); } static bool bad_middle(const point &a, const point &b, const point &c) { return floor_div(a.y - b.y, b.x - a.x) >= floor_div(b.y - c.y, c.x - b.x); } void insert(const point &p) { assert(size() == 0 || p.x >= points.back().x); if (size() > 0 && p.x == points.back().x) { if (p.y <= points.back().y) return; points.pop_back(); } while (size() >= 2 && bad_middle(points[points.size() - 2], points.back(), p)) points.pop_back(); points.push_back(p); } void insert(long long a, long long b) { insert(point(a, b)); } long long prev_x = LL_INF; long long query(long long x) { assert(x <= prev_x); prev_x = x; while (size() >= 2 && x * (points.back().x - points[size() - 2].x) <= points[size() - 2].y - points.back().y) points.pop_back(); return points.back().x * x + points.back().y; } }; int N, K; vector<long long> A; vector<long long> dp, next_dp; vector<long long> left_max, right_max; void update(int start, int end) { if (start >= end) return; if (end - start == 1) { next_dp[end] = min(next_dp[end], dp[start] + A[start]); return; } int mid = (start + end) / 2; update(start, mid); left_max[mid] = right_max[mid] = -LL_INF; for (int i = mid - 1; i >= start; i--) left_max[i] = max(left_max[i + 1], A[i]); for (int i = mid; i < end; i++) right_max[i + 1] = max(right_max[i], A[i]); reverse_monotonic_dp_hull hull; for (int right = mid + 1, left = mid; right <= end; right++) { while (left >= start && right_max[right] >= left_max[left]) { hull.insert(-left, -dp[left]); left--; } if (hull.size() > 0) next_dp[right] = min(next_dp[right], -hull.query(-right_max[right]) + right * right_max[right]); } hull.clear(); for (int right = end, left = start; right > mid; right--) { while (left <= mid && left_max[left] >= right_max[right]) { hull.insert(-left_max[left], left * left_max[left] - dp[left]); left++; } if (hull.size() > 0) next_dp[right] = min(next_dp[right], -hull.query(right)); } update(mid + 1, end); } void update_dp() { left_max.assign(N + 1, -LL_INF); right_max.assign(N + 1, -LL_INF); next_dp.assign(N + 1, LL_INF); update(0, N); swap(dp, next_dp); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> N >> K; A.resize(N); for (auto &a : A) cin >> a; dp.assign(N + 1, LL_INF); dp[0] = 0; for (int k = 0; k < K; k++) update_dp(); cout << dp[N] << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_4_V
`define SKY130_FD_SC_LP__SDFRTP_4_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_4_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Triple-port synchronous 128x32 RAM
* Port 1, read-only
* Port 2, read-only
* Port 3, write-only
*/
module pfpu_tpram(
input sys_clk,
input [6:0] p1_a,
output reg [31:0] p1_d,
input [6:0] p2_a,
output reg [31:0] p2_d,
input p3_en,
input [6:0] p3_a,
input [31:0] p3_d
);
/*
* Duplicate the contents over two dual-port BRAMs
* Port A(WO) Port B(RO)
* Mem1 P3 P1
* Mem2 P3 P2
*/
reg [31:0] mem1[0:127];
always @(posedge sys_clk) begin
if(p3_en)
mem1[p3_a] <= p3_d;
p1_d <= mem1[p1_a];
end
reg [31:0] mem2[0:127];
always @(posedge sys_clk) begin
if(p3_en)
mem2[p3_a] <= p3_d;
p2_d <= mem2[p2_a];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxbp (
VPWR,
VGND,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_1_V
`define SKY130_FD_SC_HDLL__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__probe_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <class A, class B> inline bool mina(A &first, B second) { return (first > second) ? (first = second, 1) : 0; } template <class A, class B> inline bool maxa(A &first, B second) { return (first < second) ? (first = second, 1) : 0; } map<char, int> cnt; char c[] = { B , G , R }; int main() { int N; cin >> N; string s; cin >> s; for (int(i) = 0; (i) < (N); ++(i)) { cnt[s[i]]++; } if (cnt.size() == 3) { cout << BGR << endl; return 0; } else if (cnt.size() == 1) { cout << cnt.begin()->first << endl; } else { for (int(i) = 0; (i) < (3); ++(i)) { int cc = cnt[c[i]]; if (cc == 0) { printf( %c , c[i]); } else { bool good = false; for (int(j) = 0; (j) < (3); ++(j)) { if (j != i && cnt[c[j]] >= 2) { good = true; } } if (good) printf( %c , c[i]); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void Fast() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); } inline int RD() { int i; cin >> i; return i; } inline float RF() { float i; cin >> i; return i; } inline double RDO() { double i; cin >> i; return i; } inline string RS() { string i; cin >> i; return i; } inline long long Rll() { long long i; cin >> i; return i; } inline bool super(long long n) { int x4 = 0, x7 = 0; while (n != 0) { int x = n % 10; if (x == 7) x7++; else x4++; n /= 10; } return (x4 == x7) ? true : false; } int A1[1000]; int arr[200004]; int main() { Fast(); int n = RD(), k = RD(); string t = RS(); int x = 0; for (int i = 1; i < t.size(); i++) { if (t.substr(i) == t.substr(0, t.size() - i)) { x = n - i; break; } } cout << t; for (int i = 0; i < k - 1; i++) cout << t.substr(x); }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void Boost() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const int NMax = 1e6 + 50; string convert(const string &s) { string ret = @ ; for (int i = 0; i < (int)s.size(); ++i) { ret += # + s.substr(i, 1); } ret += #$ ; return ret; } int P[NMax * 2]; void Solve() { string s; cin >> s; int n = (int)s.size(); int a = 0; int b = n - 1; while (a <= b) { if (a == b) { cout << s << n ; return; } if (s[a] == s[b]) { ++a; --b; if (a > b) { cout << s << n ; return; } } else { string nw = convert(s); int cen = 0, r = 0; for (int i = 0; i < (int)nw.size(); ++i) P[i] = 0; for (int i = 1; i < (int)nw.size() - 1; ++i) { int mir = cen - (i - cen); if (r > i) { P[i] = min(r - i, P[mir]); } while (nw[i + 1 + P[i]] == nw[i - 1 - P[i]]) { P[i]++; } if (i + P[i] > r) { cen = i; r = i + P[i]; } } int best = 0; int pos = 0; for (int i = 1; i < (int)nw.size() - 1; i++) { int start = (i - 1 - P[i]) / 2; int fin = start + P[i] - 1; if (start < a) { int mv = a - start; start += mv; fin -= mv; } if (fin > b) { int mv = fin - b; start += mv; fin -= mv; } if (start != a && fin != b) continue; if (start <= fin && (fin - start + 1) > best) { best = fin - start + 1; pos = start; } } for (int i = 0; i < a; ++i) cout << s[i]; for (int i = pos; i < pos + best; ++i) cout << s[i]; for (int i = a - 1; i >= 0; --i) cout << s[i]; cout << n ; return; } } } int main() { Boost(); int t; cin >> t; while (t--) { Solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; int dx8[] = {0, 0, 1, 1, 1, -1, -1, -1}; int dy8[] = {1, -1, -1, 0, 1, -1, 0, 1}; int kx8[] = {1, 1, 2, 2, -1, -1, -2, -2}; int ky8[] = {2, -2, 1, -1, 2, -2, 1, -1}; long long poww(long long a, long long b) { if (b == 0) return 1; long long x = poww(a, b / 2); x = x * x; if (b % 2 == 1) x = x * a; return x; } long long bigmod(long long a, long long b, long long c) { if (b == 0) return 1 % c; long long x = bigmod(a, b / 2, c); x = x * x % c; if (b % 2 == 1) x = x * a % c; return x; } long long mod_inverse(long long a, long long mod) { return bigmod(a, mod - 2, mod); } int a[100005 * 3], sp[20][100005 * 3], lg[100005 * 3], n; int spp[20][100005 * 3]; void logcal() { int cnt = 0; int p = 2; while (p <= 300000) { lg[p] = 1; p *= 2; } for (int i = 0; i <= 300000; i++) { if (lg[i]) { cnt++; } lg[i] = cnt; } } long long query1(int l, int r) { int ln = lg[r - l + 1]; int k = 1 << ln; int df = r - l + 1 - k; return (min(sp[ln][l], sp[ln][l + df])); } long long query2(int l, int r) { int ln = lg[r - l + 1]; int k = 1 << ln; int df = r - l + 1 - k; return (max(spp[ln][l], spp[ln][l + df])); } long long dp[100005 * 3]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); logcal(); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { sp[0][i] = a[i]; spp[0][i] = a[i]; } for (int i = 1; 1 << i <= n; i++) { for (int j = 1; j + (1 << i) <= n + 1; j++) { sp[i][j] = min(sp[i - 1][j], sp[i - 1][j + (1 << (i - 1))]); spp[i][j] = max(spp[i - 1][j], spp[i - 1][j + (1 << (i - 1))]); } } for (int i = 1; i <= n; i++) dp[i] = 2134567891; int N = n; for (int i = 1; i <= N; i++) { dp[i] = min(dp[i - 1] + 1, dp[i]); int lw = 1, hi = i - 1, ans = 0, mid; while (lw <= hi) { int mid = (lw + hi) / 2; int mx = query2(mid, i - 1); if (mx >= a[i]) { lw = mid + 1; ans = mid; } else { hi = mid - 1; } } if (ans > 0) { dp[i] = min(dp[ans] + 1, dp[i]); } lw = i + 1, hi = n, ans = 0, mid; while (lw <= hi) { int mid = (lw + hi) / 2; int mx = query2(i + 1, mid); if (mx >= a[i]) { ans = mid; hi = mid - 1; } else { lw = mid + 1; } } if (ans <= n && ans > 0) { dp[ans] = min(dp[ans], dp[i] + 1); } lw = 1, hi = i - 1, ans = 0, mid; while (lw <= hi) { int mid = (lw + hi) / 2; int mn = query1(mid, i - 1); if (mn > a[i]) { hi = mid - 1; } else { lw = mid + 1; ans = mid; } } if (ans > 0) { dp[i] = min(dp[ans] + 1, dp[i]); } lw = i + 1, hi = n, ans = 0, mid; while (lw <= hi) { int mid = (lw + hi) / 2; int mn = query1(i + 1, mid); if (mn > a[i]) { lw = mid + 1; } else { hi = mid - 1; ans = mid; } } if (ans <= n && ans > 0) { dp[ans] = min(dp[ans], dp[i] + 1); } } cout << dp[n] - 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { double x, y; } g[500]; int main() { int i, j, k, n, m; scanf( %d , &n); for (i = 0; i < n; ++i) { scanf( %lf%lf , &g[i].x, &g[i].y); } double maxx = 0; double m1, m2; for (i = 0; i < n - 1; ++i) for (j = i + 1; j < n; ++j) { m1 = m2 = 0; for (k = 0; k < n; ++k) { if (i == k || j == k) continue; double temp = (g[i].x - g[k].x) * (g[j].y - g[k].y) - (g[j].x - g[k].x) * (g[i].y - g[k].y); if (temp > 0) { if (temp > m1) m1 = temp; } else { if (temp < m2) m2 = temp; } } if (m1 != 0 && m2 != 0) if (maxx < m1 + abs(m2)) maxx = m1 + abs(m2); } printf( %lf , maxx / 2); }
|
#include <bits/stdc++.h> using namespace std; const int mn = 201000, inf = 1 << 30; struct node { int x, y; } pt[mn], sub[mn]; struct point { int k, x, y, r; } e[mn * 2]; int s1[mn * 2], s2[mn * 2]; int xs[mn * 2], dis[mn], sa[mn], L; int n, m, i, j, step, lo, hi, mid; bool cmp(node a, node b) { return a.x < b.x || (a.x == b.x && a.y < b.y); } bool cmp1(point a, point b) { return a.x < b.x || (a.x == b.x && a.k < b.k); } bool subway(int i, int j) { return dis[i] > dis[j]; } struct tree { int tt, rt[mn], s[mn * 20], le[mn * 20], ri[mn * 20]; int get(const int &p, int l, int r, int x, int y) { if (x <= l && y >= r) return s[p]; int m = (l + r) / 2, res = 0; if (x <= m) res += get(le[p], l, m, x, y); if (y > m) res += get(ri[p], m + 1, r, x, y); return res; } void add(const int &t, int &p, int l, int r, int k) { s[p = ++tt] = s[t] + 1; if (l == r) return; int m = (l + r) / 2; if (k <= m) add(le[t], le[p], l, m, k), ri[p] = ri[t]; else add(ri[t], ri[p], m + 1, r, k), le[p] = le[t]; } void ins(int i, int v) { add(rt[i - 1], rt[i], 1, L, v); } int query(int x, int y, int l, int r) { if (x > y || l > r || x > m) return 0; return get(rt[y], 1, L, l, r) - get(rt[x - 1], 1, L, l, r); } } T; point eva(int k, int x, int y, int r) { point res; res.k = k, res.x = x, res.y = y, res.r = r; return res; } void cross(int &l, int &r, int &x, int &y, int i, int t) { l = max(l, pt[i].x - t), x = max(x, pt[i].y - t); r = min(r, pt[i].x + t), y = min(y, pt[i].y + t); } void add(int *s, int p, int v) { for (; p <= L; p += p & (-p)) s[p] = max(s[p], v); } int query(int *s, int p) { int res = -inf; for (; p; p -= p & (-p)) res = max(res, s[p]); return res; } void get(point p) { int y = lower_bound(xs + 1, xs + 1 + L, p.y) - xs; if (p.k == 0) add(s1, y, p.x + p.y), add(s2, L - y + 1, p.x - p.y); else { int t1 = p.x + p.y - query(s1, y), t2 = p.x - p.y - query(s2, L - y + 1); dis[p.r] = min(dis[p.r], min(t1, t2)); } } void ugly(node &p) { int X = p.x - p.y, Y = p.x + p.y; p.x = X, p.y = Y; } void nearest() { int i, tt = 0; for (i = 1; i <= n; ++i) xs[++L] = pt[i].y; for (i = 1; i <= m; ++i) xs[++L] = sub[i].y; sort(xs + 1, xs + 1 + L); L = unique(xs + 1, xs + 1 + L) - xs - 1; for (i = 1; i <= n; ++i) e[++tt] = eva(1, pt[i].x, pt[i].y, i); for (i = 1; i <= m; ++i) e[++tt] = eva(0, sub[i].x, sub[i].y, i); sort(e + 1, e + 1 + tt, cmp1); fill(dis + 1, dis + 1 + n, inf); fill(s1 + 1, s1 + L + 1, -inf), fill(s2 + 1, s2 + 1 + L, -inf); for (i = 1; i <= tt; ++i) get(e[i]); for (i = 1; i <= tt; ++i) e[i].x = -e[i].x; sort(e + 1, e + 1 + tt, cmp1); fill(s1 + 1, s1 + L + 1, -inf), fill(s2 + 1, s2 + 1 + L, -inf); for (i = 1; i <= tt; ++i) get(e[i]); } int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; ++i) scanf( %d%d , &pt[i].x, &pt[i].y); for (i = 1; i <= m; ++i) scanf( %d%d , &sub[i].x, &sub[i].y); nearest(); for (i = 1; i <= n; ++i) ugly(pt[i]); for (i = 1; i <= m; ++i) ugly(sub[i]); sort(sub + 1, sub + 1 + m, cmp); L = 0; for (i = 1; i <= n; ++i) xs[++L] = pt[i].y; for (i = 1; i <= m; ++i) xs[++L] = sub[i].y; sort(xs + 1, xs + 1 + L), L = unique(xs + 1, xs + 1 + L) - xs - 1; for (i = 1; i <= m; ++i) T.ins(i, lower_bound(xs + 1, xs + 1 + L, sub[i].y) - xs); for (i = 1; i <= n; ++i) sa[i] = i; sort(sa + 1, sa + 1 + n, subway); lo = 0, hi = dis[sa[1]]; int mix, mxx, miy, mxy, ct, l, r, x, y; node su; while (lo < hi) { int mid = (lo + hi) / 2; mix = miy = -inf, mxx = mxy = inf; for (i = 1; i <= n; ++i) { if (dis[sa[i]] > mid) cross(mix, mxx, miy, mxy, sa[i], mid); else { ct = mid - dis[sa[i]]; su.y = -inf, su.x = mix - ct; l = lower_bound(sub + 1, sub + 1 + m, su, cmp) - sub; su.y = inf, su.x = mxx + ct; r = lower_bound(sub + 1, sub + 1 + m, su, cmp) - sub - 1; x = lower_bound(xs + 1, xs + 1 + L, miy - ct) - xs, y = lower_bound(xs + 1, xs + 1 + L, mxy + ct + 1) - xs - 1; if (T.query(l, r, x, y)) break; else cross(mix, mxx, miy, mxy, sa[i], mid); } if (mix > mxx || miy > mxy) break; } if (mix <= mxx && miy <= mxy) hi = mid; else lo = mid + 1; } printf( %d n , lo); return 0; }
|
`timescale 1ns / 1ps
module ad5541a
(
input wire clk,
input wire rstn,
input wire [15:0] data,
input wire valid,
output wire ready,
output wire cs,
output wire din,
output wire ldac,
output wire sclk
);
localparam [1:0]
STATE_IDLE = 3'd0,
STATE_WRITE = 3'd1,
STATE_LOAD = 3'd2,
STATE_WAIT = 3'd3;
reg [1:0] state_reg, state_next;
reg [6:0] count_reg, count_next;
reg [15:0] data_reg, data_next;
reg ready_reg, ready_next;
reg cs_reg, cs_next;
reg din_reg, din_next;
reg ldac_reg, ldac_next;
reg sclk_reg, sclk_next;
reg sclk_enable;
assign ready = ready_reg;
assign cs = cs_reg;
assign din = din_reg;
assign ldac = ldac_reg;
assign sclk = sclk_reg;
always @* begin
state_next = STATE_IDLE;
cs_next = cs_reg;
din_next = din_reg;
ldac_next = ldac_reg;
sclk_next = sclk_reg;
count_next = count_reg;
data_next = data_reg;
ready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
if (ready & valid) begin
data_next = data;
ready_next = 1'b0;
state_next = STATE_WRITE;
end else begin
ready_next = 1'b1;
end
end
STATE_WRITE: begin
state_next = STATE_WRITE;
count_next = count_reg + 1;
sclk_next = count_reg[1];
if (count_reg == 7'h04) begin
cs_next = 1'b0;
end
if (count_reg >= 7'h04 && count_reg[1:0] == 2'b00) begin
{din_next, data_next} = {data_reg, 1'b0};
end
if (count_reg == 7'h44) begin
cs_next = 1'b1;
count_next = 7'b0;
state_next = STATE_LOAD;
end
end
STATE_LOAD: begin
state_next = STATE_LOAD;
count_next = count_reg + 1;
if (count_reg[0] == 1'b1) begin
ldac_next = ~ldac_reg;
end
if (count_reg[2] == 1'b1) begin
state_next = STATE_WAIT;
count_next = 7'b0;
end
end
STATE_WAIT: begin
state_next = STATE_WAIT;
count_next = count_reg + 1;
if (count_reg == 7'h17) begin
state_next = STATE_IDLE;
count_next = 7'b0;
end
end
endcase
end
always @(posedge clk) begin
if (~rstn) begin
state_reg <= STATE_IDLE;
data_reg <= 16'b0;
ready_reg <= 1'b0;
count_reg <= 7'b0;
cs_reg <= 1'b1;
din_reg <= 1'b0;
ldac_reg <= 1'b1;
sclk_reg <= 1'b0;
end else begin
state_reg <= state_next;
data_reg <= data_next;
count_reg <= count_next;
ready_reg <= ready_next;
cs_reg <= cs_next;
din_reg <= din_next;
ldac_reg <= ldac_next;
sclk_reg <= sclk_next;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; using vi = vector<int>; using vll = vector<long long>; using vii = vector<pair<int, int>>; int main() { int n, m; scanf( %d%d , &n, &m); vector<tuple<int, int, int>> ve; for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); ve.emplace_back(x, -y, i); } sort((ve).begin(), (ve).end()); vii edge(m); int last = 1; set<pair<int, int>> cur; cur.insert({last, last}); for (auto t : ve) { int a, b, c; tie(a, b, c) = t; if (b) { assert(cur.rbegin()->first == last && cur.rbegin()->second == last); ++last; edge[c] = {last - 1, last}; auto it = cur.end(); cur.erase(prev(it)); cur.insert({last, last - 1}); cur.insert({last, last}); } else { int u = cur.begin()->first, v = cur.begin()->second; if (u == last) { puts( -1 ); return 0; } else { cur.erase(cur.begin()); ++u; edge[c] = {v, u}; cur.insert({u, v}); } } } for (auto e : edge) printf( %d %d n , e.first, e.second); }
|
#include <bits/stdc++.h> using namespace std; const int Hash = 743; const int Mod = 51123987; int powh[2000005], N, h1[2000005], h2[2000005], start[2000005], finish[2000005], a[2000005], b[2000005]; char s[2000005]; int getsub1(int lo, int hi) { return lo == 0 ? h1[hi] : h1[hi] - h1[lo - 1] * powh[hi - lo + 1]; } int getsub2(int lo, int hi) { return hi == N - 1 ? h2[lo] : h2[lo] - h2[hi + 1] * powh[hi - lo + 1]; } int main(void) { powh[0] = 1; for (int i = 1; i < 2000005; ++i) powh[i] = powh[i - 1] * Hash; scanf( %d %s , &N, s); int ch = 0; for (int i = 0; i < N; ++i) { ch = ch * Hash + s[i]; h1[i] = ch; } ch = 0; for (int i = N - 1; i >= 0; --i) { ch = ch * Hash + s[i]; h2[i] = ch; } long long tot = 0; for (int i = 0; i < N; ++i) { int lo = 1, hi = min(i + 1, N - i), mid, ans = 1; while (lo <= hi) { mid = (lo + hi) / 2; int s1 = getsub1(i, i + mid - 1); int s2 = getsub2(i - mid + 1, i); if (s1 == s2) { lo = mid + 1; ans = mid; } else hi = mid - 1; } tot += ans; tot %= Mod; a[i - ans + 1] += 1; a[i + 1] -= 1; b[i] += 1; b[i + ans] -= 1; } for (int i = 0; i + 1 < N; ++i) { if (s[i] != s[i + 1]) continue; int lo = 1, hi = min(i + 1, N - (i + 1)), mid, ans = 1; while (lo <= hi) { mid = (lo + hi) / 2; int s1 = getsub1(i + 1, i + mid); int s2 = getsub2(i - mid + 1, i); if (s1 == s2) { lo = mid + 1; ans = mid; } else hi = mid - 1; } tot += ans; tot %= Mod; a[i - ans + 1] += 1; a[i + 1] -= 1; b[i + 1] += 1; b[i + 1 + ans] -= 1; } for (int i = 0; i < N; ++i) { a[i] %= Mod; b[i] %= Mod; a[i] += Mod; b[i] += Mod; start[i] = (i == 0) ? a[i] : start[i - 1] + a[i]; finish[i] = (i == 0) ? b[i] : finish[i - 1] + b[i]; start[i] %= Mod; finish[i] %= Mod; } int sf = 0, sol = 0; for (int i = 0; i < N; ++i) { sol = (sol + (long long)(start[i]) * (long long)(sf) % Mod) % Mod; sf = (sf + finish[i]) % Mod; } cout << ((long long)(tot) * (tot - 1) / 2 - sol + Mod) % Mod << endl; return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_decrement (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter value = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_DECREMENT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_decrement_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_decrement_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_decrement_psl_logic.v"
`else
`endmodule // ovl_decrement
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_1_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state = 1'b0;
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (qualifier & fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
prev_test_expr <= {width{1'b0}};
end
else begin
if (qualifier) begin
prev_test_expr <= test_expr;
end
end
end
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("qualifier covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (qualifier == 1'b1));
assign fire_cover_2 = ((OVL_COVER_SANITY_ON > 0) && (qualifier == 1'b1) && (test_expr != prev_test_expr));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t ();
`ifndef VERILATOR
`error "Only Verilator supports PLI-ish DPI calls and sformat conversion."
`endif
import "DPI-C" context dpii_display_call
= function void \$dpii_display (input string formatted /*verilator sformat*/ );
integer a;
initial begin
// Check variable width constant string conversions
$dpii_display("");
$dpii_display("c");
$dpii_display("co");
$dpii_display("cons");
$dpii_display("constant");
$dpii_display("constant_value");
a = $c("10"); // Don't optimize away "a"
$display ("one10=%x",a); // Check single arg
$dpii_display("one10=%x",a);
$display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg
$dpii_display("Mod=%m 16=%d 10=%x",a,a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ()
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
// Sound module, channel 1. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlChannel1 //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc64, //OSC1 clock 64Hz
input wire iOsc256, //OSC1 clock 256Hz
input wire iOsc128, //OSC1 clock 128Hz
input wire iOsc262k, //OSC2 clock 131072Hz
input wire [7:0] iNR10,
input wire [7:0] iNR11,
input wire [7:0] iNR12,
input wire [7:0] iNR13,
input wire [7:0] iNR14,
output reg [4:0] oOut,
output wire oOnFlag
);
reg [2:0] rSweepShifts;
reg rSweepMode;
reg [2:0] rSweepTime;
reg [17:0] rSweepCounter;
reg [11:0] rSoundFrequencyNew;
reg [5:0] rLength;
reg [19:0] rLengthCounter;
reg [1:0] rDutyCycle;
reg rTimedMode;
reg rLengthComplete; // Channe disable.
reg rTone;
reg [10:0] rSoundFrequency;
reg [10:0] rSoundFrequencyCounter;
reg [3:0] rStep;
reg [18:0] rStepTime;
reg [18:0] rStepCounter;
reg [3:0] rInitialValue;
reg rEvelopeMode;
wire [4:0] up_value, down_value;
// register load
always @(posedge iClock) begin
if (iReset || iNR14[7]) begin // Register reload and counters restart.
rLength <= iNR11[5:0];
rLengthCounter <= 64-iNR11[5:0]; // Decrements to zero then load rLength.
rLengthComplete <= 0; // Disables channel when is asserted.
rDutyCycle <= iNR11[7:6];
rTimedMode <= iNR14[6];
rStepTime <= iNR12[2:0];
rStepCounter <= iNR12[2:0]; // Decrements to zero then load rStepTime.
rEvelopeMode <= iNR12[3];
rInitialValue <= iNR12[7:4];
rStep <= iNR12[7:4];
rTone <= 0;
rSoundFrequency[10:0] <= 2048-{iNR14[2:0],iNR13[7:0]};
rSoundFrequencyCounter[10:0] <= 2048-{iNR14[2:0],iNR13[7:0]};
rSoundFrequencyNew <= 2048-{iNR14[2:0],iNR13[7:0]};
//FREQUENCY SWEEP REGISTERS
rSweepShifts <= iNR10[2:0];
rSweepMode <= iNR10[3];
rSweepTime <= iNR10[6:4];
rSweepCounter <= iNR10[6:4];
end
end
// step gen: generates the output amplitud value.
always @(posedge iOsc64) begin
if (rStepTime != 0) begin // Check if channels step function is enabled.
if (rStepCounter ==1 ) begin
rStepCounter <= rStepTime; // Reset counter.
if(rEvelopeMode) begin // Envelope mode.
rStep <= ((rStep == 4'hF) ? rStep : rStep+1); //INCREASES ONLY IF STEP IF LOWER THAN TOP VALUE
end
else begin
rStep <= ((rStep == 4'h0) ? rStep : rStep-1); //DECREASES ONLY IF STEP IF LOWER THAN BOTTOM VALUE
end
end
else begin
rStepCounter <= rStepCounter-1;
end
end
end
// tone gen: generates the frecuency of the output.
always @(posedge iOsc262k) begin
if (rSoundFrequencyCounter ==0) begin
rSoundFrequencyCounter <= rSoundFrequency;
rTone <= ~rTone;
end
else begin
rSoundFrequencyCounter <= rSoundFrequencyCounter-1;
end
end
// sweep gen: generates the frequency sweep
always @(posedge iOsc128) begin //128Hz
if (rSweepCounter ==1 && rSweepShifts != 0 && rSweepTime > 0) begin // calucates new frequency
if (rSweepMode) begin
rSoundFrequencyNew <= rSoundFrequency + (rSoundFrequency >> rSweepShifts);
end
else begin
rSoundFrequencyNew <= rSoundFrequency - (rSoundFrequency >> rSweepShifts);
end
end
if (rSweepCounter ==0 && rSweepTime > 0) begin // set new frequency counter
if (rSoundFrequencyNew == 1 && rSoundFrequency == 1) begin // frequency is more than 131072
rLengthComplete = 1'b1 ;
end
else if (rSoundFrequencyNew <= 2047) begin // frequency is more than 131072
rSoundFrequency <= rSoundFrequencyNew;
end
rSweepCounter <= rSweepTime;
end
else begin
rSweepCounter = rSweepCounter-1;
end
end
// timmer: enable or disable channel output.
always @(posedge iOsc256) begin
if (rLengthCounter == 0) begin
rLengthCounter <= 64-rLength;
rLengthComplete <= (rTimedMode || rLengthComplete); // Disable channel only if timmer is enabled.
end
else begin
rLengthCounter <= rLengthCounter-1;
end
end
//re-map mux
assign up_value = 5'd15 + rStep;
assign down_value = 5'd15 - rStep;
always @(posedge iClock) begin
if (rLengthComplete) begin
oOut[4:0] <= 5'd15;
end
else begin
if (rTone) begin
oOut[4:0] <= up_value[4:0];
end
else begin
oOut[4:0] <= down_value[4:0];
end
end
end
assign oOnFlag = rLengthComplete;
endmodule
|
// MBT 7/7/2016
// DWP 11/27/2019
//
// 3 read-port, 1 write-port ram
//
// reads are synchronous
//
// although we could merge this with normal bsg_mem_1r1w
// and select with a parameter, we do not do this because
// it's typically a very big change to the instantiating code
// to move to/from sync/async, and we want to reflect this.
//
`include "bsg_defines.v"
module bsg_mem_3r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
, parameter enable_clock_gating_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r0_v_i | r1_v_i | r2_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_3r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r0_v_i
,.r0_addr_i
,.r0_data_o
,.r1_v_i
,.r1_addr_i
,.r1_data_o
,.r2_v_i
,.r2_addr_i
,.r2_data_o
);
//synopsys translate_off
always_ff @(negedge clk_lo)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
assert (~(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: port 2 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_3r1w_sync)
|
#include <bits/stdc++.h> using namespace std; int *a = new int[2000000]; int m, n; void add(int x, int l); void sub(int x, int l); int query(int x, int y, int x0, int y0, int t); int main() { int h, i, j, dir = 1, r, l, o, x, y, len, mid; cin >> n >> m; for (i = 0; i < 2000000; i++) a[i] = 0; for (i = 1; i <= n; i++) add(i, 1); l = 1; r = n; for (i = 0; i < m; i++) { cin >> o; if (o == 2) { cin >> x >> y; x++; if (dir == 1) { x += l - 1; y += l - 1; cout << query(1, n, x, y, 1) << endl; } else if (dir == 2) { x = r - x + 1; y = r - y + 1; cout << query(1, n, y, x, 1) << endl; } } else { cin >> len; if (len <= (r - l + 1) / 2) { if (dir == 1) { mid = l + len; for (j = 1; j <= len; j++) { x = mid - j; y = mid + j - 1; h = query(1, n, x, x, 1); add(y, h); } l += len; } else if (dir == 2) { mid = r - len; for (j = 1; j <= len; j++) { x = mid + j; y = mid - j + 1; h = query(1, n, x, x, 1); add(y, h); } r -= len; } } else { len = r - l + 1 - len; if (dir == 2) { mid = l + len; for (j = 1; j <= len; j++) { x = mid - j; y = mid + j - 1; h = query(1, n, x, x, 1); add(y, h); } l += len; } else if (dir == 1) { mid = r - len; for (j = 1; j <= len; j++) { x = mid + j; y = mid - j + 1; h = query(1, n, x, x, 1); add(y, h); } r -= len; } if (dir == 1) dir = 2; else dir = 1; } } } delete[] a; return 0; } void add(int x0, int l) { int x = 1, y = n, mid, t = 1; while (1) { a[t] += l; mid = (x + y) / 2; if (x == y) break; if (x0 <= mid) { y = mid; t = t * 2; } else { x = mid + 1; t = t * 2 + 1; } } } void sub(int x0, int l) { int x = 1, y = n, mid, t = 1; while (1) { a[t] -= l; mid = (x + y) / 2; if (x == y) break; if (x0 <= mid) { y = mid; t = t * 2; } else { x = mid + 1; t = t * 2 + 1; } } } int query(int x, int y, int x0, int y0, int t) { int mid; if (y0 < x) return 0; if (y < x0) return 0; if (x0 <= x && y <= y0) { return a[t]; } mid = (x + y) / 2; return query(x, mid, x0, y0, t * 2) + query(mid + 1, y, x0, y0, t * 2 + 1); }
|
#include<bits/stdc++.h> using namespace std; bool possible(int *arr, int n) { int s=0; s = accumulate(arr,arr+n,s); if(s%2) return false; bitset<2000000> b; b[0] = 1; for(int i=0;i<n;i++) b = b|(b<<arr[i]); return b[s/2]; } int main() { int n; cin>>n; int arr[n]; for(int i=0;i<n;i++) { cin>>arr[i]; } if(possible(arr,n)) { pair<int,int> mn; mn = make_pair(__builtin_ctz(arr[0]),1); for(int i=1;i<n;i++) { mn = min(make_pair(__builtin_ctz(arr[i]),i+1),mn); } cout<<1<<endl<<mn.second<<endl; } else { cout<<0<<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> int len(const T& a) { return a.size(); } using ll = long long; constexpr long double EPS = 1e-7; long double MaxSubarray(const vector<long double>& a) { long double best = -1e8; long double cur = 0.0; for (auto& i : a) { cur = max((long double)0, cur + i); best = max(best, cur); } return best; } long double MinSubarray(const vector<long double>& a) { long double best = 1e8; long double cur = 0.0; for (auto& i : a) { cur = min((long double)0, cur + i); best = min(best, cur); } return best; } long double Check(const vector<long double>& a, long double x) { vector<long double> new_a(a.size()); for (int i = 0; i < len(a); ++i) { new_a[i] = (long double)a[i] - x; } return max(abs(MaxSubarray(new_a)), abs(MinSubarray(new_a))); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << fixed << setprecision(6); int n; cin >> n; vector<long double> a(n); for (auto& i : a) cin >> i; long double l = -1e4 - 10, r = 1e4 + 10; for (int step = 0; step < 200; ++step) { long double m1 = l + (r - l) / 3.0; long double m2 = r - (r - l) / 3.0; if (Check(a, m1) - Check(a, m2) > EPS) { l = m1; } else { r = m2; } } cout << Check(a, l); return 0; }
|
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