text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 0; for (int i = 1; i <= n; i++) ans += abs(a[i - 1] - i); cout << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog wrapper for sleep_sergate_plv with size of 14 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_14 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_14 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(int64_t &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const int64_t &x) { printf( %lld , x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.first); putchar( ); _W(x.second); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } template <class T, class... U> void DEBUG(const T &head, const U &...tail) {} int MOD = 1e9 + 7; void ADD(long long &x, long long v) { x = (x + v) % MOD; if (x < 0) x += MOD; } const int SIZE = 5e5 + 10; long long mypow(long long x, long long y) { x %= MOD; long long res = 1 % MOD; while (y) { if (y & 1) res = res * x % MOD; y >>= 1; x = x * x % MOD; } return res; } int ll[2][SIZE]; int d[SIZE], dn; vector<pair<int, int> > seg[2]; template <class T> void maa(T &x, T y) { if (x < y) x = y; } template <class T> void mii(T &x, T y) { if (x > y) x = y; } int get_v(int x) { return lower_bound(d, d + dn, x) - d; } int get_len(int x) { return d[x] - d[x - 1]; } struct BIT { int _n; long long _d[SIZE]; void init(int __n) { _n = __n; memset(_d, 0, sizeof(long long) * (_n + 1)); } void ins(int x, long long v) { x++; for (; x <= _n; x += x & -x) ADD(_d[x], v); } long long qq(int x) { x++; long long res = 0; for (; x; x -= x & -x) ADD(res, _d[x]); return res; } long long qq_range(int x, int y) { long long ret = qq(y); if (x) ADD(ret, -qq(x - 1)); return ret; } } bit[2]; int main() { int K, N, M; R(K, N, M); if (N + M == 0) { W(mypow(2, K)); return 0; } d[dn++] = 0; for (int i = 0; i < (N); ++i) { int x, y; R(x, y); d[dn++] = x - 1; d[dn++] = y; seg[0].push_back(make_pair(x - 1, y)); } for (int i = 0; i < (M); ++i) { int x, y; R(x, y); d[dn++] = x - 1; d[dn++] = y; seg[1].push_back(make_pair(x - 1, y)); } sort(d, d + dn); dn = unique(d, d + dn) - d; for (int j = 0; j < (2); ++j) { for (int i = 0; i < (((int)(seg[j]).size())); ++i) { maa(ll[j][get_v(seg[j][i].second)], get_v(seg[j][i].first) + 1); } } for (int i = 0; i < (2); ++i) bit[i].init(dn + 2); bit[0].ins(1, mypow(2, get_len(1)) - 2); if (ll[0][1] == 0) { bit[1].ins(0, 1); } if (ll[1][1] == 0) { bit[0].ins(0, 1); } int bb[2] = {}; for (int i = (2); i < (dn); ++i) { long long both[2] = {}; int len = get_len(i); for (int j = 0; j < (2); ++j) ADD(both[j], bit[j].qq(i - 1)); while (bb[0] < ll[1][i]) { long long v = bit[0].qq_range(bb[0], bb[0]); bit[0].ins(bb[0], -v); bb[0]++; } if (ll[1][i] != i) bit[0].ins(i - 1, both[1]); while (bb[1] < ll[0][i]) { long long v = bit[1].qq_range(bb[1], bb[1]); bit[1].ins(bb[1], -v); bb[1]++; } if (ll[0][i] != i) bit[1].ins(i - 1, both[0]); bit[0].ins(i, (both[0] + both[1]) * (mypow(2, len) - 2) % MOD); } long long ans = 0; for (int i = 0; i < (2); ++i) ADD(ans, bit[i].qq(dn)); W(ans * mypow(2, (K - d[dn - 1])) % MOD); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_2_V
`define SKY130_FD_SC_LS__AND4_2_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_2_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, k; vector<pair<int, int> > g[maxn]; int d[maxn], par[maxn]; void dfs1(int u, int fa) { par[u] = fa; for (auto p : g[u]) { int v = p.first; if (v == fa) continue; d[v] = d[u] + p.second; dfs1(v, u); } } int a[maxn]; bool f[maxn]; int c[maxn]; void dfs(int u, int fa) { d[u] = 0; par[u] = fa; for (auto p : g[u]) { int v = p.first; if (v == fa) continue; dfs(v, u); c[v] = p.second; if (!f[v]) d[u] = max(d[u], d[v] + p.second); } } int l[maxn], r[maxn], t[maxn], tail = 1; int main() { scanf( %d%d , &n, &k); int u, v, w; for (int i = 1; i <= n - 1; i++) scanf( %d%d%d , &u, &v, &w), g[u].push_back(pair<int, int>(v, w)), g[v].push_back(pair<int, int>(u, w)); dfs1(1, -1); d[1] = 0; int rt = 1; for (int i = 1; i <= n; i++) if (d[i] > d[rt]) rt = i; d[rt] = 0; dfs1(rt, -1); int y = rt; for (int i = 1; i <= n; i++) if (d[i] > d[y]) y = i; int p = y; int m = 0; while (p > 0) a[++m] = p, p = par[p]; dfs(rt, -1); for (int i = 1; i <= n; i++) l[i] = d[i]; dfs(y, -1); for (int i = 1; i <= n; i++) r[i] = d[i]; for (int i = 1; i <= m; i++) f[a[i]] = 1; dfs(rt, -1); tail = 1; int head = 1; int ans = 1e9; for (int i = 1; i <= m; i++) { while (tail > head && d[a[t[tail - 1]]] <= d[a[i]]) tail--; t[tail++] = i; int q = d[a[t[head]]]; q = max(q, (i - k + 1 > 0 ? l[a[i - k + 1]] : 0)); q = max(q, r[a[i]]); ans = min(ans, q); if (t[head] == i - k) head++; } printf( %d n , ans); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, CrYCb to RGB conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
`timescale 1ns/100ps
module ad_csc_CrYCb2RGB #(
parameter DELAY_DATA_WIDTH = 16) (
// Cr-Y-Cb inputs
input clk,
input [DW:0] CrYCb_sync,
input [23:0] CrYCb_data,
// R-G-B outputs
output [DW:0] RGB_sync,
output [23:0] RGB_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// red
ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_R (
.clk (clk),
.sync (CrYCb_sync),
.data (CrYCb_data),
.C1 (17'h01989),
.C2 (17'h012a1),
.C3 (17'h00000),
.C4 (25'h10deebc),
.csc_sync_1 (RGB_sync),
.csc_data_1 (RGB_data[23:16]));
// green
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_G (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h10d01),
.C2 (17'h012a1),
.C3 (17'h10644),
.C4 (25'h0087937),
.csc_sync_1 (),
.csc_data_1 (RGB_data[15:8]));
// blue
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_B (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h00000),
.C2 (17'h012a1),
.C3 (17'h02046),
.C4 (25'h1114d60),
.csc_sync_1 (),
.csc_data_1 (RGB_data[7:0]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int mo = 998244353; const double PI = acos(-1.0); template <typename _T> _T Fabs(_T x) { return x < 0 ? -x : x; } template <typename _T> void read(_T &x) { _T f = 1; x = 0; char s = getchar(); while (s > 9 || s < 0 ) { if (s == - ) f = -1; s = getchar(); } while ( 0 <= s && s <= 9 ) { x = (x << 3) + (x << 1) + (s ^ 48); s = getchar(); } x *= f; } int n, b[400005 * 2], totx, d[400005 * 2], toty, ans; bool vis[400005]; set<int> st[400005 << 2]; int maxx[400005 << 2], minn[400005 << 2]; struct ming { int ax, ay, bx, by; } s[400005]; struct node { int l, r, val; }; vector<node> vec[400005]; void updata(int rt, bool fg) { if (fg) maxx[rt] = minn[rt] = 0; else maxx[rt] = max(maxx[rt << 1], maxx[rt << 1 | 1]), minn[rt] = min(minn[rt << 1], minn[rt << 1 | 1]); if (!st[rt].empty()) { int t = *st[rt].rbegin(); if (vis[t]) minn[rt] = max(minn[rt], t); else maxx[rt] = max(maxx[rt], t); } if (minn[rt] > maxx[rt]) maxx[rt] = 0; } void insert(int rt, int l, int r, int al, int ar, int aw) { if (al <= l && r <= ar) { if (aw > 0) st[rt].insert(aw); else st[rt].erase(-aw); updata(rt, l == r); return; } int mid = l + r >> 1; if (al <= mid) insert(rt << 1, l, mid, al, ar, aw); if (ar > mid) insert(rt << 1 | 1, mid + 1, r, al, ar, aw); updata(rt, 0); } signed main() { read(n); for (int i = 1; i <= n; i++) read(s[i].ax), read(s[i].ay), read(s[i].bx), read(s[i].by); for (int i = 1; i <= n; i++) b[++totx] = s[i].ax, b[++totx] = s[i].bx; sort(b + 1, b + totx + 1); totx = unique(b + 1, b + totx + 1) - b - 1; for (int i = 1; i <= n; i++) s[i].ax = lower_bound(b + 1, b + totx + 1, s[i].ax) - b, s[i].bx = lower_bound(b + 1, b + totx + 1, s[i].bx) - b; for (int i = 1; i <= n; i++) d[++toty] = s[i].ay, d[++toty] = s[i].by; sort(d + 1, d + toty + 1); toty = unique(d + 1, d + toty + 1) - d - 1; for (int i = 1; i <= n; i++) s[i].ay = lower_bound(d + 1, d + toty + 1, s[i].ay) - d, s[i].by = lower_bound(d + 1, d + toty + 1, s[i].by) - d - 1; for (int i = 1; i <= n; i++) vec[s[i].ax].push_back((node){s[i].ay, s[i].by, i}), vec[s[i].bx].push_back((node){s[i].ay, s[i].by, -i}); for (int i = 1; i <= totx; i++) { int siz = vec[i].size(); for (int j = 0; j < siz; j++) insert(1, 1, toty, vec[i][j].l, vec[i][j].r, vec[i][j].val); while (maxx[1]) vis[maxx[1]] = 1, insert(1, 1, toty, s[maxx[1]].ay, s[maxx[1]].by, 0), ans++; } printf( %d n , ans + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; map<string, string> m; map<string, int> used; string f(string x) { used[x] = 1; if (m[x] == x) return x; return f(m[x]); } int main() { int count = 0; vector<string> tab; int n; cin >> n; for (int i = 0; i < n; i++) { string p1, p2; cin >> p1 >> p2; if (m[p1].empty()) { ++count; tab.push_back(p1); } used[p1] = 0; used[p2] = 0; m[p1] = p2; m[p2] = p2; } cout << count << endl; for (int i = 0; i < count; ++i) { if (used[tab[i]] == 1) continue; cout << tab[i] << << f(tab[i]) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e4; int n, aa[N + 2], fib[N + 2], con[N + 2], m; void compress() { vector<int> v; for (int i = 1; i <= n; i++) v.push_back(aa[i]); sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); map<int, int> mp; for (int i = 0; i < v.size(); i++) { mp[v[i]] = i + 1; con[i + 1] = v[i] % m; } for (int i = 1; i <= n; i++) aa[i] = mp[aa[i]]; } bool vs[N + 2]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> aa[i]; compress(); fib[1] = 1; fib[2] = 1; for (int i = 3; i <= 30000; i++) fib[i] = (fib[i - 1] + fib[i - 2]) % m; int q; cin >> q; while (q--) { int l, r; cin >> l >> r; for (int i = l; i <= r; i++) vs[aa[i]] = 1; long long ans = 0; int cnt = 1; for (int i = 1; i <= 30000; i++) { if (vs[i]) { ans += con[i] * fib[cnt++]; vs[i] = 0; } } cout << ans % m << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c, co, i, j, k, l, m, n; cin >> n; co = 0; set<long long int> myset; for (i = 0; i < n; i++) { cin >> a; myset.insert(a); } if (myset.size() > 3) cout << NO n ; else if (myset.size() == 3) { i = 0; for (auto it = myset.begin(); it != myset.end(); it++) { if (i == 0) a = *it; if (i == 1) b = *it; if (i == 2) c = *it; i++; } if (abs(a - b) == abs(b - c)) cout << YES n ; else cout << NO n ; } else cout << YES n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100005], b[100005]; int main() { int i, j, n, p, k; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = a[i]; } sort(b + 1, b + 1 + n); for (i = 1; i <= n; i++) { if (b[i] != a[i]) break; } p = i; if (i == n + 1) { printf( yes n ); printf( 1 1 ); return 0; } for (j = n; j >= 1; j--) { if (b[j] != a[j]) break; } k = j; int flag = 0; for (i = p, j = k; i <= k && j >= p; i++, j--) { if (b[i] != a[j]) { flag = 1; break; } } if (flag) { printf( no n ); } else { printf( yes n ); printf( %d %d n , p, k); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:48:40 04/14/2015
// Design Name:
// Module Name: clockdivide2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clockdivide2(
input clk,
input rst,
input select,
output reg [31:0] OUT1,
output reg [31:0] OUT2,
output clkdivided1hz,
output clkdivided2hz,
output clkselect
);
always @ (posedge clk or posedge rst)
begin
if (rst)
OUT1<=32'd0;
else
if (OUT1 == 32'd50000000)
OUT1<=32'd0;
else
OUT1 <= OUT1 + 1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
OUT2<=32'd0;
else
if (OUT2 == 32'd500000)
OUT2<=32'd0;
else
OUT2 <= OUT2 + 1;
end
assign clkdivided1hz = (OUT1 == 32'd50000000);
assign clkdivided2hz = (OUT2 == 32'd500000);
assign clkselect = (select) ? clkdivided2hz : clkdivided1hz;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdl_odd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdl_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px,
// Inputs
arbpc1_pcxdp_grant_bufp1_pa_l, arbpc1_pcxdp_q0_hold_bufp1_pa,
arbpc1_pcxdp_qsel0_bufp1_pa_l, arbpc1_pcxdp_qsel1_bufp1_pa,
arbpc1_pcxdp_shift_bufp1_px_l, arbpc3_pcxdp_grant_bufp1_pa_l,
arbpc3_pcxdp_q0_hold_bufp1_pa, arbpc3_pcxdp_qsel0_bufp1_pa_l,
arbpc3_pcxdp_qsel1_bufp1_pa, arbpc3_pcxdp_shift_bufp1_px_l,
arbpc4_pcxdp_grant_bufp1_pa_l, arbpc4_pcxdp_q0_hold_bufp1_pa,
arbpc4_pcxdp_qsel0_bufp1_pa_l, arbpc4_pcxdp_qsel1_bufp1_pa,
arbpc4_pcxdp_shift_bufp1_px_l
);
output arbpc1_pcxdp_grant_pa ;
output arbpc1_pcxdp_q0_hold_pa_l ;
output arbpc1_pcxdp_qsel0_pa ;
output arbpc1_pcxdp_qsel1_pa_l ;
output arbpc1_pcxdp_shift_px ;
output arbpc3_pcxdp_grant_pa ;
output arbpc3_pcxdp_q0_hold_pa_l ;
output arbpc3_pcxdp_qsel0_pa ;
output arbpc3_pcxdp_qsel1_pa_l ;
output arbpc3_pcxdp_shift_px ;
output arbpc4_pcxdp_grant_pa ;
output arbpc4_pcxdp_q0_hold_pa_l ;
output arbpc4_pcxdp_qsel0_pa ;
output arbpc4_pcxdp_qsel1_pa_l ;
output arbpc4_pcxdp_shift_px ;
input arbpc1_pcxdp_grant_bufp1_pa_l;
input arbpc1_pcxdp_q0_hold_bufp1_pa;
input arbpc1_pcxdp_qsel0_bufp1_pa_l;
input arbpc1_pcxdp_qsel1_bufp1_pa;
input arbpc1_pcxdp_shift_bufp1_px_l;
input arbpc3_pcxdp_grant_bufp1_pa_l;
input arbpc3_pcxdp_q0_hold_bufp1_pa;
input arbpc3_pcxdp_qsel0_bufp1_pa_l;
input arbpc3_pcxdp_qsel1_bufp1_pa;
input arbpc3_pcxdp_shift_bufp1_px_l;
input arbpc4_pcxdp_grant_bufp1_pa_l;
input arbpc4_pcxdp_q0_hold_bufp1_pa;
input arbpc4_pcxdp_qsel0_bufp1_pa_l;
input arbpc4_pcxdp_qsel1_bufp1_pa;
input arbpc4_pcxdp_shift_bufp1_px_l;
assign arbpc1_pcxdp_grant_pa = ~arbpc1_pcxdp_grant_bufp1_pa_l;
assign arbpc1_pcxdp_q0_hold_pa_l = ~arbpc1_pcxdp_q0_hold_bufp1_pa;
assign arbpc1_pcxdp_qsel0_pa = ~arbpc1_pcxdp_qsel0_bufp1_pa_l;
assign arbpc1_pcxdp_qsel1_pa_l = ~arbpc1_pcxdp_qsel1_bufp1_pa;
assign arbpc1_pcxdp_shift_px = ~arbpc1_pcxdp_shift_bufp1_px_l;
assign arbpc3_pcxdp_grant_pa = ~arbpc3_pcxdp_grant_bufp1_pa_l;
assign arbpc3_pcxdp_q0_hold_pa_l = ~arbpc3_pcxdp_q0_hold_bufp1_pa;
assign arbpc3_pcxdp_qsel0_pa = ~arbpc3_pcxdp_qsel0_bufp1_pa_l;
assign arbpc3_pcxdp_qsel1_pa_l = ~arbpc3_pcxdp_qsel1_bufp1_pa;
assign arbpc3_pcxdp_shift_px = ~arbpc3_pcxdp_shift_bufp1_px_l;
assign arbpc4_pcxdp_grant_pa = ~arbpc4_pcxdp_grant_bufp1_pa_l;
assign arbpc4_pcxdp_q0_hold_pa_l = ~arbpc4_pcxdp_q0_hold_bufp1_pa;
assign arbpc4_pcxdp_qsel0_pa = ~arbpc4_pcxdp_qsel0_bufp1_pa_l;
assign arbpc4_pcxdp_qsel1_pa_l = ~arbpc4_pcxdp_qsel1_bufp1_pa;
assign arbpc4_pcxdp_shift_px = ~arbpc4_pcxdp_shift_bufp1_px_l;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Matt Myers.
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package config_pkg;
typedef struct packed {
int UPPER0;
struct packed {
int USE_QUAD0;
int USE_QUAD1;
int USE_QUAD2;
} mac;
int UPPER2;
} config_struct;
function automatic config_struct static_config(int selector);
config_struct return_config;
return_config = '0;
return_config.UPPER0 = 10;
return_config.UPPER2 = 20;
return_config.mac.USE_QUAD0 = 4;
return_config.mac.USE_QUAD2 = 6;
case (selector)
1: return_config.mac.USE_QUAD1 = 5;
endcase
return return_config;
endfunction
endpackage : config_pkg
module t;
import config_pkg::*;
localparam config_struct MY_CONFIG = static_config(1);
struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I ();
endmodule : t
module struct_submodule
import config_pkg::*;
#(parameter config_struct MY_CONFIG = '0);
initial begin
`checkd(MY_CONFIG.UPPER0, 10);
`checkd(MY_CONFIG.mac.USE_QUAD0, 4);
`checkd(MY_CONFIG.mac.USE_QUAD1, 5);
`checkd(MY_CONFIG.mac.USE_QUAD2, 6);
`checkd(MY_CONFIG.UPPER2, 20);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : struct_submodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x = 0, y = 0; string a, b; cin >> a >> b; if (a.size() > b.size()) { n = a.size(); } else { n = b.size(); } for (int i = 0; i < n; i++) { if (b[x] == a[y]) { x++; y++; } else { x++; } if (b[x] == 0 || a[y] == 0) { cout << (y + 1); break; } } }
|
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { if (a < b) { swap(a, b); } T t; while (b > 0) { t = a % b; a = b; b = t; } return a; } template <class T> T gcdL(vector<T>& v) { int l = v.size(); if (l == 1) return v[0]; T g = gcd(v[0], v[1]); for (int i = 2; i < l; i++) { g = gcd(g, v[i]); } return g; } long long foo(long long x) { while (x % 2 == 0) x /= 2; while (x % 3 == 0) x /= 3; return x; } bool ok(vector<long long>& v) { for (int i = 0; i < (int)v.size(); i++) { v[i] = foo(v[i]); } for (int i = 0; i < (int)v.size(); i++) { if (v[i] == 1) continue; else return 0; } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout << setprecision(10); long long n, x; vector<long long> v; cin >> n; for (int i = 0; i < n; i++) { cin >> x; v.push_back(x); } long long g = gcdL(v); for (int i = 0; i < n; i++) { v[i] /= g; } if (ok(v)) cout << Yes ; else cout << No ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int T, n, head[300005], cnt, in[300005], ans, rt; struct edge { int to, nxt; } e[300005 << 1]; void add(int u, int v) { e[++cnt] = (edge){v, head[u]}; head[u] = cnt; } void dfs(int u, int fa, int tot) { if (tot > ans) ans = tot, rt = u; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (v == fa) continue; dfs(v, u, tot + in[v]); } } int main() { scanf( %d , &T); while (T--) { scanf( %d , &n); cnt = 0; for (int i = 1; i <= n; i++) head[i] = 0, in[i] = -1; for (int i = 1, u, v; i < n; i++) { scanf( %d%d , &u, &v); add(u, v); add(v, u); in[u]++; in[v]++; } ans = -1; dfs(1, 0, in[1]); ans = -1; dfs(rt, 0, in[rt]); printf( %d n , ans + 2); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 28.06.2017 17:24:09
// Design Name:
// Module Name: ctrlunit
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Based off the code provided by the professor for the assignment
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ctrlunit(
input [5:0] OPCode, Funct,
output MemToReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite, Jump,
output [2:0] ALUControl
);
wire [1:0] ALUOp;
//wire zerosignal;
maindecoder md_inst(
.op( OPCode ),
.memtoreg( MemToReg ),
.memwrite( MemWrite ),
.branch( Branch ),
.alusrc( ALUSrc ),
.regdst( RegDst ),
.regwrite( RegWrite ),
.jump( Jump ),
.aluop( ALUOp )
);
aludecoder ad_inst(
.funct( Funct ),
.aluop( ALUOp ),
.alucontrol( ALUControl )
);
//PCSrc will be created at combining all the sections of the processor.
//assign PCSrc = Branch & zerosignal;
endmodule
module maindecoder(
input [5:0] op,
output memtoreg, memwrite,
output branch, alusrc,
output regdst, regwrite,
output jump,
output [1:0] aluop);
reg [8:0] controls;
assign {memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop} = controls;
always @ (op) begin
case(op)
6'b000000: controls <= 9'b000011011; //Rtype
6'b100011: controls <= 9'b100101000; //LW
6'b101011: controls <= 9'b010100000; //SW
6'b000100: controls <= 9'b001000001; //BEQ
6'b001000: controls <= 9'b000101000; //ADDI
6'b000010: controls <= 9'b000000100; //J
default: controls <= 9'bxxxxxxxxx; //???
endcase
end
endmodule
module aludecoder(
output reg [2:0] alucontrol,
input [5:0] funct,
input [1:0] aluop
);
always @ (aluop or funct) begin
case(aluop)
2'b00: alucontrol <= 3'b010; //addi
2'b01: alucontrol <= 3'b110; //sub, although not needed
default: case(funct) // Rtype
6'b100000: alucontrol <= 3'b010; // ADD
6'b100010: alucontrol <= 3'b110; // SUB
6'b100100: alucontrol <= 3'b000; // AND
6'b100101: alucontrol <= 3'b001; // OR
6'b101010: alucontrol <= 3'b111; // SLT
default: alucontrol <= 3'bxxx; // unused
endcase
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:45:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.v
// Design : system_vga_pll_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_pll_0_0,vga_pll,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_pll,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_pll_0_0
(clk_100,
clk_50,
clk_25,
clk_12_5,
clk_6_25);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_100 CLK" *) input clk_100;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_50 CLK" *) output clk_50;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_25 CLK" *) output clk_25;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_12_5 CLK" *) output clk_12_5;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_6_25 CLK" *) output clk_6_25;
wire clk_100;
wire clk_12_5;
wire clk_25;
wire clk_50;
wire clk_6_25;
system_vga_pll_0_0_vga_pll U0
(.clk_100(clk_100),
.clk_12_5(clk_12_5),
.clk_25(clk_25),
.clk_50(clk_50),
.clk_6_25(clk_6_25));
endmodule
(* ORIG_REF_NAME = "vga_pll" *)
module system_vga_pll_0_0_vga_pll
(clk_50,
clk_25,
clk_12_5,
clk_6_25,
clk_100);
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
input clk_100;
wire clk_100;
wire clk_12_5;
wire clk_12_5_s_i_1_n_0;
wire clk_25;
wire clk_25_s_i_1_n_0;
wire clk_50;
wire clk_6_25;
wire clk_6_25_s_i_1_n_0;
wire p_0_in;
LUT1 #(
.INIT(2'h1))
clk_12_5_s_i_1
(.I0(clk_12_5),
.O(clk_12_5_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_12_5_s_reg
(.C(clk_25),
.CE(1'b1),
.D(clk_12_5_s_i_1_n_0),
.Q(clk_12_5),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_25_s_i_1
(.I0(clk_25),
.O(clk_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_25_s_reg
(.C(clk_50),
.CE(1'b1),
.D(clk_25_s_i_1_n_0),
.Q(clk_25),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_50_s_i_1
(.I0(clk_50),
.O(p_0_in));
FDRE #(
.INIT(1'b0))
clk_50_s_reg
(.C(clk_100),
.CE(1'b1),
.D(p_0_in),
.Q(clk_50),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_6_25_s_i_1
(.I0(clk_6_25),
.O(clk_6_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_6_25_s_reg
(.C(clk_6_25),
.CE(1'b1),
.D(clk_6_25_s_i_1_n_0),
.Q(clk_6_25),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using pi = pair<int, int>; const int mxn = 2e5; int n; string ar[mxn]; void solve() { cin >> n; for (int i = 0; i < n; ++i) cin >> ar[i]; set<string> second; for (int i = n - 1; i >= 0; --i) { if (second.count(ar[i])) continue; cout << ar[i] << n ; second.insert(ar[i]); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; t = 1; while (t--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_PP_SYMBOL_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb16to1 (
//# {{data|Data Signals}}
input [15:0] D ,
output Z ,
//# {{control|Control Signals}}
input [15:0] S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_PP_SYMBOL_V
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_phy_dqs_iob.v
// /___/ /\ Date Last Modified: $Date: 2010/01/08 12:49:25 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data strobes in the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.2 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IODELAY primitives. PK. 11/27/08
// Rev 1.3 - IDDR primitve (u_iddr_dq_ce) is replaced with a negative-edge
// triggered flip-flop. PK. 03/20/09
// Rev 1.4 - To fix CR 540201, S and syn_preserve attributes are added
// for dqs_oe_n_r. PK. 01/08/10
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dqs_iob #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter DDR_TYPE = 1,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG"
)
(
input clk0,
input clkdiv0,
input rst0,
input dlyinc_dqs,
input dlyce_dqs,
input dlyrst_dqs,
input dlyinc_gate,
input dlyce_gate,
input dlyrst_gate,
input dqs_oe_n,
input dqs_rst_n,
input en_dqs,
inout ddr_dqs,
inout ddr_dqs_n,
output dq_ce,
output delayed_dqs
);
wire clk180;
wire dqs_bufio;
wire dqs_ibuf;
wire dqs_idelay;
wire dqs_oe_n_delay;
(* S = "TRUE" *) wire dqs_oe_n_r /* synthesis syn_preserve = 1*/;
wire dqs_rst_n_delay;
reg dqs_rst_n_r /* synthesis syn_preserve = 1*/;
wire dqs_out;
wire en_dqs_sync /* synthesis syn_keep = 1 */;
// for simulation only. Synthesis should ignore this delay
localparam DQS_NET_DELAY = 0.8;
assign clk180 = ~clk0;
// add delta delay to inputs clocked by clk180 to avoid delta-delay
// simulation issues
assign dqs_rst_n_delay = dqs_rst_n;
assign dqs_oe_n_delay = dqs_oe_n;
//***************************************************************************
// DQS input-side resources:
// - IODELAY (pad -> IDELAY)
// - BUFIO (IDELAY -> BUFIO)
//***************************************************************************
// Route DQS from PAD to IDELAY
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
(
.DELAY_SRC("I"),
.IDELAY_TYPE("VARIABLE"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_VALUE(0),
.ODELAY_VALUE(0)
)
u_idelay_dqs
(
.DATAOUT (dqs_idelay),
.C (clkdiv0),
.CE (dlyce_dqs),
.DATAIN (),
.IDATAIN (dqs_ibuf),
.INC (dlyinc_dqs),
.ODATAIN (),
.RST (dlyrst_dqs),
.T ()
);
// From IDELAY to BUFIO
BUFIO u_bufio_dqs
(
.I (dqs_idelay),
.O (dqs_bufio)
);
// To model additional delay of DQS BUFIO + gating network
// for behavioral simulation. Make sure to select a delay number smaller
// than half clock cycle (otherwise output will not track input changes
// because of inertial delay). Duplicate to avoid delta delay issues.
assign #(DQS_NET_DELAY) i_delayed_dqs = dqs_bufio;
assign #(DQS_NET_DELAY) delayed_dqs = dqs_bufio;
//***************************************************************************
// DQS gate circuit (not supported for all controllers)
//***************************************************************************
// Gate routing:
// en_dqs -> IDELAY -> en_dqs_sync -> IDDR.S -> dq_ce ->
// capture IDDR.CE
// Delay CE control so that it's in phase with delayed DQS
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
(
.DELAY_SRC ("DATAIN"),
.IDELAY_TYPE ("VARIABLE"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IDELAY_VALUE (0),
.ODELAY_VALUE (0)
)
u_iodelay_dq_ce
(
.DATAOUT (en_dqs_sync),
.C (clkdiv0),
.CE (dlyce_gate),
.DATAIN (en_dqs),
.IDATAIN (),
.INC (dlyinc_gate),
.ODATAIN (),
.RST (dlyrst_gate),
.T ()
);
// Generate sync'ed CE to DQ IDDR's using a negative-edge triggered flip-flop
// clocked by DQS. This flop should be locked to the IOB flip-flop at the same
// site as IODELAY u_idelay_dqs in order to use the dedicated route from
// the IODELAY to flip-flop (to keep this route as short as possible)
(* IOB = "FORCE" *) FDCPE_1 #
(
.INIT(1'b0)
)
u_iddr_dq_ce
(
.Q (dq_ce),
.C (i_delayed_dqs),
.CE (1'b1),
.CLR (1'b0),
.D (en_dqs_sync),
.PRE (en_dqs_sync)
) /* synthesis syn_useioff = 1 */
/* synthesis syn_replicate = 0 */;
//***************************************************************************
// DQS output-side resources
//***************************************************************************
// synthesis attribute keep of dqs_rst_n_r is "true"
always @(posedge clk180)
dqs_rst_n_r <= dqs_rst_n_delay;
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("OPPOSITE_EDGE")
)
u_oddr_dqs
(
.Q (dqs_out),
.C (clk180),
.CE (1'b1),
.D1 (dqs_rst_n_r), // keep output deasserted for write preamble
.D2 (1'b0),
.R (1'b0),
.S (1'b0)
);
(* IOB = "FORCE" *) FDP u_tri_state_dqs
(
.D (dqs_oe_n_delay),
.Q (dqs_oe_n_r),
.C (clk180),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
//***************************************************************************
// use either single-ended (for DDR1) or differential (for DDR2) DQS input
generate
if (DDR_TYPE > 0) begin: gen_dqs_iob_ddr2
IOBUFDS u_iobuf_dqs
(
.O (dqs_ibuf),
.IO (ddr_dqs),
.IOB (ddr_dqs_n),
.I (dqs_out),
.T (dqs_oe_n_r)
);
end else begin: gen_dqs_iob_ddr1
IOBUF u_iobuf_dqs
(
.O (dqs_ibuf),
.IO (ddr_dqs),
.I (dqs_out),
.T (dqs_oe_n_r)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, q; int par[26][100005], depth[100005]; vector<int> st[400005]; vector<int> G[100005]; vector<int> SS[26][100005]; int cnt, chaincnt; void get10(vector<int> &res, const vector<int> &fir, const vector<int> sec) { int c1 = 0, c2 = 0; res = vector<int>(min((int)fir.size() + (int)sec.size(), 10)); for (int i = 0; i < (int)res.size(); i++) { if (c1 != fir.size() && c2 != sec.size()) { if (fir[c1] < sec[c2]) { res[i] = fir[c1++]; } else { res[i] = sec[c2++]; } } else if (c1 == fir.size()) { res[i] = sec[c2++]; } else { res[i] = fir[c1++]; } } return; } set<int> ret1, ret2; int LCA(int u, int v) { ret1.clear(), ret2.clear(); if (depth[u] < depth[v]) swap(u, v); int dif = depth[u] - depth[v]; for (int i = 0; i <= 24; i++) { if (dif & (1 << i)) { u = par[i][u]; } } if (u == v) return u; for (int i = 24; i >= 0; i--) { if (par[i][u] != par[i][v]) { u = par[i][u], v = par[i][v]; } } return par[0][u]; } vector<int> solve(int u, int v) { int lca = LCA(u, v); int d1 = depth[u] - depth[lca] + 1; int d2 = depth[v] - depth[lca] + 1; int lvl = 26; set<int> ret1; while (d1 > 0) { if ((1 << lvl) <= d1) { d1 -= (1 << lvl); for (int i = 0; i < (int)SS[lvl][u].size() && i < 10; i++) { ret1.insert(SS[lvl][u][i]); } while (ret1.size() > 10) { ret1.erase(--ret1.end()); } u = par[lvl][u]; } lvl--; if (lvl < 0) lvl = 0; } lvl = 26; set<int> ret2; while (d2 > 0) { if ((1 << lvl) <= d2) { d2 -= (1 << lvl); for (int i = 0; i < (int)SS[lvl][v].size() && i < 10; i++) { ret2.insert(SS[lvl][v][i]); } while (ret2.size() > 10) { ret2.erase(--ret2.end()); } v = par[lvl][v]; } lvl--; if (lvl < 0) lvl = 0; } ret1.insert(ret2.begin(), ret2.end()); while (ret1.size() > 10) { ret1.erase(--ret1.end()); } vector<int> ret(ret1.begin(), ret1.end()); return ret; } void dfs(int u, int p, int dep) { depth[u] = dep; par[0][u] = p; for (int i = 0; i < (int)G[u].size(); i++) { int v = G[u][i]; if (v == p) continue; dfs(v, u, dep + 1); } } int main() { int from, to; scanf( %d %d %d , &n, &m, &q); for (int i = 1; i < n; i++) { scanf( %d %d , &from, &to); G[from].push_back(to); G[to].push_back(from); } int cur; for (int i = 1; i <= m; i++) { scanf( %d , &cur); SS[0][cur].push_back(i); } memset(par, -1, sizeof par); chaincnt = cnt = 1; dfs(1, -1, 0); for (int i = 1; i <= 24; i++) for (int j = 1; j <= n; j++) if (par[i - 1][j] != -1) { par[i][j] = par[i - 1][par[i - 1][j]]; get10(SS[i][j], SS[i - 1][par[i - 1][j]], SS[i - 1][j]); } int how; vector<int> ans; while (q--) { scanf( %d %d %d , &from, &to, &how); ans = solve(from, to); printf( %d , min((int)ans.size(), how)); for (int i = 0; i < ans.size() && how; i++, how--) { printf( %d , ans[i]); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int max_n = 1e5 + 10; vector<long long> adj[max_n]; long long par[max_n], st[max_n], p[max_n], ft[max_n], doc[max_n], x[max_n], l[max_n], r[max_n], cnt, tmp, k, n, m; bool mark[max_n]; int get_par(int u) { return par[u] == u ? u : par[u] = get_par(par[u]); } void dfs(long long v) { st[v] = cnt++; for (auto u : adj[v]) dfs(u); ft[v] = cnt; } bool cmp(long long v, long long u) { if (get_par(v) == get_par(u) && st[v] >= st[u] && ft[v] <= ft[u]) return true; else return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) { par[i] = i; p[i] = i; } while (m--) { int t; cin >> t; long long v, u; if (t == 1) { cin >> v >> u; par[v] = u; p[v] = u; } else if (t == 2) { cin >> v; l[tmp] = v; r[tmp++] = get_par(v); } else { cin >> x[k] >> doc[k]; doc[k++]--; } } for (int i = 1; i <= n; ++i) { if (p[i] != i) adj[p[i]].push_back(i); } for (int i = 1; i <= n; ++i) { if (p[i] == i) { cnt = 0; dfs(i); } } for (int i = 0; i < k; ++i) { if (cmp(l[doc[i]], x[i]) && cmp(x[i], r[doc[i]])) cout << YES << endl; else cout << NO << endl; } return 0; }
|
module butterfly_32(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [26:0] i_0;
input signed [26:0] i_1;
input signed [26:0] i_2;
input signed [26:0] i_3;
input signed [26:0] i_4;
input signed [26:0] i_5;
input signed [26:0] i_6;
input signed [26:0] i_7;
input signed [26:0] i_8;
input signed [26:0] i_9;
input signed [26:0] i_10;
input signed [26:0] i_11;
input signed [26:0] i_12;
input signed [26:0] i_13;
input signed [26:0] i_14;
input signed [26:0] i_15;
input signed [26:0] i_16;
input signed [26:0] i_17;
input signed [26:0] i_18;
input signed [26:0] i_19;
input signed [26:0] i_20;
input signed [26:0] i_21;
input signed [26:0] i_22;
input signed [26:0] i_23;
input signed [26:0] i_24;
input signed [26:0] i_25;
input signed [26:0] i_26;
input signed [26:0] i_27;
input signed [26:0] i_28;
input signed [26:0] i_29;
input signed [26:0] i_30;
input signed [26:0] i_31;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
wire signed [27:0] b_8;
wire signed [27:0] b_9;
wire signed [27:0] b_10;
wire signed [27:0] b_11;
wire signed [27:0] b_12;
wire signed [27:0] b_13;
wire signed [27:0] b_14;
wire signed [27:0] b_15;
wire signed [27:0] b_16;
wire signed [27:0] b_17;
wire signed [27:0] b_18;
wire signed [27:0] b_19;
wire signed [27:0] b_20;
wire signed [27:0] b_21;
wire signed [27:0] b_22;
wire signed [27:0] b_23;
wire signed [27:0] b_24;
wire signed [27:0] b_25;
wire signed [27:0] b_26;
wire signed [27:0] b_27;
wire signed [27:0] b_28;
wire signed [27:0] b_29;
wire signed [27:0] b_30;
wire signed [27:0] b_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_31;
assign b_1=i_1+i_30;
assign b_2=i_2+i_29;
assign b_3=i_3+i_28;
assign b_4=i_4+i_27;
assign b_5=i_5+i_26;
assign b_6=i_6+i_25;
assign b_7=i_7+i_24;
assign b_8=i_8+i_23;
assign b_9=i_9+i_22;
assign b_10=i_10+i_21;
assign b_11=i_11+i_20;
assign b_12=i_12+i_19;
assign b_13=i_13+i_18;
assign b_14=i_14+i_17;
assign b_15=i_15+i_16;
assign b_16=i_15-i_16;
assign b_17=i_14-i_17;
assign b_18=i_13-i_18;
assign b_19=i_12-i_19;
assign b_20=i_11-i_20;
assign b_21=i_10-i_21;
assign b_22=i_9-i_22;
assign b_23=i_8-i_23;
assign b_24=i_7-i_24;
assign b_25=i_6-i_25;
assign b_26=i_5-i_26;
assign b_27=i_4-i_27;
assign b_28=i_3-i_28;
assign b_29=i_2-i_29;
assign b_30=i_1-i_30;
assign b_31=i_0-i_31;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
assign o_16=enable?b_16:i_16;
assign o_17=enable?b_17:i_17;
assign o_18=enable?b_18:i_18;
assign o_19=enable?b_19:i_19;
assign o_20=enable?b_20:i_20;
assign o_21=enable?b_21:i_21;
assign o_22=enable?b_22:i_22;
assign o_23=enable?b_23:i_23;
assign o_24=enable?b_24:i_24;
assign o_25=enable?b_25:i_25;
assign o_26=enable?b_26:i_26;
assign o_27=enable?b_27:i_27;
assign o_28=enable?b_28:i_28;
assign o_29=enable?b_29:i_29;
assign o_30=enable?b_30:i_30;
assign o_31=enable?b_31:i_31;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; void B(); int main() { ios::sync_with_stdio(0); cout.tie(0); cin.tie(0); B(); } class segmen { public: long long x1, y1, x2, y2; segmen(long long xx1, long long yy1, long long xx2, long long yy2) : x1{xx1}, x2{xx2}, y1{yy1}, y2{yy2} {} segmen() {} }; vector<segmen> hor, ver; const long long N = 10010; const long long shift = 5001; bool compar(segmen A, segmen B) { return A.y1 <= B.y1; } long long T[N]; void upd(long long x, long long val) { for (; x < N; x += (x & (-x))) T[x] += val; } long long F(long long x) { long long ret = 0; for (; x; x -= (x & (-x))) ret += T[x]; return ret; } long long gett(long long l, long long r) { return F(r) - F(l - 1); } vector<pair<long long, long long> > H[N]; vector<pair<long long, long long> > V[N]; void B() { long long n; cin >> n; for (long long i = 0; i < n; i++) { long long x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; x1 += shift; x2 += shift; y1 += shift; y2 += shift; if (y1 == y2) { H[y1].push_back({min(x1, x2), max(x1, x2)}); } if (x1 == x2) { V[x1].push_back({min(y1, y2), max(y1, y2)}); } } long long ans = 0; vector<long long> endy[N]; for (long long i = 1; i < N; i++) { for (auto A : H[i]) { long long xl = A.first; long long xr = A.second; long long maxn = 0; for (long long j = xl; j <= xr; j++) { for (auto B : V[j]) { if (B.first <= i && B.second > i) { upd(j, 1); endy[B.second].push_back(j); maxn = max(maxn, B.second); } } } for (long long j = i + 1; j <= maxn; j++) { for (auto B : H[j]) { long long ret = gett(B.first, B.second); ans += (ret * (ret - 1)) >> 1; } for (auto B : endy[j]) { upd(B, -1); } endy[j].clear(); } } } cout << ans << n ; }
|
module fetch_tb();
reg dispatch2cu_wf_dispatch;
reg [14:0]dispatch2cu_wf_tag_dispatch;
reg [31:0]dispatch2cu_start_pc_dispatch;
reg [9:0]dispatch2cu_vgpr_base_dispatch;
reg [8:0]dispatch2cu_sgpr_base_dispatch;
reg [15:0]dispatch2cu_lds_base_dispatch;
reg [5:0]dispatch2cu_wf_size_dispatch;
reg [3:0]dispatch2cu_wg_wf_count;
reg buff_ack;
reg [39:0]wave_stop_fetch;
reg issue_wf_done_en;
reg [5:0]issue_wf_done_wf_id;
reg [5:0]issue_wg_wfid;
reg [5:0]salu_branch_wfid;
reg salu_branch_en;
reg salu_branch_taken;
reg [31:0]salu_branch_pc_value;
reg clk;
reg rst;
wire [14:0]cu2dispatch_wf_tag_done;
wire cu2dispatch_wf_done;
wire [31:0]buff_addr;
wire [38:0]buff_tag;
wire buff_rd_en;
wire [5:0]wave_reserve_slotid;
wire wave_reserve_valid;
wire wave_basereg_wr;
wire [5:0]wave_basereg_wfid;
wire [9:0]wave_vgpr_base;
wire [8:0]wave_sgpr_base;
wire [15:0]wave_lds_base;
wire [63:0]exec_init_value;
wire [5:0]exec_init_wf_id;
wire [5:0]issue_wg_wgid;
wire [3:0]issue_wg_wf_count;
wire exec_init_wf_en;
fetch fetch_test(
.dispatch2cu_wf_dispatch(dispatch2cu_wf_dispatch),
.dispatch2cu_wf_tag_dispatch(dispatch2cu_wf_tag_dispatch),
.dispatch2cu_start_pc_dispatch(dispatch2cu_start_pc_dispatch),
.dispatch2cu_vgpr_base_dispatch(dispatch2cu_vgpr_base_dispatch),
.dispatch2cu_sgpr_base_dispatch(dispatch2cu_sgpr_base_dispatch),
.dispatch2cu_lds_base_dispatch(dispatch2cu_lds_base_dispatch),
.dispatch2cu_wf_size_dispatch(dispatch2cu_wf_size_dispatch),
.dispatch2cu_wg_wf_count(dispatch2cu_wg_wf_count),
.buff_ack(buff_ack),
.wave_stop_fetch(wave_stop_fetch),
.issue_wf_done_en(issue_wf_done_en),
.issue_wf_done_wf_id(issue_wf_done_wf_id),
.issue_wg_wfid(issue_wg_wfid),
.salu_branch_wfid(salu_branch_wfid),
.salu_branch_en(salu_branch_en),
.salu_branch_taken(salu_branch_taken),
.salu_branch_pc_value(salu_branch_pc_value),
.cu2dispatch_wf_tag_done(cu2dispatch_wf_tag_done),
.cu2dispatch_wf_done(cu2dispatch_wf_done),
.buff_addr(buff_addr),
.buff_tag(buff_tag),
.buff_rd_en(buff_rd_en),
.wave_reserve_slotid(wave_reserve_slotid),
.wave_reserve_valid(wave_reserve_valid),
.wave_basereg_wr(wave_basereg_wr),
.wave_basereg_wfid(wave_basereg_wfid),
.wave_vgpr_base(wave_vgpr_base),
.wave_sgpr_base(wave_sgpr_base),
.wave_lds_base(wave_lds_base),
.exec_init_value(exec_init_value),
.exec_init_wf_id(exec_init_wf_id),
.exec_init_wf_en(exec_init_wf_en),
.issue_wg_wgid(issue_wg_wgid),
.issue_wg_wf_count(issue_wg_wf_count),
.clk(clk),
.rst(rst)
);
initial
begin
clk = 0;
#1 rst = 1;
#10 rst = 0;
end
initial begin
while (1) begin
#3;
clk = ~clk;
end
end
initial
begin
dispatch2cu_wf_dispatch = 1'b0;
dispatch2cu_wf_tag_dispatch = 15'dx;
dispatch2cu_start_pc_dispatch = 32'dx;
dispatch2cu_vgpr_base_dispatch = 10'dx;
dispatch2cu_sgpr_base_dispatch = 9'dx;
dispatch2cu_lds_base_dispatch = 16'dx;
dispatch2cu_wf_size_dispatch = 6'dx;
dispatch2cu_wg_wf_count = 4'dx;
buff_ack = 1'b0;
wave_stop_fetch = 40'd0;
issue_wf_done_en = 1'b0;
issue_wf_done_wf_id = 6'd0;
salu_branch_wfid = 6'dx;
salu_branch_en = 1'b0;
salu_branch_taken = 1'b0;
salu_branch_pc_value = 32'bx;
issue_wg_wfid = 6'dx;
#20;
dispatch2cu_wf_dispatch = 1'b1;
dispatch2cu_wf_tag_dispatch = 15'd0;
dispatch2cu_start_pc_dispatch = 32'd0;
dispatch2cu_vgpr_base_dispatch = 10'd0;
dispatch2cu_sgpr_base_dispatch = 9'd0;
dispatch2cu_lds_base_dispatch = 16'd0;
dispatch2cu_wf_size_dispatch = 6'd0;
dispatch2cu_wg_wf_count = 4'd3;
buff_ack = 1'b0;
wave_stop_fetch = 40'd0;
issue_wf_done_en = 1'b0;
issue_wf_done_wf_id = 6'd0;
#6;
dispatch2cu_wf_dispatch = 1'b0;
#6;
issue_wg_wfid = 1'b0;
#15;
dispatch2cu_wf_dispatch = 1'b1;
dispatch2cu_wf_tag_dispatch = 15'd5;
dispatch2cu_start_pc_dispatch = 32'd18;
dispatch2cu_vgpr_base_dispatch = 10'd9;
dispatch2cu_sgpr_base_dispatch = 9'd10;
dispatch2cu_lds_base_dispatch = 16'd20;
dispatch2cu_wf_size_dispatch = 6'd6;
dispatch2cu_wg_wf_count = 4'd7;
buff_ack = 1'b0;
wave_stop_fetch = 40'd0;
issue_wf_done_en = 1'b0;
issue_wf_done_wf_id = 6'd0;
#6;
dispatch2cu_wf_dispatch = 1'b0;
#6;
issue_wg_wfid = 1'b1;
#6;
salu_branch_en = 1'b0;
salu_branch_taken = 1'b1;
salu_branch_wfid = 6'd0;
salu_branch_pc_value = 32'h20;
#6;
salu_branch_en = 1'b1;
salu_branch_taken = 1'b1;
salu_branch_wfid = 6'd0;
salu_branch_pc_value = 32'h30;
#6;
salu_branch_en = 1'b0;
salu_branch_taken = 1'b0;
#24;
issue_wf_done_en = 1'b1;
issue_wf_done_wf_id = 6'd0;
#6;
issue_wf_done_en = 1'b0;
#12;
issue_wf_done_en = 1'b1;
issue_wf_done_wf_id = 6'd1;
#6;
issue_wf_done_en = 1'b0;
#30;
$finish;
end
always@(posedge clk) begin
$display("TIME: %g clk: %d rst: %d base_wr: %d wfid: %d vgpr_base: %d sgpr_base: %d lds_base: %d PC: %d buff_tag: %h issue_wg_wf_count: %d issue_wf_done_wf_id: %d issue_wf_done_en: %d new_vacant=%h \n",
$time, clk, rst, wave_basereg_wr, wave_basereg_wfid, wave_vgpr_base, wave_sgpr_base, wave_lds_base, buff_addr, buff_tag, issue_wg_wf_count, issue_wf_done_wf_id, issue_wf_done_en, fetch_test.wfgen.vmg.new_vacant);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5, INF = 1e9; int a[N], n, x, y, res = 0; int main() { int t; ios::sync_with_stdio(false); cin >> t; while (t--) { cin >> n >> x >> y; int res = INF; int rs = 0, rc = 0; for (int i = 1; i <= x; i++) { for (int j = 1; j <= y - x + 1; j++) { int c = i; bool flag = true; bool fa = false, fb = false; for (int k = 1; k <= n; k++) { if (c == x) { fa = true; } if (c == y) { fb = true; } if (c > x && fa == false) break; if (c > y && fb == false) break; c += j; } if (fa && fb) { if (c < res) { res = c; rs = i; rc = j; } } } } int cnt = 1; for (int i = rs; cnt <= n; cnt++, i += rc) { cout << i << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int fa[1010]; int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } int main() { int n, m; scanf( %d%d , &n, &m); if (m != n - 1) { printf( no n ); return 0; } for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); int f1 = find(x), f2 = find(y); if (f1 == f2) { printf( no n ); return 0; } fa[f1] = f2; } printf( yes n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[200001], b[200001]; int n; int main(void) { int t; cin >> t; while (t--) { cin >> n; long long sum = 0LL; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; sum += b[i]; } vector<pair<long long, long long> > c; for (int i = 0; i < n; i++) { c.push_back(make_pair(a[i], i)); } sort(c.begin(), c.end()); long long ans = sum; for (int i = 0; i < n; i++) { sum -= b[c[i].second]; ans = min(ans, max(sum, c[i].first)); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } const long long MOD = 1000000007; long long inv[105]; vector<vector<long long>> matmul(vector<vector<long long>> a, vector<vector<long long>> b) { int n = a.size(); vector<vector<long long>> ret = vector<vector<long long>>(n, vector<long long>(n, 0)); for (int i = 0; i < (int)n; ++i) for (int j = 0; j < (int)n; ++j) for (int k = 0; k < (int)n; ++k) ret[i][j] = (ret[i][j] + a[i][k] * b[k][j]) % MOD; return ret; } vector<long long> matvecmul(vector<vector<long long>> a, vector<long long> b) { int n = a.size(); auto ret = vector<long long>(n, 0); for (int i = 0; i < (int)n; ++i) for (int k = 0; k < (int)n; ++k) ret[i] = (ret[i] + a[i][k] * b[k]) % MOD; return ret; } vector<vector<long long>> matpow(vector<vector<long long>> a, long long p) { vector<vector<long long>> tmp = a; int n = a.size(); vector<vector<long long>> ret = vector<vector<long long>>(n, vector<long long>(n, 0LL)); for (int i = 0; i < (int)n; ++i) ret[i][i] = 1LL; while (p) { if (p & 1) ret = matmul(ret, tmp); tmp = matmul(tmp, tmp); p >>= 1; } return ret; } vector<pair<long long, int>> f(long long n) { vector<pair<long long, int>> ret; for (long long i = 2; i * i <= n; i++) { int cnt = 0; while (n % i == 0) { cnt++; n /= i; } if (cnt != 0) ret.push_back(make_pair(i, cnt)); } if (n != 1) ret.push_back(make_pair(n, 1)); return ret; } void init() { inv[1] = 1LL; for (int i = 2; i < 100; i++) { inv[i] = MOD - inv[MOD % i] * (MOD / i) % MOD; } } int main() { long long n, k; init(); cin >> n >> k; vector<vector<long long>> mat(51, vector<long long>(51, 0)); for (int i = 0; i < (int)51; ++i) { for (int j = i; j < (int)51; ++j) { mat[i][j] = inv[j + 1]; } } mat = matpow(mat, k); auto ff = f(n); long long ret = 1; for (auto fc : ff) { long long ex = 0; long long p = 1; vector<long long> vec(51, 0); vec[fc.second] = 1LL; vec = matvecmul(mat, vec); for (int i = 0; i < (int)fc.second + 1; ++i) { ex = (ex + (p * vec[i]) % MOD) % MOD; p = (p * fc.first) % MOD; } ret = (ret * ex) % MOD; } cout << ret << endl; return 0; }
|
//#############################################################################
//# Function: Parametrized asynchronous clock FIFO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_async # (parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth (entries)
parameter TARGET = "GENERIC",// XILINX,ALTERA,GENERIC,ASIC
parameter PROG_FULL = (DEPTH/2),// program full threshold
parameter AW = $clog2(DEPTH) // binary read count width
)
(
input nreset, // async reset
input wr_clk, // write clock
input wr_en, // write fifo
input [DW-1:0] din, // data to write
input rd_clk, // read clock
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output full, // fifo is full
output prog_full, // fifo reaches full threshold
output empty, // fifo is empty
output [AW-1:0] rd_count // # of valid entries in fifo
);
//local wires
wire [AW-1:0] wr_count; // valid entries in fifo
generate
if(TARGET=="GENERIC") begin : basic
oh_fifo_generic #(.DEPTH(DEPTH),
.DW(DW))
fifo_generic (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_count (rd_count[AW-1:0]),
.wr_count (wr_count[AW-1:0]),
// Inputs
.nreset (nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else if(TARGET=="ASIC") begin : asic
oh_fifo_generic #(.DEPTH(DEPTH),
.DW(DW))
fifo_generic (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_count (rd_count[AW-1:0]),
.wr_count (wr_count[AW-1:0]),
// Inputs
.nreset (nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else if (TARGET=="XILINX") begin : xilinx
if((DW==104) & (DEPTH==32))
begin : g104x32
fifo_async_104x32
fifo (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_data_count (rd_count[AW-1:0]),
// Inputs
.rst (~nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end // if ((DW==104) & (DEPTH==32))
end // block: xilinx
endgenerate
endmodule // oh_fifo_async
// Local Variables:
// verilog-library-directories:("." "../fpga/" "../dv")
// End:
|
module hrfp_add
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [`MSBBIT:0] op3_a, op3_b,
input wire [30:0] mantissa_3_align0, mantissa_3_align1,
input wire expdiff_msb_3,
output reg [`MSBBIT:0] result_4,
output reg [30:0] mantissa_4,
output reg [7:0] zeroesmask_4);
reg [`MSBBIT:0] result_4_comb;
reg [30:0] mantissa_4_comb;
reg [7:0] zeroesmask_4_comb;
reg [30:0] aligned_mantissa;
always @* begin
if(expdiff_msb_3) begin
aligned_mantissa <= mantissa_3_align1;
end else begin
aligned_mantissa <= mantissa_3_align0;
end
end
always @* begin
result_4_comb = op3_a; // Exponent and sign
if(op3_b`SIGN == op3_a`SIGN) begin
mantissa_4_comb = ({op3_a`MANTISSA,3'b0} + aligned_mantissa);
end else begin
mantissa_4_comb = ({op3_a`MANTISSA,3'b0} - aligned_mantissa);
end
zeroesmask_4_comb = 8'hff;
case(op3_a`EXPONENT)
0: zeroesmask_4_comb[7:0] = 0;
1: zeroesmask_4_comb[6:0] = 0;
2: zeroesmask_4_comb[5:0] = 0;
3: zeroesmask_4_comb[4:0] = 0;
4: zeroesmask_4_comb[3:0] = 0;
5: zeroesmask_4_comb[2:0] = 0;
6: zeroesmask_4_comb[1:0] = 0;
7: zeroesmask_4_comb[0] = 0; // 8 LUTs :(
endcase
end
generate
if (PIPELINESTAGES==5) begin : ADDREG
always @(posedge clk) begin
result_4 <= result_4_comb;
mantissa_4 <= mantissa_4_comb;
zeroesmask_4 <= zeroesmask_4_comb;
end
end else begin // FIXME - check number of pipeline stages!
always @* begin
result_4 <= result_4_comb;
mantissa_4 <= mantissa_4_comb;
zeroesmask_4 <= zeroesmask_4_comb;
end // else: !if(PIPELINESTAGES==5)
end // else: !if(PIPELINESTAGES==5)
endgenerate
endmodule
|
`include "setseed.vh"
`define N 500
module top(input clk, stb, di, output do);
localparam integer DIN_N = 6;
localparam integer DOUT_N = `N;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [5:0] din, output [`N-1:0] dout);
function [31:0] xorshift32(input [31:0] v);
begin
xorshift32 = v;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [31:0] hash32(input [31:0] v);
begin
hash32 = v ^ `SEED;
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
end
endfunction
function [63:0] hash64(input [31:0] v);
begin
hash64[63:32] = hash32(v);
hash64[31: 0] = hash32(~v);
end
endfunction
genvar i;
generate
for (i = 0; i < `N; i = i+1) begin:is
wire o6;
//Randomly take out 1/4 iterations
wire [3:0] hash = hash32(i);
wire opt_out = |hash;
assign dout[i] = o6 & opt_out;
LUT6 #(
.INIT(hash64(i))
) lut6 (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[10000]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> s; bool t = 0; for (int i = 1; s[i]; ++i) { if (!isdigit(s[i]) && isdigit(s[i - 1])) { t = 1; break; } } if (t == 0) { int c = 0, j; for (j = 0; !isdigit(s[j]); ++j) { c = 26 * c + s[j] - A + 1; } int r = 0; for (; s[j]; ++j) { r = 10 * r + s[j] - 0 ; } cout << R << r << C << c << endl; } else { int r = 0; int j; for (j = 1; isdigit(s[j]); ++j) { r = r * 10 + s[j] - 0 ; } int c = 0; for (++j; s[j]; ++j) { c = 10 * c + s[j] - 0 ; } int z = 0; while (c) { s[z++] = c % 26 + A - 1; if (s[z - 1] < A ) { s[z - 1] = Z ; c = c - 26; } c = c / 26; } for (int k = z - 1; k >= 0; --k) putchar(s[k]); cout << r << endl; } } return 0; }
|
/********************************************/
/* generic_input.v */
/* A generic implementation of inputs */
/* (buttons, switches) */
/* */
/* 2012, */
/********************************************/
module generic_input #(
parameter IW = 1, // input width
parameter PD = 10, // push delay
parameter DS = 1'b0, // default (off) state
parameter DBG = 0 // debug output
)(
output wire [ IW-1:0] o
);
////////////////////////////////////////
// logic //
////////////////////////////////////////
reg [ IW-1:0] state = {IW{DS}};
assign o = state;
////////////////////////////////////////
// tasks //
////////////////////////////////////////
//// on ////
task on;
input [ IW-1:0] i;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state, (DS ? i & state : i | state));
state <= #1 DS ? i & state : i | state;
end
endtask
//// off ////
task off;
input [ IW-1:0] i;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state, (DS ? i | state : i & state));
state <= #1 DS ? i | state : i & state;
end
endtask
//// push ////
task push;
input [ IW-1:0] i;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state, (i ^ state));
state = #1 i ^ state;
#PD;
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state, (i ^ state));
state = #1 i ^ state;
end
endtask
//// toggle ////
task toggle;
input [ IW-1:0] i;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state, (i ^ state));
state = #1 i ^ state;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long Min(long long a, long long b) { return a < b ? a : b; } inline int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (f == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } return x * f; } int n, k, dp[200005], que[2000005], cnt, ne[200005], fr[200005]; char s[200005]; int main() { n = read(); k = read(); scanf( %s , s + 1); for (int i = 1; i <= n; i++) dp[i] = dp[i] - 1 + (s[i] == ( ? 1 : -1); for (int i = 1; i <= n; i++) ne[i] = i + 1, fr[i] = i - 1; for (int i = 1; i <= n; i++) if (s[i] == ( && s[i + 1] == ) ) que[++cnt] = i; for (int i = 1; i <= ((n - k) >> 1); i++) { int now = que[i]; s[now] = 0 ; s[ne[now]] = 0 ; ne[fr[now]] = ne[ne[now]]; fr[ne[ne[now]]] = fr[now]; if (s[fr[now]] == ( && s[ne[ne[now]]] == ) ) que[++cnt] = fr[now]; } for (int i = 1; i <= n; i++) { if (s[i] == ( ) { for (int j = i; j <= n; j = ne[j]) { printf( %c , s[j]); } return 0; } } return 0; }
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : K-2015.06-SP1
// Date : Tue Mar 1 00:49:30 2016
/////////////////////////////////////////////////////////////
module flex_stp_sr_NUM_BITS8_SHIFT_MSB0 ( clk, n_rst, shift_enable, serial_in,
parallel_out );
output [7:0] parallel_out;
input clk, n_rst, shift_enable, serial_in;
wire n12, n14, n16, n18, n20, n22, n24, n26, n1, n2, n3, n4, n5, n6, n7,
n8;
DFFSR \parallel_out_reg[7] ( .D(n26), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[7]) );
DFFSR \parallel_out_reg[6] ( .D(n24), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[6]) );
DFFSR \parallel_out_reg[5] ( .D(n22), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[5]) );
DFFSR \parallel_out_reg[4] ( .D(n20), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[4]) );
DFFSR \parallel_out_reg[3] ( .D(n18), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[3]) );
DFFSR \parallel_out_reg[2] ( .D(n16), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[2]) );
DFFSR \parallel_out_reg[1] ( .D(n14), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[1]) );
DFFSR \parallel_out_reg[0] ( .D(n12), .CLK(clk), .R(1'b1), .S(n_rst), .Q(
parallel_out[0]) );
INVX1 U2 ( .A(n1), .Y(n26) );
MUX2X1 U3 ( .B(parallel_out[7]), .A(serial_in), .S(shift_enable), .Y(n1) );
INVX1 U4 ( .A(n2), .Y(n24) );
MUX2X1 U5 ( .B(parallel_out[6]), .A(parallel_out[7]), .S(shift_enable), .Y(
n2) );
INVX1 U6 ( .A(n3), .Y(n22) );
MUX2X1 U7 ( .B(parallel_out[5]), .A(parallel_out[6]), .S(shift_enable), .Y(
n3) );
INVX1 U8 ( .A(n4), .Y(n20) );
MUX2X1 U9 ( .B(parallel_out[4]), .A(parallel_out[5]), .S(shift_enable), .Y(
n4) );
INVX1 U10 ( .A(n5), .Y(n18) );
MUX2X1 U11 ( .B(parallel_out[3]), .A(parallel_out[4]), .S(shift_enable), .Y(
n5) );
INVX1 U12 ( .A(n6), .Y(n16) );
MUX2X1 U13 ( .B(parallel_out[2]), .A(parallel_out[3]), .S(shift_enable), .Y(
n6) );
INVX1 U14 ( .A(n7), .Y(n14) );
MUX2X1 U15 ( .B(parallel_out[1]), .A(parallel_out[2]), .S(shift_enable), .Y(
n7) );
INVX1 U16 ( .A(n8), .Y(n12) );
MUX2X1 U17 ( .B(parallel_out[0]), .A(parallel_out[1]), .S(shift_enable), .Y(
n8) );
endmodule
module shift_register ( clk, n_rst, shift_enable, d_orig, rcv_data );
output [7:0] rcv_data;
input clk, n_rst, shift_enable, d_orig;
flex_stp_sr_NUM_BITS8_SHIFT_MSB0 a0 ( .clk(clk), .n_rst(n_rst),
.shift_enable(shift_enable), .serial_in(d_orig), .parallel_out(
rcv_data) );
endmodule
|
//====================================================================
// test_bsg.v
// 11/15/2016,
//====================================================================
//
`define RANDOM_TEST 1
`ifdef RANDOM_TEST
`define NUM 100000
`else
`define NUM 4
`endif
`define WIDTH 32
`define SIGN
`define UNSIGN
module test_bsg;
reg reset;
reg clk;
integer i,j;
logic v_i, ready_o, v_o;
logic gets_high_part;
logic signed_opA,signed_opB;
logic [`WIDTH-1:0] result_o;
logic [`WIDTH-1:0] opA_i, opB_i;
logic [`WIDTH-1:0] expect_result;
logic signed [`WIDTH-1:0] s_expect_result;
logic signed [`WIDTH*2-1:0] s_full_result;
logic [`WIDTH*2-1:0] full_result;
`ifndef RANDOM_TEST
logic [`WIDTH-1:0] opA [0:`NUM-1] = {32'h0000_0000, 32'h0000_0001, 32'h8000_8000, 32'hFFFF_FFFF};
logic [`WIDTH-1:0] opB [0:`NUM-1] = {32'h8000_0000, 32'h0000_0011, 32'h0000_0011, 32'hFFFF_FFFF};
`endif
bsg_imul_iterative #(.width_p( `WIDTH )) dut (
.clk_i ( clk)
,.reset_i ( reset )
,.v_i ( v_i )//there is a request
,.ready_o ( ready_o)//idiv is idle
,.opA_i ( opA_i )
,.opB_i ( opB_i )
,.signed_opA_i( signed_opA )
,.signed_opB_i( signed_opB )
,.gets_high_part_i( gets_high_part )
,.v_o ( v_o )//result is valid
,.result_o ( result_o )
,.yumi_i ( v_o )
);
initial clk = 0;
initial reset = 1;
initial #15 reset = 0;
always #10 clk = ~clk;
initial #25 begin
for(j=0; j< 2; j++) begin
//get_hight parts or low parts
if(j==0) gets_high_part = 1'b0;
else gets_high_part = 1'b1;
for (i=0; i<`NUM; i=i+1) begin
// do the signed case
`ifdef SIGN
wait (ready_o == 1);
`ifdef RANDOM_TEST
opA_i = $random;
opB_i = $random;
`else
opA_i = opA[i];
opB_i = opB[i];
`endif
signed_opA = 1'b1;
signed_opB = 1'b1;
v_i = 1;
wait (ready_o == 0);
v_i = 0;
wait (v_o == 1);
s_full_result = signed'(opA_i) * signed'(opB_i);
if( gets_high_part) s_expect_result = s_full_result[`WIDTH+:`WIDTH];
else s_expect_result = s_full_result[0+: `WIDTH];
if ( result_o != s_expect_result ) begin
$display("----------- ERROR in signed mul -----------");
if(gets_high_part) $display(" High part test ");
else $display(" Low part test ");
$display("opA: 0x%x (%d)", opA_i, signed'(opA_i));
$display("opB: 0x%x (%d)", opB_i, signed'(opB_i) );
$display("result: 0x%x (%d),expect 0x%x", result_o, result_o, s_expect_result);
end
`endif
// do the unsigned case
`ifdef UNSIGN
wait (ready_o == 1);
`ifdef RANDOM_TEST
opA_i = $random;
opB_i = $random;
`else
opA_i = opA[i];
opB_i = opB[i];
`endif
signed_opA = 1'b0;
signed_opB = 1'b0;
v_i = 1;
wait (ready_o == 0);
v_i = 0;
wait (v_o == 1);
full_result = opA_i * opB_i;
if( gets_high_part) expect_result = full_result[`WIDTH+:`WIDTH];
else expect_result = full_result[0+: `WIDTH];
if ( result_o != expect_result ) begin
$display("----------- ERROR in unsigned mul -----------");
if(gets_high_part) $display(" High part test ");
else $display(" Low part test ");
$display("opA: 0x%x (%d)", opA_i, opA_i);
$display("opB: 0x%x (%d)", opB_i, opB_i );
$display("result: 0x%x (%d),expect 0x%x", result_o, result_o, expect_result);
end
`endif
end //end for( i=0 )
end // end for( j=0 )
#80 $finish;
end //end initial
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IQ splitter
*/
module iq_split #
(
parameter WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [WIDTH-1:0] input_i_tdata,
input wire [WIDTH-1:0] input_q_tdata,
input wire input_tvalid,
output wire input_tready,
/*
* AXI stream outputs
*/
output wire [WIDTH-1:0] output_i_tdata,
output wire output_i_tvalid,
input wire output_i_tready,
output wire [WIDTH-1:0] output_q_tdata,
output wire output_q_tvalid,
input wire output_q_tready
);
reg [WIDTH-1:0] i_data_reg = 0;
reg [WIDTH-1:0] q_data_reg = 0;
reg i_valid_reg = 0;
reg q_valid_reg = 0;
assign input_tready = (~i_valid_reg | (output_i_tready & output_i_tvalid)) & (~q_valid_reg | (output_q_tready & output_q_tvalid));
assign output_i_tdata = i_data_reg;
assign output_i_tvalid = i_valid_reg;
assign output_q_tdata = q_data_reg;
assign output_q_tvalid = q_valid_reg;
always @(posedge clk) begin
if (rst) begin
i_data_reg <= 0;
q_data_reg <= 0;
i_valid_reg <= 0;
q_valid_reg <= 0;
end else begin
if (input_tready & input_tvalid) begin
i_data_reg <= input_i_tdata;
q_data_reg <= input_q_tdata;
i_valid_reg <= 1;
q_valid_reg <= 1;
end else begin
if (output_i_tready) begin
i_valid_reg <= 0;
end
if (output_q_tready) begin
q_valid_reg <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool areParanthesisBalanced(string expr) { stack<char> s; char x; for (int i = 0; i < expr.length(); i++) { if (expr[i] == ( || expr[i] == [ || expr[i] == { ) { s.push(expr[i]); continue; } if (s.empty()) return false; switch (expr[i]) { case ) : x = s.top(); s.pop(); if (x == { || x == [ ) return false; break; case } : x = s.top(); s.pop(); if (x == ( || x == [ ) return false; break; case ] : x = s.top(); s.pop(); if (x == ( || x == { ) return false; break; } } return (s.empty()); } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; cin.ignore(); string s; cin >> s; int op = 0; int ans = 0; int st = -1, en = -1; for (int i = 0; i < n; ++i) { if (st == -1) { st = i; } if (s[i] == ( ) { op++; } else { op--; } if (op == 0) { if (areParanthesisBalanced(s.substr(st, i - st + 1))) { } else { ans += i - st + 1; } st = -1; } } if (op == 0) { cout << ans << n ; } else { cout << -1 n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef long l; typedef pair<int, int> pint; typedef vector<pint> vpint; typedef vector<int> vint; typedef vector<vint> vvint; int n, m, x[123457], cum[1234567]; int ans; map<int, int> mp; int main() { cin >> n; for (int i = 0; i < n; ++i) { cin >> x[i]; cum[i] = x[i]; } sort(cum, cum + n); for (int i = 0; i < n; ++i) { if (x[i] != cum[i]) ans++; } if (ans < 3) cout << YES ; else cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b0 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long a[100000], lim, n, flag; void DFS(long long x, long long y) { if (x > n) { if (y == a[lim]) flag = 1; return; } if (flag) return; DFS(x + 1, y); if (x != lim) { DFS(x + 1, y + a[x]); DFS(x + 1, y - a[x]); } } inline void work() { lim = flag = n = 0; memset(a, 0, sizeof(a)); scanf( %lld , &n); for (register long long i = 1; i <= n; ++i) scanf( %lld , &a[i]); for (lim = 1; lim <= n; ++lim) { DFS(1, 0); if (flag) { puts( YES ); return; } } puts( NO ); } signed main() { long long T; scanf( %lld , &T); while (T--) work(); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 99999999; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; if (n == 1) { cout << 1; return 0; } vector<int> a(n); ; for (int i = 0; i < (n); ++i) cin >> a[i]; ; vector<int> c; for (int j = 1; j < n; ++j) { if (a[j] > a[j - 1]) c.push_back(1); else if (a[j] < a[j - 1]) c.push_back(-1); else c.push_back(0); } vector<pair<int, int>> d; int p = 1; for (int k = 1; k < c.size(); ++k) { if (c[k] == c[k - 1]) p++; else { d.push_back({p, c[k - 1]}); p = 1; } } d.push_back({p, c[c.size() - 1]}); vector<int> answ; if (d[0].second == 0) answ.push_back(3); else if (d[0].second == -1) answ.push_back(5); else answ.push_back(1); int last = 0; for (int i = 0; i < d.size(); ++i) { int cnt = d[i].first; int type = d[i].second; if (type == 0) { bool f = answ[last] == 3; for (int j = 0; j < cnt - 1; ++j) { if (f) answ.push_back(4); else answ.push_back(3); f = !f; last++; } if (i + 1 < d.size() && d[i + 1].second == -1) { if (answ[last] == 5) answ.push_back(4); else answ.push_back(5); last++; } else if (i + 1 < d.size() && d[i + 1].second == 1) { if (answ[last] == 1) answ.push_back(2); else answ.push_back(1); last++; } else { if (answ[last] == 4) answ.push_back(3); else answ.push_back(4); last++; } } else { for (int j = 0; j < cnt - 1; ++j) { answ.push_back(answ[last] + type); last++; } if (answ[last] > 5 || answ[last] < 1) { cout << -1; return 0; } if (i + 1 < d.size() && d[i + 1].second == -1) { if (answ[last] == 5) { cout << -1; return 0; } answ.push_back(5); last++; } else if (i + 1 < d.size() && d[i + 1].second == 1) { if (answ[last] == 1) { cout << -1; return 0; } answ.push_back(1); last++; } else { answ.push_back(answ[last] + type); last++; if (answ[last] > 5 || answ[last] < 1) { cout << -1; return 0; } } } } for (int l = 0; l < n; ++l) { cout << answ[l] << ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int a[12][12]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]); for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { a[i][j] = min(a[i][j], a[i][k] + a[k][j]); } } } int ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) ans = max(ans, a[i][j]); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int P = 1e9 + 7; int add(int a, int b) { if ((a += b) >= P) a -= P; return a < 0 ? a + P : a; } int mul(int a, int b) { return 1ll * a * b % P; } int kpow(int a, int b) { int r = 1; for (; b; b >>= 1, a = mul(a, a)) { if (b & 1) r = mul(r, a); } return r; } const int N = 1e6 + 7; int a[N], b[N], tr[N * 4], tip[N * 4], lft[N], rht[N], tim, n, k; vector<int> g[N]; void dfs(int u) { lft[u] = ++tim; for (auto v : g[u]) dfs(v); rht[u] = tim; } void change(int l, int r, int now, int L, int R, int w) { if (L <= l && R >= r) { tip[now] += w; return; } int mid = (l + r) >> 1; if (L <= mid) change(l, mid, (now << 1), L, R, w); if (R > mid) change(mid + 1, r, ((now << 1) | 1), L, R, w); tr[now] = max(tr[(now << 1)] + tip[(now << 1)], tr[((now << 1) | 1)] + tip[((now << 1) | 1)]); } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); cin >> n >> k; for (int i = (1); i < (n + 1); i++) cin >> a[i]; for (int i = (n + 1) - 1; i >= (1); i--) { for (b[i] = i + 1; b[i] <= n && a[b[i]] <= a[i]; b[i] = b[b[i]]) ; g[b[i]].push_back(i); } dfs(n + 1); for (int i = (1); i < (k + 1); i++) change(1, tim, 1, lft[i], rht[i], 1); cout << tip[1] + tr[1] << ; for (int i = (k + 1); i < (n + 1); i++) { change(1, tim, 1, lft[i], rht[i], 1); change(1, tim, 1, lft[i - k], lft[i - k], -(1ll << (30))); cout << tr[1] + tip[1] << ; } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tg_status.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<pair<int, int>, int> > v; int a[(int)(1e5 + 50)]; string s; void solve() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); s += (char)(x + 0 ); } for (int i = 0; i < s.size();) { int st = i, len = 0; char c = s[i]; while (i < s.size() && c == s[i]) { len++; i++; } v.push_back(make_pair(make_pair(st, len), (int)(c - 0 ))); } int len = v.size(); if (v[len - 1].second == 1 || (v[len - 1].first.second == 2 && v[len - 1].second == 0 && len < 3)) { printf( NO ); return; } printf( YES n ); string ans; if (v[len - 1].first.second == 2) { for (int i = 0; i < len - 3; i++) { char toAdd = (char)(v[i].second + 0 ); for (int j = 0; j < v[i].first.second; j++) { ans += toAdd; ans += -> ; } } for (int j = 0; j < v[len - 3].first.second - 1; j++) { ans += 0 ; ans += -> ; } ans += (0->( ; for (int i = 0; i < v[len - 2].first.second; i++) { ans += 1 ; ans += -> ; } ans += 0))->0 ; cout << ans; return; } if (v[len - 1].first.second % 2 == 0) { ans += ( ; for (int i = 0; i < v[len - 1].first.second - 3; i++) { ans += 0-> ; } ans += (0->0) ; ans += ->0 ; ans += ) ; } else { ans += ( ; for (int i = 0; i < v[len - 1].first.second - 1; i++) { ans += 0-> ; } ans += 0 ; ans += ) ; } if (len - 1 == 0) { cout << ans; return; } reverse(ans.begin(), ans.end()); ans += >- ; ans += )1 ; for (int i = 0; i < v[len - 2].first.second - 1; i++) { ans += >-1 ; } ans += ( ; for (int i = len - 3; i >= 0; i--) { ans += >- ; char toAdd = (char)(v[i].second + 0 ); int curlen = v[i].first.second; for (int j = 0; j < curlen - 1; j++) { ans += toAdd; ans += >- ; } ans += toAdd; } reverse(ans.begin(), ans.end()); cout << ans; } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_gt_rx_valid_filter_7x.v
// Version : 1.7
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
module pcie_7x_v1_8_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long quickMod(long long a, long long b, long long c) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % c; b >>= 1; a = a * a % c; } return ans; } long long Euler(long long x) { long long res = x; for (long long i = 2; i * i <= x; i++) { if (x % i == 0) { res = res - res / i; while (x % i == 0) x /= i; } } if (x > 1) res = res - res / x; return res; } int main() { long long c, tmp, ans, phi, result; char b[1000005], n[1000005]; scanf( %s%s%lld , b, n, &c); phi = Euler(c); tmp = 0; for (long long i = 0; b[i]; i++) tmp = (tmp * 10 + b[i] - 0 ) % c; ans = 0; bool flag = false; for (long long i = 0; n[i]; i++) { ans = ans * 10 + n[i] - 0 ; if (ans > phi) { flag = true; ans %= phi; } } if (flag) ans += phi; ans--; if (tmp == 0) tmp = c; result = (((tmp + c - 1) % c) * quickMod(tmp, ans, c)) % c; printf( %lld n , result ? result : c); return 0; }
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_rep_upload(//input
clk,
rst,
dc_flits_rep,
v_dc_flits_rep,
flits_max,
en_flits_max,
rep_fifo_rdy,
//output
dc_flit_out,
v_dc_flit_out,
dc_ctrl_out,
dc_rep_upload_state
);
//input
input clk;
input rst;
input [175:0] dc_flits_rep;
input v_dc_flits_rep;
input [3:0] flits_max;
input en_flits_max;
input rep_fifo_rdy;
//output
output [15:0] dc_flit_out;
output v_dc_flit_out;
output [1:0] dc_ctrl_out;
output dc_rep_upload_state;
//parameter
parameter dc_rep_upload_idle=1'b0;
parameter dc_rep_upload_busy=1'b1;
//reg dc_req_nstate;
reg dc_rep_state;
reg [175:0] dc_rep_flits;
reg [3:0] sel_cnt;
reg v_dc_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
reg [3:0] flits_max_reg;
reg [1:0] dc_ctrl_out;
assign dc_rep_upload_state=dc_rep_state;
always@(*)
begin
//default value
// dc_req_nstate=dc_req_state;
v_dc_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
dc_ctrl_out=2'b00;
case(dc_rep_state)
dc_rep_upload_idle:
begin
if(v_dc_flits_rep)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
dc_rep_upload_busy:
begin
if(rep_fifo_rdy)
begin
if(sel_cnt==flits_max_reg)
begin
fsm_rst=1'b1;
dc_ctrl_out=2'b11;
end
else if(sel_cnt==3'b000)
dc_ctrl_out=2'b01;
else
dc_ctrl_out=2'b10;
inc_cnt=1'b1;
v_dc_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
dc_rep_state<=1'b0;
else if(next)
dc_rep_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
dc_rep_flits<=176'h0000;
else if(en_flits_in)
dc_rep_flits<=dc_flits_rep;
end
reg [15:0] dc_flit_out;
always@(*)
begin
case(sel_cnt)
4'b0000:dc_flit_out=dc_rep_flits[175:160];
4'b0001:dc_flit_out=dc_rep_flits[159:144];
4'b0010:dc_flit_out=dc_rep_flits[143:128];
4'b0011:dc_flit_out=dc_rep_flits[127:112];
4'b0100:dc_flit_out=dc_rep_flits[111:96];
4'b0101:dc_flit_out=dc_rep_flits[95:80];
4'b0110:dc_flit_out=dc_rep_flits[79:64];
4'b0111:dc_flit_out=dc_rep_flits[63:48];
4'b1000:dc_flit_out=dc_rep_flits[47:32];
4'b1001:dc_flit_out=dc_rep_flits[31:16];
4'b1010:dc_flit_out=dc_rep_flits[15:0];
default:dc_flit_out=dc_rep_flits[175:160];
endcase
end
// flits_max
always@(posedge clk)
begin
if(rst||fsm_rst)
flits_max_reg<=4'b0000;
else if(en_flits_max)
flits_max_reg<=flits_max;
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=4'b0000;
else if(inc_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 5411 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w1028,
w1285,
w512,
w773,
w6184,
w5411;
assign w1 = i_data0;
assign w1028 = w257 << 2;
assign w1285 = w257 + w1028;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w512 = w1 << 9;
assign w5411 = w6184 - w773;
assign w6184 = w773 << 3;
assign w773 = w1285 - w512;
assign o_data0 = w5411;
//multiplier_block area estimate = 6802.48797345294;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> struct point { double x, y, z; point() {} point(double _x, double _y, double _z) : x(_x), y(_y), z(_z) {} }; const double eps = 1e-8; double vlen(point p) { return sqrt(p.x * p.x + p.y * p.y + p.z * p.z); } point xmult(point u, point v) { point ret; ret.x = u.y * v.z - v.y * u.z; ret.y = u.z * v.x - u.x * v.z; ret.z = u.x * v.y - u.y * v.x; return ret; } point subt(point u, point v) { point ret; ret.x = u.x - v.x; ret.y = u.y - v.y; ret.z = u.z - v.z; return ret; } int dot_online_in(point p, point l1, point l2) { return (((vlen(xmult(subt(p, l1), subt(p, l2)))) > 0 ? (vlen(xmult(subt(p, l1), subt(p, l2)))) : -(vlen(xmult(subt(p, l1), subt(p, l2))))) < eps) && (l1.x - p.x) * (l2.x - p.x) < eps && (l1.y - p.y) * (l2.y - p.y) < eps && (l1.z - p.z) * (l2.z - p.z) < eps; } double x[10001], y[10001], z[10001], d[10001]; int main() { int n; scanf( %d , &n); for (int i = 0; i <= n; i++) scanf( %lf %lf %lf , &x[i], &y[i], &z[i]); double vp, vs, px, py, pz; scanf( %lf %lf , &vp, &vs); scanf( %lf %lf %lf , &px, &py, &pz); double lo = 0, hi = 0; for (int i = 1; i <= n; i++) { d[i] = sqrt((x[i] - x[i - 1]) * (x[i] - x[i - 1]) + (y[i] - y[i - 1]) * (y[i] - y[i - 1]) + (z[i] - z[i - 1]) * (z[i] - z[i - 1])); hi += d[i] / vs; } if (hi * vp < sqrt((x[n] - px) * (x[n] - px) + (y[n] - py) * (y[n] - py) + (z[n] - pz) * (z[n] - pz))) printf( NO n ); else { double X = -1, Y = -1, Z = -1; while ((hi - lo) >= 1e-10) { double mid = (lo + hi) / 2; double s = mid * vs; for (int i = 1; i <= n; i++) if (s > d[i]) s -= d[i]; else { double t = s / d[i]; X = x[i - 1] + (x[i] - x[i - 1]) * t; Y = y[i - 1] + (y[i] - y[i - 1]) * t; Z = z[i - 1] + (z[i] - z[i - 1]) * t; if (!dot_online_in(point(X, Y, Z), point(x[i - 1], y[i - 1], z[i - 1]), point(x[i], y[i], z[i]))) { X = x[i - 1] - (x[i] - x[i - 1]) * t; Y = y[i - 1] - (y[i] - y[i - 1]) * t; Z = z[i - 1] - (z[i] - z[i - 1]) * t; } break; } if (mid * vp >= sqrt((X - px) * (X - px) + (Y - py) * (Y - py) + (Z - pz) * (Z - pz))) hi = mid; else lo = mid; } printf( YES n ); printf( %.10lf n , lo); printf( %.10lf %.10lf %.10lf n , X, Y, Z); } return 0; }
|
`include "../../../rtl/verilog/gfx/gfx_triangle.v"
`include "../../../rtl/verilog/gfx/div_uu.v"
module triangle_bench();
parameter point_width = 16;
parameter subpixel_width = 16;
reg clk_i;
reg rst_i;
reg ack_i;
wire ack_o;
reg triangle_write_i;
reg texture_enable_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_y_i;
wire [point_width-1:0] x_counter_o;
wire [point_width-1:0] y_counter_o;
wire write_o;
initial begin
$dumpfile("triangle.vcd");
$dumpvars(0,triangle_bench);
// init values
clk_i = 0;
rst_i = 1;
ack_i = 0;
triangle_write_i = 0;
dest_pixel0_x_i = -5 << subpixel_width;
dest_pixel0_y_i = 5 << subpixel_width;
dest_pixel1_x_i = 210 << subpixel_width;
dest_pixel1_y_i = 10 << subpixel_width;
dest_pixel2_x_i = 5 << subpixel_width;
dest_pixel2_y_i = 210 << subpixel_width;
texture_enable_i = 0;
//timing
#4 rst_i = 0;
#10 triangle_write_i = 1;
#2 triangle_write_i = 0;
#200
dest_pixel0_x_i = 5 << subpixel_width;
dest_pixel0_y_i = 15 << subpixel_width;
dest_pixel1_x_i = 10 << subpixel_width;
dest_pixel1_y_i = 10 << subpixel_width;
dest_pixel2_x_i = 5 << subpixel_width;
dest_pixel2_y_i = 10 << subpixel_width;
#10 triangle_write_i = 1;
#2 triangle_write_i = 0;
// end sim
#1000 $finish;
end
always begin
#1 clk_i = ~clk_i;
end
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
end
gfx_triangle triangle(
.clk_i (clk_i),
.rst_i (rst_i),
.ack_i (ack_i),
.ack_o (ack_o),
.triangle_write_i (triangle_write_i),
.texture_enable_i (texture_enable_i),
.dest_pixel0_x_i (dest_pixel0_x_i),
.dest_pixel0_y_i (dest_pixel0_y_i),
.dest_pixel1_x_i (dest_pixel1_x_i),
.dest_pixel1_y_i (dest_pixel1_y_i),
.dest_pixel2_x_i (dest_pixel2_x_i),
.dest_pixel2_y_i (dest_pixel2_y_i),
.x_counter_o (x_counter_o),
.y_counter_o (y_counter_o),
.write_o (write_o)
);
defparam triangle.point_width = point_width;
defparam triangle.subpixel_width = subpixel_width;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int u[5005][10005]; int n, m, a[5005], b[5005] = {1}, c[5005] = {1}, d[5005] = {1}, e[5005]; int expmod(int a, int b, int mod) { int res = 1; for (; b; b >>= 1) { if (b & 1) res = 1ll * res * a % mod; a = 1ll * a * a % mod; } return res; } int dunc(int k, int e) { if (k + e > n) return 0; return 1ll * c[k + e - 1] * d[k - 1] % mod; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) scanf( %d , &a[i]), b[i] = expmod(a[i], mod - 2, mod); for (int i = 1; i < n; i++) c[i] = 1ll * c[i - 1] * a[i] % mod; for (int i = 1; i < n; i++) d[i] = 1ll * d[i - 1] * b[i] % mod; int m = 2 * n - 2; for (int i = 2; i <= n; i++) { u[i][1] = 1; for (int j = 2; j <= m; j++) { u[i][j] = (u[i - 1][j - 1] + 1ll * dunc(i - 1, j - 1) * (a[i - 1] - 1) % mod * b[i - 1]) % mod; } } int ans; for (int i = 1; i <= m; i++) { ans = 0; for (int j = 1; j <= n; j++) { ans = (ans + 1ll * c[j - 1] * (u[j][i] + dunc(j, i))) % mod; } if (ans & 1) printf( %d n , ans + mod >> 1); else printf( %d n , ans >> 1); } }
|
#include <bits/stdc++.h> using namespace std; struct elem { int i1, i2, p1, p2, tipo; elem() {} elem(int i1, int i2) : i1(i1), i2(i2) { tipo = 0; } elem(int i1, int i2, int p1, int p2) : i1(i1), i2(i2), p1(p1), p2(p2) { tipo = 1; } }; int inverso(int x) { if (x == 2) return 3; if (x == 3) return 2; return x; } vector<elem> lista; const int limite = 505; int m, n; int t[limite][limite]; char buff[limite]; int b[limite]; void escribe() { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << t[i][j] << , ; cout << endl; } cout << endl; } int main() { scanf( %d%d , &m, &n); for (int j = 0; j < m; j++) { scanf( %s , buff); for (int i = 0; i < n; i++) t[i][j] = buff[i] - a ; } int jlibres = 0; int itope; { int jj = 0; int i = 0; while (i < n and jj < m) { int ii = i; while (ii < n and t[ii][jj] == 0) ii++; if (ii == n) { jj++; jlibres++; } else { lista.push_back(elem(i, ii)); for (int j = jj; j < m; j++) swap(t[i][j], t[ii][j]); for (int ii = i + 1; ii < n; ii++) { if (t[ii][jj]) { int p1 = -t[ii][jj]; int p2 = t[i][jj]; lista.push_back(elem(i, ii, p1, p2)); for (int j = jj; j < m; j++) t[ii][j] = (t[ii][j] * p2 + t[i][j] * p1) % 5; } } i++; jj++; } } itope = i; jlibres += m - jj; } long long int sol = 1; for (int j = 0; j < jlibres; j++) sol = sol * 5 % int(1e9 + 7); int casos; scanf( %d , &casos); for (int cas = 0; cas < casos; cas++) { scanf( %s , buff); for (int i = 0; i < n; i++) b[i] = buff[i] - a ; for (int k = 0; k < int(lista.size()); k++) { elem &e = lista[k]; int i1 = e.i1; int i2 = e.i2; int p1 = e.p1; int p2 = e.p2; if (e.tipo == 0) { swap(b[i1], b[i2]); } else { b[i2] = (b[i2] * p2 + b[i1] * p1) % 5; } } bool error = false; for (int i = itope; i < n and not error; i++) error = b[i] != 0; if (error) printf( %d n , 0); else printf( %d n , int(sol)); } }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 1e6 + 5; int n, q, m; const int N = 105; const int L = 1505; char s[maxn]; int tr[maxn][30], tot = 0; int fail[maxn], w[maxn]; vector<int> g[maxn]; void add(char *s, int id) { int u = 0; int n = strlen(s); for (int i = 0; i < n; i++) { int c = s[i] - a ; if (!tr[u][c]) tr[u][c] = ++tot; u = tr[u][c]; } w[id] = u; } struct bit_tree { long long c[maxn], n; void init(int x) { n = x; } inline int lowbit(int x) { return x & (-x); } inline void update(int x, int v) { for (int i = x; i <= n; i += lowbit(i)) { c[i] += v; } } inline long long query(int x) { long long ans = 0; for (int i = x; i > 0; i -= lowbit(i)) ans += c[i]; return ans; } } T; void ac() { queue<int> q; for (int i = 0; i < 26; i++) { if (tr[0][i]) q.push(tr[0][i]), fail[tr[0][i]] = 0; } while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < 26; i++) { if (tr[u][i]) { fail[tr[u][i]] = tr[fail[u]][i]; q.push(tr[u][i]); } else { tr[u][i] = tr[fail[u]][i]; } } } } int ins[maxn], out[maxn], cnt = 0; int vis[maxn]; void dfs(int x) { ins[x] = ++cnt; for (int i : g[x]) dfs(i); out[x] = cnt; } int main() { cin >> q >> n; for (int i = 1; i <= n; i++) { cin >> s; add(s, i); } ac(); for (int i = 1; i <= tot; i++) { g[fail[i]].push_back(i); } dfs(0); T.init(cnt); for (int i = 1; i <= n; i++) { vis[i] = 1; T.update(ins[w[i]], 1); T.update(out[w[i]] + 1, -1); } char c; int id; while (q--) { cin >> c; if (c == + ) { cin >> id; if (vis[id]) continue; vis[id] = 1; T.update(ins[w[id]], 1); T.update(out[w[id]] + 1, -1); } else if (c == - ) { cin >> id; if (!vis[id]) continue; vis[id] = 0; T.update(ins[w[id]], -1); T.update(out[w[id]] + 1, +1); } else { cin >> s; int m = strlen(s); long long p = 0, ans = 0; for (int i = 0; i < m; i++) { p = tr[p][s[i] - a ]; ans += T.query(ins[p]); } printf( %lld n , ans); } } return 0; }
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming encoder
*/
module ham_15_11_encoder (input d[10:0],output c[14:0]);
// Output signals representing the 15-bit encoded vector
output reg [14:0] c;
// Input signals representing the 15-bit output
input [10:0] req_vector;
// Declare "reg" signals...
// Parity bits for Hamming encoding
reg [3:0] p;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Determine for each parity bit, what data bits is it made of
p[0]=((d[0]^d[1])^(d[3]^d[4]))^((d[6]^d[8])^d[10]);
p[1]=((d[0]^d[2])^(d[3]^d[5]))^((d[6]^d[9])^d[10]);
p[2]=((d[1]^d[2])^(d[3]^d[7]))^((d[8]^d[9])^d[10]);
p[3]=((d[4]^d[5])^(d[6]^d[7]))^((d[8]^d[9])^d[10]);
// Assign the encoded signal bits to data bits...
c[2]=d[0];
c[4]=d[1];
c[5]=d[2];
c[6]=d[3];
c[8]=d[4];
c[9]=d[5];
c[10]=d[6];
c[11]=d[7];
c[12]=d[8];
c[13]=d[9];
c[14]=d[10];
// Introduce parity bits to encode signal values
c[0]=p[0];
c[1]=p[1];
c[3]=p[2];
c[7]=p[3];
endmodule
|
/*There is no salvation without suffering*/ #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #include<iostream> #include<string> #include<algorithm> #include<numeric> #include<cmath> #include<vector> #include<iomanip> #include<map> #include<set> #include<stack> #include<queue> #include<utility> #include<iterator> using namespace std; #define ll long long #define pb push_back #define pf push_front #define mp make_pair #define tt ll t;cin>>t;while(t--) #define nn cout<<endl; #define ff(i,a,n) for(ll i=a;i<n;i++) #define f(i,n,a) for(ll i=n;i>=a;i--) #define fr(x, a) for(auto &x:a) #define F(a) for(auto &x:a) cin>>x #define cY cout<< YES n #define cN cout<< NO n #define cy cout<< Yes n #define cn cout<< No n #define sc second #define fs first #define c(a) cout<<a<<endl #define all(a) a.begin(),a.end() #define pi 3.14159265359 ll M=1e9+7; ll mod(ll x){return ((x%M+M)%M);} ll gcd(ll a,ll b); ll lcm(ll a,ll b); bool prime(ll n); ll BinExp(ll base,ll power); ll ModInverse(ll base); ll nCr(ll n,ll r); ll fact(ll n){ return (n<=1)? 1 : n*fact(n-1);} /* Read the damn question carefully*/ void solve() { ll n; cin>>n; string a,b; cin>>a>>b; ll o=count(all(a), 1 ),z=n-o; ll x=0; bool ans=true; // c(o<< <<z); for(ll i=n-1;i>=0;i--) { if(x==0) { if(a[i]!=b[i]) { if(o==z) { x=1-x; if(a[i]== 1 ) { a[i]= 0 ; z--; } else { a[i]= 1 ; o--; } } else { ans=false; break; } } else { if(a[i]== 0 ) z--; else o--; } } else { if(a[i]== 1 ) a[i]= 0 ; else a[i]= 1 ; if(a[i]!=b[i]) { if(o==z) { x=1-x; if(a[i]== 1 ) { a[i]= 0 ; z--; } else { a[i]= 1 ; o--; } } else { ans=false; break; } } else { if(a[i]== 0 ) z--; else o--; } } } // c(a); if(ans) cY; else cN; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); tt solve(); } /* */ ll nCr(ll n,ll r) { r=(n-r<=r) ? n-r : r; ll ans=1; for(ll i=0;i<r;i++) { ans*=(n-i); ans/=(i+1); } return ans; } ll gcd(ll a,ll b){ if(a==0) return b; return (a==1) ? a:gcd(b%a,a); } ll lcm(ll a,ll b) {return (a/gcd(a,b))*b; } bool prime(ll n){ if(n<2) return false; for(ll i=2;i<=sqrt(n);i++) if(n%i==0) return false; return true; } ll BinExp(ll base,ll power){ if(!power) return 1; ll res=1; while(power>1){ if(power%2){ power--; res*=base; } else{ base*=base; power/=2; } } return base*res; } ll ModInverse(ll base){ ll power=M-2; if(!power) return 1; ll res=1; while(power>1){ if(power%2){ power--; res=mod(res*base); } else{ base=mod(base*base); power/=2; } } return mod(base*res); }
|
// this test was yanked from another file and may require
// a few syntax error fixes.
//
module test_mesh_to_ring_stitch
#(
parameter cycle_time_p = 20,
localparam num_tiles_x_p = 8,
localparam num_tiles_y_p = 8,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
import bsg_noc_pkg ::*; // {P=0, W, E, N, S}
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
localparam b_lp = 1;
localparam f_lp = 1;
localparam x_lp = (num_tiles_x_p);
localparam y_lp = (num_tiles_y_p);
logic [x_lp-1:0][y_lp-1:0][$clog2(x_lp*y_lp)-1:0] ids;
logic [x_lp-1:0][y_lp-1:0][b_lp-1:0] back_in, back_out;
logic [x_lp-1:0][y_lp-1:0][f_lp-1:0] fwd_in, fwd_out;
bsg_mesh_to_ring_stitch #(.y_max_p(y_lp)
,.x_max_p(x_lp)
,.width_back_p(b_lp)
,.width_fwd_p(f_lp)
) m2r
(.id_o (ids )
,.back_data_in_o (back_in )
,.back_data_out_i(back_out)
,.fwd_data_in_o (fwd_in )
,.fwd_data_out_i (fwd_out )
);
always @(posedge clk)
begin
if (reset)
begin
back_out <= $bits(back_in) ' (1);
fwd_out <= $bits(fwd_in) ' (1);
end
else
begin
back_out <= back_in;
fwd_out <= fwd_in;
end
end
integer xx,yy;
always @(negedge clk)
begin
for (yy = 0; yy < y_lp; yy=yy+1)
begin
for (xx = 0; xx < x_lp; xx=xx+1)
$write("%b", fwd_in[xx][yy]);
$write(" ");
for (xx = 0; xx < x_lp; xx=xx+1)
$write("%b", back_in[xx][yy]);
$write("\n");
end
$write("\n");
end
endmodule
|
/*
* Zet processor top level file
* Copyright (c) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module zet (
// Wishbone master interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o, // io/mem
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i,
input wb_tgc_i, // intr
output wb_tgc_o, // inta
input nmi,
output nmia,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [15:0] cpu_dat_o;
wire cpu_block;
wire [19:0] cpu_adr_o;
wire cpu_byte_o;
wire cpu_mem_op;
wire cpu_m_io;
wire [15:0] cpu_dat_i;
wire cpu_we_o;
wire [15:0] iid_dat_i;
// Module instantiations
zet_core core (
.clk (wb_clk_i),
.rst (wb_rst_i),
.intr (wb_tgc_i),
.inta (wb_tgc_o),
.nmi (nmi),
.nmia (nmia),
.cpu_adr_o (cpu_adr_o),
.iid_dat_i (iid_dat_i),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_byte_o (cpu_byte_o),
.cpu_block (cpu_block),
.cpu_mem_op (cpu_mem_op),
.cpu_m_io (cpu_m_io),
.cpu_we_o (cpu_we_o),
.pc (pc)
);
zet_wb_master wb_master (
.cpu_byte_o (cpu_byte_o),
.cpu_memop (cpu_mem_op),
.cpu_m_io (cpu_m_io),
.cpu_adr_o (cpu_adr_o),
.cpu_block (cpu_block),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_we_o (cpu_we_o),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
// Assignments
assign iid_dat_i = (wb_tgc_o | nmia) ? wb_dat_i : cpu_dat_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long UNDEF = -1; const long long INF = 1e18; template <typename T> inline bool chkmax(T& aa, T bb) { return aa < bb ? aa = bb, true : false; } template <typename T> inline bool chkmin(T& aa, T bb) { return aa > bb ? aa = bb, true : false; } static char stdinBuffer[1024]; static char* stdinDataEnd = stdinBuffer + sizeof(stdinBuffer); static const char* stdinPos = stdinDataEnd; void readAhead(size_t amount) { size_t remaining = stdinDataEnd - stdinPos; if (remaining < amount) { memmove(stdinBuffer, stdinPos, remaining); size_t sz = fread(stdinBuffer + remaining, 1, sizeof(stdinBuffer) - remaining, stdin); stdinPos = stdinBuffer; stdinDataEnd = stdinBuffer + remaining + sz; if (stdinDataEnd != stdinBuffer + sizeof(stdinBuffer)) *stdinDataEnd = 0; } } int rint() { readAhead(16); int x = 0; bool neg = false; while (*stdinPos == || *stdinPos == n ) ++stdinPos; if (*stdinPos == - ) { ++stdinPos; neg = true; } while (*stdinPos >= 0 && *stdinPos <= 9 ) { x *= 10; x += *stdinPos - 0 ; ++stdinPos; } return neg ? -x : x; } char rch() { readAhead(16); while (*stdinPos == || *stdinPos == n ) ++stdinPos; char ans = *stdinPos; ++stdinPos; return ans; } long long rlong() { readAhead(32); long long x = 0; bool neg = false; while (*stdinPos == || *stdinPos == n ) ++stdinPos; if (*stdinPos == - ) { ++stdinPos; neg = true; } while (*stdinPos >= 0 && *stdinPos <= 9 ) { x *= 10; x += *stdinPos - 0 ; ++stdinPos; } return neg ? -x : x; } const int mc = 26, mn = 1e6 + 4; char s[mn], t[mn]; int sc[mc + 1], tc[mc + 1], wc[mc + 1]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); scanf( %s n%s n , s, t); int sl = strlen(s), tl = strlen(t); int q = 0; for (int i = 0; i < sl; i++) { if (s[i] != ? ) sc[s[i] - a ]++; else q++; } for (int i = 0; i < tl; i++) { tc[t[i] - a ]++; } int imin = 0, imax = mn; while (imin < imax) { int imid = (imin + imax) >> 1; long long need = 0; for (int c = 0; c < 26; c++) { long long want = (tc[c] * (long long)imid) - sc[c]; if (want >= 0) need += want; } if (need <= q) imin = imid + 1; else imax = imid; } imin--; for (int c = 0; c < 26; c++) { wc[c] = tc[c] * imin - sc[c]; } int cidx = 0; for (int i = 0; i < sl; i++) { if (s[i] == ? ) { while (cidx < mc && wc[cidx] <= 0) cidx++; if (cidx < mc) { s[i] = a + cidx; wc[cidx]--; } else { s[i] = a ; } } } printf( %s n , s); }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(0); cin.tie(0); int qq = 1; cin >> qq; for (int qqq = 0; qqq < qq; qqq++) { int n, first, v; cin >> n >> first; int maxx = 0; int maxxd = 0; for (int i = 0; i < n; i++) { cin >> v; maxx = max(maxx, v); if (v <= first) { maxxd = max(maxxd, v); } } if (maxxd == 0) cout << 2 << n ; else if (maxx == maxxd) { cout << first / maxx + (first % maxx > 0) << n ; } else if (maxxd == first) { cout << 1 << n ; } else cout << 2 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n, x, y; cin >> n >> x >> y; long long arr[n]; for (long long i = 0; i < n; i++) { cin >> arr[i]; } long long an = -1; for (long long i = 0; i < n; i++) { bool ans = true; for (long long j = i - 1; j >= 0 && j >= i - x; j--) { if (arr[j] < arr[i]) { ans = false; break; } } for (long long j = i + 1; j < n && j <= i + y; j++) { if (arr[j] < arr[i]) { ans = false; break; } } if (ans) { an = i; break; } } cout << an + 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[1001][1001]; int vis[1001][1001]; int n, m; void dfs(int x, int y) { vis[x][y] = 1; if (x - 1 >= 0 && !vis[x - 1][y] && a[x - 1][y] == # ) { dfs(x - 1, y); } if (x + 1 < n && !vis[x + 1][y] && a[x + 1][y] == # ) { dfs(x + 1, y); } if (y - 1 >= 0 && !vis[x][y - 1] && a[x][y - 1] == # ) { dfs(x, y - 1); } if (y + 1 < m && !vis[x][y + 1] && a[x][y + 1] == # ) { dfs(x, y + 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; int f1 = 0, f2 = 0, f3 = 0; int awr = 0, awc = 0, c = 0, ans = 0; for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (!f1 && a[i][j] == # ) { f1 = 1; } else if (f1 && !f2 && a[i][j] == . ) { f2 = 1; } else if (f1 && f2 && !f3 && a[i][j] == # ) { f3 = 1; } } if (f1 && f2 && f3) { cout << -1 n ; goto here; } else { f1 = f2 = f3 = 0; } } for (int j = 0; j < m; ++j) { for (int i = 0; i < n; ++i) { if (!f1 && a[i][j] == # ) { f1 = 1; } else if (f1 && !f2 && a[i][j] == . ) { f2 = 1; } else if (f1 && f2 && !f3 && a[i][j] == # ) { f3 = 1; } } if (f1 && f2 && f3) { cout << -1 n ; goto here; } else { f1 = f2 = f3 = 0; } } for (int i = 0; i < n; ++i) { c = 0; for (int j = 0; j < m; ++j) { if (a[i][j] == . ) { c++; } } if (c == m) { awr = 1; break; } } for (int j = 0; j < m; ++j) { c = 0; for (int i = 0; i < n; ++i) { if (a[i][j] == . ) { c++; } } if (c == n) { awc = 1; break; } } if (awr ^ awc) { cout << -1 n ; goto here; } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (a[i][j] == # && !vis[i][j]) { ans++; dfs(i, j); } } } cout << ans << n ; here:; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, col, row; cin >> n; col = sqrt(n); while (1) { if (n % col == 0) { int a, b; a = n / col; b = col; if (a >= b) cout << b << << a << endl; else cout << a << << b << endl; break; } else col++; } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [11:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [19:0] gpio_wire;
// instantiations
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
.dio_p ({ gpio_wire,
gpio_bd}));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; int n, m, a[N], b[N], t[N]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d%d , &a[i], &b[i]); int x = a[1], cnt = 0; for (int i = 1; i <= m; i++) if (a[i] == x || b[i] == x) cnt++; for (int i = 1; i <= m; i++) { if (a[i] == x || b[i] == x) continue; if (a[i] == b[i]) t[a[i]]++; else t[a[i]]++, t[b[i]]++; } for (int i = 1; i <= n; i++) if (t[i] + cnt == m) return puts( YES ), 0; x = b[1], cnt = 0; memset(t, 0, sizeof(t)); for (int i = 1; i <= m; i++) if (a[i] == x || b[i] == x) cnt++; for (int i = 1; i <= m; i++) { if (a[i] == x || b[i] == x) continue; if (a[i] == b[i]) t[a[i]]++; else t[a[i]]++, t[b[i]]++; } for (int i = 1; i <= n; i++) if (t[i] + cnt == m) return puts( YES ), 0; x = a[2], cnt = 0; memset(t, 0, sizeof(t)); for (int i = 1; i <= m; i++) if (a[i] == x || b[i] == x) cnt++; for (int i = 1; i <= m; i++) { if (a[i] == x || b[i] == x) continue; if (a[i] == b[i]) t[a[i]]++; else t[a[i]]++, t[b[i]]++; } for (int i = 1; i <= n; i++) if (t[i] + cnt == m) return puts( YES ), 0; x = b[2], cnt = 0; memset(t, 0, sizeof(t)); for (int i = 1; i <= m; i++) if (a[i] == x || b[i] == x) cnt++; for (int i = 1; i <= m; i++) { if (a[i] == x || b[i] == x) continue; if (a[i] == b[i]) t[a[i]]++; else t[a[i]]++, t[b[i]]++; } for (int i = 1; i <= n; i++) if (t[i] + cnt == m) return puts( YES ), 0; return puts( NO ), 0; }
|
#include <bits/stdc++.h> using namespace std; long long read() { long long x = 0, f = 0; char c = getchar(); while (!isdigit(c)) f |= c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); return f ? -x : x; } inline int max(int a, int b, int c) { return max(a, max(b, c)); } int n, m, a[200010]; struct Trie { int nxt[2], sz; } T[200010 * 31]; int rt = 1, top = 1; void insert(int x) { int now = rt; for (int i = 31; ~i; --i) { if (!T[now].nxt[x >> i & 1]) T[now].nxt[x >> i & 1] = ++top; now = T[now].nxt[x >> i & 1]; } T[now].sz = 1; } int ans; int dfs(int i, int d) { if (!i) return 0; int ls, rs; if (d == -1) return min(2, T[i].sz); ls = dfs(T[i].nxt[0], d - 1); T[i].sz += T[T[i].nxt[0]].sz; rs = dfs(T[i].nxt[1], d - 1); T[i].sz += T[T[i].nxt[1]].sz; if (ls == 2 && rs == 2) ans += min(T[T[i].nxt[0]].sz, T[T[i].nxt[1]].sz) - 1, T[i].sz -= min(T[T[i].nxt[0]].sz, T[T[i].nxt[1]].sz) - 1; return min(2, ls + rs); } int main() { cin >> n; for (int i = 1; i <= n; ++i) a[i] = read(), insert(a[i]); dfs(rt, 31); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops ) #pragma GCC target( avx,avx2,fma ) using namespace std; const long long mod1 = 998244353; const long long mod = 1e9 + 7; long long mod_mul(long long a, long long b) { a = a % mod; b = b % mod; return (((a * b) % mod) + mod) % mod; } long long inv(long long i) { if (i == 1) return 1; return (mod - ((mod / i) * inv(mod % i)) % mod) % mod; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long pwr(long long a, long long b) { a %= mod; long long res = 1; while (b > 0) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } long long findMinNumber(long long n) { long long count = 0, ans = 1; while (n % 2 == 0) { count++; n /= 2; } if (count % 2) ans *= 2; for (int i = 3; i <= sqrt(n); i += 2) { count = 0; while (n % i == 0) { count++; n /= i; } if (count % 2) ans *= i; } if (n > 2) ans *= n; return ans; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { long long n, k, i, j; cin >> n >> k; map<long long, long long> m; vector<long long> ans; vector<pair<long long, long long> > v; long long a[k][2]; for (i = 0; i < k; i++) { cin >> a[i][0] >> a[i][1]; v.push_back({a[i][0], a[i][1]}); m[a[i][0]]++; m[a[i][1]]++; } for (i = 1; i < 2 * n + 1; i++) if (m[i] == 0) ans.push_back(i); for (i = 0; i < ans.size() / 2; i++) { v.push_back({ans[i], ans[ans.size() / 2 + i]}); } long long cnt = 0; sort((v).begin(), (v).end()); for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (i != j) { long long x = (v[i].second - v[j].first) * (v[i].first - v[j].first); long long y = (v[i].second - v[j].second) * (v[i].first - v[j].second); if (x * y < 0) { cnt++; } } } } cout << cnt / 2 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void Routine() { srand(time(NULL)); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } template <class T, class U> istream &operator>>(istream &in, pair<T, U> &p) { in >> p.fi >> p.se; return in; } template <class T, class U> ostream &operator<<(ostream &out, const pair<T, U> &p) { out << p.first << << p.second; return out; } template <class T> istream &operator>>(istream &in, vector<T> &v) { for (auto &i : v) { in >> i; } return in; } template <class T> ostream &operator<<(ostream &out, const vector<T> &v) { for (auto &i : v) { out << i << n ; } return out; } const long long mod = 1e9 + 7; int main() { Routine(); long long q, l1, l2, r1, r2, i; cin >> q; for (i = 0; i < q; i++) { cin >> l1 >> r1 >> l2 >> r2; if (l1 != r2) { cout << l1 << << r2 << n ; } else { cout << r1 << << l2 << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long MOD = 998244353; inline long long Msum(long long x) { return x; } template <typename... Rest> inline long long Msum(long long x, Rest... rest) { return (x + Msum(rest...)) % MOD; } inline long long Mprod(long long x) { return x; } template <typename... Rest> inline long long Mprod(long long x, Rest... rest) { return x * Mprod(rest...) % MOD; } inline long long Mnorm(long long x) { return (x % MOD + MOD) % MOD; } long long Msq(long long x) { return x * x % MOD; } long long Mpow(long long b, long long e) { return e ? Mprod(Msq(Mpow(b, e >> 1)), (e & 1 ? b : 1)) : 1; } long long Minv(long long x) { return Mpow(x, MOD - 2); } const int MAXN = 51; int sns[MAXN], w[MAXN]; int wi, sn; int sl, sd, S; long long dp[MAXN][MAXN][MAXN]; long long f(int h, int hl, int hd, int t) { if (!t) return 0; long long &ret = dp[h][hl][hd]; if (ret != -1) return ret; ret = 0; long long cS = S + hl - hd + sn * h; ret += Mprod(wi + sn * h, Minv(cS), 1 + f(h + 1, hl, hd, t - 1)); ret = Mnorm(ret); ret += Mprod(sl + hl, Minv(cS), f(h, hl + 1, hd, t - 1)); ret = Mnorm(ret); ret += Mprod(sd - hd, Minv(cS), f(h, hl, hd + 1, t - 1)); ret = Mnorm(ret); assert(sd - hd + sl + hl + wi + sn * h == cS); return ret; } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &sns[i]); sns[i] = sns[i] * 2 - 1; } for (int i = 0; i < n; i++) { scanf( %d , &w[i]); } for (int i = 0; i < n; i++) { S = sl = sd = 0; wi = w[i]; sn = sns[i]; for (int j = 0; j < (int)n; j++) { S += w[j]; if (j != i) { if (sns[j] == 1) sl += w[j]; else sd += w[j]; } } memset(dp, -1, sizeof(dp)); printf( %lld n , Mnorm(wi + sn * f(0, 0, 0, m))); } }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:09 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.v
// Design : ip_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, n, bt[1000001] = {}, ar[1000001] = {}; vector<int> v; int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; i++) { cin >> ar[i]; ar[i] = i - ar[i]; bt[i] = 0; } int x = 0; while (!bt[x]) { v.push_back(x); bt[x] = v.size(); x = ar[x]; } cout << v.size() - bt[x] + 1 << n ; for (int i = bt[x] - 1; i < v.size(); i++) { cout << v[i] + 1; if (i < v.size() - 1) { cout << ; } } cout << n ; v.clear(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string str, result = , tmp; map<string, int> array; cin >> str; for (long long i = 0; i < 10; i++) cin >> tmp, array[tmp] = i; tmp = ; for (long long i = 0; i < 80; i++) { tmp += str[i]; if ((i + 1) % 10 == 0) result += array[tmp] + 0 , tmp = ; } cout << result << endl; return 0; }
|
#include <algorithm> #include <bitset> #include <cmath> #include <complex> #include <cstdio> #include <iostream> #include <map> #include <numeric> #include <queue> #include <random> #include <set> #include <stack> #include <string> #include <sys/types.h> #include <unistd.h> #include <unordered_map> #include <unordered_set> #include <vector> #pragma region macros #define _overload(_1, _2, _3, name, ...) name #define _rep(i, n) _range(i, 0, n) #define _range(i, a, b) for (int i = int(a); i < int(b); ++i) #define rep(...) _overload(__VA_ARGS__, _range, _rep, )(__VA_ARGS__) #define _rrep(i, n) _rrange(i, n, 0) #define _rrange(i, a, b) for (int i = int(a) - 1; i >= int(b); --i) #define rrep(...) _overload(__VA_ARGS__, _rrange, _rrep, )(__VA_ARGS__) #pragma endregion macros using namespace std; template <class T> bool chmax(T &a, const T &b) { return (a < b) ? (a = b, 1) : 0; } template <class T> bool chmin(T &a, const T &b) { return (b < a) ? (a = b, 1) : 0; } using ll = long long; using R = long double; const R EPS = 1e-9L; // [-1000,1000]->EPS=1e-8 [-10000,10000]->EPS=1e-7 inline int sgn(const R &r) { return (r > EPS) - (r < -EPS); } inline R sq(R x) { return sqrt(max(x, 0.0L)); } const int dx[8] = {1, 0, -1, 0, 1, -1, -1, 1}; const int dy[8] = {0, 1, 0, -1, 1, 1, -1, -1}; const pid_t pid = getpid(); // Problem Specific Parameter: ll p[1010][1010]; ll psum[1010]; ll p2sum[1010]; int main(void) { std::cin.tie(0); std::ios::sync_with_stdio(false); int m, k; cin >> m >> k; rep(i, k) { rep(j, m) { cin >> p[i][j]; psum[i] += p[i][j]; p2sum[i] += 1LL * p[i][j] * p[i][j]; } } const ll vsum = (psum[k - 1] - psum[0]) / (k - 1); ll y = -1; rep(i, 1, k - 1) { const ll v = (psum[i] - psum[i - 1]); if (v != vsum) { y = i; break; } } ll x; rep(j, m) { const ll v = (psum[y] - psum[y - 1]); const ll modify = vsum - v; p2sum[y] -= p[y][j] * p[y][j]; p[y][j] += modify; p2sum[y] += p[y][j] * p[y][j]; set<ll> s; rep(i, 1, k - 1) { const ll d2 = (p2sum[i - 1] + p2sum[i + 1]) - 2LL * p2sum[i]; s.insert(d2); } if (s.size() == 1) { x = p[y][j]; break; } p2sum[y] -= p[y][j] * p[y][j]; p[y][j] -= modify; p2sum[y] += p[y][j] * p[y][j]; } cout << y << << x << endl; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule
|
#include <bits/stdc++.h> using namespace std; int vis[400000], cur, path[500000], block[500000], x, y, n, m, q, k, s, t, seen[400010], ans[400010]; vector<int> g[4000]; map<pair<int, int>, vector<pair<int, int> > > M; void color(int x) { if (block[x]) return; block[x] = 1; for (int i = 0; i < g[x].size(); i++) color(g[x][i]); } void dfs(int x, int dep) { if (vis[x]) { int now = dep - 1; while (path[now] != x && now > 0) color(path[now--]); color(path[now]); } if (seen[x]) return; path[dep] = x; vis[x] = seen[x] = 1; if (M.find(make_pair(cur, x)) != M.end()) { if (!block[x]) { vector<pair<int, int> > tmp = M[make_pair(cur, x)]; for (int i = 0; i < tmp.size(); i++) if (tmp[i].first <= dep) ans[tmp[i].second] = path[tmp[i].first]; } } for (int i = 0; i < g[x].size(); i++) dfs(g[x][i], dep + 1); vis[x] = 0; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &y); g[x].push_back(y); } for (int i = 1; i <= n; i++) sort(g[i].begin(), g[i].end()); for (int i = 1; i <= q; i++) { scanf( %d%d%d , &s, &t, &k); M[make_pair(s, t)].push_back(make_pair(k, i)); } memset(ans, 0xff, sizeof(ans)); for (int i = 1; i <= n; i++) { cur = i; memset(seen, 0, sizeof(seen)); memset(block, 0, sizeof(block)); dfs(i, 1); } for (int i = 1; i <= q; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = 10000000; int n, m, x, y, a, b; int vabs(int t) { return (t > 0) ? t : (-t); } int calc(int cx, int cy) { int dx = vabs(cx - x); int dy = vabs(cy - y); if (dx == 0 && dy == 0) return 0; if (dx % a != 0 || dy % b != 0) return oo; int ca = dx / a, cb = dy / b; if (vabs(ca - cb) % 2 != 0) return oo; if (ca < cb && cx - a < 1 && cx + a > n) return oo; if (ca > cb && cy - b < 1 && cy + b > m) return oo; return max(ca, cb); } int main() { while (cin >> n) { cin >> m >> x >> y >> a >> b; int ans = oo; ans = min(ans, calc(1, 1)); ans = min(ans, calc(1, m)); ans = min(ans, calc(n, 1)); ans = min(ans, calc(n, m)); if (ans == oo) cout << Poor Inna and pony! << endl; else cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { long long int temp; while (b > 0) { temp = b; b = a % b; a = temp; } return a; } int main() { long long int N, m; cin >> N >> m; long long int a[N], B[m]; for (long long int i = 0; i < N; i++) { cin >> a[i]; } long long int n = N - 1; long long int A[n]; for (long long int i = 1; i < N; i++) { A[i - 1] = a[i] - a[i - 1]; } for (long long int i = 0; i < m; i++) { cin >> B[i]; } long long int result = A[0]; for (long long int i = 1; i < n; i++) { result = gcd(result, A[i]); } long long int j = 0; while (j < m && result % B[j] != 0) { j++; } if (j < m) { cout << YES << endl; cout << a[0] << << j + 1 << endl; } else { cout << NO << endl; } }
|
#include <bits/stdc++.h> const int MAXN = 1000000; int N; long long Ans; std::vector<int> G[MAXN + 5]; long long Val[MAXN + 5]; int Size[MAXN + 5]; int Fa[MAXN + 5], Dep[MAXN + 5]; void Dfs(int u, int fa, int dep) { Size[u] = 1; Fa[u] = fa; Dep[u] = dep; for (int i = 0; i < int(G[u].size()); i++) { int v = G[u][i]; if (v != fa) { Dfs(v, u, dep + 1); Size[u] += Size[v]; Val[u] += (long long)Size[v] * Size[v]; } } Val[u] += (long long)(N - Size[u]) * (N - Size[u]); Ans -= Val[u]; } int Pa[MAXN + 5], Num[MAXN + 5]; int Find(int u) { return Pa[u] == u ? u : Pa[u] = Find(Pa[u]); } long long In1(int u) { return (long long)(N - Num[u]) * (N - Num[u]) * Num[u] - Val[u] * Num[u]; } long long In2(int u) { return (long long)Num[u] * (Num[u] - 1) * 2 * (N - Num[u]); } long long In3(int u) { return std::max((long long)Num[u] * (Num[u] - 1) * (Num[u] - 2), 0ll); } void Merge(int u, int v) { Ans -= In1(u) + In2(u) + In3(u); Ans -= In1(v) + In2(v) + In3(v); Pa[v] = u, Num[u] += Num[v]; Val[u] += Val[v] - (long long)Size[v] * Size[v] - (long long)(N - Size[v]) * (N - Size[v]); Ans += In1(u) + In2(u) + In3(u); } int main() { scanf( %d , &N); for (int i = 1; i < N; i++) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v), G[v].push_back(u); } Ans = (long long)N * (N - 1) * (N - 1); Dfs(1, 0, 0); printf( %lld n , Ans); for (int i = 1; i <= N; i++) Pa[i] = i, Num[i] = 1; int Q; scanf( %d , &Q); while (Q--) { int u, v; scanf( %d%d , &u, &v); u = Find(u), v = Find(v); while (u != v) { if (Dep[u] < Dep[v]) std::swap(u, v); int anc = Find(Fa[u]); Merge(anc, u), u = anc; } printf( %lld n , Ans); } return 0; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Scheme Equality for nat.
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_triangle.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU triangle channel.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_triangle
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] triangle_out, // triangle channel output
output wire active_out // triangle channel active (length counter > 0)
);
//
// Timer
//
reg [10:0] q_timer_period;
wire [10:0] d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(11)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in(q_timer_period),
.pulse_out(timer_pulse)
);
assign d_timer_period = (wr_in && (a_in == 2'b10)) ? { q_timer_period[10:8], d_in[7:0] } :
(wr_in && (a_in == 2'b11)) ? { d_in[2:0], q_timer_period[7:0] } :
q_timer_period;
//
// Linear Counter
//
reg q_linear_counter_halt;
wire d_linear_counter_halt;
reg [7:0] q_linear_counter_cntl;
wire [7:0] d_linear_counter_cntl;
reg [6:0] q_linear_counter_val;
wire [6:0] d_linear_counter_val;
wire linear_counter_en;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_linear_counter_halt <= 1'b0;
q_linear_counter_cntl <= 8'h00;
q_linear_counter_val <= 7'h00;
end
else
begin
q_linear_counter_halt <= d_linear_counter_halt;
q_linear_counter_cntl <= d_linear_counter_cntl;
q_linear_counter_val <= d_linear_counter_val;
end
end
assign d_linear_counter_cntl = (wr_in && (a_in == 2'b00)) ? d_in : q_linear_counter_cntl;
assign d_linear_counter_val =
(eg_pulse_in && q_linear_counter_halt) ? q_linear_counter_cntl[6:0] :
(eg_pulse_in && (q_linear_counter_val != 7'h00)) ? q_linear_counter_val - 7'h01 :
q_linear_counter_val;
assign d_linear_counter_halt =
(wr_in && (a_in == 2'b11)) ? 1'b1 :
(eg_pulse_in && !q_linear_counter_cntl[7]) ? 1'b0 :
q_linear_counter_halt;
assign linear_counter_en = |q_linear_counter_val;
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
always @(posedge clk_in)
begin
if (rst_in)
q_length_counter_halt <= 1'b0;
else
q_length_counter_halt <= d_length_counter_halt;
end
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[7] : q_length_counter_halt;
assign length_counter_wr = wr_in && (a_in == 2'b11);
//
// Sequencer
//
reg [4:0] q_seq;
wire [4:0] d_seq;
wire [3:0] seq_out;
always @(posedge clk_in)
begin
if (rst_in)
q_seq <= 5'h0;
else
q_seq <= d_seq;
end
assign d_seq = (active_out && timer_pulse) ? q_seq + 5'h01 : q_seq;
assign seq_out = (q_seq[4]) ? q_seq[3:0] : ~q_seq[3:0];
assign active_out = linear_counter_en && length_counter_en;
assign triangle_out = seq_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; map<vector<int>, int> mp; map<int, int> dp[100050]; set<int> ans; vector<int> vec[100050]; int n, cnt = 0; int getid(vector<int> t) { if (mp.find(t) == mp.end()) return mp[t] = ++cnt; else return mp[t]; } int getv(int x, int y) { if (dp[x].find(y) != dp[x].end()) return dp[x][y]; vector<int> tmp; tmp.clear(); for (int i = 0; i <= (int)vec[x].size() - 1; i++) { int t = vec[x][i]; if (t == y) continue; tmp.push_back(getv(t, x)); } sort(tmp.begin(), tmp.end()); return dp[x][y] = getid(tmp); } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); vec[x].push_back(y), vec[y].push_back(x); } for (int i = 1; i <= n; i++) if ((int)vec[i].size() < 4) ans.insert(getv(i, 0)); printf( %d n , (int)ans.size()); return 0; }
|
module main;
reg [2:0] Q;
reg clk, clr, up;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED");
$finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b010) begin
$display("FAILED");
$finish;
end
up = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b010) begin
$display("FAILED");
$finish;
end
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP counter. The up
* count is enabled by the up signal. The clr is an asynchronous
* clear input.
*
* NOTE: This is bad style. Bad, bad style. It comes from a
* customer's customer, so I try to support it, but I'll moan
* about it. Much better (and clearer) is:
*
* if (clr)
* Q <= 0;
* else
* Q <= Q+1;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr) begin
if (up)
Q = Q + 1;
if (clr)
Q = 0;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int MAX = 200005; int visited[MAX]; int a[MAX], dis[MAX]; int n; void bfs() { queue<int> q; int b; visited[1] = 1; dis[1] = 0; q.push(1); while (!q.empty()) { b = q.front(); q.pop(); if (!visited[b + 1] && b + 1 <= n) { visited[b + 1] = 1; dis[b + 1] = dis[b] + 1; q.push(b + 1); } if (!visited[b - 1] && b - 1 > 0) { visited[b - 1] = 1; dis[b - 1] = dis[b] + 1; q.push(b - 1); } if (!visited[a[b]]) { visited[a[b]] = 1; dis[a[b]] = dis[b] + 1; q.push(a[b]); } } } int main() { while (cin >> n) { for (int i = 1; i <= n; i++) { cin >> a[i]; } memset(visited, 0, sizeof(visited)); bfs(); for (int i = 1; i <= n; i++) { if (i == 1) cout << dis[i]; else cout << << dis[i]; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; vector<int> ans; char s1[maxn], s2[maxn]; int n; void op(int x) { for (int i = 1; i <= x; ++i) { s1[i] = s1[i] == 0 ? 1 : 0 ; } reverse(s1 + 1, s1 + 1 + x); ans.push_back(x); } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { cin >> n; cin >> s1 + 1 >> s2 + 1; ans.clear(); for (int i = n; i >= 1; --i) { if (s1[i] == s2[i]) continue; if (i == 1) op(1); else { if (s1[1] == s2[i]) op(1); op(i); } } cout << ((int)ans.size()); for (auto &v : ans) cout << << v; cout << n ; } return 0; }
|
#include <bits/stdc++.h> struct DSU { private: int32_t* parents; int32_t* sizes; std::vector<std::pair<int32_t, int32_t> > actions; int32_t get_root(int32_t v) { if (parents[v] == v) return v; return get_root(parents[v]); } public: DSU(int32_t n) { parents = new int32_t[n]; sizes = new int32_t[n]; for (int32_t i = 0; i < n; i++) { parents[i] = i; sizes[i] = 1; } } bool same(int32_t v1, int32_t v2) { return get_root(v1) == get_root(v2); } void join(int32_t v1, int32_t v2) { int32_t root1 = get_root(v1), root2 = get_root(v2); if (root1 == root2) { actions.emplace_back(-1, -1); return; } if (sizes[root1] > sizes[root2]) { int32_t tmp = root1; root1 = root2; root2 = tmp; } parents[root1] = root2; sizes[root2] += sizes[root1]; actions.emplace_back(root1, root2); } void pop() { if (actions.back().first != -1) { sizes[parents[actions.back().first]] -= sizes[actions.back().first]; parents[actions.back().first] = actions.back().first; } actions.pop_back(); } }; struct Tracker { private: DSU all_dsu; DSU comp_dsu; int32_t num_edges = 0; int32_t broken_since = -1; std::set<int32_t>* graph; std::vector<int32_t> actions_time; public: Tracker(int32_t n) : all_dsu(n), comp_dsu(n) { graph = new std::set<int32_t>[n]; } void add_edge(int32_t v1, int32_t v2) { if (all_dsu.same(v1, v2)) { if (comp_dsu.same(v1, v2)) { if (broken_since == -1) broken_since = num_edges; } else { } } else { if (graph[v2].size() > 0) { comp_dsu.join(v1, *graph[v2].begin()); actions_time.push_back(num_edges); } if (graph[v1].size() > 0) { comp_dsu.join(v2, *graph[v1].begin()); actions_time.push_back(num_edges); } } all_dsu.join(v1, v2); graph[v1].insert(v2); graph[v2].insert(v1); num_edges++; } void pop_edge(int32_t v1, int32_t v2) { num_edges--; if (num_edges == broken_since) broken_since = -1; all_dsu.pop(); graph[v1].erase(v2); graph[v2].erase(v1); while (actions_time.size() > 0 && actions_time.back() >= num_edges) { comp_dsu.pop(); actions_time.pop_back(); } } bool get_ans() { return broken_since == -1; } }; std::vector<std::pair<int32_t, int32_t> >* segtree; void add_edge(int32_t node, int32_t left, int32_t right, int32_t query_left, int32_t query_right, std::pair<int32_t, int32_t> edge) { if (left >= query_right || right <= query_left) return; if (left >= query_left && right <= query_right) { segtree[node].push_back(edge); return; } int32_t m = (left + right) / 2; add_edge(node * 2 + 1, left, m, query_left, query_right, edge); add_edge(node * 2 + 2, m, right, query_left, query_right, edge); } void get_ans(int32_t node, int32_t left, int32_t right, Tracker& tracker) { for (int32_t i = 0; i < segtree[node].size(); i++) tracker.add_edge(segtree[node][i].first, segtree[node][i].second); if (right - left == 1) { std::cout << (tracker.get_ans() ? YES : NO ) << n ; for (int32_t i = 0; i < segtree[node].size(); i++) tracker.pop_edge(segtree[node][i].first, segtree[node][i].second); return; } int32_t m = (left + right) / 2; get_ans(node * 2 + 1, left, m, tracker); get_ans(node * 2 + 2, m, right, tracker); for (int32_t i = 0; i < segtree[node].size(); i++) tracker.pop_edge(segtree[node][i].first, segtree[node][i].second); } int main() { int32_t n, num_queries; std::cin >> n >> num_queries; segtree = new std::vector<std::pair<int32_t, int32_t> >[4 * num_queries]; std::map<std::pair<int32_t, int32_t>, int32_t> segments; for (int32_t q = 0; q < num_queries; q++) { int32_t v1, v2; std::cin >> v1 >> v2; v1--; v2--; if (v1 > v2) { int32_t tmp = v1; v1 = v2; v2 = tmp; } auto it = segments.find({v1, v2}); if (it == segments.end()) segments[{v1, v2}] = q; else { add_edge(0, 0, num_queries, it->second, q, {v1, v2}); segments.erase(it); } } for (auto it = segments.begin(); it != segments.end(); it++) add_edge(0, 0, num_queries, it->second, num_queries, it->first); Tracker tracker(n); get_ans(0, 0, num_queries, tracker); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> tab[100100], ans; int n, ls[10]; bool used[100100]; bool chek(int a, int b) { for (int i = 0; i < 4; i++) if (tab[a][i] == b) return true; return false; } int main() { scanf( %d , &n); for (int i = 0; i < n + n; i++) { int a, b; scanf( %d%d , &a, &b); if (a == b) { puts( -1 ); return 0; } tab[a].push_back(b); tab[b].push_back(a); } for (int i = 1; i <= n; i++) { if (tab[i].size() != 4) { puts( -1 ); return 0; } } if (n <= 10) { int ar[30] = {}; for (int i = 0; i < n; i++) ar[i] = i + 1; do { ar[n] = ar[0]; ar[n + 1] = ar[1]; bool ok = true; for (int i = 0; i < n; i++) { if (!chek(ar[i], ar[i + 1]) || !chek(ar[i], ar[i + 2])) { ok = false; break; } } if (ok) { for (int i = 0; i < n; i++) printf( %d%c , ar[i], i == n - 1 ? n : ); return 0; } } while (std::next_permutation(ar, ar + n)); puts( -1 ); return 0; } int start = 1, pre = -1; while (!used[start]) { used[start] = true; ans.push_back(start); int nxt = start; for (int i = 0; i < 4; i++) { int cnt = 0; for (int j = 0; j < 4; j++) if (chek(tab[start][i], tab[start][j])) cnt++; if (cnt == 2 && tab[start][i] != pre) { nxt = tab[start][i]; break; } } if (nxt == start) { puts( -1 ); return 0; } pre = start; start = nxt; } if ((int)ans.size() < n) { puts( -1 ); return 0; } ans.push_back(ans[0]); ans.push_back(ans[1]); for (int i = 0; i < n; i++) { if (!chek(ans[i], ans[i + 1]) || !chek(ans[i], ans[i + 2])) { puts( -1 ); return 0; } } for (int i = 0; i < n; i++) printf( %d%c , ans[i], i == n - 1 ? n : ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; const long long mod = 1e9 + 7; long long powr(long long a, long long b) { long long x = 1 % mod; a %= mod; while (b) { if (b & 1) x = (x * a) % mod; a = (a * a) % mod; b >>= 1; } return x; } long long inv(long long a) { return powr(a, mod - 2); } map<int, int> mymap, mymap2; int par[maxn]; int val[maxn]; int main() { int n; cin >> n; int x; map<int, int>::iterator it1, it2; int mx = 0, mn = 1e9 + 10; int maxi = 1, mini = 1; for (int i = 1; i <= n; i++) { cin >> x; if (i == 1) mx = mn = x; val[i] = x; if (i > 1) { if (x > mx) { par[i] = maxi; maxi = i; mx = x; } else if (x < mn) { par[i] = mini; mini = i; mn = x; } else { it2 = mymap.upper_bound(x); int x = it2->second; it2--; int y = it2->second; par[i] = max(x, y); } cout << val[par[i]] << ; } mymap[x] = i; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; template <class T> void dispvector(vector<T> v) { for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << n ; } template <class T> void disparray(T *v, int n) { for (int i = 0; i < n; i++) cout << v[i] << ; cout << n ; } template <class T> int sizeofarr(T *v) { return sizeof(v) / sizeof(T); } signed main(int argc, char **argv) { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; if (n % 2 == 0) { cout << NO << n ; return 0; } else { cout << YES << n ; vector<long long int> arr(2 * n); long long int num = 1; long long int idx1 = 0; long long int idx2 = n; bool ok = true; for (long long int i = 0; i < n; i++) { if (ok) { arr[idx1] = num; arr[idx2] = num + 1; } else { arr[idx1] = num + 1; arr[idx2] = num; } num += 2; idx1++; idx2++; if (ok) ok = false; else ok = true; } dispvector(arr); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2510; int sum[maxn][maxn]; char s[maxn][maxn]; int n, m, K; long long ans; int p1[10], p2[10]; int cal(int x1, int y1, int x2, int y2) { return sum[x2][y2] - sum[x1 - 1][y2] - sum[x2][y1 - 1] + sum[x1 - 1][y1 - 1]; } void div(int x1, int y1, int x2, int y2, bool flag) { if (x1 > x2 || y1 > y2) return; if (x1 == x2 && y1 == y2) { ans += (cal(x1, y1, x2, y2) == K); return; } if (flag) { int mid = (x1 + x2) >> 1; div(x1, y1, mid, y2, !flag); div(mid + 1, y1, x2, y2, !flag); for (int i = y1; i <= y2; i++) { for (int k = 0; k <= K; k++) { p1[k] = mid, p2[k] = mid + 1; } for (int j = y2; j >= i; j--) { for (int k = 0; k <= K; k++) { while (p1[k] >= x1 && cal(p1[k], i, mid, j) <= k) p1[k]--; while (p2[k] <= x2 && cal(mid + 1, i, p2[k], j) <= k) p2[k]++; } for (int k = 1; k < K; k++) { ans += (p1[k - 1] - p1[k]) * (p2[K - k] - p2[K - k - 1]); } if (K > 0) { ans += (mid - p1[0]) * (p2[K] - p2[K - 1]); ans += (p2[0] - mid - 1) * (p1[K - 1] - p1[K]); } else if (K == 0) { ans += (mid - p1[0]) * (p2[0] - mid - 1); } } } } else { int mid = (y1 + y2) >> 1; div(x1, y1, x2, mid, !flag); div(x1, mid + 1, x2, y2, !flag); for (int i = x1; i <= x2; i++) { for (int k = 0; k <= K; k++) { p1[k] = mid, p2[k] = mid + 1; } for (int j = x2; j >= i; j--) { for (int k = 0; k <= K; k++) { while (p1[k] >= y1 && cal(i, p1[k], j, mid) <= k) p1[k]--; while (p2[k] <= y2 && cal(i, mid + 1, j, p2[k]) <= k) p2[k]++; } for (int k = 1; k < K; k++) { ans += (p1[k - 1] - p1[k]) * (p2[K - k] - p2[K - k - 1]); } if (K > 0) { ans += (mid - p1[0]) * (p2[K] - p2[K - 1]); ans += (p2[0] - mid - 1) * (p1[K - 1] - p1[K]); } else if (K == 0) { ans += (mid - p1[0]) * (p2[0] - mid - 1); } } } } } int main() { scanf( %d%d%d , &n, &m, &K); for (int i = 1; i <= n; i++) { scanf( %s , s[i] + 1); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1] + (s[i][j] == 1 ); } div(1, 1, n, m, 0); printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; ifstream in; ofstream out; const long long kk = 1000; const long long MOD = 10e9 + 7; long long a, b, x, y; long long GCD(long long n, unsigned long long m) { while (n != 0 && m != 0) { if (n > m) { n %= m; } else { m %= n; } } return (n + m); } int main() { ios_base::sync_with_stdio(0); cin >> a >> b >> x >> y; long long x1, y1; long long k = GCD(x, y); x /= k; y /= k; cout << min(a / x, b / y); return 0; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : cabac_neighbour_2p_17x128.v
// Author : guo yong
// Created : 2013-07
// Description : cabac memory for top macroblock
//
//-------------------------------------------------------------------
module cabac_neighbour_1p_MB_X_TOTAL(
//input
clk ,
r_en ,
r_addr ,
w_en ,
w_addr ,
w_data ,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable signal
input [6:0] r_addr ; //read address of memory
input w_en ; //write enable signal
input [6:0] w_addr ; //write address of memory
input [11:0] w_data ; //write data of memory, {mb_type_top, chroma_mode_top, cbp_top} = {4, 4, 9}
output [11:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(7), .Word_Width(12))
rf_2p_cabac_neigh_12x128 (
.clka ( clk ),
.cena_i ( ~r_en ),
.addra_i ( r_addr ),
.dataa_o ( r_data ),
.clkb ( clk ),
.cenb_i ( ~w_en ),
.wenb_i ( ~w_en ),
.addrb_i ( w_addr ),
.datab_i ( w_data )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, N = 2e5 + 5; inline int read() { int sum = 0, f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -f; c = getchar(); } while (c >= 0 && c <= 9 ) sum = sum * 10 + c - 48, c = getchar(); return sum * f; } int n, d, x[N], minn = INF; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> d; for (int i = 1; i <= n; i++) cin >> x[i]; for (int i = 1; i <= 100; i++) { int j = i + d, cnt = 0; for (int k = 1; k <= n; k++) { if (x[k] < i || x[k] > j) cnt++; } minn = min(minn, cnt); ; } cout << minn << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const long long oo = 1e9 + 7; const int mod = 1e9 + 7; double x, y, tmp; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> x >> y; tmp = log(x) / log(y); if (tmp * y * 1.00 < x) cout << < ; else if (tmp * y * 1.00 > x) cout << > ; else cout << = ; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.