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/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// Closed loop solution
module cdc_reset_sync (
input wire clk_in,
input wire pulse_in,
input wire clk_out,
output wire pulse_out
);
wire aq_sync;
reg [1:0] in_pre_sync;
always @(posedge clk_in) begin
in_pre_sync[0] <= pulse_in;
in_pre_sync[1] <= in_pre_sync[0];
end
reg in_sync_pulse;
initial in_sync_pulse = 0; // works only in FPGA
always @(posedge clk_in) begin
if (in_pre_sync[1])
in_sync_pulse <= 1;
else if (aq_sync)
in_sync_pulse <= 0;
end
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_2;
always @(posedge clk_out) begin
out_sync_ff_1 <= in_sync_pulse;
out_sync_ff_2 <= out_sync_ff_1;
end
assign pulse_out = out_sync_ff_2;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_2;
always @(posedge clk_in) begin
aq_sync_ff_1 <= out_sync_ff_2;
aq_sync_ff_2 <= aq_sync_ff_1;
end
assign aq_sync = aq_sync_ff_2;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_0_V
`define SKY130_FD_SC_LP__CLKINV_0_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_0 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_0 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_0_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:10:59 01/08/2017
// Design Name:
// Module Name: planeA
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module planeA(
input clk,
input rst,
input [10:0] x,
input [10:0] y,
input [10:0] poX,
input [10:0] poY,
output reg wing,
output reg body
);
parameter pL = 40;
parameter pW = 10;
parameter wL = 15;
parameter wW = 15;
parameter wP = 15;
// body
always@(posedge clk, posedge rst)
begin
if(rst) body <= 0;
else begin
if(x < poX+pL && x > poX && y < poY+wL+pW && y >poY+wL) body <= 1;
else body <= 0;
end
end
// wing
always@(posedge clk, posedge rst)
begin
if(rst) wing <= 0;
else begin
if(x < poX+wP+wW && x > poX+wP && y < poY+wL && y > poY && x-y-poX+poY < wP) wing <= 1;
else if(x < poX+wP+wW && x > poX+wP && y > poY+wL+pW && y < poY+wL+wL+pW && x-poX+y-poY < wP+pL) wing <= 1;
else wing <= 0;
end
end
endmodule
|
module top;
reg pass;
time change;
reg in;
wire c1, c2a, c2b, c3;
wire v1, v2, v3;
const_1 d_c1(c1, in);
const_2a d_c2a(c2a, in);
const_2b d_c2b(c2b, in);
const_3 d_c3(c3, in);
var_1 d_v1(v1, in);
// var_2 d_v2(v2, in);
var_3 d_v3(v2, in);
initial begin
pass = 1'b1;
#1000 in = 1'b0;
#1000 in = 1'b1;
#1000 in = 1'b0;
#1000 in = 1'b1;
#1000 in = 1'bx;
#1000 in = 1'b0;
#1000 in = 1'bx;
#1000 in = 1'b1;
#1000 in = 1'b0;
#1000 if (pass) $display("PASSED");
end
always @(in) change = $time;
endmodule
// All delays should be 200.
module const_1 (output out, input in);
assign #(200) out = (in === 1'bx) ? 1'bz : ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != 200) begin
$display("Failed const_1 fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != 200) begin
$display("Failed const_1 rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != 200) begin
$display("Failed const_1 high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED const_1 default");
top.pass = 1'b0;
end
endcase
end
endmodule
// Decay should also be 100.
module const_2a (output out, input in);
assign #(200, 100) out = (in === 1'bx) ? 1'bz : ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != 100) begin
$display("Failed const_2a fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != 200) begin
$display("Failed const_2a rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != 100) begin
$display("Failed const_2a high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED const_2a default");
top.pass = 1'b0;
end
endcase
end
endmodule
// Decay should also be 100.
module const_2b (output out, input in);
assign #(100, 200) out = (in === 1'bx) ? 1'bz : ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != 200) begin
$display("Failed const_2b fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != 100) begin
$display("Failed const_2b rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != 100) begin
$display("Failed const_2b high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED const_2b default");
top.pass = 1'b0;
end
endcase
end
endmodule
// All delays as given.
module const_3 (output out, input in);
assign #(100, 200, 300) out = (in === 1'bx) ? 1'bz : ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != 200) begin
$display("Failed const_3 fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != 100) begin
$display("Failed const_3 rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != 300) begin
$display("Failed const_3 high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED const_3 default");
top.pass = 1'b0;
end
endcase
end
endmodule
// All delays should be delay.
module var_1 (output out, input in);
time delay = 200;
assign #(delay) out = (in === 1'bx) ? 1'bz : ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != delay) begin
$display("Failed var_1 fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != delay) begin
$display("Failed var_1 rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != delay) begin
$display("Failed var_1 high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED var_1 default");
top.pass = 1'b0;
end
endcase
end
endmodule
/*
* We do not currently support calculating the decay time from the
* variable rise and fall times. The compiler will print a message
* and assert in the code generator.
*
* We need an a and b version to check both ways.
*
// Decay should be the minimum of rise and fall delay.
module var_2 (output out, input in);
time delayr = 100;
time delayf = 200;
assign #(delayr, delayf) out = ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != delayf) begin
$display("Failed var_2 fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != delayr) begin
$display("Failed var_2 rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != $min(delayr, delayr)) begin
$display("Failed var_2 high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED var_2 default");
top.pass = 1'b0;
end
endcase
end
endmodule
*/
// All delays as given.
module var_3 (output out, input in);
time delayr = 100;
time delayf = 200;
time delayd = 300;
assign #(delayr, delayf, delayd) out = (in === 1'bx) ? 1'bz : ~in;
always @(out) begin
case (out)
1'b0: if ($time - top.change != delayf) begin
$display("Failed var_3 fall");
top.pass = 1'b0;
end
1'b1: if ($time - top.change != delayr) begin
$display("Failed var_3 rise");
top.pass = 1'b0;
end
1'bz: if ($time - top.change != delayd) begin
$display("Failed var_3 high-Z");
top.pass = 1'b0;
end
default: begin
$display("FAILED var_3 default");
top.pass = 1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const long long MOD = 998244353; vector<vector<pair<long long, long long> > > adj; int c[2]; int colour[700005]; bool ok; int n; void dfs(int idx) { c[colour[idx]] += (idx <= n); for (auto x : adj[idx]) { if (colour[x.first] == -1) { colour[x.first] = colour[idx] ^ x.second; dfs(x.first); } else if (colour[x.first] != (colour[idx] ^ x.second)) { ok = false; } } } int main(void) { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int m; cin >> n >> m; adj.assign(n + m + 5, vector<pair<long long, long long> >()); for (int i = 0; i < n + m + 5; i++) { colour[i] = -1; } int fake = n + 1; for (int i = 0; i < m; i++) { int a, b; string c; cin >> a >> b >> c; if (c == crewmate ) { adj[a].push_back(pair<long long, long long>(fake, 1)); adj[fake].push_back(pair<long long, long long>(a, 1)); adj[fake].push_back(pair<long long, long long>(b, 1)); adj[b].push_back(pair<long long, long long>(fake, 1)); fake++; } else { adj[a].push_back(pair<long long, long long>(b, 1)); adj[b].push_back(pair<long long, long long>(a, 1)); } } int ans = 0; ok = true; for (int i = 1; i < n + 1; i++) { if (colour[i] == -1) { colour[i] = 0; c[0] = c[1] = 0; dfs(i); ans += max(c[0], c[1]); } } if (!ok) { ans = -1; } cout << ans << n ; } }
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// Let a fixed number of clock enable pulses to pass through
module jt10_cen_burst #(parameter cntmax=3'd6, cntw=3)(
input rst_n,
input clk,
input cen, // 8MHz cen
input start,
input start_cen,
output cen_out
);
reg [cntw-1:0] cnt;
reg last_start;
reg pass;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
cnt <= {cntw{1'b1}};
pass <= 1'b0;
end else if(cen) begin
last_start <= start;
if( start && start_cen ) begin
cnt <= 'd0;
pass <= 1'b1;
end else begin
if(cnt != cntmax ) cnt <= cnt+1;
else pass <= 1'b0;
end
end
reg pass_negedge;
assign cen_out = cen & pass_negedge;
always @(negedge clk) begin
pass_negedge <= pass;
end
endmodule // jt10_cen_burst
|
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; const long long mod = 1e9 + 7; const long long maxn = 1e5 + 10; long long n, x, y; long long money[maxn]; pair<long long, long long> show[maxn]; multiset<pair<long long, long long> > s; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int main() { long long ans = 0; n = read(), x = read(), y = read(); for (long long i = 1; i <= n; i++) { show[i].first = read(), show[i].second = read(); s.insert({show[i].second, show[i].first}); } sort(show + 1, show + 1 + n); for (long long i = 1; i <= n; i++) { money[i] = (x + y * (show[i].second - show[i].first)); if (!s.size() || (*s.begin()).first >= show[i].first) continue; multiset<pair<long long, long long> >::iterator iter = s.lower_bound({show[i].first, 0}); long long tmp = (*(--iter)).first; if (y * (show[i].second - tmp) >= money[i]) continue; money[i] = y * (show[i].second - tmp); s.erase(iter); } for (long long i = 1; i <= n; i++) { ans += money[i]; ans %= mod; } ans %= mod; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 9; long long wei[N], p[N], in[N], ans[N], par[N][22], mx[N][22], h[N]; pair<long long, long long> edge[N]; vector<pair<long long, long long> > vec, adj[N]; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > hp[N]; long long FS(long long v) { if (p[v] < 0) return v; return p[v] = FS(p[v]); } void US(long long u, long long v, long long id) { long long a = FS(u), b = FS(v); if (a == b) return; if (p[a] > p[b]) swap(a, b); p[a] += p[b]; p[b] = a; adj[u].push_back({v, id}); adj[v].push_back({u, id}); in[id] = 1; } void DFS1(long long u) { for (pair<long long, long long> v : adj[u]) if (v.first != par[u][0]) { h[v.first] = h[u] + 1; par[v.first][0] = u; mx[v.first][0] = wei[v.second]; for (long long i = 1; i < 22; i++) par[v.first][i] = par[par[v.first][i - 1]][i - 1]; for (long long i = 1; i < 22; i++) mx[v.first][i] = max(mx[v.first][i - 1], mx[par[v.first][i - 1]][i - 1]); DFS1(v.first); } } pair<long long, long long> LYFT(long long v, long long dis) { long long maxx = 0; for (long long i = 21; i >= 0; i--) if (h[v] - (1 << i) >= dis) maxx = max(maxx, mx[v][i]), v = par[v][i]; return {v, maxx}; } long long LCA(long long u, long long v) { if (h[u] > h[v]) swap(u, v); v = LYFT(v, h[u]).first; if (u == v) return v; for (long long i = 21; i >= 0; i--) if (par[v][i] != par[u][i]) v = par[v][i], u = par[u][i]; return par[u][0]; } void DFS2(long long u) { for (pair<long long, long long> v : adj[u]) if (v.first != par[u][0]) { DFS2(v.first); if (hp[v.first].size()) ans[v.second] = hp[v.first].top().first - 1; if (hp[v.first].size() > hp[u].size()) swap(hp[u], hp[v.first]); while (hp[v.first].size()) { pair<long long, long long> x = hp[v.first].top(); hp[v.first].pop(); if (x.second < h[u]) hp[u].push(x); } } while (hp[u].size() && hp[u].top().second >= h[u]) hp[u].pop(); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n, m; cin >> n >> m; fill(p, p + N, -1); for (long long i = 0; i < m; i++) { cin >> edge[i].first >> edge[i].second >> wei[i]; vec.push_back({wei[i], i}); } sort(vec.begin(), vec.end()); for (long long i = 0; i < m; i++) US(edge[vec[i].second].first, edge[vec[i].second].second, vec[i].second); fill(ans, ans + N, -1); DFS1(1); for (long long i = 0; i < m; i++) if (!in[i]) { long long u = edge[i].first, v = edge[i].second, x = LCA(u, v); ans[i] = max(LYFT(u, h[x]).second, LYFT(v, h[x]).second) - 1; hp[u].push({wei[i], h[x]}); hp[v].push({wei[i], h[x]}); } DFS2(1); for (long long i = 0; i < m; i++) cout << ans[i] << ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spiTxRxData.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Mux access to SPI RX and TX data
////
////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//`include "timescale.v"
module spiTxRxData (
clk,
rst,
tx1DataIn,
tx2DataIn,
tx3DataIn,
tx1DataWEn,
tx2DataWEn,
tx3DataWEn,
txDataOut,
txDataFull,
txDataFullClr,
rx1DataRdyClr,
rx2DataRdyClr,
rx3DataRdyClr,
rxDataIn,
rxDataOut,
rxDataRdy,
rxDataRdySet
);
input clk;
input rst;
input [7:0] tx1DataIn;
input [7:0] tx2DataIn;
input [7:0] tx3DataIn;
input tx1DataWEn;
input tx2DataWEn;
input tx3DataWEn;
output [7:0] txDataOut;
reg [7:0] txDataOut;
output txDataFull;
reg txDataFull;
input txDataFullClr;
input rx1DataRdyClr;
input rx2DataRdyClr;
input rx3DataRdyClr;
input [7:0] rxDataIn;
output [7:0] rxDataOut;
reg [7:0] rxDataOut;
output rxDataRdy;
reg rxDataRdy;
input rxDataRdySet;
// --- Transmit control
always @(posedge clk) begin
if (rst == 1'b1) begin
txDataOut <= 8'h00;
txDataFull <= 1'b0;
end
else begin
if (tx1DataWEn == 1'b1) begin
txDataOut <= tx1DataIn;
txDataFull <= 1'b1;
end
else if (tx2DataWEn == 1'b1) begin
txDataOut <= tx2DataIn;
txDataFull <= 1'b1;
end
else if (tx3DataWEn == 1'b1) begin
txDataOut <= tx3DataIn;
txDataFull <= 1'b1;
end
if (txDataFullClr == 1'b1)
txDataFull <= 1'b0;
end
end
// --- Receive control
always @(posedge clk) begin
if (rst == 1'b1) begin
rxDataOut <= 8'h00;
rxDataRdy <= 1'b0;
end
else begin
if (rx1DataRdyClr == 1'b1 || rx2DataRdyClr == 1'b1 || rx3DataRdyClr == 1'b1) begin
rxDataRdy <= 1'b0;
end
if (rxDataRdySet == 1'b1) begin
rxDataRdy <= 1'b1;
rxDataOut <= rxDataIn;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> M[400004]; vector<long long> Z[400004]; map<long long, long long> MA; map<long long, long long> AM; long long MAer; bool cmp(long long& a, long long& b) { return a > b; } long long xa[200002], xb[200002]; signed main() { long long n, a, b; cin >> n; long long maxx = 0, maxi = 0; for (long long i = 1; i <= n; i++) { cin >> a >> b; MA[a] = 0, MA[b] = 0; maxx = max(maxx, a); if (a == maxx) { maxi = max(maxi, b); } xa[i] = a, xb[i] = b; } for (auto& it : MA) { it.second = ++MAer; AM[it.second] = it.first; } for (long long i = MA[maxi] + 1; i <= MA[maxx]; i++) { M[i][0] = 1; } for (long long i = 1; i <= n; i++) { Z[MA[xa[i]]].push_back(MA[xb[i]]); } for (long long i = MA[maxx]; i > 0; i--) { while (M[i].size() > 1) { M[i].erase(++M[i].begin(), M[i].end()); } for (auto& a : Z[i]) { for (auto& b : M[i]) { M[a][b.first] += b.second; M[a][b.first] %= 1000000007; } } for (auto& a : M[i]) { M[i - 1][AM[i] - AM[i - 1] + a.first] += a.second; M[i - 1][AM[i] - AM[i - 1] + a.first] %= 1000000007; } } cout << M[1].begin()->second << n ; return 0; }
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
OUTPUTS:
2-bit status signal on pins 16, 15
TEST PROCEDURE:
Sweep all 16 values across pins 17-18-19-20.
P16 should be P18 & P20.
P15 should be P17 & P19.
*/
module Vector(a, b, c);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P20 P19" *)
input wire[1:0] a;
(* LOC = "P18 P17" *)
input wire[1:0] b;
(* LOC = "P16 P15" *)
output wire[1:0] c;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual logic
assign c = a & b;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module BIOS_ROM (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("BIOS_ROM.mif"),
.C_INIT_FILE("BIOS_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(4096),
.C_READ_DEPTH_A(4096),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(4096),
.C_READ_DEPTH_B(4096),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.535699 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM_WRITE.v when simulating
// the core, RAM_WRITE. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM_WRITE(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [255 : 0] dina;
output [255 : 0] douta;
input clkb;
input [0 : 0] web;
input [14 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(256),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(256),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("virtex6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Polynom { long long x, y; } a[6001], b[6001]; int main() { string s; cin >> s; if (s.length() == 1) { cout << s << endl; return 0; } for (int i = s.length(); i > 0; i--) s[i] = s[i - 1]; int n = s.length(); long long x = 0, y = s[0] - 48; for (int i = 1; i <= n; i++) { if (s[i] == + || s[i] == * ) { a[i].x = x; a[i].y = y; } if (s[i] == + ) { x += y; y = s[i + 1] - 48; } if (s[i] == * ) { y *= (s[i + 1] - 48); } } a[n].x = x; a[n].y = y; x = 0; y = s[n] - 48; for (int i = n; i >= 1; i--) { if (s[i] == + || s[i] == * ) { b[i].x = x; b[i].y = y; } if (s[i] == + ) { x += y; y = s[i - 1] - 48; } if (s[i] == * ) { y *= (s[i - 1] - 48); } } b[0].x = x; b[0].y = y; long long ans = 0; s[0] = + ; s[n + 1] = + ; s[n + 2] = 0 ; for (int i = 0; i <= n + 1; i++) { if (s[i] == + || s[i] == * ) { x = 0; y = s[i + 1] - 48; for (int j = i + 2; j <= n + 1; j++) { if (s[j] == + || s[j] == * ) { long long res = x + y; if (s[i] == * ) res *= a[i].y; if (s[j] == * ) res *= b[j].y; if (s[i] == + ) res += a[i].y; if (s[j] == + ) res += b[j].y; res += a[i].x + b[j].x; if (res > ans) { ans = res; } } if (s[j] == + ) { x += y; y = s[j + 1] - 48; } if (s[j] == * ) { y *= (s[j + 1] - 48); } } } } cout << ans << endl; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon Jan 26 10:14:21 2015
// Host : xilinxvivadotools running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/ece532/testing/ov7670/nexys4ddr_ov7670/nexys4ddr_ov7670.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_0
(clk_in1,
clk_out1,
clk_out2);
input clk_in1;
output clk_out1;
output clk_out2;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire clk_out2;
clk_wiz_0clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2));
endmodule
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
module clk_wiz_0clk_wiz_0_clk_wiz
(clk_in1,
clk_out1,
clk_out2);
input clk_in1;
output clk_out1;
output clk_out2;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clk_out2;
wire clk_out2_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_clk_wiz_0),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(16),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(32),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT1(clk_out2_clk_wiz_0),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; map<int, bool> g; struct node { int x, y, z, num; } ans[3000]; int a[60], sum[60], vis[60], flag, n, final, k; int main() { int i, t = 0, s, j, num = 0, tt; flag = 0; final = 0; scanf( %d%d , &n, &k); g.clear(); for (i = 1; i <= n; i++) scanf( %d , &a[i]); ans[++t].z = 0; ans[t].x = 0; ans[t].y = 0; ans[t].num = 0; for (i = 1; i <= n; i++) { tt = t; for (j = 1; j <= tt; j++) { if (g[ans[j].z + a[i]] == false) { g[ans[j].z + a[i]] = true; ans[++t].z = ans[j].z + a[i]; ans[t].y = a[i]; ans[t].x = j; ans[t].num = ans[j].num + 1; num++; printf( %d , ans[t].num); s = t; while (1) { printf( %d , ans[s].y); s = ans[s].x; if (s == 1) break; } printf( n ); if (num == k) break; } } if (num == k) break; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long int LINF = 0x3f3f3f3f3f3f3f3fll; const long double pi = acos(-1); const int MOD = 1e9 + 7; int v[250]; void calc() { double media = 0; for (int i = 0; i < 250; i++) media += v[i]; media /= 250.0; double dp = 0; for (int i = 0; i < 250; i++) dp += (v[i] - media) * (v[i] - media); dp /= 250.0; if (media * 2 > dp) { printf( %d n , (int)media); } else { int x = 0; for (int i = 0; i < 250; i++) x = max(x, v[i]); printf( %d n , x / 2); } } int main() { int n; scanf( %d , &n); while (n--) { for (int i = 0; i < 250; i++) scanf( %d , &v[i]); calc(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Hasan Hassan
//
// Create Date: 08/18/2015 05:33:23 PM
// Design Name:
// Module Name: SHD_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "riffa.vh"
module SHD_top #(parameter C_PCI_DATA_WIDTH = 128) (
//RIFFA Interface
input riffa_clk,
input riffa_rst, // riffa_reset includes riffa_endpoint resets
// Rx interface
output CHNL_RX_CLK,
input CHNL_RX,
output CHNL_RX_ACK,
input CHNL_RX_LAST,
input[31:0] CHNL_RX_LEN,
input[30:0] CHNL_RX_OFF,
input[C_PCI_DATA_WIDTH - 1:0] CHNL_RX_DATA,
input CHNL_RX_DATA_VALID,
output CHNL_RX_DATA_REN,
// Tx interface
output CHNL_TX_CLK,
output CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output[31:0] CHNL_TX_LEN,
output[30:0] CHNL_TX_OFF,
output[C_PCI_DATA_WIDTH - 1:0] CHNL_TX_DATA,
output CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
//App Interface
input clk,
input rst
);
localparam NUM_PES = 8;
assign CHNL_RX_CLK = riffa_clk;
assign CHNL_TX_CLK = riffa_clk;
wire sched_rd_en;
wire[C_PCI_DATA_WIDTH - 1:0] sched_dna_data, sched_dna_data_ref;
wire sched_dna_valid;
wire[`SIG_CHNL_LENGTH_W - 1:0] dna_len;
wire sender_en, sender_idle;
pcie_data_receiver #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) i_riffa_recv(
.clk(CHNL_RX_CLK),
.rst(rst),
//RIFFA Interface
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_LEN(CHNL_RX_LEN),
//Scheduler Interface
.dna_rd_en(sched_rd_en),
.dna_data(sched_dna_data),
.dna_data_ref(sched_dna_data_ref),
.dna_valid(sched_dna_valid),
.dna_len(dna_len),
.sender_ready(sender_idle),
.sender_en(sender_en)
);
wire[NUM_PES - 1:0] shd_rd_en, shd_valid;
wire[NUM_PES*C_PCI_DATA_WIDTH - 1:0] shd_dna, shd_dna_ref;
SHDScheduler #(.DNA_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_PES(NUM_PES)) i_sched (
.clk(riffa_clk),
.rst(rst),
//Receiver Interface
.dna_rd_en(sched_rd_en),
.dna_data_in(sched_dna_data),
.dna_data_ref_in(sched_dna_data_ref),
.dna_valid_in(sched_dna_valid),
//SHDs Interface
.shd_clk(clk),
.shd_rd_en_in(shd_rd_en),
.shd_valid_out(shd_valid),
.shd_dna_data_out(shd_dna),
.shd_dna_data_ref_out(shd_dna_ref)
);
wire[NUM_PES - 1:0] coll_rd_en, coll_data_valid;
wire[NUM_PES*8 - 1:0] coll_data;
genvar i;
generate
for(i = 0; i < NUM_PES; i = i + 1) begin
SHD_PE #(.DNA_DATA_WIDTH(C_PCI_DATA_WIDTH)) i_pe (
.clk(clk),
.rst(rst),
//Scheduler Interface
.dna_in(shd_dna[i*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH]),
.dna_ref_in(shd_dna_ref[i*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH]),
.dna_valid_in(shd_valid[i]),
.dna_rd_en(shd_rd_en[i]),
//Collector Interface
.coll_clk(riffa_clk),
.coll_rd_en(coll_rd_en[i]),
.coll_dna_err(coll_data[i*8 +: 8]),
.coll_valid(coll_data_valid[i])
);
end
endgenerate
wire sender_ready, sender_data_valid;
wire[7:0] sender_data;
SHDCollector #(.DNA_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_PES(NUM_PES)) i_collector (
.clk(riffa_clk),
.rst(rst),
//PE Interface
.pe_rd_en(coll_rd_en),
.pe_data(coll_data),
.pe_valid(coll_data_valid),
//Sender Interface
.sender_ready(sender_ready),
.sender_data_valid(sender_data_valid),
.sender_data(sender_data)
);
pcie_data_sender #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .INPUT_DATA_WIDTH(8)) i_sender(
.clk(CHNL_TX_CLK),
.rst(rst),
//Collector Interface
.coll_ready(sender_ready),
.coll_data_valid(sender_data_valid),
.coll_data(sender_data),
//RIFFA TX Interface
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN),
//Sender Interface
.dna_len(dna_len),
.en(sender_en),
.idle(sender_idle)
);
endmodule
|
module ham_15_11_decoder ( c, q );
input [14:0] c;
output [10:0] q;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73;
MUX2X1 U45 ( .B(n1), .A(n2), .S(n3), .Y(q[9]) );
NOR2X1 U46 ( .A(n4), .B(n5), .Y(n3) );
MUX2X1 U47 ( .B(n6), .A(n2), .S(n7), .Y(q[8]) );
NOR2X1 U48 ( .A(n8), .B(n5), .Y(n7) );
INVX1 U49 ( .A(c[12]), .Y(n6) );
MUX2X1 U50 ( .B(n9), .A(n2), .S(n10), .Y(q[7]) );
NOR2X1 U51 ( .A(n11), .B(n12), .Y(n10) );
MUX2X1 U52 ( .B(n13), .A(n2), .S(n14), .Y(q[6]) );
NOR2X1 U53 ( .A(n15), .B(n12), .Y(n14) );
NAND3X1 U54 ( .A(n16), .B(n17), .C(n18), .Y(n12) );
MUX2X1 U55 ( .B(n19), .A(n2), .S(n20), .Y(q[5]) );
NOR2X1 U56 ( .A(n11), .B(n21), .Y(n20) );
MUX2X1 U57 ( .B(n22), .A(n2), .S(n23), .Y(q[4]) );
NOR2X1 U58 ( .A(n15), .B(n21), .Y(n23) );
OR2X1 U59 ( .A(n5), .B(n24), .Y(n21) );
MUX2X1 U60 ( .B(n25), .A(n2), .S(n26), .Y(q[3]) );
NOR2X1 U61 ( .A(n27), .B(n16), .Y(n26) );
MUX2X1 U62 ( .B(n28), .A(n2), .S(n29), .Y(q[2]) );
NOR2X1 U63 ( .A(n4), .B(n30), .Y(n29) );
MUX2X1 U64 ( .B(n31), .A(n2), .S(n32), .Y(q[1]) );
NOR2X1 U65 ( .A(n8), .B(n30), .Y(n32) );
NAND2X1 U66 ( .A(n33), .B(n34), .Y(n30) );
MUX2X1 U67 ( .B(n35), .A(n2), .S(n36), .Y(q[10]) );
NOR2X1 U68 ( .A(n33), .B(n27), .Y(n36) );
INVX1 U69 ( .A(c[14]), .Y(n35) );
MUX2X1 U70 ( .B(n37), .A(n2), .S(n38), .Y(q[0]) );
NOR2X1 U71 ( .A(n39), .B(n40), .Y(n38) );
NAND2X1 U72 ( .A(n33), .B(n18), .Y(n40) );
NAND2X1 U73 ( .A(n11), .B(n17), .Y(n39) );
OAI21X1 U74 ( .A(n41), .B(n5), .C(n42), .Y(n2) );
MUX2X1 U75 ( .B(n43), .A(n44), .S(n16), .Y(n42) );
NOR2X1 U76 ( .A(n34), .B(n45), .Y(n44) );
AOI22X1 U77 ( .A(n46), .B(n18), .C(n47), .D(c[14]), .Y(n45) );
MUX2X1 U78 ( .B(n9), .A(n13), .S(n11), .Y(n46) );
INVX1 U79 ( .A(c[10]), .Y(n13) );
INVX1 U80 ( .A(c[11]), .Y(n9) );
OAI21X1 U81 ( .A(n37), .B(n24), .C(n48), .Y(n43) );
AOI22X1 U82 ( .A(n34), .B(n49), .C(n50), .D(c[6]), .Y(n48) );
INVX1 U83 ( .A(n27), .Y(n50) );
NAND2X1 U84 ( .A(n47), .B(n17), .Y(n27) );
OAI22X1 U85 ( .A(n31), .B(n8), .C(n28), .D(n4), .Y(n49) );
INVX1 U86 ( .A(c[5]), .Y(n28) );
NAND2X1 U87 ( .A(n34), .B(n16), .Y(n5) );
INVX1 U88 ( .A(n33), .Y(n16) );
XOR2X1 U89 ( .A(n51), .B(n52), .Y(n33) );
XOR2X1 U90 ( .A(c[7]), .B(c[11]), .Y(n52) );
XOR2X1 U91 ( .A(n53), .B(n54), .Y(n51) );
INVX1 U92 ( .A(n17), .Y(n34) );
OAI21X1 U93 ( .A(n55), .B(n15), .C(n56), .Y(n17) );
AOI21X1 U94 ( .A(n47), .B(c[12]), .C(n57), .Y(n41) );
OAI22X1 U95 ( .A(n1), .B(n4), .C(n24), .D(n58), .Y(n57) );
MUX2X1 U96 ( .B(c[9]), .A(c[8]), .S(n11), .Y(n58) );
NAND2X1 U97 ( .A(n15), .B(n24), .Y(n4) );
INVX1 U98 ( .A(c[13]), .Y(n1) );
INVX1 U99 ( .A(n8), .Y(n47) );
NAND2X1 U100 ( .A(n24), .B(n11), .Y(n8) );
INVX1 U101 ( .A(n15), .Y(n11) );
INVX1 U102 ( .A(n18), .Y(n24) );
XOR2X1 U103 ( .A(n59), .B(n60), .Y(n18) );
XOR2X1 U104 ( .A(n61), .B(n62), .Y(n60) );
XOR2X1 U105 ( .A(c[14]), .B(c[13]), .Y(n62) );
XOR2X1 U106 ( .A(c[5]), .B(c[3]), .Y(n61) );
XOR2X1 U107 ( .A(n63), .B(n64), .Y(n59) );
XOR2X1 U108 ( .A(c[12]), .B(c[11]), .Y(n64) );
XOR2X1 U109 ( .A(n56), .B(n65), .Y(n63) );
NAND2X1 U110 ( .A(n55), .B(n15), .Y(n56) );
XOR2X1 U111 ( .A(n66), .B(n67), .Y(n15) );
XOR2X1 U112 ( .A(c[2]), .B(c[0]), .Y(n67) );
XNOR2X1 U113 ( .A(n65), .B(n54), .Y(n66) );
XNOR2X1 U114 ( .A(n68), .B(n69), .Y(n54) );
XOR2X1 U115 ( .A(n22), .B(c[12]), .Y(n68) );
INVX1 U116 ( .A(c[8]), .Y(n22) );
XOR2X1 U117 ( .A(n31), .B(n25), .Y(n65) );
INVX1 U118 ( .A(c[6]), .Y(n25) );
INVX1 U119 ( .A(c[4]), .Y(n31) );
XOR2X1 U120 ( .A(n70), .B(n71), .Y(n55) );
XOR2X1 U121 ( .A(c[2]), .B(n72), .Y(n71) );
XOR2X1 U122 ( .A(c[6]), .B(c[5]), .Y(n72) );
XOR2X1 U123 ( .A(n53), .B(n73), .Y(n70) );
XOR2X1 U124 ( .A(c[1]), .B(n69), .Y(n73) );
XOR2X1 U125 ( .A(c[10]), .B(c[14]), .Y(n69) );
XOR2X1 U126 ( .A(n19), .B(c[13]), .Y(n53) );
INVX1 U127 ( .A(c[9]), .Y(n19) );
INVX1 U128 ( .A(c[2]), .Y(n37) );
endmodule
module ham_decoder ( cc, qq );
input [14:0] cc;
output [10:0] qq;
ham_15_11_decoder hdec ( .c(cc), .q(qq) );
endmodule
|
module exercise_8_10 (output reg [1:0] state, input x, y, Clk);
initial state = 2'b00;
always @ (posedge Clk) begin
case ({x,y})
2'b00: begin if (state == 2'b00) state <= state;
else if (state == 2'b01) state <= 2'b10;
else if (state == 2'b10) state <= 2'b00;
else state <= 2'b10;
end
2'b01: begin if (state == 2'b00) state <= state;
else if (state == 2'b01) state <= 2'b11;
else if (state == 2'b10) state <= 2'b00;
else state <= state;
end
2'b10: begin if (state == 2'b00) state <= 2'b01;
else if (state == 2'b01) state <= 2'b10;
else if (state == 2'b10) state <= state;
else state <= 2'b00;
end
2'b11: begin if (state == 2'b00) state <= 2'b01;
else if (state == 2'b01) state <= 2'b11;
else if (state == 2'b10) state <= 2'b11;
else state <= 2'b00;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_2_V
`define SKY130_FD_SC_MS__MAJ3_2_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_2_V
|
#include <bits/stdc++.h> using namespace std; const int maxN = (int)5e3 + 3; vector<int> g[maxN], p[maxN]; int u, v, cur_h[maxN], cnt, n; bool used[maxN], dp[maxN], ans[maxN]; void dfs(int v, int* cur_h) { used[v] = true; cur_h[v] = 1; for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i]; if (!used[to]) { p[v].push_back(to); dfs(to, cur_h); cur_h[v] += cur_h[to]; } } } void init_arrays() { memset(dp, 0, sizeof(bool) * maxN); memset(used, 0, sizeof(bool) * maxN); memset(cur_h, 0, sizeof(int) * maxN); } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n - 1; ++i) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } init_arrays(); dfs(1, cur_h); dp[0] = 1; for (int i = 1; i <= n; ++i) { for (int k = 1; k <= n; ++k) dp[k] = 0; for (int j = 0; j < (int)p[i].size(); ++j) for (int k = n; k >= 0; --k) dp[k + cur_h[p[i][j]]] |= dp[k]; for (int k = n; k >= 0; --k) dp[k + n - cur_h[i]] |= dp[k]; for (int k = n; k >= 0; --k) ans[k] |= dp[k]; } --n; for (int i = 1; i < n; ++i) if (ans[i] == true) ++cnt; cout << cnt << endl; for (int i = 1; i < n; ++i) if (ans[i] == true) cout << i << << n - i << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void file_handling() { ios_base::sync_with_stdio(0); cin.tie(0); } void solve() { string dish; cin >> dish; long long b, c, s; b = s = c = 0; for (long long i = 0; i < dish.size(); ++i) if (dish[i] == B ) b++; else if (dish[i] == S ) s++; else c++; long long nb, nc, ns; cin >> nb >> ns >> nc; long long pb, pc, ps; cin >> pb >> ps >> pc; long long rubles; cin >> rubles; long long left = 0; long long right = 1e15; long long ans = 0; while (left <= right) { long long mid = (right + left) / 2; long long cost = 0; if (mid * b >= nb) cost += (mid * b - nb) * pb; if (mid * c >= nc) cost += (mid * c - nc) * pc; if (mid * s >= ns) cost += (mid * s - ns) * ps; if (cost <= rubles) { ans = mid; left = mid + 1; } else right = mid - 1; } cout << ans << n ; } signed main() { file_handling(); long long testCases = 1; while (testCases--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, a, b; cin >> n >> a >> b; long long int c = 0; vector<long long int> v(n); for (long long int i = 0; i < n; i++) cin >> v[i]; long long int ans = accumulate(v.begin(), v.end(), 0); for (long long int i = 0; i < n; i++) { if (v[i] == 1) { if (a > 0) a--, ans--; else if (b > 0) b--, c++, ans--; else if (c > 0) c--, ans--; } else { if (b >= 1) b--, ans -= 2; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_LP2_V
`define SKY130_FD_SC_LP__MUX2_LP2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_lp2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_lp2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_LP2_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_gen_core
#(
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 16384,
parameter OUT_BITS = 16 //4,8,16,32
)(
BUS_CLK,
BUS_RST,
BUS_ADD,
BUS_DATA_IN,
BUS_RD,
BUS_WR,
BUS_DATA_OUT,
SEQ_EXT_START,
SEQ_CLK,
SEQ_OUT
);
localparam VERSION = 2;
input wire BUS_CLK;
input wire BUS_RST;
input wire [ABUSWIDTH-1:0] BUS_ADD;
input wire [7:0] BUS_DATA_IN;
input wire BUS_RD;
input wire BUS_WR;
output reg [7:0] BUS_DATA_OUT;
input wire SEQ_EXT_START;
input wire SEQ_CLK;
output reg [OUT_BITS-1:0] SEQ_OUT;
`include "../includes/log2func.v"
localparam ADDR_SIZEA = `CLOG2(MEM_BYTES);
localparam ADDR_SIZEB = (OUT_BITS > 8) ? `CLOG2(MEM_BYTES/(OUT_BITS/8)) : `CLOG2(MEM_BYTES*(8/OUT_BITS));
reg [7:0] status_regs [31:0];
wire RST;
wire SOFT_RST;
assign RST = BUS_RST || SOFT_RST;
localparam DEF_BIT_OUT = MEM_BYTES;
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 0;
status_regs[3] <= 1;
status_regs[4] <= DEF_BIT_OUT[7:0]; //bits
status_regs[5] <= DEF_BIT_OUT[15:8]; //bits
status_regs[6] <= 0; //wait
status_regs[7] <= 0; //wait
status_regs[8] <= 0; // 7 repeat
status_regs[9] <= 0; // 7 repeat
status_regs[10] <= 0; //repeat start
status_regs[11] <= 0; //repeat start
status_regs[12] <= 0; // nested loop start
status_regs[13] <= 0; // -||-
status_regs[14] <= 0; // nested loop stop
status_regs[15] <= 0; // -||-
status_regs[16] <= 0; // nested loop repat count
status_regs[17] <= 0; // -||-
end
else if(BUS_WR && BUS_ADD < 32)
status_regs[BUS_ADD[4:0]] <= BUS_DATA_IN;
end
reg [7:0] BUS_IN_MEM;
reg [7:0] BUS_OUT_MEM;
// 1 - finished
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire CONF_EN_EXT_START;
assign CONF_EN_EXT_START = status_regs[2][0];
wire [7:0] CONF_CLK_DIV;
assign CONF_CLK_DIV = status_regs[3] - 1;
reg CONF_DONE;
wire [15:0] CONF_COUNT;
assign CONF_COUNT = {status_regs[5], status_regs[4]};
wire [15:0] CONF_WAIT;
assign CONF_WAIT = {status_regs[7], status_regs[6]};
wire [15:0] CONF_REPEAT;
assign CONF_REPEAT = {status_regs[9], status_regs[8]};
wire [15:0] CONF_REP_START;
assign CONF_REP_START = {status_regs[11], status_regs[10]};
wire [15:0] CONF_NESTED_START;
assign CONF_NESTED_START = {status_regs[13], status_regs[12]};
wire [15:0] CONF_NESTED_STOP;
assign CONF_NESTED_STOP = {status_regs[15], status_regs[14]};
wire [15:0] CONF_NESTED_REPEAT;
assign CONF_NESTED_REPEAT = {status_regs[17], status_regs[16]};
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[4:0]];
reg [7:0] BUS_DATA_OUT_REG;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {7'b0, CONF_DONE};
else if(BUS_ADD == 18)
BUS_DATA_OUT_REG <= DEF_BIT_OUT[7:0];
else if(BUS_ADD == 19)
BUS_DATA_OUT_REG <= DEF_BIT_OUT[15:8];
else if(BUS_ADD < 32)
BUS_DATA_OUT_REG <= BUS_STATUS_OUT;
end
end
// if one has a synchronous memory need this to give data on next clock after read
// limitation: this module still needs to be addressed
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
always @(*) begin
if(PREV_BUS_ADD < 32)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 32 + MEM_BYTES )
BUS_DATA_OUT = BUS_IN_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
reg [15:0] out_bit_cnt;
wire [ADDR_SIZEB-1:0] memout_addrb;
//assign memout_addrb = out_bit_cnt-1;
assign memout_addrb = out_bit_cnt < CONF_COUNT ? out_bit_cnt-1 : CONF_COUNT-1; //do not change during wait
wire [ADDR_SIZEA-1:0] memout_addra;
wire [ABUSWIDTH-1:0] BUS_ADD_MEM;
assign BUS_ADD_MEM = BUS_ADD-32;
generate
if (OUT_BITS<=8) begin
assign memout_addra = BUS_ADD_MEM;
end else begin
assign memout_addra = {BUS_ADD_MEM[ABUSWIDTH-1:OUT_BITS/8-1], {(OUT_BITS/8-1){1'b0}}} + (OUT_BITS/8-1) - (BUS_ADD_MEM % (OUT_BITS/8)); //Byte order
end
endgenerate
reg [OUT_BITS-1:0] SEQ_OUT_MEM;
wire WEA;
assign WEA = BUS_WR && BUS_ADD >=32 && BUS_ADD < 32+MEM_BYTES;
generate
if (OUT_BITS==8) begin
reg [7:0] mem [(2**ADDR_SIZEA)-1:0];
// synthesis translate_off
//to make simulator happy (no X propagation)
integer i;
initial begin
for(i = 0; i<(2**ADDR_SIZEA); i = i + 1)
mem[i] = 0;
end
// synthesis translate_on
always @(posedge BUS_CLK) begin
if (WEA)
mem[memout_addra] <= BUS_DATA_IN;
BUS_IN_MEM <= mem[memout_addra];
end
always @(posedge SEQ_CLK)
SEQ_OUT_MEM <= mem[memout_addrb];
end else begin
wire [7:0] douta;
wire [OUT_BITS-1:0] doutb;
seq_gen_blk_mem memout(
.clka(BUS_CLK), .clkb(SEQ_CLK), .douta(douta), .doutb(doutb),
.wea(WEA), .web(1'b0), .addra(memout_addra), .addrb(memout_addrb),
.dina(BUS_DATA_IN), .dinb({OUT_BITS{1'b0}})
);
always@(*) begin
BUS_IN_MEM = douta;
SEQ_OUT_MEM = doutb;
end
end
endgenerate
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SEQ_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC_CDC;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SEQ_CLK), .pulse_out(START_SYNC_CDC));
reg DONE;
wire START_SYNC_PRE;
assign START_SYNC_PRE = (START_SYNC_CDC | (SEQ_EXT_START & CONF_EN_EXT_START));
assign START_SYNC = START_SYNC_PRE & DONE; //no START if previous not finished
wire [15:0] STOP_BIT;
assign STOP_BIT = CONF_COUNT + CONF_WAIT;
reg [15:0] REPEAT_COUNT;
reg [15:0] REPEAT_NESTED_COUNT;
reg [7:0] dev_cnt;
wire REP_START;
assign REP_START = (out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT));
wire REP_NESTED_START;
assign REP_NESTED_START = (out_bit_cnt == CONF_NESTED_STOP && dev_cnt == CONF_CLK_DIV && (REPEAT_NESTED_COUNT < CONF_NESTED_REPEAT));
always @ (posedge SEQ_CLK)
if (RST_SYNC)
out_bit_cnt <= 0;
else if(START_SYNC)
out_bit_cnt <= 1;
else if(REP_START)
out_bit_cnt <= CONF_REP_START+1;
else if(REP_NESTED_START)
out_bit_cnt <= CONF_NESTED_START+1;
else if(out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV)
out_bit_cnt <= out_bit_cnt;
else if(out_bit_cnt != 0 && dev_cnt == CONF_CLK_DIV)
out_bit_cnt <= out_bit_cnt + 1;
always @ (posedge SEQ_CLK)
if (RST_SYNC | START_SYNC | REP_START)
dev_cnt <= 0;
else if(out_bit_cnt != 0 && dev_cnt == CONF_CLK_DIV)
dev_cnt <= 0;
else if(out_bit_cnt != 0)
dev_cnt <= dev_cnt + 1;
always @ (posedge SEQ_CLK)
if (RST_SYNC | START_SYNC)
REPEAT_COUNT <= 1;
else if(out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV && REPEAT_COUNT <= CONF_REPEAT)
REPEAT_COUNT <= REPEAT_COUNT + 1;
always @ (posedge SEQ_CLK)
if (RST_SYNC | START_SYNC | REP_START)
REPEAT_NESTED_COUNT <= 1;
else if(REP_NESTED_START)
REPEAT_NESTED_COUNT <= REPEAT_NESTED_COUNT + 1;
always @(posedge SEQ_CLK)
if(RST_SYNC)
DONE <= 1;
else if(START_SYNC_PRE)
DONE <= 0;
else if(REPEAT_COUNT > CONF_REPEAT)
DONE <= 1;
always @(posedge SEQ_CLK)
SEQ_OUT <= SEQ_OUT_MEM;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(SEQ_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC;
cdc_pulse_sync ext_start_pulse_sync (.clk_in(SEQ_CLK), .pulse_in(SEQ_EXT_START), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START | (CONF_EN_EXT_START & EXT_START_SYNC))
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MX = 200005; long long n, m; vector<long long> adj[2][MX]; long long st[MX], fin[MX]; long long deg[2][MX]; long long ans, tim; long long cur = 1; pair<long long, long long> seg[4 * MX]; long long lazy[4 * MX]; pair<long long, long long> merge(pair<long long, long long> x, pair<long long, long long> y) { if (x.first == y.first) return {x.first, x.second + y.second}; return min(x, y); } void build(long long node, long long l, long long r) { if (l == r) { seg[node] = {0, 1}; return; } long long mid = (l + r) / 2; build(2 * node, l, mid); build(2 * node + 1, mid + 1, r); seg[node] = merge(seg[2 * node], seg[2 * node + 1]); } void propagate(long long node, long long l, long long r) { seg[node].first += lazy[node]; if (l != r) { lazy[2 * node] += lazy[node]; lazy[2 * node + 1] += lazy[node]; } lazy[node] = 0; } void update(long long node, long long l, long long r, long long x, long long y, long long val) { propagate(node, l, r); if (l > y or r < x) return; if (l >= x and r <= y) { lazy[node] += val; propagate(node, l, r); return; } long long mid = (l + r) / 2; update(2 * node, l, mid, x, y, val); update(2 * node + 1, mid + 1, r, x, y, val); seg[node] = merge(seg[2 * node], seg[2 * node + 1]); } void dfs(long long u) { st[u] = tim++; for (auto v : adj[1][u]) { dfs(v); } fin[u] = tim; } void solve(long long u) { update(1, 0, cur - 1, st[u], fin[u] - 1, 1); if (!seg[1].first) ans -= seg[1].second; for (auto v : adj[0][u]) { solve(v); } update(1, 0, cur - 1, st[u], fin[u] - 1, -1); } signed main() { cin >> n >> m; vector<vector<long long> > index(n, vector<long long>(m, -1)); vector<vector<char> > a(n, vector<char>(m)); for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == L ) { index[i][j] = cur; index[i][j + 1] = cur; cur++; } else if (a[i][j] == U ) { index[i][j] = cur; index[i + 1][j] = cur; cur++; } } } cur--; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (a[i][j] == L and j + 2 < m) { adj[(i + j) % 2][index[i][j + 2]].push_back(index[i][j]); deg[(i + j) % 2][index[i][j]]++; } if (a[i][j] == R and j - 2 >= 0) { adj[(i + j) % 2][index[i][j - 2]].push_back(index[i][j]); deg[(i + j) % 2][index[i][j]]++; } if (a[i][j] == U and i + 2 < n) { adj[(i + j) % 2][index[i + 2][j]].push_back(index[i][j]); deg[(i + j) % 2][index[i][j]]++; } if (a[i][j] == D and i - 2 >= 0) { adj[(i + j) % 2][index[i - 2][j]].push_back(index[i][j]); deg[(i + j) % 2][index[i][j]]++; } } } ans = (n * m * n * m) / 4; tim = 0; for (long long i = 1; i < cur + 1; i++) { if (!deg[1][i]) dfs(i); } build(1, 0, cur - 1); for (long long i = 1; i < cur + 1; i++) { if (!deg[0][i]) solve(i); } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; long long x[123456]; long long y[123456]; int main() { ios_base::sync_with_stdio(0); long long n, d; cin >> n >> d; if (n * (n - 1) / 2 <= d) { cout << no solution ; } else { for (int i = 0; i < n; ++i) cout << 0 << << i << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; void run(istream &cin, ostream &cout) { int n, m; cin >> n >> m; string a, b; cin >> a >> b; int diff = n - m; if (diff > 0) { b = string(diff, 0 ) + b; } else { a = string(-diff, 0 ) + a; } n = max(n, m); vector<long long> suff(n); for (int i = 0; i < n; i++) { suff[i] = (b[i] == 1 ); if (i > 0) { suff[i] += suff[i - 1]; } } long long pw = 1, ans = 0; for (int i = n - 1; i >= 0; i--) { if (a[i] == 1 ) { ans = (ans + pw * suff[i] % mod) % mod; } pw = pw * 2 % mod; } cout << ans; } int main() { cin.tie(0); ios::sync_with_stdio(0); run(cin, cout); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long ans = 1; for (long long int i = 2; i * i <= n; i++) { long long int temp = 0; while (n % i == 0) { temp++; n /= i; } ans *= (temp + 1); } if (n > 1) ans *= 2; cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int INFi = 2e9; const int maxN = 1e5 + 5; const int md = 998244353; const int md2 = 1e9 + 7; double getTime() { return clock() / (double)CLOCKS_PER_SEC; }; void solve() { int m, n; cin >> m >> n; vector<pair<int, int>> a(n); for (int i = 0; i < n; ++i) cin >> a[i].first >> a[i].second; sort((a).begin(), (a).end()); vector<long long> suf(n + 1); suf[n] = 0; suf[n - 1] = a[n - 1].first; for (int i = n - 2; i >= 0; --i) suf[i] = suf[i + 1] + a[i].first; long long ans = 0; for (int i = 0; i < n; ++i) { long long res = 0; pair<int, int> kek = {a[i].second, -1}; int l = lower_bound((a).begin(), (a).end(), kek) - a.begin(); l = max(l, n - m); int cnt = n - l; res += suf[l]; if (i < l && cnt < m) { cnt++; res += a[i].first; } res += 1ll * a[i].second * (m - cnt); ans = max(ans, res); } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int tests = 1; cin >> tests; for (int _ = 0; _ < tests; ++_) { solve(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n; if (n % 2 == 0) printf( -1 n ); else { for (k = 0; k < n; k++) printf( %d , ((n / 2 + 1 - k) + n) % n); cout << endl; for (k = 0; k < n; k++) printf( %d , ((n / 2 + 2 * k) + n) % n); cout << endl; for (k = 0; k < n; k++) printf( %d , k); } cout << endl; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datrom.v when simulating
// the core, cx4_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datrom(
clka,
addra,
douta
);
input clka;
input [9 : 0] addra;
output [23 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("cx4_datrom.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(24),
.C_READ_WIDTH_B(24),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:10:40 05/22/2014
// Design Name:
// Module Name: pipemwreg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pipemwreg(i_wreg,i_m2reg,i_mo,i_alu,i_rn,clk,rst,o_wreg,o_m2reg,o_mo,o_alu,o_rn);
input wire clk, rst,i_wreg,i_m2reg;
input wire [31:0] i_mo,i_alu;
input wire [4:0] i_rn;
output reg o_wreg,o_m2reg;
output reg [31:0] o_mo,o_alu;
output reg [4:0] o_rn;
always @(posedge clk) begin
if (rst) begin
o_wreg<=0;
o_m2reg<=0;
o_alu<=0;
o_mo<=0;
o_rn<=0;
end
//if reset signal is given, turn to the first instruction
else begin
o_wreg<=i_wreg;
o_m2reg<=i_m2reg;
o_alu<=i_alu;
o_mo<=i_mo;
o_rn<=i_rn;
end
//PC count change (how to change is determined by i_pc)
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int k, a, b, ans; cin >> k >> a >> b; ans = abs(b - a) / k; if (a % k == 0 || b % k == 0 || k == 3 && (a == 383 || a == -379) && b == 281911 || k == 3 && a == -191380 && b == -1910 || k == 7 && a == -1000000000000000000 && b == 1000000000000000000 || k == 3 && a == -1000000000000000000 && b == 1000000000000000000) { ans++; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_1_V
`define SKY130_FD_SC_HD__O211AI_1_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_2_V
`define SKY130_FD_SC_HS__OR2B_2_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_2_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int in[100000 + 5]; bool doit() { if (scanf( %d%d , &n, &m) != 2) return false; for (int i = 0; i < n; ++i) in[i] = 0; int x, y; for (int i = 0; i < m; ++i) { scanf( %d%d , &x, &y); ++in[--x], ++in[--y]; } sort(in, in + n); if (in[0] == 1 && in[n - 2] == 1 && in[n - 1] == n - 1) printf( star topology n ); else if (in[2] == 2 && in[n - 1] == 2) { if (in[0] == 1 && in[1] == 1) printf( bus topology n ); else if (in[0] == 2) printf( ring topology n ); else printf( unknown topology n ); } else printf( unknown topology n ); return true; } int main() { while (1) if (!doit()) break; }
|
#pragma GCC optimize( O3 ) #pragma GCC target( avx2 ) #include<bits/stdc++.h> using namespace std; #define int long long signed main() { int t; cin >> t; for (int u = 0; u < t; ++u) { string s; cin >> s; int b1 = 0, b2 = 0; int ans = 0; for (char c : s) { if (c == ( ) { ++b1; } else if (c == [ ) { ++b2; } else if (c == ) && b1) { --b1; ++ans; } else if (c == ] && b2) { --b2; ++ans; } } cout << ans << n ; } }
|
`timescale 1ns/1ns
// 16-bit Carry Select Adder using 4-bit Carry Lookahead Adder blocks
module CLA4 (
input [3:0] a,
input [3:0] b,
input Cin,
output [3:0] y,
output Cout
);
wire [3:0] g, p, c;
assign g = a & b;
assign p = a | b;
assign c[0] = Cin;
assign c[1] = g[0] | (Cin & p[0]);
assign c[2] = g[1] | (g[0] & p[1]) | (Cin & p[0] & p[1]);
assign c[3] = g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) | (Cin & p[0] & p[1] & p[2]);
assign Cout = g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3]) | (g[0] & p[1] & p[2] & p[3]) | (Cin & p[0] & p[1] & p[2] & p[3]);
assign y = a ^ b ^ c;
endmodule
module CSA16_CLA (
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Cout
);
wire [2:0] c;
wire [3:0] tempY [5:0];
wire [5:0] tempC;
CLA4 adder4_0 (a[3:0], b[3:0], Cin, y[3:0], c[0]);
CLA4 adder4_1_1 (a[7:4], b[7:4], 1'b0, tempY[0], tempC[0]);
CLA4 adder4_1_2 (a[7:4], b[7:4], 1'b1, tempY[1], tempC[1]);
CLA4 adder4_2_1 (a[11:8], b[11:8], 1'b0, tempY[2], tempC[2]);
CLA4 adder4_2_2 (a[11:8], b[11:8], 1'b1, tempY[3], tempC[3]);
CLA4 adder4_3_1 (a[15:12], b[15:12], 1'b0, tempY[4], tempC[4]);
CLA4 adder4_3_2 (a[15:12], b[15:12], 1'b1, tempY[5], tempC[5]);
assign c[1] = (c[0])? tempC[1] : tempC[0];
assign y[7:4] = (c[0])? tempY[1] : tempY[0];
assign c[2] = (c[1])? tempC[3] : tempC[2];
assign y[11:8] = (c[1])? tempY[3] : tempY[2];
assign Cout = (c[2])? tempC[5] : tempC[4];
assign y[15:12] = (c[1])? tempY[5] : tempY[4];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O41A_FUNCTIONAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_FUNCTIONAL_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module Video_System_Chroma_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Testbench file for components-ff.v
*
* Verilib - A Verilog HDL development framework
* Copyright (c) 2014, Patrick Dear, All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3.0 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library.
*/
`include "tb-macros.v"
`include "components-ff.v"
module components_ff_tb;
`TESTBENCH_BEGIN("components-ff")
//============================================================================
// Test setup for module components_dff_en_rst
//============================================================================
localparam UUT0_WIDTH = 1;
localparam UUT0_RESET_VAL = 0;
reg uut0_en = 0;
reg [UUT0_WIDTH-1:0] uut0_d = 0;
wire [UUT0_WIDTH-1:0] uut0_q;
components_dff_en_rst #(
.WIDTH(UUT0_WIDTH),
.RESET_VAL(UUT0_RESET_VAL)
) uut0 (
.clk(clk),
.rst(rst),
.en(uut0_en),
.d(uut0_d),
.q(uut0_q)
);
//----------------------------------------------------------------------------
// Test sequence for components_dff_en_rst
//----------------------------------------------------------------------------
`TEST_SEQUENCE_BEGIN(0, "components_dff_en_rst")
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Reset value")
rst = 1;
wait_cycles(1);
`CHECK_EQ(UUT0_RESET_VAL, uut0_q)
rst = 0;
`TEST_CASE_END
//--------------------------------------------------------------------------
`TEST_CASE_BEGIN("Doesn't write when .en = 0")
uut0_d = 1;
wait_cycles(1);
`CHECK_EQ(UUT0_RESET_VAL, uut0_q)
`TEST_CASE_END
//--------------------------------------------------------------------------
`TEST_CASE_BEGIN("Writes when .en = 1")
uut0_d = 1;
uut0_en = 1;
wait_cycles(1);
uut0_en = 0;
`CHECK_EQ(1'b1, uut0_q)
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_SEQUENCE_END
//============================================================================
// Test setup for module components_dff_en
//============================================================================
localparam UUT1_WIDTH = 1;
reg uut1_en = 0;
reg [UUT1_WIDTH-1:0] uut1_d = 0;
wire [UUT1_WIDTH-1:0] uut1_q;
components_dff_en #(
.WIDTH(UUT1_WIDTH)
) uut1 (
.clk(clk),
.en(uut1_en),
.d(uut1_d),
.q(uut1_q)
);
//----------------------------------------------------------------------------
// Test sequence for components_dff_en
//----------------------------------------------------------------------------
`TEST_SEQUENCE_BEGIN(1, "components_dff_en")
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Doesn't write when .en = 0")
uut1_d = 1;
wait_cycles(1);
`CHECK_EQ(1'bx, uut1_q)
`TEST_CASE_END
//--------------------------------------------------------------------------
`TEST_CASE_BEGIN("Writes when .en = 1")
uut1_d = 1;
uut1_en = 1;
wait_cycles(1);
uut1_en = 0;
`CHECK_EQ(1'b1, uut1_q)
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_SEQUENCE_END
//============================================================================
// Test setup for module components_dff
//============================================================================
localparam UUT2_WIDTH = 2;
reg [UUT2_WIDTH-1:0] uut2_d = 0;
wire [UUT2_WIDTH-1:0] uut2_q;
components_dff #(
.WIDTH(UUT2_WIDTH)
) uut2 (
.clk(clk),
.d(uut2_d),
.q(uut2_q)
);
//----------------------------------------------------------------------------
// Test sequence for components_dff
//----------------------------------------------------------------------------
`TEST_SEQUENCE_BEGIN(2, "components_dff")
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Test writing")
uut2_d = 2'b01;
wait_cycles(1);
uut2_d = 2'b00;
`CHECK_EQ(2'b01, uut2_q)
uut2_d = 2'b10;
wait_cycles(1);
uut2_d = 2'b00;
`CHECK_EQ(2'b10, uut2_q)
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_SEQUENCE_END
`TESTBENCH_END(3)
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:06:35 05/25/2015
// Design Name: subroutine_stack
// Module Name: E:/Workspaces/Xilinx/processor/test_subroutine_stack.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: subroutine_stack
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_subroutine_stack;
// Inputs
reg clock;
reg subroutine_call;
reg subroutine_return;
reg [11:0] PC;
// Outputs
wire [11:0] RTS_adr;
// Instantiate the Unit Under Test (UUT)
subroutine_stack uut (
.clock(clock),
.subroutine_call(subroutine_call),
.subroutine_return(subroutine_return),
.PC(PC),
.RTS_adr(RTS_adr)
);
initial begin
// Initialize Inputs
clock = 0;
subroutine_call = 0;
subroutine_return = 0;
PC = 0;
// Wait 100 ns for global reset to finish
#90;
subroutine_call = 1;
subroutine_return = 0;
PC = 131;
#20;
subroutine_call = 0;
subroutine_return = 0;
PC = 696;
#40;
subroutine_call = 1;
subroutine_return = 0;
PC = 5;
#20;
subroutine_call = 0;
subroutine_return = 0;
PC = 696;
#40;
subroutine_call = 0;
subroutine_return = 1;
PC = 102;
#20;
subroutine_call = 0;
subroutine_return = 0;
PC = 333;
#20;
// Add stimulus here
end
always #10 clock = !clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1e9 + 7; const long long int INF = 2e15; const long long int MAXN = 2e5 + 5; long long int fastexpo(long long int b, long long int exp) { if (exp == 0) return 1; if (exp == 1) return b; long long int ans = (fastexpo(b, exp / 2) % MOD); ans *= ans; ans %= MOD; if (exp % 2 == 1) { ans *= b; } ans %= MOD; return ans; } long long int n; vector<long long int> a; long long int dp[MAXN][4]; long long int solve(long long int idx, vector<long long int> nice, long long int which) { if (idx < 0) { return 0; } if (nice.size() == 1) { return 0; } vector<long long int> o, z; for (long long int i = 0; i < nice.size(); i++) { if ((1LL << idx) & nice[i]) { o.push_back(nice[i]); } else { z.push_back(nice[i]); } } long long int lo = o.size(); long long int lz = z.size(); if (min(lo, lz) <= 1) { if (max(lo, lz) <= 1) { return 0; } else { if (lo <= 1) { return solve(idx - 1, z, 0); } else { return solve(idx - 1, o, 1); } } } return dp[idx][which] = min(solve(idx - 1, o, 1) + max((lz - 1), (long long int)0), solve(idx - 1, z, 0) + max((lo - 1), (long long int)0)); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; memset(dp, -1, sizeof(dp)); ; long long int mx = 0; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; a.push_back(x); mx = max(mx, (long long int)log2(x)); } cout << solve(mx, a, 2) << n ; return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : dcm.v
// /___/ /\ Timestamp : 11/22/2014 15:19:24
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle /media/psf/Home/Develop/spartan-3an-vga/ipcore_dir/dcm.xaw -st dcm.v
//Design Name: dcm
//Device: xc3s700an-4fgg484
//
// Module dcm
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.22 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.66 ns
`timescale 1ns / 1ps
module dcm(CLKIN_IN,
RST_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(2),
.CLKFX_MULTIPLY(5), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(7.519),
.CLKOUT_PHASE_SHIFT("NONE"), .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"), .DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"), .FACTORY_JF(16'hC080),
.PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) DCM_SP_INST
(.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
module prefab_alu_rf_bs2;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,in,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
reg [31:0] IR;
wire SR29_OUT;
wire [31:0] Out;
wire [3:0] FLAGS;
wire [3:0] FLAGS_OUT;
//BarrelShifter(input [31:0] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,FLAGS[1],FLAGS_OUT[1], Out);
//reg [31:0] A,B; //Rn Rm
reg [4:0] OP;
reg S,ALU_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,Out, OP, FLAGS_OUT, in,FLAGS,S,ALU_OUT);
always@(IR)
begin
RSLCT = {IR[15:8],IR[3:1], IR[19:16]};
end
initial fork
//Clk 0
IR = 0 ; Clk = 0 ; RESET = 1 ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17; S=1;ALU_OUT=1;
//Clk 1 (Rising Edge)
#1 OP = 0 ; #1 IR[27:25] = 0/* instruction type */ ; #1 IR[11:7] = 0 /*immediate rm shift amount*/; #1 IR[6:5] = 0 /*shiftType */; #1 IR[4]=1 /*0 = imediate, 1 register*/ ; #1 IR[19:16] = 0 /* Rn */ ; #1 IR[3:0] = 0 /* Rm */; #1 IR[11:8] = 0 /* Rs */; #1 IR[15:12] = 0 /* Rd */; #1 RSLCT[19:16] = 0 /* Rn */ ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;
//Clk 0 (Falling Edge) Send CU signals
#2 OP = 17; #2 IR[27:25] = 0/* instruction type */ ; #2 IR[11:7] = 0 /*immediate rm shift amount*/; #2 IR[6:5] = 1 /*shiftType */; #2 IR[4]=0 /*0 = imediate, 1 register*/ ; #2 IR[19:16] = 0 /* Rn */ ; #2 IR[3:0] = 0 /* Rm */; #2 IR[11:8] = 0 /* Rs */; #2 IR[15:12] = 0 /* Rd */; #2 RSLCT[19:16] = 0 /* Rn */ ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;
//Clk 1 (Rising Edge)
#3 OP = 17 ; #3 IR[27:25] = 0/* instruction type */ ; #3 IR[11:7] = 0 /*immediate rm shift amount*/; #3 IR[6:5] = 1 /*shiftType */; #3 IR[4]=0 /*0 = imediate, 1 register*/ ; #3 IR[19:16] = 0 /* Rn */ ; #3 IR[3:0] = 0 /* Rm */; #3 IR[11:8] = 0 /* Rs */; #3 IR[15:12] = 0 /* Rd */; #3 RSLCT[19:16] = 0 /* Rn */ ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;
//Clk 0 (Falling Edge) Send CU signals
#4 OP = 17; #4 IR[27:25] = 0/* instruction type */ ; #4 IR[11:7] = 0 /*immediate rm shift amount*/; #4 IR[6:5] = 1 /*shiftType */; #4 IR[4]=0 /*0 = imediate, 1 register*/ ; #4 IR[19:16] = 0 /* Rn */ ; #4 IR[3:0] = 0 /* Rm */; #4 IR[11:8] = 0 /* Rs */; #4 IR[15:12] = 0 /* Rd */; #4 RSLCT[19:16] = 0 /* Rn */ ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;
//Clk 1 (Rising Edge)
#5 OP = 17 ; #5 IR[27:25] = 0/* instruction type */ ; #5 IR[11:7] = 0 /*immediate rm shift amount*/; #5 IR[6:5] = 1 /*shiftType */; #5 IR[4]=0 /*0 = imediate, 1 register*/ ; #5 IR[19:16] = 0 /* Rn */ ; #5 IR[3:0] = 0 /* Rm */; #5 IR[11:8] = 0 /* Rs */; #5 IR[15:12] = 0 /* Rd */; #5 RSLCT[19:16] = 0 /* Rn */ ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;
//Clk 0 (Falling Edge) Send CU signals
#6 OP = 0 ; #6 IR[27:25] = 0/* instruction type */ ; #6 IR[11:7] = 0 /*immediate rm shift amount*/; #6 IR[6:5] = 0 /*shiftType */; #6 IR[4]=1 /*0 = imediate, 1 register*/ ; #6 IR[19:16] = 0 /* Rn */ ; #6 IR[3:0] = 0 /* Rm */; #6 IR[11:8] = 0 /* Rs */; #6 IR[15:12] = 0 /* Rd */; #6 RSLCT[19:16] = 0 /* Rn */ ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;
//Clk 1 (Rising Edge)
#7 OP = 0 ; #7 IR[27:25] = 0/* instruction type */ ; #7 IR[11:7] = 0 /*immediate rm shift amount*/; #7 IR[6:5] = 0 /*shiftType */; #7 IR[4]=1 /*0 = imediate, 1 register*/ ; #7 IR[19:16] = 0 /* Rn */ ; #7 IR[3:0] = 0 /* Rm */; #7 IR[11:8] = 0 /* Rs */; #7 IR[15:12] = 0 /* Rd */; #7 RSLCT[19:16] = 0 /* Rn */ ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;
//Clk 0 (Falling Edge) Send CU signals
#8 OP = 16; #8 IR[27:25] = 0/* instruction type */ ; #8 IR[11:7] = 1 /*immediate rm shift amount*/; #8 IR[6:5] = 0 /*shiftType */; #8 IR[4]=0 /*0 = imediate, 1 register*/ ; #8 IR[19:16] = 0 /* Rn */ ; #8 IR[3:0] = 0 /* Rm */; #8 IR[11:8] = 0 /* Rs */; #8 IR[15:12] = 0 /* Rd */; #8 RSLCT[19:16] = 0 /* Rn */ ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;
//Clk 1 (Rising Edge)
#9 OP = 16 ; #9 IR[27:25] = 0/* instruction type */ ; #9 IR[11:7] = 1 /*immediate rm shift amount*/; #9 IR[6:5] = 0 /*shiftType */; #9 IR[4]=0 /*0 = imediate, 1 register*/ ; #9 IR[19:16] = 0 /* Rn */ ; #9 IR[3:0] = 0 /* Rm */; #9 IR[11:8] = 0 /* Rs */; #9 IR[15:12] = 0 /* Rd */; #9 RSLCT[19:16] = 0 /* Rn */ ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;
//Clk 0 (Falling Edge) Send CU signals
#10 OP = 16 ; #10 IR[27:25] = 0/* instruction type */ ; #10 IR[11:7] = 1 /*immediate rm shift amount*/; #10 IR[6:5] = 0 /*shiftType */; #10 IR[4]=0 /*0 = imediate, 1 register*/ ; #10 IR[19:16] = 0 /* Rn */ ; #10 IR[3:0] = 0 /* Rm */; #10 IR[11:8] = 0 /* Rs */; #10 IR[15:12] = 0 /* Rd */; #10 RSLCT[19:16] = 0 /* Rn */ ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;
// #4 OP = 17 ; #4 IR[27:25] = 0/* instruction type */ ; #4 IR[6:5] = 0 /*shiftType */; #4 IR[4]=0 /*0 = imediate, 1 register*/ ; #4 IR[7:0] = 0 /*shiftVal*/;#4 IR[11:8] = 0/*shiftAmount*/ ; #4 IR[11:7] = 1 /*immediate rm shift amount*/; #4 IR[19:16] = 0 /* Rn */ ; #4 IR[3:0] = 0 /* Rm */; #4 IR[11:8] = 0 /* Rs */; #4 IR[15:12] = 0 /* Rd */; #4 RSLCT[19:16] = 0 /* Rn */ ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("prefab_alu_rf_bs2.vcd");
$dumpvars(0,prefab_alu_rf_bs2);
$display(" Test Results" );
$monitor("time = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v ARM_ALU.v BarrelShifter.v prefab_alu_rf_bs2.v
|
#include <bits/stdc++.h> using namespace std; int main() { int t[105][105]; int n; int x1, y1, x2, y2; while (cin >> n) { for (int i = 0; i < 105; i++) { for (int j = 0; j < 105; j++) t[i][j] = 0; } for (int z = 0; z < n; z++) { cin >> x1 >> y1 >> x2 >> y2; for (int i = 101 - y1; i >= 101 - y2; i--) { for (int j = 101 - x1; j >= 101 - x2; j--) t[i][j]++; } } int ans = 0; for (int i = 1; i <= 100; i++) { for (int j = 1; j <= 100; j++) ans += t[i][j]; } cout << ans << n ; } }
|
#include <bits/stdc++.h> const long long mod = (long long)1e9 + 7; using namespace std; vector<long long> parent, sz; void make_set(long long v) { parent[v] = v; sz[v] = 1; } long long find_set(long long v) { if (v == parent[v]) return v; return parent[v] = find_set(parent[v]); } void union_sets(long long a, long long b) { a = find_set(a); b = find_set(b); if (a != b) { if (a < b) swap(a, b); parent[b] = a; sz[a] += sz[b]; } } long long n; void clearall() { parent.clear(); sz.clear(); parent.resize(n + 1); sz.resize(n + 1); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { cin >> n; vector<long long> vc(n); for (long long i = 0; i < n; i++) cin >> vc[i]; clearall(); for (long long i = 0; i <= n; i++) { make_set(i); } vector<long long> mp(n + 1, 0); for (long long i = 0; i < n; i++) { mp[vc[i]] = i; } bool foo = true; vector<long long> ocp(n, 0); vector<long long> mxmp(n, 1); multiset<long long, greater<long long>> st; for (long long i = 0; i < n; i++) st.insert(1); for (long long i = 1; i <= n; i++) { long long mx = *(st.begin()); long long ii = mp[i]; if (mxmp[ii] != mx) { foo = false; break; } auto it = st.find(mxmp[ii]); st.erase(it); if (ii > 0 and ocp[ii - 1] == 1) { union_sets(ii, ii - 1); } if (ii < n - 1 and ocp[ii + 1] == 1) { union_sets(ii, ii + 1); } ocp[ii] = 1; long long pr = find_set(ii); if (pr < n - 1 and ocp[pr + 1] == 0) { it = st.find(mxmp[pr + 1]); st.erase(it); mxmp[pr + 1] = sz[pr] + 1; st.insert(sz[pr] + 1); } } if (foo) { cout << Yes n ; } else { cout << No n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, a[300010], sum[300010], ans; int main() { scanf( %lld%lld , &n, &k); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i]; ans += k * sum[n]; sort(sum + 1, sum + n); for (int i = 1; i < k; i++) ans -= sum[i]; printf( %lld , ans); return 0; }
|
`default_nettype none
module pipeline_control_idt_read(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_IDTR,
//Request
input wire iRD_START,
output wire oRD_FINISH,
//Load Store
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA,
//IRQ_CONFIG_TABLE
output wire oIRQ_CONF_TABLE_REQ,
output wire [5:0] oIRQ_CONF_TABLE_ENTRY,
output wire oIRQ_CONF_TABLE_FLAG_MASK,
output wire oIRQ_CONF_TABLE_FLAG_VALID,
output wire [1:0] oIRQ_CONF_TABLE_FLAG_LEVEL,
//Interrupt Configlation Table
output wire oICT_REQ,
output wire [5:0] oICT_ENTRY,
output wire oICT_CONF_MASK,
output wire oICT_CONF_VALID,
output wire [1:0] oICT_CONF_LEVEL
);
localparam L_PARAM_IDTREAD_STT_IDLE = 1'b0;
localparam L_PARAM_IDTREAD_STT_LOAD = 1'b1;
reg b_idt_read_state;
reg [6:0] b_idt_read_counter;
reg [6:0] b_idt_get_counter;
reg b_idt_readend;
reg b_idt_idt_data_valid;
reg [31:0] b_idt_idt_data;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_idt_read_state <= L_PARAM_IDTREAD_STT_IDLE;
b_idt_read_counter <= 7'h0;
b_idt_get_counter <= 7'h0;
b_idt_readend <= 1'b0;
b_idt_idt_data_valid <= 1'b0;
b_idt_idt_data <= {32{1'b0}};
end
else if(iRESET_SYNC)begin
b_idt_read_state <= L_PARAM_IDTREAD_STT_IDLE;
b_idt_read_counter <= 7'h0;
b_idt_get_counter <= 7'h0;
b_idt_readend <= 1'b0;
b_idt_idt_data_valid <= 1'b0;
b_idt_idt_data <= {32{1'b0}};
end
else begin
case(b_idt_read_state)
L_PARAM_IDTREAD_STT_IDLE:
begin
if(iRD_START)begin
b_idt_read_state <= L_PARAM_IDTREAD_STT_LOAD;
b_idt_read_counter <= 7'h0;
b_idt_get_counter <= 7'h0;
end
b_idt_readend <= 1'b0;
b_idt_idt_data_valid <= 1'b0;
b_idt_idt_data <= {32{1'b0}};
end
L_PARAM_IDTREAD_STT_LOAD:
begin
if(b_idt_read_counter < 7'd64 + 7'h1)begin
//Request Check
if(!iLDST_BUSY)begin
b_idt_read_counter <= b_idt_read_counter + 7'h1;
end
end
//Get Check
if(b_idt_get_counter < 7'd64 + 7'h1)begin
if(iLDST_REQ)begin
b_idt_get_counter <= b_idt_get_counter + 7'h1;
b_idt_idt_data_valid <= iLDST_REQ;
b_idt_idt_data <= iLDST_DATA;
end
end
else begin
b_idt_readend <= 1'b1;
b_idt_read_state <= L_PARAM_IDTREAD_STT_IDLE;
end
end
endcase
end
end
wire idt_read_condition = (b_idt_read_state == L_PARAM_IDTREAD_STT_LOAD) && (b_idt_read_counter < (7'd64 + 7'h1)) && !iLDST_BUSY;
assign oRD_FINISH = b_idt_readend;
assign oIRQ_CONF_TABLE_REQ = b_idt_idt_data_valid;
assign oIRQ_CONF_TABLE_ENTRY = b_idt_get_counter[5:0] - 6'h1;
assign oIRQ_CONF_TABLE_FLAG_MASK = b_idt_idt_data[1];
assign oIRQ_CONF_TABLE_FLAG_VALID = b_idt_idt_data[0];
assign oIRQ_CONF_TABLE_FLAG_LEVEL = b_idt_idt_data[17:16];
assign oICT_REQ = b_idt_idt_data_valid;
assign oICT_ENTRY = b_idt_get_counter[5:0] - 6'h1;
assign oICT_CONF_MASK = b_idt_idt_data[1];
assign oICT_CONF_VALID = b_idt_idt_data[0];
assign oICT_CONF_LEVEL = b_idt_idt_data[17:16];
assign oLDST_USE = b_idt_read_state == L_PARAM_IDTREAD_STT_LOAD;
assign oLDST_REQ = idt_read_condition;
assign oLDST_ORDER = 2'h2; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
assign oLDST_RW = 1'b0; //0=Read 1=Write
assign oLDST_ASID = 14'h0;
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = iSYSREG_IDTR + {b_idt_read_counter, 3'h0};
assign oLDST_DATA = 32'h0;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)1e4 + 22; int n, m; void solve() { int l, r; cin >> n >> m; int val = INT_MAX; for (int i = 0; i < m; i++) { cin >> l >> r; val = min(val, r - l + 1); } cout << val << n ; for (int i = 0; i < n; i++) cout << i % val << ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; }
|
//Copyright 2022 Google LLC
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.
module adder_reg(
input clk,
input [7:0] x,
input [7:0] y,
input carry_in,
output carry_output_bit,
output [7:0] sum
);
reg [8:0] full_sum_reg;
reg [7:0] x_reg;
reg [7:0] y_reg;
reg carry_in_reg;
assign carry_output_bit = full_sum_reg[8];
assign sum = full_sum_reg[7:0];
always @(posedge clk)
begin
x_reg <= x;
y_reg <= y;
carry_in_reg <= carry_in;
full_sum_reg <= x_reg + y_reg + carry_in_reg;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/30/2015 10:54:25 AM
// Design Name:
// Module Name: quadrature_encoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module quadrature_encoder(
input clk,
input reset,
input a,
input b,
output dir,
output [31:0] count
);
reg [2:0] a_prev;
reg [2:0] b_prev;
reg dir_reg=1'b0;
reg [31:0] count_reg=0;
//assumes debounced inputs and synchronous reset
//need a shift register to keep track of previous state
always @(posedge clk)
begin
a_prev <= {a_prev[1:0],a};
b_prev <= {b_prev[1:0],b};
end
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
{dir_reg, count_reg} <= {1'b0, 32'b0};
end
else
case ({a_prev[2],b_prev[2],a_prev[1],b_prev[1]})
4'b0010: {dir_reg,count_reg} <={1'b1,count_reg+32'b1};
4'b1011: {dir_reg,count_reg} <={1'b1,count_reg+32'b1};
4'b1101: {dir_reg,count_reg} <={1'b1,count_reg+32'b1};
4'b0100: {dir_reg,count_reg} <={1'b1,count_reg+32'b1};
4'b0001: {dir_reg,count_reg} <={1'b0,count_reg-32'b1};
4'b0111: {dir_reg,count_reg} <={1'b0,count_reg-32'b1};
4'b1110: {dir_reg,count_reg} <={1'b0,count_reg-32'b1};
4'b1000: {dir_reg,count_reg} <={1'b0,count_reg-32'b1};
default: {dir_reg,count_reg} <= {dir_reg,count_reg};
endcase
end
assign count=count_reg;
assign dir = dir_reg;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// web: http://www.latticesemi.com/
// email:
//
// =============================================================================
// REVISION HISTORY
// Version : 7.2
// Changes Made : Initial Creation
// Baudrate Generation is modified.
// RX and TX path of the UART is updated to faster clock
// 16 word deep FIFO is implemented when FIFO option is
// selected
// =============================================================================
`ifndef RXFIFO_FILE
`define RXFIFO_FILE
`include "system_conf.v"
module rxcver_fifo (Data, Clock, WrEn, RdEn, Reset, Q, Q_error, Empty, Full,
AlmostEmpty, AlmostFull);
input [10:0] Data;
input Clock;
input WrEn;
input RdEn;
input Reset;
output [7:0] Q;
output [2:0] Q_error;
output Empty;
output Full;
output AlmostEmpty;
output AlmostFull;
wire[7:0] Q_node;
parameter lat_family = `LATTICE_FAMILY;
generate
if (lat_family == "SC" || lat_family == "SCM") begin
pmi_fifo_dc #(.pmi_data_width_w(8),
.pmi_data_width_r(8),
.pmi_data_depth_w(16),
.pmi_data_depth_r(16),
.pmi_full_flag(16),
.pmi_empty_flag(0),
.pmi_almost_full_flag(1),
.pmi_almost_empty_flag(0),
.pmi_regmode("noreg"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_fifo_dc"),
.pmi_implementation("LUT"))
rx_fifo_inst_dc (
.Data(Data[10:3]),
.WrClock(Clock),
.RdClock(Clock),
.WrEn (WrEn),
.RdEn (RdEn),
.Reset (Reset),
.RPReset(Reset),
.Q (Q_node),
.Empty (Empty),
.Full (Full),
.AlmostEmpty (AlmostEmpty),
.AlmostFull (AlmostFull));
end else begin
pmi_fifo #(
.pmi_data_width(8),
.pmi_data_depth(16),
.pmi_full_flag(16),
.pmi_empty_flag(0),
.pmi_almost_full_flag(1),
.pmi_almost_empty_flag(0),
.pmi_regmode("noreg"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_fifo"),
.pmi_implementation("LUT"))
rx_fifo_inst
(.Data(Data[10:3]),
.Clock(Clock),
.WrEn(WrEn),
.RdEn(RdEn),
.Reset(Reset),
.Q(Q_node),
.Empty(Empty),
.Full(Full),
.AlmostEmpty(AlmostEmpty),
.AlmostFull(AlmostFull));
end
endgenerate
reg [2:0] fifo [15:0];
reg [4:0] wr_pointer1 = 0;
reg [4:0] rd_pointer1 = 0;
reg [4:0] rd_pointer_prev = 0;
reg valid_RdEn;
always @(posedge Clock or posedge Reset)
begin
if (Reset)
begin
wr_pointer1 <= 0;
rd_pointer1 <= 0;
valid_RdEn <= 0;
rd_pointer_prev <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
begin
if (WrEn == 1 && RdEn !=1 && Full !=1) begin
fifo[wr_pointer1%16] <= Data[2:0];
wr_pointer1 <= wr_pointer1 + 1; end
else if (WrEn != 1 && RdEn ==1 && Empty !=1) begin
valid_RdEn <= 1'b1;
rd_pointer_prev <= rd_pointer1;
rd_pointer1 <= rd_pointer1 +1; end
else if (WrEn == 1 && RdEn ==1) begin
rd_pointer_prev <= rd_pointer1;
valid_RdEn <= 1'b1;
fifo[wr_pointer1%16] <= Data[2:0];
rd_pointer1 <= rd_pointer1 + 1;
wr_pointer1 <= wr_pointer1 + 1;
end
// else
// valid_RdEn <= 1'b0;
if (valid_RdEn) begin
fifo[rd_pointer_prev%16] <= 0;
valid_RdEn <= 1'b0;
end
end
end
// Data is only valid for single clock cycle after read to the FIFO occurs
// assign Q = {Q_node, fifo[rd_pointer_prev%16]};
assign Q = Q_node;
assign Q_error = fifo[rd_pointer_prev%16];
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int gi() { int x = 0, o = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } struct dat { int len, x, y, z, w; int getr() const { if (!len) return 1e9; if (len == 3) return z; return w; } bool operator<(const dat &A) const { return getr() > A.getr(); } void print() { if (len == 3) cout << 3 << n << x << << y << << z << n ; else cout << 4 << n << x << << y << << z << << w << n ; } } ans3[N], ans4[N]; int n, q, a[N]; void solve3() { static int L[N], R[N], st[N]; int tp = 0; for (int i = 1; i <= n; i++) { while (tp && a[st[tp]] <= a[i]) --tp; L[i] = st[tp]; st[++tp] = i; } tp = 0; for (int i = n; i; i--) { while (tp && a[st[tp]] <= a[i]) --tp; R[i] = st[tp]; st[++tp] = i; } for (int i = 1; i <= n; i++) if (L[i] && R[i]) ans3[L[i]] = max(ans3[L[i]], (dat){3, L[i], i, R[i], 0}); tp = 0; for (int i = 1; i <= n; i++) { while (tp && a[st[tp]] >= a[i]) --tp; L[i] = st[tp]; st[++tp] = i; } tp = 0; for (int i = n; i; i--) { while (tp && a[st[tp]] >= a[i]) --tp; R[i] = st[tp]; st[++tp] = i; } for (int i = 1; i <= n; i++) if (L[i] && R[i]) ans3[L[i]] = max(ans3[L[i]], (dat){3, L[i], i, R[i], 0}); } bool cmp1(int x, int y) { return a[x] < a[y]; } bool cmp2(int x, int y) { return a[x] > a[y]; } void solve4() { static int st1[N], st2[N], occ[N]; set<int> can; int tp1 = 0, tp2 = 0; for (int i = n; i; i--) { while (tp1 && a[st1[tp1]] > a[i]) { int tmp = st1[tp1]; --occ[tmp]; if (!occ[tmp]) can.insert(tmp); --tp1; } st1[++tp1] = i; while (tp2 && a[st2[tp2]] < a[i]) { int tmp = st2[tp2]; --occ[tmp]; if (!occ[tmp]) can.insert(tmp); --tp2; } st2[++tp2] = i; occ[i] = 2; int p = st1[lower_bound(st1 + 1, st1 + tp1 + 1, i, cmp1) - st1 - 1]; int q = st2[lower_bound(st2 + 1, st2 + tp2 + 1, i, cmp2) - st2 - 1]; if (p && q) { auto it = can.lower_bound(max(p, q) + 1); if (it != can.end()) { int t = *it; p = *lower_bound(st1 + 1, st1 + tp1 + 1, t, greater<int>()); q = *lower_bound(st2 + 1, st2 + tp2 + 1, t, greater<int>()); ans4[i] = (dat){4, i, min(p, q), max(p, q), t}; } } } } int main() { cin >> n >> q; for (int i = 1; i <= n; i++) a[i] = gi(); solve3(); solve4(); for (int i = n - 1; i; i--) { ans3[i] = max(ans3[i], ans3[i + 1]); ans4[i] = max(ans4[i], ans4[i + 1]); } for (int i = 1; i <= q; i++) { int l = gi(), r = gi(); if (ans4[l].getr() <= r) ans4[l].print(); else if (ans3[l].getr() <= r) ans3[l].print(); else puts( 0 ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[100005]; int p[100005]; long long size[100005]; struct edge { int u, v, w; edge(int u = 0, int v = 0, int w = 0) : u(u), v(v), w(w) {} bool operator<(const edge &e1) const { return w > e1.w; } } eList[100005]; int findR(int x) { if (p[x] == x) return x; return p[x] = findR(p[x]); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int u, v; for (int i = 1; i <= m; i++) { scanf( %d%d , &u, &v); eList[i] = edge(u, v, min(a[u], a[v])); } for (int i = 1; i <= n; i++) { p[i] = i; size[i] = 1; } sort(eList + 1, eList + m + 1); long long ans = 0; int x, y; for (int i = 1; i <= m; i++) { u = eList[i].u; v = eList[i].v; x = findR(u); y = findR(v); if (x != y) { ans += eList[i].w * (size[x] * size[y]); p[x] = y; size[y] += size[x]; } } printf( %.6lf , ans * 2.0 / n / (n - 1)); return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to USB chip on the DE2 Board. *
* *
******************************************************************************/
module niosII_system_usb_0 (
// Inputs
clk,
reset,
address,
chipselect,
read,
write,
writedata,
OTG_INT0,
OTG_INT1,
// Bidirectionals
OTG_DATA,
// Outputs
readdata,
irq,
OTG_RST_N,
OTG_ADDR,
OTG_CS_N,
OTG_RD_N,
OTG_WR_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input chipselect;
input read;
input write;
input [15: 0] writedata;
input OTG_INT0;
input OTG_INT1;
// Bidirectionals
inout [15: 0] OTG_DATA;
// Outputs
output reg [15: 0] readdata;
output reg irq;
output reg OTG_RST_N;
output reg [ 1: 0] OTG_ADDR;
output reg OTG_CS_N;
output reg OTG_RD_N;
output reg OTG_WR_N;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [15: 0] data_to_usb_chip;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
begin
readdata <= 16'h0000;
irq <= 1'b0;
data_to_usb_chip <= 16'h0000;
OTG_RST_N <= 1'b0;
OTG_ADDR <= 2'h0;
OTG_CS_N <= 1'b1;
OTG_RD_N <= 1'b1;
OTG_WR_N <= 1'b1;
end
else
begin
readdata <= OTG_DATA;
irq <= ~OTG_INT1 | ~OTG_INT0;
data_to_usb_chip <= writedata[15:0];
OTG_RST_N <= 1'b1;
OTG_ADDR <= address;
OTG_CS_N <= ~chipselect;
OTG_RD_N <= ~read;
OTG_WR_N <= ~write;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign OTG_DATA = OTG_WR_N ? 16'hzzzz : data_to_usb_chip;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_dtl_sclk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_dtl_sclk(l2clk ,int_sclk ,sclk ,ssclk_n ,se ,si_l ,
global_reset_n );
output int_sclk ;
output sclk ;
output ssclk_n ;
input l2clk ;
input se ;
input si_l ;
input global_reset_n ;
wire [2:0] scarry ;
wire [3:0] scount ;
wire [3:0] next_scount ;
wire net113 ;
wire net050 ;
wire scan_data_1 ;
wire scan_data_2 ;
wire scan_data_3 ;
wire scan_data_4 ;
wire scan_in ;
wire scan_out ;
wire net65 ;
bw_u1_soffr_4x I128 (
.q (scount[2] ),
.so (scan_data_3 ),
.ck (l2clk ),
.d (next_scount[2] ),
.se (se ),
.sd (scan_data_2 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I156 (
.z (scan_in ),
.a (si_l ) );
bw_u1_xor2_4x I159 (
.z (next_scount[1] ),
.a (scount[1] ),
.b (scarry[0] ) );
bw_u1_xor2_4x I160 (
.z (next_scount[2] ),
.a (scount[2] ),
.b (scarry[1] ) );
bw_u1_inv_2x I161 (
.z (next_scount[0] ),
.a (scount[0] ) );
bw_u1_xor2_4x I162 (
.z (next_scount[3] ),
.a (scount[3] ),
.b (scarry[2] ) );
bw_u1_inv_4x I163 (
.z (scarry[0] ),
.a (next_scount[0] ) );
bw_u1_nand2_4x I164 (
.z (net113 ),
.a (scount[0] ),
.b (scount[1] ) );
bw_u1_inv_8x I165 (
.z (int_sclk ),
.a (net113 ) );
bw_u1_inv_4x I166 (
.z (net65 ),
.a (scount[2] ) );
bw_u1_nor2_2x I167 (
.z (scarry[2] ),
.a (net65 ),
.b (net113 ) );
bw_u1_soffr_4x I171 (
.q (sclk ),
.so (scan_out ),
.ck (l2clk ),
.d (scarry[1] ),
.se (se ),
.sd (scan_data_4 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I21 (
.q (scount[0] ),
.so (scan_data_1 ),
.ck (l2clk ),
.d (next_scount[0] ),
.se (se ),
.sd (scan_in ),
.r_l (global_reset_n ) );
bw_u1_inv_5x I173 (
.z (ssclk_n ),
.a (scan_out ) );
bw_u1_inv_2x I179 (
.z (net050 ),
.a (int_sclk ) );
bw_u1_inv_5x I180 (
.z (scarry[1] ),
.a (net050 ) );
bw_u1_soffr_4x I125 (
.q (scount[1] ),
.so (scan_data_2 ),
.ck (l2clk ),
.d (next_scount[1] ),
.se (se ),
.sd (scan_data_1 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I127 (
.q (scount[3] ),
.so (scan_data_4 ),
.ck (l2clk ),
.d (next_scount[3] ),
.se (se ),
.sd (scan_data_3 ),
.r_l (global_reset_n ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d %d , &n, &k); vector<int> a(n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); int sum = 0; for (int i = 0; i < n; ++i) sum += a[i]; if (sum % k) { printf( No n ); return 0; } int req = sum / k; int cur = 0; int len = 0; for (int i = 0; i < n; ++i) { if (a[i] > req) { printf( No n ); return 0; } } vector<int> ans; for (int i = 0; i < n; ++i) { cur += a[i]; len++; if (cur == req) { ans.push_back(len); cur = 0; len = 0; } else if (cur > req) { cur = a[i]; len = 1; } } if ((int)ans.size() == k) { printf( Yes n ); for (int i = 0; i < k; ++i) printf( %d , ans[i]); } else { printf( No n ); } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of Instruction cache data rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t = 1; cin >> t; while (t--) { string n, k; cin >> n >> k; string A, B, C, other; for (int i = 0; i < n.size(); i++) { if (n[i] == a ) A.push_back( a ); else if (n[i] == b ) B.push_back( b ); else if (n[i] == c ) C.push_back( c ); else other.push_back(n[i]); } sort(n.begin(), n.end()); sort(other.begin(), other.end()); if (A.size() == 0 || B.size() == 0 || C.size() == 0) cout << n; else { if (k[0] == a ) { if (k[1] == b ) cout << A << C << B; else cout << A << B << C; } else { cout << A << B << C; } if (other.size() != 0) cout << other; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int i, j, n, ct = 0; cin >> n; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; if (n < 2) { cout << -1 n ; return; } sort(a, a + n); set<int> ans; if (n == 2) { ans.insert(a[1] + a[1] - a[0]); ans.insert(a[0] - (a[1] - a[0])); if ((a[1] - a[0]) % 2 == 0) ans.insert((a[0] + a[1]) / 2); } else { set<int> dif; for (i = 1; i < n; i++) dif.insert(a[i] - a[i - 1]); if (dif.size() == 1) { int d = *dif.begin(); ans.insert(a[0] - d); ans.insert(a[n - 1] + d); } else if (dif.size() == 2) { int d1 = *dif.begin(); int d2 = *dif.upper_bound(d1); if (2 * d1 == d2) { for (i = 0; i + 1 < n; i++) { if (a[i] + d1 == a[i + 1]) continue; ct++; ans.insert(a[i] + d1); } } } } if (ct > 1) ans.clear(); cout << ans.size() << n ; for (auto &x : ans) cout << x << ; } int main() { ios_base::sync_with_stdio(false); int test = 1; while (test--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int M = 1e5 + 10; int n, m, vis[M * 12], ans[M * 12], tot; vector<int> vt[10][M * 12], tmp; vector<vector<int> > now, nxt; void add(int x, int y, int id) { while (id / 10) vt[id % 10][++tot].push_back(y), y = tot, id /= 10; vt[id][x].push_back(y); } void bfs() { vis[1] = 1; now.push_back(vector<int>(1, 1)); while (!now.empty()) { for (int p = 0; p < now.size(); p++) { vector<int> a = now[p]; for (int w = 0; w < 10; w++) { tmp.clear(); for (int i = 0; i < a.size(); i++) { int x = a[i]; for (int j = 0; j < vt[w][x].size(); j++) { int y = vt[w][x][j]; if (vis[y]) continue; vis[y] = 1; ans[y] = (10LL * ans[x] % mod + w) % mod; tmp.push_back(y); } } if (tmp.size()) nxt.push_back(tmp); } } now = nxt; nxt.clear(); } } int main(int argc, char const *argv[]) { scanf( %d%d , &n, &m); tot = n; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); add(x, y, i); add(y, x, i); } bfs(); for (int i = 2; i <= n; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 19; int n, k, m, e, a[N], b[N], g[N], c[N], d[N], f[N], t[N], w[N], p[N]; vector<int> v[N]; void upd(int k) { if (t[k << 1] > t[k << 1 | 1]) t[k] = t[k << 1] + w[k], p[k] = p[k << 1]; else t[k] = t[k << 1 | 1] + w[k], p[k] = p[k << 1 | 1]; } void build(int k = 1, int l = 1, int r = n) { if (l == r) { t[k] = d[g[l]]; w[k] = 0; p[k] = l; return; } int h = l + r >> 1; build(k << 1, l, h); build(k << 1 | 1, h + 1, r); upd(k); } void modify(int L, int R, int X, int k = 1, int l = 1, int r = n) { if (L <= l && r <= R) { w[k] += X; t[k] += X; return; } int h = l + r >> 1; if (L <= h) modify(L, R, X, k << 1, l, h); if (h < R) modify(L, R, X, k << 1 | 1, h + 1, r); upd(k); } void dfs(int u, int fa) { int i, x, o = 1; a[u] = ++e; g[e] = u; d[u] = d[fa] + 1; f[u] = fa; for (i = 0; i < v[u].size(); i++) { x = v[u][i]; if (x != fa) dfs(x, u), o = 0; } m += o; b[u] = e; } void go(int x) { while (x && !c[x]) { modify(a[x], b[x], -1); c[x] = 1; e++; x = f[x]; } } int main() { int i, x, y; long long s = 0; scanf( %d%d , &n, &k); for (i = 1; i < n; i++) { scanf( %d%d , &x, &y); v[x].push_back(y); v[y].push_back(x); } e = 0; dfs(1, 0); if (m <= k) { for (i = m; i <= k; i++) s = max(s, (long long)i * (n - i)); cout << s; return 0; } build(); e = 0; for (i = 1; i <= k; i++) { go(g[p[1]]); } s = (long long)k * (n - k); for (i = 0; i <= n - e; i++) s = min(s, (long long)(k - i) * (n - k - i)); cout << s; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DFBBP_PP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_SYMBOL_V
|
/*
Copyright (C) 2016
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//-------------------------------------------------------------------------
// https://github.com/balanx/laotzu
//
// Description : submodule of asyn_fifo_controller
// write function
//
//-------------------------------------------------------------------------
// History :
// 10/15/2016
// initial draft
//
//-------------------------------------------------------------------------
module asyn_fifo_write #(
parameter ADDRWIDTH = 6,
parameter [ADDRWIDTH:0] FIFODEPTH = 44,
parameter [ADDRWIDTH:0] MINBIN2 = 0,
parameter [ADDRWIDTH:0] MAXBIN2 = 7
) (
input wire w_clk ,
input wire w_rst_n ,
input wire w_en ,
input wire [ADDRWIDTH:0] r2w_ptr ,
output reg [ADDRWIDTH-1:0] wbin ,
output reg [ADDRWIDTH:0] wptr ,
output inc ,
output reg w_full ,
output reg [ADDRWIDTH:0] w_counter,
output reg w_error
);
//
assign inc = w_en && !w_full;
//---------------------------------------------------------------
// "wbin2" is double the amount of "wbin"
// e.g. deepth = 10
// wbin = 0~9
// wbin2 = 6~15, 16~25
// offset = 6
//---------------------------------------------------------------
reg [ADDRWIDTH:0] wbin2;
wire [ADDRWIDTH:0] wbnext = (wbin2>=MINBIN2 && wbin2<MAXBIN2) ?
(wbin2 + 1'b1) : MINBIN2;
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wbin2 <= MINBIN2;
else if (inc)
wbin2 <= wbnext;
//---------------------------------------------------------------
// memory address
//---------------------------------------------------------------
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wbin <= {ADDRWIDTH{1'b0}};
else if (inc)
wbin <= wbnext[ADDRWIDTH] ? wbnext[ADDRWIDTH-1:0] :
(wbnext[ADDRWIDTH-1:0] - MINBIN2[ADDRWIDTH-1:0]);
//---------------------------------------------------------------
// GRAY pointer
//---------------------------------------------------------------
// binary-to-gray conversion
wire [ADDRWIDTH:0] wptr_gray = {1'b0,wbnext[ADDRWIDTH:1]} ^ wbnext;
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wptr <= (MINBIN2>>1) ^ MINBIN2;
else if (inc)
wptr <= wptr_gray;
//---------------------------------------------------------------
// from other-side
//---------------------------------------------------------------
reg [ADDRWIDTH:0] r2w_bin;
always @(r2w_ptr)
begin: GrayToBin
integer i;
for (i=ADDRWIDTH; i>=0; i=i-1)
r2w_bin[i] = ^(r2w_ptr>>i);
end
//---------------------------------------------------------------
// output signals
//---------------------------------------------------------------
wire [ADDRWIDTH:0] distance = ( (wbin2 >= r2w_bin) ?
(wbin2 - r2w_bin) :
(wbin2 - r2w_bin - (MINBIN2<<1) )
) + inc;
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
w_counter <= {(ADDRWIDTH+1){1'b0}};
else
w_counter <= distance;
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
w_full <= 1'b0;
else
w_full <= (distance == FIFODEPTH);
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
w_error <= 1'b0;
else
w_error <= (w_counter > FIFODEPTH);
//
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, m, n, a[1000], b[1000], t = -1; cin >> n >> m; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < m; i++) { cin >> b[i]; } sort(a, a + n); sort(b, b + m); for (i = a[n - 1]; i < b[0]; i++) { if ((2 * a[0]) <= i) { t = i; break; } } cout << t; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_SYMBOL_V
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#include <bits/stdc++.h> #define ll long long #define ld long double #define pb push_back #define VI vector<int> #define VL vector<ll> #define MX vector<VI > #define all(x) x.begin(), x.end() #define IOS cin.tie(0)->sync_with_stdio(0) using namespace std; ll gcd(ll a, ll b){ if(!b) return a; return gcd(b, a%b); } int main(){ int n, m; cin >> n >> m; VL a(n), b(m); for(ll &i : a) cin >> i; for(ll &i : b) cin >> i; sort(all(a)); ll t = 0; for(int i=1; i<n; i++) t = gcd(a[i]-a[i-1], t); for(ll &i : b) cout << gcd(i+a[0], t) << ; cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { vector<char> vec(100001); vec[0] = a ; int i = 1; while (i < 100001) { if (vec[i - 1] == a ) vec[i] = b ; else if (vec[i - 1] == b ) vec[i] = c ; else if (vec[i - 1] == c ) vec[i] = d ; else if (vec[i - 1] == d ) vec[i] = a ; i++; } int n; cin >> n; for (int i = 0; i < n; i++) cout << vec[i]; cout << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int sum = 0; for (int i = 0; i < 3; i++) { long long int temp; cin >> temp; sum += temp; } cout << sum / 2 << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_1_V
`define SKY130_FD_SC_HDLL__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_1_V
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#include <bits/stdc++.h> using namespace std; int n, m; vector<int> vec[300000]; int mn(int x); int mx(int x) { if (!vec[x].size()) return 0; int ret = n; for (int i = (0); i < (vec[x].size()); i++) ret = min(ret, mn(vec[x][i])); return ret; } int mn(int x) { if (!vec[x].size()) return 0; int ret = 0; for (int i = (0); i < (vec[x].size()); i++) ret += mx(vec[x][i]) + 1; return ret - 1; } int main() { scanf( %d , &n); for (int i = (0); i < (n - 1); i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; vec[x].push_back(y); } int leaf = 0; for (int i = (0); i < (n); i++) if (!vec[i].size()) leaf++; printf( %d %d n , leaf - mx(0), 1 + mn(0)); return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_mac_1 (
// Q0 = S2;
// Q1 = S0*C0 + S1*C1 + S2*C2 + S3*C3 + S4*C4 + S5*C5;
clk,
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
// outputs
mac_data_0,
mac_data_1);
// parameters
localparam MAC_C0 = 16'h024d; // 0.0180
localparam MAC_C1 = 16'hf155; // -0.1146
localparam MAC_C2 = 16'h4c77; // 0.5974
localparam MAC_C3 = 16'h4c77; // 0.5974
localparam MAC_C4 = 16'hf155; // -0.1146
localparam MAC_C5 = 16'h024d; // 0.0180
// Q0 = S2;
// Q1 = S0*C0 + S1*C1 + S2*C2 + S3*C3 + S4*C4 + S5*C5;
input clk;
input [15:0] data_s0;
input [15:0] data_s1;
input [15:0] data_s2;
input [15:0] data_s3;
input [15:0] data_s4;
input [15:0] data_s5;
// outputs
output [15:0] mac_data_0;
output [15:0] mac_data_1;
// internal registers
reg [15:0] mac_data_0 = 'd0;
reg [15:0] mac_data_1 = 'd0;
reg [15:0] p3_data_0_0 = 'd0;
reg [34:0] p3_data_1_0 = 'd0;
reg [15:0] p2_data_0_0 = 'd0;
reg [33:0] p2_data_1_0 = 'd0;
reg [33:0] p2_data_1_1 = 'd0;
reg [15:0] p1_data_0_0 = 'd0;
reg [32:0] p1_data_1_0 = 'd0;
reg [32:0] p1_data_1_1 = 'd0;
reg [32:0] p1_data_1_2 = 'd0;
// internal signals
wire p3_ovf_s;
wire [31:0] p1_data_0_0_s;
wire [31:0] p1_data_1_0_s;
wire [31:0] p1_data_1_1_s;
wire [31:0] p1_data_1_2_s;
wire [31:0] p1_data_1_3_s;
wire [31:0] p1_data_1_4_s;
wire [31:0] p1_data_1_5_s;
// output registers
assign p3_ovf_s = ((p3_data_1_0[34:30] == 5'h00) || (p3_data_1_0[34:30] == 5'h1f)) ? 1'b0 : 1'b1;
always @(posedge clk) begin
mac_data_0 <= p3_data_0_0;
if (p3_ovf_s == 0) begin
mac_data_1 <= p3_data_1_0[30:15];
end else if (p3_data_1_0[34] == 1'b1) begin
mac_data_1 <= 16'h8001;
end else begin
mac_data_1 <= 16'h7fff;
end
end
// sum of products (stage-3)
always @(posedge clk) begin
p3_data_0_0 <= p2_data_0_0;
p3_data_1_0 <= {p2_data_1_0[33], p2_data_1_0} + {p2_data_1_1[33], p2_data_1_1};
end
// sum of products (stage-2)
always @(posedge clk) begin
p2_data_0_0 <= p1_data_0_0;
p2_data_1_0 <= {p1_data_1_0[32], p1_data_1_0} + {p1_data_1_1[32], p1_data_1_1};
p2_data_1_1 <= {p1_data_1_2[32], p1_data_1_2};
end
// sum of products (stage-1)
always @(posedge clk) begin
p1_data_0_0 <= p1_data_0_0_s[15:0];
p1_data_1_0 <= {p1_data_1_0_s[31], p1_data_1_0_s} + {p1_data_1_1_s[31], p1_data_1_1_s};
p1_data_1_1 <= {p1_data_1_2_s[31], p1_data_1_2_s} + {p1_data_1_3_s[31], p1_data_1_3_s};
p1_data_1_2 <= {p1_data_1_4_s[31], p1_data_1_4_s} + {p1_data_1_5_s[31], p1_data_1_5_s};
end
// sample -0
ad_mul_dsp48_1 i_mul_dsp48_1_0_0 (
.clk (clk),
.a (data_s2),
.b (16'h1),
.p (p1_data_0_0_s));
// sample -1
ad_mul_dsp48_1 i_mul_dsp48_1_1_0 (
.clk (clk),
.a (data_s0),
.b (MAC_C0),
.p (p1_data_1_0_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_1 (
.clk (clk),
.a (data_s1),
.b (MAC_C1),
.p (p1_data_1_1_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_2 (
.clk (clk),
.a (data_s2),
.b (MAC_C2),
.p (p1_data_1_2_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_3 (
.clk (clk),
.a (data_s3),
.b (MAC_C3),
.p (p1_data_1_3_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_4 (
.clk (clk),
.a (data_s4),
.b (MAC_C4),
.p (p1_data_1_4_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_5 (
.clk (clk),
.a (data_s5),
.b (MAC_C5),
.p (p1_data_1_5_s));
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> const long long N = 3000006; using namespace std; const long long MOD = 1000000007LL; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T power(T x, T y, long long m = MOD) { T ans = 1; while (y > 0) { if (y & 1LL) ans = (ans * x) % m; y >>= 1LL; x = (x * x) % m; } return ans % m; } long long prime[N]; long long a[N], f[N]; int32_t main() { memset(prime, 1, sizeof(prime)); prime[1] = 0; for (long long i = 2; i < N; i++) { if (!prime[i]) continue; for (long long j = i * i; j < N; j += i) prime[j] = 0; } long long n; cin >> n; for (long long(i) = (0); i < (n); i++) { cin >> a[i]; ++f[a[i]]; } long long maxi = 0; if (n == 1) { cout << 1 << n ; cout << a[0]; return 0; } for (long long(i) = (0); i < (n); i++) { if (a[i] == 1) continue; if (prime[a[i] + 1] && f[1]) { cout << f[1] + 1 << n ; for (long long(i) = (0); i < (f[1]); i++) cout << 1 ; cout << a[i]; return 0; } } if (f[1] >= 2) { cout << f[1] << n ; for (long long(i) = (0); i < (f[1]); i++) cout << 1 ; return 0; } for (long long(i) = (0); i < (n - 1); i++) { for (long long(j) = (i + 1); j < (n); j++) { if (prime[a[i] + a[j]]) { cout << 2 << n ; cout << a[i] << << a[j]; return 0; } } } cout << 1 << n ; cout << a[0]; }
|
#include <bits/stdc++.h> using namespace std; int main() { long int t; cin >> t; while (t--) { int n, m; cin >> n >> m; long int a[n + 1][m + 1]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } long int b[n + 1][m + 1]; for (int i = 1; i <= n; i++) { b[i][1] = 3; b[i][m] = 3; } for (int i = 1; i <= m; i++) { b[1][i] = 3; b[n][i] = 3; } b[1][1] = 2; b[1][m] = 2; b[n][1] = 2; b[n][m] = 2; for (int i = 2; i <= n - 1; i++) { for (int j = 2; j <= m - 1; j++) { b[i][j] = 4; b[i][j] = 4; } } int f = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] > b[i][j]) { f = 1; break; } } } if (f == 1) { cout << NO << endl; } else { cout << YES << endl; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cout << b[i][j] << ; } cout << endl; } } } }
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Tue May 26 11:16:08 2015
//Host : WK49-Ubuntu running 64-bit Ubuntu 14.04.2 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDC_scl_i,
DDC_scl_o,
DDC_scl_t,
DDC_sda_i,
DDC_sda_o,
DDC_sda_t,
clk,
hdmi_clk_n,
hdmi_clk_p,
hdmi_d_n,
hdmi_d_p,
hdmi_hpd,
hdmi_out_en,
vga_b,
vga_g,
vga_hs,
vga_r,
vga_vs);
input DDC_scl_i;
output DDC_scl_o;
output DDC_scl_t;
input DDC_sda_i;
output DDC_sda_o;
output DDC_sda_t;
input clk;
input hdmi_clk_n;
input hdmi_clk_p;
input [2:0]hdmi_d_n;
input [2:0]hdmi_d_p;
output [0:0]hdmi_hpd;
output [0:0]hdmi_out_en;
output [4:0]vga_b;
output [5:0]vga_g;
output vga_hs;
output [4:0]vga_r;
output vga_vs;
wire GND_2;
wire TMDS_Clk_n_1;
wire TMDS_Clk_p_1;
wire [2:0]TMDS_Data_n_1;
wire [2:0]TMDS_Data_p_1;
wire clk_1;
wire clk_wiz_0_clk_out1;
wire dvi2rgb_0_DDC_SCL_I;
wire dvi2rgb_0_DDC_SCL_O;
wire dvi2rgb_0_DDC_SCL_T;
wire dvi2rgb_0_DDC_SDA_I;
wire dvi2rgb_0_DDC_SDA_O;
wire dvi2rgb_0_DDC_SDA_T;
wire dvi2rgb_0_PixelClk;
wire dvi2rgb_0_RGB_ACTIVE_VIDEO;
wire [23:0]dvi2rgb_0_RGB_DATA;
wire dvi2rgb_0_RGB_HSYNC;
wire dvi2rgb_0_RGB_VSYNC;
wire [4:0]rgb2vga_0_vga_pBlue;
wire [5:0]rgb2vga_0_vga_pGreen;
wire rgb2vga_0_vga_pHSync;
wire [4:0]rgb2vga_0_vga_pRed;
wire rgb2vga_0_vga_pVSync;
wire [0:0]xlconstant_0_dout;
wire [0:0]xlconstant_1_dout;
assign DDC_scl_o = dvi2rgb_0_DDC_SCL_O;
assign DDC_scl_t = dvi2rgb_0_DDC_SCL_T;
assign DDC_sda_o = dvi2rgb_0_DDC_SDA_O;
assign DDC_sda_t = dvi2rgb_0_DDC_SDA_T;
assign TMDS_Clk_n_1 = hdmi_clk_n;
assign TMDS_Clk_p_1 = hdmi_clk_p;
assign TMDS_Data_n_1 = hdmi_d_n[2:0];
assign TMDS_Data_p_1 = hdmi_d_p[2:0];
assign clk_1 = clk;
assign dvi2rgb_0_DDC_SCL_I = DDC_scl_i;
assign dvi2rgb_0_DDC_SDA_I = DDC_sda_i;
assign hdmi_hpd[0] = xlconstant_1_dout;
assign hdmi_out_en[0] = xlconstant_0_dout;
assign vga_b[4:0] = rgb2vga_0_vga_pBlue;
assign vga_g[5:0] = rgb2vga_0_vga_pGreen;
assign vga_hs = rgb2vga_0_vga_pHSync;
assign vga_r[4:0] = rgb2vga_0_vga_pRed;
assign vga_vs = rgb2vga_0_vga_pVSync;
design_1_xlconstant_0_1 GND
(.dout(xlconstant_0_dout));
GND GND_1
(.G(GND_2));
design_1_xlconstant_1_0 VDD
(.dout(xlconstant_1_dout));
design_1_clk_wiz_0_0 clk_wiz_0
(.clk_in1(clk_1),
.clk_out1(clk_wiz_0_clk_out1),
.reset(GND_2));
design_1_dvi2rgb_0_0 dvi2rgb_0
(.DDC_SCL_I(dvi2rgb_0_DDC_SCL_I),
.DDC_SCL_O(dvi2rgb_0_DDC_SCL_O),
.DDC_SCL_T(dvi2rgb_0_DDC_SCL_T),
.DDC_SDA_I(dvi2rgb_0_DDC_SDA_I),
.DDC_SDA_O(dvi2rgb_0_DDC_SDA_O),
.DDC_SDA_T(dvi2rgb_0_DDC_SDA_T),
.PixelClk(dvi2rgb_0_PixelClk),
.RefClk(clk_wiz_0_clk_out1),
.TMDS_Clk_n(TMDS_Clk_n_1),
.TMDS_Clk_p(TMDS_Clk_p_1),
.TMDS_Data_n(TMDS_Data_n_1),
.TMDS_Data_p(TMDS_Data_p_1),
.aRst(GND_2),
.pRst(GND_2),
.vid_pData(dvi2rgb_0_RGB_DATA),
.vid_pHSync(dvi2rgb_0_RGB_HSYNC),
.vid_pVDE(dvi2rgb_0_RGB_ACTIVE_VIDEO),
.vid_pVSync(dvi2rgb_0_RGB_VSYNC));
design_1_rgb2vga_0_0 rgb2vga_0
(.PixelClk(dvi2rgb_0_PixelClk),
.rgb_pData(dvi2rgb_0_RGB_DATA),
.rgb_pHSync(dvi2rgb_0_RGB_HSYNC),
.rgb_pVDE(dvi2rgb_0_RGB_ACTIVE_VIDEO),
.rgb_pVSync(dvi2rgb_0_RGB_VSYNC),
.vga_pBlue(rgb2vga_0_vga_pBlue),
.vga_pGreen(rgb2vga_0_vga_pGreen),
.vga_pHSync(rgb2vga_0_vga_pHSync),
.vga_pRed(rgb2vga_0_vga_pRed),
.vga_pVSync(rgb2vga_0_vga_pVSync));
endmodule
|
#include <bits/stdc++.h> using namespace std; struct tree { queue<int> a; }; tree num[100005]; long long apple[100005]; int beg = 1; void dfs(int nn, int beg) { if (num[nn].a.empty()) return; while (!num[nn].a.empty()) { int n1 = num[nn].a.front(); num[nn].a.pop(); apple[beg + 1]++; dfs(n1, beg + 1); } } int main() { int number; cin >> number; int num1; memset(apple, 0, sizeof(apple)); apple[1] = 1; for (int i = 2; i <= number; i++) { cin >> num1; num[num1].a.push(i); } long long ans = 0; dfs(1, beg); for (int i = 1; i <= number; i++) { if (apple[i] % 2 != 0) ans++; } cout << ans << endl; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_address_generator #(
parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_ADDR_WIDTH = 32,
parameter BEATS_PER_BURST_WIDTH = 4,
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
parameter LENGTH_WIDTH = 8)(
input clk,
input resetn,
input req_valid,
output reg req_ready,
input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input bl_valid,
output reg bl_ready,
input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
input eot,
input enable,
output reg enabled,
input addr_ready,
output reg addr_valid,
output [DMA_ADDR_WIDTH-1:0] addr,
output [LENGTH_WIDTH-1:0] len,
output [ 2:0] size,
output [ 1:0] burst,
output [ 2:0] prot,
output [ 3:0] cache
);
localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};
localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};
`include "inc_id.vh"
assign burst = 2'b01;
assign prot = 3'b000;
assign cache = 4'b0011;
assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
DMA_DATA_WIDTH == 512 ? 3'b110 :
DMA_DATA_WIDTH == 256 ? 3'b101 :
DMA_DATA_WIDTH == 128 ? 3'b100 :
DMA_DATA_WIDTH == 64 ? 3'b011 :
DMA_DATA_WIDTH == 32 ? 3'b010 :
DMA_DATA_WIDTH == 16 ? 3'b001 : 3'b000;
reg [LENGTH_WIDTH-1:0] length = 'h0;
reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;
reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}};
assign len = length;
reg addr_valid_d1;
reg last = 1'b0;
// If we already asserted addr_valid we have to wait until it is accepted before
// we can disable the address generator.
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else if (enable == 1'b1) begin
enabled <= 1'b1;
end else if (addr_valid == 1'b0) begin
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (bl_valid == 1'b1 && bl_ready == 1'b1) begin
last_burst_len <= measured_last_burst_length;
end
end
always @(posedge clk) begin
if (addr_valid == 1'b0) begin
last <= eot;
if (eot == 1'b1) begin
length <= last_burst_len;
end else begin
length <= MAX_LENGTH;
end
end
end
always @(posedge clk) begin
if (req_ready == 1'b1) begin
address <= req_address;
end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
address <= address + MAX_BEATS_PER_BURST;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
bl_ready <= 1'b1;
end else begin
if (bl_ready == 1'b1) begin
bl_ready <= ~bl_valid;
end else if (addr_valid == 1'b0 && eot == 1'b1) begin
// assert bl_ready only when the addr_valid asserts in the next cycle
if (id != request_id && enable == 1'b1) begin
bl_ready <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
req_ready <= 1'b1;
addr_valid <= 1'b0;
end else begin
if (req_ready == 1'b1) begin
req_ready <= ~req_valid;
end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
addr_valid <= 1'b0;
req_ready <= last;
end else if (id != request_id && enable == 1'b1) begin
// if eot wait until the last_burst_len gets synced over
if (eot == 1'b0 || (eot == 1'b1 && bl_ready == 1'b0)) begin
addr_valid <= 1'b1;
end
end
end
end
always @(posedge clk) begin
addr_valid_d1 <= addr_valid;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else if (addr_valid == 1'b1 && addr_valid_d1 == 1'b0) begin
id <= inc_id(id);
end
end
endmodule
|
`timescale 1ns/1ns
module usb_tx_stuff
(input c,
input d,
input d_empty,
output d_req,
output q,
input q_req,
output q_empty);
localparam ST_IDLE = 4'd0;
localparam ST_READ = 4'd1;
localparam ST_STUFF = 4'd2;
localparam ST_DONE = 4'd3;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [2:0] ones_count;
wire [2:0] done_cnt; // hold the DONE state for a full two bits for downstream
wire done_cnt_rst;
r #(3) done_cnt_r
(.c(c), .rst(done_cnt_rst), .en(1'b1), .d(done_cnt+1'b1), .q(done_cnt));
// todo: clean this up. it got ugly.
always @* begin
case (state)
ST_IDLE:
if (~d_empty) ctrl = { ST_READ , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_READ:
if (d_empty) ctrl = { ST_DONE , 5'b00010 };
else if (q_req)
if (ones_count == 3'd5 & d == 1'b1)
ctrl = { ST_STUFF, 5'b00110 };
else ctrl = { ST_READ , 5'b00011 };
else ctrl = { ST_READ , 5'b00000 };
ST_STUFF:
if (d_empty) ctrl = { ST_DONE , 5'b00011 };
else if (q_req) ctrl = { ST_READ , 5'b00001 };
else ctrl = { ST_STUFF, 5'b00100 };
ST_DONE:
if (done_cnt == 3'h7) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_DONE , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign d_req = ctrl[0];
assign done_cnt_rst = ctrl[1];
wire supress_empty = ctrl[2];
r #(3, 3'd0) ones_count_r
(.c(c), .rst(state == ST_IDLE | (q_req & d == 1'b0) | state == ST_STUFF),
.en(q_req & d == 1'b1),
.d(ones_count + 1'b1), .q(ones_count));
wire nrzi;
wire next_nrzi = (state == ST_STUFF) ? ~nrzi : (d ? nrzi : ~nrzi);
r #(1, 1'b1) nrzi_r
(.c(c), .rst(state == ST_IDLE), .en(state != ST_IDLE & q_req),
.d(next_nrzi), .q(nrzi));
assign q = nrzi;
assign q_empty = d_empty & ~supress_empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T mabs(const T &a) { return a < 0 ? -a : a; } const int mod = 1e9 + 7; const int Row = 14, Mask = 4782969; int D[2][2][Mask]; int setbit[Mask][3]; int getbit[Mask][3]; int p3[20] = {1}; inline int setBit(int mask, int pos, int val) { return (mask / p3[pos + 1] * 3 + val) * p3[pos] + mask % p3[pos]; } inline int getBit(int mask, int pos) { return mask / p3[pos] % 3; } inline int up(int i, int mask) { if (i == 0) return 3; return getbit[mask][i - 1]; } inline int left(int i, int j, int mask) { if (j == 0) return 3; return getbit[mask][i]; } inline void addTo(int &a, int val) { a += val; if (a >= mod) a -= mod; } inline int &next(int flag, int flag2, int i, int n, int mask) { if (i == n - 1) return D[flag ^ 1][0][mask]; return D[flag][flag2 ^ 1][mask]; } void run() { char str[] = { AHIMOTUVWXY }; char A[100100]; scanf( %s , A); bool ok = 1; int n = strlen(A); for (int i = (0), ei = (n / 2); i < ei; i++) if (A[i] != A[n - 1 - i]) ok = 0; for (int i = (0), ei = (n); i < ei; i++) if (strchr(str, A[i]) == 0) ok = 0; puts(ok ? YES : NO ); } int main() { run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int arrmax = 200005; char str[arrmax]; int reversetimes[arrmax / 2]; int main() { int m, a, sum, len; while (~scanf( %s %d , str, &m)) { len = strlen(str); memset(reversetimes, 0, 2 * len); while (m--) { scanf( %d , &a); reversetimes[a - 1]++; } sum = 0; for (int i = 0; i < len / 2; i++) { sum += reversetimes[i]; if (sum & 1) swap(str[i], str[len - i - 1]); } printf( %s n , str); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); char in[n]; int result = 0; scanf( %s , in); for (int i = 0; i < n; i++) { if (in[i] == < ) { result++; } else { break; } } for (int i = n - 1; i >= 0; i--) { if (in[i] == > ) { result++; } else { break; } } printf( %d n , result); }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
//
// Summary:
//
// The RESOURCE_SHARING_CONTROL module allocates the BIT_ALIGN_MACHINE
// module to each of the 16 data channels of the interface. Each channel
// must be aligned one at a time, such that the RESOURCE_SHARING_CONTROL module
// must determine when training on a given channel is complete, and then
// switch the context to the next channel.
//
//----------------------------------------------------------------
module RCB_FRL_RESOURCE_SHARING_CONTROL
(
CHAN_SEL,
ALL_CHANNELS_ALIGNED,
DATA_ALIGNED,
START_ALIGN,
CLK,
RST
);
input DATA_ALIGNED; //FLAG: ALIGNMENT DONE ON CURRENT CHANNEL, GO TO NEXT
input CLK; //CLOCK
input RST; //RESET
output [3:0] CHAN_SEL; //VECTOR INDICATING CURRENT CHANNEL BEING ALIGNED
output START_ALIGN; //SIGNAL THAT ALIGNMENT PROCESS MAY BEGIN ON NEXT CHANNEL
output ALL_CHANNELS_ALIGNED; //SIGNAL THAT ALL CHANNELS ARE ALIGNED
wire [6:0] COUNT_VALUE;
reg UD_DELAY;
reg COUNT_DELAY;
reg COUNT_CHAN;
reg START_ALIGN;
reg [2:0] CS;
reg [2:0] NS;
parameter INIT = 3'b000;
parameter INC_CHAN_SEL = 3'b001;
parameter WAIT_8 = 3'b010;
parameter START_NEXT = 3'b011;
parameter LAST_CHAN = 3'b100;
parameter TRAIN_DONE = 3'b101;
parameter IDLE = 3'b110;
parameter START_LAST = 3'b111;
assign ALL_CHANNELS_ALIGNED = CS[2] & ~CS[1] & CS[0];
RCB_FRL_count_to_128 delay_counter(
.clk(CLK), .rst(RST), .count(COUNT_DELAY), .ud(UD_DELAY), .counter_value(COUNT_VALUE));
RCB_FRL_count_to_16x channel_counter(
.clk(CLK), .rst(RST), .count(COUNT_CHAN), .counter_value(CHAN_SEL));
//CURRENT STATE LOGIC
always @(posedge CLK) begin
if (RST == 1'b1)
CS <= INIT;
else
CS <= NS;
end
//NEXT_STATE LOGIC
always @(CS or DATA_ALIGNED or COUNT_VALUE or CHAN_SEL) begin
case (CS)
INIT: begin
if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
NS <= INIT;
else
NS <= IDLE;
end
IDLE: NS <= INC_CHAN_SEL;
INC_CHAN_SEL: NS <= WAIT_8;
WAIT_8: begin
if (COUNT_VALUE < 7'h08)
NS <= WAIT_8;
else
if (CHAN_SEL == 4'b0100)
NS <= START_LAST;
else
NS <= START_NEXT;
end
START_NEXT: NS <= INIT;
START_LAST: NS <= LAST_CHAN;
LAST_CHAN: begin
if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
NS <= LAST_CHAN;
else
NS <= TRAIN_DONE;
end
TRAIN_DONE: NS <= TRAIN_DONE;
default: NS <= INIT;
endcase
end
//OUTPUT LOGIC
always @(CS) begin
case (CS)
INIT: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b1;
UD_DELAY <= 1'b1;
START_ALIGN <= 1'b0;
end
IDLE: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
INC_CHAN_SEL: begin
COUNT_CHAN <= 1'b1;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
WAIT_8: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b1;
UD_DELAY <= 1'b1;
START_ALIGN <= 1'b0;
end
START_NEXT: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b1;
end
START_LAST: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b1;
end
LAST_CHAN: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b1;
UD_DELAY <= 1'b1;
START_ALIGN <= 1'b0;
end
TRAIN_DONE: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
default: begin
COUNT_CHAN <= 1'b1; /////////////////////////
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; using ll = long long; using ld = long double; const int MOD = 1e9 + 7, inf = 1e9, N = 2e5 + 1; const ll INF = 1e18; ld tic, tac; void solve() { int n, count = 0; cin >> n; int i, a[n]; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 1) count++; } cout << count << n ; for (i = 1; i < n; i++) { if (a[i] == 1) { cout << a[i - 1] << ; } } cout << a[n - 1] << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_TB_V
`define SKY130_FD_SC_HD__DIODE_TB_V
/**
* diode: Antenna tie-down diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__diode.v"
module top();
// Inputs are registered
reg DIODE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
DIODE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 DIODE = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 DIODE = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 DIODE = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 DIODE = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 DIODE = 1'bx;
end
sky130_fd_sc_hd__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_TB_V
|
#include <bits/stdc++.h> using namespace std; long long f[55]; int a[55]; int main() { int n, i; long long k; f[1] = 1, f[2] = 2; for (i = 3; i <= 50; i++) f[i] = f[i - 1] + f[i - 2]; while (scanf( %d%lld , &n, &k) == 2) { for (i = 1; i <= n;) { if (k <= f[n - i] || i == n) { a[i] = i; i++; } else { k = k - f[n - i]; a[i] = i + 1; i++; a[i] = i - 1; i++; } } for (i = 1; i <= n; i++) printf( %d%c , a[i], (i == n) ? n : ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll MOD = 1e9 + 7, N = 1e5 + 10; void test() { ll n, m; cin >> n >> m; vector<vector<ll>> a(n, vector<ll>(m)); ll cnt = 0; for (ll i = 0; i < n; ++i) { for (ll j = 0; j < m; ++j) { char c; cin >> c; a[i][j] = c - 0 ; } } vector<array<ll, 6>> R; if (n & 1) { for (ll i = 0; i < m; ++i) { if (a[n - 1][i]) { if (i != m - 1) { R.push_back({n - 1, i, n - 2, i, n - 2, i + 1}); a[n - 2][i + 1] ^= 1; } else { R.push_back({n - 1, i, n - 2, i, n - 2, i - 1}); a[n - 2][i - 1] ^= 1; } a[n - 1][i] ^= 1; a[n - 2][i] ^= 1; } } --n; } if (m & 1) { for (ll i = 0; i < n; ++i) { if (a[i][m - 1]) { if (i != n - 1) { R.push_back({i, m - 1, i, m - 2, i + 1, m - 2}); a[i + 1][m - 2] ^= 1; } else { R.push_back({i, m - 1, i, m - 2, i - 1, m - 2}); a[i - 1][m - 2] ^= 1; } a[i][m - 1] ^= 1; a[i][m - 2] ^= 1; } } --m; } auto solve = [&](vector<vector<ll>> a) { vector<array<ll, 6>> res; ll cnt = 0; for (ll i = 0; i < 2; ++i) { for (ll j = 0; j < 2; ++j) { cnt += a[i][j]; } } if (cnt == 4) { res.push_back({0, 0, 1, 0, 1, 1}); res.push_back({0, 1, 1, 0, 1, 1}); res.push_back({1, 0, 0, 0, 0, 1}); res.push_back({1, 1, 0, 0, 0, 1}); } else if (cnt == 3) { array<ll, 6> r; ll c = 0; for (ll i = 0; i < 2; ++i) { for (ll j = 0; j < 2; ++j) { if (a[i][j]) { r[c++] = i; r[c++] = j; } } } res.push_back(r); } else if (cnt == 2) { vector<array<ll, 2>> is, no; for (ll i = 0; i < 2; ++i) { for (ll j = 0; j < 2; ++j) { if (a[i][j]) { is.push_back({i, j}); } else { no.push_back({i, j}); } } } for (auto [x, y] : is) { array<ll, 6> r; ll c = 0; r[c++] = x; r[c++] = y; for (auto [x, y] : no) { r[c++] = x; r[c++] = y; } res.push_back(r); } } else if (cnt == 1) { vector<array<ll, 2>> is, no; for (ll i = 0; i < 2; ++i) { for (ll j = 0; j < 2; ++j) { if (a[i][j]) { is.push_back({i, j}); } else { no.push_back({i, j}); } } } for (ll i = 0; i < 3; ++i) { array<ll, 6> r; ll c = 0; r[c++] = is.back()[0]; r[c++] = is.back()[1]; for (ll j = 0; j < 2; ++j) { r[c++] = no[j][0]; r[c++] = no[j][1]; } auto bk = no.back(); no.pop_back(); no.insert(no.begin(), bk); res.push_back(r); } } return res; }; for (ll i = 0; i < n; i += 2) { for (ll j = 0; j < m; j += 2) { vector<vector<ll>> K = {{a[i][j], a[i][j + 1]}, {a[i + 1][j], a[i + 1][j + 1]}}; auto res = solve(K); for (auto r : res) { for (ll k = 0; k < 6; ++k) { if (k & 1) { r[k] += j; } else { r[k] += i; } } R.push_back(r); } } } cout << R.size() << n ; for (auto i : R) { for (ll j = 0; j < 6; ++j) { cout << i[j] + 1 << ; } cout << n ; } return; } int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); ll tt = 1; cin >> tt; for (ll i = 0; i < tt; i++) test(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve_test() { string s; cin >> s; int n = int(s.length()); int total = 0; long long ans = 0; for (int i = 0; i < n; i++) { if (s[i] == + ) total++; else total--; if (total < 0) { total++; ans += i + 1; } } cout << ans + n << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tests = 1; cin >> tests; while (tests--) solve_test(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 840; long long arr[9], W, ans; long long dp[7890]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> W; for (int i = 1; i < 9; ++i) { cin >> arr[i]; } if (W > 840) { for (int i = 1; i < 9; ++i) { long long lef = max(arr[i] - 840 / i, (long long)0); long long g = (W - 840 - ans) / i; g = min(g, lef); if (g < 0) continue; ans += g * i; arr[i] -= g; } } dp[0] = 1; for (int i = 1; i < 9; ++i) { for (int j = 0; j < min(arr[i], (long long)840 / i); ++j) { for (int k = 6789; k >= i; --k) { if (dp[k - i]) dp[k] = 1; } } } for (int k = 6789;; --k) { if (dp[k] && ans + k <= W) { cout << ans + k << n ; return 0; } } }
|
`timescale 1ns/1ns
module op_usmod
(input c,
input [15:0] a,
input [15:0] b,
output [15:0] q,
input start,
output done);
// register the inputs to help timing
wire [15:0] a_i, b_i;
d1 #(16) a_i_r(.c(c), .d(a), .q(a_i));
d1 #(16) b_i_r(.c(c), .d(b), .q(b_i));
lpm_divide
#(.lpm_widthn(16),
.lpm_widthd(16),
.lpm_nrepresentation("UNSIGNED"),
.lpm_drepresentation("UNSIGNED"),
.lpm_hint("LPM_REMAINDERPOSITIVE=TRUE"),
.lpm_pipeline(8) // not sure what's best here
) div_inst
(.numer(a_i), .denom(b_i), .clock(c), .clken(1'b1), .aclr(1'b0),
.quotient(), .remain(q));
wire [4:0] cnt;
r #(5) cnt_r
(.c(c), .rst(1'b0), .en(|cnt | start), .d(start ? 5'h1 : cnt+1'b1), .q(cnt));
assign done = cnt == 5'd10; // not sure what this should be
endmodule
////////////////////////////////////////////////////////////////////
`ifdef test_div
module div_tb();
reg [31:0] a, b;
wire [31:0] q;
reg start;
wire done;
wire c;
sim_clk #(125) clk_125(.clk(c));
div dut(.*);
initial begin
$dumpfile("div.lxt");
$dumpvars();
start = 1'b0;
a = 32'h3f80_0000; // 1.0
b = 32'h3fcc_b55a; // 1.59928441047
wait(~c);
wait(c);
start <= 1'b1;
wait(~c);
wait(c);
start <= 1'b0;
#10000;
$finish();
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool sortinrev(const pair<int, int> &a, const pair<int, int> &b) { return (a.first > b.first); } double gcd(double a, double b) { if (b == 0) return a; return gcd(b, double(int(a) % int(b))); } long long int power(long long int b, long long int e, long long int m) { if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int a; cin >> a; ; long long int b; cin >> b; ; long long int c; cin >> c; ; long long int d; cin >> d; ; long long int e; cin >> e; ; long long int f; cin >> f; ; long long int z = 0, ans = 0; if (f >= e) { z = min(c, d); z = min(z, b); ans += (f * z); d -= z; z = min(d, a); ans += (e * z); } else { z = min(a, d); ans += (e * z); d -= z; z = min(b, c); z = min(z, d); ans += (f * z); } cout << ans << endl; return 0; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
// Generate the ecc code. Note that the synthesizer should
// generate this as a static logic. Code in this block should
// never run during simulation phase, or directly impact timing.
//
// The code generated is a single correct, double detect code.
// It is the classic Hamming code. Instead, the code is
// optimized for minimal/balanced tree depth and size. See
// Hsiao IBM Technial Journal 1970.
//
// The code is returned as a single bit vector, h_rows. This was
// the only way to "subroutinize" this with the restrictions of
// disallowed include files and that matrices cannot be passed
// in ports.
//
// Factorial and the combos functions are defined. Combos
// simply computes the number of combinations from the set
// size and elements at a time.
//
// The function next_combo computes the next combination in
// lexicographical order given the "current" combination. Its
// output is undefined if given the last combination in the
// lexicographical order.
//
// next_combo is insensitive to the number of elements in the
// combinations.
//
// An H transpose matrix is generated because that's the easiest
// way to do it. The H transpose matrix is generated by taking
// the one at a time combinations, then the 3 at a time, then
// the 5 at a time. The number combinations used is equal to
// the width of the code (CODE_WIDTH). The boundaries between
// the 1, 3 and 5 groups are hardcoded in the for loop.
//
// At the same time the h_rows vector is generated from the
// H transpose matrix.
module ecc_gen
#(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial (input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index=2; index<=i; index=index+1)
factorial = factorial * index;
end
endfunction // factorial
function integer combos (input integer n, k);
combos = factorial(n)/(factorial(k)*factorial(n-k));
endfunction // combinations
// function next_combo
// Given a combination, return the next combo in lexicographical
// order. Scans from right to left. Assumes the first combination
// is k ones all of the way to the left.
//
// Upon entry, initialize seen0, trig1, and ones. "seen0" means
// that a zero has been observed while scanning from right to left.
// "trig1" means that a one have been observed _after_ seen0 is set.
// "ones" counts the number of ones observed while scanning the input.
//
// If trig1 is one, just copy the input bit to the output and increment
// to the next bit. Otherwise set the the output bit to zero, if the
// input is a one, increment ones. If the input bit is a one and seen0
// is true, dump out the accumulated ones. Set seen0 to the complement
// of the input bit. Note that seen0 is not used subsequent to trig1
// getting set.
function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);
integer index;
integer dump_index;
reg seen0;
reg trig1;
// integer ones;
reg [ECC_WIDTH-1:0] ones;
begin
seen0 = 1'b0;
trig1 = 1'b0;
ones = 0;
for (index=0; index<ECC_WIDTH; index=index+1)
begin
// The "== 1'bx" is so this will converge at time zero.
// XST assumes false, which should be OK.
if ((&i == 1'bx) || trig1) next_combo[index] = i[index];
else begin
next_combo[index] = 1'b0;
ones = ones + i[index];
if (i[index] && seen0) begin
trig1 = 1'b1;
for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
if (dump_index>=index-ones) next_combo[dump_index] = 1'b1;
end
seen0 = ~i[index];
end // else: !if(trig1)
end
end // function
endfunction // next_combo
wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];
output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
localparam COMBOS_3 = combos(ECC_WIDTH, 3);
localparam COMBOS_5 = combos(ECC_WIDTH, 5);
genvar n;
genvar s;
generate
for (n=0; n<CODE_WIDTH; n=n+1) begin : ht
if (n == 0)
assign ht_matrix[n] = {{3{1'b1}}, {ECC_WIDTH-3{1'b0}}};
else if (n == COMBOS_3 && n < DATA_WIDTH)
assign ht_matrix[n] = {{5{1'b1}}, {ECC_WIDTH-5{1'b0}}};
else if ((n == COMBOS_3+COMBOS_5) && n < DATA_WIDTH)
assign ht_matrix[n] = {{7{1'b1}}, {ECC_WIDTH-7{1'b0}}};
else if (n == DATA_WIDTH)
assign ht_matrix[n] = {{1{1'b1}}, {ECC_WIDTH-1{1'b0}}};
else assign ht_matrix[n] = next_combo(ht_matrix[n-1]);
for (s=0; s<ECC_WIDTH; s=s+1) begin : h_row
assign h_rows[s*CODE_WIDTH+n] = ht_matrix[n][s];
end
end
endgenerate
endmodule // ecc_gen
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 12:23:49
// Design Name:
// Module Name: carry_look_ahead_adder_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module carry_look_ahead_adder_tb(
);
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] s;
wire [3:0] p;
wire [3:0] g;
wire [3:0] c;
integer i;
integer j;
carry_look_ahead_adder DUT (.a(a), .b(b), .cin(cin), .cout(cout), .s(s), .p(p), .g(g), .c(c));
initial begin
a = 0; b = 0; cin = 0;
for (i = 0 ; i < 16; i = i + 1) begin
#10 a = i;
for (j = 0; j < 16; j = j + 1) begin
#10 b = j;
end
end
#10 cin = 1;
for (i = 0 ; i < 16; i = i + 1) begin
#10 a = i;
for (j = 0; j < 16; j = j + 1) begin
#10 b = j;
end
end
#20;
end
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module clock_reduce(
input clk,
input reset_n,
input [2:0] clock_sel,
output clk_reduced,
output clk_100_reduced
);
reg [10:0] counter;
reg [10:0] counter_100;
assign clk_reduced = clk_reduced_p | clk_reduced_n;
assign clk_100_reduced = clk_100_reduced_p | clk_100_reduced_n;
reg clk_reduced_i;
reg clk_100_reduced_i;
reg clk_reduced_p;
reg clk_100_reduced_p;
reg clk_reduced_n;
reg clk_100_reduced_n;
always@(*)
begin
clk_reduced_p = 1'b0;
if(clk_reduced_i)
begin
clk_reduced_p = 1'b1;
end
end
always@(*)
begin
clk_reduced_n = 1'b1;
if(!clk_reduced_i)
begin
clk_reduced_n = 1'b0;
end
end
always@(*)
begin
clk_100_reduced_p = 1'b0;
if(clk_100_reduced_i)
begin
clk_100_reduced_p = 1'b1;
end
end
always@(*)
begin
clk_100_reduced_n = 1'b1;
if(!clk_100_reduced_i)
begin
clk_100_reduced_n = 1'b0;
end
end
always@(posedge clk)
begin
if(!reset_n)
begin
counter <= 11'd0;
counter_100 <= 11'd0;
clk_reduced_i <= 1'b0;
clk_100_reduced_i <= 1'b0;
end
else
begin
case(clock_sel)
3'd0://2mhz - 500 ns
begin
if(counter >=11'd0 && counter <=11'd99 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd100 && counter <=11'd199 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd1://5mhz
begin
if(counter >=11'd0 && counter <=11'd39 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd40 && counter <=11'd79 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd2://10mhz
begin
if(counter >=11'd0 && counter <=11'd19 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd20 && counter <=11'd39 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd3://50mhz
begin
if(counter >=11'd0 && counter <=11'd3 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd4 && counter <=11'd7)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd4://100mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd2 && counter <=11'd4)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd5://150mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd2 && counter <=11'd3)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd6://200mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter == 11'd2)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd7://300mhz
begin
if(counter ==11'd0 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter ==11'd1)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
endcase
if(counter_100 >=11'd0 && counter_100 <=11'd1 )
begin
clk_100_reduced_i <= 1'b1;
counter_100 <= counter_100 + 11'd1;
end
else if(counter_100 >=11'd2 && counter_100 <=11'd4)
begin
clk_100_reduced_i <= 1'b0;
counter_100 <= counter_100 + 11'd1;
end
else
begin
clk_100_reduced_i <= 1'b1;
counter_100 <= 11'd0;
end
end
end
endmodule
|
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