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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds_1 #(
// parameters
parameter DDS_TYPE = 1,
parameter DDS_D_DW = 16,
parameter DDS_P_DW = 16) (
// interface
input clk,
input [DDS_P_DW-1:0] angle,
input [ 15:0] scale,
output reg [DDS_D_DW-1:0] dds_data);
// local parameters
localparam DDS_CORDIC_TYPE = 1;
localparam DDS_POLINOMIAL_TYPE = 2;
// internal signals
wire [ DDS_D_DW-1:0] sine_s;
wire [DDS_D_DW+17:0] s1_data_s;
// sine
generate
if (DDS_TYPE == DDS_CORDIC_TYPE) begin
ad_dds_sine_cordic #(
.CORDIC_DW(DDS_D_DW),
.PHASE_DW(DDS_P_DW),
.DELAY_DW(1))
i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.cosine (),
.ddata_in (1'b0),
.ddata_out ());
end else begin
ad_dds_sine i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.ddata_in (1'b0),
.ddata_out ());
end
endgenerate
// scale for a sine generator
ad_mul #(
.A_DATA_WIDTH(DDS_D_DW + 1),
.B_DATA_WIDTH(17),
.DELAY_DATA_WIDTH(1))
i_dds_scale (
.clk (clk),
.data_a ({sine_s[DDS_D_DW-1], sine_s}),
.data_b ({scale[15], scale}),
.data_p (s1_data_s),
.ddata_in (1'b0),
.ddata_out ());
// dds data
always @(posedge clk) begin
//15'h8000 is the maximum scale
dds_data <= s1_data_s[DDS_D_DW+13:14];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Tick Timer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// TT according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_tt.v,v $
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/02/12 01:33:47 lampret
// No longer using async rst as sync reset for the counter.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:00:49 lampret
// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
//
// Revision 1.9 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_tt(
// RISC Internal Interface
clk, rst, du_stall,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
intr
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input du_stall; // DU stall
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output intr; // Interrupt output
`ifdef OR1200_TT_IMPLEMENTED
//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg [31:0] ttmr; // TTMR bits
`else
wire [31:0] ttmr; // No TTMR register
`endif
//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg [31:0] ttcr; // TTCR bits
`else
wire [31:0] ttcr; // No TTCR register
`endif
//
// Internal wires & regs
//
wire ttmr_sel; // TTMR select
wire ttcr_sel; // TTCR select
wire match; // Asserted when TTMR[TP]
// is equal to TTCR[27:0]
wire restart; // Restart counter when asserted
wire stop; // Stop counter when asserted
reg [31:0] spr_dat_o; // SPR data out
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR
always @(posedge clk or posedge rst)
if (rst)
ttmr <= 32'b0;
else if (ttmr_sel && spr_write)
ttmr <= #1 spr_dat_i;
else if (ttmr[`OR1200_TT_TTMR_IE])
ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
`else
assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
`endif
//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR
always @(posedge clk or posedge rst)
if (rst)
ttcr <= 32'b0;
else if (restart)
ttcr <= #1 32'b0;
else if (ttcr_sel && spr_write)
ttcr <= #1 spr_dat_i;
else if (!stop)
ttcr <= #1 ttcr + 32'd1;
`else
assign ttcr = 32'b0;
`endif
//
// Read TT registers
//
always @(spr_addr or ttmr or ttcr)
case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_TT_READREGS
`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
default: spr_dat_o = ttcr;
endcase
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
//
// Restart when match and TTMR[M]==0x1
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
`else
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;
//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string x; deque<char> vec; int c; bool flag; int max = 0; for (int i = 0; i < 8; i++) { cin >> x; for (int j = 0; j < x.length(); j++) vec.push_back(x[j]); if (i % 2 == 0) { c = 0; while (true) { c++; flag = true; for (int j = 1; j < x.length(); j++) { if (x[j] == x[j - 1]) { flag = false; char temp = vec.back(); vec.pop_back(); vec.push_front(temp); break; } } if (c == 9 || flag == true) break; } } else if (i % 2 != 0) { c = 0; while (true) { c++; flag = true; for (int j = 1; j < x.length(); j++) { if (x[j] == x[j - 1]) { flag = false; char temp = vec.back(); vec.pop_back(); vec.push_front(temp); break; } } if (c == 9 || flag == true) break; } } if (c > max) max = c; } if (flag == false || max == 9) cout << NO ; else cout << YES ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void next_int(T &x) { x = 0; char c; bool neg = false; while (!isdigit(c = getchar())) if (c == - ) neg = true; do x = x * 10 + c - 48; while (isdigit(c = getchar())); if (neg) x = -x; } template <typename T> inline void write_int(T x, char last = 0) { if (x < 0) putchar( - ), x = abs(x); char tmp[20]; int cnt = 0; while (x >= 10) tmp[cnt++] = x % 10 + 48, x /= 10; tmp[cnt] = x + 48; for (int i = (cnt); i >= (0); --i) putchar(tmp[i]); if (last) putchar(last); } struct Line { long long a, b; Line(long long _a, long long _b) : a(_a), b(_b) {} }; const int N = (int)2e5 + 5; vector<Line> hull; int n; long long a[N], sum[N], sum2[N]; bool bad(Line l1, Line l2, Line l3) { return (l1.b - l3.b) * (l2.a - l1.a) <= (l3.a - l1.a) * (l1.b - l2.b); } void add(Line x) { while (((int)hull.size()) >= 2 && bad(hull[((int)hull.size()) - 2], hull[((int)hull.size()) - 1], x)) hull.pop_back(); hull.push_back(x); } long long getval(int pos, long long x) { if (pos >= ((int)hull.size())) return (long long)1e18 + 7; return hull[pos].a * x + hull[pos].b; } long long read(long long x) { int lo = 0, hi = ((int)hull.size()) - 1, mid; while (lo != hi) { mid = (lo + hi) >> 1; if (getval(mid, x) <= getval(mid + 1, x)) hi = mid; else lo = mid + 1; } return getval(lo, x); } int main() { next_int(n); for (int i = (1); i <= (n); ++i) { next_int(a[i]); sum[i] = sum[i - 1] + a[i]; sum2[i] = sum2[i - 1] + (long long)i * a[i]; } add(Line(0, 0)); long long res = 0; for (int i = (1); i <= (n); ++i) { res = max(res, -read(-sum[i]) + sum2[i]); add(Line(-i, sum2[i] - (long long)i * sum[i])); } write_int(res); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_t.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
sig_i_a,
sig_i_a2,
sig_i_ae,
sig_o_a,
sig_o_a2,
sig_o_ae
);
// Generated Module Inputs:
input sig_i_a;
input sig_i_a2;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output sig_o_a;
output sig_o_a2;
output [7:0] sig_o_ae;
// Generated Wires:
wire sig_i_a;
wire sig_i_a2;
wire [6:0] sig_i_ae;
wire sig_o_a;
wire sig_o_a2;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
// __I_OUT_OPEN wire [4:0] sig_13; // __W_BAD_BRANCH
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_clock_mon #(
parameter TOTAL_WIDTH = 32
) (
// processor interface
input up_rstn,
input up_clk,
output reg [TOTAL_WIDTH-1:0] up_d_count,
// device interface
input d_rst,
input d_clk);
// internal registers
reg [15:0] up_count = 'd1;
reg up_count_run = 'd0;
reg up_count_running_m1 = 'd0;
reg up_count_running_m2 = 'd0;
reg up_count_running_m3 = 'd0;
reg d_count_run_m1 = 'd0;
reg d_count_run_m2 = 'd0;
reg d_count_run_m3 = 'd0;
reg [TOTAL_WIDTH:0] d_count = 'd0;
// internal signals
wire up_count_capture_s;
wire d_count_reset_s;
// processor reference
// Capture on the falling edge of running
assign up_count_capture_s = up_count_running_m3 == 1'b1 && up_count_running_m2 == 1'b0;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_count_running_m1 <= 1'b0;
up_count_running_m2 <= 1'b0;
up_count_running_m3 <= 1'b0;
end else begin
up_count_running_m1 <= d_count_run_m3;
up_count_running_m2 <= up_count_running_m1;
up_count_running_m3 <= up_count_running_m2;
end
end
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_d_count <= 'd0;
up_count_run <= 1'b0;
end else begin
if (up_count_running_m3 == 1'b0) begin
up_count_run <= 1'b1;
end else if (up_count == 'h00) begin
up_count_run <= 1'b0;
end
if (up_count_capture_s == 1'b1) begin
up_d_count <= d_count[TOTAL_WIDTH-1:0];
end else if (up_count == 'h00 && up_count_run != up_count_running_m3) begin
up_d_count <= 'h00;
end
end
end
always @(posedge up_clk) begin
if (up_count_run == 1'b0 && up_count_running_m3 == 1'b0) begin
up_count <= 'h01;
end else begin
up_count <= up_count + 1'b1;
end
end
// device free running
// Reset on the rising edge of run
assign d_count_reset_s = d_count_run_m3 == 1'b0 && d_count_run_m2 == 1'b1;
always @(posedge d_clk or posedge d_rst) begin
if (d_rst == 1'b1) begin
d_count_run_m1 <= 1'b0;
d_count_run_m2 <= 1'b0;
d_count_run_m3 <= 1'b0;
end else begin
d_count_run_m1 <= up_count_run;
d_count_run_m2 <= d_count_run_m1;
d_count_run_m3 <= d_count_run_m2;
end
end
always @(posedge d_clk) begin
if (d_count_reset_s == 1'b1) begin
d_count <= 'h00;
end else if (d_count_run_m3 == 1'b1) begin
if (d_count[TOTAL_WIDTH] == 1'b0) begin
d_count <= d_count + 1'b1;
end else begin
d_count <= {TOTAL_WIDTH+1{1'b1}};
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 10; const int N = 5e5 + 10; const int INF = 0x3f3f3f3f; const long long mod = 1e9 + 7, G = 3; const int base = 30000; int t; int n, m, k; int dp[35][35][55]; int dfs(int n, int m, int k) { if (k == 0 || n * m == k) return 0; if (dp[n][m][k] != -1) return dp[n][m][k]; int ret = INF; for (int i = 1; i < n; ++i) for (int j = 0; j <= k; ++j) ret = min(ret, dfs(i, m, j) + dfs(n - i, m, k - j) + m * m); for (int i = 1; i < m; ++i) for (int j = 0; j <= k; ++j) ret = min(ret, dfs(n, i, j) + dfs(n, m - i, k - j) + n * n); if (dp[n][m][k] == -1) dp[n][m][k] = ret; return ret; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> t; memset(dp, -1, sizeof(dp)); while (t--) { cin >> n >> m >> k; cout << dfs(n, m, k) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool isPal(string s, long long l, long long r) { while (l < r) { if (s[l] != s[r]) return false; l++; r--; } return true; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; string s; cin >> s; long long ans = 0; for (long long i = 0; i < s.size(); i++) { for (long long j = i; j < s.size(); j++) { if (!isPal(s, i, j)) { if (ans < j - i + 1) ans = j - i + 1; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; long long n = s.size(); for (long long i = 0; i < n; i++) { if (s[i] == r ) { cout << i + 1 << n ; } } for (long long i = n - 1; i >= 0; i--) { if (s[i] == l ) { cout << i + 1 << n ; } } }
|
#include <bits/stdc++.h> using namespace std; const int m = 10000 * 100000 + 7; int main() { string s; cin >> s; int n = s.length(); long long p = 0, q = 1; for (int i = n - 1; i > 0; --i) { if (s[i] == 1 ) p = (p + q) % m; q = q * 2 % m; } if (s[0] == 1 ) p = (p + q) % m; cout << p * q % m; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_SYMBOL_V
|
#include <bits/stdc++.h> template <class _T> bool maximize(_T &a, _T b) { return a < b ? a = b, 1 : 0; } template <class _T> bool minimize(_T &a, _T b) { return a > b ? a = b, 1 : 0; } const int ooit = 2e9; const long long ooll = 1e15; using namespace std; int n, q, a[200005]; void enter() { cin >> n >> q; for (int i = 1; i <= n; i++) { char c; cin >> c; a[i] = (int)c; } } set<int> pos[256]; struct BIT { int val[200005]; void update(int i, int x, int n) { for (; i <= n; i += i & -i) val[i] += x; } int get(int i) { int res = 0; for (; i > 0; i -= i & -i) res += val[i]; return res; } } tree; void prepare() { for (int i = 1; i <= n; i++) pos[a[i]].insert(i), tree.update(i, 1, n); } int tfind(int x) { int l = 1, r = n, res = -1; while (l <= r) { int mid = (l + r) / 2; if (tree.get(mid) >= x) r = mid - 1, res = mid; else l = mid + 1; } return res; } bool is_remove[200005]; void update(int l, int r, int x) { auto it_down = pos[x].lower_bound(l); if (it_down == pos[x].end()) return; auto it_up = pos[x].upper_bound(r); vector<int> must_remove; for (; it_down != it_up; it_down++) must_remove.push_back(*it_down); for (auto i : must_remove) { pos[x].erase(i); tree.update(i, -1, n); is_remove[i] = true; } } void process() { prepare(); for (int i = 1; i <= q; i++) { int l, r, cx; char c; cin >> l >> r >> c; cx = (int)c; int tl = tfind(l), tr = tfind(r); update(tl, tr, cx); } for (int i = 1; i <= n; i++) if (!is_remove[i]) cout << (char)a[i]; cout << endl; } int main() { enter(); process(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_1_V
`define SKY130_FD_SC_LS__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, m, n, boys[105], girls[105]; while (cin >> n >> m) { memset(boys, 0, sizeof(boys)); memset(girls, 0, sizeof(girls)); cin >> k; while (k--) { cin >> j; boys[j] = 1; } cin >> k; while (k--) { cin >> j; girls[j] = 1; } int sqr = max(n, m); sqr = sqr * sqr; for (i = 0; i < sqr; i++) { j = (i % n); k = (i % m); boys[j] = (boys[j] || girls[k]); girls[k] = (boys[j] || girls[k]); } bool possible = true; for (i = 0; i < n; i++) { if (boys[i] == 0) possible = false; } for (i = 0; i < m; i++) { if (girls[i] == 0) possible = false; } if (possible) cout << Yes n ; else cout << No n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T sum = 0, fl = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) fl = -1; for (; isdigit(ch); ch = getchar()) sum = (sum << 3) + (sum << 1) + ch - 0 ; return sum * fl; } const int maxn = 5000 + 5; const int maxm = 1e5 + 5; int n, m, k, c; long long mx[maxn]; bool del[maxm << 1], no[maxm]; int fa[maxn], id[maxm << 1]; vector<int> vec, E; int he[maxn], ne[maxm << 1], to[maxm << 1], w[maxm << 1]; struct EDGE { int u, v, w, id; } e[maxm]; bool operator<(const EDGE& a, const EDGE& b) { return a.w < b.w; } void add_edge(int u, int v, int val) { ne[++c] = he[u]; he[u] = c; to[c] = v; w[c] = val; ne[++c] = he[v]; he[v] = c; to[c] = u; w[c] = val; } int find(int first) { return fa[first] == first ? first : fa[first] = find(fa[first]); } void forest() { for (int i = 1; i <= n; ++i) fa[i] = i; sort(e + 1, e + m + 1); for (int i = 1; i <= m; ++i) { int u = find(e[i].u), v = find(e[i].v); if (u == v || u == 1 || v == 1) continue; fa[u] = v; E.push_back(e[i].id); add_edge(e[i].u, e[i].v, e[i].w); id[c] = id[c - 1] = e[i].id; } } void get_max(int p, int f) { for (int i = he[p]; i; i = ne[i]) { if (to[i] == f || del[i] || to[i] == 1) continue; if (w[i] >= w[mx[p]]) mx[to[i]] = i; else mx[to[i]] = mx[p]; get_max(to[i], p); } } void Solve() { n = read<int>(), m = read<int>(), k = read<int>(); c = 1; for (int i = 1; i <= m; ++i) e[i] = (EDGE){read<int>(), read<int>(), read<int>(), i}; forest(); for (int i = 1; i <= m; ++i) { if (e[i].u != 1 && e[i].v != 1) continue; int u = find(e[i].u), v = find(e[i].v); if (u == v) vec.push_back(i); else fa[u] = v, add_edge(e[i].u, e[i].v, e[i].w), E.push_back(e[i].id), --k; } for (int i = 2; i <= n; ++i) if (find(i) != find(i - 1)) return (void)printf( -1 ); if (k < 0) return (void)printf( -1 ); for (int i = 1; i <= k; ++i) { memset(mx, 0, sizeof(mx)); for (int j = he[1]; j; j = ne[j]) get_max(to[j], 1); int now = -1, ans = 2147483647; for (int j = vec.size() - 1; j >= 0; --j) { int p = vec[j], var = max(e[p].u, e[p].v); if (e[p].w - w[mx[var]] < ans) ans = e[p].w - w[mx[var]], now = j; } int p = vec[now], var = e[p].u == 1 ? e[p].v : e[p].u; add_edge(e[p].v, e[p].u, e[p].w); E.push_back(e[p].id); no[id[mx[var]]] = 1; del[mx[var]] = del[mx[var] ^ 1] = 1; vec.erase(vec.begin() + now); } printf( %d n , n - 1); for (int i = E.size() - 1; i >= 0; --i) if (!no[E[i]]) printf( %d , E[i]); } int main() { Solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> int len(const T& a) { return a.size(); } using ll = long long; constexpr long double EPS = 1e-7; long double Check(const vector<long double>& a, long double x) { vector<long double> new_a(a.size()); long double bestmin = 1e8, curmin = 0; long double bestmax = -1e8, curmax = 0; for (int i = 0; i < len(a); ++i) { new_a[i] = (long double)a[i] - x; curmax = max((long double)0, curmax + new_a[i]); bestmax = max(bestmax, curmax); curmin = min((long double)0, curmin + new_a[i]); bestmin = min(bestmin, curmin); } return max(abs(bestmin), abs(bestmax)); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << fixed << setprecision(6); int n; cin >> n; vector<long double> a(n); for (auto& i : a) cin >> i; long double l = -1e4 - 10, r = 1e4 + 10; for (int step = 0; step < 200; ++step) { long double m1 = l + (r - l) / 3.0; long double m2 = r - (r - l) / 3.0; if (Check(a, m1) - Check(a, m2) > EPS) { l = m1; } else { r = m2; } } cout << Check(a, l); return 0; }
|
// megafunction wizard: %LPM_DIVIDE%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: alt_div.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module alt_div (
denom,
numer,
quotient,
remain);
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
// Retrieval info: CONNECT: remain 0 0 32 0 @remain 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; struct node { int a; int b; int index; }; bool compare(node &n1, node &n2) { if (n1.a < n2.a) return true; else return false; } bool compare1(node &n1, node &n2) { if (n1.b < n2.b) return true; else return false; } int main() { int n; cin >> n; vector<node> pq(n); for (int i = 0; i < n; i++) { cin >> pq[i].a >> pq[i].b; pq[i].index = i; } int num = 0; for (int i = 0; i < n; i++) { if (pq[i].a < pq[i].b) num++; } vector<node> track; if (num >= n / 2) { for (int i = 0; i < n; i++) { if (pq[i].a < pq[i].b) track.push_back(pq[i]); } sort(track.begin(), track.end(), compare); cout << track.size() << endl; for (int i = track.size() - 1; i >= 0; i--) { cout << track[i].index + 1 << ; } } else { for (int i = 0; i < n; i++) { if (pq[i].a > pq[i].b) track.push_back(pq[i]); } sort(track.begin(), track.end(), compare1); cout << track.size() << endl; for (int i = 0; i < track.size(); i++) { cout << track[i].index + 1 << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int i, k, b, n, m, r = 0, x = 0, y = 0, z = 0, h = 0, l; string s; cin >> s; n = s.size(); int a[n]; for (i = 0; i < n; i++) { if (s[i] == ( ) x++; else if (s[i] == ) && x > 0) x--; else if (s[i] == ) ) z = 1; else if (s[i] == # && x > 0) { a[y] = 1; y++; x--; k = i; l = x; } else if (s[i] == # ) z = 1; } x = l; if (y > 0) { r = 0; for (i = k + 1; i < n; i++) { if (s[i] == ( ) { x++; r++; } else if (s[i] == ) && x > 0) x--; else h = 1; if (s[i] == ) && r > 0) r--; } a[y - 1] = x + 1; } if (z == 1 || h == 1 || r != 0) cout << -1 ; else { for (i = 0; i < y; i++) { cout << a[i] << endl; } } return 0; }
|
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "SINGLE_ENDED",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
//BUFG u_ibufg_sys_clk
// (
// .I (sys_clk),
// .O (sys_clk_ibufg)
// );
assign sys_clk_ibufg = sys_clk;
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_0_V
`define SKY130_FD_SC_LP__A32O_0_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_0 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR4BB_BEHAVIORAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int N = 1000040; long long fact[N], invf[N]; vector<long long> primes; long long add(long long x, long long y) { return (x + y) % mod; } long long mul(long long x, long long y) { return (x % mod) * (y % mod) % mod; } long long powll(long long x, long long y) { long long res = 1LL; while (y) { if (y & 1LL) res *= x; res %= mod; x = (x * x) % mod; y >>= 1LL; } return res; } long long divll(long long x, long long y) { return (x * powll(y, mod - 2)) % mod; } long long nPr(long long n, long long r) { if (n < r || r < 0) return 0; return mul(fact[n], invf[n - r]); } long long nCr(long long n, long long r) { if (n < r || r < 0) return 0; return mul(mul(fact[n], invf[r]), invf[n - r]); } long long solve() { long long x, y; scanf( %lld %lld , &x, &y); vector<long long> c; for (long long p : primes) { int k = 0; while (x % p == 0) { k++; x /= p; } if (k) c.push_back(k); } if (x > 1) c.push_back(1); long long ret = powll(2, y - 1); for (long long a : c) { ret = (ret * nCr(y + a - 1, a)) % mod; } return ret; } int main() { int q; cin >> q; fact[0] = invf[0] = 1; for (int i = 1; i <= N - 1; ++i) { fact[i] = (fact[i - 1] * i) % mod; invf[i] = divll(invf[i - 1], i); } long long lim = 1000; vector<int> check(lim, 1); for (int i = 2; i <= lim - 1; ++i) { if (!check[i]) continue; primes.push_back(i); for (int j = 2 * i; j < lim; j += i) check[j] = 0; } while (q--) { printf( %lld n , solve()); } return 0; }
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: MBUS Register File
// Semi Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module lc_mbc_iso
(
//**************************************
//Power Domain
//Input - Always On
//Output - N/A
//**************************************
//Signals
//Input
MBC_ISOLATE,
// LC --> MBC
//Input
ADDROUT_uniso,
DATAOUT_uniso,
PENDOUT_uniso,
REQOUT_uniso,
PRIORITYOUT_uniso,
ACKOUT_uniso,
RESPOUT_uniso,
//Output
ADDROUT, // ISOL value = Low
DATAOUT, // ISOL value = Low
PENDOUT, // ISOL value = Low
REQOUT, // ISOL value = Low
PRIORITYOUT, // ISOL value = Low
ACKOUT, // ISOL value = Low
RESPOUT, // ISOL value = Low
// MBC --> LC
//Input
LRC_SLEEP_uniso,
LRC_RESET_uniso,
LRC_ISOLATE_uniso,
//Output
LRC_SLEEP, // ISOL value = High
LRC_RESET, // ISOL value = High
LRC_ISOLATE, // ISOL value = High
// MBC --> SC
//Input
SLEEP_REQ_uniso,
//Output
SLEEP_REQ // ISOL value = Low
);
//Input
input MBC_ISOLATE;
// LC --> MBC
//Input
input [31:0] ADDROUT_uniso;
input [31:0] DATAOUT_uniso;
input PENDOUT_uniso;
input REQOUT_uniso;
input PRIORITYOUT_uniso;
input ACKOUT_uniso;
input RESPOUT_uniso;
//Output
output [31:0] ADDROUT;
output [31:0] DATAOUT;
output PENDOUT;
output REQOUT;
output PRIORITYOUT;
output ACKOUT;
output RESPOUT;
// MBC --> LC
//Input
input LRC_SLEEP_uniso;
input LRC_RESET_uniso;
input LRC_ISOLATE_uniso;
//Output
output LRC_SLEEP;
output LRC_RESET;
output LRC_ISOLATE;
// MBC --> SC
input SLEEP_REQ_uniso;
output SLEEP_REQ;
// LC --> MBC
assign ADDROUT = ~LRC_ISOLATE & ADDROUT_uniso;
assign DATAOUT = ~LRC_ISOLATE & DATAOUT_uniso;
assign PENDOUT = ~LRC_ISOLATE & PENDOUT_uniso;
assign REQOUT = ~LRC_ISOLATE & REQOUT_uniso;
assign PRIORITYOUT = ~LRC_ISOLATE & PRIORITYOUT_uniso;
assign ACKOUT = ~LRC_ISOLATE & ACKOUT_uniso;
assign RESPOUT = ~LRC_ISOLATE & RESPOUT_uniso;
// MBC --> LC
assign LRC_SLEEP = MBC_ISOLATE | LRC_SLEEP_uniso;
assign LRC_RESET = MBC_ISOLATE | LRC_RESET_uniso;
assign LRC_ISOLATE = MBC_ISOLATE | LRC_ISOLATE_uniso;
// MBC --> SC
assign SLEEP_REQ = ~MBC_ISOLATE & SLEEP_REQ_uniso;
endmodule // lc_mbc_iso
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=125 clk0_duty_cycle=50 clk0_multiply_by=8 clk0_phase_shift="0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=adc_sclk" operation_mode="no_compensation" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_adc_sclk_adc_sclk_pll_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module adc_sclk_altpll1
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 125,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 8,
pll1.clk0_phase_shift = "0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "no_compensation",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //adc_sclk_altpll1
//VALID FILE
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: translation_layer.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: The translation layer provides a uniform interface for all Altera
PCIe interfaces
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`include "trellis.vh" // Defines the user-facing signal widths.
`include "altera.vh"
module translation_altera
#(
parameter C_PCI_DATA_WIDTH = 128
)
(
input CLK,
input RST_IN,
// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_FC_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_FC_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: RX Classic
output [C_PCI_DATA_WIDTH-1:0] RX_TLP,
output RX_TLP_VALID,
output RX_TLP_START_FLAG,
output [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
output RX_TLP_END_FLAG,
output [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
output [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
input RX_TLP_READY,
// Interface: TX Classic
output TX_TLP_READY,
input [C_PCI_DATA_WIDTH-1:0] TX_TLP,
input TX_TLP_VALID,
input TX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] TX_TLP_START_OFFSET,
input TX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] TX_TLP_END_OFFSET,
// Interface: Configuration
output [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
output [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
output [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
output [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
output CONFIG_INTERRUPT_MSIENABLE,
output CONFIG_CPL_BOUNDARY_SEL,
output [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
output [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
// Interface: Interrupt
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt
);
`include "functions.vh"
localparam C_ALTERA_TX_READY_LATENCY = 1;// TODO: HMmmmmm 2?
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
reg [C_PCI_DATA_WIDTH-1:0] rRxStData;
reg rRxStValid;
reg rRxStEop;
reg rRxStSop;
reg [`SIG_CFG_ADD_W-1:0] rTlCfgAdd,_rTlCfgAdd;
reg [`SIG_CFG_CTL_W-1:0] rTlCfgCtl,_rTlCfgCtl;
reg [`SIG_CFG_STS_W-1:0] rTlCfgSts,_rTlCfgSts;
reg [`SIG_CPLID_W-1:0] rCfgCompleterId;
reg rCfgBusMstrEnable;
reg [`SIG_MAXREAD_W-1:0] rCfgMaxReadRequestSize;
reg [`SIG_MAXPAYLOAD_W-1:0] rCfgMaxPayloadSize;
reg rCfgInterruptMsienable;
reg rReadCompletionBoundarySel;
reg [C_ALTERA_TX_READY_LATENCY-1:0] rTxStReady, _rTxStReady;
// Rx Interface (To PCIe Core)
assign RX_ST_READY = RX_TLP_READY;
// Rx Interface (From PCIe Core)
assign RX_TLP = RX_ST_DATA;
assign RX_TLP_VALID = RX_ST_VALID;
assign RX_TLP_END_FLAG = RX_ST_EOP;
assign RX_TLP_END_OFFSET = {3'b000,RX_ST_EMPTY};
assign RX_TLP_START_FLAG = RX_ST_SOP;
assign RX_TLP_START_OFFSET = 0;
// TX Interface (From PCIe Core)
assign TX_TLP_READY = rTxStReady[C_ALTERA_TX_READY_LATENCY-1];
// TX Interface (To PCIe Core)
assign TX_ST_DATA = TX_TLP;
assign TX_ST_VALID = TX_TLP_VALID & TX_TLP_READY;
assign TX_ST_EOP = TX_TLP_END_FLAG;
assign TX_ST_SOP = TX_TLP_START_FLAG;
// Configuration Interface
assign CONFIG_COMPLETER_ID = rCfgCompleterId;
assign CONFIG_BUS_MASTER_ENABLE = rCfgBusMstrEnable;
assign CONFIG_LINK_WIDTH = rTlCfgSts[`TLSTS_LWIDTH_R];
assign CONFIG_LINK_RATE = rTlCfgSts[`TLSTS_LRATE_R];
assign CONFIG_MAX_READ_REQUEST_SIZE = rCfgMaxReadRequestSize;
assign CONFIG_MAX_PAYLOAD_SIZE = rCfgMaxPayloadSize;
assign CONFIG_INTERRUPT_MSIENABLE = rCfgInterruptMsienable;
assign CONFIG_CPL_BOUNDARY_SEL = rReadCompletionBoundarySel;
assign CONFIG_MAX_CPL_HDR = KO_CPL_SPC_HEADER;
assign CONFIG_MAX_CPL_DATA = KO_CPL_SPC_DATA;
// Interrupt interface
assign APP_MSI_REQ = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = APP_MSI_ACK;
always @(*) begin
_rTxStReady = (rTxStReady << 1) | TX_ST_READY;
end
always @(posedge CLK) begin
rTxStReady <= _rTxStReady;
end
always @(*) begin
_rTlCfgCtl = TL_CFG_CTL;
_rTlCfgAdd = TL_CFG_ADD;
_rTlCfgSts = TL_CFG_STS;
end
always @(posedge CLK) begin // Should be the same clock as pld_clk
rTlCfgAdd <= _rTlCfgAdd;
rTlCfgCtl <= _rTlCfgCtl;
rTlCfgSts <= _rTlCfgSts;
if(rTlCfgAdd == `TLCFG_DEVCTL_I) begin
rCfgMaxReadRequestSize <= rTlCfgCtl[`TLCTL_MAXREQ_R];
rCfgMaxPayloadSize <= rTlCfgCtl[`TLCTL_MAXPAY_R];
end
if(rTlCfgAdd == `TLCFG_LNKCTL_I) begin
rReadCompletionBoundarySel <= rTlCfgCtl[`TLCTL_RCB_R];
end
if(rTlCfgAdd == `TLCFG_PRMCMD_I) begin
rCfgBusMstrEnable <= rTlCfgCtl[`TLCTL_BUSMSTR_R];
end
if(rTlCfgAdd == `TLCFG_MSICSR_I) begin
rCfgInterruptMsienable <= rTlCfgCtl[`TLCTL_MSIENABLE_R];
end
if(rTlCfgAdd == `TLCFG_BUSDEV_I) begin
rCfgCompleterId <= {rTlCfgCtl[`TLCTL_BUSDEV_R],3'b0};
end
end // always @ (posedge CLK)
generate
if (C_PCI_DATA_WIDTH == 9'd32) begin : a32
// Not possible...
end else if (C_PCI_DATA_WIDTH == 9'd64) begin : a64
assign TX_ST_EMPTY = 0;
end else if (C_PCI_DATA_WIDTH == 9'd128) begin : a128
assign TX_ST_EMPTY = ~TX_TLP_END_OFFSET[1] & TX_ST_EOP;
end else if (C_PCI_DATA_WIDTH == 9'd256) begin : a256
assign TX_ST_EMPTY = TX_TLP_END_OFFSET[2];
end
endgenerate
endmodule // translation_layer
|
#include <bits/stdc++.h> using namespace std; const int di[] = {-1, 0, 1, 0}; const int dj[] = {0, 1, 0, -1}; const long long MOD = 1e9 + 7; const long long INF = 1e9; const double EPS = 1e-11; int main() { ios::sync_with_stdio(false), cin.tie(0); int n, q, c; cin >> n >> q >> c; vector<pair<int, int> > pos(n); vector<int> s(n); vector<vector<vector<int> > > cnt( 101, vector<vector<int> >(101, vector<int>(c + 1))); for (int i = 0; i < n; ++i) { cin >> pos[i].first >> pos[i].second >> s[i]; cnt[pos[i].first][pos[i].second][s[i]]++; } for (int i = 0; i < 101; ++i) { for (int j = 0; j < 101; ++j) { for (int k = 0; k < c + 1; ++k) { if (i > 0) cnt[i][j][k] += cnt[i - 1][j][k]; if (j > 0) cnt[i][j][k] += cnt[i][j - 1][k]; if (i > 0 && j > 0) cnt[i][j][k] -= cnt[i - 1][j - 1][k]; } } } while (q--) { int t, x1, y1, x2, y2; cin >> t >> x1 >> y1 >> x2 >> y2; vector<vector<int> > cum(4, vector<int>(11)); cum[0] = cnt[x2][y2]; cum[1] = cnt[x2][y1 - 1]; cum[2] = cnt[x1 - 1][y1 - 1]; cum[3] = cnt[x1 - 1][y2]; vector<int> cur(11), cur2(11); for (int i = 0; i < c + 1; ++i) cur[i] = cum[0][i] - cum[1][i] - cum[3][i] + cum[2][i]; for (int i = 0; i < c + 1; ++i) cur2[(i + t) % (c + 1)] = cur[i]; int r = 0; for (int i = 0; i < c + 1; ++i) r += i * cur2[i]; cout << r << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 5100; const int oo = 1e9; const int MX = 100000000; const int FF = 33000; int n, m, a[N], gc[N]; int dp[5010], pre[5010]; map<int, bool> bad; map<int, int> cache; vector<int> prime; bool mark[FF + 200]; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } int fact(int num) { if (cache.find(num) != cache.end()) return cache[num]; int &ret = cache[num]; long long idx = 0, pf = prime[0]; while (pf * pf <= num) { int cnt = 0; while (num % pf == 0) num /= pf, cnt++; ret += cnt * (bad[pf] ? -1 : 1); if (++idx < prime.size()) pf = prime[idx]; } if (num != 1) ret += bad[num] ? -1 : 1; return ret; } int eval() { int res = 0; for (int i = 0; i < n; ++i) res += fact(a[i]); return res; } int rn(int l, int r, int gc) { return pre[r] - (!l ? 0 : pre[l - 1]) - (r - l + 1) * fact(gc); } int calc(int idx) { if (idx == n) return 0; int &ret = dp[idx]; if (ret != -oo) return ret; ret = rn(idx, n - 1, 1); for (int j = idx; j < n; ++j) { ret = max(ret, rn(idx, j, gc[j]) + calc(j + 1)); } return ret; } int main() { cin >> n >> m; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } for (int first, i = 0; i < m; ++i) { scanf( %d , &first); bad[first] = 1; } for (long long i = 2; i <= FF; ++i) { if (mark[i]) continue; for (int j = i; j <= FF; j += i) mark[j] = 1; prime.push_back(i); } for (int i = 0; i < n; ++i) gc[i] = !i ? a[i] : gcd(a[i], gc[i - 1]); for (int i = 0; i <= n; ++i) dp[i] = -oo; for (int i = 0; i < n; ++i) { pre[i] = fact(a[i]); if (i) pre[i] += pre[i - 1]; } cout << calc(0) << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; char str[1010000]; int b[1010000]; int a[1010000]; int bb[1010000]; int main() { int n; int flag = 1; scanf( %d , &n); scanf( %s , str); for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); } int coutt1 = 0; for (int i = 0; i <= n - 1; i++) { if (str[i] == R ) { coutt1++; a[coutt1] = b[i + 1]; } } int coutt2 = 0; for (int i = 0; i <= n - 1; i++) { if (str[i] == L ) { coutt2++; bb[coutt2] = b[i + 1]; } } int ans = 1000000005; int i, j; for (i = 1, j = 1; i <= coutt1 && j <= coutt2;) { if (a[i] < bb[j]) { flag = 0; ans = min((bb[j] - a[i]) / 2, ans); i++; } else { j++; } } if (flag) printf( -1 ); else printf( %d , ans); }
|
//% @file Receive_Data.v
//% @brief This module is used to receive data from TMIIa shift register.
//% @author pyxiong
//%
//% When start is asserted, new data will be sent to shift register one by one,
//% at the same time , the orginal data stored in shift register will be sent to
//% this module, when 170-bit data are received, a 170-bit width data will come
//% to the output port of this module.
//%
`timescale 1ns / 1ps
module Receive_Data #(parameter DATA_WIDTH=170, //% @param width of data
parameter CNT_WIDTH=8, //% @param width of internal counter.
parameter SHIFT_DIRECTION=1, //% @param 1: first bit in is MSB, 0: first bit in is LSB
parameter READ_DELAY=0 //% @param state machine delay cycle.
) (
input data_in, //% input from data stored in shift register in the chip.
input clk, //% control clock
input rst, //% module reset
input start, //% start signal
output reg [DATA_WIDTH-1:0] dout, //% parallized captured data (170-bit) from shift register
output reg valid //% valid is asserted when dout_temp is sent to dout
);
reg [2:0] current_state_in, next_state_in;
reg [DATA_WIDTH-1:0] dout_tmp;
reg [CNT_WIDTH:0] cnt;
parameter s0=3'b001;
parameter s1=3'b010;
parameter s2=3'b100;
parameter s3=3'b000;
//state machine 2, used to recieve data from SR
always@(negedge clk or posedge rst)
begin
if(rst)
begin
current_state_in<=s0;
end
else
begin
current_state_in<=next_state_in;
end
end
always@(current_state_in or rst or start or cnt)
begin
if(rst)
begin
next_state_in=s0;
end
else
begin
case(current_state_in)
s0: next_state_in=(start == 1'b1 && READ_DELAY == 0)?s2:
(start == 1'b1 && READ_DELAY == 1)?s3:
(start == 1'b1 && READ_DELAY == 2)?s1:s0;
s1: next_state_in=s3;
s3: next_state_in=s2;
s2: next_state_in=(cnt==DATA_WIDTH)?s0:s2;
default: next_state_in=s0;
endcase
end
end
always@(negedge clk or posedge rst)
begin
if(rst)
begin
cnt<=0;
dout_tmp<=0;
end
else
begin
case(next_state_in)
s0:
begin
cnt<=0;
dout_tmp<=0;
end
s1,s3:
begin
cnt<=0;
dout_tmp<=0;
end
s2:
begin
cnt<=cnt+1'b1;
if(SHIFT_DIRECTION)
begin
dout_tmp[DATA_WIDTH-1-cnt]<=data_in;
end
else
begin
dout_tmp[cnt]<=data_in;
end
end
default:
begin
cnt<=0;
dout_tmp<=0;
end
endcase
end
end
always@(negedge clk or posedge rst)
begin
if(rst)
begin
dout<=0;
valid<=0;
end
else
begin
if(cnt==DATA_WIDTH)
begin
dout<=dout_tmp;
valid<=1;
end
else
begin
dout<=dout;
valid<=valid;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x, y, nx, ny, k; int main() { cin >> x >> y; nx = x; ny = y; while (x != 1 && y != 1) { if (x > y) { k = x / y; x -= k * y; if (x == 0) { x += y; k--; } } if (x == y) { puts( Impossible ); return 0; } if (y > x) { k = y / x; y -= k * x; if (y == 0) { y += x; k--; } } } x = nx; y = ny; while (x != 1 && y != 1) { if (x > y) { k = x / y; x -= k * y; if (x == 0) { x += y; k--; } if (k != 0) printf( %I64dA , k); } if (y > x) { k = y / x; y -= k * x; if (y == 0) { y += x; k--; } if (k != 0) printf( %I64dB , k); } } if (x == 1 && y > 1) { printf( %I64dB , y - 1); } if (y == 1 && x > 1) { printf( %I64dA , x - 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; char a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } int ans = 0; for (int j = 0; j < m - 1; j++) { if (a[n - 1][j] == D ) { ans++; } } for (int i = 0; i < n - 1; i++) { if (a[i][m - 1] == R ) { ans++; } } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, MOD = 1e9 + 7; long long power(long long a, long long n) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; } n >>= 1; a *= a; } return p; } long long power(long long a, long long n, long long mod) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; p %= mod; } n >>= 1; a *= a; a %= mod; } return p % mod; } void swap(char *a, char *b) { char temp = *a; *a = *b; *b = temp; } long long int nCr(int n, int r) { long long int C[r + 1]; memset(C, 0, sizeof(C)); C[0] = 1; for (int i = 1; i <= n; i++) { for (int j = min(i, r); j > 0; j--) C[j] = (C[j] + C[j - 1]); } return C[r]; } long long int countDer(int n) { int der[n + 1]; der[0] = 1; der[1] = 0; der[2] = 1; for (int i = 3; i <= n; ++i) der[i] = (i - 1) * (der[i - 1] + der[i - 2]); return der[n]; } int digitsum(long long a) { int ans = 0; while (a > 0) { ans = ans + a % 10; a = a / 10; } return ans; } int count(long long a) { int temp = 0; while (a > 0) { a = a / 10; temp++; } return temp; } int main() { int n; cin >> n; char s[n]; for (int i = 0; i < n; i++) cin >> s[i]; sort(s, s + n); for (int i = 0; i < n; i++) cout << s[i]; cout << endl; }
|
#include <bits/stdc++.h> int main() { int sign = 1; int current = 0; int value = 0; for (char c; n != (c = getchar());) { if (c == + or c == - ) { value += sign * current; sign = (c == + ? 1 : -1); current = 0; } current *= 10; current += c - 0 ; } printf( %d , value + sign * current); return 0; }
|
`timescale 1 ns / 1 ps
module hapara_bram_dma_dup_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer DATA_WIDTH = 32
)
(
// Users to add ports here
input [DATA_WIDTH - 1 : 0] addr_ctrl,
input [DATA_WIDTH - 1 : 0] data_in_ctrl,
output [DATA_WIDTH - 1 : 0] data_out_ctrl,
input [DATA_WIDTH / 8 - 1 : 0] we_ctrl,
input clk_ctrl,
input rst_ctrl,
input en_ctrl,
output [DATA_WIDTH - 1 : 0] addr_inst,
output [DATA_WIDTH - 1 : 0] data_in_inst,
input [DATA_WIDTH - 1 : 0] data_out_inst,
output [DATA_WIDTH / 8 - 1 : 0] we_inst,
output clk_inst,
output rst_inst,
output en_inst,
output [DATA_WIDTH - 1 : 0] addr_data,
output [DATA_WIDTH - 1 : 0] data_in_data,
input [DATA_WIDTH - 1 : 0] data_out_data,
output [DATA_WIDTH / 8 - 1 : 0] we_data,
output clk_data,
output rst_data,
output en_data
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
);
// Instantiation of Axi Bus Interface S00_AXI
// Add user logic here
assign clk_inst = clk_ctrl;
assign clk_data = clk_ctrl;
assign rst_inst = rst_ctrl;
assign rst_data = rst_ctrl;
assign we_inst = we_ctrl;
assign we_data = we_ctrl;
assign addr_inst = addr_ctrl;
assign addr_data = addr_ctrl;
assign data_in_inst = data_in_ctrl;
assign data_in_data = data_in_ctrl;
assign en_inst = en_ctrl;
assign en_data = en_ctrl;
assign data_out_ctrl = data_out_data;
// User logic ends
endmodule
|
#define _CRT_SECURE_NO_WARNINGS /* To Be or Not To Be !! Allah_Almost3aan Make it happens :) */ #include<bits/stdc++.h> #include<unordered_map> //#include<unorderd_set> using namespace std; using ll = long long; using ld = long double; const ll OO = 1e16; #define ed n #define F first //#define S second #define sz(a)a.size() #define vi vector<int> #define pii pair<int,int> #define all(c)c.begin(),c.end() #define RT(v)return cout<<v,0 #define rall(s)s.rbegin(),s.rend() #define stpr(n)fixed<<setprecision(n) int di[8] = { 0, 0, 1, -1, -1, 1, -1, 1 }; int dj[8] = { 1, -1, 0, 0, 1, 1, -1, -1 }; #define show(x)cout<< > <<(#x)<< = <<x<<ed #define reset(mem,val)memset(mem,val,sizeof mem) #define fast ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); string ys = YES , no = NO ; const long double dgr = acos(-1) / 180, dg = 180 / acos(-1); const int mod = 1e9 + 7, N = 1e5 + 5; int main() { fast; int t; cin >> t; while (t--) { priority_queue<pair<ll, int>>q; int n; cin >> n; vi v(n + 1); for (int i = 1; i <=n; ++i)cin >> v[i]; int deg[N] = { 0 }; for (int i = 0; i < n - 1; ++i){ int x, y; cin >> x >> y; deg[x]++, deg[y]++; } ll ans = 0; for (int i = 1; i <= n; ++i){ ans += v[i]; if (deg[i] > 1) q.push({v[i], deg[i] - 1 }); } for (int i = 0; i < n - 1; ++i){ cout << ans << ; if (sz(q)) { pair<ll, int>p = q.top(); q.pop(); ans += p.first, p.second--; if (p.second) q.push({ p.first, p.second }); } } cout <<ed; } return 0; }
|
//library ieee;
//use ieee.std_logic_1164.all;
//use ieee.std_logic_unsigned.all;
//-----------------------------------------------------
// Design Name : ram_dp_sr_sw
// File Name : ram_dp_sr_sw.v
// Function : Synchronous read write RAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
`timescale 1ns/1ps
module blk_mem #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 4,
parameter INC_NUM_PATTERN = 0
)(
input clka,
input wea,
input [ADDRESS_WIDTH - 1 :0] addra,
input [DATA_WIDTH - 1:0] dina,
input clkb,
input [ADDRESS_WIDTH - 1:0] addrb,
output [DATA_WIDTH - 1:0] doutb
);
//Parameters
//Registers/Wires
reg [DATA_WIDTH - 1:0] mem [0:2 ** ADDRESS_WIDTH];
reg [DATA_WIDTH - 1:0] dout;
//Submodules
//Asynchronous Logic
assign doutb = dout;
//Synchronous Logic
//write only on the A side
`ifdef SIMULATION
integer i;
initial begin
i = 0;
for (i = 0; i < (2 ** ADDRESS_WIDTH); i = i + 1) begin
if (INC_NUM_PATTERN) begin
mem[i] <= i;
end
else begin
//Zero Everything Out
mem[i] <= 0;
end
end
end
`endif
always @ (posedge clka)
begin
if ( wea ) begin
mem[addra] <= dina;
end
end
//read only on the b side
always @ (posedge clkb)
begin
dout <= mem[addrb];
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.06.2017 16:31:15
// Design Name:
// Module Name: teclado
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module teclado(
input [7:0] ps2_data,
output reg [4:0] val,
output reg [2:0] control,
/////////////////////////////////////////////////////
// output [7:0] AN,
// output CA,CB,CC,CD,CE,CF,CG,DP,
output [7:0] leds
);
localparam CTRL_NUMERO = 3'd1;
localparam CTRL_ENTER = 3'd2;
localparam CTRL_FLECHA = 3'd3;
localparam CTRL_OPERACION = 3'd4;
localparam CERO = 8'h45;
localparam UNO = 8'h16;
localparam DOS = 8'h1E;
localparam TRES = 8'h26;
localparam CUATRO = 8'h25;
localparam CINCO = 8'h2E;
localparam SEIS = 8'h36;
localparam SIETE = 8'h3D;
localparam OCHO = 8'h3E;
localparam NUEVE = 8'h46;
localparam A = 8'h1C;
localparam B = 8'h32;
localparam C = 8'h21;
localparam D = 8'h23;
localparam E = 8'h24;
localparam F = 8'h2B;
localparam O = 8'h44;
localparam Y = 8'h35;
localparam SUMA = 8'h1B;
localparam RESTA = 8'h2D;
localparam MUL = 8'h3A;
localparam ENTER = 8'h5A;
localparam ARRIBA =8'h75;
localparam ABAJO =8'h72;
localparam IZQUIERDA =8'h6B;
localparam DERECHA =8'h74;
wire reloj_lento;
assign leds[4:0]= val;
assign leds[7:5]= control;
always @(*) begin
case(ps2_data)
CERO: begin
val=5'd0;
control=CTRL_NUMERO;
end
UNO: begin
val=5'd1;
control=CTRL_NUMERO;
end
DOS:begin
val=5'd2;
control=CTRL_NUMERO;
end
TRES:begin
val=5'd3;
control=CTRL_NUMERO;
end
CUATRO:begin
val=5'd4;
control=CTRL_NUMERO;
end
CINCO:begin
val=5'd5;
control=CTRL_NUMERO;
end
SEIS:begin
val=5'd6;
control=CTRL_NUMERO;
end
SIETE:begin
val=5'd7;
control=CTRL_NUMERO;
end
OCHO:begin
val=5'd8;
control=CTRL_NUMERO;
end
NUEVE:begin
val=5'd9;
control=CTRL_NUMERO;
end
A:begin
val=5'd10;
control=CTRL_NUMERO;
end
B:begin
val=5'd11;
control=CTRL_NUMERO;
end
C:begin
val=5'd12;
control=CTRL_NUMERO;
end
D:begin
val=5'd13;
control=CTRL_NUMERO;
end
E:begin
val=5'd14;
control=CTRL_NUMERO;
end
F:begin
val=5'd15;
control=CTRL_NUMERO;
end
SUMA:begin
val=5'd21;
control=CTRL_OPERACION;
end
RESTA:begin
val=5'd22;
control=CTRL_OPERACION;
end
MUL:begin
val=5'd23;
control=CTRL_OPERACION;
end
Y:begin
val=5'd24;
control=CTRL_OPERACION;
end
O:begin
val=5'd25;
control=CTRL_OPERACION;
end
ENTER:begin
val =5'd16;
control =CTRL_ENTER;
end
ARRIBA:begin
val=5'd19;
control=CTRL_FLECHA;
end
ABAJO:begin
val=5'd20;
control=CTRL_FLECHA;
end
IZQUIERDA:begin
val=5'd17;
control=CTRL_FLECHA;
end
DERECHA:begin
val=5'd18;
control=CTRL_FLECHA;
end
default: begin
val=5'd0;
control=3'd0;
end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// clock_divider clock_div(
// .clk(CLK100MHZ),
// .rst(reset),
// .clk_div(reloj_lento)
// );
// display dis(
// .clk_display(reloj_lento),
// .num({24'b0,new_data}),
// .puntos(),
// .anodos(AN[7:0]),
// .segmentos({CA,CB,CC,CD,CE,CF,CG,DP})
// );
endmodule
|
(** * Maps: Total and Partial Maps *)
(** Maps (or dictionaries) are ubiquitous data structures, both in
software construction generally and in the theory of programming
languages in particular; we're going to need them in many places
in the coming chapters. They also make a nice case study using
ideas we've seen in previous chapters, including building data
structures out of higher-order functions (from [Basics] and
[Poly]) and the use of reflection to streamline proofs (from
[IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ###################################################################### *)
(** * The Coq Standard Library *)
(** One small digression before we start.
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Logic.FunctionalExtensionality.
(** Documentation for the standard library can be found at
http://coq.inria.fr/library/.
The [SearchAbout] command is a good way to look for theorems
involving objects of specific types. *)
(* ###################################################################### *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. For this purpose, we again use the type [id] from the
[Lists] chapter. To make this chapter self contained, we repeat
its definition here, together with the equality comparison
function for [id]s and its fundamental property. *)
Inductive id : Type :=
| Id : nat -> id.
Definition beq_id id1 id2 :=
match id1,id2 with
| Id n1, Id n2 => beq_nat n1 n2
end.
Theorem beq_id_refl : forall id, true = beq_id id id.
Proof.
intros [n]. simpl. rewrite <- beq_nat_refl.
reflexivity. Qed.
(** (In the HTML version, the proof of this theorem is elided, since
the details are pretty routine at this point. Click on the box if
you want to see it.)
The following useful property of [beq_id] follows from an
analogous lemma about numbers: *)
Theorem beq_id_true_iff : forall id1 id2 : id,
beq_id id1 id2 = true <-> id1 = id2.
Proof.
intros [n1] [n2].
unfold beq_id.
rewrite beq_nat_true_iff.
split.
- (* -> *) intros H. rewrite H. reflexivity.
- (* <- *) intros H. inversion H. reflexivity.
Qed.
(** Similarly: *)
Theorem beq_id_false_iff : forall x y : id,
beq_id x y = false
<-> x <> y.
Proof.
intros x y. rewrite <- beq_id_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This useful variant follows just by rewriting: *)
Theorem false_beq_id : forall x y : id,
x <> y
-> beq_id x y = false.
Proof.
intros x y. rewrite beq_id_false_iff.
intros H. apply H. Qed.
(* ###################################################################### *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about their behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps.
We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A:Type) := id -> A.
(** Intuitively, a total map over an element type [A] _is_ just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A:Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A:Type} (m : total_map A)
(x : id) (v : A) :=
fun x' => if beq_id x x' then v else m x'.
(** This definition is a nice example of higher-order programming.
The [t_update] function takes a _function_ [m] and yields a new
function [fun x' => ...] that behaves like the desired map.
For example, we can build a map taking [id]s to [bool]s, where [Id
3] is mapped to [true] and every other key is mapped to [false],
like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) (Id 1) false)
(Id 3) true.
(** This completes the definition of total maps. Note that we don't
need to define a [find] operation because it is just function
application! *)
Example update_example1 : examplemap (Id 0) = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap (Id 1) = false.
Proof. reflexivity. Qed.
Example update_example3 : examplemap (Id 2) = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap (Id 3) = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. Even if you don't work the following
exercises, make sure you thoroughly understand the statements of
the lemmas! (Some of the proofs require the functional
extensionality axiom discussed in the [Logic] chapter, which is
also included in the standard library.) *)
(** **** Exercise: 2 stars, optional (t_update_eq) *)
(** First, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m: total_map A) x v,
(t_update m x v) x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_neq) *)
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X:Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_shadow) *)
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on [id]s with the boolean function [beq_id]. *)
(** **** Exercise: 2 stars (beq_idP) *)
(** Use the proof of [beq_natP] in chapter [IndProp] as a template to
prove the following: *)
Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP
x1 x2)] to simultaneously perform case analysis on the result of
[beq_id x1 x2] and generate hypotheses about the equality (in the
sense of [=]) of [x1] and [x2]. *)
(** **** Exercise: 2 stars (t_update_same) *)
(** Using the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (t_update_permute) *)
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A:Type) := total_map (option A).
Definition empty {A:Type} : partial_map A :=
t_empty None.
Definition update {A:Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** We can now lift all of the basic lemmas about total maps to
partial maps. *)
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
(** $Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_M_V
`define SKY130_FD_SC_LP__O211AI_M_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_m (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_m (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_M_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:35:45 11/11/2015
// Design Name:
// Module Name: LEDRotator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LEDRotator (SSLED, LEDSEL, inClk, reset);
output reg [6:0] SSLED;
output reg [3:0] LEDSEL;
input inClk, reset;
always @(posedge inClk or posedge reset) begin
if (reset) begin
SSLED = 7'b1110111; // Reset --> D
LEDSEL = 3'b0111; // LED1 = ON, LED2 = OFF, LED3 = OFF, LED4 = OFF
end
else begin
case (SSLED)
7'b0111111: SSLED = 7'b1111101; // A --> F
7'b1111101: SSLED = 7'b1111011; // F --> E
7'b1111011: SSLED = 7'b1110111; // E --> D
7'b1110111: SSLED = 7'b1101111; // D --> C
7'b1101111: SSLED = 7'b1011111; // C --> B
7'b1011111: SSLED = 7'b0111111; // B --> A
default: SSLED = 7'b0111111; // Any Arbitrary State goes to a valid State
endcase
end
end
endmodule
|
module top;
reg pass = 1'b1;
real in, bin;
wire [7:0] out = in;
wire signed [34:0] big = bin;
initial begin
// $monitor(in,, out,, bin,, big);
bin = .5; // 2**33+0.5 overflows a 32 bit long.
#1;
if (big !== 35'sd8589934593) begin
$display("Failed: multiword check, expected , got %d", big);
pass = 1'b0;
end
if (out !== 'b0) begin
$display("Failed: initial value, expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 0.499999;
bin = -25.5; // This test a different branch (small result -> big vec.).
#1;
if (big !== -26) begin
$display("Failed: small value multiword check, expected -26, got %d", out);
pass = 1'b0;
end
if (out !== 8'b0) begin
$display("Failed: rounding value (down, +), expected 8'b0, got %b", out);
pass = 1'b0;
end
in = -0.499999;
#1;
if (out !== 8'b0) begin
$display("Failed: rounding value (down, -), expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 0.5;
#1;
if (out !== 8'b01) begin
$display("Failed: rounding value (up, +), expected 8'b01, got %b", out);
pass = 1'b0;
end
in = -0.5;
#1;
if (out !== 8'b11111111) begin
$display("Failed: rounding value (up, -), expected 8'b11111111, got %b", out);
pass = 1'b0;
end
in = 256.0;
#1;
if (out !== 8'b0) begin
$display("Failed: overflow expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 511.0;
#1;
if (out !== 8'b11111111) begin
$display("Failed: pruning expected 8'b11111111, got %b", out);
pass = 1'b0;
end
in = 1.0/0.0;
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: +inf expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = -1.0/0.0;
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: -inf expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = sqrt(-1.0);
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: nan expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = .5;
#1;
if (out !== 129) begin
$display("Failed: overflow value expected 129, got %d", out);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300010; map<pair<pair<int, int>, int>, vector<int> > ans; map<pair<pair<int, int>, int>, vector<pair<int, int> > > l; map<pair<pair<int, int>, int>, vector<pair<int, int> > >::iterator it; int n, m; struct Point { int x, y; Point(int _x = 0, int _y = 0) : x(_x), y(_y){}; Point operator-(const Point &rhs) { return Point(x - rhs.x, y - rhs.y); } Point operator*(int v) { return Point(v * x, v * y); } Point operator+(const Point &rhs) { return Point(x + rhs.x, y + rhs.y); } Point operator/(int v) { return Point(x / v, y / v); } int len() { return x * x + y * y; } friend int dis(Point a, Point b) { return Point(a - b).len(); } void read() { scanf( %d%d , &x, &y); } }; struct Circle { int x, y, r; } c[1510]; inline int Pow(int x) { return x * x; } inline int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } pair<pair<int, int>, int> getLine(Point a, Point b) { if (a.x == b.x) return make_pair(make_pair(0, 0), a.x); if (a.y == b.y) return make_pair(make_pair(1, 0), a.y); int dx = a.x - b.x; int dy = a.y - b.y; int d = gcd(abs(dx), abs(dy)); dx /= d; dy /= d; if (dx < 0) { dx *= -1; dy *= -1; } int v = (a.y % dy + dy) % dy; v = a.x + (v - a.y) / dy * dx; return make_pair(make_pair(dx, dy), v); } int getAns(pair<pair<int, int>, int> tmp, int x) { if (l.find(tmp) == l.end()) return 0; vector<pair<int, int> > &u = l[tmp]; int p = upper_bound(u.begin(), u.end(), make_pair(x, 1)) - u.begin(); return ans[tmp][p]; } pair<pair<int, int>, int> getMirrorLine(Point a, Point b) { Point mid = (a + b) / 2, off = a - b; swap(off.x, off.y), off.x *= -1; return getLine(mid + off, mid - off); } int main() { scanf( %d%d , &n, &m); Point a, b; while (n--) { a.read(); b.read(); a = a * 2; b = b * 2; if (a.x == b.x) { l[getLine(a, b)].push_back(make_pair(min(a.y, b.y), 1)); l[getLine(a, b)].push_back(make_pair(max(a.y, b.y) + 1, -1)); } else { l[getLine(a, b)].push_back(make_pair(min(a.x, b.x), 1)); l[getLine(a, b)].push_back(make_pair(max(a.x, b.x) + 1, -1)); } } for (it = l.begin(); it != l.end(); ++it) { sort((*it).second.begin(), (*it).second.end()); vector<int> &tt = ans[(*it).first]; vector<pair<int, int> > &d = (*it).second; int v = 0; tt.push_back(v); for (int i = 0; i <= d.size(); ++i) { v += d[i].second; tt.push_back(v); } } for (int i = 1; i <= m; ++i) { scanf( %d%d%d , &c[i].x, &c[i].y, &c[i].r); c[i].x *= 2; c[i].y *= 2; c[i].r *= 2; } int cnt = 0; for (int i = 1; i < m; ++i) for (int j = i + 1; j <= m; ++j) { if (c[i].r == c[j].r && dis(Point(c[i].x, c[i].y), Point(c[j].x, c[j].y)) > Pow(c[i].r + c[j].r)) { int mid; if (c[i].y == c[j].y) mid = c[i].y; else mid = (c[i].x + c[j].x) >> 1; cnt += getAns( getMirrorLine(Point(c[i].x, c[i].y), Point(c[j].x, c[j].y)), mid); } } printf( %d n , cnt); return 0; }
|
// Testbench for ltcminer_icarus.v
`timescale 1ns/1ps
`ifdef SIM // Avoids wrong top selected if included in ISE/PlanAhead sources
module test_ltcminer ();
reg clk = 1'b0;
reg [31:0] cycle = 32'd0;
initial begin
clk = 0;
while(1)
begin
#5 clk = 1; #5 clk = 0;
end
end
always @ (posedge clk)
begin
cycle <= cycle + 32'd1;
end
// Running with default zero's for the data1..3 regs.
// tx_hash=553a4b69b43913a61b42013ce210f713eaa7332e48cda1bdf3b93b10161d0876 at 187,990 nS and
// final_hash (if SIM is defined) at 188,000 nS with golden_nonce_match flag NOT set since it is
// not a diff=32 share. To test golden_nonce, just tweak the target eg 31'hffffffff will match everything
// With serial input(at comm_clk_frequency=1_000_000), we get rx_done at t=70,220nS, however there is already a
// PBKDF2_SHA256_80_128 loaded in Xbuf (for nonce=00000001). The first final_hash at 188,000 nS is corrupted as
// the input data has changed from all 0's. The Xbuf starts salsa rom at t=188,000 but the nonce is incorrectly
// taken from the newly loaded data so once salsa in complete it also generates a corrupt final_hash at ~362,000 nS.
// Nonce is incremented then the newly loaded data starts PBKDF2_SHA256_80_128, so we must supply a nonce 1 less
// than the expected golden_nonce. The correct PBKDF2_SHA256_80_128 is ready at ~ 197,000 nS. We get final_hash for
// the corrupted work at ~362,000 nS then our required golden_nonce is at 536,180 nS.
// This is only really a problem for simulation. With live hashing we just lose 2 nonces every time getwork is
// loaded, which isn't a big deal.
wire RxD;
wire TxD;
wire extminer_rxd = 0;
wire extminer_txd;
wire [3:0] dip = 0;
wire [3:0] led;
wire TMP_SCL=1, TMP_SDA=1, TMP_ALERT=1;
parameter comm_clk_frequency = 1_000_000; // Speeds up serial loading enormously rx_done is at t=70,220nS
parameter baud_rate = 115_200;
ltcminer_icarus #(.comm_clk_frequency(comm_clk_frequency)) uut
(clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
// Send serial data - 84 bytes, matches on nonce 318f (included in data)
// NB starting nonce is 381e NOT 381f (see note above)
// NORMAL...
// reg [671:0] data = 672'h000007ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
// DYNPLL...
reg [671:0] data = 672'h55aa07ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg serial_send = 0;
wire serial_busy;
reg [31:0] data_32 = 0;
reg [31:0] start_cycle = 0;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) sertx (.clk(clk), .TxD(RxD), .send(serial_send), .busy(serial_busy), .word(data_32));
// TUNE this according to comm_clk_frequency so we send a single getwork (else it gets overwritten with 0's)
// parameter stop_cycle = 7020; // For comm_clk_frequency=1_000_000
parameter stop_cycle = 0; // Use this to DISABLE sending data
always @ (posedge clk)
begin
serial_send <= 0; // Default
// Send data every time tx goes idle (NB the !serial_send is to prevent serial_send
// going high for two cycles since serial_busy arrives one cycle after serial_send)
if (cycle > 5 && cycle < stop_cycle && !serial_busy && !serial_send)
begin
serial_send <= 1;
data_32 <= data[671:640];
data <= { data[639:0], 32'd0 };
start_cycle <= cycle; // Remember each start cycle (makes debugging easier)
end
end
endmodule
`endif
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#include <bits/stdc++.h> using namespace std; int n; char s[100000 + 10]; int num[30]; int main() { scanf( %d , &n); scanf( %s , s); sort(s, s + n); printf( %s n , s); }
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#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } void put1() { puts( Yes ); } void put2() { puts( No ); } void put3() { puts( -1 ); } long long qp(long long a, long long b, long long p) { long long ans = 1; while (b) { if (b & 1) { ans = (ans * a) % p; --b; } a = (a * a) % p; b >>= 1; } return ans % p; } const unsigned long long base = 2333; const unsigned long long pp = 19260811; const unsigned long long ppp = 999998639; const int manx = 2e5 + 5; const int mo = 998244353; map<long long, long long> dp; long long a[manx]; vector<long long> q; int main() { long long n = read(); long long ma = 0, ans = 0; for (int i = 1; i <= n; i++) { a[i] = read(); dp[a[i]] = max(dp[a[i] - 1] + 1, dp[a[i]]); if (dp[a[i]] > ans) ans = dp[a[i]], ma = a[i]; } for (int i = n; i >= 1; i--) if (a[i] == ma) q.push_back(i), ma--; reverse(q.begin(), q.end()); cout << q.size() << endl; for (auto x : q) cout << x << ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_FUNCTIONAL_V
|
//////////////////////////////////////////////////////////////////////
// File: CRC32.v
// Date: Thu Nov 27 13:56:49 2003
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: (Jan Zegers)
// http://www.easics.com
//
// Modified by Nathan Yawn for the Advanced Debug Module
// Changes (C) 2008 - 2010 Nathan Yawn
///////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_crc32.v,v $
// Revision 1.3 2011-10-24 02:25:11 natey
// Removed extraneous '#1' delays, which were a holdover from the original
// versions in the previous dbg_if core.
//
// Revision 1.2 2010-01-10 22:54:10 Nathan
// Update copyright dates
//
// Revision 1.1 2008/07/22 20:28:29 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:53 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/20 19:22:10 Nathan
// Reversed the direction of the CRC computation shift, for a more
// hardware-efficient implementation.
//
//
//
//
module adbg_crc32 (clk, data, enable, shift, clr, rst, crc_out, serial_out);
input clk;
input data;
input enable;
input shift;
input clr;
input rst;
output [31:0] crc_out;
output serial_out;
reg [31:0] crc;
wire [31:0] new_crc;
wire data_sim;
`ifdef SIM
assign data_sim = (data === 1'bx || data === 1'b0) ? 1'b0 : 1'b1;
`else
assign data_sim = data;
`endif
// You may notice that the 'poly' in this implementation is backwards.
// This is because the shift is also 'backwards', so that the data can
// be shifted out in the same direction, which saves on logic + routing.
assign new_crc[0] = crc[1];
assign new_crc[1] = crc[2];
assign new_crc[2] = crc[3];
assign new_crc[3] = crc[4];
assign new_crc[4] = crc[5];
assign new_crc[5] = crc[6] ^ data_sim ^ crc[0];
assign new_crc[6] = crc[7];
assign new_crc[7] = crc[8];
assign new_crc[8] = crc[9] ^ data_sim ^ crc[0];
assign new_crc[9] = crc[10] ^ data_sim ^ crc[0];
assign new_crc[10] = crc[11];
assign new_crc[11] = crc[12];
assign new_crc[12] = crc[13];
assign new_crc[13] = crc[14];
assign new_crc[14] = crc[15];
assign new_crc[15] = crc[16] ^ data_sim ^ crc[0];
assign new_crc[16] = crc[17];
assign new_crc[17] = crc[18];
assign new_crc[18] = crc[19];
assign new_crc[19] = crc[20] ^ data_sim ^ crc[0];
assign new_crc[20] = crc[21] ^ data_sim ^ crc[0];
assign new_crc[21] = crc[22] ^ data_sim ^ crc[0];
assign new_crc[22] = crc[23];
assign new_crc[23] = crc[24] ^ data_sim ^ crc[0];
assign new_crc[24] = crc[25] ^ data_sim ^ crc[0];
assign new_crc[25] = crc[26];
assign new_crc[26] = crc[27] ^ data_sim ^ crc[0];
assign new_crc[27] = crc[28] ^ data_sim ^ crc[0];
assign new_crc[28] = crc[29];
assign new_crc[29] = crc[30] ^ data_sim ^ crc[0];
assign new_crc[30] = crc[31] ^ data_sim ^ crc[0];
assign new_crc[31] = data_sim ^ crc[0];
always @ (posedge clk or posedge rst)
begin
if(rst)
crc[31:0] <= 32'hffffffff;
else if(clr)
crc[31:0] <= 32'hffffffff;
else if(enable)
crc[31:0] <= new_crc;
else if (shift)
crc[31:0] <= {1'b0, crc[31:1]};
end
//assign crc_match = (crc == 32'h0);
assign crc_out = crc; //[31];
assign serial_out = crc[0];
endmodule
|
`timescale 1ns / 1ps
//==================================================================================================
// Filename : Tenth_Phase_v2.v
// Created On : 2016-09-21 17:42:42
// Last Modified : 2016-09-22 00:16:41
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
// Dependencies: Multiplexer_AC, Mux_3x1
//
//
// Description :
//
//
//==================================================================================================
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies: Multiplexer_AC,Mux_3x1, RegisterAdd
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FRMT_STAGE
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
// //INPUTS
// input wire clk, //Clock Signal
// input wire rst, //Reset Signal
// input wire load_i,
input wire overflow_flag, //Overflow/add/subt result's mux's selector
input wire underflow_flag, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] formatted_number //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = overflow_flag | underflow_flag;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({overflow_flag,underflow_flag}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
assign exp_mux_D1 = {(EW-1){1'b1}};
assign sgf_mux_D1 = {(SW-1){1'b0}};
////////////////////////////////////////////////////////////////
assign formatted_number = {Sign_S_mux,Exp_S_mux,Sgf_S_mux};
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, k, m, x, ans = 0; cin >> n >> k >> m; vector<pair<long long, long long> > v; for (int i = 0; i < n; i++) { cin >> x; if (v.empty() || (v.back().first != x)) { v.push_back({x, 1}); } else if (v.back().first == x) { v.back().second = (v.back().second + 1) % k; if (v.back().second == 0) v.pop_back(); } } if (v.size() == 0) return cout << 0, 0; if (v.size() == 1) { return cout << ((v[0].second * m) % k), 0; } for (auto &i : v) { ans += m * i.second; } if (m == 1) return cout << ans, 0; long long rem = 0; int back = v.size() - 1, front = 0; while (back > front) { if ((v[front].first != v[back].first)) { break; } else { rem += ((v[front].second + v[back].second) - ((v[front].second + v[back].second) % k)) * (m - 1); if ((v[front].second + v[back].second) % k) break; } back--; front++; } if (back == front) { rem += ((v[back].second) * m) - ((v[back].second) * m) % k; if (((v[back].second) * m) % k == 0) { back--; front++; } } if (back < front) while (back >= 0) { if ((v[front].first != v[back].first)) { break; } else { rem += ((v[front].second + v[back].second) - ((v[front].second + v[back].second) % k)); if ((v[front].second + v[back].second) % k) break; } back--; front++; } cout << (ans - rem); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int> > a_sent; vector<pair<int, int> > b_sent; set<pair<int, int> > a_possible; set<pair<int, int> > b_possible; int vis[10]; bool certain(pair<int, int> a, vector<pair<int, int> > sent) { bool can_x = false; bool can_y = false; for (pair<int, int> b : sent) { if (0) { printf( has: [%d, %d], try: [%d, %d] n , a.first, a.second, b.first, b.second); } if (a.first == b.first && a.second == b.second) continue; if (a.first == b.second && a.second == b.first) continue; if (a.first != b.first && a.second != b.second && a.first != b.second && a.second != b.first) continue; if (a.first == b.first || a.first == b.second) can_x = true; if (a.second == b.first || a.second == b.second) can_y = true; } if (0) printf( can_x: %d, can_y: %d n , can_x, can_y); return (can_x && !can_y) || (can_y && !can_x); } int main() { cin >> n >> m; while (n--) { pair<int, int> pair; cin >> pair.first >> pair.second; if (pair.first < pair.second) swap(pair.first, pair.second); a_sent.push_back(pair); } while (m--) { pair<int, int> pair; cin >> pair.first >> pair.second; if (pair.first < pair.second) swap(pair.first, pair.second); b_sent.push_back(pair); } for (pair<int, int> a : a_sent) { for (pair<int, int> b : b_sent) { if (a.first == b.first && a.second == b.second) continue; if (a.first == b.second && a.second == b.first) continue; if (a.first != b.first && a.second != b.second && a.first != b.second && a.second != b.first) continue; if (a.first == b.first) vis[a.first]++; if (a.second == b.second) vis[a.second]++; if (a.first == b.second) vis[a.first]++; if (a.second == b.first) vis[a.second]++; a_possible.insert(a); b_possible.insert(b); } } int cnt = 0; for (int i = 1; i <= 9; ++i) { cnt += vis[i] >= 1; if (0) printf( vis[%d] = %d n , i, vis[i]); } if (0) cout << cnt << endl; if (cnt == 1) { for (int i = 1; i <= 9; ++i) { if (vis[i] >= 1) { cout << i << endl; return 0; } } } for (pair<int, int> a : a_possible) { if (!certain(a, b_sent)) { cout << -1 << endl; return 0; } } for (pair<int, int> b : b_possible) { if (!certain(b, a_sent)) { cout << -1 << endl; return 0; } } cout << 0 << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, k, f[101][50001], a[101], b[101]; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 0; i <= 100; i++) for (int j = 0; j <= 50000; j++) f[i][j] = -99999999; f[0][20000] = 0; for (int i = 1; i <= n; i++) for (int j = -10000; j <= 10000; j++) f[i][j + 20000] = max(f[i][j + 20000], max(f[i - 1][j + 20000], f[i - 1][j - a[i] + k * b[i] + 20000] + a[i])); int ans = -1; if (f[n][20000]) ans = f[n][20000]; printf( %d , ans); }
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#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> a(n); for (long long& i : a) cin >> i; vector<long long> pre(n), suf(n); long long cnt{1}; pre[0] = 1; for (long long i = 1; i < n; i++) { if (a[i] > a[i - 1]) { cnt++; } else { cnt = 1; } pre[i] = cnt; } suf[n - 1] = 1; cnt = 1; for (long long i = n - 2; i >= 0; i--) { if (a[i] < a[i + 1]) { cnt++; } else { cnt = 1; } suf[i] = cnt; } long long mx{1}; for (long long i = 0; i < n - 2; i++) { long long x = pre[i]; long long y = suf[i + 2]; if (a[i] + 1 < a[i + 2]) { mx = max(mx, x + y + 1); } else { mx = max(mx, max(pre[i] + 1, suf[i + 2] + 1)); } } if (n >= 2) { mx = max(mx, suf[1] + 1); mx = max(mx, pre[n - 2] + 1); } cout << mx; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); solve(); }
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#include <bits/stdc++.h> #pragma GCC optimize(3) #pragma GCC optimize(2) using namespace std; set<int> st; set<pair<long long, int>> bus[200011]; map<long long, set<pair<int, int>>> q; int n, k, m; int main() { int i; scanf( %d%d%d , &n, &k, &m); for (i = 1; i <= k; ++i) { int xi; scanf( %d , &xi); st.insert(xi); bus[xi].insert(make_pair(0, i)); } while (m-- > 0) { long long ti; int a, b; scanf( %I64d%d%d , &ti, &a, &b); while (!q.empty()) { auto iter = q.begin(); if (iter->first > ti) break; for (auto p : iter->second) { st.insert(p.first); bus[p.first].insert(make_pair(iter->first, p.second)); } q.erase(iter->first); } if (!st.empty()) { auto iter = st.upper_bound(a); pair<int, pair<long long, int>> car = make_pair(1e6, make_pair(1e14, 1e6)); bool ok = false; if (iter != st.end()) { car.first = *iter; car.second = *bus[car.first].begin(); ok = true; } if (iter != st.begin()) { iter = prev(iter); if (ok) { int pos = *iter; if ((abs(pos - a) < abs(car.first - a)) || (abs(pos - a) == abs(car.first - a) && car.second > *bus[pos].begin())) { car.first = pos; car.second = *bus[pos].begin(); } } else { car.first = *iter; car.second = *bus[car.first].begin(); } } printf( %d %d n , car.second.second, abs(car.first - a)); bus[car.first].erase(car.second); if (bus[car.first].empty()) st.erase(car.first); long long finish = ti + abs(car.first - a) + abs(b - a); q[finish].insert(make_pair(b, car.second.second)); } else { long long t = q.begin()->first; auto iter = q[t].upper_bound(make_pair(a, 0)); pair<int, int> car = make_pair(0, 0); if (iter != q[t].end()) { car = *iter; } if (iter != q[t].begin()) { iter = prev(iter); iter = q[t].upper_bound(make_pair(iter->first, 0)); if (car.first != 0) { if ((abs(car.first - a) > abs(iter->first - a)) || ((abs(car.first - a) == abs(iter->first - a)) && car.second > iter->second)) { car = *iter; } } else { car = *iter; } } printf( %d %I64d n , car.second, abs(t - ti) + abs(car.first - a)); q[t].erase(car); if (q[t].empty()) q.erase(t); q[t + abs(car.first - a) + abs(b - a)].insert(make_pair(b, car.second)); } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int dd = (int)2e6 + 7; int A[dd], cnt[dd]; long long tmp[dd]; pair<int, int> msk[20]; int count2[20], w; long long pw[20]; long long ans = 0; void get(int i, long long k) { if (i == w) { ans += tmp[k]; return; } if (count2[i] == 1) { get(i + 1, k + pw[i] * msk[i].first); return; } get(i + 1, k + pw[i] * msk[i].first); get(i + 1, k + pw[i] * msk[i].second); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> w >> n >> m; for (int i = 0; i < n; ++i) { cin >> A[i]; cnt[A[i]]++; } pw[0] = 1; for (int i = 1; i <= w; ++i) { pw[i] = pw[i - 1] * 3; } for (int i = 0; i < (1 << w); ++i) if (cnt[i]) { for (int j = 0; j < (1 << w); ++j) if (cnt[j]) { int k = 0; for (int l = 0; l < w; ++l) { int ii = (i >> l) & 1, jj = (j >> l) & 1; if (ii == jj && ii == 1) { k += 2 * pw[l]; } if (ii != jj) { k += pw[l]; } } tmp[k] += cnt[i] * cnt[j]; } } while (m--) { string s; cin >> s; reverse(s.begin(), s.end()); for (int i = 0; i < w; ++i) { if (s[i] == A ) msk[i] = {0, 1}, count2[i] = 2; if (s[i] == O ) msk[i] = {0, 0}, count2[i] = 1; if (s[i] == X ) msk[i] = {0, 2}, count2[i] = 2; if (s[i] == a ) msk[i] = {2, 2}, count2[i] = 1; if (s[i] == o ) msk[i] = {1, 2}, count2[i] = 2; if (s[i] == x ) msk[i] = {1, 1}, count2[i] = 1; } ans = 0; get(0, 0); cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& p) { in >> p.first >> p.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> p) { out << p.first << << p.second; return out; } template <typename T> istream& operator>>(istream& in, vector<T>& arr) { for (auto& i : arr) { in >> i; } return in; } template <typename T> ostream& operator<<(ostream& out, vector<T> arr) { for (int64_t i = 0; i < (int64_t)arr.size() - 1; ++i) out << arr[i] << ; if (arr.size()) out << arr.back(); out << n ; return out; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int64_t n; cin >> n; vector<int64_t> v(n); cin >> v; vector<int64_t> t(n); cin >> t; vector<int64_t> preft(n + 1); for (int64_t i = 0; i < n; ++i) { preft[i + 1] = preft[i] + t[i]; } vector<int64_t> bal(n + 1); vector<int64_t> pls(n); for (int64_t i = 0; i < n; ++i) { if (preft.back() - preft[i] <= v[i]) { bal[i] += 1; bal[n] -= 1; continue; } if (t[i] > v[i]) { pls[i] += v[i]; continue; } int64_t l = i, r = n; while (r - l > 1) { int64_t m = (r + l) / 2; if (v[i] > preft[m] - preft[i]) { l = m; } else { r = m; } } bal[i] += 1; bal[l] -= 1; pls[l] += v[i] - (preft[l] - preft[i]); } for (int64_t i = 1; i < n; ++i) { bal[i] += bal[i - 1]; } for (int64_t i = 0; i < n; ++i) { cout << bal[i] * t[i] + pls[i] << ; } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e5 * 2 + 7; int a[maxn], b[maxn], t[4 * maxn], n, W, H; void build(int v, int l, int r) { if (r - l == 1) { t[v] = a[l]; return; } build(2 * v + 1, l, (l + r) / 2); build(2 * v + 2, (l + r) / 2, r); t[v] = max(t[2 * v + 1], t[2 * v + 2]); } int get(int v, int l, int r, int ql, int qr) { if (ql <= l && qr >= r) return t[v]; if (ql >= r || qr <= l) return 0; return max(get(2 * v + 1, l, (l + r) / 2, ql, qr), get(2 * v + 2, (l + r) / 2, r, ql, qr)); } void upd(int v, int l, int r, int pos, int x) { if (r - l == 1) { t[v] = x; return; } if (pos < (l + r) / 2) { upd(2 * v + 1, l, (l + r) / 2, pos, x); } else { upd(2 * v + 2, (l + r) / 2, r, pos, x); } t[v] = max(t[2 * v + 1], t[2 * v + 2]); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { int ww, hh; scanf( %d %d , &ww, &hh); a[i] = hh; b[i] = ww; W += ww; } build(0, 0, n); for (int i = 0; i < n; i++) { W -= b[i]; upd(0, 0, n, i, -10000); H = get(0, 0, n, 0, n); printf( %d , H * W); W += b[i]; upd(0, 0, n, i, a[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[50005]; map<string, int> st; int sq = 300; vector<int> p[500100]; vector<int> h; string s1[500100]; int res[1010][1010]; void pro(int x1, int y1) { int x = h[x1]; int y = h[y1]; int pri = -1, prj = -1; int mn = 1e9; int r; for (int i = 0, j = 0; i < p[x].size() || j < p[y].size();) { if (i < p[x].size() && j < p[y].size()) { r = max(p[x][i] + s1[x].size(), p[y][j] + s1[y].size()) - min(p[x][i], p[y][j]); mn = min(mn, r); } if (i >= p[x].size()) prj = p[y][j], j++; else if (j >= p[y].size()) pri = p[x][i], i++; else if (p[x][i] < p[y][j]) pri = p[x][i], i++; else prj = p[x][j], j++; } res[x1][y1] = mn; res[y1][x1] = mn; } int main() { scanf( %s , s); int n = strlen(s); int k = 0; for (int i = 0; i < n; i++) { string t = ; for (int j = 0; j < 4 && j + i < n; j++) { t.push_back(s[j + i]); if (st.count(t) == 0) { s1[k] = t; st[t] = k++; } p[st[t]].push_back(i); } } for (int i = 0; i < k; i++) { if (p[i].size() > sq) { h.push_back(i); } } for (int i = 0; i < h.size(); i++) { res[i][i] = s1[h[i]].size(); for (int j = i + 1; j < h.size(); j++) { pro(i, j); } } int q; cin >> q; char s2[10]; char s3[10]; vector<int>::iterator it, it1; while (q--) { scanf( %s , s2); scanf( %s , s3); if (st.count(s2) == 0 || st.count(s3) == 0) { printf( -1 n ); continue; } int x = st[s2]; int y = st[s3]; it = lower_bound(h.begin(), h.end(), x); it1 = lower_bound(h.begin(), h.end(), y); int mn = 1e9, r; if (it != h.end() && *it == x && it1 != h.end() && *it1 == y) { printf( %d n , res[it - h.begin()][it1 - h.begin()]); continue; } else if (it == h.end() || *it != x) { for (int i = 0; i < p[x].size(); i++) { it = lower_bound(p[y].begin(), p[y].end(), p[x][i]); if (it != p[y].end()) { r = max(p[x][i] + s1[x].size(), *it + s1[y].size()); r -= min(p[x][i], *it); mn = min(mn, r); } if (it != p[y].begin()) { it--; r = max(p[x][i] + s1[x].size(), *it + s1[y].size()); r -= min(p[x][i], *it); mn = min(mn, r); } } } else { for (int i = 0; i < p[y].size(); i++) { it = lower_bound(p[x].begin(), p[x].end(), p[y][i]); if (it != p[x].end()) { r = max(p[y][i] + s1[y].size(), *it + s1[x].size()); r -= min(p[y][i], *it); mn = min(mn, r); } if (it != p[x].begin()) { it--; r = max(p[y][i] + s1[y].size(), *it + s1[x].size()); r -= min(p[y][i], *it); mn = min(mn, r); } } } printf( %d n , mn); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 10; int cnt[MAX]; vector<int> up, down; int main() { ios::sync_with_stdio(false); memset(cnt, 0, sizeof(cnt)); int n, x, max_num = -1; cin >> n; for (int i = 0; i < n; i++) { cin >> x; cnt[x]++; max_num = max(max_num, x); } for (int i = 0; i <= max_num; i++) { if (cnt[i] > 2) { cout << NO << endl; return 0; } } for (int i = max_num; i >= 0; i--) { if (cnt[i]) { down.push_back(i); cnt[i]--; } } for (int i = 0; i <= max_num; i++) { if (cnt[i]) { up.push_back(i); cnt[i]--; } } cout << YES << endl; cout << up.size() << endl; if (up.size() > 0) { for (int i = 0; i < up.size() - 1; i++) cout << up[i] << ; cout << up[up.size() - 1] << endl; } else { cout << << endl; } cout << down.size() << endl; if (down.size() > 0) { for (int i = 0; i < down.size() - 1; i++) cout << down[i] << ; cout << down[down.size() - 1] << endl; } else { cout << << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_V
/**
* sdfrtp_ov2: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_V
|
#include <bits/stdc++.h> int n = 0, m = 0, a[100002], b[1000002], c[1000002]; int main() { while (scanf( %d , &n) != EOF) { memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); if (n == 0) continue; int max = 0; int p = 0, q = 0, k = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); b[a[i]]++; if (b[a[i]] == 1) c[a[i]] = i; if (b[a[i]] > max) { max = b[a[i]]; k = a[i]; q = i; } if (b[a[i]] == max) { if (i - c[a[i]] < q - c[a[q]]) { q = i; k = a[i]; } } } for (int j = 0; j <= q; j++) { if (a[j] == k) { p = j; break; } } printf( %d %d n , p + 1, q + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5009; bool f[maxn][maxn], vis[maxn]; int pre[maxn][maxn], a[maxn]; int n, k, v, sum, cnt; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void update(int x, int y, int opt) { f[x][y] = 1; pre[x][y] = opt; } int calc(int x) { return x / k + bool(x % k); } void work(int x, int y) { if (x == 0) return; if (pre[x][y]) { vis[x] = 1; cnt++; sum += a[x]; work(x - 1, (y - a[x] % k + k) % k); } else work(x - 1, y); } int main() { n = read(); k = read(); v = read(); for (int i = 1; i <= n; i++) a[i] = read(), sum += a[i]; if (sum < v) { puts( NO ); return 0; } f[0][0] = 1; for (int i = 0; i < n; i++) for (int j = 0; j < k; j++) if (f[i][j]) { update(i + 1, j, 0); update(i + 1, (j + a[i + 1]) % k, 1); } int tmp; for (tmp = n; tmp; tmp--) if (f[tmp][v % k]) break; if (tmp == 0) puts( NO ); else { puts( YES ); work(tmp, v % k); if (cnt == 0 || cnt == n) { for (int i = 2; i <= n; i++) { if (calc(a[i])) printf( %d %d 1 n , calc(a[i]), i); a[1] += a[i]; } if (cnt == 0 && v) printf( %d 1 2 n , v / k); if (cnt && a[1] - v) printf( %d 1 2 n , (a[1] - v) / k); } else { int L = 1, R = 1; for (; L <= n && !vis[L]; L++) ; for (; R <= n && vis[R]; R++) ; for (int i = 1; i <= n; i++) if (vis[i] && i != L) { if (calc(a[i])) printf( %d %d %d n , calc(a[i]), i, L); a[L] += a[i]; } for (int i = 1; i <= n; i++) if (!vis[i] && i != R) { if (calc(a[i])) printf( %d %d %d n , calc(a[i]), i, R); a[R] += a[i]; } if (a[L] > v) printf( %d %d %d n , (a[L] - v) / k, L, R); else if (a[L] < v) printf( %d %d %d n , (v - a[L]) / k, R, L); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sub; int grp; cin >> n >> sub; if (n == sub) grp = 0; else if (sub == 0 || sub == 1) grp = 1; else if (sub >= n - n / 2) grp = n - sub; else grp = sub; cout << grp << endl; }
|
module DM9000A_IF( // HOST Side
iDATA,
oDATA,
iCMD,
iRD_N,
iWR_N,
iCS_N,
iRST_N,
iCLK,
iOSC_50,
oINT,
// DM9000A Side
ENET_DATA,
ENET_CMD,
ENET_RD_N,
ENET_WR_N,
ENET_CS_N,
ENET_RST_N,
ENET_INT,
ENET_CLK );
// HOST Side
input [15:0] iDATA;
input iCMD;
input iRD_N;
input iWR_N;
input iCS_N;
input iRST_N;
input iCLK;
input iOSC_50;
output [15:0] oDATA;
output oINT;
// DM9000A Side
inout [15:0] ENET_DATA;
output ENET_CMD;
output ENET_RD_N;
output ENET_WR_N;
output ENET_CS_N;
output ENET_RST_N;
output ENET_CLK;
input ENET_INT;
reg [15:0] TMP_DATA;
reg ENET_CMD;
reg ENET_RD_N;
reg ENET_WR_N;
reg ENET_CS_N;
reg ENET_CLK;
reg [15:0] oDATA;
reg oINT;
assign ENET_DATA = ENET_WR_N ? 16'hzzzz : TMP_DATA;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
TMP_DATA <= 0;
ENET_CMD <= 0;
ENET_RD_N <= 1;
ENET_WR_N <= 1;
ENET_CS_N <= 1;
oDATA <= 0;
oINT <= 0;
end
else
begin
oDATA <= ENET_DATA;
oINT <= ENET_INT;
TMP_DATA <= iDATA;
ENET_CMD <= iCMD;
ENET_CS_N <= iCS_N;
ENET_RD_N <= iRD_N;
ENET_WR_N <= iWR_N;
end
end
always@(posedge iOSC_50)
ENET_CLK <= ~ENET_CLK;
assign ENET_RST_N = iRST_N;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_1_V
`define SKY130_FD_SC_HD__EBUFN_1_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ebufn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ebufn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_1_V
|
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module cpu(
input clk,
input rst,
output mem_re,
output mem_we,
output reg [29:0] memaddr,
input [31:0] rmemdata,
output [31:0] wmemdata,
output [31:0] debugout
);
assign wmemdata = (mem_we && !mem_re) ? reg_c : 32'bz;
assign debugout = pc;
/* next pc */
reg [29:0] pc;
reg [29:0] nextpc;
reg [3:0] control_branch;
`define CONTROL_BRANCH_NOTAKE 4'b1xxx
`define CONTROL_BRANCH_UNCOND 4'b000?
`define CONTROL_BRANCH_COND_Z 4'b0010
`define CONTROL_BRANCH_COND_NZ 4'b0011
`define CONTROL_BRANCH_RA_UNCOND 4'b010?
`define CONTROL_BRANCH_RA_COND_Z 4'b0110
`define CONTROL_BRANCH_RA_COND_NZ 4'b0111
always @(control_branch or reg_c or aluout or reg_a or pc)
begin
casex (control_branch)
`CONTROL_BRANCH_NOTAKE: nextpc = pc;
`CONTROL_BRANCH_COND_Z: nextpc = (reg_c == 32'd0) ? aluout[29:0] : pc;
`CONTROL_BRANCH_COND_NZ: nextpc = (reg_c != 32'd0) ? aluout[29:0] : pc;
`CONTROL_BRANCH_UNCOND: nextpc = aluout[29:0];
`CONTROL_BRANCH_RA_COND_Z: nextpc = (reg_c == 32'd0) ? (reg_a >> 2) : pc;
`CONTROL_BRANCH_RA_COND_NZ: nextpc = (reg_c != 32'd0) ? (reg_a >> 2) : pc;
`CONTROL_BRANCH_RA_UNCOND: nextpc = (reg_a >> 2);
endcase
end
`define STATE_RST 3'd0
`define STATE_FETCH 3'd1
`define STATE_DECODE 3'd2
`define STATE_LOAD 3'd3
`define STATE_STORE 3'd4
reg [2:0] state;
reg control_load;
reg control_store;
/* top level states */
reg [2:0] nextstate;
always @(rst or state or control_load or control_store)
begin
if (rst)
nextstate = `STATE_RST;
else if (state == `STATE_RST || state == `STATE_LOAD || state == `STATE_STORE)
nextstate = `STATE_FETCH;
else if (state == `STATE_FETCH)
nextstate = `STATE_DECODE;
else if (control_load)
nextstate = `STATE_LOAD;
else if (control_store)
nextstate = `STATE_STORE;
else
nextstate = `STATE_FETCH;
end
assign mem_we = (nextstate == `STATE_STORE);
assign mem_re = ((nextstate == `STATE_FETCH) || (nextstate == `STATE_LOAD));
always @(nextstate or pc or nextpc or aluout)
begin
case (nextstate)
`STATE_RST: memaddr = pc;
`STATE_FETCH: memaddr = nextpc;
`STATE_DECODE: memaddr = 30'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
`STATE_LOAD: memaddr = aluout[31:2];
`STATE_STORE: memaddr = aluout[31:2];
default: memaddr = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
end
always @(posedge clk)
begin
state <= nextstate;
case (nextstate)
`STATE_RST: begin
pc <= 0;
end
`STATE_FETCH: begin
pc <= nextpc;
end
`STATE_DECODE: begin
pc <= aluout[29:0];
ir <= rmemdata;
end
endcase
end
/* alu */
reg [3:0] aluop;
wire [31:0] aluout;
wire [31:0] aluain;
wire [31:0] alubin;
alu alu0(
.op(aluop),
.a(aluain),
.b(alubin),
.res(aluout)
);
/* register file */
reg [3:0] reg_a_sel;
reg [3:0] reg_b_sel;
reg [3:0] reg_w_sel;
wire [31:0] reg_a;
wire [31:0] reg_b;
wire [31:0] reg_c;
wire [31:0] reg_wdata;
reg control_reg_wb;
regfile #(32, 4) regs(
.clk(clk),
.we(control_reg_wb),
.wsel(reg_w_sel),
.wdata(reg_wdata),
.asel(reg_a_sel),
.adata(reg_a),
.bsel(reg_b_sel),
.bdata(reg_b),
.csel(decode_rd),
.cdata(reg_c)
);
/* alu a input mux */
reg alu_a_mux_sel;
`define ALU_A_SEL_DC 1'bx
`define ALU_A_SEL_REG 1'b0
`define ALU_A_SEL_PC 1'b1
mux2 #(32) alu_a_mux(
.sel(alu_a_mux_sel),
.in0(reg_a),
.in1({ 2'b0, pc }),
.out(aluain)
);
/* alu b input mux */
reg [1:0] alu_b_mux_sel;
`define ALU_B_SEL_DC 2'bxx
`define ALU_B_SEL_REG 2'b00
`define ALU_B_SEL_IMM16 2'b01
`define ALU_B_SEL_IMM22 2'b10
`define ALU_B_SEL_ONE 2'b11
mux4 #(32) alu_b_mux(
.sel(alu_b_mux_sel),
.in0(reg_b),
.in1(decode_imm16_signed),
.in2(decode_imm22_signed),
.in3(32'd1),
.out(alubin)
);
/* register file write mux */
reg [1:0] reg_w_mux_sel;
`define REG_W_SEL_DC 2'bxx
`define REG_W_SEL_ALU 2'b00
`define REG_W_SEL_MEM 2'b01
`define REG_W_SEL_PC 2'b10
`define REG_W_SEL_ZERO 2'b11
mux4 #(32) reg_w_mux(
.sel(reg_w_mux_sel),
.in0(aluout),
.in1(rmemdata),
.in2({ pc, 2'b0 }),
.in3(0),
.out(reg_wdata)
);
/* decoder */
reg [31:0] ir;
wire [1:0] decode_form = ir[31:30];
wire [5:0] decode_op = ir[29:24];
wire [3:0] decode_rd = ir[27:24];
wire [3:0] decode_aluop = ir[23:20];
wire [3:0] decode_ra = ir[19:16];
wire [3:0] decode_rb = ir[15:12];
wire [31:0] decode_imm16_signed = (ir[15]) ? { 16'b1111111111111111, ir[15:0] } : { 16'b0000000000000000, ir[15:0] };
wire [31:0] decode_imm22_signed = (ir[21]) ? { 10'b1111111111, ir[21:0] } : { 10'b0000000000, ir[21:0] };
always @(ir or state or decode_form or decode_op or decode_rd or decode_aluop or decode_ra or decode_rb or decode_imm16_signed or decode_imm22_signed)
begin
/* undefined state */
aluop = 4'bxxxx;
control_load = 0;
control_store = 0;
control_branch = `CONTROL_BRANCH_NOTAKE;
control_reg_wb = 0;
reg_a_sel = 4'bxxxx;
reg_b_sel = 4'bxxxx;
reg_w_sel = 4'bxxxx;
alu_a_mux_sel = `ALU_A_SEL_DC;
alu_b_mux_sel = `ALU_B_SEL_DC;
reg_w_mux_sel = `REG_W_SEL_DC;
case (state)
`STATE_FETCH: begin
/* use the alu to calculate the next pc */
aluop = 4'b0000; // add
alu_a_mux_sel = `ALU_A_SEL_PC;
alu_b_mux_sel = `ALU_B_SEL_ONE;
end
`STATE_DECODE: begin
casex (decode_form)
2'b0?: begin /* form 0 and form 1 are very similar */
aluop = decode_aluop;
reg_a_sel = decode_ra;
reg_b_sel = decode_rb;
if (decode_form == 0) begin
$display("form 0");
alu_a_mux_sel = `ALU_A_SEL_REG;
alu_b_mux_sel = `ALU_B_SEL_IMM16;
end else begin
$display("form 1");
alu_a_mux_sel = `ALU_A_SEL_REG;
alu_b_mux_sel = `ALU_B_SEL_REG;
end
casex (decode_op)
default: begin
control_reg_wb = 1;
reg_w_sel = decode_rd;
reg_w_mux_sel = `REG_W_SEL_ALU;
end
/* load */
6'b01????: begin
$display("load");
control_load = 1;
end
/* store */
6'b10????: begin
$display("store");
control_store = 1;
end
endcase
end
2'b10: begin
$display("form 2 - branch");
if (ir[29] == 0) begin
// pc relative branch
aluop = 0; // add
control_branch = { 1'b0, 1'b0, ir[23], ir[22] };
alu_a_mux_sel = `ALU_A_SEL_PC;
alu_b_mux_sel = `ALU_B_SEL_IMM22;
end else begin
// branch to reg
control_branch = { 1'b0, 1'b1, ir[23], ir[22] };
reg_a_sel = decode_ra;
end
// branch and link
if (ir[28]) begin
reg_w_sel = 15; // LR
reg_w_mux_sel = `REG_W_SEL_PC;
control_reg_wb = 1;
end
end
2'b11: begin
$display("form 3 - undefined");
end
endcase
end
`STATE_LOAD: begin
control_reg_wb = 1;
reg_w_sel = decode_rd;
reg_w_mux_sel = `REG_W_SEL_MEM;
end
default: begin
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_1_V
`define SKY130_FD_SC_HDLL__CLKBUF_1_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n == 0) { cout << 0 << endl; } else if ((n + 1) % 2 == 0) { cout << (n + 1) / 2 << endl; } else { cout << n + 1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void BFS(vector<vector<long long> > &graph, long long n, vector<long long> &order) { vector<long long> vis(n + 1); set<long long> PQ; PQ.insert(1); while (!PQ.empty()) { long long x = *PQ.begin(); PQ.erase(PQ.begin()); order.push_back(x); vis[x] = 1; for (long long i = 0; i < graph[x].size(); i++) { if (vis[graph[x][i]] == 0) PQ.insert(graph[x][i]); } } } int main() { long long n, m, i, j, k, l, w, u, v, t_sum = 0; cin >> n >> m; vector<vector<long long> > graph(n + 1); for (i = 1; i <= m; i++) { cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } vector<long long> order; BFS(graph, n, order); for (i = 0; i < order.size(); i++) cout << order[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; namespace number_theory { long long gcd(long long x, long long y) { if (x == 0) return y; if (y == 0) return x; return gcd(y, x % y); } bool isprime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i += 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool prime[15000105]; void sieve(long long n) { for (long long i = 0; i <= n; i++) prime[i] = 1; for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } prime[1] = prime[0] = 0; } vector<long long> primelist; bool __primes_generated__ = 0; void genprimes(long long n) { __primes_generated__ = 1; sieve(n + 1); for (long long i = 2; i <= n; i++) if (prime[i]) primelist.push_back(i); } vector<long long> factors(long long n) { if (!__primes_generated__) { cerr << Caint genprimes you dope << endl; exit(1); } vector<long long> facs; for (long long i = 0; primelist[i] * primelist[i] <= n && i < primelist.size(); i++) { if (n % primelist[i] == 0) { while (n % primelist[i] == 0) { n /= primelist[i]; facs.push_back(primelist[i]); } } } if (n > 1) { facs.push_back(n); } sort(facs.begin(), facs.end()); return facs; } vector<long long> getdivs(long long n) { vector<long long> divs; for (long long i = 1; i * i <= n; i++) { if (n % i == 0) { divs.push_back(i); divs.push_back(n / i); } } { sort(divs.begin(), divs.end()); divs.erase(unique(divs.begin(), divs.end()), divs.end()); }; return divs; } } // namespace number_theory void solve() { long long n, k; cin >> n >> k; string s; cin >> s; long long win = 0, loss = 0, winning_streak_cnt = 0; vector<long long> lossing_streak; for (long long i = 0; i < n; i++) { if (s[i] == W ) { win++; if (i == 0 or s[i - 1] == L ) winning_streak_cnt++; } else { loss++; if (i == 0 or s[i - 1] == W ) lossing_streak.push_back(0); lossing_streak.back()++; } } if (k >= loss) { cout << 2 * n - 1 << n ; return; } if (win == 0) { if (k == 0) cout << 0; else cout << 2 * k - 1; cout << n ; return; } win += k; if (s[0] == L ) lossing_streak[0] = 1e8; if (s[n - 1] == L ) lossing_streak.back() = 1e8; sort(lossing_streak.begin(), lossing_streak.end()); for (long long ls : lossing_streak) { if (ls > k) break; k -= ls; winning_streak_cnt--; } cout << 2 * win - winning_streak_cnt << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); long long t; cin >> t; while (t--) { solve(); } return 0; }
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module JOUST_ROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("JOUST_ROM.mif"),
.C_INIT_FILE("JOUST_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long ca; cin >> ca; while (ca--) { long long n, i, j, k, l, r, m; cin >> l >> r >> m; for (i = l; i <= r; i++) { long long x1, x2; x1 = m / i; if (m % i != 0) x2 = m / i + 1; else x2 = m / i; long long y1 = m - (x1 * i); long long y2 = (x2 * i) - m; long long lim = r - l; if (y1 <= lim && x1 > 0) { cout << i << << l + y1 << << l << endl; break; } if (y2 <= lim && x2 > 0) { cout << i << << l << << l + y2 << endl; break; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, m, n, k, x, y, sum = 0; cin >> n >> k; vector<long long> sura; vector<pair<long long, long long> > dada; vector<pair<long long, long long> > dada2; vector<long long> su; long long arr[n]; priority_queue<long long, vector<long long>, greater<long long> > pq; for (i = 0; i < n; i++) { cin >> x; sura.push_back(x); } for (i = 0; i < n; i++) { cin >> x; dada.push_back(make_pair(sura[i], x)); dada2.push_back(make_pair(sura[i], i)); } sort(dada.begin(), dada.end()); sort(dada2.begin(), dada2.end()); for (i = 0; i < n; i++) { if (k == 0) { su.push_back(sum + dada[i].second); } else if (k > 0) { su.push_back(sum + dada[i].second); if (i < k) { sum += dada[i].second; pq.push(dada[i].second); } else { if (dada[i].second > pq.top()) { sum -= pq.top(); pq.pop(); sum += dada[i].second; pq.push(dada[i].second); } } } } for (i = 0; i < n; i++) { arr[dada2[i].second] = su[i]; } for (i = 0; i < n; i++) { cout << arr[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, a, b, x; cin >> t; while (t--) { cin >> a >> b; if (a < b) { x = b - a; x % 2 == 0 ? cout << 2 : cout << 1; } else if (a > b) { x = a - b; x % 2 == 0 ? cout << 1 : cout << 2; } else cout << 0; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, a; int A[6]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &A[i]); } sort(A, A + n); printf( %d , A[n / 2]); return 0; }
|
module dualport_RAM(clk, d_in_1, d_out_1, addr_1, rd_1, wr_1, d_in_2, d_out_2, addr_2, rd_2, wr_2);
input clk;
input [15:0]d_in_1;
output reg [15:0]d_out_1=0;
input [7:0]addr_1; // 8 LSB from address
input rd_1;
input wr_1;
input [15:0]d_in_2;
output reg [15:0]d_out_2=0;
input [7:0]addr_2; // 8 LSB from address
input rd_2;
input wr_2;
// Declare the RAM variable
reg [7:0] ram [0:31]; // 32-bit x 8-bit RAM
always @(negedge clk)
begin
//------------------ port 1 : core J1---------------------
if (rd_1) begin
d_out_1[7:0] <= ram[addr_1];
d_out_1[15:8] <= ram[addr_1+1];
end
else if(wr_1) begin
ram[addr_1] <= d_in_1[7:0];
ram[addr_1+1] <= d_in_1[15:8];
end
//------------------ port 1 : core J1---------------------
//------------------ port 2 : core peripheric-------------
else if (rd_2) begin
d_out_2[7:0] <= ram[addr_2];
d_out_2[15:8] <= ram[addr_2+1];
end
else if(wr_2) begin
ram[addr_2] <= d_in_2[7:0];
ram[addr_2+1] <= d_in_2[15:8];
end
// else
// ram[addr_2] <= ram[addr_2];
//------------------ port 2 : core peripheric-------------
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4BB_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7, N = 1e6 + 5; char a[51][51]; int n, m; int vis[51][51]; void dfs(int i, int j) { vis[i][j] = 1; if (i - 1 >= 0 and a[i - 1][j] == # and vis[i - 1][j] == 0) dfs(i - 1, j); if (i + 1 < n and a[i + 1][j] == # and vis[i + 1][j] == 0) dfs(i + 1, j); if (j - 1 >= 0 and a[i][j - 1] == # and vis[i][j - 1] == 0) dfs(i, j - 1); if (j + 1 < m and a[i][j + 1] == # and vis[i][j + 1] == 0) dfs(i, j + 1); } int func() { for (int i = 0; i < 51; i++) for (int j = 0; j < 51; j++) vis[i][j] = 0; int check = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == # ) check = 1, dfs(i, j); if (check) break; } if (check) break; } check = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == # and vis[i][j] == 0) { check = 0; break; } } } return check; } int main() { ios::sync_with_stdio(false), cin.tie(nullptr); cin >> n >> m; int cnt = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == # ) cnt++; } } if (cnt <= 2) cout << -1, exit(0); int ans = 2; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == # ) { a[i][j] = . ; if (func() == 0) { ans = 1; break; } a[i][j] = # ; } } if (ans == 1) break; } cout << ans; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_FUNCTIONAL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:11 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.4 2005/11/30 14:04:15 wig Exp $
// $Date: 2005/11/30 14:04:15 $
// $Log: ent_ba.v,v $
// Revision 1.4 2005/11/30 14:04:15 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 400; int dp[N + 1][N + 1]; bool solve(string str, string t1, string t2) { int n = str.size(); int m = t1.size(); for (int j = 1; j <= m; ++j) dp[0][j] = -1; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= m; ++j) { dp[i][j] = -1; if (dp[i - 1][j] != -1) { dp[i][j] = dp[i - 1][j]; if (dp[i][j] < t2.size() && str[i - 1] == t2[dp[i][j]]) ++dp[i][j]; } if (j > 0 && str[i - 1] == t1[j - 1]) { dp[i][j] = max(dp[i][j], dp[i - 1][j - 1]); } } } return dp[n][m] >= (int)t2.size(); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int tc; cin >> tc; for (int ti = 0; ti < tc; ++ti) { string src, tar; cin >> src >> tar; bool works = false; for (int a = 1; a <= tar.size(); ++a) { string le, ri; for (int i = 0; i < a; ++i) le.push_back(tar[i]); for (int i = a; i < tar.size(); ++i) ri.push_back(tar[i]); if (solve(src, le, ri)) works = true; } if (works) cout << YES n ; else cout << NO n ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:46:40 03/26/2016
// Design Name:
// Module Name: compute
// Project Name:
// Target Devices:
// Tool versions:
// Description: sobel¼ÆËãÄ£¿é£¬ºËÐÄÄ£¿é
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module compute(
rst_i,
clk_i,
//´Ómemory¶Á³öµÄ32λÊý¾Ý
dat_i,
//״̬»ú¿ØÖÆÐźÅ
shift_en, //ÐźÅÓÐЧ£¬Ôò¸üÐÂresult_row
prev_row_load, //ÐźÅÓÐЧ£¬Ôò±íʾdat_iÊǵÚ1ÐеÄÊý¾Ý
curr_row_load, //ÐźÅÓÐЧ£¬Ôò±íʾdat_iÊǵÚ2ÐеÄÊý¾Ý
next_row_load, //ÐźÅÓÐЧ£¬Ôò±íʾdat_iÊǵÚ3ÐеÄÊý¾Ý
//ÔËËã½á¹û
result_row //°üº¬ËĸöÏñËصĽá¹û
);
input clk_i;
input rst_i;
input[31:0] dat_i;
input shift_en;
input prev_row_load;
input curr_row_load;
input next_row_load;
output[31:0] result_row;
reg [31:0] prev_row=0, curr_row=0, next_row=0;
reg [7:0] O[-1:1][-1:1]; //ÓÃÀ´´æ·Å´ý¼ÆËãµÄ9£¨3*3£©¸öÏñËØÖµ
reg signed [10:0] Dx=0, Dy=0;
reg [7:0] abs_D = 0 ;
reg [31:0] result_row =0 ; //´¢´æ¼ÆËã½á¹û£¬°üº¬ËĸöÏñËصļÆËã½á¹û
//-----------------------------------------------------------------------------
//µ±XXX_row_loadÓÐЧµÄʱºò£¬½«XXXÐеÄËĸöÏñËØÖµ¶ÁÈë32bit¼Ä´æÆ÷
//µ±shift_enÓÐЧʱ£¬32bit¼Ä´æÆ÷×óÒÆ1×Ö½Ú£¬ÒƳöÈ¥µÄ²¿·Ö½øÈë3*3¼Ä´æÆ÷[7:0] O[-1:1][-1:1]
//ͬʱ3*3¼Ä´æÆ÷Êä³öÒ»¸ö¼ÆËã½á¹û
always@(posedge clk_i)
if(prev_row_load)
prev_row <= dat_i;
else
if(shift_en)
prev_row[31:8] <= prev_row[23:0];
always@(posedge clk_i)
if(curr_row_load)
curr_row<= dat_i;
else
if(shift_en )
curr_row [31:8]<=curr_row[23:0];
always@(posedge clk_i)
if(next_row_load)
next_row<=dat_i;
else
if(shift_en )
next_row [31:8]<=next_row[23:0];
//------------------------------------------------------------------------------
//Çó¾ø¶ÔÖµ
function [10:0] abs ( input signed [10:0] x);
abs = x >=0 ? x : -x ;
endfunction
//-------------------------------------------------------------------------------
always @(posedge clk_i)
if(rst_i)
begin
O[-1][-1]<=0;
O[-1][ 0]<=0;
O[-1][+1]<=0;
O[ 0][-1]<=0;
O[ 0][ 0]<=0;
O[ 0][+1]<=0;
O[+1][-1]<=0;
O[+1][ 0]<=0;
O[+1][+1]<=0;
end
else
if ( shift_en )
begin
abs_D <= (abs(Dx) + abs(Dy))>>3;
Dx <= -$signed({3'b000, O[-1][-1]}) //-1* O[-1][-1]
+$signed({3'b000, O[-1][+1]}) //+1* O[-1][+1]
-($signed({3'b000, O[ 0][-1]})<<1) //-2* O[ 0][-1]
+($signed({3'b000, O[ 0][+1]})<<1) //+2* O[ 0][+1]
-$signed({3'b000, O[+1][-1]}) //-1* O[+1][-1]
+$signed({3'b000, O[+1][+1]}); //+1* O[+1][+1]
Dy <= $signed({3'b000, O[-1][-1]}) //+1* O[-1][-1]
+($signed({3'b000, O[-1][ 0]})<<1) //+2* O[-1][0]
+$signed({3'b000, O[-1][+1]}) //+1* O[-1][+1]
-$signed({3'b000, O[+1][-1]}) //-1* O[+1][-1]
-($signed({3'b000, O[+1][ 0]})<<1) //-2* O[+1][ 0]
-$signed({3'b000, O[+1][+1]}); //-1* O[+1][+1]
O[-1][-1] <= O[-1][0];
O[-1][ 0] <= O[-1][+1];
O[-1][+1] <= prev_row[31:24];
O[ 0][-1] <= O[0][0];
O[ 0][ 0] <= O[0][+1];
O[ 0][+1] <= curr_row[31:24];
O[+1][-1] <= O[+1][0];
O[+1][ 0] <= O[+1][+1];
O[+1][+1] <= next_row[31:24];
end
//----------------------------------------------------------------------------
//¸üÐÂÊä³ö
always @(posedge clk_i)
if(shift_en)
result_row <= { result_row[23:0], abs_D};
endmodule
|
#include <bits/stdc++.h> int n, m; long long k; long long pow(int n) { if (n == 0) return 1; long long tmp = pow(n >> 1); tmp = tmp * tmp % 1000000009ll; if (n & 1) tmp = tmp * 2ll % 1000000009ll; return tmp; } int main() { scanf( %d%d%I64d , &n, &m, &k); int t = n - m; long long ans = 0; if (m == 0) { puts( 0 ); return 0; } if (n - t * k < k) { ans = m; } else { int num = (n - t * k) / k; ans = (pow(num + 1) - 2 + 1000000009ll) * k % 1000000009ll; ans = (ans + (n - t * k) % k) % 1000000009ll; ans = (ans + t * (k - 1)) % 1000000009ll; } printf( %I64d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_PP_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_rows_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_rows_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_rows_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_rows_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 105; const long long MOD = 1e9 + 7; long long dp[MAXN][MAXN], tmp[MAXN][MAXN]; void fillTmp() { for (int i = 0; i < MAXN; i++) fill(tmp[i], tmp[i] + MAXN, 0); return; } void fillDp() { for (int i = 0; i < MAXN; i++) for (int t = 0; t < MAXN; t++) dp[i][t] = tmp[i][t]; return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k, d; cin >> n >> k >> d; dp[0][0] = 1; long long res = 0; for (int i = 0; i < MAXN; i++) { fillTmp(); for (int w = 1; w <= k; w++) for (int t = 0; t < MAXN; t++) for (int j = 0; j < MAXN; j++) if (dp[t][j] != 0 && t + w < MAXN) tmp[t + w][max(w, j)] = (dp[t][j] + tmp[t + w][max(w, j)]) % MOD; fillDp(); for (int i = d; i < MAXN; i++) res = (res + dp[n][i]) % MOD; } cout << res << n ; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Sep 25 09:53:03 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.2 2006/10/30 15:38:11 wig Exp $
// $Date: 2006/10/30 15:38:11 $
// $Log: inst_t_e.v,v $
// Revision 1.2 2006/10/30 15:38:11 wig
// Updated testcase bitsplice/rfe20060904a and added some bug testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.93 2006/09/25 08:24:10 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [10:0] s20060904a;
wire [10:0] s20060904a_2;
wire [10:0] s20060904a_3;
wire [11:0] s20060904a_4;
wire [`s_def_5h:0] s20060904a_5;
wire [10:0] s20060904a_6;
wire [12:0] s20061030a_7;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
.port_a(s20060904a), // wire `s_def of signal to port_b
.port_a_2(s20060904a_2), // wire `s_def_2 from port to signal
.port_a_3(s20060904a_3), // wire port splice
.port_a_4[`p_def_4f:`p_def_4t](s20060904a_4[`p_def_4f - `p_def_4t:0]), // wire port splice 4
.port_a_5(s20060904a_5), // wire port splice 4
.port_a_6(s20060904a_6), // wire `s_def_6 (which is a slice!) to port_b
.port_a_7(s20061030a_7) // wire_7 only define
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.port_b[0](s20060904a[`s_def]), // wire `s_def of signal to port_b
.port_b_2[`s_def_2](s20060904a_2[1]), // wire `s_def_2 from port to signal
.port_b_3[`s_def_3f - `s_def_3t:0](s20060904a_3[`s_def_3f:`s_def_3t]), // wire port splice
.port_b_4[`p_def_4f:`p_def_4t](s20060904a_4[`p_def_4f - `p_def_4t:0]), // wire port splice 4
.port_b_5(s20060904a_5), // wire port splice 4
.port_b_6[3:0](s20060904a_6[`s_def_6]), // wire `s_def_6 (which is a slice!) to port_b
.port_b_7(s20061030a_7[`s20061030a_7_slice]) // wire_7 only define
);
// End of Generated Instance Port Map for inst_b
// Generated Instance Port Map for inst_c
inst_c_e inst_c (
);
// End of Generated Instance Port Map for inst_c
// Generated Instance Port Map for inst_d
inst_d_e inst_d (
);
// End of Generated Instance Port Map for inst_d
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; char s[maxn]; int size[maxn], last[200]; bool isover[maxn]; string ans[maxn], now; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> s; int len = strlen(s); bool hasdel = false; now = ; for (int no = len - 1; ~no; no--) { now = s[no] + now; if (now.size() > 1) { if (now[0] != now[1]) last[now[0]] = now[1]; } if (now.size() > 1 && !hasdel) { if (now[0] == now[1] && now[1] > last[now[1]]) { now = now.substr(2); hasdel = true; } } else hasdel = false; size[no] = now.size(); if (now.size() > 10) ans[no] = now.substr(0, 5) + ... + now.substr(now.size() - 2); else ans[no] = now; } for (int i = 0; i < len; i++) { cout << size[i] << << ans[i] << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A2111O_PP_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__DECAPKAPWR_BLACKBOX_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decapkapwr ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int d[1005][2]; char M[1005][1005]; struct Node { int l = 0, r = 0; int p; } L[1005], R[1005]; int n, m; int v[1005]; void Cal(int i) { L[i].l = L[i].p; R[i].l = R[i].p; L[i].r = m - 1 - L[i].p; R[i].r = m - 1 - R[i].p; } int main() { scanf( %d%d , &n, &m); m += 2; memset(v, 0, sizeof(v)); int Layer = -1; for (int i = 0; i < n; i++) { scanf( %s , M[i]); L[i].p = 0; R[i].p = n; for (int j = 0; j < m; j++) { if (M[i][j] == 1 ) { if (!L[i].p) L[i].p = j; R[i].p = j; if (Layer == -1) Layer = i; v[i] = 1; } } Cal(i); } d[n][0] = -1; d[n][1] = m - 1; if (Layer == -1) { cout << 0 << endl; return 0; } for (int i = n - 1; i > Layer; i--) { if (!v[i]) { d[i][0] = d[i + 1][0] + 1; d[i][1] = d[i + 1][1] + 1; continue; } d[i][0] = min(d[i + 1][1] + m - 1, d[i + 1][0] + 2 * R[i].l) + 1; d[i][1] = min(d[i + 1][0] + m - 1, d[i + 1][1] + 2 * L[i].r) + 1; } printf( %d n , 1 + min(d[Layer + 1][0] + R[Layer].l, d[Layer + 1][1] + L[Layer].r)); }
|
`timescale 1 ns / 1 ps
module multiply_accumulate #
(
// signal width definitions
parameter integer DATA_WIDTH = 16,
parameter integer COEFFICIENT_WIDTH = 16,
parameter integer CARRY_WIDTH = 48,
parameter integer OUTPUT_OFFSET = 0,
// operation definitions
parameter integer DATA_IN_NUMBER_REGS = 1,
parameter integer COEFFICIENTS_NUMBER_REGS = 1,
parameter integer USE_SILICON_CARRY = 1,
parameter integer FIRST_IN_CHAIN = 0,
parameter integer LAST_IN_CHAIN = 0
)
(
// global signals
input wire clock,
input wire reset,
// data signals
input wire [DATA_WIDTH-1:0] data_in,
input wire [COEFFICIENT_WIDTH-1:0] coefficient_in,
input wire [CARRY_WIDTH-1:0] carry_in,
output wire [CARRY_WIDTH-1:0] carry_out,
output wire [DATA_WIDTH-1:0] data_carry,
output wire [DATA_WIDTH-1:0] data_out,
// control signals
input wire ce_calculate,
input wire ce_coefficient,
input wire reset_coefficient,
input wire [6:0] op_mode,
input wire [4:0] in_mode
);
// DSP48E1 parameters
localparam integer ACASCREG = 1;
localparam integer ADREG = 1;
localparam integer ALUMODEREG = 1;
localparam integer AREG = 1;
localparam AUTORESET_PATDET = "NO_RESET"; // {NO_RESET, RESET_MATCH, RESET_NOT_MATCH}
localparam A_INPUT = "DIRECT";
localparam integer BCASCREG = 1;
localparam integer BREG = 1;
// localparam B_INPUT = "DIRECT";
localparam B_INPUT = FIRST_IN_CHAIN == 1 ? "DIRECT" : "CASCADE";
localparam integer CARRYINREG = 1;
localparam integer CARRYINSELREG = 1;
localparam integer CREG = 1;
localparam integer DREG = 1;
localparam integer INMODEREG = 1;
localparam integer MREG = 1;
localparam integer OPMODEREG = 1;
localparam integer PREG = 1;
localparam SEL_MASK = "MASK";
localparam SEL_PATTERN = "PATTERN";
localparam USE_DPORT = "FALSE";
localparam USE_MULT = "MULTIPLY";
localparam USE_PATTERN_DETECT = "NO_PATDET";
localparam USE_SIMD = "ONE48";
localparam [47:0] MASK = 48'h3FFFFFFFFFFF;
localparam [47:0] PATTERN = 48'h000000000000;
localparam [3:0] IS_ALUMODE_INVERTED = 4'b0;
localparam [0:0] IS_CARRYIN_INVERTED = 1'b0;
localparam [0:0] IS_CLK_INVERTED = 1'b0;
localparam [4:0] IS_INMODE_INVERTED = 5'b0;
localparam [6:0] IS_OPMODE_INVERTED = 7'b0;
localparam integer PCIN_WIDTH = 48;
localparam integer A_WIDTH = 30;
localparam integer B_WIDTH = 18;
localparam integer C_WIDTH = 48;
localparam integer D_WIDTH = 25;
// TODO
// DSP48E1 signals
wire [29:0] ACOUT;
wire [17:0] BCOUT;
wire CARRYCASCOUT;
wire [3:0] CARRYOUT;
wire MULTSIGNOUT;
wire OVERFLOW;
wire [47:0] P;
wire PATTERNBDETECT;
wire PATTERNDETECT;
wire [47:0] PCOUT;
wire UNDERFLOW;
wire [29:0] A;
wire [29:0] ACIN;
wire [3:0] ALUMODE;
wire [17:0] B;
wire [17:0] BCIN;
wire [47:0] C;
wire CARRYCASCIN;
wire CARRYIN;
wire [2:0] CARRYINSEL;
wire CEA1;
wire CEA2;
wire CEAD;
wire CEALUMODE;
wire CEB1;
wire CEB2;
wire CEC;
wire CECARRYIN;
wire CECTRL;
wire CED;
wire CEINMODE;
wire CEM;
wire CEP;
wire CLK;
wire [24:0] D;
wire MULTSIGNIN;
wire [6:0] OPMODE;
wire [47:0] PCIN;
wire RSTA;
wire RSTALLCARRYIN;
wire RSTALUMODE;
wire RSTB;
wire RSTC;
wire RSTCTRL;
wire RSTD;
wire RSTINMODE;
wire RSTM;
wire RSTP;
// connect the clock
assign CLK = clock;
// connect the resets
// assign RSTA = reset_coefficient | reset;
assign RSTA = reset_coefficient;
assign RSTALLCARRYIN = reset;
assign RSTALUMODE = reset;
assign RSTB = reset;
assign RSTC = reset;
assign RSTCTRL = reset;
assign RSTD = reset;
assign RSTINMODE = reset;
assign RSTM = reset;
assign RSTP = reset;
// determine whether the input and output signals should be routed
// through the hardware carry lines to the adjecent DSP48 or connected
// to the external fabric
generate
if (USE_SILICON_CARRY) begin
// decicde whether inputs should be from hardware carrys or
// exposed inputs
if (FIRST_IN_CHAIN) begin
// assign A = {{(A_WIDTH-DATA_IN_WIDTH){data_in_A[DATA_IN_WIDTH-1]}}, data_in_A};
assign B = {{(B_WIDTH-DATA_WIDTH){data_in[DATA_WIDTH-1]}}, data_in};
assign PCIN = 0;
end
else begin
assign BCIN = {{(B_WIDTH-DATA_WIDTH){data_in[DATA_WIDTH-1]}}, data_in};
assign PCIN = {{(PCIN_WIDTH-CARRY_WIDTH){carry_in[CARRY_WIDTH-1]}}, carry_in};
end
// assign carry out signals
assign data_carry = BCOUT;
// for the moment coefficient must come from external
// could change this in the future
assign A = {{(A_WIDTH-COEFFICIENT_WIDTH){coefficient_in[COEFFICIENT_WIDTH-1]}}, coefficient_in};
assign data_out = P[DATA_WIDTH+COEFFICIENT_WIDTH+OUTPUT_OFFSET-1:COEFFICIENT_WIDTH+OUTPUT_OFFSET];
assign carry_out = PCOUT;
end
else begin
assign A = {{(A_WIDTH-COEFFICIENT_WIDTH){coefficient_in[COEFFICIENT_WIDTH-1]}}, coefficient_in};
assign B = {{(B_WIDTH-DATA_WIDTH){data_in[DATA_WIDTH-1]}}, data_in};
assign PCIN = 0;
assign data_out = P[DATA_WIDTH+COEFFICIENT_WIDTH+OUTPUT_OFFSET-1:COEFFICIENT_WIDTH+OUTPUT_OFFSET];
end
endgenerate
// connect the clock enables
assign CEA1 = ce_coefficient;
assign CEA2 = ce_coefficient;
assign CEAD = ce_coefficient;
assign CEB1 = ce_calculate;
assign CEB2 = ce_calculate;
assign CEALUMODE = ce_calculate;
assign CEC = ce_calculate;
assign CECARRYIN = ce_calculate;
assign CECTRL = ce_calculate;
assign CED = ce_calculate;
assign CEINMODE = ce_calculate;
assign CEM = ce_calculate;
assign CEP = ce_calculate;
//// unconnected signals
assign ACIN = 0;
assign ALUMODE = 0;
// assign BCIN = 0;
assign CARRYCASCIN = 0;
assign CARRYINSEL = 0;
assign CARRYIN = 0;
assign MULTSIGNIN = 0;
// instantiate the DSP48E1
DSP48E1 #(
.ACASCREG(ACASCREG),
.ADREG(ADREG),
.ALUMODEREG(ALUMODEREG),
.AREG(COEFFICIENTS_NUMBER_REGS),
.AUTORESET_PATDET(AUTORESET_PATDET),
.A_INPUT(A_INPUT),
.BCASCREG(DATA_IN_NUMBER_REGS),
.BREG(DATA_IN_NUMBER_REGS),
.B_INPUT(B_INPUT),
.CARRYINREG(CARRYINREG),
.CARRYINSELREG(CARRYINSELREG),
.CREG(CREG),
.DREG(DREG),
.INMODEREG(INMODEREG),
.MREG(MREG),
.OPMODEREG(OPMODEREG),
.PREG(PREG),
.SEL_MASK(SEL_MASK),
.SEL_PATTERN(SEL_PATTERN),
.USE_DPORT(USE_DPORT),
.USE_MULT(USE_MULT),
.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
.USE_SIMD(USE_SIMD),
.MASK(MASK),
.PATTERN(PATTERN),
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
.IS_CLK_INVERTED(IS_CLK_INVERTED),
.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
) DSP48E1_inst(
.ACOUT(ACOUT),
.BCOUT(BCOUT),
.CARRYCASCOUT(CARRYCASCOUT),
.CARRYOUT(CARRYOUT),
.MULTSIGNOUT(MULTSIGNOUT),
.OVERFLOW(OVERFLOW),
.P(P),
.PATTERNBDETECT(PATTERNBDETECT),
.PATTERNDETECT(PATTERNDETECT),
.PCOUT(PCOUT),
.UNDERFLOW(UNDERFLOW),
.A(A),
.ACIN(ACIN),
.ALUMODE(ALUMODE),
.B(B),
.BCIN(BCIN),
.C(C),
.CARRYCASCIN(CARRYCASCIN),
.CARRYIN(CARRYIN),
.CARRYINSEL(CARRYINSEL),
.CEA1(CEA1),
.CEA2(CEA2),
.CEAD(CEAD),
.CEALUMODE(CEALUMODE),
.CEB1(CEB1),
.CEB2(CEB2),
.CEC(CEC),
.CECARRYIN(CECARRYIN),
.CECTRL(CECTRL),
.CED(CED),
.CEINMODE(CEINMODE),
.CEM(CEM),
.CEP(CEP),
.CLK(CLK),
.D(D),
.INMODE(in_mode),
.MULTSIGNIN(MULTSIGNIN),
.OPMODE(op_mode),
.PCIN(PCIN),
.RSTA(RSTA),
.RSTALLCARRYIN(RSTALLCARRYIN),
.RSTALUMODE(RSTALUMODE),
.RSTB(RSTB),
.RSTC(RSTC),
.RSTCTRL(RSTCTRL),
.RSTD(RSTD),
.RSTINMODE(RSTINMODE),
.RSTM(RSTM),
.RSTP(RSTP)
);
// used to create the GTKwave dump file
`ifdef COCOTB_SIM
initial begin
$dumpfile ("waveform.vcd");
$dumpvars (0, multiply_accumulate);
#1;
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n > 2) cout << n - 2 << endl; else cout << 7 << endl; }
|
#include <bits/stdc++.h> int main() { int M, N, d; scanf( %d %d , &M, &N); d = (M * N) / 2; printf( %d , d); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; bool check(int i, int j, int k) { return (i + j > k && j + k > i && j + i > j); } int main() { int n, ct = 0; cin >> n; for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { int k = i ^ j; if (k <= n && k >= j && check(i, j, k)) ct++; } } cout << ct << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_TB_V
`define SKY130_FD_SC_HDLL__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_TB_V
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