text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> template <class T> inline void read(T &x) { x = 0; int f = 0; char ch = getchar(); while (!isdigit(ch)) { f |= ch == - ; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } x = f ? -x : x; return; } int p[100010], siz[100010], find[100010]; int t, n; bool flag; int main() { read(t); while (t--) { read(n); flag = true; for (int i = 1; i <= n; ++i) read(p[i]); for (int i = 2; i <= n; ++i) { if (p[i] - p[i - 1] > 1) { flag = false; break; } } puts(flag ? Yes : No ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, s, tmp1, tmp2; vector<long long> ans; vector<vector<long long>> g(100000); bool vs[2][100000]; bool vs1[100000] = {0}, rc[100000] = {0}; bool a = false, w = false, d = false, t = false; long long cnt = 0; void hasc(long long v) { vs1[v - 1] = true; rc[v - 1] = true; for (auto el : g[v - 1]) { if (!vs1[el - 1]) hasc(el); else if (rc[el - 1]) { d = true; } } rc[v - 1] = false; } void dfs(long long v) { ans.push_back(v); vs[a][v - 1] = true; if (a && !(g[v - 1].size())) { w = 1; return; } a = !a; for (auto el : g[v - 1]) if (!vs[a][el - 1] && !w) { dfs(el); } a = !a; if (w) return; ans.pop_back(); } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> tmp1; for (int j = 0; j < tmp1; j++) { cin >> tmp2; g[i].push_back(tmp2); } } cin >> s; dfs(s); hasc(s); if (w) { cout << Win << endl; for (auto el : ans) cout << el << ; cout << endl; } else if (d) { cout << Draw << endl; } else cout << Lose << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__XOR3_PP_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_PP_SYMBOL_V
|
//----------------------------------------------------------------------
// Title : Demo Testbench
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : demo_tb.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This testbench will exercise the PHY ports of the EMAC
// to demonstrate the functionality.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module testbench;
//--------------------------------------------------------------------
// Testbench signals
//--------------------------------------------------------------------
wire reset;
wire tx_client_clk;
wire [7:0] tx_ifg_delay;
wire rx_client_clk;
wire [15:0] pause_val;
wire pause_req;
// GMII wires
wire gmii_tx_clk;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_txd;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire gmii_rx_er;
wire [7:0] gmii_rxd;
// Not asserted: full duplex only testbench
wire mii_tx_clk;
wire gmii_crs;
wire gmii_col;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Testbench Semaphores
//----------------------------------------------------------------
wire configuration_busy;
wire monitor_finished_1g;
wire monitor_finished_100m;
wire monitor_finished_10m;
//----------------------------------------------------------------
// Wire up device under test
//----------------------------------------------------------------
v6_emac_v1_5_example_design dut
(
// Client receiver interface
.EMACCLIENTRXDVLD (),
.EMACCLIENTRXFRAMEDROP (),
.EMACCLIENTRXSTATS (),
.EMACCLIENTRXSTATSVLD (),
.EMACCLIENTRXSTATSBYTEVLD (),
// Client transmitter interface
.CLIENTEMACTXIFGDELAY (tx_ifg_delay),
.EMACCLIENTTXSTATS (),
.EMACCLIENTTXSTATSVLD (),
.EMACCLIENTTXSTATSBYTEVLD (),
// MAC Control interface
.CLIENTEMACPAUSEREQ (pause_req),
.CLIENTEMACPAUSEVAL (pause_val),
// Clock signal
.GTX_CLK (gtx_clk),
// GMII interface
.GMII_TXD (gmii_txd),
.GMII_TX_EN (gmii_tx_en),
.GMII_TX_ER (gmii_tx_er),
.GMII_TX_CLK (gmii_tx_clk),
.GMII_RXD (gmii_rxd),
.GMII_RX_DV (gmii_rx_dv),
.GMII_RX_ER (gmii_rx_er),
.GMII_RX_CLK (gmii_rx_clk),
.REFCLK (refclk),
// Asynchronous reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req = 1'b0;
assign pause_val = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay = 8'b0;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the PHY stimulus and monitor
//--------------------------------------------------------------------
phy_tb phy_test
(
//----------------------------------------------------------------
// GMII interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_rx_clk (gmii_rx_clk),
.gmii_col (gmii_col),
.gmii_crs (gmii_crs),
.mii_tx_clk (mii_tx_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
//--------------------------------------------------------------------
// Instantiate the no-host configuration stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host interface: host_clk is always required
//----------------------------------------------------------------
.host_clk (host_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
endmodule
|
module test();
wire a;
tri0 b;
tri1 c;
tri1 d;
tri0 e;
wire f;
wire g;
wire h;
wire i;
tri1 j;
tri0 k;
wire l;
tri0 m;
tri1 n;
assign d = 1'b0;
assign e = 1'b1;
assign f = 1'b0;
assign f = 1'b1;
assign g = 1'b1;
assign g = 1'b0;
assign (strong1,strong0) h = 1'b0;
assign ( weak1, weak0) h = 1'b1;
assign ( weak1, weak0) i = 1'b0;
assign (strong1,strong0) i = 1'b1;
assign (pull1,pull0) j = 1'b0;
assign (pull1,pull0) k = 1'b1;
wire [1:0] A = {1'b1, a};
wire [1:0] B = {1'b1, b};
wire [1:0] C = {1'b1, c};
wire [1:0] D = {1'b1, d};
wire [1:0] E = {1'b1, e};
wire [1:0] F = {1'b1, f};
wire [1:0] G = {1'b1, g};
wire [1:0] H = {1'b1, h};
wire [1:0] I = {1'b1, i};
wire [1:0] J = {1'b1, j};
wire [1:0] K = {1'b1, k};
wire [1:0] L = {1'b1, l};
wire [1:0] M = {1'b1, m};
wire [1:0] N = {1'b1, n};
reg failed;
initial begin
failed = 0; #1;
$display("A = %b, expect 1z", A); if (A !== 2'b1z) failed = 1;
$display("B = %b, expect 10", B); if (B !== 2'b10) failed = 1;
$display("C = %b, expect 11", C); if (C !== 2'b11) failed = 1;
$display("D = %b, expect 10", D); if (D !== 2'b10) failed = 1;
$display("E = %b, expect 11", E); if (E !== 2'b11) failed = 1;
$display("F = %b, expect 1x", F); if (F !== 2'b1x) failed = 1;
$display("G = %b, expect 1x", G); if (G !== 2'b1x) failed = 1;
$display("H = %b, expect 10", H); if (H !== 2'b10) failed = 1;
$display("I = %b, expect 11", I); if (I !== 2'b11) failed = 1;
$display("J = %b, expect 1x", J); if (J !== 2'b1x) failed = 1;
$display("K = %b, expect 1x", K); if (K !== 2'b1x) failed = 1;
force l = 1'b0; #1;
$display("L = %b, expect 10", L); if (L !== 2'b10) failed = 1;
force l = 1'b1; #1;
$display("L = %b, expect 11", L); if (L !== 2'b11) failed = 1;
force m = 1'b1; #1;
$display("M = %b, expect 11", M); if (M !== 2'b11) failed = 1;
force n = 1'b0; #1;
$display("N = %b, expect 10", N); if (N !== 2'b10) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b, c; int n; cin >> n >> a; sort(a.begin(), a.end()); for (int i = 0; i < a.size(); i += n) b += a[i]; for (int i = 0; i < n; i++) c += b; b = c; sort(b.begin(), b.end()); if (b != a) cout << -1; else cout << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long spf[1000005]; vector<long long> primes, prev[1000005], next[1000005]; void sieve() { for (long long i = 2; i < 1000005; ++i) { if (spf[i] == 0) { spf[i] = i; for (long long j = 2 * i; j <= 1000005; j += i) { if (spf[j] == 0) spf[j] = i; } } } } bool cmp(const pair<long long, long long>& a, const pair<long long, long long>& b) { if (a.first == b.first) return a.second < b.second; else return a.first > b.first; } string kmp(string s) { long long n = s.size(); vector<long long> p(n); long long i = 1, len = 0; while (i < n) { if (s[i] == s[len]) { len++; p[i] = len; i++; } else { if (len != 0) { len = p[len - 1]; } else { p[i] = 0; i++; } } } long long ans = p[n - 1]; string t = s.substr(0, ans); return t; } string pal(string t) { string r = t; reverse(r.begin(), r.end()); string t1 = kmp(r + # + t); string t2 = kmp(t + # + r); return t1.size() > t2.size() ? t1 : t2; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); srand(static_cast<unsigned>(time(0))); long long t = 1; cin >> t; while (t--) { string s; cin >> s; long long n = s.size(); long long i = 0; while (i <= n - i - 1 && s[i] == s[n - i - 1]) { i++; } if (i > n - i - 1) { cout << s << n ; continue; } string t1 = s.substr(i, n - 2 * i); string ans = pal(t1); string temp = s.substr(0, i); ans = temp + ans; reverse(temp.begin(), temp.end()); ans = ans + temp; cout << ans << n ; } return 0; }
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.3
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="dut_inst,dut,{component_name=dut_inst,HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.352000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=33,HLS_SYN_LUT=34}" *)
module dut (
ap_clk,
ap_rst,
in_fifo_V_dout,
in_fifo_V_empty_n,
in_fifo_V_read,
out_fifo_V_din,
out_fifo_V_full_n,
out_fifo_V_write
);
input ap_clk;
input ap_rst;
input [31:0] in_fifo_V_dout;
input in_fifo_V_empty_n;
output in_fifo_V_read;
output [31:0] out_fifo_V_din;
input out_fifo_V_full_n;
output out_fifo_V_write;
reg in_fifo_V_read;
reg out_fifo_V_write;
reg [31:0] cnt = 32'b00000000000000000000000000000000;
reg [0:0] ap_CS_fsm = 1'b0;
reg ap_sig_bdd_24;
wire [31:0] tmp_fu_49_p2;
reg [0:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_FFFFFFFF = 32'b11111111111111111111111111111111;
parameter ap_true = 1'b1;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// cnt assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_cnt
if (ap_rst == 1'b1) begin
cnt <= ap_const_lv32_0;
end else begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~ap_sig_bdd_24)) begin
cnt <= tmp_fu_49_p2;
end
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_24)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~ap_sig_bdd_24)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// in_fifo_V_read assign process. ///
always @ (ap_CS_fsm or ap_sig_bdd_24)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~ap_sig_bdd_24)) begin
in_fifo_V_read = ap_const_logic_1;
end else begin
in_fifo_V_read = ap_const_logic_0;
end
end
/// out_fifo_V_write assign process. ///
always @ (ap_CS_fsm or ap_sig_bdd_24)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~ap_sig_bdd_24)) begin
out_fifo_V_write = ap_const_logic_1;
end else begin
out_fifo_V_write = ap_const_logic_0;
end
end
/// ap_sig_bdd_24 assign process. ///
always @ (in_fifo_V_empty_n or out_fifo_V_full_n)
begin
ap_sig_bdd_24 = ((in_fifo_V_empty_n == ap_const_logic_0) | (out_fifo_V_full_n == ap_const_logic_0));
end
assign out_fifo_V_din = (cnt + ap_const_lv32_FFFFFFFF);
assign tmp_fu_49_p2 = (cnt + ap_const_lv32_FFFFFFFF);
endmodule //dut
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR2B_PP_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
* size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long q; cin >> q; if (q == 1) { cout << 1 n0 n ; return 0; } long long a = -1, b = -1; for (long long d = 2; d * d <= q; d++) { if (q % d) continue; a = d; b = q / d; break; } if (a == -1) { cout << 1 n0 n ; return 0; } for (long long d = 2; d * d <= b; d++) { if (b % d) continue; cout << 1 n << a * d << n ; return 0; } cout << 2 n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_PP_BLACKBOX_V
|
`include "./Definition.v"
module Divider
(
input[ `size_int - 1 : 0 ]Dividend,
input[ `size_int - 1 : 0 ]Divisor,
output reg[ `size_int - 1 : 0 ]Q, // Quotient
output reg[ `size_int - 1 : 0 ]Remainder // Remainder
);
// counter
integer i;
reg[ `size_int - 1 : 0 ]Quotient; // Quotient
reg[ `size_int : 0 ]Partial;
reg[ `size_int - 1 : 0 ]div;
always@( Dividend or Divisor )
begin
Quotient = Dividend;
div = Divisor;
Partial = { `size_int'h00, 1'b0 };
for( i = 0; i < `size_int; i = i + 1 )
begin
Partial = { Partial[ `size_int - 1 : 0 ], Quotient[ `size_int - 1 ] };
Quotient = { Quotient[ `size_int - 2 : 0 ], 1'b0 };
Partial = Partial + { ~{ 1'b0, div } + 1'b1 }; // subtraction
if( Partial[ `size_int ] == 1'b0 )
Quotient[ 0 ] = 1'b1;
else
begin
Partial = Partial + div;
Quotient[ 0 ] = 1'b0;
end
end
Remainder = Partial[ `size_int - 1 : 0 ];
//to round up or down
if( Remainder * 10 >= Divisor * 5 )
Q = Quotient + 1;
else
Q = Quotient;
end
endmodule
module Divider_testbench;
// Signal declaration
reg[ `size_int - 1 : 0 ]Dividend;
reg[ `size_int - 1 : 0 ]Divisor;
wire[ `size_int - 1 : 0 ]Q;
wire[ `size_int - 1 : 0 ]Remainder;
Divider Divider_test( Dividend, Divisor, Q, Remainder );
initial
begin
#2
begin
Dividend = 100;
Divisor = 3;
end
#2 $display( "Dividend = %d\tDivisor = %d\tQuotient = %d\tRemainder = %d",
Dividend, Divisor, Q, Remainder );
#2
begin
Dividend = 200;
Divisor = 7;
end
#2 $display( "Dividend = %d\tDivisor = %d\tQuotient = %d\tRemainder = %d",
Dividend, Divisor, Q, Remainder );
#2
begin
Dividend = 400;
Divisor = 5;
end
#2 $display( "Dividend = %d\tDivisor = %d\tQuotient = %d\tRemainder = %d",
Dividend, Divisor, Q, Remainder );
#2 $stop;
#2 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_M_V
`define SKY130_FD_SC_LP__A21BO_M_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_m (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_m (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_M_V
|
#include <bits/stdc++.h> #pragma GCC optimize(3, inline , Ofast ) using namespace std; int p[1010]; bool vis[1010]; void dfs(int pos) { if (vis[pos]) return (void)(printf( %d , pos)); else vis[pos] = 1, dfs(p[pos]); } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); for (int i = 1; i <= n; i++) memset(vis, 0, sizeof vis), dfs(i); }
|
#include <bits/stdc++.h> using namespace std; long long A, B, N; long long L, T, M; bool ok(long long R) { long long mx = A + (R - 1) * B; long long mn = A + (L - 1) * B; long long D = R - L; if (mx > T) return false; return (mn * (D + 1) + B * D * (D + 1) / 2) <= T * M; } int main(void) { cin >> A >> B >> N; while (N--) { cin >> L >> T >> M; long long R = L; long long mn = A + (L - 1) * B; if (mn > T) { R = -1; } else { long long XR = 1LL << 22; while (XR > R) { long long m = (R + XR) / 2; if (!ok(m)) XR = m; else R = m + 1; } R -= 1; } cout << R << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 400; const int MOD = (int)1e9 + 7; int n, x; long long fac[N], c[N][N]; map<int, int> h; vector<int> d; int fix(int x) { for (int i = 2; i * i <= x; i++) { while (x % (i * i) == 0) { x /= i * i; } } return x; } void add(long long &x, long long y) { x += y; x %= MOD; } int main() { memset(c, 0, sizeof c); fac[0] = 1; for (int i = 1; i < N; i++) { fac[i] = fac[i - 1] * i % MOD; } for (int i = 0; i < N; i++) { c[i][0] = 1; for (int j = 1; j <= i; j++) { c[i][j] = c[i - 1][j - 1] + c[i - 1][j]; if (c[i][j] >= MOD) { c[i][j] -= MOD; } } } scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &x); x = fix(x); if (h.count(x) == 0) { h[x] = 1; } else { int y = h[x]; h[x] = y + 1; } } for (auto it = h.begin(); it != h.end(); it++) { d.push_back(it->second); } sort(d.begin(), d.end()); int now = d[0] + 1; vector<long long> dp(now + 1, 0); dp[d[0] - 1] = fac[d[0]]; for (int i = 1; i < d.size(); i++) { vector<long long> ndp(now + d[i] + 1, 0); for (int same = 0; same <= now; same++) { int dif = now - same; if (dp[same] == 0) { continue; } for (int j = 1; j <= d[i] && j <= now; j++) { for (int k = 0; k <= same && k <= j; k++) { int nsame = same - k + d[i] - j; add(ndp[nsame], dp[same] * c[d[i] - 1][j - 1] % MOD * c[same][k] % MOD * c[dif][j - k] % MOD * fac[d[i]]); } } } now += d[i]; dp.swap(ndp); } printf( %lld n , dp[0]); return 0; }
|
// Flipflop intermediate map level
module \$__FF_NOLSR (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
generate
if (_TECHMAP_WIREINIT_Q_ === 1'b1)
FD1P3JX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(1'b0), .Q(Q));
else
FD1P3IX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(1'b0), .Q(Q));
endgenerate
endmodule
module \$__FF_SYNCLSR (input D, C, E, R, output Q);
parameter SR_VAL = 1'b0;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
wire Ci, Ei, Ri, Rg, Dd;
generate
if (SR_VAL)
FD1P3JX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));
else
FD1P3IX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));
endgenerate
endmodule
module \$__FF_ASYNCLSR (input D, C, E, R, output Q);
parameter SR_VAL = 1'b0;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
wire _TECHMAP_REMOVEINIT_Q_ = (_TECHMAP_WIREINIT_Q_ === 1'bx || _TECHMAP_WIREINIT_Q_ === SR_VAL);
wire Ci, Ei, Ri, Rg, Dd;
generate
if (SR_VAL)
FD1P3BX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));
else
FD1P3DX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));
endgenerate
endmodule
module \$_DFF_P_ (input D, C, output Q); \$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(1'b1), .Q(Q)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); \$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(E), .Q(Q)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); \$__FF_ASYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); \$__FF_ASYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
module \$_SDFF_PP0_ (input D, C, R, output Q); \$__FF_SYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
module \$_SDFF_PP1_ (input D, C, R, output Q); \$__FF_SYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
module \$_DFFE_PP0P_ (input D, C, E, R, output Q); \$__FF_ASYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
module \$_DFFE_PP1P_ (input D, C, E, R, output Q); \$__FF_ASYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); \$__FF_SYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); \$__FF_SYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
module \$__NX_TINOUTPAD (input I, OE, output O, inout B);
BB _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .B(B));
endmodule
module \$__NX_TOUTPAD (input I, OE, output O);
OBZ _TECHMAP_REPLACE_ (.I(I), .O(), .T(~OE), .O(O));
endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
if (LUT == 2'b01)
INV _TECHMAP_REPLACE_ (.A(A[0]), .Z(Y));
else
LUT4 #(.INIT($sformatf("0x%04x", {{8{LUT[1]}}, {8{LUT[0]}}}))) _TECHMAP_REPLACE_ (.Z(Y),
.D(A[0]));
end else
if (WIDTH == 2) begin
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
LUT4 #(.INIT($sformatf("0x%04x", INIT))) _TECHMAP_REPLACE_ (.Z(Y),
.C(A[0]), .D(A[1]));
end else
if (WIDTH == 3) begin
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
LUT4 #(.INIT($sformatf("0x%04x", INIT))) _TECHMAP_REPLACE_ (.Z(Y),
.B(A[0]), .C(A[1]), .D(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT($sformatf("0x%04x", LUT))) _TECHMAP_REPLACE_ (.Z(Y),
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
end else
if (WIDTH == 5) begin
WIDEFN9 #(
.INIT0($sformatf("0x%04x", LUT[15:0 ])),
.INIT1($sformatf("0x%04x", LUT[31:16])),
) _TECHMAP_REPLACE_ (
.A0(A[0]), .B0(A[1]), .C0(A[2]), .D0(A[3]),
.A1(A[0]), .B1(A[1]), .C1(A[2]), .D1(A[3]),
.SEL(A[4]), .Z(Y)
);
end
endgenerate
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb(
// RISC clock, reset
clk, rst,
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
`ifdef OR1200_SB_IMPLEMENTED
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
`else // !OR1200_SB_IMPLEMENTED
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
`endif
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module doImgProc_KERNEL_BUS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 5,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
input wire [3:0] kernel_address0,
input wire kernel_ce0,
output wire [7:0] kernel_q0
);
//------------------------Address Info-------------------
// 0x10 ~
// 0x1f : Memory 'kernel' (3 * 8b)
// Word n : bit [ 7: 0] - kernel[4n]
// bit [15: 8] - kernel[4n+1]
// bit [23:16] - kernel[4n+2]
// bit [31:24] - kernel[4n+3]
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_KERNEL_BASE = 5'h10,
ADDR_KERNEL_HIGH = 5'h1f,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 5;
//------------------------Local signal-------------------
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// memory signals
wire [1:0] int_kernel_address0;
wire int_kernel_ce0;
wire int_kernel_we0;
wire [3:0] int_kernel_be0;
wire [31:0] int_kernel_d0;
wire [31:0] int_kernel_q0;
wire [1:0] int_kernel_address1;
wire int_kernel_ce1;
wire int_kernel_we1;
wire [3:0] int_kernel_be1;
wire [31:0] int_kernel_d1;
wire [31:0] int_kernel_q1;
reg int_kernel_read;
reg int_kernel_write;
reg [1:0] int_kernel_shift;
//------------------------Instantiation------------------
// int_kernel
doImgProc_KERNEL_BUS_s_axi_ram #(
.BYTES ( 4 ),
.DEPTH ( 3 )
) int_kernel (
.clk0 ( ACLK ),
.address0 ( int_kernel_address0 ),
.ce0 ( int_kernel_ce0 ),
.we0 ( int_kernel_we0 ),
.be0 ( int_kernel_be0 ),
.d0 ( int_kernel_d0 ),
.q0 ( int_kernel_q0 ),
.clk1 ( ACLK ),
.address1 ( int_kernel_address1 ),
.ce1 ( int_kernel_ce1 ),
.we1 ( int_kernel_we1 ),
.be1 ( int_kernel_be1 ),
.d1 ( int_kernel_d1 ),
.q1 ( int_kernel_q1 )
);
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA) & !int_kernel_read;
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
end
else if (int_kernel_read) begin
rdata <= int_kernel_q1;
end
end
end
//------------------------Register logic-----------------
//------------------------Memory logic-------------------
// kernel
assign int_kernel_address0 = kernel_address0 >> 2;
assign int_kernel_ce0 = kernel_ce0;
assign int_kernel_we0 = 1'b0;
assign int_kernel_be0 = 1'b0;
assign int_kernel_d0 = 1'b0;
assign kernel_q0 = int_kernel_q0 >> (int_kernel_shift * 8);
assign int_kernel_address1 = ar_hs? raddr[3:2] : waddr[3:2];
assign int_kernel_ce1 = ar_hs | (int_kernel_write & WVALID);
assign int_kernel_we1 = int_kernel_write & WVALID;
assign int_kernel_be1 = WSTRB;
assign int_kernel_d1 = WDATA;
// int_kernel_read
always @(posedge ACLK) begin
if (ARESET)
int_kernel_read <= 1'b0;
else if (ACLK_EN) begin
if (ar_hs && raddr >= ADDR_KERNEL_BASE && raddr <= ADDR_KERNEL_HIGH)
int_kernel_read <= 1'b1;
else
int_kernel_read <= 1'b0;
end
end
// int_kernel_write
always @(posedge ACLK) begin
if (ARESET)
int_kernel_write <= 1'b0;
else if (ACLK_EN) begin
if (aw_hs && AWADDR[ADDR_BITS-1:0] >= ADDR_KERNEL_BASE && AWADDR[ADDR_BITS-1:0] <= ADDR_KERNEL_HIGH)
int_kernel_write <= 1'b1;
else if (WVALID)
int_kernel_write <= 1'b0;
end
end
// int_kernel_shift
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (kernel_ce0)
int_kernel_shift <= kernel_address0[1:0];
end
end
endmodule
`timescale 1ns/1ps
module doImgProc_KERNEL_BUS_s_axi_ram
#(parameter
BYTES = 4,
DEPTH = 256,
AWIDTH = log2(DEPTH)
) (
input wire clk0,
input wire [AWIDTH-1:0] address0,
input wire ce0,
input wire we0,
input wire [BYTES-1:0] be0,
input wire [BYTES*8-1:0] d0,
output reg [BYTES*8-1:0] q0,
input wire clk1,
input wire [AWIDTH-1:0] address1,
input wire ce1,
input wire we1,
input wire [BYTES-1:0] be1,
input wire [BYTES*8-1:0] d1,
output reg [BYTES*8-1:0] q1
);
//------------------------Local signal-------------------
reg [BYTES*8-1:0] mem[0:DEPTH-1];
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 1;
m = 2;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Body---------------------------
// read port 0
always @(posedge clk0) begin
if (ce0) q0 <= mem[address0];
end
// read port 1
always @(posedge clk1) begin
if (ce1) q1 <= mem[address1];
end
genvar i;
generate
for (i = 0; i < BYTES; i = i + 1) begin : gen_write
// write port 0
always @(posedge clk0) begin
if (ce0 & we0 & be0[i]) begin
mem[address0][8*i+7:8*i] <= d0[8*i+7:8*i];
end
end
// write port 1
always @(posedge clk1) begin
if (ce1 & we1 & be1[i]) begin
mem[address1][8*i+7:8*i] <= d1[8*i+7:8*i];
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_mult_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
peripheral uut (.clk(clk) , .rst(rst) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0005; //envio A
addr = 16'h0000;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0002; //envio B
addr = 16'h0001;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0001; //envio init
addr = 16'h0002;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0000; //recivo dato
addr = 16'h0002;
cs=0; rd=1; wr=0;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_mult_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200) $finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 24.06.2017 01:23:43
// Design Name:
// Module Name: funciones_cursor
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module reconocedor_cursor(
input [2:0] visor_x,
input [1:0] visor_y,
output reg [7:0] valor,
output reg is_number
);
always @(*) begin
case ({visor_x,visor_y})
{3'd0 ,2'd0}: {valor,is_number}={8'b0,1'b1};
{3'd1 ,2'd0}: {valor,is_number}={8'b1,1'b1};
{3'd2 ,2'd0}: {valor,is_number}={8'd2,1'b1};
{3'd3 ,2'd0}: {valor,is_number}={8'd3,1'b1};
{3'd4 ,2'd0}: {valor,is_number}={8'd16,1'b0}; //suma
{3'd5 ,2'd0}: {valor,is_number}={8'd17,1'b0}; //resta
{3'd0 ,2'd1}: {valor,is_number}={8'd4,1'b1};
{3'd1 ,2'd1}: {valor,is_number}={8'd5,1'b1};
{3'd2 ,2'd1}: {valor,is_number}={8'd6,1'b1};
{3'd3 ,2'd1}: {valor,is_number}={8'd7,1'b1};
{3'd4 ,2'd1}: {valor,is_number}={8'd18,1'b0}; //mul
{3'd5 ,2'd1}: {valor,is_number}={8'd19,1'b0}; //or
{3'd0 ,2'd2}: {valor,is_number}={8'd8,1'b1};
{3'd1 ,2'd2}: {valor,is_number}={8'd9,1'b1};
{3'd2 ,2'd2}: {valor,is_number}={8'h0a,1'b1};
{3'd3 ,2'd2}: {valor,is_number}={8'h0b,1'b1};
{3'd4 ,2'd2}: {valor,is_number}={8'd20,1'b0}; //and
{3'd5 ,2'd2}: {valor,is_number}={8'd21,1'b0}; //CE
{3'd0 ,2'd3}: {valor,is_number}={8'h0c,1'b1};
{3'd1 ,2'd3}: {valor,is_number}={8'h0d,1'b1};
{3'd2 ,2'd3}: {valor,is_number}={8'h0e,1'b1};
{3'd3 ,2'd3}: {valor,is_number}={8'h0f,1'b1};
{3'd4 ,2'd3}: {valor,is_number}={8'd22,1'b0}; //EXE
default: {valor,is_number}={8'd28,1'b0};
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int r = 0, b = 0, y = 0, g = 0; int len = s.size(); for (int i = 0; i < len; i++) { if (s[i] == B ) b = i % 4; else if (s[i] == G ) g = i % 4; else if (s[i] == R ) r = i % 4; else if (s[i] == Y ) y = i % 4; } int w = 0, x = 0, yy = 0, z = 0, pos; for (int i = 0; i < len; i++) { if (s[i] == ! ) { pos = i % 4; if (pos == r) w++; else if (pos == b) x++; else if (pos == y) yy++; else if (pos == g) z++; } } cout << w << << x << << yy << << z << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_BEHAVIORAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but ensures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9, PI = acos(-1.); const int INF = 0x3f3f3f3f, MOD = 1e9 + 7; const int N = 1e5 + 5; int n, x, v; long long sm; int main() { scanf( %d%d , &n, &x); for (int i = 0; i < n; ++i) scanf( %d , &v), sm += v; printf( %s n , sm + n - 1 == x ? YES : NO ); return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/wram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Work RAM module; implements 2KB of on-board WRAM as fpga block RAM.
***************************************************************************************************/
module wram
(
input wire clk_in, // system clock
input wire en_in, // chip enable
input wire r_nw_in, // read/write select (read: 0, write: 1)
input wire [10:0] a_in, // memory address
input wire [ 7:0] d_in, // data input
output wire [ 7:0] d_out // data output
);
wire wram_bram_we;
wire [7:0] wram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) wram_bram(
.clk(clk_in),
.we(wram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(wram_bram_dout)
);
assign wram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? wram_bram_dout : 8'h00;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file TEST_TX_DP_RAM.v when simulating
// the core, TEST_TX_DP_RAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module TEST_TX_DP_RAM(
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input enb;
input [10 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ENB(enb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; struct abcd { int to, next; } table[300300 << 1]; int head[300300], tot; int n, m; char ans[300300]; void Add(int x, int y) { table[++tot].to = y; table[tot].next = head[x]; head[x] = tot; } void DFS(int x) { int i, cnt = 0; for (i = head[x]; i; i = table[i].next) if (ans[table[i].to] == ans[x]) ++cnt; if (cnt >= 2) { ans[x] ^= 1; for (i = head[x]; i; i = table[i].next) DFS(table[i].to); } } int main() { vector<int>::iterator it; int i, x, y; cin >> n >> m; for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); Add(x, y); Add(y, x); } for (i = 1; i <= n; i++) ans[i] = 0 ; for (i = 1; i <= n; i++) DFS(i); printf( %s n , ans + 1); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module daq3_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio,
spi_dir);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
output spi_dir;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> bool FLAG = 1; using namespace std; const long long MOD = (long long)1e9 + 7, N = (long long)2e6 + 222; const long long INF = (long long)1e18; long long n, k, p[N], a[N], b[N], b1[N]; string s; void clear() { for (long long i = 1; i <= n; ++i) { p[i] = a[i]; } } long long m; void solve() { cin >> n >> m; long long mx = 0; for (long long i = 1; i <= n; ++i) { cin >> a[i]; mx = max(mx, a[i]); } for (long long i = 1; i <= n; ++i) { cin >> b[i]; } sort(b + 1, b + 1 + n); for (long long i = 1; i <= n; ++i) { b1[i] = b[i] + m; } long long mn = INF; clear(); for (long long i = 1; i <= n; ++i) { long long d; if (b1[i] - mx >= 0) { d = b1[i] - mx; for (long long j = 1; j <= n; ++j) { p[j] += d; p[j] %= m; } sort(p + 1, p + 1 + n); bool ok = 0; for (long long j = 1; j <= n; ++j) { if (p[j] != b[j]) ok = 1; } if (ok == 0) { mn = min(mn, d); } clear(); } if (b[i] - mx >= 0) { d = b[i] - mx; for (long long j = 1; j <= n; ++j) { p[j] += d; p[j] %= m; } sort(p + 1, p + 1 + n); bool ok = 0; for (long long j = 1; j <= n; ++j) { if (p[j] != b[j]) ok = 1; } if (ok == 0) { mn = min(mn, d); } clear(); } } cout << mn; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; void dfs(long long int par, long long int node, vector<pair<long long int, string>> adj[], vector<long long int> &nodes, vector<bool> &visited) { visited[node] = true; nodes.push_back(node); for (auto child : adj[node]) { if (!visited[abs(child.first)]) { dfs(node, abs(child.first), adj, nodes, visited); } } } void dfs2(long long int par, long long int node, string role, vector<pair<long long int, string>> adj[], bool &ok, vector<bool> &visited2, long long int &cnt, vector<string> &cr) { for (auto child : adj[node]) { if (child.first > 0) { if (visited2[node] && (!visited2[child.first])) { visited2[child.first] = true; if (cr[node] == imposter ) { string childRole = child.second == imposter ? crewmate : imposter ; cr[child.first] = childRole; dfs2(node, child.first, childRole, adj, ok, visited2, cnt, cr); } else { string childRole = child.second == imposter ? imposter : crewmate ; cr[child.first] = childRole; dfs2(node, child.first, childRole, adj, ok, visited2, cnt, cr); } } else if ((!visited2[node]) && visited2[child.first]) { visited2[node] = true; if (cr[child.first] == imposter ) { string childRole = child.second == imposter ? crewmate : imposter ; cr[node] = childRole; } else { string childRole = child.second == imposter ? imposter : crewmate ; cr[node] = childRole; } } else if (visited2[child.first] && visited2[node]) { if (cr[child.first] == imposter ) { if (cr[node] == imposter && child.second == imposter ) { ok = false; return; } else if (cr[node] == crewmate && child.second == crewmate ) { ok = false; return; } } else { if (cr[node] == imposter && child.second == crewmate ) { ok = false; return; } else if (cr[node] == crewmate && child.second == imposter ) { ok = false; return; } } } if (!ok) { return; } } } for (auto child : adj[node]) { if (child.first < 0) { if ((!visited2[abs(child.first)]) && visited2[node] == true) { dfs2(node, abs(child.first), imposter , adj, ok, visited2, cnt, cr); } } if (!ok) { return; } } for (auto child : adj[node]) { if (child.first > 0) { if (visited2[node] && (!visited2[child.first])) { visited2[child.first] = true; if (cr[node] == imposter ) { string childRole = child.second == imposter ? crewmate : imposter ; cr[child.first] = childRole; dfs2(node, child.first, childRole, adj, ok, visited2, cnt, cr); } else { string childRole = child.second == imposter ? imposter : crewmate ; cr[child.first] = childRole; dfs2(node, child.first, childRole, adj, ok, visited2, cnt, cr); } } else if (visited2[child.first] && visited2[node]) { if (cr[child.first] == imposter ) { if (cr[node] == imposter && child.second == imposter ) { ok = false; return; } else if (cr[node] == crewmate && child.second == crewmate ) { ok = false; return; } } else { if (cr[node] == imposter && child.second == crewmate ) { ok = false; return; } else if (cr[node] == crewmate && child.second == imposter ) { ok = false; return; } } } } if (!ok) { return; } } } void answerNikalBc(long long int t1) { long long int n, m; cin >> n >> m; map<pair<long long int, long long int>, string> mp; vector<pair<long long int, string>> adj[n + 1]; bool ok = true; for (long long int i = 1; i <= m; i++) { long long int u, v; string s; cin >> u >> v >> s; if (mp.find({u, v}) == mp.end()) { adj[u].push_back({v, s}); adj[v].push_back({-1 * u, s}); mp[{u, v}] = s; } else { if (mp[{u, v}] == s) { continue; } else { ok = false; } } } if (!ok) { cout << -1 << n ; return; } long long int ans = 0; vector<bool> visited(n + 1, false); vector<bool> visited2(n + 1, false); vector<string> childRole(n + 1, imposter ); for (long long int i = 1; i <= n; i++) { if (!visited[i]) { vector<long long int> nodes; dfs(-1, i, adj, nodes, visited); bool init = false; long long int cnt1 = 0, cnt2 = 0; for (long long int j = 0; j < nodes.size(); j++) { if (!visited2[nodes[j]]) { if (!init) { visited2[nodes[j]] = true; childRole[nodes[j]] = imposter ; dfs2(-1, nodes[j], imposter , adj, ok, visited2, cnt1, childRole); init = true; } else { dfs2(-1, nodes[j], imposter , adj, ok, visited2, cnt1, childRole); } } } for (auto a : nodes) { visited2[a] = false; } for (auto a : nodes) { if (childRole[a] == imposter ) { cnt1++; } } init = false; for (long long int j = 0; j < nodes.size(); j++) { if (!visited2[nodes[j]]) { if (!init) { visited2[nodes[j]] = true; childRole[nodes[j]] = crewmate ; dfs2(-1, nodes[j], crewmate , adj, ok, visited2, cnt2, childRole); init = true; } else { dfs2(-1, nodes[j], crewmate , adj, ok, visited2, cnt2, childRole); } } } for (auto a : nodes) { if (childRole[a] == imposter ) { cnt2++; } } if (!ok) { cout << -1 << n ; return; } ans += (max(cnt1, cnt2)); } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; t = 1; cin >> t; for (long long int i = 1; i <= t; i++) { answerNikalBc(t); } cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_banktimer(
input sys_clk,
input sdram_rst,
input tim_cas,
input [1:0] tim_wr,
input read,
input write,
output reg precharge_safe
);
reg [2:0] counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter <= 3'd0;
precharge_safe <= 1'b1;
end else begin
if(read) begin
/* see p.26 of datasheet :
* "A Read burst may be followed by, or truncated with, a Precharge command
* to the same bank. The Precharge command should be issued x cycles after
* the Read command, where x equals the number of desired data element
* pairs"
*/
counter <= 3'd4;
precharge_safe <= 1'b0;
end else if(write) begin
counter <= {1'b1, tim_wr};
precharge_safe <= 1'b0;
end else begin
if(counter == 3'b1)
precharge_safe <= 1'b1;
if(~precharge_safe)
counter <= counter - 3'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_TB_V
`define SKY130_FD_SC_HD__NAND4BB_TB_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hd__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; map<int, int> mp; vector<int> ans; int a; for (int i = 0; i < n; i++) { scanf( %d , &a); mp[a] = 1; } n = m; for (int i = 1; i <= n; i++) { if (i > m) break; if (mp[i] == 0) { if (i <= m) { ans.push_back(i); m -= i; } } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtp (
VPWR,
VGND,
Q ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
wire buf_Q ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND4BB_PP_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) void solve() { long long n, m, k; cin >> n >> m >> k; long long lb = n / m; long long ub = (n + m - 1) / m; vector<long long> seat; for (long long i = 0; i <= m; i++) { long long remain = n - i * lb; if (remain >= 0 && remain % ub == 0 && (i + remain / ub == m)) { for (long long j = 0; j < i; j++) seat.push_back(lb); for (long long j = 0; j < remain / ub; j++) seat.push_back(ub); break; } } sort(seat.begin(), seat.end()); priority_queue<pair<long long, long long>> pq; for (long long i = 0; i < n; i++) pq.push({0, i}); while (k--) { priority_queue<pair<long long, long long>> temp; for (auto &x : seat) { cout << x << ; for (long long i = 0; i < x; i++) { long long p = pq.top().first, u = pq.top().second; pq.pop(); p += (x != lb); cout << (u + 1) << n [i == x - 1]; temp.push({p, u}); } } pq = temp; } cout << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { solve(); } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_256_139.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_256_139 (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [138:0] data;
input rdreq;
input wrreq;
output [138:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire [138:0] sub_wire1;
wire [7:0] usedw = sub_wire0[7:0];
wire [138:0] q = sub_wire1[138:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.empty (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 139,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "139"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "139"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "139"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 139 0 INPUT NODEFVAL data[138..0]
// Retrieval info: USED_PORT: q 0 0 139 0 OUTPUT NODEFVAL q[138..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 139 0 data 0 0 139 0
// Retrieval info: CONNECT: q 0 0 139 0 @q 0 0 139 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_139_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { pair<int, int> p[100]; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> p[i].first; p[i].second = i + 1; } sort(p, p + n); for (int i = 0; i < n; i++) cout << p[i].second << ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDLCLKP_4_V
`define SKY130_FD_SC_LS__SDLCLKP_4_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDLCLKP_4_V
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone 10 LP devices Input Buffer Primitive */
module cyclone10lp_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // cyclone10lp_io_ibuf
/* Altera Cyclone 10 LP devices Output Buffer Primitive */
module cyclone10lp_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // cyclone10lp_io_obuf
/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
module cyclone10lp_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cyclone10lp_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // cyclone10lp_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200500; int mapp[maxn], num[maxn], ans[maxn]; int main() { int n, a, b, k; while (cin >> n >> a >> b >> k) { memset(ans, 0, sizeof(ans)); char c; for (int i = 0; i < n; i++) { cin >> c; mapp[i] = c - 0 ; } int len = 0, pos = 0, tk = a; int sum, sum2 = 0; for (int i = 0; i < n; i++) { if (0 == mapp[i]) len++; if (1 == mapp[i] || i == n - 1) { num[pos++] = len; int kk = len / b; if (kk <= tk) tk -= kk; else { if (i == n - 1 && !mapp[i]) i++; for (int j = tk + 1; j <= kk; j++) { ans[i - len - 1 + j * b] = 1; sum2++; } tk = 0; } len = 0; } } sum = 1; len = 0; for (int i = 0; i < n; i++) { if (0 == mapp[i]) len++; if ((1 == mapp[i] || i == n - 1) && sum > 0) { if (i == n - 1 && !mapp[i]) i++; int kk = len / b; for (int j = 1; j <= kk; j++) { sum--; if (!ans[i - len - 1 + j * b]) sum2++; ans[i - len - 1 + j * b] = 1; if (sum <= 0) break; } len = 0; } } cout << sum2 << endl; int flag = 0; for (int i = 0; i < n; i++) { if (!ans[i]) continue; if (!flag) flag = 1; else cout << ; cout << i + 1; } cout << endl; } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_aluadder64.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_aluadder64
// Description: This block implements the adder for the sparc alu.
// It takes two operands and a carry bit. It adds them together
// and sends the output to adder_out. It outputs the overflow
// and carry condition codes for both 64 bit and 32 bit operations.
*/
module sparc_exu_aluadder64
(
rs1_data,
rs2_data,
cin,
adder_out,
cout32,
cout64
);
input [63:0] rs1_data; // 1st input operand
input [63:0] rs2_data; // 2nd input operand
input cin; // carry in
output [63:0] adder_out; // result of adder
output cout32; // Cout from lower 32 bit add
output cout64; // cout from 64 bit add
////////////////////////////////////////////
// Module implementation
////////////////////////////////////////////
assign {cout32, adder_out[31:0]} = rs1_data[31:0]+rs2_data[31:0]+
cin;
assign {cout64, adder_out[63:32]} = rs1_data[63:32]
+ rs2_data[63:32] + cout32;
endmodule // sparc_exu_aluadder64
|
#include <bits/stdc++.h> using namespace std; int n, i, j, k, x, y, w, m, Q, used[100500], start; pair<pair<int, int>, int> a[100500]; vector<pair<int, int> > g[100500]; vector<int> f[100500]; long long d[100500]; long long hea[200500]; int new_w[100500], new_d[100500]; int hea2[200500]; int st[100500], sz[100500], cur_pos[100500]; pair<int, int> G[100500]; int heapSize; void add(pair<long long, int> value) { hea[heapSize++] = value.first; int i = heapSize - 1; hea2[i] = value.second; int parent = ((i - 1) >> 1); while (i > 0 && hea[parent] < hea[i]) { swap(hea[i], hea[parent]); swap(hea2[i], hea2[parent]); i = parent; parent = ((i - 1) >> 1); } } void heapify(int i) { int largestChild; for (;;) { largestChild = i; if (hea[2 * i + 1] > hea[largestChild]) { largestChild = 2 * i + 1; } if (hea[2 * i + 2] > hea[largestChild]) { largestChild = 2 * i + 2; } if (largestChild == i) { break; } swap(hea[i], hea[largestChild]); swap(hea2[i], hea2[largestChild]); i = largestChild; } } pair<long long, int> getMax() { pair<int, int> result = make_pair(hea[0], hea2[0]); heapSize--; hea[0] = hea[heapSize]; hea2[0] = hea2[heapSize]; hea[heapSize] = -(long long)1e+18; heapify(0); return result; } inline unsigned int readUInt() { int c = getc(stdin); unsigned int x = 0; while (c <= 32) c = getc(stdin); while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getc(stdin); return x; } int main() { cin >> n >> m >> Q; for (i = 0; i <= 200000; i++) hea[i] = -(long long)1e+18; for (i = 0; i < m; i++) { int x, y, z; x = readUInt(); y = readUInt(); z = readUInt(); a[i] = make_pair(make_pair(x, y), z); } int s = 1; for (i = 0; i < m; i++) { g[a[i].first.first].push_back(make_pair(a[i].first.second, a[i].second)); } st[1] = 0; sz[1] = g[1].size(); for (i = 2; i <= n; i++) { st[i] = st[i - 1] + g[i - 1].size(); sz[i] = g[i].size(); } for (i = 1; i <= n; i++) d[i] = (long long)1e+18; d[s] = 0; for (i = 0; i < heapSize; i++) hea[i] = -(long long)1e+18; heapSize = 0; add(make_pair(0, s)); while (heapSize) { pair<int, int> tmp = getMax(); int v = tmp.second; long long cur_d = -tmp.first; if (cur_d > d[v]) continue; for (size_t j = 0; j < g[v].size(); ++j) { int to = g[v][j].first; long long len = g[v][j].second; if (d[v] + len < d[to]) { d[to] = d[v] + len; add(make_pair(-d[to], to)); } } } for (i = 0; i < m; i++) new_w[i] = min(100000000LL, a[i].second + d[a[i].first.first] - d[a[i].first.second]); for (int ii = 0; ii < Q; ii++) { int test; cin >> test; if (test == 1) { int t; cin >> t; if (d[t] == (long long)1e+18) cout << -1 << endl; else cout << d[t] << endl; } else { cin >> x; for (i = 0; i < x; i++) { int y = readUInt(); new_w[y - 1]++; a[y - 1].second++; } for (i = 1; i <= n; i++) cur_pos[i] = st[i]; for (i = 0; i < m; i++) { G[cur_pos[a[i].first.first]++] = make_pair(a[i].first.second, new_w[i]); } for (i = 0; i <= n; i++) { f[i].clear(); new_d[i] = (int)1e+9; } f[0].push_back(1); new_d[1] = 0; for (i = 0; i < n; i++) { for (j = 0; j < f[i].size(); j++) { int v = f[i][j]; if (new_d[v] == i) { for (k = st[v]; k < st[v] + sz[v]; k++) { int to = G[k].first; int val = G[k].second; if (new_d[to] > i + val) { new_d[to] = min(100000000, i + val); if (new_d[to] <= n) f[new_d[to]].push_back(to); } } } } } for (i = 1; i <= n; i++) { d[i] += new_d[i]; if (d[i] > (long long)1e+18) d[i] = (long long)1e+18; } for (i = 0; i < m; i++) new_w[i] = min(100000000LL, a[i].second + d[a[i].first.first] - d[a[i].first.second]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; string s[51]; int main() { int tot = 1; cin >> s[1]; int len = s[1].size(); for (int i = 2; i <= s[1].size(); i += 1) { s[i] = s[i - 1]; string ss; ss.resize(1); ss[0] = s[i][len - 1]; s[i].insert(0, ss); s[i].erase(len, 1); int add = 1; for (int j = 1; j < i; j += 1) if (s[i] == s[j]) add = 0; tot += add; } printf( %d , tot); return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 2022 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w513,
w1026,
w1027,
w16,
w1011,
w2022;
assign w1 = i_data0;
assign w1011 = w1027 - w16;
assign w1026 = w513 << 1;
assign w1027 = w1 + w1026;
assign w16 = w1 << 4;
assign w2022 = w1011 << 1;
assign w512 = w1 << 9;
assign w513 = w1 + w512;
assign o_data0 = w2022;
//multiplier_block area estimate = 5508.51842687647;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
//==================================================================================================
// Filename : musb_div.v
// Created On : 2014-10-27 21:59:02
// Last Modified : 2015-05-24 21:00:17
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : The multi-cycle Divider unit.
// op_div and op_divu MUST BE dis-asserted after the setup
// cycle for normal operation, or the operation will be
// restarted
// WARNING: no exception if divisor == 0.
//==================================================================================================
module musb_div(
input clk, // clock
input rst, // reset
input op_divs, // 1 for signed operation
input op_divu, // 1 for unsigned operation
input [31:0] dividend, // Operand
input [31:0] divisor, // Operand
output [31:0] quotient, // Result
output [31:0] remainder, // Result
output stall // 1 while calculating
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg active; // 1 while running
reg neg_result; // 1 if the result will be negative
reg [4:0] cycle; // number of cycles needed.
reg [31:0] result; // Store the result.
reg [31:0] denominator; // divisor
reg [31:0] residual; // current remainder
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [32:0] partial_sub; // temp
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign quotient = !neg_result ? result : -result;
assign remainder = residual;
assign stall = active;
assign partial_sub = {residual[30:0], result[31]} - denominator; // calculate partial result
//--------------------------------------------------------------------------
// State Machine. This needs 32 cycles to calculate the result.
// The result is loaded after 34 cycles
// The first cycle is setup.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
active <= 1'b0;
neg_result <= 1'b0;
cycle <= 5'b0;
result <= 32'b0;
denominator <= 32'b0;
residual <= 32'b0;
end
else begin
if(op_divs) begin
// Signed division.
cycle <= 5'd31;
result <= (dividend[31] == 1'b0) ? dividend : -dividend;
denominator <= (divisor[31] == 1'b0) ? divisor : -divisor;
residual <= 32'b0;
neg_result <= dividend[31] ^ divisor[31];
active <= 1'b1;
end
else if (op_divu) begin
// Unsigned division.
cycle <= 5'd31;
result <= dividend;
denominator <= divisor;
residual <= 32'b0;
neg_result <= 1'b0;
active <= 1'b1;
end
else if (active) begin
// run a iteration
if(partial_sub[32] == 1'b0) begin
residual <= partial_sub[31:0];
result <= {result[30:0], 1'b1};
end
else begin
residual <= {residual[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 5'b0) begin
active <= 1'b0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule
|
`include "lo_simulate.v"
/*
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_simulate;
reg pck0;
reg [7:0] adc_d;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
reg cross_lo;
wire cross_hi;
wire dbg;
lo_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg)
);
integer i, counter=0;
// main clock
always #5 pck0 = !pck0;
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24MHz/192=125kHz)
task crank_dut;
begin
@(posedge pck0) ;
counter = counter + 1;
if (counter == 192) begin
counter = 0;
ssp_dout = $random;
cross_lo = 1;
end else begin
cross_lo = 0;
end
end
endtask
initial begin
pck0 = 0;
for (i = 0 ; i < 4096 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_FUNCTIONAL_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bios.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bios (
address,
clock,
q);
input [11:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "bios.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "bios.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "bios.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------------------
// File : hierarchical_wb_slave_0.v
// Creation date : 28.11.2017
// Creation time : 16:51:22
// Description : A wishbone slave containing another wishbone slave, so now you can use a wishbone slave while using a wishbone slave.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1176 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:peripheral.subsystem:hierarchical_wb_slave:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.1.0.xml
//-----------------------------------------------------------------------------
module hierarchical_wb_slave_0 #(
parameter ADDR_WIDTH = 32, // The width of the address.
parameter BASE_ADDRESS = 128, // The first referred address of the master.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter DATA_WIDTH = 32 // The width of the both transferred and inputted data.
) (
// Interface: wb_slave
input [31:0] adr_i, // The address of the data.
input cyc_i, // Asserted by master for transfer.
input [31:0] dat_i, // Data from slave to master.
input stb_i, // Asserted, when this specific slave is selected.
input we_i, // Write = 1, Read = 0.
output ack_o, // Slave asserts acknowledge.
output [31:0] dat_o, // Data from master to slave.
// Interface: wb_system
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// sub_slave_wb_system_to_wb_system wires:
wire sub_slave_wb_system_to_wb_systemclk;
wire sub_slave_wb_system_to_wb_systemrst;
// sub_slave_wb_slave_to_wb_slave wires:
wire sub_slave_wb_slave_to_wb_slaveack;
wire [31:0] sub_slave_wb_slave_to_wb_slaveadr;
wire sub_slave_wb_slave_to_wb_slavecyc;
wire [31:0] sub_slave_wb_slave_to_wb_slavedat_ms;
wire [31:0] sub_slave_wb_slave_to_wb_slavedat_sm;
wire sub_slave_wb_slave_to_wb_slaveerr;
wire sub_slave_wb_slave_to_wb_slavestb;
wire sub_slave_wb_slave_to_wb_slavewe;
// sub_slave port wires:
wire sub_slave_ack_o;
wire [31:0] sub_slave_adr_i;
wire sub_slave_clk_i;
wire sub_slave_cyc_i;
wire [31:0] sub_slave_dat_i;
wire [31:0] sub_slave_dat_o;
wire sub_slave_err_o;
wire sub_slave_rst_i;
wire sub_slave_stb_i;
wire sub_slave_we_i;
// Assignments for the ports of the encompassing component:
assign ack_o = sub_slave_wb_slave_to_wb_slaveack;
assign sub_slave_wb_slave_to_wb_slaveadr[31:0] = adr_i[31:0];
assign sub_slave_wb_system_to_wb_systemclk = clk_i;
assign sub_slave_wb_slave_to_wb_slavecyc = cyc_i;
assign sub_slave_wb_slave_to_wb_slavedat_ms[31:0] = dat_i[31:0];
assign dat_o[31:0] = sub_slave_wb_slave_to_wb_slavedat_sm[31:0];
assign sub_slave_wb_system_to_wb_systemrst = rst_i;
assign sub_slave_wb_slave_to_wb_slavestb = stb_i;
assign sub_slave_wb_slave_to_wb_slavewe = we_i;
// sub_slave assignments:
assign sub_slave_wb_slave_to_wb_slaveack = sub_slave_ack_o;
assign sub_slave_adr_i[31:0] = sub_slave_wb_slave_to_wb_slaveadr[31:0];
assign sub_slave_clk_i = sub_slave_wb_system_to_wb_systemclk;
assign sub_slave_cyc_i = sub_slave_wb_slave_to_wb_slavecyc;
assign sub_slave_dat_i[31:0] = sub_slave_wb_slave_to_wb_slavedat_ms[31:0];
assign sub_slave_wb_slave_to_wb_slavedat_sm[31:0] = sub_slave_dat_o[31:0];
assign sub_slave_rst_i = sub_slave_wb_system_to_wb_systemrst;
assign sub_slave_stb_i = sub_slave_wb_slave_to_wb_slavestb;
assign sub_slave_we_i = sub_slave_wb_slave_to_wb_slavewe;
// An instantiation of the same wishbone slave as used in wb_example design.
// IP-XACT VLNV: tut.fi:communication.template:wb_slave:1.0
wb_slave #(
.ADDR_WIDTH (32),
.DATA_WIDTH (32),
.DATA_COUNT (8),
.BASE_ADDRESS (128))
sub_slave(
// Interface: wb_slave
.adr_i (sub_slave_adr_i),
.cyc_i (sub_slave_cyc_i),
.dat_i (sub_slave_dat_i),
.stb_i (sub_slave_stb_i),
.we_i (sub_slave_we_i),
.ack_o (sub_slave_ack_o),
.dat_o (sub_slave_dat_o),
.err_o (sub_slave_err_o),
// Interface: wb_system
.clk_i (sub_slave_clk_i),
.rst_i (sub_slave_rst_i));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int i, l = s.length(); char max = s[0]; for (i = 1; i < l; i++) { if (s[i] > max) max = s[i]; } for (i = 0; i < l; i++) { if (max == s[i]) cout << max; } }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, ans = ; cin >> s; int i = 0, j = s.size() - 1; while (i < j) { if (s[i] == s[j]) { i++; j--; continue; } else { s.insert(s.begin() + j + 1, s[i]); i++; } } cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, a[100005], res = 1e9, A, B, x[100005], kq[100005], kq1[100005], dem = 0, e[100005]; void no(int val) { if (a[n] >= 0 || a[n - 1] >= 0 || res <= val) return; res = val; for (int i = 2; i <= n - 1; i++) kq[i] = x[i]; return; } void xuli(int i, int val) { if (val >= res) return; if (i == 2 || i == n - 1 || 1 == 1) { for (int j = 0; j <= 16; j++) { bool ok = true; x[i] = j; a[i - 1] -= B * j; a[i] -= A * j; a[i + 1] -= B * j; if (a[i - 1] >= 0) ok = false; if (ok == true) { if (i == n - 1) no(val + j); else xuli(i + 1, val + j); } a[i - 1] += B * j; a[i] += A * j; a[i + 1] += B * j; } } else { int tg = max(e[i] / A + 1, max(e[i - 1] / B + 1, e[i + 1] / B + 1)); for (int j = 0; j <= tg; j++) { bool ok = true; x[i] = j; a[i - 1] -= B * j; a[i] -= A * j; a[i + 1] -= B * j; if (a[i - 1] >= 0) ok = false; if (ok == true) { if (i == n - 1) no(val + j); else xuli(i + 1, val + j); } a[i - 1] += B * j; a[i] += A * j; a[i + 1] += B * j; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> A >> B; for (int i = 1; i <= n; i++) cin >> a[i], e[i] = a[i]; xuli(2, 0); cout << res << n ; for (int i = 2; i <= n - 1; i++) for (int j = 1; j <= kq[i]; j++) kq1[++dem] = i; for (int i = 1; i <= dem; i++) cout << kq1[i] << ; return 0; }
|
`timescale 1ns / 1ps
/*
-- Module Name: Outport Scheduler
-- Description: Top Level del Planificador de Salida. El modulo se
encarga de administrar el proceso de asignacion de
uso de puertos de salida. En el rse reciben peticiones
desde de los puertos de entrada (lnk controller). Se
ejecuta un proceso de arbitraje para decidir la peticion
ganadora.
Con una peticion ganadora se procede a crear un enlace
entre el puerto de entrada y el puerto de salida por
medio de Crossbar del sistema (xbar_conf_vector_dout).
Una vez terminada una transferencia de paquete entre
entrada/salida, el modulo cierra el enlace y queda a la
espera de una nueva peticion.
-- Dependencies: -- system.vh
-- outport_scheduler_control_unit.v
-- arbiter.v
-- Parameters:
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 06 de Junio 2015
*/
`include "system.vh"
module outport_scheduler #(
parameter PORT_DIR = `X_POS
)
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire [3:0] port_request_din,
input wire credit_in_din,
// -- outputs ------------------------------------------------ >>>>>
output wire [3:0] transfer_strobe_vector_dout,
output wire [3:0] xbar_conf_vector_dout,
output wire port_status_dout
);
// -- Definicion de parametros locales --------------------------- >>>>>
localparam PORT_BUSY = 1'b0;
localparam PORT_IDLE = 1'b1;
/*
-- Instancia :: Unidad de Control del Planificador de Salida
-- Descripcion: Implementacion de maquina de estado para el control de
la recepcion de peticiones desde puertos de entrada,
asignacion de uso de puerto de salida, creacion de
enlace entre puerto de entrada y puerto de salida, y
cierre de enlace.
*/
// -- Unidad de Control del Planificador de Salida --------------- >>>>>
wire transfer_strobe;
wire arbiter_strobe;
wire clear_arbiter;
wire zero_credits;
wire any_request;
assign any_request = |port_request_din;
outport_scheduler_control_unit
#(
.PORT_DIR(PORT_DIR)
)
unidad_de_control_planificador_salida
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.any_request_din (any_request),
.credit_in_din (credit_in_din),
// -- outputs -------------------------------------------- >>>>>
.zero_credits_dout (zero_credits),
.transfer_strobe_dout (transfer_strobe),
.arbiter_strobe_dout (arbiter_strobe),
.clear_arbiter_dout (clear_arbiter)
);
/*
-- Instancia :: Arbitro
-- Descripcion: Implementacion de algoritmo de arbitraje entre 4
peticiones de uso de puerto de salida. (Round Robin).
*/
// -- Arbitro de Planificador de Salida ---------------------- >>>>>
arbiter rra_allocator
(
.clk (clk),
// -- inputs ----------------------------------------- >>>>>
.port_request_din (port_request_din),
.arbiter_strobe_din (arbiter_strobe),
.clear_arbiter_din (clear_arbiter),
// -- output ----------------------------------------- >>>>>
.xbar_conf_vector_dout (xbar_conf_vector_dout)
);
// -- Logica para Salidas del Planificador ------------------- >>>>>
assign transfer_strobe_vector_dout = xbar_conf_vector_dout & {4{transfer_strobe}};
assign port_status_dout = (|xbar_conf_vector_dout || zero_credits) ? PORT_BUSY : PORT_IDLE;
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
outport_scheduler planificador_de_salida
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.port_request_din (port_request_din),
.credit_in_din (credit_in_din),
// -- outputs ------------------------------------------------ >>>>>
.transfer_strobe_vector_dout (transfer_strobe_vector_dout),
.port_status_dout (port_status_dout),
.xbar_conf_vector_dout (xbar_conf_vector_dout)
);
*/
|
`define bsg_xor_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_250_XOR2X1_b``bits xor_gate (.i0(a_i),.i1(b_i),.o); \
end
module bsg_xor #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
`bsg_xor_macro(34) else
`bsg_xor_macro(33) else
`bsg_xor_macro(32) else
`bsg_xor_macro(31) else
`bsg_xor_macro(30) else
`bsg_xor_macro(29) else
`bsg_xor_macro(28) else
`bsg_xor_macro(27) else
`bsg_xor_macro(26) else
`bsg_xor_macro(25) else
`bsg_xor_macro(24) else
`bsg_xor_macro(23) else
`bsg_xor_macro(22) else
`bsg_xor_macro(21) else
`bsg_xor_macro(20) else
`bsg_xor_macro(19) else
`bsg_xor_macro(18) else
`bsg_xor_macro(17) else
`bsg_xor_macro(16) else
`bsg_xor_macro(15) else
`bsg_xor_macro(14) else
`bsg_xor_macro(13) else
`bsg_xor_macro(12) else
`bsg_xor_macro(11) else
`bsg_xor_macro(10) else
`bsg_xor_macro(9) else
`bsg_xor_macro(8) else
`bsg_xor_macro(7) else
`bsg_xor_macro(6) else
`bsg_xor_macro(5) else
`bsg_xor_macro(4) else
`bsg_xor_macro(3) else
`bsg_xor_macro(2) else
`bsg_xor_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = a_i ^ b_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_xor)
|
#include <bits/stdc++.h> using namespace std; int n, m, b; struct chel { int cost; int mas; int coun; }; chel f[103]; chel tem[103]; void mergesort(chel *a, chel *b, int n) { int i, i0, i1, iRight, iEnd, width, j; for (width = 1; width < n; width *= 2) for (i = 0; i < n; i += width * 2) { i0 = i; i1 = iRight = min(i + width, n); iEnd = min(i + width * 2, n); for (j = i; j < iEnd; j++) if (i0 < iRight && (i1 == iEnd || a[i0].coun < a[i1].coun)) b[j] = a[i0++]; else b[j] = a[i1++]; for (j = i; j < iEnd; j++) a[j] = b[j]; } } long long dp[(1 << 20)]; int main() { int i, j; scanf( %d %d %d , &n, &m, &b); dp[0] = 0; for (i = 1; i < (1 << m); i++) dp[i] = (long long)1000000000 * 1000000000 * 2; long long ans = (long long)1000000000 * 1000000000 * 2; int x, t; for (i = 0; i < n; i++) { scanf( %d %d %d , &f[i].cost, &f[i].coun, &t); for (j = 0; j < t; j++) { scanf( %d , &x); f[i].mas |= (1 << (x - 1)); } } mergesort(f, tem, n); for (i = 0; i < n; i++) { for (j = 0; j < (1 << m); j++) dp[(j | f[i].mas)] = min(dp[(j | f[i].mas)], dp[j] + f[i].cost); ans = min(ans, dp[(1 << m) - 1] + (long long)b * f[i].coun); } if (ans == (long long)1000000000 * 1000000000 * 2) printf( -1 n ); else printf( %I64d n , ans); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
//
// Example module to create problem.
//
// generate a 64 bit value with bits
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
// all other bits zero.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] HighLogicImm; // From example of example.v
wire [63:0] LogicImm; // From example of example.v
wire [63:0] LowLogicImm; // From example of example.v
// End of automatics
wire [5:0] LowMaskSel_Top = crc[5:0];
wire [5:0] LowMaskSel_Bot = crc[5:0];
wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]};
wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]};
example example (/*AUTOINST*/
// Outputs
.LogicImm (LogicImm[63:0]),
.LowLogicImm (LowLogicImm[63:0]),
.HighLogicImm (HighLogicImm[63:0]),
// Inputs
.LowMaskSel_Top (LowMaskSel_Top[5:0]),
.HighMaskSel_Top (HighMaskSel_Top[5:0]),
.LowMaskSel_Bot (LowMaskSel_Bot[5:0]),
.HighMaskSel_Bot (HighMaskSel_Bot[5:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
LowLogicImm, HighLogicImm, LogicImm);
`endif
if (cyc==0) begin
// Single case
crc <= 8'h0;
sum <= 64'h0;
end
else if (cyc==1) begin
// Setup
crc <= 8'hed;
sum <= 64'h0;
end
else if (cyc<90) begin
sum <= {sum[62:0],sum[63]} ^ LogicImm;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b00111000) $stop;
if (sum !== 64'h58743ffa61e41075) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module example (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [5:0] LowMaskSel_Top, HighMaskSel_Top;
input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
wire [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
end
end
endgenerate
/* verilator lint_on UNSIGNED */
/* verilator lint_on CMPCONST */
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_1_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_1_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Verilog wrapper for tapvgndnovpb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgndnovpb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapvgndnovpb base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapvgndnovpb base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_1_V
|
module riscv_tb ();
parameter ADDI = 1;
parameter ORI = 2;
parameter XORI = 3;
parameter ANDI = 4;
parameter SLTI = 5;
parameter SLTUI = 6;
parameter SLLI = 7;
parameter SRLI = 8;
parameter SRAI = 9;
parameter LUI = 10;
parameter AUIPC = 11;
parameter ADD = 12;
parameter SUB = 13;
parameter OR = 14;
parameter XOR = 15;
parameter AND = 16;
parameter SLT = 17;
parameter SLTU = 18;
parameter SLL = 19;
parameter SRL = 20;
parameter SRA = 21;
parameter JALR = 22;
parameter JAL = 23;
parameter SB = 24;
parameter SH = 25;
parameter SW = 26;
parameter LB = 27;
parameter LH = 28;
parameter LW = 29;
parameter LBU = 30;
parameter LHU = 31;
parameter BEQ = 32;
parameter BNE = 33;
parameter BLT = 34;
parameter BLTU = 35;
parameter BGE = 36;
parameter BGEU = 37;
random_pool #(3, 32) instr_pool ();
reg success;
reg [31:0] instr;
initial begin
/*
*/
encoding_add(
instr_pool.add_to_pool(SLTU, success);
instr_pool.add_to_pool(SRA, success);
instr_pool.add_to_pool(JALR, success);
instr_pool.shuffle(success);
instr_pool.get_top(instr);
instr_pool.get_top(instr);
instr_pool.get_top(instr);
instr_pool.get_top(instr);
end
endmodule
module random_pool();
parameter DEPTH = 3;
parameter DATA_W = 16;
reg [DATA_W-1:0] mem [0:DEPTH-1];
integer head;
integer tail;
integer top;
integer fullness;
integer i;
initial begin
head = 0;
top = 0;
fullness = 0;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = {DATA_W{1'b0}};
end
end
task add_to_pool (input [DATA_W-1:0] data, output success);
begin
if (fullness == DEPTH) begin
success = 1'b0;
end
else begin
success = 1'b1;
mem[head] = data;
head = head + 1;
fullness = fullness + 1;
end
end
endtask
task shuffle (output success);
begin
top = $random % DEPTH;
success = 1'b1;
end
endtask
task get_top (output [DATA_W-1:0] data);
begin
if (fullness == 0) begin
$display("top on an empty fifo");
$finish;
end
else begin
data = mem[top];
$display("Returning %x from pool", data);
top = top + 1;
if (top == fullness) begin
top = 0;
end
end
end
endtask
task shuffle_and_top(output [DATA_W-1:0] data);
reg success;
begin
shuffle(success);
get_top(data);
end
endtask
endmodule
module cam ();
parameter DEPTH = 100;
parameter KEY_W = 8;
parameter DATA_W = 16;
reg [DATA_W-1:0] data_mem [0:DEPTH-1];
reg [KEY_W-1:0] key_mem [0:DEPTH-1];
reg valids [0:DEPTH-1];
integer initial_idx;
task invalidate (input x);
integer i = 0;
begin
for (i = 0; i < DEPTH; i = i + 1) begin
data_mem[i] = 0;
key_mem [i] = 0;
valids [i] = 0;
end
end
endtask
initial begin
invalidate(1);
end
task add_pair (input [KEY_W-1:0] key, input [DATA_W-1:0] data);
reg exists = 0;
integer key_idx = 0;
integer insert_idx = 0;
integer i = 0;
begin
for (i = 0; i < DEPTH; i = i+1) begin
if (key_mem[i] == key && valid[i]) begin
exists = 1;
key_idx = i;
end
end
if (exists) begin
$display("WARNING: Key %x exists with data : %x", key, data_mem[key_idx]);
end
else begin
for (insert_idx = 0; insert_idx < DEPTH; insert_idx = insert_idx + 1) begin : FIND_INSERT_IDX
if (!valids[insert_idx])
disable FIND_INSERT_IDX;
end
//Does the for loop increment the idx after the condition evaluates false? if yes then
if (insert_idx == DEPTH) begin
//else
//if (valids[insert_idx]) begin
$display("CAM IS FULL");
end
else begin
$display("Add key pair %x : %x at index %d", key, data, head);
key_mem[insert_idx] = key;
data_mem[insert_idx] = data;
valids[insert_idx] = 1'b1;
end
end
end
endtask
task find_value_by_key (input [KEY_W-1:0] key, output [DATA_W-1:0] data, output found);
integer i = 0;
begin
found = 1'b0;
for (i = 0; i < DEPTH; i = i+1) begin : FIND_BLOCK
if (key_mem[i] == key && valids[i]) begin
found = 1;
data = data_mem[i];
disable FIND_BLOCK;
end
end
end
endtask
task next (inout integer index, output valid);
begin
valid = 1'b0;
while (index < DEPTH) begin : LOOP
if (valids[index]) begin
valid = 1'b1;
disable LOOP;
end
else begin
index = index + 1;
end
end
end
endtask
task get_pair_by_index (input integer index, output [KEY_W-1:0] key, output [DATA_W-1:0], output success);
integer i = 0;
integer idx = 0;
reg valid = 1;
begin
success = 1'b0;
while (valid) begin : SEARCH_LOOP
next(i, valid);
if (idx == index) begin
key = key_mem[i];
data = key_mem[i];
success = 1'b1;
disable SEARCH_LOOP;
end
else begin
idx = idx + 1;
end
end
success = 1'b0;
end
endtask
/*
task get_index_by_key (input [KEY_W-1:0] key, output integer index, output success);
endtask
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int a, b, c, i, j, cnt = 0; cin >> a >> b >> c; for (i = 0; i <= c; i++) { for (j = c; j >= 0; j--) { if ((j * a + i * b) == c) { cout << Yes << endl; cnt = 1; break; } } if (cnt == 1) break; } if (cnt == 0) cout << No << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 110031; long long n, m; vector<vector<long long> > one(int sz) { vector<vector<long long> > ret; ret.resize(sz); for (int i = 0; i < ret.size(); i++) { ret[i].resize(sz); for (int j = 0; j < ret.size(); j++) { ret[i][j] = (i == j); } } return ret; } vector<vector<long long> > mult(vector<vector<long long> > a, vector<vector<long long> > b) { vector<vector<long long> > ret; ret.resize(a.size()); for (int i = 0; i < ret.size(); i++) { ret[i].resize(a.size()); for (int j = 0; j < ret.size(); j++) { ret[i][j] = 0; } } for (int k = 0; k < ret.size(); k++) { for (int i = 0; i < a.size(); i++) { for (int j = 0; j < b.size(); j++) { ret[i][j] = (ret[i][j] + a[i][k] * b[k][j]); ret[i][j] %= 1000000007; } } } return ret; } vector<vector<long long> > pw(vector<vector<long long> > a, long long b) { if (b == 0) return one((int)a.size()); if (b % 2) return mult(a, pw(a, b - 1)); return pw(mult(a, a), b / 2); } vector<vector<long long> > dp; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; dp.resize(m); for (int i = 0; i < m; i++) { dp[i].resize(m); } for (int i = 0; i < dp.size(); i++) { for (int j = 0; j < dp.size(); j++) { dp[i][j] = 0; } } for (int i = 0; i < dp.size(); i++) { dp[i][(i + 1) % m]++; } dp[0][0]++; dp = pw(dp, n); cout << dp[0][0] << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// tiny_spi.v ////
//// ////
//// This file is part of the TINY SPI IP core project ////
//// http://www.opencores.org/projects/tiny_spi/ ////
//// ////
//// Author(s): ////
//// - Thomas Chou <> ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module tiny_spi(
// system
input rst_i,
input clk_i,
// memory mapped
input stb_i,
input we_i,
output [31:0] dat_o,
input [31:0] dat_i,
output int_o,
input [2:0] adr_i,
//input cyc_i, // comment out for avalon
//output ack_o, // comment out for avalon
// spi
output MOSI,
output SCLK,
input MISO
);
parameter BAUD_WIDTH = 8;
parameter BAUD_DIV = 0;
parameter SPI_MODE = 0;
parameter BC_WIDTH = 3;
parameter DIV_WIDTH = BAUD_DIV ? $clog2(BAUD_DIV / 2 - 1) : BAUD_WIDTH;
reg [7:0] sr8, bb8;
wire [7:0] sr8_sf;
reg [BC_WIDTH - 1:0] bc, bc_next;
reg [DIV_WIDTH - 1:0] ccr;
reg [DIV_WIDTH - 1:0] cc, cc_next;
wire misod;
wire cstb, wstb, bstb, istb;
reg sck;
reg sf, ld;
reg bba; // buffer flag
reg txren, txeen;
wire txr, txe;
wire cpol, cpha;
reg cpolr, cphar;
wire wr;
wire cyc_i; // comment out for wishbone
wire ack_o; // comment out for wishbone
assign cyc_i = 1'b1; // comment out for wishbone
assign ack_o = stb_i & cyc_i; // zero wait
assign wr = stb_i & cyc_i & we_i & ack_o;
assign wstb = wr & (adr_i == 1);
assign istb = wr & (adr_i == 2);
assign cstb = wr & (adr_i == 3);
assign bstb = wr & (adr_i == 4);
assign sr8_sf = { sr8[6:0],misod };
assign dat_o =
(sr8 & {8{(adr_i == 0)}})
| (bb8 & {8{(adr_i == 1)}})
| ({ txr, txe } & {8{(adr_i == 2)}})
;
parameter
IDLE = 0,
PHASE1 = 1,
PHASE2 = 2
;
reg [1:0] spi_seq, spi_seq_next;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
spi_seq <= IDLE;
else
spi_seq <= spi_seq_next;
always @(posedge clk_i)
begin
cc <= cc_next;
bc <= bc_next;
end
always @(/*AS*/bba or bc or cc or ccr or cpha or cpol or spi_seq)
begin
sck = cpol;
cc_next = BAUD_DIV ? (BAUD_DIV / 2 - 1) : ccr;
bc_next = bc;
ld = 1'b0;
sf = 1'b0;
case (spi_seq)
IDLE:
begin
if (bba)
begin
bc_next = 7;
ld = 1'b1;
spi_seq_next = PHASE2;
end
else
spi_seq_next = IDLE;
end
PHASE2:
begin
sck = (cpol ^ cpha);
if (cc == 0)
spi_seq_next = PHASE1;
else
begin
cc_next = cc - 1;
spi_seq_next = PHASE2;
end
end
PHASE1:
begin
sck = ~(cpol ^ cpha);
if (cc == 0)
begin
bc_next = bc -1;
sf = 1'b1;
if (bc == 0)
begin
if (bba)
begin
bc_next = 7;
ld = 1'b1;
spi_seq_next = PHASE2;
end
else
spi_seq_next = IDLE;
end
else
spi_seq_next = PHASE2;
end
else
begin
cc_next = cc - 1;
spi_seq_next = PHASE1;
end
end
endcase
end // always @ (...
always @(posedge clk_i)
begin
if (cstb) // control reg
{ cpolr, cphar } <= dat_i;
else
{ cpolr, cphar } <= { cpolr, cphar };
if (istb) // irq enable reg
{ txren, txeen } <= dat_i;
else
{ txren, txeen } <= { txren, txeen };
if (bstb) // baud reg
ccr <= dat_i;
else
ccr <= ccr;
if (ld) // shift reg
sr8 <= bb8;
else if (sf)
sr8 <= sr8_sf;
else
sr8 <= sr8;
if (wstb) // buffer reg
bb8 <= dat_i;
else if (ld)
bb8 <= (spi_seq == IDLE) ? sr8 : sr8_sf;
else
bb8 <= bb8;
end // always @ (posedge clk_i)
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i)
bba <= 1'b0;
else if (wstb)
bba <= 1'b1;
else if (ld)
bba <= 1'b0;
else
bba <= bba;
end
assign { cpol, cpha } = ((SPI_MODE >= 0) & (SPI_MODE < 4)) ?
SPI_MODE : { cpolr, cphar };
assign txe = (spi_seq == IDLE);
assign txr = ~bba;
assign int_o = (txr & txren) | (txe & txeen);
assign SCLK = sck;
assign MOSI = sr8[7];
assign misod = MISO;
endmodule
|
// file: bclk_dll_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module bclk_dll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.518*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
bclk_dll_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
`timescale 1ns/10ps
module mainPLL_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("1.152000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include<iostream> #include<string> using namespace std; int main() { int T; cin >> T; for (int t=0;t<T;t++) { string s; int n, q; cin >> n >> q >> s; int f0 = -1; int f1 = -1; int l0 = -1; int l1 = -1; for (int i=0;i<n;i++) { if(s[i]== 0 ) { l0=i; if( f0==-1) { f0=i; } } else if(s[i]== 1 ) { l1=i; if(f1==-1) { f1=i; } } } for(int i=0;i<q;i++) { int l, r; cin >> l >> r; l--; r--; bool extendLeft = (s[l]== 0 && f0 < l) || (s[l]== 1 && f1 < l); bool extendRight = (s[r]== 0 && l0 > r) || (s[r]== 1 && l1 > r); if(extendRight || extendLeft) { cout << YES << endl; } else { cout << NO << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, x, mx = 0, ans; cin >> n; while (n--) { cin >> x; if (x > mx) mx = x; } ans = mx ^ x; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, q; cin >> n >> q; vector<int> res(n + 1, 0); vector<vector<int>> adjacenyList(n + 1); for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adjacenyList[u].emplace_back(v); adjacenyList[v].emplace_back(u); } function<void(int, int)> DFS = [&](int u, int val) { res[u] = val; for (int v : adjacenyList[u]) { if (res[v]) continue; DFS(v, min(v, val)); } }; int c = 0, l = 0; int t, x; cin >> t >> x; x = (x + l) % n + 1; c = x; DFS(x, x); while (--q) { cin >> t >> x; x = (x + l) % n + 1; if (t & 1) { c = min(c, res[x]); } else { l = min(c, res[x]); cout << l << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_4_V
`define SKY130_FD_SC_HDLL__OR4_4_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 16; const int inf = 1e9 + 7; int f[N][N][N][2][2][2]; struct node { int x; int y; int z; int i1; int j1; int k1; int p1; int fi1, fi2; } pre[N][N][N][2][2][2]; int a[N], b[N], c[N]; char s[N * 5]; inline void Upd(int &x, int y, node &v, int t1, int t2, int t3, int ii, int jj, int kk, int pp, int p1, int p2) { if (x == -1) x = inf; if (x <= y) return; x = y; v.x = t1; v.y = t2; v.z = t3; v.i1 = ii; v.j1 = jj; v.k1 = kk; v.p1 = pp; v.fi1 = p1; v.fi2 = p2; } int main() { scanf( %s , s + 1); int na, nb, nc; na = nb = nc = 0; memset(a, -1, sizeof(a)); memset(b, -1, sizeof(b)); memset(c, -1, sizeof(c)); int len = strlen(s + 1); int ii = 1; while (s[ii] != + ) { a[++na] = s[ii] - 0 ; ii++; } ii++; while (s[ii] != = ) { b[++nb] = s[ii] - 0 ; ii++; } ii++; while (ii <= len) { c[++nc] = s[ii] - 0 ; ii++; } reverse(a + 1, a + 1 + na); reverse(b + 1, b + 1 + nb); reverse(c + 1, c + 1 + nc); memset(f, -1, sizeof(f)); f[0][0][0][0][0][0] = 0; for (int i = (0); i <= (na); i++) for (int j = (0); j <= (nb); j++) for (int k = (0); k <= (nc); k++) for (int up = (1); up >= (0); up--) for (int p1 = (0); p1 <= (1); p1++) for (int p2 = (0); p2 <= (1); p2++) if (f[i][j][k][up][p1][p2] != -1) { for (int t1 = (0); t1 <= (9); t1++) for (int t2 = (0); t2 <= (9); t2++) { int t3 = t1 + t2 + up; for (int q1 = (p1); q1 <= (1); q1++) for (int q2 = (p2); q2 <= (1); q2++) { int nxt = f[i][j][k][up][p1][p2] + 3; if (p1 && (i < na || t1)) continue; if (p2 && (i < na || t2)) continue; if ((i == na && !t1) && q1) nxt--; if ((j == nb && !t2) && q2) nxt--; Upd(f[i + (t1 == a[i + 1])][j + (t2 == b[j + 1])] [k + ((t3 % 10) == c[k + 1])][t3 / 10][q1][q2], nxt, pre[i + (t1 == a[i + 1])][j + (t2 == b[j + 1])] [k + ((t3 % 10) == c[k + 1])][t3 / 10][q1][q2], t1, t2, t3 % 10, i, j, k, up, p1, p2); } } } int i = na, j = nb, k = nc, p = 0, t1 = 1, t2 = 1; long long ra = 0, rb = 0, rc = 0; while (i || j || k) { ra = 10ll * ra + pre[i][j][k][p][t1][t2].x; rb = 10ll * rb + pre[i][j][k][p][t1][t2].y; rc = 10ll * rc + pre[i][j][k][p][t1][t2].z; int ti = i, tj = j, tk = k, tp = p, n1 = t1, n2 = t2; i = pre[ti][tj][tk][tp][n1][n2].i1; j = pre[ti][tj][tk][tp][n1][n2].j1; k = pre[ti][tj][tk][tp][n1][n2].k1; p = pre[ti][tj][tk][tp][n1][n2].p1; t1 = pre[ti][tj][tk][tp][n1][n2].fi1; t2 = pre[ti][tj][tk][tp][n1][n2].fi2; } printf( %lld+%lld=%lld n , ra, rb, rc); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200004, M = 19; vector<int> g[N]; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int d[N], fa[N][M], n; long long w[N][M], a[N], mod = 1000000007; void bfs() { d[1] = 1; for (int i = 0; i < M; i++) w[1][i] = a[1]; queue<int> q; q.push(1); while (!q.empty()) { int u = q.front(); q.pop(); for (int v : g[u]) { if (d[v]) continue; d[v] = d[u] + 1; fa[v][0] = u; w[v][0] = a[v]; for (int i = 1; i < M; i++) { fa[v][i] = fa[fa[v][i - 1]][i - 1]; w[v][i] = gcd(w[v][i - 1], w[fa[v][i - 1]][i - 1]); } q.push(v); } } } int main() { int x, y; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i < n; i++) { scanf( %d %d , &x, &y); g[x].push_back(y); g[y].push_back(x); } bfs(); long long ans = 0; for (int i = 1; i <= n; i++) { long long nw = a[i]; int pre = d[i]; for (;;) { int v = i; for (int j = M - 1; j >= 0; j--) if (w[v][j] == 0) v = fa[v][j]; for (int j = M - 1; j >= 0; j--) if (gcd(nw, w[v][j]) == nw) v = fa[v][j]; ans = (ans + nw * (pre - d[v])) % mod; if (v == 0) break; nw = gcd(nw, a[v]); pre = d[v]; } } printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n; x = (n + 1) / 2; string s, even, odd; cin >> s; for (int i = 0; i < n; i++) { if (i % 2 == 0) odd.push_back(s[i]); else even.push_back(s[i]); } if (n <= 2) { cout << s << endl; } else { if (n % 2 == 0) { reverse(odd.begin(), odd.end()); for (int i = 0; i < x; i++) { odd.push_back(even[i]); } even = odd; } else if (n % 2 == 1) { reverse(even.begin(), even.end()); for (int i = 0; i < x; i++) { even.push_back(odd[i]); } } cout << even << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)(1e5 + 123); vector<int> gg[MAXN], gb[MAXN]; bool was[MAXN], been[MAXN]; int cnt = 0; void dfs(int v) { cnt++; was[v] = been[v] = true; for (auto to : gg[v]) { if (was[to]) continue; dfs(to); } } int main() { int n; cin >> n; int good; cin >> good; for (int i = 1; i <= good; i++) { int a, b; cin >> a >> b; gg[a].push_back(b); gg[b].push_back(a); } int bad; cin >> bad; for (int i = 1; i <= bad; i++) { int a, b; cin >> a >> b; gb[a].push_back(b); gb[b].push_back(a); } int ans = 0; for (int i = 1; i <= n; i++) { if (was[i]) continue; cnt = 0; dfs(i); bool no = false; for (int j = 1; j <= n; j++) { if (been[j]) { for (auto to : gb[j]) if (been[to]) { no = true; break; } } if (no) break; } if (!no) ans = max(ans, cnt); for (int j = 1; j <= n; j++) been[j] = false; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200010]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int mn = a[n]; for (int i = 1; i <= n / 2; i++) mn = min(mn, a[i + n / 2] - a[i]); printf( %d n , mn); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:40:54 03/28/2015
// Design Name:
// Module Name: regfileparam
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module regfileparam
#(parameter BITSIZE = 16,
parameter ADDSIZE = 4)
(output [BITSIZE-1:0] adat,
output [BITSIZE-1:0] bdat,
input [ADDSIZE-1:0] ra, // Read A Address
input [ADDSIZE-1:0] rb, // Read B Address
input [ADDSIZE-1:0] rw, // Write Address
input [BITSIZE-1:0] wdat,
input wren,
input clk, rst
);
localparam NUM_REGS = 2**ADDSIZE;
wire [NUM_REGS-1:0] decodout;
wire [BITSIZE-1:0] regouts [NUM_REGS-1:0];
wire [BITSIZE*NUM_REGS-1:0] regouts2;
// Write Address Decoder
decoderparam #(.WIDTH(ADDSIZE)) inputdecoder (
.code(decodout),
.a(rw),
.clken(wren)
);
// Generate Registers.
genvar c;
generate
for (c=0; c < NUM_REGS; c=c+1) begin : GEN_REGS
regparam
# (.SIZE(BITSIZE)) regs
(.Q(regouts[c]),
.D(wdat),
.clk(clk),
.rst(rst),
.clken(decodout[c])
);
end
endgenerate
// Flatten regouts for muxes.
genvar d;
generate
for (d=0; d < NUM_REGS; d=d+1) begin : FLATTEN_REGOUTS
assign regouts2[d*BITSIZE +: BITSIZE] = regouts[d];
end
endgenerate
// Read MUX'es. There exists two.
muxparam #(.WIDTH(NUM_REGS), .BITSIZE(BITSIZE)) read1 (
.y(adat),
.a(regouts2),
.sel(ra)
);
muxparam #(.WIDTH(NUM_REGS), .BITSIZE(BITSIZE)) read2 (
.y(bdat),
.a(regouts2),
.sel(rb)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5, M = 35; int n, m, x; int g[M][M], tot, v[1000][2]; int main() { int T; cin >> T; while (T--) { cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &g[i][j]); } } int ans = 0; memset(v, 0, sizeof(v)); tot = (n + m - 1) / 2; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { int k = i + j - 1; if (k <= tot) { v[k][g[i][j]]++; } else if ((m + n - k) <= tot) { v[(m + n - k)][g[i][j]]++; } } } for (int i = 1; i <= tot; i++) { ans += min(v[i][0], v[i][1]); } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> E[65600]; vector<pair<int, int> > V; int main() { int n; scanf( %d , &n); queue<int> Q; int degree[65600 + 10], Xsum[65600 + 10]; for (int i = 0; i < n; i++) { int a, b; scanf( %d %d , &a, &b); degree[i] = a; Xsum[i] = b; if (degree[i] == 1) Q.push(i); } while (!Q.empty()) { int u = Q.front(); Q.pop(); if (degree[u] == 0) continue; int othernode = Xsum[u]; V.push_back(make_pair(u, othernode)); degree[othernode]--; degree[u]--; Xsum[othernode] = Xsum[othernode] ^ u; if (degree[othernode] == 1) Q.push(othernode); } printf( %d n , V.size()); for (int i = 0; i < V.size(); i++) printf( %d %d n , V[i].first, V[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int mod = (int)1e9 + 7; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void solve() { int n; cin >> n; if (n % 2 == 0) { cout << -1 n ; return; } for (int i = 0; i < n; i++) { cout << i << ; } cout << n ; for (int i = 0; i < n; i++) { cout << (i + 1) % n << ; } cout << n ; for (int i = 0; i < n; i++) { cout << (i + i + 1) % n << ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, a, k; int x[200030], xx[200030]; bool judge(int m) { for (int i = 1; i <= m; i++) xx[i] = x[i]; sort(xx + 1, xx + 1 + m); int ans = 0; xx[0] = 0; for (int i = 1; i <= m; i++) ans += (xx[i] - xx[i - 1]) / (a + 1); ans += (n - xx[m] + 1) / (a + 1); return ans < k; } int main() { int m; scanf( %d%d%d , &n, &k, &a); scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d , x + i); int ans = 1 << 30; int l = 1, r = m, mid; while (l <= r) { mid = (l + r) >> 1; if (judge(mid)) ans = min(ans, mid), r = mid - 1; else l = mid + 1; } if (ans == (1 << 30)) ans = -1; printf( %d n , ans); }
|
#include <bits/stdc++.h> const int N = 1000; bool vis[N + 100]; int v[N + 100]; int top = 0; int n = 0; int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) { if (!vis[i]) { vis[i] = true; for (int j = 0; j < n; j++) { if (!vis[j]) continue; if (i * j > n) break; if ((j % i == 0) || (i % j == 0)) continue; vis[i * j] = true; } v[top++] = i; } } printf( %d n , top); for (int i = 0; i < top; i++) { printf( %d , v[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long exp(long long a, long long b, long long p) { if (b == 0) return 1; if (b % 2) return a * exp(a, b - 1, p) % p; return exp(a * a % p, b / 2, p); } long long inv[1000009], E[1000009]; int main() { long long a, b, p, x; cin >> a >> b >> p >> x; vector<long long> v; for (int i = 1; i <= p; i++) { if ((p - 1) % i == 0) v.push_back(i); } long long on; for (int j = 0; j < v.size(); j++) { if (exp(a, v[j], p) == 1) { on = v[j]; break; } } for (int i = 1; i <= p; i++) { inv[i] = exp(i, p - 2, p); } long long ans = 0; for (int i = 1; i <= on; i++) { long long E = exp(a, i, p); long long N = inv[E] * b % p; long long y = (N - i + p) * inv[on] % p; long long m = i + y * on; long long M = p * on; if (x % M >= m) ans += x / M + 1; else ans += x / M; } cout << ans << endl; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_9_1 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int X1[500010], Y1[500010], X2[500010], Y2[500010]; int main() { int n, i; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d %d %d %d , &X1[i], &Y1[i], &X2[i], &Y2[i]); printf( YES n ); for (i = 1; i <= n; i++) { if (X1[i] % 2 == 0) { if (Y1[i] % 2 == 0) printf( 1 n ); else printf( 2 n ); } else { if (Y1[i] % 2 == 0) printf( 3 n ); else printf( 4 n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int vis[2005]; int main() { int n, m, k; char c; scanf( %d%d%d , &n, &m, &k); int ans = 0; for (int i = 0; i < n; i++) { getchar(); int temp = 0; for (int j = 0; j < m; j++) { scanf( %c , &c); if (c == . ) { vis[j]++; temp++; } else { vis[j] = 0; temp = 0; } if (temp >= k) ans++; if (vis[j] >= k && k != 1) ans++; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 10; const long long INF = 1e18 + 10; struct node { int next, v; } edge[maxn * 2 + 10]; int cnt, head[maxn], vis[maxn], pa[maxn]; long long sum[maxn], cost[maxn], a[maxn], ss[maxn]; queue<int> q; int find(int x) { if (x == pa[x]) return x; return pa[x] = find(pa[x]); } void add2(int x, int y) { x = find(x); y = find(y); pa[x] = y; ss[y] += ss[x]; } void dfs(int u, int fa) { int i, v; sum[u] = a[u]; for (i = head[u]; i != -1; i = edge[i].next) { v = edge[i].v; if (v == fa) continue; dfs(v, u); if (sum[v] > 0) sum[u] += sum[v]; } } void dfs2(int u, int fa) { int i, v; if (u == 1) { cost[u] = sum[u]; for (i = head[1]; i != -1; i = edge[i].next) { v = edge[i].v; dfs2(v, u); } return; } if (sum[u] <= 0) { cost[u] = max(sum[u], sum[u] + cost[fa]); } else { long long tmp = cost[fa] - sum[u]; if (tmp > 0) { cost[u] = sum[u] + tmp; add2(u, fa); } else { cost[u] = sum[u]; } } for (i = head[u]; i != -1; i = edge[i].next) { v = edge[i].v; if (fa == v) continue; dfs2(v, u); } } void add(int x, int y) { edge[cnt].next = head[x]; edge[cnt].v = y; head[x] = cnt++; } int main() { int i, n; long long ans, ret, s, u, v; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %I64d , &a[i]); } cnt = 0; memset(head, -1, sizeof(head)); for (i = 1; i <= n - 1; i++) { scanf( %d%d , &u, &v); add(u, v); add(v, u); } for (i = 1; i <= n; i++) { pa[i] = i; ss[i] = a[i]; } dfs(1, -1); dfs2(1, -1); ans = -INF; for (i = 1; i <= n; i++) ans = max(ans, cost[i]); if (ans <= 0) { ret = 0; s = 0; for (i = 1; i <= n; i++) { if (ans == cost[i]) { ret++; s += ans; } } printf( %I64d %I64d n , s, ret); } else { ret = 0; s = 0; memset(vis, 0, sizeof(vis)); for (i = 1; i <= n; i++) { if (ans == cost[i]) { int tt = find(i); if (!vis[tt] && ss[tt] == ans) { ret++; s += ans; vis[tt] = 1; } } } printf( %I64d %I64d n , s, ret); } return 0; }
|
#include <bits/stdc++.h> int main() { int n, i; scanf( %d , &n); int array[n]; for (i = 0; i < n; i++) { scanf( %d , &array[i]); } int min = 9999999, max = 0, count; for (i = 0; i < n; i++) { if (array[i] < min) { min = array[i]; } if (array[i] > max) { max = array[i]; } } int maxIndex, minIndex; for (i = 0; i < n; i++) { if (array[i] == max) { maxIndex = i; break; } } for (i = n - 1; i >= 0; i--) { if (array[i] == min) { minIndex = i; break; } } int maxDistance, minDistance; int swapCount = 0; for (i = maxIndex; i > 0; i--) { swapCount++; int temp = array[i]; array[i] = array[i - 1]; array[i - 1] = temp; } for (i = 0; i < n; i++) { if (array[i] == max) { maxIndex = i; break; } } for (i = n - 1; i >= 0; i--) { if (array[i] == min) { minIndex = i; break; } } for (i = minIndex; i < n - 1; i++) { swapCount++; int temp = array[i]; array[i] = array[i + 1]; array[i + 1] = temp; } printf( %d , swapCount); }
|
`include "config.v"
module seq_channel(
clk,
reset, operate,
out,
reg_clk, reg_addr, reg_data, reg_wr
);
parameter REGBASE = 0;
input clk;
input reset;
input operate;
output out;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
reg out;
initial out = 0;
reg [31:0] counter;
initial counter = 32'h0;
wire [31:0] config_value;
wire enabled = config_value[0];
wire initial_state = config_value[1];
register #(.ADDR(REGBASE+0)) config_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(config_value)
);
wire [31:0] initial_count;
register #(.ADDR(REGBASE+1)) initial_count_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(initial_count)
);
wire [31:0] low_count;
register #(.ADDR(REGBASE+2)) low_count_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(low_count)
);
wire [31:0] high_count;
register #(.ADDR(REGBASE+3)) high_count_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(high_count)
);
always @(posedge clk)
begin
if (reset)
begin
out <= initial_state;
counter <= initial_count;
end
else if (enabled && operate)
begin
if (counter == 0)
begin
out <= !out;
counter <= out ? low_count : high_count;
end
else
counter <= counter - operate;
end
end
endmodule
module sequencer(
clk,
outputs,
reg_clk, reg_addr, reg_data, reg_wr
);
input clk;
output [3:0] outputs;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
wire [31:0] config_value;
wire operate = config_value[0];
wire reset = config_value[1];
register #(.ADDR(8'h20)) config_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(config_value)
);
readonly_register #(.ADDR(8'h21)) clockrate_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.value(`SEQ_CLOCKRATE)
);
seq_channel #(.REGBASE(8'h28)) seq_ch0(
.clk(clk),
.reset(reset),
.operate(operate),
.out(outputs[0]),
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr)
);
seq_channel #(.REGBASE(8'h30)) seq_ch1(
.clk(clk),
.reset(reset),
.operate(operate),
.out(outputs[1]),
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr)
);
seq_channel #(.REGBASE(8'h38)) seq_ch2(
.clk(clk),
.reset(reset),
.operate(operate),
.out(outputs[2]),
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr)
);
seq_channel #(.REGBASE(8'h40)) seq_ch3(
.clk(clk),
.reset(reset),
.operate(operate),
.out(outputs[3]),
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string str[500005]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> str[i]; for (int i = n - 2; i >= 0; i--) { if (str[i] > str[i + 1]) { string temp; for (int j = 0; j < str[i].length(); j++) { if (str[i + 1].length() < j || str[i][j] > str[i + 1][j]) break; temp += str[i][j]; } str[i] = temp; } } for (int i = 0; i < n; i++) cout << str[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; const long long OO = 0x3f3f3f3f3f3f3f3fLL; const int maxn = 200000; int d, V, n; pair<int, int> a[maxn + 5]; long long dp[maxn + 5]; int Min[maxn + 5]; int main() { memset(Min, -1, sizeof Min); scanf( %d%d%d , &d, &V, &n); for (int i = (0), _end_ = (n); i < _end_; ++i) scanf( %d%d , &a[i].first, &a[i].second); a[n++] = make_pair(0, 0); a[n++] = make_pair(d, 0); sort(a, a + n); for (int i = (0), _end_ = (n - 1); i < _end_; ++i) if (a[i].first + V < a[i + 1].first) { printf( -1 n ); return 0; } long long ans = 0; int lst = 0, cur = 0; for (int i = (1), _end_ = (n); i < _end_; ++i) { cur = a[i - 1].first; while (a[lst].first + V < a[i].first) { ans += (long long)(a[lst].first + V - cur) * a[lst].second; cur = a[lst].first + V; int best = -1; for (int j = lst + 1; j <= n; j += j & -j) if (best == -1 || (Min[j] != -1 && a[Min[j]].second < a[best].second)) best = Min[j]; lst = best; } ans += (long long)(a[i].first - cur) * a[lst].second; cur = a[i].first; if (a[i].second < a[lst].second) lst = i; for (int j = i; j > 0; j -= j & -j) if (Min[j] == -1 || a[Min[j]].second > a[i].second) Min[j] = i; } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; namespace io { template <class T> void re(complex<T>& x); template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } void re(ld& x) { string t; re(t); x = stold(t); } template <class T, class... Ts> void re(T& t, Ts&... ts) { re(t); re(ts...); } template <class T> void re(complex<T>& x) { T a, b; re(a, b); x = {a, b}; } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.f, p.s); } template <class T> void re(vector<T>& a) { for (int i = (0) - (1 - 2 * (0 > ((int)a.size())) < 0); (1 - 2 * (0 > ((int)a.size()))) > 0 ? i < (((int)a.size())) : i >= (((int)a.size())); i += (1 - 2 * (0 > ((int)a.size())))) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = (0) - (1 - 2 * (0 > SZ) < 0); (1 - 2 * (0 > SZ)) > 0 ? i < (SZ) : i >= (SZ); i += (1 - 2 * (0 > SZ))) re(a[i]); } void pr(int x) { cout << x; } void pr(long x) { cout << x; } void pr(ll x) { cout << x; } void pr(unsigned x) { cout << x; } void pr(unsigned long x) { cout << x; } void pr(unsigned long long x) { cout << x; } void pr(float x) { cout << x; } void pr(double x) { cout << x; } void pr(ld x) { cout << x; } void pr(char x) { cout << x; } void pr(const char* x) { cout << x; } void pr(const string& x) { cout << x; } void pr(bool x) { pr(x ? true : false ); } template <class T> void pr(const complex<T>& x) { cout << x; } template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T> void pr(const T& x); template <class T, class... Ts> void pr(const T& t, const Ts&... ts) { pr(t); pr(ts...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.f, , , x.s, } ); } template <class T> void pr(const T& x) { pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } void ps() { pr( n ); } template <class T, class... Ts> void ps(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( ); ps(ts...); } void pc() { pr( ] n ); } template <class T, class... Ts> void pc(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( , ); pc(ts...); } } // namespace io using namespace io; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } ll n; unordered_map<ll, vector<int>> mp; int find(int u, int v) { if (u == v) return mp[v].size(); int n = ((int)mp[u].size()), m = ((int)mp[v].size()); int i = 0, j = 0, ans = 1, last; bool cur = 0; if (mp[u][i] < mp[v][j]) { cur = 0; last = mp[u][i]; i++; } else { cur = 1; last = mp[v][j], j++; } while (i < n or j < m) { if (i == n) { if (cur == 0 and last < mp[v].back()) return ans + 1; else return ans; } else if (j == m) { if (cur == 1 and last < mp[u].back()) { return ans + 1; } else return ans; } else if (cur == 0) { while (j < m and mp[v][j] < last) j++; if (j < m) last = mp[v][j], ans++, j++, cur = 1; } else { while (i < n and mp[u][i] < last) i++; if (i < n) last = mp[u][i], ans++, i++, cur = 0; } } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); re(n); int a[n]; unordered_set<ll> st; for (int i = (0) - (1 - 2 * (0 > n) < 0); (1 - 2 * (0 > n)) > 0 ? i < (n) : i >= (n); i += (1 - 2 * (0 > n))) re(a[i]), mp[a[i]].push_back(i), st.insert(a[i]); int ans = 0; vector<int> ss; for (auto i : st) ss.push_back(i); for (int ii = (0) - (1 - 2 * (0 > ((int)ss.size())) < 0); (1 - 2 * (0 > ((int)ss.size()))) > 0 ? ii < (((int)ss.size())) : ii >= (((int)ss.size())); ii += (1 - 2 * (0 > ((int)ss.size())))) { for (int jj = (ii) - (1 - 2 * (ii > ((int)ss.size())) < 0); (1 - 2 * (ii > ((int)ss.size()))) > 0 ? jj < (((int)ss.size())) : jj >= (((int)ss.size())); jj += (1 - 2 * (ii > ((int)ss.size())))) { int i = ss[ii], j = ss[jj]; ckmax(ans, find(i, j)); } } ps(ans); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
// SPDX-License-Identifier: CC0-1.0
parameter N = 4;
interface a_if #(parameter PARAM = 0) ();
logic long_name;
modport source (output long_name);
modport sink (input long_name);
endinterface
module intf_source
(
input logic [N-1:0] intf_input,
a_if.source i_intf_source[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign i_intf_source[i].long_name = intf_input[i];
end
endgenerate
endmodule
module intf_sink
(
output [N-1:0] a_out,
a_if.sink i_intf_sink[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign a_out[i] = i_intf_sink[i].long_name;
end
endgenerate
endmodule
module t
(
clk
);
input clk;
logic [N-1:0] a_in;
logic [N-1:0] a_out;
logic [N-1:0] ack_out;
a_if #(.PARAM(1)) tl_intf [N-1:0] ();
intf_source source(a_in, tl_intf);
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
if (ack_out != a_out) begin
$stop;
end
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:02:53 05/24/2016
// Design Name: escritor_lector_rtc
// Module Name: D:/TEC/I 2016/Lab Digitales/Proyecto III/Proyecto Xillinx/Proyecto_3/testbench_escitor_lector_rtc.v
// Project Name: Proyecto_3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: escritor_lector_rtc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_escitor_lector_rtc;
// Inputs
reg clk;
reg reset;
reg [7:0] port_id;
reg [7:0] in_dato;
reg write_strobe;
reg read_strobe;
// Outputs
wire reg_a_d;
wire reg_cs;
wire reg_rd;
wire reg_wr;
wire [7:0] out_dato;
wire [7:0] fin_lectura_escritura;
// Bidirs
wire [7:0] dato;
// Instantiate the Unit Under Test (UUT)
escritor_lector_rtc uut (
.clk(clk),
.reset(reset),
.port_id(port_id),
.in_dato(in_dato),
.write_strobe(write_strobe),
.read_strobe(read_strobe),
.reg_a_d(reg_a_d),
.reg_cs(reg_cs),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.out_dato(out_dato),
.fin_lectura_escritura(fin_lectura_escritura),
.dato(dato)
);
always #10 clk = ~clk;
/*
reg count;
always @ (posedge clk) begin
count = count + 1'b1;
end
always @(negedge count) begin
end
*/
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
port_id = 0;
in_dato = 0;
write_strobe = 0;
read_strobe = 0;
#10 reset = 0;
#20 port_id = 8'h10;
in_dato = 8'h01;
#20 port_id = 8'h00;
in_dato = 8'h21;
#20 port_id = 8'h01;
in_dato = 8'h01;
#100000 $stop;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_SYMBOL_V
`define SKY130_FD_SC_LS__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Freeze logic ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generates all freezes and stalls inside RISC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_freeze.v,v $
// Revision 1.8 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.2 2003/12/05 00:09:49 lampret
// No functional change.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.5 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.4 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
`define OR1200_NO_FREEZE 3'd0
`define OR1200_FREEZE_BYDC 3'd1
`define OR1200_FREEZE_BYMULTICYCLE 3'd2
`define OR1200_WAIT_LSU_TO_FINISH 3'd3
`define OR1200_WAIT_IC 3'd4
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module or1200_freeze(
// Clock and reset
clk, rst,
// Internal i/f
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
icpu_ack_i, icpu_err_i
);
//
// I/O
//
input clk;
input rst;
input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
input flushpipe;
input extend_flush;
input lsu_stall;
input if_stall;
input lsu_unstall;
input abort_ex;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
input icpu_ack_i;
input icpu_err_i;
//
// Internal wires and regs
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze ) | du_stall | mac_stall;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
//
// registered flushpipe
//
always @(posedge clk or posedge rst)
if (rst)
flushpipe_r <= #1 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= #1 flushpipe;
else if (!flushpipe)
flushpipe_r <= #1 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
//
// Multicycle counter
//
always @(posedge clk or posedge rst)
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
//$show_signal_value(or1200_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze );
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b); long long mpower(long long x, long long y, long long c); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); map<long long, long long> M; vector<long long> aa; set<long long> st; set<long long>::iterator itr; long long n, i, j, k; cin >> n; string s; cin >> s; long long cnt = 0; for (i = n - 1; i >= 0; i--) { long long flag = -1; if (2 * (i + 1) <= n) { for (j = i + 1; j < (2 * (i + 1)); j++) { if (s[j] == s[j - 1 - i]) { flag = 1; } else { flag = -1; break; } } } if (flag == 1) { i = -1; } cnt++; } cout << cnt; return 0; } long long gcd(long long a, long long b) { if (b == 0) { return a; } else { return gcd(b, a % b); } } long long mpower(long long x, long long y, long long c) { long long res = 1; while (y > 0) { if (y & 1) res = (res * x) % c; y = y >> 1; x = (x * x) % c; } return res; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.