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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:00:13 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_stub.v
// Design : fifo_generator_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[8:0],wr_data_count[9:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_SYMBOL_V
`define SKY130_FD_SC_HD__SDLCLKP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_SYMBOL_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_lp__udp_mux_4to2.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dq_pscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dq_pscan(serial_in ,serial_out ,bypass_in ,out_type ,clk ,
bypass ,ps_select ,rcv_in );
output serial_out ;
input serial_in ;
input bypass_in ;
input out_type ;
input clk ;
input bypass ;
input ps_select ;
input rcv_in ;
supply0 vss ;
wire net70 ;
wire net73 ;
wire net80 ;
wire net44 ;
wire net46 ;
wire net48 ;
wire net50 ;
wire net52 ;
wire net54 ;
wire net58 ;
wire net62 ;
wire net66 ;
bw_u1_inv_1x ps_inv1 (
.z (net48 ),
.a (net73 ) );
bw_u1_inv_1x ps_inv2 (
.z (net44 ),
.a (net58 ) );
bw_u1_soff_1x psff (
.q (net73 ),
.so (net80 ),
.ck (net54 ),
.d (net62 ),
.se (vss ),
.sd (vss ) );
bw_u1_inv_1x clk_inv (
.z (net54 ),
.a (clk ) );
bw_u1_buf_20x out_buf (
.z (serial_out ),
.a (net44 ) );
bw_u1_muxi21_1x I48 (
.z (net70 ),
.d0 (rcv_in ),
.d1 (serial_in ),
.s (out_type ) );
bw_u1_muxi21_1x I52 (
.z (net66 ),
.d0 (net52 ),
.d1 (bypass ),
.s (out_type ) );
bw_u1_inv_1x I53 (
.z (net46 ),
.a (net66 ) );
bw_u1_muxi21_1x ps_mux1 (
.z (net62 ),
.d0 (serial_in ),
.d1 (bypass_in ),
.s (out_type ) );
bw_u1_inv_1x I54 (
.z (net52 ),
.a (ps_select ) );
bw_u1_muxi21_1x ps_mux2 (
.z (net58 ),
.d0 (net50 ),
.d1 (net48 ),
.s (net46 ) );
bw_u1_inv_1x I55 (
.z (net50 ),
.a (net70 ) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void print_array(T a[], int size) { for (int i = 0; i < size; i++) cout << a[i] << ; cout << endl; } template <class T> void print_array_v(T &a) { int size = a.size(); for (int i = 0; i < size; i++) cout << a[i] << ; cout << endl; } int main() { long long int i, j, a, b, c, d, one = 0, zero = 0; cin >> a >> b >> c >> d; if (a == 0 && b == 0 && c == 0 && d == 0) { cout << 0 << endl; return 0; } one = sqrt(d * 2); if ((one * (one + 1)) == d * 2) one++; else one = -1; zero = sqrt(a * 2); if ((zero * (zero + 1)) == 2 * a) zero++; else zero = -1; if (d == 0 && b == 0 && c == 0) one = 0; if (a == 0 && b == 0 && c == 0) zero = 0; bool flag = 0; if (one == -1 || zero == -1) { cout << Impossible << endl; assert(flag == 0); return 0; } string ans; long long int s = c, zero_rem = zero, one_rem = one; for (i = 0; i < one + zero; i++) { if (s >= zero_rem) s -= zero_rem, ans += 1 , one_rem--; else ans += 0 , zero_rem--; } long long int zero_till = 0, one_till = 0; long long int zero_zero = 0, zero_one = 0, one_zero = 0, one_one = 0; for (i = 0; i < one + zero; i++) { if (ans[i] == 0 ) { zero_till++; zero_zero += zero_till - 1; one_zero += one_till; } else if (ans[i] == 1 ) { one_till++; one_one += one_till - 1; zero_one += zero_till; } else assert(1 == 0); } if (one_one != d || zero_one != b || one_zero != c || zero_zero != a) { cout << Impossible << endl; return 0; } if (!ans.size()) { cout << Impossible << endl; return 0; } if (zero_rem != 0 || one_rem != 0) { cout << Impossible << endl; return 0; } else flag = 1, cout << ans << endl; assert(ans.size() <= 1000000); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_2_V
`define SKY130_FD_SC_HDLL__MUX2I_2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2i_2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2i_2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 505; int dp[N][N]; int a[N]; int calc(int l, int r) { if (dp[l][r] != -1) return dp[l][r]; if (l > r) { return dp[l][r] = 1; } if (l == r) { return dp[l][r] = 1; } dp[l][r] = N; if (a[l] == a[r]) { dp[l][r] = min(dp[l][r], calc(l + 1, r - 1)); } for (int j = l; j < r; j++) { dp[l][r] = min(dp[l][r], calc(l, j) + calc(j + 1, r)); } return dp[l][r]; } int main() { for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) dp[i][j] = -1; int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; cout << calc(0, n - 1) << endl; }
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 23-10-2019
*/
module jt51_csr_ch(
input rst,
input clk,
input cen,
input [ 7:0] din,
input up_rl_ch,
input up_fb_ch,
input up_con_ch,
input up_kc_ch,
input up_kf_ch,
input up_ams_ch,
input up_pms_ch,
output [1:0] rl,
output [2:0] fb,
output [2:0] con,
output [6:0] kc,
output [5:0] kf,
output [1:0] ams,
output [2:0] pms
);
wire [1:0] rl_in = din[7:6];
wire [2:0] fb_in = din[5:3];
wire [2:0] con_in = din[2:0];
wire [6:0] kc_in = din[6:0];
wire [5:0] kf_in = din[7:2];
wire [1:0] ams_in = din[1:0];
wire [2:0] pms_in = din[6:4];
wire [25:0] reg_in = {
up_rl_ch ? rl_in : rl,
up_fb_ch ? fb_in : fb,
up_con_ch ? con_in : con,
up_kc_ch ? kc_in : kc,
up_kf_ch ? kf_in : kf,
up_ams_ch ? ams_in : ams,
up_pms_ch ? pms_in : pms };
wire [25:0] reg_out;
assign { rl, fb, con, kc, kf, ams, pms } = reg_out;
jt51_sh #( .width(26), .stages(8)) u_regop(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( reg_in ),
.drop ( reg_out )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> arr; int n, a; cin >> n; for (int i = 0; i < n; i++) { cin >> a; arr.push_back(a); } sort(arr.begin(), arr.end()); cout << arr[n - 1] << endl; arr.clear(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long t; long long n; long long tmp; long long gcd(long long a, long long b) { long long temp; if (a < b) { temp = a; a = b; b = temp; } while (b != 0) { temp = a % b; a = b; b = temp; } return a; } long long lcm(long long a, long long b) { long long temp_lcm; temp_lcm = a * b / gcd(a, b); return temp_lcm; } int main() { cin >> t; while (t--) { cin >> n; if (n % 2 == 0) { long long a, b; tmp = n / 2; while (tmp--) { cin >> a >> b; cout << b << << -a << ; } cout << endl; } else { long long a, b, c; tmp = (n - 2) / 2; while (tmp--) { cin >> a >> b; cout << b << << -a << ; } cin >> a >> b >> c; tmp = lcm(a, b); tmp = lcm(tmp, c); cout << tmp / a << << tmp / b << << -2 * tmp / c; cout << endl; } } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_fptoint(clock, resetn, data, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input [31:0] data;
output [31:0] result;
input valid_in, stall_in, enable;
output valid_out, stall_out;
parameter HIGH_CAPACITY = 1;
parameter HIGH_LATENCY = 0;
parameter SIGNED_INT = 1;
// Cycle 1 - Determine how much to shift data by.
reg [4:0] c1_shift;
reg [31:0] c1_integer;
reg c1_sign;
reg c1_valid;
reg [8:0] c1_exp_diff;
wire c1_stall;
wire c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(*)
if (SIGNED_INT == 1)
c1_exp_diff = 9'd157 - {1'b0, data[30:23]};
else
c1_exp_diff = 9'd158 - {1'b0, data[30:23]};
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_shift <= 5'dx;
c1_integer <= 32'dx;
c1_sign <= 1'bx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_shift <= c1_exp_diff[8] ? 5'd0 : c1_exp_diff[4:0];
if (SIGNED_INT == 1)
begin
if (c1_exp_diff[8]) // Maximum value as returned by CPU. Note that for +/-infinity it returns a maximum negative number.
c1_integer <= 32'h80000000;
else if (|c1_exp_diff[7:5])
c1_integer <= 32'd0;
else
c1_integer <= {1'b0, 1'b1, data[22:0], 7'd0};
end
else
begin
if (&data[30:23])
begin
// For unsigned values, the result of an infinity is zero on a CPU (both for positive and negative inf).
c1_integer <= 32'd0;
end
else if (c1_exp_diff[8])
begin
// For unsigned values, set the maximum value to 0xffffffff, although the behaviour outside of representable range is not specified.
c1_integer <= 32'hffffffff;
end
else if (|c1_exp_diff[7:5])
c1_integer <= 32'd00000000;
else
c1_integer <= {1'b1, data[22:0], 8'd0};
end
c1_sign <= data[31];
end
end
// Cycle 2 - shift by 24, 16, 8, or 0 to the right.
reg [2:0] c2_shift;
reg [31:0] c2_integer;
reg c2_sign;
reg c2_valid;
wire c2_stall;
wire c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_valid <= 1'b0;
c2_shift <= 3'dx;
c2_integer <= 32'dx;
c2_sign <= 1'bx;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_shift <= c1_shift[2:0];
case(c1_shift[4:3])
2'b11: c2_integer <= {24'd0, c1_integer[31:24]};
2'b10: c2_integer <= {16'd0, c1_integer[31:16]};
2'b01: c2_integer <= {8'd0, c1_integer[31:8]};
2'b00: c2_integer <= c1_integer;
endcase
c2_sign <= c1_sign;
end
end
// Cycle 3 - shift by 6, 4, 2 or 0 to the right.
reg c3_shift;
reg [31:0] c3_integer;
reg c3_sign;
reg c3_valid;
wire c3_stall;
wire c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_valid <= 1'b0;
c3_shift <= 1'dx;
c3_integer <= 32'dx;
c3_sign <= 1'bx;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
c3_shift <= c2_shift[0];
case(c2_shift[2:1])
2'b11: c3_integer <= {6'd0, c2_integer[31:6]};
2'b10: c3_integer <= {4'd0, c2_integer[31:4]};
2'b01: c3_integer <= {2'd0, c2_integer[31:2]};
2'b00: c3_integer <= c2_integer;
endcase
c3_sign <= c2_sign;
end
end
end
else
begin
always@(*)
begin
c3_valid <= c2_valid;
c3_shift <= c2_shift[0];
case(c2_shift[2:1])
2'b11: c3_integer <= {6'd0, c2_integer[31:6]};
2'b10: c3_integer <= {4'd0, c2_integer[31:4]};
2'b01: c3_integer <= {2'd0, c2_integer[31:2]};
2'b00: c3_integer <= c2_integer;
endcase
c3_sign <= c2_sign;
end
end
endgenerate
// Cycle 4 - shift by 1 or 0 to the right. Also, account for the sign in the signed mode.
reg [31:0] c4_integer;
reg c4_valid;
wire c4_stall;
wire c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
reg [31:0] c4_intermediate;
always@(*)
begin
if (c3_shift)
c4_intermediate = {1'b0, c3_integer[31:1]};
else
c4_intermediate = c3_integer;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_valid <= 1'b0;
c4_integer <= 32'dx;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
if (c3_sign)
c4_integer <= (c4_intermediate ^ 32'hffffffff) + 1'b1;
else
c4_integer <= c4_intermediate;
end
end
assign c4_stall = stall_in;
assign valid_out = c4_valid;
assign result = c4_integer;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] a;
reg [255:0] q;
reg [63:0] qq;
integer i;
always @* begin
for (i=0; i<256; i=i+1) begin
q[255-i] = a[i];
end
q[27:16] = 12'hfed;
for (i=0; i<64; i=i+1) begin
qq[63-i] = a[i];
end
qq[27:16] = 12'hfed;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x/%x %x\n", q, qq, a);
`endif
if (cyc==1) begin
a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop;
if (qq != 64'h64fe7e285fed892e) $stop;
end
if (cyc==3) begin
if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop;
if (qq != 64'h1da9cf939fed1250) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int INT_MAX_VAL = (int)0x3F3F3F3F; int INT_MIN_VAL = (int)-0x3F3F3F3F; long long LONG_MAX_VAL = (long long)0x3F3F3F3F3F3F3F3F; long long LONG_MIN_VAL = (long long)-0x3F3F3F3F3F3F3F3F; vector<long long> G[5005]; long long n; int W; int cnt[5005]; int dp[2][5005][5005]; int dfs2(int v, int p) { if (G[v].size() == 1) { cnt[v] = 1; return 1; } int res = 0; for (auto &w : G[v]) if (w != p) res += dfs2(w, v); cnt[v] = res; return res; } void dfs(int v, int p) { dp[1][v][0] = 0; if (G[v].size() == 1) { dp[0][v][1] = 0; return; } dp[0][v][0] = 0; dp[1][v][0] = 0; for (auto &w : G[v]) { if (w == p) continue; dfs(w, v); for (int i = W; i >= 0; --i) { int d0 = INT_MAX_VAL; int d1 = INT_MAX_VAL; for (int j = min(i, cnt[w]); j >= 0; --j) { d0 = min(d0, dp[0][w][j] + dp[0][v][i - j]); d0 = min(d0, dp[1][w][j] + dp[0][v][i - j] + 1); d1 = min(d1, dp[1][w][j] + dp[1][v][i - j]); d1 = min(d1, dp[0][w][j] + dp[1][v][i - j] + 1); } dp[0][v][i] = d0; dp[1][v][i] = d1; } } } int main() { cin.tie(0); ios::sync_with_stdio(false); memset(dp, 0x3F, 2 * 5005 * 5005 * sizeof(int)); cin >> n; for (long long(i) = 0LL; (i) < (n - 1); (i)++) { long long a, b; cin >> a >> b; --a, --b; G[a].push_back(b); G[b].push_back(a); } if (n == 2) { cout << 1 << n ; return 0; } int i = 0; while (G[i].size() == 1) ++i; W = dfs2(i, -1) / 2; dfs(i, -1); cout << dp[0][i][W] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct sir { int val, ind; }; sir sv[200005]; int n, m, k, v[200005], part[200005], t = 0; long long sum = 0; bool B[200005]; bool comp(sir X, sir Y) { return X.val > Y.val; } int main() { cin >> n >> m >> k; for (int i = 1; i <= n; ++i) { cin >> v[i]; sv[i].val = v[i]; sv[i].ind = i; } sort(sv + 1, sv + n + 1, comp); for (int i = 1; i <= m * k; ++i) { B[sv[i].ind] = 1; sum += sv[i].val; } int nr = 0; for (int i = 1; i <= n; ++i) { if (B[i]) nr++; if (nr == m && t < k - 1) { nr = 0; part[++t] = i; } } cout << sum << n ; for (int i = 1; i <= t; ++i) cout << part[i] << ; }
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_halfrange #(parameter HIGH_HALF=0)
(
clk,
rst,
config_valid,
config_char,
config_chained,
config_range_en,
input_valid,
input_char,
prev_matched,
this_matched,
low_smaller,
this_smaller
);
input clk;
input rst;
input config_valid;
input [7:0] config_char;
input config_chained;
input config_range_en; // only relevant if LOW_PART=0
input input_valid;
input [7:0] input_char;
input prev_matched;
input low_smaller; // only relevant if LOW_PART=0
output this_matched;
output this_smaller; // only relevant if LOW_PART=1
reg char_match;
reg [7:0] char_data;
reg is_chained;
reg is_ranged;
assign this_matched = char_match;
assign this_smaller = (HIGH_HALF==0 && input_valid==1) ? input_char>char_data-1 : 0;
always @(posedge clk)
begin
if(rst) begin
char_data <= 0;
char_match <= 0;
end
else begin
if (input_valid==1) begin
if (char_data==input_char) begin
char_match <= is_chained ? prev_matched : 1;
end
else begin
if (HIGH_HALF==1 && is_ranged==1 && char_data>input_char && low_smaller==1) begin
char_match <= 1;
end
else begin
char_match <= 0;
end
end
end
if (config_valid==1) begin
char_data <= config_char;
is_chained <= config_chained;
is_ranged <= config_range_en;
char_match <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; int p; cin >> n >> k >> p; long long ndiv2 = n / 2; long long ndiv2minus1 = n / 2 - 1; long long nminusk = n - k; for (int i = 0; i < p; i++) { long long x; scanf( %I64d , &x); printf( %c , ((((x == n) ? (n) : (1 + (x / 2) * ndiv2 - ((x - 1) / 2) * ndiv2minus1)) <= nminusk) ? ( . ) : ( X ))); } exit: return (0); }
|
module srl_init_tester #
(
parameter [255:0] PATTERN = 256'hFE1AB3FE7610D3D205D9A526C103C40F6477E986F53C53FA663A9CE45E851D30,
parameter SRL_LENGTH = 32
)
(
input wire clk,
input wire rst,
input wire ce,
output reg srl_sh,
output wire [SRL_BITS-1:0] srl_a,
output wire srl_d,
input wire srl_q,
output reg error
);
// ============================================================================
// ROM
wire [7:0] rom_adr;
wire rom_dat;
ROM #(.CONTENT(PATTERN)) rom
(
.clk (clk),
.adr (rom_adr),
.dat (rom_dat)
);
// ============================================================================
// Control
localparam SRL_BITS = $clog2(SRL_LENGTH);
// Bit counter
reg[SRL_BITS-1:0] bit_cnt;
always @(posedge clk)
if (rst)
bit_cnt <= SRL_LENGTH - 1;
else if (ce)
bit_cnt <= bit_cnt - 1;
// Data readout
assign rom_adr = bit_cnt;
// SRL32 control
assign srl_a = SRL_LENGTH - 1;
assign srl_d = srl_q;
initial srl_sh <= 1'b0;
always @(posedge clk)
srl_sh <= ce & !rst;
// Error check
initial error <= 1'b0;
always @(posedge clk)
if (rst)
error <= 1'b0;
else if(ce)
error <= rom_dat ^ srl_q;
endmodule
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
`default_nettype none
/*
* 8 bit register
*/
module reg8(
input clk,
input ce,
input [7:0] in,
output [7:0] out);
reg [8:0] register;
initial register = 8'h00;
assign out = register;
always @(posedge clk) begin
if(ce) begin
register = in;
end
end
endmodule
/*
* Divide a clock enable by a power of 2 (1,2,4 or 8)
*
* divisor:
* 00 - Divide by 1
* 01 - Divide by 2
* 10 - Divide by 4
* 11 - Divide by 8
*/
module divby1248(
input clk,
input cein,
input [1:0] divisor,
output ceout);
reg ceoutmux;
reg [2:0] counter;
initial counter = 0;
assign ceout = ceoutmux;
always @(posedge clk) begin
if(cein)
counter <= counter + 1;
end
always @(*) begin
case(divisor)
2'b00:
ceoutmux <= cein;
2'b01:
ceoutmux <= cein & counter[0];
2'b10:
ceoutmux <= cein & counter[0] & counter[1];
2'b11:
ceoutmux <= cein & counter[0] & counter[1] & counter[2];
default:
ceoutmux <= 1'bx;
endcase
end
endmodule
/*
* Fixed divide by 2
*/
module fixeddivby2(
input clk,
input cein,
output ceout);
reg q;
initial q = 0;
assign ceout = cein & q;
always @(posedge clk) begin
if(cein)
q = ~q;
end
endmodule
/*
* Fixed divide by 32 of the system clock
*/
module fixeddivby32(
input clk,
input cein,
output ceout);
reg ceoutreg = 0;
reg ceoutregs = 0;
reg [4:0] counter = 0;
assign ceout = ceoutregs;
always @(*) begin
// Generate a ce every 32 clocks
if(counter == 31)
ceoutreg <= cein;
else
ceoutreg <= 0;
end
always @(posedge clk) begin
// Resynchronize ceout
ceoutregs <= ceoutreg;
if(cein)
counter <= counter + 1;
end
endmodule
/*
* Fixed divide by 256 of the system clock
*/
module fixeddivby256(
input clk,
input cein,
output ceout);
reg ceoutreg = 0;
reg ceoutregs = 0;
reg [7:0] counter = 0;
assign ceout = ceoutregs;
always @(*) begin
// Generate a ce every 256 clocks
if(counter == 255)
ceoutreg <= cein;
else
ceoutreg <= 0;
end
always @(posedge clk) begin
// Resynchronize ceout
ceoutregs <= ceoutreg;
if(cein)
counter <= counter + 1;
end
endmodule
/*
* Watchdog timer
* Outputs a 1 clock pulse wide clock enable if watchdog timer times out
*/
module wdtimer(
input clk,
input cein,
input enable,
input wdreset,
input wdogdis,
input [7:0] wdogdivreg,
output wdtripce);
reg [7:0] counter = 0;
reg wdtripcesreg = 0;
reg wdtripcereg = 0;
reg wdogdisreg = 0;
assign wdtripce = wdtripcesreg;
always @(*) begin
if ((wdogdivreg == counter) && ~wdreset && enable && ~wdogdisreg)
wdtripcereg <= cein;
else
wdtripcereg <= 0;
end
always @(posedge clk) begin
// Resynchronize wdtripcereg to clock
wdtripcesreg <= wdtripcereg;
// Synchronize watchdog disable to clock
wdogdisreg = wdogdis;
// Only count when enable is high and reset is low, and watchdog disable is low
if(enable & ~wdreset & ~wdogdisreg) begin
if(cein)
counter <= counter + 1;
end
else
counter <= 8'h00;
end
endmodule
/*
* Watchdog register
*/
module wdregister(
input clk,
input ctrlld,
input wdtripce,
input wdogdis,
input [7:0] wrtdata,
output motorenaint,
output run0,
output run1,
output run2,
output [7:0] controlrdata);
reg motorenaintreg = 0;
reg wdtrip = 0;
reg [7:0] controlreg = 0;
reg [7:0] controlrdatareg;
assign motorenaint = motorenaintreg;
assign run0 = controlreg[0];
assign run1 = controlreg[1];
assign run2 = controlreg[2];
assign controlrdata = controlrdatareg;
always @(*) begin
// Assemble control register read value
controlrdatareg <= {wdtrip, wdogdis, 1'b0, 1'b0, controlreg[3:0]};
// Motor enable
motorenaintreg <= ~wdtrip & controlreg[3];
end
always @(posedge clk) begin
if(ctrlld)
// Load new control register value
controlreg <= wrtdata;
if(wdtripce)
// Set watchdog trip bit
wdtrip <= 1;
if(ctrlld && ( wrtdata == 8'h80))
// Clear watchdog trip bit when a 0x80 is written to the control register
wdtrip <= 0;
end
endmodule
module ledctr(
input clk,
input ce,
output ledalive);
reg [9:0] counter = 0;
assign ledalive = counter[9];
always @ (posedge clk) begin
if(ce)
counter <= counter + 1;
end
endmodule
/*
* Top level module for this file
*/
module control(
output pwmcntce0,
output pwmcntce1,
output pwmcntce2,
output filterce0,
output filterce1,
output filterce2,
output invphase0,
output invphase1,
output invphase2,
output invertpwm0,
output invertpwm1,
output invertpwm2,
output run0,
output run1,
output run2,
output motorenaint,
output ledalive,
output [7:0] controlrdata,
output [7:0] hwconfig,
output [7:0] configrdreg0,
output [7:0] configrdreg1,
output [7:0] configrdreg2,
input clk,
input cfgld0,
input cfgld1,
input cfgld2,
input ctrlld,
input wdogdivld,
input tst,
input wdogdis,
input wdreset,
input [7:0] wrtdata);
wire [7:0] configreg0;
wire [7:0] configreg1;
wire [7:0] configreg2;
wire [7:0] wdogdivreg;
wire ce32;
wire ce64;
wire ce16384;
wire cfgce0;
wire cfgce1;
wire cfgce2;
wire wdogdivregce;
wire wdtripce;
reg wdogcntce;
reg tie1 = 1;
// Assign readback busses
assign configrdreg0 = configreg0;
assign configrdreg1 = configreg1;
assign configrdreg2 = configreg2;
// Prevent config and watchdog divisor register writes when motor is enabled
assign cfgce0 = cfgld0 & ~motorenaint;
assign cfgce1 = cfgld1 & ~motorenaint;
assign cfgce2 = cfgld2 & ~motorenaint;
assign wdogdivregce = wdogdivld & ~motorenaint;
// Hardware configuration register
assign hwconfig = {1'b0,1'b0,2'b11,4'b0000};
always @(*) begin
if(tst)
wdogcntce <= ce64;
else
wdogcntce <= ce16384;
end
reg8 wdogdivregister(
.clk(clk),
.ce(wdogdivregce),
.in(wrtdata),
.out(wdogdivreg));
reg8 configregister0(
.clk(clk),
.ce(cfgce0),
.in(wrtdata),
.out(configreg0));
reg8 configregister1(
.clk(clk),
.ce(cfgce1),
.in(wrtdata),
.out(configreg1));
reg8 configregister2(
.clk(clk),
.ce(cfgce2),
.in(wrtdata),
.out(configreg2));
fixeddivby2 fdiv2(
.cein(ce32),
.clk(clk),
.ceout(ce64));
fixeddivby32 fdiv32(
.cein(tie1),
.clk(clk),
.ceout(ce32));
fixeddivby256 fdiv256(
.cein(ce64),
.clk(clk),
.ceout(ce16384));
divby1248 filterdiv0(
.clk(clk),
.cein(ce32),
.divisor(configreg0[3:2]),
.ceout(filterce0));
divby1248 pwmdiv0(
.clk(clk),
.cein(tie1),
.divisor(configreg0[1:0]),
.ceout(pwmcntce0));
divby1248 filterdiv1(
.clk(clk),
.cein(ce32),
.divisor(configreg1[3:2]),
.ceout(filterce1));
divby1248 pwmdiv1(
.clk(clk),
.cein(tie1),
.divisor(configreg1[1:0]),
.ceout(pwmcntce1));
divby1248 filterdiv2(
.clk(clk),
.cein(ce32),
.divisor(configreg2[3:2]),
.ceout(filterce2));
divby1248 pwmdiv2(
.clk(clk),
.cein(tie1),
.divisor(configreg2[1:0]),
.ceout(pwmcntce2));
wdtimer wdtimer0(
.clk(clk),
.cein(wdogcntce),
.enable(motorenaint),
.wdreset(wdreset),
.wdogdis(wdogdis),
.wdogdivreg(wdogdivreg),
.wdtripce(wdtripce));
wdregister wdreg0(
.clk(clk),
.ctrlld(ctrlld),
.wdtripce(wdtripce),
.wdogdis(wdogdis),
.wrtdata(wrtdata),
.run0(run0),
.run1(run1),
.run2(run2),
.motorenaint(motorenaint),
.controlrdata(controlrdata));
ledctr ledctr0(
.clk(clk),
.ce(ce16384),
.ledalive(ledalive));
assign invphase0 = configreg0[5];
assign invertpwm0 = configreg0[4];
assign invphase1 = configreg1[5];
assign invertpwm1 = configreg1[4];
assign invphase2 = configreg2[5];
assign invertpwm2 = configreg2[4];
endmodule
|
module uart_ctrl (
clk,
reset_,
tx,
rx,
addr,
cs,
req,
rnw,
wr_data,
rd_data,
rdy);
input clk;
input reset_;
output tx; // Transmit to host computer
input rx; // Receive from host computer
// This circuit provides software control over the RS-232 universal asynchronus
// receiver/transmitter. It exposes these software accessible registers:
//
// Transmit byte (read/write):
// [7:0] Write a value to this register to have it transmitted to the
// host computer. Has no effect if the transmitter is not ready
// at the time the register is written.
//
// Transmit ready (read):
// [0] When 1, the transmitter is ready to accept a new byte to be
// transmitted. 0 indicates the transmitter is still busy with a
// previous byte.
//
// Receive byte (read):
// [7:0] The last byte received from the host computer.
//
// Receive byte ready (read/write):
// [0] 1 indicates that the receive byte value is valid and ready to
// be consumed by software. Write any value to this register to
// clear the ready indicator.
//
// Transmit byte count high (read):
// [7:0] The high ([15:8]) bits of the number of bytes transmitted to the
// host computer.
//
// Transmit byte count low (read):
// [7:0] The low ([8:0]) bits of the number of bytes transmitted to the
// host computer.
//
// Recieve byte count high (read):
// [7:0] The high ([15:8]) bits of the number of bytes received from the
// host computer.
//
// Receive byte count low (read):
// [7:0] The low ([7:0]) bits of the number of bytes received from the
// host computer.
// Local IO bus
input [7:0] addr;
input cs;
input req;
inout rnw;
input [7:0] wr_data;
output [7:0] rd_data;
output rdy;
reg rdy;
reg [7:0] rd_data;
wire wr_enable;
wire rd_enable;
reg tx_enable;
reg [7:0] tx_data;
reg [7:0] rx_data_reg;
reg [15:0] tx_count;
reg [15:0] rx_count;
wire tx_ready;
wire [7:0] rx_data;
reg rx_ready;
// Software addressable registers
parameter TX_BYTE_REG = 8'd0;
parameter TX_BYTE_RDY_REG = 8'd1;
parameter RX_BYTE_REG = 8'd2;
parameter RX_BYTE_RDY_REG = 8'd3;
parameter TX_BYTE_CNT_HI_REG = 8'd4;
parameter TX_BYTE_CNT_LO_REG = 8'd5;
parameter RX_BYTE_CNT_HI_REG = 8'd6;
parameter RX_BYTE_CNT_LO_REG = 8'd7;
assign wr_enable = cs && !rnw && req;
assign rd_enable = cs && rnw && req;
// Transmit data register
always@ (posedge clk or negedge reset_)
if (!reset_)
tx_data <= 8'd0;
else if (wr_enable && addr == TX_BYTE_REG)
tx_data <= wr_data;
// Transmit enable generation
always@ (posedge clk or negedge reset_)
if (!reset_)
tx_enable <= 1'b0;
else if (wr_enable && addr == TX_BYTE_REG)
tx_enable <= 1'b1;
else
tx_enable <= 1'b0;
// Receive data register
always@ (posedge clk or negedge reset_)
if (!reset_)
rx_data_reg <= 8'h00;
else if (rx_enable)
rx_data_reg <= rx_data;
// Receive ready readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rx_ready <= 1'b0;
else if (wr_enable && addr == RX_BYTE_RDY_REG)
rx_ready <= 1'b0;
else if (rx_enable)
rx_ready <= 1'b1;
// Transmit byte count
always@ (posedge clk or negedge reset_)
if (!reset_)
tx_count <= 16'd0;
else if (tx_enable)
tx_count <= tx_count + 16'd1;
// Receive byte count
always@ (posedge clk or negedge reset_)
if (!reset_)
rx_count <= 16'd0;
else if (rx_enable)
rx_count <= rx_count + 16'd1;
// Register readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rd_data <= 8'd0;
else if (rd_enable)
rd_data <= (addr == TX_BYTE_RDY_REG) ? {7'd0, tx_ready} :
(addr == TX_BYTE_REG) ? tx_data :
(addr == RX_BYTE_REG) ? rx_data_reg :
(addr == RX_BYTE_RDY_REG) ? {7'd0, rx_ready} :
(addr == TX_BYTE_CNT_HI_REG) ? tx_count[15:8] :
(addr == TX_BYTE_CNT_LO_REG) ? tx_count[7:0] :
(addr == RX_BYTE_CNT_HI_REG) ? rx_count[15:8] :
(addr == RX_BYTE_CNT_LO_REG) ? rx_count[7:0] :
8'd0;
// Module ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
rdy <= 1'b0;
else
rdy <= req;
// UART instantiation
uart uart(
.clk32(clk),
.reset_(reset_),
.rx(rx),
.tx(tx),
.txdata(tx_data),
.rxdata(rx_data),
.rx_enable(rx_enable),
.tx_enable(tx_enable),
.tx_ready(tx_ready)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_1 (
Din,
Dout
);
input wire [39 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(40),
.DIN_FROM(34),
.DIN_TO(19)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const int INF = 1000 * 1000 * 1000 + 7; const long long LINF = INF * (long long)INF; const int MAX = 1000 * 100 + 47; long long A[MAX]; long long P[MAX]; long long Q[MAX]; long long R[MAX]; int main() { int n; long long p, q, r; cin >> n >> p >> q >> r; for (int i = (0); i < (n); i++) cin >> A[i]; for (int i = (0); i < (n); i++) { P[i] = p * A[i]; if (i) P[i] = max(P[i], P[i - 1]); Q[i] = P[i] + q * A[i]; if (i) Q[i] = max(Q[i], Q[i - 1]); R[i] = Q[i] + r * A[i]; if (i) R[i] = max(R[i], R[i - 1]); } cout << R[n - 1] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 20; const int mod = 1e9 + 7; long double a[N]; int n, k; long double dp[1 << N], out[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> k; int zeros = 0; for (int i = 0; i < n; i++) cin >> a[i], zeros += fabs(a[i] < (1e-7)); k = min(k, n - zeros); dp[0] = 1.0; for (int i = 0; i < 1 << n; i++) { double tmp = 1.0; for (int j = 0; j < n; j++) if (i >> j & 1) tmp -= a[j]; if (__builtin_popcount(i) == k) for (int j = 0; j < n; j++) if (i >> j & 1) out[j] += dp[i]; if (tmp == 0.0) continue; cout << fixed << setprecision(6); for (int j = 0; j < n; j++) if (!(i >> j & 1)) dp[i | 1 << j] += a[j] * dp[i] / tmp; } for (int i = 0; i < n; i++) cout << out[i] << ; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_adrgen #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [10:0] dx_c,
input [10:0] dy_c,
input [16:0] tx_c,
input [16:0] ty_c,
input [fml_depth-1-1:0] dst_fbuf, /* in 16-bit words */
input [10:0] dst_hres,
input [fml_depth-1-1:0] tex_fbuf, /* in 16-bit words */
input [10:0] tex_hres,
output pipe_stb_o,
input pipe_ack_i,
output [fml_depth-1-1:0] dadr, /* in 16-bit words */
output [fml_depth-1-1:0] tadra,
output [fml_depth-1-1:0] tadrb,
output [fml_depth-1-1:0] tadrc,
output [fml_depth-1-1:0] tadrd,
output [5:0] x_frac,
output [5:0] y_frac
);
/* Arithmetic pipeline. Enable signal is shared to ease usage of hard macros. */
wire pipe_en;
reg valid_1;
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] tadra_1;
reg [5:0] x_frac_1;
reg [5:0] y_frac_1;
reg valid_2;
reg [fml_depth-1-1:0] dadr_2;
reg [fml_depth-1-1:0] tadra_2;
reg [5:0] x_frac_2;
reg [5:0] y_frac_2;
reg valid_3;
reg [fml_depth-1-1:0] dadr_3;
reg [fml_depth-1-1:0] tadra_3;
reg [fml_depth-1-1:0] tadrb_3;
reg [fml_depth-1-1:0] tadrc_3;
reg [fml_depth-1-1:0] tadrd_3;
reg [5:0] x_frac_3;
reg [5:0] y_frac_3;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
end else if(pipe_en) begin
valid_1 <= pipe_stb_i;
dadr_1 <= dst_fbuf + dst_hres*dy_c + dx_c;
tadra_1 <= tex_fbuf + tex_hres*ty_c[16:6] + tx_c[16:6];
x_frac_1 <= tx_c[5:0];
y_frac_1 <= ty_c[5:0];
valid_2 <= valid_1;
dadr_2 <= dadr_1;
tadra_2 <= tadra_1;
x_frac_2 <= x_frac_1;
y_frac_2 <= y_frac_1;
valid_3 <= valid_2;
dadr_3 <= dadr_2;
tadra_3 <= tadra_2;
tadrb_3 <= tadra_2 + 1'd1;
tadrc_3 <= tadra_2 + tex_hres;
tadrd_3 <= tadra_2 + tex_hres + 1'd1;
x_frac_3 <= x_frac_2;
y_frac_3 <= y_frac_2;
end
end
/* Glue logic */
assign pipe_stb_o = valid_3;
assign dadr = dadr_3;
assign tadra = tadra_3;
assign tadrb = tadrb_3;
assign tadrc = tadrc_3;
assign tadrd = tadrd_3;
assign x_frac = x_frac_3;
assign y_frac = y_frac_3;
assign pipe_en = ~valid_3 | pipe_ack_i;
assign pipe_ack_o = ~valid_3 | pipe_ack_i;
assign busy = valid_1 | valid_2 | valid_3;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, a[100001], t, l, r; int _gcd[262144][19], _min[262144][19], _num[262144][19]; int gcd(int x, int y) { if (x < y) swap(x, y); if (y == 0) return x; int r = x % y; return gcd(y, r); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { _min[i][0] = a[i]; _gcd[i][0] = a[i]; _num[i][0] = 1; } for (int k = 1; k <= 18; k++) { for (int i = 1; i <= n; i++) { if (_min[i][k - 1] == _min[i + (1 << (k - 1))][k - 1]) { _min[i][k] = _min[i][k - 1]; _num[i][k] = _num[i][k - 1] + _num[i + (1 << (k - 1))][k - 1]; } else if (_min[i][k - 1] < _min[i + (1 << (k - 1))][k - 1]) { _min[i][k] = _min[i][k - 1]; _num[i][k] = _num[i][k - 1]; } else { _min[i][k] = _min[i + (1 << (k - 1))][k - 1]; _num[i][k] = _num[i + (1 << (k - 1))][k - 1]; } } } for (int k = 1; k <= 18; k++) for (int i = 1; i <= n; i++) _gcd[i][k] = gcd(_gcd[i][k - 1], _gcd[i + (1 << (k - 1))][k - 1]); scanf( %d , &t); for (int j = 1; j <= t; j++) { scanf( %d , &l); scanf( %d , &r); int tmp = r - l + 1; int k = log2(r - l + 1); int GCD = gcd(_gcd[l][k], _gcd[r - (1 << k) + 1][k]); int ans = 0; int pos = l; for (int i = 0; i <= 20; i++) { if ((tmp & (1 << i)) > 0) { if (_min[pos][i] == GCD) ans += _num[pos][i]; pos += (1 << i); } } printf( %d n , tmp - ans); } }
|
// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: four_digit_counter_enable.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module four_bit_counter_enable (
aclr,
clock,
cnt_en,
q);
input aclr;
input clock;
input cnt_en;
output [3:0] q;
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
lpm_counter LPM_COUNTER_component (
.aclr (aclr),
.clock (clock),
.cnt_en (cnt_en),
.q (sub_wire0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.clk_en (1'b1),
.cout (),
.data ({4{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "4"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's instruction fetch ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// PC, instruction fetch, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_if.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered and bugs fixed.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_if(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
// Internal i/f
if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,
if_stall, no_more_dslot, genpc_refetch, rfe,
except_itlbmiss, except_immufault, except_ibuserr
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Internal i/f
//
input if_freeze;
output [31:0] if_insn;
output [31:0] if_pc;
input if_flushpipe;
output saving_if_insn;
output if_stall;
input no_more_dslot;
output genpc_refetch;
input rfe;
output except_itlbmiss;
output except_immufault;
output except_ibuserr;
//
// Internal wires and regs
//
wire save_insn;
wire if_bypass;
reg if_bypass_reg;
reg [31:0] insn_saved;
reg [31:0] addr_saved;
reg [2:0] err_saved;
reg saved;
assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved;
assign saving_if_insn = !if_flushpipe & save_insn;
//
// IF bypass
//
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
if_bypass_reg <= 1'b0;
else
if_bypass_reg <= if_bypass;
//
// IF stage insn
//
assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
//
// Flag for saved insn/address
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
saved <= 1'b0;
else if (if_flushpipe)
saved <= 1'b0;
else if (save_insn)
saved <= 1'b1;
else if (!if_freeze)
saved <= 1'b0;
//
// Store fetched instruction
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
else if (if_flushpipe)
insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
else if (save_insn)
insn_saved <= icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
else if (!if_freeze)
insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
//
// Store fetched instruction's address
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
addr_saved <= 32'h00000000;
else if (if_flushpipe)
addr_saved <= 32'h00000000;
else if (save_insn)
addr_saved <= {icpu_adr_i[31:2], 2'b00};
else if (!if_freeze)
addr_saved <= {icpu_adr_i[31:2], 2'b00};
//
// Store fetched instruction's error tags
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
err_saved <= 3'b000;
else if (if_flushpipe)
err_saved <= 3'b000;
else if (save_insn) begin
err_saved[0] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
err_saved[1] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
err_saved[2] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
end
else if (!if_freeze)
err_saved <= 3'b000;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int Q; cin >> Q; while (Q--) { long long n, a, b, ans; cin >> n >> a >> b; double x = b / 2.0; if (x > a) { ans = a * n; cout << ans << endl; } else { if (n % 2 == 0) { ans = n / 2 * b; cout << ans << endl; } else { ans = (n - 1) / 2 * b + a; cout << ans << endl; } } } }
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : <module_name>
-- Author : mammenx
-- Associated modules:
-- Function :
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module <module_name> (
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
//----------------------- Internal Wire Declarations ----------------------
//----------------------- FSM Parameters --------------------------------------
//only for FSM state vector representation
parameter [?:0] // synopsys enum fsm_pstate
IDLE = ,
//----------------------- FSM Register Declarations ------------------
reg [?:0] // synopsys enum fsm_pstate
fsm_pstate, next_state;
//----------------------- FSM String Declarations ------------------
//synthesis translate_off
reg [8*?:0] state_name;//"state name" is user defined
//synthesis translate_on
//----------------------- FSM Debugging Logic Declarations ------------------
//synthesis translate_off
always @ (fsm_pstate)
begin
case (fsm_pstate)
<IDLE> : state_name = "IDLE";
<state2> : state_name = "state2";
.
.
.
<default> : state_name = "default";
endcase
end
//synthesis translate_on
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
//code should be <=200 lines
/* comments for assign statements
*/
//assign statements
/* comments for combinatory logic
Asynchronous part of FSM
*/
/* comments for sequential logic
*/
//<sequential logic>;
endmodule // <module_name>
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; string s; long long ans; long long mem[N][5]; int n; long long dp(int i, int last) { if (i == n) { if (last == 2 || last == 4) return 0; return 1; } if (mem[i][last] != -1) return mem[i][last]; long long p = 0; if (last == 0) { if (s[i] == 2 || s[i] == * ) return 0; if (s[i] == 1 ) p += dp(i + 1, 4); else if (s[i] == 0 ) p += dp(i + 1, 0); else { p += dp(i + 1, 4); p += dp(i + 1, 0); } } else if (last == 1) { if (s[i] == 2 || s[i] == * ) return 0; if (s[i] == 1 ) p += dp(i + 1, 4); else if (s[i] == 0 ) p += dp(i + 1, 0); else { p += dp(i + 1, 4); p += dp(i + 1, 0); } } else if (last == 4) { if (s[i] == * || s[i] == ? ) p += dp(i + 1, 3); else return 0; } else if (last == 3) { if (s[i] == 0 ) return 0; else if (s[i] == * ) p += dp(i + 1, 3); else if (s[i] == 1 ) p += dp(i + 1, 1); else if (s[i] == 2 ) p += dp(i + 1, 2); else { p += dp(i + 1, 3); p += dp(i + 1, 1); p += dp(i + 1, 2); } } else { if (s[i] == * || s[i] == ? ) p += dp(i + 1, 3); else return 0; } return mem[i][last] = p % 1000000007; } int main() { cin >> s; n = s.length(); memset(mem, -1, sizeof mem); if (s[0] == ? ) { ans += dp(1, 0); ans += dp(1, 4); ans += dp(1, 3); } else { if (s[0] == 1 ) ans += dp(1, 4); else if (s[0] == 0 ) ans += dp(1, 0); else if (s[0] == * ) ans += dp(1, 3); else ans = 0; } cout << ans % 1000000007; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
/**
* Import the design modules for other design submodules
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "acs.v"
`include "bmu.v"
`include "pmsm.v"
`include "spd.v"
*/
// Design of the Viterbi decoder
module viterbi_decoder (d, cx, clk, reset);
// Output signals for the design module
// Decoded output signal from the Viterbi decoder
output d;
// Input signals for the design module
// Received encoded signal that may have corrupted bits
input [1:0] cx;
// Input clock signal for the Viterbi decoder
input clk;
// Reset signal for the Viterbi decoder
input reset;
// Declare "reg" signals... that will be assigned values
// reg d;
// Set of branch metric outputs from the BMU
// reg [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
// reg [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
// reg d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
// reg [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
// reg [3:0] p_m0, p_m1, p_m2, p_m3;
// Declare "wire" signals...
wire d;
// Set of branch metric outputs from the BMU
wire [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
wire [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
wire d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
wire [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
wire [3:0] p_m0, p_m1, p_m2, p_m3;
// Defining constants: parameter [name_of_constant] = value;
/*******************************************************
*
* Connecting the modules of the Viterbi decoder together
* That is, link the following modules together:
* # Branch Metric calculation Unit (BMU)
* # Add-Compare-Select unit (ACS)
* # Survivor Path Decoding Unit (SPDU)
* # Survivor Path Decoder (SPD)
* # Path Metric State Memory (PMSM)
*
* Note that the SPD module includes the demux (2-to-4
* DEMUX/demultiplexer) and selector.
*
* The selector chooses the smallest path metric to
* create the control signal to select the smallest path
*
* In addition, note that the SPD module includes 15 SPDU
* units.
*
*
*
* Basic architecture of the Viterbi decoder:
*
* (1) (4) (1) (1)
* BMU->ACS->PMSM->SPD
* v ^ V ^
* | | | |
* | ----- |
* | |
* ------------|
*
*******************************************************
*/
// =====================================================
/**
* Instantiate the BMU to receive inputs for the Viterbi
* decoder, and produce outputs for the ACS units
*
* There is only one BMU for the Viterbi decoder
*/
bmu brch_met (cx[0], cx[1],
brch_met0,brch_met1,brch_met2,brch_met3,
brch_met4,brch_met5,brch_met6,brch_met7);
// =====================================================
/**
* Instantiate the 4 ACS units to receive inputs from
* the BMU and the PMSM, and produce outputs for the SPD
* and the PMSM
*
* The assignment of branch and path metrics to each
* state is based on the Trellis diagrams for different
* inputs for the input code(s), cx or cin
*
* See the BMU module for the interconnections.
*/
// Instantiate the 1st ACS unit
add_compare_select acs0 (n_pm0, d0,
p_m0, brch_met0, p_m1, brch_met2);
// Instantiate the 2nd ACS unit
add_compare_select acs1 (n_pm1, d1,
p_m2, brch_met4, p_m3, brch_met6);
// Instantiate the 3rd ACS unit
add_compare_select acs2 (n_pm2, d2,
p_m0, brch_met1, p_m1, brch_met3);
// Instantiate the 4th ACS unit
add_compare_select acs3 (n_pm3, d3,
p_m2, brch_met5, p_m3, brch_met7);
// =====================================================
/**
* Instantiate the PMSM that contains a set of 4
* registers, and circuitry to normalize the path metrics
* by subtracting the smallest path metric from all of
* the path metrics
*
* There is only one PMSM for the Viterbi decoder
*/
pmsm path_metric_sm (n_pm0, n_pm1, n_pm2, n_pm3,
p_m0, p_m1, p_m2, p_m3, clk, reset);
// =====================================================
/**
* Instantiate the SPD that uses the current path metric
* and the decision bits to determine the optimal path
* for Viterbi decoding using dynamic programming
*
* There is only one SPD for the Viterbi decoder
*/
spd survivor_path_dec (d0, d1, d2, d3, p_m0, p_m1, p_m2, p_m3,
d, clk, reset);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int i, n, f = 0; cin >> n; vector<int> v(n); vector<int> use(n + 1, 0); for (i = 0; i < n; i++) { cin >> v[i]; if (v[i] < (i + 1)) { f = 1; } } if (f) { cout << -1 << endl; continue; } vector<int> a(n, 0); for (i = 0; i < n; i++) { if (!use[v[i]]) { a[i] = v[i]; use[v[i]] = 1; } } queue<int> q; for (i = 1; i <= n; i++) { if (!use[i]) { q.push(i); } } for (i = 0; i < n; i++) { if (a[i] != 0) { cout << a[i] << ; } else { cout << q.front() << ; q.pop(); } } cout << endl; } }
|
#include <bits/stdc++.h> const int maxn = 1e5 + 10; using namespace std; long long gcd(long long p, long long q) { return q == 0 ? p : gcd(q, p % q); } long long qpow(long long p, long long q) { long long f = 1; while (q) { if (q & 1) f = f * p; p = p * p; q >>= 1; } return f; } inline long long read() { long long x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m, k, t, c[21][21], vis[21][21], num[4]; struct node { int cnt, id; bool operator<(const node& p) const { return cnt > p.cnt; } } ca[25]; bool flag; bool solve(int a, int b) { int d[21][21]; int i, j; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) d[i][j] = c[i][j]; for (i = 1; i <= n; i++) swap(d[i][a], d[i][b]); for (i = 1; i <= n; i++) { int now = 0; for (j = 1; j <= m; j++) if (d[i][j] != j) now++; if (now > 2) return false; } return true; } int main() { int i, j; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) ca[i].id = i; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { scanf( %d , &c[i][j]); if (c[i][j] != j) ca[i].cnt++; } sort(ca + 1, ca + n + 1); if (ca[1].cnt <= 2) puts( YES ); else if (ca[1].cnt > 4) puts( NO ); else { j = 0; int pos = ca[1].id; for (i = 1; i <= m; i++) if (c[pos][i] != i) num[j++] = i; for (i = 0; i <= 3; i++) for (j = i + 1; j <= 3; j++) { if (solve(num[i], num[j])) return 0 * puts( YES ); } puts( NO ); } return 0; }
|
`timescale 1ns/10ps
module system_acl_iface_acl_kernel_clk_kernel_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked,
// interface 'reconfig_to_pll'
input wire [63:0] reconfig_to_pll,
// interface 'reconfig_from_pll'
output wire [63:0] reconfig_from_pll
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.pll_fractional_cout(24),
.pll_dsm_out_sel("1st_order"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("140.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("280.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("Cyclone V"),
.pll_subtype("Reconfigurable"),
.m_cnt_hi_div(6),
.m_cnt_lo_div(5),
.n_cnt_hi_div(256),
.n_cnt_lo_div(256),
.m_cnt_bypass_en("false"),
.n_cnt_bypass_en("true"),
.m_cnt_odd_div_duty_en("true"),
.n_cnt_odd_div_duty_en("false"),
.c_cnt_hi_div0(2),
.c_cnt_lo_div0(2),
.c_cnt_prst0(1),
.c_cnt_ph_mux_prst0(0),
.c_cnt_in_src0("ph_mux_clk"),
.c_cnt_bypass_en0("false"),
.c_cnt_odd_div_duty_en0("false"),
.c_cnt_hi_div1(1),
.c_cnt_lo_div1(1),
.c_cnt_prst1(1),
.c_cnt_ph_mux_prst1(0),
.c_cnt_in_src1("ph_mux_clk"),
.c_cnt_bypass_en1("false"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_hi_div2(1),
.c_cnt_lo_div2(1),
.c_cnt_prst2(1),
.c_cnt_ph_mux_prst2(0),
.c_cnt_in_src2("ph_mux_clk"),
.c_cnt_bypass_en2("true"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_hi_div3(1),
.c_cnt_lo_div3(1),
.c_cnt_prst3(1),
.c_cnt_ph_mux_prst3(0),
.c_cnt_in_src3("ph_mux_clk"),
.c_cnt_bypass_en3("true"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_hi_div4(1),
.c_cnt_lo_div4(1),
.c_cnt_prst4(1),
.c_cnt_ph_mux_prst4(0),
.c_cnt_in_src4("ph_mux_clk"),
.c_cnt_bypass_en4("true"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_hi_div5(1),
.c_cnt_lo_div5(1),
.c_cnt_prst5(1),
.c_cnt_ph_mux_prst5(0),
.c_cnt_in_src5("ph_mux_clk"),
.c_cnt_bypass_en5("true"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_hi_div6(1),
.c_cnt_lo_div6(1),
.c_cnt_prst6(1),
.c_cnt_ph_mux_prst6(0),
.c_cnt_in_src6("ph_mux_clk"),
.c_cnt_bypass_en6("true"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_hi_div7(1),
.c_cnt_lo_div7(1),
.c_cnt_prst7(1),
.c_cnt_ph_mux_prst7(0),
.c_cnt_in_src7("ph_mux_clk"),
.c_cnt_bypass_en7("true"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_hi_div8(1),
.c_cnt_lo_div8(1),
.c_cnt_prst8(1),
.c_cnt_ph_mux_prst8(0),
.c_cnt_in_src8("ph_mux_clk"),
.c_cnt_bypass_en8("true"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_hi_div9(1),
.c_cnt_lo_div9(1),
.c_cnt_prst9(1),
.c_cnt_ph_mux_prst9(0),
.c_cnt_in_src9("ph_mux_clk"),
.c_cnt_bypass_en9("true"),
.c_cnt_odd_div_duty_en9("false"),
.c_cnt_hi_div10(1),
.c_cnt_lo_div10(1),
.c_cnt_prst10(1),
.c_cnt_ph_mux_prst10(0),
.c_cnt_in_src10("ph_mux_clk"),
.c_cnt_bypass_en10("true"),
.c_cnt_odd_div_duty_en10("false"),
.c_cnt_hi_div11(1),
.c_cnt_lo_div11(1),
.c_cnt_prst11(1),
.c_cnt_ph_mux_prst11(0),
.c_cnt_in_src11("ph_mux_clk"),
.c_cnt_bypass_en11("true"),
.c_cnt_odd_div_duty_en11("false"),
.c_cnt_hi_div12(1),
.c_cnt_lo_div12(1),
.c_cnt_prst12(1),
.c_cnt_ph_mux_prst12(0),
.c_cnt_in_src12("ph_mux_clk"),
.c_cnt_bypass_en12("true"),
.c_cnt_odd_div_duty_en12("false"),
.c_cnt_hi_div13(1),
.c_cnt_lo_div13(1),
.c_cnt_prst13(1),
.c_cnt_ph_mux_prst13(0),
.c_cnt_in_src13("ph_mux_clk"),
.c_cnt_bypass_en13("true"),
.c_cnt_odd_div_duty_en13("false"),
.c_cnt_hi_div14(1),
.c_cnt_lo_div14(1),
.c_cnt_prst14(1),
.c_cnt_ph_mux_prst14(0),
.c_cnt_in_src14("ph_mux_clk"),
.c_cnt_bypass_en14("true"),
.c_cnt_odd_div_duty_en14("false"),
.c_cnt_hi_div15(1),
.c_cnt_lo_div15(1),
.c_cnt_prst15(1),
.c_cnt_ph_mux_prst15(0),
.c_cnt_in_src15("ph_mux_clk"),
.c_cnt_bypass_en15("true"),
.c_cnt_odd_div_duty_en15("false"),
.c_cnt_hi_div16(1),
.c_cnt_lo_div16(1),
.c_cnt_prst16(1),
.c_cnt_ph_mux_prst16(0),
.c_cnt_in_src16("ph_mux_clk"),
.c_cnt_bypass_en16("true"),
.c_cnt_odd_div_duty_en16("false"),
.c_cnt_hi_div17(1),
.c_cnt_lo_div17(1),
.c_cnt_prst17(1),
.c_cnt_ph_mux_prst17(0),
.c_cnt_in_src17("ph_mux_clk"),
.c_cnt_bypass_en17("true"),
.c_cnt_odd_div_duty_en17("false"),
.pll_vco_div(2),
.pll_cp_current(20),
.pll_bwctrl(4000),
.pll_output_clk_frequency("559.999999 MHz"),
.pll_fractional_division(""),
.mimic_fbclk_type("none"),
.pll_fbclk_mux_1("glb"),
.pll_fbclk_mux_2("m_cnt"),
.pll_m_cnt_in_src("ph_mux_clk"),
.pll_slf_rst("false")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.reconfig_to_pll (reconfig_to_pll),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk),
.reconfig_from_pll (reconfig_from_pll)
);
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____6.144______0.000______50.0______571.196____386.048
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pb_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 4}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:45 EST 2016
//
// Method conflict info:
// Method: select
// Conflict-free: select
// Sequenced before: next
//
// Method: next
// Sequenced after: select
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// select O 5
// CLK I 1 clock
// RST_N I 1 reset
// select_requests I 5
// EN_next I 1
//
// Combinational paths from inputs to outputs:
// select_requests -> select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkOutputArbiter(CLK,
RST_N,
select_requests,
select,
EN_next);
input CLK;
input RST_N;
// value method select
input [4 : 0] select_requests;
output [4 : 0] select;
// action method next
input EN_next;
// signals for module outputs
wire [4 : 0] select;
// register arb_token
reg [4 : 0] arb_token;
wire [4 : 0] arb_token$D_IN;
wire arb_token$EN;
// remaining internal signals
wire [1 : 0] ab__h1657,
ab__h1672,
ab__h1687,
ab__h1702,
ab__h1717,
ab__h3098,
ab__h3545,
ab__h3938,
ab__h4282,
ab__h4577;
wire NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
ab_BIT_0___h2269,
ab_BIT_0___h2376,
ab_BIT_0___h2483,
ab_BIT_0___h2590,
ab_BIT_0___h3169,
ab_BIT_0___h3305,
ab_BIT_0___h3698,
ab_BIT_0___h4042,
ab_BIT_0___h4337,
arb_token_BIT_0___h2267,
arb_token_BIT_1___h2374,
arb_token_BIT_2___h2481,
arb_token_BIT_3___h2588,
arb_token_BIT_4___h2695;
// value method select
assign select =
{ ab__h1657[1] || ab__h3098[1],
!ab__h1657[1] && !ab__h3098[1] &&
(ab__h1672[1] || ab__h3545[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h1657[1] && !ab__h3098[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// register arb_token
assign arb_token$D_IN = { arb_token[0], arb_token[4:1] } ;
assign arb_token$EN = EN_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h1717));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h2269),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h1702));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h2376),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h1687));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h2483),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h1672));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h2590),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h1657));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h3169),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h4577));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h4337),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h4282));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h4042),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h3938));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h3698),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h3545));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h3305),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h3098));
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
(ab__h1687[1] || ab__h3938[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h1687[1] && !ab__h3938[1] && !ab__h1702[1] &&
!ab__h4282[1] &&
(ab__h1717[1] || ab__h4577[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h1672[1] && !ab__h3545[1] && !ab__h1687[1] &&
!ab__h3938[1] &&
(ab__h1702[1] || ab__h4282[1]) ;
assign ab_BIT_0___h2269 = ab__h1717[0] ;
assign ab_BIT_0___h2376 = ab__h1702[0] ;
assign ab_BIT_0___h2483 = ab__h1687[0] ;
assign ab_BIT_0___h2590 = ab__h1672[0] ;
assign ab_BIT_0___h3169 = ab__h1657[0] ;
assign ab_BIT_0___h3305 = ab__h3545[0] ;
assign ab_BIT_0___h3698 = ab__h3938[0] ;
assign ab_BIT_0___h4042 = ab__h4282[0] ;
assign ab_BIT_0___h4337 = ab__h4577[0] ;
assign arb_token_BIT_0___h2267 = arb_token[0] ;
assign arb_token_BIT_1___h2374 = arb_token[1] ;
assign arb_token_BIT_2___h2481 = arb_token[2] ;
assign arb_token_BIT_3___h2588 = arb_token[3] ;
assign arb_token_BIT_4___h2695 = arb_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
arb_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
end
else
begin
if (arb_token$EN) arb_token <= `BSV_ASSIGNMENT_DELAY arb_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
arb_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkOutputArbiter
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:43:25 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xbar_1/system_xbar_1_stub.v
// Design : system_xbar_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module system_xbar_1(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[447:0],m_axi_awprot[41:0],m_axi_awvalid[13:0],m_axi_awready[13:0],m_axi_wdata[447:0],m_axi_wstrb[55:0],m_axi_wvalid[13:0],m_axi_wready[13:0],m_axi_bresp[27:0],m_axi_bvalid[13:0],m_axi_bready[13:0],m_axi_araddr[447:0],m_axi_arprot[41:0],m_axi_arvalid[13:0],m_axi_arready[13:0],m_axi_rdata[447:0],m_axi_rresp[27:0],m_axi_rvalid[13:0],m_axi_rready[13:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [447:0]m_axi_awaddr;
output [41:0]m_axi_awprot;
output [13:0]m_axi_awvalid;
input [13:0]m_axi_awready;
output [447:0]m_axi_wdata;
output [55:0]m_axi_wstrb;
output [13:0]m_axi_wvalid;
input [13:0]m_axi_wready;
input [27:0]m_axi_bresp;
input [13:0]m_axi_bvalid;
output [13:0]m_axi_bready;
output [447:0]m_axi_araddr;
output [41:0]m_axi_arprot;
output [13:0]m_axi_arvalid;
input [13:0]m_axi_arready;
input [447:0]m_axi_rdata;
input [27:0]m_axi_rresp;
input [13:0]m_axi_rvalid;
output [13:0]m_axi_rready;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRTN_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int good = 0; int bad = 0; cin >> s; for (int i = 0; i < s.length(); i++) { if (s.at(i) == a ) good++; else bad++; } if (good > bad) cout << s.length(); else cout << s.length() - (bad - good) - 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; int PASSED_POINT = 0; void Duxar() {} void read_int(int &value) { int sign = 1; char ch; value = 0; while (!isdigit(ch = getchar())) { (ch == - ) && (sign = -1); } do { value = value * 10 + (ch - 0 ); } while (isdigit(ch = getchar())); value *= sign; } int N, M; vector<int> hero, state; vector<pair<int, int> > actionTeam; int nr_bits(int x) { int ans = 0; while (x) { ans += (x & 1); x >>= 1; } return ans; } int main() { int i, mask, act; string s; read_int(N); hero.resize(N); for (i = 0; i < N; ++i) { read_int(hero[i]); } sort((hero).rbegin(), (hero).rend()); read_int(M); state.resize((1 << M) - 1); actionTeam.resize(M); for (i = 0; i < M; ++i) { cin >> s >> actionTeam[i].second; actionTeam[i].first = 0; if (s[0] == p ) actionTeam[i].first = 1; } state[(1 << M) - 1] = 0; for (mask = (1 << M) - 2; mask >= 0; --mask) { act = nr_bits(mask); if (actionTeam[act].second == 1) { state[mask] = -1000000007; for (i = 0; i < M; ++i) { if ((mask & (1 << i)) == 0) { state[mask] = max(state[mask], state[mask | (1 << i)] + actionTeam[act].first * hero[i]); } } } else { state[mask] = 1000000007; for (i = 0; i < M; ++i) { if ((mask & (1 << i)) == 0) { state[mask] = min(state[mask], state[mask | (1 << i)] - actionTeam[act].first * hero[i]); } } } } printf( %d n , state[0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mp[1005][1005]; long long n, a, b; void output() { for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { if (i == j) printf( 0 ); else printf( %lld , a < b ? !mp[i][j] : mp[i][j]); } printf( n ); } } int main() { scanf( %lld%lld%lld , &n, &a, &b); long long root = 2; if ((a != 1 && b != 1)) { printf( NO n ); return 0; } if (n == 2 && a == 1 && b == 1) { printf( NO n ); return 0; } if (n == 3 && a == 1 && b == 1) { printf( NO n ); return 0; } printf( YES n ); if (a == 1 && b == 1) for (long long i = 1; i < n; i++) mp[i][i + 1] = mp[i + 1][i] = true; else for (long long i = 0; i < n - max(a, b); i++, root++) mp[1][root] = mp[root][1] = true; output(); }
|
/*
* Author : Tom Stanway-Mayers
* Description : RV32I Compressed Instruction Expander
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_rv32ic_expander
(
input wire [15:0] ins_i,
output reg ins_rvc_o,
output reg ins_err_o,
output reg [31:0] ins_o
);
//--------------------------------------------------------------
// rv32ic expander
wire [1:0] op;
wire [2:0] funct3;
//--------------------------------------------------------------
// rv32ic expander
//
assign op = ins_i[1:0];
assign funct3 = ins_i[15:13];
//
always @ (*) begin
ins_rvc_o = 1'b1;
ins_err_o = 1'b0;
//
ins_o = 32'b0; // NOTE: don't care
//
case (op)
2'b00 : begin
case (funct3)
3'b000 : begin // c.add14spn / c.illegal
if (ins_i[12:2] == 11'b0) begin // c.illegal
ins_err_o = 1'b1;
end else if (ins_i[12:5] != 8'b0) begin // c.add14spn
ins_o = { 2'b0, ins_i[10:7], ins_i[12:11], ins_i[5], ins_i[6], 2'b0, 5'd2, 3'b000, 2'b01, ins_i[4:2], 7'b0010011 };
end else begin
ins_err_o = 1'b1;
end
end
3'b010 : begin // c.lw
ins_o = { 5'b0, ins_i[5], ins_i[12:10], ins_i[6], 2'b0, 2'b01, ins_i[9:7], 3'b010, 2'b01, ins_i[4:2], 7'b0000011 };
end
3'b110 : begin // c.sw
ins_o = { 5'b0, ins_i[5], ins_i[12], 2'b01, ins_i[4:2], 2'b01, ins_i[9:7], 3'b010, ins_i[11:10], ins_i[6], 2'b0, 7'b0100011 };
end
default : begin
ins_err_o = 1'b1;
end
endcase
end
2'b01 : begin
case (funct3)
3'b000 : begin // c.addi / c.nop
if (ins_i[12:2] == 11'b0) begin // c.nop
ins_o = { 25'b0, 7'b0010011 }; // nop
end else if (!(ins_i[12] == 1'b0 && ins_i[6:2] == 5'b0) ) begin // c.addi
ins_o = { { 7 {ins_i[12]} }, ins_i[6:2], ins_i[11:7], 3'b000, ins_i[11:7], 7'b0010011 };
end else begin
ins_err_o = 1'b1;
end
end
3'b001 : begin // c.jal
ins_o = { ins_i[12], ins_i[8], ins_i[10:9], ins_i[6], ins_i[7], ins_i[2], ins_i[11], ins_i[5:3], ins_i[12], { 8 {ins_i[12]} }, 5'd1, 7'b1101111 };
end
3'b010 : begin // c.li
if (ins_i[11:7] != 5'd0) begin
ins_o = { { 7 {ins_i[12]} }, ins_i[6:2], 5'd0, 3'b000, ins_i[11:7], 7'b0010011 };
end else begin
ins_err_o = 1'b1;
end
end
3'b011 : begin // c.[lui/addi16sp]
if (!(ins_i[12] == 1'b0 && ins_i[6:2] == 5'b0)) begin
if (ins_i[11:7] != 5'd0) begin
if (ins_i[11:7] == 5'd2) begin // c.addi16sp
ins_o = { { 3 {ins_i[12]} }, ins_i[4], ins_i[3], ins_i[5], ins_i[2], ins_i[6], 4'b0, 5'd2, 3'b000, 5'd2, 7'b0010011 };
end else begin // lui
ins_o = { { 15 {ins_i[12]} }, ins_i[6:2], ins_i[11:7], 7'b0110111 };
end
end else begin
ins_err_o = 1'b1;
end
end else begin
ins_err_o = 1'b1;
end
end
3'b100 : begin // c.sr[l/a]i
if (ins_i[12:10] == 3'b011) begin // c.sub / c.xor / c.or / c.and
if (ins_i[6:5] == 2'b00) begin // c.sub
ins_o = { 7'b0100000, 2'b01, ins_i[4:2], 2'b01, ins_i[9:7], 3'b000, 2'b01, ins_i[9:7], 7'b0110011 };
end else if (ins_i[6:5] == 2'b01) begin // c.xor
ins_o = { 7'b0000000, 2'b01, ins_i[4:2], 2'b01, ins_i[9:7], 3'b100, 2'b01, ins_i[9:7], 7'b0110011 };
end else if (ins_i[6:5] == 2'b10) begin // c.or
ins_o = { 7'b0000000, 2'b01, ins_i[4:2], 2'b01, ins_i[9:7], 3'b110, 2'b01, ins_i[9:7], 7'b0110011 };
end else begin // c.and
ins_o = { 7'b0000000, 2'b01, ins_i[4:2], 2'b01, ins_i[9:7], 3'b111, 2'b01, ins_i[9:7], 7'b0110011 };
end
end else begin
if (ins_i[11:10] == 2'b10) begin // c.andi
ins_o = { { 7 {ins_i[12]} }, ins_i[6:2], 2'b01, ins_i[9:7], 3'b111, 2'b01, ins_i[9:7], 7'b0010011 };
end else begin
if (ins_i[12] == 1'b0 && ins_i[6:2] == 5'b0) begin
ins_err_o = 1'b1;
end else begin
if (ins_i[11:10] == 2'b00) begin // c.srli
ins_o = { 7'b0000000, ins_i[6:2], 2'b01, ins_i[9:7], 3'b101, 2'b01, ins_i[9:7], 7'b0010011 };
end else if (ins_i[11:10] == 2'b01) begin // c.srai
ins_o = { 7'b0100000, ins_i[6:2], 2'b01, ins_i[9:7], 3'b101, 2'b01, ins_i[9:7], 7'b0010011 };
end else begin
ins_err_o = 1'b1;
end
end
end
end
end
3'b101 : begin // c.j
ins_o = { ins_i[12], ins_i[8], ins_i[10:9], ins_i[6], ins_i[7], ins_i[2], ins_i[11], ins_i[5:3], ins_i[12], { 8 {ins_i[12]} }, 5'd0, 7'b1101111 };
end
3'b110 : begin // c.beqz
ins_o = { { 4 {ins_i[12]} }, ins_i[6], ins_i[5], ins_i[2], 5'd0, 2'b01, ins_i[9:7], 3'b000, ins_i[11], ins_i[10], ins_i[4], ins_i[3], ins_i[12], 7'b1100011 };
end
3'b111 : begin // c.bnez
ins_o = { { 4 {ins_i[12]} }, ins_i[6], ins_i[5], ins_i[2], 5'd0, 2'b01, ins_i[9:7], 3'b001, ins_i[11], ins_i[10], ins_i[4], ins_i[3], ins_i[12], 7'b1100011 };
end
default : begin
ins_err_o = 1'b1;
end
endcase
end
2'b10 : begin
case (funct3)
3'b000 : begin // c.slli
if (ins_i[12] == 1'b0 && ins_i[6:2] != 5'b0 && ins_i[11:7] != 5'b0) begin
ins_o = { 7'b0, ins_i[6:2], ins_i[11:7], 3'b001, ins_i[11:7], 7'b0010011 };
end else begin
ins_err_o = 1'b1;
end
end
3'b010 : begin // c.lwsp
if (ins_i[11:7] != 5'b0) begin
ins_o = { 4'b0, ins_i[3:2], ins_i[12], ins_i[6:4], 2'b0, 5'd2, 3'b010, ins_i[11:7], 7'b0000011 };
end else begin
ins_err_o = 1'b1;
end
end
3'b110 : begin // c.swsp
ins_o = { 4'b0, ins_i[8:7], ins_i[12], ins_i[6:2], 5'd2, 3'b010, ins_i[11:9], 2'b0, 7'b0100011 };
end
3'b100 : begin // c.j[al]r
if (ins_i[6:2] == 5'd0) begin // c.j[al]r / c.ebreak
if (ins_i[11:7] == 5'd0) begin
if (ins_i[12] == 1'b1) begin // c.ebreak
ins_o = { 11'b0, 1'b1, 13'b0, 7'b1110011 };
end else begin
ins_err_o = 1'b1;
end
end else begin // c.j[al]r
if (ins_i[12] == 1'b0) begin // c.jr
ins_o = { 12'b0, ins_i[11:7], 3'b000, 5'd0, 7'b1100111 };
end else begin // c.jalr
ins_o = { 12'b0, ins_i[11:7], 3'b000, 5'd1, 7'b1100111 };
end
end
end else begin // c.add / c.mv
if (ins_i[11:7] != 5'd0) begin // c.add / c.mv
if (ins_i[12] == 1'b0) begin // c.mv
ins_o = { 7'b0, ins_i[6:2], 5'd0, 3'b000, ins_i[11:7], 7'b0110011 };
end else begin // c.add
ins_o = { 7'b0, ins_i[6:2], ins_i[11:7], 3'b000, ins_i[11:7], 7'b0110011 };
end
end else begin
ins_err_o = 1'b1;
end
end
end
default : begin
ins_err_o = 1'b1;
end
endcase
end
default : begin
ins_rvc_o = 1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int n; std::cin >> n; int max = -1; int min = -1; std::vector<int> l, r; for (int i = 0; i < n; ++i) { int x, y; std::cin >> x >> y; l.push_back(x); r.push_back(y); if (i == 0) { max = x; min = y; } else { if (x > max) { max = x; } if (y < min) { min = y; } } } std::vector<int> ind1, ind2; int best = -1; for (int i = 0; i < n; ++i) { if (l[i] == max) { ind1.push_back(i); if (r[i] == min) { best = i; } } else { if (r[i] == min) { ind2.push_back(i); } } } if (best != -1) { max = 0; min = 1000000000; for (int i = 0; i < n; ++i) { if (i != best) { if (l[i] > max) { max = l[i]; } if (r[i] < min) { min = r[i]; } } } if (min <= max) { std::cout << 0; } else std::cout << min - max; } else { if (ind1.size() > 1 and ind2.size() > 1) { if (min <= max) { std::cout << 0; } else std::cout << min - max; } else { int max2 = 0; int min2 = 1000000000; for (int i = 0; i < n; ++i) { if (i != best) { if (l[i] > max2 and i != ind1[0]) { max2 = l[i]; } if (r[i] < min2 and i != ind2[0]) { min2 = r[i]; } } } int t1 = min - max2; int t2 = min2 - max; if (t1 > t2) { if (t1 < 0) std::cout << 0; else std::cout << t1; } else { if (t2 < 0) std::cout << 0; else std::cout << t2; } } } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const long long linf = 1LL << 62; const int mod = 1e9 + 7; const int MAX = 510000; const int V = 100005; struct UnionFind { vector<long long> p; vector<long long> rank; vector<long long> cnt; UnionFind(long long n) { rank.resize(n, 0); p.resize(n, 0); cnt.resize(n, 1); for (long long i = 0; i < (n); i++) { p[i] = i; rank[i] = 0; cnt[i] = 1; } } long long find(long long x) { if (x != p[x]) p[x] = find(p[x]); return p[x]; } bool same(long long x, long long y) { return find(x) == find(y); } void unite(long long x, long long y) { x = find(x); y = find(y); if (x == y) return; if (rank[x] > rank[y]) { p[y] = x; cnt[x] += cnt[y]; } else { p[x] = y; cnt[y] += cnt[x]; if (rank[x] == rank[y]) rank[y]++; } } long long getcnt(long long x) { return cnt[find(x)]; } }; int main() { long long q; cin >> q; while (q--) { long long n; cin >> n; UnionFind uf(n); for (long long i = 0; i < (n); i++) { long long a; cin >> a; a--; uf.unite(i, a); } for (long long i = 0; i < (n); i++) cout << uf.getcnt(i) << ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<string> v; string a; while (n--) { cin >> a; v.push_back(a); } int cot = 0; bool p = 1; int ans = 1000000; string c; for (int j = 0; j < v.size(); j++) { c = v[j]; cot = 0; for (int i = 0; i < v.size(); i++) { if (c == v[i] || i == j) continue; else { int ncot = 0; string b = v[i]; while (c != b) { ncot++; char d = b[0]; b.erase(b.begin()); b.push_back(d); if (ncot > b.length()) { p = 0; break; } } if (p == 0) break; else cot += ncot; } } if (p == 0) break; if (cot < ans) { ans = cot; } } if (p) cout << ans << endl; else cout << -1 << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m, s, t, g; int dl[200009], head, last, q[20009]; int dep[20010]; int h[20010], top = 1; struct edge { int to, net; long long w; } es[200009]; void add(int u, int v, long long w) { top++; es[top].w = w; es[top].net = h[u]; h[u] = top; es[top].to = v; return; } inline int read() { int sum = 0, fh = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) fh = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum *= 10; sum += c - 0 ; c = getchar(); } return sum * fh; } bool bfs() { for (int i = 1; i <= t; i++) dep[i] = 0; head = 1; last = 1; dl[1] = s; dep[s] = 1; while (head <= last) { int u = dl[head]; head++; for (int i = h[u]; i; i = es[i].net) { if (dep[es[i].to] == 0 && es[i].w) { dep[es[i].to] = dep[u] + 1; last++; dl[last] = es[i].to; } } } return dep[t]; } long long ans = 0, ssm = 0; long long dfs(int now, long long zg) { if (now == t) { return zg; } long long sum = 0; for (int i = h[now]; i; i = es[i].net) { int v = es[i].to; if (dep[v] == dep[now] + 1 && es[i].w) { long long res = dfs(v, min(es[i].w, zg)); sum += res; zg -= res; es[i].w -= res; es[i ^ 1].w += res; } } if (sum == 0) dep[now] = 0; return sum; } int main() { n = read(); m = read(); g = read(); s = 0; t = n + m + 2; for (int i = 1; i <= n; i++) q[i] = read(); for (int i = 1; i <= n; i++) { int x = read(); if (q[i] == 0) add(s, i, x), add(i, s, 0); else add(i, t, x), add(t, i, 0); } for (int i = 1; i <= m; i++) { int opt = read(), w = read(), k = read(); ssm += w; for (int j = 1; j <= k; j++) { int x = read(); if (opt == 0) { add(n + i, x, 1e18); add(x, n + i, 0); } else { add(x, n + i, 1e18); add(n + i, x, 0); } } int gt = read(); if (opt == 0) { add(s, n + i, w + g * gt); add(n + i, s, 0); } else { add(n + i, t, w + g * gt); add(t, n + i, 0); } } while (bfs()) { ans += dfs(s, 1e18); } cout << ssm - ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int calculate(long long int p, long long int q) { long long int modx = 998244353, expo; expo = modx - 2; while (expo) { { if (expo & 1) p = (p * q) % modx; } q = (q * q) % modx; expo >>= 1; } return p % modx; } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) { res = (res * x) % p; } y = y >> 1; x = (x * x) % p; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; t = 1; while (t--) { long long int n, k; cin >> n >> k; string s; long long int ans = 1; cin >> s; if (k == 0) { cout << 1 << n ; continue; } long long int i = 0, j = 0; long long int dp[n + 5][k + 5]; memset(dp, 0, sizeof(dp)); for (int p = 1; p <= k; p++) { dp[0][p] = dp[0][p - 1] + 1; } for (int p = 1; p <= n; p++) { for (int q = 1; q <= k; q++) dp[p][q] = (dp[p - 1][q] + dp[p][q - 1]) % 998244353; } long long int zero = 0, lastzero = 0, one = 0, b = 0; while (i < n) { if (s[i] == 0 ) { zero++; if (one == k) lastzero++; } else one++; if (one > k) { for (int p = 0; p < zero; p++) { ans = (ans + dp[p][k]) % 998244353; } long long int temp = 0; if (b > 0) { for (int p = 0; p < zero - lastzero; p++) { temp = (temp + dp[p][k - 1]) % 998244353; } } lastzero = 0; b = 1; ans = (998244353 + ans - temp) % 998244353; while (j < i) { if (s[j] == 1 ) { one--; j++; break; } j++; zero--; } } i++; } if (one == k) { for (int p = 0; p < zero; p++) { ans = (ans + dp[p][k]) % 998244353; } long long int temp = 0; if (b > 0) { for (int p = 0; p < zero - lastzero; p++) { temp = (temp + dp[p][k - 1]) % 998244353; } } ans = (998244353 + ans - temp) % 998244353; } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int i, j, a; int main() { for (i = 1; i <= 5; i++) { for (j = 1; j <= 5; j++) { cin >> a; if (a == 1) cout << (abs(3 - i) + abs(3 - j)) << endl; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
`timescale 1ns / 1ns
// Define this to get the original behaviour of the 74373 on the Mark2 board latching
// addresses to keep them stable during refresh rather than forcing a fixed value
// during dummy accesses.
// `define LATCH_ADR 1
`define ELK_PAGED_ROM_SEL 16'hFE05
`define PAGED_ROM_SEL 16'hFE30
`define BPLUS_SHADOW_RAM_SEL 16'hFE34
// Decode jumpers on J[1:0]
`define BEEB_MODE (j==2'b00)
`define BPLUS_MODE (j==2'b01)
`define ELK_MODE (j==2'b10)
`define MASTER_MODE (j==2'b11)
module cpld_jnr (
input [15:0] cpu_adr,
input [1:0] j,
input lat_en,
output dec_shadow_reg,
output dec_rom_reg,
output dec_fe4x,
output [11:0] bbc_adr
);
reg [11:0] bbc_adr_lat_q;
assign bbc_adr = bbc_adr_lat_q;
assign dec_shadow_reg = (`BPLUS_MODE) ? (cpu_adr==`BPLUS_SHADOW_RAM_SEL) : 1'b0;
assign dec_rom_reg = (`ELK_MODE)? (cpu_adr==`ELK_PAGED_ROM_SEL) : (cpu_adr==`PAGED_ROM_SEL);
// Flag FE4x (VIA) accesses and also all &FC, &FD expansion pages
assign dec_fe4x = (cpu_adr[15:4]==12'hFE4) || (cpu_adr[15:9]==7'b1111_110);
always @ ( * )
if ( lat_en )
bbc_adr_lat_q <= cpu_adr[11:0];
`ifndef LATCH_ADR
else
bbc_adr_lat_q <= 12'b0;
`endif
endmodule
|
`include "elink_regmap.v"
module erx_arbiter (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
// Inputs
erx_rr_access, erx_packet, emmu_access, emmu_packet, edma_access,
edma_packet, ecfg_access, ecfg_packet, timeout, rxwr_wait,
rxrd_wait, rxrr_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h800; //link id
parameter RFAW = 6;
//From IO (for rr)
input erx_rr_access;
input [PW-1:0] erx_packet;
output rx_rd_wait; //for IO
output rx_wr_wait; //for IO
//From EMMU (writes)
input emmu_access;
input [PW-1:0] emmu_packet;
//From DMA
input edma_access;
input [PW-1:0] edma_packet;
output edma_wait;
//From ETX
input ecfg_access;
input [PW-1:0] ecfg_packet;
output ecfg_wait;
//From timeout circuit
input timeout;
//To Master Write FIFO
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//To Master Read FIFO
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//To Slave Read Response FIFO
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//wires
wire emmu_write;
wire emmu_read;
wire [11:0] myid;
//####################################
//Splicing pakets
//####################################
assign myid[11:0] = ID;
//####################################
//Read response path (from IO or cfg)
//####################################
assign rxrr_access = erx_rr_access |
ecfg_access;
assign rxrr_packet[PW-1:0] = erx_rr_access ? erx_packet[PW-1:0] :
ecfg_packet[PW-1:0];
assign ecfg_wait = erx_rr_access;
//####################################
//Write Path (direct)
//####################################
assign emmu_write = emmu_packet[1];
assign rxwr_access = emmu_access & emmu_write;
assign rxwr_packet[PW-1:0] = emmu_packet[PW-1:0];
//####################################
//Read Request Path
//####################################
assign emmu_read = emmu_access & ~emmu_write;
assign rxrd_access = emmu_read | edma_access;
assign rxrd_packet[PW-1:0] = emmu_read ? emmu_packet[PW-1:0] :
edma_packet[PW-1:0];
//####################################
//Wait Signals
//####################################
assign rx_rd_wait = rxrd_wait;
assign rx_wr_wait = rxwr_wait | rxrr_wait;
assign edma_wait = rxrd_wait | emmu_read;
assign erx_cfg_wait = rxwr_wait | rxrr_wait;
endmodule // erx_arbiter
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../emmu/hdl")
// End:
//#############################################################################
/*
This file is part of the Parallella Project.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// DeBounce_v.v
//////////////////////// Button Debounceer ///////////////////////////////////////
//***********************************************************************
// FileName: DeBounce_v.v
// FPGA: MachXO2 7000HE
// IDE: Diamond 2.0.1
//
// HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
// WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
// BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
// DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
// PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
// BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
// ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
// DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
// INFRINGEMENT.
//
// Version History27
// Version 1.0 04/11/2013 Tony Storey
// Initial Public Release
// Small Footprint Button Debouncer
// https://www.eewiki.net/pages/viewpage.action?pageId=13599139
// https://www.eewiki.net/display/LOGIC/Debounce+Logic+Circuit+%28with+VHDL+example%29
`timescale 1 ns / 100 ps
module DeBounce
(
input clk, n_reset, button_in, // inputs
output reg DB_out // output
);
//// ---------------- internal constants --------------
parameter N = 11 ; // 2^11/ 50 MHz = 40.96 ms debounce time
////---------------- internal variables ---------------
reg [N-1 : 0] q_reg; // timing regs
reg [N-1 : 0] q_next;
reg DFF1, DFF2; // input flip-flops
wire q_add; // control flags
wire q_reset;
//// ------------------------------------------------------
////contenious assignment for counter control
assign q_reset = (DFF1 ^ DFF2); // xor input flip flops to look for level chage to reset counter
assign q_add = ~(q_reg[N-1]); // add to counter when q_reg msb is equal to 0
//// combo counter to manage q_next
always @ ( q_reset, q_add, q_reg)
begin
case( {q_reset , q_add})
2'b00 :
q_next <= q_reg;
2'b01 :
q_next <= q_reg + 1;
default :
q_next <= { N {1'b0} };
endcase
end
//// Flip flop inputs and q_reg update
always @ ( posedge clk )
begin
if(n_reset == 1'b0)
begin
DFF1 <= 1'b0;
DFF2 <= 1'b0;
q_reg <= { N {1'b0} };
end
else
begin
DFF1 <= button_in;
DFF2 <= DFF1;
q_reg <= q_next;
end
end
//// counter control
always @ ( posedge clk )
begin
if(q_reg[N-1] == 1'b1)
DB_out <= DFF2;
else
DB_out <= DB_out;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_NSR_PP_PG_N_TB_V
`define SKY130_FD_SC_MS__UDP_DFF_NSR_PP_PG_N_TB_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SET = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 NOTIFIER = 1'b1;
#180 RESET = 1'b1;
#200 SET = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 NOTIFIER = 1'b0;
#300 RESET = 1'b0;
#320 SET = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET = 1'b1;
#440 RESET = 1'b1;
#460 NOTIFIER = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET = 1'bx;
#560 RESET = 1'bx;
#580 NOTIFIER = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dut (.SET(SET), .RESET(RESET), .D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_NSR_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long int is_query = LLONG_MIN; struct Line { long long int m, b; mutable function<const Line*()> succ; bool operator<(const Line& rhs) const { if (rhs.b != is_query) return m < rhs.m; const Line* s = succ(); if (!s) return 0; long long int x = rhs.m; return b - s->b < (s->m - m) * x; } }; struct HullDynamic : public multiset<Line> { bool bad(iterator y) { auto z = next(y); if (y == begin()) { if (z == end()) return 0; return y->m == z->m && y->b <= z->b; } auto x = prev(y); if (z == end()) return y->m == x->m && y->b <= x->b; return 1.0 * (x->b - y->b) * (z->m - y->m) > 1.0 * (y->b - z->b) * (y->m - x->m); } void Add(long long int m, long long int b) { auto y = insert({m, b}); y->succ = [=] { return next(y) == end() ? 0 : &*next(y); }; if (bad(y)) { erase(y); return; } while (next(y) != end() && bad(next(y))) erase(next(y)); while (y != begin() && bad(prev(y))) erase(prev(y)); } long long int Query(long long int x) { auto l = lower_bound((Line){x, is_query}); if (l == end()) return LLONG_MIN; return l->m * x + l->b; } }; HullDynamic Tree[4 * 300005]; long long int query(int node, int lo, int hi, int i, int j, long long int x) { if (i > hi || j < lo) return LLONG_MIN; long long int ret = LLONG_MIN; ret = Tree[node].Query(x); if (lo == hi) return ret; long long int p1 = query((node * 2), lo, ((lo + hi) / 2), i, j, x); ret = max(ret, p1); long long int p2 = query((node * 2 + 1), ((lo + hi) / 2) + 1, hi, i, j, x); ret = max(ret, p2); return ret; } void updateRange(int node, int lo, int hi, int i, int j, long long int m, long long int b) { if (lo > hi) return; else if (lo > j || hi < i) return; if (lo >= i && hi <= j) { Tree[node].Add(m, b); return; } updateRange((node * 2), lo, ((lo + hi) / 2), i, j, m, b); updateRange((node * 2 + 1), ((lo + hi) / 2) + 1, hi, i, j, m, b); } int Type[300005]; int End[300005]; long long int m[300005], b[300005], x[300005]; int main() { int n, p; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &Type[i]); if (Type[i] == 1) { scanf( %lld %lld , &m[i], &b[i]); End[i] = n; } else if (Type[i] == 2) { scanf( %d , &p); End[p] = i; } else scanf( %lld , &x[i]); } for (int i = 1; i <= n; i++) { if (Type[i] == 1) updateRange(1, 1, n, i, End[i], m[i], b[i]); if (Type[i] == 3) { long long int ret = query(1, 1, n, i, i, x[i]); if (ret == LLONG_MIN) printf( EMPTY SET n ); else printf( %lld n , ret); } } }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const int SINF = 0x7fffffff; const long long LINF = 0x3fffffffffffffff; const long long SLINF = 0x7fffffffffffffff; const int MAXN = 30007; const int MAXD = 6; const int MOD = 998244353; int n, d; int a[MAXN][MAXD][MAXD]; int tmp[MAXD][MAXD]; int ans[MAXN]; int m1[MAXN], m2[MAXN]; map<vector<int>, int> mp; map<vector<int>, int>::iterator it; void init(); void input(); void work(); vector<int> gauss(int a[][MAXD]); int add(int x, int y) { x += y; if (x >= MOD) x -= MOD; return x; } void addv(int &x, int y) { x += y; if (x >= MOD) x -= MOD; } int dec(int x, int y) { x -= y; if (x < 0) x += MOD; return x; } void decv(int &x, int y) { x -= y; if (x < 0) x += MOD; } int qpow(int a, int b) { long long base = a, ans = 1; while (b) { if (b & 1) (ans *= base) %= MOD; (base *= base) %= MOD; b >>= 1; } return static_cast<int>(ans); } int main() { init(); input(); work(); } void init() { ios::sync_with_stdio(false); } void input() { scanf( %d%d , &n, &d); int nk; for (int i = 1; i <= n; ++i) { scanf( %d , &nk); for (int j = 1; j <= nk; ++j) { for (int k = 1; k <= d; ++k) scanf( %d , &a[i][j][k]); } } } void work() { int kc = 0; vector<int> v; for (int i = 1; i <= n; ++i) { v = gauss(a[i]); if ((it = mp.find(v)) == mp.end()) mp[v] = ans[i] = ++kc; else ans[i] = it->second; } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); putchar( n ); } vector<int> gauss(int a[][MAXD]) { for (int i = 1; i <= d; ++i) m1[i] = m2[i] = 0; for (int i = 1; i <= d; ++i) for (int j = 1; j <= d; ++j) tmp[i][j] = (a[i][j] + MOD) % MOD; long long g; int ni = 1; for (int i = 1; i <= d; ++i) { for (int j = ni; j <= d; ++j) { if (tmp[j][i]) { for (int k = 1; k <= d; ++k) swap(tmp[ni][k], tmp[j][k]); } } if (tmp[ni][i]) { m1[ni] = i, m2[i] = ni; for (int j = ni + 1; j <= d; ++j) { g = qpow(tmp[ni][i], MOD - 2) * static_cast<long long>(tmp[j][i]) % MOD; for (int k = i; k <= d; ++k) decv(tmp[j][k], g * tmp[ni][k] % MOD); } ++ni; } } for (int i = ni - 1; i > 0; --i) { for (int j = m1[i] + 1; j <= d; ++j) { if (m2[j]) { g = qpow(tmp[m2[j]][j], MOD - 2) * static_cast<long long>(tmp[i][j]) % MOD; for (int k = j; k <= d; ++k) decv(tmp[i][k], tmp[m2[j]][k] * g % MOD); } } } for (int i = 1; i < ni; ++i) { g = qpow(tmp[i][m1[i]], MOD - 2); for (int j = m1[i]; j <= d; ++j) tmp[i][j] = static_cast<long long>(tmp[i][j]) * g % MOD; } vector<int> ans; for (int i = 1; i < ni; ++i) for (int j = 1; j <= d; ++j) ans.push_back(tmp[i][j]); return ans; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] q; // From test of Test.v
// End of automatics
Test test (
// Outputs
.q (q[2:0]),
// Inputs
.clk (clk),
.reset_l (crc[0]),
.enable (crc[2]),
.q_var0 (crc[19:10]),
.q_var2 (crc[29:20]),
.q_var4 (crc[39:30]),
.q_var6 (crc[49:40])
/*AUTOINST*/);
// Aggregate outputs into a single result vector
wire [63:0] result = {61'h0,q};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h58b162c58d6e35ba
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input clk,
input reset_l,
input enable,
input [ 9:0] q_var0,
input [ 9:0] q_var2,
input [ 9:0] q_var4,
input [ 9:0] q_var6,
output reg [2:0] q
);
reg [7:0] p1_r [6:0];
always @(posedge clk) begin
if (!reset_l) begin
p1_r[0] <= 'b0;
p1_r[1] <= 'b0;
p1_r[2] <= 'b0;
p1_r[3] <= 'b0;
p1_r[4] <= 'b0;
p1_r[5] <= 'b0;
p1_r[6] <= 'b0;
end
else if (enable) begin : pass1
match(q_var0, q_var2, q_var4, q_var6);
end
end
// verilator lint_off WIDTH
always @(posedge clk) begin : l
reg [10:0] bd;
reg [3:0] idx;
q = 0;
bd = 0;
for (idx=0; idx<7; idx=idx+1) begin
q = idx+1;
bd = bd + p1_r[idx];
end
end
task match;
input [9:0] p0, p1, p2, p3;
reg [9:0] p[3:0];
begin
p[0] = p0;
p[1] = p1;
p[2] = p2;
p[3] = p3;
p1_r[0] <= p[0];
p1_r[1] <= p[1];
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A222OI_BEHAVIORAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int fun(int x, int y, int z) { return x * x + y * y + z * z + x * y + y * z + z * x; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t, n; cin >> t; while (t--) { cin >> n; int a[n]; int f = true; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < n - 1; i++) { if (a[i] > a[i - 1] && a[i] > a[i + 1]) { cout << YES << endl; f = false; cout << i << << i + 1 << << i + 2 << endl; break; } } if (f) cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, q; cin >> n >> q; bool lava[2][n]; for (int i = 0; i < 2; i++) { for (int j = 0; j < n; j++) lava[i][j] = false; } set<int> blocked1; set<int> blocked2; for (int i = 0; i < q; i++) { int r, c; cin >> r >> c; r--; c--; if (lava[r][c]) { blocked2.erase(c); if (c < n - 1 && !lava[r][c + 1]) { blocked1.erase(c); } if (c > 0 && !lava[r][c - 1]) { blocked1.erase(c - 1); } } else { if (lava[(r + 1) % 2][c]) { blocked2.insert(c); } if (c < n - 1 && lava[(r + 1) % 2][c + 1]) { blocked1.insert(c); } if (c > 0 && lava[(r + 1) % 2][c - 1]) { blocked1.insert(c - 1); } } lava[r][c] = !lava[r][c]; if (blocked1.empty() && blocked2.empty() && !lava[0][0] && !lava[1][n - 1]) { cout << Yes << endl; } else { cout << No << endl; } } }
|
#include <bits/stdc++.h> using namespace std; void solve() { int a; cin >> a; int b[a]; for (int i = 0; i < a; i++) { cin >> b[i]; } int ind = 0; for (int i = 0; i < a - 1; i++) { if (b[i] > b[i + 1]) { b[0] = b[0] - b[i] + b[i + 1]; if (b[0] < 0) { cout << NO ; return; } } } cout << YES ; } int main() { int t; cin >> t; while (t--) { solve(); cout << endl; } }
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1 ns / 1 ps
`include "xls/uncore_rtl/ice40/uart_transmitter.v"
`ifndef CLOCKS_PER_BAUD
`define CLOCKS_PER_BAUD 2
`endif
module uart_transmitter_two_bytes_test;
reg clk;
reg rst_n;
reg [7:0] tx_byte;
reg tx_byte_valid;
wire tx_byte_done;
wire tx;
integer i, start_time, first_byte_done_time, second_byte_done_time;
// #TicksPerClock waits for a single clock cycle.
localparam TicksPerClock = 2;
// Number of clock cycles that consitutes the time of a single baud.
localparam ClocksPerBaud = `CLOCKS_PER_BAUD;
uart_transmitter #(
.ClocksPerBaud(ClocksPerBaud)
) transmitter(
.clk (clk),
.rst_n (rst_n),
.tx_byte (tx_byte),
.tx_byte_valid (tx_byte_valid),
.tx_byte_done_out(tx_byte_done),
.tx_out (tx)
);
initial begin
#1 clk = 0;
forever #1 clk = !clk;
end
`include "xls/uncore_rtl/ice40/xls_assertions.inc"
// Make sure we finish after some reasonable amount of time.
initial begin
#1024 begin
$display("ERROR: timeout, simulation ran too long");
$finish;
end
end
initial begin
//$dumpfile("/tmp/uart_transmitter_two_bytes_test.vcd");
//$dumpvars(0, clk, rst_n, tx_byte, tx_byte_valid, tx_byte_done, tx,
// transmitter.tx_bitno, transmitter.tx_state,
// transmitter.tx_state_next, transmitter.tx_byte_done_next);
$display("Starting...\n");
$monitor("%t tx: %b tx_byte_done: %b", $time, tx, tx_byte_done);
rst_n <= 0;
tx_byte_valid <= 0;
tx_byte <= 'hff;
// Come out of reset after a few cycles.
#4 rst_n <= 1;
$dumpon;
#TicksPerClock;
for (i = 0; i < 10; i = i + 1) begin
xls_assert(1, tx, "idle");
#1;
end
// Present a byte to transmit after those few cycles of non-reset idle
// activity.
tx_byte <= 'h55;
tx_byte_valid <= 1;
#TicksPerClock tx_byte_valid <= 0;
#0.1 xls_assert(tx_byte_done, 0, "tx_byte_done 'h55 start");
// Wait for the start bit to show up.
wait (tx == 0);
// Note the start time!
start_time = $time;
// Check we wiggle 1-0 four times for the data.
repeat (4) begin
wait (tx == 1);
wait (tx == 0);
end
wait (transmitter.tx_state_next == 'b11); // Going to stop.
$display("About to stop @ %t", $time);
`ifdef PRESENT_BIT_EARLY
$display("Presenting bit early...");
// Present the next byte to transmit for one cycle while the stop bit is
// tranmitting.
#TicksPerClock;
$display("Presenting second byte @ %t", $time);
tx_byte <= 'haa;
tx_byte_valid <= 1;
#TicksPerClock tx_byte_valid <= 0;
`else
$display("Presenting bit late...");
wait (tx == 1); // stop bit
#((ClocksPerBaud-2)*TicksPerClock);
// Present the transfer request on the last cycle.
// Note we already observed one cycle of stop bit above.
tx_byte <= 'haa;
tx_byte_valid <= 1;
#(TicksPerClock+0.3) tx_byte_valid <= 0;
`endif
// Wait for it to say it's processing that second byte.
wait (transmitter.tx_state != 'b11);
first_byte_done_time = $time;
// Check we wiggle 0-1 four times for the data.
repeat (4) begin
wait (tx == 0);
wait (tx == 1);
end
// Wait for that second byte to be done.
wait (tx_byte_done == 1);
// Note when this second byte is done!
second_byte_done_time = $time;
$display("start: %t first_byte_done: %t second_byte_done: %t",
start_time, first_byte_done_time, second_byte_done_time);
xls_assert_int_eq(
10*ClocksPerBaud-1,
(first_byte_done_time-start_time)/2, "first byte cycles");
xls_assert_int_eq(
`ifdef PRESENT_BIT_EARLY
9*ClocksPerBaud,
`else
9*ClocksPerBaud+1,
`endif
(second_byte_done_time-first_byte_done_time)/2,
"second byte cycles");
#256 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 40 + 2; int n, m, q, dp[maxn][maxn][maxn][maxn], ones[maxn][maxn], a, b, c, d; int main() { ios::sync_with_stdio(false); char ch; cin >> n >> m >> q; for (int _b = (n), i = (1); i <= _b; ++i) for (int _b = (m), j = (1); j <= _b; ++j) { cin >> ch; ones[i][j] = ones[i - 1][j] + ones[i][j - 1] - ones[i - 1][j - 1] + ch - 0 ; } for (int _b = (n - 1), h = (0); h <= _b; ++h) for (int _b = (m - 1), w = (0); w <= _b; ++w) for (int _b = (n - h), i = (1); i <= _b; ++i) for (int _b = (m - w), j = (1); j <= _b; ++j) { a = i, b = j, c = i + h, d = j + w; dp[a][b][c][d] = ((ones[c][d] - ones[a - 1][d] - ones[c][b - 1] + ones[a - 1][b - 1]) == 0); for (int _b = ((1 << 4) - 1), mask = (1); mask <= _b; ++mask) { dp[a][b][c][d] += (-1 + 2 * (__builtin_popcount(mask) & 1)) * dp[a + (mask >> 0 & 1)][b + (mask >> 1 & 1)] [c - (mask >> 2 & 1)][d - (mask >> 3 & 1)]; } } while (q--) { cin >> a >> b >> c >> d; cout << dp[a][b][c][d] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100009; int n, m, k, a[MAX], b[MAX], pos[MAX]; int main() { cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; pos[a[i]] = i; } long long ans = 0; for (int i = 1; i <= m; i++) { cin >> b[i]; int current = pos[b[i]]; ans += (current + k - 1) / k; if (current > 1) { swap(pos[a[current]], pos[a[current - 1]]); swap(a[current], a[current - 1]); } } printf( %I64d n , ans); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:21:08 01/31/2017
// Design Name: PWM
// Module Name: /home/aaron/Git Repos/CSE311/lab2/PWM_tb.v
// Project Name: lab2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: PWM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module PWM_tb;
// Inputs
reg clk;
reg [3:0] duty_cycle;
// Outputs
wire pwm;
// Instantiate the Unit Under Test (UUT)
PWM uut (
.clk(clk),
.duty_cycle(duty_cycle),
.pwm(pwm)
);
initial begin
// Initialize Inputs
clk = 0;
duty_cycle = 0;
// Wait 100 ns for global reset to finish
#100;
// Start clock
forever begin
#5 clk=~clk;
end
end
initial begin
#1000;
// 25% Duty-cycle
duty_cycle = 4'b0011;
#1000;
duty_cycle = 4'b0111;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A31O_PP_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a31o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int a[N], f[N]; long long dis[N], pos[N], res[N]; int n; void add(long long *b, int x, long long v) { for (int i = x; i <= n; i += i & -i) b[i] += v; } long long qry(long long *b, int x) { long long ret = 0; for (int i = x; i > 0; i ^= i & -i) ret += b[i]; return ret; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], f[a[i]] = i; long long t = 0; for (int i = 1; i <= n; i++) { int p = f[i]; t += qry(pos, n) - qry(pos, p); add(pos, p, 1); add(dis, p, p); int j = (i + 1) / 2, l = 1, r = n; while (l < r) { int m = (l + r) >> 1; if (qry(pos, m) >= j) r = m; else l = m + 1; } int x = l; long long r1 = j - 1, r2 = i - j, cur = t; if (r1 > 0) cur += r1 * x - qry(dis, x - 1) - r1 * (r1 + 1) / 2; if (r2 > 0) cur += (qry(dis, n) - qry(dis, x)) - r2 * x - r2 * (r2 + 1) / 2; res[i] = cur; } for (int i = 1; i <= n; i++) cout << res[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; bool good[N], need[N]; int n; void ask(vector<int> &v) { printf( %d , (int)v.size()); for (int i = 0; i < (int)v.size(); i++) { printf( %d , v[i]); good[v[i]] = true; } puts( ); fflush(stdout); int idx; scanf( %d , &idx); for (int i = 0; i < (int)v.size(); i++) { good[idx] = false; idx++; if (idx > n) idx = 1; } } int main() { scanf( %d , &n); if (n <= 3) { puts( 0 ); fflush(stdout); return 0; } int cur, best = 0, k; for (int sz = 1; sz < n; sz++) { cur = ((n + sz) / (sz + 1)); cur = n - cur - sz; if (cur > best) { best = cur; k = sz; } } for (int i = 1; i < n; i += k + 1) { for (int j = i; j < min(n, i + k); j++) need[j] = true; } vector<int> v; while (true) { cur = 0; for (int l = 1; l <= n; l++) if (good[l]) cur++; if (cur >= best) break; v.clear(); for (int i = 1; i <= n; i++) { if (need[i] && !good[i]) v.push_back(i); } ask(v); } puts( 0 ); fflush(stdout); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename TH> void _dbg(const char* sdbg, TH h) { cerr << sdbg << = << h << n ; } template <typename TH, typename... TA> void _dbg(const char* sdbg, TH h, TA... t) { while (*sdbg != , ) { cerr << *sdbg++; } cerr << = << h << , ; _dbg(sdbg + 1, t...); } template <class C> void mini(C& a4, C b4) { a4 = min(a4, b4); } template <class C> void maxi(C& a4, C b4) { a4 = max(a4, b4); } template <class T1, class T2> ostream& operator<<(ostream& out, pair<T1, T2> pair) { return out << ( << pair.first << , << pair.second << ) ; } template <class A, class B, class C> struct Triple { A first; B second; C third; bool operator<(const Triple& t) const { if (first != t.first) return first < t.first; if (second != t.second) return second < t.second; return third < t.third; } }; template <class T> void ResizeVec(T&, vector<long long>) {} template <class T> void ResizeVec(vector<T>& vec, vector<long long> sz) { vec.resize(sz[0]); sz.erase(sz.begin()); if (sz.empty()) { return; } for (T& v : vec) { ResizeVec(v, sz); } } template <class A, class B, class C> ostream& operator<<(ostream& out, Triple<A, B, C> t) { return out << ( << t.first << , << t.second << , << t.third << ) ; } template <class T> ostream& operator<<(ostream& out, vector<T> vec) { out << ( ; for (auto& v : vec) out << v << , ; return out << ) ; } template <class T> ostream& operator<<(ostream& out, set<T> vec) { out << ( ; for (auto& v : vec) out << v << , ; return out << ) ; } template <class L, class R> ostream& operator<<(ostream& out, map<L, R> vec) { out << ( ; for (auto& v : vec) out << v << , ; return out << ) ; } int32_t main() { ios_base::sync_with_stdio(0); cout << fixed << setprecision(10); if (0) cout << fixed << setprecision(10); cin.tie(0); long long t; cin >> t; for (long long ii = (1); ii <= (t); ++ii) { long long n; cin >> n; vector<long long> v; long long sum = 0; long long ma = 0; for (long long i = (1); i <= (n); ++i) { long long a; cin >> a; v.push_back(a); sum += a; maxi(ma, a); } if (n == 1) { cout << T n ; continue; } if (2 * ma > sum) { cout << T n ; } else { cout << vector<string>{ HL , T }[sum % 2] << endl; } } return 0; }
|
module top;
reg pass;
reg [2:0] res [0:7];
reg [2:0] in [0:7];
reg [7:0] dummy [0:6];
time run_time [0:7];
time exp_time [0:7];
integer i;
initial begin
pass = 1'b1;
#1;
// Initialize the input array.
for (i=0; i<8; i=i+1) begin
in[i] = i[2:0];
end
#1;
for (i=0; i<8; i=i+1) begin
exp_time[i] = $time-1;
end
check;
// We only have 6 dummy items, check that each triggers correctly.
for (i=0; i<7; i=i+1) begin
dummy[i] = 1'b0;
#1;
exp_time[i] = $time-1;
check;
end
if (pass) $display("PASSED");
end
// Check that the value and time are correct.
task check;
integer j;
begin
for (j=0; j<8; j=j+1) begin
if (res[j] !== j[2:0]) begin
$display("FAILED: index %0d value, at %2t, expexted %b, got %b.",
j, $time, j[2:0], res[j]);
pass = 1'b0;
end
if (run_time[j] !== exp_time[j]) begin
$display("FAILED: index %0d time, at %2t, expexted %2t, got %2t.",
j, $time, exp_time[j], run_time[j]);
pass = 1'b0;
end
end
end
endtask
genvar m;
generate
for (m=0; m<=7; m=m+1) begin: idac_loop
// This should complain that dummy[7] is out of bounds.
always @ (in[m] or dummy[m]) begin
res[m] = in[m];
run_time[m] = $time;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_1_V
`define SKY130_FD_SC_LP__SDFBBN_1_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ((void)0); ((void)0); ((void)0); int T, N, M1, M2, s, e; long long X; for (cin >> T; T--;) { M1 = M2 = 0x7fffffff; s = 0; e = 1e9; for (cin >> N >> X; N--;) { int d, h; cin >> d >> h; M1 = min(M1, -d); M2 = min(M2, h - d); } if (X + M1 <= 0) { cout << 1 n ; continue; } while (s <= e) { int m = (s + e) >> 1; if (X + 1LL * m * M2 + M1 <= 0) e = m - 1; else s = m + 1; } if (s > 1e9) cout << -1 n ; else cout << s + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool KT(long long k, long long n) { long long take = 0, cur = n; while (cur > 0) { long long temp = min(k, cur); take += temp; cur -= temp; cur -= cur / 10; } if (take * 2 >= n) return true; return false; } int main() { long long n; cin >> n; long long left = 1, right = n, res = 0; while (left <= right) { long long mid = (left + right) / 2; if (KT(mid, n)) { res = mid; right = mid - 1; } else { left = mid + 1; } } cout << res; return 0; }
|
`include "./simple_fifo.v"
`include "./fifo_fwft_adapter.v"
module fifo_fwft # (
parameter DATA_WIDTH = 0,
parameter DEPTH_WIDTH = 0
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] din,
input wire wr_en,
output wire full,
output wire [DATA_WIDTH-1:0] dout,
input wire rd_en,
output wire empty,
output wire valid
);
wire [DATA_WIDTH-1:0] fifo_dout;
wire fifo_empty;
wire fifo_rd_en;
// orig_fifo is just a normal (non-FWFT) synchronous or asynchronous FIFO
simple_fifo # (
.DEPTH_WIDTH (DEPTH_WIDTH),
.DATA_WIDTH (DATA_WIDTH )
) fifo0 (
.clk (clk ),
.rst (rst ),
.rd_en (fifo_rd_en),
.rd_data (fifo_dout ),
.empty (fifo_empty),
.wr_en (wr_en ),
.wr_data (din ),
.full (full )
);
fifo_fwft_adapter # (
.DATA_WIDTH (DATA_WIDTH)
) fwft_adapter (
.clk (clk ),
.rst (rst ),
.rd_en (rd_en ),
.fifo_empty (fifo_empty),
.fifo_rd_en (fifo_rd_en),
.fifo_dout (fifo_dout ),
.dout (dout ),
.empty (empty ),
.valid (valid )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, k, l, x = 1; cin >> n >> m >> k >> l; if (k + l > n) cout << -1 ; else if ((k + l) % m == 0 && (k + l) <= n) cout << (k + l) / m; else if ((k + l) % m != 0 && ((k + l) / m + 1) * m <= n) cout << ((k + l) / m) + 1; else cout << -1 ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void read(long long &x) { char ch = getchar(); x = 0; while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); } const long long N = 2e5 + 10; long long n, mx, rt, tmp, sum, f[N], fr[N], tot, st[N], fl[N], p[N]; long long cnt, h[N], to[N << 1], nxt[N << 1], len[N << 1], d[N], vis[N]; void add(long long u, long long v, long long l) { to[++cnt] = v, len[cnt] = l, nxt[cnt] = h[u], h[u] = cnt; to[++cnt] = u, len[cnt] = l, nxt[cnt] = h[v], h[v] = cnt; } void dfs(long long u, long long la) { if (d[u] > d[mx]) mx = u; fr[u] = la; for (long long i = h[u], v; i; i = nxt[i]) { if ((v = to[i]) == la) continue; fl[v] = len[i], d[v] = d[u] + len[i], dfs(v, u); } } void get_dis(long long u, long long deep) { f[u] = deep; vis[u] = 1; for (long long i = h[u]; i; i = nxt[i]) if (!vis[to[i]]) get_dis(to[i], deep + len[i]); } long long ff[N], dp[N]; void get_fa(long long u, long long deep) { dp[u] = deep; for (long long i = h[u], v; i; i = nxt[i]) if ((v = to[i]) != ff[u]) ff[v] = u, get_fa(v, deep + 1); } bool cmp(long long x, long long y) { return f[x] == f[y] ? dp[x] < dp[y] : f[x] < f[y]; } long long fa[N], sz[N]; long long find(long long x) { return fa[x] == x ? x : (fa[x] = find(fa[x])); } void work(long long l) { long long res = 0; for (long long i = 1; i <= n; ++i) fa[i] = i, sz[i] = 1; for (long long i = n, j = n; i >= 1; --i) { while (f[p[j]] > f[p[i]] + l) --sz[find(p[j--])]; res = max(res, sz[p[i]]); fa[p[i]] = find(ff[p[i]]); sz[find(ff[p[i]])] += sz[p[i]]; } printf( %lld n , res); } signed main() { read(n); for (long long i = 1, u, v, l; i < n; ++i) read(u), read(v), read(l), add(u, v, l); dfs(1, 0); d[mx] = fl[mx] = 0, dfs(mx, 0); while (mx) sum += fl[mx], st[++tot] = mx, vis[mx] = 1, mx = fr[mx]; long long now = 0, mn = 1e15; for (long long i = 1; i <= tot; ++i) { get_dis(st[i], max(now, sum - now)); if (max(now, sum - now) < mn) mn = max(now, sum - now), rt = st[i]; now += fl[st[i]]; } get_fa(rt, 0); for (long long i = 1; i <= n; ++i) p[i] = i; sort(p + 1, p + n + 1, cmp); long long m, x; read(m); while (m--) read(x), work(x); return 0; }
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#include <bits/stdc++.h> using namespace std; map<char, int> mp1; int main() { ios_base::sync_with_stdio(0); string s, p, q; long long int a, b, c, d, i, j, k, u, v, w = 0, x, y, z; cin >> p; for (i = 0; i < p.length(); i++) mp1[p[i]] = 1; cin >> s; cin >> k; while (k--) { w = 0; cin >> q; if (s.length() > q.length() + 1) { cout << NO << endl; continue; } for (i = 0; i < q.length() && i < s.length(); i++) { if (q[i] == s[i]) continue; if (s[i] == ? && mp1[q[i]] == 1) continue; if (s[i] == * ) { w = 1; v = s.length() - 1; for (u = q.length() - 1; v > i && u >= i; u--, v--) { if (q[u] == s[v]) continue; if (s[v] == ? && mp1[q[u]] == 1) continue; break; } } else { cout << NO << endl; w = -1; break; } if (v != i) { w = -1; cout << NO << endl; break; } for (j = u; j >= i; j--) { if (mp1[q[j]] == 0) continue; break; } if (j >= i) { w = -1; cout << NO << endl; break; } i = q.length() - 1; } if (w == -1) continue; if (i != q.length()) { cout << NO << endl; continue; } if (s.length() == q.length() + 1 && w == 0 && s[q.length()] != * ) { cout << NO << endl; continue; } cout << YES << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct yo { int val; int id; int next, prev; }; vector<yo> a0, a; int n, n0, x; bool operator<(yo a, yo b) { return a.val < b.val; } int main() { cin >> n; n0 = n; if (n <= 2) { cout << 0; return 0; } for (int i = 0; i < n; i++) { cin >> x; yo cur; cur.val = x; cur.id = i; cur.next = i + 1; cur.prev = i - 1; a0.push_back(cur); a.push_back(cur); } sort(a.begin(), a.end()); long long v = 0, ans = 0; for (int i = 0; i < a.size() - 2; i++) { int cur_id = a[i].id; if (a0[cur_id].prev == -1) { a0[a0[cur_id].next].prev = -1; ans += (n - 2) * (a[i].val - v); v += (a[i].val - v); } else if (a0[cur_id].next == n0) { a0[a0[cur_id].prev].next = n0; ans += (n - 2) * (a[i].val - v); v += (a[i].val - v); } else { ans += min(a0[a0[cur_id].prev].val, a0[a0[cur_id].next].val) - v; a0[a0[cur_id].next].prev = a0[cur_id].prev; a0[a0[cur_id].prev].next = a0[cur_id].next; } n--; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; std::mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); inline int sj(int n) { unsigned long long x = rnd(); x = x << 32 | rnd(); return x % n + 1; } const int p = 998244353; inline void inc(int &x, const int y) { if ((x += y) >= p) x -= p; } inline void dec(int &x, const int y) { if ((x -= y) < 0) x += p; } inline int ksm(int x, int y) { int r = 1; while (y) { if (y & 1) r = (long long)r * x % p; x = (long long)x * x % p; y >>= 1; } return r; } priority_queue<int> ONLYYFORRCOPYY; priority_queue<int, vector<int>, greater<int>> ONLYYFORRCOPYY__; const int N = 1e6 + 2, M = 4e6 + 2; struct Q { int a, s; bool operator<(const Q &o) const { return max(a, s) < max(o.a, o.s) || max(a, s) == max(o.a, o.s) && (s < o.s || s == o.s && a < o.a); } }; Q a[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout << setiosflags(ios::fixed) << setprecision(15); int n, d, i, ans = 0; cin >> n >> d; for (i = 1; i <= n; i++) cin >> a[i].s >> a[i].a; sort(a + 1, a + n + 1); for (i = 1; i <= n; i++) if (d <= a[i].s) d = max(d, a[i].a), ++ans; cout << ans << endl; }
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//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : memory_testbench
// Author : Caleb Fangmeier
// Description : Testbench for the memory (RAM+FLASH) interface
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module memory_testbench (
// no I/O for the testbench
);
parameter CLK_PERIOD = 10;
integer slow_clk_cnt;
integer clk_cnt;
reg pll_ref_clk;
wire clk;
reg reset;
reg [7:0] instruction;
reg execute;
reg [7:0] bytes_to_read;
reg [7:0] write_buffer_data;
reg write_buffer_write;
reg read_buffer_read;
reg [7:0] instruction_shifter;
reg [23:0] address_shifter;
reg [7:0] data_shifter;
reg [7:0] status_out_shifter;
reg [63:0] data_out_shifter;
reg byte_complete;
wire busy;
wire [7:0] read_buffer_q;
wire read_buffer_empty;
wire flash_dq0;
wire flash_dq1;
wire flash_wb;
wire flash_holdb;
wire flash_c;
wire flash_sb;
wire sout;
reg sin;
reg memory_write_req;
reg memory_read_req;
reg [31:0] memory_data_write;
wire [31:0] memory_data_read;
reg [25:0] memory_addr;
wire memory_busy;
reg memory_program;
wire memory_program_ack;
// RAM PHY Interface
wire global_reset_n;
wire [15: 0] mem_dq;
wire [ 1: 0] mem_dqs;
wire [ 1: 0] mem_dqs_n;
wire [12: 0] mem_addr;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire mem_cke;
wire mem_clk;
wire mem_clk_n;
wire mem_cs_n;
wire [ 1: 0] mem_dm;
wire mem_odt;
wire mem_ras_n;
wire mem_we_n;
assign sout = flash_dq0;
assign flash_dq1 = sin;
initial pll_ref_clk = 1'b0;
always #( CLK_PERIOD/2.0 )
pll_ref_clk = ~pll_ref_clk;
initial slow_clk_cnt = 0;
initial clk_cnt = 0;
initial reset = 1'b1;
always @(posedge pll_ref_clk) begin
slow_clk_cnt = slow_clk_cnt + 1;
if ( slow_clk_cnt == 2 )
reset <= 1'b0;
end
initial memory_program = 1;
always @( posedge clk ) begin
if ( memory_program_ack ) begin
memory_program <= 0;
end
end
integer flash_clk_cnt;
integer bytes_received;
always @(posedge flash_c or negedge flash_c) begin
if ( flash_sb ) begin
instruction_shifter <= 0;
data_shifter <= 0;
address_shifter <= 0;
flash_clk_cnt <= 0;
byte_complete <= 0;
bytes_received <= 0;
status_out_shifter <= 8'hAA;
data_out_shifter <= 64'h00_00_00_02__AB_CD_EF_FF;
end
else begin
if ( flash_c ) begin
flash_clk_cnt <= flash_clk_cnt + 1;
if ( flash_clk_cnt < 8 ) begin
instruction_shifter <= {instruction_shifter[6:0], sout};
end
else begin
case ( instruction_shifter )
8'b0000_0010: begin
if ( flash_clk_cnt < 32 ) begin
address_shifter <= {address_shifter[23:0], sout};
end
else begin
data_shifter <= {data_shifter[6:0], sout};
end
if ( ((flash_clk_cnt+1) % 8) == 0 ) begin
byte_complete <= 1;
bytes_received <= bytes_received + 1;
end
else begin
byte_complete <= 0;
end
end
8'b0000_0011: begin
if ( flash_clk_cnt < 32 ) begin
address_shifter <= {address_shifter[23:0], sout};
end
if ( ((flash_clk_cnt+1) % 8) == 0 ) begin
byte_complete <= 1;
bytes_received <= bytes_received + 1;
end
else begin
byte_complete <= 0;
end
end
endcase
end
end
else begin
case ( instruction_shifter )
8'b0000_0101: begin
sin <= status_out_shifter[7];
status_out_shifter <= {status_out_shifter[6:0], status_out_shifter[7]};
end
8'b0000_0011: begin
if ( flash_clk_cnt >= 32 ) begin
sin <= data_out_shifter[63];
data_out_shifter <= {data_out_shifter[62:0], data_out_shifter[63]};
end
end
endcase
end
end
end
wire program_buffer_empty;
reg [31:0] program_buffer_q;
wire program_buffer_read;
reg [3:0] program_buffer_pointer;
reg [31:0] program_buffer_array[15:0];
assign program_buffer_empty = 0;
initial begin
program_buffer_pointer <= 0;
program_buffer_array[00] <= 32'd2;
program_buffer_array[01] <= 32'hDEADBEEF;
program_buffer_array[02] <= 32'hDEADBEEF;
program_buffer_array[03] <= 32'hDEADBEEF;
program_buffer_array[04] <= 32'hDEADBEEF;
program_buffer_array[05] <= 32'hDEADBEEF;
program_buffer_array[06] <= 32'hDEADBEEF;
program_buffer_array[07] <= 32'hDEADBEEF;
program_buffer_array[08] <= 32'hDEADBEEF;
program_buffer_array[09] <= 32'hDEADBEEF;
program_buffer_array[10] <= 32'hDEADBEEF;
program_buffer_array[11] <= 32'hDEADBEEF;
program_buffer_array[12] <= 32'hDEADBEEF;
program_buffer_array[13] <= 32'hDEADBEEF;
program_buffer_array[14] <= 32'hDEADBEEF;
program_buffer_array[15] <= 32'hDEADBEEF;
end
always @( negedge clk ) begin
if ( program_buffer_read ) begin
program_buffer_q <= program_buffer_array[program_buffer_pointer];
program_buffer_pointer <= program_buffer_pointer+1;
end
end
ram_controller_mem_model ram_controller_mem_model_inst (
.mem_addr ( mem_addr ),
.mem_ba ( mem_ba ),
.mem_cas_n ( mem_cas_n ),
.mem_cke ( mem_cke ),
.mem_clk ( mem_clk ),
.mem_clk_n ( mem_clk_n ),
.mem_cs_n ( mem_cs_n ),
.mem_dm ( mem_dm ),
.mem_odt ( mem_odt ),
.mem_ras_n ( mem_ras_n ),
.mem_we_n ( mem_we_n ),
.global_reset_n ( global_reset_n ),
.mem_dq ( mem_dq ),
.mem_dqs ( mem_dqs ),
.mem_dqs_n ( mem_dqs_n )
);
memory memory_inst(
.pll_ref_clk ( pll_ref_clk ),
.phy_clk ( clk ),
.reset ( reset ),
.write_req ( memory_write_req ),
.read_req ( memory_read_req ),
.data_write ( memory_data_write ),
.data_read ( memory_data_read ),
.addr ( memory_addr ),
.busy ( memory_busy ),
.mem_addr ( mem_addr ),
.mem_ba ( mem_ba ),
.mem_cas_n ( mem_cas_n ),
.mem_cke ( mem_cke ),
.mem_clk ( mem_clk ),
.mem_clk_n ( mem_clk_n ),
.mem_cs_n ( mem_cs_n ),
.mem_dm ( mem_dm ),
.mem_dq ( mem_dq ),
.mem_dqs ( mem_dqs ),
.mem_odt ( mem_odt ),
.mem_ras_n ( mem_ras_n ),
.mem_we_n ( mem_we_n ),
.flash_dq0 ( flash_dq0 ),
.flash_dq1 ( flash_dq1 ),
.flash_wb ( flash_wb ),
.flash_holdb ( flash_holdb ),
.flash_c ( flash_c ),
.flash_sb ( flash_sb ),
.program ( memory_program ),
.program_ack ( memory_program_ack ),
.program_buffer_empty ( program_buffer_empty ),
.program_buffer_q ( program_buffer_q ),
.program_buffer_read ( program_buffer_read )
);
endmodule
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#include <bits/stdc++.h> using namespace std; int mp[200005]; int a[200005]; int n; int main() { int y, T, n, m, i, t, j, k, x; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &x); mp[x] = i + 1; } for (i = 0; i < n; i++) { scanf( %d , &x); a[i] = mp[x]; } int c = 1; int ans = 0; for (i = 0; i < n; i++) { if (a[i] == c) { c++; ans++; } } printf( %d n , n - ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int wyn[1024]; int odp[1024]; int n; int pyt; vector<pair<int, int> > v[2]; void pytaj(vector<int>& skad, vector<int>& gdzie) { if (skad.size() == 0) return; printf( %d n , int(skad.size())); for (int i = 0; i < skad.size(); i++) printf( %d , skad[i] + 1); printf( n ); fflush(stdout); for (int i = 0; i < n; i++) scanf( %d , &odp[i]); pyt++; for (int q = 0; q < gdzie.size(); q++) { int i = gdzie[q]; wyn[i] = min(wyn[i], odp[i]); } } int main() { pyt = 0; scanf( %d , &n); for (int i = 0; i < n; i++) wyn[i] = 1000000010; v[0].push_back(make_pair(0, n - 1)); int akt = 0; while (!v[akt].empty()) { v[1 - akt].clear(); vector<int> pyt1, pyt2; for (int k = 0; k < v[akt].size(); k++) { int a = v[akt][k].first; int b = v[akt][k].second; int sr = (a + b) / 2; for (int q = a; q <= sr; q++) pyt1.push_back(q); for (int q = sr + 1; q <= b; q++) pyt2.push_back(q); if (sr > a) v[1 - akt].push_back(make_pair(a, sr)); if (b > sr + 1) v[1 - akt].push_back(make_pair(sr + 1, b)); } pytaj(pyt1, pyt2); pytaj(pyt2, pyt1); akt = 1 - akt; } printf( -1 n ); for (int i = 0; i < n; i++) printf( %d , wyn[i]); printf( n ); fflush(stdout); }
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#include <bits/stdc++.h> using namespace std; const int N = 100000 + 9; const int Mod = 1000000007; long long n, d, b; long long a[N]; int main() { cin >> n >> d >> b; for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i]); } for (int i = 1; i <= n; i++) a[i] = a[i - 1] + a[i]; long long L = 0, R = 0, Lans = 0, Rans = 0; for (int i = 1; i <= (n + 1) / 2; i++) { if (a[min(n, (d + 1) * i)] >= (L + 1) * b) L++; else Lans++; } for (int i = n; i > n - (n + 1) / 2; i--) { if (a[n] - a[max(0ll, i - (n - i + 1) * d - 1)] >= (R + 1) * b) R++; else Rans++; } cout << max(Lans, Rans) << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:14:43 07/04/2013
// Design Name:
// Module Name: serializer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serializer(
input clk,
input clk35,
input notclk35,
input [6:0] data,
input rst,
output out
);
reg [6:0] buffer [1:0]; // 14 bits buffer
reg [1:0] shiftdata = 0;
reg datacount = 0;
reg [2:0] outcount = 0;
reg DataInBuffer = 0;
reg SendOK = 0;
ODDR2 #(
.DDR_ALIGNMENT("NONE") // Sets output alignment to "NONE", "C0" or "C1"
) clock_forward_inst (
.Q(out), // 1-bit DDR output data
.C0(clk35), // 1-bit clock input
.C1(notclk35), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(shiftdata[0]), // 1-bit data input (associated with C0)
.D1(shiftdata[1]), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
always @(posedge clk or posedge rst)
begin
if(rst == 1'b1)
begin
buffer[0] <= 7'b0000000;
buffer[1] <= 7'b0000000;
datacount <= 0;
DataInBuffer <= 0;
end
else
begin
DataInBuffer <= 1;
datacount <= datacount + 1;
buffer[datacount] <= data;
//buffer[datacount] <= {data[6],data[5],data[4],data[3],data[2],data[1],data[0]};
end
end
always @(posedge clk35 or posedge rst)
begin
if(rst == 1'b1)
begin
outcount <= 0;
shiftdata <= 0;
SendOK <= 0;
end
else
begin
if(outcount == 6)
outcount <= 0;
else
outcount <= outcount + 1;
if(DataInBuffer && outcount == 6)
SendOK <= 1;
if(SendOK)
begin
case (outcount)
0: shiftdata <= { buffer[0][0], buffer[0][1] };
1: shiftdata <= { buffer[0][2], buffer[0][3] };
2: shiftdata <= { buffer[0][4], buffer[0][5] };
3: shiftdata <= { buffer[0][6], buffer[1][0] };
4: shiftdata <= { buffer[1][1], buffer[1][2] };
5: shiftdata <= { buffer[1][3], buffer[1][4] };
6: shiftdata <= { buffer[1][5], buffer[1][6] };
endcase
end
end
end
endmodule
|
`timescale 1ns / 1ps
module tx_tb();
reg reset;
reg clock;
wire [7:0] tx_data;
wire tx_enable;
reg fifo_data_start;
reg fifo_data_end;
reg [7:0] fifo_data;
wire fifo_data_read;
reg [7:0] packet [0:1518];
reg data_available;
integer i;
tx_sm U_tx_sm (
.reset(reset),
.clock(clock),
.fifo_data(fifo_data),
.fifo_data_read(fifo_data_read),
.fifo_data_start(fifo_data_start),
.fifo_data_end(fifo_data_end),
.fifo_data_available(data_available),
.fifo_retry(retry),
.mode(1'b1),
.carrier_sense(),
.collision(),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, tx_tb);
end
initial
begin
reset = 1;
clock = 0;
fifo_data = 0;
data_available = 0;
$readmemh("packet.hex", packet);
#15 reset = 0;
// Send a packet
data_available = 1;
wait_for_read();
push(packet[8], 1, 0);
for(i = 9; i < 99; i = i + 1)
begin
push(packet[i], 0, 0);
end
push(packet[i], 0, 1);
#100
$finish;
end
always
#2 clock = ~clock;
task push;
input [7:0] data;
input data_start;
input data_end;
begin
fifo_data = data;
fifo_data_start = data_start;
fifo_data_end = data_end;
@(posedge clock);
#1 fifo_data_start = 0;
fifo_data_end = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task wait_for_read;
begin
@(posedge fifo_data_read);
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_TB_V
`define SKY130_FD_SC_LS__A32O_TB_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a32o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_TB_V
|
#include <bits/stdc++.h> #define debug(x) cout << #x << = << x << endl #define REP(i, n) for (Long i = 0; i < (Long)n; i++) using namespace std; typedef long long Long; const int MX = 3e5; vector<Long> adj[MX]; set<pair<Long,Long>> queries[MX]; Long saved[MX]; Long single[MX]; Long cnt[2 * MX + 8]; Long ans = 0; void merge(Long u, Long v, Long gU, Long gV, Long lowLimit, Long &curGroup, map<pair<Long, Long>, Long> &crossedCnt) { //u to v if (queries[saved[u]].size() > queries[saved[v]].size()) { swap(u, v); swap(gU, gV); } for (auto p : queries[saved[u]]) { Long x = p.first; auto it = queries[saved[v]].lower_bound({x, -1}); if (it != queries[saved[v]].end() && it->first == x) { pair<Long, Long> pairIndex = {p.second, it->second}; queries[saved[v]].erase(it); if (pairIndex.first < lowLimit) { pairIndex.first = gU; } if (pairIndex.second < lowLimit) { pairIndex.second = gV; } Long a = min(pairIndex.first, pairIndex.second); Long b = max(pairIndex.first, pairIndex.second); if (a != lowLimit) { crossedCnt[{a, b}]++; cnt[a]--; cnt[b]--; } else { cnt[b]--; } } else { Long gInsert = p.second; if (gInsert < lowLimit) { gInsert = gU; } queries[saved[v]].insert({x, gInsert}); } } curGroup = gV; saved[u] = saved[v]; } Long groups = 1; void dfs(Long u, Long p = -1) { Long sz = queries[u].size(); Long T = 2 * single[u] + sz; Long cur = 0; map<pair<Long, Long>, Long> crossedCnt; for (Long v : adj[u]) { if (v != p) { dfs(v, u); } } Long lowLimit = groups; groups++; Long curGroup = lowLimit;; for (Long v : adj[u]) { if (v != p) { sz = queries[saved[v]].size(); T += sz; cur -= sz * (sz - 1) / 2; Long g = groups++; cnt[g] += sz; Long gU = curGroup; merge(u, v, gU, g, lowLimit, curGroup, crossedCnt); } } sz = queries[saved[u]].size(); T += sz; cur -= sz * (sz - 1) / 2; assert(T % 2 == 0); T /= 2; cur += T * (T - 1) / 2; for (auto crossed : crossedCnt) { sz = crossed.second; cur += sz * (sz - 1) / 2; } for (Long i = lowLimit + 1; i < groups; i++) { cur += cnt[i] * (cnt[i] - 1) / 2; } ans += cur; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); Long n; cin >> n; REP(i , n - 1) { Long u, v; cin >> u >> v; u--; v--; adj[u].push_back(v); adj[v].push_back(u); } REP(i , n) { saved[i] = i; } Long m; cin >> m; REP(i, m) { Long u , v; cin >> u >> v; u--; v--; if (u != v) { queries[u].insert({i, 0}); queries[v].insert({i, 0}); } else { single[u]++; } } dfs(0); assert(groups <= 2 * n); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a = 1; int b = 2; bool ok = true; int k; for (int i = 0; i < n; i++) { cin >> k; if (k != a && k != b) { ok = false; } else { if (b == 3 && a == 1) { a = min(2, k); b = max(2, k); } else if (b == 2 && a == 1) { a = min(3, k); b = max(3, k); } else if (b == 3 && a == 2) { a = min(1, k); b = max(1, k); } } } if (ok) { cout << YES ; } else { cout << NO ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int val, lazy, child; node() { val = child = 0; lazy = 1e9 + 7; } node(int vval, int llazy, int cchild) { val = vval; lazy = llazy; child = cchild; } }; int N, K, Q; int w, x, y, z; int arr[100100]; int stree[4 * 100100]; vector<node> tree; int counter, c1, c2; int squery(int n, int l, int r, int ql, int qr) { if (l > qr || r < ql) { return 1e9 + 7; } else if (ql <= l && r <= qr) { return stree[n]; } else { return min(squery(2 * n, l, (l + r) / 2, ql, qr), squery(2 * n + 1, (l + r) / 2 + 1, r, ql, qr)); } } void propogate(int n) { tree[tree[n].child].val = tree[n].lazy; tree[tree[n].child + 1].val = tree[n].lazy; tree[tree[n].child].lazy = tree[n].lazy; tree[tree[n].child + 1].lazy = tree[n].lazy; tree[n].lazy = 1e9 + 7; } void update(int n, int l, int r, int ql, int qr, int q) { if (tree[n].child == 0) { tree[n].child = counter; counter += 2; tree.push_back(node()); tree.push_back(node()); } if (tree[n].lazy != 1e9 + 7 && l != r) { propogate(n); } if (l > qr || r < ql) { if (tree[n].val == 0) { if ((r - l + 1) >= N) { tree[n].val = squery(1, 1, N, 1, N); } else { c1 = l % N; c2 = r % N; if (c1 == 0) { c1 = N; } if (c2 == 0) { c2 = N; } if (c1 <= c2) { tree[n].val = squery(1, 1, N, c1, c2); } else { tree[n].val = min(squery(1, 1, N, c1, N), squery(1, 1, N, 1, c2)); } } } return; } else if (ql <= l && r <= qr) { tree[n].val = tree[n].lazy = q; return; } else { update(tree[n].child, l, (l + r) / 2, ql, qr, q); update(tree[n].child + 1, (l + r) / 2 + 1, r, ql, qr, q); tree[n].val = min(tree[tree[n].child].val, tree[tree[n].child + 1].val); } } int query(int n, int l, int r, int ql, int qr) { if (tree[n].child == 0) { tree[n].child = counter; counter += 2; tree.push_back(node()); tree.push_back(node()); } if (tree[n].val == 0) { if ((r - l + 1) >= N) { tree[n].val = squery(1, 1, N, 1, N); } else { c1 = l % N; c2 = r % N; if (c1 == 0) { c1 = N; } if (c2 == 0) { c2 = N; } if (c1 <= c2) { tree[n].val = squery(1, 1, N, c1, c2); } else { tree[n].val = min(squery(1, 1, N, c1, N), squery(1, 1, N, 1, c2)); } } } if (tree[n].lazy != 1e9 + 7 && l != r) { propogate(n); } if (l > qr || r < ql) { return 1e9 + 7; } else if (ql <= l && r <= qr) { return tree[n].val; } else { return min(query(tree[n].child, l, (l + r) / 2, ql, qr), query(tree[n].child + 1, (l + r) / 2 + 1, r, ql, qr)); } } void buildtree(int n, int l, int r) { if (l == r) { stree[n] = arr[l]; return; } else { buildtree(2 * n, l, (l + r) / 2); buildtree(2 * n + 1, (l + r) / 2 + 1, r); stree[n] = min(stree[2 * n], stree[2 * n + 1]); } } int main() { cin >> N >> K; for (int i = 1; i <= N; i++) { cin >> arr[i]; } buildtree(1, 1, N); counter = 1; tree.push_back(node()); cin >> Q; for (int i = 0; i < Q; i++) { cin >> w; if (w == 1) { cin >> x >> y >> z; update(0, 1, N * K, x, y, z); } else { cin >> x >> y; cout << query(0, 1, N * K, x, y) << endl; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFBBP_PP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int dr[]{-1, -1, 0, 1, 1, 1, 0, -1}; const int dc[]{0, 1, 1, 1, 0, -1, -1, -1}; void run() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const int sqrtQ = 150; struct suffix_automaton { struct state { int len, link = 0, cnt = 0; bool terminal = false, is_clone = false; vector<int> nxt; state(int len = 0) : len(len), nxt(26, -1) {} bool have_next(char ch) { return nxt[ch - a ] != -1; } void clone(const state &other, int nlen) { len = nlen; nxt = other.nxt; link = other.link; is_clone = true; } }; vector<state> st; int last = 0; suffix_automaton() { st.push_back(state()); st[0].link = -1; } suffix_automaton(const string &s) : suffix_automaton() { for (char ch : s) extend(ch); calc_number_of_occurrences(); } void extend(char c) { int cur = st.size(); st.push_back(state(st[last].len + 1)); st[cur].cnt = 1; int p = last; last = cur; while (p != -1 && !st[p].have_next(c)) { st[p].nxt[c - a ] = cur; p = st[p].link; } if (p == -1) return; int q = st[p].nxt[c - a ]; if (st[p].len + 1 == st[q].len) { st[cur].link = q; return; } int clone = st.size(); st.push_back(state()); st[clone].clone(st[q], st[p].len + 1); while (p != -1 && st[p].nxt[c - a ] == q) { st[p].nxt[c - a ] = clone; p = st[p].link; } st[q].link = st[cur].link = clone; } void calc_number_of_occurrences() { vector<vector<int>> lvl(st[last].len + 1); for (int i = 1; i < st.size(); i++) lvl[st[i].len].push_back(i); for (int i = st[last].len; i >= 0; i--) for (auto cur : lvl[i]) st[st[cur].link].cnt += st[cur].cnt; } int count(const string &y) { int cur = 0; for (auto &it : y) { if (!st[cur].have_next(it)) return 0; cur = st[cur].nxt[it - a ]; } return st[cur].cnt; } } SA[(int)1e4]; string y; vector<int> longestPrefix; vector<int> Fail[26]; int fail(int k, char nxt) { int &rt = Fail[nxt - a ][k]; if (~rt) return rt; while (k > 0 && y[k] != nxt) k = longestPrefix[k - 1]; if (nxt == y[k]) k++; return rt = k; } void failure_function() { int n = y.size(); longestPrefix = vector<int>(n); for (int i = 0; i < 26; i++) Fail[i] = vector<int>(n + 1, -1); for (int i = 1, k = 0; i < n; i++) longestPrefix[i] = k = fail(k, y[i]); } int main() { run(); string s; int q; cin >> s >> q; for (int i = 0; i < (int)(s.size()); i += sqrtQ) SA[i / sqrtQ] = suffix_automaton(s.substr(i, sqrtQ)); auto solve = [&](int l, int r) { int match = 0, cnt = 0; for (int i = l; i <= r; i++) { match = fail(match, s[i]); if (match == (int)(y.size())) { cnt++; match = longestPrefix[match - 1]; } } return cnt; }; while (q--) { int t; cin >> t; if (t == 1) { int idx; char ch; cin >> idx >> ch; idx--; s[idx] = ch; SA[idx / sqrtQ] = suffix_automaton(s.substr(idx / sqrtQ * sqrtQ, sqrtQ)); } else { int l, r; cin >> l >> r >> y; l--, r--; failure_function(); if ((int)(y.size()) >= sqrtQ || r - l <= 2 * sqrtQ) { cout << solve(l, r) << n ; continue; } int ans = 0, len = (int)(y.size()); int st = l / sqrtQ, ed = r / sqrtQ; for (int i = st + 1; i <= ed; i++) ans += solve(max(l, i * sqrtQ - len + 1), min(r, i * sqrtQ + len - 2)); for (int i = st + 1; i < ed; i++) ans += SA[i].count(y); ans += solve(l, (st + 1) * sqrtQ - 1); ans += solve(ed * sqrtQ, r); cout << ans << n ; } } }
|
#include <bits/stdc++.h> int main() { int a, b, c, d, flag = 0; scanf( %d %d %d %d , &a, &b, &c, &d); if (a + b > c && b + c > a && c + a > b) flag = 1; else if (b + c > d && c + d > b && d + b > c) flag = 1; else if (c + d > a && d + a > c && a + c > d) flag = 1; else if (a + b > d && b + d > a && d + a > b) flag = 1; if (flag == 1) printf( TRIANGLE ); else { if (a + b == c || b + c == a || c + a == b) flag = 2; else if (b + c == d || c + d == b || d + b == c) flag = 2; else if (c + d == a || d + a == c || a + c == d) flag = 2; else if (a + b == d || b + d == a || d + a == b) flag = 2; } if (flag == 2) printf( SEGMENT ); else if (flag == 0) printf( IMPOSSIBLE ); }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_pre_norm_mul ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// pre-normalization entity for the multiplication unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module fpu_pre_norm_mul (
clk,
rst,
opa_i,
opb_i,
exp_10_o,
fracta_24_o,
fractb_24_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk;
input rst;
input [FP_WIDTH-1:0] opa_i;
input [FP_WIDTH-1:0] opb_i;
output reg [EXP_WIDTH+1:0] exp_10_o;
output [FRAC_WIDTH:0] fracta_24_o;
output [FRAC_WIDTH:0] fractb_24_o;
wire [EXP_WIDTH-1:0] s_expa;
wire [EXP_WIDTH-1:0] s_expb;
wire [FRAC_WIDTH-1:0] s_fracta;
wire [FRAC_WIDTH-1:0] s_fractb;
wire [EXP_WIDTH+1:0] s_exp_10_o;
wire [EXP_WIDTH+1:0] s_expa_in;
wire [EXP_WIDTH+1:0] s_expb_in;
wire s_opa_dn, s_opb_dn;
assign s_expa = opa_i[30:23];
assign s_expb = opb_i[30:23];
assign s_fracta = opa_i[22:0];
assign s_fractb = opb_i[22:0];
// Output Register
always @(posedge clk or posedge rst)
if (rst)
exp_10_o <= 'd0;
else
exp_10_o <= s_exp_10_o;
// opa or opb is denormalized
assign s_opa_dn = !(|s_expa);
assign s_opb_dn = !(|s_expb);
assign fracta_24_o = {!s_opa_dn, s_fracta};
assign fractb_24_o = {!s_opb_dn, s_fractb};
assign s_expa_in = {2'd0, s_expa} + {9'd0, s_opa_dn};
assign s_expb_in = {2'd0, s_expb} + {9'd0, s_opb_dn};
assign s_exp_10_o = s_expa_in + s_expb_in - 10'b0001111111;
endmodule // fpu_pre_norm_mul
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v; int n, x, temp, cntr = 0; cin >> n >> x; while (n--) { cin >> temp; v.push_back(temp); } sort(v.begin(), v.end()); while (v[(v.size() - 1) / 2] != x) { cntr++; v.push_back(x); sort(v.begin(), v.end()); } cout << cntr; }
|
#include <bits/stdc++.h> using namespace std; const int N = 28; vector<int> g[N]; int vis[2000000]; int main() { int k, n; string ss, s; cin >> k >> ss; for (int i = 0; i < k; ++i) s += ss; for (int i = 0; i != s.size(); ++i) g[s[i] - a ].push_back(i); cin >> n; vector<int>::iterator it; for (int i = 0; i < n; ++i) { cin >> k >> ss; it = g[ss[0] - a ].begin(); g[ss[0] - a ].erase(it + k - 1); } memset(vis, 0, sizeof(vis)); for (int i = 0; i < 26; ++i) for (int j = 0; j < g[i].size(); ++j) vis[g[i][j]] = 1; for (int i = 0; i != s.size(); ++i) if (vis[i]) cout << s[i]; return 0; }
|
/*
reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
*/
module mem_tester(
clk,
rst_n,
// pass/fail counters
pass_counter,
fail_counter,
// DRAM signals
DRAM_DQ,
DRAM_MA,
DRAM_RAS0_N,
DRAM_RAS1_N,
DRAM_LCAS_N,
DRAM_UCAS_N,
DRAM_WE_N
);
parameter DRAM_DATA_SIZE = 16;
parameter DRAM_MA_SIZE = 10;
inout [DRAM_DATA_SIZE-1:0] DRAM_DQ;
output [DRAM_MA_SIZE-1:0] DRAM_MA;
output DRAM_RAS0_N,DRAM_RAS1_N,DRAM_LCAS_N,DRAM_UCAS_N,DRAM_WE_N;
input clk;
input rst_n;
reg inc_pass_ctr;
reg inc_err_ctr;
reg check_in_progress; // when 1 - enables errors checking
//----
reg [15:0] pass_counter;
output [15:0] pass_counter;
reg [15:0] fail_counter;
output [15:0] fail_counter;
reg was_error;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
pass_counter <= 16'd0;
fail_counter <= 16'd0;
end
else if( inc_pass_ctr )
begin
if( (!was_error)&&(pass_counter!=16'hffff) )
pass_counter <= pass_counter + 16'd1;
if( (was_error)&&(fail_counter!=16'hffff) )
fail_counter <= fail_counter + 16'd1;
was_error <= 1'b0;
end
else if( inc_err_ctr )
was_error <= 1'b1;
end
//----
reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
wire [DRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(ram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
defparam my_rnd.OUT_SIZE = DRAM_DATA_SIZE;
defparam my_rnd.LFSR_LENGTH = 17;
defparam my_rnd.LFSR_FEEDBACK = 14;
reg ram_start,ram_rnw;
wire ram_stop,ram_ready;
wire [DRAM_DATA_SIZE-1:0] ram_rdat;
dram_control my_ram( .clk(clk), .start(ram_start), .rnw(ram_rnw), .stop(ram_stop), .ready(ram_ready),
.rdat(ram_rdat), .wdat(rnd_out),
.DRAM_DQ(DRAM_DQ), .DRAM_MA(DRAM_MA), .DRAM_RAS0_N(DRAM_RAS0_N), .DRAM_RAS1_N(DRAM_RAS1_N),
.DRAM_LCAS_N(DRAM_LCAS_N), .DRAM_UCAS_N(DRAM_UCAS_N), .DRAM_WE_N(DRAM_WE_N) );
// FSM states and registers
reg [3:0] curr_state,next_state;
parameter RESET = 4'h0;
parameter INIT1 = 4'h1;
parameter INIT2 = 4'h2;
parameter BEGIN_WRITE1 = 4'h3;
parameter BEGIN_WRITE2 = 4'h4;
parameter BEGIN_WRITE3 = 4'h5;
parameter BEGIN_WRITE4 = 4'h6;
parameter WRITE = 4'h7;
parameter BEGIN_READ1 = 4'h8;
parameter BEGIN_READ2 = 4'h9;
parameter BEGIN_READ3 = 4'hA;
parameter BEGIN_READ4 = 4'hB;
parameter READ = 4'hC;
parameter END_READ = 4'hD;
parameter INC_PASSES1 = 4'hE;
parameter INC_PASSES2 = 4'hF;
// FSM dispatcher
always @*
begin
case( curr_state )
RESET:
next_state <= INIT1;
INIT1:
next_state <= INIT2;
INIT2:
if( ram_stop )
next_state <= BEGIN_WRITE1;
else
next_state <= INIT2;
BEGIN_WRITE1:
next_state <= BEGIN_WRITE2;
BEGIN_WRITE2:
next_state <= BEGIN_WRITE3;
BEGIN_WRITE3:
next_state <= BEGIN_WRITE4;
BEGIN_WRITE4:
if( ram_stop )
next_state <= BEGIN_WRITE4;
else
next_state <= WRITE;
WRITE:
if( ram_stop )
next_state <= BEGIN_READ1;
else
next_state <= WRITE;
BEGIN_READ1:
next_state <= BEGIN_READ2;
BEGIN_READ2:
next_state <= BEGIN_READ3;
BEGIN_READ3:
next_state <= BEGIN_READ4;
BEGIN_READ4:
if( ram_stop )
next_state <= BEGIN_READ4;
else
next_state <= READ;
READ:
if( ram_stop )
next_state <= END_READ;
else
next_state <= READ;
END_READ:
next_state <= INC_PASSES1;
INC_PASSES1:
next_state <= INC_PASSES2;
INC_PASSES2:
next_state <= BEGIN_WRITE1;
default:
next_state <= RESET;
endcase
end
// FSM sequencer
always @(posedge clk,negedge rst_n)
begin
if( !rst_n )
curr_state <= RESET;
else
curr_state <= next_state;
end
// FSM controller
always @(posedge clk)
begin
case( curr_state )
//////////////////////////////////////////////////
RESET:
begin
// various initializings begin
inc_pass_ctr <= 1'b0;
check_in_progress <= 1'b0;
rnd_init <= 1'b1; //begin RND init
rnd_save <= 1'b0;
rnd_restore <= 1'b0;
ram_start <= 1'b1;
ram_rnw <= 1'b1;
end
INIT1:
begin
rnd_init <= 1'b0; // end rnd init
ram_start <= 1'b0;
end
INIT2:
begin
end
//////////////////////////////////////////////////
BEGIN_WRITE1:
begin
rnd_save <= 1'b1;
end
BEGIN_WRITE2:
begin
rnd_save <= 1'b0;
ram_start <= 1'b1;
ram_rnw <= 1'b0;
end
BEGIN_WRITE3:
begin
ram_start <= 1'b0;
end
/* BEGIN_WRITE4:
begin
rnd_save <= 1'b0;
ram_start <= 1'b1;
end
*/
/* WRITE:
begin
ram_start <= 1'b0;
end
*/
//////////////////////////////////////////////////
BEGIN_READ1:
begin
rnd_restore <= 1'b1;
end
BEGIN_READ2:
begin
rnd_restore <= 1'b0;
ram_start <= 1'b1;
ram_rnw <= 1'b1;
end
BEGIN_READ3:
begin
ram_start <= 1'b0;
end
BEGIN_READ4:
begin
check_in_progress <= 1'b1;
end
/*
READ:
begin
ram_start <= 1'b0;
check_in_progress <= 1'b1;
end
*/
END_READ:
begin
check_in_progress <= 1'b0;
end
INC_PASSES1:
begin
inc_pass_ctr <= 1'b1;
end
INC_PASSES2:
begin
inc_pass_ctr <= 1'b0;
end
endcase
end
always @(posedge clk)
inc_err_ctr <= check_in_progress & ram_ready & ((ram_rdat==rnd_out) ? 1'b0: 1'b1);
endmodule
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