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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [83:4] from;
reg [83:4] to;
reg [6:0] bitn;
reg [3:0] nibblep;
reg [3:0] nibblem;
reg [7:0] cyc; initial cyc = 0;
always @* begin
nibblep = from[bitn +: 4];
nibblem = from[bitn -: 4];
to = from;
to[bitn +: 4] = cyc[3:0];
to[bitn -: 4] = cyc[3:0];
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n", $time, cyc, nibblep, nibblem, from^to);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end
8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end
8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -:
8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end
8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +:
8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc
8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc
8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end
8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate
8'd09: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
8'd00: ;
8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end
8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end
8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end
8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end
8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end
8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end
8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
default: $stop;
endcase
case (cyc)
8'd00: ;
8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end
8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end
8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end
8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end
8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0
8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0
8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end
8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end
8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end
default: $stop;
endcase
end
// Additional constant folding check - this used to trigger a bug
reg [23:0] a;
reg [3:0] b;
initial begin
a = 24'd0;
b = 4'b0111;
a[3*(b[2:0]+0)+:3] = 3'd7; // Check LSB expression goes to 32-bits
if (a != 24'b11100000_00000000_00000000) $stop;
a = 24'd0;
b = 4'b0110;
a[3*(b[2:0]+0)-:3] = 3'd7; // Check MSB expression goes to 32-bits
if (a != 24'b00000111_00000000_00000000) $stop;
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 3: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 3: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 3: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1000005]; int main() { int n; while (cin >> n) { for (int i = n; i >= 0; i--) if (!a[i]) { int mm = (1 << ((int)(log2(i) + 1))) - 1; a[i] = mm ^ i; a[mm ^ i] = i; } long long int ans = 0; for (int i = 0; i <= n; i++) { ans += a[i] ^ i; } cout << ans << endl; for (int i = 0; i <= n; i++) { cout << a[i]; if (i != n) cout << ; else cout << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); int n, k; cin >> n >> k; if ((n - 1) / 2 < k) cout << -1 << n ; else { cout << (n * k) << n ; ; for (int i = 1; i <= n; i++) for (int j = 0; j < k; j++) cout << i << << (i + j) % n + 1 << n ; ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtp (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, GATE, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_V
|
module DDS(
clk,
reset,
key_s4,
clk_25M,
out_wave,
choose
);
parameter WIDTH = 8;
parameter N = 16;
input [2:0] choose;
input key_s4;
reg [N-1:0] data;
input clk;
input reset;
output [WIDTH-1:0] out_wave;
reg [WIDTH-1:0] sine;
reg [WIDTH-1:0] AM;
reg [WIDTH-1:0] FM;
reg [WIDTH-1:0] ASK;
reg [WIDTH-1:0] FSK;
reg [WIDTH-1:0] out_wave;
output clk_25M;
reg [N-1:0] ADD_A;
reg [N-1:0] ADD_B;
reg [N-1:0] ADD_C;
reg [N-1:0] ADD_D;
wire [WIDTH-1:0] sine_D;
wire [WIDTH-1:0] sine_D_high;
wire [WIDTH-1:0] FM_D;
wire [WIDTH-1:0] AM_D;
wire [WIDTH-1:0] ROM_Address;
wire [WIDTH-1:0] ROM_Address_high;
assign ROM_Address = ADD_B[N-1:N-WIDTH];
assign ROM_Address_high = ADD_D[N-1:N-WIDTH];
reg clk_25M;
reg clk_4;
reg clk_3;
integer count;
integer count2;
initial
begin
clk_4 <= 0;
clk_3 <= 0;
clk_25M <= 0;
count = 0;
data = 16'h0080;
count2 = 0;
ASK <= 0;
FSK <= 0;
end
always @ (posedge clk_4 or negedge reset)
begin
if(!reset)
begin
ADD_A <= 0;
ADD_B <= 0;
sine <= 0;
AM <= 0;
FM <= 0;
end
else
begin
ADD_A <= data;
ADD_B <= ADD_B + ADD_A;
sine <= sine_D;
AM <= AM_D;
FM <= FM_D;
end
end
sine_ROM sine_ROM_inst (
.address ( ROM_Address ),
.clock ( clk_4 ),
.q ( sine_D )
);
AM_ROM AM_ROM_inst (
.address ( ROM_Address ),
.clock ( clk_4 ),
.q ( AM_D )
);
FM_ROM FM_ROM_inst (
.address ( ROM_Address ),
.clock ( clk_4 ),
.q ( FM_D )
);
sine_ROM sine_ROM_high_inst (
.address ( ROM_Address_high ),
.clock ( clk_3 ),
.q ( sine_D_high )
);
always @ (posedge clk)
begin
if(count >= 9)
begin
count <= 0;
clk_4 <= ~clk_4;
end
else count <= count+1;
end
always @ (posedge clk)
begin
if(count2 >= 4)
begin
count2 <= 0;
clk_3 <= ~clk_3;
end
else count2 <= count2+1;
end
always @ (posedge clk)
clk_25M <= ~clk_25M;
always @ (posedge clk_25M)
case (choose)
3'b000:out_wave <= sine;
3'b001:out_wave <= AM;
3'b010:out_wave <= FM;
3'b011:out_wave <= ASK;
3'b100:out_wave <= FSK;
default:out_wave <= 0;
endcase
always @ (posedge clk_3 or negedge reset)
begin
if(!reset)
begin
ADD_C <= 0;
ADD_D <= 0;
end
else
begin
ADD_C <= data;
ADD_D <= ADD_D + ADD_C;
end
end
always @ (posedge clk_4)
begin
if (key_s4)
ASK <= sine_D;
else
ASK <= 0;
end
always @ (posedge clk_3)
begin
if (key_s4)
FSK <= sine_D_high;
else
FSK <= sine_D;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, K; vector<int> tabs; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> N >> K; tabs.resize(N); for (int i = 0; i < N; i++) cin >> tabs[i]; int most = 0; for (int b = 0; b < N; b++) { int sum = 0; for (int i = 0; i < N; i++) if (i % K != b % K) sum += tabs[i]; most = max(most, abs(sum)); } cout << most << n ; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_pll_diff_tx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example differential output transmitter for clock and data using PLL
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_pll_diff_tx (
input reset, // reset (active high)
input refclkin_p, refclkin_n, // frequency generator clock input
output [5:0] dataout_p, dataout_n, // lvds data outputs
output clkout_p, clkout_n) ; // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 7 ; // Set the serdes factor
parameter integer D = 6 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
reg [DS:0] txd ; // Registered Data to serdeses
// Parameters for clock generation
parameter [S-1:0] TX_CLK_GEN = 7'b1100001 ; // Transmit a constant to make a clock
assign rst = reset ; // active high reset pin
// Reference Clock Input genertaes IO clocks via 2 x BUFIO2
clock_generator_pll_s8_diff #(
.S (S),
.PLLX (7),
.PLLD (1),
.CLKIN_PERIOD (7.000))
inst_clkgen(
.reset (rst),
.clkin_p (refclkin_p),
.clkin_n (refclkin_n),
.ioclk (tx_bufpll_clk_xn),
.serdesstrobe (tx_serdesstrobe),
.gclk (tx_bufg_x1),
.bufpll_lckd (tx_bufpll_lckd)) ;
always @ (posedge tx_bufg_x1 or posedge rst) // Generate some data to transmit
begin
if (rst == 1'b1) begin
txd <= 42'h00000000001 ;
end
else begin
txd <= {txd[40:0], txd[41]} ;
end
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_s8_diff #(
.S (S),
.D (1))
inst_clkout (
.dataout_p (clkout_p),
.dataout_n (clkout_n),
.txioclk (tx_bufpll_clk_xn),
.txserdesstrobe (tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_s8_diff #(
.S (S),
.D (D))
inst_dataout (
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclk (tx_bufpll_clk_xn),
.txserdesstrobe (tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (txd));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_2_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_2_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s15 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s15.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University at Buffalo
// Engineer: Mahalakshmi Venkataraman
//
// Create Date: 12:34:32 06/12/2015
// Design Name: CSE 590 Proj 1
// Module Name: pa1
// Project Name: SSD
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module proj(
input [3:0] switches,
input [3:0] pushbtns,
input clk,
output [3:0] final_led,
output [6:0] final,
output [3:0] final_enable
);
reg [17:0] counter;
reg [3:0] temp_led;
reg [3:0] temp_enable = 4'b1111;
reg [6:0] temp_ssd=7'b1111111;
reg [6:0] ssd_1=7'b1111111;
reg [6:0] ssd_2=7'b1111111;
reg [6:0] ssd_3=7'b1111111;
reg [6:0] ssd_4=7'b1111111;
reg [6:0] final_ssd=7'b1111111;
always @ (switches) begin
if(switches==4'b0000)
begin
temp_led = 'h0;
temp_ssd = 7'b1000000;
end
else if(switches==4'b0001)
begin
temp_led = 'h1;
temp_ssd = 7'b1111001;
end
else if(switches==4'b0010)
begin
temp_led = 'h2;
temp_ssd = 7'b0100100;
end
else if(switches==4'b0011)
begin
temp_led = 'h3;
temp_ssd = 7'b0110000;
end
else if(switches==4'b0100)
begin
temp_led = 'h4;
temp_ssd = 7'b0011001;
end
else if(switches==4'b0101)
begin
temp_led = 'h5;
temp_ssd = 7'b0010010;
end
else if(switches==4'b0110)
begin
temp_led = 'h6;
temp_ssd = 7'b0000010;
end
else if(switches== 4'b0111)
begin
temp_led = 'h7;
temp_ssd = 7'b1111000;
end
else if(switches== 4'b1000)
begin
temp_led = 'h8;
temp_ssd = 7'b0000000;
end
else if(switches== 4'b1001)
begin
temp_led = 'h9;
temp_ssd = 7'b0010000;
end
else
begin
temp_led = 4'b0000;
temp_ssd = 7'b1111111;
end
end
always @ (posedge clk) begin
if (clk)
counter = 0;
else
counter = counter + 1;
case(counter[17:16])
2'b00: begin
final_ssd = ssd_1;
temp_enable = 4'b0111;
end
2'b01: begin
final_ssd = ssd_2;
temp_enable = 4'b1011;
end
2'b10: begin
final_ssd = ssd_3;
temp_enable = 4'b1101;
end
2'b11: begin
final_ssd = ssd_4;
temp_enable = 4'b1110;
end
endcase
case(pushbtns)
4'b0001: ssd_1 = temp_ssd;
4'b0010: ssd_2 = temp_ssd;
4'b0100: ssd_3 = temp_ssd;
4'b1000: ssd_4 = temp_ssd;
endcase
end
assign final_led = temp_led;
assign final= final_ssd;
assign final_enable = temp_enable;
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[1005]; int f[1005], flag[1005], prime[1005], g[1005]; int n, num, ok[1005], k, i, id, ans, cnt, j; int main() { scanf( %s , a + 1); n = strlen(a + 1); num = 1; ok[1] = 1; for (i = 1; a[i]; i++) g[a[i] - a ]++; for (i = 2; i <= n; i++) { if (!flag[i]) if ((prime[++cnt] = i) > n / 2) ok[i] = 1, num++; for (j = 1; j <= cnt && prime[j] * i <= n; j++) flag[prime[j] * i] = 1; } for (i = 0; i < 26; i++) if (ans < g[i]) ans = g[i], id = i; num = n - num; if (ans < num) return puts( NO ), 0; puts( YES ); for (i = 1; i <= n; i++) if (!ok[i]) putchar( a + id); else { for (k = 0; k < 26; k++) if (k != id && g[k]) { putchar( a + k); g[k]--; break; } if (k == 26) putchar( a + id); } }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; int t[m], l[m], r[m]; int a[n + 1]; fill_n(a, n + 1, -1); a[0] = 1e5; for (int i = 0; i < m; i++) { cin >> t[i] >> l[i] >> r[i]; if (t[i] == 1) { for (int j = l[i] + 1; j <= r[i]; j++) { a[j] = 1; } } } for (int i = 0; i < m; i++) { if (t[i] == 0) { bool ok = false; for (int j = l[i] + 1; j <= r[i]; j++) { ok |= (a[j] == -1); } if (ok == false) { cout << NO n ; return 0; } } } cout << YES n ; for (int i = 1; i <= n; i++) { a[i] += a[i - 1]; cout << a[i] << ; } cout << n ; }
|
#include <bits/stdc++.h> using namespace std; const long long Mod = 1e9 + 7; long long powmod(long long a, long long b) { long long res = 1; a %= Mod; for (; b; b >>= 1) { if (b & 1) res = res * a % Mod; a = a * a % Mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int N = 200005; int main() { ios::sync_with_stdio(0); int t; cin >> t; while (t--) { int n; string x; cin >> n >> x; string ans[2]; bool flag = 0; for (auto ch : x) { if (ch == 0 ) { ans[0] += 0 ; ans[1] += 0 ; } if (ch == 2 ) { if (!flag) { ans[0] += 1 ; ans[1] += 1 ; } else { ans[0] += 0 ; ans[1] += 2 ; } } if (ch == 1 ) { if (!flag) { ans[0] += 1 ; ans[1] += 0 ; flag = 1; } else { ans[0] += 0 ; ans[1] += 1 ; } } } cout << ans[0] << n << ans[1] << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O221AI_BEHAVIORAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_BEHAVIORAL_PP_V
|
// Copyright 2021 The CFU-Playground Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module Cfu (
input cmd_valid,
output cmd_ready,
input [2:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input clk,
input reset
);
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
// byte sum (unsigned)
wire [31:0] cfu0;
assign cfu0[31:0] = cmd_payload_inputs_0[7:0] + cmd_payload_inputs_1[7:0] +
cmd_payload_inputs_0[15:8] + cmd_payload_inputs_1[15:8] +
cmd_payload_inputs_0[23:16] + cmd_payload_inputs_1[23:16] +
cmd_payload_inputs_0[31:24] + cmd_payload_inputs_1[31:24];
// byte swap
wire [31:0] cfu1;
assign cfu1[31:24] = cmd_payload_inputs_0[7:0];
assign cfu1[23:16] = cmd_payload_inputs_0[15:8];
assign cfu1[15:8] = cmd_payload_inputs_0[23:16];
assign cfu1[7:0] = cmd_payload_inputs_0[31:24];
// bit reverse
wire [31:0] cfu2;
genvar n;
generate
for (n=0; n<32; n=n+1) begin
assign cfu2[n] = cmd_payload_inputs_0[31-n];
end
endgenerate
// select output
assign rsp_payload_outputs_0 = cmd_payload_function_id[1] ? cfu2 :
( cmd_payload_function_id[0] ? cfu1 : cfu0);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a; cin >> b; std::reverse(a.begin(), a.end()); if (a == b) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> int n, h; int dynamics[1001][2][31][31][31]; int progress(int a) { return (a == 0 || a == h - 1) ? 0 : a + 1; } inline void add(int& a, int b, int mod) { a = (a + b) % mod; } int main(int argc, char* argv[]) { std::cin >> n >> h; if (h == 1) dynamics[1][1][0][0][0] = 4; else dynamics[1][1][1][1][1] = 4; for (int i = 1; i < n; i++) { for (int alive = 0; alive < 2; alive++) { for (int left = 0; left < h; left++) { for (int right = 0; right < h; right++) { for (int front = 0; front < h; front++) { int current = dynamics[i][alive][left][right][front]; int next_left = progress(left); int next_right = progress(right); int next_front = progress(front); add(dynamics[i + 1][alive][next_left][next_right][next_front], current, 1e9 + 9); add(dynamics[i + 1][left > 0][alive][next_right][next_front], current, 1e9 + 9); add(dynamics[i + 1][right > 0][alive][next_left][next_front], current, 1e9 + 9); add(dynamics[i + 1][front > 0][alive][next_left][next_right], current, 1e9 + 9); } } } } } int result = 0; for (int alive = 0; alive < 2; alive++) { for (int left = 0; left < h; left++) { for (int right = 0; right < h; right++) { for (int front = 0; front < h; front++) { if (alive > 0 || left > 0 || right > 0 || front > 0) { add(result, dynamics[n][alive][left][right][front], 1e9 + 9); } } } } } std::cout << result << std::endl; return 0; }
|
#include <bits/stdc++.h> int main() { static int vv[100][100], tt[100][100], kk[100]; int n, s, h, i, j, k, t, t_, d1, d2, cnt, lead; scanf( %d%d , &n, &s); for (i = 0; i < n; i++) { scanf( %d , &kk[i]); for (j = 0; j < kk[i]; j++) scanf( %d%d , &vv[i][j], &tt[i][j]); for (j = 1; j < kk[i]; j++) tt[i][j] += tt[i][j - 1]; } cnt = 0; for (h = 0; h < n; h++) for (i = 0; i < n; i++) if (h != i) for (lead = 1, d1 = d2 = 0, j = k = 0, t = 0; j < kk[h] && k < kk[i];) { if (tt[h][j] < tt[i][k]) t_ = tt[h][j]; else t_ = tt[i][k]; if (t != t_) { if ((d1 < d2 || (d1 == d2 && !lead)) && d1 + vv[h][j] * (t_ - t) > d2 + vv[i][k] * (t_ - t)) cnt++; d1 += vv[h][j] * (t_ - t); d2 += vv[i][k] * (t_ - t); if (d1 != d2) lead = d1 > d2; } if (tt[h][j] < tt[i][k]) j++; else k++; t = t_; } printf( %d n , cnt); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10; long long h[N], e[2 * N], ne[2 * N], idx; void add(long long a, long long b) { e[idx] = b, ne[idx] = h[a], h[a] = idx++; } struct node { long long sum, add; }; node tr[N << 2]; long long arr[N]; long long f[N][20]; long long dep[N], fa[N], son[N], sz[N]; long long n, q; void dfs1(long long u, long long fz) { fa[u] = fz; dep[u] = dep[fz] + 1; sz[u] = 1; f[u][0] = fz; for (long long i = 1; i < 20; ++i) f[u][i] = f[f[u][i - 1]][i - 1]; for (long long i = h[u]; i != -1; i = ne[i]) { long long j = e[i]; if (j == fz) continue; dfs1(j, u); sz[u] += sz[j]; if (sz[j] > sz[son[u]]) { son[u] = j; } } } long long id[N], top[N], uid[N], tot; void dfs2(long long u, long long topx) { top[u] = topx; id[u] = ++tot; uid[tot] = u; if (!son[u]) return; dfs2(son[u], topx); for (long long i = h[u]; i != -1; i = ne[i]) { long long j = e[i]; if (j == fa[u] || j == son[u]) continue; dfs2(j, j); } } long long get_lca(long long a, long long b) { while (top[a] != top[b]) { if (dep[top[a]] > dep[top[b]]) a = fa[top[a]]; else b = fa[top[b]]; } return dep[a] > dep[b] ? b : a; } long long topC(long long x, long long c) { for (long long i = 19; i >= 0; i--) { if ((1 << i) <= c) { x = f[x][i]; c -= (1 << i); } } return x; } long long root; void pushup(long long u) { tr[u].sum = tr[u << 1].sum + tr[u << 1 | 1].sum; } void pushdown(long long l, long long r, long long u) { if (tr[u].add) { long long mid = l + r >> 1; tr[u << 1].sum += (mid - l + 1) * tr[u].add; tr[u << 1 | 1].sum += (r - mid) * tr[u].add; tr[u << 1].add += tr[u].add; tr[u << 1 | 1].add += tr[u].add; tr[u].add = 0; } } long long query(long long l, long long r, long long a, long long b, long long u) { if (l <= a && b <= r) { return tr[u].sum; } pushdown(a, b, u); long long mid = a + b >> 1; long long ans = 0; if (l <= mid) ans += query(l, r, a, mid, u << 1); if (r > mid) ans += query(l, r, mid + 1, b, u << 1 | 1); return ans; } void ud(long long l, long long r, long long a, long long b, long long d, long long u) { if (l <= a && b <= r) { tr[u].add += d; tr[u].sum += (b - a + 1) * d; return; } pushdown(a, b, u); long long mid = a + b >> 1; if (l <= mid) ud(l, r, a, mid, d, u << 1); if (r > mid) ud(l, r, mid + 1, b, d, u << 1 | 1); pushup(u); } void update(long long u, long long x) { ud(id[u], id[u] + sz[u] - 1, 1, n, x, 1); } long long qry(long long u) { return query(id[u], id[u] + sz[u] - 1, 1, n, 1); } void build(long long l, long long r, long long u) { tr[u].add = 0; if (l == r) { tr[u].sum = arr[uid[l]]; return; } long long mid = l + r >> 1; build(l, mid, u << 1); build(mid + 1, r, u << 1 | 1); pushup(u); } int main() { ios::sync_with_stdio(false); std::cin.tie(0); memset(h, -1, sizeof h); cin >> n >> q; for (long long i = 1; i <= n; ++i) cin >> arr[i]; for (long long i = 1; i < n; ++i) { long long a, b; cin >> a >> b; add(a, b); add(b, a); } dfs1(1, 1); dfs2(1, 1); build(1, n, 1); root = 1; while (q--) { long long t; cin >> t; long long v, u, x; if (t == 1) { cin >> v; root = v; } else if (t == 2) { cin >> u >> v >> x; long long t1 = get_lca(u, root); long long t2 = get_lca(v, root); long long t3 = get_lca(u, v); long long ans = t1; if (dep[ans] < dep[t2]) ans = t2; if (dep[ans] < dep[t3]) ans = t3; long long lca = get_lca(root, ans); if (ans == root) { update(1, x); } else if (lca != ans) { update(ans, x); } else { update(1, x); long long s = topC(root, dep[root] - dep[ans] - 1); update(s, -x); } } else { cin >> v; long long ans = v; long long lca = get_lca(root, ans); if (ans == root) { cout << qry(1) << endl; } else if (lca != ans) { cout << qry(ans) << endl; } else { long long s = topC(root, dep[root] - dep[ans] - 1); cout << (qry(1) - qry(s)) << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 7; const long long mod = 1e9 + 7; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } map<long long, long long> mp; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long i = 1; vector<long long> v; long long n, a, b, m; cin >> m >> a >> b; long long k = gcd(a, b); long long z = m / k; long long val1 = m * z - (k * z * (z + 1) / 2) + z + m + 1; long long val2 = 0; long long start = 0; long long cnt = 0; long long ans = 0; long long currmx = 0; while (start <= (a + b)) { if (mp[start]) break; mp[start] = 1; currmx = max(currmx, start); if (start <= m) { ans += min(currmx - start, m - start + 1); } if (start >= b) start -= b; else start += a; } cout << val1 - ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_4_V
`define SKY130_FD_SC_MS__A41OI_4_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_4_V
|
#include <bits/stdc++.h> using namespace std; void speed() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } void convertString(string &s, char t) { if (t == L ) { for (int i = 0; s[i] != 0 ; i++) if (s[i] >= 65 && s[i] <= 90) s[i] += 32; } else { for (int i = 0; s[i] != 0 ; i++) if (s[i] >= 97 && s[i] <= 122) s[i] -= 32; } } int compare_two_values(double a, double b) { if (fabs(a - b) <= 1e-10) return 0; return a > b ? 1 : -1; } int main() { speed(); short n, d, c = 0; cin >> n >> d; for (char i = a ; n > 0; n--) { cout << i; c++; if (c == 26 || c == d) c = 0, i = a ; else i++; } return 0; }
|
module rom8kx16 (
input [12 : 0] addr,
input clk,
output [15 : 0] dout);
//
// Generate 8 blocks of memory 8k x 2.
// Initialize memory contents from rom-init-*.v files.
//
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-a.v"
) rom_1_0 (.DO (dout[1:0]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-b.v"
) rom_3_2 (.DO (dout[3:2]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-c.v"
) rom_5_4 (.DO (dout[5:4]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-d.v"
) rom_7_6 (.DO (dout[7:6]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-e.v"
) rom_9_8 (.DO (dout[9:8]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-f.v"
) rom_11_10 (.DO (dout[11:10]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-g.v"
) rom_13_12 (.DO (dout[13:12]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-h.v"
) rom_15_14 (.DO (dout[15:14]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
endmodule
|
//----------------------------------------------------------------------------
`timescale 1 ns / 100 ps
module fifo_TB;
//----------------------------------------------------------------------------
// Parameter (may differ for physical synthesis)
//----------------------------------------------------------------------------
parameter tck = 2; // clock period in ns
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
reg clk;
reg rst;
reg rd,wr;
reg [7:0] data_in;
//----------------------------------------------------------------------------
// Device Under Test
//------------------------------------------------------------------
fifo uut(.reset(rst),.clk(clk),.rd(rd),.wr(wr),.data_in(data_in));
/* Clocking device */
initial begin
clk <= 0;
rst <=1;
#(2*tck) rst=0;
rd <=0;
wr<=0;
end
always #(tck/2) clk <= ~clk;
initial begin
#4;
data_in="h"; #1 wr=1; #2 wr=0;
data_in="o"; #1 wr=1; #2 wr=0;
data_in="l"; #1 wr=1; #2 wr=0;
data_in="a"; #1 wr=1; #2 wr=0;
data_in=" "; #1 wr=1; #2 wr=0;
data_in="m"; #1 wr=1; #2 wr=0;
data_in="u"; #1 wr=1; #2 wr=0;
data_in="n"; #1 wr=1; #2 wr=0;
data_in="d"; #1 wr=1; #2 wr=0;
data_in="o"; #1 wr=1; #2 wr=0;
data_in="."; #1 wr=1; #2 wr=0;
data_in="1"; #1 wr=1; #2 wr=0;
data_in="2"; #1 wr=1; #2 wr=0;
data_in="3"; #1 wr=1; #2 wr=0;
data_in="4"; #1 wr=1; #2 wr=0;
data_in="5"; #1 wr=1; #2 wr=0;
data_in="6"; #1 wr=1; #2 wr=0;
data_in="7"; #1 wr=1; #2 wr=0;
data_in="8"; #1 wr=1; #2 wr=0;
data_in="9"; #1 wr=1; #2 wr=0;
data_in="0"; #1 wr=1; #2 wr=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
data_in="a"; #1 wr=1; rd=0;#2 wr=0;rd=1;
data_in="b"; #1 wr=1; #2 wr=0;
data_in="c"; #1 wr=1; #2 wr=0;
data_in="d"; #1 wr=1; #2 wr=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
end
initial begin: TEST_CASE
$dumpfile("fifo_TB.vcd");
$dumpvars(-1, uut);
#(200) $finish;
end
endmodule //
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; if (k == 1) { if (n > 1) cout << n; else cout << -1 ; return 0; } int i; vector<int> res; for (i = 2; i * i <= n; i++) { while (n % i == 0 && k != 1) { n /= i; res.push_back(i); k--; } if (k == 1 && n != 1) { res.push_back(n); for (i = 0; i < res.size(); i++) { cout << res[i] << ; } return 0; } } cout << -1 ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; template <class T> void Swap(T& a, T& b) { a ^= b; b ^= a; a ^= b; } template <class type> void show(type name) { for (auto& nm : name) cerr << nm << ; cerr << n ; } using lng = long long; using ivec = vector<int>; const int mxn = 10; int check(ivec& nums, int n) { int ans = 1e9; for (int i = 0; i < (1 << (int)nums.size()); ++i) { int cnt = 0; for (int j = 0; j < (int)nums.size(); ++j) { if ((i & (1 << j)) > 0) cnt += ceil(pow(3, nums[j])); } if (cnt >= n) ans = min(ans, cnt); } return ans; } int main() { int q, n; cin >> q; while (q--) { cin >> n; ivec nums(min(n, mxn) + 1); iota(begin(nums), end(nums), 0); cout << check(nums, n) << n ; } }
|
module dut(/*AUTOARG*/
// Outputs
dut_active, wait_out, access_out, packet_out,
// Inputs
clk, nreset, vdd, vss, access_in, packet_in, wait_in
);
parameter AW = 32;
parameter DW = 32;
parameter CW = 2;
parameter IDW = 12;
parameter M_IDW = 6;
parameter S_IDW = 12;
parameter PW = 104;
parameter N = 1;
parameter ID = 12'h810;
//#######################################
//# CLOCK AND RESET
//#######################################
input clk;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
//#######################################
//#EMESH INTERFACE
//#######################################
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transactoin
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//TODO: finish readback
wire [DW-1:0] mi_dout;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mi_ctrlmode; // From e2p of packet2emesh.v
wire [DW-1:0] mi_data; // From e2p of packet2emesh.v
wire [1:0] mi_datamode; // From e2p of packet2emesh.v
wire [AW-1:0] mi_dstaddr; // From e2p of packet2emesh.v
wire [AW-1:0] mi_srcaddr; // From e2p of packet2emesh.v
wire mi_write; // From e2p of packet2emesh.v
// End of automatics
assign dut_active = 1'b1;
assign access_out = 'b0;
assign wait_out = 'b0;
assign packet_out[PW-1:0] = 'b0;
/*packet2emesh AUTO_TEMPLATE (//Stimulus
.\(.*\)_out(mi_\1[]),
);
*/
//CONFIG INTERFACE
packet2emesh e2p (/*AUTOINST*/
// Outputs
.write_out (mi_write), // Templated
.datamode_out (mi_datamode[1:0]), // Templated
.ctrlmode_out (mi_ctrlmode[3:0]), // Templated
.data_out (mi_data[DW-1:0]), // Templated
.dstaddr_out (mi_dstaddr[AW-1:0]), // Templated
.srcaddr_out (mi_srcaddr[AW-1:0]), // Templated
// Inputs
.packet_in (packet_in[PW-1:0]));
//TRACE
etrace #(.ID(ID))
etrace ( // Outputs
.mi_dout (mi_dout[DW-1:0]),
// Inputs
.mi_en (access_in),
.mi_we (mi_write),
.mi_addr (mi_dstaddr[AW-1:0]),
.mi_clk (clk),
.mi_din (mi_data[DW-1:0]),
.trace_clk (clk),
.trace_trigger (1'b1),
.trace_vector (mi_srcaddr[AW-1:0]),
.nreset (nreset));
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
// End:
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Cascaded integrator-comb (CIC) Decimator
*/
module cic_decimator #(
parameter WIDTH = 16,
parameter RMAX = 2,
parameter M = 1,
parameter N = 2,
parameter REG_WIDTH = WIDTH+$clog2((RMAX*M)**N)
)
(
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [WIDTH-1:0] input_tdata,
input wire input_tvalid,
output wire input_tready,
/*
* AXI stream output
*/
output wire [REG_WIDTH-1:0] output_tdata,
output wire output_tvalid,
input wire output_tready,
/*
* Configuration
*/
input wire [$clog2(RMAX+1)-1:0] rate
);
/*
* CIC decimator architecture
*
* ,---.
* IN -->(+)--------+--->| V |----+------->(-)--- OUT
* ^ | `---' | ^
* | | | |
* +-- z-1 --+ +-- z-M --+
*
* \___________/ \___________/
* N N
*
* Integrate Decimate Comb
*
*/
reg [$clog2(RMAX+1)-1:0] cycle_reg = 0;
reg [REG_WIDTH-1:0] int_reg[N-1:0];
wire [REG_WIDTH-1:0] int_reg_0 = int_reg[0];
wire [REG_WIDTH-1:0] int_reg_1 = int_reg[1];
reg [REG_WIDTH-1:0] comb_reg[N-1:0];
wire [REG_WIDTH-1:0] comb_reg_0 = comb_reg[0];
wire [REG_WIDTH-1:0] comb_reg_1 = comb_reg[1];
assign input_tready = output_tready | (cycle_reg != 0);
assign output_tdata = comb_reg[N-1];
assign output_tvalid = input_tvalid & cycle_reg == 0;
genvar k;
integer i;
integer j;
integer l;
integer v;
initial begin
for (i = 0; i < N; i = i + 1) begin
int_reg[i] <= 0;
comb_reg[i] <= 0;
end
end
// integrator stages
generate
for (k = 0; k < N; k = k + 1) begin : integrator
always @(posedge clk) begin
if (rst) begin
int_reg[k] <= 0;
end else begin
if (input_tready & input_tvalid) begin
if (k == 0) begin
int_reg[k] <= $signed(int_reg[k]) + $signed(input_tdata);
end else begin
int_reg[k] <= $signed(int_reg[k]) + $signed(int_reg[k-1]);
end
end
end
end
end
endgenerate
// comb stages
generate
for (k = 0; k < N; k = k + 1) begin : comb
reg [REG_WIDTH-1:0] delay_reg[M-1:0];
initial begin
for (j = 0; j < M; j = j + 1) begin
delay_reg[j] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < M; l = l + 1) begin
delay_reg[l] <= 0;
end
comb_reg[k] <= 0;
end else begin
if (output_tready & output_tvalid) begin
if (k == 0) begin
delay_reg[0] <= $signed(int_reg[N-1]);
comb_reg[k] <= $signed(int_reg[N-1]) - $signed(delay_reg[M-1]);
end else begin
delay_reg[0] <= $signed(comb_reg[k-1]);
comb_reg[k] <= $signed(comb_reg[k-1]) - $signed(delay_reg[M-1]);
end
for (v = 0; v < M-1; v = v + 1) begin
delay_reg[i+1] <= delay_reg[i];
end
end
end
end
end
endgenerate
always @(posedge clk) begin
if (rst) begin
cycle_reg <= 0;
end else begin
if (input_tready & input_tvalid) begin
if (cycle_reg < RMAX - 1 && cycle_reg < rate - 1) begin
cycle_reg <= cycle_reg + 1;
end else begin
cycle_reg <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x2, y2; long long euler(long long a, long long b) { if (b == 0) { x2 = 1; y2 = 0; return a; } else { long long res = euler(b, a % b); long long temp = x2; x2 = y2; y2 = temp - (a / b) * y2; return res; } } int main() { int T; long long x, y, m, n, vx, vy; long long k1, k2; long long res, res1, res2, xx, yy; cin >> n >> m >> x >> y >> vx >> vy; if (!vx) { if ((!x) || (x == n)) { cout << x << << (vy > 0 ? m : 0) << endl; } else cout << -1 << endl; return 0; } if (!vy) { if ((!y) || (y == m)) { cout << (vx > 0 ? n : 0) << << y << endl; } else cout << -1 << endl; return 0; } k1 = (vx == 1 ? ((n - x) % n) : (x % n)); k2 = (vy == 1 ? ((m - y) % m) : (y % m)); long long g = euler(n, m); if (abs(k1 - k2) % g) { cout << -1 << endl; return 0; } long long lcm = m * n / g; res1 = (k2 * x2) % m; res1 = res1 * (n / g); res2 = (k1 * y2) % n; res2 = res2 * (m / g); res = (res1 + res2) % lcm; res = (res + lcm) % lcm; xx = x + res * vx; yy = y + res * vy; cout << ((xx % (2 * n)) + 2 * n) % (2 * n) << << ((yy % (2 * m)) + 2 * m) % (2 * m) << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:32:05 03/25/2015
// Design Name:
// Module Name: RF
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RF(Data_in,Select,Acc_in,Data_out,Acc_out,RF_we,Acc_we,RF_clk,FG_pair,b_out,a_out,dat_out
);
input[7:0] Data_in;
input[2:0] Select;
input[7:0] Acc_in;
output[7:0] Data_out;
output[7:0] Acc_out;
output[15:0] FG_pair;
input RF_we;
input Acc_we;
input RF_clk;
output[7:0] b_out,a_out,dat_out;
reg[7:0] Data_out;
reg[7:0] Acc,B,C,D,E,F,G;
initial
begin
Acc <= 8'h49;
B <= 8'h06;
C <= 8'h06;
end
always @(posedge RF_clk)
begin
case(Select)
3'b000: Acc <= (RF_we ? Data_in: Acc);
3'b001: B <= (RF_we ? Data_in: B);
3'b010: C <= (RF_we ? Data_in: C);
3'b011: D <= (RF_we ? Data_in: D);
3'b100: E <= (RF_we ? Data_in: E);
3'b101: F <= (RF_we ? Data_in: F);
3'b110: G <= (RF_we ? Data_in: G);
endcase
if (Select != 3'b000)
Acc <= Acc_we ? Acc_in : Acc;
end
always @(Select or Acc or B or C or D or E or F or G)
begin
case (Select)
3'b000: Data_out <= Acc;
3'b001: Data_out <= B;
3'b010: Data_out <= C;
3'b011: Data_out <= D;
3'b100: Data_out <= E;
3'b101: Data_out <= F;
3'b110: Data_out <= G;
endcase
end
assign Acc_out = Acc;
assign FG_pair = {F,G};
assign b_out = B;
assign a_out = Acc;
assign dat_out = Data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const long long int MOD = 1e9 + 7; const int N = 1e6 + 6; int sum[N][3], prv[N][3]; int main() { int n; string s; cin >> n >> s; s = * + s; prv[0][0] = prv[0][1] = -1; for (int i = 1; i <= n; i++) { sum[i][0] = sum[i - 1][0]; sum[i][1] = sum[i - 1][1]; prv[i][0] = prv[i - 1][0]; prv[i][1] = prv[i - 1][1]; if (s[i] == 1 ) { sum[i][1]++; prv[i][1] = i; } if (s[i] == 0 ) { sum[i][0]++; prv[i][0] = i; } } for (int len = 1; len <= n; len++) { int now = 1; int cnt = 0; while (now + len - 1 <= n) { if (sum[now + len - 1][1] - sum[now - 1][1] == 0 || sum[now + len - 1][0] - sum[now - 1][0] == 0) { cnt++; now += len; continue; } now = min(prv[now + len - 1][0], prv[now + len - 1][1]) + 1; } cout << cnt << ; } cout << n ; }
|
// test case generated from IWLS 2005 usb_phy core
// (triggered a bug in opt_muxtree pass)
module usb_tx_phy(clk, rst, DataOut_i, TxValid_i, hold_reg);
input clk;
input rst;
input DataOut_i;
input TxValid_i;
output reg hold_reg;
reg state, next_state;
reg ld_sop_d;
reg ld_data_d;
always @(posedge clk)
if(ld_sop_d)
hold_reg <= 0;
else
hold_reg <= DataOut_i;
always @(posedge clk)
if(!rst) state <= 0;
else state <= next_state;
always @(state or TxValid_i)
begin
next_state = state;
ld_sop_d = 1'b0;
ld_data_d = 1'b0;
case(state) // synopsys full_case parallel_case
0:
if(TxValid_i)
begin
ld_sop_d = 1'b1;
next_state = 1;
end
1:
if(TxValid_i)
begin
ld_data_d = 1'b1;
next_state = 0;
end
endcase
end
endmodule
// test case inspired by softusb_navre code:
// default not as last case
module default_cases(a, y);
input [2:0] a;
output reg [3:0] y;
always @* begin
case (a)
3'b000, 3'b111: y <= 0;
default: y <= 4;
3'b001: y <= 1;
3'b010: y <= 2;
3'b100: y <= 3;
endcase
end
endmodule
// test case for muxtree with select on leaves
module select_leaves(input R, C, D, output reg Q);
always @(posedge C)
if (!R)
Q <= R;
else
Q <= Q ? Q : D ? D : Q;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_sctrdq_fifo.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_sctrdq_fifo - SCTRDQ ratio synchronous fifo queue implementation.
// _____________________________________________________________________________
//
// Description:
// The implementation uses recirculating read and write pointers to the RAM.
//
// Interface:
// enqueue - Add the entry composed 'data' to the top-of-queue. Should not
// be issued if 'full' is asserted.
//
// din - The data value to put onto the fifo.
//
// full - No more available entries in the fifo.
//
// dequeue - Remove the top entry from the fifo exposing the next entry if
// available. Should not be issued if 'empty' is asserted.
//
// dout - The data at the top of the fifo. Must be qualified with 'empty'.
//
// empty - No entries currently in the fifo.
// _____________________________________________________________________________
`include "sys.h"
module jbi_sctrdq_fifo (/*AUTOARG*/
// Outputs
full, dout, empty,
// Inputs
enqueue, din, cclk, tx_en, crst_l, dequeue, clk, rst_l, hold,
testmux_sel, rst_tri_en, arst_l
);
// Enqueue port.
input enqueue;
input [137:0] din;
output full;
input cclk;
input tx_en;
input crst_l;
// Dequeue port.
input dequeue;
output [137:0] dout;
output empty;
input clk;
input rst_l;
// Misc.
input hold;
input testmux_sel; // Memory and ATPG test mode signal.
input rst_tri_en;
input arst_l;
// Wires and Regs.
wire rd_enb;
wire [4:0] wr_addr_presync, wr_addr_sync, rd_addr_presync, rd_addr_sync;
// Write Address pointer.
// Points to the next available write entry. This is the write address about to be registered into the memory.
wire [4:0] ram_wr_addr_m1;
wire [4:0] next_ram_wr_addr_m1 = (enqueue)? ram_wr_addr_m1+1'b1: ram_wr_addr_m1;
dffrl_ns #(5) ram_wr_addr_m1_reg (.din(next_ram_wr_addr_m1), .q(ram_wr_addr_m1), .rst_l(crst_l), .clk(cclk));
// Read Address pointer.
// Points to the top-of-queue entry. This is the read address currently in the memory.
wire [4:0] ram_rd_addr; // Points to the top-of-queue entry.
wire [4:0] next_ram_rd_addr = (dequeue)? ram_rd_addr+1'b1: ram_rd_addr;
dffrl_ns #(5) ram_rd_addr_reg (.din(next_ram_rd_addr), .q(ram_rd_addr), .rst_l(rst_l), .clk(clk));
wire [4:0] ram_rd_addr_m1 = next_ram_rd_addr[4:0];
// Create fifo status bits 'full' and 'empty'.
//
// Full status.
assign full = (rd_addr_sync[3:0] == ram_wr_addr_m1[3:0]) && (rd_addr_sync[4] != ram_wr_addr_m1[4]);
//
// Empty status.
// (Needs to delay 1-cycle when going from empty to not empty (push to an empty fifo)
// since the memory read enable signals are registered and take a cycle to produce the data).
assign empty = (ram_rd_addr[4:0] == wr_addr_sync[4:0]) || !rd_enb;
// Register Array.
wire [21:0] unused;
wire rd_enb_m1 = (ram_rd_addr_m1[4:0] != wr_addr_sync[4:0]);
jbi_1r1w_16x160 array_scan (
// Write port.
.wrclk (cclk),
.wr_en (enqueue),
.wr_adr (ram_wr_addr_m1[3:0]),
.din ({ 22'b0, din }),
// Read port.
.rdclk (clk),
.read_en (rd_enb_m1),
.rd_adr (ram_rd_addr_m1[3:0]),
.dout ({ unused[21:0], dout }),
// Other.
.rst_l (arst_l),
.hold (hold),
.testmux_sel (testmux_sel),
.rst_tri_en (rst_tri_en)
);
// Signal staging and synchronizers.
//
// 'rd_enb' pipeline.
wire next_rd_enb = rd_enb_m1;
dff_ns rd_enb_reg (.din(next_rd_enb), .q(rd_enb), .clk(clk));
// 'ram_wr_addr' synchronizer (Cmp -> JBus).
wire [4:0] next_wr_addr_presync = ram_wr_addr_m1;
wire wr_addr_presync_en = tx_en;
dffe_ns #(5) wr_addr_presync_reg (.din(next_wr_addr_presync), .en(wr_addr_presync_en), .q(wr_addr_presync), .clk(cclk));
//
wire [4:0] next_wr_addr_sync = wr_addr_presync;
dff_ns #(5) wr_addr_sync_reg (.din(next_wr_addr_sync), .q(wr_addr_sync), .clk(clk));
// 'ram_rd_addr' synchronizer (JBus -> Cmp).
wire [4:0] next_rd_addr_presync = ram_rd_addr;
dff_ns #(5) rd_addr_presync_reg (.din(next_rd_addr_presync), .q(rd_addr_presync), .clk(clk));
//
wire [4:0] next_rd_addr_sync = rd_addr_presync;
dff_ns #(5) rd_addr_sync_reg (.din(next_rd_addr_sync), .q(rd_addr_sync), .clk(cclk));
// simtech modcovoff -bpen
// synopsys translate_off
// Check that no dequeue is done when empty.
always @(posedge clk) begin
if (dequeue && empty) begin
$dispmon ("jbi_mout_jbi_sctrdq_fifo", 49, "%d %m: ERROR - Attempt made to dequeue an empty queue.", $time);
end
end
// Check that no enqueue is done when full.
always @(posedge cclk) begin
if (enqueue && full) begin
$dispmon ("jbi_mout_jbi_sctrdq_fifo", 49, "%d %m: ERROR - Attempt made to enqueue a full queue.", $time);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("../../../include" "../../common/rtl")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_sctrdq")
// End:
|
//date:2016/8/02
//engineer:ZhaiShaoMin
//module name :regflie
//version: test bench
module tb_core_rf();
//input
reg clk;
reg rst;
reg [4:0] raddr1;
reg [4:0] raddr2;
reg rf_write;
reg [4:0] waddr;
reg [31:0] data;
//output
wire [31:0] rd_data1;
wire [31:0] rd_data2;
core_id_regfile duv(//input
.clk(clk),
.rst(rst),
.raddr1(raddr1),
.raddr2(raddr2),
.rf_write(rf_write),
.waddr(waddr),
.data(data),
//output
.rd_data1(rd_data1),
.rd_data2(rd_data2)
);
always #5 clk=~clk;
integer log_file;
integer i;
`define clk_step #10;
initial begin
clk=1'b0;
rst=1'b1;
raddr1=5'h00;
raddr2=5'h00;
rf_write=1'b0;
waddr=5'h01;
data=32'h11112222;
log_file=$fopen("core_rf_log.txt");
end
////////////////////////////////////////////////////////////////////////////
/////////////BEGIN TEST/////////////////////////////////////////////////////
initial begin
////////case 1: write the regfile then we should see what I want to see////////
///////here just write th rf/////////////
`clk_step
rst=1'b0;
for(i=0;i<32;i=i+1)
begin
rf_write=1'b1;
waddr=i;
data=i+1;
$display( "(%t) writing %d. to %d ", $time, data, waddr);
$fdisplay(log_file, "(%t) writing %d. to %d ", $time, data, waddr);
`clk_step
end
////////case 2: read out the content in regfile /////////////////
`clk_step
rf_write=1'b0;
for(i=0;i<32;i=i+1)
begin
raddr1=i;
raddr2=i;
$display( "(%t) get %d. from %d and get %d from %d", $time, rd_data1, raddr1 ,rd_data2, raddr2);
$fdisplay(log_file, "(%t) get %d. from %d and get %d from %d", $time, rd_data1, raddr1 ,rd_data2, raddr2);
`clk_step
end
////////case 3: when read a reg same as being written one, it should get it direct from write data////////////
////read port 1
for(i=0;i<32;i=i+1)
begin
raddr1=i;
rf_write=1'b1;
waddr=i;
data=i+32;
$display( "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
$fdisplay(log_file, "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
`clk_step
end
////read port 2
for(i=0;i<32;i=i+1)
begin
raddr2=i;
rf_write=1'b1;
waddr=i;
data=i+64;
$display( "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
$fdisplay(log_file, "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
`clk_step
end
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, t, k; int a[200005], maxx, b[200005]; vector<int> v[200005]; int cnt = 1, tmp = 0; int main() { n = read(); t = read(); k = read(); for (int i = 1; i <= t; ++i) a[i] = read(); for (int i = t; i >= 1; --i) { maxx += abs(min(0, a[i + 1] - a[i])); if (i == t) b[i] = a[i]; else b[i] = b[i + 1] + a[i] - 1; } v[0].push_back(1); if (k < maxx || k > n - t) { printf( -1 n ); return 0; } else { printf( %d n , n); for (int i = 1; i <= t; ++i) { if (k < n - t - tmp) { v[i].push_back(++cnt); printf( %d %d n , v[i - 1][0], v[i][0]); a[i]--; for (int j = 1; j < v[i - 1].size() && a[i] && k < n - t - tmp; ++j) { v[i].push_back(++cnt); printf( %d %d n , v[i - 1][j], v[i][j]); tmp++; a[i]--; } if (a[i]) { for (int j = 1; j <= a[i]; ++j) { v[i].push_back(++cnt); printf( %d %d n , cnt, v[i - 1][0]); } } } else { for (int j = 1; j <= a[i]; ++j) { v[i].push_back(++cnt); printf( %d %d n , cnt, v[i - 1][0]); } } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> t; while (t--) { int count = 0; int ans; cin >> n; for (int i = 1; i <= 1666; i++) { if ((i % 10 != 3) && i % 3 != 0) { count++; } if (count == n) { ans = i; break; } } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j, k, res[200500], st1[200500][20], st2[200500][20]; int l2(int n) { int r = 0; while (n - 1) { r++; n >>= 1; } return r; } int chk1(int l, int r) { int k = l2(r - l + 1); return max(st1[l][k], st1[r - (1 << k) + 1][k]); } int chk2(int l, int r) { int k = l2(r - l + 1); return min(st2[l][k], st2[r - (1 << k) + 1][k]); } struct sb { int id, l, r; bool operator<(const sb x) const { return r > x.r; } } tmp, s[200500]; vector<sb> v[200500]; priority_queue<sb> q; void ans() { for (int i = 1; i <= n; i++) { printf( %d , res[i]); } puts( ); } int main() { memset(st2, 0x3f, sizeof(st2)); scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d , &j, &k); s[i].id = i; s[i].l = j; s[i].r = k; v[j].push_back(s[i]); } for (i = 1; i <= n; i++) { for (auto j : v[i]) { q.push(j); } s[i] = q.top(); q.pop(); res[s[i].id] = i; st1[i][0] = s[i].r; st2[i][0] = s[i].l; } for (j = 1; j <= 18; j++) { for (i = 1; i + (1 << j) - 1 <= n; i++) { st1[i][j] = max(st1[i][j - 1], st1[i + (1 << (j - 1))][j - 1]); st2[i][j] = min(st2[i][j - 1], st2[i + (1 << (j - 1))][j - 1]); } } for (i = 1; i <= n; i++) { if (s[i].l < i && chk1(s[i].l, i - 1) >= i) { puts( NO ); ans(); for (j = i - 1;; j--) { if (s[j].r >= i) { swap(res[s[i].id], res[s[j].id]); break; } } ans(); return 0; } if (s[i].r > i && chk2(i + 1, s[i].r) <= i) { puts( NO ); ans(); for (j = i + 1;; j++) { if (s[j].l <= i) { swap(res[s[i].id], res[s[j].id]); break; } } ans(); return 0; } } puts( YES ); ans(); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { int k; cin >> k; bool ok = true; int pa = 0, pb = 0; for (int j = 0; j < k; ++j) { int a, b; cin >> a >> b; if (a < pa || b < pb) ok = false; if (a == pa && b != pb) ok = false; if (a > pa && (a - pa) < (b - pb)) ok = false; pa = a; pb = b; } cout << (ok ? YES : NO ) << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b, c, d, x, y, v, ans = 0; cin >> n >> a >> b >> c >> d; for (long long i = 1; i <= n; i++) { x = a - d + i; v = b - c + i; y = a + b - c - d + i; if ((x > 0 && x <= n) && (y > 0 && y <= n) && (v > 0 && v <= n)) ans += n; } cout << ans << endl; return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg ack,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd4;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
read_safe_counter <= 3'd5;
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 3'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 3'd3;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 3'd1;
end
end
end
/* Generate ack signal.
* After write is asserted, it should pulse after 2 cycles.
* After read is asserted, it should pulse after CL+3 cycles, that is
* 5 cycles when tim_cas = 0
* 6 cycles when tim_cas = 1
*/
reg ack_read3;
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack_read3 <= 1'b0;
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
if(tim_cas) begin
ack_read3 <= read;
ack_read2 <= ack_read3;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end else begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
ack0 <= ack_read0|write;
ack <= ack0;
end
end
/* during a 4-word write, we drive the pins for 5 cycles
* and 1 cycle in advance (first word is invalid)
* so that we remove glitches on DQS without resorting
* to asynchronous logic.
*/
/* direction must be glitch-free, as it directly drives the
* tri-state enable for DQ and DQS.
*/
reg write_d;
reg [2:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 3'd0;
direction <= 1'b0;
end else begin
if(write_d) begin
counter_writedirection <= 3'b101;
direction <= 1'b1;
end else begin
if(counter_writedirection == 3'b001)
direction <= 1'b0;
if(direction)
counter_writedirection <= counter_writedirection - 3'd1;
end
end
end
assign direction_r = write_d|(|counter_writedirection);
always @(posedge sys_clk) begin
if(sdram_rst)
write_d <= 1'b0;
else
write_d <= write;
end
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]),
.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule
|
/**
# CordicRectToPolar - CORDIC Algorithm for Rectangular to Polar Coordinates #
Implements the CORDIC algorithm for the purpose of converting rectangular
coordinates to polar coordinates. It takes N cycles, where
`N = min(IN_WIDTH, ANGLE_WIDTH-1)`.
## Algorithm ##
The algorithm is based on doing iterative rotations of the x & y coordinates
using specially chosen angles. Rotation is done towards the positive X axis.
When complete, the X coordinate will equal the polar coordinate magnitude times
a constant, and the total rotation angle will be the polar coordinate angle.
```
[ cos(t) -sin(t) ] = (1+tan(t)^2)^(-1/2) * [ 1 -tan(t) ]
[ sin(t) cos(t) ] [ tan(t) 1 ]
Choose t such that tan(t) = 2^-i, where i is the iteration number:
= (1+2^(-2*i))^(-1/2) * [ 1 -2^-i ]
[ 2^-i 1 ]
```
The maximum number of rotations can be determined by how many bits are in the
input word and the output angle. When the bit shift implied by the `2^-i` amount
would be greater than the input word width, the algorithm would be adding +/- 0,
so it can terminate. Likewise, when the angle value in the lookup table is
smaller than the LSB of the output angle word, the algorithm would be adding +/-
0 to it, so it can terminate.
## Steps ##
1. Rotate coordinate into quadrant 1 (positive x, positive y)
2. Rotate using powers of two and a lookup table for the angle used.
3. Terminate when no more bits can be computed.
## Notes ##
1. This algorithm will not complete if inStrobe is set more than once every ITER_NUM cycles.
2. No optimizations are applied - there are no attempts to fit into DSP device primitives.
*/
module CordicRectToPolar #(
parameter STAGES = 1, ///< Number of stages in CORDIC
parameter IN_WIDTH = 16, ///< Input coordinate pair width
parameter ANGLE_WIDTH = 16, ///< Output angle register width
parameter SCALE_MAGNITUDE = 0, ///< Set to 1 to scale magnitude to true value
parameter MULT_WIDTH = 16 ///< Number of bits to use for magnitude scaling word, if SCALE_MAGNITUDE is 1
)
(
input clk, ///< System clock
input rst, ///< Reset, active high and synchronous
input inStrobe, ///< Input data strobe
input signed [IN_WIDTH-1:0] x, ///< X coordinate
input signed [IN_WIDTH-1:0] y, ///< Y coordinate
output reg [ANGLE_WIDTH-1:0] angle, ///< Angle
output reg [IN_WIDTH:0] magnitude, ///< Magnitude
output reg outStrobe ///< Output data strobe
);
//////////////////////////////////////////////////////////////////////////////
// Local Parameters (do not set externally)
//////////////////////////////////////////////////////////////////////////////
parameter ITER_NUM = (IN_WIDTH > (ANGLE_WIDTH-1)) ? (ANGLE_WIDTH-1) : IN_WIDTH;
parameter ITER_WIDTH = $clog2(ITER_NUM);
parameter M_PI = $acos(-1.0);
localparam STAGES_INT = (ITER_NUM > STAGES) ? STAGES : ITER_NUM; // Max out at `ITER_NUM` of stages
//////////////////////////////////////////////////////////////////////////////
// Constant Declarations (calculated on start)
//////////////////////////////////////////////////////////////////////////////
reg [MULT_WIDTH-1:0] MAG_SCALE; ///< Magnitude Scalar
reg [ANGLE_WIDTH-1:0] ANGLE_LOOKUP [ITER_NUM-1:0]; ///< Angle lookup table
//////////////////////////////////////////////////////////////////////////////
// Signal Declarations
//////////////////////////////////////////////////////////////////////////////
reg [ITER_WIDTH-1:0] iter; ///< Iteration counter
reg [ANGLE_WIDTH-1:0] angleReg; ///< Angle register
reg signed [IN_WIDTH:0] xReg; ///< X coordinate working register
reg signed [IN_WIDTH-1:0] yReg; ///< Y coordinate working register
reg doneD1;
wire signed [IN_WIDTH+MULT_WIDTH:0] magCalc;
wire done;
integer i;
real magScaleCalc;
//////////////////////////////////////////////////////////////////////////////
// Main Code
//////////////////////////////////////////////////////////////////////////////
// Calculate constants
initial begin
for (i=0; i<ITER_NUM; i=i+1) begin
ANGLE_LOOKUP[i] = $rtoi(($atan(2.0**(-i)) * 2.0**(ANGLE_WIDTH-1) / M_PI)+0.5);
end
magScaleCalc = 1.0;
for (i=0; i<ITER_NUM; i=i+1) begin
magScaleCalc = magScaleCalc * (1.0+2.0**(-2.0*i))**(-0.5);
end
MAG_SCALE = $rtoi(2.0**(MULT_WIDTH) * magScaleCalc);
end
if (SCALE_MAGNITUDE) begin
assign magCalc = xReg * MAG_SCALE;
end
else begin
assign magCalc = 'd0;
end
// Algorithm loop
assign done = (iter == (ITER_NUM-1));
always @(posedge clk) begin
if (rst) begin
iter <= ITER_NUM-1;
doneD1 <= 1'b1;
magnitude <= 'd0;
outStrobe <= 1'b0;
angle <= 'd0;
xReg <= 'd0;
yReg <= 'd0;
angleReg <= 'd0;
end
else begin
doneD1 <= done;
outStrobe <= done & ~doneD1;
if (done & ~doneD1) begin
angle <= angleReg;
if (SCALE_MAGNITUDE) begin
magnitude <= magCalc >>> MULT_WIDTH;
end
else begin
magnitude <= xReg;
end
end
if (inStrobe) begin
iter <= 'd0;
case ({y[IN_WIDTH-1], x[IN_WIDTH-1]}) // y<0, x<0
2'b00 : begin xReg <= x; yReg <= y; angleReg <= (0 << (ANGLE_WIDTH-2)); end // 0-90 degrees
2'b01 : begin xReg <= y; yReg <= -x; angleReg <= (1 << (ANGLE_WIDTH-2)); end // 90-180 degrees
2'b11 : begin xReg <= -x; yReg <= -y; angleReg <= (2 << (ANGLE_WIDTH-2)); end // 180-270 degrees
2'b10 : begin xReg <= -y; yReg <= x; angleReg <= (3 << (ANGLE_WIDTH-2)); end // 270-360 degrees
endcase
end
else if (!done) begin
iter <= iter + 2'd1;
if (yReg[IN_WIDTH-1]) begin // yReg < 0
xReg <= xReg - (yReg >>> iter);
yReg <= yReg + (xReg >>> iter);
angleReg <= angleReg - ANGLE_LOOKUP[iter];
end
else begin
xReg <= xReg + (yReg >>> iter);
yReg <= yReg - (xReg >>> iter);
angleReg <= angleReg + ANGLE_LOOKUP[iter];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt[200005]; int calc(int t) { int res = 0; for (int i = 1; i <= 200000; i++) { res += cnt[i] / t; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { int a; cin >> a; cnt[a]++; } int lf = 1, ri = 200005, mid; while (lf < ri) { mid = (lf + ri) / 2; if (calc(mid) < k) ri = mid; else lf = mid + 1; } if (calc(mid) < k) mid--; int p, tot = 0; while (tot < k) { for (int i = 1; i <= 200000; i++) { if (tot == k) break; p = cnt[i] / mid; for (int j = 0; j < p; j++) { cout << i << ; tot++; if (tot == k) break; } } } return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/block_ram/block_ram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Various generic, inferred block ram descriptors.
***************************************************************************************************/
// Dual port RAM with synchronous read. Modified version of listing 12.4 in "FPGA Prototyping by
// Verilog Examples," itself a modified version of XST 8.11 v_rams_11.
module dual_port_ram_sync
#(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [ADDR_WIDTH-1:0] addr_b,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a,
output wire [DATA_WIDTH-1:0] dout_b
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] q_addr_a;
reg [ADDR_WIDTH-1:0] q_addr_b;
always @(posedge clk)
begin
if (we)
ram[addr_a] <= din_a;
q_addr_a <= addr_a;
q_addr_b <= addr_b;
end
assign dout_a = ram[q_addr_a];
assign dout_b = ram[q_addr_b];
endmodule
// Single port RAM with synchronous read.
module single_port_ram_sync
#(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] q_addr_a;
always @(posedge clk)
begin
if (we)
ram[addr_a] <= din_a;
q_addr_a <= addr_a;
end
assign dout_a = ram[q_addr_a];
endmodule
|
#include <bits/stdc++.h> struct Node { int sum, value; Node *ch[2], *p; __inline Node(int value = 0) : value(value) { sum = 1; ch[0] = ch[1] = p = NULL; } __inline void update() { sum = 1 + (ch[0] ? ch[0]->sum : 0) + (ch[1] ? ch[1]->sum : 0); } } pool[211111], *cur = pool; __inline bool cut(Node *y) { if (!y) return 0; Node *x = y->p; if (x != NULL) { bool d = y == x->ch[1]; x->ch[d] = NULL; x->sum -= y->sum; y->p = NULL; return d; } return 0; } __inline void link(Node *x, Node *y, bool d) { if (y == NULL) return; ; ; if (x) { ; ; y->p = x; x->ch[d] = y; x->sum += y->sum; } } __inline void rotate(Node *x, bool d) { ; ; Node *y = x->ch[d], *px = x->p, *B = y->ch[!d]; bool dd = cut(x); cut(y); cut(B); link(x, B, d); link(y, x, !d); link(px, y, dd); } __inline Node *trace_root(Node *x) { if (x == NULL) return NULL; for (; x->p != NULL; x = x->p) ; return x; } __inline Node *trace(Node *x, bool d) { if (x == NULL) return NULL; for (; x->ch[d] != NULL; x = x->ch[d]) ; return x; } __inline void splay(Node *x, Node *term) { if (x == NULL) return; for (; x->p != term;) { Node *y = x->p; bool dx = x == y->ch[1]; if (y->p == term) rotate(y, dx); else { Node *z = y->p; bool dy = y == z->ch[1]; if (dx == dy) { rotate(z, dy); rotate(y, dx); } else { rotate(y, dx); rotate(z, dy); } } } } __inline void rand_splay(Node *T) { if (T == NULL) return; Node *last; for (last = T, T = T->ch[rand() & 1]; T != NULL;) T = T->ch[rand() & 1]; splay(last, NULL); } const int N = 222222; std::map<int, Node *> node; Node *tree[N]; int nxt[N], prv[N]; int n, h, m; int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); std::cin >> h >> m >> n; long long ans = 0; for (int i = 0; i < h; ++i) nxt[i] = (i + m) % h, prv[i] = (i + h - m) % h; for (int _ = 0; _ < n; ++_) { char buf[3]; int id; std::cin >> buf >> id; if (buf[0] == + ) { int th; std::cin >> th; Node *T = tree[th]; splay(T, NULL); ans += T ? (T->ch[1] ? T->ch[1]->sum + 1 : 1) : 0; if (T != NULL) { Node *t = trace(T, 1); th = nxt[t->value]; T = tree[th]; ; ; } T = cur++; T->value = th; tree[th] = T; Node *rt0 = tree[prv[th]]; splay(rt0, NULL); Node *rt1 = trace_root(tree[nxt[th]]); link(T, rt0, 0); if (rt1 != rt0) link(T, rt1, 1); node[id] = T; } else { Node *T = node[id]; splay(T, NULL); Node *t = trace(T->ch[1], 1); cut(T->ch[0]); cut(T->ch[1]); tree[T->value] = NULL; node[id] = NULL; if (t) T = trace_root(tree[nxt[t->value]]); else T = NULL; if (T) { splay(t, NULL); link(t, T, 1); } } } std::cout << ans << std::endl; return 0; }
|
#include <bits/stdc++.h> using namespace std::chrono; using namespace std; const int mod = 1e9 + 7; string s; int op[501], cl[501]; int sop[501], scl[501]; int n; void f() { memset(op, 0, sizeof(op)); memset(cl, 0, sizeof(cl)); if (s[0] == ( ) op[0]++; else cl[0]++; memset(sop, 0, sizeof(sop)); memset(scl, 0, sizeof(scl)); if (s[n - 1] == ( ) sop[n - 1]++; else scl[n - 1]++; for (int i = n - 2; i >= 0; --i) { if (s[i] == ) ) { sop[i] = sop[i + 1]; scl[i] = scl[i + 1] + 1; } else { if (scl[i + 1]) { sop[i] = sop[i + 1]; scl[i] = scl[i + 1] - 1; } else { sop[i] = sop[i + 1] + 1; scl[i] = scl[i + 1]; } } } for (int i = 1; i < n; ++i) { if (s[i] == ( ) { op[i] = op[i - 1] + 1; cl[i] = cl[i - 1]; } else { if (op[i - 1]) { op[i] = op[i - 1] - 1; cl[i] = cl[i - 1]; } else { op[i] = op[i - 1]; cl[i] = cl[i - 1] + 1; } } } } void solve() { cin >> n; cin >> s; int x1 = 1, x2 = 1, mx = 0, c = 0; for (int i = 0; i < n; ++i) { for (int j = i; j < n; ++j) { int c = 0; swap(s[i], s[j]); f(); for (int k = 0; k < n; ++k) { int open; open = 0; if (k + 1 < n) open = sop[k + 1]; if (cl[k] == open && op[k] == 0) { if (k + 1 < n) { if (scl[k + 1] == 0) c++; } else c++; } } swap(s[i], s[j]); if (mx < c) { mx = c; x1 = i + 1; x2 = j + 1; } } } cout << mx << endl; cout << x1 << << x2; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) solve(); }
|
module inject_inst_net_case (
output logic [7:0] q2,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
logic [7:0] Q1;
register2 r2 (.q1(Q1), .ck(clk),
/*AUTOINST*/
// Outputs
.q2 (q2[7:0]),
// Inputs
.rst_n (rst_n));
register1 r1 (.q1(Q1), .ck(clk),
/*AUTOINST*/
// Inputs
.d (d[7:0]),
.rst_n (rst_n));
endmodule
module register2 (
output logic [7:0] q2,
input logic [7:0] q1,
input logic ck, rst_n
/*AUTOARG*/);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q2 <= '0;
else q2 <= q1;
endmodule
module register1 (
output logic [7:0] q1,
input logic [7:0] d,
input logic ck, rst_n
/*AUTOARG*/);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q1 <= '0;
else q1 <= d;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_Add_Subt();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Add_Subtract_Function #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) uut(
.clk(clk),
.rst(rst),
.beg_FSM(beg_FSM),
.ack_FSM(ack_FSM),
.Data_X(Data_X),
.Data_Y(Data_Y),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready),
.final_result_ieee(final_result_ieee)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
add_subt = 0;
// // Wait 100 ns for global reset to finish
// #100 rst = 0;
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
// Wait 100 ns for global reset to finish
#100 rst = 0;
//Add stimulus here
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_FSM = 0;
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Cont_CLK = Cont_CLK + 1;
ack_FSM = 0;
end
else if(Cont_CLK ==2) begin
ack_FSM = 0;
beg_FSM = 1;
Cont_CLK = Cont_CLK +1 ;
end
else begin
ack_FSM = 0;
Cont_CLK = Cont_CLK + 1;
beg_FSM = 0;
end
if(ready==1) begin
ack_FSM = 1;
Cont_CLK = 0;
end
if(ready==1 && ack_FSM) begin
Cont_CLK = 0;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n; cin >> n; int a, b; int s1 = 0; int s2 = 0; int flag = 0; while (n--) { cin >> a >> b; if ((a & 1) != (b & 1)) flag = 1; s1 += a; s2 += b; } cerr << s1 << << s2 << endl; int ans = 0; if (s1 % 2 != s2 % 2) { ans = -1; } else { if (s1 % 2 == 0) ans = 0; else if (!flag) ans = -1; else ans = 1; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_4_V
`define SKY130_FD_SC_MS__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_4_V
|
/*
DCPU16 Verilog Implementation
Copyright (C) 2012 Shawn Tan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version. This program is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU Lesser General Public
License along with this program. If not, see
<http://www.gnu.org/licenses/>. */
module dcpu16sim (/*AUTOARG*/);
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] f_adr; // From ut0 of dcpu16_cpu.v
wire [15:0] f_dti; // From ur0 of fasm_dpsram_wbr.v
wire [15:0] f_dto; // From ut0 of dcpu16_cpu.v
wire f_stb; // From ut0 of dcpu16_cpu.v
wire f_wre; // From ut0 of dcpu16_cpu.v
wire [15:0] g_adr; // From ut0 of dcpu16_cpu.v
wire [15:0] g_dti; // From ur0 of fasm_dpsram_wbr.v
wire [15:0] g_dto; // From ut0 of dcpu16_cpu.v
wire g_stb; // From ut0 of dcpu16_cpu.v
wire g_wre; // From ut0 of dcpu16_cpu.v
// End of automatics
/*AUTOREG*/
reg rst,
clk;
reg f_ack, g_ack;
initial begin
$dumpfile ("dump.vcd");
$dumpvars (2,ut0);
clk = $random;
rst = 1;
#50 rst = 0;
$readmemh ("dump.vmem", ur0.bram);
#5000 $displayh("\n*** TIMEOUT ", $stime, " ***");
$finish;
end // initial begin
always #5 clk <= !clk;
always @(negedge clk) begin
f_ack <= f_stb;
//& !f_ack;
g_ack <= g_stb;
//& !g_ack;
end
/* fasm_dpsram_wbr AUTO_TEMPLATE (
.AW(16),
.DW(16),
.xclk_i(~clk),
.clk_i(~clk),
.xwre_i(g_wre),
.xstb_i(g_stb),
.xadr_i(g_adr),
.xdat_o(g_dti[15:0]),
.xdat_i(g_dto[15:0]),
.wre_i(f_wre),
.stb_i(f_stb),
.adr_i(f_adr),
.dat_o(f_dti[15:0]),
.dat_i(f_dto[15:0]),
.rst_i(rst),
.xrst_i(rst),
) */
fasm_dpsram_wbr
#(/*AUTOINSTPARAM*/
// Parameters
.AW (16), // Templated
.DW (16)) // Templated
ur0 (/*AUTOINST*/
// Outputs
.dat_o (f_dti[15:0]), // Templated
.xdat_o (g_dti[15:0]), // Templated
// Inputs
.dat_i (f_dto[15:0]), // Templated
.adr_i (f_adr), // Templated
.wre_i (f_wre), // Templated
.stb_i (f_stb), // Templated
.rst_i (rst), // Templated
.clk_i (~clk), // Templated
.xdat_i (g_dto[15:0]), // Templated
.xadr_i (g_adr), // Templated
.xwre_i (g_wre), // Templated
.xstb_i (g_stb), // Templated
.xrst_i (rst), // Templated
.xclk_i (~clk)); // Templated
dcpu16_cpu
ut0 (/*AUTOINST*/
// Outputs
.f_adr (f_adr[15:0]),
.f_dto (f_dto[15:0]),
.f_stb (f_stb),
.f_wre (f_wre),
.g_adr (g_adr[15:0]),
.g_dto (g_dto[15:0]),
.g_stb (g_stb),
.g_wre (g_wre),
// Inputs
.clk (clk),
.f_ack (f_ack),
.f_dti (f_dti[15:0]),
.g_ack (g_ack),
.g_dti (g_dti[15:0]),
.rst (rst));
integer i;
initial begin
for (i=0; i<8; i=i+1) begin
ut0.r0.file[i] <= $random;
end
end
endmodule // dcpu16sim
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/")
// verilog-library-files:("")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { int n, g[105], sum = 0, s = 0; cin >> n; for (register int i = 0; i < n; i++) cin >> g[i], g[i] == 0 ? sum++, g[i]++ : 0, s += g[i]; if (s == 0) sum++; cout << sum << endl; } return 0; }
|
module keyed_permutation #(
parameter UNIT_WIDTH = 1
)(
input wire i_clk,
input wire [16*UNIT_WIDTH-1:0] i_dat,
input wire [16*INDEX_WIDTH-1:0] i_key,
input wire i_inverse,
output reg [16*UNIT_WIDTH-1:0] o_dat
);
localparam NUNITS = 16;
localparam INDEX_WIDTH = 4;
localparam KEY_WIDTH = 49;
function [INDEX_WIDTH-1:0] get_nth_zero_index;
input [NUNITS-1:0] in;
input [INDEX_WIDTH-1:0] index;
integer i;
reg [INDEX_WIDTH-1:0] zero_index;
reg [INDEX_WIDTH-1:0] out;
begin
out = {INDEX_WIDTH{1'bx}};
zero_index = 0;
for(i=0;i<NUNITS;i=i+1) begin
if(~in[i]) begin
if(index==zero_index) begin
out = i;
end
zero_index = zero_index + 1;
end
end
get_nth_zero_index = out;
end
endfunction
function [NUNITS*INDEX_WIDTH-1:0] compute_map;
input [KEY_WIDTH-1:0] key;
reg [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS-1:0] done;
reg [INDEX_WIDTH-1:0] outPos;
reg [NUNITS-1:0] outDone;
reg [8:0] pos;
reg [INDEX_WIDTH-1:0] index;
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 16;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=0;
map[0*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 15;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=1;
map[1*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 14;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=2;
map[2*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 13;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=3;
map[3*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 12;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=4;
map[4*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 11;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=5;
map[5*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 10;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=6;
map[6*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:4] % 9;
pos = pos + 4;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=7;
map[7*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:3] % 8;
pos = pos + 3;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=8;
map[8*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:3] % 7;
pos = pos + 3;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=9;
map[9*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:3] % 6;
pos = pos + 3;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=10;
map[10*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:3] % 5;
pos = pos + 3;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=11;
map[11*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:2] % 4;
pos = pos + 2;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=12;
map[12*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:2] % 3;
pos = pos + 2;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=13;
map[13*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
index = key[pos+:1] % 2;
pos = pos + 1;
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=14;
map[14*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
index = {INDEX_WIDTH{1'b0}};
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=15;
map[15*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
compute_map = map;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] permute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[i*UNIT_WIDTH+:UNIT_WIDTH] = in[index*UNIT_WIDTH+:UNIT_WIDTH];
end
permute = out;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] unpermute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[index*UNIT_WIDTH+:UNIT_WIDTH] = in[i*UNIT_WIDTH+:UNIT_WIDTH];
end
unpermute = out;
end
endfunction
reg [NUNITS*INDEX_WIDTH-1:0] map;
always @(posedge i_clk) begin
map <= compute_map(i_key);
o_dat <= i_inverse ? unpermute(i_dat,map) : permute(i_dat,map);
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charSent (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : jtag_cores.v
// Title : Instantiates all IP cores on JTAG chain.
// Dependencies : system_conf.v
// Version : 6.0.14
// : modified to use jtagconn for LM32,
// : all technologies 7/10/07
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// Version : 3.9
// : Support added for 'Fast Download' register in Debugger
// ============================================================================
`include "system_conf.v"
`include "lm32_include.v"
/////////////////////////////////////////////////////
// jtagconn16 Module Definition
/////////////////////////////////////////////////////
module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
input er2_tdo ;
output jtck ;
output jtdi ;
output jshift ;
output jupdate ;
output jrstn ;
output jce2 ;
output ip_enable ;
endmodule
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
(* syn_hier="hard" *) module jtag_cores (
// ----- Inputs -------
reg_d,
reg_addr_d,
// ----- Outputs -------
reg_update,
reg_q,
reg_addr_q,
jtck,
jrstn
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [7:0] reg_d;
input [2:0] reg_addr_d;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output reg_update;
wire reg_update;
`ifdef CFG_FAST_DOWNLOAD_ENABLED
output [`DOWNLOAD_BUFFER_SIZE-1:0] reg_q;
wire [`DOWNLOAD_BUFFER_SIZE-1:0] reg_q;
`else
output [7:0] reg_q;
wire [7:0] reg_q;
`endif
output [2:0] reg_addr_q;
wire [2:0] reg_addr_q;
output jtck;
wire jtck; /* synthesis syn_keep=1 */
output jrstn;
wire jrstn; /* synthesis syn_keep=1 */
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
wire jtdi; /* synthesis syn_keep=1 */
wire er2_tdo2; /* synthesis syn_keep=1 */
wire jshift; /* synthesis syn_keep=1 */
wire jupdate; /* synthesis syn_keep=1 */
wire jce2; /* synthesis syn_keep=1 */
wire ip_enable; /* synthesis syn_keep=1 */
(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
.er2_tdo (er2_tdo2),
.jtck (jtck),
.jtdi (jtdi),
.jshift (jshift),
.jupdate (jupdate),
.jrstn (jrstn),
.jce2 (jce2),
.ip_enable (ip_enable)
);
(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
.JTCK (jtck),
.JTDI (jtdi),
.JTDO2 (er2_tdo2),
.JSHIFT (jshift),
.JUPDATE (jupdate),
.JRSTN (jrstn),
.JCE2 (jce2),
.JTAGREG_ENABLE (ip_enable),
.CONTROL_DATAN (),
.REG_UPDATE (reg_update),
.REG_D (reg_d),
.REG_ADDR_D (reg_addr_d),
.REG_Q (reg_q),
.REG_ADDR_Q (reg_addr_q)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> v(26, 0); long long int n, m; bool myFun(string &a, string &s, long long int i, long long int j) { if (i >= n && j >= m) { return true; } if (j >= m) { return false; } if (i >= n) { while (j < m) { if (s[j] != * ) { return false; } j++; } return true; } if (a[i] == s[j]) { return myFun(a, s, i + 1, j + 1); } if (s[j] == ? ) { long long int temp = a[i] - a ; if (v[temp]) { return myFun(a, s, i + 1, j + 1); } return false; } if (s[j] == * ) { long long int temp = a[i] - a ; if (v[temp]) { return myFun(a, s, i, j + 1); } else { return (myFun(a, s, i + 1, j + 1) || myFun(a, s, i, j + 1)) || myFun(a, s, i + 1, j); } } return false; } int main() { string s; cin >> s; for (long long int i = 0; i < s.length(); i++) { long long int temp = s[i] - a ; v[temp] = 1; } cin >> s; long long int k; cin >> k; for (long long int i = 0; i < k; i++) { string a; cin >> a; n = a.length(); m = s.length(); if (myFun(a, s, 0, 0)) { cout << YES << endl; } else { cout << NO << endl; } } return 0; }
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module BTN_Anti_jitter(
input wire clk,
input wire [4:0]button,
input wire [7:0]SW,
output reg [4:0]button_out,
output reg [7:0]SW_OK
);
reg [31:0] counter;
always @(posedge clk)begin
if (counter > 0)begin
if (counter < 100000) //100000
counter <= counter + 1;
else begin
counter <= 32'b0;
button_out <= button;
SW_OK <= SW;
end
end else
if (button >0 || SW > 0)
counter <= counter + 1;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N, M, nn; long long a[300002]; long long suma[300002]; long long f[300002]; long long sumf[300002]; struct data { long long a, b; long long tot; } seg[1200002]; long long s, e; bool cross(long long x1, long long y1, long long x2, long long y2) { if (y1 < x2 || y2 < x1) return false; return true; } void add(long long node, long long left, long long right) { seg[node].tot += (sumf[min(right, e) - s + 1] - sumf[max(left, s) - s]); seg[node].tot %= 1000000009; if (s <= left && right <= e) { seg[node].a += f[left - s]; seg[node].b += f[left - s + 1]; seg[node].a %= 1000000009; seg[node].b %= 1000000009; return; } int mid = (left + right) / 2; if (cross(s, e, left, mid)) add(node * 2, left, mid); if (cross(s, e, mid + 1, right)) add((node * 2) + 1, mid + 1, right); } long long ans; long long x, y; void sum(long long node, long long left, long long right) { if (s <= left && right <= e) { ans += seg[node].tot; ans %= 1000000009; return; } int mid = (left + right) / 2; seg[node * 2].a += seg[node].a; seg[node * 2].b += seg[node].b; seg[node * 2].a %= 1000000009; seg[node * 2].b %= 1000000009; x = seg[node].a; y = seg[node].b; seg[node * 2].tot += ((x * sumf[mid - left]) + (y * sumf[mid - left + 1])); seg[node * 2].tot %= 1000000009; seg[(node * 2) + 1].tot += ((x * sumf[right - left]) + (y * sumf[right - left + 1])); seg[(node * 2) + 1].tot -= ((seg[node].a * sumf[mid - left]) + (seg[node].b * sumf[mid - left + 1])); seg[(node * 2) + 1].tot %= 1000000009; x = ((seg[node].a * f[mid - left]) + (seg[node].b * f[mid - left + 1])); y = ((seg[node].a * f[mid - left + 1]) + (seg[node].b * f[mid - left + 2])); seg[(node * 2) + 1].a += x; seg[(node * 2) + 1].b += y; seg[(node * 2) + 1].a %= 1000000009; seg[(node * 2) + 1].b %= 1000000009; seg[node].a = seg[node].b = 0; if (cross(s, e, left, mid)) sum(node * 2, left, mid); if (cross(s, e, mid + 1, right)) sum((node * 2) + 1, mid + 1, right); } long long tmp[300002], ans2; void process() { long long i, j; long long op, l, r; for (nn = 1; nn < N; nn *= 2) ; for (i = 1; i <= N; i++) { suma[i] = suma[i - 1] + a[i]; suma[i] %= 1000000009; } f[1] = f[2] = 1; for (i = 3; i <= N; i++) { f[i] = f[i - 1] + f[i - 2]; f[i] %= 1000000009; } for (i = 1; i <= N; i++) { sumf[i] = sumf[i - 1] + f[i]; sumf[i] %= 1000000009; tmp[i] = a[i]; } for (i = 1; i <= M; i++) { scanf( %lld %lld %lld , &op, &l, &r); if (op == 1) { s = l; e = r; add(1, 1, nn); } else { s = l; e = r; ans = 0; sum(1, 1, nn); ans += suma[e]; ans -= suma[s - 1]; ans %= 1000000009; if (ans < 0) ans += 1000000009; printf( %lld n , ans); ans2 = 0; } } } void clean() { long long i; for (i = 1; i <= nn * 2; i++) seg[i].a = seg[i].b = seg[i].tot; } int main(void) { long long i; scanf( %lld %lld , &N, &M); for (i = 1; i <= N; i++) scanf( %lld , &a[i]); process(); clean(); return 0; }
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (lin64) Build Thu Jun 2 16:32:35 MDT 2016
//Date : Thu Jul 21 21:21:48 2016
//Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
//Command : generate_target block_design_wrapper.bd
//Design : block_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module block_design_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
i2c_lcd_scl_io,
i2c_lcd_sda_io);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout i2c_lcd_scl_io;
inout i2c_lcd_sda_io;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire i2c_lcd_scl_i;
wire i2c_lcd_scl_io;
wire i2c_lcd_scl_o;
wire i2c_lcd_scl_t;
wire i2c_lcd_sda_i;
wire i2c_lcd_sda_io;
wire i2c_lcd_sda_o;
wire i2c_lcd_sda_t;
block_design block_design_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.i2c_lcd_scl_i(i2c_lcd_scl_i),
.i2c_lcd_scl_o(i2c_lcd_scl_o),
.i2c_lcd_scl_t(i2c_lcd_scl_t),
.i2c_lcd_sda_i(i2c_lcd_sda_i),
.i2c_lcd_sda_o(i2c_lcd_sda_o),
.i2c_lcd_sda_t(i2c_lcd_sda_t));
IOBUF i2c_lcd_scl_iobuf
(.I(i2c_lcd_scl_o),
.IO(i2c_lcd_scl_io),
.O(i2c_lcd_scl_i),
.T(i2c_lcd_scl_t));
IOBUF i2c_lcd_sda_iobuf
(.I(i2c_lcd_sda_o),
.IO(i2c_lcd_sda_io),
.O(i2c_lcd_sda_i),
.T(i2c_lcd_sda_t));
endmodule
|
/*
* Copyright (C) 2015-2016 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
//
module halfband_decim
(
input c,
input [17:0] tap,
input [NDSP-1:0] load_tap,
input [23:0] id0, // input data n
input [23:0] id1, // input data n+1
output [23:0] od
);
parameter integer NCH = 4; // number of channels to process, clock is NCH*OSR
parameter integer NDSP = 3; // number of DSP blocks to use, = ((NTAPS-1 / 2) + 1)/2
wire signed [47:0] pcout [0:NDSP-1];
wire signed [47:0] p [0:NDSP-1];
wire signed [23:0] a [0:NDSP-1];
wire signed [23:0] d [0:NDSP-1];
assign a[0] = id0;
reg [23:0] odr = 0;
assign od = odr;
wire [23:0] center_data;
delay #(.NB(24), .DEL(1+2+NDSP * (NCH))) cdelay(.c(c), .i(id1), .o(center_data));
genvar i;
generate
for(i=0; i<NDSP; i=i+1) begin: dsp
DSP48E1 #(.USE_DPORT("TRUE"), .ADREG(1), .AREG(2), .BREG(1), .CREG(1), .DREG(1), .OPMODEREG(1))
dsp48_i
(
// status
.OVERFLOW(), .PATTERNDETECT(), .PATTERNBDETECT(), .UNDERFLOW(),
// outs
.CARRYOUT(),
.P(p[i]),
// control
.ALUMODE(4'd0),
.CARRYINSEL(3'd0),
.CLK(c),
.INMODE(5'b00100),
.OPMODE(i==0 ? 7'b0110101 : 7'b0010101), // if i==0: P + C+(A+D)*B else PCIN instead of C
// signal inputs
.A({5'd0, a[i][23], a[i]}), // 30
.B(tap), // 18
.C(i==0 ? {4'h0, center_data, 20'h80000} : 48'h0), // 48
.D({d[i][23], d[i]}), // 25
.CARRYIN(1'b0),
// cascade ports
.ACOUT(), .BCOUT(), .CARRYCASCOUT(), .MULTSIGNOUT(), .PCOUT(pcout[i]),
.ACIN(30'h0), .BCIN(18'h0), .CARRYCASCIN(1'b0), .MULTSIGNIN(1'b0),
.PCIN(i==0 ? 48'h0 : pcout[i-1]),
// clock enables
.CEA1(1'b1), .CEA2(1'b1), .CEAD(1'b1), .CEALUMODE(1'b1),
.CEB1(load_tap[i]), .CEB2(load_tap[i]), .CEC(1'b1),
.CECARRYIN(1'b1), .CECTRL(1'b1), // opmode
.CED(1'b1), .CEINMODE(1'b1), .CEM(1'b1), .CEP(1'b1),
.RSTA(1'b0), .RSTALLCARRYIN(1'b0), .RSTALUMODE(1'b0),
.RSTB(1'b0), .RSTC(1'b0), .RSTCTRL(1'b0), .RSTD(1'b0), .RSTINMODE(1'b0), .RSTM(1'b0), .RSTP(1'b0)
);
if(i!=0)
delay #(.NB(24), .DEL(1+NCH)) del_a(.c(c), .i(a[i-1]), .o(a[i]));
if(i==(NDSP-1))
delay #(.NB(24), .DEL(1+NCH)) del_d(.c(c), .i(a[NDSP-1]), .o(d[i]));
else
delay #(.NB(24), .DEL(NCH-1)) del_d(.c(c), .i(d[i+1]), .o(d[i]));
end
endgenerate
always @ (posedge c) begin
odr <= p[NDSP-1][43:20];
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
// i0 and i1 are each two TDM channels
// o0 is even samples
module halfband_reorder(input c, s, input [23:0] i0, i1, output reg [23:0] o0, o1);
parameter N = 2; // number of input TDM channels
wire [23:0] i0d2, i1d2, i1d4;
delay #(.NB(24), .DEL(N)) delay_1(.c(c), .i(i0), .o(i0d2));
delay #(.NB(24), .DEL(N)) delay_2(.c(c), .i(i1), .o(i1d2));
delay #(.NB(24), .DEL(N*2)) delay_3(.c(c), .i(i1), .o(i1d4));
o0 <= s ? i1d4 : i0d2;
o1 <= s ? i1d2 : i0;
endmodule
module halfband_8ch_decim4(input c, input[1:0] sync, input [23:0] i0, i1, i2, i3, output [23:0] o);
wire [23:0] i0r, i1r, i2r, i3r, fo0, fo1, fo0r, fo1r;
reg sr1, sr2;
reg [2:0] count;
always @ (posedge c)
begin
count <= sync ? 1'b0 : count + 1'b1;
case(count)
0: {sr1, sr2} <= 2'b00;
1: {sr1, sr2} <= 2'b00;
2: {sr1, sr2} <= 2'b10;
3: {sr1, sr2} <= 2'b10;
4: {sr1, sr2} <= 2'b01;
5: {sr1, sr2} <= 2'b01;
6: {sr1, sr2} <= 2'b11;
7: {sr1, sr2} <= 2'b11;
endcase
end
halfband_reorder #(.N(2)) reorder0(.c(c), .s(sr1), .i0(i0), .i1(i1), .o0(i0r), .o1(i1r));
halfband_reorder #(.N(2)) reorder1(.c(c), .s(sr1), .i0(i2), .i1(i3), .o0(i2r), .o1(i3r));
halfband_decim #(.NDSP(3)) decim0(.c(c), .tap(tap), .load_tap(lt[2:0]), .id0(i0r), .id1(i1r), .od(fo0));
halfband_decim #(.NDSP(3)) decim1(.c(c), .tap(tap), .load_tap(lt[2:0]), .id0(i2r), .id1(i2r), .od(fo1));
halfband_reorder #(.N(4)) reorder1(.c(c), .s(sr2), .i0(fo0), .i1(fo1), .o0(fo0r), .o1(fo1r));
halfband_decim #(.NDSP(3)) decim1(.c(c), .tap(tap), .load_tap(lt[5:3]), .id0(fo0r), .id1(fo1r), .od(o));
endmodule
module delay (input c, input [NB-1:0] i, output [NB-1:0] o);
parameter integer NB = 1;
parameter integer DEL = 2;
genvar j;
generate
if(DEL > 1) begin
for(j=0; j<NB; j=j+1) begin: dbit
reg [DEL-1:0] dreg = 0;
always @ (posedge c)
dreg <= {dreg[DEL-2:0], i[j]};
assign o[j] = dreg[DEL-1];
end
end
else if(DEL == 1) begin
reg [NB-1:0] oq;
always @ (posedge c)
oq <= i;
assign o = oq;
end
else begin
assign o = i;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int nbElems, nbAuto; bitset<2000> autos[2000]; bitset<2000> inverse[2000]; int main() { scanf( %d%d , &nbElems, &nbAuto); vector<pair<int, int> > paires; for (int iPaire = 0; iPaire < nbAuto; iPaire++) { int pos, elem; scanf( %d%d , &pos, &elem); autos[pos - 1][elem - 1] = true; paires.push_back(make_pair(pos - 1, elem - 1)); } for (int iElem = 0; iElem < nbElems; iElem++) { inverse[iElem][iElem] = 1; } for (int iLigne = 0; iLigne < nbElems; iLigne++) { if (!autos[iLigne][iLigne]) { for (int iAutre = iLigne + 1; iAutre < nbElems; iAutre++) { if (autos[iAutre][iLigne]) { autos[iLigne] ^= autos[iAutre]; inverse[iLigne] ^= inverse[iAutre]; break; } } } for (int iAutre = 0; iAutre < nbElems; iAutre++) { if (iAutre != iLigne && autos[iAutre][iLigne]) { autos[iAutre] ^= autos[iLigne]; inverse[iAutre] ^= inverse[iLigne]; } } } for (int iPaire = 0; iPaire < nbAuto; iPaire++) { if (inverse[paires[iPaire].second][paires[iPaire].first]) { printf( NO n ); } else { printf( YES n ); } } return 0; }
|
#include <bits/stdc++.h> int main(void) { int n; while (scanf( %d , &n) != EOF) { int k = 0, flag = 0, su; for (int i = 9; i >= 0; i--) { if (i == n && i != 1) continue; if (n % i == 0) { k = n / i; su = i; break; } } if (flag == 0) { printf( %d n , k); for (int i = 0; i < k; i++) { printf( %d , su); if (i != k - 1) printf( ); } printf( n ); } } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long i, j = 0, k, sum = 0, ctr = 0, c = 0, ok = 0; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long a, b, c; cin >> a >> b >> c; for (i = a; i >= 0; i--) { if (c >= i * 4 && b >= i * 2) { ok = i; break; } } cout << ok * 7; return 0; }
|
#include <bits/stdc++.h> const int MAXN = 1e5 + 10; int n, m, k, p; int h[MAXN], a[MAXN]; namespace solver1 { long long fin[MAXN]; bool check(long long x) { long long need = 0; static long long t[MAXN]; for (int i = 1; i <= n; i++) { need += (t[i] = std::max(0ll, (fin[i] - x + p - 1) / p)); } if (need > k * m) return 0; static int cnt[MAXN]; memset(cnt, 0, sizeof cnt); for (int i = 1; i <= n; i++) { for (int j = t[i] - 1; j >= 0; j--) { long long delta = fin[i] - x - (long long)j * p; if (delta <= h[i]) { cnt[1]++; } else if (h[i] + (long long)a[i] * (m - 1) < delta) { return 0; } else { cnt[(delta - h[i] + a[i] - 1) / a[i] + 1]++; } } } int tot = 0; for (int i = 1; i <= m; i++) { tot += cnt[i]; tot = std::max(0, tot - k); } return tot == 0; } void main() { for (int i = 1; i <= n; i++) { fin[i] = (long long)a[i] * m + h[i]; } long long l = 1, r = 1e15, ans = 1e15; while (l <= r) { long long mid = (l + r) >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else { l = mid + 1; } } printf( %lld n , ans); } } // namespace solver1 int main() { scanf( %d%d%d%d , &n, &m, &k, &p); for (int i = 1; i <= n; i++) { scanf( %d%d , h + i, a + i); } solver1::main(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
|
///////////////////////////////////////////////////////////////////
//=================================================================
// Copyright (c) Alorium Technology 2016
// ALL RIGHTS RESERVED
// $Id: $
//=================================================================
//
// File name: : alorium_lfsr.v
// Author : Jason Pecor
// Description : Simple LFSR module
//=================================================================
///////////////////////////////////////////////////////////////////
module alorium_lfsr
(
// Clock and Reset
input clk,
input reset_n,
// Inputs
input new_seed,
input enable,
input wire [7:0] seed,
input long_hb,
// Output
output reg heartbeat,
output reg [7:0] lfsr_data
);
reg [29:0] hb_cnt;
wire feedback;
assign feedback = ~(lfsr_data[7] ^ lfsr_data[5] ^
lfsr_data[4] ^ lfsr_data[3]);
always @(posedge clk) begin
if (!reset_n) begin
heartbeat <= 0;
hb_cnt <= 0;
// LFSR register cannot be all 1's for XNOR LFSR
lfsr_data <= 8'h01;
end
else if (new_seed) begin
// LFSR register cannot be all 1's for XNOR LFSR
lfsr_data <= &seed ? 8'h01 : seed;
hb_cnt <= hb_cnt + 1;
end
else if (enable) begin
lfsr_data <= {lfsr_data[6:0],feedback};
hb_cnt <= hb_cnt + 1;
end // else: !if(!reset_n)
if ((long_hb) && (hb_cnt > )) begin
hb_cnt <= 0;
heartbeat <= ~heartbeat;
end
else if ((!long_hb) && (hb_cnt > 9)) begin
hb_cnt <= 0;
heartbeat <= ~heartbeat;
end
end // always @ (posedge clk)
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "syntheziedviterbi.v"
//`include "viterbi_decoder.sdf"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_viterbi_decoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the Viterbi decoder
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire data; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] encoded_input; // Input signal - cx
reg clock; // Input signal - clk
reg reset_sig; // Input signal - reset
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
data,encoded_input,clock,reset_sig);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=10,
#10
reset_sig = 1'd1;
encoded_input = 2'd0;
// @t=20,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=30,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=40,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=50,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=60,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=70,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=80,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=90,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=100,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=110,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=120,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=130,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=140,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=150,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=160,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=170,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=180,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=190,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=200,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=210,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=220,
#10
reset_sig = 0;
encoded_input = $random;
// @t=230,
#10
reset_sig = 0;
encoded_input = $random;
// @t=240,
#10
reset_sig = 0;
encoded_input = $random;
// @t=250,s
#10
reset_sig = 0;
encoded_input = $random;
// @t=260,
#10
reset_sig = 0;
encoded_input = $random;
// @t=270,
#10
reset_sig = 0;
encoded_input = $random;
// @t=280,
#10
reset_sig = 0;
encoded_input = $random;
// @t=290,
#10
reset_sig = 0;
encoded_input = $random;
// @t=300,
#10
reset_sig = 0;
encoded_input = $random;
// @t=310,
#10
reset_sig = 0;
encoded_input = $random;
// @t=320,
#10
reset_sig = 0;
encoded_input = $random;
// @t=330,
#10
reset_sig = 0;
encoded_input = $random;
// @t=340,
#10
reset_sig = 0;
encoded_input = $random;
// @t=350,
#10
reset_sig = 0;
encoded_input = $random;
// @t=360,
#10
reset_sig = 0;
encoded_input = $random;
// @t=370,
#10
reset_sig = 0;
encoded_input = $random;
// @t=380,
#10
reset_sig = 0;
encoded_input = $random;
// @t=390,
#10
reset_sig = 0;
encoded_input = $random;
// @t=400,
#10
reset_sig = 1;
encoded_input = $random;
// @t=410,
#10
reset_sig = 0;
encoded_input = $random;
// @t=420,
#10
reset_sig = 0;
encoded_input = $random;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string str[51], temp; int main() { int t, f, a; int cnt = 0, ans = 0x3f3f3f3f; scanf( %d , &t); getchar(); for (int i = 0; i < t; i++) { cin >> str[i]; } for (int i = 0; i < t; i++) { cnt = 0; for (int j = 0; j < t; j++) { temp = str[j] + str[j]; if (temp.find(str[i]) == string::npos) { cout << -1 << endl; return 0; } cnt += temp.find(str[i]); } ans = min(ans, cnt); } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
`define intN 8
`define addrN 8
`include "primitives.v"
`include "tests_three_writes.v"
`include "array.v"
module tests_three_writes_tb;
`wire(Array, (`addrN, `intN), arr_in);
`wire(Array, (`addrN, `intN), arr_out);
`reg(simple, `addrN, addr1);
`reg(simple, `addrN, addr2);
`reg(simple, `addrN, addr3);
`reg(simple, `intN, data1);
`reg(simple, `intN, data2);
`reg(simple, `intN, data3);
`testbench(tests_three_writes_tb, 20)
array arr(.clk(clk),
`out(Array, 0, arr_in));
assign `to_bus(arr_out) = 1;
always @(posedge clk) begin
if(arr_in_valid & arr_in_we & arr_in_ready) begin
$display("arr[%d] <= %d", arr_in_addr, arr_in_di);
end
end
`in_ready(inst);
`inst_sync(tests_three_writes, inst, #())(
`sync(in_valid, out_ready),
`in(Array, 0, arr_in),
`in(simple, 1, addr1),
`in(simple, 2, data1),
`in(simple, 3, addr2),
`in(simple, 4, data2),
`in(simple, 5, addr3),
`in(simple, 6, data3),
`out(Array, 0, arr_out));
initial begin
addr1 = 1;
data1 = 10;
addr2 = 2;
data2 = 20;
addr3 = 3;
data3 = 30;
`start;
`wait_for(arr_out_valid);
@(posedge clk);
$finish;
end
endmodule // tests_three_writes_tb
|
#include <bits/stdc++.h> using namespace std; int main() { long long int q = 1; while (q--) { long long int n, i, t, j, k = 0, maxm = 0, ans; cin >> n; vector<long long int> v(n), v1(30), v2; map<long long int, long long int> m; for (long long int i = 0; i < 30; i++) v1[i] = 0; for (long long int i = 0; i < n; i++) { cin >> v[i]; t = v[i]; j = 0; while (t > 0) { v1[j] = v1[j] + t % 2; t = t / 2; j++; } } sort(v.begin(), v.end()); for (long long int i = 0; i < 30; i++) { if (v1[i] == 1) v2.push_back(i); } if (v2.size() == 0) { for (i = n - 1; i >= 0; i--) cout << v[i] << ; return 0; } for (long long int i = 0; i < n; i++) { t = v[i]; j = 0; k = 0; while (t > 0) { if (j == v2[k]) { if (t % 2 != 0) m[v[i]] += pow(2, j); k++; } t = t / 2; j++; } } for (auto it = m.begin(); it != m.end(); it++) { if ((it->second) > maxm) { maxm = it->second; ans = it->first; } } cout << ans << ; for (long long int i = 0; i < n; i++) { if (v[i] == ans) continue; else cout << v[i] << ; } } }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module conbus_arb(
input sys_clk,
input sys_rst,
input [6:0] req,
output [6:0] gnt
);
parameter [6:0] grant0 = 7'b0000001,
grant1 = 7'b0000010,
grant2 = 7'b0000100,
grant3 = 7'b0001000,
grant4 = 7'b0010000,
grant5 = 7'b0100000,
grant6 = 7'b1000000;
reg [6:0] state;
reg [6:0] next_state;
assign gnt = state;
always @(posedge sys_clk) begin
if(sys_rst)
state <= grant0;
else
state <= next_state;
end
always @(*) begin
next_state = state;
case(state)
grant0: begin
if(~req[0]) begin
if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
else if(req[3]) next_state = grant3;
else if(req[4]) next_state = grant4;
else if(req[5]) next_state = grant5;
else if(req[6]) next_state = grant6;
end
end
grant1: begin
if(~req[1]) begin
if(req[2]) next_state = grant2;
else if(req[3]) next_state = grant3;
else if(req[4]) next_state = grant4;
else if(req[5]) next_state = grant5;
else if(req[6]) next_state = grant6;
else if(req[0]) next_state = grant0;
end
end
grant2: begin
if(~req[2]) begin
if(req[3]) next_state = grant3;
else if(req[4]) next_state = grant4;
else if(req[5]) next_state = grant5;
else if(req[6]) next_state = grant6;
else if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
end
end
grant3: begin
if(~req[3]) begin
if(req[4]) next_state = grant4;
else if(req[5]) next_state = grant5;
else if(req[6]) next_state = grant6;
else if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
end
end
grant4: begin
if(~req[4]) begin
if(req[5]) next_state = grant5;
else if(req[6]) next_state = grant6;
else if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
else if(req[3]) next_state = grant3;
end
end
grant5: begin
if(~req[5]) begin
if(req[6]) next_state = grant6;
else if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
else if(req[3]) next_state = grant3;
else if(req[4]) next_state = grant4;
end
end
grant6: begin
if(~req[6]) begin
if(req[0]) next_state = grant0;
else if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
else if(req[3]) next_state = grant3;
else if(req[4]) next_state = grant4;
else if(req[5]) next_state = grant5;
end
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_4_V
`define SKY130_FD_SC_LP__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_4_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (a > b) { swap(a, b); } if (a == 0) return b; return gcd(b % a, a); } int invertBits(int num) { int x = log2(num) + 1; for (int i = 0; i < x; i++) num = (num ^ (1 << i)); return num; } string add(string f, string s) { reverse(f.begin(), f.end()); reverse(s.begin(), s.end()); int i = 0, j = 0; string t = ; int carry = 0; while (i < f.size() && j < s.size()) { int k = (f[i] - 0 ) + (s[j] - 0 ) + carry; carry = k / 10; int sum = k % 10; t += (sum + 0 ); i++; j++; } while (i < f.size()) { int k = (f[i] - 0 ) + carry; carry = k / 10; int sum = k % 10; t += (sum + 0 ); i++; } while (j < s.size()) { int k = (s[j] - 0 ) + carry; carry = k / 10; int sum = k % 10; t += (sum + 0 ); j++; } if (carry) { t += (carry + 0 ); } reverse(t.begin(), t.end()); return t; } int mulmod(int a, int b, int mod) { int res = 0; a = a % mod; while (b > 0) { if (b % 2 == 1) res = (res + a) % mod; a = (a * 2) % mod; b /= 2; } return res % mod; } int main() { long long int n; long long int m = 998244353; cin >> n; long long int i, a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } long long int ans = 0; for (i = 0; i < n; i++) { long long int k = a[i]; long long int mul = 1; while (k != 0) { long long int r = k % 10; ans = (ans % m + ((r % m) * (mul % m) * (n % m)) % m) % m; mul = mul * 10; mul = mul % m; ans = (ans % m + ((r % m) * (mul % m) * (n % m)) % m) % m; mul = mul * 10; mul = mul % m; k = k / 10; } } cout << (ans + m) % m; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_SYMBOL_V
`define SKY130_FD_SC_MS__A31OI_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int l = s.length(); int fc = 0; int sc = 0; for (int i = 0; i < l; i++) { if (s[i] == 4 ) fc++; if (s[i] == 7 ) sc++; } if (!fc && !sc) cout << -1 << endl; else if (sc > fc) cout << 7 << endl; else cout << 4 << endl; return 0; }
|
`timescale 1ns / 1ps
module teclado_TB;
reg Rx;
reg clk;
teclado uut(.clk(clk),.Rx(Rx));
parameter num=2*13'd7692;
always
begin
clk =1'b1;
#1;
clk =1'b0;
#1;
end
initial
begin
Rx=1;
#num;
Rx=0;
#num;
Rx=0;//1
#num;
Rx=0;
#num;
Rx=0;
#num;
Rx=1;
#num;
Rx=1;
#num;
Rx=1;
#num;
Rx=0;
#num;
Rx=0;//8
#num;
Rx=1;
#num;
Rx=1;
#num;
Rx=1;
#num;
// Otro
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=1;
#10;
// Seguidos
Rx=0;
#2;
Rx=1;//1
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;//8
#2;
Rx=1;
#2;
// Continuación
Rx=0;
#2;
Rx=1;//1
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
// Continuación
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
// La Otra Prueba
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;//1
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
end
initial begin: TEST_CASE
$dumpfile("teclado_TB.vcd");
$dumpvars(-1, uut);
#() $finish;
end
endmodule //
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; printf( %d , ((a ^ b) & (c | d)) ^ ((b & c) | (a ^ d))); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR4_PP_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1LL << 61; int n, r; long long a[30], b[30], k[30], p[30]; long long dfs(int u, bool op1) { long long res = -INF; if (u % 2 == 0) res = max(res, inner_product(a, a + n, k, 0LL)); if (u == 0) return res; if (!op1) { for (int i = 0; i < (n); i++) a[i] ^= b[i]; res = max(res, dfs(u - 1, true)); for (int i = 0; i < (n); i++) a[i] ^= b[i]; } long long tmp[30]; memcpy(tmp, a, sizeof a); for (int i = 0; i < (n); i++) a[i] = tmp[p[i]] + r; res = max(res, dfs(u - 1, false)); memcpy(a, tmp, sizeof a); return res; } int main() { int u; scanf( %d%d%d , &n, &u, &r); for (int i = 0; i < (n); i++) scanf( %I64d , a + i); for (int i = 0; i < (n); i++) scanf( %I64d , b + i); for (int i = 0; i < (n); i++) scanf( %I64d , k + i); for (int i = 0; i < (n); i++) scanf( %I64d , p + i), p[i]--; printf( %I64d n , dfs(u, false)); return 0; }
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: div.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module div (
denom,
numer,
quotient,
remain);
input [10:0] denom;
input [19:0] numer;
output [19:0] quotient;
output [10:0] remain;
wire [19:0] sub_wire0;
wire [10:0] sub_wire1;
wire [19:0] quotient = sub_wire0[19:0];
wire [10:0] remain = sub_wire1[10:0];
lpm_divide LPM_DIVIDE_component (
.denom (denom),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 11,
LPM_DIVIDE_component.lpm_widthn = 20;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "FALSE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "11"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "20"
// Retrieval info: USED_PORT: denom 0 0 11 0 INPUT NODEFVAL "denom[10..0]"
// Retrieval info: USED_PORT: numer 0 0 20 0 INPUT NODEFVAL "numer[19..0]"
// Retrieval info: USED_PORT: quotient 0 0 20 0 OUTPUT NODEFVAL "quotient[19..0]"
// Retrieval info: USED_PORT: remain 0 0 11 0 OUTPUT NODEFVAL "remain[10..0]"
// Retrieval info: CONNECT: @denom 0 0 11 0 denom 0 0 11 0
// Retrieval info: CONNECT: @numer 0 0 20 0 numer 0 0 20 0
// Retrieval info: CONNECT: quotient 0 0 20 0 @quotient 0 0 20 0
// Retrieval info: CONNECT: remain 0 0 11 0 @remain 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL div.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL div.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL div.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL div.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL div_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL div_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const long long int N = 2e5 + 5; void solve() { long long int n; cin >> n; double ans, pi = 3.14159265358979323846; double rad = (2.0 * sin(pi / (2.0 * (double)n))); ans = (cos(pi / (4.0 * n))) / sin(pi / (2.0 * (double)n)); cout << fixed << setprecision(15) << ans << n ; } signed main() { ios_base::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); long long int t = 1; cin >> t; while (t--) { solve(); } }
|
module cu_simulator (/*AUTOARG*/
// Outputs
cu2dispatch_wf_done, cu2dispatch_wf_tag_done,
// Inputs
clk, rst, all_wf_dispatched, dispatch2cu_wf_dispatch,
dispatch2cu_lds_base_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_start_pc_dispatch, dispatch2cu_vgpr_base_dispatch,
dispatch2cu_wf_size_dispatch, dispatch2cu_wf_tag_dispatch,
dispatch2cu_wg_wf_count
) ;
parameter CU_ID_WIDTH = 3;
parameter NUMBER_CU = 8;
parameter TAG_WIDTH = 15;
parameter WAVE_ITEM_WIDTH = 6;
parameter WF_COUNT_WIDTH = 4;
parameter MEM_ADDR_WIDTH = 32;
parameter MAX_WF = 200;
input clk, rst;
input all_wf_dispatched;
input [NUMBER_CU-1:0] dispatch2cu_wf_dispatch;
input [15:0] dispatch2cu_lds_base_dispatch;
input [8:0] dispatch2cu_sgpr_base_dispatch;
input [MEM_ADDR_WIDTH-1:0] dispatch2cu_start_pc_dispatch;
input [9:0] dispatch2cu_vgpr_base_dispatch;
input [WAVE_ITEM_WIDTH-1:0] dispatch2cu_wf_size_dispatch;
input [TAG_WIDTH-1:0] dispatch2cu_wf_tag_dispatch;
input [WF_COUNT_WIDTH-1:0] dispatch2cu_wg_wf_count;
output reg [NUMBER_CU-1:0] cu2dispatch_wf_done;
output reg [NUMBER_CU*TAG_WIDTH-1:0] cu2dispatch_wf_tag_done;
reg [MAX_WF-1:0] running_wf_valid;
reg [31:0] running_wf_cycle_counter [MAX_WF-1:0];
reg [14:0] running_tag[MAX_WF-1:0];
reg [CU_ID_WIDTH-1:0] running_cu_id[MAX_WF-1:0];
// Start wf
initial begin : START_WF_BLOCK
integer i;
integer curr_dispatched;
running_wf_valid = 0;
curr_dispatched = 0;
@(posedge clk);
@(negedge rst);
@(posedge clk);
forever begin
for (i=0; i<NUMBER_CU; i=i+1) begin
if(dispatch2cu_wf_dispatch[i])begin
running_tag[curr_dispatched] = dispatch2cu_wf_tag_dispatch;
running_wf_cycle_counter[curr_dispatched] = {$random} % 500;
running_wf_valid[curr_dispatched] = 1'b1;
running_cu_id[curr_dispatched] = i;
curr_dispatched = curr_dispatched + 1;
end
end
@(posedge clk);
end
end // initial begin
// Run wf
initial begin : RUN_WF_BLOCK
integer i;
@(posedge clk);
@(negedge rst);
@(posedge clk);
forever begin
for (i=0; i<MAX_WF; i=i+1) begin
if(running_wf_valid[i]) begin
if(running_wf_cycle_counter[i] != 0) begin
running_wf_cycle_counter[i] = running_wf_cycle_counter[i]-1;
end
end
end
@(posedge clk);
end
@(posedge clk);
end // initial begin
// Finish wf
initial begin : FINISH_WF_BLOCK
integer i;
cu2dispatch_wf_done = 0;
@(posedge clk);
@(negedge rst);
@(posedge clk);
while(!all_wf_dispatched ||
(|running_wf_valid) ) begin
for (i=0; i<MAX_WF; i=i+1) begin
if(running_wf_valid[i] &&
running_wf_cycle_counter[i]==0) begin
// Do not finish two wf on the same cycle in the same cu
if(!cu2dispatch_wf_done[running_cu_id[i]]) begin
cu2dispatch_wf_done[running_cu_id[i]] = 1'b1;
cu2dispatch_wf_tag_done[running_cu_id[i]*15+:15]
= running_tag[i];
running_wf_valid[i] = 1'b0;
end
@(posedge clk);
cu2dispatch_wf_done = 0;
end // if (running_wf_valid[i] &&...
end // for (i=0; i<MAX_WF; i=i+1)
@(posedge clk);
end // while (!all_wf_dispatched ||...
repeat(100) @(posedge clk);
$stop;
end // initial begin
endmodule // cu_simulator
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:23:22 10/18/2015
// Design Name:
// Module Name: fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo
#(
B = 8, //Num of bits in data word
W = 4 //Num addr bits of FIFO
//Num words in FIFO=2^FIFO_W
)
(
input wire clk, reset,
input wire wr, rd,
input wire [B-1:0] w_data,
output wire full, empty,
output wire [B-1:0] r_data
);
//signal declaration
reg [B-1:0] array_reg [0:2**W-1]; //register array
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
//body
//register file write operation
always @(posedge clk)
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
//register file read operation
assign r_data = array_reg[r_ptr_reg];
//write enable only when FIFO is not full
assign wr_en = wr & ~full_reg;
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset)
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next; //Indice para leer el sig bit
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
//next-state logic for read and write pointers
always @*
begin
//successive pointer values
w_ptr_succ = w_ptr_reg + 4'b0001;
r_ptr_succ = r_ptr_reg + 4'b0001;
// default: keep old values
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
// 2'b00: no op
2'b01: //read
if (~empty_reg) //not empty
begin
r_ptr_next = r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: //write
if (~full_reg) //not full
begin
w_ptr_next = w_ptr_succ;
empty_next = 1'b0;
if (w_ptr_succ==r_ptr_reg)
full_next = 1'b1;
end
2'b11: //write and read
begin
w_ptr_next = w_ptr_succ;
r_ptr_next = r_ptr_succ;
end
endcase
end
//output
assign full = full_reg;
assign empty = empty_reg;
endmodule
|
/**
* Instantiates a 9Kib block RAM for the VGA buffer, and
* exposes an interface to write 32-bit blocks to 64
* addresses and read 8-bit blocks from 256 addresses.
* We are only using 2Kib of memory, but the physical
* hardware in the Spartan 6 only has two of these 9Kib
* block RAM banks.
*
* @author Robert Fotino, 2016
*/
module vga_block_ram
(
input wr_clk,
input wr_en,
input [5:0] wr_addr,
input [31:0] wr_data,
input rd_clk,
input [7:0] rd_addr,
output [7:0] rd_data
);
// Data out for the underlying block RAM. Output
// is 32 bits, but we want to have byte-level indexing
wire [31:0] DO;
assign rd_data = DO[{rd_addr[1:0], 3'b0}+:8];
// Instantiate a 9Kib simple dual-port block RAM
BRAM_SDP_MACRO
#(
.BRAM_SIZE("9Kb"),
.DEVICE("SPARTAN6"),
.WRITE_WIDTH(32),
.READ_WIDTH(32),
.DO_REG(0),
.INIT_FILE("NONE"),
.SRVAL(72'b0),
.INIT(72'b0)
)
BRAM_SDP_MACRO_inst
(
.DO(DO),
.DI(wr_data),
.RDADDR({ 2'b0, rd_addr[7:2] }),
.RDCLK(rd_clk),
.RDEN(1'b1),
.REGCE(REGCE),
.RST(1'b0),
.WE(4'b1111),
.WRADDR({ 2'b0, wr_addr }),
.WRCLK(wr_clk),
.WREN(wr_en)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int dd[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; vector<vector<int>> mat(1000, vector<int>(1000)); int n, m, si, sj; void bfs() { mat[si][sj] = 1; queue<pair<int, int>> q; q.push({si, sj}); while (!q.empty()) { auto p = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int ti = p.first + dd[i][0]; int tj = p.second + dd[i][1]; if (ti >= 0 && tj >= 0 && ti < n && tj < m && !mat[ti][tj]) { mat[ti][tj] = mat[p.first][p.second] + 1; q.push({ti, tj}); } } } } int main() { ios_base::sync_with_stdio(0); cin >> n >> m; int ei, ej; vector<pair<int, pair<int, int>>> v; for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < m; j++) { if (s[j] == E ) { si = i, sj = j; mat[i][j] = 0; } else { if (s[j] == T ) mat[i][j] = -1; else { mat[i][j] = 0; if (s[j] == S ) ei = i, ej = j; else v.push_back({s[j] - 0 , {i, j}}); } } } } bfs(); int ans = 0; int my = mat[ei][ej]; for (auto i : v) { int cur = mat[i.second.first][i.second.second]; if (cur && cur <= my) { ans += i.first; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long MAX = 200005; bool prime[MAX]; void sieve() { memset(prime, true, sizeof(prime)); prime[0] = prime[1] = false; for (long long p = 2; p * p <= MAX; p++) { if (prime[p] == true) { for (long long i = p * 2; i <= MAX; i += p) prime[i] = false; } } } long long power(long long a, long long b, long long m) { if (b == 0) return 1; if (b == 1) return a % m; long long t = power(a, b / 2, m); t = (t * t) % m; if (b & 1) t = (t * a) % m; return t; } long long modInverse(long long a, long long m) { return power(a, m - 2, m); } long long __gcd(long long a, long long b) { if (b == 0) return a; return __gcd(b, a % b); } bool cmp(const pair<long long, long long> &l, const pair<long long, long long> &r) { return l.first < r.first; } long long n, q; vector<vector<long long> > g; long long visited[MAX]; long long num[MAX]; long long cnt[MAX]; long long k; long long dfs(long long node) { visited[node] = 1; num[node] = k; k++; long long p = 0, flag = 0; for (auto i : g[node]) { if (!visited[i]) { flag = 1; p += dfs(i); } } if (flag) { cnt[node] = p; return 1 + p; } else { cnt[node] = 0; return 1; } } void solve() { cin >> n >> q; g.resize(n + 1, vector<long long>()); long long x; for (long long i = 2; i <= n; i++) { cin >> x; g[i].push_back(x); g[x].push_back(i); } memset(visited, 0, sizeof(visited)); memset(num, 0, sizeof(num)); memset(cnt, 0, sizeof(cnt)); k = 1; dfs(1); map<long long, long long> m; for (long long i = 0; i < MAX; i++) m[num[i]] = i; while (q--) { long long x, y; cin >> x >> y; if (cnt[x] < y - 1) cout << -1 << n ; else { long long w = num[x]; cout << m[w + y - 1] << n ; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); ; long long t; t = 1; while (t--) { solve(); cout << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 15000001; int64_t primes[N]; int64_t gcd(int64_t a, int64_t b) { if (a == 0) return b; else return gcd(b % a, a); } int64_t Power(int64_t base, int64_t e) { if (e == 0) return 1; int64_t ans = base; e--; while (e) { if (e & 1) ans = (ans * base); base = (base * base); e >>= 1; } return (ans); } void sieve() { for (int64_t i = 2; i <= N; i++) { if (primes[i] == -1) { for (int64_t j = i; j <= N; j += i) primes[j] = i; } } } int main() { for (int64_t i = 0; i < N; i++) { primes[i] = -1; } ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); sieve(); map<int64_t, int64_t> mp; int64_t n; cin >> n; int64_t a[n]; int64_t tmp; for (int64_t i = 0; i < n; i++) cin >> a[i]; int64_t ggcd; ggcd = a[0]; for (int64_t i = 0; i < n; i++) { ggcd = gcd(ggcd, a[i]); } int64_t ggcd2 = 1; for (int64_t i = 0; i < n; i++) { a[i] = a[i] / ggcd; } for (int64_t i = 0; i < n; i++) { tmp = a[i]; while (tmp > 1) { int64_t y = primes[tmp]; while (tmp % y == 0) { tmp = tmp / y; } mp[y]++; } } int64_t freq = 0; int64_t val = ggcd; for (auto kk : mp) { if (freq <= kk.second) { val = kk.first; freq = kk.second; } } if (freq) { cout << (n - freq) << endl; } else cout << -1 << endl; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_linkStatus (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 15: 0] in_port;
input reset_n;
wire clk_en;
wire [ 15: 0] data_in;
wire [ 15: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int INF = 0x3f3f3f3f; const long long inf = 0x3f3f3f3f3f3f3f3f; const int mod = 1e9 + 7; const int maxn = 1e3 + 5; int n, m, qq, s[maxn][maxn], f[maxn][maxn]; bool vis[maxn][maxn]; int a[4] = {0, 1, 0, -1}; int b[4] = {-1, 0, 1, 0}; bool judge(int x, int y) { for (int i = 0; i <= 3; i++) { int xx = x + a[i], yy = y + b[i]; if (xx <= 0 || xx > n || yy <= 0 || yy > m) continue; if (s[xx][yy] == s[x][y]) return true; } return false; } void bfs() { queue<pair<int, int> > q; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (judge(i, j)) { vis[i][j] = 1; f[i][j] = 0; q.push({i, j}); } } } while (!q.empty()) { int x = q.front().first; int y = q.front().second; q.pop(); for (int i = 0; i <= 3; i++) { int xx = x + a[i], yy = y + b[i]; if (xx <= 0 || xx > n || yy <= 0 || yy > m) continue; if (vis[xx][yy]) continue; f[xx][yy] = f[x][y] + 1; vis[xx][yy] = 1; q.push({xx, yy}); } } } int main() { scanf( %d%d%d , &n, &m, &qq); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %1d , &s[i][j]); } } bfs(); while (qq--) { int x, y; long long t; scanf( %d%d%lld , &x, &y, &t); if (vis[x][y]) { if (t < f[x][y]) printf( %d n , s[x][y]); else printf( %d n , s[x][y] ^ ((t - f[x][y]) & 1)); } else { printf( %d n , s[x][y]); } } }
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#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; const char choice[6][2] = {{ A , C }, { A , G }, { A , T }, { C , G }, { C , T }, { G , T }}; int n, m; string str[maxn]; int ord[2][maxn][6], cnt[2][maxn]; string out[maxn]; void print(int rc, int k) { for (int i = 0; i < n; i++) out[i] = ; if (rc == 0) { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) out[i] += choice[(i & 1) ? 5 - k : k][(j & 1) ^ ord[0][i][k]]; } else { for (int j = 0; j < m; j++) for (int i = 0; i < n; i++) out[i] += choice[(j & 1) ? 5 - k : k][(i & 1) ^ ord[1][j][k]]; } for (int i = 0; i < n; i++) cout << out[i] << endl; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> str[i]; memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < n; i++) { for (int k = 0; k < 6; k++) { int now1 = 0, now2 = 0; for (int j = 0; j < m; j++) { now1 += (str[i][j] != choice[(i & 1) ? 5 - k : k][j & 1]); now2 += (str[i][j] != choice[(i & 1) ? 5 - k : k][(j & 1) ^ 1]); } ord[0][i][k] = now1 < now2 ? 0 : 1; cnt[0][k] += min(now1, now2); } } for (int j = 0; j < m; j++) { for (int k = 0; k < 6; k++) { int now1 = 0, now2 = 0; for (int i = 0; i < n; i++) { now1 += (str[i][j] != choice[(j & 1) ? 5 - k : k][i & 1]); now2 += (str[i][j] != choice[(j & 1) ? 5 - k : k][(i & 1) ^ 1]); } ord[1][j][k] = now1 < now2 ? 0 : 1; cnt[1][k] += min(now1, now2); } } int ans = 0x3f3f3f3f, RC, K; for (int rc = 0; rc <= 1; rc++) { for (int k = 0; k < 6; k++) { if (cnt[rc][k] < ans) ans = cnt[rc][k], RC = rc, K = k; } } print(RC, K); }
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// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function int mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
typedef logic [31:0] word_t;
reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */;
reg [16:1] [31:0] memp32 /*verilator public_flat_rw @(posedge clk) */;
reg [16:1] [30:0] memp31 /*verilator public_flat_rw @(posedge clk) */;
reg [15:1] [32:0] memp33 /*verilator public_flat_rw @(posedge clk) */;
word_t [16:1] memw /*verilator public_flat_rw @(posedge clk) */;
integer i, status;
`define CHECK_MEM(mem, words) \
for (i = words; i > 0; i--) \
if (integer'(mem[i]) !== i) begin \
$write("%%Error: %s[%d] : GOT = %d EXP = %d\n", `"mem`", i, mem[i], i); \
status = -1; \
end
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`else
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_memory.cpp: C Test failed (rc=%0d)\n", status);
$stop;
end
`CHECK_MEM(mem0, 16)
`CHECK_MEM(memp32, 16)
`CHECK_MEM(memp31, 16)
`CHECK_MEM(memp33, 15)
`CHECK_MEM(memw, 16)
if (status!=0) begin
$write("%%Error: Verilog memory checks failed\n");
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always 3.1.2A always reg_lvalue <= constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4'h5)
$display("FAILED - 3.1.2A always reg_lvalue = constant\n");
else
begin
$display("PASSED\n");
$finish;
end
always value1 <= 4'h5 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; void checkDefine(); string x; string y; string z; int main() { cin >> x >> y; long long int n = x.size(); for (int i = (0), _b = (n - 1); i <= _b; i++) { if (x[i] < y[i]) { cout << -1; return 0; } } cout << y; return 0; } void checkDefine() { long long int n, a[200005]; map<long long int, long long int> m; cin >> n; for (int i = (0), _b = (n - 1); i <= _b; i++) { cin >> a[i]; m[a[i]]++; } string s; cin >> s; { cout << s << = ; cout << (s) << endl; }; { cout << a << = ; for (int _ = 0, _a = (n); _ < _a; _++) cout << a[_] << ; cout << endl; }; { cout << ------------ << = ; cout << ( ------------ ) << endl; }; for (__typeof(m.begin()) it = m.begin(); it != m.end(); ++it) { cout << it->first << << it->second << endl; } }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:41:02 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_stub.v
// Design : zqynq_lab_1_design_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[47:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bid[47:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_arid[47:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rid[47:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [47:0]m_axi_awid;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [47:0]m_axi_bid;
input [7:0]m_axi_bresp;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [47:0]m_axi_arid;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [47:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
endmodule
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