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`timescale 1ns / 1ps
`define intN 32
`define addrN 10
`include "primitives.v"
`include "tests_axil_map_w.v"
`include "array.v"
module tests_axil_map_w_tb;
localparam N = 1024;
`wire(Array, (`addrN, `intN), arr);
wire `intT res;
integer write_seed = 21;
integer read_seed = 42;
`reg(stream, `intN, sRA);
`wire(stream, `intN, sR);
`reg(stream, `intN, sWA);
`reg(stream, `intN, sW);
`wire(stream, 1, sB);
reg `intT sRA_next;
assign sR_ready = out_ready;
assign sB_ready = out_ready;
`testbench(tests_axil_map_w_tb, 5000)
array #(.N(N))
array(.clk(clk),
`out(Array, 0, arr));
`in_ready(inst);
`inst_sync(tests_axil_map_w, inst, #())(
`sync(in_valid, out_ready),
`in(Array, 0, arr),
`in(stream, 1, sRA),
`in(stream, 2, sWA),
`in(stream, 3, sW),
`out(stream, 0, sR),
`out(null_stream, 1, sB));
integer i;
initial begin
sRA = 0;
sRA_next = 0;
sRA_valid = `false;
sWA = 0;
sWA_valid = `false;
sW = 0;
sW_valid = `false;
`start;
// write some data
for(i = 0; i < N; i = i + 1) begin
sWA = i;
sWA_valid = `true;
sW = i;
sW_valid = `true;
`wait_for(sWA_ready && sW_ready);
if($random(write_seed) & 1) begin
sWA_valid = `false;
sW_valid = `false;
@(posedge clk);
sWA_valid = `true;
sW_valid = `true;
end
sRA_valid = `true;
end
sWA_valid = `false;
sW_valid = `false;
sWA = N;
`wait_for(sRA == N-1 && sR_valid);
nrst = `false;
#2;
$display("done");
$finish;
end
always @(posedge clk) begin
if(sRA_ready) begin
if(sRA_next < sWA & ($random(read_seed) & 1)) begin
sRA <= sRA_next;
sRA_next <= sRA_next + 1;
end
end
if(sR_valid & sR != sRA + 3)
$display("MISMATCH arr(%d) = %d", sRA, sR);
end
endmodule // tests_axil_map_w_tb
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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int l = s.size(); int a[2]; int b[2]; a[0] = a[1] = 0; b[0] = b[1] = 0; long long ans_odd = 0LL; long long ans_even = 0LL; for (int i = 0; i < l; i++) { ans_odd++; if (s[i] == a ) { ans_even += a[1 - i % 2]; ans_odd += a[i % 2]; } else { ans_even += b[1 - i % 2]; ans_odd += b[i % 2]; } a[i % 2] += (s[i] == a ); b[i % 2] += (s[i] == b ); } cout << ans_even << << ans_odd << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; namespace scanfuck { const int L = (1 << 21) + 1; struct io { char ibuf[L], *iS, *iT, obuf[L], *oS, *oT, c, st[55]; int f, tp; void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } void putc(char x) { *oS++ = x; if (oS == oT) flush(); } template <class T> T rd() { register T x = 0; for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, L, stdin), (iS == iT ? EOF : *iS++)) : *iS++); !isdigit(c); c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, L, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; for (x = 0; isdigit(c); c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, L, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) x = x * 10 + (c & 15); return x * f; } template <class T> void print(T x) { if (!x) putc( 0 ); else { if (x < 0) putc( - ), x = -x; for (tp = 0; x; st[tp++] = x % 10 + 48, x /= 10) ; for (tp--; ~tp; putc(st[tp--])) ; } } void gs(char* s, int& l) { for (c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, L, stdin), (iS == iT ? EOF : *iS++)) : *iS++); !isalpha(c); c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, L, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) ; for (l = 0; isalpha(c); c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, L, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) s[l++] = c; } void ps(const char* s) { for (tp = 0; tp < strlen(s); ++tp) putc(s[tp]); } io() : oS(obuf), oT(obuf + L - 1) {} ~io() { flush(); } } ip; } // namespace scanfuck int n = scanfuck::ip.rd<int>(), m = scanfuck::ip.rd<int>(), k = scanfuck::ip.rd<int>(); inline bool judge() { if (!(n & 1)) return 1; int t = sqrt(m); for (register int i = 1; i <= t; ++i) if (m % i == 0 && (i >= k && m / i > 1 || i > 1 && m / i >= k)) return 0; return 1; } int main() { scanfuck::ip.ps(judge() ? Marsel : Timur ); }
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#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n, i, j; cin >> n; long long int arr[n][n]; for (i = 0; i < n; i++) { string s; cin >> s; for (j = 0; j < n; j++) { long long int temp; temp = s[j] - 48; arr[i][j] = temp; } } int flag = 1; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (arr[i][j] == 1) { if (j != n - 1 && i != n - 1) { if (arr[i + 1][j] != 1 && arr[i][j + 1] != 1) { flag = 0; break; } } } } if (flag == 0) break; } if (flag == 1) { cout << YES n ; } else { cout << NO n ; } } }
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#include <bits/stdc++.h> using namespace std; const unsigned long long hash1 = 201326611; const double eps = 1e-8; const long long INF = 0x3f3f3f3f3f3f3f3f; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const int N = 255; const int M = 12; const int dif = 26; const double PI = acos(-1.0); inline void Mod(long long& x) { if (x >= mod) x -= mod; } void BinaryBitset(int n) { cout << bitset<sizeof(int) * 4>(n) << endl; } int n, m; long long c[N][N], m0[N], m1[N], dp[N][N]; void init(int n) { m0[0] = m1[0] = 1; for (int i = 1; i <= n; i++) { m0[i] = m0[i - 1] * m % mod; m1[i] = m1[i - 1] * (m - 1) % mod; } c[1][0] = 1; c[1][1] = 1; c[0][0] = 1; for (int i = 1; i <= n; i++) c[i][0] = 1, c[i][i] = 1; for (int i = 2; i <= n; i++) { for (int j = 1; j < n; j++) { c[i][j] = (c[i - 1][j - 1] + c[i - 1][j]) % mod; } } } int main() { scanf( %d%d , &n, &m); init(n); for (int i = 1; i <= n; i++) dp[1][i] = c[n][i] * m1[n - i] % mod; for (int i = 2; i <= n; i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k <= j; k++) { dp[i][j] = (dp[i][j] + c[n - k][j - k] * dp[i - 1][k] % mod * m1[n - j] % mod * m0[k] % mod) % mod; if (j == k) dp[i][j] = ((dp[i][j] - m1[n] * dp[i - 1][k] % mod + mod) % mod + mod) % mod; } } } printf( %lld n , dp[n][n]); }
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// Name: WcaReadWordReg.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaReadWordReg
(
input wire reset, //Active Hi
input wire clock, //System clock, should be synchronous with WcaRegbus
input wire enableIn, //Allows input if specified.
input wire [15:0] in,
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire [7:0] Q0;
wire [7:0] Q1;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire read = addrValid & rbusCtrl[3];
wire enable = enableIn & ~addrValid; //Latch if address is us.
//Alternate Register for two pulse read.
reg select;
always @(posedge rbusCtrl[0])
begin
if( reset | ~addrValid)
select <= 1'h0;
else if(rbusCtrl[1] & addrValid)
select <= ~select;
end
// Only allow latching when addres is not valid. If preparing for a read, everything must be stable.
WcaRegCore8 sr1( .Data(in[15:8]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q1));
WcaRegCore8 sr0( .Data(in[7:0]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q0));
//Place data on the buss if reading.
assign rbusData = (read & select) ? Q1 : 8'bz;
assign rbusData = (read & ~select) ? Q0 : 8'bz;
endmodule // WcaReadWordReg
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#include <bits/stdc++.h> using namespace std; const int maxN = 200009; vector<int> a; vector<int> b; vector<int> bb; int main() { long long s, x; cin >> s >> x; int s1 = s, x1 = x; int ans = 0; for (int i = 0; i < 45; i++) { if ((s & ((long long)1 << i)) && (x & ((long long)1 << i))) ans++; if (!(s & ((long long)1 << i)) && (x & ((long long)1 << i))) { cout << 0; return 0; } if ((s & ((long long)1 << i)) && !(x & ((long long)1 << i))) { cout << 0; return 0; } if (!(s & ((long long)1 << i)) && !(x & ((long long)1 << i))) { if ((s & ((long long)1 << (i + 1))) && !(x & ((long long)1 << (i + 1)))) { s -= ((long long)1 << (i + 1)); } if (!(s & ((long long)1 << (i + 1))) && (x & ((long long)1 << (i + 1)))) { s -= ((long long)1 << (i + 1)); } } } if (s1 != x1) cout << ((long long)1 << ans); else cout << ((long long)1 << ans) - 2; return 0; }
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//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_comm.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// Nathan Yawn () ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_comm.v,v $
// Revision 1.3 2009-05-17 20:55:57 Nathan
// Changed email address to opencores.org
//
// Revision 1.2 2008/07/22 18:23:25 Nathan
// Added clock and reset outputs to make simulation system simpler. Fixed P_TRST signal name. Added fflush calls to make file IO work as quickly as possible. Write the data out bit on falling clock edge. Cleanup.
//
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.3 2001/09/24 14:06:13 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.2 2001/09/20 10:10:30 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
`define GDB_IN "e:/tmp/gdb_in.dat"
`define GDB_OUT "e:/tmp/gdb_out.dat"
module dbg_comm(
SYS_CLK,
SYS_RSTN,
P_TMS,
P_TCK,
P_TRST,
P_TDI,
P_TDO
);
parameter Tp = 20;
output SYS_CLK;
output SYS_RSTN;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
// Signal for the whole system
reg SYS_CLK;
reg SYS_RSTN;
// For handling data from the input file
integer handle1, handle2;
reg [4:0] memory[0:0];
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
// Temp. signal
reg [3:0] in_word_r;
// Provide the wishbone / CPU / system clock
initial
begin
SYS_CLK = 1'b0;
forever #5 SYS_CLK = ~SYS_CLK;
end
// Provide the system reset
initial
begin
SYS_RSTN = 1'b1;
#200 SYS_RSTN = 1'b0;
#5000 SYS_RSTN = 1'b1;
end
// Set the initial state of the JTAG pins
initial
begin
in_word_r = 4'h0; // This sets the TRSTN output active...
end
// Handle input from a file for the JTAG pins
initial
begin
#5500; // Wait until reset is complete
while(1)
begin
#Tp;
$readmemh(`GDB_OUT, memory);
if(!(memory[0] & 5'b10000))
begin
in_word_r = memory[0][3:0];
handle1 = $fopen(`GDB_OUT);
$fwrite(handle1, "%h", 5'b10000 | memory[0]); // To ack that we read dgb_out.dat
$fflush(handle1);
$fclose(handle1);
end
end
end
// Send the current state of the JTAG output to a file
always @ (P_TDO or negedge P_TCK)
begin
handle2 = $fopen(`GDB_IN);
$fdisplay(handle2, "%b", P_TDO);
$fflush(handle2);
$fclose(handle2);
end
// Note these must match the bit definitions in the JTAG bridge program (adv_jtag_bridge)
assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];
endmodule // TAP
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#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 3; void read(int &x) { char ch; bool flag = 0; for (ch = getchar(); !isdigit(ch) && ((flag |= (ch == - )) || 1); ch = getchar()) ; for (x = 0; isdigit(ch); x = (x << 1) + (x << 3) + ch - 48, ch = getchar()) ; x *= 1 - 2 * flag; } string fuck[maxn]; int edge[105][105]; map<string, int> cou; int a[105], b[105]; int out = -1; vector<string> output; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { string tmp; cin >> tmp; fuck[i] = tmp; cou[tmp] = i; } for (int i = 0; i < m; i++) { string c, d; cin >> c >> d; edge[cou[c]][cou[d]] = 1; edge[cou[d]][cou[c]] = 1; } int aa[50]; for (int i = 0; i < (1 << n); i++) { memset(aa, 0, sizeof(aa)); int top = 0; for (int j = 0; j < n; j++) { if (i & (1 << j)) { aa[j] = 1; top++; } } bool f = 1; for (int j = 0; j < n; j++) { for (int k = j + 1; k < n; k++) { if (aa[j] && aa[k] && edge[j][k]) { f = 0; break; } } } if (!f) continue; if (top > out) { out = top; output.clear(); for (int j = 0; j < n; j++) { if (aa[j]) output.push_back(fuck[j]); } } } cout << output.size() << endl; sort(output.begin(), output.begin() + out); for (int i = 0; i < output.size(); i++) cout << output[i] << endl; return 0; }
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#include <bits/stdc++.h> int dr[] = {2, 2, -2, -2, 1, -1, 1, -1}; int dc[] = {1, -1, 1, -1, 2, 2, -2, -2}; int dr1[] = {0, 0, 1, 1, 1, -1, -1, -1}; int dc1[] = {1, -1, 1, 0, -1, 0, 1, -1}; int dr2[] = {0, 0, 1, -1}; int dc2[] = {1, -1, 0, 0}; using namespace std; vector<int> adj[1000005]; int a[1000005], b[1000005], dp1[1000005]; long long get(string t) { if (t == IN ) return 0; if (t == AND ) return 1; if (t == XOR ) return 2; if (t == OR ) return 3; if (t == NOT ) return 4; } long long get1(long long x, long long y, long long v) { if (a[v] == 1) return (x & y); if (a[v] == 2) return (x ^ y); if (a[v] == 3) return (x | y); } long long dfs(long long u) { if (a[u] == 0) { dp1[u] = b[u]; return dp1[u]; } long long i, j; if (adj[u].size() == 1) { long long p = adj[u][0]; long long r = dfs(p) ^ 1; dp1[u] = r; return r; } else { long long p = adj[u][0]; long long q = adj[u][1]; p = dfs(p); q = dfs(q); long long r; if (a[u] == 1) r = p & q; else if (a[u] == 2) r = p ^ q; else if (a[u] == 3) r = p | q; dp1[u] = r; return r; } } int dp[1000005][2][2]; long long cal(long long x, long long f, long long f1) { if (f1 == 0) return (dp1[x] == f); if (a[x] == 0) { if (b[x] ^ 1 == f) return 1; return 0; } int &r = dp[x][f][f1]; if (r != -1) return r; r = 0; if (adj[x].size() == 1) { long long p = adj[x][0]; r = cal(p, f ^ 1, f1); return r; } else { long long i, j; long long p = adj[x][0]; long long q = adj[x][1]; for (i = 0; i < 2; i++) { for (j = 0; j < 2; j++) { long long p1 = get1(i, j, x); if (p1 == f) { long long r1 = cal(p, i, f1) & cal(q, j, 1 - f1); long long r2 = cal(p, i, 1 - f1) & cal(q, j, f1); r |= r1; r |= r2; } } } return r; } } int mark[1000005]; void print(long long x, long long f, long long f1) { if (a[x] == 0) { mark[x] = 1; return; } if (adj[x].size() == 1) { long long p = adj[x][0]; print(p, f ^ 1, f1); return; } long long i, j; long long p = adj[x][0]; long long q = adj[x][1]; for (i = 0; i < 2; i++) { for (j = 0; j < 2; j++) { long long p1 = get1(i, j, x); if (p1 == f) { long long r1 = cal(p, i, f1) & cal(q, j, 1 - f1); if (r1 == 1) { print(p, i, f1); } r1 = cal(p, i, 1 - f1) & cal(q, j, f1); if (r1 == 1) { print(q, j, f1); } } } } } int main() { int n, i, j, x, y; while (cin >> n) { for (i = 1; i <= n; i++) { string t; cin >> t; a[i] = get(t); if (a[i] == 0 || a[i] == 4) { cin >> x; if (a[i] == 0) b[i] = x; else adj[i].push_back(x); } else { cin >> x >> y; adj[i].push_back(x); adj[i].push_back(y); } } long long ans = dfs(1); memset(dp, -1, sizeof(dp)); long long p = cal(1, ans ^ 1, 1); print(1, ans ^ 1, 1); for (i = 1; i <= n; i++) { if (a[i] == 0) { if (mark[i] == 0) cout << ans; else cout << (ans ^ 1); } } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, q; cin >> n >> q; string s; cin >> s; int pref[n + 1]; memset(pref, 0, sizeof(pref)); set<int> arr[2 * n + 5]; for (int i = 0; i < 2 * n + 5; i++) { set<int> ss; arr[i] = ss; } for (int i = 1; i <= n; i++) { if (s[i - 1] == + ) { if (i % 2 == 1) { pref[i] = pref[i - 1] + 1; } else { pref[i] = pref[i - 1] - 1; } } else { if (i % 2 == 1) { pref[i] = pref[i - 1] - 1; } else { pref[i] = pref[i - 1] + 1; } } arr[pref[i] + n].insert(i); } for (int i = 0; i < q; i++) { int l, r; cin >> l >> r; int val = pref[r] - pref[l - 1]; if (val == 0) { cout << 0 << endl; } else { if (abs(val) % 2 == 1) { if (val < 0) { val--; } else { val++; } int half = pref[l - 1] + val / 2; half += n; auto it = arr[half].lower_bound(l); int res = *it; cout << 1 << endl; cout << res << endl; } else { int diff = pref[r] - pref[r - 1]; val -= diff; if (val < 0) { val--; } else { val++; } int half = pref[l - 1] + val / 2; half += n; auto it = arr[half].lower_bound(l); int res = *it; cout << 2 << endl; cout << res << << r << endl; } } } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, i; cin >> n; long long int a[n], b[n], c[n + 1], x = n - 1; for (i = 0; i < n; i++) { b[i] = 0; c[i + 1] = 1; } c[0] = 1; for (i = 0; i < n; i++) { cin >> a[i]; a[i]--; b[a[i]]++; if (a[i] == x) { while (b[x]) { if (x == 0 && b[x]) { x = -1; break; } x--; if (x == 0 && b[x]) { x = -1; break; } } } c[i + 1] += i + 1 - (n - 1 - x); } for (i = 0; i <= n; i++) cout << c[i] << ; }
|
#include <bits/stdc++.h> using namespace std; char A[100 + 3], B[100 + 3], C[100 + 3], Ans[100 + 3]; int f[100 + 3][100 + 3][100 + 3], prei[100 + 3][100 + 3][100 + 3], prej[100 + 3][100 + 3][100 + 3], prek[100 + 3][100 + 3][100 + 3]; int Go[100 + 3][26], fail[100 + 3], la, lb, lc, len, ansi, ansj, ansk; int main() { scanf( %s%s%s , A + 1, B + 1, C + 1); la = strlen(A + 1); lb = strlen(B + 1); lc = strlen(C + 1); Go[0][C[1] - A ] = 1; Go[1][C[1] - A ] = 1; Go[1][C[2] - A ] = 2; for (int i = 2; i <= lc; i++) { int w = fail[i - 1]; for (; w && C[w + 1] != C[i]; w = fail[w]) ; if (C[i] == C[w + 1]) w++; fail[i] = w; for (int j = 0; j < 26; j++) { int w = i; for (; w && C[w + 1] - A != j; w = fail[w]) ; if (C[w + 1] - A == j) w++; Go[i][j] = w; } } memset(f, 130, sizeof(f)); f[0][0][0] = 0; for (int i = 0; i < la; i++) for (int j = 0; j < lb; j++) for (int k = 0; k < lc; k++) { if (f[i][j][k] < 0) continue; if (f[i + 1][j][k] < f[i][j][k]) { f[i + 1][j][k] = f[i][j][k]; prei[i + 1][j][k] = i; prej[i + 1][j][k] = j; prek[i + 1][j][k] = k; } if (f[i][j + 1][k] < f[i][j][k]) { f[i][j + 1][k] = f[i][j][k]; prei[i][j + 1][k] = i; prej[i][j + 1][k] = j; prek[i][j + 1][k] = k; } if (A[i + 1] == B[j + 1]) { int tk = Go[k][A[i + 1] - A ]; if (f[i + 1][j + 1][tk] < f[i][j][k] + 1) { f[i + 1][j + 1][tk] = f[i][j][k] + 1; prei[i + 1][j + 1][tk] = i; prej[i + 1][j + 1][tk] = j; prek[i + 1][j + 1][tk] = k; } } } for (int i = 1; i <= la; i++) for (int j = 1; j <= lb; j++) for (int k = 0; k < lc; k++) if (f[i][j][k] > f[ansi][ansj][ansk]) { ansi = i, ansj = j, ansk = k; } len = f[ansi][ansj][ansk]; if (!len) { printf( 0 ); return 0; } for (int w = len; w;) { int ti = prei[ansi][ansj][ansk], tj = prej[ansi][ansj][ansk], tk = prek[ansi][ansj][ansk]; if (f[ti][tj][tk] < f[ansi][ansj][ansk]) Ans[w--] = A[ansi]; ansi = ti, ansj = tj, ansk = tk; } printf( %s , Ans + 1); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:23:16 04/12/2016
// Design Name:
// Module Name: memoria_registros
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module memoria_registros_VGA
(
input clk, reset,
input wire formato_hora,
input cs_seg_hora,cs_min_hora,cs_hora_hora,
input cs_dia_fecha,cs_mes_fecha,cs_jahr_fecha,
input cs_seg_timer,cs_min_timer,cs_hora_timer,
input hold_seg_hora,hold_min_hora,hold_hora_hora,
input hold_dia_fecha,hold_mes_fecha,hold_jahr_fecha,
input hold_seg_timer,hold_min_timer,hold_hora_timer,
input hold_banderas_config,
input [7:0] data_PicoBlaze,
input [7:0] count_seg_hora,count_min_hora,count_hora_hora,
input [7:0] count_dia_fecha,count_mes_fecha,count_jahr_fecha,
input [7:0] count_seg_timer,count_min_timer,count_hora_timer,
output wire[7:0] out_seg_hora,out_min_hora,out_hora_hora,
output wire[7:0] out_dia_fecha,out_mes_fecha,out_jahr_fecha,
output wire[7:0] out_seg_timer,out_min_timer,out_hora_timer,
output[1:0] out_banderas_config,
output reg AM_PM
);
//wire flag1,flag2,flag3;
reg flag_done_timer;
//assign flag_done_timer = (flag1 && flag2 && flag3)? 1'b1:1'b0;
wire cs_banderas_config;
assign cs_banderas_config = 1'b0;
wire [7:0]data_HH;//Dato de hora del registro
reg [3:0]digit0_HH, digit1_HH;
////////instancia reg seg_hora
Registro_Universal #(.N(8))
instancia_seg_hora (
.hold(hold_seg_hora),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_seg_hora),
.clk(clk),
.reset(reset),
.chip_select(cs_seg_hora),
.out_dato(out_seg_hora)
);
////////instancia reg min_hora
Registro_Universal #(.N(8))
instancia_min_hora (
.hold(hold_min_hora),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_min_hora),
.clk(clk),
.reset(reset),
.chip_select(cs_min_hora),
.out_dato(out_min_hora)
);
////////instancia reg hora_hora
Registro_Universal #(.N(8))
instancia_hora_hora (
.hold(hold_hora_hora),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_hora_hora),
.clk(clk),
.reset(reset),
.chip_select(cs_hora_hora),
.out_dato(data_HH)
);
////////instancia reg dia_fecha
Registro_Universal #(.N(8))
instancia_dia_fecha (
.hold(hold_dia_fecha),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_dia_fecha),
.clk(clk),
.reset(reset),
.chip_select(cs_dia_fecha),
.out_dato(out_dia_fecha)
);
////////instancia reg mes_fecha
Registro_Universal #(.N(8))
instancia_mes_fecha (
.hold(hold_mes_fecha),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_mes_fecha),
.clk(clk),
.reset(reset),
.chip_select(cs_mes_fecha),
.out_dato(out_mes_fecha)
);
////////instancia reg jahr_fecha
Registro_Universal #(.N(8))
instancia_jahr_fecha (
.hold(hold_jahr_fecha),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_jahr_fecha),
.clk(clk),
.reset(reset),
.chip_select(cs_jahr_fecha),
.out_dato(out_jahr_fecha)
);
////////instancia reg seg_timer
Registro_Universal #(.N(8))
instancia_seg_timer (
.hold(hold_seg_timer),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_seg_timer),
.clk(clk),
.reset(reset),
.chip_select(cs_seg_timer),
.out_dato(out_seg_timer)
);
////////instancia reg min_timer
Registro_Universal #(.N(8))
instancia_min_timer (
.hold(hold_min_timer),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_min_timer),
.clk(clk),
.reset(reset),
.chip_select(cs_min_timer),
.out_dato(out_min_timer)
);
////////instancia reg hora_timer
Registro_Universal #(.N(8))
instancia_hora_timer(
.hold(hold_hora_timer),
.in_rtc_dato(data_PicoBlaze),
.in_count_dato(count_hora_timer),
.clk(clk),
.reset(reset),
.chip_select(cs_hora_timer),
.out_dato(out_hora_timer)
);
////////instancia reg banderas_config
Registro_Universal #(.N(2))
instancia_bandera_config(
.hold(hold_banderas_config),
.in_rtc_dato(data_PicoBlaze[1:0]),
.in_count_dato(2'b0),
.clk(clk),
.reset(reset),
.chip_select(cs_banderas_config),
.out_dato(out_banderas_config)
);
//=============================================
// BLOQUE PARA TRADUCIR FORMATO DE LA HORA
//=============================================
always@*
begin
if(formato_hora)//12 hrs (Traduce a formato 12 hrs)
begin
case(data_HH)
8'd0: begin digit1_HH = 4'b0001; digit0_HH = 4'b0010; AM_PM = 0; end//00 BCD en 8 bits
8'd1: begin digit1_HH = 4'b0000; digit0_HH = 4'b0001; AM_PM = 0; end//01 BCD en 8 bits
8'd2: begin digit1_HH = 4'b0000; digit0_HH = 4'b0010; AM_PM = 0; end//02 BCD en 8 bits
8'd3: begin digit1_HH = 4'b0000; digit0_HH = 4'b0011; AM_PM = 0; end//03 BCD en 8 bits
8'd4: begin digit1_HH = 4'b0000; digit0_HH = 4'b0100; AM_PM = 0; end//04 BCD en 8 bits
8'd5: begin digit1_HH = 4'b0000; digit0_HH = 4'b0101; AM_PM = 0; end//05 BCD en 8 bits
8'd6: begin digit1_HH = 4'b0000; digit0_HH = 4'b0110; AM_PM = 0; end//06 BCD en 8 bits
8'd7: begin digit1_HH = 4'b0000; digit0_HH = 4'b0111; AM_PM = 0; end//07 BCD en 8 bits
8'd8: begin digit1_HH = 4'b0000; digit0_HH = 4'b1000; AM_PM = 0; end//08 BCD en 8 bits
8'd9: begin digit1_HH = 4'b0000; digit0_HH = 4'b1001; AM_PM = 0; end//09 BCD en 8 bits
8'd16: begin digit1_HH = 4'b0001; digit0_HH = 4'b0000; AM_PM = 0; end//10 BCD en 8 bits
8'd17: begin digit1_HH = 4'b0001; digit0_HH = 4'b0001; AM_PM = 0; end//11 BCD en 8 bits
8'd18: begin digit1_HH = 4'b0001; digit0_HH = 4'b0010; AM_PM = 1; end//12 BCD en 8 bits
8'd19: begin digit1_HH = 4'b0000; digit0_HH = 4'b0001; AM_PM = 1; end//13 BCD en 8 bits
8'd20: begin digit1_HH = 4'b0000; digit0_HH = 4'b0010; AM_PM = 1; end//14 BCD en 8 bits
8'd21: begin digit1_HH = 4'b0000; digit0_HH = 4'b0011; AM_PM = 1; end//15 BCD en 8 bits
8'd22: begin digit1_HH = 4'b0000; digit0_HH = 4'b0100; AM_PM = 1; end//16 BCD en 8 bits
8'd23: begin digit1_HH = 4'b0000; digit0_HH = 4'b0101; AM_PM = 1; end//17 BCD en 8 bits
8'd24: begin digit1_HH = 4'b0000; digit0_HH = 4'b0110; AM_PM = 1; end//18 BCD en 8 bits
8'd25: begin digit1_HH = 4'b0000; digit0_HH = 4'b0111; AM_PM = 1; end//19 BCD en 8 bits
8'd32: begin digit1_HH = 4'b0000; digit0_HH = 4'b1000; AM_PM = 1; end//20 BCD en 8 bits
8'd33: begin digit1_HH = 4'b0000; digit0_HH = 4'b1001; AM_PM = 1; end//21 BCD en 8 bits
8'd34: begin digit1_HH = 4'b0001; digit0_HH = 4'b0000; AM_PM = 1; end//22 BCD en 8 bits
8'd35: begin digit1_HH = 4'b0001; digit0_HH = 4'b0001; AM_PM = 1; end//23 BCD en 8 bits
default: begin digit1_HH = 0; digit0_HH = 0; AM_PM = 0; end
endcase
end
else //24 hrs (Transfiere el dato simplemente)
begin
digit1_HH = data_HH[7:4];
digit0_HH = data_HH[3:0];
AM_PM = 0;
end
end
assign out_hora_hora = {digit1_HH,digit0_HH};
/*
//Para generar flag_done_timer
always@(posedge clk)
begin
if(reset) flag_done_timer <= 1'b0;
else if((rtc_seg_timer == count_seg_timer)&&(rtc_min_timer == count_min_timer)&&((count_hora_timer!=0)||(count_min_timer!=0)||(count_seg_timer!=0))&&(estado_alarma==0)) flag_done_timer <= 1'b1;
else flag_done_timer <= 1'b0;
end
/////// FSM para alarma timer //////////
localparam [1:0]
espera_conf = 2'b00,
conf = 2'b01,
timer_run = 2'b10,
alarma_on = 2'b11;
reg [1:0] state_reg , state_next;
//// secuancial
always@(posedge clk , posedge reset)
begin
if (reset) state_reg = espera_conf;
else state_reg = state_next;
end
/// combinacional
always@*
begin
state_next = state_reg ;
case (state_reg)
espera_conf: begin
flag_mostrar_count = 1'b1;
estado_alarma = 1'b0;
if(sw2) state_next = conf;
else state_next = espera_conf;
end
conf: begin
flag_mostrar_count = 1'b1;
estado_alarma = 1'b0;
if(~sw2) state_next = timer_run;
else state_next = conf;
end
timer_run: begin
flag_mostrar_count = 1'b0;
estado_alarma = 1'b0;
if (flag_done_timer) state_next = alarma_on;
else state_next = timer_run;
end
alarma_on: begin
flag_mostrar_count = 1'b1;
estado_alarma = 1'b1;
if (desactivar_alarma) state_next = espera_conf;
else state_next = alarma_on;
end
endcase
end
/////////////////////////////////////////
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFXBP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int BITS = 60; struct tree_node { int child[2] = {-1, -1}; bool full = false; }; struct tree { vector<tree_node> nodes = {tree_node()}; int get_or_create_node(int &node) { int answer = node; if (node < 0) { answer = node = nodes.size(); nodes.emplace_back(); } return answer; } void recursive_add(int node, int bit, long long prefix, long long start, long long end) { long long after = prefix + (1LL << bit); if (start <= prefix && after <= end) { nodes[node].full = true; return; } if (bit <= 0) return; long long mid = (prefix + after) / 2; if (start < mid) recursive_add(get_or_create_node(nodes[node].child[0]), bit - 1, prefix, start, end); if (end > mid) recursive_add(get_or_create_node(nodes[node].child[1]), bit - 1, mid, start, end); } void add_range(long long L, long long R) { recursive_add(0, BITS, 0, L, R); } }; tree a_tree, b_tree; vector<pair<int, int>> options[BITS + 1]; long long dfs_sum(int bit, long long prefix) { for (pair<int, int> &p : options[bit]) if (a_tree.nodes[p.first].full || b_tree.nodes[p.second].full) { long long count = 1LL << bit; long long prefix_sum = (prefix % MOD) * (count % MOD); long long bit_sum = (count / 2 % MOD) * ((count - 1) % MOD); return (prefix_sum + bit_sum) % MOD; } if (bit <= 0) return 0; long long sum = 0; for (int next = 0; next < 2; next++) { options[bit - 1].clear(); for (pair<int, int> &p : options[bit]) for (int left = 0; left < 2; left++) { int right = left ^ next; int a_child = a_tree.nodes[p.first].child[left]; int b_child = b_tree.nodes[p.second].child[right]; if (a_child >= 0 && b_child >= 0) options[bit - 1].emplace_back(a_child, b_child); } if (!options[bit - 1].empty()) { long long add = (long long)next << (bit - 1); sum = (sum + dfs_sum(bit - 1, prefix + add)) % MOD; } } return sum; } int main() { int A, B; cin >> A; for (int i = 0; i < A; i++) { long long L, R; cin >> L >> R; R++; a_tree.add_range(L, R); } cin >> B; for (int i = 0; i < B; i++) { long long L, R; cin >> L >> R; R++; b_tree.add_range(L, R); } options[BITS].emplace_back(0, 0); cout << dfs_sum(BITS, 0) << n ; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; clock_t clk = clock(); int i, j; void solve(void); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int t = 1; while (t--) solve(); return 0; } int n, m, a, b; bool cnt; bool vis[1501][1501]; char maze[1501][1501]; set<pair<int, int> > s[1501][1501]; int dfs(int x, int y, int ex, int ey, int cntx, int cnty) { auto it = s[x][y].find({cntx, cnty}); if (vis[x][y] == 1 && it != s[x][y].end()) return 0; else if (vis[x][y] == 1) return -1; vis[x][y] = 1; s[x][y].insert({cntx, cnty}); int val = 0, valx = cntx, valy = cnty; if (maze[x][((y - 1) % m + m) % m] != # && ((y - 1) % m + m) % m != ey) { valx = cntx, valy = cnty; if (y - 1 == -1) --valy; val = dfs(x, ((y - 1) % m + m) % m, x, y, valx, valy); } if (val == -1) return val; if (maze[x][((y + 1) % m + m) % m] != # && ((y + 1) % m + m) % m != ey) { valx = cntx, valy = cnty; if (y + 1 == m) ++valy; val = dfs(x, ((y + 1) % m + m) % m, x, y, valx, valy); } if (val == -1) return val; if (maze[((x - 1) % n + n) % n][y] != # && ((x - 1) % n + n) % n != ex) { valx = cntx, valy = cnty; if (x - 1 == -1) --valx; val = dfs(((x - 1) % n + n) % n, y, x, y, valx, valy); } if (val == -1) return val; if (maze[((x + 1) % n + n) % n][y] != # && ((x + 1) % n + n) % n != ex) { valx = cntx, valy = cnty; if (x + 1 == n) ++valx; val = dfs(((x + 1) % n + n) % n, y, x, y, valx, valy); } if (val == -1) return val; return 0; } void solve() { cin >> n >> m; for (i = 0; i <= n - 1; ++i) for (j = 0; j <= m - 1; ++j) { cin >> maze[i][j]; if (maze[i][j] == S ) a = i, b = j; } int val = dfs(a, b, -1, -1, 0, 0); if (val == -1) cout << Yes ; else cout << No ; cout << n ; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DIFFINBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/22/14 808642 Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DIFFINBUF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter ISTANDARD = "UNUSED",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
output O_B,
input DIFF_IN_N,
input DIFF_IN_P,
input [3:0] OSC,
input [1:0] OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "DIFFINBUF";
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 0;
localparam DIFF_TERM_TRUE = 1;
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
reg trig_attr = 1'b0;
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
wire DIFF_TERM_BIN;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg O_B_out;
reg O_out;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
`ifdef XIL_TIMING
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
`endif
reg O_OSC_in;
reg O_B_OSC_in;
integer OSC_int = 0;
assign O = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
assign O_B = (OSC_EN_in === 2'b11) ? O_B_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_B_out;
`ifdef XIL_TIMING
assign OSC_EN_in[0] = OSC_EN_delay[0];
assign OSC_EN_in[1] = OSC_EN_delay[1];
assign OSC_in = OSC_delay;
`else
assign OSC_EN_in[0] = OSC_EN[0];
assign OSC_EN_in[1] = OSC_EN[1];
assign OSC_in = OSC;
`endif
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_FALSE;
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-106] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-111] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in === 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin
O_OSC_in <= ~O_OSC_in;
O_B_OSC_in <= ~O_B_OSC_in;
end
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin
O_OSC_in <= 1'bx;
O_B_OSC_in <= 1'bx;
end
end
always @(DIFF_IN_P or DIFF_IN_N or DQS_BIAS_BIN) begin
if (DIFF_IN_P == 1'b1 && DIFF_IN_N == 1'b0) begin
O_out <= 1'b1;
O_B_out <= 1'b0;
end
else if (DIFF_IN_P == 1'b0 && DIFF_IN_N == 1'b1) begin
O_out <= 1'b0;
O_B_out <= 1'b1;
end
else if ((DIFF_IN_P === 1'bz || DIFF_IN_P == 1'b0) && (DIFF_IN_N === 1'bz || DIFF_IN_N == 1'b1)) begin
if (DQS_BIAS_BIN == 1'b1) begin
O_out <= 1'b0;
O_B_out <= 1'b1;
end
else begin
O_out <= 1'bx;
O_B_out <= 1'bx;
end
end else if ((DIFF_IN_P === 1'bx) || (DIFF_IN_N === 1'bx)) begin
O_out <= 1'bx;
O_B_out <= 1'bx;
end
// O_out <= DIFF_IN_P;
// O_B_out <= DIFF_IN_N;
end
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(DIFF_IN_N => O) = (0:0:0, 0:0:0);
(DIFF_IN_N => O_B) = (0:0:0, 0:0:0);
(DIFF_IN_P => O) = (0:0:0, 0:0:0);
(DIFF_IN_P => O_B) = (0:0:0, 0:0:0);
(OSC *> O) = (0:0:0, 0:0:0);
(OSC *> O_B) = (0:0:0, 0:0:0);
(OSC_EN *> O) = (0:0:0, 0:0:0);
(OSC_EN *> O_B) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$setuphold (negedge OSC_EN, negedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay);
$setuphold (negedge OSC_EN, posedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI stream to Avalon-ST
*/
module axis2avst #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] axis_tdata,
input wire [KEEP_WIDTH-1:0] axis_tkeep,
input wire axis_tvalid,
output wire axis_tready,
input wire axis_tlast,
input wire axis_tuser,
input wire avst_ready,
output wire avst_valid,
output wire [DATA_WIDTH-1:0] avst_data,
output wire avst_startofpacket,
output wire avst_endofpacket,
output wire [EMPTY_WIDTH-1:0] avst_empty,
output wire avst_error
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
reg frame_reg = 1'b0;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign avst_data[n*BYTE_WIDTH +: BYTE_WIDTH] = axis_tdata[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign avst_data = axis_tdata;
end
endgenerate
reg [EMPTY_WIDTH-1:0] empty;
assign avst_empty = empty;
integer k;
always @* begin
empty = KEEP_WIDTH-1;
for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
if (axis_tkeep[k]) begin
empty = KEEP_WIDTH-1-k;
end
end
end
assign avst_valid = axis_tvalid;
assign avst_startofpacket = axis_tvalid & !frame_reg;
assign avst_endofpacket = axis_tlast;
assign avst_error = axis_tuser;
assign axis_tready = avst_ready;
always @(posedge clk) begin
if (axis_tvalid && axis_tready) begin
frame_reg <= !axis_tlast;
end
if (rst) begin
frame_reg <= 1'b0;
end
end
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
|
/*********************************************************/
// MODULE: j-k flip flop
//
// FILE NAME: jk_rtl.v
// VERSION: 1.0
// DATE: January 1, 1999
// AUTHOR: Bob Zeidman, Zeidman Consulting
//
// CODE TYPE: Register Transfer Level
//
// DESCRIPTION: This module defines a J-K flip flop with an
// asynchronous, active low reset.
//
/*********************************************************/
// DEFINES
`define DEL 1 // Clock-to-output delay. Zero
// time delays can be confusing
// and sometimes cause problems.
// TOP MODULE
module bm_jk_rtl(
clk,
clr_n,
j,
k,
q,
q_n);
// INPUTS
input clk; // Clock
input clr_n; // Active low, asynchronous reset
input j; // J input
input k; // K input
// OUTPUTS
output q; // Output
output q_n; // Inverted output
// INOUTS
// SIGNAL DECLARATIONS
wire clk;
wire clr_n;
wire j;
wire k;
reg q;
wire q_n;
// PARAMETERS
// Define the J-K input combinations as parameters
parameter[1:0] HOLD = 0,
RESET = 1,
SET = 2,
TOGGLE = 3;
// ASSIGN STATEMENTS
assign #`DEL q_n = ~q;
// MAIN CODE
// Look at the falling edge of clock for state transitions
always @(negedge clk or negedge clr_n) begin
if (~clr_n) begin
// This is the reset condition. Most synthesis tools
// require an asynchronous reset to be defined this
// way.
q <= #`DEL 1'b0;
end
else begin
case ({j,k})
RESET: q <= #`DEL 1'b0;
SET: q <= #`DEL 1'b1;
TOGGLE: q <= #`DEL ~q;
endcase
end
end
endmodule // jk_FlipFlop
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_pwrgood_pp_p.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VPWR = 1'b0;
#60 UDP_IN = 1'b1;
#80 VPWR = 1'b1;
#100 UDP_IN = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 UDP_IN = 1'b1;
#180 VPWR = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ls__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
|
#include <bits/stdc++.h> using namespace std; long long digit(long long n) { long long ans = 0; long long i = 0; while (n > 0) { long long tmp = n % 10; if (tmp != 0) { ans = ans + (tmp * pow(10, i)); i++; } n = n / 10; } return ans; } int main() { char arr[8][8]; for (int i = 0; i < 8; i++) cin >> arr[i]; int w = 0, b = 0; for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) { if (arr[i][j] >= A && arr[i][j] < a && arr[i][j] != . ) { char c = arr[i][j]; if (c == Q ) w += 9; if (c == R ) w += 5; if (c == B || c == N ) w += 3; if (c == P ) w += 1; } else if (arr[i][j] >= a && arr[i][j] != . ) { char c = arr[i][j]; if (c == q ) b += 9; if (c == r ) b += 5; if (c == b || c == n ) b += 3; if (c == p ) b += 1; } } if (b > w) cout << Black ; else if (w > b) cout << White ; else cout << Draw ; }
|
`define bsg_mem_2r1w_sync_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
hard_mem_1r1w_d``words``_w``bits``_wrapper \
mem0 \
(.clk_i ( clk_i ) \
,.reset_i ( reset_i ) \
,.w_v_i ( w_v_i ) \
,.w_addr_i( w_addr_i ) \
,.w_data_i( w_data_i ) \
,.r_v_i ( r0_v_i ) \
,.r_addr_i( r0_addr_i ) \
,.r_data_o( r0_data_o ) \
); \
hard_mem_1r1w_d``words``_w``bits``_wrapper \
mem1 \
(.clk_i ( clk_i ) \
,.reset_i ( reset_i ) \
,.w_v_i ( w_v_i ) \
,.w_addr_i( w_addr_i ) \
,.w_data_i( w_data_i ) \
,.r_v_i ( r1_v_i ) \
,.r_addr_i( r1_addr_i ) \
,.r_data_o( r1_data_o ) \
); \
end
module bsg_mem_2r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 0
, parameter substitute_2r1w_p = 0
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_2r1w_sync_macro(32,32) else
`bsg_mem_2r1w_sync_macro(32,64) else
// no hardened version found
begin : z
if (substitute_2r1w_p)
begin: s2r1w
logic [width_p-1:0] r0_data_lo, r1_data_lo;
bsg_mem_2r1w #( .width_p(width_p)
, .els_p(els_p)
, .read_write_same_addr_p(0)
)
mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (w_v_i & w_v_i)
,.w_addr_i (w_addr_i)
,.w_data_i (w_data_i)
,.r0_v_i (r0_v_i & ~r0_v_i)
,.r0_addr_i(r0_addr_i)
,.r0_data_o(r0_data_lo)
,.r1_v_i (r1_v_i & ~r1_v_i)
,.r1_addr_i(r1_addr_i)
,.r1_data_o(r1_data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i) begin
r0_data_o <= r0_data_lo;
r1_data_o <= r1_data_lo;
end
end // block: s1r1w
else
begin: notmacro
bsg_mem_2r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p), .harden_p(harden_p))
synth
(.*);
end // block: notmacro
end // block: z
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_sync)
|
// File generate.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module gen(
sysclk,
reset,
wrb,
din,
rdout
);
parameter [31:0] bus_width=15;
parameter [31:0] TOP_GP2=0;
input sysclk, reset, wrb;
input [bus_width:0] din;
output [bus_width:0] rdout;
wire sysclk;
wire reset;
wire wrb;
wire [bus_width:0] din;
wire [bus_width:0] rdout;
reg [bus_width * 2:0] regSelect;
//---------------------------------------------------
// Reg : GP 2
// Active : 32
// Type : RW
//---------------------------------------------------
genvar bitnum;
generate for (bitnum=0; bitnum <= bus_width; bitnum = bitnum + 1) begin: reg_gp2
wbit1 wbit1_inst(
.clk(sysclk),
.wrb(wrb),
.reset(reset),
.enb(regSelect[TOP_GP2]),
.din(din[bitnum]),
.dout(rdout[bitnum]));
end
endgenerate
always @(posedge sysclk) begin
regSelect[1] <= 1'b 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int64_t t, a, b; cin >> t; while (t--) { cin >> a >> b; cout << max(a, max(b, min(a, b) * 2)) * max(a, max(b, min(a, b) * 2)) << endl; } }
|
#include <bits/stdc++.h> using namespace std; using seg = pair<int, int>; using ll = long long; seg intersect(seg a, seg b) { seg ret = {max(a.first, b.first), min(a.second, b.second)}; if (ret.first > ret.second) return {-1, -1}; return ret; } inline int len(const seg& a) { return a.second - a.first; } const int inf = 1234567890; struct node { int l, r; seg x; node() {} node(int _l, int _r) : l(_l), r(_r), x(0, inf) {} node(int _l, int _r, const seg& _x) : node(_l, _r) { x = _x; } node(node a, node b) : node(a.l, b.r) { x = intersect(a.x, b.x); } void update(const seg& v) { x = v; } }; struct segment_tree { int n; vector<node> arr; segment_tree(const vector<seg>& a) : n(a.size()), arr(4 * n) { mk(a, 0, 0, n - 1); } node mk(const vector<seg>& a, int i, int l, int r) { int m = (l + r) / 2; return arr[i] = l > r ? node(l, r) : l == r ? node(l, r, a[l]) : node(mk(a, 2 * i + 1, l, m), mk(a, 2 * i + 2, m + 1, r)); } node update(int at, seg v, int i = 0) { int hl = arr[i].l, hr = arr[i].r; if (at < hl || hr < at) return arr[i]; if (hl == at && at == hr) { arr[i].update(v); return arr[i]; } return arr[i] = node(update(at, v, 2 * i + 1), update(at, v, 2 * i + 2)); } node query(int l, int r, int i = 0) { int hl = arr[i].l, hr = arr[i].r; if (r < hl || hr < l) return node(hl, hr); if (l <= hl && hr <= r) return arr[i]; return node(query(l, r, 2 * i + 1), query(l, r, 2 * i + 2)); } }; int main() { ios::sync_with_stdio(false), cin.tie(nullptr); int n; cin >> n; vector<seg> a(n); for (int i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; } segment_tree st(a); int mx = 0; for (int i = 0; i < n; ++i) { st.update(i, seg(0, inf)); mx = max(mx, len(st.query(0, n - 1).x)); st.update(i, a[i]); } cout << mx << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; char s[5010]; int main() { scanf( %s , s); int n = (int)strlen(s); int res = 0; for (int i = 0; i < n; i++) { int cnt1 = 0, cnt2 = 0; for (int j = i; j < n; j++) { if (s[j] == ( ) cnt1++; if (s[j] == ) ) cnt1--; if (s[j] == ? ) cnt2++; if (cnt2 && cnt2 > cnt1) cnt2--, cnt1++; if (cnt1 < 0) break; if (cnt2 == cnt1) res++; } } printf( %d , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, shet = 0; long long int ans = 0; cin >> n; ans = n; int* mas = new int[n]; for (int i = 0; i < n; i++) { cin >> mas[i]; } for (int i = 1; i < n; i++) { if (mas[i] == mas[i - 1]) { shet++; ans += shet; } else { shet = 0; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1.0l); const long long MOD = 1e9 + 7; bool debug = 1; const int N = 3e3 + 10; int seg[2 * N]; int n, m; void build() { for (int i = n - 1; i > 0; i--) seg[i] = seg[i << 1] + seg[i << 1 | 1]; } int qry(int l, int r) { int ans = 0; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) ans += seg[l++]; if (r & 1) ans += seg[--r]; } return ans; } void up(int pos, int x) { for (seg[pos += n] = x; pos > 1; pos >>= 1) { seg[pos >> 1] = seg[pos] + seg[pos ^ 1]; } } char mat[N][N]; int dpesq[N][N], dpdir[N][N], dpdia[N][N]; bool ok(int i, int j) { return i >= 0 and i < n and j >= 0 and j < m; } vector<int> ev[N]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %c , mat[i] + j); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int ant = 0; if (j) ant = dpesq[i][j - 1]; if (mat[i][j] == z ) dpesq[i][j] = ant + 1; } } for (int i = 0; i < n; i++) { for (int j = m - 1; j >= 0; j--) { int ant = 0; if (j < m - 1) ant = dpdir[i][j + 1]; if (mat[i][j] == z ) dpdir[i][j] = ant + 1; } } for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < m; j++) { int ant = 0; if (ok(i + 1, j - 1)) ant = dpdia[i + 1][j - 1]; if (mat[i][j] == z ) dpdia[i][j] = ant + 1; } } long long ans = 0; for (int inic = 0; inic < n; inic++) { int i = inic, j = 0; memset(seg, 0, sizeof(seg)); for (int jj = 0; jj < m; jj++) ev[jj].clear(); while (ok(i, j)) { for (auto it : ev[j]) { up(it, 0); } if (mat[i][j] == z ) { up(j, 1); ev[j + dpdir[i][j]].push_back(j); int mind = min(dpesq[i][j], dpdia[i][j]); ans += qry(j - mind + 1, j + 1); } i--, j++; } } for (int inicj = 1; inicj <= m - 1; inicj++) { int i = n - 1, j = inicj; memset(seg, 0, sizeof(seg)); for (int jj = 0; jj < m; jj++) ev[jj].clear(); while (ok(i, j)) { for (auto it : ev[j]) { up(it, 0); } if (mat[i][j] == z ) { up(j, 1); ev[j + dpdir[i][j]].push_back(j); int mind = min(dpesq[i][j], dpdia[i][j]); ans += qry(j - mind + 1, j + 1); } i--, j++; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const int mod = 1e9 + 7; const int N = 1010; const int inf = 0x3f3f3f3f; using namespace std; long long sum[N]; int n, a[N], b[N], v, e; int p[N]; int find(int x) { if (p[x] != x) p[x] = find(p[x]); return p[x]; } vector<int> vt[N]; bool vis[N]; struct Data { int a, b, c; }; Data que[N * N]; int head; bool dfs(int from, int to, int cap) { if (from == to) return 1; vis[from] = 1; for (int i = 0; i < vt[from].size(); i++) { int t = vt[from][i]; if (vis[t]) continue; if (a[t] < cap) { int tmp = cap - a[t]; a[from] -= cap - a[t]; a[t] += tmp; que[head++] = (Data{from, t, tmp}); if (dfs(t, to, cap) == 0) { a[from] += tmp; a[t] -= tmp; head--; continue; } a[from] -= cap - tmp; a[t] += cap - tmp; que[head++] = (Data{from, t, cap - tmp}); } else { if (dfs(t, to, cap) == 0) continue; a[from] -= cap; a[t] += cap; que[head++] = (Data{from, t, cap}); } return 1; } return 0; } int main() { queue<int> quea[N], queb[N]; scanf( %d%d%d , &n, &v, &e); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); p[i] = i; } for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 1; i <= e; i++) { int x, y; scanf( %d%d , &x, &y); vt[x].push_back(y); vt[y].push_back(x); p[find(x)] = find(y); } for (int i = 1; i <= n; i++) { int x = find(i); sum[x] += a[i] - b[i]; if (a[i] > b[i]) quea[x].push(i); if (b[i] > a[i]) queb[x].push(i); } for (int i = 1; i <= n; i++) if (sum[i]) return puts( NO ), 0; for (int i = 1; i <= n; i++) { if (find(i) != i) continue; while (quea[i].size()) { memset(vis, 0, sizeof(vis)); int x = quea[i].front(); int y = queb[i].front(); if (a[x] - b[x] > b[y] - a[y]) { dfs(x, y, b[y] - a[y]); queb[i].pop(); } else if (a[x] - b[x] < b[y] - a[y]) { dfs(x, y, a[x] - b[x]); quea[i].pop(); } else { dfs(x, y, a[x] - b[x]); quea[i].pop(); queb[i].pop(); } } } cout << head << endl; for (int i = 0; i < head; i++) { Data da = que[i]; cout << da.a << << da.b << << da.c << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, i, j, k; cin >> n >> t; string a; cin >> a; for (i = 1; i <= t; ++i) { for (j = 0; j < n - 1; ++j) { if (a[j] == B && a[j + 1] == G ) { a[j + 1] = B ; a[j] = G ; ++j; } } } cout << a << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, pos, lpos; int q; cin >> n >> q; for (int i = 0; i < q; i++) { cin >> pos; while (pos % 2 == 0) { lpos = pos / 2 + 1; pos += n - lpos + 1; } cout << pos / 2 + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 201; int a[maxn], N, L, K; double f[maxn][maxn][maxn * 2], p[maxn]; int main() { scanf( %d%d%d , &N, &L, &K); for (int i = 0; i < N; ++i) { scanf( %lf , &p[i]); p[i] /= 100; } for (int i = 0; i < N; ++i) scanf( %d , &a[i]); f[0][0][N + min(N, K)] = 1; for (int i = 0; i < N; ++i) for (int j = 0; j <= N; ++j) for (int k = -N; k <= N; ++k) if (f[i][j][N + k] > 0) { f[i + 1][j + 1][N + min(k + a[i], N)] += p[i] * f[i][j][N + k]; f[i + 1][j][N + k] += (1 - p[i]) * f[i][j][N + k]; } double ans = 0; for (int j = L; j <= N; ++j) for (int k = N; k <= N + N; ++k) ans += f[N][j][k]; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 200005; vector<int> g[maxn]; int dis[maxn]; int pa[maxn]; set<pair<int, int>> st; void dfs(int now, int pre = 0) { if (dis[now] > 2) { st.insert({dis[now], now}); } for (auto &i : g[now]) { if (i ^ pre) { pa[i] = now; dis[i] = dis[now] + 1; dfs(i, now); } } } void go() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs(1); int ans = 0; while (st.size()) { auto x = *(--st.end()); int v = pa[x.second]; st.erase({dis[v], v}); for (auto &i : g[v]) { st.erase({dis[i], i}); } ans++; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int c = 0; int t; if (!c) { t = 1; } else { cin >> t; } while (t--) { go(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_0_V
`define SKY130_FD_SC_LP__O211AI_0_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_0 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_0_V
|
module reg32(Rout, clr, clk, write_enable, write_value);
input clr,clk, write_enable;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value;
end
end
endmodule
module reg32_R0(Rout, clr, clk, BA_out, write_enable, write_value);
input clr,clk, write_enable, BA_out;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value & (!BA_out);
end
end
endmodule
module reg32_MDR(Memory_output, Bus_output, Mem_RW, clr, clk, MDR_write_enable, Memory_write_enable, Memory_read_enable, Bus_input, Memory_input);
input clr,clk, Memory_write_enable, Memory_read_enable, MDR_write_enable;
input [31:0] Bus_input, Memory_input;
output [31:0]Memory_output, Bus_output;
output Mem_RW;
reg Mem_RW;
reg[31:0] Rout;
wire[31:0] register;
MDMux_in input_select(Bus_input, Memory_input, Memory_read_enable, register);
MDMux_out output_select(Rout, Memory_write_enable, Bus_output, Memory_output);
always @ (posedge clk)begin
Mem_RW = MDR_write_enable & (!Memory_read_enable);
if(clr) begin
Rout = 32'h00000000;
end
if(MDR_write_enable) begin
Rout = register;
end
end
endmodule
module reg32_MAR(Rout, clr, clk, write_enable, write_value);
input clr,clk, write_enable;
input [31:0] write_value;
output [8:0] Rout;
reg[31:0] value;
assign Rout = value[8:0];
always @ (posedge clk)begin
if(clr) begin
value = 32'h00000000;
end
if(write_enable) begin
value = write_value;
end
end
endmodule
module MDMux_in(Bus_data, Mdata_in, Mem_read_enable, MDMux_out); //BusMuxOut
input Mem_read_enable;
input[31:0] Bus_data, Mdata_in;
output[31:0] MDMux_out;
//assign MDMux_out = (Mem_read_enable & Mdata_in) | (!Mem_read_enable & Bus_data);
assign MDMux_out = (Mem_read_enable) ? Mdata_in : Bus_data;
endmodule
module MDMux_out(MDR_data, Mem_write_enable, BusData_out, Mdata_out);
input Mem_write_enable;
input[31:0] MDR_data;
output[31:0] BusData_out, Mdata_out;
assign Mdata_out = (Mem_write_enable) ? MDR_data : 0; //MDR_data & Mem_write_enable;
assign BusData_out = (!Mem_write_enable) ? MDR_data : 0; //MDR_data & (!Mem_write_enable);
endmodule
module reg64(Rout_hi, Rout_low, clr, clk, write_enable, input_value);
input clr,clk, write_enable;
input [63:0] input_value;
output [31:0]Rout_hi, Rout_low;
reg[31:0] Rout_hi, Rout_low;
always @ (posedge clk)begin
if(write_enable == 1) begin
Rout_hi = input_value[63:32];
Rout_low = input_value[31:0];
end
else if(clr) begin
Rout_hi = 0;
Rout_low = 0;
end
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_NIOS_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2, s; cin >> s1 >> s2 >> s; string s3 = s1 + s2; sort(s3.begin(), s3.end()); sort(s.begin(), s.end()); if (s == s3) cout << YES n ; else cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (1 << 18) + 100; const int maxnode = maxn << 2; int n, ai[maxn + 5]; int ls[maxnode + 5], rs[maxnode + 5]; int re[maxnode + 5], sp[maxnode + 5]; long long sum[maxnode + 5]; void Build(int x, int l, int r) { re[x] = sp[x] = 0; ls[x] = x << 1, rs[x] = x << 1 | 1; if (l == r) { sum[x] = ai[l]; return; } int &lson = ls[x], &rson = rs[x], mid = (l + r) >> 1; Build(lson, l, mid); Build(rson, mid + 1, r); sum[x] = sum[lson] + sum[rson]; } void Replace(int d, int x, int l, int r, int p, int v) { if (l == r) { sum[x] = v; return; } int &lson = ls[x], &rson = rs[x], mid = (l + r) >> 1; if (re[x] >> d & 1) { re[x] ^= (1 << d), sp[x] ^= (1 << d), re[lson] ^= (1 << (d + 1)), re[rson] ^= (1 << (d + 1)); } if (sp[x] >> d & 1) { sp[x] ^= (1 << d), swap(lson, rson); } re[lson] ^= re[x], re[rson] ^= re[x], re[x] = 0; sp[lson] ^= sp[x], sp[rson] ^= sp[x], sp[x] = 0; if (p <= mid) Replace(d + 1, lson, l, mid, p, v); else Replace(d + 1, rson, mid + 1, r, p, v); sum[x] = sum[lson] + sum[rson]; } long long Sum(int d, int x, int l, int r, int ll, int rr) { if (ll <= l && r <= rr) return sum[x]; int &lson = ls[x], &rson = rs[x], mid = (l + r) >> 1; long long res = 0; if (re[x] >> d & 1) { re[x] ^= (1 << d), sp[x] ^= (1 << d), re[lson] ^= (1 << (d + 1)), re[rson] ^= (1 << (d + 1)); } if (sp[x] >> d & 1) { sp[x] ^= (1 << d), swap(lson, rson); } re[lson] ^= re[x], re[rson] ^= re[x], re[x] = 0; sp[lson] ^= sp[x], sp[rson] ^= sp[x], sp[x] = 0; if (ll <= mid) res += Sum(d + 1, lson, l, mid, ll, rr); if (mid < rr) res += Sum(d + 1, rson, mid + 1, r, ll, rr); return res; } int main() { int _; scanf( %d%d , &n, &_); int pn = n; n = (1 << n); for (int i = 1; i <= n; ++i) scanf( %d , ai + i); Build(1, 1, n); while (_--) { int o, x, k, l, r; scanf( %d , &o); if (o == 1) { scanf( %d%d , &x, &k); Replace(0, 1, 1, n, x, k); } else if (o == 2) { scanf( %d , &k); k = pn - k; re[1] ^= (1 << k); } else if (o == 3) { scanf( %d , &k); k = pn - 1 - k; sp[1] ^= (1 << k); } else { scanf( %d%d , &l, &r); long long ans = Sum(0, 1, 1, n, l, r); printf( %lld n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, a, b, ans; cin >> n >> a >> b; if (b > 0) { ans = (a + b) % n; if (ans == 0) ans = n; } else if (b < 0) { if (a > abs(b)) { ans = a - abs(b); } else { ans = n - abs(a + b) % n; } } else ans = a; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int indeg[510], vis[510], indeg1[510], vis1[510]; int n, m; vector<vector<int> > adj(510); int check(int x) { int i, c, p; queue<int> q; for (i = 0; i < n; i++) { vis1[i] = vis[i]; indeg1[i] = indeg[i]; } indeg1[x]--; q.push(x); c = 1; while (!q.empty()) { p = q.front(); q.pop(); for (i = 0; i < adj[p].size(); i++) { indeg1[adj[p][i]]--; if (indeg1[adj[p][i]] == 0 && vis1[adj[p][i]] == 0) { vis1[adj[p][i]] = 1; c++; q.push(adj[p][i]); } } } return c; } int toposort() { int i, c = 0, j, p; queue<int> q; vector<int> v; for (i = 0; i < n; i++) { indeg[i] = 0; vis[i] = 0; } for (i = 0; i < n; i++) { for (j = 0; j < adj[i].size(); j++) { indeg[adj[i][j]]++; } } for (i = 0; i < n; i++) { if (indeg[i] == 0) { q.push(i); vis[i] = 1; c++; } } while (!q.empty()) { p = q.front(); q.pop(); for (i = 0; i < adj[p].size(); i++) { indeg[adj[p][i]]--; if (indeg[adj[p][i]] == 0 && vis[adj[p][i]] == 0) { vis[adj[p][i]] = 1; c++; q.push(adj[p][i]); } } } if (c == n) { cout << YES << endl; exit(0); } else { for (i = 0; i < n; i++) { if (indeg[i] == 1) { v.push_back(i); } } if (v.size() == 0) { cout << NO << endl; exit(0); } else { for (i = 0; i < v.size(); i++) if (check(v[i]) + c == n) { cout << YES << endl; exit(0); } cout << NO << endl; exit(0); } } } int main() { std::ios::sync_with_stdio(false); int u, v, i; cin >> n >> m; for (i = 0; i < m; i++) { cin >> u >> v; u--; v--; adj[u].push_back(v); } toposort(); }
|
#include <bits/stdc++.h> using namespace std; string op, s1, s2; map<string, int> mp; int solve(string s) { int ast, amp; ast = count(s.begin(), s.end(), * ); amp = count(s.begin(), s.end(), & ); return ast - amp; } string remove(string s) { s.erase(remove(s.begin(), s.end(), * ), s.end()); s.erase(remove(s.begin(), s.end(), & ), s.end()); return s; } int main() { int N; cin >> N; mp[ void ] = 0; while (N--) { cin >> op; if (op == typedef ) { cin >> s1 >> s2; int d = solve(s1); s1 = remove(s1); if (mp.find(s1) != mp.end() && mp[s1] >= 0) mp[s2] = mp[s1] + d; else mp[s2] = -1; } else { cin >> s1; int d = solve(s1); s1 = remove(s1); if (mp.find(s1) != mp.end() && mp[s1] >= 0) { d += mp[s1]; if (d >= 0) { cout << void ; for (int i = 0; i < d; i++) cout << * ; cout << endl; } else cout << errtype << endl; } else cout << errtype << endl; } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/);
// Note these are NOT pure.
import "DPI-C" function int dpii_clear ();
import "DPI-C" function int dpii_count (input int ctr);
import "DPI-C" function bit dpii_inc0 (input int ctr);
import "DPI-C" function bit dpii_inc1 (input int ctr);
import "DPI-C" function bit dpii_incx (input int ctr, input bit value);
integer i;
integer j;
integer k;
bit b;
integer errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
task check(integer line, int got, int ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
// Test loop
initial begin
// bug963
// verilator lint_off IGNOREDRETURN
dpii_clear();
// verilator lint_on IGNOREDRETURN
j = 0;
for (i=0; i<64; i++) begin
if (i[0])
j = 0;
else
j = {31'b0, dpii_inc1(0)};
k = k + j;
end
$write("%x\n",k);
check (`__LINE__, dpii_count(0), 32);
if (|errors) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//--------------------------------------------------------------------------------
// controller.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Controls the capturing & readback operation.
//
// If no other operation has been activated, the controller samples data
// into the memory. When the run signal is received, it continues to do so
// for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
// This allows to capture data from before the trigger match which is a nice
// feature.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module controller (
input wire clock,
input wire reset,
input wire run,
input wire wrSize,
input wire [31:0] config_data,
input wire validIn,
input wire [31:0] dataIn,
input wire busy,
input wire arm,
// outputs...
output reg send,
output reg [31:0] memoryWrData,
output reg memoryRead,
output reg memoryWrite,
output reg memoryLastWrite
);
reg [15:0] fwd; // Config registers...
reg [15:0] bwd;
reg next_send;
reg next_memoryRead;
reg next_memoryWrite;
reg next_memoryLastWrite;
reg [17:0] counter, next_counter;
wire [17:0] counter_inc = counter+1'b1;
always @(posedge clock)
memoryWrData <= dataIn;
//
// Control FSM...
//
localparam [2:0]
IDLE = 3'h0,
SAMPLE = 3'h1,
DELAY = 3'h2,
READ = 3'h3,
READWAIT = 3'h4;
reg [2:0] state, next_state;
initial state = IDLE;
always @(posedge clock, posedge reset)
if (reset) begin
state <= IDLE;
memoryWrite <= 1'b0;
memoryLastWrite <= 1'b0;
memoryRead <= 1'b0;
end else begin
state <= next_state;
memoryWrite <= next_memoryWrite;
memoryLastWrite <= next_memoryLastWrite;
memoryRead <= next_memoryRead;
end
always @(posedge clock)
begin
counter <= next_counter;
send <= next_send;
end
// FSM to control the controller action
always @*
begin
next_state = state;
next_counter = counter;
next_memoryWrite = 1'b0;
next_memoryLastWrite = 1'b0;
next_memoryRead = 1'b0;
next_send = 1'b0;
case(state)
IDLE :
begin
next_counter = 0;
next_memoryWrite = 1;
if (run) next_state = DELAY;
else if (arm) next_state = SAMPLE;
end
// default mode: write data samples to memory
SAMPLE :
begin
next_counter = 0;
next_memoryWrite = validIn;
if (run) next_state = DELAY;
end
// keep sampling for 4 * fwd + 4 samples after run condition
DELAY :
begin
if (validIn)
begin
next_memoryWrite = 1'b1;
next_counter = counter_inc;
if (counter == {fwd,2'b11}) // IED - Evaluate only on validIn to make behavior
begin // match between sampling on all-clocks verses occasionally.
next_memoryLastWrite = 1'b1; // Added LastWrite flag to simplify write->read memory handling.
next_counter = 0;
next_state = READ;
end
end
end
// read back 4 * bwd + 4 samples after DELAY
// go into wait state after each sample to give transmitter time
READ :
begin
next_memoryRead = 1'b1;
next_send = 1'b1;
if (counter == {bwd,2'b11})
begin
next_counter = 0;
next_state = IDLE;
end
else
begin
next_counter = counter_inc;
next_state = READWAIT;
end
end
// wait for the transmitter to become ready again
READWAIT :
begin
if (!busy && !send) next_state = READ;
end
endcase
end
//
// Set speed and size registers if indicated...
//
always @(posedge clock)
if (wrSize) {fwd, bwd} <= config_data[31:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFBBN_PP_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_PP_SYMBOL_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// Depth 1 FIFO data size 0!
module FIFO10(CLK,
RST,
ENQ,
FULL_N,
DEQ,
EMPTY_N,
CLR
);
parameter guarded = 1;
input CLK;
input RST;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
empty_reg = 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK /* or `BSV_RESET_EDGE RST */)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO10: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO10: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Dual ported, Harvard architecture, cached ram
module ram_harv_cache
#(parameter AWIDTH=15,parameter RAM_SIZE=16384,parameter ICWIDTH=6,parameter DCWIDTH=6)
(input wb_clk_i, input wb_rst_i,
input [AWIDTH-1:0] ram_loader_adr_i,
input [31:0] ram_loader_dat_i,
input ram_loader_stb_i,
input [3:0] ram_loader_sel_i,
input ram_loader_we_i,
output ram_loader_ack_o,
input ram_loader_done_i,
input [AWIDTH-1:0] iwb_adr_i,
input iwb_stb_i,
output [31:0] iwb_dat_o,
output iwb_ack_o,
input [AWIDTH-1:0] dwb_adr_i,
input [31:0] dwb_dat_i,
output [31:0] dwb_dat_o,
input dwb_we_i,
output dwb_ack_o,
input dwb_stb_i,
input [3:0] dwb_sel_i,
input flush_icache );
wire [31:0] iram_dat, dram_dat_i, dram_dat_o;
wire [AWIDTH-1:0] iram_adr, dram_adr;
wire iram_en, dram_en, dram_we;
wire [3:0] dram_sel;
dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram
(.clk(wb_clk_i),
.adr1_i(ram_loader_done_i ? iram_adr : ram_loader_adr_i),
.dat1_i(ram_loader_dat_i),
.dat1_o(iram_dat),
.we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
.en1_i(ram_loader_done_i ? iram_en : ram_loader_stb_i),
.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
.adr2_i(dram_adr),.dat2_i(dram_dat_i),.dat2_o(dram_dat_o),
.we2_i(dram_we),.en2_i(dram_en),.sel2_i(dram_sel) );
// Data bus side
dcache #(.AWIDTH(AWIDTH),.CWIDTH(DCWIDTH))
dcache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
.dwb_adr_i(dwb_adr_i),.dwb_stb_i(dwb_stb_i),
.dwb_we_i(dwb_we_i),.dwb_sel_i(dwb_sel_i),
.dwb_dat_i(dwb_dat_i),.dwb_dat_o(dwb_dat_o),
.dwb_ack_o(dwb_ack_o),
.dram_dat_i(dram_dat_o),.dram_dat_o(dram_dat_i),.dram_adr_o(dram_adr),
.dram_we_o(dram_we),.dram_en_o(dram_en), .dram_sel_o(dram_sel) );
// Instruction bus side
icache #(.AWIDTH(AWIDTH),.CWIDTH(ICWIDTH))
icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
.iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i),
.iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o),
.iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en),
.flush(flush_icache));
// RAM loader
assign ram_loader_ack_o = ram_loader_stb_i;
// Performance Monitoring
wire i_wait = iwb_stb_i & ~iwb_ack_o;
wire d_wait = dwb_stb_i & ~dwb_ack_o;
endmodule // ram_harv_cache
|
#include <bits/stdc++.h> using namespace std; const int N = 305; int c[N], a[N], d[N]; bool cmp(int first, int second) { if (a[first] != a[second]) return a[first] < a[second]; return first > second; } inline int lowbit(int first) { return first & -first; } int query(int first) { int res = 0; for (int i = first; i; i -= lowbit(i)) res += c[i]; return res; } void modify(int first, int v) { for (int i = first; i < N; i += lowbit(i)) c[i] += v; } int main() { int T; scanf( %d , &T); while (T--) { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) scanf( %d , &a[i]), d[i] = i, c[i] = 0; sort(d + 1, d + m + 1, cmp); long long res = 0; for (int i = 1; i <= m; ++i) { res += query(d[i]); modify(d[i], 1); } printf( %lld n , res); } return 0; }
|
`timescale 1ns / 1ps
module test();
localparam period = 20;
reg clk;
reg rst;
reg [4:0] waddr;
reg [31:0] wdata;
reg wvalid;
reg wready;
always begin
clk = 1'b0;
#(period/2);
clk = 1'b1;
#(period/2);
end
always @(posedge clk) begin
if (rst)
wready <= 1'b0;
else if (!wready && wvalid)
wready <= 1'b1;
end
genvar b;
for (b = 0; b < 4; b = b + 1) begin : BYTE_BRAM_GEN
wire [7:0] data_in;
reg [7:0] byte_ram [31:0];
assign data_in = wdata[b*8 +: 8];
always @(posedge clk) begin
if (wvalid && wready)
byte_ram[waddr] <= data_in;
end
end
wire [7:0] my_byte = BYTE_BRAM_GEN[0].byte_ram[0];
task automatic wait_for_wready;
begin : waiting
@(posedge wready); // wait for rising edge
end
endtask
task init_memory;
begin
@(posedge clk);
waddr <= 0;
wdata <= 1;
wvalid <= 1'b1;
wait_for_wready;
@(posedge clk);
@(posedge clk);
$display("my_byte %h", my_byte);
if (my_byte === 8'h01)
$display("PASSED");
else
$display("FAILED");
end
endtask
initial begin
wdata = 32'd0;
wvalid = 1'b0;
rst = 1'b1;
#period;
rst = 1'b0;
init_memory;
$finish(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b, ans = 6; int len[15], last[15]; void dfs(int x, int va) { if (x == 7) { ans = min(ans, va); return; } for (int i = 1; i <= va; i++) { if (last[i] >= len[x]) { last[i] -= len[x]; dfs(x + 1, va); last[i] += len[x]; } } last[va + 1] = n - len[x]; dfs(x + 1, va + 1); } int main() { scanf( %d%d%d , &n, &a, &b); for (int i = 1; i <= 4; i++) len[i] = a; for (int i = 5; i <= 6; i++) len[i] = b; dfs(1, 0); printf( %d , ans); }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int inf = 0x3f3f3f3f; const double eps = 1e-15; const long long INF = (1LL << 60); const int N = 200000 + 100; int xis[N << 1]; bool vis[N << 1]; struct QUE { bool flag; int x, y; } que[N]; struct SegTree { int l, r; int val; } tree[2][N << 2]; int use[N << 2]; int k; void pushup(int p) { tree[k][p].val = min(tree[k][p << 1].val, tree[k][p << 1 | 1].val); } void build(int p, int l, int r) { tree[k][p].l = l; tree[k][p].r = r; if (l == r) { tree[k][p].val = inf; return; } int mid = (l + r) >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); pushup(p); } void update(int p, int pos, int val) { if (tree[k][p].l == tree[k][p].r) { tree[k][p].val = val; return; } int mid = (tree[k][p].l + tree[k][p].r) >> 1; if (pos <= mid) { update(p << 1, pos, val); } else { update(p << 1 | 1, pos, val); } pushup(p); } int tar, val, pos; int query(int p, int l, int r) { if (l <= tree[k][p].l && tree[k][p].r <= r) { return tree[k][p].val; } int mid = (tree[k][p].l + tree[k][p].r) >> 1; if (r <= mid) { return query(p << 1, l, r); } else if (l > mid) { return query(p << 1 | 1, l, r); } else { return min(query(p << 1, l, mid), query(p << 1 | 1, mid + 1, r)); } } void work1(int l, int r) { int L = l, R = r, mid; while (L <= R) { mid = (L + R) >> 1; int v = query(1, mid, r); if (v <= tar) { L = mid + 1; pos = mid; val = v; } else { R = mid - 1; } } } void work2(int l, int r) { int L = l, R = r, mid; while (L <= R) { mid = (L + R) >> 1; int v = query(1, l, mid); if (v <= tar) { R = mid - 1; pos = mid; val = v; } else { L = mid + 1; } } } char op[4]; int ret; int main() { int n, q; while (~scanf( %d%d , &n, &q)) { ret = 0; memset(vis, 0, sizeof(vis)); for (int i = 1; i <= q; ++i) { scanf( %d%d%s , &que[i].x, &que[i].y, op); if (op[0] == U ) { que[i].flag = 0; } else { que[i].flag = 1; } swap(que[i].x, que[i].y); xis[++ret] = que[i].x; } sort(xis + 1, xis + 1 + ret); ret = unique(xis + 1, xis + 1 + ret) - xis - 1; k = 0; build(1, 1, ret); k = 1; build(1, 1, ret); for (int i = 1; i <= q; ++i) { int x = que[i].x; int y = que[i].y; int ans = 0; int indx = lower_bound(xis + 1, xis + 1 + ret, x) - xis; if (vis[indx]) { printf( 0 n ); continue; } val = inf; vis[indx] = 1; if (que[i].flag == 0) { tar = y; if (indx == 1) { ans = x; } else { k = 0; work1(1, indx - 1); if (val <= tar) { ans = x - xis[pos]; } else { ans = x; } } k = 1; update(1, indx, x - ans + 1); } else { tar = x; if (indx == ret) { ans = y; } else { k = 1; work2(indx + 1, ret); if (val <= tar) { ans = y - (n + 1 - xis[pos]); } else { ans = y; } } k = 0; update(1, indx, y - ans + 1); } printf( %d n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; t = 1; while (t--) { long long int n; cin >> n; long long int arr[n + 1]; long long int ans[n + 1]; unordered_map<long long int, long long int> mp; arr[0] = 0; for (__typeof(n + 1) i = (1) - ((1) > (n + 1)); i != (n + 1) - ((1) > (n + 1)); i += 1 - 2 * ((1) > (n + 1))) { cin >> arr[i]; mp[arr[i]] = 1; } long long int p = 0; for (__typeof(n + 1) i = (1) - ((1) > (n + 1)); i != (n + 1) - ((1) > (n + 1)); i += 1 - 2 * ((1) > (n + 1))) { if (arr[i] != arr[i - 1]) { ans[i] = arr[i - 1]; mp[arr[i - 1]] = 1; continue; } while (mp[p]) { p++; } ans[i] = p; mp[p] = 1; } for (__typeof(n + 1) i = (1) - ((1) > (n + 1)); i != (n + 1) - ((1) > (n + 1)); i += 1 - 2 * ((1) > (n + 1))) cout << ans[i] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Edge { int u, v, cap, cost, next; } edge[555 * 1111]; int head[555]; int NV, NE, vs, vt; void addEdge(int u, int v, int cap, int cost) { edge[NE].u = u; edge[NE].v = v; edge[NE].cap = cap; edge[NE].cost = cost; edge[NE].next = head[u]; head[u] = NE++; edge[NE].u = v; edge[NE].v = u; edge[NE].cap = 0; edge[NE].cost = -cost; edge[NE].next = head[v]; head[v] = NE++; } bool vis[555]; int d[555], pre[555]; bool SPFA() { for (int i = 0; i < NV; ++i) { vis[i] = 0; d[i] = (1 << 30); } vis[vs] = 1; d[vs] = 0; queue<int> que; que.push(vs); while (!que.empty()) { int u = que.front(); que.pop(); for (int i = head[u]; i != -1; i = edge[i].next) { int v = edge[i].v; if (edge[i].cap && d[v] > d[u] + edge[i].cost) { d[v] = d[u] + edge[i].cost; pre[v] = i; if (!vis[v]) { vis[v] = 1; que.push(v); } } } vis[u] = 0; } return d[vt] != (1 << 30); } int MCMF() { int res = 0; while (SPFA()) { int flow = (1 << 30), cost = 0; for (int u = vt; u != vs; u = edge[pre[u]].u) { flow = min(flow, edge[pre[u]].cap); } for (int u = vt; u != vs; u = edge[pre[u]].u) { edge[pre[u]].cap -= flow; edge[pre[u] ^ 1].cap += flow; cost += flow * edge[pre[u]].cost; } res += cost; } return res; } int tn, ch[55500][26], fail[55500]; vector<int> vec[55500]; void insert(char *s, int k) { int x = 0; for (int i = 0; s[i]; ++i) { int y = s[i] - a ; if (ch[x][y] == 0) ch[x][y] = ++tn; x = ch[x][y]; } vec[x].push_back(k); } void getfail() { queue<int> que; for (int i = 0; i < 26; ++i) { if (ch[0][i]) que.push(ch[0][i]); } while (!que.empty()) { int x = que.front(); que.pop(); for (int i = 0; i < 26; ++i) { if (ch[x][i]) { fail[ch[x][i]] = ch[fail[x]][i]; que.push(ch[x][i]); } else ch[x][i] = ch[fail[x]][i]; } } } int val[111], len[111]; void ac(char *s) { int x = 0; for (int i = 0; s[i]; ++i) { int y = s[i] - a ; x = ch[x][y]; for (int tmp = x; tmp; tmp = fail[tmp]) { for (int j = 0; j < vec[tmp].size(); ++j) { int k = vec[tmp][j]; addEdge(i - len[k] + 1, i + 1, 1, -val[k]); } } } } char S[555], T[555]; int main() { int n, m, x; scanf( %d%s%d , &n, S, &m); for (int i = 1; i <= m; ++i) { scanf( %s%d , T, val + i); len[i] = strlen(T); insert(T, i); } scanf( %d , &x); vs = n + 1; vt = vs + 1; NV = vt + 1; NE = 0; memset(head, -1, sizeof(head)); addEdge(vs, 0, x, 0); addEdge(n, vt, x, 0); for (int i = 1; i <= n; ++i) { addEdge(i - 1, i, (1 << 30), 0); } getfail(); ac(S); printf( %d , -MCMF()); return 0; }
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the encoder
// Import the modules that will be tested for in this testbench
`include "encoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_encoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [14:0] cout;
// Declare "reg" signals: inputs to the DUT
reg [10:0] b;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
ham_15_11_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
b,cout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
b = 11'b11010110000;
$display(b[1]," << b1 b2 >>",b[2]);
$display(b[3]," << b1 b2 >>",b[4]);
// @ t=0,
#1;
b = 11'b11100011100;
#1;
b = 11'b11001110101;
#1;
b = 11'b11110111001;
#1;
b = 11'b11111000010;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int compareAscending(const void *a, const void *b) { return (*(int *)a - *(int *)b); } int compareDecending(const void *a, const void *b) { return (*(int *)b - *(int *)a); } int compareFirst(const void *a, const void *b) { if (((pair<int, int> *)a)->first == ((pair<int, int> *)b)->first) return ((pair<int, int> *)a)->second - ((pair<int, int> *)b)->second; else return ((pair<int, int> *)a)->first - ((pair<int, int> *)b)->first; } int compareSecond(const void *a, const void *b) { if (((pair<int, int> *)a)->second == ((pair<int, int> *)b)->second) return ((pair<int, int> *)a)->first - ((pair<int, int> *)b)->first; else return ((pair<int, int> *)a)->second - ((pair<int, int> *)b)->second; } bool isPrime(int a) { if (a < 2) return false; if (a < 4) return true; if (a % 2 == 0) return false; int s = (int)sqrt(a); for (int i = 3; i <= s; i += 2) { if (a % i == 0) return false; } return true; } int bsearch(int *a, int value, int l, int r) { if (l == r) return l; if (l + 1 == r) return a[l] >= value ? l : r; int m = (l + r) / 2; if (a[m] >= value) return bsearch(a, value, l, m); else return bsearch(a, value, m + 1, r); } int main() { long long a, b, res = 0, t; scanf( %lld %lld , &a, &b); while (a != 0 && b != 0) { res += a / b; t = a % b; a = b; b = t; } printf( %lld , res); return 0; }
|
/************************************************************************
statusLED.v
Status LED control module
Domesday Duplicator - LaserDisc RF sampler
Copyright (C) 2018 Simon Inns
This file is part of Domesday Duplicator.
Domesday Duplicator is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Email:
************************************************************************/
module statusLED (
input nReset,
input clock,
// Outputs
output reg [7:0] leds
);
// Control the status LEDs
reg [31:0] timer;
reg direction;
reg [3:0] position; // 4-bit value 0-15
always @ (posedge clock, negedge nReset) begin
if (!nReset) begin
leds <= 8'b00000001;
timer <= 16'd0;
direction <= 1'b1;
position <= 4'd0;
end else begin
timer <= timer + 32'd1;
// Wait for the timer to elapse before updating LEDs
if (timer >= 32'd4000000) begin
case(position)
4'd0:leds <= 8'b00000001;
4'd1:leds <= 8'b00000010;
4'd2:leds <= 8'b00000100;
4'd3:leds <= 8'b00001000;
4'd4:leds <= 8'b00010000;
4'd5:leds <= 8'b00100000;
4'd6:leds <= 8'b01000000;
4'd7:leds <= 8'b10000000;
endcase
if (direction) begin
if (position == 4'd7) begin
position <= 4'd6;
direction <= 1'b0;
end else begin
position <= position + 4'd1;
end
end else begin
if (position == 4'd0) begin
position <= 4'd1;
direction <= 1'b1;
end else begin
position <= position - 4'd1;
end
end
// Reset timer
timer <= 16'd0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[10000]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int n, k; string s; cin >> n >> k; cin >> s; int cnt = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == s[i - 1]) { cnt++; } else { ans[s[i - 1]] += cnt / k; cnt = 1; } } ans[s[s.size() - 1]] += cnt / k; int mx = -1; for (char i = a ; i <= z ; i++) { mx = max(ans[i], mx); } cout << mx; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, r; char str[] = { R , O , Y , B , G , I , V }; cin >> n; r = n % 7; n -= r; for (i = 0; i < n; i++) cout << str[i % 7]; for (i = 0; i < r; i++) cout << str[3 + i % 4]; }
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable Single-Port RAM model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ram_sp (
// OUTPUTs
ram_dout, // RAM data output
// INPUTs
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_clk, // RAM clock
ram_din, // RAM data input
ram_wen // RAM write enable (low active)
);
// PARAMETERs
//============
parameter ADDR_MSB = 6; // MSB of the address bus
parameter MEM_SIZE = 256; // Memory size in bytes
// OUTPUTs
//============
output [15:0] ram_dout; // RAM data output
// INPUTs
//============
input [ADDR_MSB:0] ram_addr; // RAM address
input ram_cen; // RAM chip enable (low active)
input ram_clk; // RAM clock
input [15:0] ram_din; // RAM data input
input [1:0] ram_wen; // RAM write enable (low active)
// RAM
//============
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addr_reg;
wire [15:0] mem_val = mem[ram_addr];
always @(posedge ram_clk)
if (~ram_cen && (ram_addr<(MEM_SIZE/2)))
begin
if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
ram_addr_reg <= ram_addr;
end
assign ram_dout = mem[ram_addr_reg];
endmodule // ram_sp
|
#include <bits/stdc++.h> using namespace std; int n, m, k, p, x, y, f, kek, all, a[100005]; int main() { cin >> n >> k >> p >> x >> y; for (int i = 1; i <= k; i++) cin >> a[i]; int kol = (n + 1) / 2; for (int i = 1; i <= k; i++) if (a[i] >= y) kol--; if (n - k < kol) { cout << -1; return 0; } if (kol > 0) for (int j = k + 1; j <= k + kol; j++) a[j] = y; kol = max(0, kol); for (int j = k + kol + 1; j <= n; j++) a[j] = 1; int all = 0; for (int i = 1; i <= n; i++) all += a[i]; if (all > x) { cout << -1; return 0; } for (int i = k + 1; i <= n; i++) cout << a[i] << ; }
|
#include <bits/stdc++.h> using namespace std; struct flow_graph { int V, E, s, t; int *flow, *low, *cap, *to, *next, *last, *delta; int *dist, *q, *now, head, tail; flow_graph() {} flow_graph(int V, int E) { (*this).V = V; (*this).E = 0; int TE = 2 * (E + V + 1); flow = new int[TE]; low = new int[TE]; cap = new int[TE]; to = new int[TE]; next = new int[TE]; last = new int[V + 2]; delta = new int[V]; dist = new int[V + 2]; q = new int[V + 2]; now = new int[V + 2]; } void clear(int V) { (*this).V = V; (*this).E = 0; fill(last, last + V, -1); } void add_edge(int a, int b, int l, int u) { to[E] = b; low[E] = l; cap[E] = u; flow[E] = 0; next[E] = last[a]; last[a] = E++; to[E] = a; low[E] = 0; cap[E] = 0; flow[E] = 0; next[E] = last[b]; last[b] = E++; } bool bfs() { fill(dist, dist + V + 2, -1); head = tail = 0; q[tail] = t; ++tail; dist[t] = 0; while (head < tail) { int v = q[head]; ++head; for (int e = last[v]; e != -1; e = next[e]) { if (cap[e ^ 1] > flow[e ^ 1] && dist[to[e]] == -1) { q[tail] = to[e]; ++tail; dist[to[e]] = dist[v] + 1; } } } return dist[s] != -1; } int dfs(int v, int f) { if (v == t) return f; for (int &e = now[v]; e != -1; e = next[e]) { if (cap[e] > flow[e] && dist[to[e]] == dist[v] - 1) { int ret = dfs(to[e], min(f, cap[e] - flow[e])); if (ret > 0) { flow[e] += ret; flow[e ^ 1] -= ret; return ret; } } } return 0; } int max_flow(int source, int sink) { fill(delta, delta + V, 0); for (int e = 0; e < E; e += 2) { delta[to[e ^ 1]] -= low[e]; delta[to[e]] += low[e]; cap[e] -= low[e]; } last[V] = last[V + 1] = -1; int sum = 0; for (int i = 0; i < V; ++i) { if (delta[i] > 0) { add_edge(V, i, 0, delta[i]); sum += delta[i]; } if (delta[i] < 0) add_edge(i, V + 1, 0, -delta[i]); } add_edge(sink, source, 0, INT_MAX); s = V; t = V + 1; int f = 0, df; fill(flow, flow + E, 0); while (bfs()) { for (int i = V + 1; i >= 0; --i) now[i] = last[i]; while (true) { df = dfs(s, INT_MAX); if (df == 0) break; f += df; } } if (f != sum) return -1; for (int e = 0; e < E; e += 2) { cap[e] += low[e]; flow[e] += low[e]; flow[e ^ 1] -= low[e]; cap[e ^ 1] -= low[e]; } s = source; t = sink; last[s] = next[last[s]]; last[t] = next[last[t]]; E -= 2; while (bfs()) { for (int i = V - 1; i >= 0; --i) now[i] = last[i]; while (true) { df = dfs(s, INT_MAX); if (df == 0) break; f += df; } } return f; } }; const int N = 100005; pair<int, int> arr[N]; int xs[N], ys[N]; int dx[N], dy[N]; int qntx[N], qnty[N]; int pnt_id[N]; char ans[N]; int main() { int n, m; scanf( %d %d , &n, &m); int r, b; scanf( %d %d , &r, &b); char cheap = r , expensive = b ; if (r > b) { swap(cheap, expensive); swap(r, b); } for (int i = 0; i < n; ++i) { int x, y; scanf( %d %d , &x, &y); arr[i] = pair<int, int>(x, y); xs[i] = x; ys[i] = y; } sort(xs, xs + n); int xssz = unique(xs, xs + n) - xs; sort(ys, ys + n); int yssz = unique(ys, ys + n) - ys; for (int i = 0; i < n; ++i) { arr[i].first = lower_bound(xs, xs + xssz, arr[i].first) - xs; arr[i].second = lower_bound(ys, ys + yssz, arr[i].second) - ys; ++qntx[arr[i].first]; ++qnty[arr[i].second]; ++dx[arr[i].first]; ++dy[arr[i].second]; } for (int i = 0; i < m; ++i) { int t, l, d; scanf( %d %d %d , &t, &l, &d); if (t == 1) { int k = lower_bound(xs, xs + xssz, l) - xs; if (xs[k] == l) { dx[k] = min(dx[k], d); } } else { int k = lower_bound(ys, ys + yssz, l) - ys; if (ys[k] == l) { dy[k] = min(dy[k], d); } } } flow_graph fg = flow_graph(xssz + yssz + 2, n + xssz + yssz); fg.clear(xssz + yssz + 2); int source = xssz + yssz, sink = source + 1; for (int i = 0; i < xssz; ++i) { int l = (qntx[i] - dx[i] + 1) / 2; int r = (qntx[i] + dx[i]) / 2; if (l > r) { puts( -1 ); return 0; } fg.add_edge(source, i, l, r); } for (int i = 0; i < n; ++i) { pnt_id[i] = fg.E; fg.add_edge(arr[i].first, arr[i].second + xssz, 0, 1); } for (int i = 0; i < yssz; ++i) { int l = (qnty[i] - dy[i] + 1) / 2; int r = (qnty[i] + dy[i]) / 2; if (l > r) { puts( -1 ); return 0; } fg.add_edge(i + xssz, sink, l, r); } if (fg.max_flow(source, sink) < 0) { puts( -1 ); return 0; } long long qnt = 0; for (int i = 0; i < n; ++i) { int id = pnt_id[i]; if (fg.flow[id] > 0) ans[i] = cheap, ++qnt; else ans[i] = expensive; } printf( %lld n , qnt * r + (n - qnt) * b); printf( %s n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e3 + 1; int dp[N][N]; bool palid[N][N]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); string s; cin >> s; int n = s.size(); for (int d = 0; d < n; d++) for (int i = 0; i < n; i++) { int j = i + d; if (j >= n) continue; palid[i][j] = (s[i] == s[j]); if (i + 1 <= j - 1) palid[i][j] &= palid[i + 1][j - 1]; } for (int d = 0; d < n; d++) for (int i = 0; i < n; i++) { int j = i + d; if (j >= n) continue; dp[i][j] = palid[i][j]; if (i + 1 <= j) dp[i][j] += dp[i + 1][j]; if (i <= j - 1) dp[i][j] += dp[i][j - 1]; if (i + 1 <= j - 1) dp[i][j] -= dp[i + 1][j - 1]; } int q; cin >> q; for (int i = 0; i < q; i++) { int l, r; cin >> l >> r; l--; r--; cout << dp[l][r] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m, val, sum = 0; cin >> n; vector<long long> v, q; for (long long i = 0; i < n; i++) { cin >> val; v.push_back(val); sum += val; } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); cin >> m; for (long long i = 0; i < m; i++) { cin >> val; cout << sum - v[val - 1] << endl; } return 0; }
|
// shirley smokes weed #include <bits/stdc++.h> #define sz(v) ((int)(v).size()) #define all(v) (v).begin(), (v).end() using namespace std; using lint = long long; using pi = pair<int, int>; const int MAXN = 400; int n, m, s[MAXN], e[MAXN], x[MAXN]; int dp[1 << 18], indep[1 << 18], w[1 << 18], tk[1 << 18]; int main(){ scanf( %d %d ,&n,&m); for(int i=0; i<m; i++){ scanf( %d %d %d ,&s[i],&e[i],&x[i]); s[i]--; e[i]--; } for(int i=1; i<(1<<n); i++){ indep[i] = 1; for(int j=0; j<m; j++){ int b1 = (i >> s[j]) & 1; int b2 = (i >> e[j]) & 1; if(b1 && b2) indep[i] = 0; if(b1 == b2) continue; if(b1 == 1 && b2 == 0) w[i] = 1e9; else w[i] += x[j]; } } dp[0] = 0; for(int i=1; i<(1<<n); i++){ dp[i] = 1e9; if(w[i] > 1e8) continue; for(int j=i; j; j=(j-1)&i){ if(indep[j] && dp[i] > dp[i ^ j]){ dp[i] = dp[i ^ j]; tk[i] = j; } } dp[i] += w[i]; } vector<int> a(n); for(int i = (1 << n) - 1; i; i ^= tk[i]){ for(int j = 0; j < n; j++){ if((i >> j) & 1) a[j]++; } } for(int i=0; i<n; i++) printf( %d , n + 1 - a[i]); }
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHRU_7 (
CLK,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5,
read_6,
write_6,
EN_write_6
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
output [DATA_SZ-1:0] read_6;
input [DATA_SZ-1:0] write_6;
input EN_write_6;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
wire [DATA_SZ-1:0] wire_7;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign wire_7 = EN_write_6 ? write_6 : wire_6;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
assign read_6 = wire_6;
always @(posedge CLK) begin
r <= wire_7;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, p; cin >> a >> b >> p; string s; cin >> s; int len = s.size(); int pos = 0; char ss = C ; for (int i = len - 2; i >= 0; i--) { if (ss != s[i]) { p -= (s[i] == A ? a : b); ss = s[i]; if (p < 0) { pos = i + 1; break; } } } cout << pos + 1 << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:60000000 ) using namespace std; const long double eps = 1e-9; const int inf = (1 << 30) - 1; const long long inf64 = ((long long)1 << 62) - 1; const long double pi = 3.1415926535897932384626433832795; template <class T> T sqr(T x) { return x * x; } int n, m, k; vector<pair<int, int> > a; vector<int> g[300500]; int u[300500]; vector<int> q; void go(int v) { u[v] = 1; for (int i = 0; i < (int)(g[v].size()); i++) if (u[g[v][i]] == 0) go(g[v][i]); else if (u[g[v][i]] == 1) { cout << -1 << endl; exit(0); } u[v] = 2; q.push_back(v); } int main() { cin >> n >> m; k = m; for (int i = 0; i < (int)(n); i++) { a.clear(); for (int j = 0; j < (int)(m); j++) { int x; scanf( %d , &x); if (x != -1) a.push_back(make_pair(x, j)); } sort(a.begin(), a.end()); if (a.size() == 0) continue; int l = 0; int r = l; while (r + 1 < (int)a.size() && a[r + 1].first == a[l].first) r++; while (r + 1 < (int)a.size()) { int l2 = r + 1; int r2 = l2; while (r2 + 1 < (int)a.size() && a[r2 + 1].first == a[l2].first) r2++; for (int j = l; j <= r; j++) g[a[j].second].push_back(k); for (int j = l2; j <= r2; j++) g[k].push_back(a[j].second); k++; l = l2; r = r2; } } memset(u, 0, sizeof(u)); q.clear(); for (int i = 0; i < (int)(m); i++) if (!u[i]) go(i); for (int i = (int)(q.size()) - 1; i >= 0; i--) if (q[i] < m) printf( %d , q[i] + 1); cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int N = 100005; const double PI = 4 * atan(1); const double eps = 1e-7; const long long oo = 1e18; const int AlPHA = 26, B = 30; long long n, m, L, sr, t; long long adj[1005][1005]; long long yes[1005][1005]; long long dist[1005]; vector<long long> ad[N]; bool vis[1005]; vector<pair<long long, long long> > v; void dijkstra(long long src) { set<pair<long long, long long> > ss; pair<long long, long long> ras; for (int i = 0; i < n; i++) { dist[i] = 1e17; vis[i] = 0; } dist[src] = 0; ss.insert(make_pair(0, src)); while (!ss.empty()) { ras = *(ss.begin()); ss.erase(ss.begin()); src = ras.second; long long w = ras.first; if (vis[src]) continue; vis[src] = 1; for (auto u : ad[src]) { if (dist[u] > w + adj[src][u]) { dist[u] = w + adj[src][u]; ss.insert(make_pair(dist[u], u)); } } } } int main() { ios::sync_with_stdio(0); cin >> n >> m >> L >> sr >> t; for (int i = 0; i < m; i++) { long long x, y, z; cin >> x >> y >> z; ad[x].push_back(y); ad[y].push_back(x); if (z > 0) { adj[x][y] = adj[y][x] = z; } else { adj[x][y] = adj[y][x] = 1; yes[x][y] = yes[y][x] = 1; v.push_back(make_pair(x, y)); } } dijkstra(sr); long long x = dist[t]; long long i = 0; while (i < v.size() && x < L) { long long y = L - x + 1; adj[v[i].first][v[i].second] = adj[v[i].second][v[i].first] = y; dijkstra(sr); x = dist[t]; i++; } if (x != L) { cout << NO ; return 0; } else { cout << YES n ; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (adj[i][j]) cout << i << << j << << adj[i][j] << n ; } } } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 18.02.2016 11:42:49
// Design Name:
// Module Name: red_pitaya_lpf_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
/* This module takes a signed input signal of SIGNALBITS, multiplies it by a
gain ranging from 1 to 2**(SIGNALBITS-1)-1, and subtracts it from a custom
setpoint before outputting the signal. The multiplication factor is the
result from taking the absolute value of the output signal and integrating
it. That way, the output signal will be stabilized at setpoint up to the
unity-gain frequency of the integrator, but its higher-frequency components
will pass through. One useful application of this is to make a pdh signal
more robust to amplitude fluctuations that it already is, as even away from
the zero crossing of the error signal, where the pdh amplitude is
proportional to the DC power, the effective DC power after this module is
constant (and equal to the setpoint). */
module red_pitaya_normalizer_block
#(
parameter ISR = 24,
parameter SIGNALBITS = 14, //bitwidth of signals
parameter GAINBITS = 16 //minimum allowed filter bandwidth
)
(
input clk_i,
input rstn_i ,
input [SHIFTBITS:0] shift,
input filter_on,
input highpass,
input signed [SIGNALBITS-1:0] signal_i,
input signed [SIGNALBITS-1:0] inputoffset_i,
input [SIGNALBITS-2:0] setpoint_i,
input signed [GAINBITS-1:0] gain_i,
output signed [SIGNALBITS-1:0] signal_o
);
// add an offset to the (analog) input value
wire signed [SIGNALBITS+1-1:0] in_subtracted;
wire [SIGNALBITS-1:0] in_abs;
assign in_subtracted = signal_i - inputoffset_i;
// make input positive, but don't add the extra bit. That gives a tiny
// offset to negative signals (1 bit, but avoid special treatment for the
// stragne number
assign in_abs = in_subtracted[SIGNALBITS] ? ((~in_subtracted) /*+'b1*/) : in_subtracted;
// buffer
reg [SIGNALBITS-1:0] input;
always @(posedge clk_i) begin
input <= in_abs[SIGNALBITS-1:0];
end
// now, input is in principle a 13 bit number, unless something went really
// wrong with the input offset (in which case its 14 bits unsigned)
// multiply input by integral factor, add something for rounding
// integral goes from 1 to 2**(SIGNALBITS)-1
// input goes from 0 to 2**(SIGNALBITS)-1, but the MSB should be zero
// so product goes from 0 to 2**(2*SIGNALBITS)-1, but MSB should be zero
// we rescale product to product_done taking only the highest SIGNALBITS+1
// bits, of which only SIGNALBITS carry any information
wire [SIGNALBITS-1:0] integral;
wire [SIGNALBITS*2-1:0] product;
assign product = input * integral; // no rounding since unsigned arithmetic
wire [SIGNALBITS*2:0] product_signed;
wire [SIGNALBITS*2:0] setpoint_signed;
assign product_signed = {1'b0, product};
// first sign bit (0), then the MSB mentioned above, then the SIGNALBITS-1 of
// relevant information
wire signed setpoint_signed = {1'b0, 1'b0, setpoint_i, {SIGNALBITS{1'b0}};
// error doesnt need extra bit since we subtract 2 positive numbers
reg signed [SIGNALBITS*2:0] error;
always @(posedge clk_i) begin
error <= setpoint_signed - product_signed;
end
// crop the number by throwing away the 2 most significant bits
reg signed [SIGNALBITS-1:0] error_done;
always @(posedge clk_i) begin
// pos saturation
if ({error[SIGNALBITS*2], (|(error[SIGNALBITS*2-1:SIGNALBITS*2-2]))} == 2'b01)
error_done <= {1'b0, {SIGNALBITS-1{1'b1}}};
else if ({error[SIGNALBITS*2], (&(error[SIGNALBITS*2-1:SIGNALBITS*2-2]))} == 2'b10)
error_done <= {1'b1, {SIGNALBITS-1{1'b0}}};
else
error_done <= error[SIGNALBITS*2-2:SIGNALBITS-2];
end
assign signal_o = filter_on ? error_done : signal_i;
// gain calculation
// negative gain because of error calculation (setpoint - product)
// therefore just need a positive integrator
reg signed [SIGNALBITS: 0] int_sum;
always @(posedge clk_i) begin
int_sum <= $signed(int_sat) + $signed(error_done);
end
// Integrator - 2 cycles delay (but treat similar to proportional since it
// will become negligible at high frequencies where delay is important)
localparam IBW = ISR+SIGNALBITS;
reg [SIGNALBITS+GAINBITS-1: 0] ki_mult ;
wire [IBW : 0] int_sum ;
reg [IBW-1: 0] int_reg ;
wire [IBW-ISR-1: 0] int_shr ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
ki_mult <= {SIGNALBITS+GAINBITS{1'b0}};
int_reg <= {IBW{1'b0}};
end
else begin
ki_mult <= $signed(error_done) * $signed(gain_i) ;
if (ival_write)
int_reg <= { {IBW-16-ISR{set_ival[16-1]}},set_ival[16-1:0],{ISR{1'b0}}};
else if (int_sum[IBW+1-1:IBW+1-2] == 2'b01) // positive saturation
int_reg <= {1'b0,{IBW-1{1'b1}}};
else if (int_sum[IBW+1-1:IBW+1-2] == 2'b10) // negative saturation
int_reg <= {1'b1,{IBW-1{1'b0}}};
else
int_reg <= int_sum[IBW-1:0]; // use sum as it is
end
end
assign int_sum = $signed(ki_mult) + $signed(int_reg) ;
assign int_shr = $signed(int_reg[IBW-1:ISR]) ;
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4bb (
VPWR,
VGND,
X ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nand0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_PP_V
|
module fpu_array (
pcx_fpio_data_rdy_px2,
pcx_fpio_data_px2,
arst_l,
grst_l,
gclk,
cluster_cken,
fp_cpx_req_cq,
fp_cpx_data_ca,
ctu_tst_pre_grst_l,
global_shift_enable,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_macrotest,
ctu_tst_short_chain,
si,
so
);
parameter SIZE = 8;
input pcx_fpio_data_rdy_px2; // FPU request ready from PCX
input [123:0] pcx_fpio_data_px2; // FPU request data from PCX
input arst_l; // chip async. reset- asserted low
input grst_l; // chip sync. reset- asserted low
input gclk; // chip clock
input cluster_cken; // cluster clock enable
output [7:0] fp_cpx_req_cq; // FPU result request to CPX
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input ctu_tst_pre_grst_l;
input global_shift_enable;
input ctu_tst_scan_disable;
input ctu_tst_scanmode;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
input si; // scan in
output so; // scan out
reg [123:0] pcx_fpio_data_px2_bus[SIZE:0];
reg pcx_fpio_data_rdy_px2_bus[SIZE:0];
wire [7:0] fp_cpx_req_cq_bus[SIZE:0];
wire [144:0] fp_cpx_data_ca_bus[SIZE:0];
genvar i;
generate
for ( i = 0; i < SIZE; i = i+1 )
begin : array
fpu fpu(
pcx_fpio_data_rdy_px2_bus[i],
pcx_fpio_data_px2_bus[i],
arst_l,
grst_l,
gclk,
cluster_cken,
fp_cpx_req_cq,
fp_cpx_data_ca,
ctu_tst_pre_grst_l,
global_shift_enable,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_macrotest,
ctu_tst_short_chain,
si,
so
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; double prb[(1 << 21)], p[25], ans[25]; int vis[(1 << 21)]; bool eq(double a, double b) { return (abs(a - b) < 1e-12); } int main() { int i, n, k, tmp; scanf( %d , &n); scanf( %d , &k); tmp = n; for (i = 0; i < n; i++) { scanf( %lf , &p[i]); if (eq(p[i], 0)) tmp--; } k = min(k, tmp); prb[0] = 1; queue<int> all; all.push(0); while (!all.empty()) { int now = all.front(); all.pop(); if (__builtin_popcount(now) == k) for (i = 0; i < n; i++) if (now & (1 << i)) ans[i] += prb[now]; double gun = 0; for (i = 0; i < n; i++) if (!(now & (1 << i))) gun += p[i]; gun = 1 / gun; if (__builtin_popcount(now) < k) for (i = 0; i < n; i++) { if ((now & (1 << i)) || eq(p[i], 0)) continue; tmp = now ^ (1 << i); prb[tmp] += (p[i] * gun * prb[now]); if (!vis[tmp]) { vis[tmp] = 1; all.push(tmp); } } } for (i = 0; i < n; i++) printf( %.15f , ans[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; set<string> s; string v; map<string, bool> m; void rot(string x) { if (m[x] == 1) return; m[x] = 1; s.erase(x); string y = x; y[0] = x[1]; y[1] = x[2]; y[2] = x[3]; y[3] = x[0]; rot(y); y = x; y[1] = x[4]; y[4] = x[3]; y[3] = x[5]; y[5] = x[1]; rot(y); return; } int main() { cin >> v; for (int i = 0; i < 1000; i++) { next_permutation(v.begin(), v.end()); s.insert(v); } int ans = 0; while (s.size() > 0) { ans++; rot(*s.begin()); } cout << ans << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_address_generator (
input clk,
input resetn,
input req_valid,
output reg req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [3:0] req_last_burst_length,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] wait_id,
input sync_id,
input eot,
input enable,
input pause,
output reg enabled,
input addr_ready,
output reg addr_valid,
output [31:0] addr,
output [ 7:0] len,
output [ 2:0] size,
output [ 1:0] burst,
output [ 2:0] prot,
output [ 3:0] cache
);
parameter C_ID_WIDTH = 3;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BURST_ALIGN_BITS = 7;
parameter C_DMA_LENGTH_WIDTH = 24;
localparam MAX_BURST_SIZE_BEATS = 2**(C_BURST_ALIGN_BITS-C_ADDR_ALIGN_BITS);
`include "inc_id.v"
assign burst = 2'b01;
assign prot = 3'b000;
assign cache = 4'b0011;
assign len = eot ? req_last_burst_length : MAX_BURST_SIZE_BEATS - 1;
assign size = 3'b011;
reg [31-C_ADDR_ALIGN_BITS:0] address = 'h00;
reg [C_BURST_ALIGN_BITS-C_ADDR_ALIGN_BITS-1:0] last_burst_len = 'h00;
assign addr = {address, {C_ADDR_ALIGN_BITS{1'b0}}};
// If we already asserted addr_valid we have to wait until it is accepted before
// we can disable the address generator.
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (~addr_valid)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
address <= 'h00;
last_burst_len <= 'h00;
req_ready <= 1'b1;
addr_valid <= 1'b0;
end else begin
if (~enabled) begin
req_ready <= 1'b1;
end else if (req_ready) begin
if (req_valid && enable) begin
address <= req_address;
req_ready <= 1'b0;
end
end else begin
if (addr_valid && addr_ready) begin
address <= address + MAX_BURST_SIZE_BEATS;
addr_valid <= 1'b0;
if (eot)
req_ready <= 1'b1;
end else if (id != wait_id) begin
addr_valid <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <='h0;
end else begin
if ((addr_valid && addr_ready) ||
(sync_id && id != wait_id))
id <= inc_id(id);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (j == 1 || i == 1) cout << B ; else { cout << W ; } } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int upd[400000][10]; long long val[400000][10]; bool dirty[400000]; void clean(int n, int l, int r) { long long buf[10]; memset(buf, 0, sizeof buf); for (int i = 0; i < 10; i++) { buf[upd[n][i]] += val[n][i]; } dirty[n] = false; for (int i = 0; i < 10; i++) { val[n][i] = buf[i]; } if (l < r) { dirty[n * 2] = dirty[n * 2 + 1] = true; for (int i = 0; i < 10; i++) { upd[n * 2][i] = upd[n][upd[n * 2][i]]; upd[n * 2 + 1][i] = upd[n][upd[n * 2 + 1][i]]; } } for (int i = 0; i < 10; i++) { upd[n][i] = i; } } long long get(int rl, int rr, int n = 1, int l = 0, int r = 100000) { if (l > rr || r < rl) return 0; if (dirty[n]) clean(n, l, r); if (l >= rl && r <= rr) { long long ans = 0; for (int i = 0; i < 10; i++) { ans += val[n][i] * i; } return ans; } long long ans = get(rl, rr, n * 2, l, (l + r) / 2); ans += get(rl, rr, n * 2 + 1, (l + r) / 2 + 1, r); return ans; } void update(int rl, int rr, int from, int to, int n = 1, int l = 0, int r = 100000) { if (l > rr || r < rl) { clean(n, l, r); return; } if (dirty[n]) clean(n, l, r); if (l >= rl && r <= rr) { for (int i = 0; i < 10; i++) { if (upd[n][i] == from) upd[n][i] = to; } dirty[n] = true; clean(n, l, r); return; } update(rl, rr, from, to, n * 2, l, (l + r) / 2); update(rl, rr, from, to, n * 2 + 1, (l + r) / 2 + 1, r); for (int i = 0; i < 10; i++) { val[n][i] = val[n * 2][i] + val[n * 2 + 1][i]; } } int n, q; int arr[100000]; void build(int n = 1, int l = 0, int r = 100000) { for (int i = 0; i < 10; i++) upd[n][i] = i; if (l == r) { if (l < n) { int mul = 1; int c = arr[l]; while (c) { val[n][c % 10] += mul; c /= 10; mul *= 10; } } return; } build(n * 2, l, (l + r) / 2); build(n * 2 + 1, (l + r) / 2 + 1, r); for (int i = 0; i < 10; i++) { val[n][i] = val[n * 2][i] + val[n * 2 + 1][i]; } } void printtree() { for (int i = 0; i < n; i++) { cout << get(i, i) << ; } cout << endl; } int main() { ios::sync_with_stdio(false); cin >> n >> q; for (int i = 0; i < n; i++) { cin >> arr[i]; } build(); for (int i = 0; i < q; i++) { int t, l, r, x, y; cin >> t; if (t == 1) { cin >> l >> r >> x >> y; update(l - 1, r - 1, x, y); } else { cin >> l >> r; cout << get(l - 1, r - 1) << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; const int pN = 1e6; const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; void add(long long &x, long long y) { x += y; x %= MOD; } bool vis[MAXN]; int a[MAXN]; int main() { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; int ans = INF; int id; for (int i = 0; i < n; i++) { if (vis[i]) continue; int sum = 0; for (int j = i;; j = (j + k) % n) { if (vis[j]) break; vis[j] = true; sum += a[j]; } if (sum < ans) { id = i; ans = sum; } } cout << id + 1 << endl; return 0; }
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
`timescale 1ns/1ns
module RX_SPW (
input rx_din,
input rx_sin,
input rx_resetn,
output rx_error,
output reg rx_got_bit,
output rx_got_null,
output rx_got_nchar,
output rx_got_time_code,
output rx_got_fct,
output rx_got_fct_fsm,
output [8:0] rx_data_flag,
output rx_buffer_write,
output [7:0] rx_time_out,
output rx_tick_out
);
wire [5:0] counter_neg/* synthesis syn_replicate = 0 */;
wire posedge_clk;
wire negedge_clk;
wire bit_c_0;//N
wire bit_c_1;//P
wire bit_c_2;//N
wire bit_c_3;//P
wire bit_d_0;//N
wire bit_d_1;//P
wire bit_d_2;//N
wire bit_d_3;//P
wire bit_d_4;//N
wire bit_d_5;//P
wire bit_d_6;//N
wire bit_d_7;//P
wire bit_d_8;//N
wire bit_d_9;//P
wire [1:0] state_data_process;
wire is_control/* synthesis dont_replicate */;
wire last_is_control;
wire last_is_data;
wire last_is_timec;
wire [2:0] control_p_r/* synthesis dont_replicate */;
wire [7:0] timecode/* synthesis dont_replicate */;
wire [2:0] control_l_r/* synthesis dont_replicate */;
wire [8:0] dta_timec_p/* synthesis dont_replicate */;
reg ready_control;
reg ready_data;
wire ready_control_p_r;
wire ready_data_p_r;
wire parity_rec_c;
wire parity_rec_d;
wire parity_rec_c_gen;
wire parity_rec_d_gen;
wire rx_error_c;
wire rx_error_d;
wire posedge_p/* synthesis syn_replicate = 0 */;
reg f_time;
//CLOCK RECOVERY
assign posedge_clk = posedge_p;
assign negedge_clk = (f_time)?!posedge_p:1'b0;
assign rx_time_out = timecode;
buf (posedge_p,rx_din ^ rx_sin);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
f_time <= 1'b0;
end
else
begin
f_time <= 1'b1;
end
end
always@(*)
begin
rx_got_bit = 1'b0;
if(rx_din | rx_sin)
begin
rx_got_bit = 1'b1;
end
end
always@(*)
begin
ready_control = 1'b0;
ready_data = 1'b0;
if(is_control && counter_neg == 6'd4 && !posedge_p)
begin
ready_control = 1'b1;
ready_data = 1'b0;
end
else if(!is_control && counter_neg == 6'd32 && !posedge_p)
begin
ready_control = 1'b0;
ready_data = 1'b1;
end
end
rx_buffer_fsm buffer_fsm(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.last_is_data(last_is_data),
.last_is_timec(last_is_timec),
.last_is_control(last_is_control),
.rx_got_null(rx_got_null),
.rx_got_nchar(rx_got_nchar),
.rx_got_time_code(rx_got_time_code)
);
rx_data_buffer_data_w buffer_data_flag(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.state_data_process(state_data_process),
.control(control_p_r),
.last_is_timec(last_is_timec),
.last_is_data(last_is_data),
.last_is_control(last_is_control),
.rx_buffer_write(rx_buffer_write),
.rx_tick_out(rx_tick_out)
);
rx_control_data_rdy control_data_rdy(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_error_c(rx_error_c),
.rx_error_d(rx_error_d),
.control(control_p_r),
.control_l_r(control_l_r[2:0]),
.is_control(is_control),
.counter_neg(counter_neg),
.last_is_control(last_is_control),
.rx_error(rx_error),
.ready_control_p_r(ready_control_p_r),
.ready_data_p_r(ready_data_p_r),
.rx_got_fct_fsm(rx_got_fct_fsm)
);
rx_data_control_p data_control(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.bit_c_3(bit_c_3),
.bit_c_2(bit_c_2),
.bit_c_1(bit_c_1),
.bit_c_0(bit_c_0),
.bit_d_9(bit_d_9),
.bit_d_8(bit_d_8),
.bit_d_0(bit_d_0),
.bit_d_1(bit_d_1),
.bit_d_2(bit_d_2),
.bit_d_3(bit_d_3),
.bit_d_4(bit_d_4),
.bit_d_5(bit_d_5),
.bit_d_6(bit_d_6),
.bit_d_7(bit_d_7),
.last_is_control(last_is_control),
.last_is_data(last_is_data),
.is_control(is_control),
.counter_neg(counter_neg),
.dta_timec_p(dta_timec_p),
.parity_rec_d(parity_rec_d),
.parity_rec_d_gen(parity_rec_d_gen),
.control_p_r(control_p_r),
.control_l_r(control_l_r),
.parity_rec_c(parity_rec_c),
.parity_rec_c_gen(parity_rec_c_gen)
);
bit_capture_data capture_d(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_d_0(bit_d_0),//N
.bit_d_1(bit_d_1),//P
.bit_d_2(bit_d_2),//N
.bit_d_3(bit_d_3),//P
.bit_d_4(bit_d_4),//N
.bit_d_5(bit_d_5),//P
.bit_d_6(bit_d_6),//N
.bit_d_7(bit_d_7),//P
.bit_d_8(bit_d_8),//N
.bit_d_9(bit_d_9)//P
);
bit_capture_control capture_c(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_c_0(bit_c_0),
.bit_c_1(bit_c_1),
.bit_c_2(bit_c_2),
.bit_c_3(bit_c_3)
);
counter_neg cnt_neg(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.is_control(is_control),
.counter_neg(counter_neg)
);
rx_data_receive rx_dtarcv (
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.ready_control_p_r(ready_control_p_r),
.ready_data_p_r(ready_data_p_r),
.ready_control(ready_control),
.ready_data(ready_data),
.parity_rec_c(parity_rec_c),
.parity_rec_d(parity_rec_d),
.parity_rec_c_gen(parity_rec_c_gen),
.parity_rec_d_gen(parity_rec_d_gen),
.control_p_r(control_p_r),
.dta_timec_p(dta_timec_p),
.control_l_r(control_l_r),
.state_data_process(state_data_process),
.last_is_control(last_is_control),
.last_is_data(last_is_data),
.last_is_timec(last_is_timec),
.rx_error_c(rx_error_c),
.rx_error_d(rx_error_d),
.rx_got_fct(rx_got_fct),
.rx_data_flag(rx_data_flag),
.timecode(timecode)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5, M = 350; long long dp[5][N], B, a[N], b[N], t[N], n, m, d, minans = 1e9 + 10, dpL[N], dpR[N]; int last, ldel; deque<int> stac; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> d; for (int i = 0; i < m; i++) { cin >> a[i] >> b[i] >> t[i]; B += b[i]; } for (int j = 0; j < n; j++) dp[0][j] = abs(a[0] - (j + 1)); for (int i = 1; i < m; i++) { last = (i - 1) % 2; for (int j = 0; j < n; j++) { ldel = j; while (!stac.empty() && stac.front() < (j - ((t[i] - t[i - 1]) * d))) stac.pop_front(); while (!stac.empty() && dp[last][stac.back()] >= dp[last][j]) ldel = stac.back(), stac.pop_back(); if (stac.empty()) dpL[j] = dp[last][ldel]; else dpL[j] = dp[last][stac.front()]; stac.push_back(j); } for (int j = n - 1; j >= 0; j--) { ldel = j; while (!stac.empty() && stac.front() > (j + ((t[i] - t[i - 1]) * d))) stac.pop_front(); while (!stac.empty() && dp[last][stac.back()] >= dp[last][j]) ldel = stac.back(), stac.pop_back(); if (stac.empty()) dpR[j] = dp[last][ldel]; else dpR[j] = dp[last][stac.front()]; stac.push_back(j); } for (int j = 0; j < n; j++) dp[i % 2][j] = min(min(dpR[j], dpL[j]), dp[last][j]) + abs(a[i] - (j + 1)); stac.clear(); } for (int i = 0; i < n; i++) minans = min(minans, dp[(m - 1) % 2][i]); cout << B - minans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; char a[100005], ans[100005]; int main() { int n, m; cin >> n; while (n--) { cin >> a; m = strlen(a); for (int i = 0; i < m; i++) { if (a[i] != ? ) { if (ans[i] == 0) ans[i] = a[i]; else if (a[i] != ans[i]) ans[i] = ? ; } } } ans[m] = 0; for (int i = 0; i < m; i++) { if (ans[i] == 0) ans[i] = a ; } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:45:48 02/22/2015
// Design Name:
// Module Name: MultiplyMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MultiplyMult(
input [32:0] aout_Special,
input [32:0] bout_Special,
input [32:0] zout_Special,
input idle_Special,
input clock,
output reg idle_Multiply,
output reg [32:0] zout_Multiply,
output reg [49:0] productout_Multiply
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire a_sign;
wire [7:0] a_exponent;
wire [23:0] a_mantissa;
wire b_sign;
wire [7:0] b_exponent;
wire [23:0] b_mantissa;
assign a_sign = aout_Special[32];
assign a_exponent = aout_Special[31:24] - 127;
assign a_mantissa = {aout_Special[23:0]};
assign b_sign = bout_Special[32];
assign b_exponent = bout_Special[31:24] - 127;
assign b_mantissa = {bout_Special[23:0]};
always @ (posedge clock)
begin
idle_Multiply <= idle_Special;
if (idle_Special == no_idle) begin
zout_Multiply[32] <= a_sign ^ b_sign;
zout_Multiply[31:24] <= a_exponent + b_exponent + 1;
zout_Multiply[23:0] <= 0;
productout_Multiply <= a_mantissa * b_mantissa * 4;
end
else begin
zout_Multiply <= zout_Special;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 25; long long n, ans[N]; pair<int, int> arr[N]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> arr[i].first, arr[i].second = i; sort(arr, arr + n); for (int i = 0; i < n; i++) ans[arr[(i + 1) % n].second] = arr[i].first; for (int i = 0; i < n; i++) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 9; int n, u, v, w, t, p, sub[N], par[N], mark[N]; vector<pair<int, int> > g[N]; vector<pair<int, pair<int, int> > > edge[N]; pair<pair<int, int>, pair<int, int> > ed[N]; long long mx, ans[N]; set<int> s; int Get_par(int u) { if (par[u] < 0) return u; return par[u] = Get_par(par[u]); } void merge(int u, int v) { u = Get_par(u), v = Get_par(v); if (par[v] < par[u]) swap(u, v); par[u] += par[v]; par[v] = u; } void dfs1(int x) { sub[x] = par[x] * -1, mark[x] = 1; for (int i = 0; i < g[x].size(); i++) if (!mark[g[x][i].first]) dfs1(g[x][i].first), sub[x] += sub[g[x][i].first]; } void dfs2(int x, int rt, int e) { mark[x] = 2; ans[e] = 1ll * sub[x] * (sub[rt] - sub[x]); for (int i = 0; i < g[x].size(); i++) if (mark[g[x][i].first] < 2) dfs2(g[x][i].first, rt, g[x][i].second); } int main() { fill(par, par + N, -1); cin >> n; for (int i = 1; i < n; i++) { scanf( %d%d , &ed[i].second.first, &ed[i].second.second); ; scanf( %d , &ed[i].first.first); ; ed[i].first.second = i; } sort(ed + 1, ed + n); for (int i = 1; i < n; i++) { if (i != 1 && ed[i].first.first != ed[i - 1].first.first) p++; edge[p].push_back( make_pair(ed[i].first.second, make_pair(ed[i].second.first, ed[i].second.second))); } for (int k = 0; k < N; k++) { for (int i = 0; i < edge[k].size(); i++) { edge[k][i].second.first = Get_par(edge[k][i].second.first), edge[k][i].second.second = Get_par(edge[k][i].second.second); g[edge[k][i].second.first].clear(), g[edge[k][i].second.second].clear(); } for (int i = 0; i < edge[k].size(); i++) g[edge[k][i].second.first].push_back( make_pair(edge[k][i].second.second, edge[k][i].first)), g[edge[k][i].second.second].push_back( make_pair(edge[k][i].second.first, edge[k][i].first)), mark[edge[k][i].second.first] = mark[edge[k][i].second.second] = 0; for (int i = 0; i < edge[k].size(); i++) if (!mark[edge[k][i].second.first]) dfs1(edge[k][i].second.first); for (int i = 0; i < edge[k].size(); i++) { merge(edge[k][i].second.first, edge[k][i].second.second); if (mark[edge[k][i].second.first] < 2) dfs2(edge[k][i].second.first, edge[k][i].second.first, 0); } } for (int i = 1; i < n; i++) mx = max(mx, ans[i]); ; for (int i = 1; i < n; i++) t += (ans[i] == mx); cout << mx * 2 << << t << endl; for (int i = 1; i < n; i++) if (ans[i] == mx) cout << i << ; }
|
module alu(
input clk,
input [7:0] A,
input [7:0] B,
input [3:0] operation,
output reg [7:0] result,
output reg CF,
output reg ZF,
output reg SF
);
localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000;
localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001;
localparam ALU_OP_ADC /* verilator public_flat */ = 4'b0010;
localparam ALU_OP_SBC /* verilator public_flat */ = 4'b0011;
localparam ALU_OP_AND /* verilator public_flat */ = 4'b0100;
localparam ALU_OP_OR /* verilator public_flat */ = 4'b0101;
localparam ALU_OP_NOT /* verilator public_flat */ = 4'b0110;
localparam ALU_OP_XOR /* verilator public_flat */ = 4'b0111;
localparam ALU_OP_SHL /* verilator public_flat */ = 4'b1000;
localparam ALU_OP_SHR /* verilator public_flat */ = 4'b1001;
localparam ALU_OP_SAL /* verilator public_flat */ = 4'b1010;
localparam ALU_OP_SAR /* verilator public_flat */ = 4'b1011;
localparam ALU_OP_ROL /* verilator public_flat */ = 4'b1100;
localparam ALU_OP_ROR /* verilator public_flat */ = 4'b1101;
localparam ALU_OP_RCL /* verilator public_flat */ = 4'b1110;
localparam ALU_OP_RCR /* verilator public_flat */ = 4'b1111;
reg [8:0] tmp;
always @(posedge clk)
begin
case (operation)
ALU_OP_ADD :
tmp = A + B;
ALU_OP_SUB :
tmp = A - B;
ALU_OP_ADC :
tmp = A + B + { 7'b0000000, CF };
ALU_OP_SBC :
tmp = A - B - { 7'b0000000, CF };
ALU_OP_AND :
tmp = {1'b0, A & B };
ALU_OP_OR :
tmp = {1'b0, A | B };
ALU_OP_NOT :
tmp = {1'b0, ~B };
ALU_OP_XOR :
tmp = {1'b0, A ^ B};
ALU_OP_SHL :
tmp = { A[7], A[6:0], 1'b0};
ALU_OP_SHR :
tmp = { A[0], 1'b0, A[7:1]};
ALU_OP_SAL :
// Same as SHL
tmp = { A[7], A[6:0], 1'b0};
ALU_OP_SAR :
tmp = { A[0], A[7], A[7:1]};
ALU_OP_ROL :
tmp = { A[7], A[6:0], A[7]};
ALU_OP_ROR :
tmp = { A[0], A[0], A[7:1]};
ALU_OP_RCL :
tmp = { A[7], A[6:0], CF};
ALU_OP_RCR :
tmp = { A[0], CF, A[7:1]};
endcase
CF <= tmp[8];
ZF <= tmp[7:0] == 0;
SF <= tmp[7];
result <= tmp[7:0];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_4_V
`define SKY130_FD_SC_LS__AND4BB_4_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2000001; int N, M, cur, F, a[maxn], del[maxn]; int c[maxn]; inline int lowbit(int x) { return x & -x; } inline void add(int x, int d) { for (; x < maxn; x += lowbit(x)) { c[x] += d; } } inline int seek(int k) { int ans = 0, sum = 0; for (int i = 23; i >= 0; i--) { ans += 1 << i; if (ans > maxn || sum + c[ans] >= k) ans -= 1 << i; else sum += c[ans]; } return ans + 1; } int main() { scanf( %d%d , &M, &N); for (int i = 1; i <= N; ++i) { scanf( %d , &del[i]); } while (M--) { int d; scanf( %d , &d); if (d == -1) { int x = upper_bound(del + 1, del + N + 1, cur) - del; for (int i = x - 1; i > 0; --i) { cur--; int t = seek(del[i]); add(t, -1); a[t] = -1; } } else { cur++; add(++F, 1); a[F] = d; } } if (cur == 0) { printf( Poor stack! n ); } else { for (int i = 1; i <= cur; ++i) { printf( %d , a[seek(i)]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int N, M; int64_t K; cin >> N >> M >> K; vector<int> A(N); for (int i = 0; i < N; i++) cin >> A[i]; int64_t ret = 0; for (int m = 0; m < M; m++) { vector<int64_t> B(N); for (int i = 0; i < N; i++) { B[i] = A[i]; if (i % M == m) B[i] -= K; } if (!(m < N)) continue; int64_t x = B[m]; int64_t best = x; for (int i = m + 1; i < N; i++) { if (i % M == m && x < 0) x = B[i]; else x += B[i]; best = max(x, best); } ret = max(best, ret); } cout << ret << endl; return 0; }
|
`include "riscv_functions.vh"
module riscv_ex_pipe (
input clk,
input rstn,
input id_ex_rdy,
input [`EX_FUNCT_W-1:0] id_ex_funct,
input [31:0] id_ex_op1,
input [31:0] id_ex_op2,
input [`MEM_FUNCT_W-1:0] id_ex_mem_funct,
input [31:0] id_ex_mem_data,
input [4:0] id_ex_wb_rsd,
input [31:0] data_bif_rdata,
input data_bif_ack,
output [31:0] data_bif_addr,
output data_bif_req,
output data_bif_rnw,
output [3:0] data_bif_wmask,
output [31:0] data_bif_wdata,
output [31:0] wb_rf_data,
output [4:0] wb_rf_rsd,
output wb_rf_write
);
//Wires for pipeline
wire id_ex_ack;
wire ex_mem_rdy;
wire ex_mem_ack;
wire [31:0] ex_mem_result;
wire [`MEM_FUNCT_W-1:0] ex_mem_funct;
wire [31:0] ex_mem_data;
wire [4:0] ex_mem_wb_rsd;
wire mem_wb_rdy;
wire mem_wb_ack;
wire [`LD_FUNCT_W-1:0] mem_wb_funct;
wire [1:0] mem_wb_baddr;
wire [31:0] mem_wb_data;
wire [4:0] mem_wb_rsd;
riscv_ex i_riscv_ex (
.clk (clk),
.rstn (rstn),
.id_ex_rdy (id_ex_rdy),
.id_ex_ack (id_ex_ack),
.id_ex_funct (id_ex_funct),
.id_ex_op1 (id_ex_op1),
.id_ex_op2 (id_ex_op2),
.id_ex_mem_funct (id_ex_mem_funct),
.id_ex_mem_data (id_ex_mem_data),
.id_ex_wb_rsd (id_ex_wb_rsd),
.ex_mem_rdy (ex_mem_rdy),
.ex_mem_ack (ex_mem_ack),
.ex_mem_result (ex_mem_result),
.ex_mem_funct (ex_mem_funct),
.ex_mem_data (ex_mem_data),
.ex_mem_wb_rsd (ex_mem_wb_rsd)
);
riscv_mem i_riscv_mem (
.clk (clk),
.rstn (rstn),
.ex_mem_rdy (ex_mem_rdy),
.ex_mem_ack (ex_mem_ack),
.ex_mem_result (ex_mem_result),
.ex_mem_funct (ex_mem_funct),
.ex_mem_data (ex_mem_data),
.ex_mem_wb_rsd (ex_mem_wb_rsd),
.mem_wb_rdy (mem_wb_rdy),
.mem_wb_ack (mem_wb_ack),
.data_bif_addr (data_bif_addr),
.data_bif_req (data_bif_req),
.data_bif_rnw (data_bif_rnw),
.data_bif_wmask (data_bif_wmask),
.data_bif_wdata (data_bif_wdata),
.mem_wb_funct (mem_wb_funct),
.mem_wb_baddr (mem_wb_baddr),
.mem_wb_data (mem_wb_data),
.mem_wb_rsd (mem_wb_rsd)
);
riscv_wb i_riscv_wb (
.clk (clk),
.rstn (rstn),
.mem_wb_rdy (mem_wb_rdy),
.mem_wb_ack (mem_wb_ack),
.data_bif_rdata (data_bif_rdata),
.data_bif_ack (data_bif_ack),
.mem_wb_funct (mem_wb_funct),
.mem_wb_data (mem_wb_data),
.mem_wb_rsd (mem_wb_rsd),
.wb_rf_data (wb_rf_data),
.wb_rf_rsd (wb_rf_rsd),
.wb_rf_write (wb_rf_write)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int task; scanf( %d , &task); while (task--) { int n, p; scanf( %d%d , &n, &p); int rest(2 * n + p); for (int i = 1; (i <= n) && rest; i++) for (int j = i + 1; (j <= n) && rest; j++) printf( %d %d n , i, j), rest--; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, char c) { if (s.length() == 0) return vector<string>(); vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) { v.emplace_back(x); } return std::move(v); } vector<int> splitInt(const string& s, char c) { if (s.length() == 0) return vector<int>(); vector<int> v; stringstream ss(s); int x; string str; while (getline(ss, str, c)) { stringstream si(str); si >> x; v.emplace_back(x); } return std::move(v); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 0; cin >> t; while (t-- > 0) { int n; cin >> n; vector<int> arr(n, 0); for (int i = 0; i < n; ++i) cin >> arr[i]; vector<long long> seen(3001, 0); vector<vector<long long>> left(3001); for (int i = 0; i < n; ++i) { seen[arr[i]]++; left[i] = seen; } seen = vector<long long>(3001, 0); vector<vector<long long>> right(3001); for (int i = n - 1; i >= 0; --i) { seen[arr[i]]++; right[i] = seen; } long long count = 0; for (int j = 1; j < n; ++j) { for (int k = j + 1; k + 1 < n; ++k) { int aj = arr[j]; int ak = arr[k]; if (j - 1 >= 0 && k + 1 < n) { count += left[j - 1][ak] * right[k + 1][aj]; } } } cout << count << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O311A_PP_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
module bottleneck(
input [63:0] m_adr_i,
input m_cyc_i,
input [63:0] m_dat_i,
input m_signed_i,
input [1:0] m_siz_i,
input m_stb_i,
input m_we_i,
output m_ack_o,
output [63:0] m_dat_o,
output m_err_align_o,
output [63:0] s_adr_o,
output s_cyc_o,
output s_signed_o,
output s_siz_o,
output s_stb_o,
output s_we_o,
output [15:0] s_dat_o,
input s_ack_i,
input [15:0] s_dat_i,
input clk_i,
input reset_i
);
reg ack1, ack2, ack3;
wire ack1_o, ack2_o, ack3_o;
wire SWeO_MWeI;
wire SStbO_MStbI;
wire SStbO_1;
wire SSizO_MSizI0;
wire SSizO_1;
wire SSignedO_MSignedI;
wire SDatO_MDatI63_48;
wire SDatO_MDatI47_32;
wire SDatO_MDatI31_16;
wire SDatO_MDatI15_0;
wire plus6;
wire plus4;
wire plus2;
wire SAdrO_MAdrI;
wire MErrAlignO_1;
wire MDatO_SDatI;
wire MAckO_SAckI;
wire MAckO_1;
wire Hold3_SDatI;
wire Hold2_SDatI;
wire Hold1_SDatI;
wire reqByte = m_siz_i == 2'b00;
wire reqHWord = m_siz_i == 2'b01;
wire reqWord = m_siz_i == 2'b10;
wire reqDWord = m_siz_i == 2'b11;
assign s_cyc_o = m_cyc_i & ~MErrAlignO_1;
assign s_we_o = (SWeO_MWeI ? m_we_i : 0);
assign s_stb_o = (SStbO_MStbI ? m_stb_i : 0) | (SStbO_1 ? 1 : 0);
assign s_siz_o = (SSizO_MSizI0 ? m_siz_i[0] : 0) | (SSizO_1 ? 1 : 0);
assign s_signed_o = (SSignedO_MSignedI ? m_signed_i : 0);
assign s_dat_o =
((SDatO_MDatI63_48 ? m_dat_i[63:48] : 0) |
(SDatO_MDatI47_32 ? m_dat_i[47:32] : 0) |
(SDatO_MDatI31_16 ? m_dat_i[31:16] : 0) |
(SDatO_MDatI15_0 ? m_dat_i[15:0] : 0)) & (s_siz_o ? 16'hFFFF : 16'h00FF);
assign s_adr_o = (SAdrO_MAdrI ?
m_adr_i | ((plus2 ? 2 : 0) | (plus4 ? 4 : 0) | (plus6 ? 6 : 0))
: 0);
assign m_err_align_o = MErrAlignO_1;
reg [15:0] hold1, hold2, hold3;
wire [63:0] s_dat_8s = {{56{s_dat_i[7]}}, s_dat_i[7:0]};
wire [63:0] s_dat_8u = {56'd0, s_dat_i[7:0]};
wire [63:0] s_dat_16s = {{48{s_dat_i[15]}}, s_dat_i};
wire [63:0] s_dat_16u = {48'd0, s_dat_i};
wire [63:0] s_dat_32s = {{32{hold1[15]}}, hold1, s_dat_i};
wire [63:0] s_dat_32u = {32'd0, hold1, s_dat_i};
wire [63:0] s_dat_64 = {hold3, hold2, hold1, s_dat_i};
assign m_dat_o =
((MDatO_SDatI & m_signed_i & reqByte) ? s_dat_8s : 0) |
((MDatO_SDatI & ~m_signed_i & reqByte) ? s_dat_8u : 0) |
((MDatO_SDatI & m_signed_i & reqHWord) ? s_dat_16s : 0) |
((MDatO_SDatI & ~m_signed_i & reqHWord) ? s_dat_16u : 0) |
((MDatO_SDatI & m_signed_i & reqWord) ? s_dat_32s : 0) |
((MDatO_SDatI & ~m_signed_i & reqWord) ? s_dat_32u : 0) |
((MDatO_SDatI & reqDWord) ? s_dat_64 : 0);
assign m_ack_o = (MAckO_SAckI ? s_ack_i : 0) | (MAckO_1 ? 1 : 0);
BottleneckSequencer bs(
.SAckI(s_ack_i),
.ack3(ack3),
.ack2(ack2),
.ack1(ack1),
.MAdrI2(m_adr_i[2]),
.MAdrI1(m_adr_i[1]),
.MAdrI0(m_adr_i[0]),
.MSiz0(m_siz_i[0]),
.MSiz1(m_siz_i[1]),
.MStbI(m_stb_i),
.MCycI(m_cyc_i),
.ResetI(reset_i),
.SWeO_MWeI(SWeO_MWeI),
.SStbO_MStbI(SStbO_MStbI),
.SStbO_1(SStbO_1),
.SSizO_MSizI0(SSizO_MSizI0),
.SSizO_1(SSizO_1),
.SSignedO_MSignedI(SSignedO_MSignedI),
.SDatO_MDatI63_48(SDatO_MDatI63_48),
.SDatO_MDatI47_32(SDatO_MDatI47_32),
.SDatO_MDatI31_16(SDatO_MDatI31_16),
.SDatO_MDatI(SDatO_MDatI15_0),
.plus6(plus6),
.plus4(plus4),
.plus2(plus2),
.SAdrO_MAdrI(SAdrO_MAdrI),
.MErrAlignO_1(MErrAlignO_1),
.MDatO_SDatI(MDatO_SDatI),
.MAckO_SAckI(MAckO_SAckI),
.MAckO_1(MAckO_1),
.Hold3_SDatI(Hold3_SDatI),
.Hold2_SDatI(Hold2_SDatI),
.Hold1_SDatI(Hold1_SDatI),
.ack3_o(ack3_o),
.ack2_o(ack2_o),
.ack1_o(ack1_o)
);
always @(posedge clk_i) begin
ack1 <= ack1_o;
ack2 <= ack2_o;
ack3 <= ack3_o;
if(Hold1_SDatI) hold1 <= s_dat_i;
if(Hold2_SDatI) hold2 <= s_dat_i;
if(Hold3_SDatI) hold3 <= s_dat_i;
end
endmodule
|
//% @file sdm_adc_data_aurora_recv.v
//% @brief Receive external ADC and TMS_SDM data sent through aurora.
//% @author Yuan Mei
//%
//% The rate of ADC and TMS_SDM data words must be of fixed ratio relation.
//% @param[in] NCH_ADC total number of external ADC channels
//% @param[in] ADC_CYC # of CLK cycles per ADC data. Make sure this is an integer multiple of SDM_CYC.
//% @param[in] NCH_SDM total number of SDMs channels (each channel has 2 OUTs)
//% @param[in] SDM_CYC # of CLK cycles per SDM data
`timescale 1ns / 1ps
module sdm_adc_data_aurora_recv
#(
parameter NCH_ADC = 20,
parameter ADC_CYC = 20,
parameter NCH_SDM = 19,
parameter SDM_CYC = 4
)
(
input RESET,
input CLK,
input USER_CLK,
input [63:0] M_AXI_RX_TDATA,
input M_AXI_RX_TVALID,
output [511:0] DOUT,
output DOUT_VALID,
output reg FIFO_FULL
);
localparam ADC_SDM_CYC_RATIO = ADC_CYC / SDM_CYC;
localparam FIFO_DIN64_CYC = 9;
reg [ADC_SDM_CYC_RATIO*NCH_SDM*2 + NCH_ADC*16 - 1 : 0] sdm_adc_v;
reg sdm_adc_v_valid;
// aggregate data into sdm_adc_v
reg [3:0] cnt;
always @ (posedge USER_CLK or posedge RESET) begin
if (RESET) begin
sdm_adc_v <= 0;
sdm_adc_v_valid <= 0;
cnt <= 0;
end
else begin
sdm_adc_v_valid <= 0;
if (M_AXI_RX_TVALID) begin
cnt <= cnt + 1;
if (cnt >= FIFO_DIN64_CYC-1) begin
cnt <= 0;
end
sdm_adc_v[63*cnt +: 63] <= M_AXI_RX_TDATA[62:0];
if (M_AXI_RX_TDATA[63] == 1'b1) begin
cnt <= 0;
sdm_adc_v[63*cnt +: 6] <= M_AXI_RX_TDATA[5:0];
sdm_adc_v_valid <= 1;
end
end
end
end
assign DOUT[0 +: ADC_SDM_CYC_RATIO*NCH_SDM*2 + NCH_ADC*16] = sdm_adc_v;
assign DOUT[511 -: 2] = 2'b00;
assign DOUT_VALID = sdm_adc_v_valid;
endmodule // sdm_adc_data_aurora_recv
|
#include <bits/stdc++.h> using namespace std; int p[2005], c[2005]; int n, root = -1; vector<int> v[2005]; int d[2005], vis[2005]; int ans[2005]; struct cmp { bool operator()(int x, int y) { return d[x] > d[y]; } }; priority_queue<int, vector<int>, cmp> q; void dfs(int x) { if (c[x] == 0) q.push(x); for (auto y : v[x]) { if (vis[y]) continue; vis[y] = 1; d[y] = d[x] + 1; dfs(y); } } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> p[i] >> c[i]; if (!p[i]) { root = i; continue; } v[i].push_back(p[i]); v[p[i]].push_back(i); } vis[root] = 1; dfs(root); bool flag = true; int count = 1; while (!q.empty()) { int _top = q.top(); q.pop(); ans[_top] = count++; int head = p[_top]; while (head) { c[head]--; if (c[head] == 0) q.push(head); head = p[head]; } } for (int i = 1; i <= n; i++) { if (c[i] > 0) { flag = false; break; } } if (flag) { cout << YES << endl; for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; } else { cout << NO << endl; } return 0; }
|
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