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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: five_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module five_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/five_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/five_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/five_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long int mod(long long int x) { return (((x) % 1000000007) + 1000000007) % 1000000007; } long long int mod1(long long int x, long long int m) { return (((x) % m) + m) % m; } long long int solve() { string s; cin >> s; long long int d = count(s.begin(), s.end(), D ); long long int l = count(s.begin(), s.end(), L ); long long int u = count(s.begin(), s.end(), U ); long long int r = count(s.begin(), s.end(), R ); if (s.size() % 2 == 0) cout << (abs(d - u) + abs(l - r)) / 2; else cout << -1 ; return 0; } signed main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int t; t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; const int p = 257; const long long mods = 1610612741; const int maxn = 200010; long long hash1[maxn][2]; int cntzero[maxn]; char s[maxn]; int N; long long pp[maxn]; void gethash(char s[]) { hash1[0][0] = 0; hash1[0][1] = 0; for (int i = 1; i <= N; i++) { cntzero[i] = cntzero[i - 1]; if (s[i] == 0 ) { cntzero[i]++; hash1[i][0] = (hash1[i - 1][0] * p + (i & 1) + 1) % mods; hash1[i][1] = (hash1[i - 1][1] * p + ((i + 1) & 1) + 1) % mods; } else { hash1[i][0] = hash1[i - 1][0]; hash1[i][1] = hash1[i - 1][1]; } } return; } void init() { pp[0] = 1; for (int i = 1; i <= N; i++) { pp[i] = (pp[i - 1] * p) % mods; } } long long getsubhash(int L, int R) { return (hash1[R][L & 1] - (hash1[L - 1][L & 1] * pp[cntzero[R] - cntzero[L - 1]]) % mods + mods) % mods; } int main() { scanf( %d , &N); scanf( %s , s + 1); init(); gethash(s); int q; scanf( %d , &q); while (q--) { int l1, l2, lens; scanf( %d%d%d , &l1, &l2, &lens); if (getsubhash(l1, l1 + lens - 1) == getsubhash(l2, l2 + lens - 1)) printf( Yes n ); else printf( No n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; int lca[400100][20]; int len[400100]; long long s[400100][20]; int w[400100]; int main() { ios::sync_with_stdio(false); int Q; cin >> Q; int cnt = 0; int last = 0; len[0] = 1; for (long long q = 0; q < (long long)(Q); ++q) { int t, x; long long y; cin >> t >> x >> y; x ^= last; --x; y ^= last; if (t == 1) { ++cnt; w[cnt] = y; for (int i = 20 - 1; i >= 0; --i) { if (w[lca[x][i]] < y) { x = lca[x][i]; } } if (w[x] < y) { x = lca[x][0]; } if (w[x] < y) { x = cnt; } lca[cnt][0] = x; len[cnt] = len[x] + 1; s[cnt][0] = y; for (long long i = 0; i < (long long)(20 - 1); ++i) { lca[cnt][i + 1] = lca[lca[cnt][i]][i]; s[cnt][i + 1] = s[cnt][i] + s[lca[cnt][i]][i]; } } else { last = 0; int upp = len[x]; for (int i = 20 - 1; i >= 0; --i) { if (s[x][i] <= y) { y -= s[x][i]; x = lca[x][i]; last += 1 << i; } } last = min(last, upp); cout << last << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> deg(n), s(n); for (int i = 0; i < n; i++) cin >> deg[i] >> s[i]; vector<pair<int, int>> edges; queue<int> q; for (int i = 0; i < n; i++) if (deg[i] == 1) q.push(i); while (!q.empty()) { int leaf = q.front(); q.pop(); if (deg[leaf] != 1) continue; int par = s[leaf]; edges.push_back({par, leaf}); deg[par] -= 1; s[par] ^= leaf; if (deg[par] == 1) q.push(par); } cout << edges.size() << endl; for (auto p : edges) cout << p.first << << p.second << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_BEHAVIORAL_PP_V
|
//
// .. hwt-autodoc::
//
module FsmExample (
input wire a,
input wire b,
input wire clk,
output reg[2:0] dout,
input wire rst_n
);
reg[1:0] st = 0;
reg[1:0] st_next;
always @(st) begin: assig_process_dout
case(st)
0:
dout = 3'b001;
1:
dout = 3'b010;
default:
dout = 3'b011;
endcase
end
always @(posedge clk) begin: assig_process_st
if (rst_n == 1'b0)
st <= 0;
else
st <= st_next;
end
always @(a, b, st) begin: assig_process_st_next
case(st)
0:
if (a & b)
st_next = 2;
else if (b)
st_next = 1;
else
st_next = st;
1:
if (a & b)
st_next = 2;
else if (a)
st_next = 0;
else
st_next = st;
default:
if (a & ~b)
st_next = 0;
else if (~a & b)
st_next = 1;
else
st_next = st;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_2_V
`define SKY130_FD_SC_HD__DFBBN_2_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_2_V
|
#include <bits/stdc++.h> using namespace std; int Abs(int x) { if (x < 0) return -x; return x; } int N, M, K; bool no[2001][2001] = {false}, visited[2001] = {false}, rooted[2001] = {false}, notgo[2001]; vector<int> G[2001], g[2001]; int cn = 0; bool run = true; void dfs(int r) { if (!run) return; cn++; visited[r] = true; rooted[r] = true; for (int i = 0; i < g[r].size(); i++) { notgo[g[r][i]] = true; } for (int i = 0; i < G[r].size(); i++) { if (notgo[G[r][i]]) run = false; if (!visited[G[r][i]]) dfs(G[r][i]); } } int main() { scanf( %d , &N); scanf( %d , &M); for (int i = 0; i < M; i++) { int v, u; scanf( %d%d , &v, &u); G[v].push_back(u); G[u].push_back(v); } scanf( %d , &K); for (int i = 0; i < K; i++) { int v, u; scanf( %d%d , &v, &u); g[v].push_back(u); g[u].push_back(v); } int ans = 0; for (int i = 1; i <= N; i++) { cn = 0; run = true; memset(visited, false, sizeof(visited)); memset(notgo, false, sizeof(notgo)); dfs(i); if (run) ans = max(ans, cn); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, l; cin >> n >> l; vector<int> a(n, 0), b(n, 0); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; if (n == 1) cout << YES n ; else { vector<int> a_diff, b_diff, result; int check_sum = 0; for (int i = 1; i < n; ++i) { a_diff.push_back(a[i] - a[i - 1]); b_diff.push_back(b[i] - b[i - 1]); } a_diff.push_back(l - a[n - 1] + a[0]); b_diff.push_back(l - b[n - 1] + b[0]); for (int i = 0; i < n; ++i) a_diff.push_back(a_diff[i]); int i = 0, j = 0, prev_i = 0; while (i < 2 * n && j < n) { while (i < 2 * n && b_diff[0] != a_diff[i]) ++i; j = 0; prev_i = i; while (i < 2 * n && j < n && b_diff[j] == a_diff[i]) ++i, ++j; i = prev_i + 1; if (j == n) { cout << YES n ; return 0; } } cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long m; int soln[51]; long long mr = 0; int main() { cin >> n >> m; --m; for (int k = 1; k < n; ++k) { mr = mr * 2 + (m & 1); m >>= 1; } int i = 1, j = n; for (int k = 1; k <= n; ++k) { if (mr & 1) soln[j--] = k; else soln[i++] = k; mr >>= 1; } for (int k = 1; k <= n; ++k) cout << soln[k] << ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { int n, k, temp; cin >> n >> k; set<int> s; for (int i = 0; i < n; i++) { cin >> temp; s.insert(temp); } set<int>::reverse_iterator it; int count = 0; for (it = s.rbegin(); it != s.rend(); it++) { if ((*it - k * count) <= 0) break; count++; } cout << count << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int a, b, c, m; int flag = 0; int c1 = 0, c2 = 0, c3 = 0; int t; cin >> a >> b >> c >> m; t = 0; for (int i = min(c, m); i <= 2 * c && i <= 2 * m; i++) { if ((m <= i && 2 * m >= i) && (c <= i && 2 * c >= i)) { t = 1; c3 = i; break; } } if (t == 0) { flag = 1; } if (flag == 0) { t = 0; for (int i = b; i <= 2 * b; i++) { if ((m <= i) && (b <= i && 2 * b >= i) && i > c3 && (2 * m < i)) { t = 1; c2 = i; break; } } if (t == 0) { flag = 1; } } if (flag == 0) { t = 0; for (int i = a; i <= 2 * a; i++) { if ((m <= i) && (a <= i && 2 * a >= i) && i > c2 && (2 * m < i)) { t = 1; c1 = i; break; } } if (t == 0) { flag = 1; } } if (flag == 1) { cout << -1 n ; } else { cout << c1 << n << c2 << n << c3 << n ; } return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Transform_dq_to_ABC.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Transform_dq_to_ABC
// Source Path: velocityControlHdl/Transform_dq_to_ABC
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Transform_dq_to_ABC
(
d,
q,
sin,
cos,
ABC_0,
ABC_1,
ABC_2
);
input signed [17:0] d; // sfix18_En12
input signed [17:0] q; // sfix18_En12
input signed [17:0] sin; // sfix18_En16
input signed [17:0] cos; // sfix18_En16
output signed [17:0] ABC_0; // sfix18_En13
output signed [17:0] ABC_1; // sfix18_En13
output signed [17:0] ABC_2; // sfix18_En13
wire signed [17:0] Inverse_Park_Transform_out1; // sfix18_En10
wire signed [17:0] Inverse_Park_Transform_out2; // sfix18_En10
wire signed [17:0] Inverse_Clarke_Transform_out1_0; // sfix18_En13
wire signed [17:0] Inverse_Clarke_Transform_out1_1; // sfix18_En13
wire signed [17:0] Inverse_Clarke_Transform_out1_2; // sfix18_En13
// <S6>/Inverse_Park_Transform
velocityControlHdl_Inverse_Park_Transform u_Inverse_Park_Transform (.direct_voltage(d), // sfix18_En12
.quadrature_voltage(q), // sfix18_En12
.sin_coefficient(sin), // sfix18_En16
.cos_coefficient(cos), // sfix18_En16
.alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10
.beta_voltage(Inverse_Park_Transform_out2) // sfix18_En10
);
// <S6>/Inverse_Clarke_Transform
velocityControlHdl_Inverse_Clarke_Transform u_Inverse_Clarke_Transform (.alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10
.beta_voltage(Inverse_Park_Transform_out2), // sfix18_En10
.phase_voltages_0(Inverse_Clarke_Transform_out1_0), // sfix18_En13
.phase_voltages_1(Inverse_Clarke_Transform_out1_1), // sfix18_En13
.phase_voltages_2(Inverse_Clarke_Transform_out1_2) // sfix18_En13
);
assign ABC_0 = Inverse_Clarke_Transform_out1_0;
assign ABC_1 = Inverse_Clarke_Transform_out1_1;
assign ABC_2 = Inverse_Clarke_Transform_out1_2;
endmodule // velocityControlHdl_Transform_dq_to_ABC
|
#include <bits/stdc++.h> using namespace std; template <typename T> T BigMod(T b, T p, T m) { if (p == 0) return 1; if (p % 2 == 0) { T s = BigMod(b, p / 2, m); return ((s % m) * (s % m)) % m; } return ((b % m) * (BigMod(b, p - 1, m) % m)) % m; } template <typename T> T ModInv(T b, T m) { return BigMod(b, m - 2, m); } template <typename T> T in() { char ch; T n = 0; bool ng = false; while (1) { ch = getchar(); if (ch == - ) { ng = true; ch = getchar(); break; } if (ch >= 0 && ch <= 9 ) break; } while (1) { n = n * 10 + (ch - 0 ); ch = getchar(); if (ch < 0 || ch > 9 ) break; } return (ng ? -n : n); } template <typename T> T POW(T B, T printf) { if (printf == 0) return 1; if (printf & 1) return B * POW(B, printf - 1); else return (POW(B, printf / 2) * POW(B, printf / 2)); } template <typename T> T Bigmod(T b, T p, T m) { if (p == 0) return 1; else if (!(p & 1)) return (Bigmod(b, p / 2, m) * Bigmod(b, p / 2, m)) % m; else return ((b % m) * Bigmod(b, p - 1, m)) % m; } template <typename T> T Dis(T x1, T y1, T x2, T y2) { return sqrt((x1 - x2 * x1 - x2) + (y1 - y2 * y1 - y2)); } template <typename T> T Angle(T x1, T y1, T x2, T y2) { return atan(double(y1 - y2) / double(x1 - x2)); } template <typename T> T DIFF(T a, T b) { T d = a - b; if (d < 0) return -d; else return d; } template <typename T> T ABS(T a) { if (a < 0) return -a; else return a; } template <typename T> T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <typename T> T euclide(T a, T b, T &x, T &y) { if (a < 0) { T d = euclide(-a, b, x, y); x = -x; return d; } if (b < 0) { T d = euclide(a, -b, x, y); y = -y; return d; } if (b == 0) { x = 1; y = 0; return a; } else { T d = euclide(b, a % b, x, y); T t = x; x = y; y = t - (a / b) * y; return d; } } template <typename T> void ia(T a[], int n) { for (int i = 0; i < n; i++) cin >> a[i]; } template <typename T> void pa(T a[], int n) { for (int i = 0; i < n - 1; i++) cout << a[i] << ; cout << a[n - 1] << endl; } template <typename T> long long int isLeft(T a, T b, T c) { return (a.x - b.x) * (b.y - c.y) - (b.x - c.x) * (a.y - b.y); } int Set(int N, int pos) { return N = N | (1 << pos); } int Reset(int N, int pos) { return N = N & ~(1 << pos); } bool Check(int N, int pos) { return (bool)(N & (1 << pos)); } template <class T, class first> inline T togglebit(T a, first i) { T t = 1; return (a ^ (t << i)); } int toInt(string s) { int sm; stringstream ss(s); ss >> sm; return sm; } int toLlint(string s) { long long int sm; stringstream ss(s); ss >> sm; return sm; } int cdigittoint(char ch) { return ch - 0 ; } bool isVowel(char ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } bool isConst(char ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } double DEG(double x) { return (180.0 * x) / (2.0 * acos(0.0)); } double RAD(double x) { return (x * (double)2.0 * acos(0.0)) / (180.0); } int a[507][507]; int main() { int n, k; scanf( %d%d , &n, &k); int v = n * n; for (int i = 1; i <= n; i++) { for (int j = n; j >= k; j--) { a[i][j] = v--; } } for (int i = 1; i <= n; i++) { for (int j = k - 1; j; j--) a[i][j] = v--; } long long int ans = 0; for (int i = 1; i <= n; i++) ans += a[i][k]; cout << ans << endl; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) cout << a[i][j] << ; printf( n ); ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, ind, sum = 0; cin >> n; long long mas[n]; for (long long i = 0; i < n; i++) { cin >> mas[i]; sum += mas[i]; } cin >> m; long long arr[m]; sort(mas, mas + n); for (long long i = 0; i < m; i++) { cin >> arr[i]; cout << sum - mas[n - arr[i]] << endl; } return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_pio_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 255;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long x, y, z; scanf( %d , &n); for (int i = 1; i <= n; i++) { long long ans = 0; scanf( %lld%lld , &x, &y); if (x >= y) { ans += y; printf( %lld n , ans); continue; } long long d = (y - 1) / x + 1; z = x * d - y; ans += z * (d - 1) * (d - 1) + (x - z) * d * d; printf( %lld n , ans); } }
|
#include <bits/stdc++.h> using namespace std; int n; int s[220]; int d[220]; int sol[220]; vector<pair<int, int> > v; int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; cin >> n; for (int(i) = (0); (i) < (n); (i)++) cin >> s[i] >> d[i]; for (int(i) = (0); (i) < (n); (i)++) { int last = 1; int ok = 0; for (typeof(v.begin()) it = (v.begin()); it != v.end(); it++) { if (last <= s[i] && it->first >= s[i] + d[i]) { v.insert(it, make_pair((s[i]), (d[i]))); ok = 1; sol[i] = s[i]; break; } last = it->first + it->second; } if (v.empty() || v[((int)v.size()) - 1].first + v[((int)v.size()) - 1].second <= s[i]) { v.push_back(make_pair((s[i]), (d[i]))); ok = 1; sol[i] = s[i]; } if (!ok) { last = 1; for (typeof(v.begin()) it = (v.begin()); it != v.end(); it++) { if (it->first >= last + d[i]) { v.insert(it, make_pair((last), (d[i]))); sol[i] = last; ok = 1; break; } last = it->first + it->second; } } if (!ok) { v.push_back(make_pair((last), (d[i]))); sol[i] = last; } cout << sol[i] << << sol[i] + d[i] - 1 << endl; } return 0; }
|
/*
File: ewrapper_link_receiver.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_link_receiver (/*AUTOARG*/
// Outputs
rxi_wr_wait, rxi_rd_wait, emesh_clk_inb, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
// Inputs
reset, rxi_data, rxi_lclk, rxi_frame, emesh_wr_wait_outb,
emesh_rd_wait_outb
);
//#########
//# INPUTS
//#########
input reset; //reset input
//# From the lvds-serdes
input [63:0] rxi_data; //Eight Parallel Byte words
input rxi_lclk; //receive clock (synchronized to the data)
input [7:0] rxi_frame; //Parallel frame signals representing
// 4 transmission clock cycles
//# From the emesh interface
input emesh_wr_wait_outb;
input emesh_rd_wait_outb;
//##########
//# OUTPUTS
//##########
//# To the transmitter
output rxi_wr_wait; //wait indicator
output rxi_rd_wait; //wait indicator
//# To the emesh interface
output emesh_clk_inb;
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Wires
//#########
wire emesh_wr_access_inb;
wire emesh_wr_write_inb;
wire [1:0] emesh_wr_datamode_inb;
wire [3:0] emesh_wr_ctrlmode_inb;
wire [31:0] emesh_wr_dstaddr_inb;
wire [31:0] emesh_wr_srcaddr_inb;
wire [31:0] emesh_wr_data_inb;
wire emesh_rd_access_inb;
wire emesh_rd_write_inb;
wire [1:0] emesh_rd_datamode_inb;
wire [3:0] emesh_rd_ctrlmode_inb;
wire [31:0] emesh_rd_dstaddr_inb;
wire [31:0] emesh_rd_srcaddr_inb;
wire [31:0] emesh_rd_data_inb;
wire select_write_tran;
wire wr_wait;
wire rd_wait;
wire emesh_access_tmp;
//###############
//# Emesh clock
//###############
assign emesh_clk_inb = rxi_lclk;
//######################################
//# Write-Read Transactions Arbitration
//# Write has a higher priority ALWAYS
//######################################
assign select_write_tran = emesh_wr_access_inb & ~emesh_wr_wait_outb;
assign emesh_access_inb = emesh_access_tmp & ~emesh_wr_wait_outb;
assign wr_wait = emesh_wr_wait_outb;
assign rd_wait = emesh_rd_access_inb & select_write_tran |
(emesh_wr_wait_outb | emesh_rd_wait_outb);
assign emesh_srcaddr_inb[31:0] =
select_write_tran ? emesh_wr_srcaddr_inb[31:0] :
emesh_rd_srcaddr_inb[31:0];
assign emesh_dstaddr_inb[31:0] =
select_write_tran ? emesh_wr_dstaddr_inb[31:0] :
emesh_rd_dstaddr_inb[31:0];
assign emesh_datamode_inb[1:0] =
select_write_tran ? emesh_wr_datamode_inb[1:0] :
emesh_rd_datamode_inb[1:0];
assign emesh_ctrlmode_inb[3:0] =
select_write_tran ? emesh_wr_ctrlmode_inb[3:0] :
emesh_rd_ctrlmode_inb[3:0];
assign emesh_data_inb[31:0] = select_write_tran ? emesh_wr_data_inb[31:0] :
emesh_rd_data_inb[31:0];
assign emesh_access_tmp = select_write_tran ? emesh_wr_access_inb :
emesh_rd_access_inb;
assign emesh_write_inb = select_write_tran ? emesh_wr_write_inb :
emesh_rd_write_inb;
//############################################
//# Write Transactions Receiver Instantiation
//############################################
/*ewrapper_link_rxi AUTO_TEMPLATE(
.rxi_rd (1'b0),
.emesh_wait_outb (wr_wait),
.rxi_wait (rxi_wr_wait),
.emesh_\(.*\) (emesh_wr_\1[]),
);
*/
ewrapper_link_rxi wr_rxi(/*AUTOINST*/
// Outputs
.rxi_wait (rxi_wr_wait), // Templated
.emesh_access_inb (emesh_wr_access_inb), // Templated
.emesh_write_inb (emesh_wr_write_inb), // Templated
.emesh_datamode_inb (emesh_wr_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emesh_wr_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
// Inputs
.reset (reset),
.rxi_data (rxi_data[63:0]),
.rxi_lclk (rxi_lclk),
.rxi_frame (rxi_frame[7:0]),
.emesh_wait_outb (wr_wait), // Templated
.rxi_rd (1'b0)); // Templated
//############################################
//# Read Transactions Receiver Instantiation
//############################################
/*ewrapper_link_rxi AUTO_TEMPLATE(
.rxi_rd (1'b1),
.emesh_wait_outb (rd_wait),
.rxi_wait (rxi_rd_wait),
.emesh_\(.*\) (emesh_rd_\1[]),
);
*/
ewrapper_link_rxi rd_rxi(/*AUTOINST*/
// Outputs
.rxi_wait (rxi_rd_wait), // Templated
.emesh_access_inb (emesh_rd_access_inb), // Templated
.emesh_write_inb (emesh_rd_write_inb), // Templated
.emesh_datamode_inb (emesh_rd_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emesh_rd_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
// Inputs
.reset (reset),
.rxi_data (rxi_data[63:0]),
.rxi_lclk (rxi_lclk),
.rxi_frame (rxi_frame[7:0]),
.emesh_wait_outb (rd_wait), // Templated
.rxi_rd (1'b1)); // Templated
endmodule // ewrapper_link_receiver
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long N = 1e6 + 5; const long long inf = 1e18; long long powermod(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; loop: while (t--) { long long n; cin >> n; long long x = n / 4; if (n % 4 != 0) x++; n -= x; while (n--) { cout << 9; } while (x--) cout << 8; cout << n ; } return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_edge_detection_gaussian_smoothing_filter (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 8: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 7: 0] shift_reg_out[ 3: 0];
// Internal Registers
reg [ 7: 0] original_line_1[ 4: 0];
reg [ 7: 0] original_line_2[ 4: 0];
reg [ 7: 0] original_line_3[ 4: 0];
reg [ 7: 0] original_line_4[ 4: 0];
reg [ 7: 0] original_line_5[ 4: 0];
reg [15: 0] sum_level_1[12: 0];
reg [15: 0] sum_level_2[ 6: 0];
reg [15: 0] sum_level_3[ 4: 0];
reg [15: 0] sum_level_4[ 2: 0];
reg [15: 0] sum_level_5[ 1: 0];
reg [15: 0] sum_level_6;
reg [ 8: 0] sum_level_7;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Gaussian Smoothing Filter
//
// [ 2 4 5 4 2 ]
// [ 4 9 12 9 4 ]
// 1 / 115 [ 5 12 15 12 5 ]
// [ 4 9 12 9 4 ]
// [ 2 4 5 4 2 ]
//
always @(posedge clk)
begin
if (reset == 1'b1)
begin
for (i = 4; i >= 0; i = i-1)
begin
original_line_1[i] <= 8'h00;
original_line_2[i] <= 8'h00;
original_line_3[i] <= 8'h00;
original_line_4[i] <= 8'h00;
original_line_5[i] <= 8'h00;
end
for (i = 12; i >= 0; i = i-1)
begin
sum_level_1[i] <= 16'h0000;
end
for (i = 6; i >= 0; i = i-1)
begin
sum_level_2[i] <= 16'h0000;
end
for (i = 4; i >= 0; i = i-1)
begin
sum_level_3[i] <= 16'h0000;
end
sum_level_4[0] <= 16'h0000;
sum_level_4[1] <= 16'h0000;
sum_level_4[2] <= 16'h0000;
sum_level_5[0] <= 16'h0000;
sum_level_5[1] <= 16'h0000;
sum_level_6 <= 16'h0000;
sum_level_7 <= 9'h000;
end
else if (data_en == 1'b1)
begin
for (i = 4; i > 0; i = i-1)
begin
original_line_1[i] <= original_line_1[i-1];
original_line_2[i] <= original_line_2[i-1];
original_line_3[i] <= original_line_3[i-1];
original_line_4[i] <= original_line_4[i-1];
original_line_5[i] <= original_line_5[i-1];
end
original_line_1[0] <= data_in;
original_line_2[0] <= shift_reg_out[0];
original_line_3[0] <= shift_reg_out[1];
original_line_4[0] <= shift_reg_out[2];
original_line_5[0] <= shift_reg_out[3];
// Add numbers that are multiplied by 2 and multiply by 2
sum_level_1[ 0] <= {7'h00,original_line_1[0], 1'b0} + {7'h00,original_line_1[4], 1'b0};
sum_level_1[ 1] <= {7'h00,original_line_5[0], 1'b0} + {7'h00,original_line_5[4], 1'b0};
// Add numbers that are multiplied by 4 and multiply by 4
sum_level_1[ 2] <= {6'h00,original_line_1[1], 2'h0} + {6'h00,original_line_1[3], 2'h0};
sum_level_1[ 3] <= {6'h00,original_line_2[0], 2'h0} + {6'h00,original_line_2[4], 2'h0};
sum_level_1[ 4] <= {6'h00,original_line_4[0], 2'h0} + {6'h00,original_line_4[4], 2'h0};
sum_level_1[ 5] <= {6'h00,original_line_5[1], 2'h0} + {6'h00,original_line_5[3], 2'h0};
// Add numbers that are multiplied by 5
sum_level_1[ 6] <= {8'h00,original_line_1[2]} + {8'h00,original_line_5[2]};
sum_level_1[ 7] <= {8'h00,original_line_3[0]} + {8'h00,original_line_3[4]};
// Add numbers that are multiplied by 9
sum_level_1[ 8] <= {8'h00,original_line_2[1]} + {8'h00,original_line_2[3]};
sum_level_1[ 9] <= {8'h00,original_line_4[1]} + {8'h00,original_line_4[3]};
// Add numbers that are multiplied by 12
sum_level_1[10] <= {8'h00,original_line_2[2]} + {8'h00,original_line_4[2]};
sum_level_1[11] <= {8'h00,original_line_3[1]} + {8'h00,original_line_3[3]};
// Add numbers that are multiplied by 15
sum_level_1[12] <= {4'h0,original_line_3[2], 4'h0} - original_line_3[2];
// Add numbers that are multiplied by 2
sum_level_2[ 0] <= sum_level_1[ 0] + sum_level_1[ 1];
// Add numbers that are multiplied by 4
sum_level_2[ 1] <= sum_level_1[ 2] + sum_level_1[ 3];
sum_level_2[ 2] <= sum_level_1[ 4] + sum_level_1[ 5];
// Add numbers that are multiplied by 5
sum_level_2[ 3] <= sum_level_1[ 6] + sum_level_1[ 7];
// Add numbers that are multiplied by 9
sum_level_2[ 4] <= sum_level_1[ 8] + sum_level_1[ 9];
// Add numbers that are multiplied by 12
sum_level_2[ 5] <= sum_level_1[10] + sum_level_1[11];
// Multiplied by 15
sum_level_2[ 6] <= sum_level_1[12];
// Add 2s and 15s
sum_level_3[ 0] <= sum_level_2[ 0] + sum_level_2[ 6];
// Add numbers that are multiplied by 4
sum_level_3[ 1] <= sum_level_2[ 1] + sum_level_2[ 2];
// Multiplied by 5
sum_level_3[ 2] <= {sum_level_2[ 3], 2'h0} + sum_level_2[ 3];
// Multiplied by 9
sum_level_3[ 3] <= {sum_level_2[ 4], 3'h0} + sum_level_2[ 4];
// Multiplied by 12
sum_level_3[ 4] <= {sum_level_2[ 5], 3'h0} + {sum_level_2[ 5], 2'h0};
// Add
sum_level_4[ 0] <= sum_level_3[ 0] + sum_level_3[ 1];
sum_level_4[ 1] <= sum_level_3[ 2] + sum_level_3[ 3];
sum_level_4[ 2] <= sum_level_3[ 4];
sum_level_5[ 0] <= sum_level_4[ 0] + sum_level_4[ 1];
sum_level_5[ 1] <= sum_level_4[ 2];
sum_level_6 <= sum_level_5[ 0] + sum_level_5[ 1];
// Divide by 128, which is close enough to 115
sum_level_7 <= sum_level_6[15:7];
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign data_out = sum_level_7;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_in),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 8,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 8,
shift_register_2.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_3 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[1]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[2]),
.taps ()
);
defparam
shift_register_3.DW = 8,
shift_register_3.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_4 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[2]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[3]),
.taps ()
);
defparam
shift_register_4.DW = 8,
shift_register_4.SIZE = WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int h, w, r; } edge[110]; bool vis[11]; int x[5000000]; int n, k, t; void init() { cin >> n >> k >> t; for (int i = 1; i <= k; i++) cin >> edge[i].h >> edge[i].w >> edge[i].r; } void solve() { int l = 0; for (int j = 1; j <= (1 << k) - 1; j++) { int t = 0; for (int i = 1; i <= k; i++) if ((j & (1 << (i - 1))) != 0) t++; if (t > n) continue; memset(vis, 0, sizeof(vis)); int s = 0; bool flag = true; for (int i = 1; i <= k; i++) if ((j & (1 << (i - 1))) != 0) { if (vis[edge[i].h] || vis[edge[i].w + n]) { flag = false; break; } vis[edge[i].h] = vis[edge[i].w + n] = true; s += edge[i].r; } if (flag) x[++l] = s; } sort(x, x + l + 1); cout << x[t - 1] << endl; } int main() { ios::sync_with_stdio(false); init(); solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double n, a, d, t, v; cin >> n >> a >> d; double minitime = 0; for (int i = 0; i < n; i++) { cin >> t >> v; double t1 = v / a; double s = a * 0.5 * t1 * t1; if (s > d) { t += sqrt(2 * d / a); } else { double x = d - s; double t2 = x / v; t += t1 + t2; } t = max(minitime, t); minitime = t; cout << t << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; while (cin >> n) { string x; cin >> x; long long c = 0; long long arr[n + 5]; memset(arr, 0, sizeof(arr)); for (long long i = 0; i < n; i++) { if (x[i] == < ) { if ((i - 1) < 0 || arr[i - 1] == 1) arr[i] = 1; } else if (x[i] == > ) { long long lft = i; while (i < n && x[i] == > ) i++; if (i >= n) { long long rgt = i; c += (rgt - lft); } else i--; } } for (long long i = 0; i < n; i++) if (arr[i] == 1) c++; cout << c << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2000 + 11; const int MOD = 1e9 + 7; int dp[N][2][2][N]; int m, d; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> m >> d; string s1, s2; cin >> s1 >> s2; s1 = . + s1; s2 = . + s2; dp[0][0][0][0] = 1; int n = s1.size() - 1; for (int i = 1; i <= n; i++) for (int d1 = 0; d1 <= 1; d1++) for (int d2 = 0; d2 <= 1; d2++) for (int mm = 0; mm < m; mm++) { for (int x = 0; x <= 9; x++) { if (d1 == 0 && x < s1[i] - 0 ) continue; if (d2 == 0 && x > s2[i] - 0 ) continue; if (i % 2 == 1 && x == d) continue; if (i % 2 == 0 && x != d) continue; int dd1 = d1, dd2 = d2, mmm = (mm * 10 + x) % m; if (x > s1[i] - 0 ) dd1 = 1; if (x < s2[i] - 0 ) dd2 = 1; dp[i][dd1][dd2][mmm] = (dp[i][dd1][dd2][mmm] + dp[i - 1][d1][d2][mm]) % MOD; } } int ans = 0; for (int d1 = 0; d1 <= 1; d1++) for (int d2 = 0; d2 <= 1; d2++) ans = (ans + dp[n][d1][d2][0]) % MOD; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int N = 10000000; bool f[N] = {1, 1}; long long p, q, rub, primepi, res; long long rev(long long x) { long long res; for (res = 0; x; x /= 10) { res = res * 10 + x % 10; } return res; } int main() { cin >> p >> q; for (long long i = 1; i < N; ++i) { if (!f[i]) { primepi++; for (long long j = i * i; j < N; j += i) f[j] = 1; } if (rev(i) == i) rub++; if (q * primepi <= p * rub) res = i; } cout << res; return 0; }
|
#include <bits/stdc++.h> int const N = 1100; int n, m, ans, ans1; int map[N][N]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) map[i][j] = -1; for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); for (int j = 1; j <= x; ++j) if (map[i][j] != 0) map[i][j] = 1; else { printf( %d n , 0); return 0; } if (map[i][x + 1] == 1) { printf( %d n , 0); return 0; } map[i][x + 1] = 0; } for (int i = 1; i <= m; ++i) { int x; scanf( %d , &x); for (int j = 1; j <= x; ++j) if (map[j][i] != 0) map[j][i] = 1; else { printf( %d n , 0); return 0; } if (map[x + 1][i] == 1) { printf( %d n , 0); return 0; } map[x + 1][i] = 0; } ans = 0; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (map[i][j] == -1) ans++; ans1 = 1; for (int i = 1; i <= ans; ++i) ans1 = (ans1 * 2) % 1000000007; printf( %d n , ans1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int chk[300004][3]; int visit[300004]; vector<int> vec[300004]; vector<pair<int, int>> vecp; void dfs(int x) { visit[x] = 1; for (int i = 0; i < vec[x].size(); i++) { if (visit[vec[x][i]] == 0) { dfs(vec[x][i]); chk[x][0] += chk[vec[x][i]][0]; chk[x][1] += chk[vec[x][i]][1]; chk[x][2] += chk[vec[x][i]][2]; vecp.push_back({chk[vec[x][i]][1], chk[vec[x][i]][2]}); } } } int main() { int a, b, c, d, e, m = 0; cin >> a; int r = 0, bl = 0; for (int i = 1; i <= a; i++) { cin >> b; if (b == 1) r++; else if (b == 2) bl++; chk[i][b]++; } for (int i = 1; i < a; i++) { cin >> b >> c; vec[b].push_back(c); vec[c].push_back(b); } dfs(1); for (int i = 0; i < vecp.size(); i++) { int red = vecp[i].first; int blue = vecp[i].second; int redo = r - red; int blueo = bl - blue; if (red >= 1 && blue == 0 && blueo >= 1 && redo == 0) { m++; } else if (red == 0 && blue >= 1 && blueo == 0 && redo >= 1) { m++; } } cout << m << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m, k; cin >> n >> m >> k; map<long long, long long> cnt1, cnt2; vector<long long> a(n), b(m); for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < m; i++) { cin >> b[i]; } long long run = 0; for (long long i = 0; i < n; i++) { if (a[i] == 0) { if (run) { cnt1[run]++; run = 0; } } else { run++; } } if (run) { cnt1[run]++; } run = 0; for (long long i = 0; i < m; i++) { if (b[i] == 0) { if (run) { cnt2[run]++; run = 0; } } else { run++; } } if (run) { cnt2[run]++; } long long ans = 0; for (long long i = 1; i * i <= k; i++) { if (k % i == 0) { long long j = k / i; auto it1 = cnt1.lower_bound(i); auto it2 = cnt2.lower_bound(j); while (it1 != cnt1.end()) { auto it3 = it2; long long x = (it1->first - i + 1) * it1->second; while (it3 != cnt2.end()) { long long y = (it3->first - j + 1) * it3->second; ans += x * y; it3++; } it1++; } if (i != j) { it1 = cnt1.lower_bound(j); it2 = cnt2.lower_bound(i); while (it1 != cnt1.end()) { auto it3 = it2; long long x = (it1->first - j + 1) * it1->second; while (it3 != cnt2.end()) { long long y = (it3->first - i + 1) * it3->second; ans += x * y; it3++; } it1++; } } } } cout << ans; return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_usr_top.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Mon Aug 28 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module interfaces with the user. The user should provide the data
// and various commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_usr_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter CS_BITS = 0,
parameter COL_WIDTH = 10,
parameter DQ_WIDTH = 72,
parameter DQ_PER_DQS = 8,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter DQS_WIDTH = 9,
parameter ROW_WIDTH = 14
)
(
input clk0,
input clk90,
input rst0,
input [DQ_WIDTH-1:0] rd_data_in_rise,
input [DQ_WIDTH-1:0] rd_data_in_fall,
input [DQS_WIDTH-1:0] phy_calib_rden,
input [DQS_WIDTH-1:0] phy_calib_rden_sel,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input ctrl_af_rden,
output [2:0] af_cmd,
output [30:0] af_addr,
output af_empty,
output app_af_afull,
output [1:0] rd_ecc_error,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
input wdf_rden,
output app_wdf_afull,
output [(2*DQ_WIDTH)-1:0] wdf_data,
output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data
);
wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_fall;
wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_rise;
//***************************************************************************
assign rd_data_fifo_out = {i_rd_data_fifo_out_fall,
i_rd_data_fifo_out_rise};
// read data de-skew and ECC calculation
ddr2_usr_rd #
(
.DQ_PER_DQS (DQ_PER_DQS),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH),
.DQS_WIDTH (DQS_WIDTH)
)
u_usr_rd
(
.clk0 (clk0),
.rst0 (rst0),
.rd_data_in_rise (rd_data_in_rise),
.rd_data_in_fall (rd_data_in_fall),
.rd_ecc_error (rd_ecc_error),
.ctrl_rden (phy_calib_rden),
.ctrl_rden_sel (phy_calib_rden_sel),
.rd_data_valid (rd_data_valid),
.rd_data_out_rise (i_rd_data_fifo_out_rise),
.rd_data_out_fall (i_rd_data_fifo_out_fall)
);
// Command/Addres FIFO
ddr2_usr_addr_fifo #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_addr_fifo
(
.clk0 (clk0),
.rst0 (rst0),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.ctrl_af_rden (ctrl_af_rden),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.app_af_afull (app_af_afull)
);
ddr2_usr_wr #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_wr
(
.clk0 (clk0),
.clk90 (clk90),
.rst0 (rst0),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.wdf_rden (wdf_rden),
.app_wdf_afull (app_wdf_afull),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 301; int i, j, l, r, k, x, y, z, t, tot; int f[N][26], sum[N], p[N], q[N]; long long A[N][N], E[N][N], tmp[N][N]; long long n, m, a[N], INF, ans; char s[N]; void build(int value) { int x = 0, t; for (int i = 0; i < strlen(s); i++) { t = s[i] - a ; if (!f[x][t]) f[x][t] = ++tot; x = f[x][t]; } sum[x] += value; } void init() { cin >> n >> m; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) { cin >> s; build(a[i]); } } void Ac() { int l = 0, r = 0; for (i = 0; i < 26; i++) if (f[0][i]) q[++r] = f[0][i]; while (l != r) { l++; x = q[l]; for (i = 0; i < 26; i++) if (f[x][i]) { q[++r] = f[x][i]; y = p[x]; while (!f[y][i] && y) y = p[y]; if (f[y][i]) y = f[y][i]; p[f[x][i]] = y; sum[f[x][i]] += sum[y]; } } } void cal(long long c[][N], long long a[][N], long long b[][N]) { int i, j, k; for (i = 0; i <= tot; i++) for (j = 0; j <= tot; j++) tmp[i][j] = INF; for (i = 0; i <= tot; i++) for (j = 0; j <= tot; j++) for (k = 0; k <= tot; k++) if (a[i][k] + b[k][j] > tmp[i][j]) tmp[i][j] = a[i][k] + b[k][j]; for (i = 0; i <= tot; i++) for (j = 0; j <= tot; j++) c[i][j] = tmp[i][j]; } void pr(long long a[][N]) { for (i = 0; i <= tot; i++) { for (j = 0; j <= tot; j++) if (a[i][j] > INF / 2) cout << a[i][j] << ; else cout << * ; printf( n ); } printf( n ); } void Matrix() { INF = 1LL << 60; INF *= -1; for (i = 0; i <= tot; i++) for (j = 0; j <= tot; j++) A[i][j] = E[i][j] = INF; for (i = 0; i <= tot; i++) E[i][i] = 0; for (i = 0; i <= tot; i++) for (j = 0; j < 26; j++) { y = i; while (y && !f[y][j]) y = p[y]; if (f[y][j]) y = f[y][j]; A[i][y] = sum[y]; } while (m) { if (m % 2) cal(E, E, A); cal(A, A, A); m /= 2; } ans = E[0][0]; for (i = 1; i <= tot; i++) ans = max(ans, E[0][i]); cout << ans; } int main() { init(); Ac(); Matrix(); }
|
module dff0_test(n1, n1_inv, clk);
input clk;
output n1;
reg n1 = 32'd0;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff1_test(n1, n1_inv, clk);
input clk;
(* init = 32'd1 *)
output n1;
reg n1 = 32'd1;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff0a_test(n1, n1_inv, clk);
input clk;
(* init = 32'd0 *) // Must be consistent with reg initialiser below
output n1;
reg n1 = 32'd0;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff1a_test(n1, n1_inv, clk);
input clk;
(* init = 32'd1 *) // Must be consistent with reg initialiser below
output n1;
reg n1 = 32'd1;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff_test_997 (y, clk, wire4);
// https://github.com/YosysHQ/yosys/issues/997
output wire [1:0] y;
input clk;
input signed wire4;
reg [1:0] reg10 = 0;
always @(posedge clk) begin
reg10 <= wire4;
end
assign y = reg10;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; int vis[maxn], p[maxn]; int plen; void prime() { memset(vis, 0, sizeof(vis)); plen = 0; for (int i = 2, k = 4; i < maxn; ++i, k += i + i - 1) { if (!vis[i]) { p[plen++] = i; if (k < maxn) { for (int j = k; j < maxn; j += i) { vis[j] = 1; } } } } } struct node { int id; int cnt; int color; } need[maxn]; bool cmp(const node &a, const node &b) { return a.cnt > b.cnt; } bool cmp1(const node &a, const node &b) { return a.id < b.id; } char buf[maxn], out[maxn]; int cnt[maxn]; int main(int argc, char *argv[]) { prime(); while (scanf( %s , buf) != EOF) { memset(vis, -1, sizeof(vis)); memset(cnt, 0, sizeof(cnt)); int len = strlen(buf); for (int i = 0; i < len; i++) { cnt[buf[i] - a ]++; } int colornum = 0; for (int i = 0; i < plen && p[i] <= len; i++) { int color = -1; for (int j = 1; j <= len / p[i]; j++) { if (vis[j * p[i]] != -1) { color = vis[j]; break; } } if (color == -1) { color = colornum++; } for (int j = 1; j <= len / p[i]; j++) { vis[j * p[i]] = color; } } for (int i = 0; i < maxn; i++) { need[i].id = i; need[i].cnt = 0; } for (int i = 2; i <= len; i++) { need[vis[i]].cnt++; } sort(need, need + colornum, cmp); int flag = 0; for (int i = 0; i < colornum; i++) { int maxcolor = 0, k = -1; for (int j = 0; j < 26; j++) { if (cnt[j] > maxcolor) { maxcolor = cnt[j]; k = j; } } if (k == -1 || maxcolor < need[i].cnt) { flag = 1; break; } else { need[i].color = k; cnt[k] -= need[i].cnt; } } if (!flag) { printf( YES n ); for (int i = 0; i < 26; i++) { if (cnt[i]) { out[1] = i + a ; break; } } sort(need, need + colornum, cmp1); for (int i = 2; i <= len; i++) { out[i] = need[vis[i]].color + a ; } out[len + 1] = 0; printf( %s n , out + 1); } else { printf( NO n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1010, Maxm = 20; const unsigned long long Seed = 19990213; const long long Mod = 1000000007; int n, m, cnt, tot1, fst1[Maxn], pre1[Maxn << 1], to1[Maxn << 1], tot2, fst2[Maxm], pre2[Maxm << 1], to2[Maxm << 1], bel[Maxm], tot[Maxm], stat[(1 << 12) + 10][Maxm], cur[Maxm], S, w[Maxm], size[Maxm]; bool vis[Maxn], leaf[Maxm]; long long f[Maxn][Maxm], g[Maxn][(1 << 12) + 10], ans; unsigned long long ha[Maxm]; map<unsigned long long, bool> Hash; vector<int> son[Maxn], sub[Maxm]; int Get() { char ch; int v = 0; bool f = false; while (!isdigit(ch = getchar())) if (ch == - ) f = true; v = ch - 48; while (isdigit(ch = getchar())) v = v * 10 + ch - 48; if (f) return -v; else return v; } void AddE1(int x, int y) { pre1[++tot1] = fst1[x], fst1[x] = tot1, to1[tot1] = y; pre1[++tot1] = fst1[y], fst1[y] = tot1, to1[tot1] = x; } void AddE2(int x, int y) { pre2[++tot2] = fst2[x], fst2[x] = tot2, to2[tot2] = y; pre2[++tot2] = fst2[y], fst2[y] = tot2, to2[tot2] = x; } bool cmp(const int &a, const int &b) { return ha[a] < ha[b] || (ha[a] == ha[b] && size[a] < size[b]); } void Add(long long &x, long long y) { x += y; if (x >= Mod) x -= Mod; } void Calc(int x, int fa) { leaf[x] = true, size[x] = 1; sub[x].clear(); for (int i = fst2[x]; i; i = pre2[i]) if (to2[i] != fa) { Calc(to2[i], x); size[x] += size[to2[i]]; sub[x].push_back(to2[i]); leaf[x] = false; } if (leaf[x]) ha[x] = 666072; else { ha[x] = 0; sort(sub[x].begin(), sub[x].end(), cmp); for (int i = 0; i < sub[x].size(); i++) ha[x] = (ha[x] * Seed + ha[sub[x][i]]) % Mod; ha[x] = ha[x] * 1234 % Mod; } } void Transform(int x, int w, int s) { if (x == cnt + 1) { S = max(S, s); for (int i = 1; i <= cnt; i++) stat[s][i] = cur[i]; return; } else { for (int i = 0; i <= tot[x]; i++) { cur[x] = i; Transform(x + 1, w * (tot[x] + 1), s + i * w); } } } void dfs(int x) { vis[x] = true; son[x].clear(); for (int i = fst1[x]; i; i = pre1[i]) if (!vis[to1[i]]) son[x].push_back(to1[i]), dfs(to1[i]); int len1 = int(son[x].size()); for (int i = 1; i <= m; i++) if (leaf[i]) f[x][i] = 1; else if (len1 > 0) { f[x][i] = 0, cnt = 0, S = 0; int len2 = int(sub[i].size()); for (int j = 0; j <= len2 - 1; j++) { bel[++cnt] = sub[i][j], tot[cnt] = 1; for (; j < len2 - 1 && ha[sub[i][j]] == ha[sub[i][j + 1]] && size[sub[i][j]] == size[sub[i][j + 1]]; j++) tot[cnt]++; } w[1] = 1; for (int j = 2; j <= cnt; j++) w[j] = w[j - 1] * (tot[j - 1] + 1); Transform(1, 1, 0); for (int s = 0; s <= S; s++) g[0][s] = 0; g[0][S] = 1; for (int j = 0; j <= len1 - 1; j++) { int u = son[x][j]; for (int s = 0; s <= S; s++) g[j + 1][s] = g[j][s]; for (int k = 1; k <= cnt; k++) { int v = bel[k]; if (f[u][v]) { for (int s = 0; s <= S; s++) if (stat[s][k]) { Add(g[j + 1][s - w[k]], g[j][s] * f[u][v] % Mod); } } } } f[x][i] = g[len1][0]; } } void solve(int root) { for (int i = 1; i <= n; i++) vis[i] = false; dfs(1); long long res = 0; for (int i = 1; i <= n; i++) { Add(ans, f[i][root]); Add(res, f[i][root]); for (int j = 1; j <= m; j++) f[i][j] = 0; } } int main() { n = Get(); int x, y; for (int i = 1; i <= n - 1; i++) x = Get(), y = Get(), AddE1(x, y); m = Get(); for (int i = 1; i <= m - 1; i++) x = Get(), y = Get(), AddE2(x, y); for (int i = 1; i <= m; i++) { Calc(i, -1); if (!Hash[ha[i]]) { Hash[ha[i]] = true; solve(i); } } cout << ans << endl; return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module video_sys_Video_RGB_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 23;
parameter ODW = 15;
parameter IEW = 1;
parameter OEW = 0;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign converted_data[15:11] = r[ 9: 5];
assign converted_data[10: 5] = g[ 9: 4];
assign converted_data[ 4: 0] = b[ 9: 5];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int i, j, n, s = 0, c = 0, x, k, y, m, z, ans = 0; cin >> n >> m; cin >> x >> z >> y; vector<long long int> a(n), b(m); for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < m; i++) { cin >> b[i]; } if (n == m) { for (i = 0; i < n; i++) { if (a[i] != b[i]) { cout << -1; return; } } cout << 0; return; } if (m > n) { cout << -1; return; } i = 0; j = 0; k = 0; long long int ma = INT_MIN, l; while (i < n && j < m) { if (a[i] != b[j]) { ma = max(ma, a[i]); i++; } else { l = i - k; if (l == 0) { i++; j++; k = i; continue; } long long int maxel; if (k > 0) { maxel = max(a[k - 1], a[i]); } else { maxel = a[i]; } if (l < z) { if (maxel < ma) { cout << -1; return; } ans += l * y; } else { if (y * z < x && maxel > ma) { ans += l * y; } else if (y * z < x) { l = l - z; ans += x + l * y; } else { long long int rem = l % z; long long int gro = l / z; ans += gro * x + rem * y; } } j++; i++; k = i; ma = INT_MIN; } } l = n - k; for (long long int q = i; q < n; q++) { ma = max(ma, a[q]); } if (l > 0) { long long int maxel = a[k - 1]; if (l < z) { if (maxel < ma) { cout << -1; return; } ans += l * y; } else { if (y * z < x && maxel > ma) { ans += l * y; } else if (y * z < x) { l = l - z; ans += x + l * y; } else { long long int rem = l % z; long long int gro = l / z; ans += gro * x + rem * y; } } j++; i++; k = i; ma = INT_MIN; } cout << ans; } int main() { long long int t; t = 1; while (t--) { solve(); cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; int N; struct node { int val, pos; } A[2005]; int res[2005]; int cmp1(node a, node b) { return a.val > b.val; } int main() { A[0].val = 0x7fffffff; cin >> N; for (int i = 1; i <= N; i++) { scanf( %d , &A[i].val); A[i].pos = i; } sort(A + 1, A + 1 + N, cmp1); for (int i = 1; i <= N; i++) { if (A[i - 1].val == A[i].val) res[A[i].pos] = res[A[i - 1].pos]; else res[A[i].pos] = i; } for (int i = 1; i <= N; i++) printf( %d%c , res[i], i == N ? n : ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int read() { char ch = getchar(); int x = 0; while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x; } const int maxn = 2e5 + 5, inf = 1e9; struct Data { int next, to, w; }; struct LinkTable { Data data[maxn]; int head[maxn], cnt; void add(int x, int y, int w) { data[++cnt] = (Data){head[x], y, w}; head[x] = cnt; } } E, R; struct DP { int sum, id, lca; } f[maxn], g[maxn]; int N, K, mx[5], mi[5], ret[maxn], fa[maxn], w[maxn]; bool mark[maxn]; int update(int &x, int y) { if (x < y) return x = y, 1; if (x == y) return 0; return -1; } void F(int x) { int sum = mark[x] ? 0 : -inf, id = x; for (int i = E.head[x]; i; i = E.data[i].next) if (E.data[i].to != fa[x]) { Data &e = E.data[i]; fa[e.to] = x; w[e.to] = e.w; F(e.to); if (update(sum, f[e.to].sum + e.w) == 1) id = f[e.to].id; else if (!update(sum, f[e.to].sum + e.w)) id = x; } f[x].sum = sum; f[x].id = id; f[x].lca = x; } void G(int x) { g[x] = g[fa[x]]; g[x].sum += w[x]; if (mark[fa[x]] && w[x] > g[x].sum) g[x].sum = w[x], g[x].id = g[x].lca = fa[x]; for (int i = R.head[fa[x]]; i; i = R.data[i].next) if (R.data[i].to != x) { Data &e = R.data[i]; if (update(g[x].sum, f[e.to].sum + e.w + w[x]) == 1) g[x].id = f[e.to].id, g[x].lca = fa[x]; else if (update(g[x].sum, f[e.to].sum + e.w + w[x]) == 0) g[x].id = g[x].lca = fa[x]; } for (int i = 0; i < 3; ++i) mi[i] = 0, mx[i] = -inf; for (int i = E.head[x]; i; i = E.data[i].next) if (E.data[i].to != fa[x]) { Data &e = E.data[i]; if (update(mx[0], f[e.to].sum + e.w) == 1) { mx[2] = mx[1], mi[2] = mi[1]; mx[1] = mx[0], mi[1] = mi[0]; mi[0] = e.to; } else if (update(mx[1], f[e.to].sum + e.w) == 1) mx[2] = mx[1], mi[2] = mi[1], mi[1] = e.to; else if (update(mx[2], f[e.to].sum + e.w) == 1) mi[2] = e.to; } for (int i = 0; i < 3; ++i) if (mi[i]) R.add(x, mi[i], w[mi[i]]); for (int i = E.head[x]; i; i = E.data[i].next) if (E.data[i].to != fa[x]) G(E.data[i].to); } void init() { N = read(), K = read(); for (int i = 1; i <= K; ++i) mark[read()] = true; for (int i = 1, u, v, w; i < N; ++i) u = read(), v = read(), w = read(), E.add(u, v, w), E.add(v, u, w); g[0].sum = -inf; } void dfs(int x) { for (int i = E.head[x]; i; i = E.data[i].next) if (E.data[i].to != fa[x]) { Data &e = E.data[i]; dfs(e.to); ret[x] += ret[e.to]; } } void solve() { for (int i = 1; i <= N; ++i) if (mark[i] && f[i].sum != g[i].sum) if (f[i].sum > g[i].sum) ++ret[f[i].id], --ret[f[i].lca]; else ++ret[g[i].id], --ret[g[i].lca], ++ret[i], --ret[fa[g[i].lca]]; dfs(1); int sum = -inf, once = 0; for (int i = 1; i <= N; ++i) if (!mark[i]) if (ret[i] > sum) sum = ret[i], once = 1; else if (ret[i] == sum) ++once; printf( %d %d n , sum, once); } int main() { init(); F(1), G(1); solve(); return 0; }
|
module note_pitch2dds(CLK, NOTE, PITCH, ADDER);
input wire CLK;
input wire [6:0] NOTE;
input wire [13:0] PITCH;
output reg [31:0] ADDER;
reg [32:0] ADDER_sum;
reg [7:0] ADDER_mul;
reg [3:0] state;
reg [6:0] NOTE_local;
reg [13:0] PITCH_local;
initial begin
NOTE_local <= 7'd0;
PITCH_local <= 14'd08192; // 0 - pitch wheel
ADDER <= 32'd0;
state <= 4'd0;
SNOTE <= 9'D0;
end
//считаем Pitch Wheel
// in_val сначала << 7
// а потом
//; ALGORITHM:
//; Clear accumulator
//; Add input / 1024 to accumulator >> 10
//; Add input / 2048 to accumulator >> 11
//; Move accumulator to result
//; Approximated constant: 0.00146484, Error: 0 %
//вычитаем 8192
wire signed [14:0] in_val_centered = (PITCH - 14'd08192);
//15+11 = 26 бит
wire signed [26:0] in_val_fix = in_val_centered <<< 11;
//mul 0.00146484
wire signed [26:0] in_val_mul = (in_val_fix >>> 10) + (in_val_fix >>> 11);
//старшая часть, которую прибавим к номеру ноты
wire signed [26:0] t_in_val_hi = in_val_mul >>> 11;
wire signed [7:0] in_val_hi = t_in_val_hi[7:0];
//младшая 8 битная часть, которую будем применять в линейной интерполяции
wire [7:0] in_val_lo = in_val_mul[10:3];
reg signed [8:0] SNOTE ; //= NOTE;
wire [7:0] NOTE_n = ((SNOTE + in_val_hi)< 0) ? 7'd0 :
((SNOTE + in_val_hi)> 127) ? 7'd0127 : SNOTE + in_val_hi;
wire [31:0] ADDER_by_table;
note2dds note2dds_table(CLK, NOTE_n[6:0], ADDER_by_table);
always @ (posedge CLK) begin
if (state==4'd00) begin
SNOTE <= NOTE;
if ((NOTE!=NOTE_local)||(PITCH!=PITCH_local)) begin
NOTE_local<=NOTE;
PITCH_local<=PITCH;
ADDER_sum<=33'd0;
ADDER_mul<=8'd0;
end
end else if ((state==4'd01)||(state==4'd02)||(state==4'd03)) begin
SNOTE <= SNOTE + 1'b1; //if не обязателен
if (state==4'd01) ADDER_mul <= 8'd0255 - in_val_lo;
if (state==4'd02) ADDER_mul <= in_val_lo;
ADDER_sum <= ADDER_sum + (ADDER_mul * ADDER_by_table);
end else if (state==4'd04) begin
ADDER <= ADDER_sum >> 8;
end
end
always @ (posedge CLK) begin
//смена стейтов
if (state==4'd00) begin
if ((NOTE!=NOTE_local)||(PITCH!=PITCH_local)) begin
state<=4'd01;
end else begin
state<=4'd00;
end
end else if (state==4'd01) begin
state<=4'd02;
end else if (state==4'd02) begin
state<=4'd03;
end else if (state==4'd03) begin
state<=4'd04;
end else if (state==4'd04) begin
state<=4'd00;
end
end
endmodule
|
/*
* Wishbone asynchronous bridge with slave register slice
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_abrg_reg (
input sys_rst,
// Wishbone slave interface
input wbs_clk_i,
input [19:1] wbs_adr_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input [ 1:0] wbs_sel_i,
input wbs_tga_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
output wbs_ack_o,
// Wishbone master interface
input wbm_clk_i,
output reg [19:1] wbm_adr_o,
output reg [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg [ 1:0] wbm_sel_o,
output reg wbm_tga_o,
output wbm_stb_o,
output wbm_cyc_o,
output reg wbm_we_o,
input wbm_ack_i
);
// Registers and nets
wire wbs_stb;
wire init_tr;
reg wbm_stb;
reg [2:0] sync_stb;
reg [2:0] sync_ack;
reg ft_stb;
reg ft_ack;
reg stb_r;
reg ack_r;
reg [19:1] wbm_adr_o_r;
reg [15:0] wbm_dat_o_r;
reg [ 1:0] wbm_sel_o_r;
reg wbs_tga_i_r;
reg wbm_tga_o_r;
reg wbs_we_i_r;
reg wbm_we_o_r;
reg [15:0] wbs_dat_o_r;
reg [15:0] wbm_dat_i_r;
wire [19:1] wbs_adr_i_reg;
wire [15:0] wbs_dat_i_reg;
reg [15:0] wbs_dat_o_reg;
wire [ 1:0] wbs_sel_i_reg;
wire wbs_tga_i_reg;
wire wbs_stb_i_reg;
wire wbs_cyc_i_reg;
wire wbs_we_i_reg;
wire wbs_ack_o_reg;
// Instances
wb_regslice wb_slave_regslice (
.clk (wbs_clk_i),
.rst (sys_rst),
// Wishbone slave interface
.wbs_adr_i (wbs_adr_i),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o),
.wbs_sel_i (wbs_sel_i),
.wbs_tga_i (wbs_tga_i),
.wbs_stb_i (wbs_stb_i),
.wbs_cyc_i (wbs_cyc_i),
.wbs_we_i (wbs_we_i),
.wbs_ack_o (wbs_ack_o),
// Wishbone master interface
.wbm_adr_o (wbs_adr_i_reg),
.wbm_dat_o (wbs_dat_i_reg),
.wbm_dat_i (wbs_dat_o_reg),
.wbm_sel_o (wbs_sel_i_reg),
.wbm_tga_o (wbs_tga_i_reg),
.wbm_stb_o (wbs_stb_i_reg),
.wbm_cyc_o (wbs_cyc_i_reg),
.wbm_we_o (wbs_we_i_reg),
.wbm_ack_i (wbs_ack_o_reg)
);
// Continous assignments
assign wbs_stb = wbs_stb_i_reg & wbs_cyc_i_reg;
// recreate the flag from the level change
assign wbs_ack_o_reg = (sync_ack[2] ^ sync_ack[1]);
assign wbm_stb_o = wbm_stb;
assign wbm_cyc_o = wbm_stb;
/*
* A new wishbone transaction is issued:
* . by changing stb from 0 to 1
* . by continue asserting stb after ack is received
*/
assign init_tr = ~stb_r & wbs_stb | ack_r & ~wbs_ack_o_reg & wbs_stb;
// Behaviour
// wbm_stb
always @(posedge wbm_clk_i)
wbm_stb <= sys_rst ? 1'b0
: (wbm_stb ? ~wbm_ack_i : sync_stb[2] ^ sync_stb[1]);
// old stb and ack state
always @(posedge wbs_clk_i) stb_r <= wbs_stb;
always @(posedge wbs_clk_i) ack_r <= wbs_ack_o_reg;
always @(posedge wbs_clk_i)
ft_stb <= sys_rst ? 1'b0 : (init_tr ? ~ft_stb : ft_stb);
// synchronize the last level change
always @(posedge wbm_clk_i)
sync_stb <= sys_rst ? 3'h0 : {sync_stb[1:0], ft_stb};
// this changes level when a flag is seen
always @(posedge wbm_clk_i)
ft_ack <= sys_rst ? 1'b0 : (wbm_ack_i ? ~ft_ack : ft_ack);
// which can then be synched to wbs_clk_i
always @(posedge wbs_clk_i)
sync_ack <= sys_rst ? 3'h0 : {sync_ack[1:0], ft_ack};
// rest of the wishbone signals
always @(posedge wbm_clk_i)
{wbm_adr_o, wbm_adr_o_r} <= {wbm_adr_o_r, wbs_adr_i_reg};
always @(posedge wbm_clk_i)
{wbm_dat_o, wbm_dat_o_r} <= {wbm_dat_o_r, wbs_dat_i_reg};
always @(posedge wbm_clk_i)
{wbm_sel_o, wbm_sel_o_r} <= {wbm_sel_o_r, wbs_sel_i_reg};
always @(posedge wbs_clk_i) wbs_we_i_r <= wbs_we_i_reg;
always @(posedge wbm_clk_i)
{wbm_we_o, wbm_we_o_r} <= {wbm_we_o_r, wbs_we_i_r};
always @(posedge wbs_clk_i) wbs_tga_i_r <= wbs_tga_i_reg;
always @(posedge wbm_clk_i)
{wbm_tga_o, wbm_tga_o_r} <= {wbm_tga_o_r, wbs_tga_i_r};
/*
* Register input coming from the slave as that can change
* after the ack is received
*/
always @(posedge wbm_clk_i)
wbm_dat_i_r <= wbm_ack_i ? wbm_dat_i : wbm_dat_i_r;
always @(posedge wbs_clk_i)
{wbs_dat_o_reg, wbs_dat_o_r} <= {wbs_dat_o_r, wbm_dat_i_r};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_4_V
`define SKY130_FD_SC_LS__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:10:55 03/06/2016
// Design Name:
// Module Name: mult4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Multiplicador de 4 bits, Practica 1
module mult4(
input x0,
input x1,
input x2,
input x3,
input y0,
input y1,
input y2,
input y3,
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7
);
//productos
//wire p00; -> z0
wire p01;
wire p02;
wire p03;
wire p10;
wire p11;
wire p12;
wire p13;
wire p20;
wire p21;
wire p22;
wire p23;
wire p30;
wire p31;
wire p32;
wire p33;
//acarreos
wire c1;
wire c2;
wire c3;
wire c4;
wire c5;
wire c6;
wire c7;
wire c8;
wire c9;
wire c10;
wire c11;
wire c12;
wire c13;
wire c14;
wire c15;
//sumas
wire s1;
wire s2;
wire s3;
wire s4;
wire s5;
wire s6;
wire s7;
wire s8;
and(z0, x0, y0); //z0
and(p01, x0, y1);
and(p02, x0, y2);
and(p03, x0, y3);
and(p10, x1, y0);
and(p11, x1, y1);
and(p12, x1, y2);
and(p13, x1, y3);
and(p20, x2, y0);
and(p21, x2, y1);
and(p22, x2, y2);
and(p23, x2, y3);
and(p30, x3, y0);
and(p31, x3, y1);
and(p32, x3, y2);
and(p33, x3, y3);
summed HA1(p01, p10, z1, c1); //z1
summed HA2(p11, p20, s1, c2);
sumcomp FA2(p02, s1, c1, z2, c3); //z2
sumcomp FA31(p21, p30, p12, s2, c4);
summed HA3(p03, s2, s3, c5);
sumcomp FA32(c2, s3, c3, z3, c6); //z3
sumcomp FA41(p22, p31, p13, s4, c7);
summed HA4(s4, c4, s5, c8);
sumcomp FA42(c5, s5, c6, z4, c9); //z4
summed HA51(p23, p32, s6, c10);
summed HA52(s6, c7, s7, c11);
sumcomp FA5(c8, s7, c9, z5, c12); //z5
summed HA6(p33, c10, s8, c13);
sumcomp FA6(c11, s8, c12, z6, c14); //z6
summed HA7(c13, c14, z7, c15); //z7
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_4_V
`define SKY130_FD_SC_HVL__BUF_4_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_4_V
|
#include <bits/stdc++.h> const int N = 3e5 + 10; const int mod = 1e9 + 7; int n; std::vector<int> edge[N]; std::pair<int, int> v[N]; int q; std::pair<int, int> query[N]; int queue[N]; std::pair<int, int> range[N]; int father[N]; int degree[N]; int fastPower(int x, int y) { int ret = 1; for (; y; y >>= 1) { if (y & 1) { ret = (long long)ret * x % mod; } x = (long long)x * x % mod; } return ret; } int inv(int x) { return fastPower(x, mod - 2); } int lowbit(int x) { return x & (-x); } struct FenwickTree { int e[N]; void build(int size) { for (int i = 1; i <= size; i++) { e[i] = 1; } } void change(int x, int value) { for (int i = x; i <= n; i += lowbit(i)) { e[i] = (long long)e[i] * value % mod; } } int getValue(int x) { int ret = 1; for (int i = x; i >= 1; i -= lowbit(i)) { ret = (long long)ret * e[i] % mod; } return ret; } }; FenwickTree ft; struct SegmentTree { struct Node { int sum; int tag; }; Node tree[N << 2]; void update(int root, int left, int right) { tree[root].sum = (long long)tree[root].sum * tree[root].tag % mod; if (left != right) { tree[root << 1].tag = (long long)tree[root << 1].tag * tree[root].tag % mod; tree[root << 1 | 1].tag = (long long)tree[root << 1 | 1].tag * tree[root].tag % mod; } tree[root].tag = 1; } void change(int root, int left, int right, int pos, int value) { update(root, left, right); if (left == pos && right == pos) { tree[root].sum = value; return; } int mid = (left + right) >> 1; if (pos <= mid) { change(root << 1, left, mid, pos, value); } else { change(root << 1 | 1, mid + 1, right, pos, value); } update(root << 1, left, mid); update(root << 1 | 1, mid + 1, right); tree[root].sum = tree[root << 1].sum + tree[root << 1 | 1].sum; } void change2(int root, int left, int right, int ql, int qr, int value) { update(root, left, right); if (left == ql && right == qr) { tree[root].tag = value; update(root, left, right); return; } int mid = (left + right) >> 1; if (qr <= mid) { change2(root << 1, left, mid, ql, qr, value); } else if (ql > mid) { change2(root << 1 | 1, mid + 1, right, ql, qr, value); } else { change2(root << 1, left, mid, ql, mid, value); change2(root << 1 | 1, mid + 1, right, mid + 1, qr, value); } update(root << 1, left, mid); update(root << 1 | 1, mid + 1, right); tree[root].sum = tree[root << 1].sum + tree[root << 1 | 1].sum; } int getSum(int root, int left, int right, int ql, int qr) { update(root, left, right); if (left == ql && right == qr) { return tree[root].sum; } int mid = (left + right) >> 1; if (qr <= mid) { return getSum(root << 1, left, mid, ql, qr); } else if (ql > mid) { return getSum(root << 1 | 1, mid + 1, right, ql, qr); } else { return (getSum(root << 1, left, mid, ql, mid) + getSum(root << 1 | 1, mid + 1, right, mid + 1, qr)) % mod; } } }; SegmentTree st; void init() { std::cin >> v[1].second >> q; n = 1; for (int i = 1; i <= q; i++) { scanf( %d%d , &query[i].first, &query[i].second); if (query[i].first == 1) { father[++n] = query[i].second; scanf( %d , &v[n].second); edge[father[n]].push_back(n); } } } void dfs(int u) { static int tot = 0; queue[++tot] = u; range[u].first = tot; for (int i = 0; i < (int)edge[u].size(); i++) { dfs(edge[u][i]); } range[u].second = tot; } void work() { dfs(1); std::fill(degree + 1, degree + n + 1, 1); ft.build(n); int tmp = 1; v[1].first = v[1].second; st.change(1, 1, n, range[1].first, v[1].first); for (int i = 1; i <= q; i++) { if (query[i].first == 1) { int fa = query[i].second; tmp++; v[tmp].first = v[tmp].second; degree[fa]++; int cc = (long long)degree[fa] * inv(degree[fa] - 1) % mod; ft.change(range[fa].first, cc); ft.change(range[fa].second + 1, inv(cc)); st.change2(1, 1, n, range[fa].first, range[fa].second, cc); st.change(1, 1, n, range[tmp].first, (long long)v[tmp].first * ft.getValue(range[tmp].first) % mod); } else { int u = query[i].second; int answer = st.getSum(1, 1, n, range[u].first, range[u].second); if (u != 1) { answer = (long long)answer * inv(ft.getValue(range[father[u]].first)) % mod; } printf( %d n , answer); } } } int main() { init(); work(); return 0; }
|
/******************************************************
A fifo controller verilog description.
******************************************************/
module fifo(datain, rd, wr, rst, clk, dataout, full, empty);
input [7:0] datain;
input rd, wr, rst, clk;
output [7:0] dataout;
output full, empty;
wire [7:0] dataout;
reg full_in, empty_in;
reg [7:0] mem [15:0];
reg [3:0] rp, wp;//其实是一个循环读写的过程,4位二进制数刚好16个状态，也即指示16个深度
assign full = full_in;
assign empty = empty_in;
// memory read out
assign dataout = mem[rp];
// memory write in
always@(posedge clk) begin
if(wr && ~full_in) mem[wp]<=datain;
end
// memory write pointer increment
always@(posedge clk or negedge rst) begin
if(!rst) wp<=0;
else begin
if(wr && ~full_in) wp<= wp+1'b1;
end
end
// memory read pointer increment
always@(posedge clk or negedge rst)begin
if(!rst) rp <= 0;
else begin
if(rd && ~empty_in) rp <= rp + 1'b1;
end
end
// Full signal generate
always@(posedge clk or negedge rst) begin
if(!rst) full_in <= 1'b0;
else begin
if( (~rd && wr)&&((wp==rp-1)||(rp==4'h0&&wp==4'hf)))
full_in <= 1'b1;
else if(full_in && rd) full_in <= 1'b0;
end
end
// Empty signal generate
always@(posedge clk or negedge rst) begin
if(!rst) empty_in <= 1'b1;
else begin
if((rd&&~wr)&&(rp==wp-1 || (rp==4'hf&&wp==4'h0)))
empty_in<=1'b1;
else if(empty_in && wr) empty_in<=1'b0;
end
end
endmodule
[同步FIFO]
// 同步FIFO相对简单，但稍微复杂点儿的就是full和empty信号的产生，有两种方法上述代码是常用的，但不很容易理解，
// 解释下，FIFO先入先出，可知读写地址都是从零开始递增，这样才能满足先写进的将来会被先读出来。对于同步FIFO来说，时钟是同一个，
// 如果同时读写，那么FIFO永远都不会满。因为当写指针到FIFO尽头时，会继续从零地址开始写（假设零地址的数据已经被读出，当然就可以覆盖了），如此循环往复。那么到底
[空满标志如何产生：]
// 最直观的一种情况，对于full来说，假如一直写，都还没读，此时当wrp=FIFO深度时，应该产生满标志，如果继续写，就会覆盖还未读出的数据，从而使数据失效。
// 对于empty来说，假如wrp=0，而rdp=FIFO深度时，应该产生空标志，如果继续读。就会从零地址开始读，而零地址要么是以前的数据要么是空的，所以…
// 第二种情况：wrp与rdp之间差值为1，rdp-wrp=1时如果没有读，继续写的话会发生数据覆盖；wrp-rdp=1时如果没有写继续读，会读出错误数据。
// 这就是程序中标志位表达形式的原因。
[还有一种简单的方法产生空满标志：]
// 并不用读写地址判定FIFO是否空满。设计一个计数器，该计数器(pt_cnt)用于指示当前周期中FIFO中数据的个数。由于FIFO中最多只有16个数据，因此采用5位计数器来指示FIFO中数据个数。具体计算如下：
// 复位的时候，pt_cnt=0；
// 如果wr_en和rd_en同时有效的时候，pt_cnt不加也不减；表示同时对FIFO进行读写操作的时候，FIFO中的数据个数不变。
// 如果wr_en有效且full=0，则pt_cont+1;表示写操作且FIFO未满时候，FIFO中的数据个数增加了1；
// 如果rd_en有效且empty=0，则pt_cont-1; 表示读操作且FIFO未满时候，FIFO中的数据个数减少了1；
// 如果pt_cnt=0的时候，表示FIFO空，需要设置empty=1;如果pt_cnt=16的时候，表示FIFO现在已经满，需要设置full=1。
该模块的程序：
module flag_gen(clk,rst,full,emptyp,wr_en,rd_en);
input clk,rst;
input rd_en;
input wr_en;
output full,emptyp;
reg full,emptyp;
reg[4:0]count;
parameter max_count=5'b01111;
always @ (posedge clk or negedge rst)
begin
if(!rst)
count<=0;
else
begin
case({wr_en,rd_en})
2'b00:count<=count;
2'b01:
if(count!==5'b00000)
count<=count-1;
2'b10:
if(count!== max_count)
count<=count+1;
2'b11:count<=count;
endcase
end
end
always @(count)
begin
if(count==5'b00000)
emptyp<=1;
else
emptyp<=0;
end
always @(count)
begin
if(count== max_count)
full<=1;
else
full<=0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxk = 50, maxn = 100; int k, x, n, m; inline int calc(int x, int y) { if (!x && y == 2) return 1; return 0; } struct node { long long c1[2], c2[2][2]; bool h, t; node operator+(const node &Other) const { node N = {}; N.h = h; N.t = Other.t; for (int i = 0; i < 2; ++i) N.c1[i] = c1[i] + Other.c1[i]; for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) N.c2[i][j] = c2[i][j] + Other.c2[i][j]; ++N.c2[t][Other.h]; return N; } } f[maxk + 1] = {}; int dp[3][3][maxn + 1][maxn + 1]; int s1[3][3][maxn + 1][maxn + 1], s2[3][3][maxn + 1][maxn + 1]; int main() { scanf( %d%d%d%d , &k, &x, &n, &m); f[1].c1[0] = 1; f[2].c1[1] = 1; f[2].h = f[2].t = 1; for (int i = 3; i <= k; ++i) f[i] = f[i - 2] + f[i - 1]; if (n > 1) { memset(dp, -1, sizeof(dp)); for (int i = 0; i < 3; ++i) dp[i][i][1][0] = 0; for (int h = 0; h < 3; ++h) { for (int i = 2; i <= n; ++i) for (int j1 = 0; j1 < 3; ++j1) for (int k = 0; k < i - 1; ++k) if (~dp[h][j1][i - 1][k]) { for (int j2 = 0; j2 < 3; ++j2) dp[h][j2][i][k + calc(j1, j2)] = j1; } for (int t = 0; t < 3; ++t) for (int k = 0; k < n; ++k) if (~dp[h][t][n][k] && !s1[h][t][k][0]) { s1[h][t][k][0] = 1; for (int dep = n, c = t, j = k; dep; --dep) { s1[h][t][k][dep] = c; int d = dp[h][c][dep][j]; j -= calc(d, c); c = d; } } } } else { for (int i = 0; i < 3; ++i) { s1[i][i][0][0] = 1; s1[i][i][0][1] = i; } } if (m > 1) { memset(dp, -1, sizeof(dp)); for (int i = 0; i < 3; ++i) dp[i][i][1][0] = 0; for (int h = 0; h < 3; ++h) { for (int i = 2; i <= m; ++i) for (int j1 = 0; j1 < 3; ++j1) for (int k = 0; k < i - 1; ++k) for (int j2 = 0; j2 < 3; ++j2) if (~dp[h][j1][i - 1][k]) dp[h][j2][i][k + calc(j1, j2)] = j1; for (int t = 0; t < 3; ++t) for (int k = 0; k < m; ++k) if (~dp[h][t][m][k]) { s2[h][t][k][0] = 1; for (int dep = m, c = t, j = k; dep; --dep) { s2[h][t][k][dep] = c; int d = dp[h][c][dep][j]; j -= calc(d, c); c = d; } } } } else { for (int i = 0; i < 3; ++i) { s2[i][i][0][0] = 1; s2[i][i][0][1] = i; } } for (int h1 = 0; h1 < 3; ++h1) for (int t1 = 0; t1 < 3; ++t1) for (int i = 0; i < n; ++i) if (s1[h1][t1][i][0]) { for (int h2 = 0; h2 < 3; ++h2) for (int t2 = 0; t2 < 3; ++t2) for (int j = 0; j < m; ++j) if (s2[h2][t2][j][0]) { long long cnt = f[k].c1[0] * i + f[k].c1[1] * j; cnt += f[k].c2[0][0] * calc(t1, h1) + f[k].c2[0][1] * calc(t1, h2) + f[k].c2[1][0] * calc(t2, h1) + f[k].c2[1][1] * calc(t2, h2); if (cnt == x) { for (int k = 1; k <= n; ++k) putchar(s1[h1][t1][i][k] + 65); putchar( n ); for (int k = 1; k <= m; ++k) putchar(s2[h2][t2][j][k] + 65); putchar( n ); return 0; } } } puts( Happy new year! ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/02/2016 03:58:56 PM
// Design Name:
// Module Name: FSM_Convert_Fixed_To_Float
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Convert_Fixed_To_Float(
//INPUTS
input wire CLK, //system clock
input wire RST_FF, //system reset
input wire Bandcomp, //INDICA SI EL VALOR DEL EXPONENTE ES MAYOR QUE 26
input wire Begin_FSM_FF, //inicia la maquina de estados
input wire [7:0] Encd, //CONTIENE EL VALOR DEL PRIMER 1 EN LA SECUENCIA BINARIA DEL NUMERO PUNTO FIJO
// OUTPUTS
output reg EN_REG1, //ENABLE PARA EL REGISTRO QUE GUARDA EL NUMERO EN PUNTO FIJO
output reg EN_REGmult, //ENABLE PARA EL REGISTRO MULT QUE GUARDA EL VALOR A TRUNCAR
output reg LOAD, //SELECCION PARA EL REGISTRO DE DESPLAZAMIENTOS
output reg MS_1, //SELECCION DEL MUX 1 (VALOR INICIAL DE LA POSICION DEL 1 , VALOR DE DESPLAZAMIENTOS 1)
output reg ACK_FF, //INDICA QUE LA CONVERSION FUE REALIZADA
output reg EN_MS_1,
output reg EN_REG2,
output reg RST
);
parameter [3:0]
//se definen los estados que se utilizaran en la maquina
a = 4'b0000,
b = 4'b0001,
c = 4'b0010,
d = 4'b0011,
e = 4'b0100,
f = 4'b0101,
g = 4'b0110,
h = 4'b0111,
i = 4'b1000,
j = 4'b1001,
k = 4'b1010;
reg [3:0] state_reg, state_next ; //state registers declaration
////
always @(posedge CLK, posedge RST_FF)
if (RST_FF)
begin
state_reg <= a;
end
else
begin
state_reg <= state_next;
end
//assign State = state_reg;
///
always @*
begin
state_next = state_reg;
EN_REG1 = 1'b0;
EN_REGmult = 1'b0;
EN_REG2 = 1'b0;
ACK_FF = 1'b0;
EN_MS_1 = 1'b0;
MS_1 = 1'b0;
LOAD = 1'b0;
RST = 1'b0;
case(state_reg)
a:
begin
if(Begin_FSM_FF)
begin
RST = 1'b1;
ACK_FF = 1'b0;
state_next = b;
end
else
state_next = a;
end
b:
begin
EN_REG1 = 1'b1;
state_next = c;
end
c:
begin
state_next = d;
end
d:
begin
EN_REGmult = 1'b1;
state_next = e;
end
e:
begin
EN_MS_1 = 1'b1;
if(Encd == 8'b00011010)
state_next = k;
else
state_next = f;
end
f:
begin
EN_MS_1 = 1'b1;
MS_1 = 1'b1;
state_next = g;
end
g:
begin
state_next = h;
end
h:
begin
LOAD = 1'b1;
state_next = i;
end
i:
begin
EN_REG2 = 1'b1;
state_next = j;
end
j:
begin
ACK_FF = 1'b1;
if(RST_FF)
state_next = a;
else
state_next = j;
end
k:
begin
state_next = h;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename TT> ostream& operator<<(ostream& out, pair<T, TT> t) { return out << ( << t.first << , << t.second << ) ; } template <typename T> ostream& operator<<(ostream& out, vector<T> t) { for (int i = 0; i < ((int)(t).size()); i++) out << t[i] << ; return out; } template <typename T> inline bool cmin(T& a, const T& b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool cmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <typename T> void read(T& x) { int f = 1; char ch; x = 0; while (!isdigit(ch = getchar())) ; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } const int NX = 201234; int n, m, p[NX]; map<int, int> e[NX]; int main() { read(n); read(m); for (int i = 1, u, v; i <= m; i++) { read(u); read(v); e[u][v] = e[v][u] = true; } for (int i = 1; i <= n; i++) p[i] = i; for (int T = 200; T--;) { random_shuffle(p + 1, p + n + 1); int cnt = 0; for (int i = 1; i <= n; i++) { int l = p[i], r = p[i % n + 1]; cnt += !e[l].count(r); } if (cnt >= m) { for (int i = 1; i <= n; i++) { int l = p[i], r = p[i % n + 1]; if (!e[l].count(r)) { printf( %d %d n , l, r); if (!--m) return 0; } } } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, a[100009], dau, cuoi, d[100009], c[100009], Res; string st; void Input() { cin >> n >> k >> st; for (int i = 0; i < n; ++i) { a[i + 1] = st[i] - a ; } } void Solve() { dau = 1; cuoi = 1; d[0] = 0; c[0] = 0; while (cuoi <= n) { if (a[cuoi] == 0) { d[cuoi] = d[cuoi - 1] + 1; c[cuoi] = c[cuoi - 1]; } else { if (c[cuoi - 1] + 1 <= k) { d[cuoi] = d[cuoi - 1] + 1; c[cuoi] = c[cuoi - 1] + 1; } else { c[cuoi] = c[cuoi - 1] + 1; d[cuoi] = d[cuoi - 1] + 1; while (dau <= cuoi) { if (c[cuoi] > k) { if (a[dau] == 1) { c[cuoi]--; } dau++; d[cuoi]--; } else break; } } } Res = max(Res, d[cuoi]); cuoi++; } dau = 1; cuoi = 1; d[0] = 0; c[0] = 0; while (cuoi <= n) { if (a[cuoi] == 1) { d[cuoi] = d[cuoi - 1] + 1; c[cuoi] = c[cuoi - 1]; } else { if (c[cuoi - 1] + 1 <= k) { d[cuoi] = d[cuoi - 1] + 1; c[cuoi] = c[cuoi - 1] + 1; } else { c[cuoi] = c[cuoi - 1] + 1; d[cuoi] = d[cuoi - 1] + 1; while (dau <= cuoi) { if (c[cuoi] > k) { if (a[dau] == 0) { c[cuoi]--; } dau++; d[cuoi]--; } else break; } } } Res = max(Res, d[cuoi]); cuoi++; } cout << Res; } int main() { Input(); Solve(); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; int n, k; int a[MAXN], f[MAXN]; int bsL(int l, int r, int val) { int pos = -1; while (l <= r) { int mid = (l + r) >> 1; if (a[mid] >= val) { pos = mid; r = mid - 1; } else l = mid + 1; } return pos; } bool check(int x) { f[1] = 1; for (int i = 1, l = 1; i <= n; i++) { while (a[i] - a[l] > x) l++; f[i + 1] = (i >= k && f[i - k + 1] - f[l - 1] > 0); f[i + 1] += f[i]; } return f[n + 1] - f[n] > 0; } int bs(int l, int r) { int pos = 0; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) { pos = mid; r = mid - 1; } else l = mid + 1; } return pos; } int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); cout << bs(0, 1e9); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, mod = 998244353; int mu[maxn], n, m, l[51], r[51], prime[maxn], cnt; bool is_composite[maxn]; int dp[maxn], pre[maxn]; int cal(int d) { int M = m / d; for (int i = 1; i <= M; i++) dp[i] = 0; dp[0] = 1; for (int i = 1; i <= n; i++) { int L = (l[i] + d - 1) / d, R = r[i] / d; if (L > R) return 0; pre[0] = dp[0]; for (int j = 1; j <= M; j++) pre[j] = (pre[j - 1] + dp[j]) % mod; for (int j = 0; j <= M; j++) { dp[j] = (((j - L >= 0) ? pre[j - L] : 0) - ((j - R - 1 >= 0) ? pre[j - R - 1] : 0)) % mod; } } pre[0] = dp[0]; for (int j = 0; j <= M; j++) pre[j] = (pre[j - 1] + dp[j]) % mod; return pre[M]; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) scanf( %d%d , &l[i], &r[i]); mu[1] = 1; for (int i = 2; i <= m; i++) { if (!is_composite[i]) { prime[++cnt] = i; mu[i] = mod - 1; } for (int j = 1; j <= cnt && i * prime[j] <= m; j++) { is_composite[i * prime[j]] = true; if (i % prime[j]) mu[i * prime[j]] = (mod - mu[i]) % mod; else break; } } int ans = 0; for (int d = 1; d <= m; d++) { ans = (ans + 1LL * cal(d) * mu[d]) % mod; } cout << ans << n ; }
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_baser_tx_64
*/
module test_axis_baser_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter HDR_WIDTH = 2;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
parameter PTP_TAG_WIDTH = 16;
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
wire m_axis_ptp_ts_valid;
wire [1:0] start_packet;
wire error_underflow;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
ptp_ts,
ifg_delay
);
$to_myhdl(
s_axis_tready,
encoded_tx_data,
encoded_tx_hdr,
m_axis_ptp_ts,
m_axis_ptp_ts_tag,
m_axis_ptp_ts_valid,
start_packet,
error_underflow
);
// dump file
$dumpfile("test_axis_baser_tx_64.lxt");
$dumpvars(0, test_axis_baser_tx_64);
end
axis_baser_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(start_packet),
.error_underflow(error_underflow)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int n; long long p[200002], i[200002], v[200002], lvl[200002], ans; vector<int> G[200002]; void dfs(int x, int par) { if (par) lvl[x] = lvl[par] + 1; for (auto it : G[x]) { if (it == par) continue; dfs(it, x); ans = (ans + 2 * v[x] * (i[x] * p[it] % mod - p[x] * i[it] % mod + mod) % mod); i[x] += p[it]; p[x] += i[it]; } i[x]++; } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; G[x].push_back(y); G[y].push_back(x); } dfs(1, 0); for (int it = 1; it <= n; it++) { if (lvl[it] % 2) ans = (ans + 2 * v[it] * (i[it] * (p[1] - i[it] + 1) % mod - p[it] * (i[1] - p[it]) % mod + mod) % mod) % mod; else { ans = (ans + 2 * v[it] * (i[it] * (i[1] - i[it] + 1) % mod - p[it] * (p[1] - p[it]) % mod + mod) % mod) % mod; } ans = (ans - v[it] + mod) % mod; } cout << ans; return 0; }
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0.0
// \ \ Filename: debnce.v
// / / Date Created: December 25, 2006
// /___/ /\ Last Modified: December 25, 2006
// \ \ / \
// \___\/\___\
//
// Devices: Spartan-3 Generation FPGA
// Purpose: Switch debouncer with pulses for on/off events
// Contact:
// Reference: None
//
// Revision History:
// Rev 1.0.0 - (crabill) First created December 25, 2006.
//
//////////////////////////////////////////////////////////////////////////////
//
// LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".
// Xilinx and its licensors make and you receive no warranties or conditions,
// express, implied, statutory or otherwise, and Xilinx specifically disclaims
// any implied warranties of merchantability, non-infringement, or fitness for
// a particular purpose. Xilinx does not warrant that the functions contained
// in these designs will meet your requirements, or that the operation of
// these designs will be uninterrupted or error free, or that defects in the
// designs will be corrected. Furthermore, Xilinx does not warrant or make any
// representations regarding use or the results of the use of the designs in
// terms of correctness, accuracy, reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable
// for any loss of data, lost profits, cost or procurement of substitute goods
// or services, or for any special, incidental, consequential, or indirect
// damages arising from the use or operation of the designs or accompanying
// documentation, however caused and on any theory of liability. This
// limitation will apply even if Xilinx has been advised of the possibility
// of such damage. This limitation shall apply not-withstanding the failure
// of the essential purpose of any limited remedies herein.
//
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module debnce
(
input wire sync,
input wire clk,
output reg event_on,
output reg event_off
);
//******************************************************************//
// Implement debouncing. //
//******************************************************************//
reg [15:0] ctr;
reg dly;
wire sat;
assign sat = (ctr == 16'hffff);
always @(posedge clk)
begin : saturating_counter
case ({sync, sat})
0: ctr <= 0;
1: ctr <= 0;
2: ctr <= ctr + 1;
endcase
dly <= sat;
event_on <= !dly && sat;
event_off <= !sat && dly;
end
//******************************************************************//
// //
//******************************************************************//
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; vector<pair<long long, long long> > g[N]; int n, m; stack<int> st; bool inStack[N]; int cmp[N], ind[N], low[N], cnt, cont; void dfs(int x) { ind[x] = low[x] = cnt++; st.push(x); inStack[x] = true; for (int i = 0; i < g[x].size(); ++i) { int y = g[x][i].first; if (ind[y] == -1) { dfs(y); low[x] = min(low[x], low[y]); } else if (inStack[y]) { low[x] = min(low[x], ind[y]); } } if (ind[x] == low[x]) { int idx; do { idx = st.top(); st.pop(); inStack[idx] = 0; cmp[idx] = cont; } while (idx != x); cont++; } } inline void initTarjan() { memset(ind, -1, sizeof ind); } bool componentProcessed[N]; vector<pair<long long, long long> > compressedGraph[N]; long long componentCost[N]; inline long long getCost(long long x) { long long lo = 0, hi = 1000000LL; while (lo < hi) { long long md = (lo + hi + 1) >> 1; if ((md * (md - 1)) / 2LL <= x) lo = md; else hi = md - 1; } return x * lo - lo * (lo + 1) * (lo - 1) / 6LL; } long long pd[N]; long long func(int x) { if (pd[x] != -1) return pd[x]; pd[x] = componentCost[x]; for (int i = 0; i < compressedGraph[x].size(); ++i) { int y = compressedGraph[x][i].first; long long w = compressedGraph[x][i].second; pd[x] = max(pd[x], func(y) + w + componentCost[x]); } return pd[x]; } int main() { initTarjan(); scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) { int a, b, c; scanf( %d %d %d , &a, &b, &c); g[a].emplace_back(make_pair(b, c)); } for (int i = 1; i <= n; ++i) { if (ind[i] == -1) dfs(i); } int s; scanf( %d , &s); for (int x = 1; x <= n; ++x) { for (int j = 0; j < g[x].size(); ++j) { int y = g[x][j].first; if (cmp[x] != cmp[y]) compressedGraph[cmp[x]].emplace_back(make_pair(cmp[y], g[x][j].second)); else componentCost[cmp[x]] += getCost(g[x][j].second); } } memset(pd, -1, sizeof pd); printf( %lld n , func(cmp[s])); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 29; int main() { ios::sync_with_stdio(0); int n; cin >> n; int a[n]; for (int i = 0; i < (n); i++) cin >> a[i]; int b[n]; for (int i = 0; i < (n); i++) cin >> b[i]; set<int> rem; int top = 0; for (int i = 0; i < (n); i++) { int curr = 0; if (rem.find(b[i]) != rem.end()) { cout << curr << ; continue; } while (top < n) { if (a[top + curr] != b[i]) { rem.insert(a[top + curr]); ++curr; } else { rem.insert(a[top + curr]); break; } } top += curr + 1; cout << curr + 1 << ; } cout << endl; return 0; }
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//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_backend_lut_fifo.v
//
// *Module Description:
// Simple FIFO module
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_reg_fifo (
// OUTPUTs
fifo_cnt_o, // Fifo counter
fifo_empty_cnt_o, // Fifo empty words counter
fifo_data_o, // Read data output
fifo_done_evt_o, // Fifo has been emptied
fifo_empty_o, // Fifo is currentely empty
fifo_full_o, // Fifo is currentely full
fifo_ovfl_evt_o, // Fifo overflow event
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
fifo_data_i, // Read data input
fifo_enable_i, // Enable fifo (flushed when disabled)
fifo_pop_i, // Pop data from the fifo
fifo_push_i // Push new data to the fifo
);
// OUTPUTs
//=========
output [3:0] fifo_cnt_o; // Fifo counter
output [3:0] fifo_empty_cnt_o; // Fifo empty word counter
output [15:0] fifo_data_o; // Read data output
output fifo_done_evt_o; // Fifo has been emptied
output fifo_empty_o; // Fifo is currentely empty
output fifo_full_o; // Fifo is currentely full
output fifo_ovfl_evt_o; // Fifo overflow event
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input [15:0] fifo_data_i; // Read data input
input fifo_enable_i; // Enable fifo (flushed when disabled)
input fifo_pop_i; // Pop data from the fifo
input fifo_push_i; // Push new data to the fifo
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
// Some parameter(s)
parameter FIFO_EMPTY = 4'h0,
FIFO_FULL = 4'hf;
// Others
reg [3:0] fifo_cnt_o;
wire [3:0] fifo_cnt_nxt;
//============================================================================
// 5) FIFO COUNTER
//============================================================================
// Control signals
assign fifo_full_o = (fifo_cnt_o == FIFO_FULL);
assign fifo_empty_o = (fifo_cnt_o == FIFO_EMPTY);
assign fifo_empty_cnt_o = (FIFO_FULL-fifo_cnt_o);
wire fifo_push_int = fifo_push_i & !fifo_full_o;
wire fifo_pop_int = fifo_pop_i & !fifo_empty_o;
// Events
assign fifo_done_evt_o = ~fifo_empty_o & (fifo_cnt_nxt == FIFO_EMPTY);
assign fifo_ovfl_evt_o = fifo_push_i & fifo_full_o;
// Fifo counter
assign fifo_cnt_nxt = ~fifo_enable_i ? FIFO_EMPTY : // Initialize
(fifo_push_int & fifo_pop_int) ? fifo_cnt_o : // Keep value (pop & push at the same time)
fifo_push_int ? fifo_cnt_o + 3'h1 : // Push
fifo_pop_int ? fifo_cnt_o - 3'h1 : // Pop
fifo_cnt_o; // Hold
always @(posedge mclk or posedge puc_rst)
if (puc_rst) fifo_cnt_o <= FIFO_EMPTY;
else fifo_cnt_o <= fifo_cnt_nxt;
//============================================================================
// 6) FIFO MEMORY & RD/WR POINTERS
//============================================================================
// Write pointer
reg [3:0] wr_ptr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wr_ptr <= 4'h0;
else if (~fifo_enable_i) wr_ptr <= 4'h0;
else if (fifo_push_int)
begin
if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 4'h0;
else wr_ptr <= wr_ptr + 4'h1;
end
// Memory
reg [15:0] fifo_mem [0:15];
always @(posedge mclk or posedge puc_rst)
if (puc_rst)
begin
fifo_mem[0] <= 16'h0000;
fifo_mem[1] <= 16'h0000;
fifo_mem[2] <= 16'h0000;
fifo_mem[3] <= 16'h0000;
fifo_mem[4] <= 16'h0000;
fifo_mem[5] <= 16'h0000;
fifo_mem[6] <= 16'h0000;
fifo_mem[7] <= 16'h0000;
fifo_mem[8] <= 16'h0000;
fifo_mem[9] <= 16'h0000;
fifo_mem[10] <= 16'h0000;
fifo_mem[11] <= 16'h0000;
fifo_mem[12] <= 16'h0000;
fifo_mem[13] <= 16'h0000;
fifo_mem[14] <= 16'h0000;
fifo_mem[15] <= 16'h0000;
end
else if (fifo_push_int)
begin
fifo_mem[wr_ptr] <= fifo_data_i;
end
// Read pointer
reg [3:0] rd_ptr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) rd_ptr <= 4'h0;
else if (~fifo_enable_i) rd_ptr <= 4'h0;
else if (fifo_pop_int)
begin
if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 4'h0;
else rd_ptr <= rd_ptr + 4'h1;
end
assign fifo_data_o = fifo_mem[rd_ptr];
endmodule // ogfx_reg_fifo
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> hl(n, -1); vector<pair<pair<int, int>, int>> v(n); for (int i = (0); i < (n); i++) { cin >> v[i].first.first >> v[i].first.second; v[i].second = i; } sort(v.begin(), v.end()); for (int i = (0); i < (n); i++) { hl[v[i].second] = v[i].first.first; for (int j = (i + 1); j < (n); j++) { if (v[j].first.first == v[i].first.first) { v[j].first.first++; } else { break; } } sort(v.begin(), v.end()); } for (int i = (0); i < (n); i++) cout << hl[i] << ; }
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#include <bits/stdc++.h> using namespace std; const int N = 21; void solve() { int n, x; cin >> n; vector<int> cnt(N, 0); for (int i = 0; i < n; i++) { cin >> x; for (int j = 0; j < N; j++) { if (x >> j & 1) cnt[j]++; } } long long ans = 0; for (int i = 0; i < n; i++) { x = 0; for (int j = N - 1; j >= 0; j--) { if (cnt[j]) { cnt[j]--; x |= (1 << j); } } ans += (x * 1LL * x); } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } }
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_fmul_32ns_32ns_32_4_max_dsp
#(parameter
ID = 1,
NUM_STAGE = 4,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
feedforward_ap_fmul_2_max_dsp_32 feedforward_ap_fmul_2_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, n; cin >> a >> b >> n; bool aa = 0, bb = 1; if (a < b) swap(a, b), swap(aa, bb); for (int i = 0; i < a - (n + 1) / 2 - (n % 2 == 0); i++) cout << aa; for (int i = 0; i < (n + 1) / 2; i++) cout << aa << bb; for (int i = 0; i < b - (n + 1) / 2; i++) cout << bb; if (n % 2 == 0) cout << aa; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1000000; int centroid[maxn]; int parent[maxn]; int subtree[maxn]; int heaviest[maxn]; vector<int> graph[maxn]; void dfs(int u, int p = 0) { parent[u] = p; subtree[u] = 1; heaviest[u] = 0; int vert = 0; for (auto v : graph[u]) { if (v == p) continue; dfs(v, u); subtree[u] += subtree[v]; if (subtree[v] > heaviest[u]) { heaviest[u] = subtree[v]; vert = v; } } if ((int)graph[u].size() == 0 or (2 * heaviest[u] <= subtree[u])) centroid[u] = u; else { int curr = centroid[vert]; centroid[u] = curr; while (curr != u) { int P = parent[curr]; int rem = subtree[u] - subtree[P]; if (2 * heaviest[P] > subtree[u]) break; if (2 * rem <= subtree[u]) centroid[u] = P; curr = parent[curr]; } } } int main() { int n; scanf( %d , &n); int q; scanf( %d , &q); for (int i = 2; i <= n; i++) { int p; scanf( %d , &p); graph[p].push_back(i); } dfs(1); while (q--) { int v; scanf( %d , &v); printf( %d n , centroid[v]); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int kN = 2e5 + 10; int N, M; struct Ele { long long len; char c; void read() { len = 0; char s[30]; scanf( %s , s); for (int i = 0; s[i]; i++) { if (s[i] == - ) { c = s[i + 1]; break; } else { len *= 10; len += s[i] - 0 ; } } } bool operator==(const Ele &e) const { return len == e.len && c == e.c; } bool operator!=(const Ele &e) const { return !((*this) == e); } }; Ele A[kN], B[kN], T[kN]; int tn; void merge(Ele a[], int &n) { int p = 0; for (int i = 1; i <= n; i++) { if (p && a[p].c == a[i].c) { a[p].len += a[i].len; } else { p++; a[p] = a[i]; } } n = p; } bool check(int i, int j) { return i >= 1 && i <= N && A[i].len >= B[j].len && A[i].c == B[j].c; } int lst[kN]; int main() { scanf( %d %d , &N, &M); for (int i = 1; i <= N; i++) A[i].read(); for (int i = 1; i <= M; i++) B[i].read(); merge(A, N); merge(B, M); for (int i = 2; i < M; i++) T[++tn] = B[i]; long long ans = 0; if (M == 1) { for (int i = 1; i <= N; i++) { if (A[i].c == B[1].c && A[i].len >= B[1].len) { ans += A[i].len - B[1].len + 1; } } } else { lst[1] = 0; for (int i = 2; i <= tn; i++) { int p = lst[i - 1]; while (p && T[p + 1] != T[i]) p = lst[p]; if (T[p + 1] == T[i]) p++; lst[i] = p; } int j = 0; for (int i = 1; i <= N; i++) { while (j < tn && j && T[j + 1] != A[i]) j = lst[j]; if (tn && T[j + 1] == A[i]) j++; if (j == tn) { if (check(i + 1, M) && check(i - tn, 1)) { ans++; } j = lst[j]; } } } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 3005; const double PI = acos(-1); struct Point { ll x, y; }; inline Point operator+(const Point &a, const Point &b) { return {a.x + b.x, a.y + b.y}; } inline Point operator-(const Point &a, const Point &b) { return {a.x - b.x, a.y - b.y}; } inline ll cross(const Point &a, const Point &b) { return a.x * b.y - a.y * b.x; } inline double polar(const Point &a) { return atan2(a.y, a.x); } int n, m, r[N]; Point a[N], b[N]; void solve(vector<int> va, vector<pair<int, int>> vb) { while (1) { if (va.size() == 1) { for (auto &i : vb) cout << i.first << << va[0] << endl; return; } if (vb.size() == 1) { for (auto &i : va) cout << vb[0].first << << i << endl; return; } for (int i = 0; i < int(vb.size()); i++) if (vb[i].second > vb[0].second) swap(vb[i], vb[0]); vector<pair<double, pair<int, int>>> tmp((va.size() + vb.size()) * 2); int idx = 0; for (int i = 0; i < int(va.size()); i++) tmp[++idx] = {polar(a[va[i]] - b[vb[0].first]), {va[i], 0}}; for (int i = 1; i < int(vb.size()); i++) tmp[++idx] = {polar(b[vb[i].first] - b[vb[0].first]), vb[i]}; sort(tmp.begin() + 1, tmp.begin() + idx + 1); for (int i = 1; i <= idx; i++) tmp[idx + i] = tmp[i], tmp[idx + i].first += 2 * PI; for (int i = 1, j = 0, sum = 0; i <= idx; sum -= 1 - tmp[i++].second.second) { if (sum >= 1 && sum <= vb[0].second - 1) { vector<int> xa; vector<pair<int, int>> xb; xb.push_back({vb[0].first, sum}); vb[0].second -= sum; vb.resize(1); va.clear(); for (int k = i; k <= j; k++) if (!tmp[k].second.second) xa.push_back(tmp[k].second.first); else xb.push_back(tmp[k].second); for (int k = j + 1; k <= i + idx - 1; k++) if (!tmp[k].second.second) va.push_back(tmp[k].second.first); else vb.push_back(tmp[k].second); if (xa.size() + xb.size() > va.size() + vb.size()) swap(xa, va), swap(xb, vb); solve(xa, xb); break; } while (tmp[j + 1].first - tmp[i].first <= PI) sum += 1 - tmp[++j].second.second; if (sum >= 1 && sum <= vb[0].second - 1) { vector<int> xa; vector<pair<int, int>> xb; xb.push_back({vb[0].first, sum}); vb[0].second -= sum; vb.resize(1); va.clear(); for (int k = i; k <= j; k++) if (!tmp[k].second.second) xa.push_back(tmp[k].second.first); else xb.push_back(tmp[k].second); for (int k = j + 1; k <= i + idx - 1; k++) if (!tmp[k].second.second) va.push_back(tmp[k].second.first); else vb.push_back(tmp[k].second); if (xa.size() + xb.size() > va.size() + vb.size()) swap(xa, va), swap(xb, vb); solve(xa, xb); break; } } } } int main() { ios::sync_with_stdio(false); int T; cin >> T; while (T--) { int n, m; cin >> n >> m; vector<int> va; vector<pair<int, int>> vb; for (int i = 1; i <= m; i++) cin >> r[i]; for (int i = 1; i <= n; i++) cin >> a[i].x >> a[i].y, va.push_back(i); for (int i = 1; i <= m; i++) cin >> b[i].x >> b[i].y, vb.push_back({i, r[i]}); cout << YES << endl; solve(va, vb); } return 0; }
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
mulAddRecF16_add (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
wire [16:0] recF16_1 = 'h08000;
mulAddRecFN#(5, 11)
mulAddRecFN(
control, 2'b0, a, recF16_1, b, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF32_add (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
wire [32:0] recF32_1 = 33'h080000000;
mulAddRecFN#(8, 24)
mulAddRecFN(
control, 2'b0, a, recF32_1, b, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF64_add (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
wire [64:0] recF64_1 = 65'h08000000000000000;
mulAddRecFN#(11, 53)
mulAddRecFN(
control, 2'b0, a, recF64_1, b, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF128_add (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] recF128_1 = 129'h080000000000000000000000000000000;
mulAddRecFN#(15, 113)
mulAddRecFN(
control, 2'b0, a, recF128_1, b, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF16_mul (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
wire [16:0] zeroAddend = {a[16] ^ b[16], 16'b0};
mulAddRecFN#(5, 11)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF32_mul (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
wire [32:0] zeroAddend = {a[32] ^ b[32], 32'b0};
mulAddRecFN#(8, 24)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF64_mul (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
wire [64:0] zeroAddend = {a[64] ^ b[64], 64'b0};
mulAddRecFN#(11, 53)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF128_mul (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0};
mulAddRecFN#(15, 113)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF16 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [16:0] a,
input [16:0] b,
input [16:0] c,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(5, 11)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF32 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [32:0] a,
input [32:0] b,
input [32:0] c,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(8, 24)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF64 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [64:0] a,
input [64:0] b,
input [64:0] c,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(11, 53)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF128 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [128:0] a,
input [128:0] b,
input [128:0] c,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(15, 113)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 + 10; int n, d[MAXN], id[MAXN]; bool b[MAXN][MAXN]; bool cmp(int a, int b) { if (d[a] > d[b]) return true; if (d[a] < d[b]) return false; return a < b; } int main() { scanf( %d , &n); if (n == 4) puts( -1 ), exit(0); b[3][1] = b[1][2] = b[2][3] = 1; d[1] = d[2] = d[3] = 1; for (int i = 4; i <= n; ++i) { for (int j = 1; j < i; ++j) id[j] = j; sort(id + 1, id + i, cmp); for (int j = 1; j <= i / 2; ++j) b[id[j]][i] = 1, ++d[i]; for (int j = i / 2 + 1; j < i; ++j) b[i][id[j]] = 1, ++d[id[j]]; } for (int i = 1; i <= n; ++i, puts( )) for (int j = 1; j <= n; ++j) printf( %d , b[i][j]); fclose(stdin); fclose(stdout); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_TB_V
`define SKY130_FD_SC_MS__DFSBP_TB_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfsbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__dfsbp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n >> x; int cnt = 0; for (int j = 1; j * j <= x; j++) { if (x % j == 0) { if (j <= n && x / j <= n) { if (j * j == x) cnt++; else cnt += 2; } } } cout << cnt << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100100; const int INF = 1000000000; int n, m, numV; int head[MAXN], e_cnt, s, t; bool volunt[MAXN]; struct Edg { int v, next; } edg[MAXN * 4]; inline void add(int a, int b) { edg[e_cnt].v = b; edg[e_cnt].next = head[a]; head[a] = e_cnt++; } int dis[MAXN]; bool inq[MAXN]; bool spfa(int x) { for (int i = 1; i <= n; ++i) dis[i] = INF; dis[s] = 0; queue<int> q; q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); inq[u] = 0; if (volunt[u]) dis[u] = 0; for (int i = head[u]; i != -1; i = edg[i].next) { int v = edg[i].v; if (dis[v] > dis[u] + 1 && dis[u] + 1 <= x) { dis[v] = dis[u] + 1; if (!inq[v]) q.push(v); inq[v] = 1; } } } return dis[t] != INF; } int main() { while (scanf( %d%d%d , &n, &m, &numV) != EOF) { memset(volunt, 0, sizeof(volunt)); e_cnt = 0; memset(head, -1, sizeof(head)); for (int i = 0, j; i < numV; ++i) { scanf( %d , &j); volunt[j] = 1; } for (int i = 0; i < m; ++i) { int ta, tb; scanf( %d%d , &ta, &tb); add(ta, tb); add(tb, ta); } scanf( %d%d , &s, &t); int rt(m), lt(1), ans(-1); while (lt <= rt) { int mid = (lt + rt) >> 1; if (spfa(mid)) { rt = mid - 1; ans = mid; } else lt = mid + 1; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> const int inf = (1ll << 30) - 1; const int maxn = (int)1e5 + 10; using namespace std; int n; vector<int> g[100100]; int a[100100]; int in[100100]; int out[100100]; int dp[100100]; map<int, int> t[400400]; int timer = 0; void dfs(int v) { in[v] = timer; a[timer] = v; timer++; dp[v] = 1; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; dfs(to); dp[v] += dp[to]; } out[v] = timer - 1; } void build(int v, int l, int r) { if (l == r) { t[v][dp[a[l]]]++; } else { int mid = (l + r) >> 1; build(v * 2, l, mid); build(v * 2 + 1, mid + 1, r); for (int i = l; i <= r; i++) t[v][dp[a[i]]]++; } } int getu(int v, int l, int r, int tl, int tr, int x) { if (tl > tr) return inf; if (l == tl && tr == r) { map<int, int>::iterator pos = t[v].lower_bound(x); if (pos != t[v].end()) return pos->first; return inf; } int mid = (l + r) >> 1; return min(getu(v * 2, l, mid, tl, min(tr, mid), x), getu(v * 2 + 1, mid + 1, r, max(tl, mid + 1), tr, x)); } int getd(int v, int l, int r, int tl, int tr, int x) { if (tl > tr) return -inf; if (l == tl && tr == r) { map<int, int>::iterator pos = t[v].lower_bound(x + 1); if (pos != t[v].begin()) return (--pos)->first; return -inf; } int mid = (l + r) >> 1; return max(getd(v * 2, l, mid, tl, min(tr, mid), x), getd(v * 2 + 1, mid + 1, r, max(tl, mid + 1), tr, x)); } void ADD(int v, int l, int r, int pos, int x) { t[v][x]++; if (l == r) { return; } int mid = (l + r) >> 1; if (pos <= mid) { ADD(v * 2, l, mid, pos, x); } else ADD(v * 2 + 1, mid + 1, r, pos, x); } void DEL(int v, int l, int r, int pos, int x) { t[v][x]--; if (t[v][x] == 0) t[v].erase(x); if (l == r) { return; } int mid = (l + r) >> 1; if (pos <= mid) { DEL(v * 2, l, mid, pos, x); } else DEL(v * 2 + 1, mid + 1, r, pos, x); } int ans[100100]; set<int> PA; void calc(int v, int szz) { int cv = dp[v]; DEL(1, 0, n - 1, in[v], cv); PA.insert(dp[v]); for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; cv = szz + dp[v] - dp[to]; calc(to, szz + dp[v] - dp[to]); } PA.erase(dp[v]); vector<pair<int, int> > cur; if (szz) cur.push_back(make_pair(szz, 0)); for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; cur.push_back(make_pair(dp[to], to)); } sort(cur.begin(), cur.end()); int d = cur.size(); if (cur.size() <= 1 || cur[d - 2].first == cur.back().first) { ans[v] = cur.back().first; ADD(1, 0, n - 1, in[v], dp[v]); return; } ans[v] = cur[d - 1].first; int sz = (cur[0].first + cur[d - 1].first) / 2 - cur[0].first; int xx; int V = cur[d - 1].second; if (V) xx = getu(1, 0, n - 1, in[V], out[V], sz); else { xx = min(getu(1, 0, n - 1, 0, in[v] - 1, sz), getu(1, 0, n - 1, out[v] + 1, n - 1, sz)); set<int>::iterator it = PA.lower_bound(sz + dp[v]); if (it != PA.end()) xx = min(xx, *it - dp[v]); } ans[v] = min(ans[v], max(cur[d - 2].first, max(cur[0].first + xx, cur[d - 1].first - xx))); if (V) xx = getd(1, 0, n - 1, in[V], out[V], sz); else { xx = max(getd(1, 0, n - 1, 0, in[v] - 1, sz), getd(1, 0, n - 1, out[v] + 1, n - 1, sz)); set<int>::iterator it = PA.upper_bound(sz + dp[v]); if (it != PA.begin()) xx = max(xx, *(--it) - dp[v]); } ans[v] = min(ans[v], max(cur[d - 2].first, max(cur[0].first + xx, cur[d - 1].first - xx))); ADD(1, 0, n - 1, in[v], dp[v]); } void solve() { scanf( %d , &n); int root = 0; for (int i = 1, x, y; i <= n; i++) { scanf( %d%d , &x, &y); if (x) g[x].push_back(y); else root = y; } if (n == 1) { printf( 0 n ); return; } if (n == 2) { printf( 1 n1 n ); return; } dfs(root); build(1, 0, n - 1); calc(root, 0); for (int i = 1; i <= n; i++) { printf( %d n , ans[i]); } } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; string second; cin >> second; int c = 0, d = 0; for (auto u : second) { if (u == n ) c++; else if (u == z ) d++; } while (c--) cout << 1 << ; while (d--) cout << 0 << ; cout << n ; return 0; }
|
#include <bits/stdc++.h> void swap(int *, int *); int main() { int i, j, k; int n; scanf( %d , &n); int arr[n]; for (i = 0; i < n; i++) { scanf( %d , &arr[i]); } int limit = n / 2; for (i = 0; i < limit; i++) { if (i % 2 == 0) { swap(&arr[i], &arr[n - i - 1]); } } for (i = 0; i < n; i++) { printf( %d , arr[i]); } } void swap(int *a, int *b) { int t; t = *a; *a = *b; *b = t; }
|
#include <bits/stdc++.h> using namespace std; void read(int &x) { x = 0; int f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -f; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; x *= f; } void print(int x) { if (x < 0) putchar( - ), x = -x; if (!x) return; print(x / 10), putchar(x % 10 + 48); } void write(int x) { if (!x) putchar( 0 ); else print(x); putchar( n ); } const int maxn = 1e6 + 10; const int inf = 1e9; const double eps = 1e-8; const int mod = 1e9 + 7; int v[maxn]; map<pair<int, int>, int> s; int n, t, z[maxn], ans[maxn]; int query(int x, int y) { if (x > y) swap(x, y); if (s[make_pair(x, y)]) return s[make_pair(x, y)]; printf( ? %d %d n , x, y); fflush(stdout); int a; read(a); assert(a != -1); return s[make_pair(x, y)] = a; } int get(int x) { int a = (1 << t) - 1; for (int i = 0; i < t; i++) if (x != z[i]) a &= query(z[i], x); else if ((a >> i) & 1) a ^= 1 << i; return a; } int main() { srand(time(0)); read(n); for (int i = 1; i < n; i <<= 1) t++; while (1) { int x = rand() % n + 1, y = rand() % n + 1, bo = 1; for (int i = 0; i < t; i++) if (!z[i]) bo = 0; if (bo) break; if (x == y) continue; int a = query(x, y); for (int i = 0; i < t; i++) if (!((a >> i) & 1)) z[i] = x; } int a = get(1), pre = 1; for (int i = 2; i <= n; i++) if (query(pre, i) == a) a = get(i), pre = i; for (int i = 1; i <= n; i++) if (i != pre) ans[i] = query(pre, i); printf( ! ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); puts( ); return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, tmp_ara1, tmp_ara2; vector<long long> ara1(2000007, -1), ara2(2000007, -1), ans(200007, -1), in_front; cin >> n; for (i = 1; i <= n; i++) { cin >> tmp_ara1 >> tmp_ara2; ara1[tmp_ara1] = tmp_ara2; ara2[tmp_ara2] = tmp_ara1; in_front.push_back(tmp_ara1); } long long key = 0; for (i = 2; i <= n; i += 2) { ans[i] = ara1[key]; key = ara1[key]; } long long first; for (i = 0; i < n; i++) { if (ara2[in_front[i]] == -1) { first = in_front[i]; break; } } key = first; ans[1] = first; for (i = 3; i <= n; i += 2) { ans[i] = ara1[key]; key = ara1[key]; } for (i = 1; i <= n; i++) { cout << ans[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; scanf( %d%d , &m, &n); int t[m][n]; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) scanf( %d , &t[i][j]); } int latest[m]; fill(latest, latest + m, 0); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { latest[j] += t[j][i]; if (j != m - 1) latest[j + 1] = max(latest[j], latest[j + 1]); } } for (int i = 0; i < m; i++) { printf( %d , latest[i]); if (i != m - 1) putchar( ); } puts( ); }
|
// -*- Mode: Verilog -*-
// Filename : test_tools.v
// Description : Tools to help with test cases
// Author : Philip Tracton
// Created On : Wed May 27 21:11:18 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed May 27 21:11:18 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module test_tools (/*AUTOARG*/ ) ;
//
// Registers
//
reg test_passed = 1'b0;
reg test_failed = 1'b0;
reg test_done = 1'b0;
reg [31:0] test_fail_count = 32'h0000_0000;
//
// A test case can assert test_passed to signal a succesful
// end to the test. This will terminate the test.
//
always @(posedge test_passed) begin
$display("Test Passed @ %d", $time);
#100 $finish;
end
//
// A test case can assert test_failed to signal a failing
// end to the test. This will terminate the test.
//
always @(posedge test_failed) begin
$display("Test Failed @ %d", $time);
#100 $finish;
end
//
// A test case can assert test_done to signal to figure out
// if the test case passed or failed and then terminate the simulation
//
always @(posedge test_done) begin
if (test_fail_count) begin
test_failed <= 1'b1;
end else begin
test_passed <= 1'b1;
end
end
//
// Task: test_case
//
// dstring -- String to $display to user
// value -- the measured data
// expected -- the expected data, if matches value then we passed, else fail
//
task test_case;
input [32*8-1:0] dstring;
input [31:0] value;
input [31:0] expected;
begin
if (value !== expected) begin
test_fail_count <= test_fail_count + 1;
end
$display("%s\t\t0x%h\t\t0x%h\t\t", dstring, value,expected );
end
endtask // if
endmodule // test_tools
|
#include <bits/stdc++.h> int vi[60], ho[60]; int main() { int n, k, i; int x, y; scanf( %d , &n); for (k = 1; k <= n * n; k++) { scanf( %d%d , &x, &y); if (vi[x] || ho[y]) continue; vi[x] = 1; ho[y] = 1; printf( %d , k); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, k, l; cin >> n >> i >> j >> k >> l; int man = (abs(k - i) + abs(l - j)); if (i == n && k == 0 || k == n && i == 0) cout << min(man + 2 * min(n - j, n - l), man + 2 * min(j, l)); else if (j == n && l == 0 || l == n && j == 0) cout << min(man + 2 * min(n - k, n - i), man + 2 * min(k, i)); else cout << man; }
|
#include <bits/stdc++.h> using namespace std; int prime[1000100]; void get_prime() { for (int i = 2; i < 1000100; i++) { if (!prime[i]) { for (int j = i * 2; j < 1000100; j += i) { prime[j] = i; } } } for (int i = 2; i < 1000100; i++) { if (!prime[i]) { prime[i] = 1; } } } int main() { get_prime(); int x2; cin >> x2; int ans = 0x3f3f3f3f3f; for (int i = x2 - prime[x2] + 1; i <= x2; i++) { ans = min(ans, i - prime[i] + 1); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { priority_queue<pair<int, int> > pq1, pq2; int n, w; cin >> n; for (int i = 0; i < n; i++) cin >> w, pq1.push({-w, i}); n <<= 1; for (int i = 0; i < n; i++) { char ch; cin >> ch; pair<int, int> cur; int ret; if (ch == 0 ) cur = pq1.top(), ret = cur.second, pq2.push({-cur.first, cur.second}), pq1.pop(); else ret = pq2.top().second, pq2.pop(); cout << ret + 1 << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int ans; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) { int k = i ^ j; if (k >= j && k <= n && i + j > k && i + k > j && j + k > i) ans++; } cout << ans; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:52:59 10/11/2013
// Design Name:
// Module Name: FSM_Main
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Main(
input clock,
input reset,
input start,
input v_sync,
input perdio,
output actualizar_bola,
output actualizar_barra,
output revisar_bordes_bola,
output revisar_bordes_barra,
output reg revisar_estado,
output reg reset_bola,
output reg reset_barra);
/** Indica que la barra esta realizando su logica */
reg start_barra, start_ball;
wire busy_barra, busy_ball;
/** Prueba de la maquina de estados de la barra */
FSM_Barra fsm_barra(
.clock(clock),
.reset(reset),
.start_barra(start_barra),
.busy_barra(busy_barra),
.actualizar_barra(actualizar_barra),
.revisar_bordes_barra(revisar_bordes_barra)
);
/** Prueba de la maquina de estados de la bola */
FSM_Bola fsm_bola(
.clock(clock),
.reset(reset),
.start_ball(start_ball),
.busy_ball(busy_ball),
.actualizar_bola(actualizar_bola),
.revisar_bordes_bola(revisar_bordes_bola)
);
//Definimos los estados de la FSM
parameter STATE_0 = 0;
parameter STATE_1 = 1;
parameter STATE_2 = 2;
parameter STATE_3 = 3;
parameter STATE_4 = 4;
parameter STATE_5 = 5;
parameter STATE_6 = 6;
parameter STATE_7 = 7;
//Estado en que se encuentra actualmente
reg [2:0] state;
//display se utiliza para hacer que solo se modifique la posicion una vez
//por cada vsync
reg displayed;
initial
begin
state <= STATE_0;
start_barra <= 1'b0;
start_ball <= 1'b0;
displayed <= 0;
reset_bola <= 1'b0;
reset_barra <= 1'b0;
revisar_estado <= 1'b0;
end
always@(posedge clock or posedge reset)
begin
if(reset)
begin
state <= STATE_0;
start_barra <= 1'b0;
start_ball <= 1'b0;
displayed <= 1'b0;
reset_bola <= 1'b0;
reset_barra <= 1'b0;
revisar_estado <= 1'b0;
end
else
begin
case(state)
/** Solo espera que se presione start */
STATE_0:
begin
if (start)
begin
reset_barra <= 1'b1;
reset_bola <=1'b1;
state <= STATE_1;
end
end
STATE_1:
begin
reset_barra <= 1'b0;
reset_bola <=1'b0;
revisar_estado <= 1'b1;
state <= STATE_2;
end
/** Espera que se realice el chequeo de estado */
STATE_2:
begin
revisar_estado <= 1'b0;
state <= STATE_3;
end
/** El estado 5 se fija si se perdio el juego*/
STATE_3:
begin
if(perdio)
begin
state <= STATE_0;
end
else
state <= STATE_4;
end
/** Activa las maquinas de la barra y la bola */
STATE_4:
begin
if (v_sync)
begin
if(!displayed)
begin
start_barra <= 1'b1;
start_ball <= 1'b1;
displayed <= 1'b1;
state <= STATE_5;
end
end
else
displayed <= 0;
end
/** Se usa para esperar que busy_barra y busy_ball esten estables */
STATE_5:
begin
state <= STATE_6;
end
/** Desactiva las senales de inicio de las maquinas de estado*/
STATE_6:
begin
/** Para que no vuelvan a empezar se hace cero*/
start_barra <= 1'b0;
start_ball <= 1'b0;
state <= STATE_7;
end
/** El estado 4 espera que termine de moverse la barra y la bola*/
STATE_7:
begin
/**Espera que hayan terminado las posiciones*/
if (!busy_barra && !busy_ball)
begin
state <= STATE_1;
end
end
default:
begin
state <= STATE_0;
end
endcase
end //end del begin antes del case
end //end del always
endmodule
|
/*
-- ============================================================================
-- FILE NAME : gpio.v
-- DESCRIPTION : General Purpose I/O
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "gpio.h"
/********** W
[ **********/
module gpio (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // Zbg
/********** oXC^tF[X **********/
input wire cs_, // `bvZNg
input wire as_, // AhXXg[u
input wire rw, // Read / Write
input wire [`GpioAddrBus] addr, // AhX
input wire [`WordDataBus] wr_data, // «Ýf[^
output reg [`WordDataBus] rd_data, // ÇÝoµf[^
output reg rdy_ // fB
/********** ÄpüoÍ|[g **********/
`ifdef GPIO_IN_CH // üÍ|[gÌÀ
, input wire [`GPIO_IN_CH-1:0] gpio_in // üÍ|[gi§äWX^0j
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÀ
, output reg [`GPIO_OUT_CH-1:0] gpio_out // oÍ|[gi§äWX^1j
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÀ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // üoÍ|[gi§äWX^2j
`endif
);
`ifdef GPIO_IO_CH // üoÍ|[ģä
/********** üoÍM **********/
wire [`GPIO_IO_CH-1:0] io_in; // üÍf[^
reg [`GPIO_IO_CH-1:0] io_out; // oÍf[^
reg [`GPIO_IO_CH-1:0] io_dir; // üoÍûüi§äWX^3j
reg [`GPIO_IO_CH-1:0] io; // üoÍ
integer i; // Ce[^
/********** üoÍMÌp±ãü **********/
assign io_in = gpio_io; // üÍf[^
assign gpio_io = io; // üoÍ
/********** üoÍûü̧ä **********/
always @(*) begin
for (i = 0; i < `GPIO_IO_CH; i = i + 1) begin : IO_DIR
io[i] = (io_dir[i] == `GPIO_DIR_IN) ? 1'bz : io_out[i];
end
end
`endif
/********** GPIO̧ä **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
rd_data <= #1 `WORD_DATA_W'h0;
rdy_ <= #1 `DISABLE_;
`ifdef GPIO_OUT_CH // oÍ|[gÌZbg
gpio_out <= #1 {`GPIO_OUT_CH{`LOW}};
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌZbg
io_out <= #1 {`GPIO_IO_CH{`LOW}};
io_dir <= #1 {`GPIO_IO_CH{`GPIO_DIR_IN}};
`endif
end else begin
/* fB̶¬ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
/* ÇÝoµANZX */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
case (addr)
`ifdef GPIO_IN_CH // üÍ|[gÌÇÝoµ
`GPIO_ADDR_IN_DATA : begin // §äWX^ 0
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IN_CH{1'b0}},
gpio_in};
end
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÇÝoµ
`GPIO_ADDR_OUT_DATA : begin // §äWX^ 1
rd_data <= #1 {{`WORD_DATA_W-`GPIO_OUT_CH{1'b0}},
gpio_out};
end
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÇÝoµ
`GPIO_ADDR_IO_DATA : begin // §äWX^ 2
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IO_CH{1'b0}},
io_in};
end
`GPIO_ADDR_IO_DIR : begin // §äWX^ 3
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IO_CH{1'b0}},
io_dir};
end
`endif
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
/* «ÝANZX */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `WRITE)) begin
case (addr)
`ifdef GPIO_OUT_CH // oÍ|[gÖÌ«±Ý
`GPIO_ADDR_OUT_DATA : begin // §äWX^ 1
gpio_out <= #1 wr_data[`GPIO_OUT_CH-1:0];
end
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÖÌ«±Ý
`GPIO_ADDR_IO_DATA : begin // §äWX^ 2
io_out <= #1 wr_data[`GPIO_IO_CH-1:0];
end
`GPIO_ADDR_IO_DIR : begin // §äWX^ 3
io_dir <= #1 wr_data[`GPIO_IO_CH-1:0];
end
`endif
endcase
end
end
end
endmodule
|
`timescale 1ns / 1ps
module computer(
`ifdef VERILATOR
input clk,
input reset
`endif
);
wire iack;
wire [63:0] iadr;
wire istb;
wire [31:0] idatiL;
wire [63:32] idatiH; // unused; just to make iverilog happy.
wire [63:0] ddato, ddati, dadr;
wire [1:0] dsiz;
wire dwe, dcyc, dstb, dsigned, dack;
wire [11:0] cadr;
wire coe, cwe, cvalid;
wire [63:0] cdato, cdati;
wire STB;
wire [63:0] romQ;
wire [1:0] xsiz;
wire [63:0] xadr;
wire [63:0] xdati, xdato;
wire xstb, xack, xsigned;
// initial begin
// $dumpfile("wtf.vcd"); $dumpvars;
// end
`ifndef VERILATOR
reg clk, reset;
initial begin
clk <= 0;
reset <= 1;
#60; reset <= 0;
end
always begin
#20 clk <= ~clk;
end
`endif
PolarisCPU cpu(
.fence_o(),
.trap_o(),
.cause_o(),
.mepc_o(),
.mpie_o(),
.mie_o(),
.ddat_o(ddato),
.dadr_o(dadr),
.dwe_o(dwe),
.dcyc_o(dcyc),
.dstb_o(dstb),
.dsiz_o(dsiz),
.dsigned_o(dsigned),
.irq_i(1'b0),
.iack_i(iack),
.idat_i(idatiL),
.iadr_o(iadr),
.istb_o(istb),
.dack_i(dack),
.ddat_i(ddati),
.cadr_o(cadr),
.coe_o(coe),
.cwe_o(cwe),
.cvalid_i(cvalid),
.cdat_o(cdato),
.cdat_i(cdati),
.clk_i(clk),
.reset_i(reset)
);
arbiter arbiter(
.idat_i(64'd0), // CPU cannot write via I-port.
.iadr_i(iadr),
.iwe_i(1'b0),
.icyc_i(istb),
.istb_i(istb),
.isiz_i({istb, 1'b0}),
.isigned_i(1'b0),
.iack_o(iack),
.idat_o({idatiH, idatiL}),
.ddat_i(ddato),
.dadr_i(dadr),
.dwe_i(dwe),
.dcyc_i(dcyc),
.dstb_i(dstb),
.dsiz_i(dsiz),
.dsigned_i(dsigned),
.dack_o(dack),
.ddat_o(ddati),
.xdat_o(xdato),
.xadr_o(xadr),
.xwe_o(),
.xcyc_o(),
.xstb_o(xstb),
.xsiz_o(xsiz),
.xsigned_o(xsigned),
.xack_i(xack),
.xdat_i(xdati),
.clk_i(clk),
.reset_i(reset)
);
bridge bridge(
.f_signed_i(xsigned),
.f_siz_i(xsiz),
.f_adr_i(xadr[2:0]),
.f_dat_i(xdato),
.f_dat_o(xdati),
.wb_sel_o(),
.wb_dat_i(romQ),
.wb_dat_o()
);
rom rom(
.A(xadr[11:3]),
.Q(romQ),
.STB(STB)
);
address_decode ad(
.iadr_i(xadr[12]),
.istb_i(xstb),
.iack_o(xack),
.STB_o(STB)
);
output_csr outcsr(
.cadr_i(cadr),
.cvalid_o(cvalid),
.cdat_o(cdati),
.cdat_i(cdato),
.coe_i(coe),
.cwe_i(cwe),
.clk_i(clk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, k, pres[300005], cont[300005]; vector<long long int> fcts[300005]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; long long int tot = 0; pres[1] = 1; for (long long int i = 1; i <= n; ++i) for (int j = 2 * i; j <= n; j += i) fcts[j].push_back(i); for (long long int i = 2; i <= n; ++i) { if (tot >= k) { n = i - 1; break; } tot += fcts[i].size(); cont[i] += fcts[i].size(); for (long long int v : fcts[i]) cont[v]++; pres[i] = 1; } if (tot < k) { cout << No n ; return 0; } set<pair<long long int, long long int> > conts; for (long long int i = 1; i <= n; ++i) conts.insert(make_pair(cont[i], i)); long long int rmv = tot - k; while (rmv) { auto it = conts.lower_bound(make_pair(rmv + 1, -1LL)); if (it == conts.begin()) { cout << No n ; return 0; } it--; pair<long long int, long long int> xp = *it; pres[xp.second] = 0; rmv -= xp.first; conts.erase(it); for (long long int v : fcts[xp.second]) { if (pres[v]) { conts.erase(make_pair(cont[v], v)); cont[v]--; conts.insert(make_pair(cont[v], v)); } } for (long long int v = 2 * xp.second; v <= n; v += xp.second) if (pres[v]) { conts.erase(make_pair(cont[v], v)); cont[v]--; conts.insert(make_pair(cont[v], v)); } } cout << Yes n ; vector<long long int> ans; for (long long int i = 1; i <= n; ++i) if (pres[i]) ans.push_back(i); cout << ans.size() << n ; for (long long int v : ans) cout << v << ; cout << n ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int mod = 1e9 + 7; int sub[N][N][N]; int pref[N][N]; int suff[N][N]; int ans[N]; int pw[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, X; cin >> n >> X; string s; cin >> s; s = & + s; for (int i = 1; i <= n; i++) { if (s[i] == 0 ) sub[0][i][i] = 1; else sub[1][i][i] = 1; } if (s[1] == 0 ) pref[0][1] = 1; else pref[1][1] = 1; if (s[n] == 0 ) suff[0][n] = 1; else suff[1][n] = 1; pw[0] = pw[1] = 2; if (s == &0 ) ans[0] = 1; if (s == &1 ) ans[1] = 1; for (int i = 2; i <= X; i++) { pw[i] = 1ll * pw[i - 1] * pw[i - 2] % mod; for (int l = 1; l <= n; l++) { for (int r = l; r <= n; r++) { sub[i][l][r] = (sub[i - 1][l][r] + sub[i - 2][l][r]) % mod; for (int m = l; m < r; m++) { sub[i][l][r] += 1ll * sub[i - 1][l][m] * sub[i - 2][m + 1][r] % mod; sub[i][l][r] %= mod; } } } for (int l = 1; l <= n; l++) { pref[i][l] = pref[i - 1][l]; pref[i][l] += 1ll * pref[i - 2][l] * pw[i - 1] % mod; pref[i][l] %= mod; for (int x = 1; x < l; x++) { pref[i][l] += 1ll * pref[i - 1][x] * sub[i - 2][x + 1][l] % mod; pref[i][l] %= mod; } } for (int r = 1; r <= n; r++) { suff[i][r] = suff[i - 2][r]; suff[i][r] += 1ll * suff[i - 1][r] * pw[i - 2] % mod; suff[i][r] %= mod; for (int x = r; x < n; x++) { suff[i][r] += 1ll * suff[i - 2][x + 1] * sub[i - 1][r][x] % mod; suff[i][r] %= mod; } } for (int m = 1; m < n; m++) { ans[i] += 1ll * pref[i - 1][m] * suff[i - 2][m + 1] % mod; ans[i] %= mod; } ans[i] += 1ll * ans[i - 1] * pw[i - 2] % mod; ans[i] %= mod; ans[i] += 1ll * ans[i - 2] * pw[i - 1] % mod; ans[i] %= mod; } cout << ans[X] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[300004]; int n, nr, r, Min, poz, f1, f2, ch1, ch2, sol, soli, sol2, i, j, l, v[300004], m[300004]; char s[300004], b[300004]; bool ok1, ok2; int main() { scanf( %d , &n); scanf( %s , &s); nr = 0; Min = 1000000000; for (i = 0; i < n; i++) { if (s[i] == ( ) nr++; else nr--; v[i] = nr; Min = min(Min, v[i]); m[i] = Min; } if (v[n - 1] != 0) { printf( %d n%d %d n , 0, 1, 1); return 0; } poz = 0; if (m[n - 1] < 0) { nr = 0; poz = -1; for (i = (n - 1); i > 0; i--) { if (s[i] == ( ) nr++; else nr--; if ((nr + m[i - 1]) >= 0) { poz = i; break; } } nr = -1; for (j = poz; j < n; j++) b[++nr] = s[j]; for (j = 0; j < poz; j++) b[++nr] = s[j]; } else { for (i = 0; i < n; i++) b[i] = s[i]; } l = 0; r = 0; sol = 0; ch1 = 1; ch2 = 1; nr = 0; for (i = 0; i < n; i++) { if (b[i] == ( ) nr++; else nr--; v[i] = nr; Min = min(Min, v[i]); m[i] = Min; if (nr == 0) { sol++; a[++r].first = l; a[r].second = i; l = i + 1; } } soli = sol; for (i = 1; i <= r; i++) { sol2 = 0; nr = 0; ok1 = false; ok2 = false; for (j = a[i].first + 1; j < a[i].second; j++) { if (b[j] == ( ) { nr++; if (!ok1) { f1 = j; ok1 = true; } } else { nr--; if (!ok2) { f2 = j; ok2 = true; } } if (nr == 0) sol2++; } if ((sol2 + 1) > sol) { sol = sol2 + 1; ch1 = a[i].first; ch2 = a[i].second; } sol2 = 0; nr = 0; f2 = a[i].first + 1; for (j = a[i].first + 1; j < a[i].second; j++) { if (b[j] == ( ) { nr++; if (!ok1) { f1 = j; ok1 = true; } } else { nr--; if (!ok2) { f2 = j; ok2 = true; } } if (nr == 0) { if ((sol2 + soli) > sol) { sol = sol2 + soli; ch1 = f2; ch2 = j; } sol2 = 0; f2 = j + 1; } if (nr == 1) sol2++; } } ch1 = (ch1 + poz) % n + 1; ch2 = (ch2 + poz) % n + 1; printf( %d n%d %d , sol, ch1, ch2); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int c, v0, v1, a, l; cin >> c >> v0 >> v1 >> a >> l; int d = 1; int r = v0; int tmp = v0; while (1) { if (r >= c) break; tmp = tmp + a; if (tmp > v1) tmp = v1; r += (tmp - l); d++; } cout << d << endl; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// adbg_or1k_status_reg.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_or1k_status_reg.v,v $
// Revision 1.2 2010-01-10 22:54:10 Nathan
// Update copyright dates
//
// Revision 1.1 2008/07/22 20:28:31 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:54 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/26 20:52:32 Nathan
// OR1K module tested and working. Added copyright / license info
// to _define files. Other cleanup.
//
//
//
//
`include "adbg_or1k_defines.v"
module adbg_or1k_status_reg (
data_i,
we_i,
tck_i,
bp_i,
rst_i,
cpu_clk_i,
ctrl_reg_o,
cpu_stall_o,
cpu_rst_o
);
input [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
input we_i;
input tck_i;
input bp_i;
input rst_i;
input cpu_clk_i;
output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
output cpu_stall_o;
output cpu_rst_o;
reg cpu_reset;
wire [2:1] cpu_op_out;
reg stall_bp, stall_bp_csff, stall_bp_tck;
reg stall_reg, stall_reg_csff, stall_reg_cpu;
reg cpu_reset_csff;
reg cpu_rst_o;
// Breakpoint is latched and synchronized. Stall is set and latched.
// This is done in the CPU clock domain, because the JTAG clock (TCK) is
// irregular. By only allowing bp_i to set (but not reset) the stall_bp
// signal, we insure that the CPU will remain in the stalled state until
// the debug host can read the state.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i)
stall_bp <= #1 1'b0;
else if(bp_i)
stall_bp <= #1 1'b1;
else if(stall_reg_cpu)
stall_bp <= #1 1'b0;
end
// Synchronizing
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
stall_bp_csff <= #1 1'b0;
stall_bp_tck <= #1 1'b0;
end
else
begin
stall_bp_csff <= #1 stall_bp;
stall_bp_tck <= #1 stall_bp_csff;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
stall_reg_csff <= #1 1'b0;
stall_reg_cpu <= #1 1'b0;
end
else
begin
stall_reg_csff <= #1 stall_reg;
stall_reg_cpu <= #1 stall_reg_csff;
end
end
// bp_i forces a stall immediately on a breakpoint
// stall_bp holds the stall until the debug host acts
// stall_reg_cpu allows the debug host to control a stall.
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
// Writing data to the control registers (stall)
// This can be set either by the debug host, or by
// a CPU breakpoint. It can only be cleared by the host.
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
stall_reg <= #1 1'b0;
else if (stall_bp_tck)
stall_reg <= #1 1'b1;
else if (we_i)
stall_reg <= #1 data_i[0];
end
// Writing data to the control registers (reset)
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
cpu_reset <= #1 1'b0;
else if(we_i)
cpu_reset <= #1 data_i[1];
end
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_reset_csff <= #1 1'b0;
cpu_rst_o <= #1 1'b0;
end
else
begin
cpu_reset_csff <= #1 cpu_reset;
cpu_rst_o <= #1 cpu_reset_csff;
end
end
// Value for read back
assign ctrl_reg_o = {cpu_reset, stall_reg};
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
usb_system_cpu_jtag_debug_module_tck the_usb_system_cpu_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
usb_system_cpu_jtag_debug_module_sysclk the_usb_system_cpu_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic usb_system_cpu_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam usb_system_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// usb_system_cpu_jtag_debug_module_phy.sld_instance_index = 0,
// usb_system_cpu_jtag_debug_module_phy.sld_ir_width = 2,
// usb_system_cpu_jtag_debug_module_phy.sld_mfg_id = 70,
// usb_system_cpu_jtag_debug_module_phy.sld_sim_action = "",
// usb_system_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0,
// usb_system_cpu_jtag_debug_module_phy.sld_sim_total_length = 0,
// usb_system_cpu_jtag_debug_module_phy.sld_type_id = 34,
// usb_system_cpu_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = (c & 15); while (isdigit(c = getchar())) v = (v << 1) + (v << 3) + (c & 15); x = v * f; } inline void read(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = (c & 15); while (isdigit(c = getchar())) v = (v << 1) + (v << 3) + (c & 15); x = v * f; } inline void readc(char &x) { char c; while (((c = getchar()) == ) || c == n ) ; x = c; } int n, m, i, j, dp[18][1 << 18][2][2], w[524289]; void upd(int &x, int y) { x = max(x, y); } int main() { read(n); read(m); for (((i)) = (1); ((i)) <= ((m)); ((i))++) { int x; read(x); x--; w[x] = 1; } memset((dp), (-(0x16)), (sizeof((dp)))); for (((i)) = (0); ((i)) <= (((1 << (n - 1))) - 1); ((i))++) { dp[1][i][w[i * 2]][w[i * 2 + 1]] = w[i * 2] | w[i * 2 + 1]; dp[1][i][w[i * 2 + 1]][w[i * 2]] = w[i * 2] | w[i * 2 + 1]; } for (i = 2; i <= n; i++) { int all = (1 << (n - i)); for (j = 0; j < all; j++) { int a, b, c, d; for (((a)) = (0); ((a)) <= ((2) - 1); ((a))++) for (((b)) = (0); ((b)) <= ((2) - 1); ((b))++) for (((c)) = (0); ((c)) <= ((2) - 1); ((c))++) for (((d)) = (0); ((d)) <= ((2) - 1); ((d))++) { int t = dp[i - 1][j * 2][a][b] + dp[i - 1][j * 2 + 1][c][d]; upd(dp[i][j][a | c][b | d], t + ((b | d) * 2 + (a | c))); if (a | c) upd(dp[i][j][a + c - 1][1], t + ((b | d) + (a | c) + 1)); } } } int mx = 0; for (((i)) = (0); ((i)) <= ((2) - 1); ((i))++) for (((j)) = (0); ((j)) <= ((2) - 1); ((j))++) { upd(mx, dp[n][0][i][j] + (i | j)); } cout << mx << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int max_N = 2e5 + 10; const int l_N = 20; int st[l_N][max_N]; int lg[max_N]; int inp[max_N]; vector<int> bits[30]; int query_max(int i, int j); int main() { { int j = 0; for (int i = 0; i < max_N; ++i) { while ((1 << j) <= i) { ++j; } lg[i] = j - 1; } } int N; scanf( %d , &N); for (int i = 1; i <= N; ++i) { scanf( %d , &inp[i]); st[0][i] = inp[i]; } for (int j = 1; j < l_N; ++j) { for (int i = 1; i + (1 << j) - 1 <= N; ++i) { st[j][i] = max(st[j - 1][i], st[j - 1][i + (1 << (j - 1))]); } } for (int i = 1; i <= N; ++i) { for (int j = 0; j < 30; ++j) { if ((inp[i] >> j) & 1) { bits[j].push_back(i); } } } long long ans = 0; for (int i = 1; i <= N; ++i) { vector<int> or_changes; for (int j = 0; j < 30; ++j) { auto it = lower_bound(bits[j].begin(), bits[j].end(), i); if (it != bits[j].end()) { or_changes.push_back(*it); } } sort(or_changes.begin(), or_changes.end()); or_changes.push_back(N + 1); int cid = *or_changes.begin(); int cor = inp[cid]; for (int j = 1; j < or_changes.size(); ++j) { int L = cid, R = or_changes[j]; int low = L, high = R - 1, mid, best = R; while (low <= high) { mid = (low + high) >> 1; if (query_max(L, mid) >= cor) { best = mid; high = mid - 1; } else { low = mid + 1; } } ans += best - L; cid = R; cor |= inp[R]; } } cout << ans << endl; } int query_max(int i, int j) { int d = lg[j - i + 1]; return max(st[d][i], st[d][j - (1 << d) + 1]); }
|
//
// Author: Xiangfu Liu
//
// This is free and unencumbered software released into the public domain.
// For details see the UNLICENSE file at the root of the source tree.
//
// There are 5 registers
// 0x0 R Firmware version
// 0x1 RW Counter enable/disable, enable: 1, disable: 0
// 0x2 RW Counter write enable, enable: 1, disable: 0
// 0x3 RW Counter write Value
// 0x4 R Counter current value
// LED1, on: stop counting, off: counting
// LED2, on: counter > 0, off: counter == 0
module counter(clk, led1, led2);
input clk;
output led1;
output led2;
reg counter_start = 1'b0;
reg counter_we = 1'b0;
reg [31:0] counter = 32'd0;
reg [31:0] counter_set = 32'd0;
always @(posedge clk)
begin
if (counter_start == 1'b1)
counter <= counter + 1;
if (counter_we == 1'b1)
counter <= counter_set;
end
assign led1 = ~counter_start;
assign led2 = counter;
wire jt_capture, jt_drck, jt_reset, jt_sel;
wire jt_shift, jt_tck, jt_tdi, jt_update, jt_tdo;
BSCAN_SPARTAN6 # (.JTAG_CHAIN(1)) jtag_blk (
.CAPTURE(jt_capture),
.DRCK(jt_drck),
.RESET(jt_reset),
.RUNTEST(),
.SEL(jt_sel),
.SHIFT(jt_shift),
.TCK(jt_tck),
.TDI(jt_tdi),
.TDO(jt_tdo),
.TMS(),
.UPDATE(jt_update)
);
reg [37:0] dr;
reg [3:0] addr = 4'hF;
reg checksum;
wire checksum_valid = ~checksum;
wire jtag_we = dr[36];
wire [3:0] jtag_addr = dr[35:32];
assign jt_tdo = dr[0];
always @ (posedge jt_tck)
begin
if (jt_reset == 1'b1)
begin
dr <= 38'd0;
end
else if (jt_capture == 1'b1)
begin
checksum <= 1'b1;
dr[37:32] <= 6'd0;
addr <= 4'hF;
case (addr)
4'h0: dr[31:0] <= 32'h20120911;
4'h1: dr[0] <= counter_start;
4'h2: dr[0] <= counter_we;
4'h3: dr[31:0] <= counter_set;
4'h4: dr[31:0] <= counter;
default: dr[31:0] <= 32'habcdef01;
endcase
end
else if (jt_shift == 1'b1)
begin
dr <= {jt_tdi, dr[37:1]};
checksum <= checksum ^ jt_tdi;
end
else if (jt_update & checksum_valid)
begin
addr <= jtag_addr;
if (jtag_we)
begin
case (jtag_addr)
4'h1: counter_start <= dr[0];
4'h2: counter_we <= dr[0];
4'h3: counter_set <= dr[31:0];
endcase
end
end
end
endmodule
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: sa1_div.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sa1_div (
clock,
denom,
numer,
quotient,
remain);
input clock;
input [15:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [15:0] remain;
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] quotient = sub_wire0[15:0];
wire [15:0] remain = sub_wire1[15:0];
lpm_divide LPM_DIVIDE_component (
.clock (clock),
.denom (denom),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.aclr (1'b0),
.clken (1'b1));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 8,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 16,
LPM_DIVIDE_component.lpm_widthn = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "8"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "16"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 16 0 INPUT NODEFVAL "denom[15..0]"
// Retrieval info: USED_PORT: numer 0 0 16 0 INPUT NODEFVAL "numer[15..0]"
// Retrieval info: USED_PORT: quotient 0 0 16 0 OUTPUT NODEFVAL "quotient[15..0]"
// Retrieval info: USED_PORT: remain 0 0 16 0 OUTPUT NODEFVAL "remain[15..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 16 0 denom 0 0 16 0
// Retrieval info: CONNECT: @numer 0 0 16 0 numer 0 0 16 0
// Retrieval info: CONNECT: quotient 0 0 16 0 @quotient 0 0 16 0
// Retrieval info: CONNECT: remain 0 0 16 0 @remain 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_div.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_div.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_div.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_div.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_div_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_div_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_1_V
`define SKY130_FD_SC_HDLL__TAPVGND_1_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog wrapper for tapvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__tapvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_dp_macc_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_dp_macc_r(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca,
data_crit_cx_l, data_ncrit_cx_l, rclk, scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input [149:0] data_crit_cx_l;
input [149:0] data_ncrit_cx_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q1_datain_ca, q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire [149:0] data_cx_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
assign data_out_cx_l[149:0] = data_crit_cx_l[149:0] & data_ncrit_cx_l[149:0] & data_cx_l[149:0];
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
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