text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; void read_file(bool outToFile = true) {} int n, m; bool vis[500 + 9][500 + 9]; string s; int l; int x, y; int ans[100000 + 1 + 9]; string alpha = *URDL ; int dij[5][2] = {{0, 0}, {-1, 0}, {0, +1}, {+1, 0}, {0, -1}}; bool valid(int i, int j) { return 0 <= i && i < n && 0 <= j && j < m; } int main() { read_file(); while (scanf( %d%d , &n, &m) != EOF) { scanf( %d%d , &x, &y); x--, y--; memset(vis, 0, sizeof vis); cin >> s; s = * + s; l = s.length(); for (int i = 0; i < l - 1; i++) { int nx, ny; nx = x + dij[alpha.find(s[i])][0]; ny = y + dij[alpha.find(s[i])][1]; if (!valid(nx, ny)) { ans[i] = 0; continue; } x = nx, y = ny; if (!vis[x][y]) { vis[x][y] = 1; ans[i] = 1; } else ans[i] = 0; } int cnt = n * m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cnt -= vis[i][j]; ans[l - 1] = cnt; for (int i = 0; i < l; i++) printf( %d%c , ans[i], n [i == l - 1]); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, e = 0, all = 0, i = 0; cin >> a >> b; c = a; d = b; while (c) { if ((c % 10) > e) { e = c % 10; } c = c / 10; } while (d) { if ((d % 10) > e) { e = d % 10; } d = d / 10; } e = e + 1; while (a) { all = (a % 10) * pow(e, i) + all; a = a / 10; i++; } i = 0; a = b; while (a) { all = (a % 10) * pow(e, i) + all; a = a / 10; i++; } i = 0; while (all) { all = all / e; i++; } cout << i << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 10; long long int vis[N]; vector<vector<int> > v; int dfs(int t) { vis[t] = 1; for (int i = 0; i < v[t].size(); i++) { if (vis[v[t][t]] == 0) { dfs(v[t][i]); } } return 0; } int main() { long long int n, k; cin >> n >> k; long long int y = 1; long long int i = 0; long long int ans = 0, p = 0, d = 1; while (1) { if (d > n) { break; } p++; d = pow(2, p); } k = min(k, p + 1); long double o = 1 - (long double)(1 / (long double)(pow(2, k))); if (k == 1) cout << max(n, d / 2) << endl; else { ans = 2 * (d / 2) - 1; cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_TB_V
`define SKY130_FD_SC_LP__A211OI_TB_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); int n; cin >> n; int a[n][n]; int dp[2][n][n]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int v = 0; v < 2; v++) dp[v][i][j] = -100000000; dp[1][0][0] = a[0][0]; for (int k = 1; k <= n + n - 2; k++) { for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) dp[0][i][j] = dp[1][i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) dp[1][i][j] = -100000000; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (i == j) { if (i > 0 && j > 0) dp[1][i][j] = max(dp[1][i][j], dp[0][i - 1][j - 1] + a[i][k - i]); if (i < k && j < k) dp[1][i][j] = max(dp[1][i][j], dp[0][i][j] + a[i][k - i]); if (i > 0 && j < k) dp[1][i][j] = max(dp[1][i][j], dp[0][i - 1][j] + a[i][k - i]); if (i < k && j > 0) dp[1][i][j] = max(dp[1][i][j], dp[0][i][j - 1] + a[i][k - i]); } else { if (i > 0 && j > 0) dp[1][i][j] = max(dp[1][i][j], dp[0][i - 1][j - 1] + a[i][k - i] + a[j][k - j]); if (i < k && j < k) dp[1][i][j] = max(dp[1][i][j], dp[0][i][j] + a[i][k - i] + a[j][k - j]); if (i > 0 && j < k) dp[1][i][j] = max(dp[1][i][j], dp[0][i - 1][j] + a[i][k - i] + a[j][k - j]); if (i < k && j > 0) dp[1][i][j] = max(dp[1][i][j], dp[0][i][j - 1] + a[i][k - i] + a[j][k - j]); } } cout << dp[1][n - 1][n - 1] << n ; }
|
#include <bits/stdc++.h> using namespace std; int n, m, i, x, q, w[110000]; long long ans; int f(int x) { return x * (x / 2) + x % 2; } bool cmp(int x, int y) { return x > y; } int main() { scanf( %d%d , &n, &m); for (i = 0; i < m; i++) scanf( %d%d , &q, w + i); sort(w, w + m, cmp); while (f(x + 1) <= n) x++; x = min(x, m); for (i = 0; i < x; i++) ans += w[i]; printf( %I64d n , ans); return 0; }
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 16:17:32
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 7
module RecursiveKOA_STAGE_1
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
csubRecursiveKOA #(.SW(SW/2)) left(
//.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
//.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
//.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
csubRecursiveKOA #(.SW(SW/2)) left(
//.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
//.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW(SW/2+2)) middle (
//.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, j, k, l, w[200005], h[200005], a, b, m, m1; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d , &w[i], &h[i]); if (h[m] <= h[i]) { m1 = m; m = i; } else if (h[m1] <= h[i]) { m1 = i; } a += w[i]; } for (i = 1; i <= n; i++) { if (i == m) { printf( %d , (a - w[i]) * h[m1]); } else printf( %d , (a - w[i]) * h[m]); } printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFRTN_PP_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool isPrime(int num); int main() { int n; cin >> n; for (int i = 1; i <= 1000; i++) { if (!(isPrime(n * i + 1))) { cout << i; break; } } return 0; } bool isPrime(int num) { if (num <= 1) return false; else if (num == 2) return true; else if (num % 2 == 0) return false; else { bool prime = true; int divisor = 3; double num_d = static_cast<double>(num); int upperLimit = static_cast<int>(sqrt(num_d) + 1); while (divisor <= upperLimit) { if (num % divisor == 0) prime = false; divisor += 2; } return prime; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int t[N]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; t[0] = 0; t[n + 1] = 0; for (int i = 1; i <= n; ++i) { cin >> t[i]; t[i] = min(t[i - 1] + 1, t[i]); } for (int i = n; i > 0; --i) { t[i] = min(t[i + 1] + 1, t[i]); } int res = 0; for (int i = 1; i <= n; ++i) res = max(res, t[i]); cout << res << n ; }
|
module de0_top
(
input CLOCK_50, // Clock 50 MHz
input CLOCK_50_2, // Clock 50 MHz
input [ 2:0] BUTTON, // Pushbutton[2:0]
input [ 9:0] SW, // Toggle Switch[9:0]
output [ 6:0] HEX0_D, // Seven Segment Digit 0
output HEX0_DP, // Seven Segment Digit DP 0
output [ 6:0] HEX1_D, // Seven Segment Digit 1
output HEX1_DP, // Seven Segment Digit DP 1
output [ 6:0] HEX2_D, // Seven Segment Digit 2
output HEX2_DP, // Seven Segment Digit DP 2
output [ 6:0] HEX3_D, // Seven Segment Digit 3
output HEX3_DP, // Seven Segment Digit DP 3
output [ 9:0] LEDG, // LED Green[9:0]
output UART_TXD, // UART Transmitter
input UART_RXD, // UART Receiver
output UART_CTS, // UART Clear To Send
input UART_RTS, // UART Request To Send
inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output [12:0] DRAM_ADDR, // SDRAM Address bus 13 Bits
output DRAM_LDQM, // SDRAM Low-byte Data Mask
output DRAM_UDQM, // SDRAM High-byte Data Mask
output DRAM_WE_N, // SDRAM Write Enable
output DRAM_CAS_N, // SDRAM Column Address Strobe
output DRAM_RAS_N, // SDRAM Row Address Strobe
output DRAM_CS_N, // SDRAM Chip Select
output DRAM_BA_0, // SDRAM Bank Address 0
output DRAM_BA_1, // SDRAM Bank Address 1
output DRAM_CLK, // SDRAM Clock
output DRAM_CKE, // SDRAM Clock Enable
inout [14:0] FL_DQ, // FLASH Data bus 15 Bits
inout FL_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
output [21:0] FL_ADDR, // FLASH Address bus 22 Bits
output FL_WE_N, // FLASH Write Enable
output FL_RST_N, // FLASH Reset
output FL_OE_N, // FLASH Output Enable
output FL_CE_N, // FLASH Chip Enable
output FL_WP_N, // FLASH Hardware Write Protect
output FL_BYTE_N, // FLASH Selects 8/16-bit mode
input FL_RY, // FLASH Ready/Busy
inout [ 7:0] LCD_DATA, // LCD Data bus 8 bits
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout SD_DAT0, // SD Card Data 0
inout SD_DAT3, // SD Card Data 3
inout SD_CMD, // SD Card Command Signal
output SD_CLK, // SD Card Clock
input SD_WP_N, // SD Card Write Protect
inout PS2_KBDAT, // PS2 Keyboard Data
inout PS2_KBCLK, // PS2 Keyboard Clock
inout PS2_MSDAT, // PS2 Mouse Data
inout PS2_MSCLK, // PS2 Mouse Clock
output VGA_HS, // VGA H_SYNC
output VGA_VS, // VGA V_SYNC
output [3:0] VGA_R, // VGA Red[3:0]
output [3:0] VGA_G, // VGA Green[3:0]
output [3:0] VGA_B, // VGA Blue[3:0]
input [ 1:0] GPIO0_CLKIN, // GPIO Connection 0 Clock In Bus
output [ 1:0] GPIO0_CLKOUT, // GPIO Connection 0 Clock Out Bus
inout [31:0] GPIO0_D, // GPIO Connection 0 Data Bus
input [ 1:0] GPIO1_CLKIN, // GPIO Connection 1 Clock In Bus
output [ 1:0] GPIO1_CLKOUT, // GPIO Connection 1 Clock Out Bus
inout [31:0] GPIO1_D // GPIO Connection 1 Data Bus
);
// wires & inputs
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = BUTTON[0];
wire clkEnable = SW [9] | ~BUTTON[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign LEDG[0] = clk;
assign LEDG[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
assign HEX0_DP = 1'b1;
assign HEX0_DP = 1'b1;
assign HEX0_DP = 1'b1;
assign HEX0_DP = 1'b1;
sm_hex_display digit_3 ( h7segment [15:12] , HEX3_D [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2_D [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1_D [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0_D [6:0] );
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[300005], m[300005], t[300005], ans, sum, n, x, qwq; int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld%lld , &a[i], &m[i]); x = m[i]; while (x) { x >>= 1ll; t[i]++; } sum += a[i]; } if (sum < 0) for (long long i = 1; i <= n; i++) a[i] *= -1ll; for (long long i = 0; i <= 62; i++) { qwq = 0ll; for (long long j = 1; j <= n; j++) if (m[j] & (1ll << i) && t[j] - 1ll == i) qwq += a[j]; if (qwq > 0) { for (long long j = 1; j <= n; j++) if (m[j] & (1ll << i)) a[j] *= -1ll; ans += (1ll << i); } } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, sn, i, j, sum, temp, nl; map<int, int> myMap; vector<int> t[105]; int main() { cin >> n; j = 0; sn = n * n; for (i = sn; i > sn / 2; i--) { t[j % n].push_back(i); t[j % n].push_back(sn - i + 1); j++; } for (i = 0; i < n; i++) { nl = t[i].size(); for (j = 0; j < nl; j++) cout << t[i][j] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> const int mod = 1000000007; const int inf = 1000000009; const long long INF = 1000000000000000009; const long long big = 1000000000000000; const long double eps = 0.0000000001; using namespace std; int DP[2005][2005], T[2005]; int main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(); int n, h; cin >> n >> h; for (int i = 1; i <= n; i++) cin >> T[i]; DP[0][0] = 1; for (int i = 1; i <= n; i++) { int j = h - T[i]; if (j < 0) continue; DP[i][j] = (DP[i][j] + DP[i - 1][j]) % mod; DP[i][j] %= mod; if (j > 0) { DP[i][j] = (DP[i][j] + DP[i - 1][j - 1]) % mod; DP[i][j - 1] = ((long long int)DP[i][j - 1] + DP[i - 1][j - 1] + (long long int)DP[i - 1][j] * j) % mod; DP[i][j - 1] = (DP[i][j - 1] + (long long int)DP[i - 1][j - 1] * (j - 1)) % mod; } } cout << DP[n][0]; return 0; }
|
`timescale 1ns / 1ps
module KeyBoard_ctrl(CLK, RESET, ROW, COLUMN, DECODE_BCD1, DECODE_BCD0);
input CLK;
input RESET;
input [3:0] COLUMN;
output [3:0] ROW;
output [3:0] DECODE_BCD0;
output [3:0] DECODE_BCD1;
reg [3:0] ROW;
reg [3:0] DEBOUNCE_COUNT;
reg [3:0] SCAN_CODE;
reg [3:0] DECODE_BCD0;
reg [3:0] DECODE_BCD1;
reg [3:0] KEY_CODE;
reg [7:0] KEY_BUFFER;
reg [14:0] DIVIDER;
reg PRESS;
wire PRESS_VALID;
wire DEBOUNCE_CLK;
wire SCAN_CLK;
/***********************
* Time Base Generator *
***********************/
always @(posedge CLK or negedge RESET)
begin
if (!RESET)
DIVIDER <= {12'h000,2'b00};
else
DIVIDER <= DIVIDER + 1;
end
assign DEBOUNCE_CLK = DIVIDER[14];
assign SCAN_CLK = DIVIDER[14];
/***************************
* Scanning Code Generator *
***************************/
always @(posedge CLK or negedge RESET)
begin
if (!RESET)
SCAN_CODE <= 4'h0;
else if (PRESS)
SCAN_CODE <= SCAN_CODE + 1;
end
/*********************
* Scanning Keyboard *
*********************/
always @(SCAN_CODE,COLUMN)
begin
case (SCAN_CODE[3:2])
2'b00 : ROW = 4'b1110;
2'b01 : ROW = 4'b1101;
2'b10 : ROW = 4'b1011;
2'b11 : ROW = 4'b0111;
endcase
case (SCAN_CODE[1:0])
2'b00 : PRESS = COLUMN[0];
2'b01 : PRESS = COLUMN[1];
2'b10 : PRESS = COLUMN[2];
2'b11 : PRESS = COLUMN[3];
endcase
end
/********************
* Debounce Circuit *
********************/
always @(posedge DEBOUNCE_CLK or negedge RESET)
begin
if (!RESET)
DEBOUNCE_COUNT <= 4'h0;
else if (PRESS)
DEBOUNCE_COUNT <= 4'h0;
else if (DEBOUNCE_COUNT <= 4'hE)
DEBOUNCE_COUNT <= DEBOUNCE_COUNT + 1;
end
assign PRESS_VALID = (DEBOUNCE_COUNT == 4'hD)? 1'b1 : 1'b0;
/**************************************
* Fetch Key Code Store In KEY_BUFFER *
**************************************/
/**************************************************/
/*You can modify here for correct keyboard mapping*/
/**************************************************/
reg [3:0] TMP_VALUE;
always @(negedge DEBOUNCE_CLK or negedge RESET)
begin
case (SCAN_CODE)
4'b1100: TMP_VALUE <= 0;
4'b1101: TMP_VALUE <= 1;
4'b1001: TMP_VALUE <= 2;
4'b0101: TMP_VALUE <= 3;
4'b1110: TMP_VALUE <= 4;
4'b1010: TMP_VALUE <= 5;
4'b0110: TMP_VALUE <= 6;
4'b1111: TMP_VALUE <= 7;
4'b1011: TMP_VALUE <= 8;
4'b0111: TMP_VALUE <= 9;
default: TMP_VALUE <= 0;
endcase
if (!RESET)
KEY_BUFFER <= 16'hCC99;
else if (PRESS_VALID)
KEY_BUFFER <= {KEY_BUFFER[3:0],TMP_VALUE};
end
/****************************
* Data Display Multiplexer *
****************************/
always @(KEY_BUFFER)
begin
DECODE_BCD1 = KEY_BUFFER[7:4];
DECODE_BCD0 = KEY_BUFFER[3:0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long Gcd(long long a, long long b) { if (a % b == 0) return b; return Gcd(b, a % b); } long long Max(long long a, long long b) { if (a > b) return a; return b; } long long Min(long long a, long long b) { if (a < b) return a; return b; } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long modInverse(long long a, long long m) { long long x, y; long long g = gcdExtended(a, m, &x, &y); if (g != 1) return -1; else { long long res = (x % m + m) % m; return res; } } vector<int> primeFactors(int n) { vector<int> v; while (n % 2 == 0) { v.push_back(2); n = n / 2; } for (int i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { v.push_back(i); n = n / i; } } if (n > 2) v.push_back(n); return v; } long long spf[100001]; void sieve() { spf[1] = 1; for (int i = 2; i < 100001; i++) spf[i] = i; for (int i = 4; i < 100001; i += 2) spf[i] = 2; for (int i = 3; i * i < 100001; i++) { if (spf[i] == i) { for (int j = i * i; j < 100001; j += i) if (spf[j] == j) spf[j] = i; } } } long long binarySearch(long long arr[], long long l, long long r, long long x) { if (r >= l) { long long mid = l + (r - l) / 2; if (arr[mid] == x) return mid; if (arr[mid] > x) return binarySearch(arr, l, mid - 1, x); return binarySearch(arr, mid + 1, r, x); } return -1; } const long long N = 100000; long long n; long long tree[2 * N]; void build(long long arr[]) { for (long long i = 0; i < n; i++) { tree[n + i] = arr[i]; } for (long long i = n - 1; i > 0; --i) { tree[i] = tree[i << 1] + tree[i << 1 | 1]; } } void updateTreeNode(long long p, long long value) { tree[p + n] = value; p = p + n; for (long long i = p; i > 1; i >>= 1) { tree[i >> 1] = tree[i] + tree[i ^ 1]; } } long long query(long long l, long long r) { long long res = 0; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) { res += tree[l++]; } if (r & 1) { res += tree[--r]; } } return res; } void dfs(std::vector<long long> v[], long long s, bool visited[]) { visited[s] = true; for (long long i = 0; i < v[s].size(); ++i) { if (!visited[v[s][i]]) { dfs(v, v[s][i], visited); } } } long long C[2001][2000]; void binomialCoeff(long long n, long long k) { long long i, j; for (i = 0; i <= n; i++) { for (j = 0; j <= k; j++) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = (C[i - 1][j - 1] % 998244353 + C[i - 1][j] % 998244353) % 998244353; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m, k; cin >> n >> m >> k; binomialCoeff(n, k); long long mminus1 = power(m - 1, k, 998244353); mminus1 %= 998244353; long long ans = 1; ans *= mminus1 % 998244353; ans = ((ans % 998244353) * (m)) % 998244353; ans = ((ans % 998244353) * (C[n - 1][k])) % 998244353; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; for (long long i = 0; i < n; ++i) { if (i % 4 < 2) putchar( a ); else putchar( b ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; vector<long long int> cost(n); for (long long int i = 0; i < n; i++) { cin >> cost[i]; } sort(cost.begin(), cost.end()); long long int m; cin >> m; vector<long long int> coup(m); for (long long int i = 0; i < m; i++) { cin >> coup[i]; } long long int temp_sum = 0; for (long long int i = 0; i < n; i++) { temp_sum += cost[i]; } for (long long int i = 0; i < m; i++) { cout << temp_sum - cost.at(n - coup[i]) << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b; while (cin >> n >> m >> a >> b) { a--; b--; int oa, pa, ob, pb; oa = a / m; pa = a % m; ob = b / m; pb = b % m; if (b == n - 1) { pb = m - 1; } if (oa == ob) { cout << 1 ; continue; } if (pa == 0 && pb == m - 1) { cout << 1 ; continue; } if (pa - pb == 1) { cout << 2 ; continue; } int hang = ob - oa; if (pa > 0 && pb < m - 1) { if (hang == 1) { cout << 2 ; continue; } else { cout << 3 ; continue; } } cout << 2 ; } }
|
module lab5dram(CLK, RESET, ADDR, DATA, MW, Q, IOA, IOB, IOC, IOD, IOE, IOF, IOG);
input CLK;
input RESET;
input [7:0] ADDR; // 8-bit addresses
input [7:0] DATA; // 8-bit data words
input MW;
output [7:0] Q;
input [7:0] IOA;
input [7:0] IOB;
input [7:0] IOC;
output [7:0] IOD;
output [7:0] IOE;
output [7:0] IOF;
output [7:0] IOG;
reg [7:0] Q;
reg [7:0] IOreg [3:6];
reg [7:0] mem [0:247];
reg [7:0] Q_IO;
reg [7:0] Q_mem;
reg [7:0] ADDR_IO;
reg MW_IO;
reg MW_mem;
always @(*) begin
Q_mem <= mem[ADDR];
end
always @(posedge CLK) begin
// memory is currently initialized with a LUT in 2-byte BCD words
// for the heart rate monitor (big endian)
if(RESET) begin
mem[0] <= 8'b0000_0000; // 0000
mem[1] <= 8'b0000_0000;
mem[2] <= 8'b0000_1000; // 0008
mem[3] <= 8'b0000_0000;
mem[4] <= 8'b0001_0111; // 0017
mem[5] <= 8'b0000_0000;
mem[6] <= 8'b0010_0110; // 0026
mem[7] <= 8'b0000_0000;
mem[8] <= 8'b0011_0101; // 0035
mem[9] <= 8'b0000_0000;
mem[10] <= 8'b0100_0100; // 0044
mem[11] <= 8'b0000_0000;
mem[12] <= 8'b0101_0011; // 0053
mem[13] <= 8'b0000_0000;
mem[14] <= 8'b0110_0010; // 0062
mem[15] <= 8'b0000_0000;
mem[16] <= 8'b0111_0001; // 0071
mem[17] <= 8'b0000_0000;
mem[18] <= 8'b1000_0000; // 0080
mem[19] <= 8'b0000_0000;
mem[20] <= 8'b1000_1001; // 0089
mem[21] <= 8'b0000_0000;
mem[22] <= 8'b1001_1000; // 0098
mem[23] <= 8'b0000_0000;
mem[24] <= 8'b0000_0111; // 0107
mem[25] <= 8'b0000_0001;
mem[26] <= 8'b0001_0110; // 0116
mem[27] <= 8'b0000_0001;
mem[28] <= 8'b0010_0101; // 0125
mem[29] <= 8'b0000_0001;
mem[30] <= 8'b0011_0011; // 0133
mem[31] <= 8'b0000_0001;
mem[32] <= 8'b0100_0010; // 0142
mem[33] <= 8'b0000_0001;
mem[34] <= 8'b0101_0001; // 0151
mem[35] <= 8'b0000_0001;
mem[36] <= 8'b0110_0000; // 0160
mem[37] <= 8'b0000_0001;
mem[38] <= 8'b0110_1001; // 0169
mem[39] <= 8'b0000_0001;
mem[40] <= 8'b0111_1000; // 0178
mem[41] <= 8'b0000_0001;
mem[42] <= 8'b1000_0111; // 0187
mem[43] <= 8'b0000_0001;
mem[44] <= 8'b1001_0110; // 0196
mem[45] <= 8'b0000_0001;
mem[46] <= 8'b0000_0101; // 0205
mem[47] <= 8'b0000_0010;
mem[48] <= 8'b0001_0100; // 0214
mem[49] <= 8'b0000_0010;
mem[50] <= 8'b0010_0011; // 0223
mem[51] <= 8'b0000_0010;
mem[52] <= 8'b0011_0010; // 0232
mem[53] <= 8'b0000_0010;
mem[54] <= 8'b0100_0001; // 0241
mem[55] <= 8'b0000_0010;
mem[56] <= 8'b0101_0000; // 0250
mem[57] <= 8'b0000_0010;
mem[58] <= 8'b0101_1001; // 0259
mem[59] <= 8'b0000_0010;
end
else if(MW_IO == 1'b1) begin
IOreg[ADDR_IO] <= DATA;
end
else if(MW_mem == 1'b1) begin
mem[ADDR] <= DATA;
end
end
assign IOD = IOreg[3];
assign IOE = IOreg[4];
assign IOF = IOreg[5];
assign IOG = IOreg[6];
always @(*) begin
MW_mem = 0;
MW_IO = 0;
ADDR_IO = 0;
Q = 8'd0;
case(ADDR)
8'd249: begin
ADDR_IO = 0;
Q = IOA;
end
8'd250: begin
ADDR_IO = 1;
Q = IOB;
end
8'd251: begin
ADDR_IO = 2;
Q = IOC;
end
8'd252: begin
ADDR_IO = 3;
MW_IO = MW;
end
8'd253: begin
ADDR_IO = 4;
MW_IO = MW;
end
8'd254: begin
ADDR_IO = 5;
MW_IO = MW;
end
8'd255: begin
ADDR_IO = 6;
MW_IO = MW;
end
default: begin // regular memory
if(MW) begin
MW_mem = 1;
end
else begin
Q = Q_mem;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long pow_mod(long long x, long long y) { long long ret = 1; while (y) { if (y & 1) ret = (ret * x) % 1000000007; x = (x * x) % 1000000007; y >>= 1; } return ret; } long long f[2000010]; void init() { f[0] = 1; for (int i = 1; i <= 2000005; i++) f[i] = (f[i - 1] * i) % 1000000007; } long long inv(long long x) { return pow_mod(x, 1000000007 - 2); } long long C(long long x, long long y) { long long ret; ret = (f[x] * inv(f[y])) % 1000000007; ret = (ret * inv(f[x - y])) % 1000000007; return ret; } int main() { init(); int n; scanf( %d , &n); long long ans = 0; for (int i = 0; i <= n; i++) ans = (ans + C(i + n + 1, n)) % 1000000007; cout << ans << endl; }
|
module PushBtnInterface(clock,reset,button,button_pressed);
parameter Wait = 40000;
parameter Size = 16;
input wire clock;
input wire reset;
input wire button;
output wire button_pressed;
reg [Size-1:0] s_Counter;
reg s_DoneCount;
reg s_ButtonPressed;
assign button_pressed = s_ButtonPressed;
always @ (posedge clock) begin
if (reset) begin
s_Counter <= 0;
s_DoneCount <= 0;
s_ButtonPressed <= 0;
end
else begin
if (button) begin
if (!s_DoneCount) begin
if (s_Counter < Wait) begin
s_Counter <= s_Counter + 1;
s_DoneCount <= 0;
s_ButtonPressed <= 0;
end
else begin
s_Counter <= 0;
s_DoneCount <= 1;
s_ButtonPressed <= 1;
end
end
else begin
s_Counter <= 0;
s_DoneCount <= 1;
s_ButtonPressed <= 0;
end // else: !if(!s_DoneCount)
end // if (button)
else begin
s_Counter <= 0;
s_DoneCount <= 0;
s_ButtonPressed <= 0;
end // else: !if(button)
end // else: !if(reset)
end // always @ (posedge clock)
endmodule // PushBtnInterface
|
`timescale 1 ns / 1 ps
module engine (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] row_start_in, // what row should it start at
input [63:0] row_skip_in, // how many rows should be skipped when
// incrementing
input [63:0] hash_table_mask,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in,
input ll_afull_in,
output ll_write_en_out,
output [47:0] ll_address_out,
output [63:0] ll_payload_out,
input ht_rq_afull_in,
output ht_rq_read_en_out,
output [47:0] ht_rq_address_out,
output [63:0] ht_rq_data_out,
output ht_rs_afull_out,
input ht_rs_write_en_in,
input [63:0] ht_rs_data_in,
input ll_update_afull_in,
output ll_update_write_en_out,
output [47:0] ll_update_addr_out,
output [63:0] ll_update_data_out,
input ll_rs_write_en_in
);
wire rows_done_s;
wire rows_output_empty_s;
wire [63:0] rows_output_value_s;
wire rows_read_en_s;
wire build_done_s;
wire build_row_afull_s;
stream_rows ROWS (
.clk (clk),
.rst (rst),
.done (rows_done_s),
.num_rows_in (num_rows_in),
.rows_size_in (rows_size_in),
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.output_empty_out (rows_output_empty_s),
.output_read_en_in (rows_read_en_s),
.output_value_out (rows_output_value_s),
.row_rq_stall_in (row_rq_stall_in),
.row_rq_vld_out (row_rq_vld_out),
.row_rq_vadr_out (row_rq_vadr_out),
.row_rs_stall_out (row_rs_stall_out),
.row_rs_vld_in (row_rs_vld_in),
.row_rs_data_in (row_rs_data_in)
);
assign rows_read_en_s = !rows_output_empty_s && !build_row_afull_s;
build_phase BUILD (
.clk (clk),
.rst (rst),
.done (build_done_s),
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.hash_table_mask (hash_table_mask),
.row_afull_out (build_row_afull_s),
.row_write_en_in (rows_read_en_s),
.row_value_in (rows_output_value_s),
.ll_afull_in (ll_afull_in),
.ll_write_en_out (ll_write_en_out),
.ll_address_out (ll_address_out),
.ll_payload_out (ll_payload_out),
.ht_rq_afull_in (ht_rq_afull_in),
.ht_rq_read_en_out (ht_rq_read_en_out),
.ht_rq_address_out (ht_rq_address_out),
.ht_rq_data_out (ht_rq_data_out),
.ht_rs_afull_out (ht_rs_afull_out),
.ht_rs_write_en_in (ht_rs_write_en_in),
.ht_rs_data_in (ht_rs_data_in),
.ll_update_afull_in (ll_update_afull_in),
.ll_update_write_en_out (ll_update_write_en_out),
.ll_update_addr_out (ll_update_addr_out),
.ll_update_data_out (ll_update_data_out),
.ll_rs_write_en_in (ll_rs_write_en_in)
);
assign done = rows_done_s && build_done_s;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1001; long long int n, m, k; vector<pair<long long int, long long int> > adj[N]; vector<long long int> func(long long int x) { vector<long long int> dis(n + 1, INT_MAX); if (x == 0) { return dis; } vector<int> vis(n + 1, 0); set<pair<long long int, long long int> > s; s.insert(make_pair(0, x)); dis[x] = 0; while (!s.empty()) { long long int v = (*s.begin()).second; s.erase(s.begin()); if (vis[v]) { continue; } vis[v] = 1; for (auto u : adj[v]) { if (dis[u.first] > dis[v] + u.second) { dis[u.first] = dis[v] + u.second; s.insert(make_pair(dis[u.first], u.first)); } } } return dis; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m >> k; vector<pair<pair<long long int, long long int>, long long int> > edges; for (long long int i = 0; i < m; ++i) { long long int a, b, w; cin >> a >> b >> w; adj[a].push_back(make_pair(b, w)); adj[b].push_back(make_pair(a, w)); edges.push_back(make_pair(make_pair(a, b), w)); } vector<pair<long long int, long long int> > queries(k); for (long long int i = 0; i < k; ++i) { cin >> queries[i].first >> queries[i].second; } vector<vector<long long int> > dis; for (long long int i = 0; i <= n; ++i) { dis.push_back(func(i)); } long long int ans = 0; for (long long int i = 0; i < k; ++i) { ans += dis[queries[i].first][queries[i].second]; } for (long long int i = 0; i < m; ++i) { long long int a = edges[i].first.first; long long int b = edges[i].first.second; long long int w = edges[i].second; long long int cost = 0; for (long long int j = 0; j < k; ++j) { long long int x = queries[j].first, y = queries[j].second; long long int price = dis[x][y]; if (dis[x][a] < dis[x][b] && dis[y][a] > dis[y][b]) { price = min(price, dis[x][a] + dis[b][y]); } else if (dis[x][b] < dis[x][a] && dis[y][a] < dis[y][b]) { price = min(price, dis[x][b] + dis[y][a]); } cost += price; } ans = min(ans, cost); } cout << ans; return (0); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; long long int a[n]; for (long long int i = 0; i < n; i++) { a[i] = 0; } long long int x; for (long long int i = 0; i < m; i++) { cin >> x; a[x - 1] += 1; } long long int min = (m > n) ? m : n; for (long long int i = 0; i < n; i++) { if (a[i] < min) min = a[i]; } cout << min << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; const int INF = 0x7fffffff; vector<int> G[maxn]; long long weight[maxn]; long long dp[maxn]; int ans; long long maxsum = -INF; void dfs(int now, int fa) { dp[now] = weight[now]; for (int v : G[now]) { if (v != fa) { dfs(v, now); if (dp[v] > 0) dp[now] += dp[v]; } } maxsum = max(maxsum, dp[now]); } void dfs2(int now, int fa) { dp[now] = weight[now]; for (int v : G[now]) { if (v != fa) { dfs2(v, now); if (dp[v] > 0) dp[now] += dp[v]; } } if (dp[now] == maxsum) { ans++; dp[now] = 0; } } int main() { std::ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> weight[i]; int from, to; for (int i = 2; i <= n; ++i) { cin >> from >> to; G[from].push_back(to); G[to].push_back(from); } dfs(1, 0); dfs2(1, 0); cout << maxsum * ans << << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void optimizeIO() { ios_base::sync_with_stdio(false); cin.tie(NULL); } const int nmax = 150005; const long long LINF = 1e17; int ara[110]; set<int> SET; int main() { optimizeIO(); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> ara[i]; SET.insert(ara[i]); } int siz = SET.size(); if (siz > 3) { cout << -1; return 0; } if (siz == 3) { vector<int> v; for (auto x : SET) v.push_back(x); int a = v[2] - v[1]; int b = v[1] - v[0]; if (a != b) { cout << -1; return 0; } if (a == b) { cout << a << endl; return 0; } } if (siz == 2) { vector<int> v; for (auto x : SET) v.push_back(x); int a = v[1] - v[0]; if (a % 2 == 1) { cout << a << endl; return 0; } if (a % 2 == 0) { cout << a / 2 << endl; return 0; } } if (siz == 1) { cout << 0 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; const int M = 100005; int n, m; int in_degree[N]; bool visited[N]; bool tree_edge[M]; bool directed[M]; vector<int> choose[N]; vector<pair<int, int> > adj[N]; inline void dfs(int u, int p) { visited[u] = true; for (auto edge : adj[u]) { int v = edge.first; int i = edge.second; if (v == p) { continue; } if (not visited[v]) { dfs(v, u); tree_edge[i] = true; } else if (not directed[i]) { in_degree[v]++; directed[i] = true; choose[v].push_back(u); } } } inline void solve(int u, int p) { for (auto edge : adj[u]) { int v = edge.first; int i = edge.second; if ((not tree_edge[i]) || (v == p)) { continue; } solve(v, u); } if (p != -1) { if (in_degree[u] & 1) { in_degree[u]++; choose[u].push_back(p); } else { in_degree[p]++; choose[p].push_back(u); } } } int main() { cin >> n >> m; if (m & 1) { cout << No solution << endl; return 0; } for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; adj[u].push_back({v, i}); adj[v].push_back({u, i}); } dfs(1, -1); solve(1, -1); for (int i = 1; i <= n; i++) { while ((int)choose[i].size() > 0) { int u = choose[i].back(); choose[i].pop_back(); int v = choose[i].back(); choose[i].pop_back(); cout << u << << i << << v << endl; } } }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_receiveActivity (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); int freq[26]; int main() { string s; cin >> s; int mx = -1; char g = s[0]; for (int i = 0; i < s.size(); i++) { freq[s[i] - a ]++; if (s[i] >= g) { mx = max(mx, freq[s[i] - a ]); g = s[i]; } } string d(freq[g - a ], g); cout << d << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-11; int n, d; const int M = 30001; int f[M][250 * 2]; int v[M]; int solve(int i, int j) { if (i >= M) return 0; int jj = j - (d - 250); if (f[i][jj] != -1) return f[i][jj]; f[i][jj] = 0; int res = 0; if (j == 1) res += max(solve(i + j, j), solve(i + j + 1, j + 1)) + v[i]; else res += max(solve(i + j - 1, j - 1), max(solve(i + j, j), solve(i + j + 1, j + 1))) + v[i]; return f[i][jj] = res; } int main() { ios_base::sync_with_stdio(false); for (int i = 0; i < (int)M; i++) for (int j = 0; j < (int)250 * 2; j++) f[i][j] = -1; cin >> n >> d; for (int i = 0; i < (int)n; i++) { int j; cin >> j; v[j]++; } cout << solve(d, d) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; double eps = 1e-10; int main() { ios::sync_with_stdio(false); cin.tie(0); long long h, l; while (cin >> h >> l) { double L = 0.0, R = 10000000.0; long long ans = l * l - h * h; printf( %.13f n , ans / (2.0 * h)); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_BLACKBOX_V
`define SKY130_FD_SC_MS__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_BLACKBOX_V
|
// based on https://people.ece.cornell.edu/land/courses/ece5760/DE2/indexVGA.html
// read sram or switch and output color to screen
module vgaram
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b
);
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
assign sram_addr = {x[9:0], y[9:0]};
// hi byte select enabled
assign sram_ub_n = 0;
// low byte select enabled
assign sram_lb_n = 0;
// chip enable
assign sram_ce_n = 0;
// output enable is overriden by WE
assign sram_oe_n = 0;
// if key 1 is not pressed then float, otherwise
// drive it with data from sw to be stored in SRAM
assign sram_we_n = {key[0] ? 1 : 0};
assign sram_dq = (key[0] ? 16'hzzzz :
(key[1] ? {x[8:5], y[8:5] & ~{4{x[9]}}, y[8:5] & {4{x[9]}}, 4'b0} :
sw[15:0]));
// assign color based on contents of sram
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
// delay a little before resetting the device for board to power up
reset_delay r0(
.clk(clk50),
.rst(rst)
);
// vga needs ~25 mhz for 640x480 at 60 hz
// c0 is the rate at which we update the vga signals at
// c1 is a phase delay of 90 degree which we output to the vga clock
// meaning vga clock gets clocked and updated a little later than we
// update the internal vga signals like sync rgb data
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
// vga controller that gets color from r, g, b
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[300005]; vector<long long> adjlist[1048585]; int main() { long long n, i; scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld , a + i); } for (i = 1; i < n; i++) { a[i] = a[i - 1] ^ a[i]; } adjlist[0].push_back(0); for (i = 0; i < n; i++) { adjlist[a[i]].push_back(i + 1); } long long ans = 0; for (i = 0; i < 1048580; i++) { if (adjlist[i].size() > 0) { long long od = 0, ev = 0; for (auto e : adjlist[i]) { if (e % 2 == 0) ev++; else od++; } ans += (ev * (ev - 1)) / 2; ans += (od * (od - 1)) / 2; } } printf( %lld n , ans); return 0; }
|
`timescale 1ns/1ns
// READ: Tag response to a 'read' command.
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// readbit* = talking to tx module
// read_sample_* = talking to external source (adc or msp430)
// which supplies sample data to be transmitted.
// handle = current handle from random number generator
module read(reset, readbitclk, readbitout, readbitdone,
read_sample_ctl, read_sample_clk, read_sample_datain,
handle);
input reset, readbitclk;
output readbitout, readbitdone;
input read_sample_datain;
output read_sample_ctl, read_sample_clk;
input [15:0] handle;
wire [32:0] packet;
assign packet[32] = 1'b0;
assign packet[31:16] = 16'h0000;
assign packet[15:0] = handle[15:0];
reg [5:0] bitoutcounter;
reg read_sample_ctl;
wire read_sample_clk, readbitout, readbitdone;
assign read_sample_clk = readbitclk & (bitoutcounter > 15);
assign readbitout = (bitoutcounter!=32 && bitoutcounter>15) ? read_sample_datain : packet[bitoutcounter];
assign readbitdone = (bitoutcounter == 0);
reg initialized;
always @ (posedge readbitclk or posedge reset) begin
if (reset) begin
bitoutcounter <= 0;
initialized <= 0;
read_sample_ctl <= 0;
end else if (!initialized) begin
initialized <= 1;
read_sample_ctl <= 1;
bitoutcounter <= 32;
end else if (!readbitdone) begin
bitoutcounter <= bitoutcounter - 4'd1;
if (bitoutcounter >= 15) read_sample_ctl <= 1;
else read_sample_ctl <= 0;
end else begin
read_sample_ctl<= 0;
end // ~reset
end // always
endmodule
|
#include <bits/stdc++.h> int n, m, num; char tab[100][100]; int xx[10000][4]; int yy[10000][4]; int ch[100][100]; int id[100][100]; int getdir(int cd, int dd) { if (cd == 1) return (dd + 1) % 4; else return dd; } int main() { scanf( %d %d , &n, &num); for (int i = 0; i < n; i++) { scanf( %s , tab[i]); m = strlen(tab[i]); for (int j = 0; j < m; j++) { tab[i][j] -= 0 ; } } int count = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (tab[i][j] == 0) { id[i][j] = 0; continue; } if (i - 1 >= 0 && tab[i - 1][j] == tab[i][j]) { id[i][j] = id[i - 1][j]; } else if (j - 1 >= 0 && tab[i][j - 1] == tab[i][j]) { id[i][j] = id[i][j - 1]; } else { id[i][j] = count++; xx[id[i][j]][0] = i; yy[id[i][j]][0] = j; xx[id[i][j]][1] = i; yy[id[i][j]][3] = j; } if ((i + 1 >= n || tab[i][j] != tab[i + 1][j]) && (j + 1 >= m || tab[i][j] != tab[i][j + 1])) { yy[id[i][j]][1] = j; xx[id[i][j]][3] = i; xx[id[i][j]][2] = i; yy[id[i][j]][2] = j; } } } int tx, ty, cd = 0, dd = 1; int pos = id[tx][ty]; for (int p = 0; p < num; p++) { int dir = getdir(cd, dd); tx = xx[pos][dir]; ty = yy[pos][dir]; int dx, dy; if (dd == 0) { dx = -1; dy = 0; } if (dd == 1) { dx = 0; dy = 1; } if (dd == 2) { dx = 1; dy = 0; } if (dd == 3) { dx = 0; dy = -1; } if (tx + dx < 0 || tx + dx >= n || ty + dy < 0 || ty + dy >= m || id[tx + dx][ty + dy] == 0) { if (cd == 0) { cd = 1; } else { cd = 0; dd += 1; dd %= 4; } } else { pos = id[tx + dx][ty + dy]; tx += dx; ty += dy; } } printf( %d n , tab[tx][ty]); }
|
#include <bits/stdc++.h> using namespace std; char str[2010][2010]; void go(int x, int y) { int l, r, u, d; d = (int)(str[x + 1][y] == . ); u = (int)(str[x - 1][y] == . ); r = (int)(str[x][y + 1] == . ); l = (int)(str[x][y - 1] == . ); if (!d && !u && !r && !l) { cout << Not unique << endl; exit(0); } if (l && !r && !u && !d) { str[x][y - 1] = < ; str[x][y] = > ; if (str[x][y - 2] == . ) go(x, y - 2); if (str[x - 1][y - 1] == . ) go(x - 1, y - 1); if (str[x + 1][y - 1] == . ) go(x + 1, y - 1); } if (r && !l && !u && !d) { str[x][y] = < ; str[x][y + 1] = > ; if (str[x][y + 2] == . ) go(x, y + 2); if (str[x - 1][y + 1] == . ) go(x - 1, y + 1); if (str[x + 1][y + 1] == . ) go(x + 1, y + 1); } if (u && !l && !r && !d) { str[x - 1][y] = ^ ; str[x][y] = v ; if (str[x - 2][y] == . ) go(x - 2, y); if (str[x - 1][y + 1] == . ) go(x - 1, y + 1); if (str[x - 1][y - 1] == . ) go(x - 1, y - 1); } if (d && !l && !r && !u) { str[x][y] = ^ ; str[x + 1][y] = v ; if (str[x + 2][y] == . ) go(x + 2, y); if (str[x + 1][y - 1] == . ) go(x + 1, y - 1); if (str[x + 1][y + 1] == . ) go(x + 1, y + 1); } return; } int main() { int n, m, i, j; for (i = 0; i < 2010; i++) for (j = 0; j < 2010; j++) str[i][j] = * ; scanf( %d%d , &n, &m); getchar(); for (i = 1; i <= n; i++) { gets(str[i] + 1); str[i][m + 1] = * ; } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (str[i][j] == . ) go(i, j); } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (str[i][j] == . ) { cout << Not unique << endl; return 0; } } } for (i = 1; i <= n; i++) { str[i][m + 1] = 0; printf( %s n , str[i] + 1); } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1000000000 ) using namespace std; const bool db = false; int n, m, x, y; int a[1010][1010], b[1010][1010]; long long s[1010][1010], cs[1010][1010]; vector<pair<int, int> > ans; char mark[1010][1010]; pair<long long, pair<int, int> > st[1010 * 1010]; int sz = 0; long long sum(int lx, int ly, int rx, int ry) { return s[rx][ry] + s[lx - 1][ly - 1] - s[rx][ly - 1] - s[lx - 1][ry]; } int main() { scanf( %d%d%d%d , &n, &m, &x, &y); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %d , &a[i][j]); s[i][j] = a[i][j] + s[i - 1][j] + s[i][j - 1] - s[i - 1][j - 1]; } } for (int i = 1; i <= n; ++i) { deque<int> dq; for (int j = 1; j < y; ++j) { while (!dq.empty() && dq.back() > a[i][j]) dq.pop_back(); dq.push_back(a[i][j]); } for (int j = 1; j + y - 1 <= m; ++j) { if (j != 1) { if (a[i][j - 1] == dq.front()) dq.pop_front(); } while (!dq.empty() && dq.back() > a[i][j + y - 1]) dq.pop_back(); dq.push_back(a[i][j + y - 1]); b[i][j] = dq.front(); } } for (int i = 1; i + y - 1 <= m; ++i) { deque<int> dq; for (int j = 1; j < x; ++j) { while (!dq.empty() && dq.back() > b[j][i]) dq.pop_back(); dq.push_back(b[j][i]); } for (int j = 1; j + x - 1 <= n; ++j) { if (j != 1) { if (b[j - 1][i] == dq.front()) dq.pop_front(); } while (!dq.empty() && dq.back() > b[j + x - 1][i]) dq.pop_back(); dq.push_back(b[j + x - 1][i]); cs[j][i] = dq.front(); } } long long tot = 1LL << 60; for (int i = 1; i + x - 1 <= n; ++i) { for (int j = 1; j + y - 1 <= m; ++j) { st[sz].first = cs[i][j] = sum(i, j, i + x - 1, j + y - 1) - 1LL * x * y * cs[i][j]; st[sz].second.first = i; st[sz++].second.second = j; } } sort(st, st + sz); ans.reserve(n * m); for (int it = 0; it < sz; ++it) { int i = st[it].second.first, j = st[it].second.second; if (mark[i][j] || mark[i + x - 1][j] || mark[i][j + y - 1] || mark[i + x - 1][j + y - 1]) { continue; } ans.emplace_back(make_pair(i, j)); for (int di = 0; di < x; ++di) { for (int dj = 0; dj < y; ++dj) { mark[i + di][j + dj] = 1; } } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); ++i) printf( %d %d %lld n , ans[i].first, ans[i].second, cs[ans[i].first][ans[i].second]); getchar(); getchar(); return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEIVE",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEIVE",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { return (!y ? x : gcd(y, x % y)); } const int maxn = 2e5; vector<int> g[maxn], tree[maxn]; map<pair<int, int>, int> we; int par[maxn]; int gpar(int v) { return (par[v] == v ? v : par[v] = gpar(par[v])); } bool mrg(int u, int v) { u = gpar(u); v = gpar(v); if (u == v) return false; par[v] = u; return true; } int h[maxn]; void dfs(int v, int p) { for (auto u : tree[v]) { if (u == p) continue; par[u] = v; h[u] = h[v] + 1; dfs(u, v); } } vector<int> get_path(int u, int v) { if (h[u] < h[v]) swap(u, v); vector<int> p, rig; while (h[u] > h[v]) { p.push_back(u); u = par[u]; } while (u != v) { p.push_back(u); rig.push_back(v); u = par[u], v = par[v]; } p.push_back(u); reverse(rig.begin(), rig.end()); for (auto i : rig) p.push_back(i); return p; } const int maxb = 18; int mods[2] = {int(1e9 + 7), int(1e9 + 9)}; int mod; const int N = (1 << maxb); int bpw(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = 1LL * ans * a % mod; a = 1LL * a * a % mod; b >>= 1; } return ans; } void fwht(int* a, int val) { for (int len = 2; len <= N; len *= 2) for (int i = 0; i < N; i += len) { int nxt = len / 2; for (int j = 0; j < nxt; j++) { int x = a[i + j], y = a[i + j + nxt]; a[i + j] = (x + y) % mod; a[i + j + nxt] = (x - y + mod) % mod; } } if (val == -1) { int inv = bpw(N, mod - 2); for (int i = 0; i < N; i++) a[i] = 1LL * a[i] * inv % mod; } } int ans[2][N], cnt[N]; int32_t main() { ios::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; int tot = 0; for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; u--, v--; g[u].push_back(v); g[v].push_back(u); we[{u, v}] = we[{v, u}] = w; tot ^= w; } for (int i = 0; i < n; i++) par[i] = i; vector<pair<int, int> > bads; for (int i = 0; i < n; i++) { for (auto j : g[i]) { if (mrg(i, j)) { tree[i].push_back(j); tree[j].push_back(i); } else if (i < j) bads.push_back({i, j}); } } if (bads.size() == 0) { cout << tot << << 1 << n ; return 0; } dfs(0, 0); for (int it = 0; it < 2; it++) { mod = mods[it]; for (int i = 0; i < N; i++) ans[it][i] = 1; for (auto t : bads) { vector<int> p = get_path(t.first, t.second); p.push_back(p[0]); memset(cnt, 0, sizeof cnt); for (int i = 0; i + 1 < p.size(); i++) { int w = we[{p[i], p[i + 1]}]; cnt[w]++; } fwht(cnt, 1); for (int i = 0; i < N; i++) ans[it][i] = 1LL * ans[it][i] * cnt[i] % mod; } fwht(ans[it], -1); } int jav = 1e9, who = -1; for (int i = 0; i < N; i++) if (ans[0][i] || ans[1][i]) { if ((i ^ tot) < jav) { jav = i ^ tot; who = i; } } assert(who != -1); cout << jav << << ans[0][who] << n ; }
|
`timescale 1ns / 1ps
// KCP53001 2-to-1 bus arbiter.
//
// This module can be used for two purposes:
// 1. To adapt a Harvard-architecture processor to a Von Neumann-architecture
// memory bus. This use-case explains why the input ports are named I-
// and D-ports.
//
// 2. To support multiple bus masters on a common X-port. For example, you
// can have two KCP53000 CPUs, each coupled to a KCP53001 arbiter to
// yield two Von Neumann processors. Then, each of these can feed
// hierarchically into another KCP53001 to merge their combined traffic
// over a common bus.
module arbiter(
// I-Port
input [63:0] idat_i,
input [63:0] iadr_i,
input iwe_i,
input icyc_i,
input istb_i,
input [1:0] isiz_i,
input isigned_i,
output iack_o,
output [63:0] idat_o,
// D-Port
input [63:0] ddat_i,
input [63:0] dadr_i,
input dwe_i,
input dcyc_i,
input dstb_i,
input [1:0] dsiz_i,
input dsigned_i,
output dack_o,
output [63:0] ddat_o,
// X-Port
output [63:0] xdat_o,
output [63:0] xadr_o,
output xwe_o,
output xcyc_o,
output xstb_o,
output [1:0] xsiz_o,
output xsigned_o,
input xack_i,
input [63:0] xdat_i,
// Miscellaneous
input clk_i,
input reset_i
);
// The reservation bits are used only when both I and D ports request
// access at the same time. These help decide who should have priority.
//
// Priority is assigned on a first-come, first-served basis. The
// exception is when both I and D ports request access during the exact
// same clock cycle. In this case, D-port takes priority over I-port.
//
// The en_* bits are I/O enables, but also the next states for the
// reserve_* bits.
reg reserve_i, reserve_d;
wire en_i = (~reset_i & icyc_i & ~dcyc_i) |
(~reset_i & icyc_i & dcyc_i & reserve_i & ~reserve_d);
wire en_d = (~reset_i & ~icyc_i & dcyc_i) |
(~reset_i & icyc_i & dcyc_i & ~reserve_i) |
(~reset_i & icyc_i & dcyc_i & reserve_i & reserve_d);
assign xdat_o = (en_i ? idat_i : 64'd0) | (en_d ? ddat_i : 64'd0);
assign xadr_o = (en_i ? iadr_i : 64'd0) | (en_d ? dadr_i : 64'd0);
assign xwe_o = (en_i & iwe_i) | (en_d & dwe_i);
assign xcyc_o = (en_i & icyc_i) | (en_d & dcyc_i);
assign xstb_o = (en_i & istb_i) | (en_d & dstb_i);
assign xsiz_o = (en_i ? isiz_i : 2'd0) | (en_d ? dsiz_i : 2'd0);
assign xsigned_o = (en_i & isigned_i) | (en_d & dsigned_i);
assign iack_o = (en_i & xack_i);
assign dack_o = (en_d & xack_i);
assign idat_o = (en_i ? xdat_i : 64'd0);
assign ddat_o = (en_d ? xdat_i : 64'd0);
always @(posedge clk_i) begin
reserve_i <= en_i;
reserve_d <= en_d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int sum, a, b, c, ans = 0; cin >> sum >> a >> b >> c; for (int i = 0; i <= a; i += 2) for (int j = 0; j <= c; ++j) if (sum - i / 2 - 2 * j <= b && sum - i / 2 - 2 * j >= 0) ans++; cout << ans << endl; return 0; }
|
module top;
function real copy(input real r);
copy = r;
endfunction
real a, b, c, d, e, f;
initial begin
a = 0.4;
b = 0.5;
c = 0.6;
d = 2.4;
e = 2.5;
f = 2.6;
$display("a: %.1f %0d %0x %0b", copy(a), copy(a), copy(a), copy(a));
$display("b: %.1f %0d %0x %0b", copy(b), copy(b), copy(b), copy(b));
$display("c: %.1f %0d %0x %0b", copy(c), copy(c), copy(c), copy(c));
$display("d: %.1f %0d %0x %0b", copy(d), copy(d), copy(d), copy(d));
$display("e: %.1f %0d %0x %0b", copy(e), copy(e), copy(e), copy(e));
$display("f: %.1f %0d %0x %0b", copy(f), copy(f), copy(f), copy(f));
a = -0.4;
b = -0.5;
c = -0.6;
d = -2.4;
e = -2.5;
f = -2.6;
$display("a: %.1f %0d %0x %0b", copy(a), copy(a), copy(a), copy(a));
$display("b: %.1f %0d %0x %0b", copy(b), copy(b), copy(b), copy(b));
$display("c: %.1f %0d %0x %0b", copy(c), copy(c), copy(c), copy(c));
$display("d: %.1f %0d %0x %0b", copy(d), copy(d), copy(d), copy(d));
$display("e: %.1f %0d %0x %0b", copy(e), copy(e), copy(e), copy(e));
$display("f: %.1f %0d %0x %0b", copy(f), copy(f), copy(f), copy(f));
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int sieve(vector<bool> &arr, vector<int> &ans) { int res = INT_MAX; for (int i = 2; i <= sqrt(arr.size()); i++) { if (arr[i]) { for (int j = i * i; j < arr.size(); j += i) { arr[j] = false; if (ans[j] == ans[i]) ans[j]++; res = min(res, ans[j]); } } } return arr.size() > 4 ? res : 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<bool> arr(n + 2, true); vector<int> ans(n + 2, 1); int res = sieve(arr, ans); cout << res << endl; for (int i = 2; i < arr.size(); i++) cout << ans[i] << ; cout << endl; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: R_SEQ.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module R_SEQ (
address,
clock,
q);
input [7:0] address;
input clock;
output [127:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({128{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "R_SEQ.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=Rseq",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 128,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "Rseq"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "R_SEQ.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "R_SEQ.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=Rseq"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2016
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
/*
tab size 4
*/
module jt12_pg(
input clk,
input clk_en /* synthesis direct_enable */,
input rst,
// Channel frequency
input [10:0] fnum_I,
input [ 2:0] block_I,
// Operator multiplying
input [ 3:0] mul_II,
// Operator detuning
input [ 2:0] dt1_I, // same as JT51's DT1
// phase modulation from LFO
input [ 6:0] lfo_mod,
input [ 2:0] pms_I,
// phase operation
input pg_rst_II,
input pg_stop, // not implemented
output reg [ 4:0] keycode_II,
output [ 9:0] phase_VIII
);
parameter num_ch=6;
wire [4:0] keycode_I;
wire signed [5:0] detune_mod_I;
reg signed [5:0] detune_mod_II;
wire [16:0] phinc_I;
reg [16:0] phinc_II;
wire [19:0] phase_drop, phase_in;
wire [ 9:0] phase_II;
always @(posedge clk) if(clk_en) begin
keycode_II <= keycode_I;
detune_mod_II <= detune_mod_I;
phinc_II <= phinc_I;
end
jt12_pg_comb u_comb(
.block ( block_I ),
.fnum ( fnum_I ),
// Phase Modulation
.lfo_mod ( lfo_mod[6:2] ),
.pms ( pms_I ),
// Detune
.detune ( dt1_I ),
.keycode ( keycode_I ),
.detune_out ( detune_mod_I ),
// Phase increment
.phinc_out ( phinc_I ),
// Phase add
.mul ( mul_II ),
.phase_in ( phase_drop ),
.pg_rst ( pg_rst_II ),
.detune_in ( detune_mod_II ),
.phinc_in ( phinc_II ),
.phase_out ( phase_in ),
.phase_op ( phase_II )
);
jt12_sh_rst #( .width(20), .stages(4*num_ch) ) u_phsh(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_in ),
.drop ( phase_drop)
);
jt12_sh_rst #( .width(10), .stages(6) ) u_pad(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_II ),
.drop ( phase_VIII)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_M_V
`define SKY130_FD_SC_LP__O41A_M_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_m (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_m (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_M_V
|
#include <bits/stdc++.h> using namespace std; int a[5050]; int solve(int l, int r, int h) { int m, i; if (l > r) return 0; else if (l == r) return (a[l] > h); else for (i = m = l; i <= r; i++) if (a[m] > a[i]) m = i; return min(r - l + 1, a[m] - h + solve(l, m - 1, a[m]) + solve(m + 1, r, a[m])); } int main() { int i, j; int n; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; cout << solve(0, n - 1, 0) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR4_PP_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MXN = 1e5 + 20; int n, a[MXN], b[MXN], c[MXN]; vector<int> ans; void IN() { int tmp; cin >> n; for (int i = 0; i < n; i++) { cin >> tmp; a[i] = tmp; } for (int i = 0; i < n - 1; i++) { cin >> tmp; b[i] = tmp; } for (int i = 0; i < n - 2; i++) { cin >> tmp; c[i] = tmp; } } void SLV() { sort(a, a + n); sort(b, b + n - 1); sort(c, c + n - 2); for (int i = 0; i < n; i++) if (b[i] != a[i]) { ans.push_back(a[i]); break; } for (int i = 0; i < n; i++) if (c[i] != b[i]) { ans.push_back(b[i]); break; } } void OUT() { for (auto i : ans) cout << i << endl; } int main() { IN(); SLV(); OUT(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_2_V
`define SKY130_FD_SC_LP__SDFBBN_2_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_2_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_id_track.v
// Version : v1.0
// Description: To track the id received against the stored id.
// ARID and RID are tracked in case of read operations.
// AWID and BID are tracked in case of write operations.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_id_track
#(
parameter ID_WIDTH = 1
) (
input Clk ,
input rst_l ,
input [ID_WIDTH-1:0] in_push_id ,
input in_push ,
input [ID_WIDTH-1:0] in_search_id ,
input [3:0] in_clear_pos ,
input in_only_entry0,
output [3:0] out_push_pos ,
output [3:0] out_search_hit,
output [3:0] out_free
);
reg [ID_WIDTH:0] id_arr0_ff, id_arr1_ff, id_arr2_ff, id_arr3_ff;
reg [3:0] push_pos_ff, push_pos_2ff;
reg [3:0] in_clear_pos_ff;
wire [ID_WIDTH:0] push_id = { 1'b1, in_push_id[ID_WIDTH-1:0] };
wire [3:0] push_search = { (push_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] free_pre = { ~id_arr3_ff[ID_WIDTH], ~id_arr2_ff[ID_WIDTH],
~id_arr1_ff[ID_WIDTH], ~id_arr0_ff[ID_WIDTH] };
wire [3:0] free = (in_only_entry0) ? { 3'b000, free_pre[0] } : free_pre[3:0];
wire [3:0] first_free = (free[0]) ? 4'h1 :
(free[1]) ? 4'h2 :
(free[2]) ? 4'h4 :
(free[3]) ? 4'h8 : 4'h0;
wire [3:0] push_pos = (in_push == 1'b0) ? 4'h0 :
(push_search[3:0] != 4'h0) ? push_search[3:0] :
first_free[3:0];
wire [ID_WIDTH:0] search_id = { 1'b1, in_search_id[ID_WIDTH-1:0] };
wire [3:0] search_pos = { (search_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] do_clear = ~push_pos_ff[3:0] & ~push_pos_2ff[3:0] &
in_clear_pos_ff[3:0];
wire [ID_WIDTH:0] id_arr0 = (push_pos[0]) ? push_id[ID_WIDTH:0] :
{ (do_clear[0]) ? 1'b0:id_arr0_ff[ID_WIDTH], id_arr0_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr1 = (push_pos[1]) ? push_id[ID_WIDTH:0] :
{ (do_clear[1]) ? 1'b0:id_arr1_ff[ID_WIDTH], id_arr1_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr2 = (push_pos[2]) ? push_id[ID_WIDTH:0] :
{ (do_clear[2]) ? 1'b0:id_arr2_ff[ID_WIDTH], id_arr2_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr3 = (push_pos[3]) ? push_id[ID_WIDTH:0] :
{ (do_clear[3]) ? 1'b0:id_arr3_ff[ID_WIDTH], id_arr3_ff[ID_WIDTH-1:0] };
always @(posedge Clk) begin
id_arr0_ff[ID_WIDTH:0] <= (rst_l) ? id_arr0[ID_WIDTH:0] : 1'b0;
id_arr1_ff[ID_WIDTH:0] <= (rst_l) ? id_arr1[ID_WIDTH:0] : 1'b0;
id_arr2_ff[ID_WIDTH:0] <= (rst_l) ? id_arr2[ID_WIDTH:0] : 1'b0;
id_arr3_ff[ID_WIDTH:0] <= (rst_l) ? id_arr3[ID_WIDTH:0] : 1'b0;
push_pos_ff[3:0] <= (rst_l) ? push_pos[3:0] : 4'h0;
push_pos_2ff[3:0] <= (rst_l) ? push_pos_ff[3:0] : 4'h0;
in_clear_pos_ff[3:0] <= (rst_l) ? in_clear_pos[3:0] : 4'h0;
end
assign out_search_hit[3:0] = search_pos[3:0];
assign out_push_pos[3:0] = push_pos[3:0];
assign out_free[3:0] = free[3:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const char nl = n ; const int MAX_N = 100011; const long long INF = (1 << 29) + 123; const long long MOD = 1000000007; const long double PI = 4 * atan((long double)1); template <typename T> bool ckmin(T& a, const T& b) { return a > b ? a = b, 1 : 0; } template <typename T> bool ckmax(T& a, const T& b) { return b > a ? a = b, 1 : 0; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << H << ; dbg_out(T...); } mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); const int MX = 1 << 20; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; int m = n; vector<int> LOC[n + 1]; int A[n]; for (int i = 0; i < n; i++) { cin >> A[i]; LOC[A[i]].push_back(i); } int hi = 0, best = -1; for (int i = 1; i <= m; i++) if (ckmax(hi, (int)LOC[i].size())) best = i; bool done = 0; for (int i = 1; i <= m; i++) if (i != best && hi == (int)LOC[i].size()) done = 1; if (done) { cout << n << nl; return 0; } n += 2; int a[n]; for (int i = 0; i < n - 2; i++) a[i + 1] = A[i]; a[0] = a[n - 1] = best; vector<int> loc[n + 1]; for (int i = 0; i < n; i++) loc[a[i]].push_back(i); hi = (int)loc[best].size(); int idxBest[n]; for (int i = 0; i < n; i++) if (i == 0) idxBest[i] = 1; else idxBest[i] = idxBest[i - 1] + (a[i] == best); int ans = 0; int SQRTN = sqrt(n) - 100; for (int i = 1; i <= m; i++) { int SZ = (int)loc[i].size(); if (i == best || !SZ) continue; if (SZ > SQRTN) { int j = 0, k = 0; int sum = 0; int firstLoc[2 * n + 1]; for (int ii = 0; ii < 2 * n + 1; ii++) firstLoc[ii] = -1; firstLoc[sum + n] = 0; while (j != hi - 1 || k != SZ) { int curPos; if (k < SZ && loc[best][j] > loc[i][k]) { curPos = loc[i][k] + 1; ckmax(ans, curPos - 1 - firstLoc[sum + n]); sum++; k++; } else { curPos = loc[best][j] + 1; ckmax(ans, curPos - 1 - firstLoc[sum + n]); sum--; j++; } if (firstLoc[sum + n] == -1) firstLoc[sum + n] = curPos; } ckmax(ans, loc[best][j] - firstLoc[sum + n]); } else { int kkk = 0; for (int kk = 0; kk < SZ; kk++) { int j = max(0, idxBest[loc[i][kk]] - SZ - 2); int jEnd = min(hi, idxBest[loc[i][kk]] + SZ + 2); while (kkk < SZ && loc[best][j] > loc[i][kkk]) kkk++; int k = kkk; int PAD = 2 * SZ + 5; int firstLoc[2 * PAD + 1]; for (int ii = 0; ii < 2 * PAD + 1; ii++) firstLoc[ii] = -1; int sum = -1; if (j == 0) firstLoc[0 + PAD] = 0; firstLoc[sum + PAD] = loc[best][j] + 1; j++; while (j < jEnd) { int curPos; if (k < SZ && loc[i][k] < loc[best][j]) { curPos = loc[i][k] + 1; ckmax(ans, loc[i][k] - firstLoc[sum + PAD]); sum++; k++; } else { curPos = loc[best][j] + 1; ckmax(ans, loc[best][j] - firstLoc[sum + PAD]); sum--; j++; } if (firstLoc[sum + PAD] == -1) firstLoc[sum + PAD] = curPos; } if (j != hi) ckmax(ans, loc[best][j] - firstLoc[sum + PAD]); } } } cout << ans << nl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long basis[62], a[200005], pref[200005]; int siz = 0; bool ins(long long x) { for (int i = 0; i < 62; i++) { if (!(x & (1LL << i))) continue; if (!basis[i]) { basis[i] = x; siz++; return true; } else { x ^= basis[i]; } } return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; pref[i] = a[i] ^ (i ? pref[i - 1] : 0); } if (pref[n - 1] == 0) { cout << -1 << endl; } else { for (int i = 0; i < n; i++) { ins(pref[i]); } cout << siz << endl; } }
|
`default_nettype none
// ============================================================================
module error_counter #
(
parameter COUNT_WIDTH = 24,
parameter DELAY_TAPS = 32,
parameter TRIGGER_INTERVAL = 20,//100000000,
parameter HOLDOFF_TIME = 4,//10,
parameter MEASURE_TIME = 10//50000
)
(
input wire CLK,
input wire RST,
input wire I_STB,
input wire I_ERR,
output wire DLY_LD,
output wire [$clog2(DELAY_TAPS)-1:0] DLY_CNT,
output wire O_STB,
output wire [COUNT_WIDTH*DELAY_TAPS-1:0] O_DAT
);
// ============================================================================
// FSM
integer fsm;
localparam FSM_IDLE = 'h00;
localparam FSM_SETUP = 'h10;
localparam FSM_HOLDOFF = 'h20;
localparam FSM_PREPARE = 'h30;
localparam FSM_MEASURE = 'h40;
localparam FSM_STORE = 'h50;
localparam FSM_OUTPUT = 'h60;
// ============================================================================
// Counters
reg [32:0] ps_cnt;
reg [$clog2(DELAY_TAPS)-1:0] dly_cnt;
initial ps_cnt <= TRIGGER_INTERVAL - 1;
always @(posedge CLK)
case (fsm)
FSM_IDLE: ps_cnt <= ps_cnt - 1;
FSM_SETUP: ps_cnt <= HOLDOFF_TIME - 1;
FSM_HOLDOFF: ps_cnt <= ps_cnt - 1;
FSM_PREPARE: ps_cnt <= MEASURE_TIME - 1;
FSM_MEASURE: ps_cnt <= ps_cnt - 1;
FSM_OUTPUT: ps_cnt <= TRIGGER_INTERVAL - 1;
endcase
always @(posedge CLK)
case (fsm)
FSM_IDLE: dly_cnt <= 0;
FSM_STORE: dly_cnt <= dly_cnt + 1;
endcase
// ============================================================================
// IDELAY control
assign DLY_LD = (fsm == FSM_SETUP);
assign DLY_CNT = dly_cnt;
// ============================================================================
// Error counter and output shift register
reg [(COUNT_WIDTH*DELAY_TAPS)-1:0] o_dat_sr;
reg [COUNT_WIDTH-1:0] err_cnt;
always @(posedge CLK)
case (fsm)
FSM_PREPARE: err_cnt <= 0;
FSM_MEASURE: if(I_STB) err_cnt <= err_cnt + I_ERR;
endcase
always @(posedge CLK)
if (fsm == FSM_STORE)
o_dat_sr <= (o_dat_sr << COUNT_WIDTH) | err_cnt;
// ============================================================================
// Control FSM
always @(posedge CLK)
if (RST)
fsm <= FSM_IDLE;
else case (fsm)
FSM_IDLE: if (ps_cnt == 0) fsm <= FSM_SETUP;
FSM_SETUP: fsm <= FSM_HOLDOFF;
FSM_HOLDOFF: if (ps_cnt == 0) fsm <= FSM_PREPARE;
FSM_PREPARE: fsm <= FSM_MEASURE;
FSM_MEASURE: if (ps_cnt == 0) fsm <= FSM_STORE;
FSM_STORE: if (dly_cnt == (DELAY_TAPS-1))
fsm <= FSM_OUTPUT;
else
fsm <= FSM_SETUP;
FSM_OUTPUT: fsm <= FSM_IDLE;
endcase
// ============================================================================
// Output
assign O_STB = (fsm == FSM_OUTPUT);
assign O_DAT = o_dat_sr;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int number; cin >> number; long long ans = number; while (1) { int x = 100000000; for (int i = 2; i <= sqrt(number); i++) { if (number % i == 0) { x = min(x, i); } } if (x == 100000000) break; ans += number / x; number = number / x; } cout << ans + 1; }
|
#include <bits/stdc++.h> using namespace std; int mat[100001], mat2[100001]; long long k, suma, a, b, s, c; int n; map<int, int> mapa; long long ct; int main() { cin >> n >> k; for (int i = 0; i < n; ++i) { cin >> mat[i]; mapa[mat[i]]++; } sort(mat, mat + n); suma = 1; c = 1; for (int i = 0; i < n; i++) { if (i == 0) { } else if (mat[i] == mat[i - 1]) { suma += n; continue; } ct = mapa[mat[i]]; if (suma + ct * n > k) { a = mat[i]; s = k - suma; b = mat[(int)(s / ct)]; break; } suma += n; } cout << a << << b << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9; long double _A[19][100009], _b[19], _c[100009]; struct LPSolver { int m, n; vector<int> B, N; vector<vector<long double> > D; LPSolver(const vector<vector<long double> > &A, const vector<long double> &b, const vector<long double> &c) : m(b.size()), n(c.size()), N(n + 1), B(m), D(m + 2, vector<long double>(n + 2)) { for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) D[i][j] = A[i][j]; for (int i = 0; i < m; i++) { B[i] = n + i; D[i][n] = -1; D[i][n + 1] = b[i]; } for (int j = 0; j < n; j++) { N[j] = j; D[m][j] = -c[j]; } N[n] = -1; D[m + 1][n] = 1; } void Pivot(int r, int s) { double inv = 1.0 / D[r][s]; for (int i = 0; i < m + 2; i++) if (i != r) for (int j = 0; j < n + 2; j++) if (j != s) D[i][j] -= D[r][j] * D[i][s] * inv; for (int j = 0; j < n + 2; j++) if (j != s) D[r][j] *= inv; for (int i = 0; i < m + 2; i++) if (i != r) D[i][s] *= -inv; D[r][s] = inv; swap(B[r], N[s]); } bool Simplex(int phase) { int x = phase == 1 ? m + 1 : m; while (true) { int s = -1; for (int j = 0; j <= n; j++) { if (phase == 2 && N[j] == -1) continue; if (s == -1 || D[x][j] < D[x][s] || D[x][j] == D[x][s] && N[j] < N[s]) s = j; } if (D[x][s] > -EPS) return true; int r = -1; for (int i = 0; i < m; i++) { if (D[i][s] < EPS) continue; if (r == -1 || D[i][n + 1] / D[i][s] < D[r][n + 1] / D[r][s] || (D[i][n + 1] / D[i][s]) == (D[r][n + 1] / D[r][s]) && B[i] < B[r]) r = i; } if (r == -1) return false; Pivot(r, s); } } long double Solve(vector<long double> &x) { int r = 0; for (int i = 1; i < m; i++) if (D[i][n + 1] < D[r][n + 1]) r = i; if (D[r][n + 1] < -EPS) { Pivot(r, n); if (!Simplex(1) || D[m + 1][n + 1] < -EPS) return -numeric_limits<long double>::infinity(); for (int i = 0; i < m; i++) if (B[i] == -1) { int s = -1; for (int j = 0; j <= n; j++) if (s == -1 || D[i][j] < D[i][s] || D[i][j] == D[i][s] && N[j] < N[s]) s = j; Pivot(i, s); } } if (!Simplex(2)) return numeric_limits<long double>::infinity(); x = vector<long double>(n); for (int i = 0; i < m; i++) if (B[i] < n) x[B[i]] = D[i][n + 1]; return D[m][n + 1]; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, i; long double p, q; cin >> n >> p >> q; m = 2; for (i = 0; i < n; i++) { cin >> _A[0][i] >> _A[1][i]; _A[0][i] = -_A[0][i]; _A[1][i] = -_A[1][i]; _c[i] = -1; } _b[0] = -p; _b[1] = -q; vector<vector<long double> > A(m); vector<long double> b(_b, _b + m); vector<long double> c(_c, _c + n); for (i = 0; i < m; i++) A[i] = vector<long double>(_A[i], _A[i] + n); LPSolver solver(A, b, c); vector<long double> x; long double value = solver.Solve(x); cout << fixed << setprecision(10) << (-value) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1100, M = 2 * 1e5 + 10, INF = 1e9 + 10; pair<int, int> e[M]; int dp[N][N]; vector<pair<pair<int, int>, pair<int, int> > > que[M]; bool ans[M]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, q; cin >> n >> m >> q; for (int i = 0; i < m; i++) cin >> e[i].first >> e[i].second; for (int i = 0; i < q; i++) { int l, r, s, t; cin >> l >> r >> s >> t; l--; que[l].push_back({{s, t}, {r, i}}); } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i != j) dp[i][j] = INF; for (int i = m - 1; i >= 0; i--) { int u = e[i].first, v = e[i].second; dp[u][v] = dp[v][u] = i; for (int j = 1; j <= n; j++) { if (j == u || j == v) continue; if (dp[u][j] > dp[v][j]) dp[u][j] = dp[v][j]; else dp[v][j] = dp[u][j]; } for (auto X : que[i]) { int s = X.first.first, t = X.first.second, r = X.second.first, id = X.second.second; if (dp[s][t] < r) ans[id] = true; else ans[id] = false; } } for (int i = 0; i < q; i++) { if (ans[i]) cout << Yes n ; else cout << No n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, a[N] = {}, tot = 0; bool v[N] = {}; void dfs(int s) { v[s] = true; if (!v[s * 2 % n]) dfs(s * 2 % n); if (!v[s * 2 % n + 1]) dfs(s * 2 % n + 1); a[++tot] = s; } int main() { cin >> n; if (n % 2) puts( -1 ); else { dfs(0); for (int i = tot; i >= 0; --i) printf( %d%c , a[i], n [i == 0]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using ll = long long; void solve() { string s; cin >> s; int m = ((int)(s).size()); vi a(m); a[0] = ((s[0] == - ) ? -1 : 1); for (__typeof(m) i = (1) - ((1) > (m)); i != (m) - ((1) > (m)); i += 1 - 2 * ((1) > (m))) { if (s[i] == - ) { a[i] = a[i - 1] - 1; } else { a[i] = a[i - 1] + 1; } } ll res = m; int i = 0, t = -1; while (i < m) { if (a[i] != t) { i++; } else { t--; res += (i + 1); } } cout << res << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:26:30 10/31/2016
// Design Name: SeparadorNumeros
// Module Name: /home/fede/DatosWindows/Facultad/Arquitectura de Computadoras/WorkspaceXilinxIse/UART/UART_Arquitectura/testSeparador.v
// Project Name: UART
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: SeparadorNumeros
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testSeparador;
// Inputs
reg [31:0] alu_in;
reg start_conversion;
reg tx_done;
reg clk;
// Outputs
wire [7:0] value_to_send;
wire tx_start;
// Instantiate the Unit Under Test (UUT)
SeparadorNumeros uut (
.alu_in(alu_in),
.start_conversion(start_conversion),
.tx_done(tx_done),
.clk(clk),
.value_to_send(value_to_send),
.tx_start(tx_start)
);
initial begin
// Initialize Inputs
clk = 0;
alu_in = 0;
start_conversion = 0;
tx_done = 1;
alu_in = ;
#4;
start_conversion = 1;
#4;
start_conversion = 0;
#400;
alu_in = 43;
#4;
start_conversion = 1;
#4;
start_conversion = 0;
end
always@(posedge clk)
begin
if(tx_start)
begin
tx_done = 0;
#30;
tx_done = 1;
end
end
always
begin
#1; clk = 1;
#1; clk = 0;
end
endmodule
|
`timescale 1 ps / 1 ps
(* message_disable = "14320" *) module alt_mem_ddrx_fifo
# (
parameter
CTL_FIFO_DATA_WIDTH = 8,
CTL_FIFO_ADDR_WIDTH = 3
)
(
// general
ctl_clk,
ctl_reset_n,
// pop free fifo entry
get_valid,
get_ready,
get_data,
// push free fifo entry
put_valid,
put_ready,
put_data
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_FIFO_DEPTH = (2 ** CTL_FIFO_ADDR_WIDTH);
localparam CTL_FIFO_TYPE = "SCFIFO"; // SCFIFO, CUSTOM
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free fifo entry
input get_ready;
output get_valid;
output [CTL_FIFO_DATA_WIDTH-1:0] get_data;
// push free fifo entry
output put_ready;
input put_valid;
input [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// port type declaration
// -----------------------------
wire get_valid;
wire get_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] get_data;
wire put_valid;
wire put_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_FIFO_DATA_WIDTH-1:0] fifo [CTL_FIFO_DEPTH-1:0];
reg [CTL_FIFO_DEPTH-1:0] fifo_v;
wire fifo_get;
wire fifo_put;
wire fifo_empty;
wire fifo_full;
wire zero;
// -----------------------------
// module definition
// -----------------------------
assign fifo_get = get_valid & get_ready;
assign fifo_put = put_valid & put_ready;
assign zero = 1'b0;
generate
begin : gen_fifo_instance
if (CTL_FIFO_TYPE == "SCFIFO")
begin
assign get_valid = ~fifo_empty;
assign put_ready = ~fifo_full;
scfifo #(
.add_ram_output_register ( "ON" ),
.intended_device_family ( "Stratix IV" ),
.lpm_numwords ( CTL_FIFO_DEPTH ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( CTL_FIFO_DATA_WIDTH ),
.lpm_widthu ( CTL_FIFO_ADDR_WIDTH ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( "ON" )
) scfifo_component (
.aclr (~ctl_reset_n),
.clock (ctl_clk),
.data (put_data),
.rdreq (fifo_get),
.wrreq (fifo_put),
.empty (fifo_empty),
.full (fifo_full),
.q (get_data),
.almost_empty (),
.almost_full (),
.sclr (zero),
.usedw ()
);
end
else // CTL_FIFO_TYPE == "CUSTOM"
begin
assign get_valid = fifo_v[0];
assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
assign get_data = fifo[0];
// put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
// initialize every entry
fifo [i] <= 0;
fifo_v [i] <= 1'b0;
end
end
else
begin
// get request code must be above put request code
if (fifo_get)
begin
// on a get request, fifo entry is shifted to move next entry to head
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
fifo_v [i-1] <= fifo_v [i];
fifo [i-1] <= fifo [i];
end
fifo_v [CTL_FIFO_DEPTH-1] <= 0;
end
if (fifo_put)
begin
// on a put request, next empty fifo entry is written
if (~fifo_get)
begin
// put request only
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i] <= 1'b1;
fifo [i] <= put_data;
end
end
if (~fifo_v[0])
begin
fifo_v [0] <= 1'b1;
fifo [0] <= put_data;
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i-1] <= 1'b1;
fifo [i-1] <= put_data;
end
end
if (~fifo_v[0])
begin
$display("error - fifo underflow");
end
end
end
end
end
end
end
endgenerate
endmodule
//
// ASSERT
//
// fifo underflow
//
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5, M = 1e5; int dfn, cur[M + 1], in[N + 1], pre[N + 1], fin[N + 1], r[N + 1], sz[N + 1]; vector<int> adj[N + 1]; int dfs(int u, int a) { sz[u] = 1; r[u] = a; pre[u] = ++dfn; for (auto v : adj[u]) sz[u] += dfs(v, a); fin[u] = ++dfn; return sz[u]; } int main() { int n, m, k, q; scanf( %d%d%d%d , &n, &m, &k, &q); for (int i = (0), i_end = (k); i < i_end; ++i) { int a, b; scanf( %d%d , &a, &b); if (cur[b]) { ++in[a]; adj[cur[b]].push_back(a); } cur[b] = a; } for (int i = (1), i_end = (n + 1); i < i_end; ++i) if (!in[i]) dfs(i, i); for (int i = (0), i_end = (q); i < i_end; ++i) { int x, y; scanf( %d%d , &x, &y); y = cur[y]; if (r[x] == r[y] && pre[y] > pre[x] && fin[y] < fin[x]) printf( %d n , sz[x]); else puts( 0 ); } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module defines the LDEXP function, which multiplies a floating point number by 2^(shift_in).
// The result is a valid floating point number within single-precision range, +/- INF or 0.
// If a denormalized number is supplied as input, the result will be zero (until we add denormalized
// number support).
//
module acl_fp_ldexp_double_hc(clock, resetn, dataa, datab, valid_in, valid_out, stall_in, stall_out, result);
input clock, resetn;
input [63:0] dataa;
input [31:0] datab;
input valid_in, stall_in;
output valid_out, stall_out;
output [63:0] result;
// Cycle 1: Test inputs and compute resulting exponents.
wire [10:0] exponent_in = dataa[62:52];
wire [51:0] mantissa_in = dataa[51:0];
wire sign_in = dataa[63];
wire [31:0] shift_in = datab;
wire [31:0] intermediate_exp = shift_in + {1'b0, exponent_in};
reg [10:0] exp_stage_1;
reg [51:0] man_stage_1;
reg sign_stage_1;
reg stage_1_valid;
wire enable_stage_1;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exp_stage_1 <= 11'dx;
man_stage_1 <= 52'dx;
sign_stage_1 <= 1'bx;
stage_1_valid <= 1'b0;
end
else if (enable_stage_1)
begin
stage_1_valid <= valid_in;
sign_stage_1 <= sign_in;
if (exponent_in == 11'h7ff)
begin
// NaN / Inf input, so produce an NaN / Inf output.
man_stage_1 <= mantissa_in;
exp_stage_1 <= exponent_in;
end
else
if (intermediate_exp[31] | (exponent_in == 11'd0))
begin
// This flushes denorms to zero, even is a denorm is an input to this module.
man_stage_1 <= 52'd0;
exp_stage_1 <= 11'd0;
end
else if ({1'b0, intermediate_exp[30:0]} >= 12'h7ff)
begin
// infinity
man_stage_1 <= 52'd0;
exp_stage_1 <= 11'h7ff;
end
else if (intermediate_exp[10:0] == 11'd0)
begin
// If exponent ends up at 0, then flush the result to 0.
// This is the flushing of a denorm to zero after the ldexp operation.
man_stage_1 <= 52'd0;
exp_stage_1 <= 11'd0;
end
else
begin
man_stage_1 <= mantissa_in;
exp_stage_1 <= intermediate_exp[10:0];
end
end
end
assign enable_stage_1 = ~stage_1_valid | ~stall_in;
assign valid_out = stage_1_valid;
assign stall_out = stage_1_valid & stall_in;
assign result = {sign_stage_1, exp_stage_1, man_stage_1};
endmodule
|
#include <bits/stdc++.h> int isprime(long long p) { int i; double max = sqrt(p); for (i = 2; i <= max; i++) if (p % i == 0) break; if (i > max && p != 1) return 1; return 0; } long long gcd(long long a, long long b) { long long i; for (i = a < b ? a : b; i > 0; i--) if ((a % i == 0) && (b % i == 0)) break; return i; } int comp(const void *a, const void *b) { return (*(int *)a - *(int *)b); } int issame(int *a, int *b, int l) { qsort(a, l, sizeof(int), comp); qsort(b, l, sizeof(int), comp); int i; for (i = 0; i < l; i++) if (a[i] != b[i]) break; if (i == l) return 1; return 0; } void swap(int *a, int *b) { int x = *a; *a = *b; *b = x; } int arrmax(int *a, int l) { int i; int max = a[0]; for (i = 1; i < l; i++) if (a[i] > max) max = a[i]; return max; } int arrmin(int *a, int l) { int i; int min = a[0]; for (i = 1; i < l; i++) if (a[i] < min) min = a[i]; return min; } long long fact(int a) { long long p = 1; while (a > 0) p *= a--; return p; } int min(int a, int b) { if (a > b) return b; return a; } int max(int a, int b) { if (a < b) return b; return a; } void sieve(int *a, int n) { n--; long long i, j; for (i = 2; i <= n; i++) a[i] = 0; for (i = 2; i <= n; i++) if (!a[i]) for (j = i * i; j <= n; j += i) if (!a[j]) a[j]++; } int main(void) { int t; scanf( %d , &t); while (t--) { char b[100]; scanf( %s , b); int l = strlen(b); char c[l / 2 + 1]; int i; for (i = 1; i < l; i += 2) c[i / 2 + 1] = b[i]; c[0] = b[0]; for (i = 0; i < l / 2 + 1; i++) printf( %c , c[i]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> namespace { using namespace std; template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (T &t : v) is >> t; return is; } template <typename T> bool space(vector<T>) { return false; } template <typename T> bool space(T) { return true; } bool space(char) { return false; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (const T &t : v) { os << t << (space(t) ? : ); } os << n ; return os; } long long gcd(long long a, long long b) { while (b) { long long mod = a % b; a = b; b = mod; } return a; } template <typename T> void incr_sort(vector<T> &v) { stable_sort(v.begin(), v.end()); } template <typename T> void decr_sort(vector<T> &v) { stable_sort(v.rbegin(), v.rend()); } long long sum(const vector<int> &v) { long long s = 0; for (long long value : v) s += value; return s; } vector<long long> prefix_sum(const vector<int> &v) { vector<long long> res(v.size()); res[0] = v[0]; for (int i = 1; i < v.size(); ++i) res[i] = res[i - 1] + v[i]; return res; } } // namespace void solve(); int main() { cin.tie(nullptr); cout.tie(nullptr); ios::sync_with_stdio(false); int t = 1; cin >> t; for (int i = 0; i < t; ++i) solve(); return 0; } void solve() { int h, n; cin >> h >> n; vector<int> p(n); cin >> p; p.push_back(0); long long ans = 0; int i = 0; while (p[i] > 2) { if (p[i + 1] < p[i] - 1) p[i] = p[i + 1] + 1; if (p[i] <= 2) break; if (p[i + 2] == p[i + 1] - 1) i += 2; else { ++ans; p[i + 1] = p[i + 2] + 1; i++; } } cout << ans << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_BLACKBOX_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_1_V
`define SKY130_FD_SC_HS__MUX2I_1_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_1_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 33333; const int mod = 998244353, G = 3; int n, k, T, a[MAXN], W, rev[MAXN], gen[MAXN]; vector<int> vec[MAXN]; inline int qpow(int a, int b) { int re = 1; for (; b; b >>= 1, a = 1ll * a * a % mod) if (b & 1) re = 1ll * re * a % mod; return re; } inline int pls(int x, int y) { return x + y >= mod ? x + y - mod : x + y; } inline void add(int &x, int y) { x = x + y >= mod ? x + y - mod : x + y; } void NTT(vector<int> &arr, int len, int flg) { for (int i = 0; i < len; ++i) if (i < rev[i]) swap(arr[i], arr[rev[i]]); for (int v, i = 2, B = W >> 1; i <= len; i <<= 1, B >>= 1) for (int j = 0; j < len; j += i) for (int k = j, x = 0; k < j + i / 2; ++k, x += B) arr[k + i / 2] = pls( arr[k], mod - (v = 1ll * arr[k + i / 2] * gen[flg == 1 ? x : W - x] % mod)), add(arr[k], v); if (flg == -1) { int iv = qpow(len, mod - 2); for (int i = 0; i < len; ++i) arr[i] = 1ll * arr[i] * iv % mod; } } vector<int> solve(int l, int r) { if (l == r) return vec[l]; int mid = (l + r) >> 1; vector<int> L = solve(l, mid), R = solve(mid + 1, r); int len = 1; while (len <= r - l + 1) len <<= 1; for (int i = 1; i < len; ++i) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) * (len >> 1)); L.resize(len), R.resize(len); NTT(L, len, 1), NTT(R, len, 1); for (int i = 0; i < len; ++i) L[i] = 1ll * L[i] * R[i] % mod; NTT(L, len, -1); L.resize(r - l + 2); return L; } int main() { scanf( %d%d , &n, &k); for (W = 1; W <= n; W <<= 1) ; gen[0] = 1, gen[1] = qpow(G, (mod - 1) / W); for (int i = 2; i <= W; ++i) gen[i] = 1ll * gen[i - 1] * gen[1] % mod; for (int i = 1; i <= n; ++i) scanf( %d , &a[i]), vec[i].resize(2), vec[i][0] = 1; int op, q, x, y, d; for (scanf( %d , &T); T--;) { scanf( %d%d%d , &op, &q, &x); if (op == 2) scanf( %d , &y); else y = x; scanf( %d , &d); for (int i = 1; i <= n; ++i) vec[i][1] = ((q - ((x <= i && i <= y) ? (op == 1 ? d : a[i] + d) : a[i])) % mod + mod) % mod; vector<int> ans = solve(1, n); printf( %d n , ans[k]); } }
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for $ivlh_{rising,falling}_edge VPI functions
// (mostly used by the VHDL frontend).
module main;
reg a, b;
always @(a or b) begin
if ($ivlh_rising_edge(a))
$display("%0t: rising_edge(a)", $time);
if ($ivlh_falling_edge(a))
$display("%0t: falling_edge(a)", $time);
if ($ivlh_rising_edge(b))
$display("%0t: rising_edge(b)", $time);
if ($ivlh_falling_edge(b))
$display("%0t: falling_edge(b)", $time);
end
initial begin
#1 a <= 1;
#1 b <= 1;
#1 a <= 0;
#1 b <= 0;
#1 a <= 0; // nothing should be detected
#1 b <= 0;
#1 a <= 1;
#1 b <= 1;
#1 a <= 1; // nothing should be detected
#1 b <= 1;
#1 a <= 0;
#1 b <= 0;
#1 $finish(0);
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int k, i, j, l = 0; cin >> k >> i; for (j = 1; j <= 10; j++) { l = k * j; if (l % 10 == 0 || l % 10 == i) { cout << j; break; } } }
|
module membus_2_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_wr_rs,
input wire m_rq_cyc,
input wire m_rd_rq,
input wire m_wr_rq,
input wire [21:35] m_ma,
input wire [18:21] m_sel,
input wire m_fmc_select,
input wire [0:35] m_mb_write,
output wire m_addr_ack,
output wire m_rd_rs,
output wire [0:35] m_mb_read,
// Slave 0
output wire s0_wr_rs,
output wire s0_rq_cyc,
output wire s0_rd_rq,
output wire s0_wr_rq,
output wire [21:35] s0_ma,
output wire [18:21] s0_sel,
output wire s0_fmc_select,
output wire [0:35] s0_mb_write,
input wire s0_addr_ack,
input wire s0_rd_rs,
input wire [0:35] s0_mb_read,
// Slave 1
output wire s1_wr_rs,
output wire s1_rq_cyc,
output wire s1_rd_rq,
output wire s1_wr_rq,
output wire [21:35] s1_ma,
output wire [18:21] s1_sel,
output wire s1_fmc_select,
output wire [0:35] s1_mb_write,
input wire s1_addr_ack,
input wire s1_rd_rs,
input wire [0:35] s1_mb_read
);
wire [0:35] mb_out = m_mb_write | s0_mb_read | s1_mb_read;
assign m_addr_ack = s0_addr_ack | s1_addr_ack;
assign m_rd_rs = s0_rd_rs | s1_rd_rs;
assign m_mb_read = mb_out;
assign s0_wr_rs = m_wr_rs;
assign s0_rq_cyc = m_rq_cyc;
assign s0_rd_rq = m_rd_rq;
assign s0_wr_rq = m_wr_rq;
assign s0_ma = m_ma;
assign s0_sel = m_sel;
assign s0_fmc_select = m_fmc_select;
assign s0_mb_write = mb_out;
assign s1_wr_rs = m_wr_rs;
assign s1_rq_cyc = m_rq_cyc;
assign s1_rd_rq = m_rd_rq;
assign s1_wr_rq = m_wr_rq;
assign s1_ma = m_ma;
assign s1_sel = m_sel;
assign s1_fmc_select = m_fmc_select;
assign s1_mb_write = mb_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> tree[100005]; int cat[100005]; bool vis[100005]; int n, m, ans = 0; void dfs(int root, int num) { vis[root] = true; if (cat[root]) num++; else num = 0; if (num > m) return; if (tree[root].size() == 1 && vis[tree[root][0]]) { ans++; return; } for (int i = 0; i < tree[root].size(); i++) { int c = tree[root][i]; if (!vis[c]) dfs(c, num); } } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &cat[i]); for (int i = 0; i < n - 1; i++) { int f, s; scanf( %d %d , &f, &s); tree[f].push_back(s); tree[s].push_back(f); } dfs(1, 0); cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NSR_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_NSR_SYMBOL_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NSR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NSR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, A, cf, cm, m; struct node { long long x; int i; } a[100001]; long long sum[100001]; long long ans = 0; bool cmp(node a, node b) { return a.x < b.x; } bool cmp1(node a, node b) { return a.i < b.i; } long long minc = 0; long long bsearch(long long x) { int l = 0; int r = n; while (l < r) { int mid = l + (r - l) / 2; if (a[mid].x > x) r = mid; else l = mid + 1; } return l; } void solve() { for (int i = 0; i < n; ++i) { long long num = m - (A * (long long)i - (sum[n - 1] - sum[n - 1 - i])); if (num < 0) break; long long l = a[0].x - 1; long long r = A; while (l < r) { long long mid = l + (r - l) / 2; long long k = bsearch(mid) - 1; if (k + i >= n) k = n - 1 - i; long long sum1 = (mid * (k + 1) - sum[k]); if (sum1 > num) r = mid; else l = mid + 1; } l--; if (ans <= (long long)i * cf + (long long)l * cm) { ans = (long long)i * cf + (long long)l * cm; minc = l; } } } int main() { while (cin >> n >> A >> cf >> cm >> m) { for (int i = 0; i < n; ++i) { scanf( %lld , &a[i].x); a[i].i = i; } a[n].x = A + 1; a[n].i = n; ans = 0; sort(a, a + n, cmp); sum[0] = a[0].x; for (int i = 1; i < n; ++i) sum[i] = sum[i - 1] + a[i].x; if (A * n <= sum[n - 1] + m) { ans = n * cf + A * cm; minc = A; } else { solve(); } for (int i = 0; i < n; ++i) { if (a[i].x < minc) { m -= minc - a[i].x; a[i].x = minc; } else break; } for (int i = n - 1; i >= 0; --i) { if (A - a[i].x <= m) { m -= A - a[i].x; a[i].x = A; } else { a[i].x += m; m = 0; break; } } sort(a, a + n, cmp1); printf( %lld n , ans); for (int i = 0; i < n; ++i) { if (i == n - 1) printf( %lld n , a[i].x); else printf( %lld , a[i].x); } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:17:06 09/03/2013
// Design Name:
// Module Name: lab2_labkit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab2_labkit(clk, rst, reprogram, sensor, walk_btn,
bit_a_new_time, bit_b_new_time, bit_c_new_time, bit_d_new_time, bit_a_time_sel, bit_b_time_sel,
led_rm, led_ym, leg_gm, led_rs, led_ys, led_gs,led_walk, siete);
input clk;
input rst;
input reprogram;
input sensor;
input walk_btn;
input bit_a_new_time;
input bit_b_new_time;
input bit_c_new_time;
input bit_d_new_time;
input bit_a_time_sel;
input bit_b_time_sel;
output wire [6:0] siete;
output wire led_rm, led_ym, leg_gm, led_rs, led_ys, led_gs, led_walk;
//Variables que obtienen los resultados del syncronizer
wire sensor_out, reprogram_out, walk_register, rst_out;
//Write register para la maquina de estados
//Se obtiene de walk register
wire wr_fsm;
//Valores devueltos por la maquina de estados
wire wr_reset, start_timer;
wire [1:0] interval;
//Valor devuelto por el time parameters
wire [3:0] tiempo_espera;
//Senal que indica que se acabo del tiempo de espera
wire expired;
//Sincroniza las senales
synchronizer mod_sync(clk, rst, sensor, reprogram, walk_btn, rst_out, sensor_out, walk_register, reprogram_out);
//Guarda el valor del walk register
walk_register mod_wk(clk, rst_out, walk_register, wr_reset, wr_fsm);
FSM_Semaforo mod_fsm(clk, rst_out, sensor_out, wr_fsm, reprogram_out,
expired, wr_reset, interval, start_timer, led_rm, led_ym, leg_gm, led_rs, led_ys, led_gs, led_walk);
//Time parameters
time_parameters mod_time_p(clk,rst_out,reprogram_out,{bit_a_time_sel, bit_b_time_sel},
{bit_a_new_time, bit_b_new_time, bit_c_new_time, bit_d_new_time }, interval, tiempo_espera);
//Timer
timer mod_timer(clk, rst, start_timer, tiempo_espera, expired);
endmodule
|
// part of NeoGS project
//
// (c) NedoPC 2007-2008
//
// modelling is in tb_dma1.*
// look also at dma_access.png
module dma_access(
input clk,
input rst_n,
input dma_req, // DMA request
input [20:0] dma_addr, // DMA address (2mb)
input dma_rnw, // DMA READ/nWRITE
input [7:0] dma_wd, // DMA data to write
output reg [7:0] dma_rd, // DMA data just read
output reg dma_busynready, // DMA BUSY/nREADY
output reg dma_ack, // positive pulse as dma_busynready goes high
output reg dma_end, // positive pulse as dma_busynready goes low
output wire mem_dma_bus, // DMA taking over the bus
output wire [20:0] mem_dma_addr, // DMA address going to the bus
output wire [7:0] mem_dma_wd, // DMA data going to the bus
input [7:0] mem_dma_rd, // DMA data going from the bus
output wire mem_dma_rnw, // DMA bus direction (1=read, 0=write)
output reg mem_dma_oe, // DMA read strobe going to the bus
output reg mem_dma_we, // DMA write pulse going to the bus
output reg busrq_n, // CPU signals
input busak_n // control
);
reg dma_bus;
reg [20:0] int_dma_addr;
reg int_dma_rnw;
reg [7:0] int_dma_wd;
wire [7:0] int_dma_rd;
assign mem_dma_bus = dma_bus;
assign mem_dma_addr = int_dma_addr;
assign mem_dma_wd = int_dma_wd;
assign mem_dma_rnw = int_dma_rnw;
assign int_dma_rd = mem_dma_rd;
localparam IDLE = 0;
localparam START = 1;
localparam WACK = 2;
localparam READ1 = 3;
localparam READ2 = 4;
localparam WRITE1 = 5;
localparam WRITE2 = 6;
reg [3:0] state;
reg [3:0] next_state;
// for simulation purposes
initial
begin
state <= IDLE;
busrq_n <= 1'b1;
mem_dma_oe <= 1'b1;
mem_dma_we <= 1'b1;
end
// FSM
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
state <= IDLE;
else
state <= next_state;
end
always @*
begin
case( state )
//////////////////////////////////////////////////////////////////////////////////////////
IDLE:
begin
if( dma_req==1'b1 )
next_state <= START;
else
next_state <= IDLE;
end
//////////////////////////////////////////////////////////////////////////////////////////
START:
begin
next_state <= WACK;
end
//////////////////////////////////////////////////////////////////////////////////////////
WACK:
begin
if( busak_n == 1'b1 ) ///// ACHTUNG WARNING!!! probably use here registered busak?
next_state <= WACK;
else // busak_n == 1'b0
begin
if( int_dma_rnw == 1'b1 ) // read
next_state <= READ1;
else // int_dma_rnw == 1'b0 - write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
READ1:
begin
next_state <= READ2;
end
//////////////////////////////////////////////////////////////////////////////////////////
READ2:
begin
if( dma_req == 1'b0 )
next_state <= IDLE;
else // dma_req == 1'b1
begin
if( dma_rnw == 1'b1 ) // next is read
next_state <= READ1;
else // dma_rnw == 1'b0 - next is write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE1:
begin
next_state <= WRITE2;
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE2:
begin
if( dma_req == 1'b0 )
next_state <= IDLE;
else // dma_req == 1'b1
begin
if( dma_rnw == 1'b1 ) // next is read
next_state <= READ1;
else // dma_rnw == 1'b0 - next is write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
busrq_n <= 1'b1;
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b0;
dma_bus <= 1'b0;
mem_dma_oe <= 1'b1;
end
else case( next_state )
//////////////////////////////////////////////////////////////////////////////////////////
IDLE:
begin
dma_end <= 1'b0;
busrq_n <= 1'b1;
dma_bus <= 1'b0;
mem_dma_oe <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////
START:
begin
// dma_bus <= 1'b0; // if rst=0>1 and dma_ack=1 --> ??? is this really needed?
busrq_n <= 1'b0;
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
int_dma_rnw <= dma_rnw;
int_dma_addr <= dma_addr;
int_dma_wd <= dma_wd;
end
//////////////////////////////////////////////////////////////////////////////////////////
WACK:
begin
dma_ack <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////
READ1:
begin
dma_bus <= 1'b1; // take over the bus
mem_dma_oe <= 1'b0;
if( dma_busynready == 1'b0 ) // if we are here from READ2 or WRITE2
begin
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
dma_end <= 1'b0;
int_dma_rnw <= 1'b1;
int_dma_addr <= dma_addr;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
READ2:
begin
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b1;
dma_rd <= int_dma_rd;
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE1:
begin
dma_bus <= 1'b1; // take over the bus
mem_dma_oe <= 1'b1;
if( dma_busynready == 1'b0 ) // from READ2 or WRITE2
begin
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
dma_end <= 1'b0;
int_dma_rnw <= 1'b0;
int_dma_addr <= dma_addr;
int_dma_wd <= dma_wd;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE2:
begin
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////
endcase
end
// mem_dma_we generator
always @(negedge clk,negedge rst_n)
begin
if( !rst_n )
mem_dma_we <= 1'b1;
else
begin
if( dma_bus )
begin
if( !int_dma_rnw )
mem_dma_we <= ~mem_dma_we;
end
else
mem_dma_we <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 4; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); ; cin >> s; long long n = s.size(); long long sub = 0; for (int k = 1; k <= 8; k++) { for (int i = 0; i + k <= n; i++) { bool flag = false; for (int j = 1; 2 * j < k; j++) { for (int st = i; st + 2 * j < i + k; st++) { if (s[st] == s[st + j] && s[st] == s[st + 2 * j]) { flag = true; } } } if (!flag) sub++; } } cout << n * (n + 1) / 2 - sub << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hdll__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hdll__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_hdll__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hdll__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hdll__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int h[n]; for (int i = 0; i < n; ++i) { cin >> h[i]; } vector<int> v(n, 0); int maxx = 0; for (int i = n - 1; i >= 0; i--) { v[i] = max(0, maxx - h[i] + 1); maxx = max(maxx, h[i]); } for (int i = 0; i < n; i++) { cout << v[i] << ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_SYMBOL_V
`define SKY130_FD_SC_LP__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_SYMBOL_V
|
#include<iostream> #include <bits/stdc++.h> using namespace std; #define ll long long #define mod 1000000007 #define INF 100000007 #define MAX 1000000 #define nl n #define F first #define S second #define pb(a) push_back(a) typedef vector<ll> vi; typedef priority_queue<ll , vector<ll> , greater<ll>()> pqmx; typedef priority_queue<ll> pqmn; typedef pair<ll , ll> pi; typedef vector< pair<int , int> > vpi; #define fr(i,n) for(i=0;i<n;i++) #define rep(i,a,n) for(i=a;i<n;i++) int n , t , m , temp , temp2, root , p ,q , k , i , j; struct comp { bool operator()( pair<int, int> const& a, pair<int, int> const& b) { return a.first < b.first || (a.first == b.first && a.second > b.second); } }; void func(){ ll A , B , C; cin>>A>>B>>C; if((A + B + C)%9 != 0){ cout<< NO << n ; return; } ll p = (A + B + C) / 9; if(p > A || p > B || p > C){ cout<< NO << n ; return; } cout<< YES << n ; } int main(){ #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif cin>>t; while(t--){ func(); } }
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: altera_dpram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]"
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL "address_b[11..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using std::cerr; using std::cin; using std::cos; using std::cout; using std::endl; using std::make_pair; using std::map; using std::max; using std::min; using std::next_permutation; using std::pair; using std::priority_queue; using std::queue; using std::random_shuffle; using std::set; using std::sin; using std::sort; using std::sqrt; using std::stack; using std::string; using std::stringstream; using std::swap; using std::vector; const long double PI = 3.14159265358979323846; int main() { string s; cin >> s; string s1 = 127 ; if ((s.size() < s1.size()) || ((s.size() == s1.size()) && (s <= s1))) { cout << byte << endl; return 0; } s1 = 32767 ; if ((s.size() < s1.size()) || ((s.size() == s1.size()) && (s <= s1))) { cout << short << endl; return 0; } s1 = 2147483647 ; if ((s.size() < s1.size()) || ((s.size() == s1.size()) && (s <= s1))) { cout << int << endl; return 0; } s1 = 9223372036854775807 ; if ((s.size() < s1.size()) || ((s.size() == s1.size()) && (s <= s1))) { cout << long << endl; return 0; } cout << BigInteger << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; string s; cin >> n >> k >> s; for (int i = 0; i < s.size(); i++) { if (!k) break; if (i + 2 < s.size() && s[i] == 4 && s[i + 1] == 7 && s[i + 2] == 7 && i % 2 == 0) { if (k % 2) s[i + 1] = 4 ; break; } if (i + 2 < s.size() && s[i] == 4 && s[i + 1] == 4 && s[i + 2] == 7 && i % 2 == 0) { if (k % 2) s[i + 1] = 7 ; break; } if (i + 1 < s.size() && s[i] == 4 && s[i + 1] == 7 && i % 2 == 0) { s[i + 1] = 4 ; k--; } if (i + 1 < s.size() && s[i] == 4 && s[i + 1] == 7 && i % 2 != 0) { s[i] = 7 ; k--; } } cout << s; }
|
#include <bits/stdc++.h> using namespace std; string mirror = AHIMOTUVWXY ; string letter = ABCDEFGHIJKLMNOPQRSTUVWXYZ ; int main() { long long n, m, i, j, k, x, y, z, t; cin >> x >> y; if ((x == 0 || x == 1) && y == 0) { cout << 0 << endl; return 0; } if (x == 1 && y == 1) { cout << 1 << endl; return 0; } if (x > 0) { if (y > -(x - 1) && y <= x) y = 0; } else { if (y >= x && y < -x) y = 0; } if (y > 0) { if (x >= -y && x < y) x = 0; } else { if (x > y && x <= abs(y) + 1) x = 0; } if (x == 0) { long long ans = max(0LL, abs(y) - 1) * 4; if (y > 0) ans += 2; else ans += 4; cout << ans << endl; return 0; } if (y == 0) { long long ans = max(0LL, abs(x) - 1) * 4; if (x < 0) ans += 3; else ans++; cout << ans << endl; return 0; } }
|
#include <bits/stdc++.h> using namespace std; int t; int main() { scanf( %d , &t); while (t--) { int a, b; scanf( %d%d , &a, &b); int k = min(max(2 * a, b), max(a, 2 * b)); printf( %d n , k * k); } }
|
#include <bits/stdc++.h> using namespace std; int n; int b[3100]; int a[3100]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &b[i]); int bb = b[i] - b[i - 1], l; if (bb > 0) { youginzi: l = 1; while (bb) { while (a[l] == 9) l++; a[l]++; --bb; } } else if (bb < 0) { while (bb) { if (bb > 0) goto youginzi; l = 0; while (a[++l] == 0) ; do { bb += a[l] - 1; a[l] = 0; ++a[++l]; } while (a[l] >= 10); } } else { l = 0; while (a[++l] == 0) ; do { bb += a[l] - 1; a[l] = 0; ++a[++l]; } while (a[l] >= 10); goto youginzi; } int len = 3005; while (a[len] == 0) --len; for (int j = len; j >= 1; --j) printf( %d , a[j]); puts( ); } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m, count = 0; cin >> n >> m; long long a[m]; for (long long i = 0; i < m; i++) { cin >> a[i]; for (long long j = 0; j < i; j++) { if (a[j] < a[i]) count++; } } cout << count << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e17; const long long MOD = 1000000007; const long long MAX = 4000001; const long double eps = 1E-14; long long max(long long a, long long b) { if (a > b) { return a; } return b; } long long min(long long a, long long b) { if (a > b) { return b; } return a; } long long gcd(long long a, long long b) { if (b == 0) { return a; } if (a < b) { return gcd(b, a); } return gcd(b, a % b); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } struct edge { long long ind; long long fr; long long to; long long d; }; class mint { long long x; public: mint(long long x = 0) : x((x % MOD + MOD) % MOD) {} mint operator-() const { return mint(-x); } mint& operator+=(const mint& a) { if ((x += a.x) >= MOD) x -= MOD; return *this; } mint& operator-=(const mint& a) { if ((x += MOD - a.x) >= MOD) x -= MOD; return *this; } mint& operator*=(const mint& a) { (x *= a.x) %= MOD; return *this; } mint operator+(const mint& a) const { mint res(*this); return res += a; } mint operator-(const mint& a) const { mint res(*this); return res -= a; } mint operator*(const mint& a) const { mint res(*this); return res *= a; } mint pow(long long t) const { if (!t) return 1; mint a = pow(t >> 1); a *= a; if (t & 1) a *= *this; return a; } mint inv() const { return pow(MOD - 2); } mint& operator/=(const mint& a) { return (*this) *= a.inv(); } mint operator/(const mint& a) const { mint res(*this); return res /= a; } friend ostream& operator<<(ostream& os, const mint& m) { os << m.x; return os; } }; mint pw(mint a, long long b) { if (b == 0) { return 1; } mint ret = pw(a, b >> 1); ret *= ret; if (b & 1) { ret *= a; } return ret; } int main() { long long T; cin >> T; for (long long t = 1; t <= T; t++) { long long N; cin >> N; vector<long long> a(N + 1); for (long long i = 1; i <= N; i++) cin >> a[i]; long long S = 0; for (long long i = 1; i <= N; i++) S += a[i]; if (S % N != 0) { cout << -1 << endl; } else { S = S / N; vector<pair<long long, long long>> rem; for (long long i = 2; i <= N; i++) { long long x = 0; if (a[i] % i != 0) { x = i - a[i] % i; } rem.push_back({x, i}); } sort(rem.begin(), rem.end()); vector<pair<pair<long long, long long>, long long>> ans; for (long long k = 0; k < N - 1; k++) { auto p = rem[k]; if (p.first > a[1]) { break; } ans.push_back({{1, p.second}, p.first}); a[1] -= p.first; a[p.second] += p.first; ans.push_back({{p.second, 1}, a[p.second] / p.second}); a[1] += a[p.second]; a[p.second] = 0; } for (long long i = 2; i <= N; i++) { if (a[i] == 0) { continue; } ans.push_back({{i, 1}, a[i] / i}); a[1] += a[i] / i * i; a[i] %= i; } bool b = 1; for (long long i = 2; i <= N; i++) { if (a[i] > S) { cout << -1 << endl; b = 0; break; } ans.push_back({{1, i}, S - a[i]}); } if (b) { cout << ans.size() << endl; for (auto p : ans) { cout << p.first.first << << p.first.second << << p.second << endl; } } } } }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_gmii_tx
*/
module test_axis_gmii_tx;
// Parameters
parameter DATA_WIDTH = 8;
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
parameter PTP_TAG_WIDTH = 16;
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg clk_enable = 1;
reg mii_select = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
wire m_axis_ptp_ts_valid;
wire start_packet;
wire error_underflow;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
ptp_ts,
clk_enable,
mii_select,
ifg_delay
);
$to_myhdl(
s_axis_tready,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
m_axis_ptp_ts,
m_axis_ptp_ts_tag,
m_axis_ptp_ts_valid,
start_packet,
error_underflow
);
// dump file
$dumpfile("test_axis_gmii_tx.lxt");
$dumpvars(0, test_axis_gmii_tx);
end
axis_gmii_tx #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.clk_enable(clk_enable),
.mii_select(mii_select),
.ifg_delay(ifg_delay),
.start_packet(start_packet),
.error_underflow(error_underflow)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 17; int l1[N], r1[N], a[N], use[N]; map<int, bool> mt; void dfs(int v, int l, int r) { if (a[v] > l && a[v] < r) mt[a[v]] = 1; if (l1[v] != -1) dfs(l1[v], l, min(r, a[v])); if (r1[v] != -1) dfs(r1[v], max(l, a[v]), r); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i] >> l1[i] >> r1[i]; if (l1[i] != -1) use[l1[i]] = 1; if (r1[i] != -1) use[r1[i]] = 1; } for (int i = 1; i <= n; i++) if (use[i] == 0) dfs(i, -1, 1e9 + 1); int ans = 0; for (int i = 1; i <= n; i++) if (mt[a[i]] == 0) ans++; cout << ans << endl; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.