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#include <bits/stdc++.h> template <unsigned P> class modint { static_assert(1 <= P); using mint = modint<P>; protected: unsigned v; public: modint() : v() {} template <typename T, typename std::enable_if<std::is_signed<T>::value && std::is_integral<T>::value, bool>::type = true> modint(T _v) { long long tmp = _v % static_cast<long long>(P); if (tmp < 0) { tmp += P; } v = tmp; } template <typename T, typename std::enable_if<std::is_unsigned<T>::value && std::is_integral<T>::value, bool>::type = true> modint(T _v) { v = _v % P; } unsigned val() const { return v; } static constexpr unsigned mod() { return P; } static mint raw(unsigned v) { mint res; res.v = v; return res; } mint &operator+=(const mint &rhs) { v < P - rhs.v ? v += rhs.v : v -= P - rhs.v; return *this; } mint &operator++() { v + 1 < P ? ++v : v = 0; return *this; } mint operator++(int) { mint tmp = *this; v + 1 < P ? ++v : v = 0; return tmp; } mint &operator-=(const mint &rhs) { v < rhs.v ? v += P - rhs.v : v -= rhs.v; return *this; } mint &operator--() { v == 0 ? v = P - 1 : --v; return *this; } mint operator--(int) { mint tmp = *this; v == 0 ? v = P - 1 : --v; return tmp; } mint operator-() const { mint res; res.v = v == 0 ? 0 : P - v; return res; } mint &operator*=(const mint &rhs) { v = static_cast<unsigned long long>(v) * rhs.v % P; return *this; } mint pow(unsigned long long b) const { mint a(*this), s(1); for (; b; b >>= 1) { if (b & 1) { s *= a; } a *= a; } return s; } mint inv() const { return pow(P - 2); } friend mint operator+(const mint &lhs, const mint &rhs) { return mint(lhs) += rhs; } friend mint operator-(const mint &lhs, const mint &rhs) { return mint(lhs) -= rhs; } friend mint operator*(const mint &lhs, const mint &rhs) { return mint(lhs) *= rhs; } friend bool operator==(const mint &lhs, const mint &rhs) { return lhs.v == rhs.v; } friend bool operator!=(const mint &lhs, const mint &rhs) { return lhs.v != rhs.v; } friend std::istream &operator>>(std::istream &in, mint &x) { return in >> x.v; } friend std::ostream &operator<<(std::ostream &out, const mint &x) { return out << x.v; } }; using mint = modint<998244353>; const mint mi2 = mint(2), minv2 = mi2.inv(); void solve() { int n, k, x; std::cin >> n >> k >> x; if (x == 0) { if (n > k) { std::cout << 0 << n ; return; } mint pw = mi2.pow(k), now = 1; mint ans = 1; for (int i = 0; i < n; ++i) { ans *= pw - now; now += now; } std::cout << ans << n ; return; } mint pw = mi2.pow(k), pwn = pw.pow(n), inv = minv2.pow(n); mint now = 1; mint ans = 0; for (int i = 1; i <= k; ++i) { pw *= minv2; pwn *= inv; ans += pwn * now * pw; now *= 1 - pw; } std::cout << ans << n ; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int T; std::cin >> T; while (T--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; template <typename T> bool in(T a, T b, T c) { return a <= b && b < c; } unsigned int logceil(int first) { return first ? 8 * sizeof(int) - __builtin_clz(first) : 0; } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.first) ^ (u(p.second) << 7); } }; } // namespace std template <typename T, typename F> T bsh(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { l = m + 1; r = m; } else { h = m - 1; } } return r; } template <typename F> double bshd(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { l = m; } else { h = m; } } return (l + h) / 2; } template <typename T, typename F> T bsl(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { h = m - 1; r = m; } else { l = m + 1; } } return r; } template <typename F> double bsld(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { h = m; } else { l = m; } } return (l + h) / 2; } template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; class TaskD { public: void solve(istream& cin, ostream& cout) { long long N, L, R, K; cin >> N >> L >> R >> K; long long Q = (N + R - L + 1) % N; if (Q == 0) Q = N; if (K < Q) { cout << -1 n ; return; } long long ans = -1; if (K <= 2 * Q) { cout << min(N, K - Q + 1 + (N - Q)) << endl; return; } for (long long rev = 1; rev <= 1000000; ++rev) { for (long long take : { (K - Q + N) / (rev + 1), (K - Q + N) / (rev + 1), (K - Q + N) / (rev + 1), (2 * N + K - 2 * Q + 1) / (rev + 1), (2 * N + K - 2 * Q + 1) / (rev + 1), (2 * N + K - 2 * Q + 1) / (rev + 1), }) { long long s = take - N; if (s < 0) continue; if (s > N) continue; long long left = (K - Q) - rev * take; if (left < 0) continue; if (left > Q) continue; if (left > s) continue; if (min(Q, left + 1) + (N - Q) < s) continue; ans = max(ans, s); } } for (long long take = 1; take <= 1000000; ++take) { if (take < N) continue; if (take > 2 * N) continue; long long s = take - N; for (long long rev = (K - 2 * Q) / take - 1; rev <= (K - Q) / take + 1; ++rev) { if (rev <= 0) continue; long long left = (K - Q) - rev * take; if (left < 0) continue; if (left > Q) continue; if (left > s) continue; if (min(Q, left + 1) + (N - Q) < s) continue; ans = max(ans, s); } } cout << ans << endl; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); TaskD solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFSBP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const int MOD = 998244353; struct node { long long a, b; node() {} node(long long a, long long b) { this->a = a; this->b = b; } node operator+(const node& rhs) const { return node((a + rhs.a) % MOD, (b + rhs.b) % MOD); } node operator*(const node& rhs) const { return node(a * rhs.a % MOD, b * rhs.b % MOD); } bool operator==(const node& rhs) const { return a == rhs.a && b == rhs.b; } }; node BASE(2333, 233333); node h[maxn]; node ALL(0, 0); node s[maxn][15]; vector<pair<int, int> > vec[maxn]; int n, m, k, ans; void dfs(int u, node hh) { if (u > k) { ans += (hh == ALL ? 1 : 0); return; } for (int i = 0; i < u; i++) { node v = hh + s[u][i]; dfs(u + 1, v); } return; } int main() { scanf( %d%d%d , &n, &m, &k); h[0] = node(1, 1); for (int i = 1; i <= n; i++) { h[i] = h[i - 1] * BASE; ALL = ALL + h[i]; } for (int i = 1; i <= m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); vec[u].emplace_back(make_pair(v, w)); } for (int i = 1; i <= n; i++) { sort(vec[i].begin(), vec[i].end(), [](pair<int, int> a, pair<int, int> b) { return a.second < b.second; }); int lens = vec[i].size(); for (int j = 0; j < lens; j++) s[lens][j] = s[lens][j] + h[vec[i][j].first]; } dfs(1, node(0, 0)); printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int Array[10005]; int main() { int N, m, i, j, l, r, x, Count; scanf( %d%d , &N, &m); for (i = 1; i <= N; i++) scanf( %d , Array + i); for (i = 1; i <= m; i++) { Count = 0; scanf( %d%d%d , &l, &r, &x); for (j = l; j <= r; j++) { if (Array[j] < Array[x]) Count++; } if (Count == x - l) puts( Yes ); else puts( No ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const double PI = 4 * atan(1); template <int p> struct FF { long long val; FF(long long x = 0) { val = (x % p + p) % p; } bool operator==(const FF<p> other) { return val == other.val; } bool operator!=(const FF<p> other) { return val != other.val; } FF operator+() const { return val; } FF operator-() const { return -val; } FF& operator+=(const FF<p> other) { val = (val + other.val) % p; return *this; } FF& operator-=(const FF<p> other) { *this += -other; return *this; } FF& operator*=(const FF<p> other) { val = (val * other.val) % p; return *this; } FF& operator/=(const FF<p> other) { *this *= other.inv(); return *this; } FF operator+(const FF<p> other) const { return FF(*this) += other; } FF operator-(const FF<p> other) const { return FF(*this) -= other; } FF operator*(const FF<p> other) const { return FF(*this) *= other; } FF operator/(const FF<p> other) const { return FF(*this) /= other; } static FF<p> pow(const FF<p> a, long long b) { if (!b) return 1; return pow(a * a, b >> 1) * (b & 1 ? a : 1); } FF<p> pow(long long b) const { return pow(*this, b); } FF<p> inv() const { return pow(p - 2); } }; template <int p> FF<p> operator+(long long lhs, const FF<p> rhs) { return FF<p>(lhs) += rhs; } template <int p> FF<p> operator-(long long lhs, const FF<p> rhs) { return FF<p>(lhs) -= rhs; } template <int p> FF<p> operator*(long long lhs, const FF<p> rhs) { return FF<p>(lhs) *= rhs; } template <int p> FF<p> operator/(long long lhs, const FF<p> rhs) { return FF<p>(lhs) /= rhs; } int N; vector<int> adj[500013]; FF<998244353> dp[500013]; FF<998244353> ans; void dfs(int n, int par = -1) { dp[n] = 1; for (int v : adj[n]) if (v != par) { dfs(v, n); dp[n] *= 1 - dp[v] / 2; } ans += 1 - dp[n]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> N; for (int i = 0; i < N - 1; i++) { int u, v; cin >> u >> v; --u; --v; adj[u].push_back(v); adj[v].push_back(u); } dfs(0); for (int i = 0; i < N; i++) ans = ans * 2; cout << ans.val << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; float a = 1; float b = (float)360 / ((2 * n)); b /= 2; b = (3.14159265358979323846264338327950288419716939937510582 / 180) * b; float ans = 1 / tan(b); cout << fixed << setprecision(15) << ans << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; vector<int> prices[1010]; int allp[1010]; int all; int margin_price; int above_cnt[1010], margin_cnt[1010], cnt[1010]; double f[1010][1010], g[1010][1010]; double comb[1010][1010]; int main() { comb[1][0] = comb[1][1] = 1; for (int i = 2; i <= 1000; i++) { comb[i][0] = comb[i][i] = 1; for (int j = 1; j < i; j++) comb[i][j] = comb[i - 1][j] + comb[i - 1][j - 1]; } scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int k; scanf( %d , &k); while (k--) { int v; scanf( %d , &v); prices[i].push_back(v); allp[++all] = v; } } sort(allp + 1, allp + all + 1); reverse(allp + 1, allp + all + 1); margin_price = allp[n]; int need_margin = 0; for (int i = 1; i <= n; i++) if (allp[i] == margin_price) need_margin++; for (int i = 1; i <= m; i++) { for (int p : prices[i]) { if (p > margin_price) above_cnt[i]++; else if (p == margin_price) margin_cnt[i]++; cnt[i]++; } } f[0][0] = 1; g[0][0] = 1; for (int i = 1; i <= m; i++) { for (int j = 0; j <= need_margin; j++) { if (margin_cnt[i] == 0) { f[i][j] += f[i - 1][j] / comb[cnt[i]][above_cnt[i]]; g[i][j] += g[i - 1][j]; } else if (margin_cnt[i] == 1) { f[i][j] += f[i - 1][j] / comb[cnt[i]][above_cnt[i]]; g[i][j] += g[i - 1][j]; f[i][j + 1] += f[i - 1][j] / comb[cnt[i]][above_cnt[i] + 1]; g[i][j + 1] += g[i - 1][j]; } else { assert(false); } } } printf( %.15f n , f[m][need_margin] / g[m][need_margin]); return 0; }
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// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
`timescale 1ns/10ps
module logshiftright(distance,
data,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input wire [lpm_width-1 :0] data;
output wire [lpm_width-1 :0] result;
assign result = data >> distance;
endmodule
|
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming (
clk,
reset_n,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest,
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
input clk;
input reset_n;
output [7:0] source_data;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
output debug_reset;
output mgmt_valid;
output mgmt_data;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
parameter TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
parameter SYSCLK_TO_TCK_SYNC_DEPTH = 3;
output [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
// Signals in the JTAG clock domain
wire jtag_clock;
wire jtag_clock_reset_n; // system reset is synchronized with jtag_clock
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(jtag_clock),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_streaming (
.tck(jtag_clock),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(jtag_clock),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(jtag_clock),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int MAXX = 2e6 + 10; long long f(long long n) { long long ret = n; for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { while (n % i == 0) n /= i; ret -= ret / i; } } if (n > 1) ret -= ret / n; return ret; } long long g(long long n) { return n; } long long F(long long n, long long k) { if (k == 1) return f(g(n)); if (n == 1) return 1ll; if (k & 1) return F(f(n), k - 1); else return F(g(n), k - 1); } int main() { long long n, k; scanf( %lld %lld , &n, &k); long long ans = F(n, k); printf( %lld , ans % mod); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &t) { t = 0; char ch = getchar(); int f = 1; while ( 0 > ch || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } do { (t *= 10) += ch - 0 ; ch = getchar(); } while ( 0 <= ch && ch <= 9 ); t *= f; } const long long INF = 1e16; const int maxn = (2e5) + 10; int n, m, k, s[maxn], t[maxn], d[maxn], w[maxn], t1, t2; long long dp[maxn / 2][210], ans; struct cmp { bool operator()(pair<pair<int, int>, int> a, pair<pair<int, int>, int> b) { if (a > b) return 0; return 1; } }; priority_queue<pair<pair<int, int>, int>, vector<pair<pair<int, int>, int> >, cmp> q; struct node { int pos, P; } a[maxn], b[maxn]; int vis[maxn], u[maxn]; bool cmp2(node x, node y) { return x.pos < y.pos; } int main() { read(n); read(m); read(k); for (int i = 1; i <= k; i++) { read(s[i]), read(t[i]), read(d[i]), read(w[i]); a[++t1] = (node){s[i], i}; b[++t2] = (node){t[i], i}; } sort(a + 1, a + t1 + 1, cmp2); sort(b + 1, b + t2 + 1, cmp2); int I1 = 1, I2 = 1; for (int i = 1; i <= n; i++) { while (I1 <= t1 && a[I1].pos == i) { q.push(make_pair(make_pair(w[a[I1].P], d[a[I1].P]), a[I1].P)); I1++; } u[i] = -1; while (!q.empty()) { pair<pair<int, int>, int> A = q.top(); u[i] = A.second; if (!vis[u[i]]) break; else q.pop(), u[i] = -1; } while (I2 <= t2 && b[I2].pos == i) { vis[b[I2].P] = 1; I2++; } } ans = INF; for (int i = n; i >= 1; i--) { for (int j = 0; j <= m; j++) { if (u[i] != -1) dp[i][j] = dp[d[u[i]] + 1][j] + w[u[i]]; else dp[i][j] = dp[i + 1][j]; if (j) dp[i][j] = min(dp[i + 1][j - 1], dp[i][j]); if (i == 1) ans = min(ans, dp[i][j]); } } printf( %lld n , ans); return 0; }
|
`timescale 1ns / 100ps
module QMFIR_uart_top(/*AUTOARG*/
// Outputs
uart_tx,
// Inputs
uart_rx, clk, arst_n
);
output uart_tx;
input uart_rx;
input clk;
input arst_n;
wire arst_n;
wire [15:0] MEMDAT;
wire core_clk;
wire uart_rst_n;
reg init_rst_n;
reg delay;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire reg_we; // From uart_ of QMFIR_uart_if.v
wire [13:0] uart_addr; // From uart_ of QMFIR_uart_if.v
wire [31:0] uart_dout; // From uart_ of QMFIR_uart_if.v
wire uart_mem_re; // From uart_ of QMFIR_uart_if.v
wire uart_mem_we; // From uart_ of QMFIR_uart_if.v
// End of automatics
wire [23:0] uart_mem_i;
reg [23:0] uart_reg_i; //combinatory
//iReg
wire [15:0] ESCR;
wire [15:0] WPTR;
wire [15:0] ICNT;
wire [15:0] FREQ;
wire [15:0] OCNT;
wire [15:0] FCNT;
wire [31:0] firin;
//bram out
wire [15:0] MEMDATR1;
wire [15:0] MEMDATI1;
wire [15:0] MEMDATR2;
wire [15:0] MEMDATI2;
wire [15:0] MEMDATR3;
wire [15:0] MEMDATI3;
wire [15:0] RealOut1;
wire [15:0] RealOut2;
wire [15:0] RealOut3;
wire [15:0] ImagOut1;
wire [15:0] ImagOut2;
wire [15:0] ImagOut3;
//bram in
wire [9:0] mem_addr1;
wire [9:0] mem_addr2;
wire [9:0] mem_addr3;
wire [11:0] bramin_addr;
// qmfir
reg START;
wire DataValid;
// CORE
assign arst = ~arst_n;
assign arst1 = ESCR[0];
assign uart_rst_n = arst_n & init_rst_n;
QMFIR_uart_if uart_(/*AUTOINST*/
// Outputs
.uart_dout (uart_dout[31:0]),
.uart_addr (uart_addr[13:0]),
.uart_mem_we (uart_mem_we),
.uart_mem_re (uart_mem_re),
.reg_we (reg_we),
.uart_tx (uart_tx),
// Inputs
.uart_mem_i (uart_mem_i[23:0]),
.uart_reg_i (uart_reg_i[23:0]),
.clk (core_clk),
.arst_n (uart_rst_n),
.uart_rx (uart_rx));
iReg ireg_ (//outputs
.ESCR(ESCR),
.WPTR(WPTR),
.ICNT(ICNT),
.FREQ(FREQ),
.OCNT(OCNT),
.FCNT(FCNT),
//inputs
.clk(core_clk),
.arst(arst),
.idata(uart_dout[15:0]),
.iaddr(uart_addr),
.iwe(reg_we),
.FIR_WE(DataValid),
.WFIFO_WE(uart_mem_we)
);
BRAM_larg bramin_(//outputs
.doutb(firin), //32 bit
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(bramin_addr[11:0]), //12 bit
.addrb(FCNT[11:0]), //12 bit
.dina(uart_dout), //32 bit
.wea(uart_mem_we));
QM_FIR QM_FIR(//outputs
.RealOut1 (RealOut1),
.RealOut2 (RealOut2),
.RealOut3 (RealOut3),
.ImagOut1 (ImagOut1),
.ImagOut2 (ImagOut2),
.ImagOut3 (ImagOut3),
.DataValid (DataValid),
//inputs
.CLK (core_clk),
.ARST (arst1),
.InputValid (START),
.dsp_in0 (firin[31:24]),
.dsp_in1 (firin[23:16]),
.dsp_in2 (firin[15:8]),
.dsp_in3 (firin[7:0]),
.newFreq (FREQ[14]),
.freq (FREQ[6:0]));
BRAM BRAM1_ (//outputs
.doutb({MEMDATI1[15:0],MEMDATR1[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr1[6:0]),
.dina({ImagOut1[15:0],RealOut1[15:0]}),
.wea(DataValid));
BRAM BRAM2_ (//outputs
.doutb({MEMDATI2[15:0],MEMDATR2[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr2[6:0]),
.dina({ImagOut2[15:0],RealOut2[15:0]}),
.wea(DataValid));
BRAM BRAM3_ (//outputs
.doutb({MEMDATI3[15:0],MEMDATR3[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr3[6:0]),
.dina({ImagOut3[15:0],RealOut3[15:0]}),
.wea(DataValid));
always @ (posedge core_clk or posedge arst)
if (arst != 1'b0)
START = 1'b0;
else begin
if (ESCR[3]) begin
init_rst_n <= 0; //assert initial UART reset
START = ESCR[3]; //start the filter
end
else begin
init_rst_n <= 1;
START = 1'b0;
end
end
// BRAMin interface
assign bramin_addr[11:0] = {(12){uart_mem_we}} & uart_addr[11:0];
//iReg interface
always @ (/*AS*/ESCR or FCNT or FREQ or ICNT or OCNT or WPTR or uart_addr)
case (uart_addr[2:0])
3'h1: uart_reg_i = {uart_addr[7:0], ESCR[15:0]};
3'h2: uart_reg_i = {uart_addr[7:0], WPTR[15:0]};
3'h3: uart_reg_i = {uart_addr[7:0], ICNT[15:0]};
3'h4: uart_reg_i = {uart_addr[7:0], FREQ[15:0]};
3'h5: uart_reg_i = {uart_addr[7:0], OCNT[15:0]};
3'h6: uart_reg_i = {uart_addr[7:0], FCNT[15:0]};
//default: uart_reg_i = {uart_addr[7:0],16'hDEAD};
endcase // case (uart_addr[2:0])
// BRAM out interface
//read address
assign mem_addr1[6:0] = ((uart_addr[13:11] == 3'h1) | (uart_addr[13:11] == 3'h2)) ? uart_addr[6:0] : 7'b111_1111;
assign mem_addr2[6:0] = ((uart_addr[13:11] == 3'h3) | (uart_addr[13:11] == 3'h4)) ? uart_addr[6:0] : 7'b111_1111;
assign mem_addr3[6:0] = ((uart_addr[13:11] == 3'h5) | (uart_addr[13:11] == 3'h6)) ? uart_addr[6:0] : 7'b111_1111;
//read data
assign MEMDAT[15:0] = (MEMDATR1[15:0] & {16{uart_addr[13:11] == 3'h1}}) |
(MEMDATI1[15:0] & {16{uart_addr[13:11] == 3'h2}}) |
(MEMDATR2[15:0] & {16{uart_addr[13:11] == 3'h3}}) |
(MEMDATI2[15:0] & {16{uart_addr[13:11] == 3'h4}}) |
(MEMDATR3[15:0] & {16{uart_addr[13:11] == 3'h5}}) |
(MEMDATI3[15:0] & {16{uart_addr[13:11] == 3'h6}});
assign uart_mem_i[23:0] = {1'b0,uart_addr[13:11],uart_addr[3:0], MEMDAT[15:0]};
// DCM_BASE: Base Digital Clock Manager Circuit, Virtex-5
//this DCM is used to divide the clock from 100MHz to 62.5MHz (for UART)
DCM_BASE #(
.CLKFX_DIVIDE(8), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(5), // Can be any integer from 2 to 32
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLK_FEEDBACK("NONE") // Specify clock feedback of NONE or 1X
) DCM_BASE_inst (
.CLKFX(core_clk), // DCM CLK synthesis out (M/D)
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.RST(arst) // DCM asynchronous reset input
);
// End of DCM_BASE_inst instantiation
endmodule // QMFIR_uart_top
|
module top;
reg pass;
reg [7:0] a, b;
wire [15:0] ruu, rsu, rus, rss;
reg signed [15:0] res;
integer i;
assign ruu = a / b;
assign rsu = $signed(a) / b;
assign rus = a / $signed(b);
assign rss = $signed(a) / $signed(b);
initial begin
pass = 1'b1;
// Run 1000 random vectors
for (i = 0; i < 1000; i = i + 1) begin
// Random vectors
a = $random;
b = $random;
#1;
// Check unsigned / unsigned.
if (ruu !== a/b) begin
$display("FAILED: u/u (%b/%b) gave %b, expected %b", a, b, ruu, a/b);
pass = 1'b0;
end
// Check signed / unsigned.
if (rsu !== a/b) begin
$display("FAILED: s/u (%b/%b) gave %b, expected %b", a, b, rsu, a/b);
pass = 1'b0;
end
// Check unsigned / signed.
if (rus !== a/b) begin
$display("FAILED: u/s (%b/%b) gave %b, expected %b", a, b, rus, a/b);
pass = 1'b0;
end
// Check signed / signed.
res = $signed(a)/$signed(b);
if (rss !== res) begin
$display("FAILED: s/s (%b/%b) gave %b, expected %b", a, b, rss, res);
pass = 1'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; long long int n = ((int)s[1] - 0 ) + 10 * ((int)s[3] - 0 ) + 100 * ((int)s[4] - 0 ) + 1000 * ((int)s[2] - 0 ) + 10000 * ((int)s[0] - 0 ); long long int result = (n * n) % 100000; result = (result * result) % 100000; result = (result * n) % 100000; int digits = (int)log10(result + 1); digits = 4 - digits; for (int i = 0; i < digits; i++) cout << 0 ; cout << result; return 0; }
|
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard ()
// 2013 Aaron Dahlen
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
//** INSTANTIATION ********************************************
//
// To instantiate this module copy this section to your main code...
//
// uart #(
// .baud_rate(baud_rate), // default is 9600
// .sys_clk_freq(sys_clk_freq) // default is 100000000
// )
// instance_name(
// .clk(clk), // The master clock for this module
// .rst(rst), // Synchronous reset
// .rx(rx), // Incoming serial line
// .tx(tx), // Outgoing serial line
// .transmit(transmit), // Signal to transmit
// .tx_byte(tx_byte), // Byte to transmit
// .received(received), // Indicated that a byte has been received
// .rx_byte(rx_byte), // Byte received
// .is_receiving(is_receiving), // Low when receive line is idle
// .is_transmitting(is_transmitting),// Low when transmit line is idle
// .recv_error(recv_error) // Indicates error in receiving packet.
// //.recv_state(recv_state), // for test bench
// //.tx_state(tx_state) // for test bench
// );
//
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Assert to begin transmission
input [7:0] tx_byte, // Byte to transmit
output received, // Indicates that a byte has been received
output [7:0] rx_byte, // Byte received
output wire is_receiving, // Low when receive line is idle.
output wire is_transmitting,// Low when transmit line is idle.
output wire recv_error, // Indicates error in receiving packet.
output reg [3:0] rx_samples,
output reg [3:0] rx_sample_countdown
);
// The clock_divider is calculated using baud_rate and sys_clk_freq.
// To modify baud rate you can modify the defaults shown below or instantiate
// the module using the template shown in the INSTANTIATION section above.
// For aditional information about instantiation please see:
// http://www.sunburst-design.com/papers/CummingsHDLCON2002_Parameters_rev1_2.pdf
parameter baud_rate = 9600;
parameter sys_clk_freq = 12000000;
localparam one_baud_cnt = sys_clk_freq / (baud_rate);
//** SYMBOLIC STATE DECLARATIONS ******************************
localparam [2:0]
RX_IDLE = 3'd0,
RX_CHECK_START = 3'd1,
RX_SAMPLE_BITS = 3'd2,
RX_READ_BITS = 3'd3,
RX_CHECK_STOP = 3'd4,
RX_DELAY_RESTART = 3'd5,
RX_ERROR = 3'd6,
RX_RECEIVED = 3'd7;
localparam [1:0]
TX_IDLE = 2'd0,
TX_SENDING = 2'd1,
TX_DELAY_RESTART = 2'd2,
TX_RECOVER = 2'd3;
//** SIGNAL DECLARATIONS **************************************
reg [log2(one_baud_cnt * 16)-1:0] rx_clk;
reg [log2(one_baud_cnt)-1:0] tx_clk;
reg [2:0] recv_state = RX_IDLE;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
//** ASSIGN STATEMENTS ****************************************
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
//** TASKS / FUNCTIONS ****************************************
function integer log2(input integer M);
integer i;
begin
log2 = 1;
for (i = 0; 2**i <= M; i = i + 1)
log2 = i + 1;
end endfunction
//** Body *****************************************************
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// Countdown timers for the receiving and transmitting
// state machines are decremented.
if(rx_clk) begin
rx_clk = rx_clk - 1'd1;
end
if(tx_clk) begin
tx_clk = tx_clk - 1'd1;
end
//** Receive state machine ************************************
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait 1/2 of the bit period
rx_clk = one_baud_cnt / 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_clk) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period plus 3/8 of the next
rx_clk = (one_baud_cnt / 2) + (one_baud_cnt * 3) / 8;
rx_bits_remaining = 8;
recv_state = RX_SAMPLE_BITS;
rx_samples = 0;
rx_sample_countdown = 5;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_SAMPLE_BITS: begin
// sample the rx line multiple times
if (!rx_clk) begin
if (rx) begin
rx_samples = rx_samples + 1'd1;
end
rx_clk = one_baud_cnt / 8;
rx_sample_countdown = rx_sample_countdown -1'd1;
recv_state = rx_sample_countdown ? RX_SAMPLE_BITS : RX_READ_BITS;
end
end
RX_READ_BITS: begin
if (!rx_clk) begin
// Should be finished sampling the pulse here.
// Update and prep for next
if (rx_samples > 3) begin
rx_data = {1'd1, rx_data[7:1]};
end else begin
rx_data = {1'd0, rx_data[7:1]};
end
rx_clk = (one_baud_cnt * 3) / 8;
rx_samples = 0;
rx_sample_countdown = 5;
rx_bits_remaining = rx_bits_remaining - 1'd1;
if(rx_bits_remaining)begin
recv_state = RX_SAMPLE_BITS;
end else begin
recv_state = RX_CHECK_STOP;
rx_clk = one_baud_cnt / 2;
end
end
end
RX_CHECK_STOP: begin
if (!rx_clk) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_clk = 8 * sys_clk_freq / (baud_rate);
recv_state = RX_DELAY_RESTART;
end
// why is this state needed? Why not go to idle and wait for next?
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_clk ? RX_DELAY_RESTART : RX_IDLE;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
//** Transmit state machine ***********************************
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
// tx_clk_divider = clock_divide;
tx_clk = one_baud_cnt;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_clk) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1'd1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_clk = one_baud_cnt;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_clk = 16 * one_baud_cnt;// tx_countdown = 16;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_clk ? TX_DELAY_RESTART : TX_RECOVER;// TX_IDLE;
end
TX_RECOVER: begin
// Wait unitil the transmit line is deactivated. This prevents repeated characters
tx_state = transmit ? TX_RECOVER : TX_IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long read() { long long cc = getc(stdin); for (; cc < 0 || cc > 9 ;) cc = getc(stdin); long long ret = 0; for (; cc >= 0 && cc <= 9 ;) { ret = ret * 10 + cc - 0 ; cc = getc(stdin); } return ret; } long long power(long long num, long long g) { if (g == 0) return 1; if (g % 2 == 1) return (num * power((num * num) % 998244353, g / 2)) % 998244353; return power((num * num) % 998244353, g / 2); } int parent[100005]; int siz[100005]; int find(int index) { if (parent[index] == index) return index; return parent[index] = find(parent[index]); } vector<pair<int, int> > vec[100005]; int b[100005][18], c[100005][18]; int timer, intime[100005], outtime[100005], level[100005]; void dfs(int index, int par, int lev) { level[index] = lev; timer++; intime[index] = timer; parent[index] = par; for (long long i = 0; i < vec[index].size(); i++) { if (vec[index][i].first == par) continue; c[vec[index][i].first][0] = vec[index][i].second; dfs(vec[index][i].first, index, lev + 1); } timer++; outtime[index] = timer; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; pair<pair<int, int>, pair<int, int> > pa[m]; vector<pair<int, int> > vec1; for (long long i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; pa[i] = make_pair(make_pair(w, i), make_pair(u, v)); } sort(pa, pa + m); for (long long i = 0; i < n; i++) parent[i + 1] = i + 1, siz[i + 1] = 1; for (long long i = 0; i < m; i++) { int u = pa[i].second.first; int v = pa[i].second.second; int w = pa[i].first.first; int g = find(u); int h = find(v); if (g == h) continue; if (siz[g] > siz[h]) siz[g] += siz[h], parent[h] = g; else siz[h] += siz[g], parent[g] = h; vec[u].push_back(make_pair(v, w)); vec[v].push_back(make_pair(u, w)); } timer = 0; dfs(1, 1, 1); for (long long i = 0; i < n; i++) { b[i + 1][0] = parent[i + 1]; } for (int i = 1; i <= 17; i++) { for (int j = 1; j <= n; j++) { b[j][i] = b[b[j][i - 1]][i - 1]; c[j][i] = max(c[j][i - 1], c[b[j][i - 1]][i - 1]); } } for (long long i = 0; i < n; i++) parent[i + 1] = i + 1, siz[i + 1] = 1; for (long long i = 0; i < m; i++) { int u = pa[i].second.first; int v = pa[i].second.second; int w = pa[i].first.first; int xyz = pa[i].first.second; int g = find(u); int h = find(v); if (g == h) { int g = 1 << 17; int ans = 0; int h = u; for (int j = 17; j >= 0; j--) { int d = b[h][j]; if (intime[d] <= intime[v] && outtime[d] >= outtime[v]) { continue; } ans = max(ans, c[h][j]); h = d; } while (intime[h] > intime[v] || outtime[h] < outtime[v]) { ans = max(ans, c[h][0]); h = b[h][0]; } h = v; for (int j = 17; j >= 0; j--) { int d = b[h][j]; if (intime[d] <= intime[u] && outtime[d] >= outtime[u]) { continue; } ans = max(ans, c[h][j]); h = d; } while (intime[h] > intime[u] || outtime[h] < outtime[u]) { ans = max(ans, c[h][0]); h = b[h][0]; } vec1.push_back(make_pair(xyz, ans)); continue; } if (siz[g] > siz[h]) siz[g] += siz[h], parent[h] = g; else siz[h] += siz[g], parent[g] = h; vec[u].push_back(make_pair(v, w)); vec[v].push_back(make_pair(u, w)); } sort(vec1.begin(), vec1.end()); for (long long i = 0; i < vec1.size(); i++) cout << vec1[i].second << endl; return 0; }
|
/* Generated by Yosys 0.8 (git sha1 UNKNOWN, clang 10.0.0 -fPIC -Os) */
(* top = 1 *)
(* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/gc.v:4" *)
module Start_Sensor_Actuator_G1__prevStart_G1__prevSensor_net(Start, Sensor, Actuator, G1__prevStart, G1__prevSensor);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
(* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/gc.v:8" *)
output Actuator;
(* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/gc.v:10" *)
output G1__prevSensor;
(* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/gc.v:9" *)
output G1__prevStart;
(* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/gc.v:7" *)
input Sensor;
(* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/gc.v:6" *)
input Start;
assign _09_ = ~Start;
assign _10_ = ~Sensor;
assign _00_ = ~Actuator;
assign _01_ = ~(Sensor | Actuator);
assign _02_ = ~(_10_ | _00_);
assign _03_ = ~(Start | Actuator);
assign _04_ = ~(_09_ | _00_);
assign _05_ = ~(G1__prevSensor | _03_);
assign _06_ = ~(_04_ | _05_);
assign G1__prevStart = ~_06_;
assign _07_ = ~(_02_ | _06_);
assign G1__prevSensor = ~(_01_ | _07_);
assign _08_ = ~(Sensor | _04_);
assign Actuator = ~(_03_ | _08_);
endmodule
|
#include <bits/stdc++.h> const long long maxn = 1e3 + 5; const long long w = 1e8; using namespace std; int m, n, p, kq; char a[maxn][maxn]; string s; char dir[4] = { D , L , U , R }; int tdx, tdy; int x, y; inline void init() { cin >> n >> m; cin.ignore(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> a[i][j]; if (a[i][j] == S ) { x = j; y = i; } } cin >> s; p = s.length(); } inline void solve() { sort(dir, dir + 4); do { tdx = x; tdy = y; for (int i = 0; i < p; i++) { if (dir[s[i] - 48] == D ) tdy++; if (dir[s[i] - 48] == U ) tdy--; if (dir[s[i] - 48] == L ) tdx--; if (dir[s[i] - 48] == R ) tdx++; if (a[tdy][tdx] == # || tdx < 1 || tdy < 1 || tdx > m || tdy > n) break; if (a[tdy][tdx] == E ) { kq++; break; } } } while (next_permutation(dir, dir + 4)); cout << kq; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); init(); solve(); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll inf = 1e18; int n, m; int edges[22][2]; bool used[6][6]; int arr[7]; void init() {} void input() { cin >> n >> m; for (int i = 0; i < m; i++) { cin >> edges[i][0] >> edges[i][1]; edges[i][0]--; edges[i][1]--; } } int check() { int now = 0; for (int i = 1; i <= 6; i++) { for (int j = 1; j <= 6; j++) { used[i][j] = false; } } for (int i = 0; i < m; i++) { int v = edges[i][0], u = edges[i][1]; if (!used[arr[v]][arr[u]]) { now++; used[arr[v]][arr[u]] = true; used[arr[u]][arr[v]] = true; } } return now; } void solve() { int ans = 0; for (arr[0] = 1; arr[0] < 7; arr[0]++) { for (arr[1] = 1; arr[1] < 7; arr[1]++) { for (arr[2] = 1; arr[2] < 7; arr[2]++) { for (arr[3] = 1; arr[3] < 7; arr[3]++) { for (arr[4] = 1; arr[4] < 7; arr[4]++) { for (arr[5] = 1; arr[5] < 7; arr[5]++) { for (arr[6] = 1; arr[6] < 7; arr[6]++) { ans = max(ans, check()); } } } } } } } cout << ans << endl; } void output() {} int main() { ios::sync_with_stdio(false); cin.tie(0); int number_of_testcases = 1; while (number_of_testcases--) { init(); input(); solve(); output(); } return 0; }
|
module Controller(input clk,rst,output reg RdOrR2,AluOrMem,RFWE,MWE,output reg[1:0] stackContrl,pcContrl,input Zero,Cout,input[5:0] cntlInstruc);
/*always@(posedge clk,posedge rst)
if(rst)
begin
RdOrR2=1'b0;
AluOrMem=1'b0;
RFWE=1'b0;
MWE=1'b0;
stackContrl=2'b00;
pcContrl=2'b00;
end
else
begin
RdOrR2=iRdOrR2;
AluOrMem=iAluOrMem;
RFWE=iRFWE;
MWE=iMWE;
stackContrl=istackContrl;
pcContrl=ipcContrl;
end*/
//reg iRdOrR2,iAluOrMem,iRFWE,iMWE;
//reg[1:0] istackContrl,ipcContrl;
/*integer contBugger;
initial begin
contBugger = $fopen("controller.log") | 1;
forever #(2) $fdisplay(contBugger, "%6b,%6b,%6b,%6b,%6b,%6b,%6b,%6b,%6b,%6b,%6b",
clk,rst,iRdOrR2,iAluOrMem,iRFWE,iMWE,istackContrl,ipcContrl,Zero,Cout,cntlInstruc);
end*/
always@(rst,Zero,Cout,cntlInstruc)
begin
if((cntlInstruc[5] == 1'b0) || (cntlInstruc[5:3] == 3'b110)) //rtype
begin
RdOrR2=1'b0;
AluOrMem=1'b1;
RFWE=1'b1;
MWE=1'b0;
stackContrl=2'b00;
pcContrl=2'b00;
end
else if(cntlInstruc[5:1] == 5'b10000) //ldm
begin
RdOrR2=1'b0;
AluOrMem=1'b0;
RFWE=1'b1;
MWE=1'b0;
stackContrl=2'b00;
pcContrl=2'b00;
end
else if(cntlInstruc[5:1] == 5'b10001) //stm
begin
RdOrR2=1'b1;
AluOrMem=1'b1;//dont care
RFWE=1'b0;
MWE=1'b1;
stackContrl=2'b00;
pcContrl=2'b00;
end
else if(cntlInstruc[5:3] == 3'b101) //branch con
begin
RdOrR2=1'b0;//dont care
AluOrMem=1'b1;//dont care
RFWE=1'b0;
MWE=1'b0;
stackContrl=2'b00;
case(cntlInstruc[2:1])
2'b00: pcContrl= Zero ? 2'b01 : 2'b00;
2'b01: pcContrl= (~Zero) ? 2'b01 : 2'b00;
2'b10: pcContrl= Cout ? 2'b01 : 2'b00;
2'b11: pcContrl= (~Cout) ? 2'b01 : 2'b00;
endcase
end
else if(cntlInstruc[5:1] == 5'b11100) //jmp
begin
RdOrR2=1'b0;//dont care
AluOrMem=1'b1;//dont care
RFWE=1'b0;
MWE=1'b0;
stackContrl=2'b00;
pcContrl=2'b11;
end
else if(cntlInstruc[5:1] == 5'b11101) //f call
begin
RdOrR2=1'b0;//dont care
AluOrMem=1'b1;//dont care
RFWE=1'b0;
MWE=1'b0;
stackContrl=2'b01;
pcContrl=2'b11;
end
else if(cntlInstruc[5:0] == 6'b111100) //return
begin
RdOrR2=1'b0;//dont care
AluOrMem=1'b1;//dont care
RFWE=1'b0;
MWE=1'b0;
stackContrl=2'b10;
pcContrl=2'b10;
end
else
begin
RdOrR2=1'b0;
AluOrMem=1'b0;
RFWE=1'b0;
MWE=1'b0;
stackContrl=2'b00;
pcContrl=2'b00;
end
end
endmodule
|
// SNES-Hook - A tiny 5V CPLD device to hijack reset on the SNES console
//
// Copyright (C) 2015 Evan Custodio
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////
//
// Project Name: SNES-Hook
// Author: Evan Custodio (@defparam)
//
// Module Name: snes_hook (Verilog)
//
// Interfaces: (1) 40 MHz clock in
// (2) address bus B and databus inputs
// (3) SNES Reset and Address bus B Read and Write (all active low)
//
// Clock Domains: (1) 40 MHz (clk) - sourced on board clock
// (2) async RAW snes addr/data bus, (typically switches around 2MHz - 3MHz)
//
// Description: This is the top level module for the SNES-Hook CPLD. It's only job ia to come
// out of reset search for the SNES CPU access to vector $00FFFC and override the reset vector
// to point to $2184. Futhermore the CPLD sits on address range $2184-$21FF and feeds its ROM
// contents to the SNES CPU during access. A primary bootloader is intended to be stored in this
// ROM and is defined in bootcode.hex
module snes_hook (
input clk,
input rst_n,
input [7:0] addr,
inout [7:0] data,
input PARD_n,
input PAWR_n,
input USB_RXFn,
input USB_TXEn,
output reg USB_RDn,
output reg USB_WRn,
input USB_BIT0,
input USB_BIT1,
output reg ROM_oe_n,
output ROM_wr_n,
output reg [3:0] glitch_force
);
// General Variables
reg data_enable;
wire bus_latch;
reg bus_latch_r1;
reg [7:0] data_out;
reg [7:0] hist;
reg punch;
reg [3:0] delay_write;
wire usb_active;
// State Machine Variables and Parameters
reg [2:0] HOOK_STATE;
parameter ST_INIT = 3'h0;
parameter ST_RST_FOUND = 3'h1;
parameter ST_SCAN_1 = 3'h2;
parameter ST_SCAN_2 = 3'h3;
parameter ST_SCAN_3 = 3'h4;
parameter ST_IRQ_1 = 3'h5;
parameter ST_IRQ_2 = 3'h6;
// Forced Assignments
assign ROM_wr_n = 1;
assign data = (punch) ? data_out : 8'hZZ; // Bi-directional databus assignments
assign usb_active = (~USB_BIT0 & USB_BIT1) ? 1'b1 : 1'b0;
snes_bus_sync bus_sync (
.clk(clk), // clock (40 MHz and reset)
.rst_n(rst_n),
.PA(addr), // RAW SNES addr bus
.event_latch(bus_latch) // Bus change event (detects changes in PA)
);
// Emulation RST vector hooking logic
//
// In this statemachine we assume the processor just came out of reset.
// With that assumption we know that the first two address that will be
// accessed is $00:FFFC and $00:FFFD. If we want to change the reset
// vector address we need to identify the CPU cycle when the address is
// on the data bus.
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin // reset regs
HOOK_STATE <= ST_INIT;
bus_latch_r1 <= 1'b0;
delay_write <= 3'b111;
end else begin
bus_latch_r1 <= bus_latch;
delay_write[3] <= (PARD_n && (HOOK_STATE != ST_INIT) && (HOOK_STATE != ST_RST_FOUND)) ? PAWR_n : 1'b1;
delay_write[2:0] <= delay_write[3:1];
if (bus_latch_r1 == 0 && bus_latch == 1) begin
hist <= addr;
case (HOOK_STATE)
// This is the first state, SNES has been reset and we are waiting for the
// processor to go to the reset vector low address
ST_INIT: begin
if (addr == 8'hFC) begin // address found! next wait for the high word address
if (usb_active) HOOK_STATE <= ST_RST_FOUND; // go to the high word search state
else HOOK_STATE <= ST_SCAN_1;
end
end
ST_RST_FOUND: begin
if (~punch) begin
HOOK_STATE <= ST_SCAN_1;
end
end
ST_SCAN_1: begin
//if (addr == (hist-1) && ~USB_RXFn && usb_active) HOOK_STATE <= ST_SCAN_2;
HOOK_STATE <= ST_SCAN_1; // Optimize out NMI search code
end
ST_SCAN_2: begin
if (addr == (hist-1)) HOOK_STATE <= ST_SCAN_3;
else HOOK_STATE <= ST_SCAN_1;
end
ST_SCAN_3: begin
if (addr == (hist-1)) HOOK_STATE <= ST_IRQ_1;
else HOOK_STATE <= ST_SCAN_1;
end
ST_IRQ_1: begin
HOOK_STATE <= ST_IRQ_2;
if (~punch) HOOK_STATE <= ST_SCAN_1;
end
ST_IRQ_2: begin
if (~punch) HOOK_STATE <= ST_SCAN_1;
end
endcase
end
end
end
always @(*) begin
USB_RDn = 1;
USB_WRn = 1;
ROM_oe_n = 1;
data_out = 0;
punch = 0;
glitch_force = 4'bZZZZ;
if ((HOOK_STATE == ST_INIT || HOOK_STATE == ST_RST_FOUND) && (addr == 8'hFC)) begin
punch = 1;
data_out = 8'h84; // These lines override the vector when reset vector is detected
glitch_force[2] = 1'b1;
glitch_force[0] = 1'b1;
end
if ((HOOK_STATE == ST_RST_FOUND) && (addr == 8'hFD)) begin
punch = 1;
data_out = 8'h21;
glitch_force[3] = 1'b1;
glitch_force[1] = 1'b1;
end
if ((HOOK_STATE == ST_IRQ_2 || HOOK_STATE == ST_IRQ_1) && (addr == 8'hEA)) begin
punch = 1;
data_out = 8'h84; // These lines override the vector when reset vector is detected
glitch_force[2] = 1'b1;
glitch_force[0] = 1'b1;
end
if ((HOOK_STATE == ST_IRQ_2) && (addr == 8'hEB)) begin
punch = 1;
data_out = 8'h21;
glitch_force[3] = 1'b1;
glitch_force[1] = 1'b1;
end
if (addr == 8'hFE && ~PARD_n) begin
punch = 1;
if (usb_active) data_out = {~USB_RXFn,~USB_TXEn,1'b1,5'b00000};
else data_out = 8'b00000000;
end
else if (addr == 8'hFF && ~PARD_n) begin
USB_RDn = 0;
end
else if (addr == 8'hFF && ~PAWR_n) begin
USB_WRn = |delay_write[1:0];
end
else if (addr[7] && |addr[6:2] && ~PARD_n) begin // If there is a read to addr $2184-$21FF, return contents addressed in ROM
ROM_oe_n = 0;
end
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.3 (win64) Build Mon Sep 28 20:06:43 MDT 2015
// Date : Wed Mar 30 14:52:13 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_24in_24out_12kb_synth_1/scfifo_24in_24out_12kb_stub.v
// Design : scfifo_24in_24out_12kb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_0_0,Vivado 2015.3" *)
module scfifo_24in_24out_12kb(clk, rst, din, wr_en, rd_en, dout, full, empty, data_count)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[23:0],wr_en,rd_en,dout[23:0],full,empty,data_count[0:0]" */;
input clk;
input rst;
input [23:0]din;
input wr_en;
input rd_en;
output [23:0]dout;
output full;
output empty;
output [0:0]data_count;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n % 2 << endl; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module FIFO_image_filter_src1_data_stream_2_V
#(parameter
MEM_STYLE = "block",
DATA_WIDTH = 8,
ADDR_WIDTH = 15,
DEPTH = 20000
)
(
// system signal
input wire clk,
input wire reset,
// write
output wire if_full_n,
input wire if_write_ce,
input wire if_write,
input wire [DATA_WIDTH-1:0] if_din,
// read
output wire if_empty_n,
input wire if_read_ce,
input wire if_read,
output wire [DATA_WIDTH-1:0] if_dout
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
(* ram_style = MEM_STYLE *)
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
reg [DATA_WIDTH-1:0] q_buf = 1'b0;
reg [ADDR_WIDTH-1:0] waddr = 1'b0;
reg [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire push;
wire pop;
reg [ADDR_WIDTH-1:0] usedw = 1'b0;
reg full_n = 1'b1;
reg empty_n = 1'b0;
reg [DATA_WIDTH-1:0] q_tmp = 1'b0;
reg show_ahead = 1'b0;
reg [DATA_WIDTH-1:0] dout_buf = 1'b0;
reg dout_valid = 1'b0;
//------------------------Instantiation------------------
//------------------------Task and function--------------
//------------------------Body---------------------------
assign if_full_n = full_n;
assign if_empty_n = dout_valid;
assign if_dout = dout_buf;
assign push = full_n & if_write_ce & if_write;
assign pop = empty_n & if_read_ce & (~dout_valid | if_read);
assign wnext = !push ? waddr :
(waddr == DEPTH - 1) ? 1'b0 :
waddr + 1'b1;
assign rnext = !pop ? raddr :
(raddr == DEPTH - 1) ? 1'b0 :
raddr + 1'b1;
// waddr
always @(posedge clk) begin
if (reset == 1'b1)
waddr <= 1'b0;
else
waddr <= wnext;
end
// raddr
always @(posedge clk) begin
if (reset == 1'b1)
raddr <= 1'b0;
else
raddr <= rnext;
end
// usedw
always @(posedge clk) begin
if (reset == 1'b1)
usedw <= 1'b0;
else if (push & ~pop)
usedw <= usedw + 1'b1;
else if (~push & pop)
usedw <= usedw - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1)
full_n <= 1'b1;
else if (push & ~pop)
full_n <= (usedw != DEPTH - 1);
else if (~push & pop)
full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1)
empty_n <= 1'b0;
else if (push & ~pop)
empty_n <= 1'b1;
else if (~push & pop)
empty_n <= (usedw != 1'b1);
end
// mem
always @(posedge clk) begin
if (push)
mem[waddr] <= if_din;
end
// q_buf
always @(posedge clk) begin
q_buf <= mem[rnext];
end
// q_tmp
always @(posedge clk) begin
if (reset == 1'b1)
q_tmp <= 1'b0;
else if (push)
q_tmp <= if_din;
end
// show_ahead
always @(posedge clk) begin
if (reset == 1'b1)
show_ahead <= 1'b0;
else if (push && usedw == pop)
show_ahead <= 1'b1;
else
show_ahead <= 1'b0;
end
// dout_buf
always @(posedge clk) begin
if (reset == 1'b1)
dout_buf <= 1'b0;
else if (pop)
dout_buf <= show_ahead? q_tmp : q_buf;
end
// dout_valid
always @(posedge clk) begin
if (reset == 1'b1)
dout_valid <= 1'b0;
else if (pop)
dout_valid <= 1'b1;
else if (if_read_ce & if_read)
dout_valid <= 1'b0;
end
endmodule
|
/*
# jtag_uart.v - This module provides an 8-bit parallel FIFO interface to
# the Altera Virtual JTAG module.
#
# Description: Follows the design pattern recommended in Altera's Virtual
# JTAG Megafunction user guide. Links the VJTAG to two 64-byte FIFO's
#
# Copyright (C) 2014 Binary Logic (nhi.phan.logic at gmail.com).
#
# This file is part of the Virtual JTAG UART toolkit
#
# Virtual UART is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
*/
`include "system_include.v"
module jtag_uart(
input clk_i,
input nreset_i,
input nwr_i,
input [7:0] data_i,
input rd_i,
output [7:0] data_o,
output txmt,
output txfl,
output rxmt,
output rxfl
);
//=======================================================
// JTAG Command Table
//=======================================================
`define TX 2'b00
`define RX 2'b01
`define STATUS 2'b10
`define BYPASS 2'b11
//=======================================================
// REG/WIRE declarations
//=======================================================
// Virtual JTAG signals, see Altera's Virtual JTAG Megafunction user guide for infoo
wire
[1:0] ir_out, ir_in;
wire
tdo,
tck,
tdi,
virtual_state_cdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir;
// VJTAG registers
wire [7:0] out_data; // Output buffer signals
reg [7:0] shift_buffer = 0; // Internal buffer for shifting in/out
reg cdr_delayed; // Capture data register delayed by half a clock cycle
reg sdr_delayed; // shift data register delayed by half a clock cycle
reg [1:0] bypass; // Bypass register
reg TXmt, TXfl, // Transmit empty, full signals
RXmt, RXfl; // Receive empty, full signals
// Stored instruction register, default to bypass
reg [1:0] ir = `BYPASS;
// Buffer management signals
wire out_full, out_empty;
wire in_full, in_empty;
//=======================================================
// Outputs
//=======================================================
assign ir_out = ir_in; // Just pass the IR out
// If the capture instruction register points to the bypass register then output
// the bypass register, or the shift register
assign tdo = (ir == `BYPASS) ? bypass[0] : shift_buffer[0];
assign txmt = TXmt;
assign txfl = TXfl;
assign rxmt = RXmt;
assign rxfl = RXfl;
//=======================================================
// Structural coding
//=======================================================
// Virtual JTAG - prep signals are on rising edge TCK, output on falling edge
// This connects to the internal signal trap hub - see the VJTAG MF User Guide
vjtag vjtag(
.ir_out(ir_out),
.tdo(tdo),
.ir_in(ir_in),
.tck(tck),
.tdi(tdi),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_cir(),
.virtual_state_e1dr(),
.virtual_state_e2dr(),
.virtual_state_pdr(),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.virtual_state_uir(virtual_state_uir)
);
// Output buffer FIFO, write clock is system clock
// read clock is the VJTAG TCK clock
buffer out(
.aclr(!nreset_i),
// Write signals
.data(data_i),
.wrclk(clk_i),
.wrreq(!nwr_i),
.wrfull(out_full),
// Read signals
.rdclk(!tck),
.rdreq(virtual_state_cdr & (ir == `TX)),
.q(out_data),
.rdempty(out_empty)
);
// Input buffer FIFO, write clock is VJTAG TCK clock
// read clock is the system clock
buffer in(
.aclr(!nreset_i),
// Write signals
.data(shift_buffer),
.wrclk(!tck),
.wrreq(virtual_state_udr & (ir == 2'h1)),
.wrfull(in_full),
// Read signals
.rdclk(!clk_i),
.rdreq(rd_i),
.q(data_o),
.rdempty(in_empty)
);
//=======================================================
// Procedural coding
//=======================================================
// Set the full/empty signals
always @(posedge tck)
begin
TXmt = out_empty;
RXfl = in_full;
end
// Set the full/empty signals
always @(posedge clk_i)
begin
TXfl = out_full;
RXmt = in_empty;
end
// VJTAG Controls for UART output
always @(negedge tck)
begin
// Delay the CDR signal by one half clock cycle
cdr_delayed = virtual_state_cdr;
sdr_delayed = virtual_state_sdr;
end
// Capture the instruction provided
always @(negedge tck)
begin
if( virtual_state_uir ) ir = ir_in;
end
// Data is clocked out on the falling edge, rising edge is for prep
always @(posedge tck)
begin
case( ir )
// Process output
`TX :
begin
if( cdr_delayed )
shift_buffer = out_data;
else
if( sdr_delayed )
shift_buffer = {tdi,shift_buffer[7:1]};
end
// Process input
`RX :
begin
if( sdr_delayed )
shift_buffer = {tdi,shift_buffer[7:1]};
end
// Process status request (only 4 bits are required to be shifted)
`STATUS :
begin
if( cdr_delayed )
shift_buffer = {4'b0000, RXfl, RXmt, TXfl, TXmt};
else
if( sdr_delayed )
shift_buffer = {tdi,shift_buffer[7:1]};
end
// Process input
default: // Bypass 2'b11
begin
if( sdr_delayed )
bypass = {tdi,bypass[1:1]};
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:16 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_1_stub.v
// Design : bram_2048_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [10:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
/**
* Module: arbiter
*
* Description:
* A look ahead, round-robing parameterized arbiter.
*
* <> request
* each bit is controlled by an actor and each actor can 'request' ownership
* of the shared resource by bring high its request bit.
*
* <> grant
* when an actor has been given ownership of shared resource its 'grant' bit
* is driven high
*
* <> select
* binary representation of the grant signal (optional use)
*
* <> active
* is brought high by the arbiter when (any) actor has been given ownership
* of shared resource.
*
*
* Created: Sat Jun 1 20:26:44 EDT 2013
*
* Author: Berin Martini //
*/
`ifndef _arbiter_ `define _arbiter_
module arbiter
#(parameter
NUM_PORTS = 6,
SEL_WIDTH = ((NUM_PORTS > 1) ? $clog2(NUM_PORTS) : 1))
(input clk,
input rst,
input [NUM_PORTS-1:0] request,
output reg [NUM_PORTS-1:0] grant,
output reg [SEL_WIDTH-1:0] select,
output reg active
);
/**
* Local parameters
*/
localparam WRAP_LENGTH = 2*NUM_PORTS;
// Find First 1 - Start from MSB and count downwards, returns 0 when no
// bit set
function [SEL_WIDTH-1:0] ff1 (
input [NUM_PORTS-1:0] in
);
reg set;
integer i;
begin
set = 1'b0;
ff1 = 'b0;
for (i = 0; i < NUM_PORTS; i = i + 1) begin
if (in[i] & ~set) begin
set = 1'b1;
ff1 = i[0 +: SEL_WIDTH];
end
end
end
endfunction
`ifdef VERBOSE
initial $display("Bus arbiter with %d units", NUM_PORTS);
`endif
/**
* Internal signals
*/
integer yy;
wire next;
wire [NUM_PORTS-1:0] order;
reg [NUM_PORTS-1:0] token;
wire [NUM_PORTS-1:0] token_lookahead [NUM_PORTS-1:0];
wire [WRAP_LENGTH-1:0] token_wrap;
/**
* Implementation
*/
assign token_wrap = {token, token};
assign next = ~|(token & request);
always @(posedge clk)
grant <= token & request;
always @(posedge clk)
select <= ff1(token & request);
always @(posedge clk)
active <= |(token & request);
always @(posedge clk)
if (rst) token <= 'b1;
else if (next) begin
for (yy = 0; yy < NUM_PORTS; yy = yy + 1) begin : TOKEN_
if (order[yy]) begin
token <= token_lookahead[yy];
end
end
end
genvar xx;
generate
for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
assign token_lookahead[xx] = token_wrap[xx +: NUM_PORTS];
assign order[xx] = |(token_lookahead[xx] & request);
end
endgenerate
endmodule
`endif // `ifndef _arbiter_
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; inline int read() { int X = 0, w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) X = (X << 3) + (X << 1) + (ch ^ 48), ch = getchar(); return w ? -X : X; } int n, m; int dx[4][5] = { {2, 1, 0, 0, 0}, {1, 0, 0, 0, -1}, {0, 0, 0, -1, -2}, {1, 0, 0, 0, -1}}; int dy[4][5] = { {0, 0, -1, 0, 1}, {0, 0, 1, 2, 0}, {-1, 0, 1, 0, 0}, {0, -2, -1, 0, 0}}; char maze[9][9]; int ans = -1; char as[9][9]; bool check(int x, int y, int dir, char c) { for (int i = 0; i < 5; i++) { int nx = x + dx[dir][i]; int ny = y + dy[dir][i]; if (nx < 0 or nx >= n or ny < 0 or ny >= m) { return 0; } if (!(c == . or maze[nx][ny] == . )) { return 0; } } for (int i = 0; i < 5; i++) { int nx = x + dx[dir][i]; int ny = y + dy[dir][i]; maze[nx][ny] = c; } return 1; } void dfs(int x, int y, char c) { if (x == n) { if (c - A > ans) { ans = c - A ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { as[i][j] = maze[i][j]; } } } return; } if ((n - x) * m / 5 + c - A <= ans) { return; } if (y == m) { dfs(x + 1, 0, c); return; } for (int i = 0; i < 4; i++) { if (check(x, y, i, c)) { dfs(x, y + 1, c + 1); check(x, y, i, . ); } } dfs(x, y + 1, c); } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { maze[i][j] = . ; } } dfs(0, 0, A ); printf( %d n , ans); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { printf( %c , as[i][j]); } printf( n ); } return 0; }
|
`define bsg_and_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_AND2X1_b``bits and_gate (.i0(a_i),.i1(b_i),.o); \
end
module bsg_and #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
`bsg_and_macro(34) else
`bsg_and_macro(33) else
`bsg_and_macro(32) else
`bsg_and_macro(31) else
`bsg_and_macro(30) else
`bsg_and_macro(29) else
`bsg_and_macro(28) else
`bsg_and_macro(27) else
`bsg_and_macro(26) else
`bsg_and_macro(25) else
`bsg_and_macro(24) else
`bsg_and_macro(23) else
`bsg_and_macro(22) else
`bsg_and_macro(21) else
`bsg_and_macro(20) else
`bsg_and_macro(19) else
`bsg_and_macro(18) else
`bsg_and_macro(17) else
`bsg_and_macro(16) else
`bsg_and_macro(15) else
`bsg_and_macro(14) else
`bsg_and_macro(13) else
`bsg_and_macro(12) else
`bsg_and_macro(11) else
`bsg_and_macro(10) else
`bsg_and_macro(9) else
`bsg_and_macro(8) else
`bsg_and_macro(7) else
`bsg_and_macro(6) else
`bsg_and_macro(5) else
`bsg_and_macro(4) else
`bsg_and_macro(3) else
`bsg_and_macro(2) else
`bsg_and_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = a_i & b_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_and)
|
module control_exe(
clk,
rst,
branch_target, // PC+1+offset
pc_added, //PC+1
flag, // flagprev_idex
cond, // condition for branch
branch_idex, // input from control.v for branch
jal_idex, // input from control.v for jump and link
jr_idex, //input from control.v for jump return
exec_idex, //input from control.v for exec
branch2_idex, // output that finally goes to pc mux
nop_alu, // output to alu
nop_lw, //nop for sw(mem)
nop_sw, //nop for lw(mem)
execPCadded, //the previous pcadded value which is needed for exec after executing its branch instruction
putPCback, //select signal to choose pcadded for exec or branch target normal(jr/jal/br)
);
input clk;
input rst;
input [15:0] branch_target;
input [15:0] pc_added;
input branch_idex;
input jal_idex;
input jr_idex;
input exec_idex;
input [2:0] flag;
input [3:0] cond;
output branch2_idex;
reg branch2_temp;
reg branch2_temp2;
output nop_alu;
output nop_lw;
output nop_sw;
output [15:0] execPCadded;
output putPCback;
reg nop_alu_temp;
reg nop_lw_temp;
reg nop_sw_temp;
reg canBranch; // cond check
reg [2:0] NOP;
reg isBr;
reg [3:0] myCond;
reg setExec; // exec statement sets this to 1, next statement makes it 0
//reg isExec;
reg [15:0] execPCadded_temp, execPCadded_temp2;
reg [15:0] execPCadded_stored;// reg inside control_exe where the pcadded value(exec+1) is stored
reg putPCback_temp2;//reg inside control_exe which stores the mux select signal
reg putBack_temp;
always @ (pc_added)
//always @ (posedge clk)
//always @ (pc_added)
//always @ (branch_target, pc_added, branch_idex, flag, cond)
begin
putPCback_temp2=1'b0;
if(setExec===1'b1 && (!(NOP>3'b000) || NOP === 3'bxxx)) begin
/// send putPCback=1 and output execPCadded
putPCback_temp2 = 1'b1;
execPCadded_temp2 = execPCadded_stored;
setExec = 1'b0;
end
if(exec_idex===1'b1 && putPCback_temp2 === 1'b0 && (!(NOP>3'b000) || NOP === 3'bxxx)) begin
setExec = 1'b1;
execPCadded_stored = pc_added;
end
else begin
/// putPCback =0
end
myCond=cond;
isBr=branch_idex;
/*if(jal_idex === 1'b1) begin
myCond = 4'b0111;
isBr = 1'b1;
end*/
if(isBr!==1'b0) begin
if(flag[2] == 1'b1 && myCond==4'b000)
begin
//Branch EQUAL previous instruction condition
//$display("4'b000");
canBranch = 1'b1;
end
else if(flag[2] == 1'b0 && myCond==4'b001)
begin
//Branch NOT EQUAL prev instruction condition
//$display("4'b001");
canBranch = 1'b1;
end
else if(((flag[2] == 1'b0) && (flag[0] == 1'b0)) && myCond == 4'b010)
begin
//Branch GREATER THAN prev instruction condition
//$display("4'b010");
canBranch = 1'b1;
end
else if(flag[0] == 1'b1 && myCond == 4'b011)
begin
//Branch LESS THAN prev instruction condition
//$display("4'b011");
canBranch = 1'b1;
end
else if(((flag[2] == 1'b1) || ((flag[2] == 1'b0) && (flag[0] == 1'b0))) && myCond == 4'b100)
begin
//Branch Greater Than or Equal To prev instruction condition
//$display("4'b100");
//canBranch = 1'b1;
canBranch = 1'b1;
end
else if(((flag[0] == 1'b1) || (flag[2] == 1'b1)) && myCond == 4'b101)
begin
//Branch Less Than or Equal To prev instruction condition
//$display("4'b101");
canBranch = 1'b1;
end
else if(flag[1] == 1'b1 && myCond == 4'b110)
begin
//Branch overflow prev instruction condition
//$display("4'b110");
canBranch = 1'b1;
end
else if(cond==4'b111)
begin
//Branch if true
//$display("4'b111");
canBranch = 1'b1;
end
else
begin
canBranch = 1'b0;
end
end
else begin
canBranch = 1'b0;
end
/*$display("SEQ");
if((isBr===1'b1 || (jal_idex===1'b1 || jr_idex === 1'b1))) begin
$display("1true");
end
if(canBranch===1'b1 || jal_idex===1'b1 || jr_idex === 1'b1) begin
$display("2true");
end
$write(branch_target);
$write("added:");
$write(pc_added);
if(branch_target!==pc_added) begin
$display("3true");
end
if((branch_target!==pc_added) && (canBranch===1'b1 || jal_idex===1'b1 || jr_idex === 1'b1)) begin
$display("4true");
end
if((isBr===1'b1 || (jal_idex===1'b1 || jr_idex === 1'b1)) && ((branch_target!==pc_added) &&
(canBranch===1'b1 || (jal_idex===1'b1 || jr_idex === 1'b1)))) begin
$display("MAIN true");
end*/
if((isBr===1'b1 || (jal_idex===1'b1 || jr_idex === 1'b1 || exec_idex === 1'b1 || putPCback_temp2 === 1'b1)) && ((branch_target!==pc_added) &&
(canBranch===1'b1 || jal_idex===1'b1 || jr_idex === 1'b1 || exec_idex === 1'b1 || putPCback_temp2 === 1'b1))) // successful branch
begin
//if(branch_idex===1'b1) begin $display("branch=1"); end
//$display("success");
branch2_temp=1'b1; // change PC to branch_target
if(!(NOP>3'b000)|| NOP===3'bxxx) // increment NOP by 3
begin
NOP = 3'b100;
end
else
begin
//NOP = NOP + 3'b100;
// The above case will never occur, coz NOP always become 0
// before going to the EXE part of the "branched" instruction
// For a branch after a branch, the outer IF can be true
// but it still needs to fail or be bypassed as its an NOP
branch2_temp=1'b0;
//NOP = NOP + 3'b001; // DONT DO THIS
end
end
else if((isBr===1'b1 || jal_idex===1'b1 || jr_idex === 1'b1 || exec_idex === 1'b1 || putPCback_temp2 === 1'b1) && ((branch_target===pc_added)||
(canBranch===1'b0 || jal_idex===1'b1 || jr_idex === 1'b1 || exec_idex === 1'b1 || putPCback_temp2 === 1'b1))) // branch failed
begin
//$display("failed");
branch2_temp=1'b0; // don't change PC
if(!(NOP>3'b000) || NOP===3'bxxx) // increment NOP by 1 to not operate on the branch condition
begin
NOP = 3'b001;
end
else
begin
//NOP = NOP + 3'b001;
// The above doesn't happen in any situation
// if it does we need to bypass that branch
//NOP = NOP + 3'b001; // DONT DO THIS
end
end
else
begin // branch = 0 --- not a branch statement
branch2_temp=1'b0;
end
// Different if-else construct
//NOP = NOP+3'b001;
if(!(NOP>3'b000) || NOP === 3'bxxx) // do the operation when NOP = 0 && when NOP is invalid !( NOP>0)
begin
nop_alu_temp = 1'b0;
nop_lw_temp = 1'b0;
nop_sw_temp = 1'b0;
end
else
begin
nop_alu_temp = 1'b1;
if(branch2_temp===1'b1) begin
nop_lw_temp = 1'b0;
end
else begin
nop_lw_temp = 1'b1;
end
nop_sw_temp = 1'b1;
NOP = NOP - 3'b001;
end
branch2_temp2 = branch2_temp;
execPCadded_temp = execPCadded_temp2;
putBack_temp = putPCback_temp2;
end // always end
assign branch2_idex = branch2_temp2;
assign nop_alu = (putPCback===1'b0)? nop_alu_temp : 1'b0;
assign nop_lw = (putPCback===1'b0)? nop_lw_temp : 1'b0;
assign nop_sw = (putPCback===1'b0)? nop_sw_temp : 1'b0;
assign execPCadded = execPCadded_temp;
assign putPCback = putBack_temp;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_4_V
`define SKY130_FD_SC_MS__O31AI_4_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_4_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 , unroll-loops , omit-frame-pointer , inline ) #pragma GCC option( arch=native , tune=native , no-zeroupper ) #pragma GCC target( avx , popcnt ) using namespace std; const long long int INF = (long long int)1e17 + 5; const unsigned long long int MOD = 1e8 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); std::cout << std::fixed; std::cout.precision(6); int n; cin >> n; vector<pair<long long int, long long int>> v; for (int i = 0; i < n; i++) { long long int a; cin >> a; v.emplace_back(make_pair(a, 0)); } for (int i = 0; i < n; i++) { long long int a; cin >> a; v[i].second = a; } long long int mini = INF; int pos = 0; for (int j = 1; j < n - 1; j++) { long long int minl = INF; long long int minr = INF; for (int i = j - 1; i >= 0; i--) { if (v[i].first < v[j].first) minl = min(minl, v[i].second); } for (int i = j + 1; i < n; i++) { if (v[i].first > v[j].first) minr = min(minr, v[i].second); } if (minl != INF && minr != INF) { long long int l = v[j].second + minr + minl; mini = min(mini, l); } } if (mini == INF) cout << -1 n ; else cout << mini << n ; return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
module receiver_tb();
reg [15:0] story;
reg clk_i = 0, reset_i = 0;
reg rxd_i = 1, rxc_i = 0;
reg rxreg_oe_i = 0, rxregr_oe_i = 0;
wire idle_o;
wire [63:0] dat_o;
wire sample_to;
receiver #(
.SHIFT_REG_WIDTH(64),
.BAUD_RATE_WIDTH(32)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(6'd11), // 8O1
.baud_i(32'd49), // 1Mbps when clocked at 50MHz.
.eedd_i(1'b1),
.eedc_i(1'b1),
.rxd_i(rxd_i),
.rxc_i(rxc_i),
.dat_o(dat_o),
.idle_o(idle_o),
.sample_to(sample_to)
);
always begin
#10 clk_i <= ~clk_i;
end
task assert_idle;
input expected;
begin
if (expected !== idle_o) begin
$display("@E %d idle_o Expected %d; got %d", story, expected, idle_o);
$stop;
end
end
endtask
task assert_dat;
input [63:0] expected;
begin
if (expected !== dat_o) begin
$display("@E %d dat_o Expected %064B; got %064B", story, expected, dat_o);
$stop;
end
end
endtask
initial begin
$dumpfile("receiver.vcd");
$dumpvars;
story <= 1;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
reset_i <= 0;
assert_idle(1);
assert_dat(64'hFFFFFFFFFFFFFFFF);
rxd_i <= 0; #1000; assert_dat({1'b0, ~(63'h0)});
rxd_i <= 1; #1000; assert_dat({2'b10, ~(62'h0)});
rxd_i <= 0; #1000; assert_dat({3'b010, ~(61'h0)});
rxd_i <= 1; #1000; assert_dat({4'b1010, ~(60'h0)});
rxd_i <= 0; #1000; assert_dat({5'b01010, ~(59'h0)});
rxd_i <= 0; #1000; assert_dat({6'b001010, ~(58'h0)});
rxd_i <= 0; #1000; assert_dat({7'b0001010, ~(57'h0)});
rxd_i <= 0; #1000; assert_dat({8'b00001010, ~(56'h0)});
rxd_i <= 1; #1000; assert_dat({9'b100001010, ~(55'h0)});
rxd_i <= 0; #1000; assert_dat({10'b0100001010, ~(54'h0)});
rxd_i <= 1; #1000; assert_dat({11'b10100001010, ~(53'h0)});
rxd_i <= 0; #1000; assert_dat({12'b010100001010, ~(52'h0)});
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
story <= 2;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
reset_i <= 0;
rxd_i <= 0;
wait(clk_i); wait(~clk_i);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{1'b0},{63{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{2'b0},{62{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{3'b0},{61{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{4'b0},{60{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{5'b0},{59{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{6'b0},{58{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{7'b0},{57{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{8'b0},{56{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{9'b0},{55{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{10'b0},{54{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{11'b0},{53{1'b1}}}); assert_idle(1);
$display("@I Done.");
$stop;
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Tree Matrix Arbiter
*
* - 'multistage' parameter - see description in matrix_arbiter.v
*
* The tree arbiter splits the request vector into groups, performing arbitration
* simultaneously within groups and between groups. Note this has implications
* for fairness.
*
* Only builds one level of a tree
*
*/
module LAG_tree_arbiter (request, grant, success, clk, rst_n);
parameter multistage=0;
parameter size=20;
parameter groupsize=4;
parameter numgroups=size/groupsize;
input [size-1:0] request;
output [size-1:0] grant;
input success;
input clk, rst_n;
logic [size-1:0] intra_group_grant;
logic [numgroups-1:0] group_grant, any_group_request;
logic [numgroups-1:0] current_group_success, last_group_success;
logic [numgroups-1:0] group_success;
genvar i;
generate
for (i=0; i<numgroups; i=i+1) begin:arbiters
if (multistage==0) begin
//
// group_arbs need to be multistage=1, as group may not get granted
//
matrix_arb #(.size(groupsize),
.multistage(1)
) arb
(.request(request[(i+1)*groupsize-1:i*groupsize]),
.grant(intra_group_grant[(i+1)*groupsize-1:i*groupsize]),
.success(group_success[i]),
.clk, .rst_n);
end else begin
matrix_arb #(.size(groupsize),
.multistage(multistage)
) arb
(.request(request[(i+1)*groupsize-1:i*groupsize]),
.grant(intra_group_grant[(i+1)*groupsize-1:i*groupsize]),
.success(group_success[i] & success),
// .success('1),
.clk, .rst_n);
end
assign any_group_request[i] = |request[(i+1)*groupsize-1:i*groupsize];
assign grant[(i+1)*groupsize-1:i*groupsize]=
intra_group_grant[(i+1)*groupsize-1:i*groupsize] & {groupsize{group_grant[i]}};
//.success(any_group_request[i] & group_grant[i] & success),
//assign current_group_success[i]=|grant[(i+1)*groupsize-1:i*groupsize];
assign current_group_success[i]= group_grant[i];
end
if (multistage==2) begin
always@(posedge clk) begin
if (!rst_n) begin
last_group_success<='0;
end else begin
last_group_success<=current_group_success;
end
end
assign group_success=last_group_success;
end else begin
assign group_success=current_group_success;
end
endgenerate
matrix_arb #(.size(numgroups),
.multistage(multistage)
) group_arb
(.request(any_group_request),
.grant(group_grant),
.success(success),
.clk, .rst_n);
endmodule // tree_arbiter
|
#include <bits/stdc++.h> const int MaxN = 300000; using namespace std; long long arr[MaxN + 5], a[MaxN + 5], n; struct Segment { int l, r, lx, mx, rx; int Sign(long long x) { return x > 0 ? 1 : -1; } void Update(Segment A, Segment B) { lx = A.lx, rx = B.rx; mx = max(A.mx, B.mx); if (a[A.r] && a[B.l] && Sign(a[A.r]) >= Sign(a[B.l])) { mx = max(mx, A.rx + B.lx); if (A.mx == A.r - A.l + 1) lx = A.mx + B.lx; if (B.mx == B.r - B.l + 1) rx = B.mx + A.rx; } mx = max(mx, max(lx, rx)); l = A.l, r = B.r; } } seg[MaxN * 4 + 5]; void Update(int l, int r, int t, int x, int w) { if (l == r) { a[x] += w; if (a[x] != 0) seg[t] = (Segment){l, r, 1, 1, 1}; else seg[t] = (Segment){l, r, 0, 0, 0}; return; } int mid = (l + r) >> 1; if (x <= mid) Update(l, mid, t * 2, x, w); else Update(mid + 1, r, t * 2 + 1, x, w); seg[t].Update(seg[t * 2], seg[t * 2 + 1]); } int main() { while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) scanf( %d , &arr[i]); for (int i = 1; i <= n; i++) a[i] = arr[i + 1] - arr[i]; for (int i = 1; i < n; i++) Update(1, n - 1, 1, i, 0); int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { int l, r, w; scanf( %d%d%d , &l, &r, &w); if (l - 1 >= 1) Update(1, n - 1, 1, l - 1, w); if (r <= n - 1) Update(1, n - 1, 1, r, -w); printf( %d n , seg[1].mx + 1); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p = 0, ans = 0; string s, dvg, answ, r_dvg; cin >> n >> s; for (int i = 0; i < n - 1; i++) { dvg = s.substr(i, 2); for (int j = i; j < n - 1; j++) { r_dvg = s.substr(j, 2); if (dvg == r_dvg) { p++; } } if (p > ans) { ans = p; answ = dvg; } p = 0; } cout << answ << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:38:20 11/23/2014
// Design Name:
// Module Name: Anti_jitter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Anti_jitter( input wire clk,
input wire [4:0] button,
input wire [7:0] SW,
output reg [4:0]button_out,
output reg [4:0]button_pluse,
output reg [7:0] SW_OK
);
reg [31:0] counter;
reg [4:0] btn_temp;
reg [7:0] sw_temp;
reg pluse;
always @(posedge clk) begin
btn_temp <= button;
sw_temp <= SW;
if(btn_temp !=button || sw_temp !=SW) begin
counter <= 32'h00000000;
pluse <= 0;
end
else if(counter<100000)
counter<=counter+1;
else begin
button_out<=button;
pluse <= 1;
if(!pluse)
button_pluse <= button;
else button_pluse <= 0;
SW_OK <= SW;
end
end
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:gcd:1.0
// IP Revision:
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_block_design_gcd_0_1 (
s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_BRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR" *)
input wire [5 : 0] s_axi_gcd_bus_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID" *)
input wire s_axi_gcd_bus_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY" *)
output wire s_axi_gcd_bus_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA" *)
input wire [31 : 0] s_axi_gcd_bus_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB" *)
input wire [3 : 0] s_axi_gcd_bus_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID" *)
input wire s_axi_gcd_bus_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY" *)
output wire s_axi_gcd_bus_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP" *)
output wire [1 : 0] s_axi_gcd_bus_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID" *)
output wire s_axi_gcd_bus_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY" *)
input wire s_axi_gcd_bus_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR" *)
input wire [5 : 0] s_axi_gcd_bus_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID" *)
input wire s_axi_gcd_bus_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY" *)
output wire s_axi_gcd_bus_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA" *)
output wire [31 : 0] s_axi_gcd_bus_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP" *)
output wire [1 : 0] s_axi_gcd_bus_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID" *)
output wire s_axi_gcd_bus_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, \
ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY" *)
input wire s_axi_gcd_bus_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN \
gcd_block_design_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
gcd #(
.C_S_AXI_GCD_BUS_ADDR_WIDTH(6),
.C_S_AXI_GCD_BUS_DATA_WIDTH(32)
) inst (
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_AWREADY(s_axi_gcd_bus_AWREADY),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID),
.s_axi_gcd_bus_WREADY(s_axi_gcd_bus_WREADY),
.s_axi_gcd_bus_BRESP(s_axi_gcd_bus_BRESP),
.s_axi_gcd_bus_BVALID(s_axi_gcd_bus_BVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_ARREADY(s_axi_gcd_bus_ARREADY),
.s_axi_gcd_bus_RDATA(s_axi_gcd_bus_RDATA),
.s_axi_gcd_bus_RRESP(s_axi_gcd_bus_RRESP),
.s_axi_gcd_bus_RVALID(s_axi_gcd_bus_RVALID),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int ans = 0, a, b, a2, b2; cin >> a >> b; while (((a != 0) and (b != 0))) { if ((a + b) <= 2) { cout << ans << endl; return 0; } if (2 * a <= b) { cout << ans + a << endl; return 0; } if (2 * b <= a) { cout << ans + b << endl; return 0; } if (a == 2 and b == 2) { cout << ans + 1 << endl; return 0; } int aux = a; int aux2 = b; a = min(aux, aux2); b = max(aux, aux2); while (a < b) { a--; b -= 2; ans++; } aux = a / 3; a = a - aux * 3; b = b - aux * 3; aux = aux * 2; ans += aux; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int n, k; long long int a[200100]; bool check(long long int x) { long long int moves = 0; for (__typeof(n + 1) i = (n / 2 + 1) - ((n / 2 + 1) > (n + 1)); i != (n + 1) - ((n / 2 + 1) > (n + 1)); i += 1 - 2 * ((n / 2 + 1) > (n + 1))) { moves += max((long long int)0, x - a[i]); if (moves > k) return false; } if (moves <= k) return true; return false; } void solve() { cin >> n >> k; for (__typeof(n + 1) i = (1) - ((1) > (n + 1)); i != (n + 1) - ((1) > (n + 1)); i += 1 - 2 * ((1) > (n + 1))) { cin >> a[i]; } sort(a + 1, a + n + 1); long long int l = 1, r = 2e9; bool can = false; while (l < r) { long long int mid = (l + r + 1) / 2; if (check(mid)) { l = mid; } else { r = mid - 1; } } cout << l << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; t = 1; while (t--) { solve(); } }
|
module halfadder(in1, in2, sum, cout);
input wire in1, in2;
output wire sum, cout;
assign sum = in1 ^ in2;
assign cout = in1 & in2;
endmodule
module fulladder(in1, in2, cin, sum, cout);
input wire in1, in2, cin;
output wire sum, cout;
assign sum = in1 ^ in2 ^ cin;
assign cout = (in1 & in2) | (in2 & cin) | (cin & in1);
endmodule
module fourbitadder(in1, in2, cin, sum, cout);
input wire[3: 0] in1;
input wire[3: 0] in2;
input wire cin;
output wire[3: 0] sum;
output wire cout;
wire[2: 0] _cout;
fulladder f1(in1[0], in2[0], cin, sum[0], _cout[0]);
fulladder f2(in1[1], in2[1], _cout[0], sum[1], _cout[1]);
fulladder f3(in1[2], in2[2], _cout[1], sum[2], _cout[2]);
fulladder f4(in1[3], in2[3], _cout[2], sum[3], cout);
endmodule
module addersubtractor(in1, in2, s, out, cout);
input wire[3: 0] in1;
input wire[3: 0] in2;
input wire s;
output wire[3: 0] out;
output wire cout;
fourbitadder a(in1, {in2[3] ^ s, in2[2] ^ s, in2[1] ^ s, in2[0] ^ s}, s, out, cout);
endmodule
module fulladdermux(in1, in2, cin, sum, cout);
input wire in1, in2, cin;
output wire sum, cout;
fourbitmux m1({cin, !cin, !cin, cin}, {in1, in2}, sum);
fourbitmux m2({1'b1, cin, cin, 1'b0}, {in1, in2}, cout);
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr long long R = 1e3 + 69, INF = 2e9 + 6969, mod = 998244353; long long n, a[R], dp[R], fact[R], rev[R]; long long choose(long long N, long long K) { long long cur = (fact[N] * rev[K]) % mod; cur = (cur * rev[N - K]) % mod; return cur; } long long Pow(long long a, long long p) { long long w = 1; while (p) { if (p & 1) w = (w * a) % mod; a = (a * a) % mod; p >>= 1; } return w; } int main() { scanf( %lld , &n); for (int i = 0; i < n; ++i) scanf( %lld , &a[i]); fact[0] = 1; for (int i = 1; i <= n; ++i) fact[i] = (i * fact[i - 1]) % mod; rev[n] = Pow(fact[n], mod - 2); for (int i = n - 1; i >= 0; --i) rev[i] = (rev[i + 1] * (i + 1)) % mod; dp[n] = 1; for (int i = n - 1; i >= 0; --i) { if (a[i] <= 0 || a[i] + i >= n) continue; for (int j = i + a[i] + 1; j <= n; ++j) { dp[i] += (dp[j] * choose(j - i - 1, a[i])) % mod; dp[i] %= mod; } } long long sum = 0; for (int i = 0; i < n; ++i) sum = (sum + dp[i]) % mod; printf( %lld n , sum); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, unsigned long long int y) { long long int res = 1; while (y > 0) { if (y & 1) { res = res * x; } y = y >> 1; x = x * x; } return res; } long long int powermod(long long int x, unsigned long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) { res = (res * x) % p; } y = y >> 1; x = (x * x) % p; } return res; } int32_t main() { long long int n, m; cin >> n >> m; vector<long long int> f(m + n); f[0] = 1, f[1] = 1; for (long long int i = (long long int)(2); i < (long long int)(m + n); i++) { f[i] = f[i - 1] + f[i - 2]; f[i] %= 1000000007; } long long int ans = 2 * f[n]; ans %= 1000000007; ans += 2 * f[m]; ans %= 1000000007; ans -= 2; if (ans < 0) ans += 1000000007; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int bags[4]; int flag = 0; for (int i = 0; i < 4; i++) { cin >> bags[i]; } if (bags[0] + bags[1] == bags[2] + bags[3]) { cout << YES n ; } else if (bags[0] + bags[2] == bags[1] + bags[3]) { cout << YES n ; } else if (bags[0] + bags[3] == bags[1] + bags[2]) { cout << YES n ; } else if (bags[0] + bags[1] + bags[2] == bags[3] || bags[0] + bags[2] + bags[3] == bags[1] || bags[0] + bags[1] + bags[3] == bags[2] || bags[3] + bags[1] + bags[2] == bags[0]) { cout << YES n ; } else { cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long int n, c = 0; int x; cin >> n; unsigned long long int pos[11] = {}, neg[11] = {}, z = 0, i; for (i = 0; i < n; i++) { cin >> x; if (x == 0) z++; else if (x < 0) neg[(-1) * x]++; else { pos[x]++; } } for (int i = 1; i < 11; i++) { c = c + pos[i] * neg[i]; } if (z > 1) z = (z * (z - 1)) / 2; else { z = 0; } cout << c + z; }
|
#include <bits/stdc++.h> int main() { int t, n; scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 1; i <= n; ++i) printf( %d%c , n - i + 1, n [i == n]); } }
|
//-----------------------------------------------------------------------------
//-- Divisor de frecuencia entre M
//-- (c) BQ. August 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
//-- Entrada: clk_in. Señal original
//-- Salida: clk_out. Señal de frecuencia 1/M de la original
module divM(input wire clk_in, output wire clk_out);
//-- Valor por defecto del divisor
//-- Como en la iCEstick el reloj es de 12MHz, ponermos un valor de 12M
//-- para obtener una frecuencia de salida de 1Hz
parameter M = 12_000_000;
//-- Numero de bits para almacenar el divisor
//-- Se calculan con la funcion de verilog $clog2, que nos devuelve el
//-- numero de bits necesarios para representar el numero M
//-- Es un parametro local, que no se puede modificar al instanciar
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk_in)
if (divcounter == M - 1)
divcounter <= 0;
else
divcounter <= divcounter + 1;
//-- Sacar el bit mas significativo por clk_out
assign clk_out = divcounter[N-1];
endmodule
|
//==================================================================================================
// Filename : submidRecursiveKOA2.v
// Created On : 2016-10-28 08:46:44
// Last Modified : 2016-10-31 11:42:31
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : submidRecursiveKOA.v
// Created On : 2016-10-27 23:28:55
// Last Modified : 2016-10-28 08:42:21
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module submidRecursiveKOA2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] Data_S_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
reg [SW-1:0] post_Data_A_i;
reg [SW-1:0] post_Data_B_i;
always @(posedge clk) begin : SEGMENTATION
post_Data_A_i = Data_A_i;
post_Data_B_i = Data_B_i;
end
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(post_Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-SW/2-1:0]),
.Data_B_i(post_Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (post_Data_A_i[((SW/2)-1):0] + post_Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (post_Data_B_i[((SW/2)-1):0] + post_Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Data_S_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(post_Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-SW/2-1:0]),
.Data_B_i(post_Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW(SW/2+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (post_Data_A_i[SW-SW/2-1:0] + post_Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= post_Data_B_i[SW-SW/2-1:0] + post_Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Data_S_o <= {leftside2,S_B,rightside2} + {Q_left,Q_right};
end
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; string str; int memo[100005][3]; int dp(int Idx, int prev) { if (Idx == (int)str.size()) return 0; int choice1 = 1000000; if (memo[Idx][prev] != -1) return memo[Idx][prev]; if (prev == 0) { if (isupper(str[Idx])) choice1 = dp(Idx + 1, 0) + 1; else choice1 = dp(Idx + 1, 0); } else { if (isupper(str[Idx])) { choice1 = min(dp(Idx + 1, 0) + 1, dp(Idx + 1, 1)); } else choice1 = min(dp(Idx + 1, 0), dp(Idx + 1, 1) + 1); } return memo[Idx][prev] = choice1; } int main() { cin >> str; memset(memo, -1, sizeof(memo)); int ans = dp(0, 1); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[100001], c[100001]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int s = 0; for (int i = n - 1; i >= 0; i--) if (s > 0) s -= a[i]; else { c[i] = 1; s += a[i]; } if (s < 0) for (int i = 0; i < n; i++) c[i] ^= 1; for (int i = 0; i < n; i++) cout << (c[i] ? + : - ); cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_TB_V
`define SKY130_FD_SC_LS__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:11:42 05/27/2016
// Design Name:
// Module Name: TOP
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module TOP
(
input clk,
input reset,
input [7:0] RTC_out,
input ps2d,
input ps2c,
output [7:0] RTC_in,
output A_D,CS,RD,WR, hsync, vsync,
output [7:0] rgb,
output reg Flag_Alarma_VGA_1
);
wire write_strobe, interrupt,sleep, k_write_strobe, read_strobe, interrupt_ack,PB_in, Pulso_Listo,listo,contro_listo,contro_lee,contro_escribe;
wire Dato_Dir,HI;
wire [7:0] Dato;
wire [7:0] Dir;
wire [7:0] salida_bus;
wire [2:0]estado_m;
wire [3:0]c_5;
wire [3:0] direccion;
wire [7:0] port_id;
wire [7:0]in_port;
wire [7:0]out_port, RG1, RG2, RG3,VGA_1,VGA_2,VGA_3, seg_Ti, min_Ti, hor_Ti;
wire [3:0] d_seg,u_seg;
//wire [7:0] dato_seg;
wire en_out, Flag_Alarma_VGA;
wire am_pm;
wire escribiendo;
wire off_alarma;
wire on_alarma;
wire [7:0]tecla;
wire [7:0]tecla2;
wire [7:0]tecla3;
wire [7:0] Salida_G;
assign interrupt=0;
assign d_seg[3:0] = RTC_out [7:4];
assign u_seg[3:0] = RTC_out [3:0];
assign am_pm=0;
assign sleep=0;
assign off_alarma=~Flag_Alarma_VGA;
assign on_alarma=Flag_Alarma_VGA;
//____________________________________________________________________
PICOBLAZE f2(
.interrupt(interrupt),//
.sleep(sleep), //
.clk(clk),
.in_port(in_port),
.rst(reset),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe), //
.read_strobe(read_strobe), //
.out_port(out_port),
.port_id(port_id),
.interrupt_ack(interrupt_ack)//
);
MUX_DECO_FF f1 (
.tecla(tecla),
.tecla2(tecla2),
.tecla3(tecla3),
.rst(reset),
.clk(clk),
.listo(listo),
.listo_lee(listo),
.listo_escribe(listo),
.seleccion(port_id),
.salida_picoblaze(in_port),
.RG1(VGA_1),
.RG2(VGA_2),
.RG3(VGA_3)
);
registros_salida f3 (
.Write_Strobe(write_strobe),
.Out_Port(out_port),
.Port_ID(port_id),
.bandera(estado_m),
.rst(reset),
.reset(reset),
.clk(clk),
.Dir(Dir),
.Dato(Dato),
.direccion(direccion),
.contro_listo(contro_listo),
.contro_lee(contro_lee),
.contro_escribe(contro_escribe)
);
//---------------------------------------------------------------------------------------------------------------
assign PB_in=1;
// assign estado_m=0;
Contador_Control_de_Tiempos f4 (
.reset(reset),
.clk(clk),
.PB_in(PB_in),
.enable_inicio(contro_listo),
.enable_escribir(contro_escribe),
.enable_leer(contro_lee),
.estado_m(estado_m),
.c_5(c_5)
);
Control_de_Tiempos f5 (
.enable_inicio(contro_listo),
.enable_escribir(contro_escribe),
.clk(clk),
.enable_leer(contro_lee),
.estado(c_5), //
.Estado_m(estado_m), //
.A_D(A_D),
.CS(CS),
.RD(RD),
.WR(WR),
.HI(HI),
.Dato_Dir(Dato_Dir),
.listo(listo),
.en_out(en_out)
);
Buffer_Triestado_Salida f7 (
.Deco_out(salida_bus),
.en(~HI),
.RTC_in(RTC_in)
);
MUX_SALIDA f6 (
.direccion(Dir),
.dato(Dato),
.seleccion(Dato_Dir),
.salida_bus(salida_bus)
);
//___________________________________________________________________________________
MainActivity f8 (
.estado(tecla),
.RG1_P(VGA_1),
.RG2_P(VGA_2),
.RG3_P(VGA_3),
.escribiendo(escribiendo),
.en_out(en_out),
.dig0(d_seg),
.dig1(u_seg),
.direccion(direccion),
.clk(clk),
.reset(reset),
.off_alarma(off_alarma), //
.on_alarma(on_alarma), //
.COLOUR_OUT(rgb),
.HS(hsync),
.VS(vsync),
.seg_Ti(seg_Ti),
.min_Ti(min_Ti),
.hor_Ti(hor_Ti)
);
//---------------------------------------------------------------------
Deteccion_Tecla f9 (
.clk(clk),
.reset(reset),
.ps2d(ps2d),
.ps2c(ps2c),
.reset_escritura(contro_escribe),
.Segundos_RTC(seg_Ti),
.Minutos_RTC(min_Ti),
.Horas_RTC(hor_Ti),
.Senal(tecla2),
.Senal_2_ren(escribiendo),
.Parametro(tecla),
.Salida_1(RG1),
.Salida_2(RG2),
.Salida_3(RG3),
.VGA_1(VGA_1),
.VGA_2(VGA_2),
.VGA_3(VGA_3),
.Flag_VGA(Flag_Alarma_VGA),
.Flag_Pico(tecla3),
.Salida_G (Salida_G)
);
always @(posedge clk)
begin
if (!seg_Ti && !min_Ti && !hor_Ti && tecla == 8'h75 && Salida_G == 8'h70)
Flag_Alarma_VGA_1 = 1;
else
Flag_Alarma_VGA_1 = 0;
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:ovld_reg:1.0
// IP Revision: 2
(* X_CORE_INFO = "ovld_reg,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_get_0_val_r_0,ovld_reg,{}" *)
(* CORE_GENERATION_INFO = "zc702_get_0_val_r_0,ovld_reg,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ovld_reg,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DATA_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_get_0_val_r_0 (
data_in,
vld_in,
ap_done,
clk,
data_out,
vld_out
);
input wire [31 : 0] data_in;
input wire vld_in;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done" *)
input wire ap_done;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
output wire [31 : 0] data_out;
output wire vld_out;
ovld_reg #(
.DATA_WIDTH(32)
) inst (
.data_in(data_in),
.vld_in(vld_in),
.ap_done(ap_done),
.clk(clk),
.data_out(data_out),
.vld_out(vld_out)
);
endmodule
|
`default_nettype none
`timescale 1ns/1ns
`define simulation
module tb_ptp();
wire clk, reset;
clock clock(clk, reset);
reg read = 0;
wire [31:0] readdata;
reg [31:0] data;
reg iobus_iob_poweron = 1;
reg iobus_iob_reset = 0;
reg iobus_datao_clear = 0;
reg iobus_datao_set = 0;
reg iobus_cono_clear = 0;
reg iobus_cono_set = 0;
reg iobus_iob_fm_datai = 0;
reg iobus_iob_fm_status = 0;
reg [3:9] iobus_ios = 0;
reg [0:35] iobus_iob_in = 0;
wire [1:7] iobus_pi_req;
wire [0:35] iobus_iob_out;
reg key_tape_feed = 0;
wire data_rq;
ptp ptp(.clk(clk), .reset(~reset),
.iobus_iob_poweron(iobus_iob_poweron),
.iobus_iob_reset(iobus_iob_reset),
.iobus_datao_clear(iobus_datao_clear),
.iobus_datao_set(iobus_datao_set),
.iobus_cono_clear(iobus_cono_clear),
.iobus_cono_set(iobus_cono_set),
.iobus_iob_fm_datai(iobus_iob_fm_datai),
.iobus_iob_fm_status(iobus_iob_fm_status),
.iobus_ios(iobus_ios),
.iobus_iob_in(iobus_iob_in),
.iobus_pi_req(iobus_pi_req),
.iobus_iob_out(iobus_iob_out),
.key_tape_feed(key_tape_feed),
.s_read(read),
.s_readdata(readdata),
.fe_data_rq(data_rq));
initial begin
$dumpfile("dump.vcd");
$dumpvars();
#100;
iobus_iob_reset <= 1;
#100;
iobus_iob_reset <= 0;
#100;
iobus_ios <= 7'b001_000_0;
#200;
key_tape_feed <= 1;
ptp.ptp_pia <= 1;
ptp.ptp_flag <= 0;
// ptp.ptp_busy <= 1;
ptp.ptp <= 'o123;
/*
#200;
ptp.ptp_busy <= 0;
#2200;
ptp.ptp_busy <= 1;
*/
end
initial begin: foo
integer i;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
read <= 1;
@(posedge clk);
data <= readdata;
read <= 0;
/*
@(posedge (|iobus_pi_req));
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
iobus_datao_clear <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
iobus_datao_clear <= 0;
iobus_datao_set <= 1;
iobus_iob_in <= 'o321;
@(posedge clk);
@(posedge clk);
@(posedge clk);
iobus_datao_set <= 0;
*/
@(posedge data_rq);
for(i = 0; i < 200; i = i+1) begin
@(posedge clk);
end
read <= 1;
@(posedge clk);
data <= readdata;
read <= 0;
/*
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o255;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o244;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o233;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o222;
@(posedge clk);
write <= 0;
@(posedge (|iobus_pi_req));
iobus_iob_fm_datai <= 1;
#400;
iobus_iob_fm_datai <= 0;
key_stop <= 1;
#20;
key_stop <= 0;
*/
end
initial begin
#50000;
$finish;
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "arrmul.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_arrmul();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
arrmul am (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'hff02030405060708f00a0b0cff0eff00;
r_B=128'hfe010202030303031004f505ff09fe10;
e_r=128'hfd020006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'hf502030405060708f00a0b0cff0eff00;
r_B=128'h0b010202030303031004f505ff09fe10;
e_r=128'h0a870006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'h1002030405060708f00a0b0cff0eff00;
r_B=128'hf0010202030303031004f505ff09fe10;
e_r=128'h0f000006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h00010202030303031004f505ff09fe10;
e_r=128'h00000006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200002, SQ = 450; int n, c, a[N], first[N]; long long sum[SQ]; bool solve() { int x = c; for (int i = x; i >= 1; --i) { i = min(i, x); if (!sum[i / SQ]) { i = i / SQ * SQ; continue; } if (sum[i / SQ] <= x) x -= sum[i / SQ], i = i / SQ * SQ; else x -= min(first[i], x / i) * i; if (!x) break; } return x > 0; } bool check(int i) { ++first[i]; sum[i / SQ] += i; bool fail = solve(); --first[i]; sum[i / SQ] -= i; return fail; } int main() { scanf( %d%d , &c, &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]), ++first[a[i]], sum[a[i] / SQ] += a[i]; for (int i = 1; i <= c; ++i) if (check(i)) return cout << i, 0; cout << Greed is good ; }
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table2_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#72
`assert(result, 7);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, fa, h[N]; vector<int> G[N], p, q; int main() { scanf( %d , &n); for (int i = (1); i <= (n - 1); ++i) scanf( %d , &fa), G[fa].push_back(i); function<void(int)> dfs = [&](int u) { for (int v : G[u]) dfs(v), h[u] = max(h[u], h[v] + 1); }; dfs(0); function<int(int, int)> solve = [&](int u, int nd) { sort(G[u].begin(), G[u].end(), [&](int x, int y) { return h[x] < h[y]; }); p.push_back(u); for (int i = (1); i <= (nd); ++i) q.push_back(u); nd = 0; for (int v : G[u]) nd = solve(v, nd); return nd + 1; }; solve(0, 0); for (int x : p) printf( %d , x); printf( n%d n , q.size()); for (int x : q) printf( %d , x); return 0; }
|
#include <bits/stdc++.h> int dp[200100]; int X[200100]; int Y[200100]; int T[200100]; int MX[200100]; int main(void) { int n, r; scanf( %d %d , &r, &n); for (int i = 1; i <= n; i++) dp[i] = MX[i] = -200100; MX[0] = X[0] = Y[0] = dp[0] = T[0] = 0; for (int i = 1; i <= n; i++) { scanf( %d %d %d , &T[i], &X[i], &Y[i]); X[i]--; Y[i]--; for (int j = i - 1; j >= 0; j--) { if (T[i] - T[j] > r * 2) { dp[i] = std::max(dp[i], MX[j] + 1); break; }; int xdiff = std::abs(X[i] - X[j]); int ydiff = std::abs(Y[i] - Y[j]); if (xdiff + ydiff <= T[i] - T[j]) { dp[i] = std::max(dp[i], dp[j] + 1); }; }; MX[i] = std::max(MX[i - 1], dp[i]); }; printf( %d n , MX[n]); return 0; };
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_PP_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_SYMBOL_V
`define SKY130_FD_SC_LP__OR4BB_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long arr[1000]; long long seg[1000005]; long long gcd(long long a, long long b) { if (b == 0) { return a; } return gcd(b, a % b); } void buildtree(long long start, long long end, long long treenode) { if (start == end) { seg[treenode] = arr[start]; return; } long long mid = (start + end) / 2; buildtree(start, mid, 2 * treenode); buildtree(mid + 1, end, 2 * treenode + 1); seg[treenode] = gcd(seg[2 * treenode], seg[2 * treenode + 1]); return; } long long query(long long left, long long right, long long start, long long end, long long treenode) { long long mid = (start + end) / 2; if (start > right || end < left) { return 0; } if (start >= left && end <= right) { return seg[treenode]; } long long ans = gcd(query(left, right, start, mid, 2 * treenode), query(left, right, mid + 1, end, 2 * treenode + 1)); return ans; } bool check(long long n, long long k) { long long num1 = n; long long sum1 = 0; long long sum2 = 0; while (n > 0) { if (n >= k) { n = n - k; sum1 += k; } else { sum1 += n; n = 0; break; } if (n < 10) { continue; } sum2 += n / 10; n = n - n / 10; } return sum1 >= sum2; } long long dp[101][101][101]; int solvedp(long long i, long long j, long long* pref, long long* suf, long long B, long long* arr) { if (i == j) { return 0; } if (B < 0) { return INT_MIN; } if (dp[i][j][B] != -1) { return dp[i][j][B]; } long long ans = 0; for (int k = i + 1; k < j - 1; k++) { if (i == 0) { if (!pref[k] && !suf[k + 1]) { ans = max((long long)1 + solvedp(k + 1, j, pref, suf, B - abs(arr[k + 1] - arr[k]), arr), ans); } } else { if (!(pref[k] - pref[i - 1]) && !suf[k + 1]) { ans = max((long long)1 + solvedp(k + 1, j, pref, suf, B - abs(arr[k + 1] - arr[k]), arr), ans); } } } dp[i][j][B] = ans; return dp[i][j][B]; } map<string, int> m1; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<int> a = {0, 4, 10, 20, 35, 56, 83, 116, 155, 198, 244, 292}; if (n < a.size()) cout << a[n]; else cout << a[11] + 49 * (n - 11); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> struct rge { T b, e; }; template <class T> rge<T> range(T i, T j) { return rge<T>{i, j}; } template <class T> auto dud(T *x) -> decltype(cerr << *x, 0); template <class T> char dud(...); struct debug { template <class T> debug &operator<<(const T &) { return *this; } }; const int N = 1e5 + 5; const int M = N; const int inf = 1e9 + 7; struct dsu { vector<int> pr; dsu(int n) : pr(n + 5) { iota(pr.begin(), pr.end(), 0); } int find(int u) { return pr[u] == u ? u : pr[u] = find(pr[u]); } void unite(int u, int v) { u = find(u), v = find(v); if (u != v) { pr[v] = u; debug() << the boss of << v : << (v) << is << u : << (u) << ; } } }; struct query { int t, u, v, doc; }; vector<int> graph[N]; int pr[N], dep[N], tot[N], heavy[N]; int head[N], pos[N], who[N]; set<pair<int, int> > st[N]; vector<query> queries; int indeg[N]; int timer = 0; int n, m; int dfs(int u) { tot[u] = 1, heavy[u] = head[u] = 0; for (int v : graph[u]) if (v != pr[u]) { pr[v] = u; dep[v] = dep[u] + 1; tot[u] += dfs(v); if (tot[v] > tot[heavy[u]]) heavy[u] = v; } return tot[u]; } void hld(int u, int h) { head[u] = h, pos[u] = ++timer, who[timer] = u; if (heavy[u] != 0) hld(heavy[u], h); for (int v : graph[u]) if (v != pr[u] && v != heavy[u]) hld(v, v); } template <class F> void process_path(int u, int v, F fun) { for (; head[u] != head[v]; v = pr[head[v]]) { if (dep[head[u]] > dep[head[v]]) swap(u, v); fun(pos[head[v]], pos[v]); } if (dep[u] > dep[v]) swap(u, v); if (u != v) fun(pos[heavy[u]], pos[v]); fun(pos[u], pos[u]); } void update_path(int u, int v, int doc) { debug() << sign from << u : << (u) << to << v : << (v) << << doc : << (doc) << ; process_path(u, v, [&](int l, int r) { st[doc].insert({l, r}); }); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; int doc = 0; for (auto i = (0) - ((0) > (m)); i != m - ((0) > (m)); i += 1 - 2 * ((0) > (m))) { query q; cin >> q.t >> q.u; if (q.t == 1) { cin >> q.v; swap(q.u, q.v); graph[q.u].push_back(q.v); indeg[q.v]++; } else if (q.t == 2) { q.doc = ++doc; st[doc].insert({-inf, -inf}); st[doc].insert({inf, inf}); } else if (q.t == 3) cin >> q.doc; queries.push_back(q); } for (auto u = (1) - ((1) > (n + 1)); u != n + 1 - ((1) > (n + 1)); u += 1 - 2 * ((1) > (n + 1))) if (indeg[u] == 0) { dfs(u); hld(u, u); } dsu boss(n); for (auto &q : queries) { if (q.t == 1) boss.unite(q.u, q.v); else if (q.t == 2) update_path(q.u, boss.find(q.u), q.doc); else { debug() << << st[q.doc] : << (st[q.doc]) << ; int k = pos[q.u]; auto it = --st[q.doc].upper_bound({k, inf}); debug() << << k : << (k) << << *it : << (*it) << ; for (auto jt : {prev(it), it, next(it)}) if (jt != st[q.doc].end()) if (jt->first <= k && k <= jt->second) { k = inf; break; } cout << (k == inf ? YES : NO ) << n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_4_V
`define SKY130_FD_SC_HDLL__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_4_V
|
#include <bits/stdc++.h> using namespace std; long long x[100002]; vector<int> P[2 * 100002]; void NoSol() { printf( No n ); exit(0); } long long sqr(int x) { return 1LL * x * x; } int bs(int x, long long val) { int i = -1, sz = P[x].size(), p = 1; while (p < sz) p <<= 1; while (p) { if (i + p < sz && sqr(P[x][i + p]) <= val) i += p; p >>= 1; } return i + 1; } int main() { int n; long long Xmax = 0; scanf( %d , &n); for (int i = 0; i < n / 2; ++i) { scanf( %lld , &x[i * 2 + 1]); Xmax = max(Xmax, x[i * 2 + 1]); if (x[i * 2 + 1] % 4 == 2) NoSol(); } long long s = 0; for (int a = 1; a < Xmax; ++a) for (int b = a + 1; sqr(b) - sqr(a) <= Xmax; ++b) P[sqr(b) - sqr(a)].push_back(a); long long sum = 0; for (int i = 0; i < n / 2; ++i) { long long X = x[i * 2 + 1]; if (P[X].empty()) NoSol(); if (sqr(P[X].back()) <= sum) NoSol(); x[i * 2] = sqr(P[X][bs(X, sum)]) - sum; sum = sum + x[i * 2] + X; } printf( Yes n ); s = 0; for (int i = 0; i < n; ++i) { printf( %lld , x[i]); s += x[i]; long long r = sqrt(s); if (r * r != s) while (1) ; } return 0; }
|
`include "tinker.vh"
module top
(
///////// OSC ////////
input OSC_50_B3B,
input OSC_50_B3D,
input OSC_50_B4A,
input OSC_50_B4D,
input OSC_50_B7A,
input OSC_50_B7D,
input OSC_50_B8A,
input OSC_50_B8D,
//////// PCIe //////////
input pcie_refclk,
input pcie_reset_n, // Reset to embedded PCIe
input pcie_rx_in0,
input pcie_rx_in1,
input pcie_rx_in2,
input pcie_rx_in3,
input pcie_rx_in4,
input pcie_rx_in5,
input pcie_rx_in6,
input pcie_rx_in7,
output pcie_tx_out0,
output pcie_tx_out1,
output pcie_tx_out2,
output pcie_tx_out3,
output pcie_tx_out4,
output pcie_tx_out5,
output pcie_tx_out6,
output pcie_tx_out7,
//////// DDR3 //////////
`ifdef ENABLE_DDR3_A
output ddr3_a_mem_reset_n,
output [14:0] ddr3_a_mem_a,
output [2:0] ddr3_a_mem_ba,
output ddr3_a_mem_cas_n,
output ddr3_a_mem_cke,
output ddr3_a_mem_ck,
output ddr3_a_mem_ck_n,
output ddr3_a_mem_cs_n,
output [7:0] ddr3_a_mem_dm,
inout [63:0] ddr3_a_mem_dq,
inout [7:0] ddr3_a_mem_dqs,
inout [7:0] ddr3_a_mem_dqs_n,
output ddr3_a_mem_odt,
output ddr3_a_mem_ras_n,
output ddr3_a_mem_we_n,
input ddr3_a_mem_oct_rzqin,
`endif
//////// DDR3 //////////
`ifdef ENABLE_DDR3_B
output ddr3_b_mem_reset_n,
output [14:0] ddr3_b_mem_a,
output [2:0] ddr3_b_mem_ba,
output ddr3_b_mem_cas_n,
output ddr3_b_mem_cke,
output ddr3_b_mem_ck,
output ddr3_b_mem_ck_n,
output ddr3_b_mem_cs_n,
output [7:0] ddr3_b_mem_dm,
inout [63:0] ddr3_b_mem_dq,
inout [7:0] ddr3_b_mem_dqs,
inout [7:0] ddr3_b_mem_dqs_n,
output ddr3_b_mem_odt,
output ddr3_b_mem_ras_n,
output ddr3_b_mem_we_n,
input ddr3_b_mem_oct_rzqin,
`endif
/////////QDRII_A/////////
`ifdef ENABLE_QDRII_A
output [19:0] qdrii_a_mem_a,
output [1:0] qdrii_a_mem_bws_n,
input qdrii_a_mem_cq_n,
input qdrii_a_mem_cq,
output [17:0] qdrii_a_mem_d,
output qdrii_a_mem_doff_n,
output qdrii_a_mem_k_n,
output qdrii_a_mem_k,
output qdrii_a_mem_odt,
input [17:0] qdrii_a_mem_q,
input qdrii_a_mem_qvld,
output qdrii_a_mem_rps_n,
output qdrii_a_mem_wps_n,
`endif
/////////QDRII_B/////////
`ifdef ENABLE_QDRII_B
output [19:0] qdrii_b_mem_a,
output [1:0] qdrii_b_mem_bws_n,
input qdrii_b_mem_cq_n,
input qdrii_b_mem_cq,
output [17:0] qdrii_b_mem_d,
output qdrii_b_mem_doff_n,
output qdrii_b_mem_k_n,
output qdrii_b_mem_k,
output qdrii_b_mem_odt,
input [17:0] qdrii_b_mem_q,
input qdrii_b_mem_qvld,
output qdrii_b_mem_rps_n,
output qdrii_b_mem_wps_n,
/// RZQ ///
input qdrii_b_mem_oct_rzqin,
`endif
/////////QDRII_C/////////
`ifdef ENABLE_QDRII_C
output [19:0] qdrii_c_mem_a,
output [1:0] qdrii_c_mem_bws_n,
input qdrii_c_mem_cq_n,
input qdrii_c_mem_cq,
output [17:0] qdrii_c_mem_d,
output qdrii_c_mem_doff_n,
output qdrii_c_mem_k_n,
output qdrii_c_mem_k,
output qdrii_c_mem_odt,
input [17:0] qdrii_c_mem_q,
input qdrii_c_mem_qvld,
output qdrii_c_mem_rps_n,
output qdrii_c_mem_wps_n,
`endif
/////////QDRII_D/////////
`ifdef ENABLE_QDRII_D
output [19:0] qdrii_d_mem_a,
output [1:0] qdrii_d_mem_bws_n,
input qdrii_d_mem_cq_n,
input qdrii_d_mem_cq,
output [17:0] qdrii_d_mem_d,
output qdrii_d_mem_doff_n,
output qdrii_d_mem_k_n,
output qdrii_d_mem_k,
output qdrii_d_mem_odt,
input [17:0] qdrii_d_mem_q,
input qdrii_d_mem_qvld,
output qdrii_d_mem_rps_n,
output qdrii_d_mem_wps_n,
`endif
//////// LED //////////
output [7:0] leds);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// REG/WIRE declarations
//=======================================================
wire resetn;
wire npor;
wire ddr3_a_pll_ref_clk;
wire ddr3_b_pll_ref_clk;
wire config_clk_clk;
wire kernel_pll_refclk_clk;
wire qdrii_b_pll_ref_clk;
wire qdrii_d_pll_ref_clk;
//=======================================================
// Board-specific
//=======================================================
assign ddr3_a_pll_ref_clk = OSC_50_B8A;
assign ddr3_b_pll_ref_clk = OSC_50_B7A;
assign config_clk_clk = OSC_50_B3B;
assign qdrii_b_pll_ref_clk = OSC_50_B4A;
assign qdrii_d_pll_ref_clk = OSC_50_B8D;
assign kernel_pll_refclk_clk = OSC_50_B3D;
//=======================================================
// Reset logic
//=======================================================
assign resetn = 1'b1;
//=======================================================
// System instantiation
//=======================================================
system system_inst
(
.*,
// Global signals
.global_reset_reset_n( resetn ), // No hard reset !!!
// PCIe pins
.pcie_npor_pin_perst(pcie_reset_n),
.pcie_npor_npor(1'b1),
.pcie_npor_out_reset_n(npor),
.pcie_refclk_clk( pcie_refclk ),
.reconfig_to_xcvr_reconfig_to_xcvr({10{24'h0, 2'b11, 44'h0}}),
.reconfig_from_xcvr_reconfig_from_xcvr());
assign leds[7:0] = 8'b0101000;
endmodule
|
//bram.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* This BRAM code was inspired by this website:
* http://www.dilloneng.com/documents/howto/ram_inference
*
*/
`timescale 1ps / 1ps
module bram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10,
parameter MEM_FILE = "NOTHING",
parameter MEM_FILE_LENGTH = -1
)(
input clk,
input rst,
input en,
input we,
input [(ADDR_WIDTH - 1):0] write_address,
input [(ADDR_WIDTH - 1):0] read_address,
input [(DATA_WIDTH - 1):0] data_in,
output reg [(DATA_WIDTH - 1):0] data_out
);
//synthesis attribute ram_style of mem is block
reg [(DATA_WIDTH - 1):0] mem [0:((1 << ADDR_WIDTH) - 1)]; //pragma attribute mem ram_block TRUE
reg [(ADDR_WIDTH - 1):0] read_address_reg;
initial begin
if (MEM_FILE != "NOTHING") begin
$display("Loading file...");
$readmemh(MEM_FILE, mem, 0, MEM_FILE_LENGTH - 1);
end
end
always @ (posedge clk) begin
if (rst) begin
data_out <= 0;
end
else begin
if (en) begin
read_address_reg <= read_address;
if (we) begin
mem[write_address] <= data_in;
end
data_out <= mem[read_address_reg];
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m, i, j, k; cin >> n >> m; int a[101] = {0}; for (i = 0; i < m; i++) { cin >> j; a[j]++; } vector<int> v; for (i = 1; i <= 100; i++) { if (a[i] != 0) v.push_back(a[i]); } sort(v.rbegin(), v.rend()); j = m / n; if (j == 0) cout << j; else { for (i = j; i >= 1; i--) { int x = 0; for (k = 0; k < v.size(); k++) { x += (v[k] / i); } if (x >= n) break; } cout << i; } }
|
// File: top_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 20 12:46:54 2018
`timescale 1ns/10ps
module top_TBV (
);
// myHDL -> Verilog Testbench for `top`
reg clk = 0;
wire [3:0] led;
wire [7:0] top0_0_pwm0_0_1_2_dutyCount;
reg [7:0] top0_0_pwm0_0_1_2_counter = 0;
wire [7:0] top0_0_pwm1_0_1_dutyCount;
reg [7:0] top0_0_pwm1_0_1_counter = 0;
wire [7:0] top0_0_pwm2_0_dutyCount;
reg [7:0] top0_0_pwm2_0_counter = 0;
wire [7:0] top0_0_pwm3_0_dutyCount;
reg [7:0] top0_0_pwm3_0_counter = 0;
reg top0_0_led_i [0:4-1];
initial begin: INITIALIZE_TOP0_0_LED_I
integer i;
for(i=0; i<4; i=i+1) begin
top0_0_led_i[i] = 0;
end
end
assign top0_0_pwm0_0_1_2_dutyCount = 8'd4;
assign top0_0_pwm1_0_1_dutyCount = 8'd16;
assign top0_0_pwm2_0_dutyCount = 8'd64;
assign top0_0_pwm3_0_dutyCount = 8'd255;
always @(led, clk) begin: TOP_TBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", led);
$write("\n");
end
always @(posedge clk) begin: TOP_TBV_TOP0_0_PWM0_0_1_2_LOGIC
top0_0_pwm0_0_1_2_counter <= (top0_0_pwm0_0_1_2_counter + 1);
top0_0_led_i[0] <= (top0_0_pwm0_0_1_2_counter < top0_0_pwm0_0_1_2_dutyCount);
end
always @(posedge clk) begin: TOP_TBV_TOP0_0_PWM1_0_1_LOGIC
top0_0_pwm1_0_1_counter <= (top0_0_pwm1_0_1_counter + 1);
top0_0_led_i[1] <= (top0_0_pwm1_0_1_counter < top0_0_pwm1_0_1_dutyCount);
end
always @(posedge clk) begin: TOP_TBV_TOP0_0_PWM2_0_LOGIC
top0_0_pwm2_0_counter <= (top0_0_pwm2_0_counter + 1);
top0_0_led_i[2] <= (top0_0_pwm2_0_counter < top0_0_pwm2_0_dutyCount);
end
always @(posedge clk) begin: TOP_TBV_TOP0_0_PWM3_0_LOGIC
top0_0_pwm3_0_counter <= (top0_0_pwm3_0_counter + 1);
top0_0_led_i[3] <= (top0_0_pwm3_0_counter < top0_0_pwm3_0_dutyCount);
end
assign led = {top0_0_led_i[3], top0_0_led_i[2], top0_0_led_i[1], top0_0_led_i[0]};
initial begin: TOP_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: TOP_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
if ((i == 1000)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long double l, v1, v2; long double a[100000]; long double p[100001]; vector<pair<long double, int> > events; int main() { cout << fixed << setprecision(12); cin >> n >> l >> v1 >> v2; long double dist = l * v2 / (v1 + v2); events.push_back(make_pair(0, 0)); events.push_back(make_pair(2 * l, 0)); for (int i = 0; i < n; ++i) { cin >> a[i]; events.push_back(make_pair(a[i] - dist, 1)); events.push_back(make_pair(a[i] + 2 * l - dist, 1)); events.push_back(make_pair(a[i], -1)); } sort(events.begin(), events.end()); memset(p, 0, sizeof p); int choc = 0, i = 0; while (events[i].second != 0) { choc += events[i].second; ++i; } ++i; while (events[i].second != 0) { p[choc] += events[i].first - events[i - 1].first; choc += events[i].second; ++i; } p[choc] += events[i].first - events[i - 1].first; for (int i = 0; i <= n; ++i) cout << (p[i] / 2 / l) << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_PP_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; vector<pair<int, int> > dp(n); dp[n - 1].second = 0; dp[n - 1].first = 1; int mx = 0; for (int i = n - 2; i > -1; i--) { if (a[i + 1] > a[i]) dp[i].second = dp[i + 1].second + 1; else dp[i].second = 0; if (a[i] < a[i + 1]) { dp[i].first = dp[i + 1].first + 1; } else dp[i].first = 1; if (i < n - 2 && a[i + 2] > a[i]) dp[i].second = max(dp[i].second, dp[i + 2].first + 1); mx = max(mx, dp[i].first); mx = max(mx, dp[i].second); } cout << mx; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; int x, y, i; if (b * c > a * d) { x = b * c - a * d; y = b * c; } else { x = a * d - b * c; y = a * d; } while (1) { int k = 0; for (i = 2; i <= x; i++) { if (x % i == 0 && y % i == 0) { x = x / i; y = y / i; k++; } } if (k == 0) break; } if (x == 0) cout << x << / << 1 ; else cout << x << / << y; return 0; }
|
/*
* CRC-16 Encoder/Decoder
*
* Calculation of 16-bit cyclic redundancy checks
*
* For more detailed information about CRC-16 for EPC Gen2, refer to annex F of the protocol
*/
`timescale 1us / 1ns
module crc16
(
output reg crc16_check_pass_reg,
output [15:0]crc_16,
input clk_crc16,
input rst_crc16,
input data,
input reply_data,
input sync,
input package_complete,
input en_crc16_for_rpy
);
wire d_in;
reg crc16_check_pass;
reg [15:0]reg_crc;
assign d_in = en_crc16_for_rpy? reply_data : data;
assign crc_16 = ~reg_crc;
always@(*) begin
if(reg_crc == 16'h1d0f) crc16_check_pass = 1'b1;
else crc16_check_pass = 1'b0;
end
always@(posedge clk_crc16 or negedge rst_crc16) begin
if(~rst_crc16) crc16_check_pass_reg <= 1'b0;
else if(package_complete) crc16_check_pass_reg <= crc16_check_pass;
end
always@(posedge clk_crc16 or negedge rst_crc16) begin
if(~rst_crc16) reg_crc <= 16'hffff;
else if(sync | en_crc16_for_rpy) begin
reg_crc[15] <= reg_crc[14];
reg_crc[14] <= reg_crc[13];
reg_crc[13] <= reg_crc[12];
reg_crc[12] <= reg_crc[11] ^ (d_in ^ reg_crc[15]);
reg_crc[11] <= reg_crc[10];
reg_crc[10] <= reg_crc[9];
reg_crc[9] <= reg_crc[8];
reg_crc[8] <= reg_crc[7];
reg_crc[7] <= reg_crc[6];
reg_crc[6] <= reg_crc[5];
reg_crc[5] <= reg_crc[4] ^ (d_in ^ reg_crc[15]);
reg_crc[4] <= reg_crc[3];
reg_crc[3] <= reg_crc[2];
reg_crc[2] <= reg_crc[1];
reg_crc[1] <= reg_crc[0];
reg_crc[0] <= d_in ^ reg_crc[15];
end
end
endmodule
|
module ula_test (
input reset,
input clk_sys, // master clock
output ce_vid,
// VRAM interfacing
output [14:0] vram_addr,
input [7:0] vram_dout,
output [7:0] port_ff,
// ULA+
input ulap_avail,
// Timex mode
input tmx_avail,
// Misc. signals
input mZX,
input m128,
input page_scr,
input [2:0] page_ram,
input [2:0] border_color,
// Video outputs
output reg HSync,
output reg VSync,
output reg HBlank,
output reg [2:0] Rx,
output reg [2:0] Gx,
output reg [2:0] Bx
);
assign ce_vid = ce_7mp;
reg ce_7mp, ce_7mn;
reg clk_7;
reg [2:0] clk_div;
always @(posedge clk_sys) begin
clk_div <= clk_div + 1'd1;
ce_7mp <= clk_div == 0;
ce_7mn <= clk_div == 4;
if (ce_7mp) clk_7 <= 1;
if (ce_7mn) clk_7 <= 0;
end
wire out_sel = 0; // 0 - sync, 1 - async model
assign HSync = out_sel ? HSync_async : HSync_sync;
assign VSync = out_sel ? VSync_async : VSync_sync;
assign Rx = out_sel ? Rx_async : Rx_sync;
assign Gx = out_sel ? Gx_async : Gx_sync;
assign Bx = out_sel ? Bx_async : Bx_sync;
assign vram_addr = out_sel ? {1'b0, vram_addr_async} : vram_addr_sync;
wire ce_cpu_sp, ce_cpu_sn;
wire [15:0] cpu_addr;
wire [7:0] cpu_din;
wire [7:0] cpu_dout;
wire nMREQ;
wire nIORQ;
wire nRFSH;
wire nRD;
wire nWR;
wire nINT;
/* verilator lint_off MULTIDRIVEN */
CPU CPU (
.reset(reset),
.clk_pos(clk_sys),
.clk_neg(clk_sys),
.ce_n(ce_cpu_sn),
.ce_p(ce_cpu_sp),
.cpu_addr(cpu_addr),
.cpu_din(cpu_din),
.cpu_dout(cpu_dout),
.nMREQ(nMREQ),
.nIORQ(nIORQ),
.nINT(nINT),
.nRD(nRD),
.nWR(nWR),
.nM1(),
.nRFSH()
);
/* verilator lint_on MULTIDRIVEN */
wire HSync_sync;
wire VSync_sync;
wire [2:0] Rx_sync;
wire [2:0] Gx_sync;
wire [2:0] Bx_sync;
wire [14:0] vram_addr_sync;
ULA ULA (
.reset(reset),
.clk_sys(clk_sys),
.ce_7mp(ce_7mp),
.ce_7mn(ce_7mn),
.ce_cpu_sp(ce_cpu_sp),
.ce_cpu_sn(ce_cpu_sn),
.addr(cpu_addr),
.din(cpu_din),
.nMREQ(nMREQ),
.nIORQ(nIORQ),
.nRFSH(nRFSH),
.nRD(nRD),
.nWR(nWR),
.nINT(nINT),
.nPortRD(),
.nPortWR(),
.vram_addr(vram_addr_sync),
.vram_dout(vram_dout),
.port_ff(port_ff),
.ulap_avail(ulap_avail),
.ulap_sel(),
.ulap_dout(),
.ulap_ena(),
.ulap_mono(),
.tmx_avail(tmx_avail),
.mode512(),
.snow_ena(1'b1),
.mZX(mZX),
.m128(m128),
.page_scr(page_scr),
.page_ram(page_ram),
.border_color(border_color),
.HSync(HSync_sync),
.VSync(VSync_sync),
.HBlank(HBlank),
.Rx(Rx_sync),
.Gx(Gx_sync),
.Bx(Bx_sync)
);
/* verilator lint_off MULTIDRIVEN */
/* verilator lint_off UNOPTFLAT */
wire cpuclk;
wire [15:0] cpu_addr_a;
wire [7:0] cpu_dout_a;
wire nMREQ_a, nIORQ_a, nRD_a, nWR_a;
CPU CPU_ASYNC (
.reset(reset),
.clk_pos(cpuclk & ~reset),
.clk_neg(~cpuclk & ~reset),
.ce_n(1),
.ce_p(1),
.cpu_addr(cpu_addr_a),
.cpu_din(cpu_din),
.cpu_dout(cpu_dout_a),
.nMREQ(nMREQ_a),
.nIORQ(nIORQ_a),
.nINT(nINT),
.nRD(nRD_a),
.nWR(nWR_a),
.nM1(),
.nRFSH()
);
wire HSync_async;
wire VSync_async;
wire [2:0] Rx_async;
wire [2:0] Gx_async;
wire [2:0] Bx_async;
wire [13:0] vram_addr_async;
/* verilator lint_on UNOPTFLAT */
/* verilator lint_on MULTIDRIVEN */
ULA_ASYNC ULA_ASYNC (
.reset(reset),
.clk_7(clk_7),
.cpuclk(cpuclk),
.addr(cpu_addr_a),
.din(cpu_din),
.nMREQ(nMREQ_a),
.nIORQ(nIORQ_a),
.nRD(nRD_a),
.nWR(nWR_a),
.nINT(),
.RAS_N(),
.CAS_N(),
.vram_addr(vram_addr_async),
.vram_dout(vram_dout),
.port_ff(),
.mZX(mZX),
.m128(m128),
.page_scr(page_scr),
.page_ram(page_ram),
.border_color(border_color),
.HSync(HSync_async),
.VSync(VSync_async),
.HBlank(),
.Rx(Rx_async),
.Gx(Gx_async),
.Bx(Bx_async)
);
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table3.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table3_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#90
`assert(result, 12);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 211; vector<pair<int, int> > con[maxn]; vector<pair<int, int> > edge; bool vis[maxn]; int n, w, tmx, tv, ans; void dfs(int x, int dis) { vis[x] = 1; if (dis > tmx) tmx = dis, tv = x; for (int i = 0; i < con[x].size(); i++) if (!vis[con[x][i].first] && w != con[x][i].second) dfs(con[x][i].first, dis + 1); } int go(int x) { memset(vis, 0, sizeof(vis)); tmx = tv = 0, dfs(x, 0); memset(vis, 0, sizeof(vis)); tmx = 0, dfs(tv, 0); return tmx; } int main() { scanf( %d , &n); int x, y; for (int i = 1; i < n; i++) { scanf( %d %d , &x, &y); con[x].push_back(make_pair(y, i)); con[y].push_back(make_pair(x, i)); edge.push_back(make_pair(x, y)); } for (w = 1; w < n; w++) ans = max(ans, go(edge[w - 1].first) * go(edge[w - 1].second)); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; using LL = long long; using DD = long double; using pii = pair<int, int>; const LL INFLL = 0x7f7f7f7f7f7f7f7fLL; const int INFint = 0x7f7f7f7f; LL exactMatchingSubranges(vector<int> &cumulative, int match) { LL rr = 0; for (int i = 0; i < int((int((cumulative).size()))); ++i) { int looking_for = match ^ cumulative[i]; int p = lower_bound((cumulative).begin(), (cumulative).end(), looking_for) - cumulative.begin(); int q = upper_bound((cumulative).begin(), (cumulative).end(), looking_for) - cumulative.begin(); rr += q - p; } return rr; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.precision(16); int n, k; cin >> n >> k; vector<int> aa(n, 0); for (int i = 0; i < int(n); ++i) cin >> aa[i]; vector<int> cumulative((int((aa).size())), 0); cumulative[0] = aa[0]; int amax = 0; for (int i = int(1); i < int((int((aa).size()))); ++i) { cumulative[i] = cumulative[i - 1] ^ aa[i]; amax = max(amax, aa[i]); } cumulative.push_back(0); sort((cumulative).begin(), (cumulative).end()); LL rr = exactMatchingSubranges(cumulative, k); while (true) { if ((k & 1) == 0) { k |= 1; rr += exactMatchingSubranges(cumulative, k); } k >>= 1; amax >>= 1; if (amax == 0) break; for (int i = 0; i < int((int((cumulative).size()))); ++i) cumulative[i] >>= 1; } cout << rr / 2 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, pos, l, r, ans = 0; cin >> n >> pos >> l >> r; if (abs(pos - l) > abs(pos - r)) { ans += abs(pos - r) + 1; if (n == r) ans -= abs(pos - r) + 1; n == r ? 0 : pos = r; ans += abs(pos - l) + 1; if (1 == l) ans -= abs(pos - l) + 1; } else { ans += abs(pos - l) + 1; if (1 == l) ans -= abs(pos - l) + 1; 1 == l ? 0 : pos = l; ans += abs(pos - r) + 1; if (n == r) ans -= abs(pos - r) + 1; } cout << ans << n ; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
input wire B,
output wire Y
);
parameter [0:0] INV_A = 1'b0;
endmodule
module top(
input wire [1:0] di,
output wire [5:0] do
);
wire [1:0] d;
\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
box b00 (.A(d[0]), .B( ), .Y(do[0]));
box b01 (.A(d[0]), .B( ), .Y(do[1]));
box b02 (.A( ), .B(d[0]), .Y(do[2]));
\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
box b10 (.A(d[1]), .B( ), .Y(do[3]));
box b11 (.A(d[1]), .B( ), .Y(do[4]));
box b12 (.A(d[1]), .B( ), .Y(do[5]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_1_V
`define SKY130_FD_SC_LS__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_1_V
|
#include <bits/stdc++.h> using namespace std; int n, k, p[111], c[111], l[111], bottleneck[111], par[111], cost[111][111]; bitset<200005> prime; vector<vector<int> > vert; int edmondskarp(int s, int t) { int mf = 0; while (1) { memset(bottleneck, 0, sizeof(bottleneck)); bottleneck[s] = 1e9; par[s] = s; queue<int> q; q.push(s); while (!q.empty() && !bottleneck[t]) { int u = q.front(); q.pop(); for (int i = 0; i < vert[u].size(); i++) { int v = vert[u][i]; if (cost[u][v] > 0 && !bottleneck[v]) { q.push(v); par[v] = u; bottleneck[v] = min(bottleneck[u], cost[u][v]); } } } if (!bottleneck[t]) break; mf += bottleneck[t]; for (int u = t; par[u] != u; u = par[u]) { cost[par[u]][u] -= bottleneck[t]; cost[u][par[u]] += bottleneck[t]; } } return mf; } int ok(int x) { int idx = 0; p[0] = -1; for (int i = 1; i <= n; i++) { if (c[i] == 1 && l[i] <= x && p[i] > p[idx]) { idx = i; } } vert.assign(111, vector<int>()); memset(cost, 0, sizeof(cost)); for (int i = 1; i <= n; i++) { if (l[i] > x) continue; if (c[i] & 1) continue; if (c[i] == 1) continue; for (int j = 1; j <= n; j++) { if (l[j] > x) continue; if (i == j) continue; if (c[j] == 1) continue; if (prime[c[i] + c[j]]) { vert[i].push_back(j); vert[j].push_back(i); cost[i][j] = 1e9; } } } int s = 101, t = 102; for (int i = 1; i <= n; i++) { if (l[i] > x) continue; if (c[i] & 1) continue; if (c[i] == 1) continue; vert[s].push_back(i); vert[i].push_back(s); cost[s][i] = p[i]; } for (int i = 1; i <= n; i++) { if (l[i] > x) continue; if (!(c[i] & 1)) continue; if (c[i] == 1) continue; vert[i].push_back(t); vert[t].push_back(i); cost[i][t] = p[i]; } if (idx) { vert[idx].push_back(t); vert[t].push_back(idx); cost[idx][t] = p[idx]; for (int i = 1; i <= n; i++) { if (l[i] > x) continue; if (c[i] & 1) continue; if (!prime[1 + c[i]]) continue; vert[i].push_back(idx); vert[idx].push_back(i); cost[i][idx] = 1e9; } } int sum = 0; for (int i = 1; i <= n; i++) { if (l[i] > x || c[i] == 1) continue; sum += p[i]; } if (idx) sum += p[idx]; int ek = edmondskarp(s, t); return sum - ek >= k; } int main() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d%d%d , &p[i], &c[i], &l[i]); } prime.set(); prime[0] = prime[1] = 0; for (long long i = 2; i <= 200000; i++) { if (prime[i]) { for (long long j = i * i; j <= 200000; j += i) { prime[j] = 0; } } } if (!ok(n)) { printf( %d n , -1); return 0; } int lo = 0, hi = n; while (hi - lo > 1) { int m = (lo + hi) / 2; if (ok(m)) hi = m; else lo = m; } printf( %d n , hi); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int MOD2 = 1007681537; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> inline int chkmin(T& a, const T& val) { return val < a ? a = val, 1 : 0; } template <class T> inline int chkmax(T& a, const T& val) { return a < val ? a = val, 1 : 0; } inline long long isqrt(long long k) { long long r = sqrt(k) + 1; while (r * r > k) r--; return r; } inline long long icbrt(long long k) { long long r = cbrt(k) + 1; while (r * r * r > k) r--; return r; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } inline int sign(long double x) { return x < -EPS ? -1 : x > +EPS; } inline int sign(long double x, long double y) { return sign(x - y); } long long ff(long long n, long long k) { return min(k + k, k + (n - k) * (n - k - 1) / 2); } void solve() { int test; cin >> test; while (test--) { long long n; cin >> n; if (n <= 4) { cout << n - 1 << n ; continue; } long long lo = 1, hi = n - 3; while (lo < hi) { long long mi = lo + hi >> 1; if (ff(n, mi) > ff(n, mi + 1)) { hi = mi; } else { lo = mi + 1; } } cout << max(n - 1, ff(n, lo + hi >> 1)) << n ; } } int main() { int JUDGE_ONLINE = 1; if (fopen( in.txt , r )) { JUDGE_ONLINE = 0; assert(freopen( in.txt , r , stdin)); } else { ios_base::sync_with_stdio(0), cin.tie(0); } solve(); if (!JUDGE_ONLINE) { } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int x[maxn], y[maxn]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> x[i]; } for (int i = 1; i <= m; i++) { cin >> y[i]; } int u = 0, d = 0, ans = 0; int sumu = 0, sumd = 0; while (u <= n && d <= m) { if (sumu && sumu == sumd) { ans++; sumd = y[++d]; sumu = x[++u]; } else if (sumu > sumd) { sumd += y[++d]; } else if (sumu <= sumd) { sumu += x[++u]; } } cout << ans << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconcat_0_0/RAT_xlconcat_0_0_stub.v
// Design : RAT_xlconcat_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlconcat,Vivado 2016.4" *)
module RAT_xlconcat_0_0(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[7:0],In1[1:0],dout[9:0]" */;
input [7:0]In0;
input [1:0]In1;
output [9:0]dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long L, v, l, r; cin >> L >> v >> l >> r; long long tot = L / v; long long minus = r / v; minus -= (l - 1) / v; cout << tot - minus << n ; } return 0; }
|
#include <bits/stdc++.h> int x[100010]; int main() { int a, b, c, i; scanf( %d%d%d , &a, &b, &c); for (i = 1; i <= a; i++) scanf( %d , &x[i]); int s = 0, t = 1; long long int count = 0; while (1) { if (t > a && s == 0) { printf( %I64d , count); return 0; } while (t <= a && s + x[t] <= b) s += x[t], t++; if (s < c) { count++; s = 0; } else { count += (s / c); s = s % c; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans; long long sum = 0; map<long long, int> d; cin >> n; ans = n - 1; for (int i = 0; i < n; i++) { int t; cin >> t; sum += t; d[sum]++; ans = min(ans, n - d[sum]); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(int test) { int x; cin >> x; int no = x % 10; int cnt = 0; while (x) { cnt++; x /= 10; } int ans = (no - 1) * 10; while (cnt) { ans += cnt; cnt--; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout << setprecision(20); long long int t = 1, k; cin >> t; k = t; while (t--) { solve(k - t); } cerr << Timpe elapsed : << clock() * 1000.0 / CLOCKS_PER_SEC << mps n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 201110, M = 501110; int n, m, numeven, numodd; int a[N]; stack<int> odd, even; map<int, int> mp; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); mp[a[i]]++; if (a[i] % 2 == 0) numeven++; else numodd++; } for (int i = 1; i <= min(M, m); i++) { if (i % 2 == 0 && mp[i] == 0) even.push(i); if (i % 2 == 1 && mp[i] == 0) odd.push(i); } int ans = 0; for (int i = 1; i <= n; i++) if (mp[a[i]] > 1) { if (a[i] % 2 == 0) numeven--; else numodd--; mp[a[i]]--; if (numeven > numodd) { ans++; if (odd.size() == 0) { cout << -1 << endl; return 0; } a[i] = odd.top(); odd.pop(); numodd++; } else { ans++; if (even.size() == 0) { cout << -1 << endl; return 0; } a[i] = even.top(); even.pop(); numeven++; } } for (int i = 1; i <= n; i++) { if (numeven > numodd && a[i] % 2 == 0) { ans++; if (odd.size() == 0) { cout << -1 << endl; return 0; } a[i] = odd.top(); odd.pop(); numeven--; numodd++; } if (numeven < numodd && a[i] % 2 == 1) { ans++; if (even.size() == 0) { cout << -1 << endl; return 0; } a[i] = even.top(); even.pop(); numeven++; numodd--; } } printf( %d n , ans); for (int i = 1; i <= n; i++) printf( %d , a[i]); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { long long int n; scanf( %lld , &n); printf( %lld n , n); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:17:23 10/24/2016
// Module Name: ALU_MUX_tb
// Project Name: MIPS
// Description: Testing MIPS 2-to-1 32-bit MUX implementation in verilog.
//
// Dependencies: ALU_MUX.v
//
////////////////////////////////////////////////////////////////////////////////
module ALU_MUX_tb;
// Declare inputs.
reg [31:0] A, B;
reg sel;
// Declare outputs.
wire [31:0] Y;
// Instantiate the MUX module.
ALU_MUX mux(.a(A), .b(B), .sel(sel), .y(Y));
initial begin
// Initialize inputs.
A = 0;
B = 0;
sel = 0;
// Provide test values.
A = 32'hAAAAAAAA;
B = 32'h55555555;
sel = 1'b1;
#10;
A = 32'h00000000;
#10;
sel = 1'b1;
#10;
B = 32'hFFFFFFFF;
#5;
A = 32'hA5A5A5A5;
#5;
sel = 1'b0;
B = 32'hDDDDDDDD;
#5;
sel = 1'bx;
// Terminate.
$finish;
end
// Whenever a change occurs to A, B or sel, display information.
always @ (A or B or sel)
#1 $display("At t = %0d sel %b A = %h B = %h Y = %h",
$time, sel, A, B, Y);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { long long n, s, t; cin >> n >> s >> t; cout << max(n - s + 1, n - t + 1) << n ; } return 0; }
|
/*******************************************************************************
Vendor: Xilinx
Associated Filename: realfft_rtl_tb.v
Purpose: Part of a Vivado HLS tutorial example
Device: All
Revision History: March 31, 2013 - initial release
*******************************************************************************
Copyright (C) 2013 XILINX, Inc.
This file contains confidential and proprietary information of Xilinx, Inc. and
is protected under U.S. and international copyright and other intellectual
property laws.
DISCLAIMER
This disclaimer is not a license and does not grant any rights to the materials
distributed herewith. Except as otherwise provided in a valid license issued to
you by Xilinx, and to the maximum extent permitted by applicable law:
(1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX
HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature related to, arising under
or in connection with these materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage (including loss of data,
profits, goodwill, or any type of loss or damage suffered as a result of any
action brought by a third party) even if such damage or loss was reasonably
foreseeable or Xilinx had been advised of the possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-safe, or for use in any
application requiring fail-safe performance, such as life-support or safety
devices or systems, Class III medical devices, nuclear facilities, applications
related to the deployment of airbags, or any other applications that could lead
to death, personal injury, or severe property or environmental damage
(individually and collectively, "Critical Applications"). Customer asresultes the
sole risk and liability of any use of Xilinx products in Critical Applications,
subject only to applicable laws and regulations governing limitations on product
liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT
ALL TIMES.
*******************************************************************************/
`timescale 1 ns / 1 ps
`define EOF 32'hFFFF_FFFF
`define NULL 0
`define MAX_LINE_LENGTH 1000
module realfft_rtl_tb ();
reg aclk = 1'b0;
reg aresetn = 1'b1;
reg [15:0]real2xfft_din_tdata;
wire real2xfft_din_tready;
reg real2xfft_din_tvalid;
wire [31:0]xfft2real_dout_tdata;
reg xfft2real_dout_tready;
wire xfft2real_dout_tvalid;
//RealFFT_wrapper dut0 (
RealFFT_wrapper dut0 (
.aclk(aclk),
.aresetn(aresetn),
.real2xfft_din_tdata(real2xfft_din_tdata),
.real2xfft_din_tready(real2xfft_din_tready),
.real2xfft_din_tvalid(real2xfft_din_tvalid),
.xfft2real_dout_tdata(xfft2real_dout_tdata),
.xfft2real_dout_tready(xfft2real_dout_tready),
.xfft2real_dout_tvalid(xfft2real_dout_tvalid)
);
// Clock generator
always #5 aclk = ~aclk;
// Reset generator
initial begin
#10
@(posedge aclk)
aresetn = 1'b0;
#100
@(posedge aclk)
aresetn = 1'b1;
end
// real2fft stimulus process
initial begin : tvin_block
integer tvin_fd, c, r, i;
reg [8*`MAX_LINE_LENGTH:0] line; /* Line of text read from file */
reg [31:0] num_sent;
tvin_fd = $fopen("../../../../verilog_tb/realfft_fe_tvin.dat", "r");
if (tvin_fd == `NULL) begin// If error opening file
$display("Could not open input test vector file. Bailing out...");
disable tvin_block; // Just quit
end
// Wait for areset to assert and de-assert
wait(aresetn == 1'b0) @(posedge aclk);
num_sent = 0;
real2xfft_din_tdata = 32'hDEADBEEF;
real2xfft_din_tvalid = 1'b0;
wait(aresetn == 1'b1) @(posedge aclk);
#20
@(negedge aclk)
// Read entire input TV file
c = $fgetc(tvin_fd);
while (c != `EOF) begin
/* Check the first character for comment */
if (c == "/")
r = $fgets(line, tvin_fd);
else begin
// Push the character back to the tvin_fd then read the next TV
r = $ungetc(c, tvin_fd);
r = $fscanf(tvin_fd," %h\n", real2xfft_din_tdata);
real2xfft_din_tvalid = 1'b1;
// Hold AXIS output signals until TREADY is asserted
wait(real2xfft_din_tready == 1'b1) @(negedge aclk)
num_sent = num_sent + 1;
end // if c else
c = $fgetc(tvin_fd);
end // while not EOF
// Flush the FFT pipeline
for (i = 0; i < 1024; i = i + 1) begin
real2xfft_din_tdata = 32'h0000_0000;
real2xfft_din_tvalid = 1'b1;
// Hold AXIS output signals until TREADY is asserted
wait(real2xfft_din_tready == 1'b1) @(negedge aclk)
num_sent = num_sent + 1;
end
real2xfft_din_tdata = 32'hCAFEDECA;
real2xfft_din_tvalid = 1'b0;
$fclose(tvin_fd);
end // initial
// xfft2real response process
initial begin : tvout_block
integer tvout_fd, c, r;
reg [8*`MAX_LINE_LENGTH:0] line; /* Line of text read from file */
reg [31:0] tvout_expected;
reg [31:0] num_rx;
integer err_cnt;
tvout_fd = $fopen("../../../../verilog_tb/realfft_be_tvout.dat", "r");
if (tvout_fd == `NULL) begin // If error opening file
$display("Could not open output test vector file. Bailing out...");
disable tvout_block; // Just quit
end
// Wait for areset to assert and de-assert
wait(aresetn == 1'b0) @(posedge aclk);
err_cnt = 0;
num_rx = 0;
xfft2real_dout_tready = 1'b0;
wait(aresetn == 1'b1) @(posedge aclk);
#20
@(negedge aclk)
// Set TREADY - never de-asserted until all responses received
xfft2real_dout_tready = 1'b1;
// Read entire output TV file and compare against golden data
c = $fgetc(tvout_fd);
while (c != `EOF) begin
/* Check the first character for comment */
if (c == "/")
r = $fgets(line, tvout_fd);
else begin
// Push the character back to the tvout_fd then read the next TV
r = $ungetc(c, tvout_fd);
r = $fscanf(tvout_fd," %h\n", tvout_expected);
@(negedge aclk)
// Wait for TVALID
while(xfft2real_dout_tvalid == 1'b0) begin
@(negedge aclk);
end
// TODO: Check tvout_val against expected data accounting for
// precision losses...
$display("%d - Expected: 0x%8h; Got: 0x%8h", num_rx[8:0], tvout_expected, xfft2real_dout_tdata);
$display("Expect differences of less than 2-3 bits due to rounding");
num_rx = num_rx + 1;
end // if c else
c = $fgetc(tvout_fd);
end // while not EOF
//xfft2real_dout_tready = 1'b0;
#200
$fclose(tvout_fd);
$finish;
end // initial
endmodule
|
#include <bits/stdc++.h> using namespace std; int on[10001]; int main() { std::ios::sync_with_stdio(false); cin.tie(0); int n, t, r, ans = 0; cin >> n >> t >> r; for (int i = 0; i < n; ++i) { int w; cin >> w; w += 400; int cnt = 0; for (int j = w; j > w - t; --j) { if (on[j]) { ++cnt; } } int todo = max(r - cnt, 0); for (int j = w; j > w - t; --j) { if (!on[j] and todo > 0) { on[j] = 1; todo -= 1; ++ans; } } if (todo > 0) { cout << -1; return 0; } } cout << ans; }
|
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