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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 9; int a[N], n; double ans(double x) { double arr[N]; for (int i = 0; i < n; i++) arr[i] = a[i] - x; double neg = 0; double pos = 0; double ans = 0; for (int i = 0; i < n; i++) { if (neg > 0) neg = 0; if (pos < 0) pos = 0; neg += arr[i]; pos += arr[i]; ans = max(ans, max(-neg, pos)); } return ans; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; double l = -1e5 - 9, r = 1e5 + 9; for (int i = 0; i < 100; i++) { double m1 = l + (r - l) / 3, m2 = r - (r - l) / 3; if (ans(m1) > ans(m2)) l = m1; else r = m2; } cout << setprecision(12) << fixed << ans(l) << endl; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
txnrx,
enable,
gpio_muxout_tx,
gpio_muxout_rx,
gpio_resetb,
gpio_sync,
gpio_en_agc,
gpio_ctl,
gpio_status,
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_udc_csn_tx,
spi_udc_csn_rx,
spi_udc_sclk,
spi_udc_data);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [15:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output txnrx;
output enable;
inout gpio_muxout_tx;
inout gpio_muxout_rx;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
inout [ 3:0] gpio_ctl;
inout [ 7:0] gpio_status;
output spi_csn;
output spi_clk;
output spi_mosi;
input spi_miso;
output spi_udc_csn_tx;
output spi_udc_csn_rx;
output spi_udc_sclk;
output spi_udc_data;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire spi_udc_csn_tx;
wire spi_udc_csn_rx;
wire spi_udc_sclk;
wire spi_udc_data;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(31)) i_iobuf (
.dio_t ({gpio_t[50:32],gpio_t[15:12], gpio_t[3:0]}),
.dio_i ({gpio_o[50:32],gpio_o[15:12], gpio_o[3:0]}),
.dio_o ({gpio_i[50:32],gpio_i[15:12], gpio_i[3:0]}),
.dio_p ({ gpio_muxout_tx,
gpio_muxout_rx,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
gpio_ctl,
gpio_status,
gpio_bd[15:12],
gpio_bd[3:0]}));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.rx_clk_in_n (rx_clk_in_n),
.rx_clk_in_p (rx_clk_in_p),
.rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p),
.spdif (spdif),
.spi0_csn_i (1'b1),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o(),
.spi0_csn_2_o(),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.spi1_clk_i (1'b0),
.spi1_clk_o (spi_udc_sclk),
.spi1_csn_i (1'b1),
.spi1_csn_0_o (spi_udc_csn_tx),
.spi1_csn_1_o (spi_udc_csn_rx),
.spi1_csn_2_o(),
.spi1_sdo_i (spi_udc_data),
.spi1_sdo_o (spi_udc_data),
.spi1_sdi_i (1'b0),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// annotshy #include <bits/stdc++.h> #define Task CF #define pb push_back #define MOD 1000000007 #define F first #define S second #define int long long using namespace std; const int maxn = 2005; int n, m, w; int a[maxn][maxn]; int dx[5] = {1, 0, -1, 0}; int dy[5] = {0, 1, 0, -1}; long long dp[maxn][maxn], to1 = 0, to2 = 0; long long BFS(int i, int j) { queue<pair<int, int> > Q; Q.push({i, j}); for(int p = 1; p <= n; ++ p) { for(int q = 1; q <= m; ++ q) dp[p][q] = 1e18; } dp[i][j] = 0; while(Q.size()) { int u = Q.front().F; int v = Q.front().S; Q.pop(); for(int k = 0; k < 4; ++ k) { int x = u + dx[k]; int y = v + dy[k]; if(x < 1 || y < 1 || x > n || y > m || a[x][y] == -1) continue; if(dp[x][y] > dp[u][v] + w) { dp[x][y] = dp[u][v] + w; Q.push({x, y}); } } } long long res = 1e18; if(i == 1 && j == 1) to1 = dp[n][m]; if(i == n && j == m) to2 = dp[1][1]; for(int i = 1; i <= n; ++ i) { for(int j = 1; j <= m; ++ j) if(a[i][j] > 0) { res = min(res, dp[i][j] + a[i][j]); } } return res; } void Solve() { cin >> n >> m >> w; for(int i = 1; i <= n; ++ i) { for(int j = 1; j <= m; ++ j) cin >> a[i][j]; } long long res1 = BFS(1, 1); long long res2 = BFS(n, m); if(res1 + res2 >= 1e18 && to1 == 1e18 && to2 == 1e18) cout << - 1 << n ; else cout << min({to1, to2, res1 + res2}) << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); if(fopen(Task .inp , r )) { freopen(Task .inp , r , stdin); freopen(Task .out , w , stdout); } int test = 1; // cin >> test; while(test --) { Solve(); } }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
module interrupt_controller
(
input wire iClock,
input wire iReset,
input wire iMcuWe,
input wire [3:0] iMcuRegSelect, //control register select comes from cpu
input wire [7:0] iMcuWriteData, //what does the cpu want to write
output wire[7:0] oInterruptEnableRegister,
output wire[7:0] oInterruptFlag,
input wire [7:0] iInterruptRequest,
output reg [7:0] oInterruptResquestPending
);
////////////////////////////////////////////////
//
// Register 0xFFFF: IE. Interrupt Enable register
// reset to 0 whenever written to
//
// Bit 0: V-Blank Interrupt Enable (INT 40h) (1=Enable)
// Bit 1: LCD STAT Interrupt Enable (INT 48h) (1=Enable)
// Bit 2: Timer Interrupt Enable (INT 50h) (1=Enable)
// Bit 3: Serial Interrupt Enable (INT 58h) (1=Enable)
// Bit 4: Joypad Interrupt Enable (INT 60h) (1=Enable)
////////////////////////////////////////////////
wire wWeInterrutpRegister;
assign wWeInterrutpRegister = (iMcuWe & iMcuRegSelect == 4'h0) ? 1'b1 : 1'b0;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FF_IE(
iClock, iReset , wWeInterrutpRegister , iMcuWriteData, oInterruptEnableRegister );
////////////////////////////////////////////////
//
// Register 0xFF0F: IF. Interrupt Flag
// Bit 0: V-Blank Interrupt Request (INT 40h) (1=Request)
// Bit 1: LCD STAT Interrupt Request (INT 48h) (1=Request)
// Bit 2: Timer Interrupt Request (INT 50h) (1=Request)
// Bit 3: Serial Interrupt Request (INT 58h) (1=Request)
// Bit 4: Joypad Interrupt Request (INT 60h) (1=Request)
////////////////////////////////////////////////
wire wWeInterruptFlag;
assign wWeInterruptFlag = (iMcuWe & iMcuRegSelect == 4'hf) ? 1'b1: 1'b0;
FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( 8 )FF_IF(
iClock, iReset | wWeInterruptFlag , |iInterruptRequest , iMcuWriteData, iInterruptRequest, oInterruptFlag );
wire [7:0] wPendingInterrupts;
assign wPendingInterrupts = oInterruptFlag & oInterruptEnableRegister;
always @ (*)
begin
case (wPendingInterrupts)
8'h1: oInterruptResquestPending = 8'b00000001; //VBLANK
8'h2: oInterruptResquestPending = 8'b00000010; //LCDSTAT
8'h4: oInterruptResquestPending = 8'b00000100; //TIMER
8'h8: oInterruptResquestPending = 8'b00001000; //SERIAL
8'h10: oInterruptResquestPending = 8'b00010000; //JOYPAD
default: oInterruptResquestPending = 8'b0;
endcase
end
endmodule
|
/**
* bsg_wormhole_router_adapter_out.v
*
* packet = {payload, length, cord}
*/
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_wormhole_router_adapter_out
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_link_sif_width(flit_width_p)
, localparam bsg_wormhole_packet_width_lp =
`bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
)
(input clk_i
, input reset_i
, input [bsg_ready_and_link_sif_width_lp-1:0] link_i
, output [bsg_ready_and_link_sif_width_lp-1:0] link_o
, output [bsg_wormhole_packet_width_lp-1:0] packet_o
, output v_o
, input yumi_i
);
// Casting ports
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_cast_i, link_cast_o;
assign link_cast_i = link_i;
assign link_o = link_cast_o;
`declare_bsg_wormhole_router_header_s(cord_width_p, len_width_p, bsg_wormhole_header_s);
bsg_wormhole_header_s header_li;
assign header_li = link_cast_i.data;
`declare_bsg_wormhole_router_packet_s(cord_width_p,len_width_p,max_payload_width_p,bsg_wormhole_packet_s);
localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p);
localparam protocol_len_lp = `BSG_SAFE_CLOG2(max_num_flits_lp);
logic [max_num_flits_lp*flit_width_p-1:0] packet_padded_lo;
bsg_serial_in_parallel_out_dynamic
#(.width_p(flit_width_p)
,.max_els_p(max_num_flits_lp)
)
sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_cast_i.data)
,.len_i(protocol_len_lp'(header_li.len))
,.ready_o(link_cast_o.ready_and_rev)
,.len_ready_o(/* unused */)
,.v_i(link_cast_i.v)
,.v_o(v_o)
,.data_o(packet_padded_lo)
,.yumi_i(yumi_i)
);
assign packet_o = packet_padded_lo[0+:bsg_wormhole_packet_width_lp];
// Stub the output data dna valid, since this is an output
assign link_cast_o.data = '0;
assign link_cast_o.v = '0;
`ifndef SYNTHESIS
logic recv_r;
bsg_dff_reset_en
#(.width_p(1))
recv_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(link_cast_i.v || yumi_i)
,.data_i(link_cast_i.v)
,.data_o(recv_r)
);
wire new_header_li = ~recv_r & link_cast_i.v;
// TODO: This assertion is buggy and fires erroneously
//always_ff @(negedge clk_i)
// assert(reset_i || ~new_header_li || (header_li.len <= max_num_flits_lp))
// else
// $error("Header received with len: %x > max_num_flits: %x", header_li.len, max_num_flits_lp);
`endif
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_router_adapter_out)
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long m = 0, a = 1, b = 1, ans = 0; while (m <= n) { m = a + b; a = b; b = m; ans++; } cout << ans - 1; return 0; }
|
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
assign sys_clk_ibufg = sys_clk;
/*
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
end
endgenerate
*/
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2e5 + 7; int N, M, head[maxN], cnt; struct Eddge { int nex, to, id; Eddge(int a = -1, int b = 0, int c = 0) : nex(a), to(b), id(c) {} } edge[maxN << 1]; inline void addEddge(int u, int v, int id) { edge[cnt] = Eddge(head[u], v, id); head[u] = cnt++; } inline void _add(int u, int v, int id) { addEddge(u, v, id); addEddge(v, u, id); } inline void init() { cnt = 0; for (int i = 1; i <= N; i++) head[i] = -1; } struct node { int u, v, op; node(int a = 0, int b = 0, int c = -1) : u(a), v(b), op(c) {} } t[maxN]; struct Point { int id, op; Point(int a = 0, int b = 0) : id(a), op(b) {} }; queue<Point> Q; bool bfs() { t[1].op = 1; Q.push(Point(t[1].u, 1)); while (!Q.empty()) { Point now = Q.front(); Q.pop(); int u = now.id; for (int i = head[u], v, id; ~i; i = edge[i].nex) { id = edge[i].id; if (~t[id].op) { if (t[id].u == u) { if (t[id].op == 0 && now.op == 1) return false; if (t[id].op == 1 && now.op == -1) return false; } else { if (t[id].op == 0 && now.op == -1) return false; if (t[id].op == 1 && now.op == 1) return false; } continue; } v = edge[i].to; if (now.op == 1) { Q.push(Point(v, -1)); if (t[id].u == u) t[id].op = 1; else t[id].op = 0; } else { Q.push(Point(v, 1)); if (t[id].u == u) t[id].op = 0; else t[id].op = 1; } } } Q.push(Point(t[1].v, -1)); while (!Q.empty()) { Point now = Q.front(); Q.pop(); int u = now.id; for (int i = head[u], v, id; ~i; i = edge[i].nex) { id = edge[i].id; if (~t[id].op) { if (t[id].u == u) { if (t[id].op == 0 && now.op == 1) return false; if (t[id].op == 1 && now.op == -1) return false; } else { if (t[id].op == 0 && now.op == -1) return false; if (t[id].op == 1 && now.op == 1) return false; } continue; } v = edge[i].to; if (now.op == 1) { Q.push(Point(v, -1)); if (t[id].u == u) t[id].op = 1; else t[id].op = 0; } else { Q.push(Point(v, 1)); if (t[id].u == u) t[id].op = 0; else t[id].op = 1; } } } return true; } int main() { scanf( %d%d , &N, &M); init(); for (int i = 1, u, v; i <= M; i++) { scanf( %d%d , &u, &v); t[i] = node(u, v, -1); _add(u, v, i); } if (bfs()) { printf( YES n ); for (int i = 1; i <= M; i++) printf( %d , t[i].op); printf( n ); } else printf( NO n ); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Driss Hafdi.
// SPDX-License-Identifier: CC0-1.0
`begin_keywords "VAMS-2.3"
module t (/*AUTOARG*/);
// Just get errors on bad keywords (for code coverage)
int above;
int abs;
int absdelay;
int abstol;
int ac_stim;
int access;
int acos;
int acosh;
int aliasparam;
int analog;
int analysis;
int assert;
int branch;
int connect;
int connectmodule;
int connectrules;
int continuous;
int cross;
int ddt;
int ddt_nature;
int ddx;
int discipline;
int discrete;
int domain;
int driver_update;
int endconnectrules;
int enddiscipline;
int endnature;
int endparamset;
int exclude;
int final_step;
int flicker_noise;
int flow;
int from;
int ground;
int idt;
int idt_nature;
int idtmod;
int inf;
int initial_step;
int laplace_nd;
int laplace_np;
int laplace_zd;
int laplace_zp;
int last_crossing;
int limexp;
int max;
int merged;
int min;
int nature;
int net_resolution;
int noise_table;
int paramset;
int potential;
int resolveto;
int slew;
int split;
int timer;
int transition;
int units;
int white_noise;
int zi_nd;
int zi_np;
int zi_zd;
int zi_zp;
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module zet_jmp_cond (
input [4:0] logic_flags,
input [3:0] cond,
input is_cx,
input [15:0] cx,
output reg jmp
);
// Net declarations
wire of, sf, zf, pf, cf;
wire cx_zero;
// Assignments
assign of = logic_flags[4];
assign sf = logic_flags[3];
assign zf = logic_flags[2];
assign pf = logic_flags[1];
assign cf = logic_flags[0];
assign cx_zero = ~(|cx);
// Behaviour
always @(cond or is_cx or cx_zero or zf or of or cf or sf or pf)
if (is_cx) case (cond)
4'b0000: jmp <= cx_zero; /* jcxz */
4'b0001: jmp <= ~cx_zero; /* loop */
4'b0010: jmp <= zf & ~cx_zero; /* loopz */
default: jmp <= ~zf & ~cx_zero; /* loopnz */
endcase
else case (cond)
4'b0000: jmp <= of;
4'b0001: jmp <= ~of;
4'b0010: jmp <= cf;
4'b0011: jmp <= ~cf;
4'b0100: jmp <= zf;
4'b0101: jmp <= ~zf;
4'b0110: jmp <= cf | zf;
4'b0111: jmp <= ~cf & ~zf;
4'b1000: jmp <= sf;
4'b1001: jmp <= ~sf;
4'b1010: jmp <= pf;
4'b1011: jmp <= ~pf;
4'b1100: jmp <= (sf ^ of);
4'b1101: jmp <= (sf ^~ of);
4'b1110: jmp <= zf | (sf ^ of);
4'b1111: jmp <= ~zf & (sf ^~ of);
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int M = 1000000000; char s[30]; bool answer(int x, int y) { printf( %d %d n , x, y); fflush(stdout); scanf( %s , s); return s[0] == b ; } int n; int main() { scanf( %d , &n); bool ty = answer(0, M / 2); int vl = 0, vr = M; int l = 1, r = M; for (int i = 1; i < n; i++) { int mid = (l + r) >> 1; bool ty2 = answer(mid, M / 2); if (ty2 == ty) { vl = max(vl, mid); l = mid + 1; } else { vr = min(vr, mid); r = mid - 1; } } printf( %d %d %d %d n , vl, 0, vr, M); }
|
/*
Text Mode Memory
Screen Memory is 16kB, and is organized into 128-bit cells.
Also has a 2kB fixed font.
*/
module ModTxtMemW(clock, reset,
pixCellIx, cellData,
fontGlyph, fontData,
busAddr, busData, busOE, busWR, busOK);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[13:0] pixCellIx;
output[127:0] cellData;
input[15:0] fontGlyph;
output[63:0] fontData;
input[31:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output[1:0] busOK;
reg[1:0] tBusOK; //Read OK State
reg[31:0] tBusData; //Output Data
wire tBusCSel; //Bus Chip-Select (Addr Matches)
assign busOK = (busOE && tBusCSel) ? tBusOK : 2'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[31:16]==16'h0080);
reg[13:0] tPixCellIx; //base cell index
reg[13:0] nxtPixCellIx; //base cell index
(* ram_style="block" *) reg[31:0] scrCell1A[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1B[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1C[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1D[0:1023];
reg[63:0] fontMem[255:0];
reg[63:0] fontGfx1Mem[127:0];
reg[63:0] fontGfx2Mem[127:0];
reg[31:0] scrRegCtrl[7:0]; //Control Registers
reg[127:0] tCell1;
reg[127:0] tNextCell1;
reg[15:0] tFontGlyph;
reg[63:0] tFontData1;
reg[63:0] tFontData2;
reg[63:0] tFontDataAsc1;
reg[63:0] tFontDataGfx1;
reg[63:0] tFontDataGfx2;
assign cellData = tCell1;
assign fontData = tFontData1;
initial begin
$readmemh("fontmem.txt", fontMem);
$readmemh("gfxfont0.txt", fontGfx1Mem);
$readmemh("gfxfont1.txt", fontGfx2Mem);
$readmemh("scrmem_1a.txt", scrCell1A);
$readmemh("scrmem_1b.txt", scrCell1B);
$readmemh("scrmem_1c.txt", scrCell1C);
$readmemh("scrmem_1d.txt", scrCell1D);
end
always @ (clock)
begin
nxtPixCellIx = pixCellIx;
tBusOK = 0;
tBusData = 0;
if(busOE && tBusCSel)
begin
nxtPixCellIx = busAddr[15:2];
if(busAddr[15:8]==255)
begin
tBusOK=1;
case(busAddr[6:2])
0: tBusData = scrRegCtrl[0];
1: tBusData = scrRegCtrl[1];
2: tBusData = scrRegCtrl[2];
3: tBusData = scrRegCtrl[3];
8: tBusData = {18'h0, pixCellIx};
endcase
end
else
begin
// tBusOK = tPixCellIx == busAddr[15:2];
// tBusData = tCell1;
tBusOK = (tPixCellIx[11:0] == busAddr[15:4]) ? 1: 0;
case(busAddr[3:2])
2'b00: tBusData = tCell1[ 31: 0];
2'b01: tBusData = tCell1[ 63:32];
2'b10: tBusData = tCell1[ 95:64];
2'b11: tBusData = tCell1[127:96];
endcase
end
end
tFontDataAsc1 = fontMem[tFontGlyph[7:0]];
tFontDataGfx1 = fontGfx1Mem[tFontGlyph[6:0]];
tFontDataGfx2 = fontGfx2Mem[tFontGlyph[6:0]];
case(tFontGlyph[9:7])
3'b000: tFontData2 = tFontDataAsc1;
3'b001: tFontData2 = tFontDataAsc1;
3'b010: tFontData2 = tFontDataGfx2;
3'b011: tFontData2 = tFontDataGfx1;
// 3'b100: tFontData2 = tFontDataAsc1;
// 3'b101: tFontData2 = tFontDataGfx2;
default: tFontData2 = tFontDataAsc1;
endcase
end
always @ (posedge clock)
begin
// tCell1 <= tNextCell1;
// tPixCellIx <= pixCellIx;
tPixCellIx <= nxtPixCellIx;
tCell1[ 31: 0] <= scrCell1A[tPixCellIx[9:0]];
tCell1[ 63:32] <= scrCell1B[tPixCellIx[9:0]];
tCell1[ 95:64] <= scrCell1C[tPixCellIx[9:0]];
tCell1[127:96] <= scrCell1D[tPixCellIx[9:0]];
tFontGlyph <= fontGlyph;
tFontData1 <= tFontData2;
if(tBusCSel && busOE)
tPixCellIx <= busAddr[15:2];
else
tPixCellIx <= pixCellIx;
if(tBusCSel && busWR && !busOE)
begin
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else
begin
// scrCell1[busAddr[11:2]] <= busData;
case(busAddr[3:2])
2'b00: scrCell1A[busAddr[13:4]] <= busData;
2'b01: scrCell1B[busAddr[13:4]] <= busData;
2'b10: scrCell1C[busAddr[13:4]] <= busData;
2'b11: scrCell1D[busAddr[13:4]] <= busData;
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e5 + 1, INF = 1e17, MOD = 1e9 + 7; long long n; string s, t = UDRL ; map<char, long long> m; int32_t main() { ios_base::sync_with_stdio(0); cin >> n >> s; for (long long i = 0; i < n; ++i) { m[s[i]]++; } cout << 2 * (min(m[t[0]], m[t[1]]) + min(m[t[2]], m[t[3]])) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; int mx = 0; for (int i = 0; i < n; i++) { cin >> a[i]; mx = max(a[i], mx); } int cnt = 0; int maxcnt = 0; for (int i = 0; i < n; i++) { if (a[i] == mx) cnt++; else { maxcnt = max(cnt, maxcnt); cnt = 0; } if (i == n - 1) { maxcnt = max(cnt, maxcnt); } } cout << maxcnt; }
|
`timescale 1ns / 1ps
module UDM_nxnB
#(parameter W=2) (
input wire [W-1:0] in1,
input wire [W-1:0] in2,
output wire [2*W-1:0] res
);
wire [W/2-1:0] L_in1;
wire [W/2-1:0] R_in1;
wire [W/2-1:0] L_in2;
wire [W/2-1:0] R_in2;
generate
if (W==2) begin : SmallBLOCK
wire [2:0] temp_res;
UDM_2x2 UDM_2x2 (.in1(in1), .in2(in2), .res(temp_res));
assign res = {1'b0, temp_res};
end else begin : BIGBLOCK
assign L_in1 = in1[W-1:W/2];
assign R_in1 = in1[W/2-1:0];
assign L_in2 = in2[W-1:W/2];
assign R_in2 = in2[W/2-1:0];
wire [W-1:0] res_Lin1Lin2;
wire [W-1:0] res_Hin1Lin2;
wire [W-1:0] res_Lin1Hin2;
wire [W-1:0] res_Hin1Hin2;
UDM_nxnB #(.W(W/2)) A_LxB_L (.in1(R_in1), .in2(R_in2), .res(res_Lin1Lin2));
UDM_nxnB #(.W(W/2)) A_HxB_L (.in1(L_in1), .in2(R_in2), .res(res_Hin1Lin2));
UDM_nxnB #(.W(W/2)) A_LxB_H (.in1(R_in1), .in2(L_in2), .res(res_Lin1Hin2));
UDM_nxnB #(.W(W/2)) A_HxB_H (.in1(L_in1), .in2(L_in2), .res(res_Hin1Hin2));
assign res = {res_Hin1Hin2, {W{1'b0}}} + {res_Hin1Lin2, {(W/2){1'b0}}} + {res_Lin1Hin2, {(W/2){1'b0}}} + {{W{1'b0}}, res_Lin1Lin2};
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef vector<int> vt; int a[110000]; int n; void solve() { vt v; vt::iterator it; for (int i = 0; i < n; i++) { it = upper_bound(v.begin(), v.end(), a[i]); if (it == v.end()) v.push_back(a[i]); else *it = a[i]; } cout << v.size() << endl; } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int p = 1000003; const int n = 10; int inv[1000005], a[15][15], ans[15]; int read() { char c = getchar(); int x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } int calc(int x) { int res = 0; for (int i = n; i >= 0; i--) res = (1LL * res * x + ans[i]) % p; return res; } int main() { inv[1] = 1; for (int i = 2; i < p; i++) inv[i] = 1LL * (p - p / i) * inv[p % i] % p; printf( ? 0 n ); fflush(stdout); ans[0] = read(); for (int i = 1; i <= n; i++) { printf( ? %d n , i); fflush(stdout); a[i][0] = 1; for (int j = 1; j <= n; j++) a[i][j] = a[i][j - 1] * i % p; a[i][n + 1] = (read() + p - ans[0]) % p; } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { int t = 1LL * a[j][i] * inv[a[i][i]] % p; for (int k = i + 1; k <= n + 1; k++) a[j][k] = (a[j][k] + p - 1LL * a[i][k] * t % p) % p; a[j][i] = 0; } } for (int i = n; i >= 1; i--) { int res = a[i][n + 1]; for (int j = i + 1; j <= n; j++) res = (res + p - 1LL * a[i][j] * ans[j] % p) % p; ans[i] = 1LL * res * inv[a[i][i]] % p; } for (int i = 0; i < p; i++) { if (calc(i) == 0) { printf( ! %d n , i); fflush(stdout); exit(0); } } printf( ! -1 n ); fflush(stdout); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_1_V
`define SKY130_FD_SC_LS__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int t; cin >> t; while (t--) { int n; cin >> n; string a, b; a += M , b += M ; string tmp1, tmp2; cin >> tmp1 >> tmp2; a += tmp1, b += tmp2; for (int i = (1); i < n + 1; i++) a[i] -= 0 , b[i] -= 0 ; vector<int> ans; int pos = 1; for (int i = (1); i < n + 1; i++) { if (b[n - i + 1] == (a[pos] + i - 1) % 2) ans.push_back(1); ans.push_back(n - i + 1); if (pos <= n / 2) pos = n - pos + 1; else pos = n - pos + 2; } cout << ans.size() << ; for (auto p : ans) cout << p << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, m, ans = 0; scanf( %I64d%I64d%I64d , &a, &b, &m); if (a >= m || b >= m) printf( 0 n ); else if (a <= 0 && b <= 0) printf( -1 n ); else { if (a < 0 || b < 0) { if (a > b) swap(a, b); ans = -a / b; a += b * ans; } while (a < m && b < m) { if (a > b) swap(a, b); ans++; a += b; } printf( %I64d n , ans); } return 0; }
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
module testmuxpv();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [WIDTH-1:0] out; // From testmuxpv_boo of testmuxpv.v, ..., Couldn't Merge
// End of automatics
//======================================================================
/* testmuxpv AUTO_TEMPLATE (
) */
testmuxpv #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.sel (sel[2:0]),
.a (a[15:0]));
//======================================================================
testmuxpv #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[WIDTH-1:0]),
// Inputs
.sel (sel[2:0]),
.a (a[WIDTH-1:0]));
//======================================================================
// bug331: vl-width should correct when param values propagating
/* testmuxpv AUTO_TEMPLATE (
.a ({@"vl-width"{1'b0}}),
) */
testmuxpv #(.IGNORE((1)),
.WIDTH(16),
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.sel (sel[2:0]),
.a ({16{1'b0}})); // Templated
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End:
|
#include <bits/stdc++.h> using namespace std; const int N = 14, M = 1 << N; int n, p[M]; char s[N][N]; vector<long long> f[M][N]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %s , s[i]); for (int i = 1; i < 1 << n; ++i) { p[i] = p[i >> 1] + (i & 1); for (int j = 0; j < n; ++j) if (i >> j & 1) f[i][j].resize(1 << (p[i] - 1)); } for (int i = 0; i < n; ++i) f[1 << i][i][0] = 1; for (int i = 1; i < 1 << n; ++i) for (int j = 0; j < n; ++j) if (i >> j & 1) for (int k = 0; k < n; ++k) if (!(i >> k & 1)) { int x = s[j][k] == 1 , y = i | (1 << k), z = x << p[i] >> 1; for (int t = 0; t < 1 << (p[i] - 1); ++t) f[y][k][t | z] += f[i][j][t]; } for (int i = 0; i < 1 << n >> 1; ++i) { long long x = 0; for (int j = 0; j < n; ++j) x += f[(1 << n) - 1][j][i]; printf( %lld , x); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 0) { cout << O-|-OOOO << endl; return 0; } while (n != 0) { int k = n % 10; if (k >= 5) { cout << -O| ; k -= 5; } else cout << O-| ; int i = 0; for (; i < k; i++) cout << O ; cout << - ; i++; for (; i < 5; i++) cout << O ; cout << endl; n /= 10; } }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_hr_to_fr(
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk)
begin
q_h0 <= d_h0;
q_l0 <= d_l0;
q_h1 <= d_h1;
q_l1 <= d_l1;
end
always @(negedge clk)
begin
q_l0_neg <= q_l0;
q_l1_neg <= q_l1;
end
assign q0 = clk ? q_l0_neg : q_h0;
assign q1 = clk ? q_l1_neg : q_h1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int K = 1048576; int n; long long t[2][2 * K]; vector<int> g[N]; int T[N]; long long h[N], x[N], dp[N]; long long total; void build() { for (int i = 0; i < 2 * K; i++) t[0][i] = t[1][i] = 0; } void upd(int id, long long X, int type) { id += K - 1; while (id > 0) { t[type][id] += X; id /= 2; } } long long get(int L, int R, int type) { if (R == 0) return 0; else if (type == 0 && R == K) return 2e18; L += K - 1; R += K - 1; long long res = 0; while (L <= R) { if (L % 2 == 1) res += t[type][L++]; if (R % 2 == 0) res += t[type][R--]; L /= 2; R /= 2; } return res; } void dfs(int v) { upd(T[v], x[v] * T[v], 0); upd(T[v], x[v], 1); int l = 1, r = K; while (l + 1 < r) { int mid = (l + r) / 2; if (h[v] + h[v] + get(1, mid - 1, 0) <= total) l = mid; else r = mid; } dp[v] = get(1, l - 1, 1); long long residue = total - get(1, l - 1, 0) - h[v] - h[v]; dp[v] += min(t[0][l + K - 1], residue) / l; for (int u : g[v]) { h[u] += h[v]; dfs(u); } if (v == 1) { for (int u : g[v]) dp[v] = max(dp[v], dp[u]); } else { long long max1 = 0, max2 = 0; for (int u : g[v]) { if (dp[u] > max1) { max2 = max1; max1 = dp[u]; } else if (dp[u] > max2) { max2 = dp[u]; } } dp[v] = max(dp[v], max2); } upd(T[v], -x[v] * T[v], 0); upd(T[v], -x[v], 1); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> total; for (int i = 1; i <= n; i++) cin >> x[i]; for (int i = 1; i <= n; i++) cin >> T[i]; for (int i = 2; i <= n; i++) { int parent; cin >> parent >> h[i]; g[parent].push_back(i); } build(); h[1] = 0; dfs(1); cout << dp[1] << n ; return 0; }
|
module mem2serial #(parameter AW = 8)
(
output reg read_clock_enable,
input [47:0] read_data,
input read_empty, // high is input is empty
input reset, // active low
input clock,
input uart_ready,
output reg [7:0] uart_data,
output reg uart_clock_enable);
parameter idle = 0, write_data = 1, wait_write_done = 2,
write_trailer = 3, wait_write_trailer_done = 4;
reg [2:0] state;
reg [7:0] write_pos;
reg [47:0] data;
always @(negedge reset or negedge clock) begin
if (~reset) begin
state <= idle;
uart_clock_enable <= 0;
read_clock_enable <= 0;
write_pos <= 00;
end
else
case (state)
idle: begin
if (~read_empty)
if (read_clock_enable) begin
data <= read_data;
state <= write_data;
read_clock_enable <= 0;
write_pos <= 40;
end else
read_clock_enable <= 1;
else
read_clock_enable <= 0;
end
write_data: begin
if (uart_ready) begin
uart_data[7] <= data[write_pos + 7];
uart_data[6] <= data[write_pos + 6];
uart_data[5] <= data[write_pos + 5];
uart_data[4] <= data[write_pos + 4];
uart_data[3] <= data[write_pos + 3];
uart_data[2] <= data[write_pos + 2];
uart_data[1] <= data[write_pos + 1];
uart_data[0] <= data[write_pos + 0];
uart_clock_enable <= 1;
write_pos <= write_pos - 8;
state <= wait_write_done;
end
end
wait_write_done: begin
if (~uart_ready) begin
uart_clock_enable <= 0;
if (write_pos > 40) begin /* overflow. finished writing */
write_pos <= 0;
state <= write_trailer;
end else
state <= write_data;
end
end
write_trailer: begin
if (uart_ready) begin
if (write_pos == 0) begin
uart_clock_enable <= 1;
uart_data <= 'h0a;
state <= wait_write_trailer_done;
end
else if (write_pos == 1) begin
uart_clock_enable <= 1;
uart_data <= 'h0d;
state <= wait_write_trailer_done;
end
else if (write_pos >= 2) begin
state <= idle;
end
write_pos <= write_pos + 1;
end
end
wait_write_trailer_done: begin
if (~uart_ready) begin
uart_clock_enable <= 0;
state <= write_trailer;
end
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O221A_BEHAVIORAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_lp_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_lp_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire SLEEP_B_delayed;
wire D_delayed ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 2e9; int32_t main() { cin.tie(0)->sync_with_stdio(0); long long n, m; string s, t; cin >> n >> m >> s >> t; vector<long long> pi(m, 0), nxt(m, 0); for (long long i = 1; i < m; i++) { { t[i] = char( 0 + (t[i] - 0 ) ^ 1); long long j = pi[i - 1]; while (j > 0 and t[i] != t[j]) { j = pi[j - 1]; } if (t[i] == t[j]) j++; nxt[i] = j; t[i] = char( 0 + (t[i] - 0 ) ^ 1); } { long long j = pi[i - 1]; while (j > 0 and t[i] != t[j]) { j = pi[j - 1]; } if (t[i] == t[j]) j++; pi[i] = j; } } s = # + s; long long dp[n + 1][m][n - m + 2]; fill(**dp, **dp + sizeof dp / sizeof(long long), inf); dp[0][0][0] = 0; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { for (long long k = 0; k < n - m + 2; k++) { if (dp[i][j][k] == inf) continue; if (j == m - 1) { dp[i + 1][pi.back()][k + 1] = min(dp[i + 1][pi.back()][k + 1], dp[i][j][k] + (s[i + 1] != t[j])); } else { dp[i + 1][j + 1][k] = min(dp[i + 1][j + 1][k], dp[i][j][k] + (s[i + 1] != t[j])); } dp[i + 1][nxt[j]][k] = min(dp[i + 1][nxt[j]][k], dp[i][j][k] + (s[i + 1] == t[j])); } } } for (long long i = 0; i < n - m + 2; i++) { long long mn = inf; for (long long j = 0; j < m; j++) { mn = min(mn, dp[n][j][i]); } if (mn == inf) mn = -1; cout << mn << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; long long int mx = 0; for (long long int i = 0; i < a.size(); i++) { long long int g = (a[i] - 0 ); mx = max(mx, g); } for (long long int i = 0; i < b.size(); i++) { long long int g = (b[i] - 0 ); mx = max(mx, g); } mx++; string h = ; long long int c = 0, s = 0; for (long long int i = 0; i < 20; i++) { if (a.size() < i) a = 0 + a; if (b.size() < i) b = 0 + b; } for (long long int i = 18; i >= 0; i--) { long long int q = (a[i] - 0 ), w = (b[i] - 0 ); s = (q + w + c) % mx; char ch = ( 0 + s); h = ch + h; c = (q + w + c) / mx; } long long int k = 0; while (h[k] == 0 ) k++; cout << 19 - k << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_1_V
`define SKY130_FD_SC_HS__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_1_V
|
#include <bits/stdc++.h> using namespace std; #define ll long long typedef pair<ll, ll> pll; typedef pair<ll, int> pli; typedef pair<int, ll> pil; typedef pair<int, int> pii; typedef vector<int> vi; typedef vector<vi> vvi; typedef vector<bool> vb; typedef vector<vb> vvb; typedef vector<char> vc; typedef vector<vc> vvc; typedef vector<string> vs; typedef vector<vs> vvs; typedef vector<ll> vll; typedef vector<vll> vvll; typedef vector<pii> vpii; typedef vector<vpii> vvpii; typedef vector<pll> vpll; typedef vector<vpll> vvpll; typedef set<int> si; typedef set<vi> svi; typedef set<ll> sll; typedef set<vll> svll; typedef set<pii> spii; typedef set<vpii> svpii; typedef set<pll> spll; typedef set<vpll> svpll; typedef vector<si> vsi; typedef vector<sll> vsll; typedef vector<spii> vspii; typedef vector<spll> vspll; #define ft first #define sc second #define pb push_back #define ins insert #define io ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL) #define all(v) v.begin(), v.end() #define Sort(v) sort(all(v)) #define sortarr(a, n) sort(a, a + n) #define tt ll tc; cin >> tc; while (tc--) #define rep(var, start, end, interval) for (ll var = start; (interval > 0 and var < end) or (interval < 0 and var > end); var += interval) #define each(x, v) for (auto x : v) #define takearr0(a, n) rep(z, 0, n, 1) cin >> a[z]; #define takearr1(a, n) rep(z, 1, n + 1, 1) cin >> a[z]; const ll max_n = 2e3 + 5; const ll inf = 1e16; ll n, m, w; vvll a; vpll neighbours(pll p) { vpll vec; if (p.ft > 0 and a[p.ft - 1][p.sc] >= 0) vec.pb({p.ft - 1, p.sc}); if (p.ft < n - 1 and a[p.ft + 1][p.sc] >= 0) vec.pb({p.ft + 1, p.sc}); if (p.sc > 0 and a[p.ft][p.sc - 1] >= 0) vec.pb({p.ft, p.sc - 1}); if (p.sc < m - 1 and a[p.ft][p.sc + 1] >= 0) vec.pb({p.ft, p.sc + 1}); return vec; } int main() { io; cin >> n >> m >> w; a.resize(n); a.assign(n, vll(m)); rep(i, 0, n, 1) takearr0(a[i], m); // each(vec, a) // { // each(x, vec) cout << setw(18) << x << ; // cout << endl; // } // cout << endl; vvb v(n, vb(m, false)); vvll dists(n, vll(m, inf)); queue<pll> q; q.push({0, 0}); v[0][0] = true; dists[0][0] = 0; while (!q.empty()) { pll p = q.front(); q.pop(); vpll nb = neighbours(p); each(pr, nb) if (!v[pr.ft][pr.sc]) { dists[pr.ft][pr.sc] = dists[p.ft][p.sc] + w; v[pr.ft][pr.sc] = true; q.push(pr); } } rep(i, 0, n, 1) rep(j, 0, m, 1) v[i][j] = false; vvll distt(n, vll(m, inf)); q.push({n - 1, m - 1}); v[n - 1][m - 1] = true; distt[n - 1][m - 1] = 0; while (!q.empty()) { pll p = q.front(); q.pop(); vpll nb = neighbours(p); each(pr, nb) if (!v[pr.ft][pr.sc]) { distt[pr.ft][pr.sc] = distt[p.ft][p.sc] + w; v[pr.ft][pr.sc] = true; q.push(pr); } } ll pors = inf, port = inf; rep(i, 0, n, 1) rep(j, 0, m, 1) if (a[i][j] > 0) { pors = min(pors, dists[i][j] + a[i][j]); port = min(port, distt[i][j] + a[i][j]); } ll ans = min(dists[n - 1][m - 1], pors + port); if (ans >= inf) cout << -1 << endl; else cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_BLACKBOX_V
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module carry_tree #( parameter n_words = 4
)( input [n_words-1:0] g
, input [n_words-1:0] p
, output [n_words-1:0] c
);
localparam n_leaves = 1 << $clog2(n_words);
localparam n_levels = 2*$clog2(n_words);
reg [n_leaves-1:0] g_int[n_levels-1:0];
reg [n_leaves-1:0] p_int[n_levels-1:0];
genvar CIter;
generate
if (n_words < 3) begin
assign c[0] = g[0];
if (n_words == 2) begin
assign c[1] = g[1] | (g[0] & p[1]);
end
end else begin
for(CIter=0; CIter<n_words; CIter++) begin: CAssign
assign c[CIter] = g_int[n_levels-1][CIter];
end
end
endgenerate
always_comb begin
if (n_words < 3) begin
g_int = '{default:0};
p_int = '{default:0};
end else begin
for(int i=0; i<n_leaves; i++) begin
if (i < n_words) begin
g_int[0][i] = g[i];
p_int[0][i] = p[i];
end else begin
g_int[0][i] = 1'b0;
p_int[0][i] = 1'b0;
end
end
for(int CStep=1; CStep<n_leaves; CStep*=2) begin
automatic int CLevel = $clog2(CStep) + 1;
automatic int CBot = CStep - 1;
automatic int CTop = CBot + CStep;
for(int CIter=0; CIter<n_leaves; CIter++) begin
if (CIter != CTop) begin
g_int[CLevel][CIter] = g_int[CLevel-1][CIter];
p_int[CLevel][CIter] = p_int[CLevel-1][CIter];
end else begin
g_int[CLevel][CIter] = g_int[CLevel-1][CIter] | (g_int[CLevel-1][CBot] & p_int[CLevel-1][CIter]);
p_int[CLevel][CIter] = p_int[CLevel-1][CIter] & p_int[CLevel-1][CBot];
CBot += CStep;
CTop += CStep;
end
end
end
for(int CStep=n_leaves/2; CStep>1; CStep/=2) begin
automatic int CLevel = 2 * $clog2(n_leaves) - $clog2(CStep);
automatic int CBot = CStep - 1;
automatic int CTop = CBot + CStep/2;
for(int CIter=0; CIter<n_leaves; CIter++) begin
if (CIter != CTop) begin
g_int[CLevel][CIter] = g_int[CLevel-1][CIter];
p_int[CLevel][CIter] = p_int[CLevel-1][CIter];
end else begin
g_int[CLevel][CIter] = g_int[CLevel-1][CIter] | (g_int[CLevel-1][CBot] & p_int[CLevel-1][CIter]);
p_int[CLevel][CIter] = p_int[CLevel-1][CIter] & p_int[CLevel-1][CBot];
CBot += CStep;
CTop += CStep;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long qr() { long long x = 0, f = 1; char ch; while (!isdigit(ch = getchar())) if (ch == - ) f = -1; for (; isdigit(ch); x = x * 10 + ch - 48, ch = getchar()) ; return x * f; } const int N = 100010; int n, k, a[N], res; int s[N], top, b[N], c[N]; int lt[N], nt[N]; vector<int> ans[500]; int LIS() { for (int i = 1; i <= top; ++i) b[i] = lt[i] = nt[i] = 0; s[top = 1] = 1e5 + 1; for (int i = 1; i <= n; ++i) { int p = upper_bound(s + 1, s + 1 + top, a[i]) - s; s[p] = a[i]; lt[i] = b[p]; b[p] = i; nt[i] = b[p - 1]; if (p == top) s[++top] = 1e5 + 1; } return top - 1; } void Find(int x) { ans[++res].clear(); for (int i = b[x]; i; i = nt[i]) ans[res].push_back(a[i]), a[i] = -1; } void Div(int n) { for (int i = 1; i <= n; ++i) { ans[++res].clear(); for (int j = b[i]; j; j = lt[j]) ans[res].push_back(a[j]); } } int main() { int kase = qr(); while (kase--) { n = qr(); res = 0; for (int i = 1; i <= n; ++i) a[i] = qr(); while (n) { int k = LIS(); if (1LL * k * (k + 1) > 2 * n) Find(k); else { Div(k); break; } int ct = 0; for (int i = 1; i <= n; ++i) if (a[i] != -1) a[++ct] = a[i]; n = ct; } printf( %d n , res); for (int i = 1; i <= res; ++i) { int l = ans[i].size(); printf( %d , l); for (int j = l - 1; j >= 0; --j) printf( %d , ans[i][j]); puts( ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int v[7], x[7]; int main() { for (int i = 0; i < 6; ++i) scanf( %d , &v[i]); int ans = -1; for (int i = 0; i <= 100000; ++i) { x[1] = v[1] - v[2] + v[3] - v[4] + 2 * i; if (x[1] % 2 || x[1] < 0) continue; x[2] = v[2] + v[4] - v[0] - 2 * i; if (x[2] % 2 || x[2] < 0) continue; x[3] = v[0] - v[2] - v[5] + v[3] + 2 * i; if (x[3] % 2 || x[3] < 0) continue; x[4] = v[2] + v[5] - v[1] - 2 * i; if (x[4] % 2 || x[4] < 0) continue; x[5] = v[4] + v[5] - v[3] - 2 * i; if (x[5] % 2 || x[5] < 0) continue; x[6] = v[0] - v[5] + v[1] - v[4] + 2 * i; if (x[6] % 2 || x[6] < 0) continue; ans = i; break; } if (ans != -1) { x[0] = ans; int res = ans; for (int i = 1; i <= 6; ++i) { x[i] /= 2; res += x[i]; } printf( %d n , res); for (int i = 0; i < res; ++i) printf( a ); printf( n ); for (int i = 0; i < x[0] + x[1] + x[2]; ++i) printf( a ); for (int i = 0; i < x[3] + x[4] + x[5] + x[6]; ++i) printf( b ); printf( n ); for (int i = 0; i < x[0]; ++i) printf( a ); for (int i = 0; i < x[1] + x[2]; ++i) printf( b ); for (int i = 0; i < x[3] + x[4]; ++i) printf( a ); for (int i = 0; i < x[5] + x[6]; ++i) printf( b ); printf( n ); for (int i = 0; i < x[0]; ++i) printf( b ); for (int i = 0; i < x[1]; ++i) printf( a ); for (int i = 0; i < x[2]; ++i) printf( b ); for (int i = 0; i < x[3]; ++i) printf( a ); for (int i = 0; i < x[4]; ++i) printf( b ); for (int i = 0; i < x[5]; ++i) printf( a ); for (int i = 0; i < x[6]; ++i) printf( b ); printf( n ); } else { printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxs = 405; const int inf = 1e9 + 7; int dp[maxs][maxs]; string s, t, x, y; int slen, tlen; int nxt[maxs][26]; int g(int x) { return x + 1; } int f(int a, int b) { if (a == -1 && b == -1) return 0; if (a < -1 || b < -1) return inf; int& r = dp[g(a)][g(b)]; if (r == -1) { r = inf; int idx; if (a >= 0) { idx = f(a - 1, b); if (idx < inf) r = min(r, nxt[idx][x[a] - a ] + 1); } if (b >= 0) { idx = f(a, b - 1); if (idx < inf) r = min(r, nxt[idx][y[b] - a ] + 1); } } return r; } int main(void) { ios_base::sync_with_stdio(0); cin.tie(0); int T; cin >> T; while (T--) { cin >> s >> t; int i = 0, j = 0; slen = s.size(), tlen = t.size(); while (i < slen && j < tlen) { if (s[i] == t[j]) ++j; ++i; } if (j == tlen) { cout << YES n ; continue; } for (int i = 0; i <= slen; ++i) for (int j = 0; j < 26; ++j) nxt[i][j] = inf; for (int i = slen - 1; i >= 0; --i) { for (int j = 0; j < 26; ++j) nxt[i][j] = nxt[i + 1][j]; nxt[i][s[i] - a ] = i; } bool yes = false; for (int i = 1; i < tlen; ++i) { for (int j = 0; j <= tlen; ++j) for (int k = 0; k <= tlen; ++k) dp[j][k] = -1; x = t.substr(0, i); y = t.substr(i, tlen - i); if (f(i - 1, tlen - i - 1) < inf) { yes = true; break; } } cout << (yes ? YES n : NO n ); } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int N = 3e5 + 100; const double PI = acos(-1.0); void fre() { freopen( /Users/luras/Desktop/in.txt , r , stdin); freopen( /Users/luras/Desktop/out.txt , w , stdout); } int n, m, i, j, ans, p; char s[N], ch; int main() { while (~scanf( %d%d , &n, &m)) { scanf( %s , s + 1); ans = 0; for (i = 2; i <= n; i++) { if (s[i] == . && s[i - 1] == . ) ans++; } for (i = 1; i <= m; i++) { scanf( %d %c , &p, &ch); if ((s[p] == . && ch == . ) || (s[p] != . && ch != . )) { printf( %d n , ans); continue; } if (s[p] == . ) { if (p == 1) { if (s[p + 1] == . ) { ans--; } } else { if (s[p + 1] == . ) ans--; if (s[p - 1] == . ) ans--; } } else { if (p == 1) { if (s[p + 1] == . ) ans++; } else { if (s[p + 1] == . ) ans++; if (s[p - 1] == . ) ans++; } } s[p] = ch; printf( %d n , ans); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_2_V
`define SKY130_FD_SC_LP__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_2_V
|
`timescale 1ns / 10ps
module test ();
reg [3:0] a_in;
reg [3:0] b_in;
reg [3:0] s_in;
reg M_in,Ci_inverse_in;
wire [3:0] Y_out;
wire P_out,Q_out,Co_inverse_out,AequalsB_out;
ALU alu(a_in,b_in,s_in,M_in,Ci_inverse_in,P_out,Q_out,Co_inverse_out,Y_out,AequalsB_out);
integer i,j,k,l,m;
initial begin
a_in = 4'b0000;
b_in = 4'b0000;
s_in = 4'b0000;
M_in = 1'b0;
Ci_inverse_in = 1'b0;
end
initial begin
for (i=0;i<2;i=i+1)
begin
for(j=0;j<2;j=j+1)
begin
for(k=0;k<16;k=k+1)
begin
for(l=0;l<16;l=l+1)
begin
for(m=0;m<16;m=m+1)
begin
#100 a_in = m;
b_in = l;
s_in = k;
M_in = j;
Ci_inverse_in = i;
#10 $display($time,,"a_in=%b,b_in=%b,s_in=%b,M_in=%b,Ci_inverse_in=%b Y_out=%b,P_out=%b,Q_out=%b,Co_inverse_out=%b,AequalsB_out=%b",a_in,b_in,s_in,M_in,Ci_inverse_in,Y_out,P_out,Q_out,Co_inverse_out,AequalsB_out);
end
end
end
end
end
end
endmodule // test
|
#include <bits/stdc++.h> using namespace std; char a[100005]; int b[100005]; map<pair<int, int>, int> maps; int main() { int nx, ny, x, y, x1, y1, n; scanf( %d%d%d%d , &nx, &ny, &x, &y); scanf( %s , a); for (int i = 0; i < 100005; i++) b[i] = 0; b[0] = 1; maps[make_pair(x, y)] = 1; for (n = 0; a[n] != 0 ; n++) ; for (int i = 0; i < n; i++) { switch (a[i]) { case L : y1 = y - 1; x1 = x; break; case R : y1 = y + 1; x1 = x; break; case U : x1 = x - 1; y1 = y; break; case D : x1 = x + 1; y1 = y; break; } if (x1 <= nx && y1 <= ny && x1 > 0 && y1 > 0) { if (maps[make_pair(x1, y1)] == 0) { b[i + 1]++; maps[make_pair(x1, y1)] = 1; } x = x1; y = y1; } } b[n] += nx * ny - maps.size(); for (int i = 0; i <= n; i++) printf( %d , b[i]); printf( n ); return 0; }
|
#include<bits/stdc++.h> #define maxn 20010 using namespace std; int n, m, a[maxn]; int lg[maxn], mx[maxn][21], f[maxn][35][21], s[35], t[35]; int mxx(int x,int y){return x+a[x]>y+a[y]?x:y;} int qry(int x,int y){return mxx(mx[x][lg[y-x+1]],mx[y-(1<<lg[y-x+1])+1][lg[y-x+1]]);} int main() { lg[0]=-1; scanf( %d%d ,&n,&m); for(int i=1;i<=n;i++) scanf( %d ,&a[i]),lg[i]=lg[i>>1]+1,mx[i][0]=i; for(int j=1;j<=14;j++) for(int i=1;i<=n-(1<<j)+1;i++) mx[i][j]=mxx(mx[i][j-1],mx[i+(1<<(j-1))][j-1]); for(int i=1;i<=n;i++) for(int j=0;j<31;j++) f[i][j][0]=min(n,i+a[i]+j); for(int j=1;j<15;j++) for(int i=1;i<=n;i++) for(int x=0;x<31;x++) for(int y=0;x+y<31;y++) f[i][x+y][j]=max(f[i][x+y][j],f[qry(i,f[i][x][j-1])][y][j-1]); while(m--) { int l,r,k; scanf( %d%d%d ,&l,&r,&k); if(l==r){puts( 0 );continue;} for(int i=0;i<=k;i++) s[i]=t[i]=l; int ans=0; for(int j=14;j>=0;j--) { for(int i=0;i<=k;i++) t[i]=s[i]; for(int x=0;x<=k;x++) for(int y=0;x+y<=k;y++) t[x+y]=std::max(t[x+y],f[qry(l,s[x])][y][j]); bool flg=0; for(int i=0;i<=k;i++) if(t[i]>=r) flg=1; if(flg) continue; ans+=(1<<j); for(int i=0;i<=k;i++) s[i]=t[i]; } printf( %d n ,ans+1); } return 0; }
|
#include <bits/stdc++.h> const int maxn = 300 + 10; char st[maxn][maxn]; int n, m, p; int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; i++) scanf( %s , st[i] + 1); for (int k = 1; k <= n; k++) { for (int i = 1 + k; i + k <= n; i++) for (int j = 1 + k; j + k <= m; j++) if (st[i][j] == * && st[i - k][j] == * && st[i + k][j] == * && st[i][j - k] == * && st[i][j + k] == * ) { p--; if (!p) { printf( %d %d n%d %d n%d %d n%d %d n%d %d n , i, j, i - k, j, i + k, j, i, j - k, i, j + k); return 0; } } } printf( -1 n ); }
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_scramble
*/
module test_lfsr_scramble;
// Parameters
parameter LFSR_WIDTH = 58;
parameter LFSR_POLY = 58'h8000000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 1;
parameter DATA_WIDTH = 8;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg data_in_valid = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
data_in_valid
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_scramble.lxt");
$dumpvars(0, test_lfsr_scramble);
end
lfsr_scramble #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.11 2009/08/21 23:55:43 harikr Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF (O, IO, I, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO)= (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_8_V
`define SKY130_FD_SC_LS__CLKINV_8_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_8_V
|
#include <bits/stdc++.h> const int N = 600000 + 7; using namespace std; char o[] = { I , E , A , O , U , Y }; bool mark[N]; long long sum[N]; long double ans; int main() { ios_base::sync_with_stdio(0); cin.tie(0); string s; cin >> s; for (int i = 0; i < (((int)s.size())); i++) for (int j = 0; j < (6); j++) if (s[i] == o[j]) mark[i + 1] = true; int n = ((int)s.size()); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + mark[i]; long long cnt = sum[n]; ans = cnt; for (int i = 2; i <= n; i++) { cnt += (sum[n - i + 1] - sum[i - 1]); ans += (long double)cnt / (long double)i; } cout << setprecision(7) << fixed << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; set<int> a, b; set<int> pre; char str[10]; int main() { int n; cin >> n; long long ans = 1; a.insert(0); b.insert(1e9 + 5); for (int i = 0; i < n; ++i) { int x; scanf( %s%d , str, &x); if (str[1] == D ) { int l = *a.rbegin(); int r = *b.begin(); if (x > l && x < r) { pre.insert(x); } else { if (x < l) a.insert(x); else b.insert(x); } } else { if (pre.count(x)) { ans *= 2; ans %= mod; for (auto it : pre) { if (it > x) b.insert(it); else if (it < x) a.insert(it); } pre.clear(); } else { int l = *a.rbegin(); int r = *b.begin(); if (x == l) { a.erase(x); for (auto it : pre) { if (it != x) b.insert(it); } } else if (x == r) { b.erase(x); for (auto it : pre) { if (it != x) a.insert(it); } } else return puts( 0 ); pre.clear(); } } } int x = pre.size(); ans *= (x + 1); ans %= mod; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, a = 0; cin >> n; int* arr = new int[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); for (int j = 0; j < n; j++) { cout << arr[j] << ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: IIT Roorkee
// Engineers: Rohith Asrk, Nitin Sethi, Sri Vathsa, Shashwat Kumar
//
// Create Date: 13:34:17 04/08/2017
// Design Name:
// Module Name: Insertion
// Project Name: FPGA Implementation of Image Watermarking
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Insertion(
input clk,
input [7:0]Data1,
input [7:0]Data2,
input [7:0]Data3,
input [7:0]Data4,
input [1:0]WM_Data,
output [7:0]WM_IM_Data
);
wire [8:0] Adder1, Adder2, Adder;
wire [7:0] m1, m11, m2, m12;
reg [7:0] temp;
adder8 A1(.a(Data2), .b(Data4), .add(1), .s(Adder1));
wire [7:0] shiftedAdder1 = Adder1[8:1];
adder8 A2(.a(Data3), .b(shiftedAdder1), .add(1), .s(Adder2));
wire [7:0] shiftedAdder2 = Adder2[8:1];
Amul mul2(.a(shiftedAdder2), .clk(clk), .p(m2));
Cmul mul1(.a(Data1), .p(m11));
Bmul mul3(.a(Data1), .p(m12));
assign m1 = (WM_Data == 2'b01)? m11 : ((WM_Data == 2'b10)? m12 : 0);
adder8 A3(.a(m1), .b(m2), .add(1), .s(Adder));
assign WM_IM_Data = (WM_Data== 2'b00 | WM_Data == 2'b11)? Data1 : Adder[7:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; struct vec { long long x, y; }; bool operator==(const vec& a, const vec& b) { return a.x == b.x and a.y == b.y; } bool operator!=(const vec& a, const vec& b) { return not(a == b); } bool operator<(const vec& a, const vec& b) { return make_pair(a.x, a.y) < make_pair(b.x, b.y); } vec operator+(const vec& a, const vec& b) { return (vec){a.x + b.x, a.y + b.y}; } int main() { ios_base::sync_with_stdio(false); long long n, m; vec d; cin >> n >> m >> d.x >> d.y; vector<vec> apple(m); for (int i = 0; i < (m); ++i) cin >> apple[i].x >> apple[i].y; sort(apple.begin(), apple.end()); vector<int> x2y(n); { vec p = d; while (p != (vec){0, 0}) { x2y[p.x] = p.y; p = p + d; p.x %= n; p.y %= n; } } vector<int> bucket(n); { int i = 0; for (int x = 0; x < (n); ++x) { for (; i < m and apple[i].x <= x; ++i) { bucket[(apple[i].y - x2y[x] + n) % n] += 1; } } } { int ix; int sz = -1; for (int i = 0; i < (n); ++i) if (sz < bucket[i]) { sz = bucket[i]; ix = i; } cout << 0 << << ix << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, d, t; int a[1000005], b[1000005], c[1000005]; char ch[1000005], ans[1000005]; void mul(int* a, int* b) { for (int i = 0; i < n; ++i) { c[i] = b[a[i]]; } for (int i = 0; i < n; ++i) { a[i] = c[i]; } } int main() { scanf( %s , ch); n = strlen(ch); scanf( %d , &t); while (t--) { scanf( %d%d , &k, &d); int now = 0; for (int i = 0; i < d; ++i) { for (int j = i; j < k; j += d) { a[j] = now++; } } for (int i = k; i < n; ++i) { a[i] = i; } for (int i = 0; i < n; ++i) { a[i] = (a[i] - 1 + n) % n; } for (int i = 0; i < n; ++i) { b[i] = i; } now = (n - k + 1); while (now) { if (now & 1) { mul(b, a); } mul(a, a); now >>= 1; } for (int i = 0; i < n; ++i) { ans[(b[i] + n - k + 1) % n] = ch[i]; } for (int i = 0; i < n; ++i) { ch[i] = ans[i]; } printf( %s n , ch); } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:43:53 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_1/system_auto_us_1_stub.v
// Design : system_auto_us_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_1(s_axi_aclk, s_axi_aresetn, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_araddr, m_axi_arlen, m_axi_arsize,
m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, tot, len[(int)(3e3 + 4)]; pair<int, int> bound[(int)(3e3 + 4)]; string s; vector<int> poz, ans[3000004]; void fail(); int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> k; cin >> s; for (int i = s.size() - 1; i >= 0; --i) if (s[i] == R ) { len[poz.size()] = (s.size() - poz.size()) - i - 1; tot += len[poz.size()]; poz.push_back(i); } if (k > tot) fail(); int p = 0; while (p < poz.size() && !len[p]) ++p; bound[p] = {1, len[p]}; tot -= len[p]; for (int i = p + 1; i < poz.size(); ++i) { int l, r, dist, ramas; dist = dist = poz[i - 1] - poz[i] - 1; l = max(1, bound[i - 1].first + 1 - dist); tot -= len[i]; if (k - tot - len[i] + 1 >= l) bound[i] = {k - tot - len[i] + 1, k - tot}; else if (l + len[i] - 1 <= k) bound[i] = {l, l + len[i] - 1}; else fail(); } for (int i = 0; i < poz.size(); ++i) { int p = poz[i]; while (bound[i].first <= bound[i].second) { ans[bound[i].first].push_back(p + 1); ++p; ++bound[i].first; } } for (int i = 1; i < k + 1; ++i) { printf( %d , ans[i].size()); for (auto it : ans[i]) printf( %d , it); printf( n ); } return 0; } void fail() { cout << -1; exit(0); }
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// This module updates the read_data immediately upon getting
// a delete signal (using assign).
module buffer_BB
#(
parameter WIDTH = 32,
parameter MEM_SIZE = 64
)
(
input wire clk,
input wire rst_n,
// Write new data.
input wire write_strobe,
input wire [WIDTH-1: 0] write_data,
// Delete the current read data.
input wire read_delete,
// The current read data.
output wire read_full,
output wire [WIDTH-1: 0] read_data,
// Buffer overflow.
output wire error
);
reg read_error;
reg write_error;
assign error = read_error | write_error;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
localparam integer LOG_MEM_SIZE = clog2(MEM_SIZE);
reg [MEM_SIZE-1:0] full;
reg [WIDTH-1: 0] RAM[MEM_SIZE-1:0];
reg [LOG_MEM_SIZE-1: 0] write_addr;
reg [LOG_MEM_SIZE-1: 0] read_addr0;
reg read_full0;
reg read_full1;
reg [WIDTH-1:0] read_data0;
reg [WIDTH-1:0] read_data1;
wire [LOG_MEM_SIZE-1: 0] read_addr1;
wire [LOG_MEM_SIZE-1: 0] read_addr2;
assign read_addr1 = read_addr0 + 1;
assign read_addr2 = read_addr0 + 2;
assign read_full = (read_delete)?read_full1:read_full0;
assign read_data = (read_delete)?read_data1:read_data0;
always @(posedge clk)
if (!rst_n)
begin
write_error <= 1'b0;
read_error <= 1'b0;
full <= {MEM_SIZE{1'b0}};
write_addr <= {LOG_MEM_SIZE{1'b0}};
read_addr0 <= {LOG_MEM_SIZE{1'b0}};
end
else
begin
if (error)
$display("There was an error");
if (write_strobe)
begin
if (!full[write_addr])
begin
RAM[write_addr] <= write_data;
full[write_addr] <= 1'b1;
write_addr <= write_addr + 1;
end
else
write_error <= 1'b1;
end
if (read_delete)
begin
if (full[read_addr0])
begin
full[read_addr0] <= 1'b0;
read_addr0 <= read_addr1;
read_full0 <= full[read_addr1];
read_data0 <= RAM[read_addr1];
read_full1 <= full[read_addr2];
read_data1 <= RAM[read_addr2];
end
else
begin
read_error <= 1'b1;
read_full0 <= full[read_addr0];
read_data0 <= RAM[read_addr0];
read_full1 <= full[read_addr1];
read_data1 <= RAM[read_addr1];
end
end
else
begin
read_full0 <= full[read_addr0];
read_data0 <= RAM[read_addr0];
read_full1 <= full[read_addr1];
read_data1 <= RAM[read_addr1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 2e5 + 5; const long long INF = (1LL << 62); const long double pi = 3.14159265359; void SRAND() { auto duration = std::chrono::system_clock::now().time_since_epoch(); auto millis = std::chrono::duration_cast<std::chrono::milliseconds>(duration).count(); srand(millis); } long long n, k, u[N], p[N], ans, x, y; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (long long i = 1; i <= n; i++) cin >> u[i]; for (long long i = n; i >= 1; i--) { p[i] = (u[i] == 1 ? p[i + 1] + 1 : 0); } for (long long i = 1; i <= n; i++) { x = u[i]; y = u[i]; if (x == y * k) ans++; for (long long j = i + 1; j <= n; j++) { if (u[j] == 1) { if (x % k == 0 && (x - k * y) / k >= 1 && (x - k * y) / k <= p[j]) ans++; y += p[j]; j += p[j] - 1; continue; } if (x >= INF / u[j]) break; x *= u[j]; y += u[j]; if (x == y * k) ans++; } } cout << ans << n ; return 0; }
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module fifomem_dp
#(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4, // Number of mem address bits
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire a_clk,
input wire [DATASIZE-1:0] a_wdata,
output wire [DATASIZE-1:0] a_rdata,
input wire [ADDRSIZE-1:0] a_addr,
input wire a_rinc,
input wire a_winc,
input wire b_clk,
input wire [DATASIZE-1:0] b_wdata,
output wire [DATASIZE-1:0] b_rdata,
input wire [ADDRSIZE-1:0] b_addr,
input wire b_rinc,
input wire b_winc
);
reg [DATASIZE-1:0] a_rdata_r;
reg [DATASIZE-1:0] b_rdata_r;
generate
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
if (FALLTHROUGH == "TRUE") begin : fallthrough
always @(posedge a_clk)
if (a_winc)
mem[a_addr] <= a_wdata;
assign a_rdata = mem[a_addr];
always @(posedge b_clk)
if (b_winc)
mem[b_addr] <= b_wdata;
assign b_rdata = mem[b_addr];
end else begin : registered
wire a_en = a_rinc | a_winc;
always @(posedge a_clk)
if (a_en) begin
if (a_winc)
mem[a_addr] <= a_wdata;
a_rdata_r <= mem[a_addr];
end
assign a_rdata = a_rdata_r;
wire b_en = b_rinc | b_winc;
always @(posedge b_clk)
if (b_en) begin
if (b_winc)
mem[b_addr] <= b_wdata;
b_rdata_r <= mem[b_addr];
end
assign b_rdata = b_rdata_r;
end // block: registered
endgenerate
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int const N = 100000; long long a[N + 1]; long long f[N * 3]; inline int lc(int root) { return root << 1; } inline int rc(int root) { return (root << 1) | 1; } void build(int root, int l, int r) { f[root] = -1; if (l == r) { f[root] = a[l]; return; } int mid = (l + r) >> 1; build(lc(root), l, mid); build(rc(root), mid + 1, r); if (f[lc(root)] == f[rc(root)]) { f[root] = f[lc(root)]; } } void update(int root, int l, int r, int fi, int la, long long val) { if (fi == l && la == r) { f[root] = val; return; } int mid = (l + r) >> 1; f[root] = -1; if (fi > mid) { update(rc(root), mid + 1, r, fi, la, val); } else if (la <= mid) { update(lc(root), l, mid, fi, la, val); } else { update(lc(root), l, mid, fi, mid, val); update(rc(root), mid + 1, r, mid + 1, la, val); } if (f[lc(root)] == f[rc(root)]) { f[root] = f[lc(root)]; } } long long query(int root, int l, int r, int fi, int la) { if (f[root] != -1) { return f[root]; } int mid = (l + r) >> 1; if (fi > mid) { return query(rc(root), mid + 1, r, fi, la); } else if (la <= mid) { return query(lc(root), l, mid, fi, la); } else { return max(query(lc(root), l, mid, fi, mid), query(rc(root), mid + 1, r, mid + 1, la)); } } void work() { int n; int m; long long w, h; long long res; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %I64d , &a[i]); } build(1, 1, n); scanf( %d , &m); while (m--) { scanf( %I64d%I64d , &w, &h); res = query(1, 1, n, 1, w); printf( %I64d n , res); update(1, 1, n, 1, w, res + h); } } int main() { work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000 * 1000 + 10; vector<int> vec[N]; vector<int> d[2]; bool mark[N]; void dfs(int v, int hh) { mark[v] = true; d[hh].push_back(v); for (int u : vec[v]) if (!mark[u]) dfs(u, 1 - hh); } int main() { int o; cin >> o; while (o--) { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) vec[i].clear(), mark[i] = false; ; d[0].clear(); d[1].clear(); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; vec[a].push_back(b); vec[b].push_back(a); } dfs(0, 0); if ((int)d[0].size() > (int)d[1].size()) swap(d[0], d[1]); cout << (int)d[0].size() << endl; for (int a : d[0]) cout << a + 1 << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const unsigned int MOD = 1000000007; void solve() { string s; cin >> s; string t; cin >> t; vector<char> v; bool check1 = false; bool check2 = false; bool check3 = false; for (int i = 0; i < s.length(); i++) { if (s[i] == a ) { check1 = true; } if (s[i] == b ) { check2 = true; } if (s[i] == c ) { check3 = true; } } if (t[0] == a && t[1] == b && t[2] == c && check1 && check2 && check3) { for (int j = 0; j < s.length(); j++) { if (s[j] == a ) { v.push_back(s[j]); } } for (int j = 0; j < s.length(); j++) { if (s[j] == c ) { v.push_back(s[j]); } } for (int j = 0; j < s.length(); j++) { if (s[j] == b ) { v.push_back(s[j]); } } } else { for (int j = 0; j < s.length(); j++) { if (s[j] == a ) { v.push_back(s[j]); } } for (int j = 0; j < s.length(); j++) { if (s[j] == b ) { v.push_back(s[j]); } } for (int j = 0; j < s.length(); j++) { if (s[j] == c ) { v.push_back(s[j]); } } } sort(s.begin(), s.end()); for (int i = 0; i < s.length(); i++) { if (s[i] != a && s[i] != b && s[i] != c ) { v.push_back(s[i]); } } for (auto it : v) { cout << it; } cout << endl; } signed main() { int t; cin >> t; while (t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
`include "clk_gen.v"
`include "monopix_core.v"
`include "utils/bus_to_ip.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/reset_gen.v"
`include "utils/CG_MOD_pos.v"
`include "spi/spi_core.v"
`include "spi/spi.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "gpio/gpio.v"
`include "tlu/tlu_controller.v"
`include "tlu/tlu_controller_core.v"
`include "tlu/tlu_controller_fsm.v"
`include "timestamp/timestamp.v"
`include "timestamp/timestamp_core.v"
`include "timestamp640/timestamp640.v"
`include "timestamp640/timestamp640_core.v"
`include "utils/fx2_to_bus.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "sram_fifo/sram_fifo_core.v"
`include "sram_fifo/sram_fifo.v"
`include "utils/3_stage_synchronizer.v"
`include "rrp_arbiter/rrp_arbiter.v"
`include "utils/ddr_des.v"
`include "utils/flag_domain_crossing.v"
`include "mono_data_rx/mono_data_rx.v"
`include "mono_data_rx/mono_data_rx_core.v"
`include "utils/cdc_reset_sync.v"
`ifdef COCOTB_SIM //for simulation
`include "utils/ODDR_sim.v"
`include "utils/IDDR_sim.v"
`include "utils/DCM_sim.v"
`include "utils/clock_multiplier.v"
`include "utils/BUFG_sim.v"
`include "utils/RAMB16_S1_S9_sim.v"
`else
`include "utils/IDDR_s3.v"
`include "utils/ODDR_s3.v"
`endif
module monopix_mio (
input wire FCLK_IN, // 48MHz
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FDATA,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//LED
output wire [4:0] LED,
//SRAM
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
input wire [2:0] LEMO_RX,
output wire [2:0] LEMO_TX, // TX[0] == RJ45 trigger clock output, TX[1] == RJ45 busy output
input wire RJ45_RESET,
input wire RJ45_TRIGGER,
input wire SR_OUT, //DIN4
output wire SR_IN, //DOUT11
output wire LDPIX, //DOUT15
output wire CKCONF, //DOUT10
output wire LDDAC, //DOUT12
output wire SR_EN, //DOUT13
output wire RESET, //DOUT14
output wire INJECTION,
input wire MONITOR, //DIN1
output wire CLK_BX, //DOUT1
output wire READ, //DOUT2
output wire FREEZE, //DOUT3
output wire nRST, //DOUT4
output wire EN_TEST_PATTERN, //DOUT5
output wire RST_GRAY, //DOUT6
output wire EN_DRIVER, //DOUT7
output wire EN_DATA_CMOS, //DOUT8
output wire CLK_OUT, //DOUT9
input wire TOKEN, //DIN2
input wire DATA, //DIN0
input wire DATA_LVDS, //DIN8_LVDS0
output wire DEBUG, //DOUT0
// I2C
inout wire SDA,
inout wire SCL
);
assign SDA = 1'bz;
assign SCL = 1'bz;
// ------- RESRT/CLOCK ------- //
wire BUS_RST;
(* KEEP = "{TRUE}" *)
wire CLK320;
(* KEEP = "{TRUE}" *)
wire CLK160;
(* KEEP = "{TRUE}" *)
wire CLK40;
(* KEEP = "{TRUE}" *)
wire CLK16;
(* KEEP = "{TRUE}" *)
wire BUS_CLK;
(* KEEP = "{TRUE}" *)
wire CLK8;
reset_gen reset_gen(.CLK(BUS_CLK), .RST(BUS_RST));
wire CLK_LOCKED;
clk_gen clk_gen(
.CLKIN(FCLK_IN),
.BUS_CLK(BUS_CLK),
.U1_CLK8(CLK8),
.U2_CLK40(CLK40),
.U2_CLK16(CLK16),
.U2_CLK160(CLK160),
.U2_CLK320(CLK320),
.U2_LOCKED(CLK_LOCKED)
);
// ------- MODULE ADREESSES ------- //
localparam FIFO_BASEADDR = 16'h8000;
localparam FIFO_HIGHADDR = 16'h9000-1;
// ------- BUS SYGNALING ------- //
wire [15:0] BUS_ADD;
wire BUS_RD, BUS_WR;
// ------- BUS SYGNALING ------- //
fx2_to_bus fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CS_FPGA()
);
// ------- USER MODULES ------- //
wire FIFO_NEAR_FULL,FIFO_FULL;
wire USB_READ;
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
assign USB_READ = FREAD & FSTROBE;
sram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR)
) sram_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(FDATA),
.FIFO_READ_NEXT_OUT(ARB_READY_OUT),
.FIFO_EMPTY_IN(!ARB_WRITE_OUT),
.FIFO_DATA(ARB_DATA_OUT),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR()
);
monopix_core i_monopix_core(
//local bus
.BUS_CLK(BUS_CLK),
.BUS_DATA(BUS_DATA),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_RST(BUS_RST),
//clocks
.CLK8(CLK8),
.CLK40(CLK40),
.CLK16(CLK16),
.CLK160(CLK160),
.CLK320(CLK320),
//fifo
.ARB_READY_OUT(ARB_READY_OUT),
.ARB_WRITE_OUT(ARB_WRITE_OUT),
.ARB_DATA_OUT(ARB_DATA_OUT),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
//LED
.LED(LED[4:0]),
.LEMO_RX(LEMO_RX),
.LEMO_TX(LEMO_TX), // TX[0] == RJ45 trigger clock output, TX[1] == RJ45 busy output
.RJ45_RESET(RJ45_RESET),
.RJ45_TRIGGER(RJ45_TRIGGER),
.SR_OUT(SR_OUT), //DIN4
.SR_IN(SR_IN), //DOUT11
.LDPIX(LDPIX), //DOUT15
.CKCONF(CKCONF), //DOUT10
.LDDAC(LDDAC), //DOUT12
.SR_EN(SR_EN), //DOUT13
.RESET(RESET), //DOUT14
.INJECTION(INJECTION),
.MONITOR(MONITOR), //DIN1
.CLK_BX(CLK_BX), //DOUT1
.READ(READ), //DOUT2
.FREEZE(FREEZE), //DOUT3
.nRST(nRST), //DOUT4
.EN_TEST_PATTERN(EN_TEST_PATTERN), //DOUT5
.RST_GRAY(RST_GRAY), //DOUT6
.EN_DRIVER(EN_DRIVER), //DOUT7
.EN_DATA_CMOS(EN_DATA_CMOS), //DOUT8
.CLK_OUT(CLK_OUT), //DOUT9
.TOKEN(TOKEN), //DIN2
.DATA(DATA), //DIN0
.DATA_LVDS(DATA_LVDS), //DIN8_LVDS0
.DEBUG(DEBUG) //nc
);
endmodule
|
//----------------------------------------------------------------------------
//-- Memoria ROM genérica
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Memoria con los siguientes parametros:
//-- * AW: Numero de bits de las direcciones
//-- * DW: Numero de bits de los datos
//-- * ROMFILE: Fichero a usar para cargar la memoria
//--
//-- Con este componente podemos hacer memorias rom de cualquier tamaño
//----------------------------------------------------------------------------
module genrom #( //-- Parametros
parameter AW = 6, //-- Bits de las direcciones (Adress width)
parameter DW = 8) //-- Bits de los datos (Data witdh)
( //-- Puertos
input clk, //-- Señal de reloj global
input wire [AW-1: 0] addr, //-- Direcciones
output reg [DW-1: 0] data); //-- Dato de salida
//-- Parametro: Nombre del fichero con el contenido de la ROM
parameter ROMFILE = "rom1.list";
//-- Calcular el numero de posiciones totales de memoria
localparam NPOS = 2 ** AW;
//-- Memoria
reg [DW-1: 0] rom [0: NPOS-1];
//-- Lectura de la memoria
always @(posedge clk) begin
data <= rom[addr];
end
//-- Cargar en la memoria el fichero ROMFILE
//-- Los valores deben estan dados en hexadecimal
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int n, m; int a[200000]; char tmp[200000]; int b[200000]; int bi; int c[200000]; int ci; int d[200000]; vector<int> dab; void calc() { int i, j; int cnt = 0; d[0] = -((1 << 30) - 1); ci = 0; for (i = 0; i < bi; i++) { if (b[i] == ((1 << 30) - 1)) cnt++; else { c[++ci] = cnt; d[ci] = b[i]; cnt = 0; } } c[++ci] = cnt; d[ci++] = ((1 << 30) - 1); for (i = 0; i < ci - 1; i++) { if (d[i + 1] - d[i] - 1 < c[i + 1]) { printf( Incorrect sequence ); exit(0); } } dab.clear(); for (i = 0; i < ci - 1; i++) { if (c[i + 1] == 0) continue; if (d[i] <= 0 && d[i + 1] <= 0) { for (j = d[i + 1] - c[i + 1]; j <= d[i + 1] - 1; j++) dab.push_back(j); } else if (d[i] >= 0 && d[i + 1] >= 0) { for (j = d[i] + 1; j <= d[i] + c[i + 1]; j++) dab.push_back(j); } else { if (min(abs(d[i + 1] - 1), abs(d[i] + 1)) * 2 + 1 >= c[i + 1]) { for (j = -(c[i + 1] - 1) / 2; j <= (c[i + 1] / 2); j++) dab.push_back(j); } else { int u = min(abs(d[i + 1] - 1), abs(d[i] + 1)); if (abs(d[i + 1] - 1) > abs(d[i] + 1)) { for (j = -u; j <= u; j++) dab.push_back(j); for (j = u + 1; j <= u + c[i + 1] - min(abs(d[i + 1] - 1), abs(d[i] + 1)) * 2 - 1; j++) dab.push_back(j); } else { for (j = -u - (c[i + 1] - min(abs(d[i + 1] - 1), abs(d[i] + 1)) * 2 - 1); j <= -u - 1; j++) dab.push_back(j); for (j = -u; j <= u; j++) dab.push_back(j); } } } } } int main() { int i, j, k; cin >> n >> m; for (i = 0; i < n; i++) { scanf( %s , tmp); if (tmp[0] == ? ) a[i] = ((1 << 30) - 1); else a[i] = atoi(tmp); } for (i = 0; i < m; i++) { bi = 0; for (j = i; j < n; j += m) { b[bi++] = a[j]; } calc(); int u = 0; for (j = i; j < n; j += m) { if (a[j] == ((1 << 30) - 1)) a[j] = dab[u++]; } } for (i = 0; i < n; i++) printf( %d , a[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; ifstream fin( test.in ); struct intr { int l, r, id; }; intr q[200005]; int p, n, qq; long long sol; int a[200005]; long long rez[200005]; int mp[5 * 200005]; bool cmp(intr &q1, intr &q2) { return (q1.r / p < q2.r / p || (q1.r / p == q2.r / p && q1.l < q2.l)); } void add(int x) { int v = mp[x]; sol = sol - 1LL * v * v * x; sol = sol + 1LL * (v + 1) * (v + 1) * x; mp[x]++; } void del(int x) { int v = mp[x]; sol = sol - 1LL * v * v * x; if (v >= 1) { sol = sol + 1LL * (v - 1) * (v - 1) * x; mp[x]--; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int i, lx, rx; cin >> n >> qq; for (i = 1; i <= n; i++) cin >> a[i]; p = sqrt(n); for (i = 1; i <= qq; i++) { cin >> q[i].l >> q[i].r; q[i].id = i; } sort(q + 1, q + qq + 1, cmp); lx = 1; rx = 0; sol = 0; for (i = 1; i <= qq; i++) { while (q[i].r > rx) add(a[++rx]); while (q[i].r < rx) del(a[rx--]); while (q[i].l > lx) del(a[lx++]); while (q[i].l < lx) add(a[--lx]); rez[q[i].id] = sol; } for (i = 1; i <= qq; i++) cout << rez[i] << n ; }
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire r1,r2;
wire g1,g2;
wire d1,d2;
wire a1,a2,r0;
wire [7:0] dataout;
two_phase_event_gen U_PORT1_EVENT_GEN (
.run(rst_async_n),
.req(r1),
.ack(a1)
);
two_phase_event_gen U_PORT2_EVENT_GEN (
.run(rst_async_n),
.req(r2),
.ack(a2)
);
arbitrer_r1_2ph U_ARBITER(
// Input ports (req/ack)
.r1(r1),
.a1(a1),
.r2(r2),
.a2(a2),
// Output ports
.g1(g1),
.d1(d1),
.g2(g2),
.d2(d2),
.rstn(rst_async_n)
);
selector_r1_2ph U_SELECTOR(
.r1(g1),
.a1(d1),
.r2(g2),
.a2(d2),
.datain1(8'hAA),
.datain2(8'h55),
.dataout(dataout),
.rstn(rst_async_n)
);
assign #12 d1 = g1;
assign #55 d2 = g2;
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
reg clk;
initial clk = 0;
always
#100 clk = ~clk;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n = 1'b0;
#5;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#200000;
$display("-I- Done !");
$finish;
end
// four_phase_assertion U_CHECKER0(.req(r0),.ack(a0),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER1(.req(r1),.ack(a1),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER2(.req(r2),.ack(a2),.rstn(rst_async_n));
// just for debug
assign input_port1_ongoing_req = r1 ^ a1;
assign input_port2_ongoing_req = r2 ^ a2;
assign output_port1_unstable = g1 ^ d1;
assign output_port2_unstable = g2 ^ d2;
assign error = output_port1_unstable & output_port2_unstable;
initial begin
#1;
@(posedge error);
$display("-E error found in protocol");
#100;
$finish;
end
endmodule // tb
|
#include <bits/stdc++.h> using namespace std; const int N = 700 + 5; int n, m, d[N], cnt[N][N]; bitset<N> adj[N]; long long ans; int main() { scanf( %d%d , &n, &m); for (int i = 0, u, v; i < m; i++) { scanf( %d%d , &u, &v); d[--u]++, d[--v]++; adj[u][v] = adj[v][u] = true; } for (int u = 0; u < n; u++) for (int v = u; v < n; v++) cnt[u][v] = cnt[v][u] = (adj[u] & adj[v]).count(); for (int u = 0; u < n; u++) for (int v = 0; v < n; v++) if (adj[u][v]) { for (int x = 0; x < n; x++) ans += 1LL * (u ^ x && v ^ x) * (cnt[u][x] - adj[x][v]) * (cnt[v][x] - adj[x][u]); ans -= cnt[u][v] * (d[u] - 2); } printf( %lld n , ans / 10); }
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_8_b2s_incr_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
reg [11:0] axaddr_incr;
reg [8:0] axlen_cnt;
reg next_pending_r;
wire [3:0] axsize_shift;
wire [11:0] axsize_mask;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// calculate cmd_byte_addr
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
end
endgenerate
assign axsize_shift = (1 << axsize[1:0]);
assign axsize_mask = ~(axsize_shift - 1'b1);
// Incremented version of axaddr
always @(posedge clk) begin
if (sel_first) begin
if(~next) begin
axaddr_incr <= axaddr[11:0] & axsize_mask;
end else begin
axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
end
end else if (next) begin
axaddr_incr <= axaddr_incr + axsize_shift;
end
end
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen;
next_pending_r <= (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= ((axlen_cnt - 1) >= 1);
end else begin
axlen_cnt <= 9'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = ((axlen_cnt - 1) >= 1);
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:57:55 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_stub.v
// Design : design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e6 + 3; const int INFI = 1e9 * 2; const long long LINFI = 1e17; const double pi = acos(-1.0); const double s2 = sqrt(2.0); const int N = 222; const int M = 11; const int move[8][2] = {1, 0, -1, 0, 0, 1, 0, -1, 1, 1, 1, -1, -1, 1, -1, -1}; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int a, b, c, d, p, q, m, x, y; while (scanf( %d%d%d%d , &a, &b, &c, &d) != EOF) { m = c * d / gcd(c, d); a *= m; b *= m; x = a / c; y = b / d; if (x >= y) { q = a; p = a - y * c; } else { q = b; p = b - x * d; } m = gcd(p, q); q /= m; p /= m; printf( %d/%d n , p, q); } return 0; }
|
/*
* Copyright (c) 1998 Purdea Andrei ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This demonstrates proper handling of leading zeroes, and the %0b format.
*/
module main();
initial
begin
$display("|%b|", 10'b11);
$display("|%0b|", 10'b11);
$display("|%b|", 10'b0);
$display("|%0b|", 10'b0);
$finish ;
end
endmodule
|
module quadrature_decoder(
direction_o,
count_pulse_o,
error_o,
clk,
enable_i,
reset_i,
quadA_i,
quadB_i,
quadA,
quadA_old,
quadB,
quadB_old
);
output direction_o, count_pulse_o, error_o, quadA, quadA_old, quadB, quadB_old;
input clk, enable_i, reset_i, quadA_i, quadB_i;
wire clk_i, enable_i, reset_i, quadA_i, quadB_i;
reg direction_o, count_pulse_o, error_o;
reg quadA, quadA_old, quadB, quadB_old;
always @(posedge clk) begin
if (reset_i) begin
quadA_old <= 0;
quadB_old <= 0;
quadA <= 0;
quadB <= 0;
direction_o <= 0;
count_pulse_o <= 0;
error_o <= 0;
end
if (enable_i) begin
count_pulse_o <= quadA^quadA_old^quadB^quadB_old;
error_o <= quadA_i^quadA_old && quadB_i^quadB_old;
direction_o <= quadA_i & !quadB_i & !quadA_old & !quadB_old
| quadA_i & quadB_i & quadA_old & !quadB_old
| !quadA_i & quadB_i & quadA_old & quadB_old
| !quadA_i & !quadB_i & !quadA_old & quadB_old;
quadA_old <= quadA;
quadB_old <= quadB;
quadA <= quadA_i;
quadB <= quadB_i;
end
end
/*
always @(quadA_i or quadB_i) begin
end
//This section is Asynchronous
/*
always @(quadA_i) begin
if ( ( quadA_i && quadB_i ) || ( !quadA_i && !quadB_i ) ) begin
direction_o = 0;
end else begin
direction_o = 1;
end
count_pulse_o <= 1;
end
always @(quadB_i) begin
if ( ( quadB_i && !quadA_i ) || ( !quadB_i && quadA_i ) ) begin
direction_o = 0;
end else begin
direction_o = 1;
end
count_pulse_o <= 1;
end
/*
always @(posedge count_pulse_o) begin
count_o <= count_o + direction_o;
count_pulse_o <= 0;
end
*/
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Sat Mar 15 16:19:54 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_1/part_2/ip/clk_base/clk_base_stub.v
// Design : clk_base
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_base(clk_100MHz, clk_250MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_100MHz,clk_250MHz,locked" */;
input clk_100MHz;
output clk_250MHz;
output locked;
endmodule
|
//#############################################################################
//# Purpose: MIO Receiver IO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module mrx_io #(parameter IOW = 64, // IO width
parameter TARGET = "GENERIC" // target selector
)
( //reset, clk, cfg
input nreset, // async active low reset
input ddr_mode, // select between sdr/ddr data
input [1:0] iowidth, // dynamically configured io bus width
//IO interface
input rx_clk, // clock for IO
input [IOW-1:0] rx_packet, // data for IO
input rx_access, // access signal for IO
//FIFO interface (core side)
output io_access,// fifo write
output reg [7:0] io_valid, // fifo byte valid
output [63:0] io_packet // fifo packet
);
// local wires
wire [IOW-1:0] ddr_data;
wire io_nreset;
wire [63:0] io_data;
wire [63:0] mux_data;
wire [7:0] data_select;
wire [7:0] valid_input;
wire [7:0] valid_next;
wire [IOW/2-1:0] ddr_even;
wire [IOW/2-1:0] ddr_odd;
wire io_frame;
wire dmode8;
wire dmode16;
wire dmode32;
wire dmode64;
wire reload;
wire transfer_done;
wire transfer_active;
reg [63:0] shiftreg;
reg [IOW-1:0] sdr_data;
reg [1:0] rx_access_reg;
//########################################
//# STATE MACHINE
//########################################
assign dmode8 = (iowidth[1:0]==2'b00);
assign dmode16 = ((iowidth[1:0]==2'b01) & ~ddr_mode) |
(iowidth[1:0]==2'b00) & ddr_mode;
assign dmode32 = ((iowidth[1:0]==2'b10) & ~ddr_mode) |
(iowidth[1:0]==2'b01) & ddr_mode;
assign dmode64 = ((iowidth[1:0]==2'b11) & ~ddr_mode) |
(iowidth[1:0]==2'b10) & ddr_mode;
assign valid_input[7:0] = dmode8 ? 8'b00000001 :
dmode16 ? 8'b00000011 :
dmode32 ? 8'b00001111 :
8'b11111111;
assign valid_next[7:0] = dmode8 ? {io_valid[6:0],1'b1} :
dmode16 ? {io_valid[5:0],2'b11} :
dmode32 ? {io_valid[3:0],4'b1111} :
8'b11111111;
//Keep track of valid bytes in shift register
always @ (posedge rx_clk or negedge io_nreset)
if(!io_nreset)
io_valid[7:0] <= 8'b0;
else if(reload)
io_valid[7:0] <= valid_input[7:0];
else if(io_frame)
io_valid[7:0] <= valid_next[7:0];
else
io_valid[7:0] <= 8'b0;
assign reload = (io_frame & transfer_done) | // continuing stream
(io_frame & ~transfer_active); // new frame
assign transfer_active = |io_valid[7:0];
assign transfer_done = &io_valid[7:0];
//Access signal for FIFO
assign io_access = transfer_done | // full vector
(~io_frame & transfer_active); // partial vector
//########################################
//# DATA CAPTURE
//########################################
// DDR
oh_iddr #(.DW(IOW/2))
data_iddr(.q1 (ddr_even[IOW/2-1:0]),
.q2 (ddr_odd[IOW/2-1:0]),
.clk (rx_clk),
.ce (rx_access),
.din (rx_packet[IOW/2-1:0]));
assign ddr_data[IOW-1:0] = (iowidth[1:0]==2'b00) ? {ddr_odd[3:0],ddr_even[3:0]} :
(iowidth[1:0]==2'b01) ? {ddr_odd[7:0],ddr_even[7:0]} :
(iowidth[1:0]==2'b10) ? {ddr_odd[15:0],ddr_even[15:0]} :
{ddr_odd[31:0],ddr_even[31:0]};
// SDR
always @ (posedge rx_clk)
if(rx_access)
sdr_data[IOW-1:0] <= rx_packet[IOW-1:0];
// select between ddr/sdr data
assign io_data[IOW-1:0] = ddr_mode ? ddr_data[IOW-1:0] :
sdr_data[IOW-1:0];
//align data based on IOW
assign mux_data[IOW-1:0] = dmode8 ? {(8){io_data[7:0]}} :
dmode16 ? {(4){io_data[15:0]}} :
dmode32 ? {(2){io_data[31:0]}} :
io_data[IOW-1:0];
// pipeline access signal
always @ (posedge rx_clk or negedge io_nreset)
if(!io_nreset)
rx_access_reg[1:0] <= 1'b0;
else
rx_access_reg[1:0] <= {rx_access_reg[0],rx_access};
assign io_frame = ddr_mode ? rx_access_reg[1] :
rx_access_reg[0];
//########################################
//# PACKETIZER
//########################################
//detect selection based on valid pattern edge
assign data_select[7:0] = reload ? valid_input[7:0] :
valid_next[7:0] & ~io_valid[7:0];
integer i;
always @ (posedge rx_clk)
for (i=0;i<8;i=i+1)
shiftreg[i*8+:8] <= data_select[i] ? mux_data[i*8+:8] : shiftreg[i*8+:8];
assign io_packet[63:0] = shiftreg[63:0];
//########################################
//# SYNCHRONIZERS
//########################################
oh_rsync oh_rsync(.nrst_out (io_nreset),
.clk (rx_clk),
.nrst_in (nreset));
endmodule // mrx_io
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 200100; const long long INF = 2000000100; const long long MOD = 998244353; long long N, S[MAXN], P[MAXN]; long long B[MAXN]; void update(int ind, long long v) { for (int i = ind; i <= N; i += (i & -i)) { B[i] += v; } } long long query(int ind) { if (ind == 0) return 0; long long s = 0; for (int i = ind; i > 0; i -= (i & -i)) { s += B[i]; } return s; } int main() { ios_base::sync_with_stdio(0); cin >> N; for (int i = 0; i < N; i++) cin >> S[i]; for (int i = 1; i <= N; i++) update(i, i); for (int i = N - 1; i >= 0; i--) { long long a = 1, b = N, c; long long ans = -39; while (a <= b) { c = (a + b) / 2; if (query(c - 1) > S[i]) { b = c - 1; } else { ans = c; a = c + 1; } } P[i] = ans; update(ans, -ans); } for (int i = 0; i < N; i++) cout << P[i] << (i == N - 1 ? n : ); }
|
#include <bits/stdc++.h> using namespace std; long long rate[2000002]; int n, k; int main() { cin >> n >> k; for (int i = 0; i < n; i++) cin >> rate[i]; long long p = 0, c; int del = 0; vector<int> vec; for (int i = 1; i <= n; i++) { if (i - del > 1) c = (-rate[i - 1] * ((n - del) - (i - del))) * (i - del - 1) + p; else c = 0; if (c < k) del++, vec.push_back(i); else p += rate[i - 1] * (i - del - 1); } for (int i = 0; i < vec.size(); i++) cout << vec[i] << endl; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define mp make_pair #define fi first #define se second #define pb push_back #define FOR(i,a,b) for(int i=a;i<=b;i++) #define FORD(i,a,b) for(int i=a;i>=b;i--) #define faster() ios_base::sync_with_stdio(0); cin.tie(NULL);cout.tie(NULL); typedef long long ll; typedef vector<int> vi; typedef vector<ll> vll; int main() { faster(); int t; cin>>t; while(t--) { int a[4]; FOR(i,0,3) cin>>a[i]; int max1=max(a[0],a[1]),max2=max(a[2],a[3]); sort(a,a+4); if(max1>max2 && max1==a[3] && max2==a[2]) cout<< YES <<endl; else if(max1<max2 && max2==a[3] && max1==a[2]) cout<< YES <<endl; else cout<< NO <<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bitset<22500> a, b, c, e; int n, m, k; char s[100010]; int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < n; i++) { scanf( %s , s); for (int j = 0; j < m; j++) { if (s[j] != # ) a[i * m + j] = 1; if (s[j] == E ) e[i * m + j] = 1; if (s[j] == # ) b[i * m + j] = 1; } } scanf( %s , s); c = a; for (int i = 0; i < k; i++) { if (c == e) { printf( %d n , i); return 0; } if (s[i] == U ) c = ((c >> m) & a) | (c & (b << m)); if (s[i] == D ) c = ((c << m) & a) | (c & (b >> m)); if (s[i] == L ) c = ((c >> 1) & a) | (c & (b << 1)); if (s[i] == R ) c = ((c << 1) & a) | (c & (b >> 1)); } printf( %d n , c == e ? k : -1); return 0; }
|
#include <bits/stdc++.h> int product(long long a) { int maxi = 0, mini = 9, x, ans; long long temp = a; while (temp) { x = temp % 10; if (x < mini) mini = x; if (x > maxi) maxi = x; temp /= 10; } if (mini == 0) return 0; ans = mini * maxi; return ans; } using namespace std; int main() { ios_base::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); long long a, k, ans; int t; cin >> t; while (t--) { cin >> a >> k; k--; while (k--) { if (product(a) == 0) break; else { a += product(a); } } cout << a << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n1, n2, k1, k2; cin >> n1 >> n2 >> k1 >> k2; if (n1 > n2) cout << First << endl; else if (n1 == n2) cout << Second << endl; else cout << Second << endl; return 0; }
|
module premuat1_32(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
output signed [15:0] o_8;
output signed [15:0] o_9;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
output signed [15:0] o_16;
output signed [15:0] o_17;
output signed [15:0] o_18;
output signed [15:0] o_19;
output signed [15:0] o_20;
output signed [15:0] o_21;
output signed [15:0] o_22;
output signed [15:0] o_23;
output signed [15:0] o_24;
output signed [15:0] o_25;
output signed [15:0] o_26;
output signed [15:0] o_27;
output signed [15:0] o_28;
output signed [15:0] o_29;
output signed [15:0] o_30;
output signed [15:0] o_31;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [15:0] o1;
reg signed [15:0] o2;
reg signed [15:0] o3;
reg signed [15:0] o4;
reg signed [15:0] o5;
reg signed [15:0] o6;
reg signed [15:0] o7;
reg signed [15:0] o8;
reg signed [15:0] o9;
reg signed [15:0] o10;
reg signed [15:0] o11;
reg signed [15:0] o12;
reg signed [15:0] o13;
reg signed [15:0] o14;
reg signed [15:0] o15;
reg signed [15:0] o16;
reg signed [15:0] o17;
reg signed [15:0] o18;
reg signed [15:0] o19;
reg signed [15:0] o20;
reg signed [15:0] o21;
reg signed [15:0] o22;
reg signed [15:0] o23;
reg signed [15:0] o24;
reg signed [15:0] o25;
reg signed [15:0] o26;
reg signed [15:0] o27;
reg signed [15:0] o28;
reg signed [15:0] o29;
reg signed [15:0] o30;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2 ;
o2 =i_4 ;
o3 =i_6 ;
o4 =i_8 ;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_16;
o9 =i_18;
o10=i_20;
o11=i_22;
o12=i_24;
o13=i_26;
o14=i_28;
o15=i_30;
o16=i_1 ;
o17=i_3 ;
o18=i_5 ;
o19=i_7 ;
o20=i_9 ;
o21=i_11;
o22=i_13;
o23=i_15;
o24=i_17;
o25=i_19;
o26=i_21;
o27=i_23;
o28=i_25;
o29=i_27;
o30=i_29;
end
else
begin
o1 =i_16;
o2 =i_1;
o3 =i_17;
o4 =i_2;
o5 =i_18;
o6 =i_3;
o7 =i_19;
o8 =i_4;
o9 =i_20;
o10=i_5;
o11=i_21;
o12=i_6;
o13=i_22;
o14=i_7;
o15=i_23;
o16=i_8;
o17=i_24;
o18=i_9;
o19=i_25;
o20=i_10;
o21=i_26;
o22=i_11;
o23=i_27;
o24=i_12;
o25=i_28;
o26=i_13;
o27=i_29;
o28=i_14;
o29=i_30;
o30=i_15;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=enable?o15:i_15;
assign o_16=enable?o16:i_16;
assign o_17=enable?o17:i_17;
assign o_18=enable?o18:i_18;
assign o_19=enable?o19:i_19;
assign o_20=enable?o20:i_20;
assign o_21=enable?o21:i_21;
assign o_22=enable?o22:i_22;
assign o_23=enable?o23:i_23;
assign o_24=enable?o24:i_24;
assign o_25=enable?o25:i_25;
assign o_26=enable?o26:i_26;
assign o_27=enable?o27:i_27;
assign o_28=enable?o28:i_28;
assign o_29=enable?o29:i_29;
assign o_30=enable?o30:i_30;
assign o_31=i_31;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_2_V
`define SKY130_FD_SC_LP__OR4BB_2_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4bb_2 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4bb_2 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_2_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; T f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } int max(int x, int y) { return x > y ? x : y; } int min(int x, int y) { return x < y ? x : y; } char s[500010], t[500010]; int m, n, cnt0, cnt1; int nxt[500010], ans[500010]; void Get_Next() { nxt[0] = -1; int j = 0, k = -1; while (j <= n) { if (k == -1 || t[j] == t[k]) nxt[++j] = ++k; else k = nxt[k]; } } bool fl; int main() { scanf( %s , s), scanf( %s , t), m = strlen(s), n = strlen(t); t[n] = $ ; for (int i = 1; i <= m; ++i) if (s[i - 1] == 0 ) cnt0++; else cnt1++; Get_Next(); for (int i = 0; i < n; ++i) { if (t[i] == 0 && cnt0 == 0) { fl = 1; break; } if (t[i] == 1 && cnt1 == 0) { fl = 1; break; } ans[i] = t[i] - 0 ; if (t[i] == 0 ) cnt0--; else cnt1--; } if (fl) { cout << s << n ; return 0; } int now = n, kk = n; while (1) { if (now == n) now = nxt[n]; if (t[now] == 0 && cnt0 == 0) { for (int i = 1; i <= cnt1; ++i) ans[kk + i - 1] = 1; break; } if (t[now] == 1 && cnt1 == 0) { for (int i = 1; i <= cnt0; ++i) ans[kk + i - 1] = 0; break; } ans[kk++] = t[now] - 0 ; if (t[now] == 0 ) cnt0--; else cnt1--; now++; if (kk > m) break; } for (int i = 0; i < m; ++i) cout << ans[i]; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; double EPS = 1e-9; int INF = 2000000000; long long INFF = 8000000000000000000LL; double PI = acos(-1); int dirx[8] = {-1, 0, 0, 1, -1, -1, 1, 1}; int diry[8] = {0, 1, -1, 0, -1, 1, -1, 1}; inline string IntToString(int a) { char x[100]; sprintf(x, %d , a); string s = x; return s; } inline int StringToInt(string a) { char x[100]; int res; strcpy(x, a.c_str()); sscanf(x, %d , &res); return res; } inline string GetString(void) { char x[1000005]; scanf( %s , x); string s = x; return s; } inline string uppercase(string s) { int n = (int)s.size(); for (int(i) = (0); (i) < (n); ++(i)) if (s[i] >= a && s[i] <= z ) s[i] = s[i] - a + A ; return s; } inline string lowercase(string s) { int n = (int)s.size(); for (int(i) = (0); (i) < (n); ++(i)) if (s[i] >= A && s[i] <= Z ) s[i] = s[i] - A + a ; return s; } inline void OPEN(string s) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } vector<int> angka; int n, data[2005]; long long dewa[2005]; long long MOD = 1000000007; bool sudah[2005]; int to[2005]; int conn; int pisah; long long risan; long long C[2005][2005]; int main() { scanf( %d , &n); for (int(i) = (1); (i) <= (n); ++(i)) { scanf( %d , &data[i]); to[i] = data[i]; } for (int(i) = (0); (i) <= (n); ++(i)) { C[i][0] = C[i][i] = 1; for (int(j) = (1); (j) <= (i - 1); ++(j)) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } dewa[1] = 0; dewa[2] = 1; dewa[0] = 1; for (int(i) = (3); (i) <= (n); ++(i)) { dewa[i] = (i - 1) * (dewa[i - 1] + dewa[i - 2]); dewa[i] %= MOD; } memset(sudah, 0, sizeof(sudah)); for (int(i) = (1); (i) <= (n); ++(i)) { if (to[i] == -1) continue; int x = i; while (x != -1) { if (sudah[x]) goto hell; sudah[x] = 1; x = to[x]; if (x == i) goto hell; } ++conn; hell:; } for (int(i) = (1); (i) <= (n); ++(i)) if (!sudah[i]) ++pisah; for (int(i) = (0); (i) <= (conn); ++(i)) { long long pos = (C[conn][i] * dewa[i + pisah]) % MOD; risan = (risan + pos) % MOD; } printf( %d n , (int)risan); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, prnt[N]; long long k; long long sum = 0; vector<int> g[N]; int sz[N]; void DFS(int node, int prnt) { sz[node] = 1; for (int i = 0; i < (int)g[node].size(); i++) { if (g[node][i] == prnt) continue; DFS(g[node][i], node); sz[node] += sz[g[node][i]]; } } int get_centroid(int node, int prnt) { for (int i = 0; i < (int)g[node].size(); i++) { if (g[node][i] == prnt) continue; if (sz[g[node][i]] > n / 2) return get_centroid(g[node][i], node); } return node; } int Idx, cur[N], in[N], depth[N], val[N], root; bool taken[N]; void init(int node) { cur[node] = Idx; val[Idx]++; sum += depth[node]; for (int i = 0; i < (int)g[node].size(); i++) { if (g[node][i] == prnt[node]) continue; depth[g[node][i]] = depth[node] + 1; prnt[g[node][i]] = node; init(g[node][i]); in[node]++; } } vector<int> has[N]; priority_queue<pair<int, int> > q[N]; set<pair<int, int> > st[N]; set<pair<int, int> >::iterator it, it2; vector<pair<int, int> > ans; priority_queue<pair<int, int> > pq, q2; void finish(int node) { it2 = st[cur[node]].find(make_pair(depth[node], node)); if (it2 != st[cur[node]].end()) st[cur[node]].erase(it2); int idx = -1; for (int i = 0; i < (int)g[node].size(); i++) { if (g[node][i] == prnt[node]) continue; if (idx == -1 || (int)has[g[node][i]].size() > (int)has[g[node][idx]].size()) { idx = i; } } if (idx != -1) swap(has[node], has[g[node][idx]]); for (int i = 0; i < (int)g[node].size(); i++) { if (i == idx || g[node][i] == prnt[node]) continue; while ((int)has[g[node][i]].size() > 0) { has[node].push_back(has[g[node][i]].back()); has[g[node][i]].pop_back(); } } if (!taken[node]) has[node].push_back(node); if (prnt[node] == root) return; in[prnt[node]]--; if ((int)has[node].size() > 0) q[prnt[node]].push(make_pair((int)has[node].size(), node)); if (in[prnt[node]] == 0) { st[cur[node]].insert(make_pair(depth[prnt[node]], prnt[node])); } } vector<int> lll; int main() { scanf( %d%lld , &n, &k); for (int u, v, i = 0; i < n - 1; i++) { scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } DFS(1, -1); root = get_centroid(1, -1); prnt[root] = -1; for (int i = 0; i < (int)g[root].size(); i++) { Idx = i; prnt[g[root][i]] = root; depth[g[root][i]] = 1; init(g[root][i]); in[root]++; pq.push(make_pair(val[Idx], Idx)); } if (k > sum || (sum % 2) != (k % 2)) { puts( NO ); return 0; } for (int i = 1; i <= n; i++) { if (in[i] == 0) { lll.push_back(i); } } for (int i = 0; i < (int)lll.size(); i++) { finish(lll[i]); } int tmp1, tmp2, tmp3, tmp4; long long needed; while (sum > k && (int)pq.size() > 0) { tmp1 = pq.top().second; pq.pop(); if (val[tmp1] < 2) break; needed = (sum - k) / 2; assert((int)st[tmp1].size() > 0); while (true) { it = st[tmp1].end(); it--; tmp2 = it->second; if ((long long)it->first > needed) { finish(tmp2); continue; } if ((int)q[tmp2].size() > 1) { tmp3 = q[tmp2].top().second; q[tmp2].pop(); tmp4 = q[tmp2].top().second; q[tmp2].pop(); ans.push_back(make_pair(has[tmp3].back(), has[tmp4].back())); taken[has[tmp3].back()] = taken[has[tmp4].back()] = true; has[tmp3].pop_back(); has[tmp4].pop_back(); if ((int)has[tmp3].size() > 0) q[tmp2].push(make_pair((int)has[tmp3].size(), tmp3)); if ((int)has[tmp4].size() > 0) q[tmp2].push(make_pair((int)has[tmp4].size(), tmp4)); sum -= (long long)2 * depth[tmp2]; break; } if (taken[tmp2] || (int)q[tmp2].size() == 0) { finish(tmp2); continue; } tmp3 = q[tmp2].top().second; q[tmp2].pop(); ans.push_back(make_pair(tmp2, has[tmp3].back())); taken[tmp2] = true; taken[has[tmp3].back()] = true; has[tmp3].pop_back(); finish(tmp2); sum -= (long long)2 * depth[tmp2]; break; } val[tmp1] -= 2; if (val[tmp1] > 0) pq.push(make_pair(val[tmp1], tmp1)); } for (int i = 1; i <= n; i++) has[i].clear(); for (int i = 1; i <= n; i++) { if (i != root && !taken[i]) has[cur[i]].push_back(i); } for (int i = 0; i < (int)g[root].size(); i++) { if ((int)has[i].size() > 0) q2.push(make_pair((int)has[i].size(), i)); } while ((int)q2.size() > 1) { tmp1 = q2.top().second; q2.pop(); tmp2 = q2.top().second; q2.pop(); ans.push_back(make_pair(has[tmp1].back(), has[tmp2].back())); has[tmp1].pop_back(); has[tmp2].pop_back(); if ((int)has[tmp1].size() > 0) q2.push(make_pair((int)has[tmp1].size(), tmp1)); if ((int)has[tmp2].size() > 0) q2.push(make_pair((int)has[tmp2].size(), tmp2)); } assert((int)q2.size() > 0); tmp1 = q2.top().second; tmp1 = has[tmp1].back(); ans.push_back(make_pair(root, tmp1)); if (sum == k) { puts( YES ); assert((int)ans.size() == n / 2); for (int i = 0; i < (int)ans.size(); i++) { printf( %d %d n , ans[i].first, ans[i].second); } } else puts( NO ); return 0; }
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//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
//Date : Tue Sep 19 00:28:00 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target bd_c3fe.bd
//Design : bd_c3fe
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "bd_c3fe,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_c3fe,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "zynq_design_1_system_ila_0_0.hwdef" *)
module bd_c3fe
(SLOT_0_AXI_araddr,
SLOT_0_AXI_arready,
SLOT_0_AXI_arvalid,
SLOT_0_AXI_awaddr,
SLOT_0_AXI_awready,
SLOT_0_AXI_awvalid,
SLOT_0_AXI_bready,
SLOT_0_AXI_bresp,
SLOT_0_AXI_bvalid,
SLOT_0_AXI_rdata,
SLOT_0_AXI_rready,
SLOT_0_AXI_rresp,
SLOT_0_AXI_rvalid,
SLOT_0_AXI_wdata,
SLOT_0_AXI_wready,
SLOT_0_AXI_wstrb,
SLOT_0_AXI_wvalid,
clk,
resetn);
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arready;
input SLOT_0_AXI_arvalid;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awready;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_bready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input [31:0]SLOT_0_AXI_rdata;
input SLOT_0_AXI_rready;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input [31:0]SLOT_0_AXI_wdata;
input SLOT_0_AXI_wready;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input clk;
input resetn;
wire [8:0]Conn_ARADDR;
wire Conn_ARREADY;
wire Conn_ARVALID;
wire [8:0]Conn_AWADDR;
wire Conn_AWREADY;
wire Conn_AWVALID;
wire Conn_BREADY;
wire [1:0]Conn_BRESP;
wire Conn_BVALID;
wire [31:0]Conn_RDATA;
wire Conn_RREADY;
wire [1:0]Conn_RRESP;
wire Conn_RVALID;
wire [31:0]Conn_WDATA;
wire Conn_WREADY;
wire [3:0]Conn_WSTRB;
wire Conn_WVALID;
wire clk_1;
wire [1:0]net_slot_0_axi_ar_cnt;
wire [1:0]net_slot_0_axi_ar_ctrl;
wire [8:0]net_slot_0_axi_araddr;
wire net_slot_0_axi_arready;
wire net_slot_0_axi_arvalid;
wire [1:0]net_slot_0_axi_aw_cnt;
wire [1:0]net_slot_0_axi_aw_ctrl;
wire [8:0]net_slot_0_axi_awaddr;
wire net_slot_0_axi_awready;
wire net_slot_0_axi_awvalid;
wire [1:0]net_slot_0_axi_b_cnt;
wire [1:0]net_slot_0_axi_b_ctrl;
wire net_slot_0_axi_bready;
wire [1:0]net_slot_0_axi_bresp;
wire net_slot_0_axi_bvalid;
wire [1:0]net_slot_0_axi_r_cnt;
wire [1:0]net_slot_0_axi_r_ctrl;
wire [31:0]net_slot_0_axi_rdata;
wire net_slot_0_axi_rready;
wire [1:0]net_slot_0_axi_rresp;
wire net_slot_0_axi_rvalid;
wire [1:0]net_slot_0_axi_w_ctrl;
wire [31:0]net_slot_0_axi_wdata;
wire net_slot_0_axi_wready;
wire [3:0]net_slot_0_axi_wstrb;
wire net_slot_0_axi_wvalid;
wire resetn_1;
assign Conn_ARADDR = SLOT_0_AXI_araddr[8:0];
assign Conn_ARREADY = SLOT_0_AXI_arready;
assign Conn_ARVALID = SLOT_0_AXI_arvalid;
assign Conn_AWADDR = SLOT_0_AXI_awaddr[8:0];
assign Conn_AWREADY = SLOT_0_AXI_awready;
assign Conn_AWVALID = SLOT_0_AXI_awvalid;
assign Conn_BREADY = SLOT_0_AXI_bready;
assign Conn_BRESP = SLOT_0_AXI_bresp[1:0];
assign Conn_BVALID = SLOT_0_AXI_bvalid;
assign Conn_RDATA = SLOT_0_AXI_rdata[31:0];
assign Conn_RREADY = SLOT_0_AXI_rready;
assign Conn_RRESP = SLOT_0_AXI_rresp[1:0];
assign Conn_RVALID = SLOT_0_AXI_rvalid;
assign Conn_WDATA = SLOT_0_AXI_wdata[31:0];
assign Conn_WREADY = SLOT_0_AXI_wready;
assign Conn_WSTRB = SLOT_0_AXI_wstrb[3:0];
assign Conn_WVALID = SLOT_0_AXI_wvalid;
assign clk_1 = clk;
assign resetn_1 = resetn;
bd_c3fe_g_inst_0 g_inst
(.aclk(clk_1),
.aresetn(resetn_1),
.m_slot_0_axi_ar_cnt(net_slot_0_axi_ar_cnt),
.m_slot_0_axi_araddr(net_slot_0_axi_araddr),
.m_slot_0_axi_arready(net_slot_0_axi_arready),
.m_slot_0_axi_arvalid(net_slot_0_axi_arvalid),
.m_slot_0_axi_aw_cnt(net_slot_0_axi_aw_cnt),
.m_slot_0_axi_awaddr(net_slot_0_axi_awaddr),
.m_slot_0_axi_awready(net_slot_0_axi_awready),
.m_slot_0_axi_awvalid(net_slot_0_axi_awvalid),
.m_slot_0_axi_b_cnt(net_slot_0_axi_b_cnt),
.m_slot_0_axi_bready(net_slot_0_axi_bready),
.m_slot_0_axi_bresp(net_slot_0_axi_bresp),
.m_slot_0_axi_bvalid(net_slot_0_axi_bvalid),
.m_slot_0_axi_r_cnt(net_slot_0_axi_r_cnt),
.m_slot_0_axi_rdata(net_slot_0_axi_rdata),
.m_slot_0_axi_rready(net_slot_0_axi_rready),
.m_slot_0_axi_rresp(net_slot_0_axi_rresp),
.m_slot_0_axi_rvalid(net_slot_0_axi_rvalid),
.m_slot_0_axi_wdata(net_slot_0_axi_wdata),
.m_slot_0_axi_wready(net_slot_0_axi_wready),
.m_slot_0_axi_wstrb(net_slot_0_axi_wstrb),
.m_slot_0_axi_wvalid(net_slot_0_axi_wvalid),
.slot_0_axi_araddr(Conn_ARADDR),
.slot_0_axi_arready(Conn_ARREADY),
.slot_0_axi_arvalid(Conn_ARVALID),
.slot_0_axi_awaddr(Conn_AWADDR),
.slot_0_axi_awready(Conn_AWREADY),
.slot_0_axi_awvalid(Conn_AWVALID),
.slot_0_axi_bready(Conn_BREADY),
.slot_0_axi_bresp(Conn_BRESP),
.slot_0_axi_bvalid(Conn_BVALID),
.slot_0_axi_rdata(Conn_RDATA),
.slot_0_axi_rready(Conn_RREADY),
.slot_0_axi_rresp(Conn_RRESP),
.slot_0_axi_rvalid(Conn_RVALID),
.slot_0_axi_wdata(Conn_WDATA),
.slot_0_axi_wready(Conn_WREADY),
.slot_0_axi_wstrb(Conn_WSTRB),
.slot_0_axi_wvalid(Conn_WVALID));
bd_c3fe_ila_lib_0 ila_lib
(.clk(clk_1),
.probe0(net_slot_0_axi_ar_cnt),
.probe1(net_slot_0_axi_araddr),
.probe10(net_slot_0_axi_wstrb),
.probe11(net_slot_0_axi_aw_ctrl),
.probe12(net_slot_0_axi_w_ctrl),
.probe13(net_slot_0_axi_b_ctrl),
.probe14(net_slot_0_axi_ar_ctrl),
.probe15(net_slot_0_axi_r_ctrl),
.probe2(net_slot_0_axi_aw_cnt),
.probe3(net_slot_0_axi_awaddr),
.probe4(net_slot_0_axi_b_cnt),
.probe5(net_slot_0_axi_bresp),
.probe6(net_slot_0_axi_r_cnt),
.probe7(net_slot_0_axi_rdata),
.probe8(net_slot_0_axi_rresp),
.probe9(net_slot_0_axi_wdata));
bd_c3fe_slot_0_ar_0 slot_0_ar
(.In0(net_slot_0_axi_arvalid),
.In1(net_slot_0_axi_arready),
.dout(net_slot_0_axi_ar_ctrl));
bd_c3fe_slot_0_aw_0 slot_0_aw
(.In0(net_slot_0_axi_awvalid),
.In1(net_slot_0_axi_awready),
.dout(net_slot_0_axi_aw_ctrl));
bd_c3fe_slot_0_b_0 slot_0_b
(.In0(net_slot_0_axi_bvalid),
.In1(net_slot_0_axi_bready),
.dout(net_slot_0_axi_b_ctrl));
bd_c3fe_slot_0_r_0 slot_0_r
(.In0(net_slot_0_axi_rvalid),
.In1(net_slot_0_axi_rready),
.dout(net_slot_0_axi_r_ctrl));
bd_c3fe_slot_0_w_0 slot_0_w
(.In0(net_slot_0_axi_wvalid),
.In1(net_slot_0_axi_wready),
.dout(net_slot_0_axi_w_ctrl));
endmodule
|
Require Import VPHL.PrImp.
(* Require Import Sf.Maps. *)
Print aeval.
(* aeval = *)
(* fix aeval (a : aexp) (st : state) {struct a} : nat := *)
(* match a with *)
(* | ANum n => n *)
(* | AId x => fst st x *)
(* | APlus a1 a2 => (aeval a1 st + aeval a2 st)%nat *)
(* | AMinus a1 a2 => (aeval a1 st - aeval a2 st)%nat *)
(* | AMult a1 a2 => (aeval a1 st * aeval a2 st)%nat *)
(* end *)
(* : aexp -> state -> nat *)
Print aid.
(* Inductive aid : Set := Aid : nat -> aid *)
Print aexp.
(* Inductive aexp : Set := *)
(* ANum : nat -> aexp *)
(* | AId : aid -> aexp *)
(* | APlus : aexp -> aexp -> aexp *)
(* | AMinus : aexp -> aexp -> aexp *)
(* | AMult : aexp -> aexp -> aexp *)
Print bexp.
(* Inductive bexp : Set := *)
(* BTrue : bexp *)
(* | BFalse : bexp *)
(* | BId : bid -> bexp *)
(* | BEq : aexp -> aexp -> bexp *)
(* | BLe : aexp -> aexp -> bexp *)
(* | BNot : bexp -> bexp *)
(* | BAnd : bexp -> bexp -> bexp *)
Print com.
(* Inductive com : Set := *)
(* Skip : com *)
(* | Assign : aid -> aexp -> com *)
(* | BAssign : bid -> bexp -> com *)
(* | Seq : com -> com -> com *)
(* | If : bid -> com -> com -> com *)
(* | While : bid -> com -> com *)
(* | Toss : forall p : R, 0 < p < 1 -> aid -> com *)
(* | BToss : forall p : R, 0 < p < 1 -> bid -> com *)
Print aeval.
(* aeval = *)
(* fix aeval (a : aexp) (st : state) {struct a} : nat := *)
(* match a with *)
(* | ANum n => n *)
(* | AId x => fst st x *)
(* | APlus a1 a2 => (aeval a1 st + aeval a2 st)%nat *)
(* | AMinus a1 a2 => (aeval a1 st - aeval a2 st)%nat *)
(* | AMult a1 a2 => (aeval a1 st * aeval a2 st)%nat *)
(* end *)
(* : aexp -> state -> nat *)
Print state.
(* state = ((aid -> nat) * (bid -> bool))%type *)
(* : Set *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
(* Notation "x '::=' a" := *)
(* (Assign x a) (at level 60). *)
(* Assign : aid -> aexp -> com *)
(* Notation "y ':==' b" := *)
(* (BAssign y b) (at level 60). *)
(* BAssign : bid -> bexp -> com *)
(* Notation "c1 ; c2" := *)
(* (Seq c1 c2) (at level 80, right associativity). *)
(* Seq : com -> com -> com *)
(* Notation "'WHILE' x 'DO' c 'END'" := *)
(* (While x c) (at level 80, right associativity). *)
(* Notation "'IFB' y 'THEN' c1 'ELSE' c2 'FI'" := *)
(* (If y c1 c2) (at level 80, right associativity). *)
(* Notation "x '$=(' p ',' v ')'" := *)
(* (Toss p v x) (at level 60, right associativity). *)
(* Notation "y '$=[' p ',' v ']'" := *)
(* (BToss p v y) (at level 60, right associativity). *)
(* BToss : forall p : R, 0 < p < 1 -> bid -> com *)
Fixpoint ceval_step (st : state) (c : com) (i : nat) : option state :=
match i with
| O => None
| S i' => match c with
| Skip =>
Some st
| l ::= a1 =>
Some (update st l (aeval a1 st))
| l :== b1 =>
Some (update_b st l (beval b1 st))
| c1 ; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| BToss p v y =>
Some (update_b st y true)
| _ => None
end
end.
Compute ceval_step empty_state (Seq Skip Skip) 777.
(* = Some (fun _ : aid => 0%nat, fun _ : bid => false) *)
Compute ceval_step empty_state (Assign (Aid 2) (ANum 13)) 777.
(* = Some *)
(* (fun x : aid => *)
(* if *)
(* match x with *)
(* | Aid 0%nat => false *)
(* | Aid 1%nat => false *)
(* | Aid 2%nat => true *)
(* | Aid (S (S (S _))) => false *)
(* end *)
(* then 13%nat *)
(* else 0%nat, fun _ : bid => false) *)
(* : option state *)
Extraction "imp1.ml" ceval_step.
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ################################################################# *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
magic declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
(* Require Import Imp. *)
(* Require Import ImpParser. *)
Extraction "imp.ml" empty_state ceval_step (* parse *).
|
#include <bits/stdc++.h> using namespace std; const int N = 105; template <typename T> inline void read(T &AKNOI) { T x = 0, flag = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) flag = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } AKNOI = flag * x; } template <typename T> inline void cmax(T &x, T y) { if (x < y) x = y; } int n, m, lb[N][N], rb[N][N], dp[N][N]; void init() { read(n); read(m); for (int i = 1; i <= n; ++i) { int k; read(k); while (k--) { int l, r; read(l); read(r); for (int j = l; j <= r; ++j) { lb[i][j] = l; rb[i][j] = r; } } } } void solve() { for (int l = 1; l <= m; ++l) { for (int i = 1, j = i + l - 1; j <= m; ++i, ++j) { for (int k = i; k <= j; ++k) { int cnt = 0; for (int p = 1; p <= n; ++p) { cnt += (i <= lb[p][k] && rb[p][k] <= j); } cmax(dp[i][j], dp[i][k - 1] + cnt * cnt + dp[k + 1][j]); } } } printf( %d n , dp[1][m]); } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int spf[100001]; void sieve(); set<long long int> factors(long long int x); void getZarr(string str, long long int Z[]); int n; vector<int> ans; vector<bool> vis; vector<int> mas; vector<int> del; vector<int> koll; vector<vector<int>> edges; int nod(int a, int b) { if (b == 0) return a; return nod(b, a % b); } void dfs1(int v) { vis[v] = 1; for (auto u : edges[v]) if (!vis[u]) { ans[u] = nod(ans[v], mas[u]); dfs1(u); } } void dfs2(int v, int dist) { vis[v] = 1; for (int i = 0; i < del.size(); i++) { koll[i] += (mas[v] % del[i] == 0); if (koll[i] >= dist) ans[v] = max(ans[v], del[i]); } for (auto u : edges[v]) if (!vis[u]) dfs2(u, dist + 1); for (int i = 0; i < del.size(); i++) koll[i] -= (mas[v] % del[i] == 0); } signed main() { ios_base::sync_with_stdio(0); int n; cin >> n; ans.resize(n); vis.resize(n); mas.resize(n); edges.resize(n); for (int i = 0; i < n; i++) cin >> mas[i]; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; edges[a].push_back(b); edges[b].push_back(a); } int p = mas[0]; mas[0] = 0; ans[0] = 0; dfs1(0); mas[0] = p; for (int i = 0; i < n; i++) vis[i] = 0; for (int i = 1; i * i <= mas[0]; i++) { if (mas[0] % i == 0) { del.push_back(i); del.push_back(mas[0] / i); if (i * i == mas[0]) del.pop_back(); } } sort(del.begin(), del.end()); koll.resize(del.size()); dfs2(0, 0); for (int i = 0; i < n; i++) cout << ans[i] << ; return 0; } void sieve() { spf[1] = 1; for (long long int i = 2; i < 100001; i++) spf[i] = i; for (long long int i = 4; i < 100001; i += 2) spf[i] = 2; for (long long int i = 3; i * i < 100001; i++) { if (spf[i] == i) { for (long long int j = i * i; j < 100001; j += i) if (spf[j] == j) spf[j] = i; } } } void getZarr(string str, long long int Z[]) { long long int n = str.length(); long long int L, R, k; L = R = 0; for (long long int i = 1; i < n; ++i) { if (i > R) { L = R = i; while (R < n && str[R - L] == str[R]) R++; Z[i] = R - L; R--; } else { k = i - L; if (Z[k] < R - i + 1) Z[i] = Z[k]; else { L = i; while (R < n && str[R - L] == str[R]) R++; Z[i] = R - L; R--; } } } } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e5 + 7; long long n, k, a, b, q; long long arr[MAXN]; void read() { cin >> n >> k >> a >> b >> q; } long long acnt[MAXN << 2], asum[MAXN << 2], bcnt[MAXN << 2], bsum[MAXN << 2]; long long getacnt(long long v, long long tl, long long tr, long long l, long long r) { if (tr < l || r < tl) return 0; if (l <= tl && tr <= r) return acnt[v]; long long tm = (tl + tr) >> 1; return getacnt(v * 2 + 1, tl, tm, l, r) + getacnt(v * 2 + 2, tm + 1, tr, l, r); } long long getbcnt(long long v, long long tl, long long tr, long long l, long long r) { if (tr < l || r < tl) return 0; if (l <= tl && tr <= r) return bcnt[v]; long long tm = (tl + tr) >> 1; return getbcnt(v * 2 + 1, tl, tm, l, r) + getbcnt(v * 2 + 2, tm + 1, tr, l, r); } long long getasum(long long v, long long tl, long long tr, long long l, long long r) { if (tr < l || r < tl) return 0; if (l <= tl && tr <= r) return asum[v]; long long tm = (tl + tr) >> 1; return getasum(v * 2 + 1, tl, tm, l, r) + getasum(v * 2 + 2, tm + 1, tr, l, r); } long long getbsum(long long v, long long tl, long long tr, long long l, long long r) { if (tr < l || r < tl) return 0; if (l <= tl && tr <= r) return bsum[v]; long long tm = (tl + tr) >> 1; return getbsum(v * 2 + 1, tl, tm, l, r) + getbsum(v * 2 + 2, tm + 1, tr, l, r); } void updacnt(long long v, long long tl, long long tr, long long p, long long x) { if (tl == tr) { acnt[v] = (arr[p] + x >= a); return; } long long tm = (tl + tr) >> 1; if (p <= tm) updacnt(v * 2 + 1, tl, tm, p, x); else updacnt(v * 2 + 2, tm + 1, tr, p, x); acnt[v] = acnt[v * 2 + 1] + acnt[v * 2 + 2]; } void updbcnt(long long v, long long tl, long long tr, long long p, long long x) { if (tl == tr) { bcnt[v] = (arr[p] + x >= b); return; } long long tm = (tl + tr) >> 1; if (p <= tm) updbcnt(v * 2 + 1, tl, tm, p, x); else updbcnt(v * 2 + 2, tm + 1, tr, p, x); bcnt[v] = bcnt[v * 2 + 1] + bcnt[v * 2 + 2]; } void updasum(long long v, long long tl, long long tr, long long p, long long x) { if (tl == tr) { asum[v] = (arr[p] + x) * (arr[p] + x < a); return; } long long tm = (tl + tr) >> 1; if (p <= tm) updasum(v * 2 + 1, tl, tm, p, x); else updasum(v * 2 + 2, tm + 1, tr, p, x); asum[v] = asum[v * 2 + 1] + asum[v * 2 + 2]; } void updbsum(long long v, long long tl, long long tr, long long p, long long x) { if (tl == tr) { bsum[v] = (arr[p] + x) * (arr[p] + x < b); return; } long long tm = (tl + tr) >> 1; if (p <= tm) updbsum(v * 2 + 1, tl, tm, p, x); else updbsum(v * 2 + 2, tm + 1, tr, p, x); bsum[v] = bsum[v * 2 + 1] + bsum[v * 2 + 2]; } void print() { for (long long i = 0; i < q; ++i) { long long t; cin >> t; if (t == 1) { long long p, x; cin >> p >> x; --p; updacnt(0, 0, MAXN, p, x); updbcnt(0, 0, MAXN, p, x); updasum(0, 0, MAXN, p, x); updbsum(0, 0, MAXN, p, x); arr[p] += x; } else { long long p; cin >> p; --p; long long sum1 = getbcnt(0, 0, MAXN, 0, p - 1) * b + getbsum(0, 0, MAXN, 0, p - 1); long long sum2 = getacnt(0, 0, MAXN, p + k, MAXN) * a + getasum(0, 0, MAXN, p + k, MAXN); cout << sum1 + sum2 << n ; } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); read(); print(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_1_V
`define SKY130_FD_SC_HD__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p = 1000000000; cin >> n; int k[n], i; for (i = 0; i < n; i++) { cin >> k[i]; } i = 0; int j = 0, sum = 0; while (n--) { sum = 0; while (k[i]--) { cin >> j; sum = sum + j * 5 + 15; } i++; if (sum < p) { p = sum; } } cout << p; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long MAXN = 1e5 + 100; long long F[MAXN]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); F[0] = 1; F[1] = 1; for (long long i = 2; i < MAXN; i++) F[i] = (F[i - 1] + F[i - 2]) % MOD; long long N, M; cin >> N >> M; cout << 2 * (F[N] + F[M] + MOD - 1) % MOD << n ; return 0; }
|
// A zero value MCD should be allowed, but does it process the arguments?
module top;
integer mcd, test;
initial begin
test = 0;
// Skipped, but function is called.
#1;
$display($stime);
mcd = 0;
$fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd);
$fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1));
$fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1));
#1;
$display($stime);
mcd = 1;
$fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd);
$fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1));
$fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1));
$fflush(mcd);
// Skipped, but function is called.
#1;
$display($stime);
mcd = 0;
$fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd);
$fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1));
$fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1));
#1;
$display($stime);
if (test != 6) $display("FAILED side effect test");
else $display("PASSED");
end
function integer my_func;
input incr;
begin
test = test + incr;
my_func = test;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the export parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
interface test_if;
// Pre-declare function
extern function myfunc (input logic val);
// Interface variable
logic data;
// Modport
modport mp_e(
export myfunc,
output data
);
// Modport
modport mp_i(
import myfunc,
output data
);
endinterface // test_if
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if i ();
testmod_callee testmod_callee_i (.ie (i.mp_e));
testmod_caller testmod_caller_i (.clk (clk),
.ii (i.mp_i));
endmodule
module testmod_callee
(
test_if.mp_e ie
);
function automatic logic ie.myfunc (input logic val);
begin
myfunc = (val == 1'b0);
end
endfunction
endmodule // testmod_caller
module testmod_caller
(
input clk,
test_if.mp_i ii
);
always @(posedge clk) begin
ii.data = 1'b0;
if (ii.myfunc (1'b0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int INF = 1e18; int32_t main() { long long int n; cin >> n; if (n % 2 != 0) { cout << 0 << n ; return 0; ; } long long int k = pow(2, n / 2); cout << k << n ; return 0; ; }
|
#include <bits/stdc++.h> using namespace std; char board[8][8]; int main() { for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) scanf( %c , &board[i][j]); } int minA = 100, minB = 100; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { if (board[i][j] == W ) { int k; for (k = i; k >= 0; k--) { if (k == i) continue; if (board[k][j] != . ) break; } if (k < 0 and i < minA) minA = i; } if (board[i][j] == B ) { int k; for (k = i; k < 8; k++) { if (k == i) continue; if (board[k][j] != . ) break; } if (k >= 8 and 7 - i < minB) minB = 7 - i; } } } if (minA <= minB) cout << A << endl; else cout << B << endl; return 0; }
|
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