repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_1.v
| 2,427 |
module MODULE2 (
VAR6 ,
VAR7,
VAR11,
VAR8 ,
VAR4 ,
VAR2,
VAR3,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR7;
input VAR11;
input VAR8 ;
input VAR4 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR1 ;
VAR10 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7,
VAR11,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR7;
input VAR11;
input VAR8 ;
input VAR4 ;
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR1 ;
VAR10 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
bigeagle/riffa
|
fpga/xilinx/vc707/riffa_wrapper_vc707.v
| 37,829 |
module MODULE1
parameter VAR326 = 128,
parameter VAR2 = 256,
parameter VAR207 = 5
)
(
input [VAR326-1:0] VAR176,
input [(VAR326/8)-1:0] VAR48,
input VAR152,
input VAR103,
output VAR44,
input [VAR334-1:0] VAR335,
output VAR149,
output VAR214,
output [VAR326-1:0] VAR225,
output [(VAR326/8)-1:0] VAR60,
output VAR16,
output VAR325,
input VAR74,
output [VAR358-1:0] VAR338,
output VAR261,
input [VAR134-1:0] VAR88,
input [VAR41-1:0] VAR343,
input [VAR126-1:0] VAR184,
input [VAR349-1:0] VAR302,
input [VAR349-1:0] VAR115,
input [VAR349-1:0] VAR97,
input [VAR349-1:0] VAR292,
input [VAR321-1:0] VAR144,
input [VAR291-1:0] VAR350,
output [VAR307-1:0] VAR206,
input VAR39,
input VAR81,
output VAR36,
input VAR213,
input VAR279,
output VAR256,
input [VAR170-1:0] VAR116, output [VAR170-1:0] VAR67, input [VAR170-1:0] VAR306, output [VAR170-1:0] VAR5, output [(VAR170*VAR198)-1:0] VAR25, output [(VAR170*VAR70)-1:0] VAR295, output [(VAR170*VAR326)-1:0] VAR296, output [VAR170-1:0] VAR153, input [VAR170-1:0] VAR109,
input [VAR170-1:0] VAR322, input [VAR170-1:0] VAR157, output [VAR170-1:0] VAR56, input [VAR170-1:0] VAR266, input [(VAR170*VAR198)-1:0] VAR53, input [(VAR170*VAR70)-1:0] VAR249, input [(VAR170*VAR326)-1:0] VAR352, input [VAR170-1:0] VAR129, output [VAR170-1:0] VAR356
);
localparam VAR69 = "VAR205"; localparam VAR50 = VAR2 * 2;
localparam VAR242 = "VAR132";
localparam VAR253 = VAR326 / 32;
localparam VAR340 = 1;
localparam VAR215 = 1;
localparam VAR259 = 10;
wire clk;
wire VAR159;
wire [VAR326-1:0] VAR146;
wire VAR268;
wire VAR162;
wire [(VAR326/32)-1:0] VAR150;
wire [VAR29(VAR326/32)-1:0] VAR275;
wire [VAR104-1:0] VAR101;
wire VAR210;
wire [VAR29(VAR326/32)-1:0] VAR311;
wire [VAR209-1:0] VAR49;
wire [VAR289-1:0] VAR82;
wire [VAR200-1:0] VAR151;
wire [VAR93-1:0] VAR80;
wire [VAR220-1:0] VAR147;
wire [VAR19-1:0] VAR64;
wire [VAR190-1:0] VAR260;
wire VAR127;
wire [VAR326-1:0] VAR139;
wire VAR294;
wire [(VAR326/32)-1:0] VAR9;
wire VAR272;
wire [VAR29(VAR326/32)-1:0] VAR140;
wire [VAR104-1:0] VAR341;
wire VAR46;
wire [VAR29(VAR326/32)-1:0] VAR171;
wire [VAR209-1:0] VAR196;
wire [VAR137-1:0] VAR154;
wire [VAR161-1:0] VAR107;
wire [VAR289-1:0] VAR54;
wire [VAR93-1:0] VAR178;
wire [VAR201-1:0] VAR143;
wire [VAR270-1:0] VAR155;
wire [VAR269-1:0] VAR119;
wire [VAR220-1:0] VAR305;
wire VAR94;
wire VAR316;
wire [VAR326-1:0] VAR66;
wire VAR164;
wire [VAR29(VAR326/32)-1:0] VAR78;
wire VAR331;
wire [VAR29(VAR326/32)-1:0] VAR114;
wire VAR128;
wire VAR86;
wire [VAR104-1:0] VAR158;
wire [VAR209-1:0] VAR212;
wire [VAR200-1:0] VAR304;
wire [VAR93-1:0] VAR241;
wire [VAR220-1:0] VAR218;
wire [VAR19-1:0] VAR301;
wire [VAR289-1:0] VAR59;
wire [VAR269-1:0] VAR167;
wire [VAR137-1:0] VAR112;
wire [VAR161-1:0] VAR271;
wire VAR347;
wire VAR355;
wire VAR264;
wire VAR226;
wire [VAR326-1:0] VAR202;
wire VAR282;
wire [VAR29(VAR326/32)-1:0] VAR293;
wire VAR121;
wire [VAR29(VAR326/32)-1:0] VAR199;
wire VAR239;
wire VAR117;
wire [VAR104-1:0] VAR91;
wire [VAR209-1:0] VAR328;
wire [VAR201-1:0] VAR108;
wire [VAR220-1:0] VAR84;
wire [VAR289-1:0] VAR216;
wire [VAR137-1:0] VAR89;
wire [VAR161-1:0] VAR122;
wire [VAR93-1:0] VAR173;
wire VAR98;
wire VAR281;
wire VAR175;
wire VAR251;
wire [VAR326-1:0] VAR142;
wire VAR234;
wire [VAR71-1:0] VAR203;
wire VAR141;
wire [VAR71-1:0] VAR100;
wire VAR244;
wire [VAR270-1:0] VAR258;
wire VAR102;
wire [VAR326-1:0] VAR344;
wire VAR136;
wire [VAR71-1:0] VAR99;
wire VAR37;
wire [VAR71-1:0] VAR73;
wire VAR254;
wire VAR106;
wire [VAR326-1:0] VAR224;
wire [VAR330-1:0] VAR21;
wire [(VAR326/32)-1:0] VAR342;
wire VAR79 = 0;
wire VAR315;
wire [VAR326-1:0] VAR265 = 0;
wire [VAR346-1:0] VAR310 = 0;
wire VAR263 = 0;
wire [(VAR326/32)-1:0] VAR68 = 0;
wire VAR179 = 0;
wire VAR314;
wire [VAR326-1:0] VAR77 = 0;
wire [VAR303-1:0] VAR232 = 0;
wire VAR353 = 0;
wire [(VAR326/32)-1:0] VAR195 = 0;
wire VAR63 = 0;
wire VAR235 = 0;
wire [VAR326-1:0] VAR23;
wire [VAR13-1:0] VAR267;
wire VAR95;
wire [(VAR326/32)-1:0] VAR130;
wire VAR309;
wire VAR320 = 0;
wire VAR211;
wire [VAR190-1:0] VAR223;
wire VAR299;
wire VAR40;
wire [VAR27-1:0] VAR35;
wire [VAR317-1:0] VAR284;
wire [VAR339-1:0] VAR65;
wire [VAR8-1:0] VAR123;
wire [VAR321-1:0] VAR182;
wire [VAR291-1:0] VAR180;
wire VAR22;
wire VAR228;
genvar VAR186;
reg VAR192;
reg VAR1;
assign clk = VAR213;
assign VAR159 = VAR279;
VAR297
.VAR326 (VAR326))
VAR238
(
.VAR318 (VAR142[VAR326-1:0]),
.VAR52 (VAR244),
.VAR288 (VAR141),
.VAR221 (VAR100[VAR29(VAR326/32)-1:0]),
.VAR96 (VAR234),
.VAR168 (VAR203[VAR29(VAR326/32)-1:0]),
.VAR233 (VAR258[VAR270-1:0]),
.VAR148 (VAR102),
.VAR111 (VAR223[VAR190-1:0]),
.VAR252 (VAR211),
.VAR12 (VAR284[VAR317-1:0]),
.VAR188 (VAR35[VAR27-1:0]),
.VAR133 (VAR123[VAR8-1:0]),
.VAR145 (VAR65[VAR339-1:0]),
.VAR348 (VAR40),
.VAR51 (VAR299),
.VAR30 (VAR182[VAR321-1:0]),
.VAR85 (VAR180[VAR291-1:0]),
.VAR262 (VAR228),
.VAR285 (clk),
.VAR300 (VAR159),
.VAR169 (VAR251),
.VAR166 (VAR344[VAR326-1:0]),
.VAR323 (VAR254),
.VAR7 (VAR37),
.VAR236 (VAR73[VAR29(VAR326/32)-1:0]),
.VAR138 (VAR136),
.VAR58 (VAR99[VAR29(VAR326/32)-1:0]),
.VAR45 (VAR22),
.VAR44 (VAR44),
.VAR149 (VAR149),
.VAR214 (VAR214),
.VAR225 (VAR225[VAR326-1:0]),
.VAR60 (VAR60[(VAR326/8)-1:0]),
.VAR16 (VAR16),
.VAR325 (VAR325),
.VAR338 (VAR338[VAR358-1:0]),
.VAR261 (VAR261),
.VAR206 (VAR206[VAR307-1:0]),
.VAR36 (VAR36),
.VAR176 (VAR176[VAR326-1:0]),
.VAR48 (VAR48[(VAR326/8)-1:0]),
.VAR152 (VAR152),
.VAR103 (VAR103),
.VAR335 (VAR335[VAR334-1:0]),
.VAR74 (VAR74),
.VAR88 (VAR88[VAR134-1:0]),
.VAR343 (VAR343[VAR41-1:0]),
.VAR184 (VAR184[VAR126-1:0]),
.VAR302 (VAR302[VAR349-1:0]),
.VAR115 (VAR115[VAR349-1:0]),
.VAR97 (VAR97[VAR349-1:0]),
.VAR292 (VAR292[VAR349-1:0]),
.VAR144 (VAR144[VAR321-1:0]),
.VAR350 (VAR350[VAR291-1:0]),
.VAR39 (VAR39),
.VAR81 (VAR81));
VAR72
.VAR207 (VAR207),
.VAR215 (VAR215),
.VAR340 (VAR340),
.VAR183 (VAR2/4),
.VAR242 (VAR242))
VAR204
( .VAR163 (VAR146[VAR326-1:0]),
.VAR105 (VAR150[(VAR326/32)-1:0]),
.VAR156 (VAR268),
.VAR257 (VAR162),
.VAR42 (VAR275[VAR29(VAR326/32)-1:0]),
.VAR194 (VAR101[VAR104-1:0]),
.VAR222 (VAR210),
.VAR324 (VAR311[VAR29(VAR326/32)-1:0]),
.VAR246 (VAR49[VAR209-1:0]),
.VAR28 (VAR82[VAR289-1:0]),
.VAR351 (VAR151[VAR200-1:0]),
.VAR243 (VAR80[VAR93-1:0]),
.VAR181 (VAR147[VAR220-1:0]),
.VAR174 (VAR64[VAR19-1:0]),
.VAR165 (VAR260[VAR190-1:0]),
.VAR47 (VAR127),
.VAR312 (VAR139[VAR326-1:0]),
.VAR185 (VAR9[(VAR326/32)-1:0]),
.VAR43 (VAR294),
.VAR286 (VAR272),
.VAR354 (VAR140[VAR29(VAR326/32)-1:0]),
.VAR55 (VAR46),
.VAR357 (VAR171[VAR29(VAR326/32)-1:0]),
.VAR280 (VAR341[VAR104-1:0]),
.VAR61 (VAR196[VAR209-1:0]),
.VAR283 (VAR154[VAR137-1:0]),
.VAR359 (VAR107[VAR161-1:0]),
.VAR6 (VAR54[VAR289-1:0]),
.VAR219 (VAR178[VAR93-1:0]),
.VAR90 (VAR143[VAR201-1:0]),
.VAR187 (VAR155[VAR270-1:0]),
.VAR245 (VAR119[VAR269-1:0]),
.VAR32 (VAR305[VAR220-1:0]),
.VAR277 (VAR94),
.VAR33 (VAR128),
.VAR34 (VAR355),
.VAR247 (VAR264),
.VAR118 (VAR239),
.VAR278 (VAR281),
.VAR319 (VAR175),
.VAR166 (VAR344),
.VAR323 (VAR254),
.VAR7 (VAR37),
.VAR236 (VAR73),
.VAR138 (VAR136),
.VAR58 (VAR99),
.VAR169 (VAR251),
.VAR285 (clk),
.VAR300 (VAR159),
.VAR111 (VAR223[VAR190-1:0]),
.VAR172 (VAR316),
.VAR313 (VAR66[VAR326-1:0]),
.VAR230 (VAR164),
.VAR290 (VAR78[VAR29(VAR326/32)-1:0]),
.VAR38 (VAR331),
.VAR189 (VAR114[VAR29(VAR326/32)-1:0]),
.VAR120 (VAR86),
.VAR298 (VAR158[VAR104-1:0]),
.VAR17 (VAR212[VAR209-1:0]),
.VAR75 (VAR304[VAR200-1:0]),
.VAR329 (VAR241[VAR93-1:0]),
.VAR160 (VAR218[VAR220-1:0]),
.VAR62 (VAR301[VAR19-1:0]),
.VAR131 (VAR59[VAR289-1:0]),
.VAR327 (VAR167[VAR269-1:0]),
.VAR227 (VAR112[VAR137-1:0]),
.VAR24 (VAR271[VAR161-1:0]),
.VAR92 (VAR347),
.VAR83 (VAR226),
.VAR250 (VAR202[VAR326-1:0]),
.VAR333 (VAR282),
.VAR26 (VAR293[VAR29(VAR326/32)-1:0]),
.VAR113 (VAR121),
.VAR248 (VAR199[VAR29(VAR326/32)-1:0]),
.VAR125 (VAR117),
.VAR237 (VAR91[VAR104-1:0]),
.VAR332 (VAR328[VAR209-1:0]),
.VAR276 (VAR108[VAR201-1:0]),
.VAR31 (VAR84[VAR220-1:0]),
.VAR110 (VAR216[VAR289-1:0]),
.VAR336 (VAR89[VAR137-1:0]),
.VAR18 (VAR122[VAR161-1:0]),
.VAR87 (VAR173[VAR93-1:0]),
.VAR217 (VAR98),
.VAR318 (VAR142),
.VAR52 (VAR244),
.VAR288 (VAR141),
.VAR221 (VAR100),
.VAR96 (VAR234),
.VAR168 (VAR203),
.VAR233 (VAR258),
.VAR148 (VAR102),
.VAR273 (VAR235),
.VAR287 (VAR314),
.VAR345 (VAR309),
.VAR229 (VAR95),
.VAR10 (VAR23[VAR326-1:0]),
.VAR193 (VAR130[(VAR326/32)-1:0]),
.VAR124 (VAR267[VAR13-1:0]),
.VAR197 (VAR315),
.VAR208 (VAR106),
.VAR11 (VAR224[VAR326-1:0]),
.VAR337 (VAR342[(VAR326/32)-1:0]),
.VAR135 (VAR21[VAR330-1:0]),
.VAR177 (VAR63),
.VAR20 (VAR353),
.VAR255 (VAR77[VAR326-1:0]),
.VAR274 (VAR195[(VAR326/32)-1:0]),
.VAR15 (VAR232[VAR303-1:0]),
.VAR191 (VAR179),
.VAR14 (VAR263),
.VAR4 (VAR265[VAR326-1:0]),
.VAR240 (VAR68[(VAR326/32)-1:0]),
.VAR231 (VAR310[VAR346-1:0]),
.VAR308 (VAR320),
.VAR76 (VAR79)
);
VAR57
.VAR326 (VAR326),
.VAR170 (VAR170),
.VAR50 (VAR50),
.VAR242 (VAR242),
.VAR69 (VAR69),
.VAR259 (VAR259))
VAR3
( .VAR313 (VAR66[VAR326-1:0]),
.VAR172 (VAR316),
.VAR230 (VAR164),
.VAR290 (VAR78[VAR29(VAR326/32)-1:0]),
.VAR38 (VAR331),
.VAR189 (VAR114[VAR29(VAR326/32)-1:0]),
.VAR120 (VAR86),
.VAR298 (VAR158[VAR104-1:0]),
.VAR17 (VAR212[VAR209-1:0]),
.VAR75 (VAR304[VAR200-1:0]),
.VAR329 (VAR241[VAR93-1:0]),
.VAR160 (VAR218[VAR220-1:0]),
.VAR62 (VAR301[VAR19-1:0]),
.VAR131 (VAR59[VAR289-1:0]),
.VAR327 (VAR167[VAR269-1:0]),
.VAR227 (VAR112[VAR137-1:0]),
.VAR24 (VAR271[VAR161-1:0]),
.VAR92 (VAR347),
.VAR83 (VAR226),
.VAR250 (VAR202[VAR326-1:0]),
.VAR333 (VAR282),
.VAR26 (VAR293[VAR29(VAR326/32)-1:0]),
.VAR113 (VAR121),
.VAR248 (VAR199[VAR29(VAR326/32)-1:0]),
.VAR125 (VAR117),
.VAR237 (VAR91[VAR104-1:0]),
.VAR332 (VAR328[VAR209-1:0]),
.VAR276 (VAR108[VAR201-1:0]),
.VAR31 (VAR84[VAR220-1:0]),
.VAR110 (VAR216[VAR289-1:0]),
.VAR336 (VAR89[VAR137-1:0]),
.VAR18 (VAR122[VAR161-1:0]),
.VAR87 (VAR173[VAR93-1:0]),
.VAR217 (VAR98),
.VAR45 (VAR22),
.VAR285 (clk),
.VAR300 (VAR159),
.VAR312 (VAR139[VAR326-1:0]),
.VAR43 (VAR294),
.VAR286 (VAR272),
.VAR354 (VAR140[VAR29(VAR326/32)-1:0]),
.VAR185 (VAR9[(VAR326/32)-1:0]),
.VAR55 (VAR46),
.VAR357 (VAR171[VAR29(VAR326/32)-1:0]),
.VAR280 (VAR341[VAR104-1:0]),
.VAR61 (VAR196[VAR209-1:0]),
.VAR283 (VAR154[VAR137-1:0]),
.VAR359 (VAR107[VAR161-1:0]),
.VAR6 (VAR54[VAR289-1:0]),
.VAR219 (VAR178[VAR93-1:0]),
.VAR90 (VAR143[VAR201-1:0]),
.VAR187 (VAR155[VAR270-1:0]),
.VAR245 (VAR119[VAR269-1:0]),
.VAR32 (VAR305[VAR220-1:0]),
.VAR277 (VAR94),
.VAR156 (VAR268),
.VAR163 (VAR146[VAR326-1:0]),
.VAR257 (VAR162),
.VAR42 (VAR275[VAR29(VAR326/32)-1:0]),
.VAR105 (VAR150[(VAR326/32)-1:0]),
.VAR222 (VAR210),
.VAR324 (VAR311[VAR29(VAR326/32)-1:0]),
.VAR194 (VAR101[VAR104-1:0]),
.VAR246 (VAR49[VAR209-1:0]),
.VAR28 (VAR82[VAR289-1:0]),
.VAR351 (VAR151[VAR200-1:0]),
.VAR243 (VAR80[VAR93-1:0]),
.VAR181 (VAR147[VAR220-1:0]),
.VAR174 (VAR64[VAR19-1:0]),
.VAR165 (VAR260[VAR190-1:0]),
.VAR47 (VAR127),
.VAR33 (VAR128),
.VAR34 (VAR355),
.VAR247 (VAR264),
.VAR118 (VAR239),
.VAR278 (VAR281),
.VAR319 (VAR175),
.VAR111 (VAR223[VAR190-1:0]),
.VAR252 (VAR211),
.VAR12 (VAR284[VAR317-1:0]),
.VAR188 (VAR35[VAR27-1:0]),
.VAR133 (VAR123[VAR8-1:0]),
.VAR145 (VAR65[VAR339-1:0]),
.VAR348 (VAR40),
.VAR51 (VAR299),
.VAR30 (VAR182[VAR321-1:0]),
.VAR85 (VAR180[VAR291-1:0]),
.VAR262 (VAR228),
.VAR256 (VAR256),
.VAR67 (VAR67[VAR170-1:0]),
.VAR5 (VAR5[VAR170-1:0]),
.VAR25 (VAR25[(VAR170*32)-1:0]),
.VAR295 (VAR295[(VAR170*31)-1:0]),
.VAR296 (VAR296[(VAR170*VAR326)-1:0]),
.VAR153 (VAR153[VAR170-1:0]),
.VAR56 (VAR56[VAR170-1:0]),
.VAR356 (VAR356[VAR170-1:0]),
.VAR116 (VAR116[VAR170-1:0]),
.VAR306 (VAR306[VAR170-1:0]),
.VAR109 (VAR109[VAR170-1:0]),
.VAR322 (VAR322[VAR170-1:0]),
.VAR157 (VAR157[VAR170-1:0]),
.VAR266 (VAR266[VAR170-1:0]),
.VAR53 (VAR53[(VAR170*32)-1:0]),
.VAR249 (VAR249[(VAR170*31)-1:0]),
.VAR352 (VAR352[(VAR170*VAR326)-1:0]),
.VAR129 (VAR129[VAR170-1:0]));
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/edfxbp/sky130_fd_sc_ls__edfxbp.blackbox.v
| 1,378 |
module MODULE1 (
VAR2 ,
VAR7,
VAR4,
VAR6 ,
VAR3
);
output VAR2 ;
output VAR7;
input VAR4;
input VAR6 ;
input VAR3 ;
supply1 VAR5;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o311a/sky130_fd_sc_lp__o311a_2.v
| 2,422 |
module MODULE2 (
VAR10 ,
VAR12 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR9,
VAR7,
VAR1 ,
VAR2
);
output VAR10 ;
input VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR1 ;
input VAR2 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR10 ,
VAR12,
VAR4,
VAR3,
VAR8,
VAR11
);
output VAR10 ;
input VAR12;
input VAR4;
input VAR3;
input VAR8;
input VAR11;
supply1 VAR9;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.pp.symbol.v
| 1,442 |
module MODULE1 (
input VAR8 ,
output VAR7 ,
output VAR1 ,
input VAR9 ,
input VAR6 ,
input VAR4 ,
input VAR3 ,
input VAR2,
input VAR10,
input VAR5
);
endmodule
|
apache-2.0
|
jon-whit/4-bit_comp
|
verilog modules/cpu_controller.v
| 7,059 |
module MODULE1(clk, VAR37, VAR25, VAR21, VAR20, VAR5, VAR2, VAR18, VAR4, VAR10,
VAR1, VAR17, VAR6, VAR19, VAR42, VAR38, VAR9, VAR40, VAR41);
input clk, VAR37, VAR5, VAR2;
input [7:0] VAR21; input [7:0] VAR20;
input [1:0] VAR25;
output reg VAR18, VAR1, VAR17, VAR6, VAR19, VAR42, VAR41;
output reg [3:0] VAR4, VAR10;
output reg [1:0] VAR40;
output [3:0] VAR38, VAR9;
parameter VAR24 = 4'b0000,
VAR7 = 4'b0001,
VAR43 = 4'b0010,
VAR36 = 4'b0011,
VAR28 = 4'b0100,
VAR14 = 4'b0101,
VAR11 = 4'b0110,
VAR27 = 4'b0111,
VAR26 = 4'b1000,
VAR35 = 4'b1001,
VAR31 = 4'b1010,
VAR16 = 4'b1011,
VAR30 = 4'b1100,
VAR22 = 4'b1101,
VAR3 = 4'b1110;
reg [3:0] VAR15, VAR33;
wire [1:0] VAR34, VAR29, VAR23, VAR8;
wire [3:0] VAR38;
assign VAR34 = VAR21[7:6];
assign VAR29 = VAR21[5:4];
assign VAR23 = VAR21[3:2];
assign VAR38 = VAR21[3:0];
assign VAR8 = VAR21[1:0];
wire [1:0] VAR12, VAR39, VAR32, VAR13;
wire [3:0] VAR9;
assign VAR12 = VAR20[7:6];
assign VAR39 = VAR20[5:4];
assign VAR32 = VAR20[3:2];
assign VAR9 = VAR20[3:0];
assign VAR13 = VAR20[1:0];
always@
begin
VAR18 = 1'b0;
VAR1 = 1'b0;
VAR19 = 1'b0; VAR42 = 1'b0;
VAR41 = 1'b0;
VAR17 = 1'b0; VAR6 = 1'b0;
VAR4 = 4'b0000; VAR10 = 4'b0000;
VAR40 = 2'b00;
case(VAR15)
VAR7:
begin
case(VAR29)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
VAR1 = 1'b1;
end
VAR43:
begin
VAR19 = 1'b1;
case(VAR29)
0: VAR4[0] = 1'b1;
1: VAR4[1] = 1'b1;
2: VAR4[2] = 1'b1;
3: VAR4[3] = 1'b1;
default:;
endcase
end
VAR36:
begin
VAR18 = 1'b1;
case(VAR29)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
end
VAR28:
begin
case(VAR23)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
case(VAR29)
0: VAR4[0] = 1'b1;
1: VAR4[1] = 1'b1;
2: VAR4[2] = 1'b1;
3: VAR4[3] = 1'b1;
default:;
endcase
end
VAR14:
begin
case(VAR23)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
VAR40 = VAR8;
VAR17 = 1'b1;
end
VAR11:
begin
VAR6 = 1'b1;
case(VAR29)
0: VAR4[0] = 1'b1;
1: VAR4[1] = 1'b1;
2: VAR4[2] = 1'b1;
3: VAR4[3] = 1'b1;
default:;
endcase
end
VAR35:
begin
case(VAR39)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
VAR1 = 1'b1;
end
VAR31:
begin
VAR42 = 1'b1;
case(VAR39)
0: VAR4[0] = 1'b1;
1: VAR4[1] = 1'b1;
2: VAR4[2] = 1'b1;
3: VAR4[3] = 1'b1;
default:;
endcase
VAR41 = 1'b1;
end
VAR16:
begin
VAR18 = 1'b1;
case(VAR39)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
VAR41 = 1'b1;
end
VAR30:
begin
case(VAR32)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
case(VAR39)
0: VAR4[0] = 1'b1;
1: VAR4[1] = 1'b1;
2: VAR4[2] = 1'b1;
3: VAR4[3] = 1'b1;
default:;
endcase
VAR41 = 1'b1;
end
VAR22:
begin
case(VAR32)
0: VAR10[0] = 1'b1;
1: VAR10[1] = 1'b1;
2: VAR10[2] = 1'b1;
3: VAR10[3] = 1'b1;
default:;
endcase
VAR40 = VAR13;
VAR17 = 1'b1;
end
VAR3:
begin
VAR6 = 1'b1;
case(VAR39)
0: VAR4[0] = 1'b1;
1: VAR4[1] = 1'b1;
2: VAR4[2] = 1'b1;
3: VAR4[3] = 1'b1;
default:;
endcase
VAR41 = 1'b1;
end
default:;
endcase
end
endmodule
|
mit
|
Cosmos-OpenSSD/Cosmos-OpenSSD-plus
|
project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/CompletionDataChannel.v
| 7,148 |
module MODULE1
(
parameter VAR6 = 32 ,
parameter VAR26 = 16 ,
parameter VAR7 = 1
)
(
VAR10 ,
VAR1 ,
VAR14 ,
VAR30 ,
VAR16 ,
VAR21 ,
VAR34 ,
VAR23 ,
VAR24 ,
VAR17 ,
VAR22 ,
VAR9 ,
VAR29 ,
VAR3
);
input VAR10 ;
input VAR1 ;
input [4:0] VAR30 ;
input [VAR26 - 1:0] VAR14 ;
input VAR16 ;
output VAR21 ;
input [VAR6 - 1:0] VAR34 ;
input VAR23 ;
input VAR24 ;
output VAR17 ;
output [VAR6 - 1:0] VAR22 ;
output VAR9 ;
output VAR29 ;
input VAR3 ;
reg VAR33 ;
reg VAR18 ;
reg VAR25 ;
wire VAR8 ;
wire VAR31 ;
wire VAR13 ;
wire VAR28 ;
wire VAR19 ;
wire VAR11 ;
wire [VAR26 - 1:0] VAR4 ;
wire [4:0] VAR32 ;
reg [VAR6 - 1:0] VAR15 ;
assign VAR8 = VAR16 & VAR21 ;
assign VAR17 = VAR33 ;
assign VAR22 = VAR15 ;
assign VAR9 = VAR18 ;
assign VAR29 = VAR25 ;
assign VAR21 = !VAR13 ;
localparam VAR2 = 2'b00;
localparam VAR20 = 2'b01;
localparam VAR12 = 2'b11;
reg [1:0] VAR27 ;
reg [1:0] VAR5;
always @ (posedge VAR10)
if (VAR1)
VAR27 <= VAR2;
else
VAR27 <= VAR5;
always @
case (VAR27)
VAR20:
VAR15 <= 32'hA5000001;
VAR12:
VAR15 <= VAR34;
default:
VAR15 <= 1'b0;
endcase
always @
case (VAR27)
VAR20:
VAR18 <= 1'b1;
VAR12:
VAR18 <= VAR23;
default:
VAR18 <= 1'b0;
endcase
always @ (*)
case (VAR27)
VAR20:
VAR25 <= 1'b1;
default:
VAR25 <= VAR24;
endcase
endmodule
|
gpl-3.0
|
Jafet95/proy_3_grupo_2_sem_1_2016
|
contador_AD_HH_2dig.v
| 2,936 |
module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0]VAR4,
input wire VAR3,
input wire VAR8,
output wire [7:0] VAR5);
localparam VAR2 = 5; reg [VAR2-1:0] VAR9, VAR1;
wire [VAR2-1:0] VAR10;
reg [3:0] VAR6, VAR7;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR9 <= 5'b0;
end
else
begin
VAR9 <= VAR1;
end
end
always@*
begin
if (VAR4 == 3)
begin
if (VAR3)
begin
if (VAR9 >= 5'd23) VAR1 = 5'd0;
end
else VAR1 = VAR9 + 5'd1;
end
else if (VAR8)
begin
if (VAR9 == 5'd0) VAR1 = 5'd23;
end
else VAR1 = VAR9 - 5'd1;
end
else VAR1 = VAR9;
end
else VAR1 = VAR9;
end
assign VAR10 = VAR9;
always@*
begin
case(VAR10)
5'd0: begin VAR6 = 4'b0000; VAR7 = 4'b0000; end
5'd1: begin VAR6 = 4'b0000; VAR7 = 4'b0001; end
5'd2: begin VAR6 = 4'b0000; VAR7 = 4'b0010; end
5'd3: begin VAR6 = 4'b0000; VAR7 = 4'b0011; end
5'd4: begin VAR6 = 4'b0000; VAR7 = 4'b0100; end
5'd5: begin VAR6 = 4'b0000; VAR7 = 4'b0101; end
5'd6: begin VAR6 = 4'b0000; VAR7 = 4'b0110; end
5'd7: begin VAR6 = 4'b0000; VAR7 = 4'b0111; end
5'd8: begin VAR6 = 4'b0000; VAR7 = 4'b1000; end
5'd9: begin VAR6 = 4'b0000; VAR7 = 4'b1001; end
5'd10: begin VAR6 = 4'b0001; VAR7 = 4'b0000; end
5'd11: begin VAR6 = 4'b0001; VAR7 = 4'b0001; end
5'd12: begin VAR6 = 4'b0001; VAR7 = 4'b0010; end
5'd13: begin VAR6 = 4'b0001; VAR7 = 4'b0011; end
5'd14: begin VAR6 = 4'b0001; VAR7 = 4'b0100; end
5'd15: begin VAR6 = 4'b0001; VAR7 = 4'b0101; end
5'd16: begin VAR6 = 4'b0001; VAR7 = 4'b0110; end
5'd17: begin VAR6 = 4'b0001; VAR7 = 4'b0111; end
5'd18: begin VAR6 = 4'b0001; VAR7 = 4'b1000; end
5'd19: begin VAR6 = 4'b0001; VAR7 = 4'b1001; end
5'd20: begin VAR6 = 4'b0010; VAR7 = 4'b0000; end
5'd21: begin VAR6 = 4'b0010; VAR7 = 4'b0001; end
5'd22: begin VAR6 = 4'b0010; VAR7 = 4'b0010; end
5'd23: begin VAR6 = 4'b0010; VAR7 = 4'b0011; end
default: begin VAR6 = 0; VAR7 = 0; end
endcase
end
assign VAR5 = {VAR6,VAR7};
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfxtp/sky130_fd_sc_ms__dfxtp.pp.blackbox.v
| 1,279 |
module MODULE1 (
VAR6 ,
VAR3 ,
VAR2 ,
VAR7,
VAR1,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR4 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.functional.v
| 1,046 |
module MODULE1( VAR6, VAR3, VAR7 );
input VAR7, VAR6;
output VAR3;
wire VAR1;
not VAR4( VAR1, VAR7 );
wire VAR8;
not VAR2( VAR8, VAR6 );
or VAR5( VAR3, VAR1, VAR8 );
endmodule
|
apache-2.0
|
tejchava1460/Evaluation-Project-for-ASIC-FPGA-Design-Engineer
|
Verilog_Noise_generator/log_impltn.v
| 1,291 |
module MODULE1(VAR11, VAR7, clk);
input [47:0]VAR11;
input clk;
output [30:0]VAR7;
reg [30:0]VAR7;
reg [7:0]VAR1;
reg [47:0]VAR10;
reg [113:0]VAR13, VAR6, VAR2, VAR5;
reg [65:0]VAR6;
reg [15:0]VAR4;
reg [18:0]VAR12;
reg [33:0]VAR12, VAR5;
reg [34:0]VAR14;
reg [16:0]VAR15;
reg [16:0]VAR3, VAR9;
reg [48:0]VAR10;
integer VAR8;
always@(posedge clk)
begin
VAR8 = 47; while(VAR8>=0)
begin
if(VAR11[VAR8] == 1'b1)
begin
VAR1 = 48 - VAR8; VAR8 = 0;
end
VAR8 = VAR8-1;
end
VAR10 = VAR10&(48'h000000000000);
VAR10 = VAR11 << VAR1;
VAR5 = 0;
VAR15 = 17'b00011011000001110;
VAR3 = 17'b10101000111110001;
VAR9 = 17'b10001101010001101;
VAR10[47:0] = VAR10[47:0];
VAR10[48] = 1;
VAR13 = VAR15*VAR10*VAR10 ;
VAR6 = VAR3*VAR10 ;
VAR2[113] = 0;
VAR6[113:48] = VAR6[65:0];
VAR6[47:0] = 0;
VAR2[112:96] = VAR9[16:0];
VAR2[95:0] = 0;
VAR5 = -VAR13 + VAR6 - VAR2;
VAR4 = 16'b1011000101110010;
VAR12 = VAR1*VAR4;
VAR5[33:31] = 0;
VAR5[30:0] = VAR5[111:81];
VAR12[33:15] = VAR12[18:0];
VAR12[14:0] = 0;
VAR14 = VAR12 + VAR5;
VAR7[27:0] = VAR14[34:7];
VAR7[30:28] = 0;
end
endmodule
|
gpl-3.0
|
mda-ut/SubZero
|
fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk.v
| 6,946 |
module MODULE1 (
clk,
VAR10,
VAR3,
VAR21,
VAR30,
VAR25,
VAR26,
VAR18,
VAR29,
VAR16,
VAR17,
VAR7,
VAR24,
VAR22,
VAR13,
VAR23,
VAR14,
VAR11,
VAR12
)
;
output [ 37: 0] VAR25;
output VAR26;
output VAR18;
output VAR29;
output VAR16;
output VAR17;
output VAR7;
output VAR24;
output VAR22;
output VAR13;
output VAR23;
output VAR14;
output VAR11;
output VAR12;
input clk;
input [ 1: 0] VAR10;
input [ 37: 0] VAR3;
input VAR21;
input VAR30;
reg VAR4 ;
reg [ 1: 0] VAR28 ;
reg [ 37: 0] VAR25 ;
reg VAR33 ;
reg VAR5 ;
reg VAR9 ;
wire VAR27;
wire VAR15;
wire VAR26;
wire VAR18;
wire VAR29;
wire VAR16;
wire VAR17;
wire VAR7;
wire VAR24;
wire VAR22;
wire VAR13;
wire VAR23;
wire VAR14;
wire VAR11;
wire VAR12;
wire VAR2;
wire VAR32;
reg VAR8 ;
assign VAR2 = 1'b1;
VAR20 VAR19
(
.clk (clk),
.din (VAR21),
.dout (VAR27),
.VAR31 (VAR2)
);
assign VAR32 = 1'b1;
VAR20 VAR6
(
.clk (clk),
.din (VAR30),
.dout (VAR15),
.VAR31 (VAR32)
);
always @(posedge clk)
begin
VAR5 <= VAR27;
VAR8 <= VAR27 & ~VAR5;
VAR4 <= VAR8;
VAR9 <= VAR15;
VAR33 <= VAR15 & ~VAR9;
end
assign VAR16 = VAR4 && (VAR28 == 2'b00) &&
~VAR25[35] && VAR25[34];
assign VAR11 = VAR4 && (VAR28 == 2'b00) &&
~VAR25[35] && ~VAR25[34];
assign VAR17 = VAR4 && (VAR28 == 2'b00) &&
VAR25[35];
assign VAR24 = VAR4 && (VAR28 == 2'b01) &&
~VAR25[37] &&
VAR25[36];
assign VAR12 = VAR4 && (VAR28 == 2'b01) &&
~VAR25[37] &&
~VAR25[36];
assign VAR22 = VAR4 && (VAR28 == 2'b01) &&
VAR25[37];
assign VAR26 = VAR4 && (VAR28 == 2'b10) &&
~VAR25[36] &&
VAR25[37];
assign VAR13 = VAR4 && (VAR28 == 2'b10) &&
~VAR25[36] &&
~VAR25[37];
assign VAR18 = VAR4 && (VAR28 == 2'b10) &&
VAR25[36] && ~VAR25[35] &&
VAR25[37];
assign VAR23 = VAR4 && (VAR28 == 2'b10) &&
VAR25[36] && ~VAR25[35] &&
~VAR25[37];
assign VAR29 = VAR4 && (VAR28 == 2'b10) &&
VAR25[36] && VAR25[35] &&
VAR25[37];
assign VAR14 = VAR4 && (VAR28 == 2'b10) &&
VAR25[36] && VAR25[35] &&
~VAR25[37];
assign VAR7 = VAR4 && (VAR28 == 2'b11) &&
VAR25[15];
always @(posedge clk)
begin
if (VAR33)
VAR28 <= VAR10;
if (VAR8)
VAR25 <= VAR3;
end
endmodule
|
mit
|
gajjanag/6111_Project
|
src/vga.v
| 2,787 |
module MODULE1(input VAR9,
output reg [9:0] VAR19, output reg [9:0] VAR8, output reg VAR13,VAR14,VAR4);
parameter VAR20 = 10'd639;
parameter VAR2 = 10'd655;
parameter VAR23 = 10'd751;
parameter VAR10 = 10'd799;
parameter VAR25 = 10'd479;
parameter VAR18 = 10'd490;
parameter VAR26 = 10'd492;
parameter VAR7 = 10'd523;
reg VAR11,VAR12;
wire VAR3,VAR5,VAR1,VAR17;
assign VAR17 = (VAR19 == VAR20);
assign VAR3 = (VAR19 == VAR2);
assign VAR5 = (VAR19 == VAR23);
assign VAR1 = (VAR19 == VAR10);
wire VAR22,VAR16,VAR21,VAR6;
assign VAR6 = VAR1 & (VAR8 == VAR25);
assign VAR22 = VAR1 & (VAR8 == VAR18);
assign VAR16 = VAR1 & (VAR8 == VAR26);
assign VAR21 = VAR1 & (VAR8 == VAR7);
wire VAR15,VAR24;
assign VAR15 = VAR1 ? 0 : VAR17 ? 1 : VAR11;
assign VAR24 = VAR21 ? 0 : VAR6 ? 1 : VAR12;
always @(posedge VAR9) begin
VAR19 <= VAR1 ? 0 : VAR19 + 1;
VAR11 <= VAR15;
VAR14 <= VAR3 ? 0 : VAR5 ? 1 : VAR14;
VAR8 <= VAR1 ? (VAR21 ? 0 : VAR8 + 1) : VAR8;
VAR12 <= VAR24;
VAR13 <= VAR22 ? 0 : VAR16 ? 1 : VAR13;
VAR4 <= VAR24 | (VAR15 & ~VAR1);
end
endmodule
|
gpl-3.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_vref_logic.v
| 2,747 |
module MODULE1(VAR4 ,VAR17 ,VAR36 ,VAR23 ,VAR3 );
output [7:0] VAR17 ;
input VAR4 ;
input VAR36 ;
input VAR23 ;
input VAR3 ;
wire VAR9 ;
wire VAR24 ;
wire VAR22 ;
wire VAR2 ;
wire VAR33 ;
wire VAR30 ;
wire VAR25 ;
wire VAR7 ;
wire VAR20 ;
wire VAR34 ;
wire VAR35 ;
VAR19 VAR16 (
.VAR15 (VAR9 ),
.VAR4 (VAR4 ),
.VAR23 (VAR23 ),
.VAR36 (VAR36 ) );
VAR31 VAR28 (
.VAR15 (VAR30 ),
.VAR4 (VAR4 ),
.VAR23 (VAR23 ) );
VAR31 VAR14 (
.VAR15 (VAR2 ),
.VAR4 (VAR25 ),
.VAR23 (VAR4 ) );
VAR6 VAR10 (
.VAR15 (VAR22 ),
.VAR4 (VAR36 ),
.VAR23 (VAR23 ) );
VAR31 VAR13 (
.VAR15 (VAR7 ),
.VAR4 (VAR23 ),
.VAR23 (VAR36 ) );
VAR27 VAR29 (
.VAR15 (VAR24 ),
.VAR4 (VAR23 ),
.VAR23 (VAR4 ) );
VAR21 VAR26 (
.VAR15 (VAR35 ),
.VAR4 (VAR36 ),
.VAR23 (VAR23 ),
.VAR36 (VAR4 ) );
VAR11 VAR8 (
.VAR15 (VAR33 ),
.VAR4 (VAR4 ) );
VAR11 VAR1 (
.VAR15 (VAR20 ),
.VAR4 (VAR34 ) );
VAR31 VAR18 (
.VAR15 (VAR34 ),
.VAR4 (VAR33 ),
.VAR23 (VAR7 ) );
VAR11 VAR32 (
.VAR15 (VAR25 ),
.VAR4 (VAR22 ) );
VAR5 VAR12 (
.in ({VAR9 ,VAR30 ,VAR2 ,VAR33 ,VAR20 ,VAR24
,VAR35 } ),
.VAR17 ({VAR17 } ),
.VAR3 (VAR3 ) );
endmodule
|
gpl-2.0
|
Blunk-electronic/M-1
|
HW/ise/trc_mini/src/i2c_slave.v
| 2,498 |
module MODULE1 (VAR4, VAR11, VAR12, VAR1, reset, VAR6);
inout VAR4; input VAR11;
input reset;
input [6:0] VAR1; output reg [7:0] VAR12;
output VAR6;
reg VAR13 = 1; reg VAR5 = 1; reg [4:0] VAR9 = -1; reg [6:0] address = -1;
reg [7:0] VAR2 = -1;
wire VAR8;
wire VAR3 ;
assign VAR3 = !VAR8;
wire VAR10 ;
assign VAR10 = !VAR3;
always @(negedge VAR4 or negedge VAR10)
if (!VAR10) begin VAR13 <= 1'b1;
end else
begin
VAR13 <= !VAR11; end
always @(posedge VAR11 or negedge reset) begin
if (!reset)
begin
VAR12 <= -1;
address <= -1;
VAR2 <= -1;
end
else
begin
case (VAR9)
5'h00 : address[6] <= VAR4;
5'h01 : address[5] <= VAR4;
5'h02 : address[4] <= VAR4;
5'h03 : address[3] <= VAR4;
5'h04 : address[2] <= VAR4;
5'h05 : address[1] <= VAR4;
5'h06 : address[0] <= VAR4;
5'h09 : VAR2[7] <= VAR4;
5'h0a : VAR2[6] <= VAR4;
5'h0b : VAR2[5] <= VAR4;
5'h0c : VAR2[4] <= VAR4;
5'h0d : VAR2[3] <= VAR4;
5'h0e : VAR2[2] <= VAR4;
5'h0f : VAR2[1] <= VAR4;
5'h10 : VAR2[0] <= VAR4;
5'h11 : if (address == VAR1) VAR12 <= VAR2;
endcase
end
end
assign VAR8 = VAR13 & reset; always @(negedge VAR11 or negedge VAR8)
begin
if (!VAR8) VAR9 <= -1;
end
else VAR9 <= VAR9 +1; end
always @(VAR9, VAR1, address)
begin
case (VAR9)
5'h08 : if (address == VAR1) VAR5 <= 0;
5'h11 : if (address == VAR1) VAR5 <= 0;
default : VAR5 <= 1;
endcase
end
assign VAR6 = VAR5;
assign VAR4 = VAR5 ? 1'VAR7 : 1'b0;
endmodule
|
gpl-2.0
|
binderclip/BCOpenMIPS
|
cpu-code/mem.v
| 12,160 |
module MODULE1 (
input wire rst,
input wire[VAR46] VAR51,
input wire VAR60,
input wire[VAR58] VAR56,
input wire VAR24,
input wire[VAR58] VAR15,
input wire[VAR58] VAR54,
input wire[VAR66] VAR14,
input wire[VAR58] VAR30,
input wire[VAR58] VAR2,
input wire[VAR58] VAR57,
input wire VAR47,
input wire VAR61,
input wire VAR55,
input wire[VAR58] VAR63,
input wire[VAR46] VAR10,
input wire VAR53,
input wire[VAR58] VAR29,
input wire[VAR58] VAR16,
input wire VAR70,
input wire VAR27,
input wire[VAR58] VAR35,
input wire[VAR58] VAR8,
input wire[VAR58] VAR20,
input wire VAR41,
input wire[4:0] VAR12,
input wire[VAR58] VAR59,
output reg[VAR46] VAR23,
output reg VAR22,
output reg[VAR58] VAR68,
output reg VAR25,
output reg[VAR58] VAR65,
output reg[VAR58] VAR6,
output reg VAR45,
output reg VAR5,
output reg[VAR58] VAR26,
output wire VAR39,
output reg[3:0] VAR11,
output reg[VAR58] VAR7,
output reg VAR1,
output reg[VAR58] VAR36,
output reg[VAR46] VAR38,
output reg VAR52,
output wire[VAR58] VAR19,
output reg[VAR58] VAR40,
output wire[VAR58] VAR64,
output wire VAR32,
output wire VAR62
);
wire[VAR58] VAR9;
reg VAR31;
reg VAR18;
reg[VAR58] VAR37;
reg[VAR58] VAR4;
reg[VAR58] VAR48;
assign VAR39 = VAR31 & (~(|VAR40));
assign VAR9 = VAR28;
assign VAR62 = VAR27;
assign VAR64 = VAR16;
assign VAR32 = VAR70;
always @ begin
if (rst == VAR33) begin
VAR48 <= VAR28;
end
else if (VAR41 == VAR3 && VAR12 == VAR67) begin
VAR48 <= VAR59;
end
else begin
VAR48 <= VAR20;
end
end
assign VAR19 = VAR48;
always @ begin
if (rst == VAR33) begin
VAR40 <= VAR28;
end
else begin
VAR40 <= VAR28;
if (((VAR4[15:8] & VAR37[15:8]) != 8'h00) && (VAR37[1] == 1'b0 && VAR37[0] == 1'b1)) begin
VAR40 <= VAR13; end
else if (VAR29[8] == 1'b1) begin
VAR40 <= VAR21; end
else if (VAR29[9] == 1'b1) begin
VAR40 <= VAR49; end
else if (VAR29[10] == 1'b1) begin
VAR40 <= VAR69; end
else if (VAR29[11] == 1'b1) begin
VAR40 <= VAR50; end
else if (VAR29[12] == 1'b1) begin
VAR40 <= VAR17; end
end
end
always @ begin
if (rst == VAR33) begin
VAR23 <= VAR42;
VAR22 <= VAR34;
VAR68 <= VAR28;
VAR25 <= VAR34;
VAR65 <= VAR28;
VAR6 <= VAR28;
VAR26 <= VAR28;
VAR31 <= VAR34;
VAR11 <= 4'b0000;
VAR7 <= VAR28;
VAR1 <= VAR43;
VAR45 <= VAR34;
VAR5 <= 1'b0;
VAR36 <= VAR28;
VAR38 <= 5'b00000;
VAR52 <= VAR34;
end
else begin
VAR23 <= VAR51;
VAR22 <= VAR60;
VAR68 <= VAR56;
VAR25 <= VAR24;
VAR65 <= VAR15;
VAR6 <= VAR54;
VAR26 <= VAR28;
VAR31 <= VAR34;
VAR11 <= 4'b1111;
VAR7 <= VAR28;
VAR1 <= VAR43;
VAR45 <= VAR34;
VAR5 <= 1'b0;
VAR36 <= VAR63;
VAR38 <= VAR10;
VAR52 <= VAR53;
case (VAR14)
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
case (VAR30[1:0])
2'b00: begin
VAR68 <= {{24{VAR57[7]}}, VAR57[7:0]};
VAR11 <= 4'b0001;
end
2'b01: begin
VAR68 <= {{24{VAR57[15]}}, VAR57[15:8]};
VAR11 <= 4'b0010;
end
2'b10: begin
VAR68 <= {{24{VAR57[23]}}, VAR57[23:16]};
VAR11 <= 4'b0100;
end
2'b11: begin
VAR68 <= {{24{VAR57[31]}}, VAR57[31:24]};
VAR11 <= 4'b1000;
end
default: begin
VAR68 <= VAR28;
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
case (VAR30[1:0])
2'b00: begin
VAR68 <= {{16{VAR57[15]}}, VAR57[15:0]};
VAR11 <= 4'b0011;
end
2'b10: begin
VAR68 <= {{16{VAR57[31]}}, VAR57[31:16]};
VAR11 <= 4'b1100;
end
default: begin
VAR68 <= VAR28;
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
VAR11 <= 4'b1111;
case (VAR30[1:0])
2'b00: begin
VAR68 <= {VAR57[7:0], VAR2[23:0]};
VAR11 <= 4'b0001;
end
2'b01: begin
VAR68 <= {VAR57[15:0], VAR2[15:0]};
VAR11 <= 4'b0011;
end
2'b10: begin
VAR68 <= {VAR57[23:0], VAR2[7:0]};
VAR11 <= 4'b0111;
end
2'b11: begin
VAR68 <= VAR57;
VAR11 <= 4'b1111;
end
default: begin
VAR68 <= VAR28;
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
VAR68 <= VAR57;
VAR11 <= 4'b1111;
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
case (VAR30[1:0])
2'b00: begin
VAR68 <= {{24{1'b0}}, VAR57[7:0]};
VAR11 <= 4'b0001;
end
2'b01: begin
VAR68 <= {{24{1'b0}}, VAR57[15:8]};
VAR11 <= 4'b0010;
end
2'b10: begin
VAR68 <= {{24{1'b0}}, VAR57[23:16]};
VAR11 <= 4'b0100;
end
2'b11: begin
VAR68 <= {{24{1'b0}}, VAR57[31:24]};
VAR11 <= 4'b1000;
end
default: begin
VAR68 <= VAR28;
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
case (VAR30[1:0])
2'b00: begin
VAR68 <= {{16{1'b0}}, VAR57[15:0]};
VAR11 <= 4'b0011;
end
2'b10: begin
VAR68 <= {{16{1'b0}}, VAR57[31:16]};
VAR11 <= 4'b1100;
end
default: begin
VAR68 <= VAR28;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
VAR11 <= 4'b1111;
case (VAR30[1:0])
2'b00: begin
VAR68 <= VAR57;
VAR11 <= 4'b1111;
end
2'b01: begin
VAR68 <= {VAR2[31:24], VAR57[31:8]};
VAR11 <= 4'b1110;
end
2'b10: begin
VAR68 <= {VAR2[31:16], VAR57[31:16]};
VAR11 <= 4'b1100;
end
2'b11: begin
VAR68 <= {VAR2[31:8], VAR57[31:24]};
VAR11 <= 4'b1000;
end
default: begin
VAR68 <= VAR28;
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR3;
VAR1 <= VAR44;
VAR7 <= {4{VAR2[7:0]}};
case (VAR30[1:0])
2'b00: begin
VAR11 <= 4'b0001;
end
2'b01: begin
VAR11 <= 4'b0010;
end
2'b10: begin
VAR11 <= 4'b0100;
end
2'b11: begin
VAR11 <= 4'b1000;
end
default: begin
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR3;
VAR1 <= VAR44;
VAR7 <= {2{VAR2[15:0]}};
case (VAR30[1:0])
2'b00: begin
VAR11 <= 4'b0011;
end
2'b10: begin
VAR11 <= 4'b1100;
end
default: begin
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR3;
VAR1 <= VAR44;
case (VAR30[1:0])
2'b00: begin
VAR7 <= {VAR9[31:8], VAR2[31:24]};
VAR11 <= 4'b0001;
end
2'b01: begin
VAR7 <= {VAR9[31:16], VAR2[31:16]};
VAR11 <= 4'b0011;
end
2'b10: begin
VAR7 <= {VAR9[31:24], VAR2[31:8]};
VAR11 <= 4'b0111;
end
2'b11: begin
VAR7 <= VAR2;
VAR11 <= 4'b1111;
end
default: begin
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR3;
VAR1 <= VAR44;
VAR7 <= VAR2;
VAR11 <= 4'b1111;
end
VAR26 <= VAR30;
VAR31 <= VAR3;
VAR1 <= VAR44;
case (VAR30[1:0])
2'b00: begin
VAR7 <= VAR2;
VAR11 <= 4'b1111;
end
2'b01: begin
VAR7 <= {VAR2[23:0], VAR9[7:0]};
VAR11 <= 4'b1110;
end
2'b10: begin
VAR7 <= {VAR2[15:0], VAR9[15:0]};
VAR11 <= 4'b1100;
end
2'b11: begin
VAR7 <= {VAR2[7:0], VAR9[23:0]};
VAR11 <= 4'b1000;
end
default: begin
VAR11 <= 4'b0000;
end
endcase
end
VAR26 <= VAR30;
VAR31 <= VAR34;
VAR1 <= VAR44;
VAR68 <= VAR57;
VAR11 <= 4'b1111;
VAR45 <= VAR3;
VAR5 <= 1'b1;
end
if (VAR18 == 1'b1) begin
VAR26 <= VAR30;
VAR31 <= VAR3;
VAR1 <= VAR44;
VAR68 <= 32'b1;
VAR7 <= VAR2;
VAR11 <= 4'b1111;
VAR45 <= VAR3;
VAR5 <= 1'b0;
end
else begin
VAR68 <= 32'b0;
end
end
default: begin
end
endcase
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/and4/sky130_fd_sc_lp__and4_4.v
| 2,242 |
module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR11 ,
VAR5,
VAR9,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR11 ;
input VAR5;
input VAR9;
input VAR6 ;
input VAR8 ;
VAR10 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR1,
VAR3,
VAR2,
VAR11
);
output VAR4;
input VAR1;
input VAR3;
input VAR2;
input VAR11;
supply1 VAR5;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR8 ;
VAR10 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR11(VAR11)
);
endmodule
|
apache-2.0
|
ncos/Xilinx-Verilog
|
INTERFACES/src/CAN/queue.v
| 2,990 |
module MODULE1 #
(
parameter integer VAR14 = 108,
parameter integer VAR12 = 4
)
(
input wire VAR16,
input wire VAR11,
input wire VAR4,
input wire VAR3,
output reg VAR5 = 1'b0,
output reg VAR1 = 1'b1,
input wire [VAR14-1:0] VAR15,
output reg [VAR14-1:0] VAR9
);
reg [VAR14-1:0] VAR7[0:VAR12-1];
reg [63:0] head = 64'd0;
reg VAR13 = 1'b1;
reg VAR6 = 1'b1;
wire VAR2;
wire VAR10;
assign VAR2 = VAR4 & VAR13;
assign VAR10 = VAR3 & VAR6;
always @(posedge VAR16) begin
if (VAR11 == 1'b1) begin
VAR13 <= 1'b1;
end
else if (VAR4 == 1'b0) begin
VAR13 <= 1'b1;
end
else if (VAR2 == 1'b1) begin
VAR13 <= 1'b0;
end
if (VAR11 == 1'b1) begin
VAR6 <= 1'b1;
end
else if (VAR3 == 1'b0) begin
VAR6 <= 1'b1;
end
else if (VAR10 == 1'b1) begin
VAR6 <= 1'b0;
end
end
integer VAR8 = 0;
always @(posedge VAR16) begin
if (VAR10 & !VAR2) begin
for (VAR8 = VAR12 - 1; VAR8 > 0; VAR8 = VAR8 - 1) begin
VAR7[VAR8] <= VAR7[VAR8 - 1];
end
VAR7[0] <= VAR15;
end
if (VAR2 & !VAR10 & !VAR1) begin
VAR9 <= VAR7[head - 64'd1];
end
else if (VAR2 & VAR10) begin
VAR9 <= VAR15;
end
end
always @(posedge VAR16) begin
if (VAR11 == 1'b1) begin
head <= 64'd0;
VAR5 <= 1'b0;
VAR1 <= 1'b1;
end
else if (!VAR5 & VAR10 & !VAR2) begin
head <= head + 64'd1;
VAR1 <= 1'b0; if (head == VAR12 - 1) begin
VAR5 <= 1'b1;
end
end
else if (!VAR1 & VAR2 & !VAR10) begin
head <= head - 64'd1;
VAR5 <= 1'b0; if (head == 64'd1) begin
VAR1 <= 1'b1;
end
end
else begin
head <= head;
VAR5 <= VAR5;
VAR1 <= VAR1;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/decap/sky130_fd_sc_hd__decap.pp.blackbox.v
| 1,198 |
module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR4
);
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/phy_init.v
| 138,478 |
module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR127 = 4, parameter VAR72 = 3000, parameter VAR87 = 0, parameter VAR166 = 64, parameter VAR313 = 2,
parameter VAR121 = 10,
parameter VAR277 = 1, parameter VAR10 = 64,
parameter VAR160 = 8,
parameter VAR297 = 3, parameter VAR48 = 14,
parameter VAR7 = 1,
parameter VAR199 = 1, parameter VAR262 = 1, parameter VAR188 = "VAR288",
parameter VAR198 = "VAR183",
parameter VAR4= "1T",
parameter VAR141 = 16'h0000, parameter VAR285 = 12'h000, parameter VAR230 = 3'h0,
parameter VAR116 = "0", parameter VAR289 = "8", parameter VAR261 = "VAR294", parameter VAR283 = 5, parameter VAR19 = 5, parameter VAR41 = 110000, parameter VAR18 = "VAR225", parameter VAR73 = "60", parameter VAR50 = "60", parameter VAR164 = "VAR183", parameter VAR201 = "VAR236", parameter VAR241 = 1, parameter VAR186 = "VAR321", parameter VAR247 = "VAR321" )
(
input clk,
input rst,
input [VAR166-1:0] VAR5,
input VAR193,
input VAR51,
input VAR111,
input VAR118,
output VAR69,
output VAR304,
input VAR34,
input VAR68,
input VAR293,
input VAR151,
input VAR192,
input [5:0] VAR22,
input [6*VAR199-1:0] VAR221,
input VAR53,
input VAR324,
input VAR38,
input [7:0] VAR85,
input [7:0] VAR307,
output reg VAR83,
output reg VAR207,
output reg VAR205,
output reg VAR255,
input VAR117,
input VAR142,
output reg VAR60,
output reg VAR209,
output reg VAR81,
input VAR26,
input VAR218,
input VAR97,
output reg VAR322,
output reg VAR1,
output reg VAR35,
output reg VAR196,
output reg [VAR127*VAR48-1:0] VAR77,
output reg [VAR127*VAR313-1:0]VAR278,
output reg [VAR127-1:0] VAR155,
output reg [VAR127-1:0] VAR21,
output reg [VAR127-1:0] VAR17,
output reg VAR134,
output [VAR7*VAR277*VAR127-1:0] VAR40,
input VAR90,
input VAR238,
input VAR319,
input VAR182,
output reg VAR295,
output reg VAR37,
output reg [1:0] VAR213,
output reg VAR280,
output reg VAR13,
output reg [2:0] VAR243,
output reg [3:0] VAR82,
output [1:0] VAR95,
output reg [1:0] VAR57,
output reg [5:0] VAR271,
output reg VAR195,
output reg [2*VAR127*VAR10-1:0] VAR172,
output VAR130,
output VAR113
);
localparam VAR212 = (VAR289 == "8") ? 128 :
(VAR289 == "4") ? 256 : 128;
localparam VAR29 = (VAR289 == "8") ? 8 :
(VAR289 == "4") ? 4 : 8;
localparam VAR208 = "40";
localparam VAR6 = "40";
localparam VAR106 = (VAR87 == 1) ? VAR73 : VAR50;
localparam VAR129 = (VAR188 == "VAR288")? 1'b0 :
(VAR289 == "8") ? 1'b0 :
((VAR289 == "4") ? 1'b1 : 1'b0);
localparam VAR272 = VAR72 / VAR127;
localparam VAR76 = 200000;
localparam VAR114 = 500000 + VAR76;
localparam VAR264 = 200000;
localparam VAR190 =
((VAR76+VAR72-1)/VAR72);
localparam VAR133 = (VAR188 == "VAR288") ?
(((VAR114+VAR72-1)/VAR72)) :
(((VAR264+VAR72-1)/VAR72));
localparam VAR98 = 400000;
localparam VAR219 =
((VAR98+VAR72-1)/VAR72)-1;
localparam VAR30 =
(5*VAR272 > VAR41+10000) ?
(((5+VAR127-1)/VAR127)-1)+11 :
(((VAR41+10000+VAR72-1)/VAR72)-1)+11;
localparam VAR135 = 255;
localparam VAR310 = ((15000) % VAR272) ?
(15000/VAR272) + 1 : 15000/VAR272;
localparam VAR93 = 7'b1111111;
localparam VAR216 = 2'b00;
localparam VAR96 = 2'b01;
localparam VAR282 = 2'b10;
localparam VAR222 = 2'b11;
localparam VAR163 = 2'b11;
localparam VAR214 = 8'b00000000;
localparam VAR64 = (VAR199 <= 2) ? 8'b00110001 : 8'b00000001;
localparam VAR8 = 8'b00000010;
localparam VAR312 = 8'b00000011;
localparam VAR232 = 8'b00000100;
localparam VAR36 = 8'b00000101;
localparam VAR80 = (VAR116 == "VAR248-1") ? VAR283 - 1 : 0;
localparam VAR298 = (VAR198 == "VAR183") ? VAR19 + VAR80 + 1 : VAR19 + VAR80;
localparam VAR67 = 40000/(VAR72/1000);
localparam VAR240 = 6'b000000; localparam VAR296 = 6'b000001; localparam VAR197 = 6'b000010; localparam VAR44 = 6'b000011; localparam VAR88 = 6'b000100; localparam VAR292 = 6'b000101; localparam VAR123 = 6'b000110; localparam VAR39 = 6'b000111; localparam VAR249 = 6'b001000; localparam VAR75 = 6'b001001; localparam VAR171 = 6'b001010; localparam VAR70 = 6'b001011; localparam VAR273 = 6'b001100; localparam VAR71 = 6'b001101; localparam VAR33 = 6'b001110; localparam VAR2 = 6'b001111; localparam VAR145 = 6'b010000; localparam VAR138 = 6'b010001; localparam VAR165 = 6'b010010; localparam VAR102 = 6'b010011; localparam VAR200 = 6'b010100; localparam VAR187 = 6'b010101; localparam VAR287 = 6'b010110; localparam VAR235 = 6'b010111; localparam VAR320 = 6'b011000; localparam VAR217 = 6'b011001; localparam VAR254 = 6'b011010; localparam VAR74 = 6'b011011; localparam VAR242 = 6'b011100; localparam VAR257 = 6'b011101; localparam VAR84 = 6'b011110; localparam VAR79 = 6'b011111; localparam VAR315 = 6'b100000; localparam VAR276 = 6'b100001; localparam VAR303 = 6'b100010; localparam VAR150 = 6'b100011; localparam VAR105 = 6'b100100; localparam VAR258 = 6'b100101;
integer VAR229, VAR91, VAR233, VAR170, VAR89, VAR32, VAR227, VAR251;
reg VAR177;
reg VAR206;
reg VAR149;
reg VAR203;
reg [14:0] VAR159;
reg VAR11;
reg VAR43;
reg VAR46;
reg VAR12;
reg VAR316;
reg VAR86;
reg VAR237;
reg VAR252;
reg VAR191;
reg VAR323;
reg [1:0] VAR9;
reg [6:0] VAR152;
reg VAR110;
reg [7:0] VAR226;
reg VAR143;
reg VAR270;
reg [1:0] VAR256;
reg [1:0] VAR154;
reg [1:0] VAR126;
reg VAR139;
reg VAR62;
reg [7:0] VAR314;
reg [9:0] VAR104;
reg VAR250;
reg VAR234;
reg [8:0] VAR156;
reg VAR274;
reg VAR185;
reg [7:0] VAR178;
reg VAR299;
reg VAR281;
reg VAR265;
reg [4:0] VAR204;
reg VAR59;
reg VAR279;
reg VAR120;
reg [5:0] VAR167;
reg [5:0] VAR223;
reg [5:0] VAR24;
wire [15:0] VAR131;
wire [15:0] VAR66;
wire [15:0] VAR244;
wire [15:0] VAR107;
reg VAR290;
reg [1:0] VAR128 [0:3];
reg [2:0] VAR305 [0:3];
reg VAR42;
reg [15:0] VAR99;
wire VAR157;
reg [VAR127-1:0] VAR144;
reg [VAR127-1:0] VAR136;
reg [VAR7*VAR277-1:0] VAR20;
reg [VAR7*VAR277*VAR127-1:0] VAR220;
wire VAR275;
reg [15:0] VAR231;
reg VAR269;
reg VAR31;
reg VAR55;
reg VAR180;
reg VAR124;
reg VAR286;
reg [VAR48-1:0] VAR146;
reg [VAR313-1:0] VAR140;
reg VAR184;
reg [15:0] VAR27;
reg VAR101;
reg VAR202;
wire VAR115;
wire VAR14;
reg VAR176;
wire VAR309;
reg [2:0] VAR25;
reg [1:0] VAR302 [0:3];
reg [2:0] VAR215 [0:3];
reg VAR189;
reg VAR267;
reg VAR49;
reg VAR246;
reg VAR52;
reg VAR263;
reg VAR108;
reg VAR284;
reg VAR318;
reg [2:0] VAR266;
reg VAR28;
reg VAR194;
reg VAR3;
reg VAR181;
reg [1:0] VAR210;
reg [8:0] VAR291;
reg VAR92;
reg VAR211;
reg [1:0] VAR317;
reg [VAR166-1:0] VAR112;
reg [VAR166-1:0] VAR61;
reg [VAR166-1:0] VAR301;
reg [VAR166-1:0] VAR15;
reg [VAR166-1:0] VAR224;
reg [VAR166-1:0] VAR153;
reg [VAR166-1:0] VAR65;
always @(posedge VAR290) begin
if (!rst)
end
always @(posedge VAR293) begin
if (!rst && (VAR164 == "VAR183"))
end
always @(posedge VAR117) begin
if (!rst)
end
always @(posedge VAR191) begin
if (!rst)
end
always @(posedge VAR111) begin
if (!rst)
end
always @(posedge VAR324) begin
if (!rst && (VAR164 == "VAR183"))
end
assign VAR304 = VAR191;
always @(posedge clk)
if (rst)
else if ((VAR223 == VAR33) || (VAR223 == VAR2)
|| (VAR223 == VAR276) || (VAR223 == VAR303))
else
always @(posedge clk)
if (rst)
else if (VAR223 == VAR105)
else
always @(posedge clk)
if (rst) begin
end else begin
if (VAR223 == VAR287)
end
generate
if(VAR188 == "VAR288") begin: VAR78
assign VAR131[1:0] = (VAR289 == "8") ? 2'b00 :
(VAR289 == "VAR245") ? 2'b01 :
(VAR289 == "4") ? 2'b10 : 2'b11;
assign VAR131[2] = (VAR283 >= 12) ? 1'b1 : 1'b0; assign VAR131[3] = (VAR261 == "VAR294") ? 1'b0 : 1'b1;
assign VAR131[6:4] = ((VAR283 == 5) || (VAR283 == 13)) ? 3'b001 :
((VAR283 == 6) || (VAR283 == 14)) ? 3'b010 :
(VAR283 == 7) ? 3'b011 :
(VAR283 == 8) ? 3'b100 :
(VAR283 == 9) ? 3'b101 :
(VAR283 == 10) ? 3'b110 :
(VAR283 == 11) ? 3'b111 :
(VAR283 == 12) ? 3'b000 : 3'b111;
assign VAR131[7] = 1'b0;
assign VAR131[8] = 1'b1; assign VAR131[11:9] = (VAR310 == 5) ? 3'b001 :
(VAR310 == 6) ? 3'b010 :
(VAR310 == 7) ? 3'b011 :
(VAR310 == 8) ? 3'b100 :
(VAR310 == 9) ? 3'b101 :
(VAR310 == 10) ? 3'b101 :
(VAR310 == 11) ? 3'b110 :
(VAR310 == 12) ? 3'b110 :
(VAR310 == 13) ? 3'b111 :
(VAR310 == 14) ? 3'b111 :
(VAR310 == 15) ? 3'b000 :
(VAR310 == 16) ? 3'b000 : 3'b010;
assign VAR131[12] = 1'b0; assign VAR131[15:13] = 3'b000;
end else if (VAR188 == "VAR162") begin: VAR132 assign VAR131[2:0] = (VAR289 == "8") ? 3'b011 :
(VAR289 == "4") ? 3'b010 : 3'b111;
assign VAR131[3] = (VAR261 == "VAR294") ? 1'b0 : 1'b1;
assign VAR131[6:4] = (VAR283 == 3) ? 3'b011 :
(VAR283 == 4) ? 3'b100 :
(VAR283 == 5) ? 3'b101 :
(VAR283 == 6) ? 3'b110 : 3'b111;
assign VAR131[7] = 1'b0;
assign VAR131[8] = 1'b1; assign VAR131[11:9] = (VAR310 == 2) ? 3'b001 :
(VAR310 == 3) ? 3'b010 :
(VAR310 == 4) ? 3'b011 :
(VAR310 == 5) ? 3'b100 :
(VAR310 == 6) ? 3'b101 : 3'b010;
assign VAR131[15:12]= 4'b0000; end
endgenerate
generate
if(VAR188 == "VAR288") begin: VAR100
assign VAR66[0] = 1'b0; assign VAR66[1] = (VAR18 == "VAR174") ? 1'b0 : 1'b1;
assign VAR66[2] = ((VAR106 == "30") || (VAR106 == "40") ||
(VAR106 == "60")) ? 1'b1 : 1'b0;
assign VAR66[4:3] = (VAR116 == "0") ? 2'b00 :
(VAR116 == "VAR248-1") ? 2'b01 :
(VAR116 == "VAR248-2") ? 2'b10 : 2'b11;
assign VAR66[5] = 1'b0;
assign VAR66[6] = ((VAR106 == "40") || (VAR106 == "120")) ?
1'b1 : 1'b0;
assign VAR66[7] = 1'b0; assign VAR66[8] = 1'b0;
assign VAR66[9] = ((VAR106 == "20") || (VAR106 == "30")) ?
1'b1 : 1'b0;
assign VAR66[10] = 1'b0;
assign VAR66[15:11] = 5'b00000;
end else if (VAR188 == "VAR162") begin: VAR260
assign VAR66[0] = 1'b0; assign VAR66[1] = (VAR18 == "VAR174") ? 1'b1 : 1'b0;
assign VAR66[2] = ((VAR106 == "75") || (VAR106 == "50")) ?
1'b1 : 1'b0;
assign VAR66[5:3] = (VAR116 == "0") ? 3'b000 :
(VAR116 == "1") ? 3'b001 :
(VAR116 == "2") ? 3'b010 :
(VAR116 == "3") ? 3'b011 :
(VAR116 == "4") ? 3'b100 : 3'b111;
assign VAR66[6] = ((VAR106 == "50") ||
(VAR106 == "150")) ? 1'b1 : 1'b0;
assign VAR66[9:7] = 3'b000;
assign VAR66[10] = (VAR201 == "VAR236") ? 1'b0 : 1'b1;
assign VAR66[15:11] = 5'b00000;
end
endgenerate
generate
if(VAR188 == "VAR288") begin: VAR63
assign VAR244[2:0] = 3'b000;
assign VAR244[5:3] = (VAR19 == 5) ? 3'b000 :
(VAR19 == 6) ? 3'b001 :
(VAR19 == 7) ? 3'b010 :
(VAR19 == 8) ? 3'b011 :
(VAR19 == 9) ? 3'b100 :
(VAR19 == 10) ? 3'b101 :
(VAR19 == 11) ? 3'b110 : 3'b111;
assign VAR244[6] = 1'b0;
assign VAR244[7] = 1'b0;
assign VAR244[8] = 1'b0;
assign VAR244[10:9] = 2'b00;
assign VAR244[15:11] = 5'b00000;
end else begin: VAR300
assign VAR244[15:0] = 16'd0;
end
endgenerate
assign VAR107[1:0] = 2'b00;
assign VAR107[2] = 1'b0;
assign VAR107[15:3] = 13'b0000000000000;
assign VAR95 = VAR9;
assign VAR157 = (VAR223 == VAR150);
assign VAR275 = (((VAR223 == VAR145) ||
(VAR202 && (VAR223 == VAR71) && VAR110) ||
(VAR223 == VAR138) ||
((VAR223 == VAR315) && VAR110)) &&
VAR269 &&
!VAR31);
always @(posedge clk) begin
VAR101};
VAR157};
VAR275};
end
always @(posedge clk)
generate
if (VAR199 < 2) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR111 && VAR110 &&
(VAR223 == VAR71))
if (VAR111 &&
(VAR223 == VAR145))begin
end
end
end else begin
always @(posedge clk)
if (rst || VAR142) begin
end else begin
if (VAR111 && VAR110 &&
(VAR223 == VAR71))
if (VAR111 &&
(VAR223 == VAR145))begin
end
end
end
endgenerate
always @(posedge clk) begin
if (rst || VAR118) begin
end else begin
if (!VAR111 && VAR223 == VAR138)
if (VAR99[5])
end
end
always @(posedge clk)
if (rst)
end
else
always @(posedge clk)
if (rst || (VAR223 == VAR145))
end
else if ((VAR223 == VAR71) &&
( VAR46 == 1'b1))
always @(posedge clk)
if (rst ||
((VAR24 != VAR123) &&
(VAR223 == VAR123)))
end
else if (VAR151 && ~VAR49)
generate
if (VAR127 == 4) begin: VAR169
always @ (posedge clk)
if (rst)
end
else if ((VAR223 == VAR123) ||
(VAR194 && (VAR204 == 5'd0)))
end
else if ((VAR204 > 5'd0) && ~(VAR238 || VAR319))
always @(posedge clk)
if (rst || VAR28)
end
else if (VAR204 == 5'd1)
end else begin: VAR253
always @ (posedge clk)
if (rst)
end
else if ((VAR223 == VAR123) ||
(VAR194 && (VAR204 == 5'd0)))
end
else if ((VAR204 > 5'd0) && ~(VAR238 || VAR319))
always @(posedge clk)
if (rst || VAR28)
end
else if (VAR204 == 5'd1)
end
endgenerate
always @(posedge clk)
if (rst || VAR151 || VAR192)
else if ((VAR204 == 5'd1) && VAR194 && !VAR3)
always @(posedge clk)begin
if(rst || (VAR204 != 5'd1)) begin
end else if ((VAR204 == 5'd1) && (VAR181)) begin
end
end
always @ (posedge clk) begin
if (rst)
end
else if (VAR92 && VAR317 != 2'd3)
end
always @ (posedge clk) begin
if (rst || ~VAR3)
end
else if (VAR317 == 2'd3)
end
always @(posedge clk) begin
if (rst)
end
else
end
always @(posedge clk) begin
end
always @ (posedge clk) begin
if (rst)
end
else if (VAR151)
end
assign VAR179 = VAR26 | VAR38;
always @(posedge clk)
if (rst) begin
end else begin
if (VAR31)
end
else if (VAR275)
end
always @(posedge clk) begin
case (VAR223)
VAR44,
VAR75,
VAR70,
VAR71,
VAR2,
VAR165,
VAR315,
VAR303,
VAR105,
VAR102,
VAR187,
VAR320,
VAR242,
VAR254: begin
if (VAR238 || VAR319)
end
else
end
VAR39:
default:
endcase
end
always @(posedge clk)
always @(posedge clk) begin
if (rst)
end
else if ((VAR152 == VAR93) &&
(VAR223 == VAR165))
else
end
always @(posedge clk)
if (rst) begin
end else begin
end
always @(posedge clk)
if (rst)
end
else if (VAR180)
always @(posedge clk)
if (rst || ~VAR90) begin
end else begin
if ((VAR186 == "VAR306") ||
(VAR186 == "VAR173")) begin
end else begin
if (VAR188 == "VAR288") begin
if (!VAR274)
VAR274
if (!VAR250)
VAR250
VAR250
end
end
end
always @(posedge clk)
always @(posedge clk) begin
end
always @(posedge clk)
if (!VAR250) begin
end else begin
if (!VAR185)
end
always @(posedge clk)
if (!VAR250) begin
end else begin
if (!VAR62)
VAR62
end
always @(posedge clk)
if (VAR223 == VAR88) begin
end else if (~(VAR238 || VAR319)) begin
if (!VAR143)
VAR143
end
always @(posedge clk)
if ((VAR223 == VAR240)||
((VAR223 == VAR217)
&& (~VAR290))) begin
end else if (VAR223 == VAR197) begin
end
always @(posedge clk)
if (VAR223 == VAR240)
end
else if (VAR223 == VAR197)
end
else if ((VAR281) &&
(VAR223 == VAR44)&&
(VAR110) && (VAR139))
always @(posedge clk)
if (VAR223 == VAR240)
end
else if ((VAR223 == VAR217) && (~VAR290))
end
else if ((VAR281) &&
(VAR223 == VAR44)&&
(VAR110) && (VAR139))
always @(posedge clk)
if (VAR223 == VAR240) begin
end else if ((VAR223 == VAR217) && (~VAR290))begin
end
always @(posedge clk)
if (VAR223 == VAR240)
end
else if (VAR223 == VAR74)
generate
if (VAR199 < 2) begin: VAR228
always @(posedge clk)
if (VAR223 == VAR240)
end
else if (VAR223 == VAR2)
end else begin: VAR56
always @(posedge clk)
if ((VAR223 == VAR240) ||
(VAR142 ))
end
else if (VAR223 == VAR2)
end
endgenerate
always @(posedge clk)
if (rst)
end
else if (VAR11 &&
(VAR223 == VAR254) && VAR110)
always @(posedge clk)
if (rst)begin
end else begin
end
always @(VAR323 or VAR9 or VAR110
or VAR143 or VAR270
or VAR139 or VAR90 or VAR238
or VAR68 or VAR11 or VAR218
or VAR319 or VAR210 or VAR43
or VAR62 or VAR250
or VAR185 or VAR299
or VAR281 or VAR265
or VAR223 or VAR290 or VAR118
or VAR31 or VAR324 or VAR97
or VAR117 or VAR142 or VAR184
or VAR291 or VAR26 or VAR38
or VAR86 or VAR237 or VAR191
or VAR111 or VAR53 or VAR209
or VAR25 or VAR267 or VAR318) begin
VAR167 = VAR223;
case (VAR223)
VAR240:
if (VAR250 && VAR90
&& ~(VAR238 || VAR319) && VAR68) begin
if (VAR186 == "VAR173")
if (VAR164 == "VAR183")
VAR167 = VAR123;
end
else VAR167 = VAR273;
end
else
VAR167 = VAR296;
end
VAR296:
if ((VAR185) && (VAR188 == "VAR288")
&& ~(VAR238 || VAR319)) begin
if((VAR198 == "VAR183") && ((VAR277 > 1) ||
(VAR199 > 1)))
VAR167 = VAR74;
end
else
VAR167 = VAR197;
end else if ((VAR62) && (VAR188 == "VAR162")
&& ~(VAR238 || VAR319))
VAR167 = VAR235;
VAR74:
VAR167 = VAR242;
VAR242:
if (VAR110 && ~(VAR238 || VAR319)) begin
if(VAR25 == 3'd5)
VAR167 = VAR197;
end
else
VAR167 = VAR74;
end
VAR197:
VAR167 = VAR44;
VAR44:
if (VAR110 && ~(VAR238 || VAR319)) begin
if (VAR117 && VAR111)
VAR167 = VAR200;
end
else if (VAR139)begin
if(VAR188 == "VAR288")
VAR167 = VAR88;
end
else begin if(VAR281)begin
if (!VAR290 && (VAR9 <= VAR199-1))
VAR167 = VAR257;
end
else
VAR167 = VAR273;
end else
VAR167 = VAR235;
end
end else
VAR167 = VAR197;
end
VAR257:
VAR167 = VAR84;
VAR84:
VAR167 = VAR235;
VAR88:
VAR167 = VAR292;
VAR292:
if (VAR143 && ~(VAR238 || VAR319))
if (!VAR290 && (VAR9 <= VAR199-1))
VAR167 = VAR197;
else if (VAR164 == "VAR183")
VAR167 = VAR123;
else
VAR167 = VAR273;
VAR235:
VAR167 = VAR320;
VAR320:
if (VAR110 && ~(VAR238 || VAR319)) begin
if (VAR299)
VAR167 = VAR217;
end
else VAR167 = VAR197;
end
VAR217:
VAR167 = VAR254;
VAR254:
if (VAR110 && ~(VAR238 || VAR319))begin
if(VAR270 && (~VAR290))
VAR167 = VAR197;
end
else if (((VAR117 && VAR111) && (VAR164 == "VAR183"))
&& VAR290)
VAR167 = VAR79;
else if (VAR290) begin
if (VAR199 < 2)
VAR167 = VAR273;
end
else if (VAR11 && ~VAR43 && ~VAR117)
VAR167 = VAR200;
else
VAR167 = VAR273;
end else VAR167 = VAR217;
end
VAR123:
VAR167 = VAR39;
VAR39:
if (VAR318 && ~(VAR238 || VAR319))
VAR167 = VAR249;
VAR249:
VAR167 = VAR75;
VAR75:
if (VAR110 && ~(VAR238 || VAR319))
VAR167 = VAR171;
VAR171:
VAR167 = VAR70;
VAR70:
if (VAR110 && ~(VAR238 || VAR319)) begin
if ((VAR199 == 2) && VAR246)
VAR167 = VAR70;
end
else if (~VAR267)
VAR167 = VAR123;
else if (VAR247 == "VAR125")
VAR167 = VAR287;
else
VAR167 = VAR273;
end
VAR273:
VAR167 = VAR71;
VAR71:
if (VAR110 && ~(VAR238 || VAR319)) begin
if (!VAR191)
VAR167 = VAR258;
end
else if (!VAR111)
VAR167 = VAR138;
else if (!VAR117 && ~VAR11 && ~VAR218)
VAR167 = VAR33;
else if (!VAR117 && VAR184) begin
if (VAR218)
VAR167 = VAR71;
end
else
VAR167 = VAR145;
end else
VAR167 = VAR102;
end
VAR258:
if (VAR206 && ~VAR149)
VAR167 = VAR102;
VAR33:
if (VAR291 == 9'd1)
VAR167 = VAR2;
VAR2:
if (VAR110 && ~(VAR238 || VAR319))
VAR167 = VAR145;
VAR145:
if (VAR142 || VAR117 || VAR31)
VAR167 = VAR102;
VAR138:
if (VAR210 == 'b1)
VAR167 = VAR165;
VAR165:
if (~(VAR238 || VAR319)) begin
if (VAR53 ||
VAR111 || VAR31)
VAR167 = VAR102;
end
else if (VAR110)
VAR167 = VAR138;
end
VAR79:
VAR167 = VAR315;
VAR315:
if (VAR110 && ~VAR38)
VAR167 = VAR276;
else if (VAR324 || VAR31)
VAR167 = VAR102;
VAR276:
if (VAR323 == 1'b1)
VAR167 = VAR303;
VAR303:
if (VAR110 && ~(VAR238 || VAR319))
VAR167 = VAR150;
else if (VAR118)
VAR167 = VAR165;
VAR150:
if (VAR323 == 1'b1)
VAR167 = VAR105;
VAR105:
if (~(VAR238 || VAR319)) begin
if (VAR97)
VAR167 = VAR276;
end
else if (VAR324 || VAR31)
VAR167 = VAR102;
else if (VAR118)
VAR167 = VAR165;
end
VAR102:
if (VAR110 && ~(VAR238 || VAR319))
VAR167 = VAR200;
VAR200:
VAR167 = VAR187;
VAR187:
if (VAR110 && ~(VAR238 || VAR319)) begin
if ((VAR324 || (VAR164 == "VAR47")) && VAR117 &&
VAR111 && ((VAR265) || (VAR188 == "VAR162")))
VAR167 = VAR287;
end
else if ((VAR324 || (VAR164 == "VAR47")) && VAR117
&& VAR111)
VAR167 = VAR197;
else if (VAR117 && VAR111 && (VAR164 == "VAR183"))
VAR167 = VAR217;
else
VAR167 = VAR217;
end
VAR287:
VAR167 = VAR287;
endcase
end
always @(posedge clk)
if (rst)
else if ((!VAR143 &&
(VAR226 == VAR135) &&
(VAR9 == VAR199-1) && (VAR188 == "VAR288"))
|| ( (VAR223 == VAR44) &&
(VAR281) && (VAR9 == VAR199-1)
&& (VAR139) && (VAR188 == "VAR162")))
generate
if (VAR199 < 2) begin: VAR54
always @(posedge clk) begin
if (rst || VAR192)
end
else if (VAR181)
end
end else begin: VAR119
always @(posedge clk) begin
if (rst ||
((VAR223 == VAR75) &&
(VAR189 || (VAR247 == "VAR109"))))
end
else if (VAR181)
end
end
endgenerate
always @(posedge clk) begin
if (rst || VAR191)
end
else if (~VAR191 && (VAR223 == VAR71) &&
(VAR152 == VAR93))
end
always @(posedge clk)
always @(posedge clk) begin
if (rst || VAR191)
end
else if (~VAR191 && (VAR223 == VAR258))
end
always @(posedge clk)
if (rst)
else if (VAR203 && (VAR9 == VAR199-1))
always @(posedge clk)
if (rst)
else if (VAR206 && ~VAR149)
else
always @(posedge clk) begin
if (rst)
end
else if ((VAR223 == VAR258) &&
(VAR159 != VAR67))
else
end
assign VAR69 = (VAR159 == VAR67) ? 1'b1 : 1'b0;
always @(posedge clk)
if (rst)
else if ((VAR223 == VAR44) && VAR324)
always @(posedge clk) begin
end
generate
if (VAR199 < 2) begin: VAR137
always @(posedge clk)
end else begin: VAR311
always @(posedge clk)
if (rst || VAR117 || (VAR189 &&
(VAR223==VAR70)))begin
end else if ((((VAR223 == VAR292) &&
(VAR226 == VAR135)) ||
((VAR223!=VAR70) &&
(VAR167==VAR70)) &&
(VAR188 == "VAR288")) ||
(VAR142 && ~VAR218) ||
(VAR11 && (VAR223 == VAR217) &&
~(VAR43 && VAR218)) ||
(~VAR177 &&
(VAR167==VAR102)&&
(VAR152=='d36)) ||
(VAR53 && ~VAR12) ||
((VAR223 == VAR44)&& VAR110
&& VAR324) ||
((VAR223 == VAR257)
&& (VAR188 == "VAR162"))) begin
if ((~VAR290 || ~VAR117 || ~VAR111 ||
~VAR252 || VAR324)
&& (VAR9 != VAR199-1))
end
else
end
end
endgenerate
generate
if ((VAR198 == "VAR183") && (VAR199 == 1)) begin: VAR239
always @(posedge clk) begin
if (rst)
end
else if (VAR223 == VAR74) begin
end else begin
for (VAR251 = 0; VAR251 < VAR277*VAR127; VAR251 = VAR251 + VAR277) begin
end
end
end
end else if (VAR199 == 1) begin: VAR103
always @(posedge clk) begin
if (rst)
end
else
end
end else if (VAR199 == 2) begin: VAR268
always @(posedge clk) begin
if (rst)
end
else if (VAR223 == VAR74)
end
else begin
case (VAR9)
2'b00:begin
for (VAR32 = 0; VAR32 < VAR277*VAR127*2; VAR32 = VAR32 + (VAR277*2)) begin
end
end
2'b01:begin
for (VAR227 = VAR277; VAR227 < VAR277*VAR127*2; VAR227 = VAR227 + (VAR277*2)) begin
end
end
endcase
end
end end
/* end else begin: VAR162
always @(posedge clk)
if (rst) begin
end else begin
if (VAR223 == VAR74) begin
end else if ((VAR194) ||
(VAR223 == VAR197) ||
(VAR223 == VAR88) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR273) ||
(VAR223 == VAR258) ||
(VAR223 == VAR33) ||
(VAR223 == VAR145) ||
(VAR223 == VAR200) ||
(VAR223 == VAR138) ||
(VAR223 == VAR79) ||
(VAR223 == VAR150) ||
(VAR223 == VAR276) ||
(VAR223 == VAR235) ||
(VAR223 == VAR217)) begin
end
end end endgenerate
assign VAR40 = VAR220;
assign VAR14 = (VAR223 == VAR33) ||
(VAR223 == VAR276);
assign VAR115 = (VAR223 == VAR258) ||
(VAR223 == VAR145) ||
(VAR223 == VAR138) ||
(VAR223 == VAR150);
assign VAR309 = VAR14 | VAR115;
always @(posedge clk)
if (rst || VAR324)
end
else if ((VAR223 == VAR315) ||
(VAR223 == VAR276) ||
(VAR223 == VAR303) ||
(VAR223 == VAR150) ||
(VAR223 == VAR105))
end
else if (VAR309 && VAR42)
else
always @(posedge clk)
if (rst || (VAR223 == VAR2) ||
VAR117 || (VAR291==9'd0))
else if ((VAR223 == VAR33) && VAR42)
always @(posedge clk)
if (rst || (VAR223 == VAR165))
else if ((VAR210 > 2'b00) && ~(VAR238 || VAR319))
else if ((VAR223 == VAR138) || VAR238 ||
VAR319 && VAR42)
always @(posedge clk)
if (VAR309) begin
if (VAR127 == 2) begin
if (!VAR238)
end else
end else
always @(posedge clk) begin
end
generate
if ((VAR127 == 4) || (VAR289 == "4")) begin: VAR158
always @(VAR182 or VAR223) begin
if (~VAR182 && ((VAR223 == VAR33) ||
(VAR223 == VAR276)))
VAR124 = 1'b1;
end
else
VAR124 = 1'b0;
end
end else begin: VAR259 always @(VAR14 or VAR238 or VAR42 or VAR286
or VAR182)
if((VAR14 & ~VAR238 & VAR42 & ~VAR182)
| VAR286)
VAR124 = 1'b1;
end
else
VAR124 = 1'b0;
always @(posedge clk)
& ~VAR182;
end
endgenerate
assign VAR130 = ~VAR34;
assign VAR113 = (VAR279) ? VAR130 : 1'b0;
always @(posedge clk)
if ((VAR223 == VAR240) ||
(VAR223 == VAR33))
else if (VAR124)
else if (VAR223 == VAR276)
always @(posedge clk) begin
end
generate
if (VAR127 == 4) begin: VAR168
always @(posedge clk)
if (!VAR117)
VAR61[VAR10-1:0],VAR301[VAR10-1:0],
VAR15[VAR10-1:0],VAR224[VAR10-1:0],
VAR153[VAR10-1:0],VAR65[VAR10-1:0]};
end
else if (VAR117)
{VAR10/4{4'hA}},{VAR10/4{4'h5}},
{VAR10/4{4'h5}},{VAR10/4{4'hA}},
{VAR10/4{4'h0}},{VAR10/4{4'hF}}};
end else begin: VAR45
always @(posedge clk)
if (!VAR117)
VAR112[VAR10-1:0],
VAR61[VAR10-1:0],
VAR301[VAR10-1:0]};
end
else begin
if (!VAR286)
{VAR10/4{4'hA}},
{VAR10/4{4'h0}},
{VAR10/4{4'hF}}};
end
else
{VAR10/4{4'h9}},
{VAR10/4{4'hA}},
{VAR10/4{4'h5}}};
end
end
endgenerate
generate
if (VAR127 == 4) begin: VAR58
always @(posedge clk) begin
end
end
endgenerate
generate
if (!(VAR298 % 2)) begin: VAR122
always @(posedge clk) begin
if ((VAR223 == VAR197) ||
(VAR223 == VAR74) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR273) ||
(VAR223 == VAR79) ||
(VAR223 == VAR200) ||
(VAR223 == VAR235) ||
(VAR223 == VAR217))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR223 == VAR197) ||
(VAR223 == VAR74) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR217) ||
(VAR309 && VAR42))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR223 == VAR197) ||
(VAR223 == VAR74) ||
(VAR223 == VAR88) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR200) ||
(VAR223 == VAR235)||
(VAR14 && VAR42))begin
end else begin
end
end
end else begin: VAR325
always @(posedge clk) begin
if ((VAR223 == VAR197) ||
(VAR223 == VAR74) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR273) ||
(VAR223 == VAR79) ||
(VAR223 == VAR200) ||
(VAR223 == VAR235) ||
(VAR223 == VAR217))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR223 == VAR197) ||
(VAR223 == VAR74) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR217) ||
(VAR309 && VAR42))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR223 == VAR197) ||
(VAR223 == VAR74) ||
(VAR223 == VAR88) ||
(VAR223 == VAR123) ||
(VAR223 == VAR249) ||
(VAR223 == VAR171) ||
(VAR223 == VAR200) ||
(VAR223 == VAR235)||
(VAR14 && VAR42))begin
end else begin
end
end
end
endgenerate
always @(posedge clk) begin
if (VAR92) begin
end
end else if (VAR14 && VAR42) begin
end
end else if (VAR115 && VAR42) begin
if (VAR298 % 2)
end
else
if (~VAR191)
end
else if (~VAR46)
end
else
end else begin
if (VAR298 % 2)
end
else
end
end
always @(posedge clk) begin
if (rst) begin
end else if (VAR250 && VAR90
&& ~(VAR238 || VAR319 )) begin
end else begin
end
end
generate
genvar VAR147;
for (VAR147 = 0; VAR147 < 4; VAR147 = VAR147 + 1) begin: VAR308
always @(posedge clk) begin
if (rst) begin
end else begin
end
end
end
endgenerate
generate
if (VAR241 == 1) begin: VAR148
always @(posedge clk) begin
if (rst) begin
end else begin
case ({VAR85[0],VAR85[1],
VAR85[2],VAR85[3]})
4'b1111: begin
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
VAR20[((VAR9*VAR277)
end
4'b1000: begin
if ((VAR198 == "VAR183") && (VAR277 > 1)) begin
end else begin
end
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
((VAR126 == 2'd0) || (VAR87 == 1)))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1100: begin
VAR20[((VAR9*VAR277)
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
default: begin
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293)) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
endcase
end
end
end else if (VAR241 == 2) begin: VAR16
always @ (posedge clk) begin
if (rst) begin
end else begin
case ({VAR85[0],VAR85[1],
VAR307[0],VAR307[1]})
4'b1000: begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
end
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293)) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b0010: begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
end
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293)) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b0011: begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
VAR144
end
VAR20[(VAR9*VAR277) +: VAR277]
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1100: begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
end
VAR20[(VAR9*VAR277) +: VAR277]
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1010: begin
if(VAR188 == "VAR162")begin
if(VAR9 == 2'b00)begin
VAR144
VAR144
end else begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
VAR144
(VAR223 == VAR145) ||
(VAR223 == VAR138) ||
(VAR223 == VAR150)) begin
if (VAR9 == 2'b00) begin
VAR144
end else if (VAR9 == 2'b01) begin
VAR144
end
end
end
VAR20[(VAR9*VAR277) +: VAR277]
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR106 == "120") ? 3'b010 :
(VAR106 == "20") ? 3'b100 :
(VAR106 == "30") ? 3'b101 :
3'b011;
2'b10;
(VAR106 == "120") ? 3'b010 :
(VAR106 == "20") ? 3'b100 :
(VAR106 == "30") ? 3'b101 :
3'b011;
end
end
4'b1011: begin
(VAR6 == "120") ? 3'b010 :
(VAR6 == "20") ? 3'b100 :
(VAR6 == "30") ? 3'b101 :
3'b011;
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR106 == "120") ? 3'b010 :
(VAR106 == "20") ? 3'b100 :
(VAR106 == "30") ? 3'b101 :
3'b011;
2'b10;
end
if(VAR188 == "VAR162")begin
if(VAR9 == 2'b00)begin
VAR144
end else begin
VAR144
end
end else begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
if (VAR9[0] == 1'b1) begin
VAR144
end else begin
VAR144
end else if ((VAR223 == VAR145)
|| (VAR223 == VAR258) ||
(VAR223 == VAR138) ||
(VAR223 == VAR150))begin
if (VAR9 == 2'b00) begin
VAR144
end else begin
VAR144
end
end
end
VAR20[(VAR9*VAR277) +: VAR277]
end
4'b1110: begin
(VAR208 == "120") ? 3'b010 :
(VAR208 == "20") ? 3'b100 :
(VAR208 == "30") ? 3'b101 :
3'b011;
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR106 == "120") ? 3'b010 :
(VAR106 == "20") ? 3'b100 :
(VAR106 == "30") ? 3'b101 :
3'b011;
2'b10;
end
if(VAR188 == "VAR162")begin
if(VAR9[1] == 1'b1)begin
VAR144 <=
end else begin
VAR144
end else begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
if (VAR9[1] == 1'b1) begin
VAR144
end else begin
VAR144 <=
end
end else if ((VAR223 == VAR145)
|| (VAR223 == VAR258) ||
(VAR223 == VAR138) ||
(VAR223 == VAR150)) begin
if (VAR9[1] == 1'b1) begin
VAR144[(1*VAR277) +: VAR277]
end else begin
VAR144
end
end
end
VAR20[(VAR9*VAR277) +: VAR277]
end
4'b1111: begin
(VAR208 == "120") ? 3'b010 :
(VAR208 == "20") ? 3'b100 :
(VAR208 == "30") ? 3'b101 :
3'b011;
(VAR6 == "120") ? 3'b010 :
(VAR6 == "20") ? 3'b100 :
(VAR6 == "30") ? 3'b101 :
3'b011;
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293 &&
(VAR266==3'd0))) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
2'b10;
end
if(VAR188 == "VAR162")begin
if(VAR9[1] == 1'b1)begin
VAR144
end else begin
VAR144
end
end else begin
if ( (VAR223 == VAR33) ||
(VAR223 == VAR276)) begin
if (VAR9[0] == 1'b1) begin
VAR144
end else begin
VAR144
end
end else if ((VAR223 == VAR145)
|| (VAR223 == VAR258) ||
(VAR223 == VAR138) ||
(VAR223 == VAR150))begin
if (VAR9[0] == 1'b1) begin
VAR144
end else begin
VAR144
end
end
end
VAR20[(VAR9*VAR277) +: VAR277]
end
default: begin
VAR20[(VAR9*VAR277) +: VAR277]
if ((VAR50 == "VAR47") ||
((VAR164=="VAR183") && ~VAR293)) begin
(VAR106 == "60") ? 3'b001 :
3'b010;
(VAR106 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR106 == "120") ? 3'b010 :
(VAR106 == "20") ? 3'b100 :
(VAR106 == "30") ? 3'b101 :
3'b011;
2'b10;
(VAR106 == "120") ? 3'b010 :
(VAR106 == "20") ? 3'b100 :
(VAR106 == "30") ? 3'b101 :
3'b011;
end
end
endcase
end
end
end
endgenerate
generate
if ((VAR241 == 1) && (VAR199 < 2)) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR250 && ~VAR234)begin
end else begin
end
if ((((VAR73 == "VAR94") && (VAR50 == "VAR47")) ||
VAR151 || VAR49 ||
(VAR293 && !VAR189)) && (VAR188 == "VAR288")) begin
end else if (((VAR188 == "VAR288")
||((VAR73 != "VAR94") && (VAR188 == "VAR162")))
&& (((VAR223 == VAR39) && VAR194) ||
(VAR223 == VAR33) ||
(VAR223 == VAR276))) begin
end else begin
end
end
end else if ((VAR241 == 1) && (VAR199 == 2)) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR250 && ~VAR234)begin
end else begin
end
if ((((VAR73 == "VAR94") && (VAR50 == "VAR47")) ||
VAR246 ||
(VAR293 && !VAR189)) && (VAR188 == "VAR288")) begin
end else if (((VAR188 == "VAR288")
||((VAR73 != "VAR94") && (VAR188 == "VAR162")))
&& (((VAR223 == VAR39) && VAR194) ||
(VAR223 == VAR33) ||
(VAR223 == VAR276))) begin
end else begin
end
end
end else if ((VAR241 == 2) && (VAR199 == 2)) begin
always @(posedge clk)
if (rst)
end
else begin
if (VAR250 && ~VAR234)begin
end else begin
end
if ((((VAR73 == "VAR94") && (VAR50 == "VAR47")) ||
VAR246 ||
(VAR293 && !VAR189)) && (VAR188 == "VAR288")) begin
end else if (((VAR188 == "VAR288")
||((VAR73 != "VAR94") && (VAR188 == "VAR162")))
&& (((VAR223 == VAR39) && VAR194) ||
(VAR223 == VAR33) ||
(VAR223 == VAR276))) begin
if (VAR127 == 2) begin
VAR82[1]
VAR82[3]
end else begin
end
end else begin
end
end
end
endgenerate
always @(VAR323 or VAR126 or VAR9
or VAR281 or VAR223 or VAR131
or VAR66 or VAR244 or VAR107 or VAR305[VAR9]
or VAR128[VAR9] or VAR25 or VAR291
or VAR117 or VAR111 or VAR309)begin
VAR146 = 'b0;
VAR140 = 'b0;
if ((VAR223 == VAR200) ||
(VAR223 == VAR88) ||
(VAR223 == VAR235)) begin
VAR146 = 'b0;
VAR146[10] = 1'b1;
VAR140 = 'b0;
end else if (VAR223 == VAR123) begin
VAR140[1:0] = 2'b01;
VAR146 = VAR66[VAR48-1:0];
VAR146[7] = 1'b1;
end else if (VAR223 == VAR249) begin
VAR140[1:0] = 2'b01;
VAR146 = VAR66[VAR48-1:0];
VAR146[2] = VAR305[VAR9][0];
VAR146[6] = VAR305[VAR9][1];
VAR146[9] = VAR305[VAR9][2];
end else if (VAR223 == VAR171) begin
VAR140[1:0] = 2'b10;
VAR146 = VAR244[VAR48-1:0];
VAR146[10:9] = VAR128[VAR9];
end else if ((VAR223 == VAR74)&
(VAR188 == "VAR288"))begin
VAR140 = 'b0;
VAR146 = 'b0;
case (VAR25)
VAR214[2:0]: VAR146[4:0] = VAR214[4:0];
VAR64[2:0]:begin
VAR146[4:0] = VAR64[4:0];
VAR140 = VAR64[7:5];
end
VAR8[2:0]: VAR146[4:0] = VAR8[4:0];
VAR312[2:0]: VAR146[4:0] = VAR312[4:0];
VAR232[2:0]: VAR146[4:0] = VAR232[4:0];
VAR36[2:0]: VAR146[4:0] = VAR36[4:0];
endcase
end else if (VAR223 == VAR197) begin
VAR146 = 'b0;
VAR140 = 'b0;
if(VAR188 == "VAR288")begin
if(VAR117 && VAR111)begin
VAR140[1:0] = 2'b00;
VAR146 = VAR131[VAR48-1:0];
VAR146[8]= 1'b0; end else begin
case (VAR126)
VAR216: begin
VAR140[1:0] = 2'b10;
VAR146 = VAR244[VAR48-1:0];
VAR146[10:9] = VAR128[VAR9];
end
VAR96: begin
VAR140[1:0] = 2'b11;
VAR146 = VAR107[VAR48-1:0];
end
VAR282: begin
VAR140[1:0] = 2'b01;
VAR146 = VAR66[VAR48-1:0];
VAR146[2] = VAR305[VAR9][0];
VAR146[6] = VAR305[VAR9][1];
VAR146[9] = VAR305[VAR9][2];
end
VAR222: begin
VAR140[1:0] = 2'b00;
VAR146 = VAR131[VAR48-1:0];
VAR146[1:0] = 2'b00;
end
default: begin
VAR140 = {VAR313{1'VAR175}};
VAR146 = {VAR48{1'VAR175}};
end
endcase
end
end else begin case (VAR126)
VAR216: begin
if(~VAR281)begin
VAR140[1:0] = 2'b10;
VAR146 = VAR244[VAR48-1:0];
end else begin VAR140[1:0] = 2'b00;
VAR146 = VAR131[VAR48-1:0];
VAR146[8]= 1'b0;
end
end
VAR96: begin
if(~VAR281)begin
VAR140[1:0] = 2'b11;
VAR146 = VAR107[VAR48-1:0];
end else begin VAR140[1:0] = 2'b00;
VAR146 = VAR131[VAR48-1:0];
VAR146[8]= 1'b0;
end
end
VAR282: begin
VAR140[1:0] = 2'b01;
if(~VAR281)begin
VAR146 = VAR66[VAR48-1:0];
end else begin VAR146 = VAR66[VAR48-1:0];
VAR146[9:7] = 3'b111;
end
end
VAR222: begin
if(~VAR281)begin
VAR140[1:0] = 2'b00;
VAR146 = VAR131[VAR48-1:0];
end else begin VAR140[1:0] = 2'b01;
VAR146 = VAR66[VAR48-1:0];
if((VAR9 == 2'd1) || (VAR9 == 2'd3))begin
VAR146[2] = 'b0;
VAR146[6] = 'b0;
end
end
end
default: begin
VAR140 = {VAR313{1'VAR175}};
VAR146 = {VAR48{1'VAR175}};
end
endcase
end
end else if ((VAR223 == VAR258) ||
(VAR223 == VAR33) ||
(VAR223 == VAR145)) begin
VAR140 = VAR230[VAR313-1:0];
VAR146[VAR48-1:VAR121] = {VAR48-VAR121{1'b0}};
if (VAR291 == VAR212)
VAR146[VAR121-1:0] = {VAR121{1'b0}};
end
else if ((VAR291 >= 9'd0) && VAR42)
VAR146[VAR121-1:0] = VAR77[VAR121-1:0] + VAR29;
end else if ((VAR223 == VAR276) ||
(VAR223 == VAR150) ||
(VAR223 == VAR138)) begin
VAR140 = VAR230[VAR313-1:0];
VAR146[VAR48-1:VAR121] = {VAR48-VAR121{1'b0}};
VAR146[VAR121-1:0] =
{VAR285[VAR121-1:3],VAR323, 3'b000};
VAR146[12] = 1'b1;
end else if ((VAR223 == VAR273) ||
(VAR223 == VAR79)) begin
VAR140 = VAR230[VAR313-1:0];
VAR146 = VAR141[VAR48-1:0];
end else begin
VAR140 = {VAR313{1'VAR175}};
VAR146 = {VAR48{1'VAR175}};
end
end
always @(posedge clk) begin
for (VAR229 = 0; VAR229 < VAR127; VAR229 = VAR229 + 1) begin: VAR161
end
end
endmodule
|
lgpl-3.0
|
joaocarlos/udlx-verilog
|
rtl/decode/control.v
| 2,789 |
module MODULE1
parameter VAR3 = 5
)
(
input VAR10,
input [VAR3-1:0] VAR8,
input VAR4,
input VAR1,
input [VAR3-1:0] VAR2,
input [VAR3-1:0] VAR13,
input VAR6,
output reg VAR11,
output reg VAR5,
output reg VAR7,
output reg VAR12
);
wire VAR9;
assign VAR9 = VAR10 &
(((VAR8==VAR2)&VAR4)|
((VAR8==VAR13)&VAR1));
always@(*)begin
if(VAR6)begin
VAR11 = 1;
VAR5 = 0;
VAR7 = 1;
VAR12 = 1;
end
else if(VAR9)begin
VAR11 = 0;
VAR5 = 1;
VAR7 = 0;
VAR12 = 1;
end
else begin
VAR11 = 1;
VAR5 = 0;
VAR7 = 0;
VAR12 = 0;
end
end
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.v
| 1,315 |
module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR5,
input VAR7,
input VAR2
);
endmodule
|
apache-2.0
|
Ribeiro/sd2snes
|
verilog/sd2snes_cx4/mcu_cmd.v
| 12,874 |
module MODULE1(
input clk,
input VAR28,
input VAR51,
input [7:0] VAR23,
input [7:0] VAR9,
output [2:0] VAR40,
output VAR22,
output VAR34,
output VAR5,
input VAR2,
output [7:0] VAR25,
input [7:0] VAR3,
output [7:0] VAR38,
input [31:0] VAR18,
input [2:0] VAR26,
output [23:0] VAR37,
output [23:0] VAR44,
output [23:0] VAR19,
output VAR12,
input VAR54,
input VAR24,
input [7:0] VAR48,
input VAR50,
output [1:0] VAR17,
output VAR47,
output [10:0] VAR46,
output [10:0] VAR7,
output reg VAR36,
output reg VAR33,
output [10:0] VAR32,
input VAR4,
output VAR10,
output VAR20,
output [13:0] VAR29,
input [6:0] VAR16,
output [5:0] VAR30,
output [5:0] VAR35,
output VAR42,
input [31:0] VAR15,
input [15:0] VAR49,
input [7:0] VAR41,
output [13:0] VAR53,
output VAR1,
output reg [7:0] VAR27,
output reg VAR13,
output reg VAR11,
input VAR52,
input [7:0] VAR39,
output reg [7:0] VAR6,
output reg [8:0] VAR21,
output reg VAR14,
output reg [7:0] VAR8,
output reg [31:0] VAR31,
output reg VAR45,
output reg [15:0] VAR43 = 16'h0000
);
|
gpl-2.0
|
markusC64/1541ultimate2
|
fpga/nios_c5/nios/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v
| 3,035 |
module MODULE1 (
VAR42,
VAR47,
VAR35,
VAR37,
VAR62,
VAR17);
parameter VAR56 = "VAR45.VAR1";
input VAR42;
input [31:0] VAR47;
input [5:0] VAR35;
input [5:0] VAR37;
input VAR62;
output [31:0] VAR17;
tri1 VAR42;
tri0 VAR62;
wire [31:0] VAR27;
wire [31:0] VAR17 = VAR27[31:0];
VAR28 VAR21 (
.VAR64 (VAR37),
.VAR60 (VAR42),
.VAR54 (VAR47),
.VAR23 (VAR62),
.VAR20 (VAR35),
.VAR46 (VAR27),
.VAR61 (1'b0),
.VAR7 (1'b0),
.VAR26 (1'b0),
.VAR51 (1'b0),
.VAR63 (1'b1),
.VAR55 (1'b1),
.VAR59 (1'b1),
.VAR36 (1'b1),
.VAR3 (1'b1),
.VAR57 (1'b1),
.VAR31 (1'b1),
.VAR50 ({32{1'b1}}),
.VAR48 (),
.VAR40 (),
.VAR34 (1'b0),
.VAR19 (1'b1),
.VAR39 (1'b0));
VAR21.VAR6 = "VAR4",
VAR21.VAR38 = "VAR13",
VAR21.VAR16 = "VAR58",
VAR21.VAR10 = "VAR58",
VAR21.VAR43 = "VAR58",
VAR21.VAR33 = "VAR45.VAR52"
VAR21.VAR33 = VAR56
,
VAR21.VAR25 = "VAR44 VAR29",
VAR21.VAR22 = "VAR28",
VAR21.VAR14 = 40,
VAR21.VAR11 = 40,
VAR21.VAR32 = "VAR18",
VAR21.VAR30 = "VAR4",
VAR21.VAR2 = "VAR13",
VAR21.VAR41 = "VAR49",
VAR21.VAR12 = "VAR15",
VAR21.VAR5 = 6,
VAR21.VAR24 = 6,
VAR21.VAR9 = 32,
VAR21.VAR53 = 32,
VAR21.VAR8 = 1;
endmodule
|
gpl-3.0
|
kevintownsend/convey_spmv
|
rtl/pe/x_vector_cache.v
| 4,514 |
module MODULE1(clk, rst, VAR29, VAR51, VAR3, VAR6, VAR33, VAR4, VAR49, VAR8, VAR45, VAR31, VAR2);
parameter VAR12 = 8; parameter VAR5 = VAR14(VAR12 - 1);
parameter VAR42 = 16;
input clk;
input rst;
input [31:0] VAR29;
input VAR51;
input [47:0] VAR3;
output VAR6;
output [47:0] VAR33;
input VAR4;
input [63:0] VAR49;
output VAR8;
output [63:0] VAR45;
input VAR31;
output VAR2;
reg [0:VAR12 - 1] VAR17;
reg [31 - VAR5:0] VAR36;
reg VAR24;
reg VAR13;
reg [31:0] VAR27, VAR39;
always @(posedge clk) begin
VAR24 <= VAR51;
VAR27 <= VAR29;
VAR13 <= VAR24;
VAR39 <= VAR27;
end
reg VAR21;
reg VAR40;
reg [31:0] VAR43;
always @(posedge clk) begin
if(VAR13)
VAR17[VAR39[VAR5-1:0]] <= 1;
VAR40 <= VAR17[VAR39[VAR5-1:0]];
if(VAR24)
VAR36 <= VAR27[31:VAR5];
if(VAR36 != VAR27[31:VAR5] && VAR24 || rst)
VAR17 <= 0;
VAR21 <= VAR13;
VAR43 <= VAR39;
end
reg [47:0] VAR50;
reg VAR47;
always @(posedge clk) begin
VAR47 <= VAR21 && !VAR40;
VAR50 <= VAR3 + VAR43 * 8;
end
assign VAR6 = VAR47;
assign VAR33 = VAR50;
reg VAR34;
wire [VAR5:0] VAR52;
wire VAR32;
wire VAR15;
VAR16 #(.VAR46(1 + VAR5), .VAR38(1024), .VAR9(0)) VAR41(rst, clk, VAR21, VAR34, {VAR43[VAR5 - 1:0], VAR40}, VAR52, VAR32, VAR15, , , );
reg VAR22;
wire [63:0] VAR37;
wire VAR28;
wire VAR54;
localparam VAR11=1024;
VAR16 #(.VAR46(64), .VAR38(VAR11), .VAR9(1)) VAR19(rst, clk, VAR4, VAR22, VAR49, VAR37, VAR28, VAR54, , , );
localparam VAR1=VAR14(VAR11-1);
reg [VAR1:0] VAR30;
VAR20 VAR30 = 0;
always @(posedge clk) begin
if(VAR22 && VAR47) begin
end else if(VAR22) begin
VAR30 <= VAR30 - 1;
end else if(VAR47) begin
VAR30 <= VAR30 + 1;
end
if(rst)
VAR30 <= 0;
end
assign VAR2 = VAR30 > VAR11 - VAR42;
reg [63:0] VAR26 [0:VAR12 - 1];
reg VAR35;
reg VAR7;
always @* begin
VAR35 = !VAR15 && VAR52[0] && !VAR31;
VAR7 = !VAR52[0] && !VAR54 && !VAR31;
VAR34 = VAR35 || VAR7;
VAR22 = VAR7;
end
reg [VAR5 - 1:0] VAR53;
reg VAR48;
reg VAR18;
always @(posedge clk) begin
VAR53 <= VAR52[VAR5:1];
VAR48 <= VAR35;
VAR18 <= VAR7;
end
reg [VAR5 - 1:0] VAR23;
reg [63:0] VAR10;
always @(posedge clk) begin
if(VAR18)
VAR26[VAR53] <= VAR37;
VAR10 <= VAR26[VAR23];
end
reg VAR44;
always @(posedge clk) begin
VAR44 <= VAR48 || VAR18;
VAR23 <= VAR53;
end
reg VAR25;
always @(posedge clk)
VAR25 <= VAR44;
assign VAR8 = VAR25;
assign VAR45 = VAR10;
endmodule
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/digital/azpr_soc/bus/rtl/bus_master_mux.v
| 2,878 |
module MODULE1 (
input wire [VAR9] VAR21, input wire VAR17, input wire VAR8, input wire [VAR2] VAR30, input wire VAR18, input wire [VAR9] VAR13, input wire VAR23, input wire VAR27, input wire [VAR2] VAR10, input wire VAR16, input wire [VAR9] VAR6, input wire VAR29, input wire VAR26, input wire [VAR2] VAR20, input wire VAR28, input wire [VAR9] VAR24, input wire VAR15, input wire VAR31, input wire [VAR2] VAR12, input wire VAR4,
output reg [VAR9] VAR7, output reg VAR1, output reg VAR5, output reg [VAR2] VAR11 );
always @(*) begin
if (VAR18 == VAR19) begin VAR7 = VAR21;
VAR1 = VAR17;
VAR5 = VAR8;
VAR11 = VAR30;
end else if (VAR16 == VAR19) begin VAR7 = VAR13;
VAR1 = VAR23;
VAR5 = VAR27;
VAR11 = VAR10;
end else if (VAR28 == VAR19) begin VAR7 = VAR6;
VAR1 = VAR29;
VAR5 = VAR26;
VAR11 = VAR20;
end else if (VAR4 == VAR19) begin VAR7 = VAR24;
VAR1 = VAR15;
VAR5 = VAR31;
VAR11 = VAR12;
end else begin VAR7 = VAR22'h0;
VAR1 = VAR25;
VAR5 = VAR14;
VAR11 = VAR3'h0;
end
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a2111oi/sky130_fd_sc_hs__a2111oi.behavioral.pp.v
| 1,983 |
module MODULE1 (
VAR14,
VAR4,
VAR1 ,
VAR3 ,
VAR5 ,
VAR16 ,
VAR9 ,
VAR13
);
input VAR14;
input VAR4;
output VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR16 ;
input VAR9 ;
input VAR13 ;
wire VAR9 VAR2 ;
wire VAR12 ;
wire VAR6;
and VAR7 (VAR2 , VAR3, VAR5 );
nor VAR15 (VAR12 , VAR16, VAR9, VAR13, VAR2 );
VAR8 VAR10 (VAR6, VAR12, VAR14, VAR4);
buf VAR11 (VAR1 , VAR6 );
endmodule
|
apache-2.0
|
thinkoco/de1_soc_opencl
|
de10_standard_sharedonly_vga/ip/TERASIC_AUDIO/AUDIO_ADC.v
| 3,989 |
module MODULE1(
clk,
reset,
read,
VAR10,
VAR8,
VAR17,
VAR11,
VAR21,
VAR25
);
parameter VAR19 = 32;
input clk;
input reset;
input read;
output [(VAR19-1):0] VAR10;
output VAR8;
input VAR17;
input VAR11;
input VAR21;
input VAR25;
reg [4:0] VAR7; reg VAR2;
reg VAR4;
reg [(VAR19-1):0] VAR14;
reg [(VAR19-1):0] VAR23;
reg VAR22;
wire VAR18;
reg VAR1;
wire VAR3;
assign VAR3 = ~VAR21;
always @ (posedge VAR11)
begin
if (reset || VAR17)
begin
VAR7 = VAR19;
VAR4 = VAR3;
VAR22 = 1'b0;
VAR2 = 0;
end
else
begin
if (VAR22)
VAR22 = 1'b0;
if (VAR4 ^ VAR3)
begin VAR4 = VAR3;
VAR2 = 1'b1;
VAR1 = 1'b1;
if (VAR4)
VAR7 = VAR19;
end
if (VAR2 && VAR1)
VAR1 = 1'b0;
end
else if (VAR2 && !VAR1)
begin
VAR7 = VAR7 - 1'b1;
VAR14[VAR7] = VAR25;
if ((VAR7 == 0) || (VAR7 == (VAR19/2)))
begin
if (VAR7 == 0 && !VAR18)
begin VAR23 = VAR14;
VAR22 = 1'b1; end
VAR2 = 0;
end
end
end
end
VAR20 VAR15(
.VAR9(VAR11),
.VAR26(VAR22),
.VAR6(VAR23),
.VAR24(VAR18),
.VAR13(VAR17), .VAR27(clk),
.VAR5(read),
.VAR12(VAR10),
.VAR16(VAR8)
);
endmodule
|
apache-2.0
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/tec-drums/i2s_out.v
| 1,786 |
module MODULE1(input VAR6, input reset, input[15:0] VAR3,
input[15:0] VAR5, output VAR4, output VAR2, output VAR7, output reg VAR8);
reg [3:0] VAR1;
begin
begin
begin
begin
end
begin
begin
begin
end
begin
|
mit
|
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM
|
mwram_gen.v
| 4,365 |
module MODULE1
localparam VAR8 = VAR3*VAR9/VAR2 ; localparam VAR1 = VAR4(VAR8) ; localparam VAR5 = VAR4(VAR3) ; localparam VAR10 = VAR4(VAR9/VAR2);
reg [VAR9-1:0] VAR6 [0:VAR3-1]; integer VAR7;
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a31oi/sky130_fd_sc_hd__a31oi_1.v
| 2,350 |
module MODULE1 (
VAR3 ,
VAR5 ,
VAR1 ,
VAR11 ,
VAR6 ,
VAR8,
VAR9,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR11 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR4 ;
input VAR7 ;
VAR10 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3 ,
VAR5,
VAR1,
VAR11,
VAR6
);
output VAR3 ;
input VAR5;
input VAR1;
input VAR11;
input VAR6;
supply1 VAR8;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR7 ;
VAR10 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dfbbn/sky130_fd_sc_hd__dfbbn_2.v
| 2,601 |
module MODULE2 (
VAR8 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR1 ,
VAR10,
VAR2 ,
VAR3 ,
VAR9 ,
VAR11
);
output VAR8 ;
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR10;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR11 ;
VAR7 VAR12 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR11(VAR11)
);
endmodule
module MODULE2 (
VAR8 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR1 ,
VAR10
);
output VAR8 ;
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR10;
supply1 VAR2;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR11 ;
VAR7 VAR12 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/dlrtp/sky130_fd_sc_hvl__dlrtp.pp.blackbox.v
| 1,403 |
module MODULE1 (
VAR3 ,
VAR7,
VAR1 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR7;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
endmodule
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature_KOA/FastMultiplier-master/BoothPPG_32R4.v
| 2,256 |
module MODULE1(VAR25 ,VAR44, VAR23,
VAR6, VAR34, VAR19, VAR24, VAR4,
VAR29, VAR41, VAR26, VAR2,
VAR16, VAR7, VAR1, VAR22,
VAR36, VAR28, VAR9, VAR40,
VAR38);
input wire[31:0] VAR25;
input wire[31:0] VAR44;
input wire VAR23;
output wire[15:0] VAR6;
output wire[33:0] VAR34;
output wire[33:0] VAR19;
output wire[33:0] VAR24;
output wire[33:0] VAR4;
output wire[33:0] VAR29;
output wire[33:0] VAR41;
output wire[33:0] VAR26;
output wire[33:0] VAR2;
output wire[33:0] VAR16;
output wire[33:0] VAR7;
output wire[33:0] VAR1;
output wire[33:0] VAR22;
output wire[33:0] VAR36;
output wire[33:0] VAR28;
output wire[33:0] VAR9;
output wire[33:0] VAR40;
output wire[31:0] VAR38;
assign VAR6[15:0] = {VAR44[31], VAR44[29], VAR44[27], VAR44[25], VAR44[23], VAR44[21], VAR44[19], VAR44[17], VAR44[15], VAR44[13], VAR44[11], VAR44[9], VAR44[7], VAR44[5], VAR44[3], VAR44[1]};
VAR43 VAR21( .VAR10(VAR25), .VAR15({VAR44[1:0],1'b0}), .VAR23(VAR23), .VAR5(VAR34));
VAR43 VAR14( .VAR10(VAR25), .VAR15(VAR44[3:1]), .VAR23(VAR23), .VAR5(VAR19));
VAR43 VAR20( .VAR10(VAR25), .VAR15(VAR44[5:3]), .VAR23(VAR23), .VAR5(VAR24));
VAR43 VAR17( .VAR10(VAR25), .VAR15(VAR44[7:5]), .VAR23(VAR23), .VAR5(VAR4));
VAR43 VAR12( .VAR10(VAR25), .VAR15(VAR44[9:7]), .VAR23(VAR23), .VAR5(VAR29));
VAR43 VAR27( .VAR10(VAR25), .VAR15(VAR44[11:9]), .VAR23(VAR23), .VAR5(VAR41));
VAR43 VAR11( .VAR10(VAR25), .VAR15(VAR44[13:11]), .VAR23(VAR23), .VAR5(VAR26));
VAR43 VAR18( .VAR10(VAR25), .VAR15(VAR44[15:13]), .VAR23(VAR23), .VAR5(VAR2));
VAR43 VAR3( .VAR10(VAR25), .VAR15(VAR44[17:15]), .VAR23(VAR23), .VAR5(VAR16));
VAR43 VAR8( .VAR10(VAR25), .VAR15(VAR44[19:17]), .VAR23(VAR23), .VAR5(VAR7));
VAR43 VAR42(.VAR10(VAR25), .VAR15(VAR44[21:19]), .VAR23(VAR23), .VAR5(VAR1));
VAR43 VAR32(.VAR10(VAR25), .VAR15(VAR44[23:21]), .VAR23(VAR23), .VAR5(VAR22));
VAR43 VAR13(.VAR10(VAR25), .VAR15(VAR44[25:23]), .VAR23(VAR23), .VAR5(VAR36));
VAR43 VAR39(.VAR10(VAR25), .VAR15(VAR44[27:25]), .VAR23(VAR23), .VAR5(VAR28));
VAR43 VAR33(.VAR10(VAR25), .VAR15(VAR44[29:27]), .VAR23(VAR23), .VAR5(VAR9));
VAR43 VAR31(.VAR10(VAR25), .VAR15(VAR44[31:29]), .VAR23(VAR23), .VAR5(VAR40));
VAR37 VAR35(.VAR10(VAR25), .VAR30(VAR44[31]), .VAR23(VAR23), .VAR5(VAR38));
endmodule
|
gpl-3.0
|
Jawanga/ece385lab9
|
lab9_soc/synthesis/submodules/lab9_soc_sysid_qsys_0.v
| 1,454 |
module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1428568153 : 0;
endmodule
|
apache-2.0
|
trun/fpgaboy
|
src/tv80/rtl/core/tv80s.v
| 5,324 |
module MODULE1 (
VAR23, VAR39, VAR9, VAR42, VAR15, VAR28, VAR18, VAR38, VAR16, do,
VAR27, VAR13, VAR19, VAR6, VAR25, VAR5, VAR26, VAR22, VAR29, VAR21,
VAR20, clk, VAR14, VAR1, VAR36, VAR4, VAR8
);
parameter VAR37 = 3; parameter VAR12 = 1; parameter VAR30 = 1;
input VAR20;
input clk;
input VAR14;
input VAR1;
input VAR36;
input VAR4;
output VAR23;
output VAR39;
output VAR9;
output VAR42;
output VAR15;
output VAR28;
output VAR18;
output VAR38;
output [15:0] VAR16;
input [7:0] VAR8;
output [7:0] do;
output [15:0] VAR27;
output [15:0] VAR13;
output [15:0] VAR19;
output [7:0] VAR25;
output [7:0] VAR6;
output [15:0] VAR5;
output [15:0] VAR26;
output VAR22;
output VAR29;
output VAR21;
reg VAR39;
reg VAR9;
reg VAR42;
reg VAR15;
wire VAR31;
wire VAR7;
wire VAR11;
wire write;
wire VAR10;
reg [7:0] VAR2;
wire [6:0] VAR32;
wire [6:0] VAR34;
assign VAR31 = 1;
VAR33 #(VAR37, VAR30) VAR35
(
.VAR31 (VAR31),
.VAR23 (VAR23),
.VAR10 (VAR10),
.VAR11 (VAR11),
.write (write),
.VAR28 (VAR28),
.VAR18 (VAR18),
.VAR14 (VAR14),
.VAR1 (VAR1),
.VAR36 (VAR36),
.VAR20 (VAR20),
.VAR4 (VAR4),
.VAR38 (VAR38),
.clk (clk),
.VAR17 (),
.VAR3 (),
.VAR16 (VAR16),
.VAR41 (VAR8),
.VAR8 (VAR2),
.do (do),
.VAR40 (VAR32),
.VAR24 (VAR34),
.VAR7 (VAR7),
.VAR27 (VAR27),
.VAR13 (VAR13),
.VAR19 (VAR19),
.VAR25 (VAR25),
.VAR6 (VAR6),
.VAR5 (VAR5),
.VAR26 (VAR26),
.VAR22(VAR22),
.VAR29(VAR29),
.VAR21(VAR21)
);
always @(posedge clk)
begin
if (!VAR20)
begin
VAR42 <= 1'b1;
VAR15 <= 1'b1;
VAR9 <= 1'b1;
VAR39 <= 1'b1;
VAR2 <= 0;
end
else
begin
VAR42 <= 1'b1;
VAR15 <= 1'b1;
VAR9 <= 1'b1;
VAR39 <= 1'b1;
if (VAR32[0])
begin
if (VAR34[1] || (VAR34[2] && VAR14 == 1'b0))
begin
VAR42 <= ~ VAR7;
VAR39 <= ~ VAR7;
VAR9 <= VAR7;
end
if (VAR34[3])
VAR39 <= 1'b0;
end else
begin
if ((VAR34[1] || (VAR34[2] && VAR14 == 1'b0)) && VAR11 == 1'b0 && write == 1'b0)
begin
VAR42 <= 1'b0;
VAR9 <= ~ VAR10;
VAR39 <= VAR10;
end
if (VAR12 == 0)
begin
if (VAR34[2] && write == 1'b1)
begin
VAR15 <= 1'b0;
VAR9 <= ~ VAR10;
VAR39 <= VAR10;
end
end
else
begin
if ((VAR34[1] || (VAR34[2] && VAR14 == 1'b0)) && write == 1'b1)
begin
VAR15 <= 1'b0;
VAR9 <= ~ VAR10;
VAR39 <= VAR10;
end
end
end
if (VAR34[2] && VAR14 == 1'b1)
VAR2 <= VAR8;
end end
endmodule
|
mit
|
Proxmark/proxmark3
|
fpga/hi_get_trace.v
| 3,245 |
module MODULE1(
VAR14,
VAR20, VAR13, VAR15,
VAR2, VAR7, VAR17
);
input VAR14;
input [7:0] VAR20;
input VAR13;
input [2:0] VAR15;
output VAR2, VAR7, VAR17;
reg [6:0] VAR10;
always @(negedge VAR14)
begin
VAR10 <= VAR10 + 1;
end
reg [2:0] VAR5;
always @(negedge VAR14)
begin
if (VAR5 == 3'd7)
VAR5 <= 3'd0;
end
else
VAR5 <= VAR5 + 1;
end
reg [11:0] addr;
reg [11:0] VAR3;
reg [2:0] VAR4;
reg VAR1;
reg VAR9;
always @(negedge VAR14)
begin
VAR4 <= VAR15;
if (VAR15 == VAR19)
begin
VAR1 <= 1'b0;
VAR9 <= 1'b0;
if (VAR4 != VAR19) addr <= VAR3;
if (VAR10 == 7'd0)
begin
if (addr == 12'd3071)
addr <= 12'd0;
end
else
addr <= addr + 1;
end
end
else if (VAR15 != VAR18)
begin
if (VAR13)
begin
if (addr[11] == 1'b0)
begin
VAR1 <= 1'b1;
VAR9 <= 1'b0;
end
else
begin
VAR1 <= 1'b0;
VAR9 <= 1'b1;
end
if (VAR5 == 3'b000)
begin
if (addr == 12'd3071)
begin
addr <= 12'd0;
VAR1 <= 1'b1;
VAR9 <= 1'b0;
end
else
addr <= addr + 1;
end
end
else
begin
VAR1 <= 1'b0;
VAR9 <= 1'b0;
VAR3 <= addr;
end
end
else begin
VAR1 <= 1'b0;
VAR9 <= 1'b0;
if (VAR4 != VAR18 && VAR4 != VAR19) VAR3 <= addr;
end
end
reg [7:0] VAR16, VAR6;
reg [7:0] VAR8 [2047:0];
reg [7:0] VAR12 [1023:0];
always @(negedge VAR14)
begin
if (VAR1)
begin
VAR8[addr[10:0]] <= VAR20;
VAR16 <= VAR20;
end
else
VAR16 <= VAR8[addr[10:0]];
if (VAR9)
begin
VAR12[addr[9:0]] <= VAR20;
VAR6 <= VAR20;
end
else
VAR6 <= VAR12[addr[9:0]];
end
reg VAR17;
reg VAR2;
reg [7:0] VAR11;
always @(negedge VAR14)
begin
if(VAR10[3:0] == 4'd0) begin
if(VAR10[6:4] == 3'd0) begin
if (addr[11] == 1'b0)
VAR11 <= VAR16;
end
else
VAR11 <= VAR6;
end
else VAR11[7:1] <= VAR11[6:0];
end
VAR17 <= ~VAR10[3];
if(VAR10[6:4] == 3'b000) VAR2 <= 1'b1;
else
VAR2 <= 1'b0;
end
assign VAR7 = VAR11[7];
endmodule
|
gpl-2.0
|
freecores/eco32
|
fpga/src/kbd/keyboard.v
| 3,114 |
module MODULE1(VAR13, VAR25,
clk, reset,
VAR14, VAR22);
input VAR13;
input VAR25;
input clk;
input reset;
output [7:0] VAR14;
output VAR22;
reg VAR23;
reg VAR16;
reg VAR15;
reg VAR20;
wire [3:0] VAR11;
reg [3:0] VAR3;
reg VAR5;
reg VAR12;
wire VAR1;
wire VAR24;
wire VAR9;
wire [9:0] VAR21;
reg [9:0] VAR4;
wire [12:0] VAR2;
reg [12:0] VAR19;
wire VAR18;
wire [3:0] VAR26;
reg [3:0] VAR6;
wire VAR17;
reg VAR7;
wire VAR10;
reg VAR8;
always @(posedge clk) begin
VAR23 <= VAR13;
VAR16 <= VAR23;
VAR15 <= VAR25;
VAR20 <= VAR15;
end
assign VAR11 =
(VAR3 == 4'b1111 && VAR16 == 1) ? 4'b1111 :
(VAR3 == 4'b0000 && VAR16 == 0) ? 4'b0000 :
(VAR16 == 1) ? VAR3 + 1 :
VAR3 - 1;
always @(posedge clk) begin
if (reset == 1) begin
VAR12 <= 1;
VAR5 <= 1;
end else begin
VAR12 <= VAR5;
if (VAR3 == 4'b0100) begin
VAR5 <= 0;
end
if (VAR3 == 4'b1011) begin
VAR5 <= 1;
end
end
end
assign VAR1 = VAR12 & ~VAR5;
assign VAR24 = ~VAR12 & VAR5;
assign VAR9 = VAR1 | VAR24;
assign VAR21 =
(VAR1 == 1) ? { VAR20, VAR4[9:1]} : VAR4;
assign VAR2 =
(VAR9 == 1) ? 13'b0000000000000 : VAR19 + 1;
assign VAR18 =
(VAR19 == 13'b1010000000000 && VAR5 == 1) ? 1 : 0;
assign VAR26 =
(VAR1 == 1) ? VAR6 + 1 :
(VAR18 == 1 || VAR8 == 1) ? 4'b0000:
VAR6;
assign VAR17 =
(VAR6 == 4'b1011 && VAR18 == 1) ? 1 : 0;
assign VAR10 =
((VAR19 == 13'b1010000000000 &&
VAR5 == 0) ||
(VAR18 == 1 &&
VAR6 != 4'b1011 &&
VAR6 != 4'b0000)) ? 1 : VAR8;
always @(posedge clk) begin
if (reset == 1 || VAR8 == 1) begin
VAR3 <= 4'b1111;
VAR4 <= 10'b0000000000;
VAR19 <= 13'b0000000000000;
VAR6 <= 4'b0000;
VAR7 <= 0;
VAR8 <= 0;
end else begin
VAR3 <= VAR11;
VAR4 <= VAR21;
VAR19 <= VAR2;
VAR6 <= VAR26;
VAR7 <= VAR17;
VAR8 <= VAR10;
end
end
assign VAR14 = VAR4[7:0];
assign VAR22 = VAR7;
endmodule
|
bsd-2-clause
|
shaform/ArkanoidOnVerilog
|
Arkanoid.v
| 3,519 |
module MODULE1(
input VAR65,
input VAR7, VAR80, VAR48, VAR27,
input [3:0] VAR92,
input VAR95, VAR104,
output VAR85, VAR112, VAR66, VAR121, VAR32,
output [7:0] VAR89
);
localparam VAR20 = 2;
localparam VAR86 = 2;
reg VAR39;
wire VAR87, VAR2;
wire [4:0] VAR4;
wire [9:0] VAR11, VAR107, VAR29, VAR113;
wire reset, VAR61, VAR62, VAR54;
wire VAR64, VAR42;
wire [5:0] VAR23, VAR21;
wire [1:0] VAR106;
wire [2:0] VAR5;
wire VAR31;
wire [VAR20*10-1:0] VAR102, VAR101;
wire [10:0] VAR35; wire [11:0] VAR73; wire [3:0] VAR109, VAR16, VAR105, VAR30, VAR74, VAR8, VAR90;
wire [4:0] VAR14, VAR108, VAR81, VAR49;
wire [1:0] VAR38, VAR46;
wire VAR118, VAR125;
wire VAR15, VAR116;
always @(posedge VAR65)
VAR39 = ~VAR39;
VAR47 VAR69(VAR65, reset, VAR80, VAR62);
VAR47 VAR94(VAR65, reset, VAR7, VAR54);
VAR47 VAR17(VAR65, reset, VAR27, VAR61);
VAR45 VAR99(.VAR28(VAR65), .VAR76(VAR95), .VAR93(VAR104),
.VAR64(VAR64), .VAR42(VAR42));
VAR82 VAR9(.VAR119(VAR65), .reset(reset), .enable(1'b1), .VAR64(VAR64),
.VAR42(VAR42), .VAR60(VAR4), .VAR50(VAR21), .VAR87(VAR87), .VAR59(VAR11), .VAR44(VAR107));
VAR12 VAR25(.VAR119(VAR65), .reset(reset), .VAR61(VAR61), .VAR54(VAR54), .VAR62(VAR62), .VAR92(VAR92),
.VAR118(VAR118), .VAR8(VAR8),
.VAR11(VAR11), .VAR107(VAR107), .VAR21(VAR21),
.VAR106(VAR106), .VAR23(VAR23), .VAR43(VAR102), .VAR36(VAR101),
.VAR125(VAR125), .VAR81(VAR81), .VAR49(VAR49), .VAR46(VAR46), .VAR38(VAR38),
.VAR29(VAR29), .VAR113(VAR113), .VAR5(VAR5), .VAR31(VAR31),
.VAR87(VAR87), .VAR4(VAR4), .VAR2(VAR2),
.VAR10(VAR89[7:2]), .VAR114(VAR116), .VAR67(VAR15), .VAR22(VAR111));
VAR40 VAR100(.VAR119(VAR65), .reset(reset), .enable(VAR125),
.VAR96(VAR81), .VAR63(VAR14), .VAR24(VAR49), .VAR19(VAR108),
.VAR51(VAR46), .VAR103(VAR38), .VAR117(VAR8), .VAR97(VAR74), .ready(VAR118));
VAR70 VAR120(.VAR119(VAR39), .reset(reset), .VAR53(VAR53),
.VAR114(VAR116), .VAR67(VAR15), .VAR22(VAR111),
.VAR3(VAR30), .VAR83(VAR90), .VAR18(VAR105), .VAR55(VAR16), .VAR6(VAR109), .VAR122({VAR85, VAR112, VAR66}));
VAR75 VAR52(.out(VAR109), .VAR35(VAR35), .VAR73(VAR73),
.VAR114(VAR116), .VAR67(VAR15), .VAR22(VAR111));
VAR34 VAR33(.VAR119(VAR39), .VAR35(VAR35), .VAR73(VAR73), .VAR91(VAR74),
.VAR84(VAR14), .VAR72(VAR108), .out(VAR105));
VAR88 VAR77(.out(VAR30), .VAR35(VAR35), .VAR73(VAR73), .VAR53(VAR2),
.VAR37(VAR102), .VAR79(VAR101), .VAR1(VAR106), .VAR50(VAR23));
VAR88 VAR26(.out(VAR56), .VAR35(VAR35), .VAR73(VAR73),
.VAR37(VAR57), .VAR79(VAR110), .VAR1(VAR68), .VAR50(4));
VAR13 VAR123(.VAR35(VAR35), .VAR73(VAR73),
.VAR115(VAR11), .VAR71(VAR107), .VAR50(VAR21), .out(VAR16));
VAR98 VAR58(.VAR35(VAR35), .VAR73(VAR73),
.VAR115(VAR29), .VAR71(VAR113), .VAR124(VAR5), .VAR1(VAR31), .out(VAR90));
VAR78 VAR41(.VAR28(VAR39), .reset(reset), .VAR35(VAR35), .VAR73(VAR73),
.VAR53(VAR53), .VAR121(VAR121), .VAR32(VAR32));
assign reset = VAR48;
assign VAR89[1:0] = VAR111 ? 2'b11 : (VAR116 ? 2'b01 : 2'b00);
endmodule
|
gpl-3.0
|
GSejas/Aproximate-Arithmetic-Operators
|
src_lib/multlib/KOA_1c_approx.v
| 6,381 |
module MODULE1
(
input wire clk,
input wire rst,
input wire VAR17,
input wire [VAR27-1:0] VAR31,
input wire [VAR27-1:0] VAR40,
output wire [2*VAR27-1:0] VAR4
);
wire [1:0] VAR3;
wire [3:0] VAR36;
assign VAR3 = 2'b00;
assign VAR36 = 4'b0000;
wire [VAR27/2-1:0] VAR28;
wire [VAR27/2:0] VAR21;
wire [VAR27/2-3:0] VAR25;
wire [VAR27/2-4:0] VAR41;
reg [4*(VAR27/2)+2:0] VAR29;
reg [4*(VAR27/2)-1:0] VAR8;
assign VAR28 = {(VAR27/2){1'b0}};
assign VAR21 = {(VAR27/2+1){1'b0}};
assign VAR25 = {(VAR27/2-4){1'b0}}; assign VAR41 = {(VAR27/2-5){1'b0}};
localparam VAR9 = VAR27/2;
generate
case (VAR27%2)
0:begin : VAR1
wire [VAR27/2:0] VAR35;
wire [VAR27/2:0] VAR18;
wire [VAR27-1:0] VAR13;
wire [VAR27-1:0] VAR26;
wire [VAR27+1:0] VAR20;
reg [2*(VAR27/2+2)-1:0] VAR43;
reg [VAR27+1:0] VAR19;
VAR33 #(.VAR27(VAR27/2)) VAR32(
.VAR31(VAR31[VAR27-1:VAR27-VAR27/2]),
.VAR40(VAR40[VAR27-1:VAR27-VAR27/2]),
.VAR37(VAR13)
);
VAR33 #(.VAR27(VAR27/2)) VAR12(
.VAR31(VAR31[VAR27-VAR27/2-1:0]),
.VAR40(VAR40[VAR27-VAR27/2-1:0]),
.VAR37(VAR26)
);
VAR33 #(.VAR27((VAR27/2)+1)) VAR6 (
.VAR31(VAR35),
.VAR40(VAR18),
.VAR37(VAR20)
);
VAR11 #(.VAR23(VAR27/2))
VAR39 (
.VAR30 (1'b0),
.VAR34 (VAR31[((VAR27/2)-1):0] ),
.VAR16 (VAR31[(VAR27-1) -: VAR27/2]),
.VAR2 (VAR35));
VAR11 #(.VAR23(VAR27/2))
VAR38(
.VAR30 (1'b0),
.VAR34 (VAR40[((VAR27/2)-1):0]),
.VAR16 (VAR40[(VAR27-1) -: VAR27/2]),
.VAR2 (VAR18));
always @* begin : VAR7
VAR19 <= (VAR20 - VAR13 - VAR26);
VAR29[4*(VAR27/2):0] <= {VAR25,VAR19,VAR28} + {VAR13,VAR26};
end
VAR22 #(.VAR23(4*(VAR27/2))) VAR15 ( .clk(clk),
.rst(rst),
.VAR5(VAR17),
.VAR42(VAR29[4*(VAR27/2)-1:0]),
.VAR10({VAR4})
);
end
1:begin : VAR14
wire [VAR27/2+1:0] VAR35;
wire [VAR27/2+1:0] VAR18;
wire [2*(VAR27/2)-1:0] VAR13;
wire [2*(VAR27/2+1)-1:0] VAR26;
wire [2*(VAR27/2+2)-1:0] VAR20;
reg [2*(VAR27/2+2)-1:0] VAR43;
reg [VAR27+4-1:0] VAR19;
VAR33 #(.VAR27(VAR27/2)) VAR32(
.VAR31(VAR31[VAR27-1:VAR27-VAR27/2]),
.VAR40(VAR40[VAR27-1:VAR27-VAR27/2]),
.VAR37(VAR13)
);
VAR33 #(.VAR27(VAR27/2+1)) VAR12(
.VAR31(VAR31[VAR27-VAR27/2-1:0]),
.VAR40(VAR40[VAR27-VAR27/2-1:0]),
.VAR37(VAR26)
);
VAR33 #(.VAR27(VAR27/2+2)) VAR6 (
.VAR31(VAR35),
.VAR40(VAR18),
.VAR37(VAR20)
);
VAR11 #(.VAR23(VAR27/2+1))
VAR39(
.VAR30 (1'b0),
.VAR34 (VAR31[((VAR27/2)-1):0] ),
.VAR16 (VAR31[(VAR27-1) -: VAR27/2]),
.VAR2 (VAR35));
VAR11 #(.VAR23(VAR27/2+1))
VAR38(
.VAR30 (1'b0),
.VAR34 (VAR40[((VAR27/2)-1):0]),
.VAR16 (VAR40[(VAR27-1) -: VAR27/2]),
.VAR2 (VAR18));
always @* begin : VAR24
VAR19 <= (VAR20 - VAR13 - VAR26);
VAR29[4*(VAR27/2)+2:0]<= {VAR41,VAR19,VAR21} + {VAR13,VAR26};
end
VAR22 #(.VAR23(4*(VAR27/2)+2)) VAR15 ( .clk(clk),
.rst(rst),
.VAR5(VAR17),
.VAR42(VAR29[2*VAR27-1:0]),
.VAR10({VAR4})
);
end
endcase
endgenerate
endmodule
|
apache-2.0
|
johan92/altera_opencl_sandbox
|
vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_hps_hps_io.v
| 6,754 |
module MODULE1 (
output wire [14:0] VAR7, output wire [2:0] VAR33, output wire VAR4, output wire VAR10, output wire VAR40, output wire VAR26, output wire VAR25, output wire VAR13, output wire VAR16, output wire VAR31, inout wire [31:0] VAR22, inout wire [3:0] VAR42, inout wire [3:0] VAR9, output wire VAR14, output wire [3:0] VAR27, input wire VAR17, output wire VAR36, output wire VAR23, output wire VAR11, output wire VAR32, output wire VAR2, input wire VAR38, inout wire VAR12, output wire VAR6, input wire VAR19, output wire VAR29, input wire VAR41, input wire VAR35, input wire VAR24, input wire VAR15, inout wire VAR18, inout wire VAR39, inout wire VAR28, output wire VAR5, inout wire VAR20, inout wire VAR3, input wire VAR34, output wire VAR21, inout wire VAR37, inout wire VAR43, inout wire VAR1 );
VAR30 VAR8 (
.VAR7 (VAR7), .VAR33 (VAR33), .VAR4 (VAR4), .VAR10 (VAR10), .VAR40 (VAR40), .VAR26 (VAR26), .VAR25 (VAR25), .VAR13 (VAR13), .VAR16 (VAR16), .VAR31 (VAR31), .VAR22 (VAR22), .VAR42 (VAR42), .VAR9 (VAR9), .VAR14 (VAR14), .VAR27 (VAR27), .VAR17 (VAR17), .VAR36 (VAR36), .VAR23 (VAR23), .VAR11 (VAR11), .VAR32 (VAR32), .VAR2 (VAR2), .VAR38 (VAR38), .VAR12 (VAR12), .VAR6 (VAR6), .VAR19 (VAR19), .VAR29 (VAR29), .VAR41 (VAR41), .VAR35 (VAR35), .VAR24 (VAR24), .VAR15 (VAR15), .VAR18 (VAR18), .VAR39 (VAR39), .VAR28 (VAR28), .VAR5 (VAR5), .VAR20 (VAR20), .VAR3 (VAR3), .VAR34 (VAR34), .VAR21 (VAR21), .VAR37 (VAR37), .VAR43 (VAR43), .VAR1 (VAR1) );
endmodule
|
mit
|
carstenbru/fpga-log
|
spartanmc/hardware/contrast_box/src/contrast_box_in_out.v
| 6,177 |
module MODULE1 #(parameter VAR16 = 16000000,
parameter VAR37 = 1000,
parameter VAR13 = 3, parameter VAR22 = 11,
parameter VAR9 = 100, parameter VAR6 = 11,
parameter VAR4 = 5, parameter VAR42 = 11,
parameter VAR35 = 10,
parameter VAR28 = 1023, parameter VAR32 = 17) (
input wire clk, input wire reset, input wire VAR30, input wire VAR24,
output reg VAR33, output wire VAR3,
output wire [VAR35-1:0] VAR17
);
parameter VAR40 = (VAR16/VAR37)/(VAR28+1);
parameter VAR7 = VAR16*VAR4/100;
parameter VAR25 = VAR16*VAR9/100;
parameter VAR20 = VAR28 - VAR6 + 1;
parameter VAR23 = VAR28 - VAR22 + 1;
parameter VAR12 = 25;
reg [VAR35-1:0] VAR43;
reg [VAR35-1:0] VAR29;
wire VAR39;
wire VAR11;
wire VAR45;
wire VAR8;
reg [VAR35-1:0] VAR44; reg [VAR12-1:0] VAR34;
reg [VAR12-1:0] VAR1;
reg VAR18;
reg VAR21;
VAR2 #(.VAR41(VAR32)) VAR5 (
.clk(clk),
.VAR14(VAR24),
.VAR31(VAR11),
.VAR15(),
.VAR10(VAR39));
VAR2 #(.VAR41(VAR32)) VAR38 (
.clk(clk),
.VAR14(VAR30),
.VAR31(VAR45),
.VAR15(),
.VAR10());
VAR36 #(.VAR26(VAR35), .VAR46(VAR35), .VAR13(VAR13)) VAR19 (
.addr(VAR43),
.VAR27(VAR17));
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR34 <= {(VAR12){1'b0}};
VAR18 <= 1'b0;
VAR1 <= {(VAR12){1'b0}};
VAR21 <= 1'b0;
end else begin
if((VAR11 ^ VAR45)) begin
if(VAR34 < VAR7) VAR34 <= VAR34 + 1;
end
else VAR34 <= {(VAR12){1'b0}};
if(VAR34 == VAR7) VAR18 <= 1'b1;
end
else VAR18 <= 1'b0;
end else begin
VAR34 <= {(VAR12){1'b0}};
VAR18 <= 1'b0;
end
if(VAR9 > 0) begin
if(VAR1 < VAR25) VAR1 <= VAR1 + 1;
end
else VAR1 <= {(VAR12){1'b0}};
if(VAR1 == VAR25) VAR21 <= 1'b1;
end
else VAR21 <= 1'b0;
end else begin
VAR1 <= {(VAR12){1'b0}};
VAR21 <= 1'b0;
end
end
end
always @(posedge clk) begin
if(VAR11 ^ VAR45) begin
if(VAR11) begin
if(VAR18 && (VAR43 > (VAR42-1))) begin
VAR43 <= VAR43 - VAR42;
VAR33 <= 1'b1;
end else VAR33 <= 1'b0;
end else begin
if(VAR18 && (VAR43 < VAR20)) begin
VAR43 <= VAR43 + VAR6;
VAR33 <= 1'b1;
end else VAR33 <= 1'b0;
end
end else begin
if(VAR21 && (VAR43 < VAR23)) begin
VAR43 <= VAR43 + VAR22;
VAR33 <= 1'b1;
end else VAR33 <= 1'b0;
end
end
assign VAR8 = VAR44 < (VAR40>>2);
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR44 <= {(VAR35){1'b0}}; end else begin
if(VAR44 < VAR40) VAR44 <= VAR44 + 1;
end
else VAR44 <= {(VAR35){1'b0}};
end
end
assign VAR3 = (VAR29 < VAR17);
always @(posedge VAR8 or posedge reset) begin
if(reset) begin
VAR29 <= {(VAR35){1'b0}}; end else begin
if (VAR29 == VAR28) begin
VAR29 <= {(VAR35){1'b0}}; end else begin
VAR29 <= VAR29 + 1;
end
end
end
endmodule
|
gpl-3.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/sparc/ffu/rtl/sparc_ffu.v
| 30,781 |
module MODULE1 (
VAR76, VAR127, VAR150, VAR121,
VAR13, VAR73, VAR86,
VAR2, VAR8, VAR91,
VAR55, VAR65, VAR30,
VAR113, VAR43, VAR162,
VAR66, VAR87, VAR167,
VAR101, VAR112, VAR108, VAR72,
VAR67, VAR145,
VAR141, VAR63, VAR110, VAR129, VAR17, VAR71,
VAR143, VAR128, VAR11,
VAR111, VAR78, VAR52,
VAR45, VAR105, VAR166,
VAR164, VAR119, VAR49,
VAR29, VAR95, VAR98,
VAR38, VAR32, VAR20,
VAR135, VAR130, VAR16,
VAR148, VAR165, VAR142, VAR33,
VAR152, VAR70, VAR138,
VAR159, VAR161, VAR154,
VAR160, VAR9, VAR27, VAR93,
VAR83, VAR75, VAR117,
VAR99, VAR102, VAR31,
VAR97, VAR51, VAR92, VAR19, VAR168, VAR3,
VAR84, VAR34, VAR69, VAR6,
VAR80
) ;
output [80:0] VAR72; output VAR67;
input VAR34;
input VAR69;
input VAR6;
input VAR84; input [1:0] VAR3; input VAR168; input [4:0] VAR19; input [63:0] VAR92; input [3:0] VAR51; input VAR97; input [2:0] VAR31; input [31:0] VAR102; input [2:0] VAR99; input [4:0] VAR117; input VAR75; input VAR83; input VAR93; input VAR27; input [6:0] VAR9; input VAR160; input [1:0] VAR154; input VAR161; input VAR159; input VAR138; input [8:0] VAR70; input [4:0] VAR152; input [4:0] VAR33; input [4:0] VAR142; input VAR165; input VAR148; input VAR16; input VAR130; input VAR135; input VAR20; input VAR32; input VAR38; input [1:0] VAR98; input VAR95; input VAR29; input VAR49; input VAR119; input VAR164; input [6:0] VAR166; input VAR105; input [2:0] VAR45; input VAR52; input VAR78; input [63:0] VAR111; input VAR11; input VAR128; input VAR143; input VAR71; input VAR17; input VAR80; input VAR129; input VAR110; input VAR63; input VAR141;
output [3:0] VAR108; output [7:0] VAR112; output VAR101; output VAR167; output [5:0] VAR87; output [13:0] VAR66; output VAR162; output VAR43; output VAR113; output VAR30; output [1:0] VAR65; output VAR55; output [5:3] VAR91; output VAR8; output VAR2; output VAR86; output [1:0] VAR73; output VAR13; output VAR121; output VAR150; output VAR127; output VAR76;
wire VAR124; wire [9:0] VAR103; wire [7:0] VAR82; wire VAR96; wire VAR42; wire [3:0] VAR146; wire [3:0] VAR107; wire [3:0] VAR21; wire [3:0] VAR60; wire [2:0] VAR48; wire [3:0] VAR132; wire VAR149; wire VAR153; wire VAR1; wire VAR79; wire VAR88; wire VAR109; wire VAR64; wire VAR4; wire VAR39; wire VAR61; wire VAR140; wire VAR77; wire VAR115; wire VAR59; wire VAR44; wire VAR41; wire [1:0] VAR147; wire [3:0] VAR53; wire [36:0] VAR144; wire VAR74; wire [6:0] VAR139; wire VAR58; wire [1:0] VAR134; wire VAR122; wire VAR10; wire VAR100; wire VAR114; wire VAR133; wire VAR120; wire VAR5; wire VAR62; wire VAR54; wire VAR47; wire VAR22; wire VAR37; wire VAR50; wire VAR18; wire VAR68; wire VAR24; wire VAR156; wire VAR90; wire VAR116; wire VAR123; wire VAR106; wire [4:0] VAR118; wire [4:0] VAR15; wire [7:0] VAR14; wire [1:0] VAR157; wire [4:0] VAR26; wire [31:0] VAR81; wire [4:0] VAR125; wire [7:0] VAR151; wire [1:0] VAR7; wire [6:0] VAR35; wire [6:0] VAR36; wire [63:0] VAR158; wire [63:0] VAR23; wire [77:0] VAR85; wire [63:0] VAR28; wire [77:0] VAR89;
output [63:0] VAR145;
wire [31:0] VAR155;
wire [2:0] VAR94;
wire [7:0] VAR12;
wire VAR46;
assign VAR145[63:0] = {VAR155[31:0], 4'b0,
VAR94[2:0], 17'b0,
VAR12[7:0]};
VAR136 VAR131(
.VAR141(VAR6),
.VAR76(VAR46),
.VAR89 (VAR89[77:0]),
.VAR126 (VAR69),
.VAR85 (VAR85[77:0]),
.VAR129 (VAR129),
.VAR110 (VAR110),
.VAR63 (VAR63),
.VAR134 (VAR134[1:0]),
.VAR58 (VAR58),
.VAR139 (VAR139[6:0]));
VAR57 VAR163(
.VAR89 ({VAR89[70:39],VAR89[31:0]}),
.VAR76 (VAR76),
.VAR72 (VAR72[63:0]),
.VAR158 (VAR158[63:0]),
.VAR23 (VAR23[63:0]),
.VAR7 (VAR7[1:0]),
.VAR14 (VAR14[7:0]),
.VAR157 (VAR157[1:0]),
.VAR26 (VAR26[4:0]),
.VAR118 (VAR118[4:0]),
.VAR15 (VAR15[4:0]),
.VAR151 (VAR151[7:0]),
.VAR81 (VAR81[31:0]),
.VAR125 (VAR125[4:0]),
.VAR36 (VAR36[6:0]),
.VAR35(VAR35[6:0]),
.VAR129 (VAR129),
.VAR110 (VAR110),
.VAR141 (VAR141),
.VAR59 (VAR59),
.VAR85 (VAR85[77:0]),
.VAR92 (VAR92[63:0]),
.VAR111 (VAR111[63:0]),
.VAR28 (VAR28[63:0]),
.VAR144 (VAR144[36:0]),
.VAR147 (VAR147[1:0]),
.VAR103 (VAR103[9:0]),
.VAR82 (VAR82[7:0]),
.VAR48 (VAR48[2:0]),
.VAR79(VAR79),
.VAR41(VAR41),
.VAR44(VAR44),
.VAR74(VAR74),
.VAR64(VAR64),
.VAR4(VAR4),
.VAR88(VAR88),
.VAR109(VAR109),
.VAR1 (VAR1),
.VAR42 (VAR42),
.VAR153 (VAR153),
.VAR96 (VAR96),
.VAR61 (VAR61),
.VAR115 (VAR115),
.VAR77(VAR77),
.VAR140(VAR140),
.VAR39 (VAR39),
.VAR146 (VAR146[3:0]),
.VAR60 (VAR60[3:0]),
.VAR21 (VAR21[3:0]),
.VAR107 (VAR107[3:0]),
.VAR132 (VAR132[3:0]),
.VAR53 (VAR53[3:0]),
.VAR149 (VAR149),
.VAR124 (VAR124));
VAR40 VAR25(
.VAR141(VAR46),
.VAR76 (VAR67),
.VAR155(VAR155[31:0]),
.VAR12(VAR12[7:0]),
.VAR94(VAR94[2:0]),
.VAR104({VAR89[77:71],VAR89[38:32]}),
.VAR126 (VAR34),
.VAR132 (VAR132[3:0]),
.VAR53 (VAR53[3:0]),
.VAR144(VAR144[36:0]),
.VAR122 (VAR122),
.VAR10 (VAR10),
.VAR100 (VAR100),
.VAR114 (VAR114),
.VAR133 (VAR133),
.VAR120 (VAR120),
.VAR5 (VAR5),
.VAR62(VAR62),
.VAR54(VAR54),
.VAR47(VAR47),
.VAR22(VAR22),
.VAR37(VAR37),
.VAR50(VAR50),
.VAR18(VAR18),
.VAR68(VAR68),
.VAR24(VAR24),
.VAR156(VAR156),
.VAR90 (VAR90),
.VAR116 (VAR116),
.VAR123 (VAR123),
.VAR106 (VAR106),
.VAR59 (VAR59),
.VAR162(VAR162),
.VAR108 (VAR108[3:0]),
.VAR112 (VAR112[7:0]),
.VAR65 (VAR65[1:0]),
.VAR30 (VAR30),
.VAR101 (VAR101),
.VAR167 (VAR167),
.VAR87(VAR87[5:0]),
.VAR66(VAR66[13:0]),
.VAR43 (VAR43),
.VAR2(VAR2),
.VAR113 (VAR113),
.VAR72 (VAR72[80:64]),
.VAR8(VAR8),
.VAR91(VAR91[5:3]),
.VAR55 (VAR55),
.VAR121(VAR121),
.VAR150(VAR150),
.VAR127 (VAR127),
.VAR13(VAR13),
.VAR73 (VAR73[1:0]),
.VAR86 (VAR86),
.VAR58 (VAR58),
.VAR134 (VAR134[1:0]),
.VAR139 (VAR139[6:0]),
.VAR146 (VAR146[3:0]),
.VAR82 (VAR82[7:0]),
.VAR48 (VAR48[2:0]),
.VAR103 (VAR103[9:0]),
.VAR124(VAR124),
.VAR64(VAR64),
.VAR4(VAR4),
.VAR88(VAR88),
.VAR109(VAR109),
.VAR61(VAR61),
.VAR115(VAR115),
.VAR77(VAR77),
.VAR140(VAR140),
.VAR39 (VAR39),
.VAR21 (VAR21[3:0]),
.VAR107(VAR107[3:0]),
.VAR60(VAR60[3:0]),
.VAR79(VAR79),
.VAR41(VAR41),
.VAR44(VAR44),
.VAR74(VAR74),
.VAR149 (VAR149),
.VAR147 (VAR147[1:0]),
.VAR96 (VAR96),
.VAR42 (VAR42),
.VAR153 (VAR153),
.VAR1 (VAR1),
.VAR81 (VAR81[31:0]),
.VAR125(VAR125[4:0]),
.VAR31(VAR31[2:0]),
.VAR102(VAR102[31:0]),
.VAR99 (VAR99[2:0]),
.VAR117(VAR117[4:0]),
.VAR83(VAR83),
.VAR166 (VAR166[6:0]),
.VAR80 (VAR80), .VAR129 (VAR129),
.VAR110 (VAR110),
.VAR93 (VAR93),
.VAR84 (VAR84),
.VAR7 (VAR7[1:0]),
.VAR97 (VAR97),
.VAR168 (VAR168),
.VAR51 (VAR51[3:0]),
.VAR3 (VAR3[1:0]),
.VAR19 (VAR19[4:0]),
.VAR14 (VAR14[7:0]),
.VAR157 (VAR157[1:0]),
.VAR26 (VAR26[4:0]),
.VAR118 (VAR118[4:0]),
.VAR15 (VAR15[4:0]),
.VAR36(VAR36[6:0]),
.VAR35(VAR35[6:0]),
.VAR159 (VAR159),
.VAR138 (VAR138),
.VAR95 (VAR95),
.VAR70(VAR70[8:0]),
.VAR33 (VAR33[4:0]),
.VAR142 (VAR142[4:0]),
.VAR152 (VAR152[4:0]),
.VAR161 (VAR161),
.VAR165 (VAR165),
.VAR130(VAR130),
.VAR98 (VAR98[1:0]),
.VAR154 (VAR154[1:0]),
.VAR20 (VAR20),
.VAR148(VAR148),
.VAR9 (VAR9[6:0]),
.VAR16 (VAR16),
.VAR135 (VAR135),
.VAR38 (VAR38),
.VAR32 (VAR32),
.VAR164(VAR164),
.VAR78(VAR78),
.VAR119 (VAR119),
.VAR105 (VAR105),
.VAR11 (VAR11),
.VAR45 (VAR45[2:0]),
.VAR151 (VAR151[7:0]),
.VAR160 (VAR160),
.VAR27(VAR27),
.VAR52 (VAR52),
.VAR75 (VAR75),
.VAR49(VAR49),
.VAR29 (VAR29),
.VAR128 (VAR128),
.VAR143 (VAR143),
.VAR71 (VAR71),
.VAR17 (VAR17));
VAR137 VAR56(
.VAR28 (VAR28[63:0]),
.VAR158 (VAR158[63:0]),
.VAR23 (VAR23[63:0]),
.VAR90 (VAR90),
.VAR123 (VAR123),
.VAR116 (VAR116),
.VAR122 (VAR122),
.VAR106 (VAR106),
.VAR5 (VAR5),
.VAR10 (VAR10),
.VAR100 (VAR100),
.VAR114 (VAR114),
.VAR133 (VAR133),
.VAR120 (VAR120),
.VAR24(VAR24),
.VAR18(VAR18),
.VAR68(VAR68),
.VAR156(VAR156),
.VAR54(VAR54),
.VAR47(VAR47),
.VAR62(VAR62),
.VAR22(VAR22),
.VAR37(VAR37),
.VAR50(VAR50));
endmodule
|
gpl-2.0
|
hakehuang/pycpld
|
ips/ip/i2c_master_two_ad/I2C_wr.v
| 10,793 |
module MODULE1(
VAR54,VAR52,ack,VAR9,clk,VAR35,VAR47,VAR41,VAR18
);
input VAR9,VAR35,VAR47,clk;
input VAR18;
output VAR52,ack;
inout [7:0] VAR41;
inout VAR54;
reg VAR22,VAR30;
reg[7:0] VAR20;
reg VAR52,ack,VAR53,VAR5,VAR2;
reg VAR6;
reg VAR12;
reg[8:0] VAR51;
reg[9:0] VAR43;
reg VAR27;
reg[6:0] VAR38;
reg[7:0] VAR17;
reg[7:0] VAR45;
reg[7:0] VAR33;
assign VAR54 = (VAR22) ? VAR20[7] : 1'VAR7;
assign VAR41 = (VAR30) ? VAR17 : 8'VAR49;
parameter VAR28 = 10'd32,
VAR13 = 10'd32;
parameter
VAR29 = 10'b0000001,
ready = 10'b0000010,
VAR34 = 11'b0000100,
VAR19 = 11'b0001000,
VAR31 = 11'b0010000,
VAR36 = 11'b0100000,
VAR42 = 11'b1000000;
parameter
VAR10 = 9'b000000001,
VAR39 = 9'b000000010,
VAR23 = 9'b000000100,
VAR55 = 9'b000001000,
VAR44 = 9'b000010000,
VAR48 = 9'b000100000,
VAR21 = 9'b001000000,
VAR50 = 9'b010000000,
VAR15 = 9'b100000000;
parameter
VAR3 = 10'b0000000001,
VAR1 = 10'b0000000010,
VAR32 = 10'b0000000100,
VAR26 = 10'b0000001000,
VAR40 = 10'b0000010000,
VAR37 = 10'b0000100000,
VAR25 = 10'b0001000000,
VAR24 = 10'b0010000000,
VAR11 = 10'b0100000000,
VAR4 = 10'b1000000000;
always @(negedge clk or negedge VAR9) begin
if(!VAR9)
VAR52 <= 1'b0;
end
else
VAR52 <= ~VAR52;
end
always @(posedge clk or negedge VAR9) begin
if(!VAR9)begin
VAR22 <= 1'b0;
ack <= 1'b0;
VAR5 <= 1'b0;
VAR53 <= 1'b0;
VAR2 <= 1'b0;
VAR38 <= VAR29;
VAR12 <= 'h0;
VAR51<= VAR10;
VAR43 <= VAR3;
VAR27 <= 'h0;
VAR45 <= 'h1;
VAR33 <= 'h1;
end
else begin
case(VAR38)
VAR29:begin
VAR30 <= 'h0;
VAR22 <= 'h0;
if(VAR35) begin
VAR53 <= 1'b1;
VAR38 <= ready;
end
else if(VAR47)begin
VAR5 <= 1'b1;
VAR38 <= ready;
end
else begin
VAR53 <= 1'b0;
VAR5 <= 1'b0;
VAR38 <=VAR29;
end
end
ready:begin
VAR2 <= 1'b0;
VAR38 <= VAR34;
end
VAR34:begin
if(VAR2==1'b0)
VAR16;
end
else begin
if(VAR53 == 1'b1)
VAR20 <= VAR18 ? {1'b0,1'b1,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0}:{1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0};
end
else
VAR20 <= VAR18 ? {1'b0,1'b1,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}:{1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b1};
VAR2 <= 1'b0;
VAR51 <= VAR39;
VAR38 <= VAR19;
end
end
VAR19:begin
if(VAR2==1'b0)
VAR14;
end
else begin
if(VAR5==1'b1)begin
VAR20 <= 'h0;
VAR22 <= 1'b0;
VAR2 <= 1'b0;
VAR45 <= 1'b1;
VAR38 <= VAR31;
end
else if(VAR53==1'b1)begin
VAR2 <= 1'b0;
VAR38 <= VAR31;
VAR20 <= VAR41;
VAR33 <= 1'b1;
end
end
end
VAR31:begin
if(VAR5==1'b1)begin
if(VAR45 <= VAR13)
VAR8;
end
else begin
VAR38 <= VAR36;
VAR2 <= 1'b0;
end
end
else if(VAR53==1'b1)begin
if(VAR33 <= VAR28)
case(VAR6)
1'b0:begin
if(!VAR52)begin
VAR20 <= VAR41;
VAR22 <= 1'b1;
VAR51<=VAR39;
VAR6 <= 1'b1;
ack <= 1'b0;
end
else
VAR6 <= 1'b0;
end
1'b1:VAR14;
endcase
end
else begin
VAR38 <= VAR36;
VAR6 <= 1'b0;
VAR2 <= 1'b0;
end
end
end
VAR36:begin
if(VAR2 == 1'b0)
VAR46;
end
else begin
ack <= 1'b1;
VAR2 <= 1'b0;
VAR38 <= VAR42;
end
end
VAR42:begin
ack <= 1'b0;
VAR53 <= 1'b0;
VAR5 <= 1'b0;
VAR38 <= VAR29;
end
default:VAR38 <= VAR29;
endcase
end
end
task VAR16;
begin
case(VAR12)
1'b0:begin
if(!VAR52)begin
VAR22 <= 1'b1;
VAR20[7] <= 1'b1;
VAR12 <= 1'b1;
end
else
VAR12 <= 1'b0;
end
1'b1:begin
if(VAR52)begin
VAR2 <= 1'b1;
VAR20[7] <= 1'b0;
VAR12 <= 1'b0;
end
else
VAR12<= 1'b1;
end
endcase
end
endtask
task VAR14;
begin
case(VAR51)
VAR10:begin
if(!VAR52) begin
VAR22 <= 1'b1;
VAR51 <= VAR39;
end
else
VAR51 <= VAR10;
end
VAR39:begin
if(!VAR52) begin
VAR51 <= VAR23;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR39;
end
VAR23:begin
if(!VAR52) begin
VAR51 <= VAR55;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR23;
end
VAR55:begin
if(!VAR52) begin
VAR51 <= VAR44;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR55;
end
VAR44:begin
if(!VAR52) begin
VAR51 <= VAR48;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR44;
end
VAR48:begin
if(!VAR52) begin
VAR51 <= VAR21;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR48;
end
VAR21:begin
if(!VAR52) begin
VAR51 <= VAR50;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR21;
end
VAR50:begin
if(!VAR52) begin
VAR51 <= VAR15;
VAR20 <= VAR20<<1'b1;
end
else
VAR51 <= VAR50;
end
VAR15:begin
if((VAR52 == 1'b0) && (VAR6 == 1'b1) ) begin
VAR22 <= 1'b0;
VAR51 <= VAR10;
VAR6 <= 1'b0;
VAR2 <= 1'b1;
VAR33 <= VAR33 + 1'b1;
ack <= 1'b1;
end
else if(VAR52==0)begin
VAR22 <= 1'b0;
VAR51 <= VAR10;
VAR6 <= 1'b0;
VAR2 <= 1'b1;
VAR33 <= VAR33 + 1'b1;
end
else;
end
endcase
end
endtask
task VAR8;
begin
case(VAR43)
VAR3:begin
VAR43 <= VAR1;
VAR30 <= 1'b0;
ack <= 1'b0;
end
VAR1:begin
if(VAR52)begin
VAR17[7] <= VAR54;
VAR43 <= VAR32;
end
else begin
VAR22 <= 1'b0;
VAR43 <= VAR1;
end
end
VAR32:begin
if(VAR52)begin
VAR17[6] <= VAR54;
VAR43 <= VAR26;
end
else
VAR43 <= VAR32;
end
VAR26:begin
if(VAR52)begin
VAR17[5] <= VAR54;
VAR43 <= VAR40;
end
else
VAR43 <= VAR26;
end
VAR40:begin
if(VAR52)begin
VAR17[4] <= VAR54;
VAR43 <= VAR37;
end
else
VAR43 <= VAR40;
end
VAR37:begin
if(VAR52)begin
VAR17[3] <= VAR54;
VAR43 <= VAR25;
end
else
VAR43 <= VAR37;
end
VAR25:begin
if(VAR52)begin
VAR17[2] <= VAR54;
VAR43 <= VAR24;
end
else
VAR43 <= VAR25;
end
VAR24:begin
if(VAR52)begin
VAR17[1] <= VAR54;
VAR43 <= VAR11;
end
else
VAR43 <= VAR24;
end
VAR11:begin
if(VAR52)begin
VAR17[0] <= VAR54;
VAR43 <= VAR4;
end
else
VAR43 <= VAR11;
end
VAR4:begin
if(VAR45 == VAR13)begin
VAR30 <= 1'b1;
VAR22 <= 1'b1;
VAR43 <= VAR3;
VAR2 <= 1'b1;
VAR20[7] <= 1'b1;
VAR45 <= VAR45 + 1'b1;
ack <= 1'b1;
end
else begin
VAR30 <= 1'b1;
VAR22 <= 1'b1;
VAR43 <= VAR3;
VAR2 <= 1'b1;
VAR20[7] <= 1'b0;
VAR45 <= VAR45 + 1'b1;
ack <= 1'b1;
end
end
default:begin
VAR43 <= VAR3;
end
endcase
end
endtask
task VAR46;
begin
case(VAR27)
1'b0:begin
if(!VAR52)begin
VAR22 <= 1'b1;
VAR27 <= 1'b1;
VAR20[7]<= 1'b0;
end
else
VAR27 <= 1'b0;
end
1'b1:begin
if(VAR52)begin
VAR20[7] <= 1'b1;
VAR2 <= 1'b1;
VAR27 <= 1'b0;
end
else
VAR27 <=1'b1;
end
endcase
end
endtask
endmodule
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_idle_and_ver_gen.v
| 11,627 |
module MODULE1
(
VAR30,
VAR1,
VAR26,
VAR36,
VAR37,
VAR38,
VAR32,
VAR25
);
input VAR30;
output VAR1;
output VAR26;
output [0:1] VAR36;
output [0:1] VAR37;
output [0:1] VAR38;
input VAR32;
input VAR25;
reg [0:3] VAR2;
reg [0:3] VAR17;
reg VAR34;
reg VAR23;
wire VAR7;
wire VAR4;
wire VAR22;
wire [0:2] VAR5;
wire [0:1] VAR16;
wire [0:1] VAR11;
wire [0:1] VAR20;
wire VAR13;
wire [0:1] VAR18;
wire [0:1] VAR21;
wire [0:1] VAR12;
wire VAR29;
wire VAR14;
wire VAR15;
wire VAR33;
wire VAR6;
VAR28 VAR2 = 4'h0;
always @(posedge VAR25)
VAR2 <= VAR27 {VAR22,VAR2[0:2]};
VAR24 VAR31
(
.VAR8 (VAR7),
.VAR9 (VAR25),
.VAR35 (VAR2[3]),
.VAR3 (VAR32)
);
assign VAR4 = !(VAR2[3] ^ VAR7);
VAR24 VAR19
(
.VAR8 (VAR22),
.VAR9 (VAR25),
.VAR35 (VAR4),
.VAR3 (VAR32)
);
assign VAR5 = {VAR22,VAR2[3],VAR7};
|
gpl-2.0
|
SergKolo/msudenver_eet_4020_verilog
|
LAB_4/eight_bit_counter.v
| 3,139 |
module MODULE1(VAR6,enable,VAR17,VAR16);
input enable,VAR17,VAR16;
output [7:0] VAR6;
wire [6:0] VAR5;
wire VAR13;
MODULE2 MODULE1(VAR13,VAR17);
VAR10 VAR1(VAR6[0],enable,VAR13,VAR16);
assign VAR5[0] = VAR6[0] & enable;
VAR10 VAR2(VAR6[1],VAR5[0],VAR13,VAR16);
assign VAR5[1] = VAR5[0] & VAR6[1];
VAR10 VAR8(VAR6[2],VAR5[1],VAR13,VAR16);
assign VAR5[2] = VAR5[1] & VAR6[2];
VAR10 VAR3(VAR6[3],VAR5[2],VAR13,VAR16);
assign VAR5[3] = VAR5[2] & VAR6[3];
VAR10 VAR14(VAR6[4],VAR5[3],VAR13,VAR16);
assign VAR5[4] = VAR5[3] & VAR6[4];
VAR10 VAR15(VAR6[5],VAR5[4],VAR13,VAR16);
assign VAR5[5] = VAR5[4] & VAR6[5];
VAR10 VAR9(VAR6[6],VAR5[5],VAR13,VAR16);
assign VAR5[6] = VAR5[5] & VAR6[6];
VAR10 VAR12(VAR6[7],VAR5[6],VAR13,VAR16);
endmodule
module MODULE2(VAR7,VAR4);
input VAR4;
output reg VAR7;
reg [24:0] counter;
begin
begin
begin
end
begin
end
begin
begin
|
mit
|
asicguy/gplgpu
|
hdl/altera_project/dpram_64_32x32/dpram_64_32x32_bb.v
| 7,216 |
module MODULE1 (
VAR1,
VAR4,
VAR7,
VAR5,
VAR3,
VAR6,
VAR2);
input [31:0] VAR1;
input VAR4;
input [4:0] VAR7;
input [3:0] VAR5;
input VAR3;
input VAR6;
output [63:0] VAR2;
endmodule
|
gpl-3.0
|
vvk/sysrek
|
hdmi_example/src/hdmi_main.v
| 10,867 |
module MODULE1
(
input wire VAR7, input wire VAR73,
input wire [3:0] VAR88,
input wire [3:0] VAR117,
output wire [3:0] VAR146,
output wire [3:0] VAR18,
output wire [7:0] VAR99
);
wire VAR1, VAR71;
VAR25 #(.VAR152("VAR44"), .VAR24(5))
VAR114 (.VAR116(VAR71), .VAR15(), .VAR128(), .VAR121(VAR73));
VAR110 VAR76 (.VAR121(VAR71), .VAR59(VAR1));
wire VAR60, VAR29, VAR38, VAR82;
wire VAR28;
wire VAR66;
wire VAR11;
wire VAR120; wire VAR101; wire VAR68; wire VAR72; wire [7:0] VAR92; wire [7:0] VAR109; wire [7:0] VAR127; wire [29:0] VAR151;
wire VAR135;
wire VAR57;
wire VAR122;
wire VAR16;
wire VAR107;
wire VAR134;
VAR54 VAR23 (
.VAR77 (VAR88[3]),
.VAR79 (VAR117[3]),
.VAR62 (VAR88[0]),
.VAR100 (VAR88[1]),
.VAR69 (VAR88[2]),
.VAR144 (VAR117[0]),
.VAR22 (VAR117[1]),
.VAR49 (VAR117[2]),
.VAR50 (~VAR7),
.reset (VAR66),
.VAR132 (VAR60),
.VAR106 (VAR29),
.VAR64 (VAR38),
.VAR56 (VAR82), .VAR42 (VAR58), .VAR103 (VAR10), .VAR61 (VAR28),
.VAR67 (VAR14),
.VAR93(VAR11),
.VAR115 (VAR120),
.VAR78 (VAR101),
.VAR4 (VAR68),
.VAR143 (VAR135),
.VAR3 (VAR57),
.VAR85 (VAR122),
.VAR84 (VAR16),
.VAR119 (VAR107),
.VAR48 (VAR134),
.VAR80 (VAR72),
.VAR75 (VAR151),
.VAR55 (VAR92),
.VAR40 (VAR109),
.VAR13 (VAR127));
VAR97 VAR23 (
.VAR77 (VAR88[3]),
.VAR79 (VAR117[3]),
.VAR62 (VAR88[0]),
.VAR100 (VAR88[1]),
.VAR69 (VAR88[2]),
.VAR144 (VAR117[0]),
.VAR22 (VAR117[1]),
.VAR49 (VAR117[2]),
.VAR50 (~VAR7),
.reset (VAR66),
.VAR132 (VAR60),
.VAR106 (VAR29),
.VAR64 (VAR38),
.VAR56 (VAR82), .VAR42 (VAR58), .VAR103 (VAR10), .VAR61 (VAR28),
.VAR67 (VAR14),
.VAR93(VAR11),
.VAR115 (VAR120),
.VAR78 (VAR101),
.VAR4 (VAR68),
.VAR143 (VAR135),
.VAR3 (VAR57),
.VAR85 (VAR122),
.VAR84 (VAR16),
.VAR119 (VAR107),
.VAR48 (VAR134),
.VAR80 (VAR72),
.VAR75 (VAR151),
.VAR55 (VAR92),
.VAR40 (VAR109),
.VAR13 (VAR127));
wire [7:0] VAR140;
wire [7:0] VAR43;
wire [7:0] VAR39;
VAR19 VAR141 (
.VAR145(VAR92), .clk(VAR60), .VAR91(VAR43) );
VAR19 VAR130 (
.VAR145(VAR109), .clk(VAR60), .VAR91(VAR39) );
VAR19 VAR32 (
.VAR145(VAR127), .clk(VAR60), .VAR91(VAR140) );
reg VAR150 = 0;
reg VAR125 = 0;
reg VAR70 = 0;
always @(posedge VAR60)
begin
VAR150 <= VAR68;
VAR125 <= VAR120;
VAR70 <= VAR101;
end
wire VAR2;
wire VAR113;
wire VAR5;
wire VAR63;
wire VAR131;
wire VAR41;
wire [7:0] VAR90;
wire [7:0] VAR142;
wire [7:0] VAR53;
wire VAR46;
wire VAR74;
wire VAR118;
assign VAR118 = VAR66;
assign VAR2 = VAR150;
assign VAR46 = VAR125;
assign VAR74 = VAR70;
assign VAR90 = VAR140 & VAR39 & VAR43;
assign VAR142 = VAR140 & VAR39 & VAR43;
assign VAR53 = VAR140 & VAR39 & VAR43;
wire VAR12, VAR6, VAR96;
wire VAR139, VAR133;
VAR34 # (
.VAR149(10),
.VAR86(10), .VAR112(1),
.VAR81(10),
.VAR45(5),
.VAR147("VAR37")
) VAR136 (
.VAR124(VAR12),
.VAR123(VAR139),
.VAR148(),
.VAR65(VAR133),
.VAR129(),
.VAR87(),
.VAR108(),
.VAR30(VAR96),
.VAR111(VAR6),
.VAR9(VAR113),
.VAR33(VAR118)
);
VAR83 VAR94 (.VAR98(1'b1), .VAR51(VAR58), .VAR17(VAR58), .VAR59(VAR113));
VAR110 VAR126 (.VAR121(VAR12), .VAR59(VAR6));
VAR110 VAR52 (.VAR121(VAR133), .VAR59(VAR5));
wire VAR95;
VAR36 #(.VAR24(5)) VAR35 (.VAR21(VAR139), .VAR47(VAR5), .VAR30(VAR96),
.VAR15(VAR63), .VAR128(VAR131), .VAR8(VAR26));
assign VAR104 = ~VAR95;
VAR102 VAR137 (
.VAR132 (VAR113),
.VAR106 (VAR5),
.VAR64 (VAR63),
.VAR93(VAR131),
.VAR31 (VAR41),
.VAR138 (VAR90),
.VAR20 (VAR142),
.VAR89 (VAR53),
.VAR115 (VAR46),
.VAR78 (VAR74),
.VAR4 (VAR2),
.VAR105 (VAR146),
.VAR27 (VAR18));
assign VAR99 = {VAR134, VAR107, VAR16, VAR134, VAR107, VAR16,
VAR68, VAR68};
endmodule
|
gpl-2.0
|
hpeng2/ECE492_Group4_Project
|
ECE_492_Project_new/Video_System/synthesis/submodules/altera_up_video_scaler_multiply_width.v
| 7,790 |
module MODULE1 (
clk,
reset,
VAR6,
VAR12,
VAR15,
VAR3,
VAR14,
VAR8,
VAR11,
VAR4,
VAR16,
VAR1
);
parameter VAR9 = 15;
parameter VAR2 = 0;
input clk;
input reset;
input [VAR9: 0] VAR6;
input VAR12;
input VAR15;
input VAR3;
input VAR14;
output VAR8;
output reg [VAR9: 0] VAR11;
output reg VAR4;
output reg VAR16;
output reg VAR1;
reg [VAR9: 0] VAR7;
reg VAR5;
reg VAR13;
reg valid;
reg [VAR2: 0] VAR10;
always @(posedge clk)
begin
if (reset)
begin
VAR11 <= 'h0;
VAR4 <= 1'b0;
VAR16 <= 1'b0;
VAR1 <= 1'b0;
end
else if (VAR14 | ~VAR1)
begin
VAR11 <= VAR7;
if (|(VAR10))
VAR4 <= 1'b0;
end
else
VAR4 <= VAR5;
if (&(VAR10))
VAR16 <= VAR13;
end
else
VAR16 <= 1'b0;
VAR1 <= valid;
end
end
always @(posedge clk)
begin
if (reset)
begin
VAR7 <= 'h0;
VAR5 <= 1'b0;
VAR13 <= 1'b0;
valid <= 1'b0;
end
else if (VAR8)
begin
VAR7 <= VAR6;
VAR5 <= VAR12;
VAR13 <= VAR15;
valid <= VAR3;
end
end
always @(posedge clk)
begin
if (reset)
VAR10 <= 'h0;
end
else if ((VAR14 | ~VAR1) & valid)
VAR10 <= VAR10 + 1;
end
assign VAR8 = (~valid) |
((&(VAR10)) & (VAR14 | ~VAR1));
endmodule
|
gpl-2.0
|
BilkentCompGen/GateKeeper
|
FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_eq.v
| 35,592 |
module MODULE1 #
(
parameter VAR104 = "VAR88",
parameter VAR54 = "VAR76",
parameter VAR109 = 1
)
(
input VAR30,
input VAR112,
input VAR3,
input [ 1:0] VAR40,
input [ 3:0] VAR41,
input [ 3:0] VAR20,
input [ 5:0] VAR128,
input [ 1:0] VAR7,
input [ 2:0] VAR107,
input [ 5:0] VAR22,
input [ 3:0] VAR98,
input VAR83,
input [17:0] VAR114,
input VAR55,
output VAR117,
output [ 4:0] VAR23,
output [ 6:0] VAR89,
output [ 4:0] VAR135,
output [17:0] VAR50,
output VAR106,
output [ 5:0] VAR94,
output [17:0] VAR127,
output VAR63,
output VAR5,
output VAR21,
output [ 5:0] VAR52
);
reg VAR35;
reg VAR69;
reg [ 1:0] VAR132;
reg [ 3:0] VAR15;
reg [ 5:0] VAR118;
reg [ 1:0] VAR136;
reg [ 3:0] VAR37;
reg [ 5:0] VAR68;
reg [ 1:0] VAR99;
reg [ 2:0] VAR137;
reg [ 5:0] VAR101;
reg [ 3:0] VAR93;
reg VAR9;
reg [17:0] VAR18;
reg VAR130;
reg [ 1:0] VAR119;
reg [ 2:0] VAR125;
reg [ 5:0] VAR77;
reg [ 3:0] VAR116;
reg VAR103;
reg [17:0] VAR92;
reg VAR25;
reg [18:0] VAR28 = 19'd0;
reg VAR138 = 1'd0;
reg [ 1:0] VAR51 = 2'd0;
reg [ 2:0] VAR86 = 3'd0;
reg VAR16 = 1'd0;
reg [ 3:0] VAR24 = 4'd0;
reg [17:0] VAR84 = 18'd0;
reg [ 2:0] VAR81 = 3'd0;
reg [ 5:0] VAR12 = 6'd0;
reg [ 5:0] VAR73 = 6'd0;
reg VAR70 = 1'd0;
reg [18:0] VAR36 = 19'd0;
reg VAR38 = 1'd0;
reg [ 5:0] VAR58 = 6'd0;
reg [17:0] VAR67 = 18'd0;
reg VAR53 = 1'd0;
reg VAR100 = 1'd0;
reg VAR8 = 1'd0;
reg VAR82 = 1'd0;
reg [ 5:0] VAR34 = 6'd0;
wire VAR87;
wire VAR108;
wire [17:0] VAR72;
wire VAR62;
wire VAR11;
localparam VAR78 = 6'b000001;
localparam VAR122 = 6'b000010;
localparam VAR46 = 6'b000100;
localparam VAR14 = 6'b001000;
localparam VAR47 = 6'b010000;
localparam VAR56 = 6'b100000;
localparam VAR97 = 6'b000001;
localparam VAR1 = 6'b000010;
localparam VAR33 = 6'b000100;
localparam VAR110 = 6'b001000;
localparam VAR27 = 6'b010000;
localparam VAR61 = 6'b100000;
localparam VAR29 = 6'd0; localparam VAR85 = 7'd60;
localparam VAR45 = 6'd20;
localparam VAR129 = 6'd0; localparam VAR60 = 7'd68; localparam VAR123 = 6'd13;
localparam VAR43 = 6'd0; localparam VAR42 = 7'd64;
localparam VAR17 = 6'd16;
localparam VAR105 = 6'd0; localparam VAR121 = 7'd70;
localparam VAR66 = 6'd10;
localparam VAR71 = 6'd0; localparam VAR139 = 7'd80;
localparam VAR49 = 6'd0;
localparam VAR59 = 6'd8; localparam VAR64 = 7'd72;
localparam VAR140 = 6'd0;
localparam VAR124 = 6'd10; localparam VAR131 = 7'd70;
localparam VAR44 = 6'd0;
localparam VAR111 = 6'd8; localparam VAR13 = 7'd56;
localparam VAR39 = 6'd16;
localparam VAR19 = 6'd10; localparam VAR26 = 7'd60;
localparam VAR75 = 6'd10;
localparam VAR80 = 6'd13; localparam VAR10 = 7'd68; localparam VAR57 = 6'd0;
localparam VAR4 = 6'd0; localparam VAR113 = 7'd56; localparam VAR115 = 6'd25;
always @ (posedge VAR30)
begin
if (!VAR112)
begin
VAR35 <= 1'd0;
VAR132 <= 2'd0;
VAR15 <= 4'd0;
VAR118 <= 6'd1;
VAR99 <= 2'd0;
VAR137 <= 3'd0;
VAR101 <= 6'd0;
VAR93 <= 4'd0;
VAR9 <= 1'd0;
VAR18 <= 18'd0;
VAR130 <= 1'd0;
VAR69 <= 1'd0;
VAR136 <= 2'd0;
VAR37 <= 4'd0;
VAR68 <= 6'd1;
VAR119 <= 2'd0;
VAR125 <= 3'd0;
VAR77 <= 6'd0;
VAR116 <= 4'd0;
VAR103 <= 1'd0;
VAR92 <= 18'd0;
VAR25 <= 1'd0;
end
else
begin
VAR35 <= VAR3;
VAR132 <= VAR40;
VAR15 <= VAR41;
VAR118 <= VAR128;
VAR99 <= VAR7;
VAR137 <= VAR107;
VAR101 <= VAR22;
VAR93 <= VAR98;
VAR9 <= VAR83;
VAR18 <= VAR114;
VAR130 <= VAR55;
VAR69 <= VAR35;
VAR136 <= VAR132;
VAR37 <= VAR15;
VAR68 <= VAR118;
VAR119 <= VAR99;
VAR125 <= VAR137;
VAR77 <= VAR101;
VAR116 <= VAR93;
VAR103 <= VAR9;
VAR92 <= VAR18;
VAR25 <= VAR130;
end
end
always @ (posedge VAR30)
begin
if (!VAR112)
begin
case (VAR20)
4'd0 : VAR28 <= {VAR45, VAR85, VAR29};
4'd1 : VAR28 <= {VAR123, VAR60, VAR129};
4'd2 : VAR28 <= {VAR17, VAR42, VAR43};
4'd3 : VAR28 <= {VAR66, VAR121, VAR105};
4'd4 : VAR28 <= {VAR49, VAR139, VAR71};
4'd5 : VAR28 <= {VAR140, VAR64, VAR59};
4'd6 : VAR28 <= {VAR44, VAR131, VAR124};
4'd7 : VAR28 <= {VAR39, VAR13, VAR111};
4'd8 : VAR28 <= {VAR75, VAR26, VAR19};
4'd9 : VAR28 <= {VAR57, VAR10, VAR80};
4'd10 : VAR28 <= {VAR115, VAR113, VAR4};
default : VAR28 <= 19'd4;
endcase
VAR138 <= 1'd0;
end
else
begin
if (VAR58 == VAR122)
begin
case (VAR37)
4'd0 : VAR28 <= {VAR45, VAR85, VAR29};
4'd1 : VAR28 <= {VAR123, VAR60, VAR129};
4'd2 : VAR28 <= {VAR17, VAR42, VAR43};
4'd3 : VAR28 <= {VAR66, VAR121, VAR105};
4'd4 : VAR28 <= {VAR49, VAR139, VAR71};
4'd5 : VAR28 <= {VAR140, VAR64, VAR59};
4'd6 : VAR28 <= {VAR44, VAR131, VAR124};
4'd7 : VAR28 <= {VAR39, VAR13, VAR111};
4'd8 : VAR28 <= {VAR75, VAR26, VAR19};
4'd9 : VAR28 <= {VAR57, VAR10, VAR80};
4'd10 : VAR28 <= {VAR115, VAR113, VAR4};
default : VAR28 <= 19'd4;
endcase
VAR138 <= 1'd1;
end
else
begin
VAR28 <= VAR28;
VAR138 <= 1'd0;
end
end
end
always @ (posedge VAR30)
begin
if (!VAR112)
begin
VAR58 <= VAR78;
VAR36 <= 19'd0;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
else
begin
case (VAR58)
VAR78 :
begin
case (VAR136)
2'd0 :
begin
VAR58 <= VAR78;
VAR36 <= VAR36;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
2'd1 :
begin
VAR58 <= VAR122;
VAR36 <= VAR36;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
2'd2 :
begin
VAR58 <= VAR46;
VAR36 <= {VAR68, VAR36[18:6]};
VAR51 <= 2'd1;
VAR38 <= 1'd0;
end
2'd3 :
begin
VAR58 <= VAR47;
VAR36 <= VAR36;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
default :
begin
VAR58 <= VAR78;
VAR36 <= VAR36;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
endcase
end
VAR122 :
begin
VAR58 <= (VAR138 ? VAR56 : VAR122);
VAR36 <= VAR28;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
VAR46 :
begin
VAR58 <= ((VAR51 == 2'd2) ? VAR14 : VAR46);
if (VAR51 == 2'd1)
VAR36 <= {1'd0, VAR68, VAR36[18:7]};
end
else
VAR36 <= {VAR68, VAR36[18:6]};
VAR51 <= VAR51 + 2'd1;
VAR38 <= 1'd0;
end
VAR14 :
begin
VAR58 <= VAR56;
VAR36 <= VAR36 << 1; VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
VAR47:
begin
VAR58 <= VAR56;
VAR36 <= VAR36;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
VAR56 :
begin
VAR58 <= ((VAR136 == 2'd0) ? VAR78 : VAR56);
VAR36 <= VAR36;
VAR51 <= 2'd0;
VAR38 <= 1'd1;
end
default :
begin
VAR58 <= VAR78;
VAR36 <= 19'd0;
VAR51 <= 2'd0;
VAR38 <= 1'd0;
end
endcase
end
end
always @ (posedge VAR30)
begin
if (!VAR112)
begin
VAR34 <= VAR97;
VAR86 <= 3'd0;
VAR16 <= 1'd0;
VAR24 <= 4'd0;
VAR84 <= 18'd0;
VAR81 <= 3'd0;
VAR12 <= 6'd0;
VAR73 <= 6'd0;
VAR70 <= 1'd0;
VAR67 <= 18'd0;
VAR53 <= 1'd0;
VAR100 <= 1'd0;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
else
begin
case (VAR34)
VAR97 :
begin
case (VAR119)
2'd1 :
begin
VAR34 <= VAR1;
VAR86 <= VAR125;
VAR16 <= 1'd0;
VAR24 <= VAR24;
VAR84 <= VAR84;
VAR81 <= 3'd0;
VAR12 <= VAR12;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd0;
VAR100 <= 1'd0;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
2'd2 :
begin
VAR34 <= VAR33;
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR116;
VAR84 <= {VAR68, VAR84[17:6]};
VAR81 <= 3'd1;
VAR12 <= VAR77;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd0;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
2'd3 :
begin
VAR34 <= VAR33;
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR116;
VAR84 <= {VAR68, VAR84[17:6]};
VAR81 <= 3'd1;
VAR12 <= VAR77;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd0;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
default :
begin
VAR34 <= VAR97;
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR24;
VAR84 <= VAR84;
VAR81 <= 3'd0;
VAR12 <= VAR12;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd0;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
endcase
end
VAR1 :
begin
VAR34 <= (VAR108 ? VAR61 : VAR1);
VAR86 <= VAR125;
VAR16 <= 1'd1;
VAR24 <= VAR24;
VAR84 <= VAR84;
VAR81 <= 3'd0;
VAR12 <= VAR12;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd0;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
VAR33 :
begin
VAR34 <= ((VAR81 == 3'd2) ? VAR110 : VAR33);
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR116;
VAR84 <= {VAR68, VAR84[17:6]};
VAR81 <= VAR81 + 2'd1;
VAR12 <= VAR12;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd1;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
VAR110 :
begin
VAR34 <= ((VAR81 == 3'd7) ? VAR27 : VAR110);
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR24;
VAR84 <= VAR84;
VAR81 <= VAR81 + 2'd1;
VAR12 <= VAR12;
VAR73 <= ((VAR81 == 3'd7) ? VAR77 : VAR73);
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= 1'd1;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
VAR27 :
begin
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR24;
VAR84 <= VAR84;
VAR81 <= 3'd0;
VAR12 <= VAR12;
VAR73 <= VAR73;
if (VAR62)
begin
VAR34 <= VAR61;
VAR70 <= 1'd0;
VAR67 <= VAR87 ? {14'd0, VAR72[3:0]} : VAR72;
VAR53 <= VAR87;
VAR100 <= VAR11 || VAR100;
VAR8 <= VAR11 || VAR100;
VAR82 <= 1'd1;
end
else
begin
VAR34 <= VAR27;
VAR70 <= 1'd1;
VAR67 <= VAR67;
VAR53 <= 1'd0;
VAR100 <= VAR100;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
end
VAR61 :
begin
VAR34 <= ((VAR119 == 2'd0) ? VAR97 : VAR61);
VAR86 <= VAR86;
VAR16 <= 1'd0;
VAR24 <= VAR24;
VAR84 <= VAR84;
VAR81 <= 3'd0;
VAR12 <= VAR12;
VAR73 <= VAR73;
VAR70 <= 1'd0;
VAR67 <= VAR67;
VAR53 <= VAR53;
VAR100 <= VAR100;
VAR8 <= VAR8;
VAR82 <= 1'd1;
end
default :
begin
VAR34 <= VAR97;
VAR86 <= 3'd0;
VAR16 <= 1'd0;
VAR24 <= 4'd0;
VAR84 <= 18'd0;
VAR81 <= 3'd0;
VAR12 <= 6'd0;
VAR73 <= 6'd0;
VAR70 <= 1'd0;
VAR67 <= 18'd0;
VAR53 <= 1'd0;
VAR100 <= 1'd0;
VAR8 <= 1'd0;
VAR82 <= 1'd0;
end
endcase
end
end
VAR79 #
(
.VAR104 (VAR104),
.VAR54 (VAR54),
.VAR109 (VAR109)
)
VAR6
(
.VAR95 (VAR30),
.VAR126 (VAR112),
.VAR48 (VAR119),
.VAR102 (VAR12),
.VAR31 (VAR73),
.VAR96 (VAR86),
.VAR91 (VAR16),
.VAR2 (VAR24),
.VAR65 (VAR84),
.VAR90 (VAR70),
.VAR74 (VAR108),
.VAR134 (VAR72),
.VAR120 (VAR62),
.VAR133 (VAR87),
.VAR32 (VAR11)
);
assign VAR117 = VAR36[0];
assign VAR23 = VAR69 ? VAR36[ 4: 0] : 5'h00;
assign VAR89 = VAR69 ? VAR36[12: 6] : 7'h00;
assign VAR135 = VAR69 ? VAR36[17:13] : 5'h00;
assign VAR50 = {1'd0, VAR36[18:14], VAR36[12:7], 1'd0, VAR36[5:1]}; assign VAR106 = VAR38;
assign VAR94 = VAR58;
assign VAR127 = VAR103 ? VAR92 : VAR67;
assign VAR63 = VAR103 ? VAR25 : VAR53;
assign VAR5 = VAR8;
assign VAR21 = VAR82;
assign VAR52 = VAR34;
endmodule
|
gpl-3.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_116.v
| 1,562 |
module MODULE2 (
VAR6,
VAR12
);
input [31:0] VAR6;
output [31:0]
VAR12;
wire [31:0]
VAR4,
VAR15,
VAR5,
VAR8,
VAR13,
VAR10,
VAR14,
VAR9,
VAR1,
VAR3;
assign VAR4 = VAR6;
assign VAR5 = VAR15 - VAR4;
assign VAR15 = VAR4 << 10;
assign VAR9 = VAR14 << 2;
assign VAR8 = VAR4 << 11;
assign VAR3 = VAR1 << 3;
assign VAR1 = VAR13 - VAR9;
assign VAR13 = VAR5 + VAR8;
assign VAR10 = VAR4 << 5;
assign VAR14 = VAR4 + VAR10;
assign VAR12 = VAR3;
endmodule
module MODULE1(
VAR6,
VAR12,
clk
);
input [31:0] VAR6;
output [31:0] VAR12;
reg [31:0] VAR12;
input clk;
reg [31:0] VAR11;
wire [30:0] VAR7;
always @(posedge clk) begin
VAR11 <= VAR6;
VAR12 <= VAR7;
end
MODULE2 MODULE1(
.VAR6(VAR11),
.VAR12(VAR7)
);
endmodule
|
mit
|
fallen/milkymist-mmu
|
cores/hpdmc_ddr32/rtl/hpdmc.v
| 5,508 |
module MODULE1 #(
parameter VAR48 = 4'h0,
parameter VAR39 = 26,
parameter VAR1 = 9
) (
input VAR15,
input VAR74,
input VAR22,
input [13:0] VAR20,
input VAR73,
input [31:0] VAR16,
output [31:0] VAR46,
input [VAR39-1:0] VAR27,
input VAR18,
input VAR68,
output VAR43,
input [7:0] VAR2,
input [63:0] VAR21,
output [63:0] VAR49,
output reg VAR72,
output reg VAR60,
output reg VAR11,
output reg VAR59,
output reg VAR26,
output reg [12:0] VAR54,
output reg [1:0] VAR53,
output [3:0] VAR38,
inout [31:0] VAR9,
inout [3:0] VAR63
);
wire VAR28;
wire VAR24;
wire VAR75;
wire VAR25;
wire VAR4;
wire [12:0] VAR44;
wire [1:0] VAR66;
always @(posedge VAR15) begin
VAR72 <= VAR28;
VAR60 <= VAR24;
VAR11 <= VAR75;
VAR59 <= VAR25;
VAR26 <= VAR4;
VAR53 <= VAR66;
VAR54 <= VAR44;
end
wire VAR35;
wire VAR45;
wire VAR13;
wire VAR42;
wire VAR10;
wire [12:0] VAR67;
wire [1:0] VAR14;
wire VAR65;
wire VAR56;
wire VAR5;
wire VAR62;
wire [12:0] VAR58;
wire [1:0] VAR40;
assign VAR24 = VAR35 ? VAR45 : VAR65;
assign VAR75 = VAR35 ? VAR13 : VAR56;
assign VAR25 = VAR35 ? VAR42 : VAR5;
assign VAR4 = VAR35 ? VAR10 : VAR62;
assign VAR44 = VAR35 ? VAR67 : VAR58;
assign VAR66 = VAR35 ? VAR14 : VAR40;
wire VAR41;
wire [2:0] VAR34;
wire [2:0] VAR69;
wire VAR7;
wire [10:0] VAR71;
wire [3:0] VAR61;
wire [1:0] VAR12;
wire VAR30;
wire VAR47;
wire VAR17;
wire VAR19;
VAR57 #(
.VAR48(VAR48)
) VAR51 (
.VAR15(VAR15),
.VAR22(VAR22),
.VAR20(VAR20),
.VAR73(VAR73),
.VAR16(VAR16),
.VAR46(VAR46),
.VAR35(VAR35),
.VAR41(VAR41),
.VAR72(VAR28),
.VAR60(VAR45),
.VAR11(VAR13),
.VAR59(VAR42),
.VAR26(VAR10),
.VAR54(VAR67),
.VAR53(VAR14),
.VAR34(VAR34),
.VAR69(VAR69),
.VAR7(VAR7),
.VAR71(VAR71),
.VAR61(VAR61),
.VAR12(VAR12),
.VAR30(VAR30),
.VAR47(VAR47),
.VAR17(VAR17),
.VAR19(VAR19)
);
wire read;
wire write;
wire [3:0] VAR23;
wire VAR37;
wire VAR3;
wire [3:0] VAR52;
VAR29 #(
.VAR39(VAR39),
.VAR1(VAR1)
) VAR32 (
.VAR15(VAR15),
.VAR41(VAR41),
.VAR34(VAR34),
.VAR69(VAR69),
.VAR71(VAR71),
.VAR61(VAR61),
.VAR6(VAR18),
.VAR70(VAR68),
.address(VAR27[VAR39-1:3]),
.ack(VAR43),
.read(read),
.write(write),
.VAR23(VAR23),
.VAR37(VAR37),
.VAR3(VAR3),
.VAR52(VAR52),
.VAR60(VAR65),
.VAR11(VAR56),
.VAR59(VAR5),
.VAR26(VAR62),
.VAR54(VAR58),
.VAR53(VAR40)
);
wire VAR50;
VAR64 VAR31(
.VAR15(VAR15),
.VAR41(VAR41),
.read(read),
.write(write),
.VAR23(VAR23),
.VAR37(VAR37),
.VAR3(VAR3),
.VAR52(VAR52),
.VAR50(VAR50),
.VAR7(VAR7),
.VAR12(VAR12)
);
VAR8 VAR55(
.VAR15(VAR15),
.VAR74(VAR74),
.VAR50(VAR50),
.VAR36(~VAR2),
.do(VAR21),
.VAR33(VAR49),
.VAR38(VAR38),
.VAR9(VAR9),
.VAR63(VAR63),
.VAR30(VAR30),
.VAR47(VAR47),
.VAR17(VAR17),
.VAR19(VAR19)
);
endmodule
|
lgpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/axi_hdmi_rx/axi_hdmi_rx.v
| 7,574 |
module MODULE1 (
VAR29,
VAR36,
VAR57,
VAR23,
VAR39,
VAR41,
VAR48,
VAR77,
VAR8,
VAR90,
VAR82,
VAR35,
VAR20,
VAR37,
VAR89,
VAR97,
VAR19,
VAR18,
VAR70,
VAR55,
VAR3,
VAR66,
VAR78,
VAR26,
VAR27,
VAR81,
VAR34);
parameter VAR83 = 0;
input VAR29;
input [15:0] VAR36;
output VAR57;
output VAR23;
output VAR39;
output [63:0] VAR41;
input VAR48;
input VAR77;
input VAR90;
input VAR8;
input VAR82;
input [31:0] VAR35;
output VAR20;
input VAR37;
input [31:0] VAR89;
input [ 3:0] VAR97;
output VAR19;
output VAR18;
output [ 1:0] VAR70;
input VAR55;
input VAR3;
input [31:0] VAR66;
output VAR78;
output VAR26;
output [ 1:0] VAR27;
output [31:0] VAR81;
input VAR34;
wire VAR7;
wire [13:0] VAR88;
wire [31:0] VAR59;
wire VAR61;
wire VAR51;
wire [13:0] VAR21;
wire [31:0] VAR93;
wire VAR13;
wire VAR46;
wire VAR91;
wire VAR38;
wire VAR65;
wire [15:0] VAR11;
wire [15:0] VAR17;
wire VAR4;
wire VAR60;
wire VAR12;
wire VAR67;
wire VAR73;
wire [15:0] VAR15;
wire [15:0] VAR74;
wire VAR84;
wire [15:0] VAR5;
assign VAR57 = VAR29;
assign VAR5 = VAR36;
assign VAR53 = VAR90;
assign VAR95 = VAR8;
VAR87 VAR86 (
.VAR53 (VAR53),
.VAR95 (VAR95),
.VAR75 (VAR82),
.VAR64 (VAR35),
.VAR31 (VAR20),
.VAR30 (VAR37),
.VAR76 (VAR89),
.VAR92 (VAR97),
.VAR52 (VAR19),
.VAR24 (VAR18),
.VAR16 (VAR70),
.VAR50 (VAR55),
.VAR1 (VAR3),
.VAR69 (VAR66),
.VAR96 (VAR78),
.VAR56 (VAR26),
.VAR25 (VAR27),
.VAR85 (VAR81),
.VAR42 (VAR34),
.VAR32 (VAR7),
.VAR45 (VAR88),
.VAR28 (VAR59),
.VAR6 (VAR61),
.VAR44 (VAR51),
.VAR72 (VAR21),
.VAR58 (VAR93),
.VAR68 (VAR13));
VAR14 VAR98 (
.VAR57 (VAR57),
.VAR84 (VAR84),
.VAR43 (VAR46),
.VAR40 (VAR91),
.VAR10 (VAR38),
.VAR2 (VAR65),
.VAR33 (VAR11),
.VAR63 (VAR17),
.VAR48 (VAR48),
.VAR77 (VAR77),
.VAR80 (VAR4),
.VAR54 (VAR60),
.VAR94 (VAR12),
.VAR71 (VAR67),
.VAR79 (VAR73),
.VAR49 (VAR15),
.VAR22 (VAR74),
.VAR47 (32'd1),
.VAR53 (VAR53),
.VAR95 (VAR95),
.VAR32 (VAR7),
.VAR45 (VAR88),
.VAR28 (VAR59),
.VAR6 (VAR61),
.VAR44 (VAR51),
.VAR72 (VAR21),
.VAR58 (VAR93),
.VAR68 (VAR13));
VAR9 VAR62 (
.VAR57 (VAR57),
.VAR84 (VAR84),
.VAR5 (VAR5),
.VAR43 (VAR46),
.VAR40 (VAR91),
.VAR10 (VAR38),
.VAR2 (VAR65),
.VAR33 (VAR11),
.VAR63 (VAR17),
.VAR80 (VAR4),
.VAR54 (VAR60),
.VAR94 (VAR12),
.VAR71 (VAR67),
.VAR79 (VAR73),
.VAR49 (VAR15),
.VAR22 (VAR74),
.VAR23 (VAR23),
.VAR39 (VAR39),
.VAR41 (VAR41));
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.blackbox.v
| 1,311 |
module MODULE1 (
VAR4,
VAR1 ,
VAR3 ,
VAR2
);
output VAR4;
input VAR1 ;
input VAR3 ;
input VAR2 ;
endmodule
|
apache-2.0
|
CospanDesign/nysa-verilog
|
verilog/axi/master/axi_lite_master.v
| 12,807 |
module MODULE1 #(
parameter VAR13 = 1,
parameter VAR70 = 32,
parameter VAR22 = 32,
parameter VAR11 = 32'd100000000 )(
output [31:0] VAR68,
output reg VAR46,
input VAR16,
output reg VAR63,
output reg VAR54,
input [VAR70 - 1:0] VAR37,
input VAR18, input [3:0] VAR62,
input [31:0] VAR19,
output reg [31:0] VAR41,
input clk,
input rst,
output [3:0] VAR3, output [VAR70 - 1:0] VAR42, output [2:0] VAR17,
output reg VAR27, input VAR15,
output [3:0] VAR14, output reg [31:0] VAR5, output reg [3:0] VAR53, output VAR30, output reg VAR56, input VAR65,
input [3:0] VAR12, input [1:0] VAR57, input VAR28, output reg VAR33,
output [3:0] VAR4, output [VAR70 - 1:0] VAR45, output reg [7:0] VAR26, output [2:0] VAR51, output reg VAR10, input VAR25, input [3:0] VAR67, input [31: 0] VAR31, input [1:0] VAR39, input [3:0] VAR6, input VAR71, input VAR47, output reg VAR29, input [VAR22 - 1:0] VAR23
);
localparam VAR21 = 4'h0;
localparam VAR48 = 4'h1; localparam VAR60 = 4'h2; localparam VAR69 = 4'h3;
localparam VAR59 = 4'h4; localparam VAR72 = 4'h5; localparam VAR20 = 4'h6;
localparam VAR7 = 4'h7;
localparam VAR38 = 4'h8;
localparam VAR49 = 5'h9;
reg [3:0] state = VAR21;
wire [15:0] VAR32;
wire [31:0] VAR55;
reg [VAR70 - 1:0] VAR44;
reg [31:0] VAR61;
wire [31:0] VAR8;
reg [31:0] VAR2; reg [31:0] VAR43;
wire VAR40;
reg [1:0] VAR34;
wire VAR35;
reg [VAR22 - 1:0] VAR9;
reg VAR52 = 0;
reg VAR36;
reg [31:0] VAR50;
assign VAR68[VAR66] = (state != VAR21);
assign VAR68[3:1] = 0;
assign VAR68[VAR24] = VAR52;
assign VAR68[VAR1] = VAR36;
assign VAR68[7:6] = 0;
assign VAR68[VAR64] = VAR34;
assign VAR68[9:8] = 0;
assign VAR68[31:6] = 0;
assign VAR17 = VAR58;
assign VAR51 = VAR58;
assign VAR35 = (VAR13) ? ~rst : rst;
assign VAR42 = VAR44;
assign VAR45 = VAR44;
assign VAR30 = 1'b1;
assign VAR4 = 4'h0;
assign VAR3 = 4'h0;
assign VAR14 = 4'h0;
always @ (posedge clk) begin
VAR27 <= 0;
VAR33 <= 0;
VAR10 <= 0;
if (VAR35) begin
VAR63 <= 0;
VAR61 <= 0;
VAR52 <= 0;
VAR36 <= 0;
VAR44 <= 0;
VAR2 <= 32'h0;
VAR50 <= VAR11;
VAR9 <= 0;
VAR26 <= 0;
VAR34 <= 0;
VAR54 <= 0;
VAR46 <= 0;
VAR53 <= 0;
VAR41 <= 0;
VAR56 <= 0;
VAR29 <= 0;
VAR5 <= 0;
end
else begin
case (state)
VAR21: begin
VAR52 <= 0;
VAR36 <= 0;
VAR29 <= 0;
VAR56 <= 0;
VAR44 <= 32'h0;
VAR2 <= 32'h0;
VAR5 <= VAR19;
VAR53 <= VAR62;
if (VAR16) begin
VAR26 <= 1;
VAR34 <= 0;
VAR2 <= 0;
VAR44 <= VAR37;
if (VAR18) begin
state <= VAR48;
end
else begin
state <= VAR59;
end
end
else if (((!VAR9) & VAR23) > 0) begin
state <= VAR49;
VAR43 <= 0;
end
end
VAR48: begin
VAR27 <= 1;
if (VAR15 && VAR27) begin
VAR27 <= 0;
state <= VAR60;
end
end
VAR60: begin
VAR56 <= 1;
if (VAR65 && VAR56) begin
VAR56 <= 0;
state <= VAR69;
end
end
VAR69: begin
VAR33 <= 1;
if (VAR28)begin
VAR34 <= VAR57;
if (VAR34 != 0) begin
VAR63 <= 1;
end
state <= VAR7;
end
end
VAR59: begin
VAR10 <= 1;
if (VAR25 && VAR10) begin
VAR10 <= 0;
state <= VAR72;
end
end
VAR72: begin
VAR29 <= 1;
if (VAR47 && VAR29) begin
VAR29 <= 0;
VAR41 <= VAR31;
VAR34 <= VAR39;
state <= VAR7;
end
end
VAR7: begin
VAR54 <= 1;
if (!VAR16 && VAR54) begin
state <= VAR21;
end
end
VAR49: begin
end
default: begin
end
endcase
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o41ai/sky130_fd_sc_ms__o41ai.symbol.v
| 1,374 |
module MODULE1 (
input VAR1,
input VAR2,
input VAR8,
input VAR3,
input VAR9,
output VAR4
);
supply1 VAR10;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_asin.v
| 1,346 |
module MODULE1(VAR7, VAR13, enable, VAR2, VAR1);
input VAR7, VAR13, enable;
input [31:0] VAR2;
output [31:0] VAR1;
VAR10 VAR8(
.VAR11(VAR7),
.reset(~VAR13),
.enable(enable),
.VAR3(VAR2[31]),
.VAR9(VAR2[30:23]),
.VAR12(VAR2[22:0]),
.VAR4(VAR1[31]),
.VAR6(VAR1[30:23]),
.VAR5(VAR1[22:0])
);
endmodule
|
mit
|
jmassucco17/full_mips
|
processor/SingleCycleDatapath/Main.v
| 1,495 |
module MODULE1;
reg VAR4;
reg VAR1;
VAR2 VAR3(VAR4, VAR1);
|
mit
|
eda-globetrotter/PicenoDecoders
|
coding_theory/syn/netlist/ham_decoder.syn.v
| 4,463 |
module MODULE1 ( VAR56, VAR65 );
input [14:0] VAR56;
output [10:0] VAR65;
wire VAR40, VAR167, VAR100, VAR44, VAR179, VAR149, VAR14, VAR84, VAR174, VAR79, VAR173, VAR74, VAR172, VAR63, VAR61, VAR143,
VAR73, VAR80, VAR156, VAR8, VAR128, VAR53, VAR134, VAR3, VAR71, VAR57, VAR60, VAR124, VAR135, VAR110,
VAR108, VAR45, VAR25, VAR48, VAR144, VAR39, VAR89, VAR120, VAR46, VAR70, VAR76, VAR117, VAR165, VAR157,
VAR162, VAR121, VAR155, VAR68, VAR58, VAR164, VAR82, VAR6, VAR103, VAR77, VAR118, VAR177, VAR166, VAR145,
VAR33, VAR83, VAR66, VAR38, VAR90, VAR59, VAR43, VAR62, VAR158, VAR10, VAR170, VAR105, VAR98, VAR142,
VAR131;
VAR67 VAR19 ( .VAR159(VAR40), .VAR23(VAR167), .VAR49(VAR100), .VAR12(VAR65[9]) );
VAR54 VAR34 ( .VAR23(VAR44), .VAR159(VAR179), .VAR12(VAR100) );
VAR67 VAR29 ( .VAR159(VAR149), .VAR23(VAR167), .VAR49(VAR14), .VAR12(VAR65[8]) );
VAR54 VAR116 ( .VAR23(VAR84), .VAR159(VAR179), .VAR12(VAR14) );
VAR168 VAR28 ( .VAR23(VAR56[12]), .VAR12(VAR149) );
VAR67 VAR94 ( .VAR159(VAR174), .VAR23(VAR167), .VAR49(VAR79), .VAR12(VAR65[7]) );
VAR54 VAR2 ( .VAR23(VAR173), .VAR159(VAR74), .VAR12(VAR79) );
VAR67 VAR20 ( .VAR159(VAR172), .VAR23(VAR167), .VAR49(VAR63), .VAR12(VAR65[6]) );
VAR54 VAR136 ( .VAR23(VAR61), .VAR159(VAR74), .VAR12(VAR63) );
VAR107 VAR106 ( .VAR23(VAR143), .VAR159(VAR73), .VAR24(VAR80), .VAR12(VAR74) );
VAR67 VAR5 ( .VAR159(VAR156), .VAR23(VAR167), .VAR49(VAR8), .VAR12(VAR65[5]) );
VAR54 VAR160 ( .VAR23(VAR173), .VAR159(VAR128), .VAR12(VAR8) );
VAR67 VAR64 ( .VAR159(VAR53), .VAR23(VAR167), .VAR49(VAR134), .VAR12(VAR65[4]) );
VAR54 VAR87 ( .VAR23(VAR61), .VAR159(VAR128), .VAR12(VAR134) );
VAR9 VAR47 ( .VAR23(VAR179), .VAR159(VAR3), .VAR12(VAR128) );
VAR67 VAR26 ( .VAR159(VAR71), .VAR23(VAR167), .VAR49(VAR57), .VAR12(VAR65[3]) );
VAR54 VAR141 ( .VAR23(VAR60), .VAR159(VAR143), .VAR12(VAR57) );
VAR67 VAR75 ( .VAR159(VAR124), .VAR23(VAR167), .VAR49(VAR135), .VAR12(VAR65[2]) );
VAR54 VAR151 ( .VAR23(VAR44), .VAR159(VAR110), .VAR12(VAR135) );
VAR67 VAR91 ( .VAR159(VAR108), .VAR23(VAR167), .VAR49(VAR45), .VAR12(VAR65[1]) );
VAR54 VAR154 ( .VAR23(VAR84), .VAR159(VAR110), .VAR12(VAR45) );
VAR130 VAR163 ( .VAR23(VAR25), .VAR159(VAR48), .VAR12(VAR110) );
VAR67 VAR133 ( .VAR159(VAR144), .VAR23(VAR167), .VAR49(VAR39), .VAR12(VAR65[10]) );
VAR54 VAR152 ( .VAR23(VAR25), .VAR159(VAR60), .VAR12(VAR39) );
VAR168 VAR7 ( .VAR23(VAR56[14]), .VAR12(VAR144) );
VAR67 VAR13 ( .VAR159(VAR89), .VAR23(VAR167), .VAR49(VAR120), .VAR12(VAR65[0]) );
VAR54 VAR52 ( .VAR23(VAR46), .VAR159(VAR70), .VAR12(VAR120) );
VAR130 VAR18 ( .VAR23(VAR25), .VAR159(VAR80), .VAR12(VAR70) );
VAR130 VAR140 ( .VAR23(VAR173), .VAR159(VAR73), .VAR12(VAR46) );
VAR111 VAR93 ( .VAR23(VAR76), .VAR159(VAR179), .VAR24(VAR117), .VAR12(VAR167) );
VAR67 VAR125 ( .VAR159(VAR165), .VAR23(VAR157), .VAR49(VAR143), .VAR12(VAR117) );
VAR54 VAR31 ( .VAR23(VAR48), .VAR159(VAR162), .VAR12(VAR157) );
VAR30 VAR139 ( .VAR23(VAR121), .VAR159(VAR80), .VAR24(VAR155), .VAR85(VAR56[14]), .VAR12(VAR162) );
VAR67 VAR147 ( .VAR159(VAR174), .VAR23(VAR172), .VAR49(VAR173), .VAR12(VAR121) );
VAR168 VAR55 ( .VAR23(VAR56[10]), .VAR12(VAR172) );
VAR168 VAR97 ( .VAR23(VAR56[11]), .VAR12(VAR174) );
VAR111 VAR17 ( .VAR23(VAR89), .VAR159(VAR3), .VAR24(VAR68), .VAR12(VAR165) );
VAR30 VAR161 ( .VAR23(VAR48), .VAR159(VAR58), .VAR24(VAR164), .VAR85(VAR56[6]), .VAR12(VAR68) );
VAR168 VAR101 ( .VAR23(VAR60), .VAR12(VAR164) );
VAR130 VAR169 ( .VAR23(VAR155), .VAR159(VAR73), .VAR12(VAR60) );
VAR153 VAR113 ( .VAR23(VAR108), .VAR159(VAR84), .VAR24(VAR124), .VAR85(VAR44), .VAR12(VAR58) );
VAR168 VAR178 ( .VAR23(VAR56[5]), .VAR12(VAR124) );
VAR130 VAR16 ( .VAR23(VAR48), .VAR159(VAR143), .VAR12(VAR179) );
VAR168 VAR104 ( .VAR23(VAR25), .VAR12(VAR143) );
VAR37 VAR69 ( .VAR23(VAR82), .VAR159(VAR6), .VAR12(VAR25) );
VAR37 VAR96 ( .VAR23(VAR56[7]), .VAR159(VAR56[11]), .VAR12(VAR6) );
VAR37 VAR99 ( .VAR23(VAR103), .VAR159(VAR77), .VAR12(VAR82) );
VAR168 VAR114 ( .VAR23(VAR73), .VAR12(VAR48) );
VAR111 VAR123 ( .VAR23(VAR118), .VAR159(VAR61), .VAR24(VAR177), .VAR12(VAR73) );
VAR22 VAR4 ( .VAR23(VAR155), .VAR159(VAR56[12]), .VAR24(VAR166), .VAR12(VAR76) );
VAR153 VAR86 ( .VAR23(VAR40), .VAR159(VAR44), .VAR24(VAR3), .VAR85(VAR145), .VAR12(VAR166) );
VAR67 VAR122 ( .VAR159(VAR56[9]), .VAR23(VAR56[8]), .VAR49(VAR173), .VAR12(VAR145) );
VAR130 VAR42 ( .VAR23(VAR61), .VAR159(VAR3), .VAR12(VAR44) );
VAR168 VAR129 ( .VAR23(VAR56[13]), .VAR12(VAR40) );
VAR168 VAR137 ( .VAR23(VAR84), .VAR12(VAR155) );
VAR130 VAR32 ( .VAR23(VAR3), .VAR159(VAR173), .VAR12(VAR84) );
VAR168 VAR50 ( .VAR23(VAR61), .VAR12(VAR173) );
VAR168 VAR119 ( .VAR23(VAR80), .VAR12(VAR3) );
VAR37 VAR127 ( .VAR23(VAR33), .VAR159(VAR83), .VAR12(VAR80) );
VAR37 VAR72 ( .VAR23(VAR66), .VAR159(VAR38), .VAR12(VAR83) );
VAR37 VAR1 ( .VAR23(VAR56[14]), .VAR159(VAR56[13]), .VAR12(VAR38) );
VAR37 VAR150 ( .VAR23(VAR56[5]), .VAR159(VAR56[3]), .VAR12(VAR66) );
VAR37 VAR138 ( .VAR23(VAR90), .VAR159(VAR59), .VAR12(VAR33) );
VAR37 VAR175 ( .VAR23(VAR56[12]), .VAR159(VAR56[11]), .VAR12(VAR59) );
VAR37 VAR41 ( .VAR23(VAR177), .VAR159(VAR43), .VAR12(VAR90) );
VAR130 VAR11 ( .VAR23(VAR118), .VAR159(VAR61), .VAR12(VAR177) );
VAR37 VAR88 ( .VAR23(VAR62), .VAR159(VAR158), .VAR12(VAR61) );
VAR37 VAR132 ( .VAR23(VAR56[2]), .VAR159(VAR56[0]), .VAR12(VAR158) );
VAR102 VAR35 ( .VAR23(VAR43), .VAR159(VAR77), .VAR12(VAR62) );
VAR102 VAR126 ( .VAR23(VAR10), .VAR159(VAR170), .VAR12(VAR77) );
VAR37 VAR78 ( .VAR23(VAR53), .VAR159(VAR56[12]), .VAR12(VAR10) );
VAR168 VAR21 ( .VAR23(VAR56[8]), .VAR12(VAR53) );
VAR37 VAR27 ( .VAR23(VAR108), .VAR159(VAR71), .VAR12(VAR43) );
VAR168 VAR92 ( .VAR23(VAR56[6]), .VAR12(VAR71) );
VAR168 VAR115 ( .VAR23(VAR56[4]), .VAR12(VAR108) );
VAR37 VAR51 ( .VAR23(VAR105), .VAR159(VAR98), .VAR12(VAR118) );
VAR37 VAR95 ( .VAR23(VAR56[2]), .VAR159(VAR142), .VAR12(VAR98) );
VAR37 VAR112 ( .VAR23(VAR56[6]), .VAR159(VAR56[5]), .VAR12(VAR142) );
VAR37 VAR176 ( .VAR23(VAR103), .VAR159(VAR131), .VAR12(VAR105) );
VAR37 VAR148 ( .VAR23(VAR56[1]), .VAR159(VAR170), .VAR12(VAR131) );
VAR37 VAR15 ( .VAR23(VAR56[10]), .VAR159(VAR56[14]), .VAR12(VAR170) );
VAR37 VAR109 ( .VAR23(VAR156), .VAR159(VAR56[13]), .VAR12(VAR103) );
VAR168 VAR81 ( .VAR23(VAR56[9]), .VAR12(VAR156) );
VAR168 VAR146 ( .VAR23(VAR56[2]), .VAR12(VAR89) );
endmodule
module MODULE2 ( VAR36, VAR171 );
input [14:0] VAR36;
output [10:0] VAR171;
MODULE1 MODULE1 ( .VAR56(VAR36), .VAR65(VAR171) );
endmodule
|
mit
|
sh-chris110/chris
|
FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_sdram_p0_generic_ddio.v
| 2,314 |
module MODULE1(
VAR11,
VAR8,
VAR9,
VAR18,
VAR20
);
parameter VAR22 = 1;
localparam VAR5 = 4 * VAR22;
localparam VAR7 = VAR22;
input [VAR5-1:0] VAR11;
input VAR8;
input [VAR22-1:0] VAR18;
input [VAR22-1:0] VAR20;
output [VAR7-1:0] VAR9;
generate
genvar VAR16;
for (VAR16 = 0; VAR16 < VAR22; VAR16 = VAR16 + 1)
begin:VAR24
wire VAR1;
wire VAR13;
VAR19
.VAR10("true"),
.VAR3("true"),
.VAR21("none")
) VAR6 (
.VAR17(VAR11[VAR16 * 4]),
.VAR14(VAR11[VAR16 * 4 + 2]),
.VAR9(VAR1),
.VAR15 (VAR18[VAR16]),
.VAR26 (VAR18[VAR16]),
.VAR12(VAR8),
.VAR25 (VAR18[VAR16])
);
VAR19
.VAR10("true"),
.VAR3("true"),
.VAR21("none")
) VAR4 (
.VAR17(VAR11[VAR16 * 4 + 1]),
.VAR14(VAR11[VAR16 * 4 + 3]),
.VAR9(VAR13),
.VAR15 (VAR18[VAR16]),
.VAR26 (VAR18[VAR16]),
.VAR12(VAR8),
.VAR25 (VAR18[VAR16])
);
VAR19
.VAR21("none"),
.VAR10("false"),
.VAR23("none"),
.VAR3("true")
) VAR2 (
.VAR17(VAR1),
.VAR14(VAR13),
.VAR9(VAR9[VAR16]),
.VAR15 (VAR20[VAR16]),
.VAR26 (VAR20[VAR16]),
.VAR25 (VAR20[VAR16])
);
end
endgenerate
endmodule
|
gpl-2.0
|
DreamSourceLab/DSLogic-hdl
|
src/dso_ctl.v
| 7,020 |
module MODULE1(
input VAR29,
input VAR16,
input VAR1,
inout VAR48,
output reg VAR40,
output reg [23:0] VAR42,
output reg [23:0] VAR50,
output [7:0] VAR62,
output [7:0] VAR10,
output reg [15:0] VAR3,
input VAR18,
output VAR27
);
wire [11:0] VAR25; wire [15:0] VAR12;
wire VAR24;
wire [7:0] VAR55;
wire [7:0] VAR21;
wire [7:0] VAR45;
wire VAR8;
reg VAR13;
wire VAR49;
wire [7:0] VAR33;
wire VAR53;
wire [7:0] VAR20;
wire VAR9;
wire VAR17;
wire VAR2;
wire VAR59;
wire VAR30;
wire VAR47;
wire VAR5;
wire VAR61;
assign VAR25 = VAR64;
assign VAR12 = VAR43;
assign VAR49 = (VAR13 | VAR53) ? 1'b0 :
(~VAR24 & ~VAR53) ? 1'b1 : VAR13;
always @(posedge VAR29)
begin
if (VAR16 == 1'b1)
VAR13 <= 1'b0;
end
else
VAR13 <= VAR49;
end
VAR63 VAR63(
.clk(VAR29),
.rst(rst),
.VAR48(VAR48),
.VAR1(VAR1),
.VAR55(VAR55),
.VAR21(VAR21),
.VAR8(VAR8),
.VAR45(VAR45)
);
assign VAR17 = VAR8 & (VAR55[7:2] == 6'd0);
assign VAR2 = VAR8 & (VAR55[7:2] == 6'd1);
assign VAR59 = VAR8 & (VAR55[7:2] == 6'd2);
assign VAR30 = VAR8 & (VAR55[7:2] == 6'd3);
assign VAR47 = VAR8 & (VAR55[7:2] == 6'd4);
assign VAR5 = VAR8 & (VAR55[7:2] == 6'd5);
assign VAR61 = VAR8 & (VAR55[7:2] == 6'd6);
VAR15 VAR15 (
.clk(VAR29), .rst(VAR16), .din(VAR21), .VAR51(VAR17), .VAR58(VAR13), .dout(VAR33), .VAR39(), .VAR24(VAR24) );
VAR15 VAR32 (
.clk(VAR29), .rst(VAR16), .din(VAR20), .VAR51(VAR9), .VAR58(1'b1), .dout(), .VAR39(), .VAR24() );
VAR41 VAR44
(
.VAR56(VAR29), .reset(VAR16),
.VAR60(VAR18), .VAR28(VAR27),
.VAR20(VAR20), .VAR9(VAR9),
.VAR33(VAR33), .VAR13(VAR13), .VAR53(VAR53),
.VAR25(VAR25), .VAR12(VAR12),
.VAR22()
);
reg VAR37;
reg VAR38;
reg VAR4;
wire VAR23;
wire VAR14;
wire VAR46;
wire VAR19;
reg [23:0] VAR36;
reg [23:0] VAR35;
reg [7:0] VAR57;
reg [7:0] VAR31;
reg [15:0] VAR6;
wire [23:0] VAR26;
wire [23:0] VAR11;
wire [7:0] VAR54;
wire [7:0] VAR52;
wire [15:0] VAR34;
assign VAR26[7:0] = (VAR2 & (VAR55[1:0] == 2'b00)) ? VAR21 : VAR36[7:0];
assign VAR26[15:8] = (VAR2 & (VAR55[1:0] == 2'b01)) ? VAR21 : VAR36[15:8];
assign VAR26[23:16] = (VAR2 & (VAR55[1:0] == 2'b10)) ? VAR21 : VAR36[23:16];
assign VAR11[7:0] = (VAR59 & (VAR55[1:0] == 2'b00)) ? VAR21 : VAR35[7:0];
assign VAR11[15:8] = (VAR59 & (VAR55[1:0] == 2'b01)) ? VAR21 : VAR35[15:8];
assign VAR11[23:16] = (VAR59 & (VAR55[1:0] == 2'b10)) ? VAR21 : VAR35[23:16];
assign VAR54[7:0] = (VAR30 & (VAR55[1:0] == 2'b00)) ? VAR21 : VAR57;
assign VAR52[7:0] = (VAR47 & (VAR55[1:0] == 2'b00)) ? VAR21 : VAR31;
assign VAR34[7:0] = (VAR5 & (VAR55[1:0] == 2'b00)) ? VAR21 : VAR6[7:0];
assign VAR34[15:8] = (VAR5 & (VAR55[1:0] == 2'b01)) ? VAR21 : VAR6[15:8];
assign VAR23 = (VAR2 & (VAR55[1:0] == 2'b10));
assign VAR14 = (VAR59 & (VAR55[1:0] == 2'b10));
assign VAR46 = (VAR5 & (VAR55[1:0] == 2'b01));
assign VAR19 = (VAR61 & (VAR55[1:0] == 2'b10));
always @(posedge VAR29)
begin
VAR36 <= VAR7 VAR26;
VAR35 <= VAR7 VAR11;
VAR57 <= VAR7 VAR54;
VAR31 <= VAR7 VAR52;
VAR6 <= VAR7 VAR34;
VAR37 <= VAR7 VAR23;
VAR38 <= VAR7 VAR14;
VAR4 <= VAR7 VAR46;
VAR40 <= VAR7 VAR19;
VAR50 <= VAR7 VAR38 ? VAR35 : VAR50;
VAR42 <= VAR7 VAR37 ? VAR36 : VAR42;
VAR3 <= VAR7 VAR4 ? VAR6 : VAR3;
end
assign VAR62 = VAR57;
assign VAR10 = VAR31;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/and3b/sky130_fd_sc_hs__and3b_4.v
| 2,091 |
module MODULE2 (
VAR7 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR6,
VAR5
);
output VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR5;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR8,
VAR4 ,
VAR3
);
output VAR7 ;
input VAR8;
input VAR4 ;
input VAR3 ;
supply1 VAR6;
supply0 VAR5;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.pp.symbol.v
| 1,540 |
module MODULE1 (
input VAR4 ,
output VAR3 ,
output VAR1 ,
input VAR2,
input VAR9 ,
input VAR10 ,
input VAR5 ,
input VAR7 ,
input VAR8 ,
input VAR6
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.symbol.v
| 1,457 |
module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR2,
input VAR9 ,
input VAR8 ,
input VAR1
);
supply1 VAR10;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/a21oi/sky130_fd_sc_hvl__a21oi.symbol.v
| 1,353 |
module MODULE1 (
input VAR6,
input VAR1,
input VAR4,
output VAR8
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.behavioral.v
| 1,098 |
module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR2 VAR4(.VAR3(VAR3),.VAR5(VAR5));
VAR2 VAR1(.VAR3(VAR3),.VAR5(VAR5));
|
apache-2.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v
| 12,347 |
module MODULE3 (
clk,
reset,
VAR101,
VAR4,
VAR76,
VAR92,
VAR3
);
parameter VAR24 = 18;
parameter VAR15 = 15;
parameter VAR13 = 8;
localparam VAR61 = 16;
input clk;
input reset;
input VAR101;
input VAR4;
input [VAR24-1:0] VAR76; output VAR92;
output [VAR24-1:0] VAR3;
localparam VAR27 = 18; localparam VAR36 = 36; localparam VAR29 = 17;
localparam VAR22 = 15;
reg [VAR24-1:0] VAR2;
reg [VAR24-1:0] VAR75;
reg [VAR24-1:0] VAR91;
reg [VAR24-1:0] VAR79;
reg [VAR24-1:0] VAR53;
reg [VAR24-1:0] VAR28;
reg [VAR24-1:0] VAR85;
reg [VAR24-1:0] VAR34;
always@(posedge clk) begin
VAR2 <= 18'd88;
VAR75 <= 18'd0;
VAR91 <= -18'd97;
VAR79 <= -18'd197;
VAR53 <= -18'd294;
VAR28 <= -18'd380;
VAR85 <= -18'd447;
VAR34 <= -18'd490;
end
reg [VAR61-1:0] VAR46;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR46 <= 0;
end else begin
if(VAR101) begin
VAR46 <= {VAR46[VAR61-2:0], VAR4};
end else begin
VAR46 <= VAR46;
end
end
end
wire [VAR24-1:0] VAR21;
wire [VAR24-1:0] VAR9;
wire [VAR24-1:0] VAR1;
wire [VAR24-1:0] VAR10;
wire [VAR24-1:0] VAR82;
wire [VAR24-1:0] VAR40;
wire [VAR24-1:0] VAR25;
wire [VAR24-1:0] VAR78;
wire [VAR24-1:0] VAR71;
wire [VAR24-1:0] VAR45;
wire [VAR24-1:0] VAR67;
wire [VAR24-1:0] VAR87;
wire [VAR24-1:0] VAR31;
wire [VAR24-1:0] VAR98;
wire [VAR24-1:0] VAR47;
MODULE4 MODULE18(
.clk(clk), .VAR101(VAR101),
.VAR32(VAR76),
.VAR94(VAR21),
.VAR65(VAR9),
.VAR7(VAR1),
.VAR72(VAR10),
.VAR26(VAR82),
.VAR11(VAR40),
.VAR20(VAR25),
.VAR74(VAR78),
.VAR43(VAR71),
.VAR56(VAR45),
.VAR95(VAR67),
.VAR51(VAR87),
.VAR60(VAR31),
.VAR103(VAR98),
.VAR17(VAR47),
.reset(reset) );
wire [VAR24-1:0] VAR62;
wire [VAR24-1:0] VAR86;
wire [VAR24-1:0] VAR58;
wire [VAR24-1:0] VAR37;
wire [VAR24-1:0] VAR16;
wire [VAR24-1:0] VAR12;
wire [VAR24-1:0] VAR48;
wire [VAR24-1:0] VAR97;
MODULE2 VAR93(
.VAR66 (VAR21),
.VAR6 (VAR47),
.VAR89(VAR62)
);
MODULE2 VAR69(
.VAR66 (VAR9),
.VAR6 (VAR98),
.VAR89(VAR86)
);
MODULE2 VAR90(
.VAR66 (VAR1),
.VAR6 (VAR31),
.VAR89(VAR58)
);
MODULE2 VAR81(
.VAR66 (VAR10),
.VAR6 (VAR87),
.VAR89(VAR37)
);
MODULE2 VAR59(
.VAR66 (VAR82),
.VAR6 (VAR67),
.VAR89(VAR16)
);
MODULE2 VAR52(
.VAR66 (VAR40),
.VAR6 (VAR45),
.VAR89(VAR12)
);
MODULE2 VAR5(
.VAR66 (VAR25),
.VAR6 (VAR71),
.VAR89(VAR48)
);
MODULE1 VAR70(
.VAR66 (VAR78),
.VAR89(VAR97)
);
wire [VAR24-1:0] VAR30;
wire [VAR24-1:0] VAR19;
wire [VAR24-1:0] VAR88;
wire [VAR24-1:0] VAR57;
wire [VAR24-1:0] VAR83;
wire [VAR24-1:0] VAR99;
wire [VAR24-1:0] VAR23;
wire [VAR24-1:0] VAR77;
MODULE5 VAR54(
.VAR66 (VAR62),
.VAR6 (VAR2),
.VAR89(VAR30)
);
MODULE5 VAR42(
.VAR66 (VAR86),
.VAR6 (VAR75),
.VAR89(VAR19)
);
MODULE5 VAR73(
.VAR66 (VAR58),
.VAR6 (VAR91),
.VAR89(VAR88)
);
MODULE5 VAR18(
.VAR66 (VAR37),
.VAR6 (VAR79),
.VAR89(VAR57)
);
MODULE5 VAR44(
.VAR66 (VAR16),
.VAR6 (VAR53),
.VAR89(VAR83)
);
MODULE5 VAR55(
.VAR66 (VAR12),
.VAR6 (VAR28),
.VAR89(VAR99)
);
MODULE5 VAR64(
.VAR66 (VAR48),
.VAR6 (VAR85),
.VAR89(VAR23)
);
MODULE5 VAR102(
.VAR66 (VAR97),
.VAR6 (VAR34),
.VAR89(VAR77)
);
wire [VAR24-1:0] VAR50;
wire [VAR24-1:0] VAR68;
wire [VAR24-1:0] VAR33;
wire [VAR24-1:0] VAR35;
MODULE2 VAR49(
.VAR66 (VAR30),
.VAR6 (VAR19),
.VAR89(VAR50)
);
MODULE2 VAR96(
.VAR66 (VAR88),
.VAR6 (VAR57),
.VAR89(VAR68)
);
MODULE2 VAR41(
.VAR66 (VAR83),
.VAR6 (VAR99),
.VAR89(VAR33)
);
MODULE2 VAR38(
.VAR66 (VAR23),
.VAR6 (VAR77),
.VAR89(VAR35)
);
wire [VAR24-1:0] VAR84;
wire [VAR24-1:0] VAR100;
MODULE2 VAR39(
.VAR66 (VAR50),
.VAR6 (VAR68),
.VAR89(VAR84)
);
MODULE2 VAR14(
.VAR66 (VAR33),
.VAR6 (VAR35),
.VAR89(VAR100)
);
wire [VAR24-1:0] VAR80;
MODULE2 VAR63(
.VAR66 (VAR84),
.VAR6 (VAR100),
.VAR89(VAR80)
);
reg [17:0] VAR3;
always @(posedge clk) begin
if(VAR101) begin
VAR3 <= VAR80;
end
end
assign VAR92 = VAR46[VAR61-1];
endmodule
module MODULE4 (
clk,
VAR101,
VAR32,
VAR94,
VAR65,
VAR7,
VAR72,
VAR26,
VAR11,
VAR20,
VAR74,
VAR43,
VAR56,
VAR95,
VAR51,
VAR60,
VAR103,
VAR17,
reset);
parameter VAR8 = 1;
input clk;
input VAR101;
input [VAR8-1:0] VAR32;
output [VAR8-1:0] VAR94;
output [VAR8-1:0] VAR65;
output [VAR8-1:0] VAR7;
output [VAR8-1:0] VAR72;
output [VAR8-1:0] VAR26;
output [VAR8-1:0] VAR11;
output [VAR8-1:0] VAR20;
output [VAR8-1:0] VAR74;
output [VAR8-1:0] VAR43;
output [VAR8-1:0] VAR56;
output [VAR8-1:0] VAR95;
output [VAR8-1:0] VAR51;
output [VAR8-1:0] VAR60;
output [VAR8-1:0] VAR103;
output [VAR8-1:0] VAR17;
reg [VAR8-1:0] VAR94;
reg [VAR8-1:0] VAR65;
reg [VAR8-1:0] VAR7;
reg [VAR8-1:0] VAR72;
reg [VAR8-1:0] VAR26;
reg [VAR8-1:0] VAR11;
reg [VAR8-1:0] VAR20;
reg [VAR8-1:0] VAR74;
reg [VAR8-1:0] VAR43;
reg [VAR8-1:0] VAR56;
reg [VAR8-1:0] VAR95;
reg [VAR8-1:0] VAR51;
reg [VAR8-1:0] VAR60;
reg [VAR8-1:0] VAR103;
reg [VAR8-1:0] VAR17;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR94 <= 0;
VAR65 <= 0;
VAR7 <= 0;
VAR72 <= 0;
VAR26 <= 0;
VAR11 <= 0;
VAR20 <= 0;
VAR74 <= 0;
VAR43 <= 0;
VAR56 <= 0;
VAR95 <= 0;
VAR51 <= 0;
VAR60 <= 0;
VAR103 <= 0;
VAR17 <= 0;
end else begin
if(VAR101) begin
VAR94 <= VAR32;
VAR65 <= VAR94;
VAR7 <= VAR65;
VAR72 <= VAR7;
VAR26 <= VAR72;
VAR11 <= VAR26;
VAR20 <= VAR11;
VAR74 <= VAR20;
VAR43 <= VAR74;
VAR56 <= VAR43;
VAR95 <= VAR56;
VAR51 <= VAR95;
VAR60 <= VAR51;
VAR103 <= VAR60;
VAR17 <= VAR103;
end end
end
endmodule
module MODULE2 (
VAR66,
VAR6,
VAR89);
input clk;
input VAR101;
input [17:0] VAR66;
input [17:0] VAR6;
output [17:0] VAR89;
assign VAR89 = VAR66 + VAR6;
endmodule
module MODULE5 (
VAR66,
VAR6,
VAR89);
input clk;
input VAR101;
input [17:0] VAR66;
input [17:0] VAR6;
output [17:0] VAR89;
assign VAR89 = VAR66 * VAR6;
endmodule
module MODULE1 (
VAR66,
VAR89);
input clk;
input VAR101;
input [17:0] VAR66;
output [17:0] VAR89;
assign VAR89 = VAR66;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dfsbp/sky130_fd_sc_hd__dfsbp.behavioral.pp.v
| 2,300 |
module MODULE1 (
VAR8 ,
VAR4 ,
VAR17 ,
VAR2 ,
VAR12,
VAR16 ,
VAR21 ,
VAR19 ,
VAR23
);
output VAR8 ;
output VAR4 ;
input VAR17 ;
input VAR2 ;
input VAR12;
input VAR16 ;
input VAR21 ;
input VAR19 ;
input VAR23 ;
wire VAR3 ;
wire VAR5 ;
reg VAR10 ;
wire VAR6 ;
wire VAR14;
wire VAR1 ;
wire VAR13 ;
wire VAR20 ;
wire VAR22 ;
not VAR15 (VAR5 , VAR14 );
VAR9 VAR18 (VAR3 , VAR6, VAR1, VAR5, VAR10, VAR16, VAR21);
assign VAR13 = ( VAR16 === 1'b1 );
assign VAR20 = ( VAR14 === 1'b1 );
assign VAR22 = ( VAR12 === 1'b1 );
buf VAR11 (VAR8 , VAR3 );
not VAR7 (VAR4 , VAR3 );
endmodule
|
apache-2.0
|
olofk/oh
|
elink/hdl/ereset.v
| 2,141 |
module MODULE1 (
VAR4, VAR7, VAR1,
reset, VAR6, VAR3, VAR12
);
input reset;
input VAR6; input VAR3; input VAR12;
output VAR4; output VAR7; output VAR1;
wire VAR5;
wire VAR8;
wire VAR9;
VAR11 VAR10 (.out (VAR8),
.in (1'b1),
.clk (VAR3),
.reset (reset)
);
VAR11 VAR2 (.out (VAR9),
.in (1'b1),
.clk (VAR6),
.reset (reset)
);
assign VAR4 =~VAR8;
assign VAR1 =~VAR9;
assign VAR7 = reset;
endmodule
|
gpl-3.0
|
andres-erbsen/sha3-verilog-mirror
|
low_throughput_core/rtl/rconst.v
| 1,542 |
module MODULE1(VAR2, VAR1);
input [23:0] VAR2;
output reg [63:0] VAR1;
always @ (VAR2)
begin
VAR1 = 0;
VAR1[0] = VAR2[0] | VAR2[4] | VAR2[5] | VAR2[6] | VAR2[7] | VAR2[10] | VAR2[12] | VAR2[13] | VAR2[14] | VAR2[15] | VAR2[20] | VAR2[22];
VAR1[1] = VAR2[1] | VAR2[2] | VAR2[4] | VAR2[8] | VAR2[11] | VAR2[12] | VAR2[13] | VAR2[15] | VAR2[16] | VAR2[18] | VAR2[19];
VAR1[3] = VAR2[2] | VAR2[4] | VAR2[7] | VAR2[8] | VAR2[9] | VAR2[10] | VAR2[11] | VAR2[12] | VAR2[13] | VAR2[14] | VAR2[18] | VAR2[19] | VAR2[23];
VAR1[7] = VAR2[1] | VAR2[2] | VAR2[4] | VAR2[6] | VAR2[8] | VAR2[9] | VAR2[12] | VAR2[13] | VAR2[14] | VAR2[17] | VAR2[20] | VAR2[21];
VAR1[15] = VAR2[1] | VAR2[2] | VAR2[3] | VAR2[4] | VAR2[6] | VAR2[7] | VAR2[10] | VAR2[12] | VAR2[14] | VAR2[15] | VAR2[16] | VAR2[18] | VAR2[20] | VAR2[21] | VAR2[23];
VAR1[31] = VAR2[3] | VAR2[5] | VAR2[6] | VAR2[10] | VAR2[11] | VAR2[12] | VAR2[19] | VAR2[20] | VAR2[22] | VAR2[23];
VAR1[63] = VAR2[2] | VAR2[3] | VAR2[6] | VAR2[7] | VAR2[13] | VAR2[14] | VAR2[15] | VAR2[16] | VAR2[17] | VAR2[19] | VAR2[20] | VAR2[21] | VAR2[23];
end
endmodule
|
apache-2.0
|
fredchen00/MDA-Software
|
fpga/fpga_hw/top_level/motor_controller/slave_controller.v
| 1,831 |
module MODULE1(input clk, input VAR8, input write, input [3:0]addr, input [31:0] VAR1, output [23:0] VAR4);
reg [11:0] in = 12'd0;
reg [6*VAR6-1:0] VAR3 = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (VAR8 & write)
casex (addr)
4'b0000:
in[1:0] <= VAR1[1:0];
4'b0001:
in[3:2] <= VAR1[1:0];
4'b0010:
in[5:4] <= VAR1[1:0];
4'b0011:
in[7:6] <= VAR1[1:0];
4'b0100:
in[9:8] <= VAR1[1:0];
4'b0101:
in[11:10] <= VAR1[1:0];
4'b1000:
VAR3[VAR6-1:0] <= VAR1[VAR6-1:0];
4'b1001:
VAR3[2*VAR6-1:VAR6] <= VAR1[VAR6-1:0];
4'b1010:
VAR3[3*VAR6-1:2*VAR6] <= VAR1[VAR6-1:0];
4'b1011:
VAR3[4*VAR6-1:3*VAR6] <= VAR1[VAR6-1:0];
4'b1100:
VAR3[5*VAR6-1:4*VAR6] <= VAR1[VAR6:0];
4'b1101:
VAR3[6*VAR6-1:5*VAR6] <= VAR1[VAR6:0];
4'b1110:
period <= VAR1[15:0];
default:
; endcase
generate
genvar VAR2;
for (VAR2=0; VAR2<6; VAR2=VAR2+1)
begin : VAR7
VAR9 VAR5(clk, in[VAR2*2 + 1], in[VAR2*2], period, VAR3[(VAR2+1)*VAR6-1:VAR2*VAR6], VAR4[VAR2*4+3:VAR2*4]);
end
endgenerate
endmodule
|
apache-2.0
|
antmicro/yosys
|
techlibs/nexus/lrams_map.v
| 1,161 |
module \VAR24 (VAR11, VAR15, VAR1, VAR14, VAR23, VAR30, VAR22);
parameter VAR8 = 14;
parameter VAR10 = 32;
parameter VAR3 = 4;
parameter VAR20 = 1;
parameter [524287:0] VAR9 = 524287'b0;
input VAR11;
input [VAR8-1:0] VAR15;
input [VAR10-1:0] VAR1;
input [VAR3-1:0] VAR14;
input [VAR8-1:0] VAR23;
output [VAR10-1:0] VAR30;
input VAR22;
wire clk;
wire [31:0] rd;
assign VAR30 = rd[VAR10-1:0];
generate
if (VAR20)
assign clk = VAR11;
else
VAR29 VAR38 (.VAR40(VAR11), .VAR39(clk));
endgenerate
wire VAR37 = |VAR14;
localparam VAR34 = 4096;
function [5119:0] VAR32;
input [VAR34-1:0] VAR4;
integer VAR25;
begin
for (VAR25 = 0; VAR25 < 128; VAR25 = VAR25 + 1'b1)
VAR32[VAR25 * 40 +: 40] = {8'b0, VAR4[VAR25 * 32 +: 32]};
end
endfunction
generate
VAR13 #(
.VAR19("VAR16"),
.VAR17("VAR31"),
.VAR18("VAR41")
) VAR28 (
.VAR35(clk), .VAR12(1'b0),
.VAR27(VAR1), .VAR6(VAR15), .VAR21(VAR37), .VAR5(VAR37), .VAR2(1'b1),
.VAR7(VAR23), .VAR26(rd), .VAR33(VAR22), .VAR36(1'b1),
);
endgenerate
endmodule
|
isc
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.behavioral.v
| 1,262 |
module MODULE1( VAR6, VAR4, VAR1, VAR5 );
input VAR5, VAR1, VAR6;
output VAR4;
VAR7 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5));
VAR7 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5));
|
apache-2.0
|
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/clk_wiz_v3_3.v
| 6,923 |
module MODULE1
( input VAR24,
output VAR28,
input VAR38,
output VAR8
);
VAR53 VAR73
(.VAR33 (VAR15),
.VAR19 (VAR24));
wire [15:0] VAR16;
wire VAR78;
wire VAR1;
wire VAR21;
wire VAR59;
wire VAR49;
wire VAR61;
wire VAR40;
wire VAR37;
wire VAR50;
wire VAR5;
wire VAR55;
wire VAR10;
wire VAR22;
wire VAR45;
wire VAR42;
wire VAR69;
wire VAR46;
VAR75
.VAR74 ("VAR36"),
.VAR7 ("VAR36"),
.VAR64 ("VAR43"),
.VAR23 ("VAR36"),
.VAR31 (1),
.VAR17 (40.000),
.VAR56 (0.000),
.VAR11 ("VAR36"),
.VAR63 (5.000),
.VAR26 (0.000),
.VAR4 (0.500),
.VAR60 ("VAR36"),
.VAR48 (40.000),
.VAR35 (0.010))
VAR12
(.VAR30 (VAR21),
.VAR77 (VAR49),
.VAR79 (VAR41),
.VAR6 (VAR61),
.VAR28 (VAR40),
.VAR27 (VAR37),
.VAR71 (VAR50),
.VAR18 (VAR5),
.VAR58 (VAR55),
.VAR47 (VAR10),
.VAR62 (VAR22),
.VAR14 (VAR45),
.VAR44 (VAR42),
.VAR52 (VAR59),
.VAR24 (VAR15),
.VAR68 (1'b0),
.VAR34 (1'b1),
.VAR9 (7'h0),
.VAR76 (1'b0),
.VAR2 (1'b0),
.VAR51 (16'h0),
.VAR3 (VAR16),
.VAR54 (VAR78),
.VAR39 (1'b0),
.VAR57 (1'b0),
.VAR32 (1'b0),
.VAR29 (1'b0),
.VAR65 (VAR1),
.VAR8 (VAR8),
.VAR66 (VAR46),
.VAR20 (VAR69),
.VAR67 (1'b0),
.VAR70 (VAR38));
VAR72 VAR25
(.VAR33 (VAR59),
.VAR19 (VAR21));
VAR72 VAR13
(.VAR33 (VAR28),
.VAR19 (VAR41));
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/or4bb/sky130_fd_sc_ms__or4bb.blackbox.v
| 1,326 |
module MODULE1 (
VAR7 ,
VAR3 ,
VAR1 ,
VAR5,
VAR6
);
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR5;
input VAR6;
supply1 VAR2;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
Elphel/x353
|
sensor/sensor_phase353.v
| 24,337 |
module MODULE1 #(
parameter VAR170 = "VAR100",
parameter VAR184 = "0",
parameter VAR147 = "0"
)(
VAR84, VAR129, VAR8, VAR189, VAR10, VAR107, VAR104, VAR36, VAR13, VAR81, VAR167, VAR123, VAR73, VAR96, VAR64, VAR162, VAR2, VAR191, VAR101, VAR199, VAR26, VAR83);
parameter VAR3=130; VAR139 VAR21
parameter VAR120=1;
parameter VAR120=0;
input VAR84; input VAR129; input [5:0] VAR8; input VAR189; input VAR10; input [11:0] VAR107; input [1:0] VAR104; input [13:0] VAR36; input VAR13; input VAR81; input VAR167;
input VAR123; input VAR73;
input VAR96; input VAR64; output VAR162; input VAR2; output VAR191; output [13:0] VAR101; output VAR199; output [7:0] VAR26; output VAR83;
wire VAR63;
reg [2:0] VAR142;
reg VAR135;
reg VAR95;
reg VAR199;
wire VAR39; reg VAR75;
reg [2:0] VAR12;
reg [1:0] VAR106;
reg [2:0] VAR74;
wire VAR83;
wire VAR126,VAR58,VAR71;
wire VAR93;
reg VAR20;
wire VAR161, VAR46;
reg VAR38;
reg VAR30;
reg VAR70;
wire [7:0] VAR26;
wire VAR137;
VAR141 VAR65(.VAR59(VAR63), .VAR85((VAR129 && (VAR8[1:0] == 2'b11)) || (VAR63 && !VAR142[2])), .VAR157(VAR84)) ;
always @ (posedge VAR84) begin
VAR12[2:0] <= {VAR12[1] & ~VAR12[0], VAR12[0], VAR75}; VAR135 <= VAR129 && (VAR8[1]!=VAR8[0]);
VAR95 <= VAR129 && VAR8[0];
if (VAR129) begin
if (VAR8[2] && VAR8[3]) VAR106[1:0] <= 2'h0;
end
else if (VAR8[2]) VAR106[1:0] <= VAR106[1:0] +1;
end
else if (VAR8[3]) VAR106[1:0] <= VAR106[1:0] -1;
end
if (VAR129) begin
if (VAR8[4] && VAR8[5]) VAR74[2:0] <= 3'h0;
end
else if (VAR8[4]) VAR74[2:0] <= VAR74[2:0] +1;
else if (VAR8[5]) VAR74[2:0] <= VAR74[2:0] -1;
end
end
always @ (posedge VAR96) begin
VAR142[2:0] <= VAR142[2]? 3'b0:{VAR142[1], VAR142[0], VAR63};
VAR75 <= VAR142[0] || VAR142[1] || VAR142[2] ;
end
always @ (posedge VAR84)
if (VAR129 && |VAR8[2:0]) VAR199 <=1'b0;
else if (VAR39 || VAR12[2]) VAR199 <=1'b1;
always @ (posedge VAR93) begin
VAR30 <= VAR106[0]; VAR70 <= VAR106[1]; VAR38 <=VAR30?VAR46:VAR161; VAR20 <= VAR38 ^ VAR70;
end
VAR80 VAR22 (.VAR35(VAR93), .VAR24(VAR58), .VAR153(VAR71), .VAR105(VAR30));
VAR140 #(
.VAR152("VAR88"), .VAR109(10.0), .VAR103("VAR119"), .VAR132("1X"), .VAR177("VAR117"), .VAR155("VAR185"), .VAR6("VAR51"), .VAR15(0), .VAR158("VAR88") ) VAR82(
.VAR197 (VAR96),
.VAR61 (VAR126),
.VAR148 (VAR75),
.VAR181 (VAR135),
.VAR201 (VAR95),
.VAR163 (VAR84),
.VAR166 (1'b0),
.VAR56 (VAR126),
.VAR175 (VAR161), .VAR143 (VAR46), .VAR188 (),
.VAR186 (),
.VAR4 (VAR58),
.VAR1 (VAR71),
.VAR92 (),
.VAR25 (),
.VAR57 (VAR26[7:0]),
.VAR198 (VAR83),
.VAR116 (VAR39));
reg [1:0] VAR131; reg [3:0] VAR194; reg VAR183; always @ (posedge VAR64) begin
VAR131[1:0] <= {VAR131[0],VAR83};
if (!VAR131[1]) VAR183 <= 1'b0;
end
else if (VAR194[3:0]==4'h0) VAR183 <= 1'b1;
if (!VAR131[1]) VAR194[3:0] <= 4'hf;
else if (!VAR183) VAR194[3:0] <= VAR194[3:0]-1;
end
wire [11:0] VAR114;
reg [13:0] VAR89;
wire VAR150, VAR200;
reg VAR169,VAR45;
wire VAR94;
reg [2:1] VAR68;
reg [3:0] VAR190;
reg [3:0] VAR72;
reg [3:0] VAR115;
reg [3:0] VAR69;
reg VAR136; reg VAR179; reg VAR34; reg VAR121; reg [1:0] VAR7;
reg VAR149;
reg [1:0] VAR31;
reg VAR5;
wire VAR67;
wire VAR44;
reg [2:0] VAR195;
reg VAR171;
reg VAR16;
reg VAR159;
reg VAR191,VAR162;
reg [13:0] VAR101;
wire[13:0] VAR130;
wire VAR76;
wire VAR77; reg VAR168;
wire VAR79,VAR37;
reg [13:0] VAR54;
reg VAR174;
reg [13:0] VAR40;
reg VAR47; reg VAR48; reg VAR122;
assign VAR67=VAR68[1] && (VAR94 || VAR68[2]); assign VAR44=VAR68[1] && !VAR94 && !VAR68[2]; wire VAR66= VAR10 || VAR189;
reg VAR146;
always @ (negedge VAR62.VAR124 or posedge VAR66) begin
if (VAR66) VAR146 <= 1'b0;
end
else VAR146 <= 1'b1;
end
assign VAR137=VAR62.VAR124 || VAR146;
wire VAR192,VAR41;
VAR33 #(
.VAR29 (VAR170),
.VAR110 (VAR147),
.VAR49 (VAR184)
) VAR79 (.VAR178(VAR189), .VAR35(VAR79));
VAR33 #(
.VAR29 (VAR170),
.VAR110 (VAR147),
.VAR49 (VAR184)
) VAR37 (.VAR178(VAR10), .VAR35(VAR37));
always @ (posedge VAR93) begin
VAR169 <= VAR192;
VAR45 <= VAR41;
VAR72[3:0]<={VAR72[2:0],VAR150};
VAR190[3:0]<={VAR190[2:0],VAR169};
VAR69[3:0]<={VAR69[2:0],VAR200};
VAR115[3:0]<={VAR115[2:0],VAR45};
end
always @ (posedge VAR93) if (VAR20) begin
{VAR179,VAR136} <= VAR195[2]?
(VAR195[1]?
(VAR195[0]?{VAR115[2],VAR190[2]}:{VAR69[3],VAR72[3]}):
(VAR195[0]?{VAR115[3],VAR190[3]}:{VAR69[0],VAR72[0]})):
(VAR195[1]?
(VAR195[0]?{VAR115[0],VAR190[0]}:{VAR69[1],VAR72[1]}):
(VAR195[0]?{VAR115[1],VAR190[1]}:{VAR69[2],VAR72[2]}));
end
VAR127 VAR133 (.VAR182(VAR150),.VAR154(VAR192),.VAR32(VAR93),.VAR108(!VAR93),.VAR27(1'b1), .VAR85(VAR79), .VAR145(1'b0), .VAR105(1'b0) );
VAR127 VAR165 (.VAR182(VAR200),.VAR154(VAR41),.VAR32(VAR93),.VAR108(!VAR93),.VAR27(1'b1), .VAR85(VAR37), .VAR145(1'b0), .VAR105(1'b0) );
VAR134 VAR138 (.VAR59(VAR94), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR73));
VAR134 VAR112 (.VAR59(VAR114[ 0]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 0]));
VAR134 VAR111 (.VAR59(VAR114[ 1]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 1]));
VAR134 VAR11 (.VAR59(VAR114[ 2]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 2]));
VAR134 VAR50 (.VAR59(VAR114[ 3]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 3]));
VAR134 VAR160 (.VAR59(VAR114[ 4]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 4]));
VAR134 VAR91 (.VAR59(VAR114[ 5]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 5]));
VAR134 VAR144 (.VAR59(VAR114[ 6]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 6]));
VAR134 VAR9 (.VAR59(VAR114[ 7]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 7]));
VAR134 VAR97 (.VAR59(VAR114[ 8]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 8]));
VAR134 VAR99 (.VAR59(VAR114[ 9]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[ 9]));
VAR134 VAR43 (.VAR59(VAR114[10]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[10]));
VAR134 VAR156 (.VAR59(VAR114[11]), .VAR157(VAR93),.VAR27(VAR20),.VAR118(1'b0),.VAR85(VAR107[11]));
reg [1:0] VAR14; always @ (posedge VAR93) if (VAR20) begin
VAR89[13:4] <= VAR114[11:2];
VAR89[ 3:2] <= (VAR16 || VAR159)? VAR114[1:0]:2'h0;
VAR89[ 1:0] <= VAR159? {VAR69[0],VAR72[0]}:2'h0;
VAR68[2:1]<={VAR68[1], VAR94 & VAR171}; VAR195[2:0] <= VAR74[2:0];
VAR159 <= VAR167;
VAR16 <= VAR81;
if ((!VAR72[0]) && VAR14[1]) VAR48 <= VAR13;
VAR171 <= VAR123;
VAR34 <= VAR171? VAR67 : VAR136;
VAR121 <= VAR171? VAR44 : VAR179;
VAR7[1:0]<={VAR7[0], VAR34 && VAR48 };
VAR149 <= (VAR34 && !VAR7[0]) ||
(VAR7[0] && !VAR7[1]);
VAR31[1:0]<={VAR31[0],VAR121};
VAR5 <= (VAR104[0] || !VAR34 && !VAR7[0] && !VAR7[1]) && ((VAR121 && !VAR31[0]) ||
(VAR31[0] && !VAR31[1]));
end
reg [3:0] VAR19;
reg [3:0] VAR164;
reg [3:0] VAR193;
reg VAR173;
wire VAR187;
reg VAR172;
reg VAR151;
reg [2:0] VAR87;
assign VAR187= VAR151 || (VAR120 && VAR137) ;
always @ (posedge VAR93) if (VAR20) begin
if (VAR120 && VAR137) VAR19[3:0] <= 4'h0;
end
else VAR19[3:0] <= VAR19[3:0] + 1;
if (VAR120 && VAR137) VAR164[3:0] <= 4'hc;
else VAR164[3:0] <= VAR19[3:0] - 3; if (VAR173) VAR193[3:0] <= VAR19[3:0] - 4'h6; end
always @ (posedge VAR93 or posedge VAR187) begin
if (VAR187) VAR172 <= 1'b0;
end
else if (VAR173 && VAR20) VAR172 <= 1'b1;
end
reg [3:0] VAR196;
always @ (posedge VAR64) begin
VAR87[2:0]<={VAR87[1:0], VAR172};
VAR151<=VAR87[1] && ! VAR87[2];
if (VAR151 && VAR183) VAR196[3:0] <= VAR193[3:0];
end
else VAR196[3:0] <= VAR196[3:0]+1;
end
reg VAR42;
reg VAR23;
reg [2:0] VAR180;
wire VAR52;
assign VAR52= VAR23 || (VAR120 && VAR137) ;
always @ (posedge VAR64 or posedge VAR52) begin
if (VAR52) VAR42 <= 1'b0;
end
else if ( VAR151) VAR42 <= 1'b1;
end
reg VAR125;
always @ (posedge VAR93) if (VAR20) begin
VAR14[1:0]<={VAR14[0], ~VAR162}; VAR180[2:0]<={VAR180[1:0], VAR42};
VAR23<=VAR180[1] && ! VAR180[2];
VAR125 <= !(VAR120 && VAR137) && !VAR34 && VAR14[1] && (VAR173 || (VAR125 && !VAR23));
VAR173 <= (VAR120 && VAR137) || (!VAR34 && VAR14[1] && !VAR125 && !VAR173);
end
wire VAR60;
VAR17 #( .VAR98(2),.VAR55(4))
VAR128(.VAR85({VAR5,VAR149}),
.VAR18(VAR20),
.clk(VAR93),
.VAR90(VAR164[3:0]),
.VAR102(VAR196[3:0]),
.VAR28(),
.VAR176({VAR60,VAR76}));
VAR17 #( .VAR98(14),.VAR55(4))
VAR113(.VAR85(VAR89[13:0]),
.VAR18(VAR20),
.clk(VAR93),
.VAR90(VAR19[3:0]),
.VAR102(VAR196[3:0]),
.VAR28(),
.VAR176(VAR130[13:0]));
reg VAR78;
assign VAR77= (VAR104[1]?VAR78:VAR60) && (!(VAR120 && VAR137));
reg [7:0] VAR53=8'h80;
reg VAR86;
always @ (posedge VAR64) begin
VAR78<=VAR5;
VAR40[13:0] <= VAR36[13:0];
VAR47 <= VAR48;
VAR174 <= VAR76;
if (VAR120 && VAR137) VAR162 <= 1'b0;
end
else if (VAR76 && !VAR174) VAR162 <= 1'b1;
else if (VAR47?VAR122:(!VAR76)) VAR162 <= 1'b0;
if (!VAR162) VAR54[13:0] <= VAR40[13:0];
else VAR54[13:0] <= VAR54[13:0]-1;
VAR122 <= (VAR54[13:0]== 14'h2); VAR101[13:0] <= VAR130[13:0];
VAR86 <= VAR2;
VAR168 <= VAR77;
if (VAR168) VAR53 <= 8'h82-VAR3;
else if (VAR120 && VAR137) VAR53 <= 8'h78;
else if (!VAR53[7]) VAR53 <= VAR53+1;
VAR191 <= VAR77 && ! VAR168 && VAR86 && VAR53[7];
end
endmodule
|
gpl-3.0
|
SiLab-Bonn/basil
|
basil/firmware/modules/utils/rgmii_io.v
| 11,611 |
module MODULE1 (
output wire [3:0] VAR37 ,
output wire VAR19 ,
output wire VAR20 ,
input wire [3:0] VAR11 ,
input wire VAR41 ,
input wire [7:0] VAR32 , input wire VAR23 ,
input wire VAR18 ,
output wire VAR56 ,
output wire VAR51 ,
output reg [7:0] VAR48 , output reg VAR34 , output reg VAR67 , output reg VAR10 ,
output reg [1:0] VAR69 ,
output reg VAR42 ,
input wire VAR24 , input wire VAR46, input wire VAR40 , input wire reset
);
reg [7:0] VAR1; reg VAR36; reg VAR55; reg [3:0] VAR31;
reg VAR26;
wire [3:0] VAR17;
wire [3:0] VAR35; wire VAR14;
reg [7:0] VAR12;
reg VAR71; reg VAR63; reg [7:0] VAR7; reg VAR59; reg VAR8;
wire VAR47;
VAR38 #(
.VAR28("VAR43"),
.VAR29(1'b0),
.VAR70("VAR21")
) VAR30 (
.VAR45(VAR47),
.VAR16(VAR46),
.VAR3(1'b1),
.VAR44(1'b1),
.VAR60(1'b0),
.VAR13(1'b0),
.VAR15(1'b0)
);
VAR62 VAR2 (.VAR54(VAR47), .VAR5(VAR20));
wire VAR50;
assign VAR50 = VAR23 ^ VAR18;
always @(posedge VAR24 or posedge reset)
begin
if (reset)
begin
VAR1 <= 8'b0;
VAR36 <= 1'b0;
VAR55 <= 1'b0;
end
else
begin
VAR1 <= VAR32;
VAR36 <= VAR23;
VAR55 <= VAR50;
end
end
wire VAR57;
assign VAR57 = ~(VAR24);
always @(posedge VAR57 or posedge reset)
begin
if (reset)
begin
VAR31 <= 4'b0;
VAR26 <= 1'b0;
end
else
begin
VAR31 <= VAR1[7:4];
VAR26 <= VAR55;
end
end
VAR38 #(
.VAR28("VAR43"),
.VAR29(1'b0),
.VAR70("VAR21")
) VAR58 (
.VAR45(VAR17[3]),
.VAR16(VAR24),
.VAR3(1'b1),
.VAR44(VAR1[3]),
.VAR60(VAR31[3]),
.VAR13(reset),
.VAR15(1'b0)
);
VAR38 #(
.VAR28("VAR43"),
.VAR29(1'b0),
.VAR70("VAR21")
) VAR73 (
.VAR45(VAR17[2]),
.VAR16(VAR24),
.VAR3(1'b1),
.VAR44(VAR1[2]),
.VAR60(VAR31[2]),
.VAR13(reset),
.VAR15(1'b0)
);
VAR38 #(
.VAR28("VAR43"),
.VAR29(1'b0),
.VAR70("VAR21")
) VAR25 (
.VAR45(VAR17[1]),
.VAR16(VAR24),
.VAR3(1'b1),
.VAR44(VAR1[1]),
.VAR60(VAR31[1]),
.VAR13(reset),
.VAR15(1'b0)
);
VAR38 #(
.VAR28("VAR43"),
.VAR29(1'b0),
.VAR70("VAR21")
) VAR65 (
.VAR45(VAR17[0]),
.VAR16(VAR24),
.VAR3(1'b1),
.VAR44(VAR1[0]),
.VAR60(VAR31[0]),
.VAR13(reset),
.VAR15(1'b0)
);
wire VAR52;
VAR38 #(
.VAR28("VAR43"),
.VAR29(1'b0),
.VAR70("VAR21")
) VAR33
(
.VAR45(VAR52),
.VAR16(VAR24),
.VAR3(1'b1),
.VAR44(VAR36),
.VAR60(VAR26),
.VAR13(reset),
.VAR15(1'b0)
);
VAR62 VAR39 (.VAR54(VAR52), .VAR5(VAR19));
VAR62 VAR61 (.VAR54(VAR17[3]), .VAR5(VAR37[3]));
VAR62 VAR49 (.VAR54(VAR17[2]), .VAR5(VAR37[2]));
VAR62 VAR4 (.VAR54(VAR17[1]), .VAR5(VAR37[1]));
VAR62 VAR6 (.VAR54(VAR17[0]), .VAR5(VAR37[0]));
VAR72 VAR22 (.VAR54(VAR41), .VAR5(VAR14));
VAR72 VAR64 (.VAR54(VAR11[3]), .VAR5(VAR35[3]));
VAR72 VAR53 (.VAR54(VAR11[2]), .VAR5(VAR35[2]));
VAR72 VAR68 (.VAR54(VAR11[1]), .VAR5(VAR35[1]));
VAR72 VAR9 (.VAR54(VAR11[0]), .VAR5(VAR35[0]));
always @(posedge VAR40 or posedge reset)
begin
if (reset)
begin
VAR12[3:0] <= 4'b0;
VAR71 <= 1'b0;
end
else
begin
VAR12[3:0] <= VAR35;
VAR71 <= VAR14;
end
end
wire VAR27;
assign VAR27 = ~(VAR40);
always @(posedge VAR27 or posedge reset)
begin
if (reset)
begin
VAR12[7:4] <= 4'b0;
VAR63 <= 1'b0;
end
else
begin
VAR12[7:4] <= VAR35;
VAR63 <= VAR14;
end
end
always @(posedge VAR40 or posedge reset)
begin
if (reset)
begin
VAR7[3:0] <= 4'b0;
VAR59 <= 1'b0;
end
else
begin
VAR7[3:0] <= VAR12[3:0];
VAR59 <= VAR71;
end
end
always @(posedge VAR27 or posedge reset)
begin
if (reset)
begin
VAR7[7:4] <= 4'b0;
VAR8 <= 1'b0;
end
else
begin
VAR7[7:4] <= VAR12[7:4];
VAR8 <= VAR63;
end
end
always @(posedge VAR40 or posedge reset)
begin
if (reset)
begin
VAR48[7:0] <= 8'b0;
VAR34 <= 1'b0;
VAR67 <= 1'b0;
end
else
begin
VAR48[7:0] <= VAR7[7:0];
VAR34 <= VAR59;
VAR67 <= VAR8 ^ VAR59;
end
end
wire VAR66;
assign VAR66 = !(VAR34 || VAR67);
always @(posedge VAR40 or posedge reset)
begin
if (reset)
begin
VAR10 <= 1'b0;
VAR69[1:0] <= 2'b0;
VAR42 <= 1'b0;
end
else
if (VAR66)
begin
VAR10 <= VAR48[0];
VAR69[1:0] <= VAR48[2:1];
VAR42 <= VAR48[3];
end
end
assign VAR56 = (VAR23 | VAR18) & (VAR34 | VAR67);
assign VAR51 = (VAR23 | VAR18) | (VAR34 | VAR67);
endmodule
|
bsd-3-clause
|
CospanDesign/vivado-ip-cores
|
ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/nh_lcd.v
| 5,135 |
module MODULE1 #(
parameter VAR4 = 24,
parameter VAR20 = 12
)(
input rst,
input clk,
output [31:0] VAR5,
input VAR32,
input VAR12,
input VAR3,
input VAR18,
input VAR24,
input VAR23,
input VAR48,
input [7:0] VAR21,
output [7:0] VAR8,
output VAR56,
input VAR33,
input VAR53,
input [31:0] VAR17,
input [31:0] VAR6,
input VAR14,
input VAR51,
output [1:0] VAR39,
input [1:0] VAR34,
input VAR26,
output [23:0] VAR35,
input [VAR4:0] VAR47,
output VAR36,
output VAR15,
output VAR45,
output VAR54,
input [7:0] VAR55,
output [7:0] VAR9,
output VAR42,
output VAR50,
input VAR2,
input VAR10,
input VAR41,
input VAR44
);
wire [7:0] VAR52;
wire VAR1;
wire VAR16;
wire [7:0] VAR40;
wire VAR37;
wire VAR11;
wire VAR25;
wire [7:0] VAR30;
wire VAR38;
wire VAR29;
wire VAR13;
VAR22 VAR46 (
.rst (rst ),
.clk (clk ),
.VAR32 (VAR32 ),
.VAR24 (VAR24 ),
.VAR23 (VAR23 ),
.VAR48 (VAR48 ),
.VAR21 (VAR21 ),
.VAR8 (VAR8 ),
.VAR27 (VAR11 ),
.VAR56 (VAR56 ),
.VAR43 (VAR37 ),
.VAR28 (VAR1 ),
.VAR31 (VAR16 ),
.VAR7 (VAR40 ),
.VAR57 (VAR55 )
);
VAR19 #(
.VAR4 (VAR4 ),
.VAR20 (VAR20 )
)VAR49(
.rst (rst ),
.clk (clk ),
.VAR5 (VAR5 ),
.VAR32 (VAR32 ),
.VAR18 (VAR18 ),
.VAR17 (VAR17 ),
.VAR6 (VAR6 ),
.VAR14 (VAR14 ),
.VAR51 (VAR51 ),
.VAR39 (VAR39 ),
.VAR34 (VAR34 ),
.VAR26 (VAR26 ),
.VAR35 (VAR35 ),
.VAR47 (VAR47 ),
.VAR43 (VAR25 ),
.VAR7 (VAR30 ),
.VAR57 (VAR55 ),
.VAR28 (VAR38 ),
.VAR31 (VAR29 ),
.VAR27 (VAR13 ),
.VAR2 (VAR2 ),
.VAR10 (VAR10 ),
.VAR44 (VAR44 ),
.VAR41 (VAR41 )
);
assign VAR50 = ~VAR12;
assign VAR42 = ~VAR53;
assign VAR15 = (VAR3) ? VAR37 : VAR25;
assign VAR45 = (VAR3) ? ~VAR1 : ~VAR38;
assign VAR54 = (VAR3) ? ~VAR16 : ~VAR29;
assign VAR36 = (VAR3) ? VAR11 : VAR13;
assign VAR9 = (VAR3) ? VAR40 : VAR30;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/bufinv/sky130_fd_sc_ls__bufinv.symbol.v
| 1,272 |
module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
htuNCSU/MmcCommunicationVerilog
|
DE2_115_SLAVE/source_code/PHYctrl_Slave.v
| 6,711 |
module MODULE1 (
input VAR50,
input [0: 0] VAR118,
input [17: 0] VAR124,
output [17: 0] VAR75,
output [10: 0] VAR20,
output [8: 0] VAR3,
output [6:0]VAR8,VAR66,VAR65,VAR54,VAR18,VAR60,VAR74,VAR99,
output VAR73,
inout VAR25,
output VAR52,
output VAR96,
input VAR126,
input VAR10,
input [3: 0] VAR88,
input VAR31,
output [3: 0] VAR64,
output VAR9,
output VAR77,
output VAR106,
output VAR43,
inout VAR130,
output VAR26,
input VAR85,
input VAR90,
input [3: 0] VAR116,
input VAR32,
output [3: 0] VAR45,
output VAR15
);
wire rst;
assign rst = VAR124[17];
wire VAR7;
assign VAR73 = VAR7;
assign VAR43 = VAR7;
assign VAR52 = 1'b1;
assign VAR26 = 1'b1;
assign VAR20[0] = VAR126;
assign VAR20[1] = VAR64[1];
assign VAR20[2] = VAR9;
assign VAR20[3] = VAR32;
assign VAR15 = VAR124[9];
wire VAR51;
wire VAR78;
wire VAR80;
wire VAR97;
assign VAR51 = VAR126;
assign VAR78 = VAR85;
assign VAR80 = VAR10;
assign VAR97 = VAR90;
wire [7:0] VAR100;
wire [7:0] VAR129;
VAR69 VAR2(
.VAR86(VAR129),
.VAR107(VAR100),
.VAR23(1'b0),
.clk(VAR97),
.VAR81(VAR129)
);
wire [7:0]VAR70;
wire [7:0]VAR110;
wire VAR103;
wire [7:0]VAR53;
VAR33 VAR89(
.VAR125(VAR110),
.VAR63(VAR70),
.VAR107(VAR124[7:2]),
.VAR71(VAR103),
.VAR23(1'b0),
.clk(VAR97),
.VAR81(VAR53)
);
reg [5:0]VAR5;
always @ (posedge VAR97 )
begin
if (rst)
begin
VAR5 <= 6'b0;
end
else
if(VAR109)
VAR5 <= 6'b0;
end
else
if (VAR32)begin
if (VAR5 < 6'b111110 )
VAR5 <= VAR5 + 1'b1;
end
end
wire [3:0]VAR67;
VAR13 VAR121(
.VAR125(VAR116),
.VAR63(VAR5),
.VAR107(VAR124[7:2]),
.VAR71(VAR32),
.VAR23(1'b0),
.clk(VAR97),
.VAR81(VAR67)
);
wire VAR41;
VAR27 VAR115
(
.VAR56(VAR97),
.VAR38(rst),
.VAR44(VAR41)
);
VAR34 VAR39(VAR54, VAR67[3:0]);
wire [7:0]VAR58;
wire [7:0]VAR111;
wire [7:0]VAR59;
wire [7:0]VAR48;
wire [3:0]VAR98;
wire VAR109;
VAR14 VAR35
(
.VAR83(VAR97),
.VAR12(VAR51),
.VAR41(VAR41),
.VAR17(VAR32),
.VAR19(VAR116),
.VAR42(rst),
.VAR129(VAR129),
.VAR93(8'd0),
.VAR119(8'd2),
.VAR123(VAR64),
.VAR11(VAR9),
.VAR110(VAR110),
.VAR103(VAR103),
.VAR70(VAR70),
.VAR100(VAR100),
.VAR6(VAR20[9]),
.VAR111(VAR111),
.VAR58(VAR58),
.VAR59(VAR59),
.VAR48(VAR48),
.VAR109(VAR109),
.VAR30(VAR75[1]),
.VAR92(VAR75[2]),
.VAR61(VAR75[3]),
.VAR113(VAR75[5:4]),
.VAR36(VAR75[6]),
.VAR127(VAR75[7]),
.VAR102(VAR75[9:8]),
.VAR79(VAR75[11]),
.VAR104(VAR75[12]),
.VAR84(VAR75[14:13]),
.VAR72(VAR75[15]),
.VAR105(VAR75[16])
);
assign VAR98 = VAR124[1]?VAR58[3:0]:VAR111[3:0];
reg [7:0]VAR95;
always@ (*)
begin
if(VAR124[16:14]==3'b001)
VAR95 = VAR59;
end
else
if(VAR124[16:14]==3'b010)
VAR95 = 8'b0;
else
if(VAR124[16:14]==3'b011)
VAR95 = 8'b0;
else
if(VAR124[16:14]==3'b100)
VAR95 = 8'b0;
else
if(VAR124[16:14]==3'b101)
VAR95 = VAR48;
else
VAR95 = VAR53;
end
VAR34 VAR120(VAR65, VAR98);
VAR34 VAR22(VAR66, VAR95[3:0]);
VAR34 VAR68(VAR8, VAR95[7:4]);
wire [31:0] VAR46;
wire [15:0] VAR16;
wire [3: 0] VAR112;
wire [15:0] VAR55;
wire [15:0] VAR114;
VAR108 VAR122 (
.clk(VAR50),
.reset(VAR124[0]),
.VAR7(VAR7),
.VAR128(VAR25),
.VAR24(VAR130),
.VAR49(VAR46),
.VAR28(VAR16),
.VAR1(VAR112),
.VAR94(VAR124[5:2]),
.VAR21(1'b1),
.VAR76(VAR3[0]),
.VAR40(VAR114),
.VAR29(VAR3[8]),
.VAR87(VAR3[7])
);
VAR57 VAR62 (
.clk(VAR50),
.VAR4(VAR46),
.addr(VAR112)
);
VAR117 VAR101 (
.clk(VAR50),
.VAR4(VAR16),
.addr(VAR112)
);
VAR34 VAR82(VAR99, VAR114[3:0]);
VAR34 VAR91(VAR74, VAR114[7:4]);
VAR34 VAR47(VAR60, VAR114[11:8]);
VAR34 VAR37(VAR18, VAR114[15:12]);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/or3/sky130_fd_sc_ls__or3.functional.pp.v
| 1,801 |
module MODULE1 (
VAR12 ,
VAR4 ,
VAR1 ,
VAR9 ,
VAR7,
VAR3,
VAR2 ,
VAR6
);
output VAR12 ;
input VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR3;
input VAR2 ;
input VAR6 ;
wire VAR13 ;
wire VAR10;
or VAR8 (VAR13 , VAR1, VAR4, VAR9 );
VAR5 VAR14 (VAR10, VAR13, VAR7, VAR3);
buf VAR11 (VAR12 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sregsbp/sky130_fd_sc_lp__sregsbp.symbol.v
| 1,413 |
module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR8 ,
input VAR10,
input VAR7 ,
input VAR1 ,
input VAR5
);
supply1 VAR11;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/xor2/sky130_fd_sc_hdll__xor2_1.v
| 2,133 |
module MODULE2 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR4,
VAR2,
VAR5 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR8 VAR9 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1,
VAR3,
VAR7
);
output VAR1;
input VAR3;
input VAR7;
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
VAR8 VAR9 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
svenstaro/uni-projekt
|
verilog/rom.v
| 6,509 |
module MODULE1 (
address,
VAR14,
VAR24,
VAR30);
input [7:0] address;
input VAR14;
input VAR24;
output [31:0] VAR30;
tri1 VAR14;
tri1 VAR24;
wire [31:0] VAR34;
wire [31:0] VAR30 = VAR34[31:0];
VAR52 VAR33 (
.VAR48 (address),
.VAR19 (VAR14),
.VAR16 (VAR24),
.VAR42 (VAR34),
.VAR37 (1'b0),
.VAR26 (1'b0),
.VAR11 (1'b1),
.VAR12 (1'b0),
.VAR22 (1'b0),
.VAR50 (1'b1),
.VAR39 (1'b1),
.VAR25 (1'b1),
.VAR18 (1'b1),
.VAR3 (1'b1),
.VAR23 (1'b1),
.VAR43 (1'b1),
.VAR4 ({32{1'b1}}),
.VAR1 (1'b1),
.VAR17 (),
.VAR44 (),
.VAR10 (1'b1),
.VAR45 (1'b0),
.VAR35 (1'b0));
VAR33.VAR9 = "VAR36",
VAR33.VAR29 = "VAR15",
VAR33.VAR20 = "VAR15",
VAR33.VAR6 = "MODULE1.VAR13",
VAR33.VAR38 = "VAR27 VAR21",
VAR33.VAR47 = "VAR49=VAR41",
VAR33.VAR51 = "VAR52",
VAR33.VAR31 = 256,
VAR33.VAR46 = "VAR5",
VAR33.VAR8 = "VAR36",
VAR33.VAR28 = "VAR40",
VAR33.VAR2 = 8,
VAR33.VAR32 = 32,
VAR33.VAR7 = 1;
endmodule
|
gpl-3.0
|
chriswynnyk/american-put-verilog
|
american_put_stratix/src/value_buffer.v
| 6,929 |
module MODULE1(
clk,
VAR101,
VAR17,
VAR30,
VAR83,
VAR102,
VAR21,
VAR74,
VAR100,
VAR127,
VAR60,
VAR56,
VAR99,
VAR114,
VAR105,
VAR69,
VAR61,
VAR108,
VAR115,
VAR89,
VAR75,
VAR29,
VAR121,
VAR52,
VAR67,
VAR71,
VAR16,
VAR42,
VAR126,
VAR109,
VAR12,
VAR94,
VAR65,
VAR2,
VAR68,
VAR22,
VAR27,
VAR26,
VAR90,
VAR4,
VAR97,
VAR5,
VAR78,
VAR9,
VAR128,
VAR81,
VAR44,
VAR25,
VAR79,
VAR86,
VAR34,
VAR84,
VAR33,
VAR59,
VAR1,
VAR82,
VAR92,
VAR120,
VAR35,
VAR15,
VAR53,
VAR64,
VAR93,
VAR58,
VAR87,
VAR3,
VAR72,
VAR106,
VAR111,
VAR70,
VAR57,
VAR28,
VAR122,
VAR119,
VAR48,
VAR8,
VAR98,
VAR103,
VAR63,
VAR6,
VAR96,
VAR41,
VAR125,
VAR45,
VAR47,
VAR80,
VAR20,
VAR14,
VAR38,
VAR24,
VAR23,
VAR54,
VAR10,
VAR73,
VAR43,
VAR110,
VAR124
);
input clk;
input [63:0] VAR101;
input [63:0] VAR17;
input [63:0] VAR30;
input [63:0] VAR83;
input [63:0] VAR102;
input [63:0] VAR21;
input [63:0] VAR74;
input [63:0] VAR100;
input [63:0] VAR127;
input [63:0] VAR60;
input [63:0] VAR56;
input [63:0] VAR99;
input [63:0] VAR114;
input [63:0] VAR105;
input [63:0] VAR69;
input [63:0] VAR61;
input [63:0] VAR108;
input [63:0] VAR115;
input [63:0] VAR89;
input [63:0] VAR75;
input [63:0] VAR29;
input [63:0] VAR121;
input [63:0] VAR52;
input [63:0] VAR67;
input [63:0] VAR71;
input [63:0] VAR16;
input [63:0] VAR42;
input [63:0] VAR126;
input [63:0] VAR109;
input [63:0] VAR12;
input [63:0] VAR94;
input [63:0] VAR65;
output [63:0] VAR2;
output [63:0] VAR68;
output [63:0] VAR22;
output [63:0] VAR27;
output [63:0] VAR26;
output [63:0] VAR90;
output [63:0] VAR4;
output [63:0] VAR97;
output [63:0] VAR5;
output [63:0] VAR78;
output [63:0] VAR9;
output [63:0] VAR128;
output [63:0] VAR81;
output [63:0] VAR44;
output [63:0] VAR25;
output [63:0] VAR79;
output [63:0] VAR86;
output [63:0] VAR34;
output [63:0] VAR84;
output [63:0] VAR33;
output [63:0] VAR59;
output [63:0] VAR1;
output [63:0] VAR82;
output [63:0] VAR92;
output [63:0] VAR120;
output [63:0] VAR35;
output [63:0] VAR15;
output [63:0] VAR53;
output [63:0] VAR64;
output [63:0] VAR93;
output [63:0] VAR58;
output [63:0] VAR87;
output [63:0] VAR3;
output [63:0] VAR72;
output [63:0] VAR106;
output [63:0] VAR111;
output [63:0] VAR70;
output [63:0] VAR57;
output [63:0] VAR28;
output [63:0] VAR122;
output [63:0] VAR119;
output [63:0] VAR48;
output [63:0] VAR8;
output [63:0] VAR98;
output [63:0] VAR103;
output [63:0] VAR63;
output [63:0] VAR6;
output [63:0] VAR96;
output [63:0] VAR41;
output [63:0] VAR125;
output [63:0] VAR45;
output [63:0] VAR47;
output [63:0] VAR80;
output [63:0] VAR20;
output [63:0] VAR14;
output [63:0] VAR38;
output [63:0] VAR24;
output [63:0] VAR23;
output [63:0] VAR54;
output [63:0] VAR10;
output [63:0] VAR73;
output [63:0] VAR43;
output [63:0] VAR110;
output [63:0] VAR124;
reg [63:0] VAR13;
reg [63:0] VAR107;
reg [63:0] VAR11;
reg [63:0] VAR39;
reg [63:0] VAR18;
reg [63:0] VAR116;
reg [63:0] VAR91;
reg [63:0] VAR76;
reg [63:0] VAR62;
reg [63:0] VAR66;
reg [63:0] VAR46;
reg [63:0] VAR118;
reg [63:0] VAR51;
reg [63:0] VAR88;
reg [63:0] VAR40;
reg [63:0] VAR85;
reg [63:0] VAR37;
reg [63:0] VAR77;
reg [63:0] VAR32;
reg [63:0] VAR36;
reg [63:0] VAR49;
reg [63:0] VAR123;
reg [63:0] VAR104;
reg [63:0] VAR112;
reg [63:0] VAR117;
reg [63:0] VAR50;
reg [63:0] VAR19;
reg [63:0] VAR55;
reg [63:0] VAR95;
reg [63:0] VAR7;
reg [63:0] VAR113;
reg [63:0] VAR31;
always@(posedge clk) begin
VAR13 <= VAR101;
VAR107 <= VAR17;
VAR11 <= VAR30;
VAR39 <= VAR83;
VAR18 <= VAR102;
VAR116 <= VAR21;
VAR91 <= VAR74;
VAR76 <= VAR100;
VAR62 <= VAR127;
VAR66 <= VAR60;
VAR46 <= VAR56;
VAR118 <= VAR99;
VAR51 <= VAR114;
VAR88 <= VAR105;
VAR40 <= VAR69;
VAR85 <= VAR61;
VAR37 <= VAR108;
VAR77 <= VAR115;
VAR32 <= VAR89;
VAR36 <= VAR75;
VAR49 <= VAR29;
VAR123 <= VAR121;
VAR104 <= VAR52;
VAR112 <= VAR67;
VAR117 <= VAR71;
VAR50 <= VAR16;
VAR19 <= VAR42;
VAR55 <= VAR126;
VAR95 <= VAR109;
VAR7 <= VAR12;
VAR113 <= VAR94;
VAR31 <= VAR65;
end
assign VAR3 = VAR13;
assign VAR72 = VAR107;
assign VAR106 = VAR11;
assign VAR111 = VAR39;
assign VAR70 = VAR18;
assign VAR57 = VAR116;
assign VAR28 = VAR91;
assign VAR122 = VAR76;
assign VAR119 = VAR62;
assign VAR48 = VAR66;
assign VAR8 = VAR46;
assign VAR98 = VAR118;
assign VAR103 = VAR51;
assign VAR63 = VAR88;
assign VAR6 = VAR40;
assign VAR96 = VAR85;
assign VAR41 = VAR37;
assign VAR125 = VAR77;
assign VAR45 = VAR32;
assign VAR47 = VAR36;
assign VAR80 = VAR49;
assign VAR20 = VAR123;
assign VAR14 = VAR104;
assign VAR38 = VAR112;
assign VAR24 = VAR117;
assign VAR23 = VAR50;
assign VAR54 = VAR19;
assign VAR10 = VAR55;
assign VAR73 = VAR95;
assign VAR43 = VAR7;
assign VAR110 = VAR113;
assign VAR124 = VAR31;
assign VAR2 = VAR107;
assign VAR68 = VAR11;
assign VAR22 = VAR39;
assign VAR27 = VAR18;
assign VAR26 = VAR116;
assign VAR90 = VAR91;
assign VAR4 = VAR76;
assign VAR97 = VAR62;
assign VAR5 = VAR66;
assign VAR78 = VAR46;
assign VAR9 = VAR118;
assign VAR128 = VAR51;
assign VAR81 = VAR88;
assign VAR44 = VAR40;
assign VAR25 = VAR85;
assign VAR79 = VAR37;
assign VAR86 = VAR77;
assign VAR34 = VAR32;
assign VAR84 = VAR36;
assign VAR33 = VAR49;
assign VAR59 = VAR123;
assign VAR1 = VAR104;
assign VAR82 = VAR112;
assign VAR92 = VAR117;
assign VAR120 = VAR50;
assign VAR35 = VAR19;
assign VAR15 = VAR55;
assign VAR53 = VAR95;
assign VAR64 = VAR7;
assign VAR93 = VAR113;
assign VAR58 = VAR31;
assign VAR87 = VAR101;
endmodule
|
apache-2.0
|
P3Stor/P3Stor
|
pcie/app/BAR1.v
| 21,940 |
module MODULE1# (
parameter VAR28 = 4'b0010,
parameter VAR21 = 8'h14
)
(
clk, VAR53, en,
VAR42, VAR9,
VAR84,
VAR34,
VAR88, VAR56, VAR8,
VAR30, VAR35, VAR86, VAR76,
VAR38,
VAR63, VAR45, VAR47, VAR81, VAR20, VAR22, VAR83, VAR26, VAR82, VAR10, VAR52, VAR55, VAR43,
VAR72, VAR73, VAR87, VAR57, VAR79, VAR31, VAR18, VAR5, VAR2, VAR70, VAR17, VAR25, VAR67,
VAR80, VAR44,
VAR36, VAR74, VAR68, VAR33, VAR23, VAR60, VAR7, VAR51, VAR71, VAR1, VAR12 VAR40
VAR32,
VAR69,
VAR24,
VAR59,
VAR19,
VAR61,
VAR49,
VAR29,
VAR4,
VAR14,
VAR27,
VAR16,
VAR58,
VAR66,
VAR65,
VAR15,
VAR39,
VAR48,
VAR6,
VAR77
);
input clk;
input VAR53;
input en;
input [5:0] VAR42;
input [5:0] VAR9;
input [3:0] VAR84;
input [3:0] VAR34;
input [2:0] VAR88;
input [2:0] VAR56;
input [2:0] VAR8;
input [6:0] VAR30;
input VAR35;
output [31:0] VAR86;
input [31:0] VAR76;
output VAR38;
output VAR63;
input VAR45;
output [31:0] VAR47;
output [15:0] VAR81;
output [2:0] VAR20;
output VAR22;
output VAR83;
output [7:0] VAR26;
output [31:0] VAR82;
output VAR10;
output VAR52;
output [7:0] VAR55;
output VAR43;
output VAR72;
input VAR73;
output [31:0] VAR87;
output [15:0] VAR57;
output [2:0] VAR79;
output VAR31;
output VAR18;
output [7:0] VAR5;
output [31:0] VAR2;
output VAR70;
output VAR17;
output [7:0] VAR25;
output VAR67;
input [7:0] VAR80;
input [7:0] VAR44;
input [31:0] VAR36;
input [31:0] VAR74;
input VAR68;
output VAR33;
output VAR23;
output VAR6;
output VAR77;
output [7:0] VAR60;
input [7:0] VAR7;
input [2:0] VAR51;
input VAR71;
output VAR1;
output [1:0] VAR32;
input [5:0] VAR69;
output [1:0] VAR24;
output VAR59;
output VAR19;
output VAR61;
input [1:0] VAR49;
input VAR29;
input VAR4;
input VAR14;
input [2:0] VAR27;
input VAR16;
input [1:0] VAR58;
input VAR66;
input VAR65;
output VAR15;
output VAR39;
input VAR48;
reg VAR38;
reg [31:0] VAR86 ;
reg VAR63;
reg [31:0] VAR47;
reg [15:0] VAR81;
reg [31:0] VAR82;
reg [2:0] VAR20;
reg VAR22;
reg VAR83;
reg [7:0] VAR26;
reg VAR10;
reg VAR52;
reg [7:0] VAR55;
reg VAR72;
reg [31:0] VAR87;
reg [15:0] VAR57;
reg [31:0] VAR2;
reg [2:0] VAR79;
reg VAR31;
reg VAR18;
reg [7:0] VAR5;
reg VAR70;
reg VAR17;
reg [7:0] VAR25;
reg [31:0] VAR37;
reg [31:0] VAR78;
reg VAR33;
reg VAR23;
reg VAR6;
reg VAR77;
reg [7:0] VAR89;
reg VAR46;
reg [13:0] VAR3;
reg VAR41;
reg VAR75;
reg VAR67;
reg VAR43;
reg [1:0] VAR32;
reg [1:0] VAR24;
wire VAR59;
reg [1:0] VAR11;
reg VAR19;
reg VAR61;
reg VAR50;
reg VAR13;
reg VAR15;
reg VAR39;
wire [1:0] VAR64;
wire [7:0] VAR62;
wire [3:0] VAR54;
wire [7:0] VAR85;
assign VAR85 = 8'h16;
assign VAR54 = VAR28;
assign VAR62 = VAR21;
assign VAR60[7:0] = VAR89[7:0];
assign VAR1 = VAR46;
assign VAR64 = (VAR29 == 0) ? 2'b01 : 2'b10;
assign VAR59 = (VAR11 == 2'b01) ?
0 : 1;
always @ ( VAR53 or VAR56 ) begin
if( !VAR53 )
VAR3 = 13'b0;
end
else
begin
case ( VAR56 )
3'b000: VAR3 = 1 << 7;
3'b001: VAR3 = 1 << 8;
3'b010: VAR3 = 1 << 9;
3'b011: VAR3 = 1 << 10;
3'b100: VAR3 = 1 << 11;
3'b101: VAR3 = 1 << 12;
default: VAR3 = 1 << 7;
endcase
end
end
always @(posedge clk ) begin
if ( !VAR53 ) begin
VAR38 <= 1'b0;
VAR63 <= 1'b0;
VAR47 <= 32'b0;
VAR81 <= 16'b0;
VAR82 <= 32'b0;
VAR20 <= 3'b0;
VAR22 <= 1'b0;
VAR26 <= 8'b0;
VAR10 <= 1'b0;
VAR52 <= 1'b0;
VAR83 <= 1'b0;
VAR18 <= 1'b0;
VAR72 <= 1'b0;
VAR87 <= 32'b0;
VAR57 <= 16'b0;
VAR2 <= 32'b0;
VAR79 <= 3'b0;
VAR31 <= 1'b0;
VAR5 <= 8'b0;
VAR70 <= 1'b0;
VAR17 <= 1'b0;
VAR33 <= 1'b1;
VAR23 <= 1'b1;
VAR6 <= 1'b0;
VAR77 <= 1'b0;
VAR25 <= 8'h08;
VAR55 <= 8'h08;
VAR41 <= 1'b0;
VAR75 <= 1'b0;
VAR43 <= 1'b0;
VAR67 <= 1'b0;
VAR15 <= 1'b0;
VAR39 <= 1'b0;
VAR32 <= 2'h0;
VAR24 <= 2'h0;
VAR11 <= 2'b0;
VAR19 <= 1'b0;
VAR61 <= 1'b0;
VAR50 <= 0;
VAR13 <= 0;
VAR89 <= 8'h00;
VAR46 <= 1'b0;
end
else begin
if (VAR30[6:0] != 7'b010011) begin
VAR50 <= VAR66;
VAR13 <= VAR65;
VAR32 <=
VAR48 ? 0 : VAR32;
end
VAR38 <= !en;
VAR57 <= VAR3 >> 2; VAR81 <= 1 << 5;
VAR41 <= VAR63;
VAR75 <= VAR72;
if( VAR75 && !VAR72 )
VAR67 <= 1'b1;
end
else
VAR67 <= 1'b0;
if( VAR41 && !VAR63 )
VAR43 <= 1'b1;
end
else
VAR43 <= 1'b0;
case (VAR30[6:0])
7'b0000000: begin
VAR86 <= { VAR62 , { 4'b0 } , VAR54 , VAR85 , { 7'b0 } , VAR38 };
end
7'b0000001: begin
if (VAR35) begin
VAR72 <= VAR76[0];
VAR70 <= VAR76[5];
VAR17 <= VAR76[6];
VAR63 <= VAR76[16];
VAR10 <= VAR76[21];
VAR52 <= VAR76[22];
end
VAR86 <= {7'b0, VAR45,
1'b0, VAR52, VAR10, 4'b0, VAR63,
7'b0, VAR73,
1'b0, VAR17, VAR70, 4'b0, VAR72};
end
7'b0000010: begin
VAR86 <= 32'b0;
end
7'b0000011: begin
VAR86 <= { VAR81 , VAR57 };
end
7'b0000100: begin
if( VAR35 )
VAR82 <= VAR76;
VAR86 <= VAR82;
end
7'b000101: begin
if( VAR35 )
VAR2 <= VAR76;
VAR86 <= VAR2;
end
7'b000110: begin
if( VAR35 )
VAR47 <= VAR76;
VAR86 <= VAR47;
end
7'b000111: begin
if( VAR35 )
VAR87 <= VAR76;
VAR86 <= VAR87;
end
7'b001000: begin
if (VAR35) begin
VAR20 <= VAR76[18:16];
VAR22 <= VAR76[19];
VAR83 <= VAR76[20];
VAR26 <= VAR76[31:24];
end
VAR86 <= {VAR26,
3'b0, VAR83, VAR22, VAR20,
16'b0};
end
7'b001001: begin
if (VAR35) begin
VAR79 <= VAR76[18:16];
VAR31 <= VAR76[19];
VAR18 <= VAR76[20];
VAR5 <= VAR76[31:24];
end
VAR86 <= {VAR5,
3'b0, VAR18, VAR31, VAR79,
16'b0};
end
7'b001010: begin
VAR86 <= VAR37;
end
7'b001011: begin
VAR86 <= VAR78;
end
7'b001100: begin
VAR86 <= {{15'b0}, VAR68, VAR44, VAR80};
end
7'b001101: begin
VAR86 <= {VAR36};
end
7'b001110: begin
VAR86 <= {VAR74};
end
7'b001111: begin
VAR86 <= {4'b0, VAR34,
4'b0, VAR84,
2'b0, VAR9,
2'b0, VAR42};
end
7'b010000: begin
VAR86 <= {8'b0,
5'b0, VAR8,
5'b0, VAR56,
5'b0, VAR88};
end
7'b010001: begin
if (VAR35) begin
VAR33 <= VAR76[0];
VAR23 <= VAR76[1];
VAR6 <= VAR76[8];
VAR77 <= VAR76[9];
VAR25 <= VAR76[23:16];
VAR55 <= VAR76[31:24];
end
VAR86 <= {VAR55,
VAR25,
6'b0, VAR77, VAR6,
6'b0, VAR23, VAR33};
end
7'b010010: begin
if (VAR35) begin
VAR89[7:0] <= VAR76[7:0];
VAR46 <= VAR76[8];
end
VAR86 <= {4'h0,
VAR71,
VAR51[2:0],
VAR7[7:0],
7'h0,
VAR46,
VAR89[7:0]};
end
7'b010011: begin
if (VAR35) begin
VAR15 <= VAR76[29];
VAR39 <= VAR76[28];
VAR61 <= VAR76[15]; VAR19 <= VAR76[14]; VAR11 <= VAR76[13:12]; VAR24 <= VAR76[9:8]; VAR32 <= VAR76[1:0]; end else
begin
VAR15 <= 1'b0;
VAR39 <= 1'b0;
VAR32 <= VAR48 ?
0 : VAR32;
end
VAR86 <= {
VAR58[1:0], VAR50, VAR13, VAR16, VAR27[2:0], VAR14, VAR4, VAR64[1:0], 2'b0, VAR49[1:0], VAR61, VAR19, VAR11[1:0], 2'b0, VAR24[1:0], VAR69[5:0], VAR32[1:0] };
end
default: begin
VAR86 <= 32'b0;
end
endcase
end
end
always @(posedge clk ) begin
if ( !VAR53 ) begin
VAR78 <= 32'b0;
end else begin
if ( VAR38 || VAR67 )
VAR78 <= 32'b0;
end
else if (VAR72 && !VAR73)
VAR78 <= VAR78 + 1'b1;
end
end
always @(posedge clk ) begin
if ( !VAR53 ) begin
VAR37 <= 32'b0;
end else begin
if ( VAR38 || VAR43 )
VAR37 <= 32'b0;
end
else if (VAR63 && !VAR45)
VAR37 <= VAR37 + 1'b1;
end
end
endmodule
|
gpl-2.0
|
fpgasystems/caribou
|
hw/src/nukv/nukv_fifogen_aclk.v
| 14,348 |
module MODULE1 #(
parameter VAR47=5, parameter VAR61=16 )
(
input wire VAR20,
input wire VAR14,
input wire rst,
input wire [VAR61-1:0] VAR37,
input wire VAR19,
output wire VAR49,
output wire VAR33,
output wire [VAR61-1:0] VAR46,
output wire VAR3,
input wire VAR38
);
wire[(VAR61+72):0] VAR55;
assign VAR55[VAR61-1:0] = {72'b0, VAR37[VAR61-1:0]};
reg [1:0] VAR4 = 0;
wire VAR51;
assign VAR51 = VAR4 == 2 ? 1 : 0;
always @(posedge VAR20) begin
if(rst) begin
VAR4 <= 0;
end else begin
if (VAR4<2) begin
VAR4 <= VAR4+1;
end
end
end
reg VAR63;
reg VAR6;
always @(posedge VAR14) begin
VAR63 <= rst;
VAR6 <= 0;
if (VAR63 == 0) begin
VAR6 <= 1;
end
end
genvar VAR57;
generate
if (VAR47<=9) begin
wire[(VAR61+71)/72-1:0] VAR50;
wire[(VAR61+71)/72-1:0] VAR29;
wire[(VAR61+71)/72-1:0] VAR11;
wire[(VAR61+71)/72-1:0] VAR44;
wire[(VAR61+71):0] VAR22;
assign VAR46[VAR61-1:0] = VAR22[VAR61-1:0];
assign VAR49 = ~rst & (VAR29!=0 ? 0 :1);
assign VAR33 = VAR29==0 ? 0 :1;
assign VAR3 = VAR11==0 ? 1 : 0;
for (VAR57=0; VAR57<(VAR61+71)/72; VAR57=VAR57+1) begin
VAR60 #(
.VAR30(13'h0080), .VAR2(VAR47>8 ? 2**VAR47-8 : 2**VAR47), .VAR39(72), .VAR43(1), .VAR13("VAR56"), .VAR48("VAR56"), .VAR7("VAR56"), .VAR53("VAR35"), .VAR25("VAR31"), .VAR58(72'h000000000000000000), .VAR28("7SERIES"), .VAR42(72'h000000000000000000) )
VAR36 (
.VAR65(), .VAR32(), .VAR10(), .VAR8(VAR22[VAR57*72 +: 64]), .VAR27(VAR22[VAR57*72+64 +: 8]), .VAR41(VAR44[VAR57]), .VAR34(VAR29[VAR57]), .VAR24(VAR11[VAR57]), .VAR52(VAR50[VAR57]), .VAR17(), .VAR12(), .VAR45(), .VAR40(), .VAR18(), .VAR1(),
.VAR59(VAR14), .VAR9(VAR38 & VAR6), .VAR54(1'b1), .VAR15(rst), .VAR26(rst), .VAR16(VAR20), .VAR21(VAR19 & VAR51 & ~VAR29[VAR57]), .VAR23(VAR55[VAR57*72 +: 64]), .VAR64(VAR55[VAR57*72+64 +: 8]) );
end
end else if (VAR47<=10) begin
wire[(VAR61+35)/36-1:0] VAR50;
wire[(VAR61+35)/36-1:0] VAR29;
wire[(VAR61+35)/36-1:0] VAR11;
wire[(VAR61+35)/36-1:0] VAR44;
wire[(VAR61+35):0] VAR22;
assign VAR46[VAR61-1:0] = VAR22[VAR61-1:0];
assign VAR49 = ~rst & (VAR29!=0 ? 0 : 1);
assign VAR33 = VAR29==0 ? 0 :1;
assign VAR3 = VAR11==0 ? 1 : 0;
for (VAR57=0; VAR57<(VAR61+35)/36; VAR57=VAR57+1) begin
VAR60 #(
.VAR30(13'h0080), .VAR2(2**VAR47-8), .VAR39(36), .VAR43(1), .VAR13("VAR56"), .VAR48("VAR56"), .VAR7("VAR56"), .VAR53("VAR5"), .VAR25("VAR31"), .VAR58(36'h000000000000000000), .VAR28("7SERIES"), .VAR42(36'h000000000000000000) )
VAR36 (
.VAR65(), .VAR32(), .VAR10(), .VAR8(VAR22[VAR57*36 +: 32]), .VAR27(VAR22[VAR57*36+32 +: 4]), .VAR41(VAR44[VAR57]), .VAR34(VAR29[VAR57]), .VAR24(VAR11[VAR57]), .VAR52(VAR50[VAR57]), .VAR17(), .VAR12(), .VAR45(), .VAR40(), .VAR18(), .VAR1(),
.VAR59(VAR14), .VAR9(VAR38 & VAR6), .VAR54(1'b1), .VAR15(rst), .VAR26(rst), .VAR16(VAR20), .VAR21(VAR19 & VAR51 & ~VAR29[VAR57]), .VAR23(VAR55[VAR57*36 +: 32]), .VAR64(VAR55[VAR57*36+32 +: 4]) );
end
end else if (VAR47<=11) begin
wire[(VAR61+17)/18-1:0] VAR50;
wire[(VAR61+17)/18-1:0] VAR29;
wire[(VAR61+17)/18-1:0] VAR11;
wire[(VAR61+17)/18-1:0] VAR44;
wire[(VAR61+17):0] VAR22;
assign VAR46[VAR61-1:0] = VAR22[VAR61-1:0];
assign VAR49 = ~rst & (VAR29!=0 ? 0 : 1);
assign VAR33 = VAR29==0 ? 0 :1;
assign VAR3 = VAR11==0 ? 1 : 0;
for (VAR57=0; VAR57<(VAR61+17)/18; VAR57=VAR57+1) begin
VAR60 #(
.VAR30(13'h0080), .VAR2(2**VAR47), .VAR39(18), .VAR43(1), .VAR13("VAR56"), .VAR48("VAR56"), .VAR7("VAR56"), .VAR53("VAR62"), .VAR25("VAR31"), .VAR58(18'h000000000000000000), .VAR28("7SERIES"), .VAR42(18'h000000000000000000) )
VAR36 (
.VAR65(), .VAR32(), .VAR10(), .VAR8(VAR22[VAR57*18 +: 16]), .VAR27(VAR22[VAR57*18+16 +: 2]), .VAR41(VAR44[VAR57]), .VAR34(VAR29[VAR57]), .VAR24(VAR11[VAR57]), .VAR52(VAR50[VAR57]), .VAR17(), .VAR12(), .VAR45(), .VAR40(), .VAR18(), .VAR1(),
.VAR59(VAR14), .VAR9(VAR38 & VAR6), .VAR54(1'b1), .VAR15(rst), .VAR26(rst), .VAR16(VAR20), .VAR21(VAR19 & VAR51 & ~VAR29[VAR57]), .VAR23(VAR55[VAR57*18 +: 16]), .VAR64(VAR55[VAR57*18+16 +: 2]) );
end
end
endgenerate
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/dlxtn/sky130_fd_sc_hdll__dlxtn_2.v
| 2,220 |
module MODULE1 (
VAR9 ,
VAR4 ,
VAR1,
VAR3 ,
VAR2 ,
VAR7 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR1;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR9 ,
VAR4 ,
VAR1
);
output VAR9 ;
input VAR4 ;
input VAR1;
supply1 VAR3;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR8 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
olgirard/openmsp430
|
core/bench/verilog/ram.v
| 3,027 |
module MODULE1 (
VAR4,
VAR10, VAR11, VAR5, VAR3, VAR7 );
parameter VAR6 = 6; parameter VAR1 = 256;
output [15:0] VAR4;
input [VAR6:0] VAR10; input VAR11; input VAR5; input [15:0] VAR3; input [1:0] VAR7;
reg [15:0] VAR9 [0:(VAR1/2)-1];
reg [VAR6:0] VAR2;
wire [15:0] VAR8 = VAR9[VAR10];
always @(posedge VAR5)
if (~VAR11 & VAR10<(VAR1/2))
begin
if (VAR7==2'b00) VAR9[VAR10] <= VAR3;
end
else if (VAR7==2'b01) VAR9[VAR10] <= {VAR3[15:8], VAR8[7:0]};
else if (VAR7==2'b10) VAR9[VAR10] <= {VAR8[15:8], VAR3[7:0]};
VAR2 <= VAR10;
end
assign VAR4 = VAR9[VAR2];
endmodule
|
bsd-3-clause
|
cfangmeier/VFPIX-telescope-Code
|
DAQ_Firmware/src/aux_io.v
| 6,234 |
module MODULE1(
input wire clk,
input wire reset,
input wire VAR40,
input wire VAR14,
input wire [31:0] VAR24,
output reg [31:0] VAR38,
input wire [25:0] address,
output wire VAR48,
input wire VAR35,
input wire [112:0] VAR56,
output wire [64:0] VAR20
);
localparam VAR45 = 3'd0,
VAR23 = 3'd1,
VAR37 = 3'd2,
VAR30 = 3'd3;
localparam VAR34 = 10'd512,
VAR55 = 10'd4;
wire [31:0] VAR16;
wire [31:0] VAR43;
reg [31:0] VAR25;
wire [31:0] VAR53;
reg VAR41;
wire VAR11;
wire VAR31;
wire VAR36;
reg VAR8;
wire VAR57;
wire [12:0] VAR50;
wire [12:0] VAR15;
wire [12:0] VAR39;
wire [12:0] VAR22;
wire [65*2-1:0] VAR27;
reg [2:0] state;
reg VAR1;
reg [31:0] VAR52;
assign VAR31 = (VAR50 == 0);
assign VAR57 = VAR22[12];
assign VAR48 = VAR1 | VAR40 | VAR14;
always @(posedge clk ) begin
if ( reset ) begin
VAR1 <= 1;
VAR52 <= 32'd0;
state <= VAR45;
end
else begin
VAR41 <= 0;
VAR8 <= 0;
case ( state )
VAR45: begin
VAR38 <= 32'd0;
VAR1 <= 0;
if ( VAR14 ) begin
case ( address[1:0] )
2'd0: begin
VAR1 <= 1;
state <= VAR23;
end
2'd1: begin
VAR38 <= {19'd0, VAR50};
end
2'd2: begin
VAR38 <= {19'd0, VAR22};
end
endcase
end
else if ( VAR40 ) begin
VAR1 <= 1;
VAR52 <= VAR24;
state <= VAR30;
end
end
VAR23: begin
if ( !VAR31 ) begin
VAR41 <= 1;
state <= VAR37;
end
end
VAR37: begin
VAR38 <= VAR43;
VAR1 <= 0;
state <= VAR45;
end
VAR30: begin
if ( !VAR57 ) begin
VAR8 <= 1;
VAR25 <= VAR52;
VAR1 <= 0;
state <= VAR45;
end
end
endcase
end
end
VAR47 # (.VAR51(2)) VAR13 (VAR20, VAR27);
VAR44 VAR28 (
.VAR29 ( clk ),
.VAR18 ( VAR35 ),
.VAR2 ( reset ),
.VAR17 ( VAR25),
.VAR4 ( VAR53 ),
.VAR21 ( VAR8 ),
.VAR46 ( VAR36 ),
.VAR6 ( VAR39 ),
.VAR33 ( VAR22 )
);
VAR49 VAR54(
.VAR56 ( VAR56 ),
.VAR20 ( VAR27[64:0] ),
.VAR5 ( 8'hA0 ),
.VAR32 ( VAR53 ),
.VAR3 ( VAR36 ),
.VAR19 ( ),
.VAR7 ( VAR39 >= VAR55 )
);
VAR44 VAR10 (
.VAR29 ( VAR35 ),
.VAR18 ( clk ),
.VAR2 ( reset ),
.VAR17 ( VAR16),
.VAR4 ( VAR43 ),
.VAR21 ( VAR11 ),
.VAR46 ( VAR41 ),
.VAR33 ( VAR15 ),
.VAR6 ( VAR50 )
);
VAR42 VAR26(
.VAR56 ( VAR56 ),
.VAR20 ( VAR27[129:65] ),
.VAR5 (8'h80 ),
.VAR9 ( VAR16),
.VAR12 ( VAR11 ),
.VAR19 ( ),
.VAR7 ( VAR15 >= VAR34 )
);
endmodule
|
gpl-2.0
|
hydai/Verilog-Practice
|
DigitalDesign/hw2/hw2_101062124/hw2_A/hw2_A.v
| 1,397 |
module MODULE1 (
input in,
input clk,
input VAR5,
output reg out
);
parameter VAR3 = 0;
parameter VAR2 = 1;
reg state, VAR1;
reg VAR4;
always @(posedge clk or negedge VAR5) begin
if (~VAR5) begin
state <= VAR3;
end else begin
state <= VAR1;
end end
always @ begin
case (state)
VAR3: begin if (in == 0) begin VAR4 <= 0;
end else begin VAR4 <= 1;
end
end
VAR2: begin VAR4 <= 0;
end
endcase
end
always @(posedge clk or negedge VAR5) begin
if(~VAR5) begin
out <= 0;
end else begin
out <= VAR4;
end
end
endmodule
|
mit
|
DougFirErickson/parallella-hw
|
fpga/old/esaxi/hdl/esaxi_v1_0_S00_AXI.v
| 20,520 |
module MODULE1 #
(
parameter [11:0] VAR87 = 12'h810,
parameter integer VAR67 = 1,
parameter integer VAR42 = 32,
parameter integer VAR59 = 30,
parameter integer VAR62 = 0,
parameter integer VAR10 = 0,
parameter integer VAR96 = 0,
parameter integer VAR85 = 0,
parameter integer VAR15 = 0
)
(
output reg [102:0] VAR3,
output reg VAR29,
input wire VAR30,
input wire VAR5,
output reg [102:0] VAR53,
output reg VAR43,
input wire VAR54,
input wire VAR19,
input wire [102:0] VAR88,
output wire VAR71,
input wire VAR81,
input wire [3:0] VAR93,
input wire [11:0] VAR49,
input wire VAR94,
input wire VAR89,
input wire [VAR67-1 : 0] VAR38,
input wire [VAR59-1 : 0] VAR12,
input wire [7 : 0] VAR46,
input wire [2 : 0] VAR86,
input wire [1 : 0] VAR28,
input wire VAR16,
input wire [3 : 0] VAR76,
input wire [2 : 0] VAR82,
input wire [3 : 0] VAR79,
input wire [3 : 0] VAR75,
input wire [VAR62-1 : 0] VAR57,
input wire VAR31,
output wire VAR40,
input wire [VAR42-1 : 0] VAR32,
input wire [(VAR42/8)-1 : 0] VAR17,
input wire VAR1,
input wire [VAR96-1 : 0] VAR23,
input wire VAR66,
output wire VAR47,
output wire [VAR67-1 : 0] VAR78,
output wire [1 : 0] VAR50,
output wire [VAR15-1 : 0] VAR35,
output wire VAR34,
input wire VAR77,
input wire [VAR67-1 : 0] VAR18,
input wire [VAR59-1 : 0] VAR36,
input wire [7 : 0] VAR90,
input wire [2 : 0] VAR97,
input wire [1 : 0] VAR41,
input wire VAR95,
input wire [3 : 0] VAR9,
input wire [2 : 0] VAR80,
input wire [3 : 0] VAR44,
input wire [3 : 0] VAR13,
input wire [VAR10-1 : 0] VAR8,
input wire VAR22,
output wire VAR52,
output wire [VAR67-1 : 0] VAR45,
output wire [VAR42-1 : 0] VAR84,
output wire [1 : 0] VAR25,
output wire VAR91,
output wire [VAR85-1 : 0] VAR20,
output wire VAR4,
input wire VAR65
);
reg [31:0] VAR69; reg [1:0] VAR6;
reg [2:0] VAR61;
reg VAR27;
reg VAR51;
reg [VAR67-1:0] VAR24;
reg [1:0] VAR74;
reg VAR63;
reg [31:0] VAR21; reg [7:0] VAR70;
reg [1:0] VAR39;
reg [2:0] VAR2;
reg VAR55;
reg [VAR67-1:0] VAR58;
reg [VAR42-1:0] VAR7;
reg [1:0] VAR56;
reg VAR98;
reg VAR72;
localparam integer VAR83 = (VAR42/32)+ 1;
assign VAR40 = VAR27;
assign VAR47 = VAR51;
assign VAR50 = VAR74;
assign VAR78 = VAR24;
assign VAR34 = VAR63;
assign VAR52 = VAR55;
assign VAR84 = VAR7;
assign VAR25 = VAR56;
assign VAR91 = VAR98;
assign VAR4 = VAR72;
assign VAR45 = VAR58;
assign VAR35 = 'd0;
assign VAR35 = 'd0;
assign VAR20 = 'd0;
reg VAR37;
reg VAR92;
wire VAR48 = VAR51 & VAR66 & VAR1;
always @( posedge VAR94 ) begin
if( VAR89 == 1'b0 ) begin
VAR27 <= 1'b0;
VAR37 <= 1'b0;
end else begin
if( ~VAR27 & ~VAR37 & ~VAR92 )
VAR27 <= 1'b1;
end
else if( VAR31 )
VAR27 <= 1'b0;
if( VAR27 & VAR31 )
VAR37 <= 1'b1;
end
else if( VAR48 )
VAR37 <= 1'b0;
end end
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR24 <= 'd0; VAR69 <= 'd0;
VAR61 <= 3'd0;
VAR6 <= 2'd0;
end else begin
if( VAR27 & VAR31 ) begin
VAR24 <= VAR38;
VAR69 <= { VAR49[11:VAR59-20],
VAR12 };
VAR61 <= VAR86; VAR6 <= VAR28;
end else if( VAR66 & VAR51 ) begin
if( VAR6 == 2'b01 ) begin
VAR69[31:VAR83] <= VAR69[31:VAR83] + 32'd1;
VAR69[VAR83-1:0] <= {VAR83{1'b0}};
end
end end end
always @( posedge VAR94 ) begin
if( VAR89 == 1'b0 ) begin
VAR51 <= 1'b0;
end else begin
if( VAR48 )
VAR51 <= 1'b0;
end
else if( VAR37 )
VAR51 <= ~VAR5;
end end
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR63 <= 1'b0;
VAR74 <= 2'b0;
VAR92 <= 1'b0;
end else begin
if( VAR48 ) begin
VAR63 <= 1'b1;
VAR74 <= 2'b0; VAR92 <= ~VAR77;
end else if (VAR77 & VAR63) begin
VAR63 <= 1'b0;
VAR92 <= 1'b0;
end
end end
reg VAR64;
reg [31:0] VAR73;
wire VAR14 = VAR72 & VAR98 & VAR65;
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR55 <= 1'b0;
VAR64 <= 1'b0;
end else begin
if( ~VAR55 & ~VAR64 )
VAR55 <= 1'b1;
end
else if( VAR22 )
VAR55 <= 1'b0;
if( VAR55 & VAR22 )
VAR64 <= 1'b1;
end
else if( VAR14 )
VAR64 <= 1'b0;
end end
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR21 <= 0;
VAR70 <= 8'd0;
VAR39 <= 2'd0;
VAR2 <= 2'b0;
VAR98 <= 1'b0;
VAR58 <= 'd0;
end else begin
if( VAR55 & VAR22 ) begin
VAR21 <= { VAR49[11:VAR59-20],
VAR36 }; VAR70 <= VAR90;
VAR39 <= VAR41;
VAR2 <= VAR97;
VAR98 <= ~(|VAR90);
VAR58 <= VAR18;
end else if(VAR72 & VAR65) begin
VAR70 <= VAR70 - 1;
if(VAR70 == 8'd1)
VAR98 <= 1'b1;
if( VAR41 == 2'b01) begin
VAR21[VAR59 - 1:VAR83] <= VAR21[VAR59 - 1:VAR83] + 1;
VAR21[VAR83-1:0] <= {VAR83{1'b0}};
end
end
end end
reg [31:0] VAR11;
reg [31:0] VAR100;
reg [1:0] VAR33;
reg VAR26; reg [3:0] VAR60;
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR11 <= 'd0;
VAR100 <= 'd0;
VAR33 <= 2'd0;
VAR3 <= 'd0;
VAR26 <= 1'b0;
VAR29 <= 1'b0;
VAR60 <= 'd0;
end else begin
VAR60 <= VAR93;
VAR100[31:2] <= VAR69[31:2];
if( VAR17[0] ) begin
VAR11 <= VAR32[31:0];
VAR100[1:0] <= 2'd0;
end else if(VAR17[1] ) begin
VAR11 <= {8'd0, VAR32[31:8]};
VAR100[1:0] <= 2'd1;
end else if(VAR17[2] ) begin
VAR11 <= {16'd0, VAR32[31:16]};
VAR100[1:0] <= 2'd2;
end else begin
VAR11 <= {24'd0, VAR32[31:24]};
VAR100[1:0] <= 2'd3;
end
VAR33 <= VAR61[1:0];
VAR26 <= VAR51 & VAR66;
VAR29 <= VAR26;
VAR3 <=
{ 1'b1, VAR33, VAR60,
VAR100, 32'd0, VAR11};
end end
reg VAR68; reg VAR99;
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR43 <= 1'b0;
VAR53 <= 'd0;
VAR68 <= 1'b0;
VAR99 <= 1'b0;
end else begin
VAR68 <= VAR64;
VAR99 <= VAR72 & VAR65 & ~VAR98;
VAR43 <= ( ~VAR68 & VAR64 ) | VAR99;
VAR53 <=
{ 1'b0, VAR2[1:0], VAR60,
VAR21, {VAR87, 20'd0}, 32'd0 };
end end
assign VAR71 = ~VAR81;
always @( posedge VAR94 ) begin
if ( VAR89 == 1'b0 ) begin
VAR72 <= 1'b0;
VAR7 <= 'd0;
VAR56 <= 2'd0;
end else begin
if( ~VAR81 ) begin
VAR72 <= 1'b1;
VAR56 <= 2'd0;
case( VAR2[1:0] )
2'b00: VAR7 <= {4{VAR88[7:0]}};
2'b01: VAR7 <= {2{VAR88[15:0]}};
default: VAR7 <= VAR88;
endcase
end else if( VAR65 ) begin
VAR72 <= 1'b0;
end
end end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a2111o/sky130_fd_sc_lp__a2111o.pp.blackbox.v
| 1,427 |
module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR2 ,
VAR10,
VAR8,
VAR4 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
input VAR10;
input VAR8;
input VAR4 ;
input VAR7 ;
endmodule
|
apache-2.0
|
AngelTerrones/Antares
|
Hardware/verilog/antares_control_unit.v
| 19,296 |
module MODULE1 #(parameter VAR60 = 1, parameter VAR63 = 1, parameter VAR29 = 1 )(
input [5:0] VAR24, input [5:0] VAR30, input [4:0] VAR51, input [4:0] VAR40, output [7:0] VAR67,
output VAR35, output VAR14, output VAR11, output VAR47, output VAR68, output VAR28, output VAR22, output VAR10, output VAR17, output VAR56, output VAR53, output VAR73, output VAR48, output VAR66, output VAR21, output VAR45, output VAR5, output VAR20, output VAR70, output VAR42, output [4:0] VAR62, output [1:0] VAR38, output [1:0] VAR55, output [1:0] VAR34, output VAR2, output VAR72, output VAR26, output VAR57, output VAR44, output VAR50 );
reg [31:0] VAR15;
wire VAR1;
wire VAR12;
wire VAR64;
assign VAR35 = (VAR24 != VAR7) & (VAR24 != VAR3) & (VAR24 != VAR71);
assign VAR14 = (VAR24 == VAR13) & (VAR30 == VAR49);
assign VAR11 = (VAR24 == VAR13) & (VAR30 == VAR65);
assign VAR47 = (VAR24 == VAR31) | (VAR24 == VAR54);
assign VAR68 = (VAR24 == VAR13) & (VAR30 == VAR58);
assign VAR28 = (VAR24 == VAR13) & (VAR30 == VAR59);
assign VAR10 = (VAR24 == VAR19) & (VAR51 == VAR61);
assign VAR17 = (VAR24 == VAR19) & (VAR51 == VAR4);
assign VAR56 = (VAR24 == VAR19) & (VAR51 == VAR27) & (VAR30 == VAR36);
assign VAR53 = (VAR24 == VAR33);
assign VAR73 = (VAR24 == VAR69);
assign VAR48 = (VAR24 == VAR6);
assign VAR22 = VAR1 | VAR12 | VAR64;
generate
if(VAR60) begin
assign VAR1 = 1'b0;
end
else begin
assign VAR1 = ((VAR15[20:16] == VAR43) | (VAR15[20:16] == VAR46) |
(VAR15[20:16] == VAR18) | (VAR15[20:16] == VAR9) |
(VAR15[20:16] == VAR16) | (VAR15[20:16] == VAR23));
end
endgenerate
generate
if(VAR63) begin
assign VAR12 = 1'b0;
end
else begin
assign VAR12 = ((VAR15[20:16] == VAR25) | (VAR15[20:16] == VAR37));
end
endgenerate
generate
if(VAR29) begin
assign VAR64 = 1'b0;
end
else begin
assign VAR64 = ((VAR15[20:16] == VAR32) | (VAR15[20:16] == VAR8));
end
endgenerate
assign VAR67 = VAR15[31:24];
assign VAR66 = VAR15[23];
assign VAR21 = VAR15[22];
assign VAR45 = VAR15[21];
assign VAR62 = VAR15[20:16];
assign VAR5 = VAR15[15];
assign VAR20 = VAR15[14];
assign VAR70 = VAR15[13];
assign VAR42 = VAR15[12];
assign VAR38 = VAR15[11:10];
assign VAR55 = VAR15[9:8];
assign VAR34 = VAR15[7:6];
assign VAR2 = VAR15[5];
assign VAR72 = VAR15[4];
assign VAR26 = VAR15[3];
assign VAR57 = VAR15[2];
assign VAR44 = VAR15[1];
assign VAR50 = VAR15[0];
always @(*) begin
case(VAR24)
case (VAR30)
default : begin VAR15 = VAR52; end
endcase end VAR41 : begin
case (VAR30)
default : begin VAR15 = VAR52; end
endcase end VAR39 : begin
case (VAR40)
default : begin VAR15 = VAR52; end
endcase end VAR19 : begin
case (VAR51)
default : begin VAR15 = VAR52; end
endcase end
default : begin VAR15 = VAR52; end
endcase end endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.blackbox.v
| 1,454 |
module MODULE1 (
VAR5 ,
VAR3,
VAR7,
VAR4 ,
VAR9
);
output VAR5 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR9 ;
supply1 VAR6;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
Ricky-Gong/LegoCar
|
DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_nios2_qsys_0_jtag_debug_module_tck.v
| 8,636 |
module MODULE1 (
VAR14,
VAR16,
VAR23,
VAR25,
VAR8,
VAR39,
VAR35,
VAR12,
VAR5,
VAR40,
VAR34,
VAR26,
VAR9,
VAR32,
VAR37,
VAR4,
VAR22,
VAR20,
VAR24,
VAR28,
VAR33,
VAR19,
VAR21,
VAR18,
VAR29,
VAR11,
VAR2,
VAR30,
VAR31,
VAR6,
VAR17
)
;
output [ 1: 0] VAR2;
output VAR30;
output [ 37: 0] VAR31;
output VAR6;
output VAR17;
input [ 31: 0] VAR14;
input [ 31: 0] VAR16;
input VAR23;
input VAR25;
input VAR8;
input VAR39;
input VAR35;
input [ 1: 0] VAR12;
input VAR5;
input VAR40;
input VAR34;
input VAR26;
input VAR9;
input VAR32;
input VAR37;
input VAR4;
input [ 35: 0] VAR22;
input VAR20;
input [ 6: 0] VAR24;
input VAR28;
input VAR33;
input VAR19;
input VAR21;
input VAR18;
input VAR29;
input VAR11;
reg [ 2: 0] VAR38 ;
wire VAR3;
reg [ 1: 0] VAR2;
wire VAR30;
wire VAR1;
reg [ 37: 0] VAR31 ;
wire VAR6;
wire VAR17;
wire VAR7;
wire VAR10;
always @(posedge VAR32)
begin
if (VAR18)
case (VAR12)
2'b00: begin
VAR31[35] <= VAR3;
VAR31[34] <= VAR40;
VAR31[33] <= VAR9;
VAR31[32 : 1] <= VAR14;
VAR31[0] <= VAR1;
end
2'b01: begin
VAR31[35 : 0] <= VAR22;
VAR31[37] <= VAR20;
VAR31[36] <= VAR4;
end
2'b10: begin
VAR31[37] <= VAR21;
VAR31[36] <= VAR39;
VAR31[35] <= VAR8;
VAR31[34] <= VAR25;
VAR31[33] <= VAR23;
VAR31[32 : 1] <= VAR16;
VAR31[0] <= VAR19;
end
2'b11: begin
VAR31[15 : 12] <= 1'b0;
VAR31[11 : 2] <= VAR24;
VAR31[1] <= VAR33;
VAR31[0] <= VAR28;
end
endcase if (VAR29)
case (VAR38)
3'b000: begin
VAR31 <= {VAR37, VAR31[37 : 2], VAR37};
end
3'b001: begin
VAR31 <= {VAR37, VAR31[37 : 9], VAR37, VAR31[7 : 1]};
end
3'b010: begin
VAR31 <= {VAR37, VAR31[37 : 17], VAR37, VAR31[15 : 1]};
end
3'b011: begin
VAR31 <= {VAR37, VAR31[37 : 33], VAR37, VAR31[31 : 1]};
end
3'b100: begin
VAR31 <= {VAR37, VAR31[37], VAR37, VAR31[35 : 1]};
end
3'b101: begin
VAR31 <= {VAR37, VAR31[37 : 1]};
end
default: begin
VAR31 <= {VAR37, VAR31[37 : 2], VAR37};
end
endcase if (VAR11)
case (VAR12)
2'b00: begin
VAR38 <= 3'b100;
end
2'b01: begin
VAR38 <= 3'b101;
end
2'b10: begin
VAR38 <= 3'b101;
end
2'b11: begin
VAR38 <= 3'b010;
end
endcase end
assign VAR17 = VAR31[0];
assign VAR6 = VAR5;
assign VAR7 = VAR30;
VAR13 VAR27
(
.clk (VAR32),
.din (VAR35),
.dout (VAR3),
.VAR26 (VAR7)
);
assign VAR10 = VAR30;
VAR13 VAR15
(
.clk (VAR32),
.din (VAR34),
.dout (VAR1),
.VAR26 (VAR10)
);
always @(posedge VAR32 or negedge VAR30)
begin
if (VAR30 == 0)
VAR2 <= 2'b0;
end
else
VAR2 <= {VAR3, VAR1};
end
assign VAR30 = VAR26;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/buf/sky130_fd_sc_hvl__buf_2.v
| 2,001 |
module MODULE2 (
VAR1 ,
VAR3 ,
VAR4,
VAR8,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR5 ;
VAR2 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR4;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR5 ;
VAR2 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v
| 10,847 |
module MODULE1 #
(parameter VAR71 = 3,
parameter VAR15 = 100,
parameter VAR39 = "8",
parameter VAR60 = 12,
parameter VAR82 = 8,
parameter VAR49 = "VAR22",
parameter VAR37 = 2,
parameter VAR5 = 4,
parameter VAR58 = 16)
(
VAR45, VAR11, VAR38, VAR12,
VAR54, VAR26, VAR59, VAR65, VAR73,
VAR3, VAR56, VAR35, VAR13, VAR40,
VAR4, VAR29, VAR7, VAR67, VAR10,
clk, VAR74, VAR61, VAR8, VAR34, VAR9, VAR18,
VAR55, VAR33, VAR64, VAR81, VAR14, VAR52, VAR77,
VAR62, VAR16, VAR47, VAR24, VAR42, VAR78
);
input clk;
input VAR74;
input VAR61;
input [VAR82-1:0]VAR8;
output reg [VAR82-1:0] VAR45;
wire [VAR82-1:0] VAR66 =
VAR61
? VAR8
: VAR45;
input VAR34;
reg VAR72;
wire VAR6 = VAR74
? VAR34
: VAR72;
output wire VAR11;
assign VAR11 = VAR72;
input VAR9;
wire VAR41;
generate
if (VAR39 == "4") begin : VAR75
assign VAR41 = 1'b0;
end
else
if (VAR39 == "8") begin : VAR68
assign VAR41 = 1'b1;
end
else
if (VAR39 == "VAR57") begin : VAR53
reg VAR27;
wire VAR17 = VAR74
? (VAR34 || VAR9)
: VAR27;
assign VAR41 = VAR27;
end
endgenerate
output wire VAR38;
assign VAR38 = VAR41;
input [2:0] VAR18;
reg [2:0] VAR70;
wire [2:0] VAR36 = VAR74
? (VAR34 ? 3'b001 : VAR18)
: VAR70;
VAR32: assert property
(@(posedge clk) ((VAR49 != "VAR22") || VAR74 || ~|VAR36[2:1]));
input VAR55;
reg VAR76;
wire VAR43 = VAR74
? ((VAR36[1:0] == 2'b11) || VAR36[0])
: ~VAR55 && VAR76;
output wire VAR12;
assign VAR12 = VAR76;
input [VAR37-1:0] VAR33;
input [VAR37-1:0] VAR64;
reg [VAR37-1:0] VAR19 = {VAR37{1'b0}};
reg [VAR37-1:0] VAR28 = {VAR37{1'b0}};
generate
if (VAR5 != 1) begin
always @(VAR74 or VAR34
or VAR64 or VAR33 or VAR19) VAR28 = VAR74
? VAR34
? VAR64
: VAR33
: VAR19;
end
endgenerate
output wire [VAR37-1:0] VAR54;
assign VAR54 = VAR19;
input [VAR71-1:0] VAR81;
reg [VAR71-1:0] VAR31;
wire [VAR71-1:0] VAR1 = VAR74 ? VAR81 : VAR31;
output wire[VAR71-1:0] VAR26;
assign VAR26 = VAR31;
input [VAR58-1:0] VAR14;
reg [VAR58-1:0] VAR63;
wire [VAR58-1:0] VAR51 = VAR74 ? VAR14 : VAR63;
output wire [VAR58-1:0] VAR59;
assign VAR59 = VAR63;
input [VAR60-1:0] VAR52;
reg [15:0] VAR20 = 16'b0;
wire [VAR60-1:0] VAR48 = VAR74 ? VAR52 : VAR20[VAR60-1:0];
reg VAR50;
wire VAR80 = VAR74
? ((VAR36[1:0] == 2'b11) || ~VAR36[0])
: VAR50;
output wire VAR65;
assign VAR65 = VAR50;
input VAR77;
output reg VAR73;
wire VAR44 = VAR74 ? VAR77 : VAR73;
wire VAR21 = (VAR19 == (VAR34
? VAR64
: VAR33));
wire VAR30 = (VAR31 == VAR81);
wire VAR25 = VAR21 && VAR30;
output reg VAR3; wire VAR79;
assign VAR79 = VAR25 && ~VAR74;
output wire VAR56;
assign VAR56 = VAR79;
wire VAR23 = (VAR63 == VAR14);
output reg VAR35;
input [VAR37-1:0] VAR62;
input VAR16;
input VAR47;
output wire VAR13;
assign VAR13 = (VAR19 == VAR62) || VAR16 || VAR47;
input VAR24;
input VAR42;
reg [15:0] VAR2 = 16'b0;
always @(VAR24 or VAR42 or VAR20
or VAR41) begin
VAR2 = VAR20;
VAR2[10] = VAR24 && ~VAR42;
VAR2[11] = VAR20[10];
VAR2[12] = VAR41;
VAR2[13] = VAR20[11];
end
output wire [VAR58-1:0] VAR40;
assign VAR40 = VAR2[VAR58-1:0];
output wire VAR4;
output wire VAR29;
output wire VAR7;
input VAR78;
assign VAR4 = 1'b0;
assign VAR29 = 1'b1;
assign VAR7 = VAR78;
output reg [VAR58-1:0] VAR67;
always @(VAR78 or VAR63) begin
VAR67 = VAR63;
if (~VAR78) VAR67[10] = 1'b0;
end
localparam VAR46 = 1;
output reg [VAR5-1:0] VAR10;
wire [VAR5-1:0] VAR69 = {VAR5{~VAR74}} & (VAR46[VAR5-1:0] << VAR28);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/mux4/sky130_fd_sc_ms__mux4.functional.v
| 1,592 |
module MODULE1 (
VAR9 ,
VAR8,
VAR10,
VAR5,
VAR2,
VAR3,
VAR4
);
output VAR9 ;
input VAR8;
input VAR10;
input VAR5;
input VAR2;
input VAR3;
input VAR4;
wire VAR11;
VAR7 VAR6 (VAR11, VAR8, VAR10, VAR5, VAR2, VAR3, VAR4);
buf VAR1 (VAR9 , VAR11 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/bufinv/sky130_fd_sc_lp__bufinv.functional.pp.v
| 1,782 |
module MODULE1 (
VAR2 ,
VAR5 ,
VAR7,
VAR11,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR7;
input VAR11;
input VAR3 ;
input VAR1 ;
wire VAR8 ;
wire VAR4;
not VAR6 (VAR8 , VAR5 );
VAR12 VAR10 (VAR4, VAR8, VAR7, VAR11);
buf VAR9 (VAR2 , VAR4 );
endmodule
|
apache-2.0
|
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