repo_name
stringlengths 6
79
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stringlengths 4
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| size
int64 1.02k
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| content
stringlengths 15
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| license
stringclasses 14
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|---|---|---|---|---|
KestrelComputer/polaris
|
processor/bench/verilog/polaris.v
| 30,496 |
module MODULE1();
reg [31:0] VAR50;
reg VAR39;
reg VAR43;
reg VAR9;
reg [31:0] VAR62;
wire [63:0] VAR24;
wire VAR52;
wire VAR31;
wire [3:0] VAR57;
reg VAR33;
reg [63:0] VAR40;
wire [63:0] VAR59;
wire [63:0] VAR4;
wire [1:0] VAR20;
wire VAR25;
wire VAR14;
wire VAR23;
wire VAR38;
wire [11:0] VAR61;
wire [63:0] VAR44;
reg [63:0] VAR35;
wire VAR19, VAR17;
reg VAR64;
wire [63:0] VAR47;
wire VAR28, VAR1;
reg VAR6;
task VAR55; input [15:0] VAR58;
begin
VAR50 <= {VAR58, 16'h0000};
@(VAR39);
@(~VAR39);
", VAR58, VAR58);
end
endtask
task VAR11;
input [15:0] VAR58;
begin
VAR50 <= {VAR50[31:16], VAR58};
end
endtask
task VAR30;
input [63:0] VAR45;
begin
if(VAR24 !== VAR45) begin
end
end
endtask
task VAR16;
input [63:0] VAR45;
begin
if(VAR44 !== VAR45) begin
end
end
endtask
task VAR10;
input [11:0] VAR45;
begin
if(VAR61 !== VAR45) begin
end
end
endtask
task VAR54;
input [63:0] VAR45;
begin
if(VAR47 !== VAR45) begin
end
end
endtask
task VAR18;
input VAR45;
begin
if(VAR52 !== VAR45) begin
end
end
endtask
task VAR2;
input VAR45;
begin
if(VAR31 !== VAR45) begin
end
end
endtask
task VAR3;
input VAR45;
begin
if(VAR28 !== VAR45) begin
end
end
endtask
task VAR48;
input VAR45;
begin
if(VAR1 !== VAR45) begin
end
end
endtask
task VAR46;
input [3:0] VAR45;
begin
if(VAR57 !== VAR45) begin
end
end
endtask
task VAR22;
input [63:0] VAR45;
begin
if(VAR4 !== VAR45) begin
end
end
endtask
task VAR15;
input [63:0] VAR45;
begin
if(VAR59 !== VAR45) begin
end
end
endtask
task VAR36;
input [1:0] VAR45;
begin
if(VAR20 !== VAR45) begin
end
end
endtask
task VAR37;
input VAR45;
begin
if(VAR14 !== VAR45) begin
end
end
endtask
task VAR51;
input VAR45;
begin
if(VAR19 !== VAR45) begin
end
end
endtask
task VAR60;
input VAR45;
begin
if(VAR17 !== VAR45) begin
end
end
endtask
task VAR53;
input VAR45;
begin
if(VAR23 !== VAR45) begin
end
end
endtask
task VAR29;
input VAR45;
begin
if(VAR38 !== VAR45) begin
end
end
endtask
task VAR7;
input VAR45;
begin
if(VAR25 !== VAR45) begin
end
end
endtask
always begin
end
VAR26 VAR21(
.VAR31(VAR31),
.VAR57(VAR57),
.VAR47(VAR47),
.VAR1(VAR1),
.VAR28(VAR28),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR62(VAR62),
.VAR24(VAR24),
.VAR52(VAR52),
.VAR33(VAR33),
.VAR40(VAR40),
.VAR59(VAR59),
.VAR4(VAR4),
.VAR38(VAR38),
.VAR14(VAR14),
.VAR23(VAR23),
.VAR20(VAR20),
.VAR25(VAR25),
.VAR61(VAR61),
.VAR19(VAR19),
.VAR17(VAR17),
.VAR64(VAR64),
.VAR44(VAR44),
.VAR35(VAR35),
.VAR39(VAR39),
.VAR43(VAR43)
);
task VAR49;
begin
VAR55(0);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR11(2);
VAR18(0);
VAR43 <= 0;
VAR11(3);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR9 <= 0;
VAR11(4);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR9 <= 0;
VAR11(5);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR9 <= 1;
VAR11(6);
VAR18(0);
VAR11(7);
VAR18(0);
VAR2(1); VAR46(2);
VAR11(8); VAR2(0);
VAR11(9);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFE00);
end
endtask
task VAR41;
begin
VAR55(1);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'h00000013; VAR11(3);
VAR18(0);
VAR2(0);
VAR11(4);
VAR18(0);
VAR2(0);
VAR11(5);
VAR18(0);
VAR2(0);
VAR11(6);
VAR30(64'hFFFFFFFFFFFFFF04);
VAR18(1);
VAR2(0);
VAR62 <= 32'h12400113; VAR11(7);
VAR18(0);
VAR11(8);
VAR18(0);
VAR11(9);
VAR18(0);
VAR11(10);
VAR18(1);
VAR62 <= 32'h00010067; VAR11(11);
VAR11(12);
VAR11(13);
VAR11(14);
VAR11(15);
VAR18(1);
VAR30(64'h0000000000000124);
VAR62 <= 32'h12410113; VAR11(16);
VAR11(17);
VAR11(18);
VAR11(19);
VAR18(1);
VAR62 <= 32'h000100E7; VAR11(20); VAR11(21);
VAR11(22);
VAR11(23);
VAR11(24);
VAR18(1);
VAR30(64'h0000000000000248);
VAR62 <= 32'hFFC08067; VAR11(25);
VAR11(26);
VAR11(27);
VAR11(28);
VAR11(29);
VAR30(64'h0000000000000128);
VAR18(1);
VAR62 <= 32'b00001111111100010111000100010011;
VAR11(30); VAR11(31); VAR11(32);
VAR11(33);
VAR30(64'h000000000000012C);
VAR18(1);
VAR62 <= 32'b00000001000000010001000100010011;
VAR11(35); VAR11(36);
VAR11(37);
VAR11(38);
VAR30(64'h0000000000000130);
VAR18(1);
VAR62 <= 32'b00000000000000010000000001100111;
VAR11(40); VAR11(41);
VAR11(42);
VAR11(43);
VAR11(44);
VAR30(64'h0000000000480000);
VAR18(1);
VAR62 <= 32'b00000000000100000000000110010011;
VAR11(50); VAR11(51);
VAR11(52);
VAR11(53);
VAR62 <= 32'b00000001111100011001000110011011;
VAR11(55); VAR11(56);
VAR11(57);
VAR11(58);
VAR62 <= 32'b00000000000000011000000001100111;
VAR11(60); VAR11(61);
VAR11(62);
VAR11(63);
VAR11(64);
VAR18(1);
VAR30(64'hFFFFFFFF80000000);
VAR62 <= 32'b11111111111100000000000010010011; VAR11(100);
VAR11(101);
VAR11(102);
VAR11(103);
VAR62 <= 32'b00000000000100001010000100010011; VAR11(105);
VAR11(106);
VAR11(107);
VAR11(108);
VAR62 <= 32'b00000000000000010000000001100111; VAR11(110);
VAR11(111);
VAR11(112);
VAR11(113);
VAR11(114);
VAR18(1);
VAR30(64'h0000000000000001);
VAR62 <= 32'b11111111111100000000000010010011; VAR11(100);
VAR11(101);
VAR11(102);
VAR11(103);
VAR62 <= 32'b00000000000100001011000100010011; VAR11(105);
VAR11(106);
VAR11(107);
VAR11(108);
VAR62 <= 32'b00000000000000010000000001100111; VAR11(110);
VAR11(111);
VAR11(112);
VAR11(113);
VAR11(114);
VAR18(1);
VAR30(64'h0000000000000000);
end
endtask
task VAR12;
begin
VAR55(2);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'b11111111111100000000000100010011;
VAR11(0);
VAR11(1);
VAR11(2);
VAR11(3);
VAR62 <= 32'b00001010101000000000000110010011;
VAR11(5);
VAR11(6);
VAR11(7);
VAR11(8);
VAR62 <= 32'b00000101010100000000001000010011;
VAR11(10);
VAR11(11);
VAR11(12);
VAR11(13);
VAR62 <= 32'b00000001000000011001000110010011;
VAR11(15);
VAR11(16);
VAR11(17);
VAR11(18);
VAR62 <= 32'b00000000001100010100000100110011;
VAR11(20);
VAR11(21);
VAR11(22);
VAR11(23);
VAR11(24);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF14);
VAR62 <= 32'b00000000100000011001000110010011;
VAR11(25);
VAR11(26);
VAR11(27);
VAR11(28);
VAR62 <= 32'b00000000001100010100000100110011;
VAR11(30);
VAR11(31);
VAR11(32);
VAR11(33);
VAR11(34);
VAR62 <= 32'b00000010000000100001001000010011;
VAR11(35);
VAR11(36);
VAR11(37);
VAR11(38);
VAR62 <= 32'b00000000010000010100000100110011;
VAR11(40);
VAR11(41);
VAR11(42);
VAR11(43);
VAR11(44);
VAR62 <= 32'b00000000100000100001001000010011;
VAR11(45);
VAR11(46);
VAR11(47);
VAR11(48);
VAR62 <= 32'b00000000010000010100000100110011;
VAR11(50);
VAR11(51);
VAR11(52);
VAR11(53);
VAR11(54);
VAR62 <= 32'b00000000000000010000000001100111;
VAR11(90); VAR11(91);
VAR11(92);
VAR11(93);
VAR11(94);
VAR18(1);
VAR30(64'hFFFFAAAA5555FFFF);
end
endtask
task VAR63;
begin
VAR55(3);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'b11011110101011011011000100110111;
VAR11(10);
VAR11(11);
VAR11(12);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF04);
VAR62 <= 32'b00000000000000010000000001100111;
VAR11(20);
VAR11(21);
VAR11(22);
VAR11(23);
VAR11(24);
VAR18(1);
VAR30(64'hFFFFFFFFDEADB000);
VAR62 <= 32'b00000000010100100100001010010111;
VAR11(30);
VAR11(31);
VAR11(32);
VAR18(1);
VAR30(64'hFFFFFFFFDEADB004);
VAR62 <= 32'b00000000000000101000000001100111;
VAR11(40);
VAR11(41);
VAR11(42);
VAR11(43);
VAR11(44);
VAR18(1);
VAR30(64'hFFFFFFFFDEFFF000);
end
endtask
task VAR5;
begin
VAR55(4);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'b11011110101011011011000100110111;
VAR11(10);
VAR11(11);
VAR11(12);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF04);
VAR62 <= 32'b00010010001100010101000010000011;
VAR11(20);
VAR11(21);
VAR11(22);
VAR37(1);
VAR53(1);
VAR36(2'b01);
VAR7(0);
VAR29(0);
VAR22(64'hFFFFFFFFDEADB123);
VAR11(23);
VAR37(1);
VAR53(1);
VAR36(2'b01);
VAR7(0);
VAR29(0);
VAR11(24);
VAR37(1);
VAR53(1);
VAR36(2'b01);
VAR7(0);
VAR29(0);
VAR40 <= 64'h000000000000FFFC;
VAR33 <= 1;
VAR11(25);
VAR37(0);
VAR53(0);
VAR18(1);
VAR62 <= 32'b00000000010000001000000010000011;
VAR11(30);
VAR11(31);
VAR11(32);
VAR37(1);
VAR53(1);
VAR36(2'b00);
VAR7(1);
VAR29(0);
VAR22(64'h0000000000010000);
VAR40 <= 64'h000000000000FFFC;
VAR33 <= 1;
VAR11(35);
VAR37(0);
VAR53(0);
VAR18(1);
VAR62 <= 32'b00000000000100001011011000100011;
VAR33 <= 0;
VAR11(40);
VAR11(41);
VAR11(42);
VAR37(1);
VAR53(1);
VAR36(2'b11);
VAR29(1);
VAR22(64'h0000000000010008);
VAR15(64'h000000000000FFFC);
VAR11(43);
VAR37(1);
VAR53(1);
VAR36(2'b11);
VAR29(1);
VAR22(64'h0000000000010008);
VAR15(64'h000000000000FFFC);
VAR33 <= 1;
VAR11(44);
VAR37(0);
VAR53(0);
VAR18(1);
end
endtask
task VAR32;
begin
VAR55(5);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'b10010000000011110000001011101111;
VAR11(10);
VAR11(11);
VAR11(12);
VAR11(13);
VAR18(1);
VAR30(64'hFFFFFFFFFFFF0000);
VAR62 <= 32'b00000000010100000011000000100011;
VAR11(20);
VAR11(21);
VAR11(22);
VAR36(2'b11);
VAR37(1);
VAR53(1);
VAR22(64'd0);
VAR15(64'hFFFFFFFFFFFFFF04);
VAR29(1);
end
endtask
task VAR56;
begin
VAR55(6);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'b00000000000000000000000010010011;
VAR11(10);
VAR11(11);
VAR11(12);
VAR11(13);
VAR18(1);
VAR62 <= 32'b00000000000000001000100001100011;
VAR11(20);
VAR11(21);
VAR11(22);
VAR11(23);
VAR11(24);
VAR11(25);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF14);
VAR62 <= 32'b00000000000000001001100001100011;
VAR11(30);
VAR11(31);
VAR11(32);
VAR11(33);
VAR11(34);
VAR11(35);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF18);
VAR62 <= 32'b00000000000000001100100001100011;
VAR11(40);
VAR11(41);
VAR11(42);
VAR11(43);
VAR11(44);
VAR11(45);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF1C);
VAR62 <= 32'b00000000000000001101100001100011;
VAR11(50);
VAR11(51);
VAR11(52);
VAR11(53);
VAR11(54);
VAR11(55);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF2C);
VAR62 <= 32'b00000000000000001110100001100011;
VAR11(60);
VAR11(61);
VAR11(62);
VAR11(63);
VAR11(64);
VAR11(65);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF30);
VAR62 <= 32'b00000000000000001111100001100011;
VAR11(70);
VAR11(71);
VAR11(72);
VAR11(73);
VAR11(74);
VAR11(75);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF40);
VAR62 <= 32'b11111111111100000000000010010011;
VAR11(110);
VAR11(111);
VAR11(112);
VAR11(113);
VAR18(1);
VAR62 <= 32'b00000000000000001000100001100011;
VAR11(120);
VAR11(121);
VAR11(122);
VAR11(123);
VAR11(124);
VAR11(125);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF48);
VAR62 <= 32'b00000000000000001001100001100011;
VAR11(130);
VAR11(131);
VAR11(132);
VAR11(133);
VAR11(134);
VAR11(135);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF58);
VAR62 <= 32'b00000000000000001100100001100011;
VAR11(140);
VAR11(141);
VAR11(142);
VAR11(143);
VAR11(144);
VAR11(145);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF68);
VAR62 <= 32'b00000000000000001101100001100011;
VAR11(150);
VAR11(151);
VAR11(152);
VAR11(153);
VAR11(154);
VAR11(155);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF6C);
VAR62 <= 32'b00000000000000001110100001100011;
VAR11(160);
VAR11(161);
VAR11(162);
VAR11(163);
VAR11(164);
VAR11(165);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF70);
VAR62 <= 32'b00000000000000001111100001100011;
VAR11(170);
VAR11(171);
VAR11(172);
VAR11(173);
VAR11(174);
VAR11(175);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF80);
VAR62 <= 32'b00000000000100000000000010010011;
VAR11(210);
VAR11(211);
VAR11(212);
VAR11(213);
VAR18(1);
VAR62 <= 32'b00000000000000001000100001100011;
VAR11(220);
VAR11(221);
VAR11(222);
VAR11(223);
VAR11(224);
VAR11(225);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF88);
VAR62 <= 32'b00000000000000001001100001100011;
VAR11(230);
VAR11(231);
VAR11(232);
VAR11(233);
VAR11(234);
VAR11(235);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF98);
VAR62 <= 32'b00000000000000001100100001100011;
VAR11(240);
VAR11(241);
VAR11(242);
VAR11(243);
VAR11(244);
VAR11(245);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF9C);
VAR62 <= 32'b00000000000000001101100001100011;
VAR11(250);
VAR11(251);
VAR11(252);
VAR11(253);
VAR11(254);
VAR11(255);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFFAC);
VAR62 <= 32'b00000000000000001110100001100011;
VAR11(260);
VAR11(261);
VAR11(262);
VAR11(263);
VAR11(264);
VAR11(265);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFFB0);
VAR62 <= 32'b00000000000000001111100001100011;
VAR11(270);
VAR11(271);
VAR11(272);
VAR11(273);
VAR11(274);
VAR11(275);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFFC0);
end
endtask
task VAR34;
begin
VAR55(7);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR9 <= 1;
VAR62 <= 32'b00001010010100000000000000001111;
VAR11(10);
VAR11(11);
VAR11(12);
VAR11(13);
VAR11(14);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF04);
VAR62 <= 32'b00000000000000000001000000001111;
VAR11(20);
VAR11(21);
VAR11(22);
VAR11(23);
VAR11(24);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF08);
end
endtask
task VAR27;
begin
VAR55(8);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR48(0);
VAR3(1);
VAR9 <= 1;
VAR62 <= 32'b00000000000000000000000001110011;
VAR11(10); VAR2(1);
VAR46(11);
VAR11(11); VAR2(0);
VAR11(12); VAR18(1);
VAR30(64'hFFFFFFFFFFFFFE00);
VAR54(64'hFFFFFFFFFFFFFF00);
VAR48(0);
VAR3(0);
VAR62 <= 32'b00110000001000000000000001110011;
VAR11(30);
VAR11(31);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR48(0);
VAR3(1);
VAR62 <= 32'b00000000000100000000000001110011;
VAR11(20);
VAR2(1);
VAR46(3);
VAR11(21);
VAR2(0);
VAR11(22);
VAR18(1);
VAR30(64'hFFFFFFFFFFFFFE00);
end
endtask
task VAR13;
begin
VAR55(9);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR48(0);
VAR3(1);
VAR9 <= 1;
VAR62 <= 32'b11111111111100010001000011110011;
VAR11(10);
VAR10(12'hFFF);
VAR11(11);
VAR18(0);
VAR2(1);
VAR46(2);
VAR11(12);
VAR11(13);
VAR18(1);
VAR2(0);
VAR62 <= 32'b00001010101000000000000010011011;
VAR11(20);
VAR11(21);
VAR11(22);
VAR11(23);
VAR18(1);
VAR62 <= 32'b00110100000000001001000001110011;
VAR11(30);
VAR11(31);
VAR51(0); VAR60(1);
VAR16(64'h00000000000000aa);
VAR11(32);
VAR62 <= 32'b00000101010100000000000010011011;
VAR11(40);
VAR11(41);
VAR11(42);
VAR11(43);
VAR18(1);
VAR62 <= 32'b00000000000100001000000000100011;
VAR11(45);
VAR11(46);
VAR11(47);
VAR36(2'b00);
VAR37(1);
VAR53(1);
VAR22(64'h0000000000000055);
VAR15(64'h0000000000000055);
VAR29(1);
VAR11(48);
VAR62 <= 32'b00110100000000001001000011110011;
VAR11(50);
VAR11(51);
VAR51(1); VAR60(1);
VAR16(64'h0000000000000055);
VAR11(52);
VAR62 <= 32'b00000000000100001000000000100011;
VAR11(60);
VAR11(61);
VAR11(62);
VAR36(2'b00);
VAR37(1);
VAR53(1);
VAR22(64'h00000000000000AA);
VAR15(64'h00000000000000AA);
VAR29(1);
VAR11(63);
VAR62 <= 32'b00110100000000001001000011110011;
VAR11(70);
VAR11(71);
VAR51(1); VAR60(1);
VAR16(64'h00000000000000AA);
VAR11(72);
VAR62 <= 32'b00000000000100001000000000100011;
VAR11(80);
VAR11(81);
VAR11(82);
VAR36(2'b00);
VAR37(1);
VAR53(1);
VAR22(64'h0000000000000055);
VAR15(64'h0000000000000055);
VAR29(1);
VAR11(83);
VAR62 <= 32'b00110100000011111101000001110011;
VAR11(90);
VAR11(91);
VAR51(0);
VAR60(1);
VAR16(64'h000000000000001F);
VAR11(92);
end
endtask
task VAR42;
begin
VAR55(10);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR48(0);
VAR3(1);
VAR9 <= 1;
VAR62 <= 32'b00000000000000000000000010011011;
VAR11(10);
VAR11(11);
VAR11(12);
VAR11(13);
VAR18(1);
VAR62 <= 32'b00110100000000001001000011110011;
VAR11(20);
VAR11(21);
VAR16(64'h0);
VAR11(22);
VAR18(1);
VAR62 <= 32'b00000000000000001000000010000011;
VAR11(30);
VAR11(31);
VAR11(32);
VAR40 <= 64'hAAAAAAAAAAAAAAAA;
VAR33 <= 1;
VAR11(33);
VAR18(1);
VAR62 <= 32'b00110100000000001010000001110011;
VAR11(40);
VAR11(41);
VAR11(42);
VAR16(64'hAAAAAAAAAAAAAAAA);
VAR11(43);
VAR18(1);
VAR62 <= 32'b00000000000000001000000010000011;
VAR11(50);
VAR11(51);
VAR11(52);
VAR40 <= 64'h5555555555555555;
VAR33 <= 1;
VAR11(53);
VAR18(1);
VAR62 <= 32'b00110100000000001010000101110011;
VAR11(60);
VAR11(61);
VAR11(62);
VAR11(63);
VAR18(1);
VAR62 <= 32'b00000000001000010011000000100011;
VAR11(70);
VAR11(71);
VAR11(72);
VAR15(64'hAAAAAAAAAAAAAAAA);
VAR11(73);
VAR62 <= 32'b00110100000000000001000101110011;
VAR11(80);
VAR11(81);
VAR11(82);
VAR62 <= 32'b00000000001000010011000000100011;
VAR11(90);
VAR11(91);
VAR11(92);
VAR15(64'hFFFFFFFFFFFFFFFF);
VAR11(93);
VAR62 <= 32'b00110100000011111111000001110011;
VAR11(100);
VAR11(101);
VAR11(102);
VAR11(103);
VAR18(1);
VAR62 <= 32'b00110100000000000001000011110011;
VAR11(110);
VAR11(111);
VAR11(112);
VAR62 <= 32'b00000000000100001011000000100011;
VAR11(120);
VAR11(121);
VAR11(122);
VAR15(64'hFFFFFFFFFFFFFFE0);
VAR11(123);
end
endtask
task VAR8;
begin
VAR55(11);
VAR43 <= 1;
VAR11(1);
VAR18(0);
VAR36(2'b00);
VAR7(0);
VAR29(0);
VAR43 <= 0;
VAR11(2);
VAR30(64'hFFFFFFFFFFFFFF00);
VAR18(1);
VAR2(0);
VAR48(0);
VAR3(1);
VAR9 <= 1;
VAR62 <= 32'b00110100010000000001000011110011;
VAR11(1000);
VAR11(1001);
VAR11(1002);
VAR18(1);
VAR62 <= 32'b00000000000000001000000001100111;
VAR11(1010);
VAR11(1011);
VAR11(1012);
VAR11(1013);
VAR11(1014);
VAR18(1);
VAR30(64'h0000000000000000);
VAR6 <= 1;
VAR62 <= 32'b00110100010000000001000011110011;
VAR11(1000);
VAR11(1001);
VAR11(1002);
VAR18(1);
VAR62 <= 32'b00000000000000001000000001100111;
VAR11(1010);
VAR11(1011);
VAR11(1012);
VAR11(1013);
VAR11(1014);
VAR18(1);
VAR30(64'h0000000000000800);
VAR6 <= 0;
VAR62 <= 32'b00110000000000000001000011110011;
VAR11(10);
VAR11(11);
VAR11(12);
VAR18(1);
VAR62 <= 32'b00110000000001000110000001110011;
VAR11(20);
VAR11(21);
VAR11(22);
VAR11(23);
VAR18(1);
VAR62 <= 32'b00110000000000000001000101110011;
VAR11(30);
VAR11(31);
VAR11(32);
VAR18(1);
VAR62 <= 32'b00000000001000001100000010110011;
VAR11(40);
VAR11(41);
VAR11(42);
VAR11(43);
VAR11(44);
VAR18(1);
VAR62 <= 32'b00000000000000001000000001100111;
VAR11(50);
VAR11(51);
VAR11(52);
VAR11(53);
VAR11(54);
VAR18(1);
VAR30(64'h0000000000000008);
VAR62 <= 32'b00110000010000000001000011110011;
VAR11(60);
VAR11(61);
VAR11(62);
VAR18(1);
VAR62 <= 32'b10000000000000000000000100011011;
VAR11(70);
VAR11(71);
VAR11(72);
VAR11(73);
VAR18(1);
VAR62 <= 32'b00110000010000010001000001110011;
VAR11(80);
VAR11(81);
VAR11(82);
VAR18(1);
VAR62 <= 32'b00110000010000000001000111110011;
VAR11(90);
VAR11(91);
VAR11(92);
VAR18(1);
VAR62 <= 32'b00000000001100001100000010110011;
VAR11(100);
VAR11(101);
VAR11(102);
VAR11(103);
VAR11(104);
VAR18(1);
VAR62 <= 32'b00000000000000001000000001100111;
VAR11(110);
VAR11(111);
VAR11(112);
VAR11(113);
VAR11(114);
VAR18(1);
VAR30(64'h0000000000000800);
VAR6 <= 1;
VAR62 <= 32'b00000000000100000000000001110011;
VAR11(120); VAR18(1);
VAR30(64'hFFFFFFFFFFFFFE00);
VAR62 <= 32'b00110100001000000001000011110011;
VAR11(121);
VAR11(122);
VAR11(123);
VAR18(1);
VAR62 <= 32'b00000000000000001000000001100111;
VAR11(130);
VAR11(131);
VAR11(132);
VAR11(133);
VAR11(134);
VAR18(1);
VAR30(64'h800000000000000B);
VAR6 <= 0; VAR62 <= 32'b00110000001000000000000001110011;
VAR11(140);
VAR11(141);
VAR18(1);
VAR30(64'h0000000000000800);
end
endtask
|
mpl-2.0
|
hcabrera-/lancetfish
|
RTL/router/verif/harness.v
| 5,291 |
module MODULE1();
parameter VAR28 = 2,
VAR45 = 2,
VAR27 = 100,
VAR18 = 15,
VAR33 = 5;
reg clk;
reg reset;
wire VAR36;
wire [VAR10-1:0] VAR2;
wire VAR38;
wire [VAR10-1:0] VAR12;
wire VAR20;
wire[VAR10-1:0] VAR3;
wire VAR24;
wire [VAR10-1:0] VAR6;
wire VAR11;
wire [VAR10-1:0] VAR1;
wire VAR7;
wire [VAR10-1:0] VAR31;
wire VAR35;
wire [VAR10-1:0] VAR44;
wire VAR15;
wire [VAR10-1:0] VAR43;
wire VAR4;
wire [VAR10-1:0] VAR23;
wire VAR30;
wire [VAR10-1:0] VAR42;
VAR25
.VAR28(VAR28),
.VAR45(VAR45)
)
VAR32
(
.clk (clk),
.reset (reset),
.VAR36 (VAR36),
.VAR2 (VAR2),
.VAR38 (VAR38),
.VAR12 (VAR12),
.VAR20 (VAR20),
.VAR3 (VAR3),
.VAR24 (VAR24),
.VAR6 (VAR6),
.VAR11 (VAR11), .VAR1 (VAR1),
.VAR7 (VAR7),
.VAR31 (VAR31),
.VAR35 (VAR35),
.VAR44 (VAR44),
.VAR15 (VAR15),
.VAR43 (VAR43),
.VAR4 (VAR4),
.VAR23 (VAR23),
.VAR30 (VAR30), .VAR42 (VAR42)
);
VAR41
.VAR33(VAR33)
)
VAR29
(
.clk (clk),
.VAR37 (VAR36),
.VAR16(VAR2)
);
VAR21
.VAR33(VAR33)
)
VAR13
(
.clk (clk),
.VAR26 (VAR31),
.VAR9 (VAR7)
);
VAR41
.VAR33(VAR33)
)
VAR34
(
.clk (clk),
.VAR37 (VAR38),
.VAR16(VAR12)
);
VAR21
.VAR33(VAR33)
)
VAR39
(
.clk (clk),
.VAR26 (VAR44),
.VAR9 (VAR35)
);
VAR41
.VAR33(VAR33)
)
VAR8
(
.clk (clk),
.VAR37 (VAR20),
.VAR16(VAR3)
);
VAR21
.VAR33(VAR33)
)
VAR17
(
.clk (clk),
.VAR26 (VAR43),
.VAR9 (VAR15)
);
VAR41
.VAR33(VAR33)
)
VAR14
(
.clk (clk),
.VAR37 (VAR24),
.VAR16(VAR6)
);
VAR21
.VAR33(VAR33)
)
VAR40
(
.clk (clk),
.VAR26 (VAR23),
.VAR9 (VAR4)
);
VAR41
.VAR33(VAR33)
)
VAR19
(
.clk (clk),
.VAR37 (VAR11),
.VAR16(VAR1)
);
VAR21
.VAR33(VAR33)
)
VAR22
(
.clk (clk),
.VAR26 (VAR42),
.VAR9 (VAR30)
);
always
begin
end
task VAR5;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
end
reset <= 1'b0;
end
endtask : VAR5
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a221o/sky130_fd_sc_ls__a221o.blackbox.v
| 1,395 |
module MODULE1 (
VAR8 ,
VAR7,
VAR10,
VAR3,
VAR1,
VAR9
);
output VAR8 ;
input VAR7;
input VAR10;
input VAR3;
input VAR1;
input VAR9;
supply1 VAR5;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
tmatsuya/milkymist-ml401
|
cores/softusb/rtl/softusb_rx.v
| 5,001 |
module MODULE1(
input VAR10,
input VAR1,
input VAR2,
input VAR4,
input VAR13,
output reg [7:0] VAR22,
output reg VAR23,
output reg VAR5,
input VAR11
);
wire VAR27 = VAR2 ^ VAR11;
wire VAR8 = ~VAR4 & ~VAR13;
reg [2:0] VAR25;
reg [2:0] VAR26;
always @(posedge VAR10) begin
if(VAR1)
VAR25 <= 3'd0;
end
else
VAR25 <= VAR26;
end
reg VAR7;
always @ begin
VAR3 = 1'b0;
VAR24 = VAR21;
case(VAR21)
VAR14: if(~VAR27 & ~VAR5)
VAR24 = VAR6;
VAR6: if(VAR27)
VAR24 = VAR19;
VAR19: if(~VAR27)
VAR24 = VAR20;
VAR20: if(VAR27)
VAR24 = VAR16;
VAR16: if(~VAR27)
VAR24 = VAR18;
VAR18: if(VAR27)
VAR24 = VAR9;
VAR9: if(~VAR27)
VAR24 = VAR12;
VAR12: if(VAR17) begin
if(~VAR27)
VAR24 = VAR15;
end
else
VAR24 = VAR14;
end
VAR15: if(VAR17) begin
if(~VAR27)
VAR3 = 1'b1;
VAR24 = VAR14;
end
endcase
end
endmodule
|
lgpl-3.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_hexdot.v
| 2,118 |
module MODULE1 (
address,
VAR1,
clk,
VAR2,
VAR7,
VAR4,
VAR9,
VAR6
)
;
output [ 5: 0] VAR9;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR2;
input VAR7;
input [ 31: 0] VAR4;
wire VAR3;
reg [ 5: 0] VAR5;
wire [ 5: 0] VAR9;
wire [ 5: 0] VAR8;
wire [ 31: 0] VAR6;
assign VAR3 = 1;
assign VAR8 = {6 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR5 <= 0;
end
else if (VAR1 && ~VAR7 && (address == 0))
VAR5 <= VAR4[5 : 0];
end
assign VAR6 = {32'b0 | VAR8};
assign VAR9 = VAR5;
endmodule
|
gpl-2.0
|
Jawanga/ece385final
|
finalproject/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v
| 11,552 |
module MODULE1
parameter VAR17 = 32,
parameter VAR92 = 8,
parameter VAR80 = 10,
parameter VAR37 = 1,
parameter VAR77 = 4,
parameter VAR38 = 4,
parameter VAR55 = 2,
parameter VAR67 = 2,
parameter VAR51 = VAR17 / VAR92
)
(
input VAR19,
input VAR26,
input VAR63,
input VAR87,
output VAR25,
output [VAR17-1:0] VAR62,
output VAR47,
input [VAR37-1:0] VAR41,
input [VAR17-1:0] VAR7,
input [VAR80-1:0] VAR71,
input VAR78,
input VAR3,
input [VAR51-1:0] VAR27,
input VAR39,
input VAR75,
input [VAR17-1:0] VAR32,
input VAR70,
output [VAR37-1:0] VAR40,
output [VAR17-1:0] VAR58,
output [VAR80-1:0] VAR79,
output VAR9,
output VAR13,
output [VAR51-1:0] VAR61,
output VAR28
);
localparam VAR16 = VAR37 + VAR17 + VAR80
+ VAR51
+ 3;
localparam VAR12 = VAR17 / VAR92;
localparam VAR4 = VAR17;
localparam VAR59 = (1 << (VAR37-1));
localparam VAR1 = VAR53(VAR38) + 1;
localparam VAR11 = (VAR59 == 1);
localparam VAR34 = VAR37;
wire [VAR16-1:0] VAR20;
wire [VAR16-1:0] VAR2;
wire VAR66;
wire VAR10;
wire VAR84;
wire VAR90;
wire VAR14;
wire VAR23;
reg [VAR1-1:0] VAR93;
wire [VAR1-1:0] VAR8;
wire VAR85;
reg VAR21;
wire VAR31;
wire VAR68;
reg VAR5;
wire [VAR34-1:0] VAR49;
VAR6
.VAR22 (1),
.VAR64 (VAR16),
.VAR46 (VAR77),
.VAR44 (VAR55),
.VAR18 (VAR67),
.VAR57 (1)
)
VAR45
(
.VAR33 (VAR19),
.VAR30 (~VAR26),
.VAR36 (VAR63),
.VAR81 (~VAR87),
.VAR15 (VAR20),
.VAR35 (VAR66),
.VAR88 (VAR14),
.VAR24 (VAR2),
.VAR42 (VAR10),
.VAR74 (VAR23),
.VAR76 (1'b0),
.VAR82 (1'b0),
.VAR43 (1'b0),
.VAR65 (1'b0),
.VAR83 (1'b0),
.VAR52 (1'b0),
.VAR73 (1'b0),
.VAR69 (1'b0),
.VAR91 (32'b0),
.VAR60 (1'b0),
.VAR50 (1'b0),
.VAR48 (1'b0),
.VAR29 (32'b0)
);
assign VAR25 = ~VAR14;
assign VAR66 = VAR78 | VAR3;
assign VAR20 = {VAR71,
VAR41,
VAR3,
VAR78,
VAR7,
VAR27,
VAR39};
assign {VAR79,
VAR40,
VAR90,
VAR84,
VAR58,
VAR61,
VAR28} = VAR2;
assign VAR23 = ~VAR75 &
~(VAR90 & VAR21 & ~VAR5);
assign VAR9 = VAR84 & VAR10;
assign VAR13 = VAR90 & VAR10 & (~VAR21 | VAR5);
assign VAR31 = VAR13 & ~VAR75;
generate if (VAR11)
begin
always @(posedge VAR63, posedge VAR87) begin
if (VAR87) begin
VAR93 <= 0;
end
else begin
if (VAR31 & VAR70)
VAR93 <= VAR93;
end
else if (VAR70)
VAR93 <= VAR93 - 1;
end
else if (VAR31)
VAR93 <= VAR93 + 1;
end
end
end
else begin
assign VAR49 = VAR40;
always @(posedge VAR63, posedge VAR87) begin
if (VAR87) begin
VAR93 <= 0;
end
else begin
if (VAR31 & VAR70)
VAR93 <= VAR93 +
VAR49 - 1;
end
else if (VAR70)
VAR93 <= VAR93 - 1;
end
else if (VAR31)
VAR93 <= VAR93 +
VAR49;
end
end
end
endgenerate
assign VAR85 = (VAR93 + 2*VAR59) > VAR8;
always @(posedge VAR63, posedge VAR87) begin
if (VAR87) begin
VAR21 <= 1'b0;
VAR5 <= 1'b0;
end
else begin
VAR21 <= VAR85;
VAR5 <= VAR13 & VAR75;
end
end
VAR6
.VAR22 (1),
.VAR64 (VAR4),
.VAR46 (VAR38),
.VAR44 (VAR67),
.VAR18 (VAR55),
.VAR54 (1)
)
VAR89
(
.VAR33 (VAR63),
.VAR30 (~VAR87),
.VAR36 (VAR19),
.VAR81 (~VAR26),
.VAR15 (VAR32),
.VAR35 (VAR70),
.VAR88 (VAR68),
.VAR24 (VAR62),
.VAR42 (VAR47),
.VAR74 (1'b1),
.VAR72 (VAR8),
.VAR76 (1'b0),
.VAR82 (1'b0),
.VAR43 (1'b0),
.VAR65 (1'b0),
.VAR83 (1'b0),
.VAR52 (1'b0),
.VAR73 (1'b0),
.VAR69 (1'b0),
.VAR91 (32'b0),
.VAR60 (1'b0),
.VAR50 (1'b0),
.VAR48 (1'b0),
.VAR29 (32'b0)
);
always @(posedge VAR63) begin
if (~VAR68 & VAR70) begin
end
if (VAR93 > VAR8) begin
end
end
function integer VAR53;
input integer VAR56;
integer VAR86;
begin
VAR86 = 1;
VAR53 = 0;
while (VAR86 < VAR56) begin
VAR53 = VAR53 + 1;
VAR86 = VAR86 << 1;
end
end
endfunction
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_axi_basic_tx.v
| 10,238 |
module MODULE1 #(
parameter VAR34 = 128, parameter VAR46 = "VAR8", parameter VAR3 = "VAR12", parameter VAR6 = "VAR12", parameter VAR5 = 1,
parameter VAR44 = (VAR34 == 128) ? 2 : 1, parameter VAR36 = VAR34 / 8 ) (
input [VAR34-1:0] VAR26, input VAR29, output VAR42, input [VAR36-1:0] VAR39, input VAR13, input [3:0] VAR15,
input VAR37, input VAR17,
output [VAR34-1:0] VAR43, output VAR38, output VAR11, output VAR14, input VAR2, output VAR18, output [VAR44-1:0] VAR45, output VAR28, output VAR40, input [5:0] VAR47, output VAR31,
input VAR24, output VAR21, input VAR9,
input [2:0] VAR32,
input VAR25, input [1:0] VAR22, input [31:0] VAR41, input VAR27,
input VAR19, output VAR33,
input VAR23, input VAR20 );
wire VAR7;
VAR10 #(
.VAR34( VAR34 ),
.VAR6( VAR6 ),
.VAR5( VAR5 ),
.VAR44( VAR44 ),
.VAR36( VAR36 )
) VAR1 (
.VAR26( VAR26 ),
.VAR42( VAR42 ),
.VAR29( VAR29 ),
.VAR39( VAR39 ),
.VAR13( VAR13 ),
.VAR15( VAR15 ),
.VAR43( VAR43 ),
.VAR38( VAR38 ),
.VAR11( VAR11 ),
.VAR14( VAR14 ),
.VAR2( VAR2 ),
.VAR18( VAR18 ),
.VAR45( VAR45 ),
.VAR28( VAR28 ),
.VAR40( VAR40 ),
.VAR31( VAR31 ),
.VAR9( VAR9 ),
.VAR7( VAR7 ),
.VAR23( VAR23 ),
.VAR20( VAR20 )
);
generate
if(VAR6 == "VAR12") begin : VAR35
VAR30 #(
.VAR34( VAR34 ),
.VAR46( VAR46 ),
.VAR3( VAR3 ),
.VAR5( VAR5 )
) VAR4 (
.VAR26( VAR26 ),
.VAR29( VAR29 ),
.VAR15( VAR15 ),
.VAR13( VAR13 ),
.VAR37( VAR37 ),
.VAR17( VAR17 ),
.VAR47( VAR47 ),
.VAR2( VAR2 ),
.VAR24( VAR24 ),
.VAR21( VAR21 ),
.VAR9( VAR9 ),
.VAR32( VAR32 ),
.VAR25( VAR25 ),
.VAR22( VAR22 ),
.VAR41( VAR41 ),
.VAR27( VAR27 ),
.VAR19( VAR19 ),
.VAR33( VAR33 ),
.VAR7( VAR7 ),
.VAR23( VAR23 ),
.VAR20( VAR20 )
);
end
else begin : VAR16
assign VAR7 = 1'b0;
assign VAR33 = VAR37;
assign VAR21 = VAR17;
end
endgenerate
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o311ai/sky130_fd_sc_ls__o311ai.functional.v
| 1,481 |
module MODULE1 (
VAR2 ,
VAR6,
VAR11,
VAR4,
VAR5,
VAR3
);
output VAR2 ;
input VAR6;
input VAR11;
input VAR4;
input VAR5;
input VAR3;
wire VAR7 ;
wire VAR8;
or VAR9 (VAR7 , VAR11, VAR6, VAR4 );
nand VAR1 (VAR8, VAR3, VAR7, VAR5);
buf VAR10 (VAR2 , VAR8 );
endmodule
|
apache-2.0
|
hcabrera-/lancetfish
|
RTL/processing_element/des_engine/rtl/des_sbox7.v
| 3,336 |
module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd4;
4'd1: VAR2 = 4'd11;
4'd2: VAR2 = 4'd2;
4'd3: VAR2 = 4'd14;
4'd4: VAR2 = 4'd15;
4'd5: VAR2 = 4'd0;
4'd6: VAR2 = 4'd8;
4'd7: VAR2 = 4'd13;
4'd8: VAR2 = 4'd3;
4'd9: VAR2 = 4'd12;
4'd10: VAR2 = 4'd9;
4'd11: VAR2 = 4'd7;
4'd12: VAR2 = 4'd5;
4'd13: VAR2 = 4'd10;
4'd14: VAR2 = 4'd6;
4'd15: VAR2 = 4'd1;
endcase
2'b01:
case (VAR1[1:4])
4'd0: VAR2 = 4'd13;
4'd1: VAR2 = 4'd0;
4'd2: VAR2 = 4'd11;
4'd3: VAR2 = 4'd7;
4'd4: VAR2 = 4'd4;
4'd5: VAR2 = 4'd9;
4'd6: VAR2 = 4'd1;
4'd7: VAR2 = 4'd10;
4'd8: VAR2 = 4'd14;
4'd9: VAR2 = 4'd3;
4'd10: VAR2 = 4'd5;
4'd11: VAR2 = 4'd12;
4'd12: VAR2 = 4'd2;
4'd13: VAR2 = 4'd15;
4'd14: VAR2 = 4'd8;
4'd15: VAR2 = 4'd6;
endcase
2'b10:
case (VAR1[1:4])
4'd0: VAR2 = 4'd1;
4'd1: VAR2 = 4'd4;
4'd2: VAR2 = 4'd11;
4'd3: VAR2 = 4'd13;
4'd4: VAR2 = 4'd12;
4'd5: VAR2 = 4'd3;
4'd6: VAR2 = 4'd7;
4'd7: VAR2 = 4'd14;
4'd8: VAR2 = 4'd10;
4'd9: VAR2 = 4'd15;
4'd10: VAR2 = 4'd6;
4'd11: VAR2 = 4'd8;
4'd12: VAR2 = 4'd0;
4'd13: VAR2 = 4'd5;
4'd14: VAR2 = 4'd9;
4'd15: VAR2 = 4'd2;
endcase
2'b11:
case (VAR1[1:4])
4'd0: VAR2 = 4'd6;
4'd1: VAR2 = 4'd11;
4'd2: VAR2 = 4'd13;
4'd3: VAR2 = 4'd8;
4'd4: VAR2 = 4'd1;
4'd5: VAR2 = 4'd4;
4'd6: VAR2 = 4'd10;
4'd7: VAR2 = 4'd7;
4'd8: VAR2 = 4'd9;
4'd9: VAR2 = 4'd5;
4'd10: VAR2 = 4'd0;
4'd11: VAR2 = 4'd15;
4'd12: VAR2 = 4'd14;
4'd13: VAR2 = 4'd2;
4'd14: VAR2 = 4'd3;
4'd15: VAR2 = 4'd12;
endcase
endcase
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/a22oi/sky130_fd_sc_hvl__a22oi.functional.v
| 1,549 |
module MODULE1 (
VAR8 ,
VAR7,
VAR12,
VAR2,
VAR5
);
output VAR8 ;
input VAR7;
input VAR12;
input VAR2;
input VAR5;
wire VAR9 ;
wire VAR11 ;
wire VAR10;
nand VAR3 (VAR9 , VAR12, VAR7 );
nand VAR1 (VAR11 , VAR5, VAR2 );
and VAR6 (VAR10, VAR9, VAR11);
buf VAR4 (VAR8 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.v
| 2,154 |
module MODULE1 (
VAR7,
VAR8,
VAR4 ,
VAR9,
VAR6,
VAR3 ,
VAR1
);
output VAR7;
input VAR8;
input VAR4 ;
input VAR9;
input VAR6;
input VAR3 ;
input VAR1 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR8,
VAR4
);
output VAR7;
input VAR8;
input VAR4 ;
supply1 VAR9;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
tejchava1460/Evaluation-Project-for-ASIC-FPGA-Design-Engineer
|
Verilog_Noise_generator/main.v
| 1,545 |
module MODULE1(clk, reset, VAR1, VAR11, VAR23, VAR14, VAR22, VAR6, VAR28, VAR20);
input clk, reset;
input [31:0]VAR1, VAR11, VAR23, VAR14, VAR22, VAR6;
output [15:0]VAR28, VAR20;
wire [31:0]VAR35, VAR7;
wire [47:0]VAR33;
wire [15:0]VAR2, VAR36, VAR26, VAR36, VAR26;
wire [30:0]VAR29;
wire [16:0]VAR16;
wire [1:0]VAR13, VAR13;
VAR19 VAR32(.clk(clk), .reset(reset), .VAR17(VAR1), .VAR15(VAR11), .VAR25(VAR23), .VAR38(VAR35));
VAR19 VAR5(.clk(clk), .reset(reset), .VAR17(VAR14), .VAR15(VAR22), .VAR25(VAR6), .VAR38(VAR7));
VAR18 VAR30(.clk(clk), .VAR33(VAR33), .VAR2(VAR2), .VAR34(VAR35), .VAR10(VAR7));
VAR12 VAR21(.clk(clk), .VAR33(VAR33), .VAR29(VAR29));
VAR37 VAR3(.clk(clk), .VAR2(VAR2), .VAR36(VAR36), .VAR26(VAR26), .VAR13(VAR13));
VAR9 VAR27(.clk(clk), .VAR29(VAR29), .VAR16(VAR16), .VAR36(VAR36), .VAR26(VAR26), .VAR36(VAR36), .VAR26(VAR26), .VAR13(VAR13), .VAR13(VAR13));
VAR24 VAR8(.clk(clk), .VAR16(VAR16), .VAR36(VAR36), .VAR26(VAR26), .VAR4(VAR28), .VAR31(VAR20), .VAR13(VAR13));
endmodule
|
gpl-3.0
|
efabless/openlane
|
designs/jpeg_encoder/src/div_uu.v
| 5,855 |
module MODULE1(clk, VAR8, VAR7, VAR3, VAR12, VAR10, VAR2, VAR15);
parameter VAR17 = 16;
parameter VAR19 = VAR17 /2;
input clk; input VAR8;
input [VAR17 -1:0] VAR7; input [VAR19 -1:0] VAR3; output [VAR19 -1:0] VAR12; reg [VAR19-1:0] VAR12;
output [VAR19 -1:0] VAR10; reg [VAR19-1:0] VAR10;
output VAR2;
reg VAR2;
output VAR15;
reg VAR15;
function [VAR17:0] VAR1;
input [VAR17:0] VAR9;
input [VAR17:0] VAR5;
begin
if(VAR9[VAR17])
VAR1 = {VAR9[VAR17-1:0], 1'b0} + VAR5;
end
else
VAR1 = {VAR9[VAR17-1:0], 1'b0} - VAR5;
end
endfunction
function [VAR19-1:0] VAR14;
input [VAR19-1:0] VAR20;
input [VAR17:0] VAR9;
begin
VAR14 = {VAR20[VAR19-2:0], ~VAR9[VAR17]};
end
endfunction
function [VAR19-1:0] VAR21;
input [VAR17:0] VAR9;
input [VAR17:0] VAR5;
reg [VAR17:0] VAR11;
begin
if(VAR9[VAR17])
VAR11 = VAR9 + VAR5;
end
else
VAR11 = VAR9;
VAR21 = VAR11[VAR17-1:VAR17-4];
end
endfunction
reg [VAR19-1:0] VAR13 [VAR19-1:0];
reg [VAR17:0] VAR18 [VAR19:0];
reg [VAR17:0] VAR6 [VAR19:0];
reg [VAR19:0] VAR16, VAR4;
begin
begin
begin
|
apache-2.0
|
tmolteno/TART
|
hardware/FPGA/ddr_controller/spartan3/rtl/cmp_data.v
| 4,607 |
module MODULE1(
clk,
VAR6,
VAR3,
VAR4,
rst,
VAR10,
VAR9,
VAR7,
VAR1
);
input clk;
input VAR6;
input [143:0]VAR3;
input [143:0]VAR4;
input rst;
output [143:0] VAR10;
output [143:0] VAR9;
output VAR7;
output VAR1;
reg VAR5;
reg valid;
reg VAR8;
wire VAR12;
reg [3:0]VAR11;
reg [143:0] VAR2;
always @ (posedge clk)
begin
if (rst == 1'b1)
VAR11 <= 4'd0;
end
else begin
if(VAR2[35:0] != VAR3[35:0])
VAR11[0] <= 1'b1;
end
else
VAR11[0] <= 1'b0;
if(VAR2[71:36] != VAR3[71:36])
VAR11[1] <= 1'b1;
else
VAR11[1] <= 1'b0;
if(VAR2[107:72] != VAR3[107:72])
VAR11[2] <= 1'b1;
else
VAR11[2] <= 1'b0;
if(VAR2[143:108] != VAR3[143:108])
VAR11[3] <= 1'b1;
else
VAR11[3] <= 1'b0;
end
end
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
VAR8 <= 1'b0;
valid <= 1'b0;
VAR2 <= 144'd0;
end
else
begin
valid <= VAR6;
VAR8 <= valid;
VAR2 <= VAR4;
end
end
assign VAR1 = valid;
assign VAR10 = VAR2;
assign VAR9 = VAR3;
assign VAR12 = ( VAR8 && (|VAR11[3:0]));
always @ (posedge clk)
begin
if (rst == 1'b1)
end
VAR5 <= 1'b0; else
begin
case(VAR5)
1'b0 : begin
if (VAR12 == 1'b1)
end
VAR5 <= 1'b1; else
VAR5 <= 1'b0; end
1'b1 : VAR5 <= 1'b1;
default : VAR5 <= 1'b0;
endcase
end
end
assign VAR7 = (VAR5 == 1'b1) ? 1'b1 : 1'b0;
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_p_pp_pkg_sn.blackbox.v
| 1,477 |
module MODULE1 (
VAR3 ,
VAR5 ,
VAR2 ,
VAR7 ,
VAR6,
VAR4 ,
VAR1 ,
VAR8
);
output VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR6;
input VAR4 ;
input VAR1 ;
input VAR8 ;
endmodule
|
apache-2.0
|
markusC64/1541ultimate2
|
fpga/nios_c5/nios/synthesis/submodules/rw_manager_ac_ROM_reg.v
| 1,407 |
module MODULE1(
VAR7,
VAR1,
VAR5,
VAR8,
VAR2,
VAR4);
parameter VAR9 = "";
parameter VAR3 = "";
input [(VAR3-1):0] VAR7;
input VAR1;
input [(VAR3-1):0] VAR5;
input [(VAR9-1):0] VAR8;
input VAR2;
output reg [(VAR9-1):0] VAR4;
reg [(VAR9-1):0] VAR6[(2**VAR3-1):0];
always @(posedge VAR1)
begin
if(VAR2)
VAR6[VAR5] <= VAR8;
VAR4 <= VAR6[VAR7];
end
endmodule
|
gpl-3.0
|
hhuang25/uwaterloo_ece224
|
Lab1/timer_0.v
| 6,613 |
module MODULE1 (
address,
VAR30,
clk,
VAR11,
VAR32,
VAR21,
irq,
VAR3
)
;
output irq;
output [ 15: 0] VAR3;
input [ 2: 0] address;
input VAR30;
input clk;
input VAR11;
input VAR32;
input [ 15: 0] VAR21;
wire VAR9;
wire VAR12;
wire VAR8;
reg [ 3: 0] VAR6;
wire VAR4;
reg VAR31;
wire VAR18;
wire [ 31: 0] VAR20;
reg [ 31: 0] VAR19;
reg VAR14;
wire VAR29;
wire VAR25;
reg VAR15;
reg [ 31: 0] VAR2;
wire irq;
reg [ 15: 0] VAR28;
wire VAR5;
reg [ 15: 0] VAR23;
wire VAR1;
wire [ 15: 0] VAR7;
reg [ 15: 0] VAR3;
wire VAR17;
wire VAR27;
wire [ 31: 0] VAR16;
wire VAR24;
wire VAR33;
wire VAR10;
wire VAR22;
wire VAR13;
reg VAR26;
assign VAR9 = 1;
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR2 <= 32'hC34F;
end
else if (VAR31 || VAR15)
if (VAR18 || VAR15)
VAR2 <= VAR20;
else
VAR2 <= VAR2 - 1;
end
assign VAR18 = VAR2 == 0;
assign VAR20 = {VAR28,
VAR23};
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR15 <= 0;
end
else if (VAR9)
VAR15 <= VAR5 || VAR1;
end
assign VAR29 = VAR33;
assign VAR25 = (VAR22 ) ||
(VAR15 ) ||
(VAR18 && ~VAR12 );
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR31 <= 1'b0;
end
else if (VAR9)
if (VAR29)
VAR31 <= -1;
else if (VAR25)
VAR31 <= 0;
end
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR14 <= 0;
end
else if (VAR9)
VAR14 <= VAR18;
end
assign VAR13 = (VAR18) & ~(VAR14);
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR26 <= 0;
end
else if (VAR9)
if (VAR10)
VAR26 <= 0;
else if (VAR13)
VAR26 <= -1;
end
assign irq = VAR26 && VAR8;
assign VAR7 = ({16 {(address == 2)}} & VAR23) |
({16 {(address == 3)}} & VAR28) |
({16 {(address == 4)}} & VAR16[15 : 0]) |
({16 {(address == 5)}} & VAR16[31 : 16]) |
({16 {(address == 1)}} & VAR6) |
({16 {(address == 0)}} & {VAR31,
VAR26});
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR3 <= 0;
end
else if (VAR9)
VAR3 <= VAR7;
end
assign VAR1 = VAR30 && ~VAR32 && (address == 2);
assign VAR5 = VAR30 && ~VAR32 && (address == 3);
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR23 <= 49999;
end
else if (VAR1)
VAR23 <= VAR21;
end
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR28 <= 0;
end
else if (VAR5)
VAR28 <= VAR21;
end
assign VAR27 = VAR30 && ~VAR32 && (address == 4);
assign VAR17 = VAR30 && ~VAR32 && (address == 5);
assign VAR24 = VAR27 || VAR17;
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR19 <= 0;
end
else if (VAR24)
VAR19 <= VAR2;
end
assign VAR16 = VAR19;
assign VAR4 = VAR30 && ~VAR32 && (address == 1);
always @(posedge clk or negedge VAR11)
begin
if (VAR11 == 0)
VAR6 <= 0;
end
else if (VAR4)
VAR6 <= VAR21[3 : 0];
end
assign VAR22 = VAR21[3] && VAR4;
assign VAR33 = VAR21[2] && VAR4;
assign VAR12 = VAR6[1];
assign VAR8 = VAR6;
assign VAR10 = VAR30 && ~VAR32 && (address == 0);
endmodule
|
mit
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/ex_stage.v
| 4,555 |
module MODULE1 (
input wire clk, input wire reset,
input wire VAR21, input wire VAR29, input wire VAR10,
output wire [VAR4] VAR34,
input wire [VAR32] VAR3, input wire VAR13, input wire [VAR31] VAR22, input wire [VAR4] VAR37, input wire [VAR4] VAR16, input wire VAR40, input wire [VAR17] VAR19, input wire [VAR4] VAR11, input wire [VAR15] VAR20, input wire [VAR23] VAR28, input wire VAR36, input wire [VAR8] VAR9,
output wire [VAR32] VAR39, output wire VAR2, output wire VAR27, output wire [VAR17] VAR35, output wire [VAR4] VAR1, output wire [VAR15] VAR18, output wire [VAR23] VAR5, output wire VAR38, output wire [VAR8] VAR24, output wire [VAR4] VAR33 );
wire [VAR4] VAR30; wire VAR12;
assign VAR34 = VAR30;
alu alu (
.VAR25 (VAR37), .VAR6 (VAR16), .VAR7 (VAR22), .out (VAR30), .VAR26 (VAR12) );
VAR14 VAR14 (
.clk (clk), .reset (reset),
.VAR30 (VAR30), .VAR12 (VAR12),
.VAR21 (VAR21), .VAR29 (VAR29), .VAR10 (VAR10),
.VAR3 (VAR3), .VAR13 (VAR13), .VAR40 (VAR40), .VAR19 (VAR19), .VAR11 (VAR11), .VAR20 (VAR20), .VAR28 (VAR28), .VAR36 (VAR36), .VAR9 (VAR9),
.VAR39 (VAR39), .VAR2 (VAR2), .VAR27 (VAR27), .VAR35 (VAR35), .VAR1 (VAR1), .VAR18 (VAR18), .VAR5 (VAR5), .VAR38 (VAR38), .VAR24 (VAR24), .VAR33 (VAR33) );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o21ba/sky130_fd_sc_ms__o21ba.functional.pp.v
| 2,037 |
module MODULE1 (
VAR15 ,
VAR5 ,
VAR13 ,
VAR16,
VAR12,
VAR14,
VAR10 ,
VAR3
);
output VAR15 ;
input VAR5 ;
input VAR13 ;
input VAR16;
input VAR12;
input VAR14;
input VAR10 ;
input VAR3 ;
wire VAR4 ;
wire VAR1 ;
wire VAR9;
nor VAR8 (VAR4 , VAR5, VAR13 );
nor VAR2 (VAR1 , VAR16, VAR4 );
VAR11 VAR7 (VAR9, VAR1, VAR12, VAR14);
buf VAR6 (VAR15 , VAR9 );
endmodule
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/GDA_St_N8_M8_P5.v
| 3,596 |
module MODULE1(
input [7:0] VAR9,
input [7:0] VAR16,
output [8:0] VAR104
);
wire [2:0] VAR22, VAR28, VAR43, VAR93, VAR7, VAR65, VAR96, VAR116;
wire VAR13,VAR100,VAR15,VAR2,VAR59,VAR62,VAR36,VAR79,VAR24,VAR30,VAR25,VAR60,VAR33,VAR32,VAR115,VAR27,VAR55,VAR72,VAR94,VAR49,VAR92;
wire VAR45,VAR38,VAR20,VAR17,VAR57,VAR103,VAR64,VAR77,VAR46,VAR89,VAR70,VAR87,VAR101,VAR99,VAR34,VAR108;
wire VAR6,VAR12;
wire VAR113,VAR5,VAR84,VAR80,VAR58,VAR40;
wire VAR8;
wire VAR10,VAR1;
wire VAR107,VAR50,VAR56;
wire VAR82,VAR52,VAR35;
wire VAR19,VAR3,VAR42;
and VAR68(VAR79,VAR9[0],VAR16[0]);
and VAR54(VAR24,VAR9[1],VAR16[1]);
and VAR39(VAR30,VAR9[2],VAR16[2]);
and VAR71(VAR25,VAR9[3],VAR16[3]);
and VAR78(VAR60,VAR9[4],VAR16[4]);
and VAR114(VAR33,VAR9[5],VAR16[5]);
and VAR23(VAR32,VAR9[6],VAR16[6]);
xor VAR37(VAR13,VAR9[0],VAR16[0]);
xor VAR21(VAR100,VAR9[1],VAR16[1]);
xor VAR14(VAR15,VAR9[2],VAR16[2]);
xor VAR109(VAR2,VAR9[3],VAR16[3]);
xor VAR69(VAR59,VAR9[4],VAR16[4]);
xor VAR18(VAR62,VAR9[5],VAR16[5]);
xor VAR97(VAR36,VAR9[6],VAR16[6]);
assign VAR115 = VAR79;
assign VAR27 = VAR24;
and VAR105(VAR45,VAR100,VAR115);
or VAR66(VAR113,VAR27,VAR45);
assign VAR55 = VAR30;
and VAR76(VAR38,VAR15,VAR27);
and VAR48(VAR64,VAR15,VAR45);
or VAR117(VAR8,VAR38,VAR64);
or VAR73(VAR5,VAR55,VAR8);
assign VAR72 = VAR25;
and VAR31(VAR20,VAR2,VAR55);
and VAR91(VAR77,VAR2,VAR38);
and VAR111(VAR87,VAR2,VAR64);
or VAR90(VAR10,VAR77,VAR87);
or VAR102(VAR1,VAR20,VAR10);
or VAR88(VAR84,VAR72,VAR1);
assign VAR94 = VAR60;
and VAR118(VAR17,VAR59,VAR72);
and VAR4(VAR46,VAR59,VAR20);
and VAR26(VAR101,VAR59,VAR77);
and VAR85(VAR99,VAR59,VAR87);
or VAR83(VAR107,VAR101,VAR99);
or VAR41(VAR50,VAR46,VAR107);
or VAR81(VAR56,VAR17,VAR50);
or VAR67(VAR80,VAR94,VAR56);
assign VAR49 = VAR33;
and VAR63(VAR57,VAR62,VAR94);
and VAR98(VAR89,VAR62,VAR17);
and VAR61(VAR34,VAR62,VAR46);
and VAR47(VAR108,VAR62,VAR101);
or VAR112(VAR82,VAR34,VAR108);
or VAR74(VAR52,VAR89,VAR82);
or VAR75(VAR35,VAR57,VAR52);
or VAR110(VAR58,VAR49,VAR35);
assign VAR92 = VAR32;
and VAR11(VAR103,VAR36,VAR49);
and VAR44(VAR70,VAR36,VAR57);
and VAR53(VAR6,VAR36,VAR89);
and VAR86(VAR12,VAR36,VAR34);
or VAR51(VAR19,VAR6,VAR12);
or VAR29(VAR3,VAR70,VAR19);
or VAR95(VAR42,VAR103,VAR3);
or VAR106(VAR40,VAR92,VAR42);
assign VAR22[1:0] = VAR9[0] + VAR16[0];
assign VAR28[1:0] = VAR9[1] + VAR16[1] + VAR115;
assign VAR43[1:0] = VAR9[2] + VAR16[2] + VAR113;
assign VAR93[1:0] = VAR9[3] + VAR16[3] + VAR5;
assign VAR7[1:0] = VAR9[4] + VAR16[4] + VAR84;
assign VAR65[1:0] = VAR9[5] + VAR16[5] + VAR80;
assign VAR96[1:0] = VAR9[6] + VAR16[6] + VAR58;
assign VAR116[1:0] = VAR9[7] + VAR16[7] + VAR40;
assign VAR104[8:0] = {VAR116[1:0],VAR96[0],VAR65[0],VAR7[0],VAR93[0],VAR43[0],VAR28[0],VAR22[0]};
endmodule
|
gpl-3.0
|
GREO/gnuradio-git
|
gr-gpio/src/fpga/lib/rx_chain_dig.v
| 1,512 |
module MODULE1
(input VAR5,
input reset,
input enable,
input wire [15:0] VAR6,
input wire [15:0] VAR2,
input wire VAR1,
input wire VAR4,
output wire [15:0] VAR7,
output wire [15:0] VAR3
);
assign VAR7 = (enable)?{VAR6[15:1],VAR1}:VAR6;
assign VAR3 = (enable)?{VAR2[15:1],VAR4}:VAR2;
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.behavioral.pp.v
| 1,241 |
module MODULE1( VAR7, VAR1, VAR8, VAR2, VAR3 );
input VAR7, VAR1;
inout VAR2, VAR3;
output VAR8;
VAR6 VAR4(.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3));
VAR6 VAR5(.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3));
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_and.v
| 1,545 |
if (VAR7 && (VAR3==VAR12)) \
begin: VAR2 \
VAR4 VAR5 (.VAR9(VAR10),.VAR14(VAR11),.VAR6); \
end
module MODULE1 #(parameter VAR20(VAR3)
, parameter VAR7=0
)
(input [VAR3-1:0] VAR10
, input [VAR3-1:0] VAR11
, output [VAR3-1:0] VAR6
);
begin :VAR1
end
VAR16 assert(VAR7==0) else ("## %VAR13 VAR8 VAR17 VAR15 VAR18 VAR19 VAR2");
assign VAR6 = VAR10 & VAR11;
end
endmodule
|
bsd-3-clause
|
Fabeltranm/FPGA-Game-D1
|
HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/Bloquetouch/FIFO/fifo.v
| 2,590 |
module MODULE1
parameter VAR11 = 4,
parameter VAR17 = 8
)
(
input clk, reset,
input rd, wr,
input [VAR17-1:0] VAR18,
output [VAR17-1:0] VAR1,
output VAR3,
output VAR16
);
parameter VAR7 = (1 << VAR11);
reg [VAR17-1:0] VAR4 [VAR7-1:0];
reg [VAR11-1:0] VAR2, VAR14;
reg [VAR11-1:0] VAR12, VAR5;
reg VAR15, VAR10, VAR13, VAR8;
wire VAR6;
reg [1:0] VAR9;
assign VAR1 = VAR4[VAR12];
assign VAR6 = wr & ~VAR15;
assign VAR16 = VAR15;
assign VAR3 = VAR10;
always @(posedge clk) begin
if (VAR6)
VAR4[VAR2] <= VAR18;
end
always @(posedge clk, posedge reset) begin
if (reset)
begin
VAR2 <= 0;
VAR12 <= 0;
VAR15 <= 1'b0;
VAR10 <= 1'b1;
end
else
begin
VAR2 <= VAR14;
VAR12 <= VAR5;
VAR15 <= VAR13;
VAR10 <= VAR8;
end
end
always @(posedge clk)
begin
if(!wr&&rd)
begin
VAR9 = 2'b01;
end
if(wr&&!rd)
begin
VAR9 = 2'b10;
end
if(wr&&rd)
begin
VAR9 = 2'b11;
end
end
always @(posedge clk)
begin
if (reset) begin
VAR14 = 0;
VAR5 = 0;
end else begin
VAR13 = VAR15;
VAR8 = VAR10;
case (VAR9)
2'b01: if (~VAR10) begin
VAR5 = VAR12 + 1;
VAR13 = 1'b0;
if (VAR5==VAR2)
VAR8 = 1'b1;
end
2'b10: if (~VAR15) begin
VAR14 = VAR2 + 1;
VAR8 = 1'b0;
if (VAR14==VAR12)
VAR13 = 1'b1;
end
2'b11: begin
VAR14 = VAR2 + 1;
VAR5 = VAR12 + 1;
end
endcase
end
end
endmodule
|
gpl-3.0
|
efabless/openlane
|
designs/digital_pll_sky130_fd_sc_hd/src/digital_pll_controller.v
| 4,530 |
module MODULE1(reset, VAR6, VAR9, VAR10, VAR3);
input reset;
input VAR6;
input VAR9;
input [4:0] VAR10;
output [25:0] VAR3;
wire [25:0] VAR3;
reg [2:0] VAR1;
reg [2:0] VAR7;
reg [4:0] VAR2;
reg [4:0] VAR4;
reg [6:0] VAR5; wire [4:0] VAR8;
wire [5:0] sum;
assign sum = VAR2 + VAR4;
assign VAR8 = VAR5[6:2];
assign VAR3 = (VAR8 == 5'd0) ? 26'b00000000000000000000000000 :
(VAR8 == 5'd1) ? 26'b00000000000000000000000001 :
(VAR8 == 5'd2) ? 26'b00000000000000000001000001 :
(VAR8 == 5'd3) ? 26'b00000000000000010001000001 :
(VAR8 == 5'd4) ? 26'b00000000000000010001001001 :
(VAR8 == 5'd5) ? 26'b00000000000000010101001001 :
(VAR8 == 5'd6) ? 26'b00000000000001010101001001 :
(VAR8 == 5'd7) ? 26'b00000000000001010101101001 :
(VAR8 == 5'd8) ? 26'b00000000000001010101101101 :
(VAR8 == 5'd9) ? 26'b00000000000001011101101101 :
(VAR8 == 5'd10) ? 26'b00000000000001011101111101 :
(VAR8 == 5'd11) ? 26'b00000000000001111101111101 :
(VAR8 == 5'd12) ? 26'b00000000000001111101111111 :
(VAR8 == 5'd13) ? 26'b00000000000001111111111111 :
(VAR8 == 5'd14) ? 26'b00000000000011111111111111 :
(VAR8 == 5'd15) ? 26'b00000010000011111111111111 :
(VAR8 == 5'd16) ? 26'b00100010000011111111111111 :
(VAR8 == 5'd17) ? 26'b00100010010011111111111111 :
(VAR8 == 5'd18) ? 26'b00101010010011111111111111 :
(VAR8 == 5'd19) ? 26'b10101010010011111111111111 :
(VAR8 == 5'd20) ? 26'b10101011010011111111111111 :
(VAR8 == 5'd21) ? 26'b10101011011011111111111111 :
(VAR8 == 5'd22) ? 26'b10111011011011111111111111 :
(VAR8 == 5'd23) ? 26'b10111011111011111111111111 :
(VAR8 == 5'd24) ? 26'b11111011111011111111111111 :
(VAR8 == 5'd25) ? 26'b11111011111111111111111111 :
26'b11111111111111111111111111;
always @(posedge VAR6 or posedge reset) begin
if (reset == 1'b1) begin
VAR5 <= 7'd0; VAR1 <= 3'd0;
VAR7 <= 3'd0;
VAR2 <= 5'd0;
VAR4 <= 5'd0;
end else begin
VAR1 <= {VAR1[1:0], VAR9};
if (VAR1[2] != VAR1[1]) begin
VAR4 <= VAR2;
VAR2 <= 5'b00001;
VAR7 <= {VAR7[1:0], 1'b1};
if (VAR7 == 3'b111) begin
if (sum > VAR10) begin
VAR5 <= VAR5 + 1;
end else if (sum < VAR10) begin
VAR5 <= VAR5 - 1;
end
end
end else begin
if (VAR2 != 5'b11111) begin
VAR2 <= VAR2 + 1;
end
end
end
end
endmodule
|
apache-2.0
|
YosysHQ/yosys
|
techlibs/efinix/brams_map.v
| 3,603 |
module MODULE1 (...);
parameter VAR35 = 0;
parameter VAR21 = "VAR28";
parameter VAR60 = 20;
parameter VAR42 = 1;
parameter VAR27 = 20;
parameter VAR4 = 1;
input VAR44;
input VAR9;
input [11:0] VAR49;
output [VAR60-1:0] VAR51;
input VAR40;
input VAR3;
input [11:0] VAR18;
input [VAR27-1:0] VAR52;
localparam VAR31 = VAR60 >= 5 && VAR27 >= 5;
localparam VAR53 =
VAR60 == 1 ? 12 :
VAR60 == 2 ? 11 :
VAR60 == 5 ? 10 :
VAR60 == 10 ? 9 :
8;
localparam VAR57 =
VAR27 == 1 ? 12 :
VAR27 == 2 ? 11 :
VAR27 == 5 ? 10 :
VAR27 == 10 ? 9 :
8;
localparam VAR26 =
VAR60 == 1 ? 1 :
VAR60 == 2 ? 2 :
VAR60 == 5 ? (VAR31 ? 5 : 4) :
VAR60 == 10 ? (VAR31 ? 10 : 8) :
(VAR31 ? 20 : 16);
localparam VAR58 =
VAR27 == 1 ? 1 :
VAR27 == 2 ? 2 :
VAR27 == 5 ? (VAR31 ? 5 : 4) :
VAR27 == 10 ? (VAR31 ? 10 : 8) :
(VAR31 ? 20 : 16);
wire [VAR53-1:0] VAR45 = VAR49[11:12-VAR53];
wire [VAR57-1:0] VAR39 = VAR18[11:12-VAR57];
wire [VAR58-1:0] VAR43;
wire [VAR26-1:0] VAR48;
generate
case (VAR58)
1: assign VAR43 = VAR52;
2: assign VAR43 = VAR52;
4: assign VAR43 = VAR52[3:0];
5: assign VAR43 = VAR52;
8: assign VAR43 = {
VAR52[8:5],
VAR52[3:0]
};
10: assign VAR43 = VAR52;
16: assign VAR43 = {
VAR52[18:15],
VAR52[13:10],
VAR52[8:5],
VAR52[3:0]
};
20: assign VAR43 = VAR52;
endcase
case (VAR26)
1: assign VAR51 = VAR48;
2: assign VAR51 = VAR48;
4: assign VAR51[3:0] = VAR48;
5: assign VAR51 = VAR48;
8: assign {
VAR51[8:5],
VAR51[3:0]
} = VAR48;
10: assign VAR51 = VAR48;
16: assign {
VAR51[18:15],
VAR51[13:10],
VAR51[8:5],
VAR51[3:0]
} = VAR48;
20: assign VAR51 = VAR48;
endcase
endgenerate
function [255:0] VAR16;
input integer VAR59;
integer VAR11;
if (VAR31)
VAR16 = VAR35[VAR59 * 256 +: 256];
else if (VAR59 > 16)
VAR16 = 0;
else
for (VAR11 = 0; VAR11 < 64; VAR11 = VAR11 + 1)
VAR16[VAR11*4+:4] = VAR35[(VAR59 * 64 + VAR11) * 5+:4];
endfunction
VAR61 #(
.VAR26(VAR26),
.VAR58(VAR58),
.VAR54(1'b0),
.VAR47(VAR42),
.VAR13(1'b1),
.VAR24(VAR4),
.VAR5(1'b1),
.VAR56(1'b1),
.VAR33(VAR21),
.VAR29(VAR16('h00)),
.VAR32(VAR16('h01)),
.VAR22(VAR16('h02)),
.VAR1(VAR16('h03)),
.VAR6(VAR16('h04)),
.VAR38(VAR16('h05)),
.VAR14(VAR16('h06)),
.VAR30(VAR16('h07)),
.VAR7(VAR16('h08)),
.VAR36(VAR16('h09)),
.VAR10(VAR16('h0a)),
.VAR19(VAR16('h0b)),
.VAR15(VAR16('h0c)),
.VAR8(VAR16('h0d)),
.VAR37(VAR16('h0e)),
.VAR50(VAR16('h0f)),
.VAR41(VAR16('h10)),
.VAR20(VAR16('h11)),
.VAR55(VAR16('h12)),
.VAR25(VAR16('h13)),
) VAR46 (
.VAR43(VAR43),
.VAR39(VAR39),
.VAR2(VAR3),
.VAR34(VAR40),
.VAR17(1'b1),
.VAR48(VAR48),
.VAR45(VAR45),
.VAR23(VAR9),
.VAR12(VAR44)
);
endmodule
|
isc
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/nor2b/sky130_fd_sc_hd__nor2b.blackbox.v
| 1,307 |
module MODULE1 (
VAR1 ,
VAR5 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR6;
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v
| 19,765 |
module MODULE1 #
(
parameter VAR68 = 100,
parameter VAR14 = "VAR10",
parameter VAR104 = "1T",
parameter VAR106 = 11,
parameter VAR15 = 3,
parameter VAR95 = "8",
parameter VAR59 = 4,
parameter VAR9 = 5,
parameter VAR30 = 5,
parameter VAR71 = 31,
parameter VAR6 = 8,
parameter VAR57 = "VAR111",
parameter VAR107 = "VAR51", parameter VAR28 = "VAR10",
parameter VAR32 = "VAR10",
parameter VAR65 = 4,
parameter VAR88 = 2, parameter VAR11 = 1,
parameter VAR123 = 37500, parameter VAR109 = 12500, parameter VAR118 = 2,
parameter VAR42 = 6, parameter VAR119 = 1,
parameter VAR31 = 15,
parameter VAR86 = 2,
parameter VAR77 = 63,
parameter VAR117 = 16,
parameter VAR70 = "40",
parameter VAR43 = "120",
parameter VAR45 = 8'b00000101,
parameter VAR54 = 8'b00001010
)
(
output [VAR117-1:0] VAR99, output [VAR15-1:0] VAR63, output [VAR6-1:0] VAR97, output VAR13, output [VAR86-1:0] VAR80, output VAR53, output VAR113,
output [VAR117-1:0] VAR3, output VAR108, output [VAR6-1:0] VAR82, output wire [VAR88-1:0] VAR93,
output wire [VAR88-1:0] VAR55,
output wire [VAR88-1:0] VAR58,
output wire [VAR88*VAR117-1:0] VAR52,
output wire [VAR88*VAR15-1:0] VAR87,
output wire [VAR59*VAR11*VAR88-1:0] VAR29,
output wire [1:0] VAR120,
output wire [VAR88-1:0] VAR110,
output wire [3:0] VAR81,
output wire [3:0] VAR36,
output [2:0] VAR78,
output [5:0] VAR98,
output [5:0] VAR46,
output [5:0] VAR50,
output [1:0] VAR19,
output [VAR86-1:0] VAR1, output VAR12, output [VAR65-1:0] VAR102, output [VAR65-1:0] VAR74,
output VAR121, output VAR37, output VAR92, output [VAR65-1:0] VAR75,
output VAR5,
output VAR105,
output VAR89,
input clk,
input rst,
input VAR100,
input [6*VAR119-1:0] VAR101,
input [6*VAR119-1:0] VAR61,
input [6*VAR119-1:0] VAR16,
input [VAR77:0] VAR90, input [VAR65-1:0] VAR66, input VAR26, input [VAR86-1:0] VAR67, input VAR114, input VAR22, input VAR72, input [VAR65-1:0] VAR35, input [VAR106:0] VAR27, input [VAR65-1:0] VAR8, input [VAR71:0] VAR41, input [VAR65-1:0] VAR33, input [VAR31:0] VAR38, input [VAR65-1:0] VAR94, input [VAR77:0] VAR18, input [VAR65-1:0] VAR103, input [VAR65-1:0] VAR47, input [VAR77:0] VAR64, input [VAR65-1:0] VAR56, input [VAR65-1:0] VAR122, input [VAR65-1:0] VAR116, input [VAR65-1:0] VAR44, input [VAR65-1:0] VAR39, input [7:0] VAR21, input [7:0] VAR115
);
wire VAR69; wire VAR23; wire [VAR65-1:0] VAR34; wire [VAR65-1:0] VAR73; wire [VAR65-1:0] VAR83; wire [VAR65-1:0] VAR79; wire [VAR65-1:0] VAR2; wire VAR60; wire VAR49; wire VAR40; wire VAR91;
wire VAR17;
wire VAR20;
wire VAR76;
wire VAR7;
wire [5:0] VAR48;
wire VAR96;
wire VAR24;
wire VAR85;
assign VAR121 = VAR96;
VAR25 #
(
.VAR68 (VAR68),
.VAR104 (VAR104),
.VAR30 (VAR30),
.VAR28 (VAR28),
.VAR65 (VAR65),
.VAR88 (VAR88),
.VAR123 (VAR123),
.VAR109 (VAR109),
.VAR42 (VAR42))
VAR62
(
.VAR79 (VAR79[VAR65-1:0]),
.VAR2 (VAR2[VAR65-1:0]),
.VAR92 (VAR92),
.VAR102 (VAR102[VAR65-1:0]),
.VAR74 (VAR74[VAR65-1:0]),
.VAR83 (VAR83[VAR65-1:0]),
.VAR5 (VAR5),
.VAR89 (VAR89),
.VAR12 (VAR12),
.VAR34 (VAR34[VAR65-1:0]),
.VAR75 (VAR75[VAR65-1:0]),
.VAR121 (VAR96),
.VAR37 (VAR37),
.VAR73 (VAR73[VAR65-1:0]),
.VAR60 (VAR60),
.VAR49 (VAR49),
.VAR40 (VAR40),
.VAR91 (VAR91),
.VAR17 (VAR17),
.VAR20 (VAR20),
.VAR76 (VAR76),
.VAR7 (VAR7),
.VAR48 (VAR48),
.VAR69 (VAR69),
.VAR23 (VAR23),
.VAR24 (VAR24),
.VAR85 (VAR85),
.VAR105 (VAR105),
.clk (clk),
.rst (rst),
.VAR44 (VAR44[VAR65-1:0]),
.VAR39 (VAR39[VAR65-1:0]),
.VAR26 (VAR26),
.VAR116 (VAR116[VAR65-1:0]),
.VAR122 (VAR122[VAR65-1:0]),
.VAR66 (VAR66[VAR65-1:0]));
VAR4 #
(
.VAR68 (VAR68),
.VAR14 (VAR14),
.VAR104 (VAR104),
.VAR106 (VAR106),
.VAR15 (VAR15),
.VAR95 (VAR95),
.VAR59 (VAR59),
.VAR9 (VAR9),
.VAR30 (VAR30),
.VAR71 (VAR71),
.VAR6 (VAR6),
.VAR57 (VAR57),
.VAR28 (VAR28),
.VAR32 (VAR32),
.VAR107 (VAR107),
.VAR65 (VAR65),
.VAR88 (VAR88),
.VAR11 (VAR11),
.VAR118 (VAR118),
.VAR119 (VAR119),
.VAR31 (VAR31),
.VAR86 (VAR86),
.VAR77 (VAR77),
.VAR117 (VAR117),
.VAR70 (VAR70),
.VAR43 (VAR43),
.VAR45 (VAR45),
.VAR54 (VAR54))
VAR112
(
.VAR13 (VAR13),
.VAR80 (VAR80[VAR86-1:0]),
.VAR63 (VAR63[VAR15-1:0]),
.VAR99 (VAR99[VAR117-1:0]),
.VAR53 (VAR53),
.VAR113 (VAR113),
.VAR108 (VAR108),
.VAR3 (VAR3[VAR117-1:0]),
.VAR97 (VAR97[VAR6-1:0]),
.VAR82 (VAR82[VAR6-1:0]),
.VAR87 (VAR87),
.VAR52 (VAR52),
.VAR93 (VAR93),
.VAR55 (VAR55),
.VAR58 (VAR58),
.VAR29 (VAR29),
.VAR120 (VAR120),
.VAR110 (VAR110),
.VAR81 (VAR81),
.VAR36 (VAR36),
.VAR78 (VAR78),
.VAR98 (VAR98),
.VAR46 (VAR46),
.VAR50 (VAR50),
.VAR19 (VAR19),
.VAR48 (VAR48),
.VAR1 (VAR1),
.clk (clk),
.rst (rst),
.VAR100 (VAR100),
.VAR101 (VAR101),
.VAR61 (VAR61),
.VAR16 (VAR16),
.VAR38 (VAR38[VAR31:0]),
.VAR27 (VAR27[VAR106:0]),
.VAR94 (VAR94[VAR65-1:0]),
.VAR8 (VAR8[VAR65-1:0]),
.VAR47 (VAR47[VAR65-1:0]),
.VAR79 (VAR79[VAR65-1:0]),
.VAR2 (VAR2[VAR65-1:0]),
.VAR64 (VAR64[VAR77:0]),
.VAR56 (VAR56[VAR65-1:0]),
.VAR105 (VAR105),
.VAR114 (VAR114),
.VAR22 (VAR22),
.VAR72 (VAR72),
.VAR67 (VAR67[VAR86-1:0]),
.VAR33 (VAR33[VAR65-1:0]),
.VAR103 (VAR103[VAR65-1:0]),
.VAR35 (VAR35[VAR65-1:0]),
.VAR18 (VAR18[VAR77:0]),
.VAR90 (VAR90[VAR77:0]),
.VAR41 (VAR41[VAR71:0]),
.VAR34 (VAR34[VAR65-1:0]),
.VAR73 (VAR73[VAR65-1:0]),
.VAR60 (VAR60),
.VAR49 (VAR49),
.VAR40 (VAR40),
.VAR91 (VAR91),
.VAR17 (VAR17),
.VAR20 (VAR20),
.VAR76 (VAR76),
.VAR7 (VAR7),
.VAR121 (VAR14 == "VAR84" ? VAR37 : VAR121),
.VAR69 (VAR69),
.VAR23 (VAR23),
.VAR24 (VAR24),
.VAR85 (VAR85),
.VAR83 (VAR83[VAR65-1:0]),
.VAR5 (VAR5),
.VAR21 (VAR21[7:0]),
.VAR115 (VAR115[7:0]));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a31oi/sky130_fd_sc_hs__a31oi.pp.blackbox.v
| 1,338 |
module MODULE1 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR1,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR2;
endmodule
|
apache-2.0
|
osrf/wandrr
|
firmware/motor_controller/fpga/eth_rx.v
| 2,455 |
module MODULE2
(input VAR39, input [1:0] VAR40,
input VAR32,
output [7:0] VAR42,
output VAR12,
output VAR30);
wire [1:0] VAR9;
sync #(2) VAR1
(.in(VAR40), .clk(VAR39), .out(VAR9));
wire VAR27;
sync VAR16
(.in(VAR32), .clk(VAR39), .out(VAR27));
wire VAR18;
d1 VAR3(.VAR42(VAR27), .VAR39(VAR39), .VAR31(VAR18));
wire [7:0] VAR11;
VAR14 #(8) VAR43
(.VAR39(VAR39), .VAR42({VAR9, VAR11[7:2]}), .rst(1'b0), .en(1'b1), .VAR31(VAR11));
wire VAR47;
wire [1:0] VAR26;
VAR14 #(2) VAR2
(.VAR39(VAR39), .VAR42(VAR26+1'b1), .en(1'b1), .rst(VAR47), .VAR31(VAR26));
assign VAR42 = VAR11;
localparam VAR20 = 3, VAR41 = 3;
localparam VAR33 = 3'd0;
localparam VAR10 = 3'd1;
localparam VAR46 = 3'd2;
localparam VAR15 = 3'd3;
reg [VAR41+VAR20-1:0] VAR6;
wire [VAR20-1:0] state;
wire [VAR20-1:0] VAR25 = VAR6[VAR20+VAR41-1:VAR41];
VAR14 #(VAR20) VAR34(.VAR39(VAR39), .rst(1'b0), .en(1'b1), .VAR42(VAR25), .VAR31(state));
always @* begin
case (state)
VAR33:
if (VAR27 && VAR42 == 8'h55) VAR6 = { VAR10, 3'b000 };
end
else VAR6 = { VAR33 , 3'b000 };
VAR10:
if (VAR27 && VAR42 == 8'h55) VAR6 = { VAR10, 3'b000 };
else if (VAR27 && VAR42 == 8'hd5) VAR6 = { VAR46 , 3'b100 };
else VAR6 = { VAR33 , 3'b000 };
VAR46:
if (VAR27 | VAR18) VAR6 = { VAR46 , 3'b001 };
else VAR6 = { VAR15 , 3'b010 };
VAR15: VAR6 = { VAR33 , 3'b000 }; default: VAR6 = { VAR33 , 3'b000 };
endcase
end
assign VAR12 = state == VAR46 & &VAR26;
assign VAR30 = VAR6[1];
assign VAR47 = VAR6[2];
endmodule
module MODULE1();
wire VAR39;
VAR24 #(50) VAR37(VAR39);
wire [1:0] VAR19, VAR22;
wire VAR8, VAR21, VAR35;
wire VAR17, VAR48;
VAR4 #(.VAR44("VAR38.VAR28")) VAR23
(.VAR13(VAR39), .rst(VAR8), .VAR21(VAR21), .VAR35(VAR35),
.VAR45(VAR19), .VAR5(VAR17),
.VAR7(VAR22), .VAR36(VAR48));
wire [7:0] VAR7;
wire VAR36, VAR30;
MODULE2 MODULE1
(.VAR39(VAR39), .VAR40(VAR22), .VAR32(VAR48),
.VAR42(VAR7), .VAR12(VAR36), .VAR30(VAR30));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.behavioral.v
| 1,440 |
module MODULE1 (
VAR1,
VAR9
);
output VAR1;
input VAR9;
supply1 VAR8;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
wire VAR2;
not VAR6 (VAR2, VAR9 );
buf VAR5 (VAR1 , VAR2 );
endmodule
|
apache-2.0
|
aj-michael/Digital-Systems
|
Lab4-Part2-RAMwithHyperTerminalDisplay/DebouncerWithoutLatch.v
| 1,262 |
module MODULE1(VAR11, VAR2, VAR4, VAR6) ;
input VAR11, VAR4, VAR6;
output reg VAR2;
parameter VAR7=0, VAR12=1, VAR5=2, VAR9=3;
reg [1:0] VAR3, VAR8;
wire VAR14;
reg VAR13;
always @ (posedge VAR6) begin
if(VAR4==1) VAR3 <= 0;
end
else VAR3<=VAR8;
case (VAR3)
0: begin VAR2<=0; VAR13<=1; end 1: begin VAR2<=0; VAR13<=0; end 2: begin VAR2<=0; VAR13<=0; end
3: begin VAR2<=1; VAR13<=0; end
endcase
end
always@(VAR3 or VAR11 or VAR14)
case (VAR3)
end
0: if (VAR11==0) VAR8<=VAR7; else VAR8<=VAR12;
end
1: if (VAR14==0) VAR8<=VAR12; else VAR8<=VAR5;
2: if (VAR11==0) VAR8<=VAR7; else VAR8<=VAR9;
3: if (VAR11==0) VAR8<=VAR7; else VAR8<=VAR9;
endcase
VAR10 VAR1(VAR13,VAR14,VAR6);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/ebufn/sky130_fd_sc_hd__ebufn.pp.symbol.v
| 1,327 |
module MODULE1 (
input VAR5 ,
output VAR7 ,
input VAR1,
input VAR6 ,
input VAR4,
input VAR3,
input VAR2
);
endmodule
|
apache-2.0
|
jotego/jt12
|
hdl/jt12_reg.v
| 12,134 |
module MODULE1(
input rst,
input clk,
input VAR41 ,
input [7:0] din,
input [2:0] VAR28, input [1:0] VAR33,
input VAR49,
input VAR16,
input VAR39,
input VAR14,
input VAR21,
input VAR30,
input VAR24,
input VAR48,
input VAR10,
input VAR36,
input VAR2,
input VAR44,
input VAR32,
input VAR55,
output reg VAR31, output reg [2:0] VAR42,
output reg [1:0] VAR19,
input VAR25,
input [10:0] VAR45,
input [10:0] VAR26,
input [10:0] VAR54,
input [ 2:0] VAR9,
input [ 2:0] VAR57,
input [ 2:0] VAR60,
input [ 5:0] VAR23,
output reg VAR3,
output VAR34,
output VAR56,
output VAR22,
output VAR12,
output VAR27,
output VAR5,
output VAR18,
output VAR51,
output VAR61,
output VAR8,
output [10:0] VAR37,
output [ 2:0] VAR13,
output [1:0] VAR29,
output reg [2:0] VAR7,
output [2:0] VAR38,
output [ 3:0] VAR4,
output [ 2:0] VAR40,
output [4:0] VAR17, output [4:0] VAR53, output [4:0] VAR35, output [3:0] VAR11, output [3:0] VAR1, output [1:0] VAR59, output VAR15,
output [2:0] VAR58,
output [6:0] VAR63,
output [2:0] VAR62,
output [1:0] VAR20,
output VAR46,
output VAR52
);
parameter VAR47=6;
reg [1:0] VAR50;
reg [2:0] VAR43;
reg VAR6;
|
gpl-3.0
|
FAST-Switch/fast
|
lib/hardware/platform/NetMagic08/ddr2/ddr2_phy_alt_mem_phy_dq_dqs.v
| 31,991 |
module MODULE1
(
VAR28,
VAR25,
VAR33,
VAR60,
VAR5,
VAR7,
VAR29,
VAR3,
VAR41,
VAR57,
VAR34,
VAR47,
VAR11,
VAR45,
VAR65,
VAR44,
VAR27,
VAR6,
VAR52,
VAR36,
VAR13,
VAR63,
VAR48,
VAR38,
VAR2,
VAR53,
VAR22,
VAR56) ;
input [7:0] VAR28;
input [7:0] VAR25;
output [7:0] VAR33;
output [7:0] VAR60;
input [7:0] VAR5;
output [7:0] VAR7;
input [7:0] VAR29;
input [7:0] VAR3;
output [7:0] VAR41;
input [5:0] VAR57;
input VAR34;
input VAR47;
input VAR11;
input VAR45;
input [0:0] VAR65;
input [0:0] VAR44;
output [0:0] VAR27;
input [0:0] VAR6;
input [0:0] VAR52;
output [0:0] VAR36;
input VAR13;
input [0:0] VAR63;
output [0:0] VAR48;
input [0:0] VAR38;
output [0:0] VAR2;
input [0:0] VAR53;
input [0:0] VAR22;
output [0:0] VAR56;
tri0 [7:0] VAR28;
tri0 [7:0] VAR25;
tri0 [7:0] VAR5;
tri0 [7:0] VAR29;
tri0 [7:0] VAR3;
tri0 [5:0] VAR57;
tri0 VAR34;
tri0 VAR47;
tri1 VAR11;
tri1 VAR45;
tri0 [0:0] VAR65;
tri0 [0:0] VAR44;
tri0 [0:0] VAR6;
tri0 [0:0] VAR52;
tri0 VAR13;
tri0 [0:0] VAR63;
tri0 [0:0] VAR38;
tri0 [0:0] VAR53;
tri0 [0:0] VAR22;
reg VAR64;
reg VAR26;
reg VAR37;
reg VAR68;
reg VAR54;
reg VAR61;
reg VAR14;
reg VAR12;
reg VAR19;
wire VAR10;
wire VAR4;
wire VAR17;
wire VAR20;
wire VAR21;
wire VAR8;
wire VAR18;
wire VAR59;
wire VAR35;
wire VAR30;
wire VAR51;
wire VAR62;
wire VAR32;
wire VAR24;
wire VAR1;
wire VAR42;
wire VAR15;
wire VAR43;
wire VAR16;
wire VAR67;
wire VAR50;
wire VAR46;
wire VAR31;
wire VAR69;
wire VAR55;
wire VAR40;
wire VAR49;
wire VAR58;
wire VAR39;
wire VAR23;
wire VAR9;
wire [0:0] VAR66;
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_async/bsg_sync_sync.v
| 4,267 |
\
module MODULE2 \
( \
input VAR14 \
, input [VAR22-1:0] VAR19 \
, output [VAR22-1:0] VAR2 ); \
\
\
genvar VAR6; \
\
logic [VAR22-1:0] VAR1; \
\
assign VAR2 = VAR1; \
\
for (VAR6 = 0; VAR6 < VAR22; VAR6 = VAR6 + 1) \
begin : VAR3 \
VAR10 VAR9 \
(.VAR15 (VAR19[VAR6]) \
,.VAR5 (VAR14) \
,.VAR20 (1'b0) \
,.VAR4 (1'b0) \
,.VAR13 (VAR1[VAR6]) \
); \
end \
\
endmodule
VAR12 VAR11 \
(.VAR14 \
,.VAR19(VAR19[VAR22-1-:VAR18]) \
,.VAR2(VAR2[VAR22-1-:VAR18]) \
); end
module MODULE1 #(parameter VAR7(VAR22 ))
(
input VAR14
, input [VAR22-1:0] VAR19
, output [VAR22-1:0] VAR2 );
genvar VAR6;
for (VAR6 = 0; VAR6 < (VAR22/VAR8); VAR6 = VAR6 + 1)
begin : VAR17
VAR21 VAR16
(.VAR14
,.VAR19(VAR19[VAR6*VAR8+:VAR8])
,.VAR2(VAR2[VAR6*VAR8+:VAR8])
);
end
endmodule
|
bsd-3-clause
|
htogarcia/Microcontrolador-Calculadora
|
VGA Mouse/vga640x480.v
| 2,282 |
module MODULE1(
input wire clk,
input wire [2:0] VAR2,
input wire [2:0] VAR3,
input wire [1:0] VAR11,
output reg [9:0] hc,
output reg [9:0] VAR7,
output wire VAR4,
output wire VAR6,
output reg [2:0] VAR1,
output reg [2:0] VAR9,
output reg [1:0] VAR12
);
parameter VAR10 = 800;parameter VAR16 = 521; parameter VAR8 = 96; parameter VAR15 = 2; parameter VAR13 = 144; parameter VAR5 = 784; parameter VAR14 = 31; parameter VAR17 = 511;
always @(posedge clk)
begin
if (hc < VAR10 - 1) hc <= (hc + 1'b1);
end
else begin
hc <= 0;
if (VAR7 < VAR16 - 1)
VAR7 <= (VAR7 + 1'b1);
end
else
VAR7 <= 0;
end
end
assign VAR4 = (hc < VAR8) ? 1'b0:1'b1;
assign VAR6 = (VAR7 < VAR15) ? 1'b0:1'b1;
always @(*)
begin
if (VAR7 >= VAR14 && VAR7 < VAR17) begin
if (hc >= VAR13 && hc < (VAR13+640)) begin
VAR1 = VAR2;
VAR9 = VAR3;
VAR12 = VAR11;
end
else begin
VAR1 = 0;
VAR9 = 0;
VAR12 = 0;
end
end
else begin
VAR1 = 0;
VAR9 = 0;
VAR12 = 0;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a22o/sky130_fd_sc_ms__a22o.functional.pp.v
| 2,151 |
module MODULE1 (
VAR6 ,
VAR18 ,
VAR3 ,
VAR17 ,
VAR8 ,
VAR1,
VAR14,
VAR19 ,
VAR12
);
output VAR6 ;
input VAR18 ;
input VAR3 ;
input VAR17 ;
input VAR8 ;
input VAR1;
input VAR14;
input VAR19 ;
input VAR12 ;
wire VAR9 ;
wire VAR11 ;
wire VAR4 ;
wire VAR15;
and VAR10 (VAR9 , VAR17, VAR8 );
and VAR7 (VAR11 , VAR18, VAR3 );
or VAR5 (VAR4 , VAR11, VAR9 );
VAR2 VAR16 (VAR15, VAR4, VAR1, VAR14);
buf VAR13 (VAR6 , VAR15 );
endmodule
|
apache-2.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/one_hot_mux.v
| 4,781 |
module MODULE1
parameter VAR9 = 2,
parameter VAR4 = VAR9*VAR2
)
(
input [VAR9-1:0] VAR7,
input [VAR4-1:0] VAR1,
output [VAR2-1:0] VAR6);
genvar VAR8;
wire [VAR2-1:0] VAR5[(1<<VAR9):1];
reg [VAR2-1:0] VAR3;
assign VAR6 = VAR3;
generate
for( VAR8 = 0 ; VAR8 < VAR9; VAR8 = VAR8 + 1 ) begin : VAR10
assign VAR5[(1<<VAR8)] = VAR1[VAR2*VAR8 +: VAR2];
end
if(VAR9 == 1) begin
always @ begin
case(VAR7)
2'b01: VAR3 = VAR5[1];
2'b10: VAR3 = VAR5[2];
default:VAR3 = VAR5[1];
endcase end
end else if( VAR9 == 4) begin
always @ begin
case(VAR7)
8'b00000001: VAR3 = VAR5[1];
8'b00000010: VAR3 = VAR5[2];
8'b00000100: VAR3 = VAR5[4];
8'b00001000: VAR3 = VAR5[8];
8'b00010000: VAR3 = VAR5[16];
8'b00100000: VAR3 = VAR5[32];
8'b01000000: VAR3 = VAR5[64];
8'b10000000: VAR3 = VAR5[128];
default:VAR3 = VAR5[1];
endcase end
end
endgenerate
endmodule
|
gpl-3.0
|
kevintownsend/R3
|
verilog/intermediator.v
| 7,617 |
module MODULE1(
input reset,
input clk,
input VAR48,
input [63:0] VAR68,
input [9:0] VAR26,
input VAR74,
input [63:0] VAR57,
input [9:0] VAR19,
output VAR41,
output [63:0] VAR75,
output VAR83,
output [63:0] VAR24,
output [63:0] VAR59,
output [9:0] VAR18,
input VAR62
);
reg [2:0] VAR7, VAR28, VAR60, VAR56, VAR67;
reg [2:0] VAR39, VAR79, VAR20, VAR49, VAR76;
reg VAR8, VAR21, VAR69, VAR45, VAR88;
reg [63:0] VAR30, VAR1, VAR12, VAR70, VAR58;
reg [9:0] VAR37, VAR9, VAR35, VAR51, VAR93;
reg [63:0] VAR94, VAR34, VAR29, VAR13, VAR78;
reg [9:0] VAR38, VAR54, VAR33, VAR89, VAR65;
reg [9:0] VAR92, VAR52;
reg [31:0] VAR5;
reg [1:0] VAR80;
reg VAR36;
reg VAR46;
reg [63:0] VAR42;
reg VAR86;
reg [63:0] VAR10;
reg [63:0] VAR91;
reg [63:0] VAR95;
wire [63:0] VAR72, VAR47;
always @(posedge clk) begin
if(reset) begin
VAR7 <= 0;
VAR39 <= 0;
VAR8 <= 0;
end else begin
VAR7 <= {2'VAR3, VAR48};
VAR39 <= {2'VAR3, VAR74};
VAR8 <= 0;
end
VAR30 <= VAR68;
VAR37 <= VAR26;
VAR94 <= VAR57;
VAR38 <= VAR19;
end
always @(posedge clk) begin
VAR28 <= VAR7;
VAR79 <= VAR39;
VAR21 <= (VAR38 == VAR37) && VAR7[0] && VAR39[0];
VAR1 <= VAR30;
VAR9 <= VAR37;
VAR34 <= VAR94;
VAR54 <= VAR38;
end
always @(posedge clk) begin
VAR60 <= VAR28;
VAR20 <= VAR79;
if(VAR21) begin
VAR60[1:0] <= 0;
VAR20[1:0] <= 0;
end
VAR69 <= VAR21;
VAR12 <= VAR1;
VAR35 <= VAR9;
VAR29 <= VAR34;
VAR33 <= VAR54;
if(VAR36) begin
if(!(VAR28[0])) begin
VAR60[2] <= 1;
VAR35 <= VAR92;
end else if(!VAR79[0]) begin
VAR20[2] <= 1;
VAR33 <= VAR92;
end
end
end
always @(posedge clk) begin
if(reset) begin
VAR92 <= 0;
VAR52 <= 0;
VAR5 <= 0;
VAR80 <= VAR32;
VAR36 <= 0;
end else begin
VAR36 <= 0;
VAR52 <= {VAR37[9:4] + 1, 4'VAR3};
if(VAR52[4] == VAR37[4]) begin
if(VAR52[4])
VAR5[31:16] <= 0;
end
else
VAR5[15:0] <= 0;
end
case(VAR80)
if(VAR7[0]) begin
VAR80 <= VAR63;
VAR92 <= {VAR37[9:4], 4'VAR3};
end
VAR5 <= 0;
end
if(VAR92[9:4] + 6'VAR31 == VAR52[9:4])
VAR80 <= VAR16;
if(VAR62)
VAR80 <= VAR25;
end
if(VAR92[9:4] + 6'VAR31 != VAR52[9:4])begin
VAR36 <= 1;
end
if(VAR62)
VAR80 <= VAR25;
end
VAR36 <= 1;
if(VAR92 == VAR52)
VAR80 <= VAR32;
end
endcase
if((!VAR28[0] || !VAR79[0]) && VAR36)
VAR92 <= VAR92 + 1;
if(VAR60[0]) begin
VAR5[VAR35[4:0]] <= ~VAR5[VAR35[4:0]];
end
if(VAR20[0])
VAR5[VAR33[4:0]] <= ~VAR5[VAR33[4:0]];
end
end
wire VAR11, VAR66;
assign VAR11 = VAR5[VAR35[4:0]];
assign VAR66 = VAR5[VAR33[4:0]];
always @(posedge clk) begin
VAR56 <= VAR60;
VAR49 <= VAR20;
VAR56[1] <= VAR60[0] && !VAR11;
VAR49[1] <= VAR20[0] && !VAR66;
VAR45 <= VAR69;
VAR70 <= VAR12;
VAR51 <= VAR35;
VAR13 <= VAR29;
VAR89 <= VAR33;
end
VAR22 VAR15(
.VAR73(clk),
.VAR64(VAR56[1]),
.VAR61(VAR51),
.VAR82(VAR70),
.VAR43(VAR72),
.VAR6(clk),
.VAR81(VAR49[1]),
.VAR84(VAR89),
.VAR55(VAR13),
.VAR4(VAR47));
always @(posedge clk) begin
VAR67 <= VAR56;
VAR76 <= VAR49;
VAR88 <= VAR45;
VAR58 <= VAR70;
VAR93 <= VAR51;
VAR78 <= VAR13;
VAR65 <= VAR89;
end
wire VAR71;
reg VAR96;
wire VAR40, VAR85;
wire [9:0] VAR23;
wire [63:0] VAR17;
wire [63:0] VAR77;
assign VAR71 = (VAR56[1:0] != 2'VAR44) && !VAR45 && !VAR40;
always @(posedge clk) begin
VAR96 <= VAR71;
end
VAR53 VAR90(
.clk(clk),
.VAR27(reset),
.din({VAR65, VAR78, VAR47}),
.VAR87((VAR76[1:0] == 2'VAR44)),
.VAR14(VAR71),
.dout({VAR23, VAR17, VAR77}),
.VAR50(VAR85),
.VAR2(VAR40));
always @(posedge clk) begin
VAR86 <= 0;
VAR10 <= 0;
VAR91 <= 0;
VAR95 <= 0;
if(VAR88) begin
VAR86 <= 1;
VAR10 <= VAR58;
VAR91 <= VAR78;
VAR95 <= VAR93;
end else if(VAR67[1:0] == 2'VAR44) begin
VAR86 <= 1;
VAR10 <= VAR58;
VAR91 <= VAR72;
VAR95 <= VAR93;
end else if(VAR96) begin
VAR86 <= 1;
VAR10 <= VAR17;
VAR91 <= VAR77;
VAR95 <= VAR23;
end
end
assign VAR83 = VAR86;
assign VAR24 = VAR10;
assign VAR59 = VAR91;
assign VAR18 = VAR95;
always @(posedge clk) begin
VAR46 <= 0;
VAR42 <= 0;
if(reset)
VAR46 <= 0;
if(VAR67[2]) begin
VAR46 <= 1;
VAR42 <= VAR72;
end else if(VAR76[2]) begin
VAR46 <= 1;
VAR42 <= VAR47;
end
end
assign VAR41 = VAR46;
assign VAR75 = VAR42;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/or2b/sky130_fd_sc_hdll__or2b.behavioral.v
| 1,450 |
module MODULE1 (
VAR3 ,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR8 ;
input VAR4;
supply1 VAR11;
supply0 VAR12;
supply1 VAR7 ;
supply0 VAR1 ;
wire VAR2 ;
wire VAR6;
not VAR5 (VAR2 , VAR4 );
or VAR10 (VAR6, VAR2, VAR8 );
buf VAR9 (VAR3 , VAR6 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.pp.blackbox.v
| 1,175 |
module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/tap/sky130_fd_sc_lp__tap_2.v
| 1,877 |
module MODULE2 (
VAR6,
VAR1,
VAR4 ,
VAR2
);
input VAR6;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR5 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
VAR5 VAR3 ();
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/or4bb/sky130_fd_sc_lp__or4bb.behavioral.pp.v
| 1,988 |
module MODULE1 (
VAR5 ,
VAR1 ,
VAR16 ,
VAR2 ,
VAR4 ,
VAR13,
VAR7,
VAR14 ,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR16 ;
input VAR2 ;
input VAR4 ;
input VAR13;
input VAR7;
input VAR14 ;
input VAR6 ;
wire VAR17 ;
wire VAR11 ;
wire VAR12;
nand VAR8 (VAR17 , VAR4, VAR2 );
or VAR3 (VAR11 , VAR16, VAR1, VAR17 );
VAR9 VAR15 (VAR12, VAR11, VAR13, VAR7);
buf VAR10 (VAR5 , VAR12 );
endmodule
|
apache-2.0
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/debounce.v
| 1,199 |
module MODULE1 (
input VAR10,
input reset,
input VAR13,
input VAR12,
input VAR5,
input VAR9,
input VAR2,
output reg VAR6,
output reg VAR8,
output reg VAR4,
output reg VAR1,
output reg VAR11,
output reg VAR3,
output VAR7
);
begin
begin
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dlclkp/sky130_fd_sc_ls__dlclkp.behavioral.pp.v
| 1,924 |
module MODULE1 (
VAR13,
VAR16,
VAR8 ,
VAR17,
VAR14,
VAR11 ,
VAR1
);
output VAR13;
input VAR16;
input VAR8 ;
input VAR17;
input VAR14;
input VAR11 ;
input VAR1 ;
wire VAR15 ;
wire VAR3 ;
wire VAR6 ;
wire VAR7;
reg VAR9 ;
wire VAR12 ;
not VAR4 (VAR3 , VAR6 );
VAR5 VAR10 (VAR15 , VAR7, VAR3, VAR9, VAR17, VAR14);
and VAR2 (VAR13 , VAR15, VAR6 );
assign VAR12 = ( VAR17 === 1'b1 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.pp.symbol.v
| 1,579 |
module MODULE1 (
input VAR9 ,
output VAR3 ,
output VAR6 ,
input VAR5,
input VAR7 ,
input VAR8 ,
input VAR4 ,
input VAR11 ,
input VAR10 ,
input VAR1 ,
input VAR2 ,
input VAR12
);
endmodule
|
apache-2.0
|
markusC64/1541ultimate2
|
fpga/nios/nios/synthesis/submodules/nios_altmemddr_0_mem_model.v
| 24,610 |
module MODULE1 (
VAR10,
VAR3,
VAR9,
VAR11,
VAR1,
VAR2
)
;
parameter VAR8 = 2048;
output [ 15: 0] VAR2;
input [ 15: 0] VAR10;
input [ 24: 0] VAR3;
input [ 24: 0] VAR9;
input VAR11;
input VAR1;
wire [ 15: 0] VAR4;
reg [ 41: 0] VAR12 [2047: 0];
wire [ 15: 0] VAR2;
assign VAR4 = VAR12[0][15:0];
reg [ 16 - 1: 0] out;
integer VAR7;
reg VAR5;
reg VAR6;
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
gpl-3.0
|
qiuzou/nysa_saya
|
rtl/sata_stack.v
| 25,549 |
module MODULE1 (
input rst, input clk, input VAR287,
input VAR51,
input VAR191, output wire VAR237, output VAR156,
output VAR275,
input VAR218,
input [15:0] VAR40,
output VAR15,
output VAR221,
input VAR98,
input VAR251,
input VAR139,
input VAR192,
input VAR232,
input [7:0] VAR76,
output VAR170,
input [15:0] VAR239,
input [47:0] VAR210,
output VAR209,
output VAR62,
output VAR113,
output VAR244,
output VAR87,
output wire VAR118,
output VAR164,
output VAR110,
output VAR97,
output VAR109,
output VAR3,
output [3:0] VAR195,
output [7:0] VAR52,
output [47:0] VAR169,
output [15:0] VAR115,
output [7:0] VAR23,
output [7:0] VAR82,
input VAR194,
input [31:0] VAR241,
input VAR137,
output [1:0] VAR144,
input [1:0] VAR234,
output [23:0] VAR93,
output [31:0] VAR146,
output VAR94,
input VAR212,
input VAR259,
output [23:0] VAR32,
output VAR243,
output VAR133,
output VAR79,
output [31:0] VAR91,
output VAR103,
output VAR150,
output VAR78,
output VAR188,
input [31:0] VAR202,
input [3:0] VAR69,
input VAR46,
input VAR284,
input VAR119,
input VAR201,
output VAR63,
output VAR14,
output VAR278,
output VAR108,
output VAR274,
output [15:0] VAR198,
output [7:0] VAR47,
output [7:0] VAR73,
output [15:0] VAR184,
output [7:0] VAR96,
output [3:0] VAR81,
output [7:0] VAR172,
output [47:0] VAR206,
output [15:0] VAR37,
output VAR193,
output VAR61,
output [23:0] VAR158,
output VAR70,
output [31:0] VAR140,
output [1:0] VAR280,
output [1:0] VAR175,
output VAR220,
output [31:0] VAR55,
output [23:0] VAR71,
output [3:0] VAR105,
output [3:0] VAR101,
output [3:0] VAR279,
output [3:0] VAR285,
output [3:0] VAR86,
output [3:0] VAR5,
output [3:0] VAR228,
output [3:0] VAR8,
input VAR112,
input VAR74,
output VAR132,
output VAR102,
output VAR59,
output VAR34,
output VAR272,
output [31:0] VAR28,
output [31:0] VAR92,
output VAR155,
output VAR39,
output VAR68,
output VAR135,
output [31:0] VAR286,
output VAR124,
output VAR27,
output VAR185,
output VAR56,
output VAR186,
output [3:0] VAR219,
output VAR48,
output VAR151,
output VAR227,
output VAR207,
output VAR11,
output VAR190,
output VAR25,
output VAR199,
output VAR263,
output VAR83,
output VAR160,
output VAR134,
output VAR225,
output VAR29,
output VAR163,
output VAR66,
output VAR238,
output [23:0] VAR12,
output [12:0] VAR167,
output [12:0] VAR122,
output [3:0] VAR67
);
wire VAR264;
wire VAR255;
wire VAR141;
wire VAR213;
wire [31:0] VAR2;
wire VAR35;
wire VAR7;
wire [23:0] VAR230;
wire VAR60;
wire [31:0] VAR129;
wire [1:0] VAR152;
wire [1:0] VAR229;
wire [23:0] VAR126;
wire VAR104;
wire VAR231;
wire VAR17;
wire VAR54;
wire [31:0] VAR248;
wire [31:0] VAR208;
wire VAR77;
wire VAR44;
wire VAR106;
wire VAR21;
wire VAR18;
wire [31:0] VAR58;
wire VAR84;
wire VAR242;
wire VAR166;
wire VAR145;
wire [31:0] VAR215;
wire VAR217;
wire [31:0] VAR253;
wire VAR114;
wire VAR265;
wire [7:0] VAR4;
wire [15:0] VAR266;
wire [7:0] VAR41;
wire [3:0] VAR6;
wire [7:0] VAR262;
wire [47:0] VAR197;
wire [15:0] VAR85;
wire VAR131;
wire VAR178;
wire VAR36;
wire VAR281;
wire VAR38;
wire [15:0] VAR270;
wire [7:0] VAR161;
wire VAR260;
wire VAR271;
wire [23:0] VAR130;
wire VAR273;
wire [31:0] VAR211;
wire [1:0] VAR111;
wire [1:0] VAR72;
wire VAR90;
wire [31:0] VAR256;
wire [23:0] VAR16;
wire VAR261;
wire VAR43;
wire VAR205;
wire VAR49;
wire [31:0] VAR153;
wire [31:0] VAR173;
wire VAR121;
wire VAR147;
wire VAR214;
wire VAR258;
wire VAR180;
wire [31:0] VAR30;
wire VAR224;
wire VAR189;
wire VAR136;
wire VAR123;
VAR277 VAR181 (
.rst (rst | !VAR237 ),
.clk (clk ),
.VAR287 (VAR287 ),
.VAR51 (VAR51 ),
.VAR275 (VAR275 ),
.VAR116 (VAR156 ),
.VAR15 (VAR15 ),
.VAR80 (VAR221 ),
.VAR218 (VAR218 ),
.VAR40 (VAR40 ),
.VAR98 (VAR98 ),
.VAR251 (VAR251 ),
.VAR139 (VAR139 ),
.VAR192(VAR192 ),
.VAR232 (VAR232 ),
.VAR76 (VAR76 ),
.VAR170 (VAR170 ),
.VAR239 (VAR239 ),
.VAR210 (VAR210 ),
.VAR194 (VAR194 ),
.VAR241 (VAR241 ),
.VAR137 (VAR137 ),
.VAR144 (VAR144 ),
.VAR234 (VAR234 ),
.VAR93 (VAR93 ),
.VAR146 (VAR146 ),
.VAR94 (VAR94 ),
.VAR212 (VAR212 ),
.VAR259 (VAR259 ),
.VAR32 (VAR32 ),
.VAR243(VAR243 ),
.VAR265 (VAR265 ),
.VAR240 (VAR264 ),
.VAR268 (VAR255 ),
.VAR179 (VAR141 ),
.VAR203 (VAR209 ),
.VAR226 (VAR62 ),
.VAR159 (VAR113 ),
.VAR50 (VAR244 ),
.VAR157 (VAR87 ),
.VAR222(VAR118 ),
.VAR123 (VAR131 ),
.VAR214 (VAR178 ),
.VAR246 (VAR36 ),
.VAR142 (VAR281 ),
.VAR120 (VAR38 ),
.VAR107 (VAR270 ),
.VAR154 (VAR161 ),
.VAR4 (VAR4 ),
.VAR266 (VAR266 ),
.VAR41 (VAR41 ),
.VAR6 (VAR6 ),
.VAR262 (VAR262 ),
.VAR197 (VAR197 ),
.VAR85 (VAR85 ),
.VAR109 (VAR109 ),
.VAR3 (VAR3 ),
.VAR195 (VAR195 ),
.VAR52 (VAR52 ),
.VAR169 (VAR169 ),
.VAR115 (VAR115 ),
.VAR23 (VAR23 ),
.VAR82 (VAR82 ),
.VAR283 (VAR213 ),
.VAR53 (VAR2 ),
.VAR19 (VAR35 ),
.VAR196 (VAR7 ),
.VAR65 (VAR230 ),
.VAR245 (VAR60 ),
.VAR233 (VAR129 ),
.VAR177 (VAR152 ),
.VAR125 (VAR229 ),
.VAR42 (VAR126 ),
.VAR100 (VAR105 ),
.VAR31 (VAR101 ),
.VAR249 (VAR279 )
);
VAR252 VAR45 (
.rst (rst | !VAR237 ),
.clk (clk ),
.VAR79 (VAR79 ),
.VAR243 (VAR243 ),
.VAR265 (VAR265 ),
.VAR264 (VAR264 ),
.VAR255 (VAR255 ),
.VAR141 (VAR141 ),
.VAR209 (VAR209 ),
.VAR62 (VAR62 ),
.VAR113 (VAR113 ),
.VAR244 (VAR244 ),
.VAR87 (VAR87 ),
.VAR118 (VAR118 ),
.VAR131 (VAR131 ),
.VAR178 (VAR178 ),
.VAR36 (VAR36 ),
.VAR281 (VAR281 ),
.VAR38 (VAR38 ),
.VAR270 (VAR270 ),
.VAR161 (VAR161 ),
.VAR4 (VAR4 ),
.VAR266 (VAR266 ),
.VAR41 (VAR41 ),
.VAR6 (VAR6 ),
.VAR262 (VAR262 ),
.VAR197 (VAR197 ),
.VAR85 (VAR85 ),
.VAR109 (VAR109 ),
.VAR3 (VAR3 ),
.VAR195 (VAR195 ),
.VAR52 (VAR52 ),
.VAR169 (VAR169 ),
.VAR115 (VAR115 ),
.VAR23 (VAR23 ),
.VAR82 (VAR82 ),
.VAR194 (VAR194 ),
.VAR260 (VAR260 ),
.VAR271 (VAR271 ),
.VAR130 (VAR130 ),
.VAR273 (VAR273 ),
.VAR211 (VAR211 ),
.VAR111 (VAR111 ),
.VAR72 (VAR72 ),
.VAR90 (VAR90 ),
.VAR256 (VAR256 ),
.VAR16 (VAR16 ),
.VAR133 (VAR133 ),
.VAR104 (VAR261 ),
.VAR231 (VAR43 ),
.VAR17 (VAR205 ),
.VAR54 (VAR49 ),
.VAR248 (VAR153 ),
.VAR208 (VAR173 ),
.VAR77 (VAR121 ),
.VAR44 (VAR147 ),
.VAR145 (VAR214 ),
.VAR21 (VAR258 ),
.VAR106 (VAR180 ),
.VAR58 (VAR30 ),
.VAR18 (VAR224 ),
.VAR84 (VAR189 ),
.VAR242 (VAR136 ),
.VAR166 (VAR123 ),
.VAR219 (VAR285 )
);
VAR88 VAR127(
.rst (rst | !VAR237 ),
.clk (clk ),
.VAR133 (VAR133 ),
.VAR265 (VAR104 ),
.VAR250 (VAR132 ),
.VAR117 (VAR102 ),
.VAR20 (1'b0 ),
.VAR26 (VAR231 ),
.VAR171 (VAR17 ),
.VAR276 (VAR54 ),
.VAR75 (VAR248 ),
.VAR138 (VAR208 ),
.VAR1 (VAR77 ),
.VAR257 (VAR44 ),
.VAR149 (VAR58 ),
.VAR200 (VAR18 ),
.VAR254 (VAR106 ),
.VAR33 (VAR21 ),
.VAR57 (VAR84 ),
.VAR131 (VAR166 ),
.VAR178 (VAR145 ),
.VAR176 (VAR242 ),
.VAR112 (VAR112 ),
.VAR74 (VAR74 ),
.VAR79 (VAR79 ),
.VAR191 (VAR191 ),
.VAR91 (VAR215 ),
.VAR103 (VAR217 ),
.VAR202 (VAR202 ),
.VAR69 (VAR69 ),
.VAR99 (1'b0 ),
.VAR89 (VAR48 ),
.VAR187 (VAR151 ),
.VAR162 (VAR227 ),
.VAR148 (VAR207 ),
.VAR165 (VAR11 ),
.VAR223 (VAR190 ),
.VAR267 (VAR25 ),
.VAR9 (VAR199 ),
.VAR269 (VAR263 ),
.VAR204 (VAR83 ),
.VAR22 (VAR160 ),
.VAR24 (VAR134 ),
.VAR143 (VAR225 ),
.VAR174 (VAR29 ),
.VAR10 (VAR163 ),
.VAR247 (VAR66 ),
.VAR238 (VAR238 ),
.VAR95 (VAR186 ),
.VAR168 (VAR86 ),
.VAR282 (VAR5 ),
.VAR128 (VAR228 ),
.VAR235 (VAR8 ),
.VAR236 (VAR12 ),
.VAR182 (VAR167 ),
.VAR13 (VAR122 ),
.VAR216 (VAR67 )
);
VAR183 VAR64 (
.rst (rst ),
.clk (clk ),
.VAR191 (VAR191 ),
.VAR237 (VAR237 ),
.VAR91 (VAR253 ),
.VAR103 (VAR114 ),
.VAR150 (VAR150 ),
.VAR78 (VAR78 ),
.VAR188 (VAR188 ),
.VAR202 (VAR202 ),
.VAR69 (VAR69 ),
.VAR284 (VAR284 ),
.VAR119 (VAR119 ),
.VAR46 (VAR46 ),
.VAR201 (VAR201 ),
.VAR219 (VAR219 ),
.VAR79 (VAR79 )
);
assign VAR91 = (VAR79) ? VAR215 : VAR253;
assign VAR103 = (VAR79) ? VAR217 : VAR114;
assign VAR231 = VAR43;
assign VAR59 = VAR43;
assign VAR248 = VAR153;
assign VAR28 = VAR153;
assign VAR77 = VAR121;
assign VAR155 = VAR121;
assign VAR208 = VAR173;
assign VAR92 = VAR173;
assign VAR44 = VAR147;
assign VAR39 = VAR147;
assign VAR106 = VAR180;
assign VAR124 = VAR180;
assign VAR104 = VAR261;
assign VAR34 = VAR17;
assign VAR205 = VAR17;
assign VAR272 = VAR54;
assign VAR49 = VAR54;
assign VAR135 = VAR18;
assign VAR68 = VAR21;
assign VAR27 = VAR84;
assign VAR286 = VAR58;
assign VAR185 = VAR166;
assign VAR56 = VAR145;
assign VAR224 = VAR18;
assign VAR258 = VAR21;
assign VAR189 = VAR84;
assign VAR30 = VAR58;
assign VAR123 = VAR166;
assign VAR214 = VAR145;
assign VAR136 = VAR242;
assign VAR164 = VAR264;
assign VAR110 = VAR255;
assign VAR97 = VAR141;
assign VAR63 = VAR131;
assign VAR14 = VAR178;
assign VAR278 = VAR36;
assign VAR73 = VAR4;
assign VAR184 = VAR266;
assign VAR96 = VAR41;
assign VAR81 = VAR6;
assign VAR172 = VAR262;
assign VAR37 = VAR85;
assign VAR260 = VAR35;
assign VAR61 = VAR271;
assign VAR7 = VAR271;
assign VAR158 = VAR230;
assign VAR130 = VAR230;
assign VAR70 = VAR273;
assign VAR213 = VAR273;
assign VAR140 = VAR2;
assign VAR211 = VAR2;
assign VAR111 = VAR152;
assign VAR280 = VAR152;
assign VAR229 = VAR72;
assign VAR175 = VAR72;
assign VAR60 = VAR90;
assign VAR220 = VAR90;
assign VAR129 = VAR256;
assign VAR55 = VAR256;
assign VAR16 = VAR126;
assign VAR71 = VAR126;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.pp.blackbox.v
| 1,431 |
module MODULE1 (
VAR3 ,
VAR2 ,
VAR5,
VAR4 ,
VAR1 ,
VAR7 ,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR5;
input VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
endmodule
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v
| 2,281 |
module MODULE1
, parameter VAR4(VAR22)
, VAR6 = 0
)
(input VAR20
, input VAR21
, input VAR10
, output logic VAR25
, input [VAR13-1:0] VAR18
, output logic [VAR22-1:0][VAR13-1:0] VAR7
, output logic VAR29
, input VAR31
);
localparam VAR24 = VAR26(VAR22);
logic [VAR22-1:0] VAR16;
assign VAR29 = VAR10 & VAR16[VAR22-1]; assign VAR25 = ~VAR16[VAR22-1] | VAR31;
wire VAR35 = VAR29 & VAR31; wire VAR14 = VAR10 & VAR25;
if (VAR22 == 1)
begin : VAR17
assign VAR16 = 1'b1;
end
else
begin : VAR1
VAR27
VAR15
(.VAR20(VAR20)
,.VAR21(VAR21)
,.VAR19(VAR35)
,.VAR28(VAR14 & ~VAR16[VAR22-1])
,.VAR34(VAR16)
);
end
logic [VAR22-1:0][VAR13-1:0] VAR9;
for (genvar VAR30 = 0; VAR30 < VAR22-1; VAR30++)
begin: VAR11
wire VAR33 = VAR10 & VAR16[VAR30];
VAR36 #(.VAR13(VAR13)) VAR32
(.VAR20
,.VAR18
,.VAR8 (VAR33)
,.VAR7 (VAR9 [VAR30])
);
end
assign VAR9[VAR22-1] = VAR18;
if (VAR6 == 0)
begin: VAR5
assign VAR7 = VAR9;
end
else
begin: VAR2
VAR3
VAR12
(.VAR30(VAR9)
,.VAR23(VAR7)
);
end
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/buf/sky130_fd_sc_ls__buf.behavioral.v
| 1,319 |
module MODULE1 (
VAR9,
VAR1
);
output VAR9;
input VAR1;
supply1 VAR7;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR4 ;
wire VAR6;
buf VAR3 (VAR6, VAR1 );
buf VAR8 (VAR9 , VAR6 );
endmodule
|
apache-2.0
|
parallella/oh
|
common/hdl/oh_clockgate.v
| 1,064 |
module MODULE1 (
input clk, input VAR5, input en, output VAR7 );
VAR3 VAR4 (.en(en),
.VAR5(VAR5),
.clk(clk),
.VAR7(VAR7));
wire VAR8;
wire VAR6;
assign VAR6 = en | VAR5;
VAR1 VAR2 (.out (VAR8),
.in (VAR6),
.clk (clk));
assign VAR7 = clk & VAR8;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlxtn/sky130_fd_sc_lp__dlxtn.blackbox.v
| 1,300 |
module MODULE1 (
VAR6 ,
VAR1 ,
VAR3
);
output VAR6 ;
input VAR1 ;
input VAR3;
supply1 VAR2;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a21boi/sky130_fd_sc_ms__a21boi.symbol.v
| 1,397 |
module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR8,
output VAR1
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
Marcoslz22/Tercer_Proyecto
|
Prueba_Alarma.v
| 1,982 |
module MODULE1(
input clk,
input VAR14,
input [7:0] VAR26,
input [7:0] VAR3,
input [7:0] VAR15,
input [7:0] VAR4,
input [7:0] VAR18,
input [7:0] VAR7,
input [7:0] VAR6,
output [7:0] VAR25,
output VAR8
);
wire VAR21;
wire [7:0] VAR13;
wire [7:0] VAR24;
wire [7:0] VAR17;
wire [7:0] VAR9;
wire [7:0] VAR12;
VAR28 VAR27 (
.VAR26(VAR26),
.clk(clk),
.reset(VAR21),
.VAR13(VAR13)
);
VAR5 VAR1 (
.VAR26(VAR26),
.clk(clk),
.reset(VAR21),
.VAR24(VAR24)
);
VAR16 VAR22 (
.VAR26(VAR26),
.clk(clk),
.VAR14(VAR14),
.VAR21(VAR21)
);
VAR11 VAR23 (
.clk(clk),
.VAR3(VAR3),
.VAR15(VAR15),
.VAR4(VAR4),
.VAR26(VAR13),
.VAR17(VAR17),
.VAR9(VAR9),
.VAR12(VAR12)
);
VAR10 VAR19 (
.VAR3(VAR17),
.VAR15(VAR9),
.VAR4(VAR12),
.VAR18(VAR18),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR20(VAR13),
.VAR2(VAR24),
.clk(clk),
.reset(VAR21),
.VAR25(VAR25),
.VAR8(VAR8)
);
endmodule
|
mit
|
DProvinciani/Arquitectura_TPF
|
Codigo_fuente/6-pipe_registers/latch_EX_MEM.v
| 3,783 |
module MODULE1
parameter VAR9=32, VAR23=5
)
(
input wire clk,
input wire reset,
inout wire VAR18,
input wire [VAR9-1:0] VAR2,
input wire [VAR9-1:0] VAR11,
input wire [VAR23-1:0] VAR5,
output wire [VAR9-1:0]VAR10,
output wire [VAR9-1:0]VAR17,
output wire [VAR23-1:0]VAR7,
input wire VAR15,
input wire VAR14,
input wire VAR4,
input [5:0] VAR19,
output wire VAR13,
output wire VAR16,
output wire VAR12,
output wire [5:0] VAR24
);
reg [VAR9-1:0] VAR3;
reg [VAR9-1:0] VAR20;
reg [VAR23-1:0] VAR6;
reg VAR22;
reg VAR1;
reg VAR8;
reg [5:0] VAR21;
always @(posedge clk)
begin
if (reset)
begin
VAR3 <= 0;
VAR20 <= 0;
VAR6 <= 0;
VAR22 <= 0;
VAR1 <= 0;
VAR8 <= 0;
VAR21 <= 0;
end
else
if(VAR18==1'b1)
begin
VAR3 <= VAR2;
VAR20 <= VAR11;
VAR6 <= VAR5;
VAR22 <= VAR15;
VAR1 <= VAR14;
VAR8 <= VAR4;
VAR21 <= VAR19;
end
end
assign VAR10 = VAR3;
assign VAR17 = VAR20;
assign VAR7 = VAR6;
assign VAR13 = VAR22;
assign VAR16 = VAR1;
assign VAR12 = VAR8;
assign VAR24 = VAR21;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.v
| 2,398 |
module MODULE1 (
VAR10 ,
VAR9,
VAR11,
VAR7 ,
VAR8 ,
VAR1,
VAR4,
VAR6 ,
VAR5
);
output VAR10 ;
input VAR9;
input VAR11;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR4;
input VAR6 ;
input VAR5 ;
VAR3 VAR2 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR10 ,
VAR9,
VAR11,
VAR7 ,
VAR8
);
output VAR10 ;
input VAR9;
input VAR11;
input VAR7 ;
input VAR8 ;
supply1 VAR1;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR5 ;
VAR3 VAR2 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/fill/sky130_fd_sc_hd__fill_1.v
| 1,840 |
module MODULE2 (
VAR2,
VAR3,
VAR4 ,
VAR5
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR5 ;
VAR1 VAR6 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
VAR1 VAR6 ();
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hs__udp_dff_nsr_pp_pg_n.symbol.v
| 1,655 |
module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR3 ,
input VAR5 ,
input VAR4 ,
input VAR2,
input VAR1 ,
input VAR8
);
endmodule
|
apache-2.0
|
PhilippMundhenk/AutomotiveEthernetSwitch
|
aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup.v
| 11,704 |
module MODULE1
parameter VAR28 = 48,
parameter VAR39 = 4,
parameter VAR48 = 0,
parameter VAR18 = 9,
parameter VAR12 = 64,
parameter VAR44 = 0,
parameter VAR55 = 0,
parameter VAR14 = 20,
parameter VAR61 = 40,
parameter VAR19 = 0,
parameter VAR25 = 63,
parameter VAR22 = 60,
parameter VAR23 = 48,
parameter VAR45 = 0,
parameter VAR62 = 0
)
(
clk,
reset,
VAR37,
VAR27,
VAR31,
VAR15,
VAR26,
VAR5,
VAR41,
VAR46,
VAR16,
VAR34,
VAR60,
VAR42,
VAR4,
VAR47
);
input clk ;
input reset;
input [VAR28-1:0] VAR37;
input VAR27;
input [VAR44-1:0] VAR31;
input VAR15;
input [VAR55-1:0] VAR26;
output reg VAR5;
output [VAR39-1:0] VAR41;
output [VAR44-1:0] VAR46;
output VAR16;
output [VAR55-1:0] VAR34;
output reg VAR60;
output reg VAR42;
output reg [VAR18-1:0] VAR4;
input [VAR12-1:0] VAR47;
parameter VAR11 = 2'd0;
parameter VAR1 = 2'd1;
parameter VAR17 = 2'd2;
parameter VAR20 = 2'd3;
reg [1:0] state;
reg VAR10;
reg VAR50;
reg VAR33;
reg VAR40;
reg VAR36;
reg VAR38;
reg VAR56;
reg [VAR18-1 : 0] VAR21;
reg [VAR18-1 : 0] VAR53;
reg [VAR28-1 : 0] VAR59;
reg VAR54;
reg [VAR44-1 : 0] VAR7;
reg [VAR18-1 : 0] VAR58;
reg [VAR18-1 : 0] VAR32;
reg [VAR18-1 : 0] VAR9;
reg [VAR18-1 : 0] VAR2;
reg [VAR39-1 : 0] VAR35;
reg [VAR44-1 : 0] VAR57;
reg VAR6;
reg [VAR55-1 : 0] VAR3;
wire [VAR18-1 : 0] VAR24;
wire [VAR18-1 : 0] VAR52;
wire [VAR18-1 : 0] VAR8;
wire VAR43;
wire [VAR39-1 : 0] VAR29;
wire [VAR44-1 : 0] VAR30;
wire VAR51;
wire [VAR28-1 : 0] VAR13;
reg [VAR18-1 : 0] VAR49 = 'd0;
reg [VAR18-1 : 0] VAR63;
assign VAR24 = VAR47[VAR14+VAR18-1 : VAR14];
assign VAR52 = VAR47[VAR61+VAR18-1 : VAR61];
assign VAR8 = VAR47[VAR19+VAR18-1 : VAR19];
assign VAR43 = VAR47[VAR25];
assign VAR29 = VAR47[VAR22+VAR39-1 : VAR22];
assign VAR30 = VAR47[VAR23+VAR44-1 : VAR23];
assign VAR51 = VAR47[VAR45];
assign VAR13 = VAR47[VAR62+VAR28-1 : VAR62];
always @ (posedge clk)
begin
if (reset) begin
state <= VAR11;
VAR10 <= 1'b0; VAR50 <= 1'b0; VAR33 <= 1'b0; VAR40 <= 1'b0; VAR36 <= 1'b0; VAR38 <= 1'b0; VAR32 <= 'b0;
VAR53 <= 'b0;
VAR58 <= 'b0;
VAR21 <= 'b0;
VAR9 <= 'b0;
VAR2 <= 'b0;
VAR42 <= 1'b0;
VAR56 <= 1'b0;
VAR4 <= 'hFFF;
VAR59 <= 'b0;
VAR54 <= 1'b0;
VAR7 <= 'b0;
VAR3 <= 'b0;
VAR5 <= 1'b0;
end
else begin
VAR10 <= 1'b0;
VAR50 <= 1'b0;
VAR33 <= 1'b0;
VAR40 <= 1'b0;
VAR36 <= 1'b0;
VAR38 <= 1'b0;
VAR5 <= 1'b0;
VAR32 <= VAR53;
VAR58 <= VAR21;
VAR56 <= VAR42;
case(state)
VAR11 : begin if (VAR15) begin
state <= VAR1;
VAR10 <= 1'b1; VAR42 <= 1'b1;
VAR4 <= VAR49;
VAR59 <= VAR37;
VAR54 <= VAR27;
VAR7 <= VAR31;
VAR3 <= VAR26;
VAR5 <= 1'b1;
end
end
VAR1 : begin if (VAR56 && VAR42) begin
VAR56 <= 1'b0; VAR50 <= 1'b1; VAR2 <= VAR8;
VAR42 <= 1'b1;
if (~VAR43) begin state <= VAR20;
VAR4 <= VAR8;
end
else begin state <= VAR17;
VAR53 <= VAR52; VAR32 <= VAR52; VAR21 <= VAR24; VAR58 <= VAR24; VAR4 <= (VAR52 + VAR24)/2; end
end
end
VAR17 : begin if (VAR56 && VAR42) begin
VAR56 <= 1'b0; if (VAR59 == VAR13) begin state <= VAR11;
VAR36 <= 1'b1; VAR40 <= 1'b1; VAR42 <= 1'b0;
end
else if (VAR32 == VAR58) begin state <= VAR20;
VAR4 <= VAR2;
end
else begin VAR38 <= 1'b1; state <= VAR17;
if (VAR59 > VAR13) begin
if (VAR53 == VAR21 + 1'b1) begin
VAR53 <= VAR21;
VAR4 <= VAR21;
end
else begin
VAR21 <= VAR4; VAR4 <= (VAR53[VAR18-1:1] + VAR4[VAR18-1:1] + (|{VAR4[0],VAR53[0]}));
end
end
else begin if (VAR53 == VAR21 + 1'b1) begin
VAR53 <= VAR21;
VAR4 <= VAR21;
end
else begin
VAR53 <= VAR4; VAR4 <= (VAR21[VAR18-1:1] + VAR4[VAR18-1:1] + (|{VAR4[0],VAR21[0]}));
end
end
end
end
VAR9 <= (VAR53 + VAR21);
end
VAR20 : begin
if (VAR56 && VAR42) begin
state <= VAR11;
VAR33 <= 1'b1; VAR40 <= 1'b1; VAR42 <= 1'b0;
end
end
endcase
end
end
always @ (posedge clk)
begin
if (reset) begin
VAR35 <= 'b0;
VAR57 <= 'b0;
VAR6 <= 1'b0;
end
else begin
VAR35 <= VAR35;
VAR57 <= VAR57;
VAR6 <= VAR6;
if (VAR33) begin
VAR35 <= VAR29;
VAR35[VAR48] <= 1'b0;
if (VAR27)
VAR57 <= VAR7;
end
else
VAR57 <= VAR30;
VAR6 <= VAR51;
end
else if (VAR36) begin
VAR35 <= VAR29;
VAR35[VAR48] <= 1'b0; if (VAR27)
VAR57 <= VAR7;
end
else
VAR57 <= VAR30;
VAR6 <= 1'b0;
end
end
end
always @ (posedge clk)
begin
if (reset)
VAR60 <= 1'b0;
end
else begin
VAR60 <= 1'b0;
if (VAR40)
VAR60 <= 1'b1;
end
end
assign VAR41 = VAR35;
assign VAR46 = VAR57;
assign VAR16 = VAR6;
assign VAR34 = VAR3;
endmodule
|
mit
|
tmolteno/TART
|
hardware/FPGA/wishbone/rtl/wb_fetch.v
| 8,088 |
module MODULE1
parameter VAR13 = 1<<VAR5, parameter VAR14 = VAR13-1, parameter VAR5 = 2, parameter VAR21 = VAR5-1,
parameter VAR30 = 1,
parameter VAR11 = 3) (
input VAR26,
input VAR29,
output reg VAR2 = 1'b0,
output reg VAR8 = 1'b0,
output VAR16,
input VAR18,
input VAR28,
input VAR6,
input VAR10,
output [VAR22:0] VAR23,
input VAR20,
output reg VAR15 = 1'b0
);
parameter VAR19 = {VAR33{1'b0}};
parameter VAR9 = {VAR5{1'b0}};
parameter VAR3 = {{VAR21{1'b0}}, 1'b1};
reg [VAR22:0] VAR32 = VAR19;
assign VAR16 = 1'b0;
assign VAR23 = VAR32;
reg [VAR21:0] VAR31 = VAR14;
wire [VAR33:0] VAR25 = VAR32 + 1;
wire VAR4 = VAR32 == VAR1;
wire VAR24, VAR27;
assign VAR24 = !VAR10 && !VAR6 && !(VAR31 == VAR9 && VAR18);
assign VAR27 = VAR28 || !VAR4;
always @(posedge VAR26)
if (VAR29)
{VAR2, VAR8} <= #VAR11 2'b00;
else if (VAR20)
{VAR2, VAR8} <= #VAR11 2'b11;
else if (VAR2)
{VAR2, VAR8} <= #VAR11 {VAR24, VAR27};
else
{VAR2, VAR8} <= #VAR11 2'b00;
always @(posedge VAR26)
if (VAR20) VAR32 <= #VAR11 VAR19;
else if (VAR8 && !VAR28 && !VAR4) VAR32 <= #VAR11 VAR25[VAR22:0];
always @(posedge VAR26)
if (VAR20) VAR31 <= #VAR11 VAR14;
else
case ({VAR8, VAR18, VAR28})
3'b000: VAR31 <= #VAR11 VAR31; 3'b001: VAR31 <= #VAR11 3'VAR12; 3'b010: VAR31 <= #VAR11 VAR31 - 1; 3'b011: VAR31 <= #VAR11 3'VAR12; 3'b100: VAR31 <= #VAR11 VAR31 + 1; 3'b101: VAR31 <= #VAR11 VAR31; 3'b110: VAR31 <= #VAR11 VAR31; 3'b111: VAR31 <= #VAR11 VAR31 - 1; endcase
always @(posedge VAR26)
VAR15 <= #VAR11 VAR2 && !VAR24;
wire [VAR33:0] VAR7 = VAR17 - 1;
wire VAR24 = !VAR10 && !VAR6 && (VAR17 > 0 || !VAR18);
wire VAR27 = VAR8 && (VAR32 < VAR1 || VAR28);
always @(posedge VAR26)
if (VAR29)
{VAR2, VAR8} <= #VAR11 2'b00;
else if (VAR20)
{VAR2, VAR8} <= #VAR11 2'b11;
else if (VAR2)
{VAR2, VAR8} <= #VAR11 {VAR24, VAR27};
else
{VAR2, VAR8} <= #VAR11 2'b00;
always @(posedge VAR26)
if (VAR20)
VAR32 <= #VAR11 {VAR33{1'b0}};
else if (VAR2 && !VAR28)
VAR32 <= #VAR11 VAR25[VAR22:0];
always @(posedge VAR26)
if (VAR29 || VAR15)
VAR17 <= #VAR11 VAR1;
else if (VAR2 && VAR18)
VAR17 <= #VAR11 VAR7[VAR22:0];
always @(posedge VAR26)
VAR15 <= #VAR11 VAR2 && VAR17 == VAR19 && VAR18;
endmodule
|
lgpl-3.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_054.v
| 1,527 |
module MODULE1 (
VAR14,
VAR12
);
input [31:0] VAR14;
output [31:0]
VAR12;
wire [31:0]
VAR7,
VAR13,
VAR4,
VAR2,
VAR10,
VAR5,
VAR11,
VAR6,
VAR3;
assign VAR7 = VAR14;
assign VAR6 = VAR10 << 2;
assign VAR3 = VAR11 - VAR6;
assign VAR11 = VAR5 - VAR4;
assign VAR5 = VAR10 << 6;
assign VAR10 = VAR4 - VAR2;
assign VAR13 = VAR7 << 9;
assign VAR4 = VAR7 + VAR13;
assign VAR2 = VAR7 << 3;
assign VAR12 = VAR3;
endmodule
module MODULE2(
VAR14,
VAR12,
clk
);
input [31:0] VAR14;
output [31:0] VAR12;
reg [31:0] VAR12;
input clk;
reg [31:0] VAR1;
wire [30:0] VAR9;
always @(posedge clk) begin
VAR1 <= VAR14;
VAR12 <= VAR9;
end
MODULE1 MODULE1(
.VAR14(VAR1),
.VAR12(VAR9)
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.behavioral.v
| 1,517 |
module MODULE1 (
VAR10 ,
VAR11,
VAR12
);
output VAR10 ;
input VAR11;
input VAR12 ;
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR8 ;
wire VAR6;
not VAR4 (VAR8 , VAR11 );
and VAR3 (VAR6, VAR8, VAR12 );
buf VAR1 (VAR10 , VAR6 );
endmodule
|
apache-2.0
|
AnAtomInTheUniverse/578_project_col_panic
|
final_verilog/verif/router/ugal_source.v
| 9,987 |
module MODULE1(
VAR61, VAR79,
clk, reset, VAR19, VAR69, VAR77, VAR26, VAR12,
VAR29
);
parameter VAR22 = 3;
parameter VAR17 = 16;
parameter VAR3 = 1;
localparam VAR56 = 2;
localparam VAR39 = VAR3 * VAR56;
parameter VAR9 = 1;
localparam VAR81 = VAR39 * VAR9;
parameter VAR63 = 6;
parameter VAR46 = 4;
localparam VAR68 = VAR7(VAR46);
parameter VAR23 = 2;
localparam VAR11 = VAR23 * VAR68;
parameter VAR32 = 4;
localparam VAR76 = VAR7(VAR32);
localparam VAR80 = VAR11 + VAR76;
parameter VAR6 = VAR10;
localparam VAR74
= ((VAR6 == VAR2) ||
(VAR6 == VAR50)) ?
2 :
(VAR6 == VAR10) ?
(VAR46 - 1) :
-1;
localparam VAR42
= VAR23 * VAR74 + VAR32;
localparam VAR20 = VAR7(VAR42);
parameter VAR24 = VAR5;
parameter VAR49 = VAR18;
localparam VAR15
= (VAR24 == VAR5) ?
(VAR56 * VAR11 + VAR76) :
-1;
parameter VAR36 = VAR31;
input clk;
input reset;
input VAR19;
input VAR69;
input [0:VAR11-1] VAR77;
input [0:VAR3-1] VAR26;
input [0:VAR80-1] VAR12;
localparam VAR62 = VAR7(VAR17)+1;
input [0:(VAR42-VAR32)*VAR62-1] VAR29;
output [0:VAR11-1] VAR61;
output VAR79;
localparam [0:VAR56-1] VAR34
= (1 << (VAR56 - 1 - 1));
wire [0:VAR42-1] VAR4;
wire [0:VAR56-1] VAR40;
VAR73
.VAR46(VAR46),
.VAR9(VAR9),
.VAR23(VAR23),
.VAR32(VAR32),
.VAR6(VAR6),
.VAR24(VAR24),
.VAR49(VAR49))
VAR13
(.VAR35(VAR77),
.VAR26('d1),
.VAR34(VAR34),
.VAR12({VAR77,VAR12}),
.VAR25(VAR4),
.VAR40(VAR40));
localparam [0:VAR56-1] VAR64
= (1 << (VAR56 - 1 - 0));
wire [0:VAR42-1] VAR27;
wire [0:VAR56-1] VAR66;
VAR73
.VAR46(VAR46),
.VAR9(VAR9),
.VAR23(VAR23),
.VAR32(VAR32),
.VAR6(VAR6),
.VAR24(VAR24),
.VAR49(VAR49))
VAR21
(.VAR35(VAR77),
.VAR26('d1),
.VAR34(VAR64),
.VAR12({VAR61,VAR12}),
.VAR25(VAR27),
.VAR40(VAR66));
wire [0:VAR62-1] VAR58;
wire [0:VAR62-1] VAR52;
VAR78
.VAR8 (VAR62))
VAR82
(
.VAR75 (VAR58[0:VAR62-1]),
.select (VAR4[0:VAR42-VAR32-1]),
.VAR48 ( VAR29[0:(VAR42-VAR32)*VAR62-1]));
VAR78
.VAR8 (VAR62))
VAR65
(
.VAR75 (VAR52[0:VAR62-1]),
.select (VAR27[0:VAR42-VAR32-1]),
.VAR48 ( VAR29[0:(VAR42-VAR32)*VAR62-1]));
wire VAR67 ;
wire VAR45;
wire [0:VAR62-1+2] VAR33;
assign VAR33 [0:VAR62-1+2] = {VAR58[0:VAR62-1],2'b0};
wire [0:VAR62-1+2] VAR44;
assign VAR44 [0:VAR62-1+2] = {1'b0,VAR52[0:VAR62-1],1'b0};
assign VAR67 =( (VAR44+VAR22) > VAR33);
wire VAR43 = (VAR69&VAR19)?VAR67:VAR45;
localparam VAR57 = VAR42-VAR32;
assign VAR79 = |(VAR4[VAR57:VAR42-1])|VAR43;
VAR30
.VAR36 (VAR36),
.VAR59 (1'b1))
VAR1
(
.VAR14 (VAR45),
.clk (clk),
.reset (reset),
.VAR16 (VAR16),
.VAR70 ((VAR69&VAR19)?VAR67:VAR45));
wire [0:VAR11-1] VAR41;
wire [0:VAR11-1] VAR71;
VAR72
.VAR53(1))
VAR38
(.VAR28(VAR71));
VAR55
.VAR8 ( VAR11),
.VAR54 ( VAR11),
.VAR36 (VAR36))
VAR60
(
.VAR14 (VAR41[0:VAR11-1]),
.clk (clk),
.reset (reset),
.VAR37 (reset),
.VAR51 (VAR69&VAR19),
.VAR28 (VAR71[0:VAR11-1]),
.VAR83 (1'b0),
.VAR70 (VAR41[0:VAR11-1]));
wire VAR47;
assign {VAR61[0:VAR11-1],VAR47} = {VAR77[0:VAR11-1],1'b0}+{VAR41[0:VAR11-1],1'b0};
endmodule
|
gpl-2.0
|
fredchen00/MDA-Software
|
fpga/fpga_hw/top_level/RS232/Altera_UP_RS232_Counters.v
| 4,252 |
module MODULE1 (
clk,
reset,
VAR7,
VAR8,
VAR3,
VAR11
);
parameter VAR5 = 9;
parameter VAR2 = 9'd1;
parameter VAR1 = 9'd433;
parameter VAR9 = 9'd216;
parameter VAR6 = 11;
input clk;
input reset;
input VAR7;
output reg VAR8;
output reg VAR3;
output reg VAR11;
reg [(VAR5 - 1):0] VAR4;
reg [3:0] VAR10;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR4 <= {VAR5{1'b0}};
end
else if (VAR7)
VAR4 <= {VAR5{1'b0}};
else if (VAR4 == VAR1)
VAR4 <= {VAR5{1'b0}};
else
VAR4 <= VAR4 + VAR2;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR8 <= 1'b0;
end
else if (VAR4 == VAR1)
VAR8 <= 1'b1;
else
VAR8 <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR3 <= 1'b0;
end
else if (VAR4 == VAR9)
VAR3 <= 1'b1;
else
VAR3 <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR10 <= 4'h0;
end
else if (VAR7)
VAR10 <= 4'h0;
else if (VAR10 == VAR6)
VAR10 <= 4'h0;
else if (VAR4 == VAR1)
VAR10 <= VAR10 + 4'h1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR11 <= 1'b0;
end
else if (VAR10 == VAR6)
VAR11 <= 1'b1;
else
VAR11 <= 1'b0;
end
endmodule
|
apache-2.0
|
LoniasGR/Just_NTUA_ECE_Stuff
|
MicroSys/Assignment_2/Exercise_7/exercise_8_10.v
| 1,159 |
module MODULE1 (output reg [1:0] state, input VAR1, VAR4, VAR3);
VAR2 state = 2'b00;
always @ (posedge VAR3) begin
case ({VAR1,VAR4})
2'b00: begin if (state == 2'b00) state <= state;
end
else if (state == 2'b01) state <= 2'b10;
end
else if (state == 2'b10) state <= 2'b00;
else state <= 2'b10;
end
2'b01: begin if (state == 2'b00) state <= state;
end
else if (state == 2'b01) state <= 2'b11;
else if (state == 2'b10) state <= 2'b00;
else state <= state;
end
2'b10: begin if (state == 2'b00) state <= 2'b01;
end
else if (state == 2'b01) state <= 2'b10;
else if (state == 2'b10) state <= state;
else state <= 2'b00;
end
2'b11: begin if (state == 2'b00) state <= 2'b01;
end
else if (state == 2'b01) state <= 2'b11;
else if (state == 2'b10) state <= 2'b11;
else state <= 2'b00;
end
endcase
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/or4b/sky130_fd_sc_lp__or4b_m.v
| 2,288 |
module MODULE2 (
VAR10 ,
VAR6 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR1,
VAR4,
VAR9 ,
VAR2
);
output VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR9 ;
input VAR2 ;
VAR7 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR10 ,
VAR6 ,
VAR8 ,
VAR11 ,
VAR5
);
output VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR5;
supply1 VAR1;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR2 ;
VAR7 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
alexforencich/verilog-ethernet
|
lib/axis/rtl/axis_crosspoint.v
| 6,193 |
module MODULE1 #
(
parameter VAR27 = 4,
parameter VAR37 = 4,
parameter VAR36 = 8,
parameter VAR16 = (VAR36>8),
parameter VAR25 = ((VAR36+7)/8),
parameter VAR9 = 1,
parameter VAR40 = 0,
parameter VAR1 = 8,
parameter VAR4 = 0,
parameter VAR29 = 8,
parameter VAR20 = 1,
parameter VAR15 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR27*VAR36-1:0] VAR13,
input wire [VAR27*VAR25-1:0] VAR43,
input wire [VAR27-1:0] VAR7,
input wire [VAR27-1:0] VAR3,
input wire [VAR27*VAR1-1:0] VAR8,
input wire [VAR27*VAR29-1:0] VAR42,
input wire [VAR27*VAR15-1:0] VAR2,
output wire [VAR37*VAR36-1:0] VAR30,
output wire [VAR37*VAR25-1:0] VAR14,
output wire [VAR37-1:0] VAR31,
output wire [VAR37-1:0] VAR26,
output wire [VAR37*VAR1-1:0] VAR19,
output wire [VAR37*VAR29-1:0] VAR32,
output wire [VAR37*VAR15-1:0] VAR38,
input wire [VAR37*VAR44(VAR27)-1:0] select
);
parameter VAR10 = VAR44(VAR27);
reg [VAR27*VAR36-1:0] VAR18 = {VAR27*VAR36{1'b0}};
reg [VAR27*VAR25-1:0] VAR5 = {VAR27*VAR25{1'b0}};
reg [VAR27-1:0] VAR34 = {VAR27{1'b0}};
reg [VAR27-1:0] VAR23 = {VAR27{1'b0}};
reg [VAR27*VAR1-1:0] VAR22 = {VAR27*VAR1{1'b0}};
reg [VAR27*VAR29-1:0] VAR28 = {VAR27*VAR29{1'b0}};
reg [VAR27*VAR15-1:0] VAR35 = {VAR27*VAR15{1'b0}};
reg [VAR37*VAR36-1:0] VAR6 = {VAR37*VAR36{1'b0}};
reg [VAR37*VAR25-1:0] VAR11 = {VAR37*VAR25{1'b0}};
reg [VAR37-1:0] VAR39 = {VAR37{1'b0}};
reg [VAR37-1:0] VAR17 = {VAR37{1'b0}};
reg [VAR37*VAR1-1:0] VAR41 = {VAR37*VAR1{1'b0}};
reg [VAR37*VAR29-1:0] VAR12 = {VAR37*VAR29{1'b0}};
reg [VAR37*VAR15-1:0] VAR21 = {VAR37*VAR15{1'b0}};
reg [VAR37*VAR10-1:0] VAR24 = {VAR37*VAR10{1'b0}};
assign VAR30 = VAR6;
assign VAR14 = VAR16 ? VAR11 : {VAR37*VAR25{1'b1}};
assign VAR31 = VAR39;
assign VAR26 = VAR9 ? VAR17 : {VAR37{1'b1}};
assign VAR19 = VAR40 ? VAR41 : {VAR37*VAR1{1'b0}};
assign VAR32 = VAR4 ? VAR12 : {VAR37*VAR29{1'b0}};
assign VAR38 = VAR20 ? VAR21 : {VAR37*VAR15{1'b0}};
integer VAR33;
always @(posedge clk) begin
VAR18 <= VAR13;
VAR5 <= VAR43;
VAR34 <= VAR7;
VAR23 <= VAR3;
VAR22 <= VAR8;
VAR28 <= VAR42;
VAR35 <= VAR2;
VAR24 <= select;
for (VAR33 = 0; VAR33 < VAR37; VAR33 = VAR33 + 1) begin
VAR6[VAR33*VAR36 +: VAR36] <= VAR18[VAR24[VAR33*VAR10 +: VAR10]*VAR36 +: VAR36];
VAR11[VAR33*VAR25 +: VAR25] <= VAR5[VAR24[VAR33*VAR10 +: VAR10]*VAR25 +: VAR25];
VAR39[VAR33] <= VAR34[VAR24[VAR33*VAR10 +: VAR10]];
VAR17[VAR33] <= VAR23[VAR24[VAR33*VAR10 +: VAR10]];
VAR41[VAR33*VAR1 +: VAR1] <= VAR22[VAR24[VAR33*VAR10 +: VAR10]*VAR1 +: VAR1];
VAR12[VAR33*VAR29 +: VAR29] <= VAR28[VAR24[VAR33*VAR10 +: VAR10]*VAR29 +: VAR29];
VAR21[VAR33*VAR15 +: VAR15] <= VAR35[VAR24[VAR33*VAR10 +: VAR10]*VAR15 +: VAR15];
end
if (rst) begin
VAR34 <= {VAR27{1'b0}};
VAR39 <= {VAR27{1'b0}};
VAR24 <= {VAR37*VAR10{1'b0}};
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o32ai/sky130_fd_sc_ms__o32ai.behavioral.pp.v
| 2,191 |
module MODULE1 (
VAR10 ,
VAR5 ,
VAR4 ,
VAR14 ,
VAR8 ,
VAR12 ,
VAR6,
VAR1,
VAR16 ,
VAR20
);
output VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR14 ;
input VAR8 ;
input VAR12 ;
input VAR6;
input VAR1;
input VAR16 ;
input VAR20 ;
wire VAR13 ;
wire VAR2 ;
wire VAR19 ;
wire VAR7;
nor VAR11 (VAR13 , VAR14, VAR5, VAR4 );
nor VAR3 (VAR2 , VAR8, VAR12 );
or VAR15 (VAR19 , VAR2, VAR13 );
VAR9 VAR18 (VAR7, VAR19, VAR6, VAR1);
buf VAR17 (VAR10 , VAR7 );
endmodule
|
apache-2.0
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_3/synth/design_1_auto_pc_3.v
| 14,654 |
module MODULE1 (
VAR52,
VAR1,
VAR17,
VAR46,
VAR86,
VAR72,
VAR97,
VAR15,
VAR29,
VAR67,
VAR43,
VAR100,
VAR58,
VAR112,
VAR8,
VAR9,
VAR91,
VAR24,
VAR35,
VAR104,
VAR38,
VAR28,
VAR73,
VAR54,
VAR13,
VAR62,
VAR114,
VAR4,
VAR42,
VAR22,
VAR79,
VAR60,
VAR78,
VAR68,
VAR89,
VAR63,
VAR70,
VAR32,
VAR23,
VAR33,
VAR111,
VAR64,
VAR49,
VAR65,
VAR51,
VAR21,
VAR83,
VAR5,
VAR40,
VAR55,
VAR76,
VAR110,
VAR19,
VAR30,
VAR71,
VAR26,
VAR106,
VAR101,
VAR103
);
input wire VAR52;
input wire VAR1;
input wire [11 : 0] VAR17;
input wire [31 : 0] VAR46;
input wire [3 : 0] VAR86;
input wire [2 : 0] VAR72;
input wire [1 : 0] VAR97;
input wire [1 : 0] VAR15;
input wire [3 : 0] VAR29;
input wire [2 : 0] VAR67;
input wire [3 : 0] VAR43;
input wire VAR100;
output wire VAR58;
input wire [11 : 0] VAR112;
input wire [31 : 0] VAR8;
input wire [3 : 0] VAR9;
input wire VAR91;
input wire VAR24;
output wire VAR35;
output wire [11 : 0] VAR104;
output wire [1 : 0] VAR38;
output wire VAR28;
input wire VAR73;
input wire [11 : 0] VAR54;
input wire [31 : 0] VAR13;
input wire [3 : 0] VAR62;
input wire [2 : 0] VAR114;
input wire [1 : 0] VAR4;
input wire [1 : 0] VAR42;
input wire [3 : 0] VAR22;
input wire [2 : 0] VAR79;
input wire [3 : 0] VAR60;
input wire VAR78;
output wire VAR68;
output wire [11 : 0] VAR89;
output wire [31 : 0] VAR63;
output wire [1 : 0] VAR70;
output wire VAR32;
output wire VAR23;
input wire VAR33;
output wire [31 : 0] VAR111;
output wire [2 : 0] VAR64;
output wire VAR49;
input wire VAR65;
output wire [31 : 0] VAR51;
output wire [3 : 0] VAR21;
output wire VAR83;
input wire VAR5;
input wire [1 : 0] VAR40;
input wire VAR55;
output wire VAR76;
output wire [31 : 0] VAR110;
output wire [2 : 0] VAR19;
output wire VAR30;
input wire VAR71;
input wire [31 : 0] VAR26;
input wire [1 : 0] VAR106;
input wire VAR101;
output wire VAR103;
VAR84 #(
.VAR95("VAR82"),
.VAR45(2),
.VAR96(1),
.VAR27(0),
.VAR57(12),
.VAR18(32),
.VAR81(32),
.VAR109(1),
.VAR90(1),
.VAR75(0),
.VAR56(1),
.VAR107(1),
.VAR77(1),
.VAR3(1),
.VAR41(1),
.VAR85(2)
) VAR39 (
.VAR52(VAR52),
.VAR1(VAR1),
.VAR17(VAR17),
.VAR46(VAR46),
.VAR86(VAR86),
.VAR72(VAR72),
.VAR97(VAR97),
.VAR15(VAR15),
.VAR29(VAR29),
.VAR67(VAR67),
.VAR44(4'VAR37),
.VAR43(VAR43),
.VAR113(1'VAR37),
.VAR100(VAR100),
.VAR58(VAR58),
.VAR112(VAR112),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR91(VAR91),
.VAR105(1'VAR37),
.VAR24(VAR24),
.VAR35(VAR35),
.VAR104(VAR104),
.VAR38(VAR38),
.VAR34(),
.VAR28(VAR28),
.VAR73(VAR73),
.VAR54(VAR54),
.VAR13(VAR13),
.VAR62(VAR62),
.VAR114(VAR114),
.VAR4(VAR4),
.VAR42(VAR42),
.VAR22(VAR22),
.VAR79(VAR79),
.VAR59(4'VAR37),
.VAR60(VAR60),
.VAR88(1'VAR37),
.VAR78(VAR78),
.VAR68(VAR68),
.VAR89(VAR89),
.VAR63(VAR63),
.VAR70(VAR70),
.VAR32(VAR32),
.VAR98(),
.VAR23(VAR23),
.VAR33(VAR33),
.VAR50(),
.VAR111(VAR111),
.VAR20(),
.VAR93(),
.VAR94(),
.VAR69(),
.VAR12(),
.VAR64(VAR64),
.VAR48(),
.VAR6(),
.VAR102(),
.VAR49(VAR49),
.VAR65(VAR65),
.VAR53(),
.VAR51(VAR51),
.VAR21(VAR21),
.VAR10(),
.VAR66(),
.VAR83(VAR83),
.VAR5(VAR5),
.VAR99(12'VAR87),
.VAR40(VAR40),
.VAR36(1'VAR37),
.VAR55(VAR55),
.VAR76(VAR76),
.VAR14(),
.VAR110(VAR110),
.VAR74(),
.VAR7(),
.VAR11(),
.VAR61(),
.VAR92(),
.VAR19(VAR19),
.VAR16(),
.VAR2(),
.VAR47(),
.VAR30(VAR30),
.VAR71(VAR71),
.VAR31(12'VAR87),
.VAR26(VAR26),
.VAR106(VAR106),
.VAR80(1'VAR25),
.VAR108(1'VAR37),
.VAR101(VAR101),
.VAR103(VAR103)
);
endmodule
|
mit
|
skyfex/svo-raycaster
|
raycaster2/raycast_master.v
| 10,900 |
module MODULE1
(
VAR38, VAR54, VAR22,
VAR8, VAR64, VAR77,
VAR74, VAR68, VAR21,
VAR42, VAR34,
VAR33, VAR61, VAR30,
VAR25, VAR75, VAR72,
VAR15, VAR59,
VAR16, VAR50,
VAR27, VAR3, VAR62, VAR66,
VAR76,
VAR58, VAR37, VAR31, VAR20,
VAR44,
VAR70, VAR19, VAR13, VAR18,
VAR53,
VAR56, VAR10, VAR29, VAR57,
VAR11,
VAR51, VAR52,
);
parameter VAR32 = 64, VAR6 = 6;
parameter VAR5 = 5;
parameter VAR73 = 8;
parameter VAR7 = 2'b00;
input VAR51;
input VAR52;
output [31:0] VAR38;
output [3:0] VAR54;
output VAR22;
input [31:0] VAR64;
output [31:0] VAR8;
output VAR77;
output VAR74;
input VAR68;
input VAR21;
output [2:0] VAR42; output [1:0] VAR34;
input [31:0] VAR33;
input [3:0] VAR61;
input VAR30;
output [31:0] VAR25;
input [31:0] VAR75;
input VAR72;
input VAR15;
output VAR59;
input [2:0] VAR16;
input [1:0] VAR50;
input VAR62;
input VAR66;
input [31:0] VAR27;
output VAR76;
output reg [31:0] VAR3;
wire VAR55 = VAR62 & VAR66;
assign VAR76 = VAR28 & VAR62;
wire [31:0] VAR27 = 0;
reg [31:0] VAR3;
wire VAR55 = 0;
input VAR31;
input VAR20;
input [31:0] VAR58;
output VAR44;
output reg [31:0] VAR37;
wire VAR47 = VAR31 & VAR20;
assign VAR44 = VAR14 & VAR31;
wire [31:0] VAR58 = 0;
reg [31:0] VAR37;
wire VAR47 = 0;
input VAR13;
input VAR18;
input [31:0] VAR70;
output VAR53;
output reg [31:0] VAR19;
wire VAR45 = VAR13 & VAR18;
assign VAR53 = VAR49 & VAR13;
wire [31:0] VAR70 = 0;
reg [31:0] VAR19;
wire VAR45 = 0;
input VAR29;
input VAR57;
input [31:0] VAR56;
output VAR11;
output reg [31:0] VAR10;
wire VAR48 = VAR29 & VAR57;
assign VAR11 = VAR9 & VAR29;
wire [31:0] VAR56 = 0;
reg [31:0] VAR10;
wire VAR48 = 0;
reg VAR43;
reg [3:0] VAR63;
reg VAR28, VAR14, VAR49, VAR9;
reg VAR39;
reg VAR24;
reg VAR1;
reg [2:0] VAR65;
reg [2:0] VAR23;
reg VAR2;
reg [31:0] VAR26;
reg [31:0] VAR4 [0:VAR32-1];
reg [31:0] VAR71 [0:VAR32-1];
reg valid [0:VAR32-1];
reg [31:0] VAR17 = 0;
reg [31:0] VAR35 = 0;
wire [VAR6-1:0] VAR40 = VAR26[VAR6-1:0];
wire [31:0] VAR36 = VAR4[VAR40];
wire [31:0] VAR60 = VAR71[VAR40];
wire VAR69 = valid[VAR40];
wire VAR41 = (VAR69==1) && (VAR71[VAR40]==VAR26);
wire [VAR5-1:0] VAR67 = VAR26[VAR5:0]+4'd4;
wire VAR46 = VAR43 && VAR68;
assign VAR77 = !VAR2 & (!VAR43 ? VAR72 : VAR1) ;
assign VAR74 = !VAR2 & (!VAR43 ? VAR15 : VAR1) ;
assign VAR38 = !VAR43 ? VAR33 : VAR26 ;
assign VAR54 = (!VAR43 & !VAR2) ? VAR61 : 4'b1111 ;
assign VAR22 = (!VAR43 & !VAR2) ? VAR30 : 0 ;
assign VAR8 = (!VAR43 & !VAR2) ? VAR75 : 0 ;
assign VAR42 = (!VAR43 & !VAR2) ? VAR16 : 0; assign VAR34 = (!VAR43 & !VAR2) ? VAR50 : VAR7 ;
assign VAR25 = (!VAR43 & !VAR2) ? VAR64: 32'b0;
assign VAR59 = !VAR2 & !VAR43 & VAR68;
always @(posedge VAR51) begin
if (VAR52) begin
VAR43 <= 0;
VAR2 <= 0;
end
else begin
if (VAR2) begin
VAR2 <= 0;
end
else begin
if (VAR43) begin
if (VAR68) begin
VAR43 <= 0;
VAR2 <= 1;
end
end
else if (!VAR72 && VAR1) begin
VAR43 <= 1;
VAR2 <= 1;
end
end
end
end
always @(posedge VAR51) begin
if (VAR52) begin
VAR63 <= 4'b0;
VAR39 <= 0;
VAR26 <= 0;
end
else if (!VAR39 && !VAR1) begin
if (VAR55 && !VAR28) begin
VAR26 <= VAR27;
VAR63[0] <= 1;
VAR39 <= 1;
end else
if (VAR47 && !VAR14) begin
VAR26 <= VAR58;
VAR63[1] <= 1;
VAR39 <= 1;
end else
if (VAR45 && !VAR49) begin
VAR26 <= VAR70;
VAR63[2] <= 1;
VAR39 <= 1;
end else
if (VAR48 && !VAR9) begin
VAR26 <= VAR56;
VAR63[3] <= 1;
VAR39 <= 1;
end
end
else begin
VAR39 <= 0;
if (VAR46)
VAR26 <= {VAR26[31:VAR5], VAR67};
if (VAR41 || VAR46)
VAR63 <= 0;
end
end
always @(posedge VAR51) begin
if (VAR52) begin
VAR1 <= 0;
end
else if (VAR1) begin
if (VAR46) begin
VAR35 = VAR35 + 1;
if (VAR63[0]) begin
VAR3 <= VAR64;
end
if (VAR63[1]) begin
VAR37 <= VAR64;
end
if (VAR63[2]) begin
VAR19 <= VAR64;
end
if (VAR63[3]) begin
VAR10 <= VAR64;
end
VAR1 <= 0;
end
end
else if (VAR39) begin
if (VAR41) begin
VAR17 = VAR17 + 1;
if (VAR63[0]) begin
VAR3 <= VAR36;
end
if (VAR63[1]) begin
VAR37 <= VAR36;
end
if (VAR63[2]) begin
VAR19 <= VAR36;
end
if (VAR63[3]) begin
VAR10 <= VAR36;
end
end
else begin
VAR1 <= 1;
end
end
end
always @(posedge VAR51)
begin
if (VAR46) begin
VAR24 <= 1;
VAR4[VAR40] <= VAR64;
VAR71[VAR40] <= VAR26;
valid[VAR40] <= 1;
end
else begin
VAR24 <= 0;
end
end
always @(posedge VAR51)
if (VAR52)
VAR28 <= 0;
else if (VAR28)
VAR28 <= 0;
else if (VAR63[0]) begin
if (VAR24)
VAR28 <= 1;
end
else if (VAR39 && VAR41)
VAR28 <= 1;
end
always @(posedge VAR51)
if (VAR52)
VAR14 <= 0;
else if (VAR14)
VAR14 <= 0;
else if (VAR63[1]) begin
if (VAR24)
VAR14 <= 1;
end
else if (VAR39 && VAR41)
VAR14 <= 1;
end
always @(posedge VAR51)
if (VAR52)
VAR49 <= 0;
else if (VAR49)
VAR49 <= 0;
else if (VAR63[2]) begin
if (VAR24)
VAR49 <= 1;
end
else if (VAR39 && VAR41)
VAR49 <= 1;
end
always @(posedge VAR51)
if (VAR52)
VAR9 <= 0;
else if (VAR9)
VAR9 <= 0;
else if (VAR63[3]) begin
if (VAR24)
VAR9 <= 1;
end
else if (VAR39 && VAR41)
VAR9 <= 1;
end
integer VAR12;
begin
|
mit
|
mbus/mbus
|
layer_controller_v1/verilog/mem_ctrl.v
| 2,106 |
module MODULE1(
VAR19,
VAR4,
VAR16,
VAR11,
VAR10,
VAR8,
VAR17,
VAR3
);
parameter VAR9 = 65536;
parameter VAR2 = 32;
parameter VAR13 = 32;
input VAR19;
input VAR4;
input [VAR13-3:0] VAR16;
input [VAR2-1:0] VAR11;
input VAR10;
input VAR8;
output reg [VAR2-1:0] VAR17;
output reg VAR3;
wire [VAR7(VAR9-1)-1:0] VAR5 = VAR16[VAR7(VAR9-1)-1:0];
reg [VAR2-1:0] VAR1 [0:VAR9-1];
reg [1:0] fsm;
parameter VAR6 = 2'b00;
parameter VAR12 = 2'b01;
parameter VAR18 = 2'b10;
parameter VAR15 = 2'b11;
integer VAR14;
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
|
apache-2.0
|
peteasa/parallella-fpga
|
AdiHDLLib/library/common/ad_addsub.v
| 4,383 |
module MODULE1 (
clk,
VAR11,
VAR5,
out,
VAR1
);
parameter VAR3 = 32;
parameter VAR12 = 32'h1;
parameter VAR13 = 0;
localparam VAR10 = 1;
localparam VAR6 = 0;
input clk;
input [(VAR3-1):0] VAR11;
input [(VAR3-1):0] VAR5;
output [(VAR3-1):0] out;
input VAR1;
reg [(VAR3-1):0] out = 'b0;
reg [VAR3:0] VAR7 = 'b0;
reg [VAR3:0] VAR9 = 'b0;
reg [(VAR3-1):0] VAR15 = 'b0;
reg [(VAR3-1):0] VAR2 = 'b0;
reg [(VAR3-1):0] VAR4 = 'b0;
reg [(VAR3-1):0] VAR8 = 'b0;
reg [(VAR3-1):0] VAR14 = VAR12;
always @(posedge clk) begin
VAR15 <= VAR11;
VAR2 <= VAR15;
VAR4 <= VAR5;
VAR8 <= VAR4;
end
always @(posedge clk) begin
if ( VAR13 == VAR10 ) begin
VAR7 <= VAR15 + VAR14;
end else begin
VAR7 <= VAR15 - VAR14;
end
end
always @(posedge clk) begin
if ( VAR13 == VAR10 ) begin
if ( VAR7 > VAR8 ) begin
VAR9 <= VAR7 - VAR8;
end else begin
VAR9 <= VAR7;
end
end else begin if ( VAR7[VAR3] == 1'b1 ) begin
VAR9 <= VAR8 + VAR7;
end else begin
VAR9 <= VAR7;
end
end
end
always @(posedge clk) begin
if ( VAR1 ) begin
out <= VAR9;
end else begin
out <= 'b0;
end
end
endmodule
|
lgpl-3.0
|
lucasrangit/Multicycle_MIPS
|
mipsparts.v
| 2,949 |
module MODULE1( input [31:0] VAR18, VAR3,
input [2:0] VAR13,
output reg [31:0] VAR11, output VAR20);
always @ ( * )
case (VAR13[2:0])
3'b000: VAR11 <= VAR18 & VAR3;
3'b001: VAR11 <= VAR18 | VAR3;
3'b010: VAR11 <= VAR18 + VAR3;
3'b011: VAR11 <= VAR18 & ~VAR3;
3'b101: VAR11 <= VAR18 + ~VAR3;
3'b110: VAR11 <= VAR18 - VAR3;
3'b111: VAR11 <= VAR18 < VAR3 ? 1:0;
default: VAR11 <= 0; endcase
assign VAR20 = (VAR11 == 32'b0);
endmodule
module MODULE2(input clk,
input VAR14,
input [4:0] VAR19, VAR1, VAR23,
input [31:0] VAR10,
output [31:0] VAR12, VAR4);
reg [31:0] VAR22[31:0];
always @(posedge clk)
if (VAR14) VAR22[VAR23] <= VAR10;
assign VAR12 = (VAR19 != 0) ? VAR22[VAR19] : 0;
assign VAR4 = (VAR1 != 0) ? VAR22[VAR1] : 0;
endmodule
module MODULE7(input [31:0] VAR17,
output [31:0] VAR2);
assign VAR2 = {VAR17[29:0], 2'b00};
endmodule
module MODULE6(input [15:0] VAR17,
output [31:0] VAR2);
assign VAR2 = {{16{VAR17[15]}}, VAR17};
endmodule
module MODULE5 #(parameter VAR6 = 8)
(input clk, reset,
input [VAR6-1:0] VAR15,
output reg [VAR6-1:0] VAR16);
always @(posedge clk, posedge reset)
if (reset) VAR16 <= 0;
else VAR16 <= VAR15;
endmodule
module MODULE3 #(parameter VAR6 = 8)
(input clk, reset,
input en,
input [VAR6-1:0] VAR15,
output reg [VAR6-1:0] VAR16);
always @(posedge clk, posedge reset)
if (reset) VAR16 <= 0;
else if (en) VAR16 <= VAR15;
endmodule
module MODULE8 #(parameter VAR6 = 8)
(input [VAR6-1:0] VAR7, VAR21,
input VAR9,
output [VAR6-1:0] VAR2);
assign VAR2 = VAR9 ? VAR21 : VAR7;
endmodule
module MODULE4 #(parameter VAR6 = 8)
(input [VAR6-1:0] VAR7, VAR21, VAR8,
input [1:0] VAR9,
output [VAR6-1:0] VAR2);
assign VAR2 = VAR9[1] ? VAR8 : (VAR9[0] ? VAR21 : VAR7);
endmodule
module MODULE9 #(parameter VAR6 = 8)
(input [VAR6-1:0] VAR7, VAR21, VAR8, VAR5,
input [1:0] VAR9,
output reg [VAR6-1:0] VAR2);
always @( * )
case(VAR9)
2'b00: VAR2 <= VAR7;
2'b01: VAR2 <= VAR21;
2'b10: VAR2 <= VAR8;
2'b11: VAR2 <= VAR5;
endcase
endmodule
|
apache-2.0
|
olajep/oh
|
src/adi/hdl/library/axi_dmac/dest_axi_mm.v
| 6,435 |
module MODULE1 #(
parameter VAR29 = 3,
parameter VAR40 = 64,
parameter VAR56 = 32,
parameter VAR73 = VAR4(VAR40/8),
parameter VAR5 = 4,
parameter VAR7 = 128,
parameter VAR61 = VAR4(VAR7),
parameter VAR32 = 8)(
input VAR26,
input VAR47,
input VAR34,
output VAR51,
input [VAR56-1:VAR73] VAR36,
input VAR17,
output VAR74,
input [VAR5-1:0] VAR30,
input enable,
output VAR15,
output VAR9,
input VAR23,
output [1:0] VAR53,
output VAR12,
output VAR18,
output [VAR61-1:0] VAR76,
input [VAR29-1:0] VAR10,
output [VAR29-1:0] VAR28,
output [VAR29-1:0] VAR68,
input VAR55,
input VAR72,
input VAR64,
output VAR43,
input [VAR40-1:0] VAR2,
input VAR58,
input [VAR61-1:0] VAR1,
input VAR63,
input [VAR29-1:0] VAR60,
input VAR44,
input VAR59,
output VAR70,
output [VAR56-1:0] VAR25,
output [VAR32-1:0] VAR8,
output [ 2:0] VAR66,
output [ 1:0] VAR50,
output [ 2:0] VAR49,
output [ 3:0] VAR16,
output [VAR40-1:0] VAR22,
output [(VAR40/8)-1:0] VAR14,
input VAR24,
output VAR38,
output VAR69,
input VAR13,
input [ 1:0] VAR3,
output VAR20
);
wire VAR46;
VAR42 #(
.VAR29(VAR29),
.VAR5(VAR5),
.VAR73(VAR73),
.VAR40(VAR40),
.VAR65(VAR32),
.VAR56(VAR56)
) VAR31 (
.clk(VAR26),
.VAR62(VAR47),
.enable(enable),
.VAR15(VAR46),
.VAR77(VAR68),
.VAR10(VAR10),
.VAR34(VAR34),
.VAR51(VAR51),
.VAR36(VAR36),
.VAR17(VAR17),
.VAR74(VAR74),
.VAR30(VAR30),
.VAR41(VAR55),
.VAR57(VAR59),
.VAR11(VAR70),
.addr(VAR25),
.VAR39(VAR8),
.VAR21(VAR66),
.VAR52(VAR50),
.VAR37(VAR49),
.VAR45(VAR16)
);
assign VAR38 = VAR64;
assign VAR43 = VAR24;
assign VAR69 = VAR58;
assign VAR22 = VAR2;
assign VAR14 = {(VAR40/8){1'b1}};
VAR27 #(
.VAR29(VAR29)
) VAR35 (
.clk(VAR26),
.VAR62(VAR47),
.VAR33(VAR13),
.VAR71(VAR20),
.VAR48(VAR3),
.enable(VAR46),
.VAR15(VAR15),
.VAR77(VAR28),
.VAR10(VAR68),
.VAR41(VAR72),
.VAR54(VAR9),
.VAR67(VAR23),
.VAR6(VAR53),
.VAR75(VAR12)
);
reg [VAR61+1-1:0] VAR19 [0:2**(VAR29)-1];
assign {VAR18,
VAR76} = VAR19[VAR28];
always @(posedge VAR26) begin
if (VAR44) begin
VAR19[VAR60] <= {VAR63,
VAR1};
end
end
endmodule
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.functional.v
| 1,664 |
module MODULE1( VAR2, VAR12, VAR22, VAR9, VAR15, VAR7 );
input VAR9, VAR22, VAR2, VAR12, VAR7;
output VAR15;
wire VAR19;
not VAR4( VAR19, VAR22 );
wire VAR17;
not VAR6( VAR17, VAR2 );
wire VAR3;
and VAR21( VAR3, VAR19, VAR17 );
wire VAR10;
not VAR18( VAR10, VAR12 );
wire VAR13;
and VAR5( VAR13, VAR19, VAR10 );
wire VAR16;
and VAR20( VAR16, VAR10, VAR2 );
or VAR1( VAR14, VAR3, VAR13, VAR16 );
VAR11( VAR8, 1'b0, 1'b0, VAR9, VAR14, VAR7 );
not VAR23( VAR15, VAR8 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/edfxtp/sky130_fd_sc_hs__edfxtp.blackbox.v
| 1,309 |
module MODULE1 (
VAR4 ,
VAR3,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR3;
input VAR1 ;
input VAR2 ;
supply1 VAR5;
supply0 VAR6;
endmodule
|
apache-2.0
|
scalable-networks/ext
|
uhd/fpga/usrp1/megacells/fifo_1kx16_bb.v
| 5,864 |
module MODULE1 (
VAR2,
VAR3,
VAR8,
VAR1,
VAR6,
VAR4,
VAR7,
VAR9,
VAR5,
VAR10);
input VAR2;
input VAR3;
input [15:0] VAR8;
input VAR1;
input VAR6;
output VAR4;
output VAR7;
output VAR9;
output [15:0] VAR5;
output [9:0] VAR10;
endmodule
|
gpl-2.0
|
intelligenttoasters/CPC2.0
|
FPGA/Quartus/custom/audio_clock/audio_clock_0002.v
| 2,141 |
module MODULE1(
input wire VAR70,
input wire rst,
output wire VAR8,
output wire VAR49,
output wire VAR50
);
VAR51 #(
.VAR20("false"),
.VAR54("12.0 VAR46"),
.VAR62("VAR63"),
.VAR43(2),
.VAR61("3.072000 VAR46"),
.VAR14("0 VAR35"),
.VAR17(50),
.VAR60("1.000000 VAR46"),
.VAR71("0 VAR35"),
.VAR53(50),
.VAR30("0 VAR46"),
.VAR4("0 VAR35"),
.VAR15(50),
.VAR41("0 VAR46"),
.VAR26("0 VAR35"),
.VAR12(50),
.VAR47("0 VAR46"),
.VAR52("0 VAR35"),
.VAR55(50),
.VAR73("0 VAR46"),
.VAR6("0 VAR35"),
.VAR2(50),
.VAR42("0 VAR46"),
.VAR5("0 VAR35"),
.VAR29(50),
.VAR66("0 VAR46"),
.VAR16("0 VAR35"),
.VAR31(50),
.VAR10("0 VAR46"),
.VAR1("0 VAR35"),
.VAR39(50),
.VAR67("0 VAR46"),
.VAR45("0 VAR35"),
.VAR59(50),
.VAR65("0 VAR46"),
.VAR37("0 VAR35"),
.VAR36(50),
.VAR64("0 VAR46"),
.VAR22("0 VAR35"),
.VAR40(50),
.VAR7("0 VAR46"),
.VAR32("0 VAR35"),
.VAR21(50),
.VAR58("0 VAR46"),
.VAR48("0 VAR35"),
.VAR13(50),
.VAR56("0 VAR46"),
.VAR72("0 VAR35"),
.VAR19(50),
.VAR44("0 VAR46"),
.VAR3("0 VAR35"),
.VAR38(50),
.VAR34("0 VAR46"),
.VAR33("0 VAR35"),
.VAR11(50),
.VAR18("0 VAR46"),
.VAR23("0 VAR35"),
.VAR25(50),
.VAR24("VAR57"),
.VAR27("VAR57")
) VAR68 (
.rst (rst),
.VAR9 ({VAR49, VAR8}),
.VAR50 (VAR50),
.VAR69 ( ),
.VAR28 (1'b0),
.VAR70 (VAR70)
);
endmodule
|
gpl-3.0
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_control.v
| 6,902 |
module MODULE1 (
output wire VAR28 ,
input wire VAR43 ,
input wire [31 : 0] VAR8 ,
input wire VAR2 ,
output wire VAR51 ,
output wire [31 : 0] VAR56 ,
output wire VAR16 ,
input wire VAR31 ,
input wire VAR14 ,
input wire VAR24 ,
output wire VAR47 ,
output wire [23 : 0] VAR1 ,
output wire [23 : 0] VAR7 ,
output wire [23 : 0] VAR67 ,
output wire VAR32 ,
input wire VAR22 ,
input wire VAR15 ,
input wire VAR38 ,
output wire VAR10 ,
output wire [23 : 0] VAR42 ,
output wire [23 : 0] VAR39 ,
output wire [23 : 0] VAR40 ,
output wire [ 3 : 0] VAR23 ,
output wire [ 3 : 0] VAR26 ,
output wire [ 3 : 0] VAR33 ,
output wire [ 3 : 0] VAR21 ,
output wire [ 3 : 0] VAR63 ,
output wire [ 3 : 0] VAR3 ,
input wire VAR46 ,
input wire VAR17
);
localparam VAR27 = 6'd1;
localparam VAR5 = 6'd2;
localparam VAR35 = 6'd3;
localparam VAR44 = 6'd4;
localparam VAR41 = 6'd5;
localparam VAR34 = 6'd6;
localparam VAR68 = 6'd7;
localparam VAR20 = 8'h1;
localparam VAR48 = 8'hA;
localparam VAR36 = 8'h11;
localparam VAR62 = 8'h12;
localparam VAR61 = 8'h13;
localparam VAR6 = 8'h14;
localparam VAR55 = 8'h21;
localparam VAR50 = 8'h22;
localparam VAR45 = 8'h23;
localparam VAR12 = 8'h24;
wire VAR18;
reg [ 5:0] state ;
reg [31:0] VAR13 ;
reg [31:0] VAR53 ;
reg [31:0] VAR52 ;
reg [31:0] VAR9 ;
assign VAR28 = (state == VAR27);
assign VAR51 = (state == VAR68);
assign VAR56 = VAR53;
reg VAR29;
reg VAR60;
reg [3:0] VAR64;
reg [3:0] VAR49;
reg [3:0] VAR65;
reg [3:0] VAR54;
reg [3:0] VAR25;
reg [3:0] VAR58;
reg [23:0] VAR19 ;
reg [23:0] VAR57 ;
reg [23:0] VAR11 ;
reg VAR66 ;
reg [23:0] VAR4 ;
reg [23:0] VAR30 ;
reg [23:0] VAR37 ;
reg VAR59 ;
assign VAR18 = VAR31 & VAR22;
assign VAR23 = VAR64 ;
assign VAR26 = VAR49 ;
assign VAR33 = VAR65 ;
assign VAR21 = VAR54 ;
assign VAR63 = VAR25 ;
assign VAR3 = VAR58 ;
assign VAR16 = VAR29 ;
assign VAR1 = VAR19 ;
assign VAR7 = VAR57 ;
assign VAR67 = VAR11 ;
assign VAR47 = VAR66 ;
assign VAR32 = VAR60 ;
assign VAR42 = VAR4 ;
assign VAR39 = VAR30 ;
assign VAR40 = VAR37 ;
assign VAR10 = VAR59 ;
always @(posedge VAR46)
begin
if(!VAR17) begin
state <= VAR27;
VAR29 <= 1'd0;
VAR60 <= 1'd0;
VAR66 <= 1'd0;
VAR19 <= 24'd0;
VAR57 <= 24'd0;
VAR11 <= 24'd0;
VAR59 <= 1'd0;
VAR4 <= 24'd0;
VAR30 <= 24'd0;
VAR37 <= 24'd0;
VAR13 <= 32'd0;
VAR53 <= 32'd0;
end
else begin
case (state)
VAR27: begin
if (VAR43 == 1) begin
VAR13 <= VAR8;
state <= VAR5;
end
else begin
state <= VAR27;
end
end
VAR5: begin
case (VAR13[31 : 24])
VAR20 : state <= VAR35;
VAR48 : begin
state <= VAR44;
end
VAR62 : begin
VAR19 <= VAR13[23 : 0];
state <= VAR27;
end
VAR61 : begin
VAR57 <= VAR13[23 : 0];
state <= VAR27;
end
VAR6 : begin
VAR11 <= VAR13[23 : 0];
state <= VAR27;
end
VAR36 : begin
VAR66 <= VAR13[0];
state <= VAR27;
end
VAR50 : begin
VAR4 <= VAR13[23 : 0];
state <= VAR27;
end
VAR45 : begin
VAR30 <= VAR13[23 : 0];
state <= VAR27;
end
VAR12 : begin
VAR37 <= VAR13[23 : 0];
state <= VAR27;
end
VAR55 : begin
VAR59 <= VAR13[0];
state <= VAR27;
end
default: begin
state <= VAR27;
end
endcase
end
VAR35: begin
VAR64 <= VAR13[23 : 20];
VAR49 <= VAR13[19 : 16];
VAR65 <= VAR13[15 : 12];
VAR54 <= VAR13[11 : 8];
VAR25 <= VAR13[ 7 : 4];
VAR58 <= VAR13[ 3 : 0];
state <= VAR27;
end
VAR44: begin
if (VAR14 == 1 & VAR15 == 1) begin
VAR29 <= 1;
VAR60 <= 1;
state <= VAR41;
end
else begin
state <= VAR44;
end
end
VAR41: begin
VAR29 <= 0;
VAR60 <= 0;
if (VAR31 == 0 & VAR22 == 0) begin
state <= VAR41;
end
else if (VAR31 == 1 & VAR22 == 1) begin
VAR53 <= 32'hFFFF ;
state <= VAR68 ;
end
else if (VAR31 == 1 | VAR22 == 1) begin
state <= VAR34;
end
end
VAR34: begin
if (VAR31 == 1 | VAR22 == 1) begin
VAR53 <= 32'hFFFF ;
state <= VAR68 ;
end
end
VAR68: begin
if (VAR2 == 1) begin
state <= VAR27;
end
else begin
state <= VAR68;
end
end
endcase
end
end
endmodule
|
bsd-3-clause
|
qiuzou/nysa_saya
|
rtl/phy/oob_controller.v
| 9,323 |
module MODULE1 (
input rst, input clk,
input VAR31, output reg VAR15,
output reg VAR7, output reg VAR4,
input VAR29, input VAR1,
input [31:0] VAR18,
input [3:0] VAR6,
input VAR28,
input VAR5,
output reg [31:0] VAR25,
output reg VAR19,
output reg VAR27,
output [3:0] VAR3
);
parameter VAR8 = 4'h0;
parameter VAR12 = 4'h1;
parameter VAR11 = 4'h2;
parameter VAR2 = 4'h3;
parameter VAR13 = 4'h4;
parameter VAR30 = 4'h5;
parameter VAR10 = 4'h6;
parameter VAR21 = 4'h7;
parameter VAR22 = 4'h8;
parameter VAR14 = 4'h9;
parameter VAR23 = 4'hA;
parameter VAR32 = 4'hB;
reg [3:0] state;
reg [31:0] VAR16;
reg [1:0] VAR24;
wire timeout;
wire VAR20;
wire VAR9;
assign timeout = (VAR16 == 0);
assign VAR20 = ((VAR6 > 0) && (VAR18 == VAR17) && VAR5);
assign VAR9 = ((VAR6 > 0) && (VAR18 == VAR26));
assign VAR3 = state;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o22ai/sky130_fd_sc_hd__o22ai.behavioral.pp.v
| 2,159 |
module MODULE1 (
VAR1 ,
VAR5 ,
VAR16 ,
VAR12 ,
VAR8 ,
VAR13,
VAR15,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR16 ;
input VAR12 ;
input VAR8 ;
input VAR13;
input VAR15;
input VAR10 ;
input VAR6 ;
wire VAR3 ;
wire VAR14 ;
wire VAR7 ;
wire VAR2;
nor VAR9 (VAR3 , VAR12, VAR8 );
nor VAR11 (VAR14 , VAR5, VAR16 );
or VAR19 (VAR7 , VAR14, VAR3 );
VAR17 VAR4 (VAR2, VAR7, VAR13, VAR15);
buf VAR18 (VAR1 , VAR2 );
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.behavioral.pp.v
| 2,623 |
module MODULE1( VAR3, VAR2, VAR4, VAR1, VAR7, VAR5 );
input VAR2, VAR3, VAR4;
inout VAR7, VAR5;
output VAR1;
VAR6 VAR9(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5));
VAR6 VAR8(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5));
|
apache-2.0
|
CospanDesign/python
|
game/panda/panda_path/example_project/rtl/bus/master/wishbone_master.v
| 22,457 |
module MODULE1 (
input clk,
input rst,
output reg VAR37,
input VAR58,
input VAR64,
input [31:0] VAR15,
input [31:0] VAR6,
input [31:0] VAR27,
input [27:0] VAR60,
input VAR40,
output reg VAR59 = 0,
output reg [31:0] VAR11 = 32'h0,
output reg [31:0] VAR18 = 32'h0,
output reg [31:0] VAR1 = 32'h0,
output wire [27:0] VAR68,
output reg [31:0] VAR9,
output reg [31:0] VAR48,
output reg [31:0] VAR8,
input [31:0] VAR52,
output reg VAR67,
output reg VAR41,
output reg VAR53,
output reg VAR26,
output reg [3:0] VAR21,
input VAR57,
input VAR3,
output reg VAR32,
output reg [31:0] VAR25,
output reg [31:0] VAR7,
input [31:0] VAR54,
output reg VAR66,
output reg VAR30,
output reg VAR51,
output reg [3:0] VAR70,
input VAR34,
input VAR56
);
localparam VAR63 = 32'h00000000;
localparam VAR16 = 32'h00000001;
localparam VAR29 = 32'h00000002;
localparam VAR46 = 32'h00000003;
localparam VAR35 = 32'h0000C594;
localparam VAR45 = 14;
reg [31:0] state = VAR63;
reg [31:0] VAR31 = 32'h0;
reg [31:0] VAR2 = 32'h0;
reg [27:0] VAR61 = 28'h0;
reg VAR44;
reg [31:0] VAR23 = 32'h0;
reg VAR12 = 0;
reg [31:0] VAR55 = 32'h00000000;
reg [31:0] VAR69 = VAR5;
reg [31:0] VAR36 = 0;
reg [31:0] VAR65 = 0;
reg [31:0] VAR42 = 0;
reg [31:0] VAR38 = 0;
reg [31:0] VAR33 = 0;
reg [31:0] VAR20 = 0;
reg [31:0] VAR62 = 0;
reg [31:0] VAR13 = 0;
reg [31:0] VAR47 = 0;
reg [31:0] VAR19 = 0;
reg [31:0] VAR10 = 0;
reg [31:0] VAR50 = 0;
reg [31:0] VAR17 = 0;
reg [31:0] VAR14 = 0;
reg [31:0] VAR4 = 0;
reg [31:0] VAR22 = 0;
reg VAR24 = 0;
wire [15:0] VAR43;
wire VAR28;
wire [15:0] VAR49;
wire VAR39;
assign VAR68 = ((state == VAR29) || (state == VAR46)) ? VAR61 : 28'h0;
assign VAR43 = VAR15[31:16];
assign VAR49 = VAR15[15:0];
assign VAR28 = VAR23[0];
assign VAR39 = rst & ~VAR24;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/fahcin/sky130_fd_sc_lp__fahcin.blackbox.v
| 1,332 |
module MODULE1 (
VAR1,
VAR6 ,
VAR5 ,
VAR4 ,
VAR8
);
output VAR1;
output VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR8 ;
supply1 VAR2;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
borti4938/sd2snes
|
verilog/sd2snes_gsu/ipcore_dir/gsu_mult.v
| 5,622 |
module MODULE1 (
VAR38, VAR40, VAR24
);
output [15 : 0] VAR38;
input [7 : 0] VAR40;
input [7 : 0] VAR24;
wire \VAR41/VAR32<34>VAR43 ;
wire \VAR41/VAR32<33>VAR43 ;
wire \VAR41/VAR32<32>VAR43 ;
wire \VAR41/VAR32<31>VAR43 ;
wire \VAR41/VAR32<30>VAR43 ;
wire \VAR41/VAR32<29>VAR43 ;
wire \VAR41/VAR32<28>VAR43 ;
wire \VAR41/VAR32<27>VAR43 ;
wire \VAR41/VAR32<26>VAR43 ;
wire \VAR41/VAR32<25>VAR43 ;
wire \VAR41/VAR32<24>VAR43 ;
wire \VAR41/VAR32<23>VAR43 ;
wire \VAR41/VAR32<22>VAR43 ;
wire \VAR41/VAR32<21>VAR43 ;
wire \VAR41/VAR32<20>VAR43 ;
wire \VAR41/VAR32<19>VAR43 ;
wire \VAR41/VAR32<18>VAR43 ;
wire \VAR41/VAR32<17>VAR43 ;
wire \VAR41/VAR32<16>VAR43 ;
wire \VAR41/VAR32<15>VAR43 ;
VAR42 \VAR11/VAR20 (
.VAR29({VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[7], VAR40[6], VAR40[5], VAR40[4], VAR40[3], VAR40[2], VAR40[1], VAR40[0]}),
.VAR1({VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[7], VAR24[6], VAR24[5], VAR24[4], VAR24[3], VAR24[2], VAR24[1], VAR24[0]}),
.VAR17({VAR38[15], \VAR41/VAR32<34>VAR43 , \VAR41/VAR32<33>VAR43 ,
\VAR41/VAR32<32>VAR43 , \VAR41/VAR32<31>VAR43 , \VAR41/VAR32<30>VAR43 ,
\VAR41/VAR32<29>VAR43 , \VAR41/VAR32<28>VAR43 , \VAR41/VAR32<27>VAR43 ,
\VAR41/VAR32<26>VAR43 , \VAR41/VAR32<25>VAR43 , \VAR41/VAR32<24>VAR43 ,
\VAR41/VAR32<23>VAR43 , \VAR41/VAR32<22>VAR43 , \VAR41/VAR32<21>VAR43 ,
\VAR41/VAR32<20>VAR43 , \VAR41/VAR32<19>VAR43 , \VAR41/VAR32<18>VAR43 ,
\VAR41/VAR32<17>VAR43 , \VAR41/VAR32<16>VAR43 , \VAR41/VAR32<15>VAR43 ,
VAR38[14], VAR38[13], VAR38[12], VAR38[11], VAR38[10], VAR38[9], VAR38[8], VAR38[7], VAR38[6], VAR38[5], VAR38[4], VAR38[3], VAR38[2], VAR38[1], VAR38[0]})
);
endmodule
module MODULE2 ();
parameter VAR7 = 100000;
parameter VAR37 = 0;
wire VAR8;
wire VAR16;
wire VAR26;
wire VAR2;
tri1 VAR18;
tri (weak1, strong0) VAR27 = VAR18;
wire VAR25;
wire VAR15;
reg VAR21;
reg VAR3;
reg VAR9;
wire VAR4;
wire VAR28;
wire VAR14;
wire VAR36;
wire VAR6;
reg VAR5;
reg VAR33;
reg VAR22;
reg VAR34;
reg VAR44;
reg VAR30 = 0;
reg VAR23 = 0 ;
reg VAR13 = 0;
reg VAR35 = 0;
reg VAR19 = 1'VAR39;
reg VAR10 = 1'VAR39;
reg VAR12 = 1'VAR39;
reg VAR31 = 1'VAR39;
assign (weak1, weak0) VAR8 = VAR21;
assign (weak1, weak0) VAR16 = VAR3;
assign (weak1, weak0) VAR2 = VAR9;
|
gpl-2.0
|
olajep/oh
|
src/adi/hdl/library/common/ad_csc_1_add.v
| 5,044 |
module MODULE1 #(
parameter VAR3 = 16) (
input clk,
input [24:0] VAR6,
input [24:0] VAR26,
input [24:0] VAR16,
input [24:0] VAR22,
output reg [ 7:0] VAR30,
input [VAR21:0] VAR2,
output reg [VAR21:0] VAR9);
localparam VAR21 = VAR3 - 1;
reg [VAR21:0] VAR29 = 'd0;
reg [24:0] VAR31 = 'd0;
reg [24:0] VAR17 = 'd0;
reg [24:0] VAR15 = 'd0;
reg [24:0] VAR28 = 'd0;
reg [VAR21:0] VAR13 = 'd0;
reg [24:0] VAR14 = 'd0;
reg [24:0] VAR19 = 'd0;
reg [VAR21:0] VAR18 = 'd0;
reg [24:0] VAR25 = 'd0;
wire [24:0] VAR8;
wire [24:0] VAR24;
wire [24:0] VAR7;
wire [24:0] VAR20;
wire [24:0] VAR10;
wire [24:0] VAR27;
wire [24:0] VAR11;
wire [24:0] VAR4;
wire [24:0] VAR12;
wire [24:0] VAR5;
wire [24:0] VAR23;
wire [24:0] VAR1;
assign VAR8 = {1'b0, VAR6[23:0]};
assign VAR24 = ~VAR8 + 1'b1;
assign VAR7 = (VAR6[24] == 1'b1) ? VAR24 : VAR8;
assign VAR20 = {1'b0, VAR26[23:0]};
assign VAR10 = ~VAR20 + 1'b1;
assign VAR27 = (VAR26[24] == 1'b1) ? VAR10 : VAR20;
assign VAR11 = {1'b0, VAR16[23:0]};
assign VAR4 = ~VAR11 + 1'b1;
assign VAR12 = (VAR16[24] == 1'b1) ? VAR4 : VAR11;
assign VAR5 = {1'b0, VAR22[23:0]};
assign VAR23 = ~VAR5 + 1'b1;
assign VAR1 = (VAR22[24] == 1'b1) ? VAR23 : VAR5;
always @(posedge clk) begin
VAR29 <= VAR2;
VAR31 <= VAR7;
VAR17 <= VAR27;
VAR15 <= VAR12;
VAR28 <= VAR1;
end
always @(posedge clk) begin
VAR13 <= VAR29;
VAR14 <= VAR31 + VAR17;
VAR19 <= VAR15 + VAR28;
end
always @(posedge clk) begin
VAR18 <= VAR13;
VAR25 <= VAR14 + VAR19;
end
always @(posedge clk) begin
VAR9 <= VAR18;
if (VAR25[24] == 1'b1) begin
VAR30 <= 8'h00;
end else if (VAR25[23:20] == 'd0) begin
VAR30 <= VAR25[19:12];
end else begin
VAR30 <= 8'hff;
end
end
endmodule
|
mit
|
zaqwes8811/spec-emb
|
ip-cores/spi_host_ram_host/deserializer.v
| 3,532 |
module MODULE1 (
output reg VAR15,
input VAR11, VAR9, req, clk, VAR6);
parameter [1:0] VAR7 = 2'b00,
VAR13 = 2'b01,
VAR3 = 2'b10,
VAR4 = 2'b11;
reg [1:0] state;
reg [1:0] VAR14;
always @(posedge clk
) begin
state <= VAR14;
end
always @(state or VAR11 or VAR9 or req) begin
VAR14 = 2'VAR17;
VAR15 = 1'b0;
case (state)
VAR7:
if (req)
VAR14 = VAR13;
end
else
VAR14 = VAR7;
VAR13: begin
VAR15 = 1'b1;
if (!VAR9)
VAR14 = VAR13;
end
else begin
if ( VAR11 )
VAR14 = VAR3;
end
else
VAR14 = VAR4;
end
end
VAR3: begin
VAR15 = 1'b1;
if (!VAR11)
VAR14 = VAR4;
end
else begin
VAR14 = VAR3;
end
end
VAR4:
if ( req )
VAR14 = VAR13;
else
VAR14 = VAR7;
endcase
end
endmodule
module MODULE1(
clk,
VAR8,
VAR16,
ready,
VAR5,
VAR1 );
input clk;
input VAR8;
input VAR16;
output ready;
input [VAR2-1:0] VAR5;
output VAR1;
endmodule
module MODULE2;
reg clk, VAR8;
wire VAR12;
reg [7:0] VAR10;
|
mit
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_114.v
| 1,442 |
module MODULE1 (
VAR3,
VAR2
);
input [31:0] VAR3;
output [31:0]
VAR2;
wire [31:0]
VAR10,
VAR8,
VAR12,
VAR11,
VAR5,
VAR6,
VAR7;
assign VAR10 = VAR3;
assign VAR5 = VAR11 - VAR10;
assign VAR11 = VAR12 << 2;
assign VAR12 = VAR8 - VAR10;
assign VAR6 = VAR12 << 10;
assign VAR7 = VAR5 + VAR6;
assign VAR8 = VAR10 << 5;
assign VAR2 = VAR7;
endmodule
module MODULE2(
VAR3,
VAR2,
clk
);
input [31:0] VAR3;
output [31:0] VAR2;
reg [31:0] VAR2;
input clk;
reg [31:0] VAR1;
wire [30:0] VAR4;
always @(posedge clk) begin
VAR1 <= VAR3;
VAR2 <= VAR4;
end
MODULE1 MODULE1(
.VAR3(VAR1),
.VAR2(VAR4)
);
endmodule
|
mit
|
hoang26/processor_verilog
|
0_cpu.v
| 4,059 |
module MODULE1(
input clk,
input VAR50,
input VAR11,
input [31:0] VAR15,
input [31:0] VAR49,
output wire[31:0] VAR4,
output wire[31:0] VAR59,
output wire[31:0] VAR44,
output wire VAR76,
output wire VAR81
);
wire [31:0] VAR33;
wire [31:0] VAR10;
wire [31:0] VAR20;
wire [31:0] VAR23;
wire [31:0] VAR21;
wire [4:0] VAR13;
wire [31:0] VAR75;
wire [31:0] VAR19;
wire [31:0] VAR8;
wire [31:0] VAR18;
wire [31:0] VAR45;
wire [31:0] VAR67;
wire [31:0] VAR79;
wire [31:0] VAR69;
wire [31:0] VAR72;
wire [25:0] VAR65;
wire [27:0] VAR54;
wire [15:0] VAR31;
wire [5:0] VAR12;
wire [5:0] VAR35;
wire [4:0]VAR70;
wire [4:0]VAR36;
wire [4:0] VAR43;
wire [4:0] VAR78;
wire [4:0] VAR62;
wire [3:0] VAR77;
wire [1:0] VAR61;
wire VAR53, VAR73, VAR7, VAR57, VAR27, VAR48, VAR37, VAR22, VAR63, VAR52;
assign VAR18 = 32'd4; assign VAR72 = {VAR45[31:28], VAR54[27:0]}; assign VAR35 = VAR15[5:0]; assign VAR37 = VAR7 & VAR22; assign VAR43 = VAR15[25-21];
assign VAR78 = VAR15[20-16];
assign VAR59 = VAR10;
assign VAR4 = VAR23;
assign VAR44 = VAR79;
assign VAR62 = VAR13;
assign VAR12 = VAR15[31:26];
assign VAR31 = VAR15[15:0];
assign VAR65 = VAR15[25:0];
assign VAR70 = VAR15[20:16];
assign VAR36 = VAR15[15:11];
VAR56 VAR80(
.in(VAR33), .clk,
.rst(VAR50),
.en(VAR11),
.out(VAR10) );
VAR58 VAR64(
.clk,
.VAR12(VAR12), .VAR53(VAR53),
.VAR73(VAR73),
.VAR7(VAR7),
.VAR63(VAR76),
.VAR57(VAR57),
.VAR52(VAR81),
.VAR27(VAR27),
.VAR48(VAR48),
.VAR61(VAR61) );
VAR6 VAR34(
.clk,
.VAR71(VAR10), .VAR46(VAR18), .out(VAR45) );
VAR6 VAR2(
.clk,
.VAR71(VAR45), .VAR46(VAR69), .out(VAR67) );
VAR3 VAR29(
.clk,
.VAR14(VAR48),
.VAR43(VAR43), .VAR78(VAR78), .VAR62(VAR62), .VAR28(VAR19), .VAR20(VAR20), .VAR23(VAR23) );
VAR5 VAR41(
.clk,
.in(VAR31), .out(VAR21) );
VAR40 VAR42(
.clk,
.in(VAR65), .out(VAR54) );
VAR47 VAR66(
.clk,
.in(VAR21), .out(VAR69) );
VAR1 VAR17(
.clk,
.VAR71(VAR70), .VAR46(VAR36), .select(VAR53),
.out(VAR13) );
VAR51 VAR9(
.clk,
.VAR71(VAR23), .VAR46(VAR21), .select(VAR27),
.out(VAR75) );
VAR51 VAR39(
.clk,
.VAR71(VAR79), .VAR46(VAR49), .select(VAR57),
.out(VAR19) );
VAR51 VAR74(
.clk,
.VAR71(VAR45), .VAR46(VAR67), .select(VAR37),
.out(VAR8) );
VAR51 VAR16(
.clk,
.VAR71(VAR8), .VAR46(VAR72), .select(VAR73),
.out(VAR33) );
VAR24 VAR77(
.clk,
.VAR61, .VAR38(VAR35), .VAR26(VAR77) );
VAR25 VAR32(
.clk,
.VAR68(VAR77), .VAR30(VAR20), .VAR60(VAR75), .VAR55(VAR79), .VAR22
);
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.blackbox.v
| 1,377 |
module MODULE1 (
VAR3 ,
VAR10,
VAR2,
VAR7 ,
VAR5,
VAR4
);
output VAR3 ;
output VAR10;
input VAR2;
input VAR7 ;
input VAR5;
input VAR4;
supply1 VAR8;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/and2/sky130_fd_sc_hdll__and2.pp.blackbox.v
| 1,268 |
module MODULE1 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR6,
VAR4,
VAR5 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR2 ;
endmodule
|
apache-2.0
|
marmolejo/zet
|
cores/ps2/rtl/ps2.v
| 19,706 |
module MODULE1 (
input VAR37, input VAR46, input [15:0] VAR12, output [15:0] VAR53, input VAR54, input VAR25, input [ 2:1] VAR99, input [ 1:0] VAR4, input VAR49, output VAR93, output VAR8, output VAR26,
input VAR96, inout VAR42, inout VAR91, inout VAR74 );
wire [7:0] VAR85;
wire [2:0] VAR28;
wire VAR59;
wire VAR100;
wire VAR68;
wire VAR13;
wire VAR3;
wire VAR71;
wire VAR86;
wire VAR94;
wire VAR64;
wire VAR10;
wire VAR72;
wire [7:0] VAR75;
reg [7:0] VAR70; wire VAR88;
wire VAR61;
wire VAR63;
wire VAR38;
wire VAR17;
wire VAR90;
wire VAR48;
wire VAR62;
wire VAR98;
wire VAR24;
wire VAR27;
wire VAR5;
wire [7:0] VAR36;
wire [7:0] VAR95;
wire [7:0] VAR76;
wire [7:0] VAR84;
wire [7:0] VAR9;
wire [7:0] VAR78;
wire [7:0] VAR97;
wire [7:0] VAR16;
wire VAR32;
wire VAR33;
reg VAR60; reg VAR79; reg VAR55; reg VAR34; reg VAR7;
reg VAR40; wire VAR77;
wire [7:0] VAR67; wire [7:0] VAR83;
wire VAR80; wire VAR50; wire VAR82; wire VAR15; wire VAR30;
wire VAR58;
wire [7:0] VAR101;
wire VAR20;
wire VAR89;
wire VAR29;
always @(posedge VAR37) begin if(VAR46) begin
VAR70 <= VAR92; VAR60 <= 1'b0; VAR79 <= 1'b0; VAR55 <= 1'b0; VAR34 <= 1'b0; VAR7 <= 1'b0; end
else
if(VAR62) begin
VAR60 <= 1'b1; end
else
if(VAR98) begin
VAR79 <= 1'b1; VAR55 <= 1'b0; end
else
if(VAR24) begin
VAR55 <= 1'b1; end
else
if(VAR27) begin
VAR34 <= 1'b1; end
else
if(VAR5) begin
VAR7 <= 1'b1; end
else
if(VAR17) begin
if(VAR60) VAR60 <= 1'b0; if(VAR34) VAR34 <= 1'b0; if(VAR7) VAR7 <= 1'b0; end
else
if(VAR38) begin
if(VAR79) begin
VAR70 <= VAR85; VAR79 <= 1'b0; end
end
if(VAR55 && VAR50) VAR55 <= 1'b0; end
always @(posedge VAR37 or posedge VAR46) begin if(VAR46) VAR40 <= 1'b0; else begin
if(VAR80) VAR40 <= 1'b1; if(VAR77) VAR40 <= 1'b0; end
end
VAR44 VAR66 (
.clk (VAR37),
.reset (VAR46),
.VAR22 (VAR91),
.VAR6 (VAR74),
.VAR57 (VAR83), .write (VAR30), .VAR81 (VAR50),
.VAR1 (VAR67), .irq (VAR80), .VAR31 (VAR40),
.VAR52 (VAR82), .VAR18 (VAR15) );
VAR51 #(
.VAR47 (750),
.VAR69 (10),
.VAR56 (60),
.VAR41 (6)
) VAR35 (
.clk (VAR37),
.reset (VAR46),
.VAR14 (VAR89), .VAR65 (VAR20),
.VAR73 (VAR101), .VAR19 (VAR58), .VAR29 (VAR29),
.VAR22 (VAR96), .VAR11 (VAR42)
);
assign VAR85 = VAR4[0] ? VAR12[7:0] : VAR12[15:8]; assign VAR53 = VAR4[0] ? {8'h00, VAR36} : {VAR36, 8'h00}; assign VAR28 = {VAR99, VAR4[1]}; assign VAR59 = VAR25 & VAR54; assign VAR93 = VAR59;
assign VAR100 = VAR59 & VAR49; assign VAR68 = VAR59 & ~VAR49; assign VAR26 = VAR40 & VAR61; assign VAR8 = VAR58 & VAR88;
assign VAR13 = VAR33; assign VAR3 = VAR20; assign VAR71 = 1'b1; assign VAR86 = 1'b0; assign VAR94 = 1'b1; assign VAR64 = VAR50; assign VAR10 = VAR82; assign VAR72 = VAR15; assign VAR75 = {VAR72, VAR10, VAR64, VAR94, VAR86, VAR71, VAR3, VAR13}; assign VAR88 = VAR70[0]; assign VAR61 = VAR70[1];
assign VAR63 = (VAR28 == VAR45);
assign VAR38 = VAR63 && VAR100;
assign VAR17 = VAR63 && VAR68;
assign VAR90 = (VAR28 == VAR23);
assign VAR48 = VAR90 && VAR100;
assign VAR62 = VAR48 && (VAR85 == VAR87); assign VAR98 = VAR48 && (VAR85 == VAR43); assign VAR24 = VAR48 && (VAR85 == VAR21); assign VAR27 = VAR48 && (VAR85 == VAR39); assign VAR5 = VAR48 && (VAR85 == VAR2);
assign VAR36 = VAR95; assign VAR95 = VAR63 ? VAR76 : VAR75; assign VAR76 = VAR60 ? VAR70 : VAR84; assign VAR84 = VAR34 ? VAR97 : VAR9; assign VAR9 = VAR7 ? VAR16 : VAR78; assign VAR78 = VAR40 ? VAR67 : VAR101; assign VAR97 = 8'h55; assign VAR16 = 8'h00; assign VAR32 = VAR55 && VAR38; assign VAR33 = VAR40 || VAR58 || VAR60 || VAR34 || VAR7;
assign VAR77 = VAR17 && !(VAR60 || VAR34 || VAR7);
assign VAR83 = VAR85; assign VAR30 = VAR32;
endmodule
|
gpl-3.0
|
f3zz3h/Embedded-Co-Design
|
ts7300_top_restored/ethernet/eth_fifo.v
| 6,551 |
module MODULE1 (VAR11, VAR3, clk, reset, write, read, VAR26, VAR22, VAR16, VAR23, VAR14, VAR8);
parameter VAR18 = 32;
parameter VAR5 = 8;
parameter VAR15 = 4;
parameter VAR2 = 1;
input clk;
input reset;
input write;
input read;
input VAR26;
input [VAR18-1:0] VAR11;
output [VAR18-1:0] VAR3;
output VAR22;
output VAR16;
output VAR23;
output VAR14;
output [VAR15-1:0] VAR8;
reg [VAR18-1:0] VAR25 [0:VAR5-1];
reg [VAR18-1:0] VAR3;
reg [VAR15-1:0] VAR8;
reg [VAR15-2:0] VAR12;
reg [VAR15-2:0] VAR21;
always @ (posedge clk or posedge reset)
begin
if(reset)
VAR8 <=#VAR2 0;
end
else
if(VAR26)
VAR8 <=#VAR2 { {(VAR15-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
VAR8 <=#VAR2 VAR8 - 1'b1;
else
VAR8 <=#VAR2 VAR8 + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
VAR12 <=#VAR2 0;
end
else
if(VAR26)
VAR12 <=#VAR2 { {(VAR15-2){1'b0}}, read};
else
if(read & ~VAR14)
VAR12 <=#VAR2 VAR12 + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
VAR21 <=#VAR2 0;
end
else
if(VAR26)
VAR21 <=#VAR2 { {(VAR15-2){1'b0}}, write};
else
if(write & ~VAR16)
VAR21 <=#VAR2 VAR21 + 1'b1;
end
assign VAR14 = ~(|VAR8);
assign VAR23 = VAR8 == 1;
assign VAR16 = VAR8 == VAR5;
assign VAR22 = &VAR8[VAR15-2:0];
VAR10 VAR25
( .VAR3(VAR3),
.VAR1(write & ~VAR16),
.VAR11(VAR11),
.VAR4( VAR26 ? {VAR15-1{1'b0}} : VAR12),
.VAR6(VAR26 ? {VAR15-1{1'b0}} : VAR21),
.VAR24(clk)
);
VAR19 VAR27
(
.VAR28 (VAR11),
.VAR7 (write & ~VAR16),
.VAR20 (VAR26 ? {VAR15-1{1'b0}} : VAR21),
.VAR13 (VAR26 ? {VAR15-1{1'b0}} : VAR12 ),
.VAR9 (clk),
.VAR17 (VAR3)
); else always @ (posedge clk)
begin
if(write & VAR26)
VAR25[0] <=#VAR2 VAR11;
end
else
if(write & ~VAR16)
VAR25[VAR21] <=#VAR2 VAR11;
end
always @ (posedge clk)
begin
if(VAR26)
VAR3 <=#VAR2 VAR25[0];
end
else
VAR3 <=#VAR2 VAR25[VAR12];
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_s.blackbox.v
| 1,519 |
module MODULE1 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR5,
VAR7 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
endmodule
|
apache-2.0
|
peteasa/parallella-fpga
|
AdiHDLLib/library/common/ad_axis_dma_rx.v
| 10,163 |
module MODULE1 (
VAR17,
VAR65,
VAR43,
VAR57,
VAR36,
VAR22,
VAR45,
VAR26,
VAR32,
VAR18,
VAR12,
VAR72,
VAR25,
VAR20,
VAR21,
VAR58,
VAR44);
parameter VAR14 = 64;
localparam VAR60 = VAR14 - 1;
localparam VAR1 = 6'd3;
localparam VAR75 = 6'd60;
localparam VAR50 = VAR14/8;
input VAR17;
input VAR65;
output VAR43;
output VAR57;
output [VAR60:0] VAR36;
input VAR22;
output VAR45;
output VAR26;
output VAR32;
output [31:0] VAR18;
input VAR12;
input VAR72;
input VAR25;
input [VAR60:0] VAR20;
input VAR21;
input VAR58;
input [31:0] VAR44;
reg VAR29 = 'd0;
reg VAR73 = 'd0;
reg [VAR60:0] VAR42 = 'd0;
reg VAR38 = 'd0;
reg [31:0] VAR47 = 'd0;
reg VAR55 = 'd0;
reg [ 5:0] VAR2 = 'd0;
reg VAR13 = 'd0;
reg VAR64 = 'd0;
reg VAR61 = 'd0;
reg [ 5:0] VAR51 = 'd0;
reg [ 5:0] VAR81 = 'd0;
reg [ 5:0] VAR8 = 'd0;
reg [ 5:0] VAR76 = 'd0;
reg [ 5:0] VAR54 = 'd0;
reg VAR66 = 'd0;
reg VAR11 = 'd0;
reg VAR45 = 'd0;
reg VAR26 = 'd0;
reg VAR24 = 'd0;
reg VAR23 = 'd0;
reg [ 5:0] VAR68 = 'd0;
reg [ 5:0] VAR4 = 'd0;
reg [ 3:0] VAR19 = 'd0;
reg [VAR60:0] VAR52 = 'd0;
reg VAR56 = 'd0;
reg [ 5:0] VAR63 = 'd0;
reg VAR53 = 'd0;
reg VAR31 = 'd0;
reg VAR28 = 'd0;
wire VAR46;
wire VAR41;
wire VAR79;
wire VAR59;
wire VAR7;
wire [ 6:0] VAR6;
wire VAR77;
wire VAR16;
wire [VAR60:0] VAR39;
function [5:0] VAR27;
input [5:0] VAR62;
reg [5:0] VAR10;
begin
VAR10[5] = VAR62[5];
VAR10[4] = VAR62[5] ^ VAR62[4];
VAR10[3] = VAR62[4] ^ VAR62[3];
VAR10[2] = VAR62[3] ^ VAR62[2];
VAR10[1] = VAR62[2] ^ VAR62[1];
VAR10[0] = VAR62[1] ^ VAR62[0];
VAR27 = VAR10;
end
endfunction
function [5:0] VAR9;
input [5:0] VAR10;
reg [5:0] VAR62;
begin
VAR62[5] = VAR10[5];
VAR62[4] = VAR62[5] ^ VAR10[4];
VAR62[3] = VAR62[4] ^ VAR10[3];
VAR62[2] = VAR62[3] ^ VAR10[2];
VAR62[1] = VAR62[2] ^ VAR10[1];
VAR62[0] = VAR62[1] ^ VAR10[0];
VAR9 = VAR62;
end
endfunction
assign VAR18 = VAR50;
assign VAR32 = VAR38;
always @(posedge VAR17) begin
VAR29 <= VAR46;
VAR73 <= VAR41;
VAR42 <= VAR39;
end
assign VAR46 = VAR38 & VAR55;
assign VAR41 = (VAR47 == VAR44) ? VAR46 : 1'b0;
always @(posedge VAR17) begin
if ((VAR58 == 1'b0) && (VAR41 == 1'b1)) begin
VAR38 <= 1'b0;
end else if (VAR21 == 1'b1) begin
VAR38 <= 1'b1;
end
if ((VAR38 == 1'b0) || (VAR41 == 1'b1)) begin
VAR47 <= VAR18;
end else if (VAR55 == 1'b1) begin
VAR47 <= VAR47 + VAR18;
end
end
assign VAR79 = (~VAR38) | VAR22;
assign VAR59 = (VAR51 == VAR2) ? 1'b0 : VAR79;
always @(posedge VAR17) begin
VAR55 <= VAR59;
if ((VAR24 == 1'b1) || (VAR65 == 1'b1)) begin
VAR2 <= 6'd0;
end else if (VAR59 == 1'b1) begin
VAR2 <= VAR2 + 1'b1;
end
end
assign VAR7 = VAR61 ^ VAR64;
always @(posedge VAR17) begin
if (VAR65 == 1'b1) begin
VAR13 <= 'd0;
VAR64 <= 'd0;
VAR61 <= 'd0;
end else begin
VAR13 <= VAR56;
VAR64 <= VAR13;
VAR61 <= VAR64;
end
if (VAR24 == 1'b1) begin
VAR51 <= 6'd0;
end else if (VAR7 == 1'b1) begin
VAR51 <= VAR63;
end
end
assign VAR6 = {1'b1, VAR76} - VAR2;
assign VAR77 = (VAR54 < VAR1) ? VAR66 : 1'b0;
assign VAR16 = (VAR54 > VAR75) ? VAR11 : 1'b0;
always @(posedge VAR17) begin
if (VAR65 == 1'b1) begin
VAR81 <= 'd0;
VAR8 <= 'd0;
end else begin
VAR81 <= VAR4;
VAR8 <= VAR81;
end
VAR76 <= VAR9(VAR8);
VAR54 <= VAR6[5:0];
if (VAR54 > VAR75) begin
VAR66 <= 1'b1;
end else begin
VAR66 <= 1'b0;
end
if (VAR54 < VAR1) begin
VAR11 <= 1'b1;
end else begin
VAR11 <= 1'b0;
end
VAR45 <= VAR77;
VAR26 <= VAR16;
VAR24 <= VAR45 | VAR26;
end
always @(posedge VAR12) begin
VAR23 <= VAR25;
if ((VAR28 == 1'b1) || (VAR72 == 1'b1)) begin
VAR68 <= 6'd0;
end else if (VAR23 == 1'b1) begin
VAR68 <= VAR68 + 1'b1;
end
VAR4 <= VAR27(VAR68);
VAR52 <= VAR20;
VAR19 <= VAR19 + 1'b1;
if (VAR19 == 4'hf) begin
VAR56 <= ~VAR56;
VAR63 <= VAR68;
end
if (VAR72 == 1'b1) begin
VAR53 <= 'd0;
VAR31 <= 'd0;
end else begin
VAR53 <= VAR24;
VAR31 <= VAR53;
end
VAR28 <= VAR31;
end
VAR48 #(.VAR14(VAR14)) VAR30 (
.clk (VAR17),
.rst (VAR65),
.valid (VAR29),
.VAR80 (VAR73),
.VAR67 (VAR42),
.VAR70 (VAR43),
.VAR37 (VAR57),
.VAR15 (VAR36),
.VAR69 (VAR22));
VAR49 #(.VAR14(VAR14), .VAR74(6)) VAR40 (
.VAR3 (VAR12),
.VAR33 (VAR23),
.VAR35 (VAR68),
.VAR71 (VAR52),
.VAR5 (VAR17),
.VAR34 (VAR2),
.VAR78 (VAR39));
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor4/sky130_fd_sc_hdll__nor4.functional.pp.v
| 1,888 |
module MODULE1 (
VAR5 ,
VAR13 ,
VAR12 ,
VAR9 ,
VAR15 ,
VAR3,
VAR2,
VAR1 ,
VAR10
);
output VAR5 ;
input VAR13 ;
input VAR12 ;
input VAR9 ;
input VAR15 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR10 ;
wire VAR14 ;
wire VAR7;
nor VAR11 (VAR14 , VAR13, VAR12, VAR9, VAR15 );
VAR6 VAR4 (VAR7, VAR14, VAR3, VAR2);
buf VAR8 (VAR5 , VAR7 );
endmodule
|
apache-2.0
|
trivoldus28/pulsarch-verilog
|
verif/env/cmp/tlu_mon.v
| 80,576 |
module MODULE1(
clk,
VAR230,
VAR107,
VAR167,
VAR223,
VAR249,
VAR22,
VAR208,
VAR88,
VAR234,
VAR172,
VAR64,
VAR53,
VAR251,
VAR205,
VAR33,
VAR233,
VAR246,
VAR242,
VAR109,
VAR94,
VAR213,
VAR115,
VAR157,
VAR1,
VAR97,
VAR73,
VAR8,
VAR259,
VAR181,
VAR39,
VAR211,
VAR269,
VAR186,
VAR231,
VAR55,
VAR218,
VAR158,
VAR150,
VAR128,
VAR106,
VAR127,
VAR96,
VAR225,
VAR177,
VAR256,
VAR270,
VAR116,
VAR144,
VAR130,
VAR6,
VAR209,
VAR58,
VAR196,
VAR212,
VAR83,
VAR11,
VAR122,
VAR258,
VAR102,
VAR72,
VAR71,
VAR98,
VAR262,
VAR23,
VAR240,
VAR264,
VAR30,
VAR148,
VAR35,
VAR65,
VAR261,
VAR255,
VAR44,
VAR239,
VAR25,
VAR147,
VAR197,
VAR86,
VAR217,
VAR248,
VAR146,
VAR79,
VAR235,
VAR174,
VAR36,
VAR15,
VAR226,
VAR203,
VAR41,
VAR214,
VAR57,
VAR252,
VAR219,
VAR142,
VAR70,
VAR63,
VAR204,
VAR13,
VAR10,
VAR48,
VAR207,
VAR129,
VAR123,
VAR100,
VAR18,
VAR60,
VAR159,
VAR26,
VAR51,
VAR90,
VAR152,
VAR61,
VAR140
);
input clk;
input VAR230;
input VAR107;
input VAR167;
input VAR223;
input VAR249;
input VAR22;
input [3:0] VAR208;
input [3:0] VAR88;
input [3:0] VAR234;
input [3:0] VAR172;
input [3:0] VAR64;
input [3:0] VAR53;
input [3:0] VAR251;
input [3:0] VAR205;
input VAR33;
input VAR233;
input VAR246;
input VAR242;
input [7:0] VAR109;
input [47:0] VAR94;
input VAR213;
input VAR115;
input VAR157;
input VAR1;
input [1:0] VAR97;
input [1:0] VAR73;
input [1:0] VAR8;
input [1:0] VAR259;
input [1:0] VAR181;
input [1:0] VAR39;
input [1:0] VAR211;
input [1:0] VAR269;
input [1:0] VAR186;
input VAR231;
input VAR55;
input VAR218;
input [3:0] VAR150;
input [3:0] VAR128;
input [3:0] VAR106;
input VAR158;
input [6:0] VAR127;
input VAR96;
input VAR225;
input VAR177;
input [63:0] VAR256;
input [3:0] VAR270;
input [3:0] VAR116;
input [3:0] VAR144;
input VAR130;
input [1:0] VAR6;
input VAR209;
input [3:0] VAR58;
input [3:0] VAR196;
input [3:0] VAR212;
input [3:0] VAR83;
input [3:0] VAR11;
input VAR122;
input VAR258;
input VAR102;
input VAR72;
input VAR214;
input [63:0] VAR71;
input [3:0] VAR98;
input [3:0] VAR262;
input [3:0] VAR23;
input VAR240;
input [48:0] VAR264;
input [8:0] VAR30;
input [1:0] VAR148;
input VAR35;
input [7:0] VAR65;
input [7:0] VAR261;
input [7:0] VAR255;
input [7:0] VAR44;
input [32:0] VAR57;
input [32:0] VAR252;
input [32:0] VAR219;
input [32:0] VAR142;
input [32:0] VAR70;
input [32:0] VAR63;
input [32:0] VAR204;
input [32:0] VAR13;
input [3:0] VAR239;
input [3:0] VAR25;
input [3:0] VAR147;
input [3:0] VAR197;
input [3:0] VAR86;
input [3:0] VAR217;
input [3:0] VAR248;
input [3:0] VAR146;
input [3:0] VAR79;
input [3:0] VAR235;
input [3:0] VAR174;
input [3:0] VAR36;
input [2:0] VAR15;
input [2:0] VAR226;
input [2:0] VAR203;
input [2:0] VAR41;
input [3:0] VAR10;
input VAR48;
input VAR207;
input VAR129;
input VAR123;
input VAR100;
input [2:0] VAR18;
input VAR60;
input VAR159;
input [58:0] VAR26;
input [42:0] VAR51;
input VAR90;
input VAR152;
input VAR61;
input VAR140;
wire [3:0] VAR92;
wire [2:0] VAR85;
wire [3:0] VAR151;
wire [3:0] VAR271;
wire [3:0] VAR187;
wire [3:0] VAR17;
wire [3:0] VAR95;
wire VAR227;
wire VAR80;
wire VAR250;
wire VAR16;
wire [3:0] VAR28;
wire [3:0] VAR29;
wire [3:0] VAR24;
wire [1:0] VAR82;
wire [3:0] VAR32;
wire [3:0] VAR154;
wire [3:0] VAR3;
wire [32:0] VAR136;
wire [32:0] VAR118;
wire [32:0] VAR137;
wire [32:0] VAR236;
wire [7:0] VAR184;
wire [7:0] VAR14;
wire [7:0] VAR267;
wire [7:0] VAR139;
wire [7:0] VAR46;
wire [7:0] VAR131;
wire [7:0] VAR134;
wire [7:0] VAR145;
wire [3:0] VAR19;
wire [3:0] VAR183;
wire [3:0] VAR244;
wire [3:0] VAR194;
wire [63:0] VAR124;
wire [63:0] VAR191;
wire [63:0] VAR149;
wire [63:0] VAR160;
wire VAR216;
wire [13:0] VAR188; wire [8:0] VAR81 = 9'h4f;
wire VAR238;
wire VAR113;
wire [3:0] VAR45;
wire [3:0] VAR62;
wire [7:0] VAR75;
wire [7:0] VAR185;
wire [7:0] VAR220;
wire [7:0] VAR200;
wire VAR190;
wire VAR133;
wire VAR245;
wire VAR20;
wire VAR2;
wire VAR153;
reg VAR112;
reg VAR87;
reg VAR189;
reg VAR40;
reg [58:0] VAR178;
reg [42:0] VAR260;
reg VAR52;
reg VAR108;
wire VAR180;
reg enable;
reg [63:0] VAR9;
reg [63:0] VAR193;
reg [63:0] VAR54;
reg [63:0] VAR31;
reg [32:0] VAR254;
reg [32:0] VAR228;
reg [32:0] VAR91;
reg [32:0] VAR241;
reg [32:0] VAR110;
reg [32:0] VAR221;
reg [32:0] VAR263;
reg [32:0] VAR69;
reg [32:0] VAR104;
reg [32:0] VAR237;
reg [32:0] VAR27;
reg [32:0] VAR49;
reg [1:0] VAR166;
reg [1:0] VAR42;
reg [1:0] VAR4;
reg [1:0] VAR66;
reg [1:0] VAR43;
reg [1:0] VAR265;
reg VAR34;
reg VAR120;
reg [3:0] VAR138, VAR143, VAR202, VAR121;
reg VAR165;
reg [6:0] VAR229;
reg VAR38;
reg VAR155;
reg VAR161;
reg VAR182;
reg VAR179;
reg VAR93;
reg VAR50;
reg VAR232;
reg VAR105;
reg VAR195;
reg [1:0] VAR126;
reg [3:0] VAR175;
reg [3:0] VAR7;
reg [3:0] VAR77;
reg [3:0] VAR199;
reg [3:0] VAR162;
reg [3:0] VAR169;
reg [8:0] VAR21;
reg VAR201;
reg VAR266;
reg VAR67;
reg [13:0] VAR117;
reg [13:0] VAR125; reg [13:0] VAR247;
reg VAR89;
reg [3:0] VAR268;
reg VAR176;
reg VAR192;
reg VAR103;
reg VAR170;
reg VAR74;
reg VAR173;
reg VAR132;
reg VAR5;
reg VAR111;
reg VAR101;
always @(posedge clk)
if ( ~VAR230 ) VAR132 <= 1'b0;
else if ( VAR213 ) VAR132 <= 1'b1;
else VAR132 <= VAR132;
always @(posedge clk)
if ( ~VAR230 ) VAR5 <= 1'b0;
else if ( VAR115 ) VAR5 <= 1'b1;
else VAR5 <= VAR5;
always @(posedge clk)
if ( ~VAR230 ) VAR111 <= 1'b0;
else if ( VAR157 ) VAR111 <= 1'b1;
else VAR111 <= VAR111;
always @(posedge clk)
if ( ~VAR230 ) VAR101 <= 1'b0;
else if ( VAR1 ) VAR101 <= 1'b1;
else VAR101 <= VAR101;
always @(posedge clk) begin
if ((VAR132 === 1'b1) && (VAR97 !== VAR181)) begin
end
if ((VAR5 === 1'b1) && (VAR73 !== VAR39)) begin
end
if ((VAR111 === 1'b1) && (VAR8 !== VAR211)) begin
end
if ((VAR101 === 1'b1) && (VAR259 !== VAR269)) begin
end
end
always @(posedge clk) begin
VAR74 <= VAR167;
VAR173 <= VAR74;
end
assign VAR2 = (VAR4 === VAR66) ? 1'b1 : 1'b0;
assign VAR153 = (VAR66 === VAR43) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (VAR173 & VAR223 & VAR153 & ~VAR249) begin
end
if (VAR74 & VAR22 & VAR2) begin
end
if (VAR74 & VAR208[0] & VAR2) begin
end
if (VAR74 & VAR88[0] & VAR2) begin
end
if (VAR74 & VAR234[0] & VAR2) begin
end
if (VAR74 & VAR172[0] & VAR2) begin
end
if (VAR74 & VAR64[0] & VAR2) begin
end
if (VAR74 & VAR53[0] & VAR2) begin
end
if (VAR74 & VAR251[0] & VAR2) begin
end
if (VAR74 & VAR205[0] & VAR2) begin
end
if (VAR74 & VAR208[1] & VAR2) begin
end
if (VAR74 & VAR88[1] & VAR2) begin
end
if (VAR74 & VAR234[1] & VAR2) begin
end
if (VAR74 & VAR172[1] & VAR2) begin
end
if (VAR74 & VAR64[1] & VAR2) begin
end
if (VAR74 & VAR53[1] & VAR2) begin
end
if (VAR74 & VAR251[1] & VAR2) begin
end
if (VAR74 & VAR205[1] & VAR2) begin
end
if (VAR74 & VAR208[2] & VAR2) begin
end
if (VAR74 & VAR88[2] & VAR2) begin
end
if (VAR74 & VAR234[2] & VAR2) begin
end
if (VAR74 & VAR172[2] & VAR2) begin
end
if (VAR74 & VAR64[2] & VAR2) begin
end
if (VAR74 & VAR53[2] & VAR2) begin
end
if (VAR74 & VAR251[2] & VAR2) begin
end
if (VAR74 & VAR205[2] & VAR2) begin
end
if (VAR74 & VAR208[3] & VAR2) begin
end
if (VAR74 & VAR88[3] & VAR2) begin
end
if (VAR74 & VAR234[3] & VAR2) begin
end
if (VAR74 & VAR172[3] & VAR2) begin
end
if (VAR74 & VAR64[3] & VAR2) begin
end
if (VAR74 & VAR53[3] & VAR2) begin
end
if (VAR74 & VAR251[3] & VAR2) begin
end
if (VAR74 & VAR205[3] & VAR2) begin
end
end
wire VAR257 = (~VAR94[5] | (VAR94[5] & VAR94[4])) & ~(|VAR94[2:0]);
wire VAR135 = (&VAR94[9:6]) & ~(|VAR94[2:0]);
wire VAR224 = VAR33 & VAR246 & (VAR109[7:0]==8'h20) & VAR257;
wire VAR210 = VAR233 & VAR246 & (VAR109[7:0]==8'h20) & VAR257;
wire VAR47 = VAR33 & VAR246 & (VAR109[7:0]==8'h25) & VAR135 & ~VAR94[3];
wire VAR141 = VAR233 & VAR246 & (VAR109[7:0]==8'h25) & VAR135 & ~VAR94[3];
wire VAR168 = VAR33 & VAR246 & (VAR109[7:0]==8'h25) & VAR135 & VAR94[3];
wire VAR253 = VAR58[VAR166];
wire VAR198 = (VAR224 | VAR210 | VAR47 | VAR141 | VAR168) & VAR253;
reg VAR59;
reg VAR164;
reg VAR84;
always @(posedge clk) begin
VAR59 <= VAR198;
VAR164 <= VAR59;
VAR84 <= VAR242;
end
always @(posedge clk) begin
if (VAR34 & VAR164 & VAR74 & ~VAR84 & VAR2) begin
end
end
assign VAR75 = { VAR9[VAR37], VAR9[VAR222],
VAR9[VAR215:VAR76],
VAR9[VAR12:VAR206]};
assign VAR185 = { VAR193[VAR37], VAR193[VAR222],
VAR193[VAR215:VAR76],
VAR193[VAR12:VAR206]};
assign VAR220 = { VAR54[VAR37], VAR54[VAR222],
VAR54[VAR215:VAR76],
VAR54[VAR12:VAR206]};
assign VAR200 = { VAR31[VAR37], VAR31[VAR222],
VAR31[VAR215:VAR76],
VAR31[VAR12:VAR206]};
assign VAR95[0] = ~(|VAR186[1:0]);
assign VAR95[1] = ~VAR186[1] & VAR186[0];
assign VAR95[2] = VAR186[1] & ~VAR186[0];
assign VAR95[3] = (&VAR186[1:0]);
assign VAR45[0] = ~VAR4[1] & ~VAR4[0];
assign VAR45[1] = ~VAR4[1] & VAR4[0];
assign VAR45[2] = VAR4[1] & ~VAR4[0];
assign VAR45[3] = VAR4[1] & VAR4[0];
assign VAR62[0] = ~VAR66[1] & ~VAR66[0];
assign VAR62[1] = ~VAR66[1] & VAR66[0];
assign VAR62[2] = VAR66[1] & ~VAR66[0];
assign VAR62[3] = VAR66[1] & VAR66[0];
assign VAR227 = (VAR127[6:0] == 7'h10);
assign VAR80 =
(VAR229[6:0] == 7'h10) & (VAR38 | VAR225);
assign VAR16 =
(VAR229[6:0] == 7'h11) & (VAR38 | VAR225);
assign VAR250 =
(VAR229[6:0] == 7'h31) & (VAR38 | VAR225);
assign VAR24[3:0] = {4{VAR182}} & { VAR31[VAR206],
VAR54[VAR206],
VAR193[VAR206],
VAR9[VAR206]};
assign VAR28[3:0] = VAR11[3:0] & {4{VAR179}};
assign VAR29[3:0] = VAR11[3:0] & ({4{VAR50}} | {4{VAR93}});
assign VAR124[63:0] = (VAR138[0]) ? VAR9[VAR156:VAR206] :
(VAR138[1]) ? VAR193[VAR156:VAR206] :
(VAR138[2]) ? VAR54[VAR156:VAR206] :
(VAR138[3]) ? VAR31[VAR156:VAR206] :
{64{1'b0}};
assign VAR191[63:0] = (VAR138[0]) ? {VAR110[31:0], VAR254[31:0]} :
(VAR138[1]) ? {VAR221[31:0], VAR228[31:0]} :
(VAR138[2]) ? {VAR263[31:0], VAR91[31:0]} :
(VAR138[3]) ? {VAR69[31:0], VAR241[31:0]} :
{64{1'b0}};
assign VAR149[63:0] = (VAR165) ? VAR124[63:0] : VAR191[63:0];
assign VAR160[63:0] = (VAR121[0]) ? VAR9[VAR156:VAR206] :
(VAR121[1]) ? VAR193[VAR156:VAR206] :
(VAR121[2]) ? VAR54[VAR156:VAR206] :
(VAR121[3]) ? VAR31[VAR156:VAR206] :
{64{1'b0}};
assign VAR151[3:0] = {4{VAR105}} & VAR128[3:0];
assign VAR271[3:0] = {4{VAR195}} & VAR128[3:0];
assign VAR187[3:0] = {4{VAR130}} & VAR128[3:0];
assign VAR17[0] = VAR209 & (~VAR6[1] & ~VAR6[0]);
assign VAR17[1] = VAR209 & (~VAR6[1] & VAR6[0]);
assign VAR17[2] = VAR209 & ( VAR6[1] & ~VAR6[0]);
assign VAR17[3] = VAR209 & ( VAR6[1] & VAR6[0]);
assign VAR82[1:0] = VAR126[1:0] + 2'b01;
assign VAR32[0] = ~|(VAR82[1:0]);
assign VAR32[1] = ~VAR82[1] & VAR82[0];
assign VAR32[2] = VAR82[1] & ~VAR82[0];
assign VAR32[3] = &(VAR82[1:0]);
assign VAR154[0] =
(~VAR196[0] & ~VAR58[0] & VAR9[VAR12]) |
(~VAR212[0] & (VAR196[0] | VAR58[0]) & VAR9[VAR119]) |
( VAR212[0] & ~VAR196[0] & VAR58[0] & VAR9[VAR119]);
assign VAR154[1] =
(~VAR196[1] & ~VAR58[1] & VAR193[VAR12]) |
(~VAR212[1] & (VAR196[1] | VAR58[1]) & VAR193[VAR119]) |
( VAR212[1] & ~VAR196[1] & VAR58[1] & VAR193[VAR119]);
assign VAR154[2] =
(~VAR196[2] & ~VAR58[2] & VAR54[VAR12]) |
(~VAR212[2] & (VAR196[2] | VAR58[2]) & VAR54[VAR119]) |
( VAR212[2] & ~VAR196[2] & VAR58[2] & VAR54[VAR119]);
assign VAR154[3] =
(~VAR196[3] & ~VAR58[3] & VAR31[VAR12]) |
(~VAR212[3] & (VAR196[3] | VAR58[3]) & VAR31[VAR119]) |
( VAR212[3] & ~VAR196[3] & VAR58[3] & VAR31[VAR119]);
assign VAR3[3:0] = VAR175[3:0] & VAR7[3:0] & ({4{~VAR35 | VAR214}});
assign VAR136[32:0] = VAR110[32:0] + VAR3[0];
assign VAR118[32:0] = VAR221[32:0] + VAR3[1];
assign VAR137[32:0] = VAR263[32:0] + VAR3[2];
assign VAR236[32:0] = VAR69[32:0] + VAR3[3];
assign VAR184[7] = ((VAR9[VAR215:VAR76] == VAR56) & VAR154[0]);
assign VAR184[6] = ((VAR9[VAR215:VAR76] == VAR78) & VAR154[0]);
assign VAR184[5] = ((VAR9[VAR215:VAR76] == VAR171) & VAR154[0]);
assign VAR184[4] = ((VAR9[VAR215:VAR76] == VAR99) & VAR154[0]);
assign VAR184[3] = ((VAR9[VAR215:VAR76] == VAR243) & VAR154[0]);
assign VAR184[2] = ((VAR9[VAR215:VAR76] == VAR68) & VAR154[0]);
assign VAR184[1] = ((VAR9[VAR215:VAR76] == VAR163) & VAR154[0]);
assign VAR184[0] = ((VAR9[VAR215:VAR76] == VAR114) & VAR154[0]);
assign VAR14[7] = ((VAR193[VAR215:VAR76] == VAR56) & VAR154[1]);
assign VAR14[6] = ((VAR193[VAR215:VAR76] == VAR78) & VAR154[1]);
assign VAR14[5] = ((VAR193[VAR215:VAR76] == VAR171) & VAR154[1]);
assign VAR14[4] = ((VAR193[VAR215:VAR76] == VAR99) & VAR154[1]);
assign VAR14[3] = ((VAR193[VAR215:VAR76] == VAR243) & VAR154[1]);
assign VAR14[2] = ((VAR193[VAR215:VAR76] == VAR68) & VAR154[1]);
assign VAR14[1] = ((VAR193[VAR215:VAR76] == VAR163) & VAR154[1]);
assign VAR14[0] = ((VAR193[VAR215:VAR76] == VAR114) & VAR154[1]);
assign VAR267[7] = ((VAR54[VAR215:VAR76] == VAR56) & VAR154[2]);
assign VAR267[6] = ((VAR54[VAR215:VAR76] == VAR78) & VAR154[2]);
assign VAR267[5] = ((VAR54[VAR215:VAR76] == VAR171) & VAR154[2]);
assign VAR267[4] = ((VAR54[VAR215:VAR76] == VAR99) & VAR154[2]);
assign VAR267[3] = ((VAR54[VAR215:VAR76] == VAR243) & VAR154[2]);
assign VAR267[2] = ((VAR54[VAR215:VAR76] == VAR68) & VAR154[2]);
assign VAR267[1] = ((VAR54[VAR215:VAR76] == VAR163) & VAR154[2]);
assign VAR267[0] = ((VAR54[VAR215:VAR76] == VAR114) & VAR154[2]);
assign VAR139[7] = ((VAR31[VAR215:VAR76] == VAR56) & VAR154[3]);
assign VAR139[6] = ((VAR31[VAR215:VAR76] == VAR78) & VAR154[3]);
assign VAR139[5] = ((VAR31[VAR215:VAR76] == VAR171) & VAR154[3]);
assign VAR139[4] = ((VAR31[VAR215:VAR76] == VAR99) & VAR154[3]);
assign VAR139[3] = ((VAR31[VAR215:VAR76] == VAR243) & VAR154[3]);
assign VAR139[2] = ((VAR31[VAR215:VAR76] == VAR68) & VAR154[3]);
assign VAR139[1] = ((VAR31[VAR215:VAR76] == VAR163) & VAR154[3]);
assign VAR139[0] = ((VAR31[VAR215:VAR76] == VAR114) & VAR154[3]);
assign VAR46[7:0] = {VAR144[0], VAR17[0], VAR151[0], VAR270[0],
VAR271[0], VAR187[0], VAR106[0], VAR116[0]};
assign VAR131[7:0] = {VAR144[1], VAR17[1], VAR151[1], VAR270[1],
VAR271[1], VAR187[1], VAR106[1], VAR116[1]};
assign VAR134[7:0] = {VAR144[2], VAR17[2], VAR151[2], VAR270[2],
VAR271[2], VAR187[2], VAR106[2], VAR116[2]};
assign VAR145[7:0] = {VAR144[3], VAR17[3], VAR151[3], VAR270[3],
VAR271[3], VAR187[3], VAR106[3], VAR116[3]};
assign VAR19[3:0] = { (|(VAR139[7:0] & VAR145[7:0])), (|(VAR267[7:0] & VAR134[7:0])),
(|(VAR14[7:0] & VAR131[7:0])), (|(VAR184[7:0] & VAR46[7:0])) };
assign VAR244[0] = ((VAR162[0] ^ VAR110[32]) & VAR154[0]);
assign VAR244[1] = ((VAR162[1] ^ VAR221[32]) & VAR154[1]);
assign VAR244[2] = ((VAR162[2] ^ VAR263[32]) & VAR154[2]);
assign VAR244[3] = ((VAR162[3] ^ VAR69[32]) & VAR154[3]);
assign VAR183[0] = ((VAR199[0] ^ VAR254[32]) & VAR77[0]);
assign VAR183[1] = ((VAR199[1] ^ VAR228[32]) & VAR77[1]);
assign VAR183[2] = ((VAR199[2] ^ VAR91[32]) & VAR77[2]);
assign VAR183[3] = ((VAR199[3] ^ VAR241[32]) & VAR77[3]);
assign VAR194[0] = (&VAR110[31:0]) & VAR154[0];
assign VAR194[1] = (&VAR221[31:0]) & VAR154[1];
assign VAR194[2] = (&VAR263[31:0]) & VAR154[2];
assign VAR194[3] = (&VAR69[31:0]) & VAR154[3];
assign VAR238 = ( (VAR122) |
(VAR176 & VAR258 &
(VAR4[1:0] === VAR66[1:0])) );
assign VAR113 = VAR192 & (VAR4[1:0] === VAR66[1:0]);
assign VAR92[3:0] = (VAR202[3]) ? VAR36[3:0] :
(VAR202[2]) ? VAR174[3:0] :
(VAR202[1]) ? VAR235[3:0] :
(VAR202[0]) ? VAR79[3:0] :
4'h0;
assign VAR85[2:0] = (VAR202[3]) ? VAR41[2:0] :
(VAR202[2]) ? VAR203[2:0] :
(VAR202[1]) ? VAR226[2:0] :
(VAR202[0]) ? VAR15[2:0] :
3'h0;
assign VAR190 = VAR100 & ( (VAR45[3]) ? VAR123 :
(VAR45[2]) ? VAR129 :
(VAR45[1]) ? VAR207 :
(VAR45[0]) ? VAR48 : 1'b0 );
assign VAR216 =
(|((VAR244[3:0] | VAR169[3:0] |
(VAR194[3:0] & VAR45[3:0] & VAR62[3:0] & VAR7[3:0])) &
(~VAR10[3:0] | VAR196[3:0]) &
(VAR83[3:0]) &
(VAR202[3:0]))) &
(VAR34) & (VAR92[3:0] < 15) &
(~(VAR238 | VAR113 | VAR158));
assign VAR188 = (VAR216 & (VAR85[2:0] === 3'h2) & VAR212[VAR4]) ? 14'h040 : 14'h9e0;
|
gpl-2.0
|
Rmin1995/NoC
|
priority_vc_perInput.v
| 4,826 |
module MODULE1(
output [0:VAR2-1] VAR22,
output [0:VAR2-1] VAR18,
output [1:VAR21 * VAR2] VAR5,
output VAR28,
output [0:VAR6*VAR2-1] VAR16,
input VAR13,
input [0:VAR4-1] VAR8,
input [0:VAR2-1] VAR17,
input [0:VAR2-1] VAR33,
input [0:VAR2-1] VAR1,
input [1:VAR21] VAR24,
input [1:VAR21 * VAR2] VAR27,
input [0:VAR6*VAR2-1] VAR7,
input [0:VAR3-1]VAR9
);
parameter VAR10 = 4;
genvar VAR20;
wire [0:VAR4-1] VAR25;
VAR14 VAR29(.VAR11(VAR25),
.select(VAR24 VAR15),
.VAR9(VAR9)
);
genvar VAR26;
generate
for(VAR26=0;VAR26<VAR2;VAR26=VAR26+1)
begin : VAR12
assign VAR22[VAR26] = (VAR26 == VAR8 && VAR13 ? ((VAR17[VAR26]==1'b0 && VAR33[VAR25]==1'b0 &&
VAR1[VAR25]==1'b1 &&
(VAR31[VAR25] VAR32==1'b0 ||
(VAR31[VAR25] VAR32==1'b1 && VAR31[VAR25] VAR30 == VAR26)) ) ? 1'b1
: VAR17[VAR26])
: VAR17[VAR26]);
assign VAR5[VAR26*VAR21+1 : (VAR26+1)*VAR21] = (VAR26 == VAR8 && VAR13 ? ((VAR17[VAR26]==1'b0 && VAR33[VAR25]==1'b0 &&
VAR1[VAR25]==1'b1 &&
(VAR31[VAR25] VAR32==1'b0 ||
(VAR31[VAR25] VAR32 && VAR31[VAR25] VAR30 == VAR26)) ) ? VAR24
: VAR27[VAR26*VAR21+1 : (VAR26+1)*VAR21])
: VAR27[VAR26*VAR21+1 : (VAR26+1)*VAR21]);
assign VAR18[VAR26] = (VAR26 == VAR25 && VAR13 ? ((VAR17[VAR8]==1'b0 && VAR33[VAR25]==1'b0 &&
VAR1[VAR25]==1'b1 &&
(VAR31[VAR25] VAR32==1'b0 ||
(VAR31[VAR25] VAR32==1'b1 && VAR31[VAR25] VAR30 == VAR8)) ) ? 1'b1
:VAR33[VAR26])
:VAR33[VAR26]);
assign VAR19[VAR26] = (VAR26 == VAR25 && VAR13 ? ((VAR17[VAR8]==1'b0 && VAR33[VAR25]==1'b0 &&
VAR1[VAR25]==1'b1 &&
(VAR31[VAR25] VAR32==1'b0 ||
(VAR31[VAR25] VAR32==1'b1 && VAR31[VAR25] VAR30 == VAR8)) ) ? (VAR24 VAR23 ? {VAR6{1'b0}} : {1'b1,VAR8[0:VAR4-1]})
:VAR31[VAR26])
:VAR31[VAR26]);
end
assign VAR28 = ((VAR17[VAR8]==1'b0 && VAR33[VAR25]==1'b0 &&
VAR1[VAR25]==1'b1 &&
(VAR31[VAR25] VAR32==1'b0 ||
(VAR31[VAR25] VAR32 && VAR31[VAR25] VAR30 == VAR8)) ) ? 1'b1 : 1'b0);
endgenerate
endmodule
|
gpl-3.0
|
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