repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.behavioral.v
| 1,175 |
module MODULE1( VAR5, VAR1, VAR6 );
input VAR5, VAR1;
output VAR6;
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6));
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nor2b/sky130_fd_sc_lp__nor2b.pp.symbol.v
| 1,325 |
module MODULE1 (
input VAR3 ,
input VAR4 ,
output VAR6 ,
input VAR2 ,
input VAR5,
input VAR1,
input VAR7
);
endmodule
|
apache-2.0
|
somethingnew2-0/CS552-CPU
|
ExecuteForwarding.v
| 2,105 |
module MODULE1(VAR16, VAR13, VAR6, VAR10, VAR7, VAR4, VAR3, VAR1, VAR12, VAR24, VAR14, VAR17, VAR25, VAR23, VAR11, VAR9, VAR20, VAR8, VAR22, VAR18, VAR15, VAR5, VAR2);
input [15:0] VAR16, VAR13, VAR3, VAR12, VAR25, VAR11, VAR20, VAR8;
input [3:0] VAR6, VAR10, VAR7, VAR14, VAR22;
input VAR4, VAR1, VAR24, VAR17, VAR23, VAR9, VAR18;
output [15:0] VAR15, VAR5;
output VAR2;
wire [15:0] VAR19, VAR21;
assign VAR19 = VAR1 ? VAR12 : VAR3;
assign VAR21 = VAR23 ? VAR11 : (VAR9 ? VAR20 : VAR25);
assign VAR15 = (VAR6 == 4'b0000) ? VAR16 :
(VAR4 && (VAR6 == VAR7) && !(VAR17 && VAR9 && (VAR6 == VAR14))) ? VAR19 :
(VAR17 && (VAR6 == VAR14)) ? VAR21:
(VAR18 && (VAR6 == VAR22)) ? VAR8 :
VAR16;
assign VAR5 = (VAR10 == 4'b0000) ? VAR13 :
(VAR4 && (VAR10 == VAR7) && !(VAR17 && VAR9 && (VAR10 == VAR14))) ? VAR19 :
(VAR17 && (VAR10 == VAR14)) ? VAR21 :
(VAR18 && (VAR10 == VAR22)) ? VAR8 :
VAR13;
assign VAR2 = (VAR4 &&
(((VAR6 == VAR7) && VAR24 &&
!(VAR17 && VAR9 && (VAR6 == VAR14))) ||
((VAR10 == VAR7) && VAR24 &&
!(VAR17 && VAR9 && (VAR10 == VAR14)))));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.blackbox.v
| 1,391 |
module MODULE1 (
VAR8 ,
VAR4 ,
VAR2 ,
VAR10 ,
VAR3 ,
VAR6
);
output VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR10 ;
input VAR3 ;
input VAR6;
supply1 VAR1;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/verilog/convolve_kernel_fbkb.v
| 1,946 |
module MODULE1
VAR22 = 0,
VAR19 = 5,
VAR15 = 32,
VAR26 = 32,
VAR2 = 32
)(
input wire clk,
input wire reset,
input wire VAR1,
input wire [VAR15-1:0] VAR8,
input wire [VAR26-1:0] VAR12,
output wire [VAR2-1:0] dout
);
wire VAR10;
wire VAR6;
wire VAR13;
wire [31:0] VAR11;
wire VAR17;
wire [31:0] VAR7;
wire VAR21;
wire [31:0] VAR23;
reg [VAR15-1:0] VAR4;
reg [VAR26-1:0] VAR16;
VAR24 VAR18 (
.VAR10 ( VAR10 ),
.VAR6 ( VAR6 ),
.VAR9 ( VAR13 ),
.VAR3 ( VAR11 ),
.VAR14 ( VAR17 ),
.VAR5 ( VAR7 ),
.VAR20 ( VAR21 ),
.VAR25 ( VAR23 )
);
assign VAR10 = clk;
assign VAR6 = VAR1;
assign VAR13 = 1'b1;
assign VAR11 = VAR4;
assign VAR17 = 1'b1;
assign VAR7 = VAR16;
assign dout = VAR23;
always @(posedge clk) begin
if (VAR1) begin
VAR4 <= VAR8;
VAR16 <= VAR12;
end
end
endmodule
|
mit
|
vad-rulezz/megabot
|
minsoc/rtl/verilog/minsoc_startup/spi_clgen.v
| 5,136 |
module MODULE1 (VAR9, rst, VAR8, enable, VAR7, VAR3, posedge, negedge);
parameter VAR5 = 2;
parameter VAR6 = 1;
parameter VAR10 = 1;
input VAR9; input rst; input enable; input VAR8; input VAR7; output VAR3; output posedge; output negedge;
reg VAR3;
reg posedge;
reg negedge;
reg [VAR5-1:0] VAR1; wire VAR4; wire VAR2;
assign VAR4 = VAR1 == {VAR5{1'b0}};
assign VAR2 = VAR1 == {{VAR5-1{1'b0}}, 1'b1};
always @(posedge VAR9 or posedge rst)
begin
if(rst)
VAR1 <= #VAR10 {VAR5{1'b1}};
end
else
begin
if(!enable || VAR4)
VAR1 <= #VAR10 VAR6;
end
else
VAR1 <= #VAR10 VAR1 - {{VAR5-1{1'b0}}, 1'b1};
end
end
always @(posedge VAR9 or posedge rst)
begin
if(rst)
VAR3 <= #VAR10 1'b0;
end
else
VAR3 <= #VAR10 (enable && VAR4 && (!VAR7 || VAR3)) ? ~VAR3 : VAR3;
end
always @(posedge VAR9 or posedge rst)
begin
if(rst)
begin
posedge <= #VAR10 1'b0;
negedge <= #VAR10 1'b0;
end
else
begin
posedge <= #VAR10 (enable && !VAR3 && VAR2) || (!(|VAR6) && VAR3) || (!(|VAR6) && VAR8 && !enable);
negedge <= #VAR10 (enable && VAR3 && VAR2) || (!(|VAR6) && !VAR3 && enable);
end
end
endmodule
|
gpl-2.0
|
scalable-networks/ext
|
uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v
| 1,674 |
module MODULE1
(input clk,
input VAR4,
input VAR23,
input [VAR29-1:0] VAR3,
input [VAR29-1:0] VAR28,
output reg [(2*VAR29)-1:0] out);
wire [VAR29-1:0] VAR24;
wire VAR25;
wire [(2*VAR29)-1:0] VAR34;
reg [(2*VAR29)-1:0] VAR13;
VAR14 #(.VAR18("VAR5"), .VAR17("VAR6"))
VAR32 (.VAR20(VAR25), .VAR16(VAR4), .VAR21(VAR23));
genvar VAR1;
generate
for(VAR1 = 0; VAR1 < VAR29; VAR1 = VAR1 + 1)
begin : VAR26
VAR31 #(.VAR18("VAR5"),.VAR17("VAR33")) VAR12
(.VAR20(VAR24[VAR1]), .VAR16(VAR3[VAR1]), .VAR21(VAR28[VAR1]) );
VAR30 #(.VAR2("VAR15")) VAR8
(.VAR27(VAR34[2*VAR1]), .VAR7(VAR34[(2*VAR1)+1]), .VAR19(VAR25), .VAR15(~VAR25),
.VAR11(1'b1), .VAR10(VAR24[VAR1]), .VAR9(1'b0), .VAR22(1'b0));
end
endgenerate
always @(posedge clk)
VAR13 <= VAR34;
always @(posedge clk)
out <= VAR13;
endmodule
|
gpl-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/channel_adapter/master_0_b2p_adapter.v
| 1,510 |
module MODULE1 (
input clk,
input VAR10,
output reg VAR9,
input VAR2,
input [ 7: 0] VAR6,
input [ 7: 0] VAR8,
input VAR4,
input VAR7,
input VAR5,
output reg VAR11,
output reg [ 7: 0] VAR3,
output reg VAR12,
output reg VAR13
);
reg VAR1;
always @* begin
VAR9 = VAR5;
VAR11 = VAR2;
VAR3 = VAR6;
VAR12 = VAR4;
VAR13 = VAR7;
VAR1 = VAR8 ;
if (VAR8 > 0) begin
VAR11 = 0;
end
end
endmodule
|
mit
|
takeshineshiro/fpga_fibre_scan
|
HUCB2P0_150701/usb_core/usb_121pll/usb_121pll_0002.v
| 2,235 |
module MODULE1(
input wire VAR27,
input wire rst,
output wire VAR36,
output wire VAR8,
output wire VAR64
);
VAR55 #(
.VAR40("false"),
.VAR7("20.0 VAR35"),
.VAR47("VAR21"),
.VAR11(2),
.VAR30("60.000000 VAR35"),
.VAR38("0 VAR20"),
.VAR50(50),
.VAR12("60.000000 VAR35"),
.VAR5("8333 VAR20"),
.VAR39(50),
.VAR70("0 VAR35"),
.VAR9("0 VAR20"),
.VAR60(50),
.VAR34("0 VAR35"),
.VAR69("0 VAR20"),
.VAR62(50),
.VAR16("0 VAR35"),
.VAR59("0 VAR20"),
.VAR25(50),
.VAR4("0 VAR35"),
.VAR45("0 VAR20"),
.VAR1(50),
.VAR44("0 VAR35"),
.VAR57("0 VAR20"),
.VAR14(50),
.VAR71("0 VAR35"),
.VAR15("0 VAR20"),
.VAR51(50),
.VAR65("0 VAR35"),
.VAR56("0 VAR20"),
.VAR17(50),
.VAR23("0 VAR35"),
.VAR53("0 VAR20"),
.VAR19(50),
.VAR2("0 VAR35"),
.VAR33("0 VAR20"),
.VAR43(50),
.VAR28("0 VAR35"),
.VAR58("0 VAR20"),
.VAR13(50),
.VAR67("0 VAR35"),
.VAR37("0 VAR20"),
.VAR31(50),
.VAR54("0 VAR35"),
.VAR3("0 VAR20"),
.VAR48(50),
.VAR24("0 VAR35"),
.VAR61("0 VAR20"),
.VAR22(50),
.VAR46("0 VAR35"),
.VAR66("0 VAR20"),
.VAR10(50),
.VAR26("0 VAR35"),
.VAR72("0 VAR20"),
.VAR73(50),
.VAR29("0 VAR35"),
.VAR18("0 VAR20"),
.VAR68(50),
.VAR41("VAR49"),
.VAR52("VAR49")
) VAR32 (
.rst (rst),
.VAR6 ({VAR8, VAR36}),
.VAR64 (VAR64),
.VAR42 ( ),
.VAR63 (1'b0),
.VAR27 (VAR27)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a41oi/sky130_fd_sc_ls__a41oi.symbol.v
| 1,389 |
module MODULE1 (
input VAR4,
input VAR6,
input VAR2,
input VAR8,
input VAR7,
output VAR5
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/prbs_gen.v
| 5,781 |
module MODULE1 #
(
parameter VAR7 = 4
)
(
input clk,
input VAR6,
input rst,
output [VAR7-1:0] VAR9
);
localparam VAR11 = 0;
reg [VAR7 - 1:0] VAR2;
reg [VAR7 - 1:0] VAR4;
reg [3:0] VAR10;
reg VAR1, VAR5;
integer VAR3;
always @ (posedge clk)
begin
if (rst )
VAR4 <= {{VAR7-1{1'b0}},1'b1};
end
else if (VAR6) begin
if ( VAR11 == 0)
VAR4 <= VAR2;
VAR10 <= {VAR10[2:0],VAR4[VAR7-1]};
end
end
always @ (VAR4)
begin :VAR8
VAR1 = ~| VAR4[VAR7-2:0];
VAR5 = VAR4[VAR7-1]^VAR1;
for (VAR3 = VAR7 - 1; VAR3 >= 1 ; VAR3 = VAR3-1)
VAR2[VAR3] = VAR4[VAR3-1];
case (VAR7)
32'd4:
VAR2[0] = VAR5^VAR4[2];
32'd8:
VAR2[0] = VAR5^VAR4[3]^VAR4[4]^VAR4[5];
32'd10:
VAR2[0] = VAR5^VAR4[6];
32'd14:
VAR2[0] = VAR5^VAR4[0]^VAR4[2]^VAR4[4];
32'd24:
VAR2[0] = VAR5^VAR4[16]^VAR4[21]^VAR4[22];
32'd32:
VAR2[0] = VAR5^VAR4[0]^VAR4[1]^VAR4[21];
32'd42:
VAR2[0] = VAR5^VAR4[18]^VAR4[19]^VAR4[40];
32'd56:
VAR2[0] = VAR5^VAR4[33]^VAR4[34]^VAR4[54];
32'd64:
VAR2[0] = VAR5^VAR4[59]^VAR4[60]^VAR4[62];
32'd72:
VAR2[0] = VAR5^VAR4[18]^VAR4[24]^VAR4[65];
default:
VAR2[0] = VAR5^VAR4[59]^VAR4[60]^VAR4[62];
endcase
end
assign VAR9 = VAR4;
endmodule
|
lgpl-3.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_performance_counter_0.v
| 5,070 |
module MODULE1 (
address,
VAR18,
clk,
VAR17,
write,
VAR16,
VAR19
)
;
output [ 31: 0] VAR19;
input [ 2: 0] address;
input VAR18;
input clk;
input VAR17;
input write;
input [ 31: 0] VAR16;
wire VAR14;
reg [ 63: 0] VAR15;
reg [ 63: 0] VAR9;
wire VAR3;
wire VAR12;
wire VAR10;
wire VAR6;
wire [ 31: 0] VAR5;
reg [ 31: 0] VAR19;
wire VAR7;
wire VAR2;
reg [ 63: 0] VAR4;
reg [ 63: 0] VAR8;
reg VAR13;
reg VAR11;
wire VAR1;
assign VAR14 = -1;
assign VAR1 = write & VAR18;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR4 <= 0;
end
else if ((VAR13 & VAR3) | VAR12)
if (VAR12)
VAR4 <= 0;
else
VAR4 <= VAR4 + 1;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR15 <= 0;
end
else if ((VAR10 & VAR3) | VAR12)
if (VAR12)
VAR15 <= 0;
else
VAR15 <= VAR15 + 1;
end
assign VAR7 = (address == 0) && VAR1;
assign VAR10 = (address == 1) && VAR1;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR13 <= 0;
end
else if (VAR14)
if (VAR7 | VAR12)
VAR13 <= 0;
else if (VAR10)
VAR13 <= -1;
end
assign VAR3 = VAR13 | VAR10;
assign VAR12 = VAR7 && VAR16[0];
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR8 <= 0;
end
else if ((VAR11 & VAR3) | VAR12)
if (VAR12)
VAR8 <= 0;
else
VAR8 <= VAR8 + 1;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR9 <= 0;
end
else if ((VAR6 & VAR3) | VAR12)
if (VAR12)
VAR9 <= 0;
else
VAR9 <= VAR9 + 1;
end
assign VAR2 = (address == 4) && VAR1;
assign VAR6 = (address == 5) && VAR1;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR11 <= 0;
end
else if (VAR14)
if (VAR2 | VAR12)
VAR11 <= 0;
else if (VAR6)
VAR11 <= -1;
end
assign VAR5 = ({32 {(address == 0)}} & VAR4[31 : 0]) |
({32 {(address == 1)}} & VAR4[63 : 32]) |
({32 {(address == 2)}} & VAR15) |
({32 {(address == 4)}} & VAR8[31 : 0]) |
({32 {(address == 5)}} & VAR8[63 : 32]) |
({32 {(address == 6)}} & VAR9);
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR19 <= 0;
end
else if (VAR14)
VAR19 <= VAR5;
end
endmodule
|
gpl-2.0
|
rkrajnc/minimig-mist
|
rtl/cache/CacheBlockRAM.v
| 10,770 |
module MODULE1 (
VAR8,
VAR25,
VAR4,
VAR16,
VAR6,
VAR52,
VAR9,
VAR64,
VAR57);
input [8:0] VAR8;
input [8:0] VAR25;
input VAR4;
input [17:0] VAR16;
input [17:0] VAR6;
input VAR52;
input VAR9;
output [17:0] VAR64;
output [17:0] VAR57;
tri1 VAR4;
tri0 VAR52;
tri0 VAR9;
wire [17:0] VAR62;
wire [17:0] VAR36;
wire [17:0] VAR64 = VAR62[17:0];
wire [17:0] VAR57 = VAR36[17:0];
VAR33 VAR3 (
.VAR17 (VAR4),
.VAR52 (VAR52),
.VAR25 (VAR25),
.VAR6 (VAR6),
.VAR9 (VAR9),
.VAR8 (VAR8),
.VAR16 (VAR16),
.VAR64 (VAR62),
.VAR57 (VAR36),
.VAR50 (1'b0),
.VAR54 (1'b0),
.VAR43 (1'b0),
.VAR21 (1'b0),
.VAR59 (1'b1),
.VAR12 (1'b1),
.VAR41 (1'b1),
.VAR66 (1'b1),
.VAR1 (1'b1),
.VAR47 (1'b1),
.VAR7 (1'b1),
.VAR49 (),
.VAR23 (1'b1),
.VAR10 (1'b1));
VAR3.VAR26 = "VAR48",
VAR3.VAR11 = "VAR29",
VAR3.VAR51 = "VAR29",
VAR3.VAR28 = "VAR29",
VAR3.VAR2 = "VAR29",
VAR3.VAR39 = "VAR48",
VAR3.VAR61 = "VAR37 VAR24",
VAR3.VAR42 = "VAR33",
VAR3.VAR15 = 512,
VAR3.VAR58 = 512,
VAR3.VAR5 = "VAR13",
VAR3.VAR45 = "VAR46",
VAR3.VAR27 = "VAR46",
VAR3.VAR55 = "VAR32",
VAR3.VAR31 = "VAR32",
VAR3.VAR60 = "VAR18",
VAR3.VAR35 = "VAR19",
VAR3.VAR14 = "VAR44",
VAR3.VAR65 = "VAR34",
VAR3.VAR56 = "VAR34",
VAR3.VAR30 = 9,
VAR3.VAR22 = 9,
VAR3.VAR40 = 18,
VAR3.VAR20 = 18,
VAR3.VAR53 = 1,
VAR3.VAR63 = 1,
VAR3.VAR38 = "VAR48";
endmodule
|
gpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/prcfg/bist/prcfg_adc.v
| 6,030 |
module MODULE1 (
clk,
VAR20,
VAR11,
VAR5,
VAR28,
VAR8,
VAR15,
VAR6,
VAR10,
VAR17,
VAR24
);
localparam VAR26 = 8'hA1;
parameter VAR7 = 0;
input clk;
input [31:0] VAR20;
output [31:0] VAR11;
input VAR5;
input VAR28;
input [31:0] VAR8;
output VAR15;
output VAR6;
output VAR10;
output [31:0] VAR17;
input VAR24;
reg VAR6;
reg VAR10;
reg [31:0] VAR17;
reg VAR15;
reg [31:0] VAR11 = 0;
reg [31:0] VAR1 = 0;
reg [ 3:0] VAR2;
reg [ 3:0] VAR14;
wire VAR22;
wire [31:0] VAR9;
wire VAR12;
wire VAR16;
function [31:0] VAR19;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[14] ^ din[13];
dout[30] = din[13] ^ din[12];
dout[29] = din[12] ^ din[11];
dout[28] = din[11] ^ din[10];
dout[27] = din[10] ^ din[9];
dout[26] = din[9] ^ din[8];
dout[25] = din[8] ^ din[7];
dout[24] = din[7] ^ din[6];
dout[23] = din[6] ^ din[5];
dout[22] = din[5] ^ din[4];
dout[21] = din[4] ^ din[3];
dout[20] = din[3] ^ din[2];
dout[19] = din[2] ^ din[1];
dout[18] = din[1] ^ din[0];
dout[17] = din[0] ^ din[14] ^ din[13];
dout[16] = din[14] ^ din[12];
dout[15] = din[13] ^ din[11];
dout[14] = din[12] ^ din[10];
dout[13] = din[11] ^ din[9];
dout[12] = din[10] ^ din[8];
dout[11] = din[9] ^ din[7];
dout[10] = din[8] ^ din[6];
dout[9] = din[7] ^ din[5];
dout[8] = din[6] ^ din[4];
dout[7] = din[5] ^ din[3];
dout[6] = din[4] ^ din[2];
dout[5] = din[3] ^ din[1];
dout[4] = din[2] ^ din[0];
dout[3] = din[1] ^ din[14] ^ din[13];
dout[2] = din[0] ^ din[13] ^ din[12];
dout[1] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[0] = din[13] ^ din[11] ^ din[12] ^ din[10];
VAR19 = dout;
end
endfunction
assign VAR22 = VAR5 & VAR28;
always @(posedge clk) begin
VAR14 <= VAR20[3:0];
VAR2 <= VAR20[7:4];
end
always @(posedge clk) begin
if(VAR22 == 1'b1) begin
VAR1 <= VAR19(VAR9);
end
end
assign VAR9 = (VAR12 == 1'b1) ? VAR8 : VAR1;
VAR29 #(
.VAR18(32)
) VAR4 (
.VAR3(clk),
.VAR23(VAR22),
.VAR21(VAR8),
.VAR25(VAR1),
.VAR13(VAR12),
.VAR27(VAR16));
always @(posedge clk) begin
VAR6 <= VAR5;
VAR10 <= VAR28;
VAR17 <= VAR8;
VAR15 <= VAR24;
end
always @(posedge clk) begin
if((VAR2 == 3'd2) && (VAR14 == VAR7)) begin
VAR11 <= {22'h0, VAR16, VAR12, VAR26};
end else begin
VAR11 <= {24'h0, VAR26};
end
end
endmodule
|
gpl-3.0
|
alankarkotwal/lca-processor
|
misc/mux.v
| 1,221 |
module MODULE2(VAR7, VAR6, VAR3, VAR5, VAR4, VAR1, VAR9, VAR2, VAR8, out);
output reg [15:0] out;
input [15:0] VAR7, VAR6, VAR3, VAR5, VAR4, VAR1, VAR9, VAR2;
input [2:0] VAR8;
always@(VAR7 or VAR6 or VAR3 or VAR5 or VAR4 or VAR1 or VAR9 or VAR2 or VAR8) begin
case(VAR8)
0: out = VAR7;
1: out = VAR6;
2: out = VAR3;
3: out = VAR5;
4: out = VAR4;
5: out = VAR1;
6: out = VAR9;
7: out = VAR2;
endcase
end
endmodule
module MODULE3(VAR7, VAR6, VAR3, VAR5, VAR8, out);
output reg [15:0] out;
input [15:0] VAR7, VAR6, VAR3, VAR5;
input [1:0] VAR8;
always@(VAR7 or VAR6 or VAR3 or VAR5 or VAR8) begin
case(VAR8)
0: out = VAR7;
1: out = VAR6;
2: out = VAR3;
3: out = VAR5;
endcase
end
endmodule
module MODULE1(VAR7, VAR6, VAR8, out);
output reg [15:0] out;
input [15:0] VAR7, VAR6;
input VAR8;
always@(VAR7 or VAR6 or VAR8) begin
case(VAR8)
0: out = VAR7;
1: out = VAR6;
endcase
end
endmodule
|
gpl-2.0
|
peteasa/oh
|
src/common/hdl/oh_clockdiv.v
| 4,553 |
module MODULE1
(
input clk, input VAR11, input VAR25, input VAR15, input [7:0] VAR7, input [15:0] VAR26, input [15:0] VAR23, output VAR17, output VAR10, output VAR31, output VAR8, output VAR2, output VAR3, output VAR28 );
reg [7:0] counter;
reg VAR19;
reg VAR5;
reg VAR24;
reg [2:0] period;
wire VAR29;
wire [3:0] VAR21;
wire [3:0] VAR22;
wire [1:0] VAR4;
wire [1:0] VAR1;
always @ (posedge clk or negedge VAR11)
if(!VAR11)
period[2:0] <= 'b0;
else if (VAR25)
period[2:0] <='b0;
else if(VAR29 & ~VAR28)
period[2:0] <= period[2:0] +1'b1;
assign VAR28 = (period[2:0]==3'b111);
always @ (posedge clk or negedge VAR11)
if (!VAR11)
counter[7:0] <= 'b0;
else if(VAR15)
if(VAR29)
counter[7:0] <= 'b0;
else
counter[7:0] <= counter[7:0] + 1'b1;
assign VAR29 = (counter[7:0]==VAR7[7:0]);
assign VAR10 = (counter[7:0]==VAR26[7:0]);
assign VAR31 = (counter[7:0]==VAR26[15:8]);
assign VAR2 = (counter[7:0]==VAR23[7:0]);
assign VAR3 = (counter[7:0]==VAR23[15:8]);
always @ (posedge clk or negedge VAR11)
if(!VAR11)
VAR19 <= 1'b0;
else if(VAR10)
VAR19 <= 1'b1;
else if(VAR31)
VAR19 <= 1'b0;
assign VAR4[1] = (VAR7[7:0]==8'd0); assign VAR4[0] = ~(VAR7[7:0]==8'd0);
VAR30 #(.VAR20(2))
VAR18 (.out (VAR1[1:0]),
.clk (clk),
.in (VAR4[1:0]));
VAR6 #(.VAR16(2))
VAR14 (.VAR9(VAR17),
.en(VAR4[1:0]),
.VAR12({clk, VAR19}));
always @ (posedge clk or negedge VAR11)
if(!VAR11)
VAR5 <= 1'b0;
else if(VAR2)
VAR5 <= 1'b1;
else if(VAR3)
VAR5 <= 1'b0;
always @ (negedge clk)
VAR24 <= VAR5;
assign VAR21[3] = 1'b0; assign VAR21[2] = (VAR7[7:0]==8'd0); assign VAR21[1] = (VAR7[7:0]==8'd1); assign VAR21[0] = |VAR7[7:1];
VAR30 #(.VAR20(4))
VAR13 (.out (VAR22[3:0]),
.clk (clk),
.in (VAR21[3:0]));
VAR6 #(.VAR16(4))
VAR27 (.VAR9(VAR8),
.en(VAR21[3:0]),
.VAR12({1'b0, clk, VAR24, VAR5}));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.functional.pp.v
| 2,146 |
module MODULE1 (
VAR10,
VAR9,
VAR12 ,
VAR6,
VAR4,
VAR8 ,
VAR17
);
input VAR10;
input VAR9;
output VAR12 ;
input VAR6;
input VAR4;
input VAR8 ;
input VAR17 ;
wire VAR17 VAR1 ;
wire VAR17 VAR15 ;
wire VAR14 ;
wire VAR5;
and VAR7 (VAR1 , VAR8, VAR17 );
nor VAR13 (VAR15 , VAR6, VAR4 );
nor VAR11 (VAR14 , VAR15, VAR1 );
VAR3 VAR16 (VAR5, VAR14, VAR10, VAR9);
buf VAR2 (VAR12 , VAR5 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/inv/sky130_fd_sc_ms__inv.functional.v
| 1,225 |
module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
wire VAR3;
not VAR4 (VAR3, VAR2 );
buf VAR5 (VAR1 , VAR3 );
endmodule
|
apache-2.0
|
monotone-RK/FACE
|
MCSoC-15/8-way_2-parallel/src/vivado_ip_dram/ui/mig_7series_v2_3_ui_cmd.v
| 11,340 |
module MODULE1 #
(
parameter VAR52 = 100,
parameter VAR11 = 33,
parameter VAR13 = 3,
parameter VAR37 = 12,
parameter VAR40 = 5,
parameter VAR33 = 2,
parameter VAR38 = 16,
parameter VAR36 = 4,
parameter VAR10 = "VAR55"
)
(
VAR34, VAR20, VAR18, VAR25, VAR9, VAR39, VAR28, VAR53, VAR51,
VAR4, VAR12, VAR22,
rst, clk, VAR30, VAR26, VAR58, VAR41, VAR17,
VAR5, VAR42, VAR48, VAR1, VAR46
);
input rst;
input clk;
input VAR30;
input VAR26;
input VAR58;
wire VAR3 = VAR30 && ~VAR26 && ~VAR58;
reg VAR56 = 1'b0 ;
output wire VAR34;
assign VAR34 = VAR56;
input [VAR11-1:0] VAR41;
input [2:0] VAR17;
input VAR5;
input VAR42;
input VAR48;
reg [VAR11-1:0] VAR15 = {VAR11{1'b0}};
reg [VAR11-1:0] VAR44 = {VAR11{1'b0}};
reg [2:0] VAR49;
reg [2:0] VAR14;
reg VAR23;
reg VAR50;
reg VAR57;
reg VAR35;
reg VAR21;
reg VAR32;
wire [VAR11-1:0] VAR19 = VAR56 && VAR48 ? VAR41 : VAR15;
wire [VAR11-1:0] VAR29 = VAR56 ? VAR15 : VAR44;
wire [2:0] VAR6 = VAR56 ? VAR17 : VAR49;
wire [2:0] VAR31 = VAR56 ? VAR49 : VAR14;
wire VAR47 = VAR56 ? VAR5 : VAR23;
wire VAR24 = VAR56 ? VAR23 : VAR50;
wire VAR8 = VAR56 ? VAR42 : VAR57;
wire VAR54 = VAR56 ? VAR57 : VAR35;
wire VAR43 = ~rst && (VAR56 ? VAR48 : VAR21);
wire VAR27 = ~rst && (VAR56 ? VAR21 : VAR32);
always @(posedge clk) begin
if (rst) begin
end else begin
end
end
wire VAR7 = VAR32 && VAR56;
output wire VAR20;
assign VAR20 = VAR7;
output wire [VAR33-1:0] VAR18;
output wire [VAR13-1:0] VAR25;
output wire [VAR38-1:0] VAR9;
output wire [VAR37-1:0] VAR39;
output wire VAR28;
output wire [2:0] VAR53;
output wire VAR51;
generate
begin
if (VAR10 == "VAR16")
begin
assign VAR39[4:0] = VAR56
? VAR15[0+:5]
: VAR44[0+:5];
if (VAR36==1)
begin
assign VAR39[VAR37-1:VAR37-2] = VAR56
? VAR15[5+3+VAR13+:2]
: VAR44[5+3+VAR13+:2];
assign VAR39[VAR37-3:5] = VAR56
? VAR15[5+3+VAR13+2+2+:VAR37-7]
: VAR44[5+3+VAR13+2+2+:VAR37-7];
end
else
begin
assign VAR39[VAR37-1:VAR37-2] = VAR56
? VAR15[5+3+VAR13+VAR33+:2]
: VAR44[5+3+VAR13+VAR33+:2];
assign VAR39[VAR37-3:5] = VAR56
? VAR15[5+3+VAR13+VAR33+2+2+:VAR37-7]
: VAR44[5+3+VAR13+VAR33+2+2+:VAR37-7];
end
assign VAR9[2:0] = VAR56
? VAR15[5+:3]
: VAR44[5+:3];
if (VAR36==1)
begin
assign VAR9[VAR38-1:VAR38-2] = VAR56
? VAR15[5+3+VAR13+2+:2]
: VAR44[5+3+VAR13+2+:2];
assign VAR9[VAR38-3:3] = VAR56
? VAR15[5+3+VAR13+2+2+VAR37-7+:VAR38-5]
: VAR44[5+3+VAR13+2+2+VAR37-7+:VAR38-5];
end
else
begin
assign VAR9[VAR38-1:VAR38-2] = VAR56
? VAR15[5+3+VAR13+VAR33+2+:2]
: VAR44[5+3+VAR13+VAR33+2+:2];
assign VAR9[VAR38-3:3] = VAR56
? VAR15[5+3+VAR13+VAR33+2+2+VAR37-7+:VAR38-5]
: VAR44[5+3+VAR13+VAR33+2+2+VAR37-7+:VAR38-5];
end
assign VAR25 = VAR56
? VAR15[5+3+:VAR13]
: VAR44[5+3+:VAR13];
assign VAR18 = (VAR36 == 1)
? 1'b0
: VAR56
? VAR15[5+3+VAR13+:VAR33]
: VAR44[5+3+VAR13+:VAR33];
end
else if (VAR10 == "VAR45")
begin
assign VAR39 = VAR56
? VAR15[0+:VAR37]
: VAR44[0+:VAR37];
assign VAR9 = VAR56
? VAR15[VAR37+VAR13+:VAR38]
: VAR44[VAR37+VAR13+:VAR38];
assign VAR25 = VAR56
? VAR15[VAR37+:VAR13]
: VAR44[VAR37+:VAR13];
assign VAR18 = (VAR36 == 1)
? 1'b0
: VAR56
? VAR15[VAR37+VAR38+VAR13+:VAR33]
: VAR44[VAR37+VAR38+VAR13+:VAR33];
end
else
begin
assign VAR39 = VAR56
? VAR15[0+:VAR37]
: VAR44[0+:VAR37];
assign VAR9 = VAR56
? VAR15[VAR37+:VAR38]
: VAR44[VAR37+:VAR38];
assign VAR25 = VAR56
? VAR15[VAR37+VAR38+:VAR13]
: VAR44[VAR37+VAR38+:VAR13];
assign VAR18 = (VAR36 == 1)
? 1'b0
: VAR56
? VAR15[VAR37+VAR38+VAR13+:VAR33]
: VAR44[VAR37+VAR38+VAR13+:VAR33];
end
end
endgenerate
assign VAR28 = VAR56
? VAR23
: VAR50;
assign VAR53 = VAR56
? VAR49
: VAR14;
assign VAR51 = VAR56
? VAR57
: VAR35;
wire VAR2 = VAR7 && VAR56;
wire rd = VAR14[1:0] == 2'b01;
wire wr = VAR14[1:0] == 2'b00;
wire VAR59 = VAR14[1:0] == 2'b11;
wire write = wr || VAR59;
output wire VAR4;
assign VAR4 = VAR2 && rd;
output wire VAR12;
assign VAR12 = VAR2 && write;
input [VAR40-1:0] VAR1;
input [VAR40-1:0] VAR46;
output wire [VAR40-1:0] VAR22;
assign VAR22 = ~write ? VAR46 : VAR1;
endmodule
|
mit
|
MeshSr/onetswitch45
|
ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/core/onet_core_logic.v
| 28,719 |
module MODULE1(
input clk, input reset,
input VAR217,
output VAR113,
input [31:0] VAR192,
input VAR42,
input VAR178,
input [3:0] VAR188,
output VAR43,
output VAR75,
output [31:0] VAR7,
output VAR104,
output VAR215,
output [3:0] VAR276,
input VAR24,
input VAR157,
output VAR263,
input [31:0] VAR63,
input VAR218,
input VAR29,
input [3:0] VAR244,
output VAR139,
output VAR236,
output [31:0] VAR229,
output VAR290,
output VAR9,
output [3:0] VAR198,
input VAR82,
input VAR114,
output VAR288,
input [31:0] VAR148,
input VAR89,
input VAR18,
input [3:0] VAR39,
output VAR294,
output VAR235,
output [31:0] VAR155,
output VAR14,
output VAR66,
output [3:0] VAR186,
input VAR223,
input VAR51,
output VAR137,
input [31:0] VAR238,
input VAR222,
input VAR172,
input [3:0] VAR216,
output VAR226,
output VAR141,
output [31:0] VAR147,
output VAR166,
output VAR77,
output [3:0] VAR219,
input VAR71,
input VAR37,
input [31:0] VAR132,
input VAR8,
input VAR84,
input [3:0] VAR124,
output VAR232,
output [31:0] VAR196,
output VAR116,
output VAR83,
output [3:0] VAR15,
input VAR202,
input VAR213,
input [31:0] VAR230,
input VAR227,
input VAR26,
input [3:0] VAR267,
output VAR34,
output [31:0] VAR101,
output VAR169,
output VAR23,
output [3:0] VAR94,
input VAR160,
input VAR50,
input [31:0] VAR162,
input VAR91,
input VAR210,
input [3:0] VAR95,
output VAR65,
output [31:0] VAR68,
output VAR2,
output VAR16,
output [3:0] VAR12,
input VAR301,
input VAR303,
input [31:0] VAR248,
input VAR100,
input VAR272,
input [3:0] VAR20,
output VAR49,
output [31:0] VAR79,
output VAR299,
output VAR62,
output [3:0] VAR111,
input VAR88,
input VAR187,
input VAR181,
input [31:0] VAR6,
input [2:0] VAR255,
input VAR231,
output VAR177,
input [31:0] VAR99,
input [3:0] VAR183,
input VAR145,
output VAR122,
output [1:0] VAR38,
output VAR126,
input VAR53,
input [31:0] VAR270,
input [2:0] VAR130,
input VAR64,
output VAR41,
output [31:0] VAR151,
output [1:0] VAR13,
output VAR287,
input VAR27,
output [4*12 - 1 : 0] VAR182,
output [4*1 - 1 : 0] VAR197
);
localparam VAR76 = 64;
localparam VAR158 = VAR76/8;
localparam VAR269 = 8;
localparam VAR81 = 11;
localparam VAR253 = 2;
wire VAR257;
wire VAR251;
wire [31:0] VAR28;
wire [31:0] VAR221;
wire VAR1;
wire [31:0] VAR85;
wire VAR11;
wire VAR180;
wire [31:0] VAR264;
wire [31:0] VAR297;
wire VAR143;
wire [31:0] VAR110;
wire VAR22;
wire VAR200;
wire [31:0] VAR25;
wire [31:0] VAR256;
wire VAR246;
wire [31:0] VAR131;
wire [3:0] VAR237;
wire [3:0] VAR128;
wire [3:0] VAR86;
wire [4 * VAR280-1:0] VAR106;
wire [4 * 32 - 1:0] VAR70;
wire [4 * 32 - 1:0] VAR90;
wire [15:0] VAR73;
wire [15:0] VAR136;
wire [15:0] VAR164;
wire [16 * VAR45-1:0] VAR60;
wire [16 * 32 - 1:0] VAR152;
wire [16 * 32 - 1:0] VAR115;
wire [3:0] VAR19;
wire [31:0] VAR36 [3:0];
wire VAR173 [3:0];
wire VAR52 [3:0];
wire [3:0] VAR249 [3:0];
wire VAR165 [3:0];
wire [31:0] VAR254 [3:0];
wire VAR125 [3:0];
wire VAR205 [3:0];
wire [3:0] VAR5 [3:0];
wire VAR103 [3:0];
wire [3:0] VAR191;
wire [31:0] VAR33 [3:0];
wire VAR47 [3:0];
wire VAR74 [3:0];
wire [3:0] VAR109 [3:0];
wire VAR159 [3:0];
wire [31:0] VAR135 [3:0];
wire VAR296 [3:0];
wire VAR156 [3:0];
wire [3:0] VAR121 [3:0];
wire VAR247 [3:0];
wire [VAR269-1:0] VAR278;
wire [VAR269-1:0] VAR211;
wire [VAR76-1:0] VAR220 [VAR269-1:0];
wire [VAR158-1:0] VAR258 [VAR269-1:0];
wire [VAR269-1:0] VAR174;
wire [VAR269-1:0] VAR292;
wire [VAR76-1:0] VAR283 [VAR269-1:0];
wire [VAR158-1:0] VAR195 [VAR269-1:0];
generate
genvar VAR204;
for(VAR204=0; VAR204<4; VAR204=VAR204+1) begin: VAR119
VAR117 #(
.VAR76(VAR76),
.VAR55(1),
.VAR140(2 * VAR204),
.VAR87(VAR298)
) VAR117
( .VAR92 (VAR73[VAR184(VAR30 + VAR204,1)]),
.VAR69 (VAR164[VAR184(VAR30 + VAR204,1)]),
.VAR289 (VAR136[VAR184(VAR30 + VAR204,1)]),
.VAR48 (VAR60[VAR184(VAR30 + VAR204,
.VAR167 (VAR115[VAR184(VAR30 + VAR204,32)]),
.VAR243 (VAR152[VAR184(VAR30 + VAR204,32)]),
.VAR278 (VAR174[VAR204*2]),
.VAR211 (VAR292[VAR204*2]),
.VAR220 (VAR283[VAR204*2]),
.VAR258 (VAR195[VAR204*2]),
.VAR174 (VAR278[VAR204*2]),
.VAR292 (VAR211[VAR204*2]),
.VAR283 (VAR220[VAR204*2]),
.VAR195 (VAR258[VAR204*2]),
.VAR273 (VAR36[VAR204]),
.VAR72 (VAR173[VAR204]),
.VAR179 (VAR52[VAR204]),
.VAR275 (VAR165[VAR204]),
.VAR268 (VAR249[VAR204]),
.VAR57 (VAR125[VAR204]),
.VAR266 (VAR254[VAR204]),
.VAR170 (VAR205[VAR204]),
.VAR35 (VAR5[VAR204]),
.VAR146 (VAR103[VAR204]),
.VAR240 (),
.VAR233 (),
.VAR260 (VAR19[VAR204]),
.clk (clk),
.reset (reset)
);
end
endgenerate
VAR3 VAR3 (
.VAR6 (VAR6),
.VAR255 (VAR255),
.VAR231 (VAR231),
.VAR177 (VAR177),
.VAR99 (VAR99),
.VAR183 (VAR183),
.VAR145 (VAR145),
.VAR122 (VAR122),
.VAR38 (VAR38),
.VAR126 (VAR126),
.VAR53 (VAR53),
.VAR270 (VAR270),
.VAR130 (VAR130),
.VAR64 (VAR64),
.VAR41 (VAR41),
.VAR151 (VAR151),
.VAR13 (VAR13),
.VAR287 (VAR287),
.VAR27 (VAR27),
.VAR257 (VAR257),
.VAR251 (VAR251),
.VAR28 (VAR28),
.VAR221 (VAR221),
.VAR1 (VAR1),
.VAR85 (VAR85),
.VAR187 (VAR187),
.VAR181 (VAR181),
.reset (reset),
.clk (clk)
);
VAR208 VAR208 (
.VAR257 (VAR257),
.VAR251 (VAR251),
.VAR28 (VAR28),
.VAR221 (VAR221),
.VAR1 (VAR1),
.VAR85 (VAR85),
.VAR11 (VAR11),
.VAR180 (VAR180),
.VAR264 (VAR264),
.VAR297 (VAR297),
.VAR143 (VAR143),
.VAR110 (VAR110),
.VAR22 (VAR22),
.VAR200 (VAR200),
.VAR25 (VAR25),
.VAR256 (VAR256),
.VAR246 (VAR246),
.VAR131 (VAR131),
.clk (clk),
.reset (reset)
);
VAR54
.VAR76(VAR76),
.VAR158(VAR158),
.VAR253 (VAR253),
.VAR80(VAR269),
.VAR93(VAR269)
)VAR54
(
.VAR120 (VAR283[0]),
.VAR4 (VAR195[0]),
.VAR144 (VAR174[0]),
.VAR61 (VAR292[0]),
.VAR185 (VAR283[1]),
.VAR214 (VAR195[1]),
.VAR107 (VAR174[1]),
.VAR112 (VAR292[1]),
.VAR142 (VAR283[2]),
.VAR281 (VAR195[2]),
.VAR168 (VAR174[2]),
.VAR282 (VAR292[2]),
.VAR304 (VAR283[3]),
.VAR305 (VAR195[3]),
.VAR225 (VAR174[3]),
.VAR209 (VAR292[3]),
.VAR224 (VAR283[4]),
.VAR286 (VAR195[4]),
.VAR32 (VAR174[4]),
.VAR228 (VAR292[4]),
.VAR295 (VAR283[5]),
.VAR252 (VAR195[5]),
.VAR127 (VAR174[5]),
.VAR250 (VAR292[5]),
.VAR40 (VAR283[6]),
.VAR138 (VAR195[6]),
.VAR149 (VAR174[6]),
.VAR234 (VAR292[6]),
.VAR284 (VAR283[7]),
.VAR17 (VAR195[7]),
.VAR300 (VAR174[7]),
.VAR161 (VAR292[7]),
.VAR98 (VAR220[0]),
.VAR261 (VAR258[0]),
.VAR206 (VAR278[0]),
.VAR163 (VAR211[0]),
.VAR58 (VAR220[1]),
.VAR150 (VAR258[1]),
.VAR31 (VAR278[1]),
.VAR118 (VAR211[1]),
.VAR10 (VAR220[2]),
.VAR259 (VAR258[2]),
.VAR190 (VAR278[2]),
.VAR59 (VAR211[2]),
.VAR189 (VAR220[3]),
.VAR134 (VAR258[3]),
.VAR291 (VAR278[3]),
.VAR207 (VAR211[3]),
.VAR44 (VAR220[4]),
.VAR271 (VAR258[4]),
.VAR201 (VAR278[4]),
.VAR265 (VAR211[4]),
.VAR241 (VAR220[5]),
.VAR293 (VAR258[5]),
.VAR302 (VAR278[5]),
.VAR242 (VAR211[5]),
.VAR285 (VAR220[6]),
.VAR176 (VAR258[6]),
.VAR274 (VAR278[6]),
.VAR245 (VAR211[6]),
.VAR194 (VAR220[7]),
.VAR108 (VAR258[7]),
.VAR133 (VAR278[7]),
.VAR262 (VAR211[7]),
.VAR257 (VAR22),
.VAR1 (VAR246),
.VAR251 (VAR200),
.VAR28 (VAR25),
.VAR85 (VAR131),
.VAR221 (VAR256),
.reset (reset),
.clk (clk)
);
VAR154 #(
.VAR171(VAR105), .VAR239(4)
) VAR306
(
.VAR257 (VAR11),
.VAR251 (VAR180),
.VAR28 (VAR264),
.VAR221 (VAR297),
.VAR1 (VAR143),
.VAR85 (VAR110),
.VAR97 (VAR237),
.VAR21 (VAR128),
.VAR67 (VAR106),
.VAR129 (VAR70),
.VAR56 (VAR86),
.VAR279 (VAR90),
.clk (clk),
.reset (reset)
);
VAR154 #(
.VAR171(VAR105 - 2), .VAR239(16)
) VAR203
(
.VAR257 (VAR237[VAR184(1,1)]),
.VAR1 (VAR86[VAR184(1,1)]),
.VAR251 (VAR128[VAR184(1,1)]),
.VAR28 (VAR106[VAR184(1, VAR280)]),
.VAR85 (VAR90[VAR184(1, 32)]),
.VAR221 (VAR70[VAR184(1, 32)]),
.VAR97 (VAR73),
.VAR21 (VAR136),
.VAR67 (VAR60),
.VAR129 (VAR152),
.VAR56 (VAR164),
.VAR279 (VAR115),
.clk (clk),
.reset (reset)
);
generate
for (VAR204 = 0; VAR204 < 4; VAR204 = VAR204 + 1) begin: VAR46
if (!(VAR204 == 1))
VAR78 #(
.VAR153(VAR280)
) VAR193 (
.VAR257 (VAR237[VAR184(VAR204,1)]),
.VAR1 (VAR86[VAR184(VAR204,1)]),
.VAR251 (VAR128[VAR184(VAR204,1)]),
.VAR28 (VAR106[VAR184(VAR204, VAR280)]),
.VAR85 (VAR90[VAR184(VAR204, 32)]),
.VAR221 (VAR70[VAR184(VAR204, 32)]),
.clk (clk),
.reset (reset)
);
end
endgenerate
generate
for (VAR204 = 0; VAR204 < 16; VAR204 = VAR204 + 1) begin: VAR277
if (!(VAR204 >= VAR30 &&
VAR204 < VAR30 + VAR269/2) &&
!(VAR204 >= VAR96 &&
VAR204 < VAR96 + VAR269/2)
)
VAR78 #(
.VAR153(VAR45)
) VAR102 (
.VAR257 (VAR73[VAR184(VAR204,1)]),
.VAR1 (VAR164[VAR184(VAR204,1)]),
.VAR251 (VAR136[VAR184(VAR204,1)]),
.VAR28 (VAR60[VAR184(VAR204, VAR45)]),
.VAR85 (VAR115[VAR184(VAR204, 32)]),
.VAR221 (VAR152[VAR184(VAR204, 32)]),
.clk (clk),
.reset (reset)
);
end
endgenerate
assign VAR19[0] = VAR217;
assign VAR19[1] = VAR157;
assign VAR19[2] = VAR114;
assign VAR19[3] = VAR51;
assign VAR36[0] = VAR192;
assign VAR173[0] = VAR42;
assign VAR52[0] = VAR178;
assign VAR249[0] = VAR188;
assign VAR43 = VAR165[0];
assign VAR7 = VAR254[0];
assign VAR104 = VAR125[0];
assign VAR215 = VAR205[0];
assign VAR276 = VAR5[0];
assign VAR103[0] = VAR24;
assign VAR36[1] = VAR63;
assign VAR173[1] = VAR218;
assign VAR52[1] = VAR29;
assign VAR249[1] = VAR244;
assign VAR139 = VAR165[1];
assign VAR229 = VAR254[1];
assign VAR290 = VAR125[1];
assign VAR9 = VAR205[1];
assign VAR198 = VAR5[1];
assign VAR103[1] = VAR82;
assign VAR36[2] = VAR148;
assign VAR173[2] = VAR89;
assign VAR52[2] = VAR18;
assign VAR249[2] = VAR39;
assign VAR294 = VAR165[2];
assign VAR155 = VAR254[2];
assign VAR14 = VAR125[2];
assign VAR66 = VAR205[2];
assign VAR186 = VAR5[2];
assign VAR103[2] = VAR223;
assign VAR36[3] = VAR238;
assign VAR173[3] = VAR222;
assign VAR52[3] = VAR172;
assign VAR249[3] = VAR216;
assign VAR226 = VAR165[3];
assign VAR147 = VAR254[3];
assign VAR166 = VAR125[3];
assign VAR77 = VAR205[3];
assign VAR219 = VAR5[3];
assign VAR103[3] = VAR71;
assign VAR191[0] = VAR37;
assign VAR191[1] = VAR213;
assign VAR191[2] = VAR50;
assign VAR191[3] = VAR303;
assign VAR33[0] = VAR132;
assign VAR47[0] = VAR8;
assign VAR74[0] = VAR84;
assign VAR109[0] = VAR124;
assign VAR232 = VAR159[0];
assign VAR196 = VAR135[0];
assign VAR116 = VAR296[0];
assign VAR83 = VAR156[0];
assign VAR15 = VAR121[0];
assign VAR247[0] = VAR202;
assign VAR33[1] = VAR230;
assign VAR47[1] = VAR227;
assign VAR74[1] = VAR26;
assign VAR109[1] = VAR267;
assign VAR34 = VAR159[1];
assign VAR101 = VAR135[1];
assign VAR169 = VAR296[1];
assign VAR23 = VAR156[1];
assign VAR94 = VAR121[1];
assign VAR247[1] = VAR160;
assign VAR33[2] = VAR162;
assign VAR47[2] = VAR91;
assign VAR74[2] = VAR210;
assign VAR109[2] = VAR95;
assign VAR65 = VAR159[2];
assign VAR68 = VAR135[2];
assign VAR2 = VAR296[2];
assign VAR16 = VAR156[2];
assign VAR12 = VAR121[2];
assign VAR247[2] = VAR301;
assign VAR33[3] = VAR248;
assign VAR47[3] = VAR100;
assign VAR74[3] = VAR272;
assign VAR109[3] = VAR20;
assign VAR49 = VAR159[3];
assign VAR79 = VAR135[3];
assign VAR299 = VAR296[3];
assign VAR62 = VAR156[3];
assign VAR111 = VAR121[3];
assign VAR247[3] = VAR88;
assign VAR113 = !reset;
assign VAR123 = !reset;
assign VAR263 = !reset;
assign VAR175 = !reset;
assign VAR288 = !reset;
assign VAR212 = !reset;
assign VAR137 = !reset;
assign VAR199 = !reset;
endmodule
|
lgpl-2.1
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.symbol.v
| 1,394 |
module MODULE1 (
input VAR1,
input VAR7,
input VAR8 ,
input VAR6 ,
output VAR9
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.v
| 2,337 |
module MODULE1 (
VAR8 ,
VAR9 ,
VAR1 ,
VAR5,
VAR10 ,
VAR2 ,
VAR7 ,
VAR3
);
output VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR5;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR3 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR8 ,
VAR9 ,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR5;
supply1 VAR10;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR3 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o211a/sky130_fd_sc_hs__o211a.pp.symbol.v
| 1,339 |
module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR6 ,
input VAR1 ,
output VAR3 ,
input VAR5,
input VAR4
);
endmodule
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
| 2,868 |
module MODULE1
,parameter VAR9(VAR37)
,parameter VAR35 = VAR10(VAR37)
)
(input VAR30
,input VAR22
,input VAR34
,input [VAR35-1:0] VAR25
,input [VAR37-1:0][VAR33-1:0] VAR28
,output VAR32
,output VAR8
,output VAR13
,output [VAR33-1:0] VAR26
,input VAR21
);
logic VAR23;
logic [VAR35-1:0] VAR4;
logic [VAR37-1:0][VAR33-1:0] VAR15;
VAR31
) VAR17
(.VAR30 (VAR30 )
,.VAR22(VAR22 )
,.VAR32(VAR32 )
,.VAR28 (VAR25 )
,.VAR34 (VAR34 )
,.VAR8 (VAR8 )
,.VAR26 (VAR4 )
,.VAR21 (VAR23)
);
VAR31
) VAR20
(.VAR30 (VAR30 )
,.VAR22(VAR22 )
,.VAR32( )
,.VAR28 (VAR28 )
,.VAR34 (VAR34 )
,.VAR8 ( )
,.VAR26 (VAR15 )
,.VAR21 (VAR23 )
);
logic [VAR35-1:0] VAR18, VAR11;
logic VAR29, VAR7;
logic VAR1, VAR36;
assign VAR11 = VAR18;
assign VAR1 = (VAR11 == VAR35'(0));
assign VAR36 = (VAR11 == VAR4 );
assign VAR13 = VAR1;
assign VAR7 = VAR21 & ~VAR36;
assign VAR29 = VAR21 & VAR36;
assign VAR23 = VAR29;
VAR6
,.VAR2(0)
) VAR12
(.VAR30 (VAR30 )
,.VAR22 (VAR22 )
,.VAR14 (VAR29)
,.VAR16 (VAR7 )
,.VAR3 (VAR18 )
);
VAR27
,.VAR24 (VAR37 )
) VAR5
(.VAR28 (VAR15)
,.VAR19 (VAR11 )
,.VAR26 (VAR26 )
);
endmodule
|
bsd-3-clause
|
chaohu/Daily-Learning
|
Digital-Logic/lab/lab4/lab4_3/lab4_3_1/lab4_3_1.srcs/sources_1/new/lab4_3_1.v
| 1,387 |
module MODULE1(
input VAR3,clk,
output reg [3:0] VAR1
);
reg [1:0] state,VAR7;
parameter VAR4 = 2'b00,VAR6 = 2'b01,VAR2 = 2'b11,VAR5 = 2'b10;
begin
begin
begin
end
begin
|
mit
|
seyedmaysamlavasani/GorillaPP
|
chisel/Gorilla++/verilogOrig/Top-harness-augmented-k-means.v
| 1,734 |
module MODULE1;
reg clk = 0;
reg reset = 1;
|
bsd-3-clause
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/vfabric_rsqrt.v
| 2,297 |
module MODULE1(VAR5, VAR22,
VAR24, VAR21, VAR12,
VAR4, VAR6, VAR11);
parameter VAR27 = 32;
parameter VAR19 = 11;
parameter VAR26 = 64;
input VAR5, VAR22;
input [VAR27-1:0] VAR24;
input VAR21;
output VAR12;
output [VAR27-1:0] VAR4;
output VAR6;
input VAR11;
reg [VAR19-1:0] VAR25;
wire [VAR27-1:0] VAR7;
wire VAR13;
wire VAR28;
wire VAR18;
VAR17 VAR23 ( .VAR5(VAR5), .VAR22(VAR22),
.VAR7(VAR24), .VAR14(VAR7), .VAR20(VAR21),
.VAR2( VAR13 ), .VAR9(VAR18), .VAR15(VAR12) );
always @(posedge VAR5 or negedge VAR22)
begin
if (~VAR22)
begin
VAR25 <= {VAR19{1'b0}};
end
else
begin
if(~VAR28)
VAR25 <= { VAR13, VAR25[VAR19-1:1] };
end
end
assign VAR28 = (VAR25[0] & VAR11);
assign VAR18 = (VAR25[0] & VAR11) | !(VAR13);
VAR10 VAR3(
.enable(~VAR28), .VAR5(VAR5), .VAR16(VAR7), .VAR8(VAR4));
assign VAR6 = VAR25[0];
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.functional.pp.v
| 1,238 |
module MODULE1 (
VAR2,
VAR1,
VAR3 ,
VAR4
);
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v
| 7,530 |
module MODULE1
parameter VAR10 = 100,
parameter VAR16 = 3
)
(
VAR15, VAR1,
clk, rst, req, VAR4, VAR17, VAR9
);
input clk;
input rst;
input [VAR16-1:0] req;
wire [VAR16-1:0] VAR20;
reg [VAR16*2-1:0] VAR3;
always @(VAR20)
VAR3 = {VAR20, VAR20};
reg [VAR16*2-1:0] VAR19;
always @(req) VAR19 = {req, req};
reg [VAR16-1:0] VAR12 = {VAR16{1'b0}};
genvar VAR8;
genvar VAR11;
generate
for (VAR8 = 0; VAR8 < VAR16; VAR8 = VAR8 + 1) begin : VAR14
wire [VAR16-1:1] VAR7;
for (VAR11 = 0; VAR11 < (VAR16-1); VAR11 = VAR11 + 1) begin : VAR5
assign VAR7[VAR11+1] =
VAR3[VAR8+VAR11] && |VAR19[VAR8+VAR16-1:VAR8+VAR11+1];
end
always @(VAR7) VAR12[VAR8] = |VAR7;
end
endgenerate
input VAR4;
output wire [VAR16-1:0] VAR15;
assign VAR15 = req & ~VAR12 & {VAR16{~VAR4}};
output reg [VAR16-1:0] VAR1;
input [VAR16-1:0] VAR17;
input VAR9;
reg [VAR16-1:0] VAR2;
localparam VAR13 = 1 << (VAR16 - 1); assign VAR20 = rst
? VAR13[0+:VAR16]
: VAR9
? VAR17
: VAR2;
VAR18:
assert property (@(posedge clk) (rst || 0(VAR15)));
VAR6:
assert property (@(posedge clk) (rst || (VAR2)));
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.functional.pp.v
| 2,700 |
module MODULE1 (
VAR5 ,
VAR4 ,
VAR17 ,
VAR1 ,
VAR16 ,
VAR14 ,
VAR3,
VAR24 ,
VAR12 ,
VAR23 ,
VAR25 ,
VAR13
);
output VAR5 ;
input VAR4 ;
input VAR17 ;
input VAR1 ;
input VAR16 ;
input VAR14 ;
input VAR3;
input VAR24 ;
input VAR12 ;
input VAR23 ;
input VAR25 ;
input VAR13 ;
wire VAR20 ;
wire VAR9 ;
wire VAR19 ;
wire VAR10;
not VAR15 (VAR20 , VAR14 );
VAR22 VAR11 (VAR9 , VAR17, VAR1, VAR16 );
VAR21 VAR6 VAR2 (VAR19 , VAR9, VAR4, VAR20, VAR3, , VAR24, VAR23, VAR12);
VAR8 VAR18 (VAR10, VAR19, VAR12, VAR23 );
buf VAR7 (VAR5 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/dlxtp/sky130_fd_sc_hvl__dlxtp.functional.v
| 1,532 |
module MODULE1 (
VAR7 ,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR8;
wire VAR3;
VAR2 VAR5 VAR6 (VAR3 , VAR4, VAR8 );
buf VAR1 (VAR7 , VAR3 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.behavioral.v
| 1,873 |
module MODULE1 (
VAR7 ,
VAR2 ,
VAR10
);
output VAR7 ;
input VAR2 ;
input VAR10;
supply1 VAR1;
supply0 VAR14;
supply1 VAR9 ;
supply0 VAR12 ;
wire VAR5 ;
reg VAR6 ;
wire VAR8;
wire VAR3 ;
VAR13 VAR11 (VAR5 , VAR3, VAR8, VAR6, VAR1, VAR14);
buf VAR4 (VAR7 , VAR5 );
endmodule
|
apache-2.0
|
onchipuis/mriscv_vivado
|
mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v
| 8,727 |
module MODULE1 #
(
parameter VAR17 = 100,
parameter VAR13 = 3636,
parameter VAR3 = 3,
parameter VAR14 = 3,
parameter VAR10 = "VAR1"
)
(
input clk,
input rst,
input VAR6,
output reg [VAR14-1:0] VAR27,
output reg VAR2,
output reg VAR21,
output reg VAR25,
output reg VAR30,
output VAR29
);
localparam VAR11 = 63;
localparam VAR19 = (VAR13 > 5000 ? 4 :
VAR13 > 2500 ? 2 : 1);
localparam integer VAR24 = ((VAR13/2)/64);
localparam VAR28 = (VAR13 >= 1250) ? 350 : 300;
localparam VAR9 = 0;
localparam VAR18 = (VAR10 == "VAR20") ? 0 : 29;
reg VAR4;
reg VAR15;
reg VAR8;
reg VAR22;
reg VAR5 ;
reg [5:0] VAR16;
reg [5:0] VAR12;
reg VAR26;
reg VAR7;
reg [3:0] VAR23;
assign VAR29 = ((VAR9 == 0) && (VAR18 == 0)) ? 1'b1 : VAR5;
always @(posedge clk) begin
if (rst || VAR7 || VAR26)
end
else if (VAR6 && (VAR23 > 'd0))
end
always @(posedge clk) begin
if (rst || (VAR12 > 6'd0) || (VAR16 == 'd0) || (VAR18 == 0))
end
else if ((VAR16 > 'd0) && (VAR23 == 'd1))
else
end
always @(posedge clk) begin
if (rst || (VAR12 == 'd0))
end
else if (VAR6 && (VAR12 > 'd0) && (VAR23 == 'd1))
else
end
always @(posedge clk) begin
if (rst) begin
end else begin
if (VAR7) begin
end else begin
end
if (VAR26) begin
end else begin
end
end
end
always @(posedge clk) begin
if (rst || (VAR13 >= 2500) || (VAR10 == "VAR20"))
end
else if ((VAR12 > 6'd0) ||((VAR16 == 6'd0) && (VAR27 != VAR14-1)))
end
else if (VAR26 && (VAR16 > 6'd0))
end
always @(posedge clk) begin
if (rst || ~VAR6 ||((VAR12 == 6'd0) && (VAR16 == 6'd0) && (VAR27 != VAR14-1)))
end
else if (VAR7 && (VAR12 > 6'd0))
end
always @(posedge clk) begin
if (rst || ~VAR6 )
end
else if (~VAR4 && (VAR27 == VAR14-1) && (VAR12 == 6'd1))
else if ((VAR27 != VAR14-1) && (VAR12 == 6'd0) && (VAR16 == 'd0))
end
always @(posedge clk) begin
if (rst || ~VAR6) begin
end else if (((VAR9 == 0) && (VAR18 == 0)) ||
((VAR12 == 6'd0) && (VAR16 == 'd0) && (VAR27 == VAR14-1))) begin
end
end
always @(posedge clk) begin
end
endmodule
|
mit
|
svenstaro/uni-projekt
|
verilog/c25Board.v
| 2,272 |
module MODULE1 (
clk, reset, VAR16, VAR8, VAR39, VAR58, VAR51, VAR41, VAR46, VAR7, VAR10, VAR30, VAR45, VAR4, VAR14, VAR1, VAR60, VAR31, VAR9, VAR55, VAR36,
);
input clk;
input VAR33;
input [3:0] VAR16;
output [3:0] VAR8;
wire [3:0] VAR8;
input VAR39;
output VAR58;
wire VAR58;
wire VAR25;
wire [15:0] VAR35;
wire [31:0] VAR12;
wire [31:0] VAR54;
wire VAR48;
wire VAR15;
wire VAR6;
wire [31:0] VAR32;
wire [31:0] VAR24;
assign VAR12 = VAR48 ? VAR32 : 'VAR38;
assign VAR12 = VAR15 ? VAR24 : 'VAR38;
wire [7:0] VAR52;
wire [7:0] VAR44;
wire VAR22;
wire VAR2;
wire VAR57;
VAR27 VAR49 (
.clk(clk),
.reset(VAR33),
.VAR16(VAR16),
.VAR8(VAR8),
.VAR39(VAR39),
.VAR58(VAR58),
.VAR35(VAR35),
.VAR3(VAR12),
.VAR40(VAR54),
.VAR48(VAR48),
.VAR15(VAR15),
.VAR6(VAR6),
.VAR52(VAR52),
.VAR22(VAR22),
.VAR2(VAR2),
.VAR57(VAR57),
.VAR43(1'b0),
.VAR44(VAR44)
);
VAR18 VAR56 (
.address(VAR35[9:0]),
.VAR19(4'h1),
.VAR29(clk),
.VAR26(VAR54),
.VAR34(VAR15),
.VAR28(VAR6),
.VAR50(VAR24)
);
VAR42 VAR17 (
.address(VAR35[7:0]),
.VAR29(clk),
.VAR34(VAR48),
.VAR50(VAR32)
);
VAR53 VAR11 (
.VAR29(clk),
.VAR26(VAR52),
.VAR21(VAR22),
.VAR47(VAR2),
.VAR20(VAR57),
.VAR50(VAR44)
);
VAR23 VAR37 (
.VAR5(reset),
.VAR59(clk),
.VAR13(VAR25)
);
endmodule
|
gpl-3.0
|
webmaster442/prog-elektonikak
|
Kodok/Verilog/03-1.v
| 1,211 |
module MODULE1(VAR2, VAR3, select);
output VAR2;
input [31:0] VAR3;
input [5:0] select;
wire VAR2;
wire [31:0] VAR3;
wire [5:0] select;
assign VAR2 =
(select == 5'h00) ? VAR3[0] :
(select == 5'h01) ? VAR3[1] :
(select == 5'h02) ? VAR3[2] :
(select == 5'h03) ? VAR3[3] :
(select == 5'h04) ? VAR3[4] :
(select == 5'h05) ? VAR3[5] :
(select == 5'h06) ? VAR3[6] :
(select == 5'h07) ? VAR3[7] :
(select == 5'h08) ? VAR3[8] :
(select == 5'h09) ? VAR3[9] :
(select == 5'h0A) ? VAR3[10] :
(select == 5'h0B) ? VAR3[11] :
(select == 5'h0C) ? VAR3[12] :
(select == 5'h0D) ? VAR3[13] :
(select == 5'h0E) ? VAR3[14] :
(select == 5'h0F) ? VAR3[15] :
(select == 5'h10) ? VAR3[16] :
(select == 5'h11) ? VAR3[17] :
(select == 5'h12) ? VAR3[18] :
(select == 5'h13) ? VAR3[19] :
(select == 5'h14) ? VAR3[20] :
(select == 5'h15) ? VAR3[21] :
(select == 5'h16) ? VAR3[22] :
(select == 5'h17) ? VAR3[23] :
(select == 5'h18) ? VAR3[24] :
(select == 5'h19) ? VAR3[25] :
(select == 5'h1A) ? VAR3[26] :
(select == 5'h1B) ? VAR3[27] :
(select == 5'h1C) ? VAR3[28] :
(select == 5'h1D) ? VAR3[29] :
(select == 5'h1E) ? VAR3[30] :
(select == 5'h1F) ? VAR3[31] : 1'VAR1;
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor4b/sky130_fd_sc_hdll__nor4b_2.v
| 2,318 |
module MODULE1 (
VAR7 ,
VAR10 ,
VAR5 ,
VAR11 ,
VAR2 ,
VAR3,
VAR9,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR3;
input VAR9;
input VAR4 ;
input VAR6 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7 ,
VAR10 ,
VAR5 ,
VAR11 ,
VAR2
);
output VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR11 ;
input VAR2;
supply1 VAR3;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR6 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.behavioral.v
| 2,879 |
module MODULE1 (
VAR23,
VAR12 ,
VAR31 ,
VAR13 ,
VAR25 ,
VAR20 ,
VAR19 ,
VAR14
);
input VAR23;
input VAR12 ;
input VAR31 ;
output VAR13 ;
input VAR25 ;
input VAR20 ;
input VAR19 ;
input VAR14 ;
wire VAR6 ;
wire VAR18 ;
wire VAR11 ;
wire VAR2 ;
reg VAR15 ;
wire VAR26 ;
wire VAR7 ;
wire VAR5 ;
wire VAR21;
wire VAR30 ;
wire VAR17 ;
wire VAR1 ;
wire VAR9 ;
wire VAR27 ;
wire VAR29 ;
wire VAR24 ;
not VAR3 (VAR18 , VAR21 );
not VAR28 (VAR11 , VAR30 );
VAR8 VAR4 (VAR2, VAR26, VAR7, VAR5 );
VAR10 VAR16 (VAR6 , VAR2, VAR11, VAR18, VAR15, VAR19, VAR14);
assign VAR17 = ( VAR19 === 1'b1 );
assign VAR1 = ( VAR17 && ( VAR21 === 1'b1 ) );
assign VAR9 = ( ( VAR5 === 1'b0 ) && VAR1 );
assign VAR27 = ( ( VAR5 === 1'b1 ) && VAR1 );
assign VAR29 = ( ( VAR26 !== VAR7 ) && VAR1 );
assign VAR24 = ( VAR17 && ( VAR23 === 1'b1 ) );
buf VAR22 (VAR13 , VAR6 );
endmodule
|
apache-2.0
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/acl_fp_custom_normalize.v
| 4,186 |
module MODULE1(
VAR14, VAR15,
VAR22, VAR27, VAR6,
VAR1, VAR5, VAR16, VAR19,
enable, VAR12);
parameter VAR25 = 1;
parameter VAR8 = 0;
parameter VAR23 = 1;
parameter VAR11 = 0;
input VAR14, VAR15;
input VAR1, VAR5;
output VAR16, VAR19;
input enable;
input [27:0] VAR22;
input [8:0] VAR27; input VAR6;
output [31:0] VAR12;
wire [26:0] VAR17;
wire [8:0] VAR28;
wire VAR26, VAR9, VAR18;
VAR10 VAR21(
.VAR14(VAR14),
.VAR15(VAR15),
.VAR22(VAR22),
.VAR27(VAR27),
.VAR6(VAR6),
.VAR1(VAR18),
.VAR5(VAR5),
.VAR16(VAR16),
.VAR19(VAR9),
.enable(enable),
.VAR17(VAR17),
.VAR28(VAR28),
.VAR26(VAR26));
wire [26:0] VAR7;
wire [8:0] VAR13;
wire VAR3,VAR4, VAR20;
VAR2 VAR24(
.VAR14(VAR14),
.VAR15(VAR15),
.VAR22(VAR17),
.VAR27(VAR28),
.VAR6(VAR26),
.VAR17(VAR7),
.VAR28(VAR13),
.VAR26(VAR3),
.VAR5(VAR9),
.VAR19(VAR19),
.VAR1(VAR1),
.VAR16(VAR18),
.enable(enable));
assign VAR12 = {VAR3, VAR13[7:0], VAR7[25:3] };
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/inv/sky130_fd_sc_hs__inv_1.v
| 1,868 |
module MODULE1 (
VAR4 ,
VAR6 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR6 ;
input VAR5;
input VAR3;
VAR2 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR5;
supply0 VAR3;
VAR2 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.behavioral.v
| 2,113 |
module MODULE1( VAR10, VAR3, VAR8 );
input VAR10, VAR3;
output VAR8;
reg VAR6;
VAR11 VAR1(.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR6(VAR6));
VAR11 VAR9(.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR6(VAR6));
not VAR4(VAR5,VAR3);
buf VAR2(VAR7,VAR3);
|
apache-2.0
|
hsnuonly/PikachuVolleyFPGA
|
VGA.srcs/sources_1/ip/ball_small/ball_small_stub.v
| 1,295 |
module MODULE1(VAR4, VAR3, VAR5, VAR1, VAR2)
;
input VAR4;
input [0:0]VAR3;
input [9:0]VAR5;
input [11:0]VAR1;
output [11:0]VAR2;
endmodule
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rotate.v
| 3,076 |
module MODULE1
parameter VAR8 = "VAR1",
parameter VAR4 = 4
)
(
input [VAR4-1:0] VAR9,
input [VAR2(VAR4)-1:0] VAR11,
output [VAR4-1:0] VAR7
);
wire [2*VAR4-1:0] VAR5;
wire [2*VAR4-1:0] VAR3;
wire [2*VAR4-1:0] VAR10;
wire [2*VAR4-1:0] VAR6;
assign VAR3 = {VAR9,VAR9};
assign VAR5 = {VAR9,VAR9};
assign VAR6 = VAR3 << VAR11;
assign VAR10 = VAR5 >> VAR11;
generate
if(VAR8 == "VAR1") begin
assign VAR7 = VAR6[2*VAR4-1:VAR4];
end else if (VAR8 == "VAR12") begin
assign VAR7 = VAR10[VAR4-1:0];
end
endgenerate
endmodule
|
gpl-3.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO_EP.v
| 10,482 |
module MODULE1 (
clk,
VAR77,
VAR72,
VAR57,
VAR69,
VAR28,
VAR4,
VAR76,
VAR6,
VAR12,
VAR79,
VAR34,
VAR14,
VAR37,
VAR46,
VAR33,
VAR22,
VAR53,
VAR48,
VAR9
);
input clk;
input VAR77;
output [63:0] VAR72;
output [7:0] VAR57;
output [127:0] VAR72;
output [1:0] VAR57;
output VAR69;
output VAR28;
output VAR4;
input VAR76;
input VAR6;
input [63:0] VAR12;
input [7:0] VAR79;
input [127:0] VAR12;
input [1:0] VAR79;
input [31:0] VAR12;
input VAR34;
input VAR14;
input [6:0] VAR46;
input VAR37;
output VAR33;
output VAR22;
output VAR53;
input [15:0] VAR48;
input VAR9;
wire [10:0] VAR15;
wire [3:0] VAR5;
wire [31:0] VAR16;
wire [10:0] VAR3;
wire [7:0] VAR20;
wire [31:0] VAR73;
wire VAR40;
wire VAR17;
wire VAR67;
wire VAR59;
wire [2:0] VAR39;
wire VAR29;
wire VAR10;
wire [1:0] VAR41;
wire [9:0] VAR64;
wire [15:0] VAR1;
wire [7:0] VAR51;
wire [7:0] VAR60;
wire [12:0] VAR2;
VAR65 VAR74 (
.clk(clk), .VAR77(VAR77),
.VAR75(VAR15), .VAR52(VAR5), .VAR30(VAR16),
.VAR36(VAR3), .VAR54(VAR20), .VAR50(VAR73), .VAR32(VAR40), .VAR63(VAR17)
);
.clk(clk), .VAR77(VAR77),
.VAR12(VAR12), VAR66 VAR70
.VAR79(VAR79), VAR55 .VAR21(VAR21), .VAR34(VAR34), .VAR14(VAR14), .VAR37(VAR37), .VAR46(VAR46), .VAR33(VAR33),
.VAR22(VAR67), .VAR43(VAR59),
.VAR23(VAR39), .VAR82(VAR29), .VAR35(VAR10), .VAR71(VAR41), .VAR44(VAR64), .VAR61(VAR1), .VAR7(VAR51), .VAR49(VAR60), .VAR45(VAR2),
.VAR58(VAR3), .VAR8(VAR20), .VAR38(VAR73), .VAR25(VAR40), .VAR83(VAR17)
);
.clk(clk), .VAR77(VAR77),
.VAR72(VAR72), VAR66 VAR70
.VAR57(VAR57), VAR55 .VAR80(VAR80), .VAR69(VAR69), .VAR28(VAR28), .VAR4(VAR4), .VAR76(VAR76), .VAR6(VAR6),
.VAR11(VAR67), .VAR53(VAR59),
.VAR27(VAR39), .VAR68(VAR29), .VAR56(VAR10), .VAR47(VAR41), .VAR78(VAR64), .VAR62(VAR1), .VAR24(VAR51), .VAR18(VAR60), .VAR26(VAR2),
.VAR13(VAR15), .VAR31(VAR5), .VAR42(VAR16),
.VAR81(VAR48), .VAR19(VAR9)
);
assign VAR22 = VAR67;
assign VAR53 = VAR59;
endmodule
|
lgpl-3.0
|
bangonkali/sram
|
i2c_slave.v
| 2,564 |
module MODULE1 (
VAR13,
VAR12,
VAR14,
VAR4,
VAR18,
state,
VAR7
);
inout VAR13;
input VAR12;
wire VAR11;
reg VAR9;
reg VAR16;
input [6:0] VAR14;
output reg [6:0] VAR18;
reg [7:0] VAR15;
output reg VAR7;
reg [2:0] counter;
output reg [2:0] state;
output reg [7:0] VAR4;
assign VAR11 = VAR13;
assign VAR13 = VAR9 ? VAR16: 1'VAR1;
parameter VAR6 = 3'h0;
parameter VAR2 = 3'h1;
parameter VAR19 = 3'h3;
parameter VAR10 = 3'h7;
parameter VAR3 = 3'h6;
parameter VAR5 = 3'h5;
parameter VAR8 = 3'h4;
parameter VAR17 = 3'h2;
|
mit
|
mindrobots/P8X32A_Emulation
|
P8X32A_BeMicroCV/hub.v
| 7,955 |
module MODULE1
(
input VAR6,
input VAR43,
input VAR14,
input [7:0] VAR3,
input VAR50,
input VAR13,
input VAR17,
input [1:0] VAR16,
input [15:0] VAR12,
input [31:0] VAR7,
output reg [31:0] VAR22,
output VAR41,
output [7:0] VAR46,
output reg [7:0] VAR25,
output [7:0] VAR1,
output [27:0] VAR34,
output reg [7:0] VAR23
);
reg VAR20;
reg VAR21;
reg VAR49;
reg [1:0] VAR19;
reg [15:0] VAR11;
reg [31:0] VAR38;
always @(posedge VAR6)
if (VAR43)
VAR20 <= VAR50;
always @(posedge VAR6 or negedge VAR14)
if (!VAR14)
VAR21 <= 1'b0;
else if (VAR43)
VAR21 <= VAR13;
always @(posedge VAR6)
if (VAR43)
VAR49 <= VAR17;
always @(posedge VAR6)
if (VAR43)
VAR19 <= VAR16;
always @(posedge VAR6)
if (VAR43)
VAR11 <= VAR12;
always @(posedge VAR6)
if (VAR43)
VAR38 <= VAR7;
wire VAR33 = VAR21 && ~&VAR19 && VAR49;
wire [3:0] VAR35 = VAR19[1] ? 4'b1111 : VAR19[0] ? VAR11[1] ? 4'b1100 : 4'b0011 : 4'b0001 << VAR11[1:0];
wire [31:0] VAR2 = VAR19[1] ? VAR38 : VAR19[0] ? {2{VAR38[15:0]}} : {4{VAR38[7:0]}};
wire [31:0] VAR18;
VAR31 VAR31 ( .VAR6 (VAR6),
.VAR43 (VAR43),
.VAR29 (VAR33),
.VAR10 (VAR35),
.VAR36 (VAR11[15:2]),
.VAR45 (VAR2),
.VAR47 (VAR18) );
reg rd;
reg VAR39;
reg [1:0] VAR4;
reg [1:0] VAR15;
always @(posedge VAR6)
if (VAR43)
rd <= !VAR20 && VAR11[15];
always @(posedge VAR6 or negedge VAR14)
if (!VAR14)
VAR39 <= 1'b0;
else if (VAR43)
VAR39 <= VAR21;
always @(posedge VAR6)
if (VAR43)
VAR4 <= VAR19;
always @(posedge VAR6)
if (VAR43)
VAR15 <= VAR11[1:0];
wire [31:0] VAR9 = !rd ? VAR18 : {VAR18[03], VAR18[07], VAR18[21], VAR18[12], VAR18[06], VAR18[19], VAR18[04], VAR18[17],
VAR18[20], VAR18[15], VAR18[08], VAR18[11],
VAR18[00], VAR18[14], VAR18[30], VAR18[01],
VAR18[23], VAR18[31], VAR18[16], VAR18[05],
VAR18[09], VAR18[18], VAR18[25], VAR18[02],
VAR18[28], VAR18[22], VAR18[13], VAR18[27],
VAR18[29], VAR18[24], VAR18[26], VAR18[10]};
always @(posedge VAR6)
VAR22 <= VAR4[1] ? VAR4[0] ? {29'b0, VAR28} : VAR9 : VAR4[0] ? VAR9 >> {VAR15[1], 4'b0} & 32'h0000FFFF : VAR9 >> {VAR15[1:0], 3'b0} & 32'h000000FF;
assign VAR41 = VAR26;
assign VAR46 = VAR39 ? {VAR3[1:0], VAR3[7:2]} : 8'b0;
wire VAR32 = VAR21 && (&VAR19);
wire [7:0] VAR44 = VAR11[2] ? VAR24 : VAR40;
wire VAR8 = &VAR44;
wire [2:0] VAR27 = &VAR44[3:0] ? &VAR44[5:4] ? VAR44[6] ? 3'b111 : 3'b110 : VAR44[4] ? 3'b101 : 3'b100 : &VAR44[1:0] ? VAR44[2] ? 3'b011 : 3'b010 : VAR44[0] ? 3'b001 : 3'b000;
wire [2:0] VAR42 = VAR11[2:0] == 3'b010 && VAR38[3] || VAR11[2:0] == 3'b100 ? VAR27 : VAR38[2:0];
wire [7:0] VAR30 = 1'b1 << VAR42;
always @(posedge VAR6 or negedge VAR14)
if (!VAR14)
VAR23 <= 8'b0;
else if (VAR43 && VAR32 && VAR11[2:0] == 3'b000)
VAR23 <= VAR38[7:0];
reg [7:0] VAR40;
wire VAR37 = VAR32 && VAR11[2:0] == 3'b010 && !(VAR38[3] && VAR8);
always @(posedge VAR6 or negedge VAR14)
if (!VAR14)
VAR40 <= 8'b00000001;
else if (VAR43 && VAR32 && VAR11[2:1] == 2'b01)
VAR40 <= VAR40 & ~VAR30 | {8{!VAR11[0]}} & VAR30;
always @(posedge VAR6 or negedge VAR14)
if (!VAR14)
VAR25 <= 8'b0;
else if (VAR43)
VAR25 <= VAR40 & ~({8{VAR37}} & VAR30);
assign VAR1 = {8{VAR37}} & VAR30;
assign VAR34 = VAR38[31:4];
reg [7:0] VAR24;
reg [7:0] VAR5;
always @(posedge VAR6 or negedge VAR14)
if (!VAR14)
VAR24 <= 8'b0;
else if (VAR43 && VAR32 && VAR11[2:1] == 2'b10)
VAR24 <= VAR24 & ~VAR30 | {8{!VAR11[0]}} & VAR30;
always @(posedge VAR6)
if (VAR43 && VAR32 && VAR11[2:1] == 2'b11)
VAR5 <= VAR5 & ~VAR30 | {8{!VAR11[0]}} & VAR30;
wire VAR48 = VAR5[VAR38[2:0]];
reg [2:0] VAR28;
reg VAR26;
always @(posedge VAR6)
if (VAR43 && VAR32)
VAR28 <= VAR11[2:0] == 3'b001 ? { VAR3[7] || VAR3[6] || VAR3[5] || VAR3[0], VAR3[7] || VAR3[4] || VAR3[3] || VAR3[0],
VAR3[6] || VAR3[4] || VAR3[2] || VAR3[0] }
: VAR42;
always @(posedge VAR6)
if (VAR43 && VAR32)
VAR26 <= VAR11[2:1] == 2'b11 ? VAR48 : VAR8;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/and4/sky130_fd_sc_ms__and4.functional.pp.v
| 1,837 |
module MODULE1 (
VAR11 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR15 ,
VAR10,
VAR6,
VAR5 ,
VAR1
);
output VAR11 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR15 ;
input VAR10;
input VAR6;
input VAR5 ;
input VAR1 ;
wire VAR9 ;
wire VAR4;
and VAR12 (VAR9 , VAR3, VAR2, VAR7, VAR15 );
VAR14 VAR8 (VAR4, VAR9, VAR10, VAR6);
buf VAR13 (VAR11 , VAR4 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.pp.symbol.v
| 1,518 |
module MODULE1 (
input VAR9 ,
output VAR3 ,
output VAR11 ,
input VAR6 ,
input VAR10 ,
input VAR8 ,
input VAR7 ,
input VAR4 ,
input VAR1,
input VAR5,
input VAR2
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_8.behavioral.pp.v
| 1,069 |
module MODULE1( VAR1, VAR4 );
inout VAR1, VAR4;
VAR2 VAR5(.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR3(.VAR1(VAR1),.VAR4(VAR4));
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/afifo.v
| 6,341 |
module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR16 = 32,
parameter VAR9 = 16,
parameter VAR7 = 4,
parameter VAR4 = 1 )
(
input VAR33,
input rst,
input VAR35,
input [VAR16-1:0] VAR11,
input VAR22,
input VAR17,
output [VAR16-1:0] VAR26,
output reg VAR31,
output reg VAR28,
output reg VAR38
);
reg [VAR16-1:0] VAR3 [0:VAR9-1];
reg [VAR7:0] VAR29;
reg [VAR7:0] VAR13;
reg [VAR7:0] VAR30;
reg [VAR7:0] VAR2;
reg [VAR7:0] VAR34;
reg [VAR7:0] VAR10;
wire [VAR7:0] VAR20;
wire [VAR7:0] VAR32;
wire [VAR7-1:0] VAR24, VAR5;
reg [VAR7:0] VAR36, VAR12,VAR8;
integer VAR25,VAR27,VAR1;
generate
if (VAR4 == 1) begin: VAR19
always @ (VAR12)
VAR29 = VAR12;
end
endgenerate
generate
if (VAR4 == 1) begin: VAR18
always @ (VAR36)
VAR2 = VAR36;
end
endgenerate
assign VAR24 = VAR36[VAR7-1:0];
assign VAR26 = VAR3[VAR5];
always @(posedge VAR33)
begin
if (VAR35 && !VAR31)
end
assign VAR5 = VAR8[VAR7-1:0];
assign VAR6 = VAR22 && !VAR28;
integer VAR21;
always @(posedge VAR17)
begin
if (rst)
begin
end
else begin
if (VAR6) begin
end
end
end
assign VAR32 = VAR2 - VAR12;
always @ (posedge VAR17 )
begin
if (rst)
end
else if ((VAR32 == 0) || (VAR32 == 1 && VAR6))
else
end
reg [VAR7:0] VAR15;
wire [VAR7:0] VAR14, VAR37;
always @(posedge VAR17)
begin
if (rst)
begin
end
else begin
if (VAR35)
end
end
assign VAR20 = (VAR29 + 5'd16) - VAR36;
always @ (posedge VAR33 )
begin
if (rst)
end
else if ((VAR20 == 0) || (VAR20 == 1 && VAR35))
else
end
always @ (posedge VAR33 )
begin
if (rst)
end
else if ((VAR20 == VAR9 - 2 ) || ((VAR20 == VAR9 -3) && VAR35))
else
end
endmodule
|
lgpl-3.0
|
joseluisquiroga/bj-actor-model
|
hlang/hgen_net/vlg_fnd/pakout.v
| 1,685 |
module MODULE1
VAR32=VAR7,
VAR15=VAR1,
VAR18=VAR24,
VAR5=VAR9,
VAR29=VAR2
)(
);
parameter VAR22 = VAR12;
parameter VAR25 = VAR27;
localparam VAR34 = ((VAR3 / VAR32) + 1);
localparam VAR28 = (((VAR8(VAR15)-1) >= 0)?(VAR8(VAR15)-1):(0));
localparam VAR31 = (((VAR8(VAR34)-1) >= 0)?(VAR8(VAR34)-1):(0));
reg [0:0] VAR4 = VAR20;
reg [0:0] VAR10 = VAR20;
reg [0:0] VAR26 = VAR20;
reg [0:0] VAR14 = VAR20;
always @(posedge VAR21)
begin
if(VAR33) begin
VAR4 <= VAR20;
end
if(! VAR33 && ! VAR4) begin
VAR4 <= ! VAR4;
VAR10 <= VAR20;
VAR26 <= VAR20;
VAR14 <= VAR20;
end
if(! VAR33 && VAR4) begin
if(VAR16 && (! VAR26)) begin
end
if((! VAR16) && VAR26) begin
VAR26 <= VAR20;
end
end
end
assign VAR17 = VAR4 && VAR30 && VAR23;
assign VAR6 = VAR19;
assign VAR13 = VAR10;
assign VAR11 = VAR26;
endmodule
|
gpl-3.0
|
hpeng2/ECE492_Group4_Project
|
ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_AV_Config.v
| 15,606 |
module MODULE1 (
clk,
reset,
address,
VAR12,
read,
write,
VAR46,
VAR15,
VAR17,
VAR74,
irq,
VAR30,
VAR1
);
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] VAR12;
input read;
input write;
input [31: 0] VAR46;
inout VAR15;
output reg [31: 0] VAR17;
output VAR74;
output irq;
output VAR30;
output VAR1;
localparam VAR64 = 26;
localparam VAR13 = 8'h02;
localparam VAR26 = {8'h00, 1'b1, 8'hFF, 1'b0, 8'h00, 1'b1};
localparam VAR70 = {8'h00, 1'b1, 8'h00, 1'b1, 8'h00, 1'b1};
localparam VAR65 = 'h9;
localparam VAR10 = 50; localparam VAR25 = 5;
localparam VAR68 = 9'h01A;
localparam VAR67 = 9'h01A;
localparam VAR8 = 9'h07B;
localparam VAR22 = 9'h07B;
localparam VAR47 = 9'd149;
localparam VAR40 = 9'h006;
localparam VAR32 = 9'h000;
localparam VAR31 = 9'd73;
localparam VAR66 = 9'd0;
localparam VAR3 = 9'h001;
localparam VAR36 = 4; localparam VAR37 = 11;
localparam VAR49 = 3'h0,
VAR60 = 3'h1,
VAR16 = 3'h2,
VAR71 = 3'h3,
VAR55 = 3'h4,
VAR29 = 3'h5,
VAR63 = 3'h6;
wire VAR44;
wire [VAR25:0] VAR7;
wire [VAR64: 0] VAR4;
wire ack;
wire [VAR64: 0] VAR58;
wire VAR33;
wire VAR57;
wire VAR34;
wire [VAR64: 0] VAR28;
wire [VAR64: 0] VAR61;
wire [VAR64: 0] VAR38;
wire [VAR64: 0] VAR41;
wire VAR21;
wire VAR56;
reg [31: 0] VAR42;
reg [31: 0] VAR69;
reg [31: 0] VAR75;
reg VAR18;
reg VAR48;
reg [ 7: 0] VAR20;
reg [ 1: 0] VAR51;
reg [ 2: 0] VAR76;
reg [ 2: 0] VAR35;
always @(posedge clk)
begin
if (VAR44)
VAR35 <= VAR49;
end
else
VAR35 <= VAR76;
end
always @(*)
begin
VAR76 = VAR49;
case (VAR35)
VAR49:
begin
if (VAR56 | ~VAR57)
VAR76 = VAR49;
end
else if (write & (address == 2'h3))
VAR76 = VAR60;
end
else if (read & (address == 2'h3))
begin
if (VAR42[17:16] == 2'h0)
VAR76 = VAR63;
end
else
VAR76 = VAR55;
end
else
VAR76 = VAR49;
end
VAR60:
begin
VAR76 = VAR16;
end
VAR16:
begin
if (VAR56)
VAR76 = VAR71;
end
else
VAR76 = VAR16;
end
VAR71:
begin
VAR76 = VAR49;
end
VAR55:
begin
VAR76 = VAR29;
end
VAR29:
begin
if (VAR56)
VAR76 = VAR63;
end
else
VAR76 = VAR29;
end
VAR63:
begin
VAR76 = VAR49;
end
default:
begin
VAR76 = VAR49;
end
endcase
end
always @(posedge clk)
begin
if (VAR44)
VAR17 <= 32'h00000000;
end
else if (read)
begin
if (address == 2'h0)
VAR17 <= VAR42;
end
else if (address == 2'h1)
begin
VAR17 <= {8'h00, VAR13, 7'h00,
VAR57 & ~VAR34, 6'h00,
~VAR18 & VAR57,
ack};
end
else if (address == 2'h2)
VAR17 <= VAR69;
else if (VAR42[17:16] == 2'h0)
VAR17 <= {23'h000000,
VAR41[10],
VAR41[ 8: 1]};
else
VAR17 <= {24'h000000, VAR41[ 8: 1]};
end
end
always @(posedge clk)
begin
if (VAR44)
begin
VAR42 <= 32'h00000000;
VAR69 <= 32'h00000000;
VAR75 <= 32'h00000000;
end
else if (write & ~VAR74)
begin
if ((address == 2'h0) & VAR12[0])
VAR42[ 2: 1] <= VAR46[ 2: 1];
if ((address == 2'h0) & VAR12[2])
VAR42[17:16] <= VAR46[17:16];
if ((address == 2'h2) & VAR12[0])
VAR69[ 7: 0] <= VAR46[ 7: 0];
if ((address == 2'h3) & VAR12[0])
VAR75[ 7: 0] <= VAR46[ 7: 0];
if ((address == 2'h3) & VAR12[1])
VAR75[15: 8] <= VAR46[15: 8];
if ((address == 2'h3) & VAR12[2])
VAR75[23:16] <= VAR46[23:16];
if ((address == 2'h3) & VAR12[3])
VAR75[31:24] <= VAR46[31:24];
end
end
always @(posedge clk)
begin
if (VAR44)
begin
VAR18 <= 1'b0;
VAR48 <= 1'b0;
VAR20 <= 8'h00;
VAR51 <= 2'h0;
end
else if (VAR56)
begin
VAR18 <= 1'b0;
VAR48 <= 1'b0;
VAR20 <= 8'h00;
end
else if (VAR35 == VAR60)
begin
VAR18 <= 1'b1;
VAR48 <= 1'b0;
VAR20 <= VAR69[7:0];
VAR51 <= VAR42[17:16];
end
else if (VAR35 == VAR55)
begin
VAR18 <= 1'b1;
VAR48 <= 1'b1;
VAR20 <= VAR69[7:0];
VAR51 <= VAR42[17:16];
end
end
assign VAR74 =
((address == 2'h3) & write & (VAR35 != VAR60)) |
((address == 2'h3) & read & (VAR35 != VAR63));
assign irq = VAR42[1] & ~VAR18 & VAR57;
assign VAR44 = reset |
((address == 2'h0) & write & VAR12[0] & VAR46[0]);
assign VAR28 = VAR70;
assign VAR61 =
(~VAR57) ?
VAR58 :
(VAR51 == 2'h0) ?
{8'h34, 1'b0,
VAR20[6:0], VAR75[8], 1'b0,
VAR75[7:0], 1'b0} :
(VAR51 == 2'h1) ?
{8'h40, 1'b0,
VAR20[7:0], VAR48,
VAR75[7:0], 1'b0} :
{8'h42, 1'b0,
VAR20[7:0], VAR48,
VAR75[7:0], 1'b0};
assign VAR38 =
(VAR51 == 2'h1) ?
{8'h41, 1'b0, 8'h00, 1'b0, 8'h00, ack} :
{8'h43, 1'b0, 8'h00, 1'b0, 8'h00, ack};
assign VAR21 = (VAR57) ?
VAR18 :
VAR33;
assign ack = VAR41[18] |
VAR41[ 9] |
VAR41[ 0];
VAR62 VAR9 (
.clk (clk),
.reset (VAR44),
.VAR53 (1'b0),
.ack (ack),
.VAR56 (VAR56),
.VAR4 (VAR4),
.VAR11 (VAR58),
.VAR43 (VAR33),
.VAR7 (VAR7),
.VAR57 (VAR57),
.VAR34 (VAR34)
);
VAR9.VAR23 = VAR10,
VAR9.VAR5 = VAR25,
VAR9.VAR64 = VAR64;
VAR19 VAR59 (
.VAR7 (VAR7),
.VAR4 (VAR4)
);
VAR59.VAR68 = VAR68,
VAR59.VAR67 = VAR67,
VAR59.VAR8 = VAR8,
VAR59.VAR22 = VAR22,
VAR59.VAR47 = VAR47,
VAR59.VAR40 = VAR40,
VAR59.VAR32 = VAR32,
VAR59.VAR31 = VAR31,
VAR59.VAR66 = VAR66,
VAR59.VAR3 = VAR3;
VAR59.VAR6 = 16'h0040,
VAR59.VAR52 = 16'h2df4,
VAR59.VAR24 = 16'h2e00;
VAR39 VAR72 (
.clk (clk),
.reset (VAR44),
.VAR21 (VAR21),
.VAR50 (VAR61),
.VAR28 (VAR28),
.VAR77 (VAR65),
.VAR2 (VAR38),
.VAR73 (VAR26),
.VAR27 (VAR15),
.VAR14 (VAR1),
.VAR54 (VAR30),
.VAR11 (VAR41),
.VAR56 (VAR56)
);
VAR72.VAR64 = VAR64,
VAR72.VAR45 = VAR36,
VAR72.VAR37 = VAR37;
endmodule
|
gpl-2.0
|
davidjabon/Verilog
|
Binary_to_BCD/binary_to_BCD_ten_bit.v
| 1,519 |
module MODULE1(
input [9:0] in,
output [3:0] VAR29,
output [3:0] VAR24,
output [3:0] VAR41,
output VAR23
);
wire [3:0] VAR1,VAR13,VAR19,VAR36,VAR4,VAR16,VAR11,VAR37,VAR10,VAR8,VAR31,VAR9;
wire [3:0] VAR40,VAR20,VAR28,VAR32,VAR17,VAR7,VAR5,VAR6,VAR39,VAR34,VAR18,VAR27;
assign VAR40 = {1'b0,in[9:7]};
assign VAR20 = {VAR1[2:0],in[6]};
assign VAR28 = {VAR13[2:0],in[5]};
assign VAR32 = {1'b0,VAR1[3],VAR13[3],VAR19[3]};
assign VAR17 = {VAR19[2:0],in[4]};
assign VAR7 = {VAR36[2:0],VAR4[3]};
assign VAR5 = {VAR4[2:0],in[3]};
assign VAR6 = {VAR16[2:0],VAR11[3]};
assign VAR39 = {VAR11[2:0],in[2]};
assign VAR34 = {1'b0,VAR36[3],VAR16[3],VAR37[3]};
assign VAR18 = {VAR37[2:0],VAR10[3]};
assign VAR27 = {VAR10[2:0],in[1]};
VAR25 VAR12(VAR40,VAR1);
VAR25 VAR21(VAR20,VAR13);
VAR25 VAR33(VAR28,VAR19);
VAR25 VAR2(VAR32,VAR36);
VAR25 VAR38(VAR17,VAR4);
VAR25 VAR26(VAR7,VAR16);
VAR25 VAR14(VAR5,VAR11);
VAR25 VAR3(VAR6,VAR37);
VAR25 VAR22(VAR39,VAR10);
VAR25 VAR30(VAR34,VAR8);
VAR25 VAR15(VAR18,VAR31);
VAR25 VAR35(VAR27,VAR9);
assign VAR29 = {VAR9[2:0],in[0]};
assign VAR24 = {VAR31[2:0],VAR9[3]};
assign VAR41 = {VAR8[2:0],VAR31[3]};
assign VAR23 = VAR8[3];
endmodule
|
gpl-2.0
|
jhol/butterflylogic
|
rtl/eia232.v
| 4,083 |
module MODULE1 #(
parameter [31:0] VAR3 = 100000000,
parameter [31:0] VAR23 = 28,
parameter [31:0] VAR36 = 115200,
parameter VAR33 = VAR3 / VAR23 )(
input wire VAR4,
input wire reset,
input wire [1:0] VAR35, input wire VAR8, input wire [31:0] VAR14, input wire VAR17, output wire VAR11, output wire [39:0] VAR12,
output wire VAR10, output wire VAR31 );
wire VAR6;
reg VAR16, VAR15;
reg VAR24, VAR34;
reg VAR9, VAR2;
reg VAR21, VAR7;
reg VAR30, VAR29;
reg [3:0] VAR32, VAR1;
wire [7:0] VAR25;
wire [31:0] VAR28;
assign VAR12 = {VAR28,VAR25};
always @(posedge VAR4)
begin
VAR16 <= VAR15;
VAR24 <= VAR34;
VAR9 <= VAR2;
VAR21 <= VAR7;
VAR30 <= VAR29;
VAR32 <= VAR1;
end
always
begin
VAR15 = 1'b0;
VAR34 = 1'b0;
VAR2 = 1'b0;
VAR7 = 1'b0;
VAR29 = VAR10;
if (!VAR30 && VAR10)
case(VAR25)
8'h02 : VAR15 = 1'b1;
8'h11 : VAR34 = 1'b1;
8'h13 : VAR2 = 1'b1;
8'h82 : VAR7 = 1'b1;
endcase
VAR1 = VAR32;
if (VAR21) VAR1 = VAR28[5:2];
end
VAR20 #(
.VAR23(VAR23)
) VAR20 (
.VAR4 (VAR4),
.reset (reset),
.VAR26 (VAR35),
.VAR27 (VAR6)
);
VAR19 #(
.VAR3(VAR33),
.VAR36(VAR36)
) VAR19 (
.VAR4 (VAR4),
.reset (reset),
.VAR17 (VAR17),
.VAR6 (VAR6),
.VAR13 (VAR25),
.VAR18 (VAR28),
.VAR10 (VAR10)
);
VAR22 #(
.VAR3(VAR33),
.VAR36(VAR36)
) VAR22 (
.VAR4 (VAR4),
.VAR6 (VAR6),
.reset (reset),
.VAR5 (VAR32),
.write (VAR8),
.VAR14 (VAR14),
.VAR16 (VAR16),
.VAR24 (VAR24),
.VAR9 (VAR9),
.VAR11 (VAR11),
.VAR31 (VAR31)
);
endmodule
|
gpl-2.0
|
cr88192/bgbtech_bjx1core
|
smalltst/compdec/ModFbCc.v
| 9,403 |
module MODULE1(VAR64, reset,
VAR18, VAR4, VAR24, VAR22, VAR35,
VAR49, VAR17, VAR3);
input VAR64;
input reset;
input[9:0] VAR18;
input[9:0] VAR4;
output[7:0] VAR24;
output[7:0] VAR22;
output[7:0] VAR35;
output[13:0] VAR49;
input[31:0] VAR17;
input[31:0] VAR3;
reg[9:0] VAR50;
reg[9:0] VAR34;
reg[7:0] VAR65;
reg[7:0] VAR57;
reg[7:0] VAR16;
reg[7:0] VAR6;
reg[7:0] VAR44;
reg[7:0] VAR9;
reg[13:0] VAR23; reg[13:0] VAR13;
reg[13:0] VAR10; reg[3:0] VAR28;
reg[13:0] VAR19; reg[3:0] VAR54;
reg VAR8; reg VAR61;
reg VAR21;
reg[31:0] VAR37;
reg[31:0] VAR59;
reg[31:0] VAR45;
reg[31:0] VAR38;
reg[31:0] VAR63;
reg[9:0] VAR15;
reg[9:0] VAR20;
reg[9:0] VAR39;
reg[9:0] VAR32;
reg[9:0] VAR53;
reg[9:0] VAR29;
reg[9:0] VAR56;
reg[9:0] VAR60;
reg[9:0] VAR14;
reg[9:0] VAR33;
reg[9:0] VAR40;
reg[9:0] VAR25;
reg[9:0] VAR11;
reg[9:0] VAR30;
reg[9:0] VAR27;
reg[9:0] VAR52;
reg[7:0] VAR43;
reg[7:0] VAR1;
reg[7:0] VAR26;
reg[7:0] VAR12;
reg[7:0] VAR5;
reg[7:0] VAR55;
reg[7:0] VAR51;
reg[7:0] VAR47;
reg[7:0] VAR36;
reg[7:0] VAR58;
reg[7:0] VAR42;
reg[7:0] VAR2;
reg[1:0] VAR62;
reg[1:0] VAR7;
reg[31:0] VAR48;
reg[31:0] VAR46;
reg VAR31;
reg VAR41;
assign VAR49 = VAR10;
assign VAR24 = VAR65;
assign VAR22 = VAR57;
assign VAR35 = VAR16;
always @ (VAR64)
begin
VAR8 = 1;
VAR61 = 0;
VAR15=0;
VAR20=0;
VAR39=0;
VAR32=0;
VAR40=VAR53;
VAR25=VAR29;
VAR11=VAR56;
VAR30=VAR29;
VAR27=VAR14;
VAR52=VAR33;
VAR46=0;
VAR7=0;
VAR41=0;
VAR23=0;
VAR13=0;
if(VAR8)
begin
VAR23[6:0] = VAR50[9:3];
VAR13[6:0] = VAR34[8:2];
VAR54[1:0] = VAR50[2:1];
VAR54[3:2] = VAR34[1:0];
if(VAR61)
VAR19 = VAR13*160 + VAR23*2;
end
else
VAR19 = VAR13*80 + VAR23;
end
else
begin
VAR23[7:0] = VAR50[9:2];
VAR13[6:0] = VAR34[8:2];
VAR54[1:0] = VAR50[1:0];
VAR54[3:2] = VAR34[1:0];
VAR19 = VAR13*160 + VAR23;
end
if(VAR61)
begin
case(VAR59[31:30])
2: begin
VAR40[7:1]=VAR59[29:23];
VAR25[7:1]=VAR59[22:16];
VAR40[0]=VAR59[29];
VAR25[0]=VAR59[22];
VAR11[7:4]=VAR59[15:12];
VAR27[7:4]=VAR59[11: 8];
VAR30[7:4]=VAR59[ 7: 4];
VAR52[7:4]=VAR59[ 3: 0];
VAR11[3:0]=0;
VAR27[3:0]=0;
VAR30[3:0]=0;
VAR52[3:0]=0;
VAR46 = VAR45;
VAR41 = 1;
end
3: begin
VAR15[7:0]=VAR59[15: 8];
VAR20[7:0]=VAR59[ 7: 0];
VAR39[7:1]=VAR59[29:23];
VAR32[7:1]=VAR59[22:16];
VAR39[0]=0;
VAR32[0]=0;
VAR40=VAR15-(VAR20>>1);
VAR25=VAR53+VAR20;
VAR11=VAR39;
VAR30=VAR39;
VAR27=VAR32;
VAR52=VAR32;
VAR46 = VAR45;
VAR41 = 1;
end
endcase
end
else
begin
VAR37 = VAR10[0] ? VAR45 : VAR59;
case(VAR37[31:30])
0: begin
VAR46[31:0] = VAR37[31:0];
VAR41=1;
end
1: begin
VAR46[31:0] = VAR37[31:0];
VAR41=1;
end
2: begin
VAR40[7:5]=VAR37[29:27];
VAR25[7:5]=VAR37[26:24];
VAR40[4:2]=VAR37[29:27];
VAR25[4:2]=VAR37[26:24];
VAR40[1:0]=VAR37[29:28];
VAR25[1:0]=VAR37[26:25];
VAR11[7:6]=VAR37[23:22];
VAR27[7:6]=VAR37[21:20];
VAR30[7:6]=VAR37[19:18];
VAR52[7:6]=VAR37[17:16];
VAR11[5:0]=0;
VAR27[5:0]=0;
VAR30[5:0]=0;
VAR52[5:0]=0;
VAR46[15:0] = VAR37[15:0];
end
3: begin
VAR15[7:4]=VAR37[29:26];
VAR15[3:0]=VAR37[29:26];
VAR20[7:4]=VAR37[25:22];
VAR20[3:0]=VAR37[25:22];
VAR39[7:5]=VAR37[21:19];
VAR32[7:5]=VAR37[18:16];
VAR39[4:0]=0;
VAR32[4:0]=0;
VAR40=VAR15-(VAR20>>1);
VAR25=VAR53+VAR20;
VAR11=VAR39;
VAR30=VAR39;
VAR27=VAR32;
VAR52=VAR32;
VAR46[15:0] = VAR37[15:0];
end
endcase
end
if(VAR31)
begin
case(VAR28)
0: VAR7=VAR48[31:30];
1: VAR7=VAR48[29:28];
2: VAR7=VAR48[27:26];
3: VAR7=VAR48[25:24];
4: VAR7=VAR48[23:22];
5: VAR7=VAR48[21:20];
6: VAR7=VAR48[19:18];
7: VAR7=VAR48[17:16];
8: VAR7=VAR48[15:14];
9: VAR7=VAR48[13:12];
10: VAR7=VAR48[11:10];
11: VAR7=VAR48[ 9: 8];
12: VAR7=VAR48[ 7: 6];
13: VAR7=VAR48[ 5: 4];
14: VAR7=VAR48[ 3: 2];
15: VAR7=VAR48[ 1: 0];
endcase
end
else
begin
VAR7[1]=0;
case(VAR28)
0: VAR7[0]=VAR48[15];
1: VAR7[0]=VAR48[14];
2: VAR7[0]=VAR48[13];
3: VAR7[0]=VAR48[12];
4: VAR7[0]=VAR48[11];
5: VAR7[0]=VAR48[10];
6: VAR7[0]=VAR48[ 9];
7: VAR7[0]=VAR48[ 8];
8: VAR7[0]=VAR48[ 7];
9: VAR7[0]=VAR48[ 6];
10: VAR7[0]=VAR48[ 5];
11: VAR7[0]=VAR48[ 5];
12: VAR7[0]=VAR48[ 3];
13: VAR7[0]=VAR48[ 2];
14: VAR7[0]=VAR48[ 1];
15: VAR7[0]=VAR48[ 0];
endcase
end
VAR6 = 0;
VAR44 = 0;
VAR9 = 0;
if(VAR29[9])
VAR43 = 0;
else if(VAR29[8])
VAR43 = 255;
else
VAR43 = VAR29[7:0];
if(VAR60[9])
VAR1 = 0;
else if(VAR60[8])
VAR1 = 255;
else
VAR1 = VAR60[7:0];
if(VAR33[9])
VAR26 = 0;
else if(VAR33[8])
VAR26 = 255;
else
VAR26 = VAR33[7:0];
if(VAR53[9])
VAR12 = 0;
else if(VAR53[8])
VAR12 = 255;
else
VAR12 = VAR53[7:0];
if(VAR56[9])
VAR5 = 0;
else if(VAR56[8])
VAR5 = 255;
else
VAR5 = VAR56[7:0];
if(VAR14[9])
VAR55 = 0;
else if(VAR14[8])
VAR55 = 255;
else
VAR55 = VAR14[7:0];
VAR51=(VAR43>>1)+(VAR43>>2)+(VAR12>>2);
VAR47=(VAR1>>1)+(VAR1>>2)+(VAR5>>2);
VAR36=(VAR26>>1)+(VAR26>>2)+(VAR55>>2);
VAR58=(VAR12>>1)+(VAR12>>2)+(VAR43>>2);
VAR42=(VAR5>>1)+(VAR5>>2)+(VAR1>>2);
VAR2=(VAR55>>1)+(VAR55>>2)+(VAR26>>2);
if(VAR62[1])
begin
if(VAR62[0])
begin
VAR6 = VAR51;
VAR44 = VAR47;
VAR9 = VAR36;
end
else
begin
VAR6 = VAR58;
VAR44 = VAR42;
VAR9 = VAR2;
end
end
else
begin
if(VAR62[0])
begin
VAR6 = VAR43;
VAR44 = VAR1;
VAR9 = VAR26;
end
else
begin
VAR6 = VAR12;
VAR44 = VAR5;
VAR9 = VAR55;
end
end
end
always @ (posedge VAR64)
begin
VAR50 <= VAR18;
VAR34 <= VAR4;
VAR10 <= VAR19;
VAR28 <= VAR54;
VAR59 <= VAR17;
VAR45 <= VAR3;
VAR53 <= VAR40;
VAR29 <= VAR25;
VAR56 <= VAR11;
VAR60 <= VAR30;
VAR14 <= VAR27;
VAR33 <= VAR52;
VAR48 <= VAR46;
VAR62 <= VAR7;
VAR31 <= VAR41;
VAR65 <= VAR6;
VAR57 <= VAR44;
VAR16 <= VAR9;
end
endmodule
|
mit
|
sh-chris110/chris
|
FPGA/chris.sdram.ok/db/ip/soc_design/submodules/soc_design_niosII_core_cpu_debug_slave_wrapper.v
| 9,640 |
module MODULE1 (
VAR53,
VAR45,
clk,
VAR31,
VAR39,
VAR21,
VAR12,
VAR37,
VAR56,
VAR38,
VAR24,
VAR26,
VAR10,
VAR54,
VAR4,
VAR2,
VAR49,
VAR14,
VAR9,
VAR47,
VAR36,
VAR43,
VAR51,
VAR27,
VAR35,
VAR44,
VAR52,
VAR41,
VAR1,
VAR55,
VAR40,
VAR6,
VAR13
)
;
output [ 37: 0] VAR36;
output VAR43;
output VAR51;
output VAR27;
output VAR35;
output VAR44;
output VAR52;
output VAR41;
output VAR1;
output VAR55;
output VAR40;
output VAR6;
output VAR13;
input [ 31: 0] VAR53;
input [ 31: 0] VAR45;
input clk;
input VAR31;
input VAR39;
input VAR21;
input VAR12;
input VAR37;
input VAR56;
input VAR38;
input VAR24;
input VAR26;
input VAR10;
input [ 35: 0] VAR54;
input VAR4;
input [ 6: 0] VAR2;
input VAR49;
input VAR14;
input VAR9;
input VAR47;
wire [ 37: 0] VAR36;
wire VAR43;
wire [ 37: 0] VAR11;
wire VAR51;
wire VAR27;
wire VAR35;
wire VAR44;
wire VAR52;
wire VAR41;
wire VAR1;
wire VAR55;
wire VAR40;
wire VAR6;
wire VAR13;
wire VAR16;
wire [ 1: 0] VAR33;
wire [ 1: 0] VAR57;
wire VAR8;
wire VAR46;
wire VAR20;
wire VAR34;
wire VAR7;
wire VAR42;
wire VAR17;
VAR22 VAR23
(
.VAR53 (VAR53),
.VAR45 (VAR45),
.VAR31 (VAR31),
.VAR39 (VAR39),
.VAR21 (VAR21),
.VAR12 (VAR12),
.VAR37 (VAR37),
.VAR3 (VAR33),
.VAR5 (VAR57),
.VAR43 (VAR43),
.VAR32 (VAR8),
.VAR56 (VAR56),
.VAR38 (VAR38),
.VAR24 (VAR24),
.VAR26 (VAR26),
.VAR11 (VAR11),
.VAR51 (VAR51),
.VAR30 (VAR20),
.VAR18 (VAR34),
.VAR48 (VAR7),
.VAR10 (VAR10),
.VAR54 (VAR54),
.VAR4 (VAR4),
.VAR2 (VAR2),
.VAR49 (VAR49),
.VAR14 (VAR14),
.VAR9 (VAR9),
.VAR47 (VAR47),
.VAR29 (VAR16),
.VAR50 (VAR46),
.VAR15 (VAR17)
);
VAR28 VAR19
(
.clk (clk),
.VAR3 (VAR33),
.VAR36 (VAR36),
.VAR11 (VAR11),
.VAR27 (VAR27),
.VAR35 (VAR35),
.VAR44 (VAR44),
.VAR52 (VAR52),
.VAR41 (VAR41),
.VAR1 (VAR1),
.VAR55 (VAR55),
.VAR40 (VAR40),
.VAR6 (VAR6),
.VAR13 (VAR13),
.VAR25 (VAR42),
.VAR15 (VAR17)
);
assign VAR20 = 1'b0;
assign VAR34 = 1'b0;
assign VAR46 = 1'b0;
assign VAR16 = 1'b0;
assign VAR8 = 1'b0;
assign VAR17 = 1'b0;
assign VAR42 = 1'b0;
assign VAR33 = 2'b0;
endmodule
|
gpl-2.0
|
mogorschampion/VGA_animated_object
|
pixelGeneration.v
| 2,114 |
module MODULE1(clk, rst, VAR8, VAR12, VAR4, VAR1, VAR6, VAR13);
input clk, rst;
input [3:0] VAR8;
input [2:0] VAR12;
input [9:0] VAR4, VAR1;
input VAR6;
output reg [2:0] VAR13;
wire VAR3, VAR5;
localparam VAR11 = 640;
localparam VAR15 = 480;
localparam VAR9 = 40;
localparam VAR14 = 5;
wire [9:0] VAR19, VAR18, VAR20, VAR7;
reg [9:0] VAR17, VAR10;
reg [9:0] VAR2, VAR16;
always @(posedge clk) begin
if(rst) begin
VAR17 <= 240;
VAR2 <= 320;
end
else begin
VAR17 <= VAR10;
VAR2 <= VAR16;
end
end
assign VAR5 = (VAR1 ==481) && (VAR4 ==0);
assign VAR20 = VAR17;
assign VAR19 = VAR2;
assign VAR7 = VAR20 + VAR9 - 1;
assign VAR18 = VAR19 + VAR9 - 1;
always @ begin
VAR10 = VAR17;
VAR16 = VAR2;
if(VAR5) begin
if (VAR8[0] && (VAR18 < VAR11 - 1)) begin VAR16 = VAR2 + VAR14; end
else if (VAR8[1] && (VAR19 > 1 )) begin
VAR16 = VAR2 - VAR14; end
else if (VAR8[2] && (VAR7 < VAR15 - 1 )) begin
VAR10 = VAR17 + VAR14; end
else if (VAR8[3] && (VAR20 > 1)) begin
VAR10 = VAR17 - VAR14; end
end
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/dlrtp/sky130_fd_sc_hvl__dlrtp.functional.pp.v
| 2,192 |
module MODULE1 (
VAR12 ,
VAR6,
VAR2 ,
VAR13 ,
VAR18 ,
VAR11 ,
VAR3 ,
VAR16
);
output VAR12 ;
input VAR6;
input VAR2 ;
input VAR13 ;
input VAR18 ;
input VAR11 ;
input VAR3 ;
input VAR16 ;
wire VAR15 ;
wire VAR8 ;
wire VAR14;
not VAR5 (VAR15 , VAR6 );
VAR9 VAR4 VAR10 (VAR8 , VAR2, VAR13, VAR15, , VAR18, VAR11);
buf VAR17 (VAR14, VAR8 );
VAR7 VAR1 (VAR12 , VAR14, VAR18, VAR11 );
endmodule
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_ready_and_link_async_to_wormhole.v
| 6,819 |
module MODULE1
,parameter VAR26(VAR8 )
,parameter VAR5 = 2
,parameter int VAR18[VAR5:0] = '{5, 4, 0}
,parameter VAR26(VAR29 )
,localparam VAR27 = VAR25(VAR7)
,localparam VAR11 = VAR25(VAR8)
,localparam VAR10 = VAR18[VAR5]
)
( input VAR2
,input VAR19
,input [VAR27-1:0] VAR15
,output [VAR27-1:0] VAR9
,input [VAR10-1:0] VAR13
,input VAR6
,input VAR12
,input [VAR11-1:0] VAR24
,output [VAR11-1:0] VAR1
);
localparam VAR3 = 3;
genvar VAR20;
typedef struct packed {
logic [VAR7-1:0] VAR14;
VAR22 VAR4;
} VAR17;
localparam VAR21 = VAR23(VAR17);
localparam VAR28 = VAR16(VAR21, VAR8);
begin
end
begin
|
bsd-3-clause
|
jamesbowman/swapforth
|
j1a/verilog/j1.v
| 4,076 |
module MODULE1(
input wire clk,
input wire VAR6,
output wire VAR13,
output wire VAR9,
output wire [15:0] VAR12,
output wire VAR39,
output wire [VAR11-1:0] dout,
input wire [VAR11-1:0] VAR8,
output wire [12:0] VAR14,
input wire [15:0] VAR23);
reg [3:0] VAR31, VAR40; reg [VAR11-1:0] VAR34, VAR28; reg VAR35;
reg [12:0] VAR19 , VAR24; wire [12:0] VAR18 = VAR19 + 13'd1;
reg VAR4; wire [VAR11-1:0] VAR2; reg VAR7 = 1;
assign VAR12 = VAR34[15:0];
assign VAR14 = VAR24;
wire [VAR11-1:0] VAR21, VAR10;
reg [1:0] VAR27, VAR3;
VAR5 #(.VAR37(15)) VAR29(.clk(clk), .rd(VAR21), .VAR32(VAR35), .VAR20(VAR34), .VAR22(VAR27));
VAR5 #(.VAR37(17)) VAR30(.clk(clk), .rd(VAR10), .VAR32(VAR4), .VAR20(VAR2), .VAR22(VAR3));
wire [16:0] VAR26 = {1'b1, ~VAR34} + VAR21 + 1;
wire VAR33 = VAR34[15] ^ VAR21[15] ? VAR21[15] : VAR26[16];
always @*
begin
casez ({VAR19[12], VAR23[15:8]})
9'b1????????: VAR28 = VAR23; 9'b01???????: VAR28 = { {(VAR11 - 15){1'b0}}, VAR23[14:0] }; 9'b0000?????: VAR28 = VAR34; 9'b0010?????: VAR28 = VAR34; 9'b0001?????: VAR28 = VAR21; 9'b0011?0000: VAR28 = VAR34; 9'b0011?0001: VAR28 = VAR21;
9'b0011?0010: VAR28 = VAR34 + VAR21;
9'b0011?0011: VAR28 = VAR34 & VAR21;
9'b0011?0100: VAR28 = VAR34 | VAR21;
9'b0011?0101: VAR28 = VAR34 ^ VAR21;
9'b0011?0110: VAR28 = ~VAR34;
9'b0011?0111: VAR28 = {VAR11{(VAR26 == 0)}}; 9'b0011?1000: VAR28 = {VAR11{(VAR33)}};
9'b0011?1001: VAR28 = {VAR34[VAR11 - 1], VAR34[VAR11 - 1:1]};
9'b0011?1010: VAR28 = {VAR34[VAR11 - 2:0], 1'b0};
9'b0011?1011: VAR28 = VAR10;
9'b0011?1100: VAR28 = VAR26[15:0];
9'b0011?1101: VAR28 = VAR8;
9'b0011?1110: VAR28 = {{(VAR11 - 4){1'b0}}, VAR31};
9'b0011?1111: VAR28 = {VAR11{(VAR26[16])}}; default: VAR28 = {VAR11{1'VAR38}};
endcase
end
wire VAR1 = (VAR23[6:4] == 1);
wire VAR15 = (VAR23[6:4] == 2);
wire VAR17 = (VAR23[6:4] == 3);
wire VAR16 = (VAR23[6:4] == 4);
wire VAR25 = (VAR23[6:4] == 5);
wire VAR36 = !VAR19[12] & (VAR23[15:13] == 3'b011);
assign VAR39 = !VAR7 & VAR36 & VAR17;
assign dout = VAR21;
assign VAR9 = !VAR7 & VAR36 & VAR16;
assign VAR13 = !VAR7 & VAR36 & VAR25;
assign VAR2 = (VAR23[13] == 1'b0) ? {{(VAR11 - 14){1'b0}}, VAR18, 1'b0} : VAR34;
always @*
begin
casez ({VAR19[12], VAR23[15:13]})
4'b1???,
4'b01??: {VAR35, VAR27} = {1'b1, 2'b01};
4'b0001: {VAR35, VAR27} = {1'b0, 2'b11};
4'b0011: {VAR35, VAR27} = {VAR1, {VAR23[1:0]}};
default: {VAR35, VAR27} = {1'b0, 2'b00};
endcase
VAR40 = VAR31 + {VAR27[1], VAR27[1], VAR27};
casez ({VAR19[12], VAR23[15:13]})
4'b1???: {VAR4, VAR3} = {1'b0, 2'b11};
4'b0010: {VAR4, VAR3} = {1'b1, 2'b01};
4'b0011: {VAR4, VAR3} = {VAR15, VAR23[3:2]};
default: {VAR4, VAR3} = {1'b0, 2'b00};
endcase
casez ({VAR7, VAR19[12], VAR23[15:13], VAR23[7], |VAR34})
7'b10?????: VAR24 = 0;
7'b00000??,
7'b00010??,
7'b00001?0: VAR24 = VAR23[12:0];
7'b01?????,
7'b000111?: VAR24 = VAR10[13:1];
default: VAR24 = VAR18;
endcase
end
always @(negedge VAR6 or posedge clk)
begin
if (!VAR6) begin
VAR7 <= 1'b1;
{ VAR19, VAR31, VAR34} <= 0;
end else begin
VAR7 <= 0;
{ VAR19, VAR31, VAR34} <= { VAR24, VAR40, VAR28 };
end
end
endmodule
|
bsd-3-clause
|
scalable-networks/ext
|
uhd/fpga/usrp2/fifo/fifo_cascade.v
| 2,556 |
module MODULE1
(input clk, input reset, input VAR3,
input [VAR22-1:0] VAR26,
input VAR27,
output VAR24,
output [VAR22-1:0] VAR19,
output VAR25,
input VAR17,
output [15:0] VAR28,
output [15:0] VAR7);
wire [VAR22-1:0] VAR15, VAR21;
wire VAR6, VAR5, VAR18, VAR10;
wire [4:0] VAR14, VAR9, VAR4, VAR8;
wire [15:0] VAR16, VAR13;
VAR2 #(.VAR22(VAR22)) VAR12
(.clk(clk),.reset(reset),.VAR3(VAR3),
.VAR26(VAR26), .VAR27(VAR27), .VAR24(VAR24),
.VAR19(VAR15), .VAR25(VAR6), .VAR17(VAR5),
.VAR28(VAR14),.VAR7(VAR9) );
VAR23 #(.VAR22(VAR22),.VAR20(VAR20)) VAR1
(.clk(clk),.reset(reset),.VAR3(VAR3),
.VAR26(VAR15), .VAR27(VAR6), .VAR24(VAR5),
.VAR19(VAR21), .VAR25(VAR18), .VAR17(VAR10),
.VAR28(VAR16),.VAR7(VAR13) );
VAR2 #(.VAR22(VAR22)) VAR11
(.clk(clk),.reset(reset),.VAR3(VAR3),
.VAR26(VAR21), .VAR27(VAR18), .VAR24(VAR10),
.VAR19(VAR19), .VAR25(VAR25), .VAR17(VAR17),
.VAR28(VAR4),.VAR7(VAR8) );
assign VAR28 = {11'b0,VAR14} + {11'b0,VAR4} + VAR16;
assign VAR7 = {11'b0,VAR9} + {11'b0,VAR8} + VAR13;
endmodule
|
gpl-2.0
|
ShirmanXia/EE469SPRING16
|
lab4/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_cpu_debug_slave_wrapper.v
| 10,470 |
module MODULE1 (
VAR5,
VAR41,
clk,
VAR31,
VAR25,
VAR9,
VAR37,
VAR45,
VAR38,
VAR21,
VAR35,
VAR30,
VAR43,
VAR51,
VAR8,
VAR42,
VAR2,
VAR22,
VAR29,
VAR55,
VAR56,
VAR40,
VAR13,
VAR10,
VAR44,
VAR53,
VAR15,
VAR4,
VAR18,
VAR12,
VAR23,
VAR7,
VAR59,
VAR32,
VAR39,
VAR47
)
;
output [ 37: 0] VAR56;
output VAR40;
output VAR13;
output VAR10;
output VAR44;
output VAR53;
output VAR15;
output VAR4;
output VAR18;
output VAR12;
output VAR23;
output VAR7;
output VAR59;
output VAR32;
output VAR39;
output VAR47;
input [ 31: 0] VAR5;
input [ 31: 0] VAR41;
input clk;
input VAR31;
input VAR25;
input VAR9;
input VAR37;
input VAR45;
input VAR38;
input VAR21;
input VAR35;
input VAR30;
input VAR43;
input [ 35: 0] VAR51;
input VAR8;
input [ 6: 0] VAR42;
input VAR2;
input VAR22;
input VAR29;
input VAR55;
wire [ 37: 0] VAR56;
wire VAR40;
wire [ 37: 0] VAR46;
wire VAR13;
wire VAR10;
wire VAR44;
wire VAR53;
wire VAR15;
wire VAR4;
wire VAR18;
wire VAR12;
wire VAR23;
wire VAR7;
wire VAR59;
wire VAR32;
wire VAR39;
wire VAR47;
wire VAR16;
wire [ 1: 0] VAR24;
wire [ 1: 0] VAR60;
wire VAR57;
wire VAR50;
wire VAR26;
wire VAR14;
wire VAR19;
wire VAR52;
wire VAR34;
VAR54 VAR17
(
.VAR5 (VAR5),
.VAR41 (VAR41),
.VAR31 (VAR31),
.VAR25 (VAR25),
.VAR9 (VAR9),
.VAR37 (VAR37),
.VAR45 (VAR45),
.VAR11 (VAR24),
.VAR3 (VAR60),
.VAR40 (VAR40),
.VAR49 (VAR57),
.VAR38 (VAR38),
.VAR21 (VAR21),
.VAR35 (VAR35),
.VAR30 (VAR30),
.VAR46 (VAR46),
.VAR13 (VAR13),
.VAR28 (VAR26),
.VAR58 (VAR14),
.VAR1 (VAR19),
.VAR43 (VAR43),
.VAR51 (VAR51),
.VAR8 (VAR8),
.VAR42 (VAR42),
.VAR2 (VAR2),
.VAR22 (VAR22),
.VAR29 (VAR29),
.VAR55 (VAR55),
.VAR48 (VAR16),
.VAR20 (VAR50),
.VAR33 (VAR34)
);
VAR27 VAR36
(
.clk (clk),
.VAR11 (VAR24),
.VAR56 (VAR56),
.VAR46 (VAR46),
.VAR10 (VAR10),
.VAR44 (VAR44),
.VAR53 (VAR53),
.VAR15 (VAR15),
.VAR4 (VAR4),
.VAR18 (VAR18),
.VAR12 (VAR12),
.VAR23 (VAR23),
.VAR7 (VAR7),
.VAR59 (VAR59),
.VAR32 (VAR32),
.VAR39 (VAR39),
.VAR47 (VAR47),
.VAR6 (VAR52),
.VAR33 (VAR34)
);
assign VAR26 = 1'b0;
assign VAR14 = 1'b0;
assign VAR50 = 1'b0;
assign VAR16 = 1'b0;
assign VAR57 = 1'b0;
assign VAR34 = 1'b0;
assign VAR52 = 1'b0;
assign VAR24 = 2'b0;
endmodule
|
gpl-3.0
|
rkrajnc/minimig-mist
|
bench/ps2mouse/ps2mouse_ctrl.v
| 6,437 |
module MODULE1 (
input wire clk,
input wire reset,
inout wire VAR32,
inout wire VAR22
);
reg [ 8-1:0] VAR31;
reg [ 8-1:0] VAR30;
reg [ 8-1:0] VAR10;
reg VAR12;
reg VAR19;
reg VAR13;
reg VAR25;
wire VAR21;
reg [ 2-1:0] VAR33;
reg [ 3-1:0] VAR3;
reg [11-1:0] VAR23;
reg [12-1:0] VAR14;
reg [16-1:0] VAR5;
reg [ 3-1:0] VAR28;
reg [ 3-1:0] VAR7;
wire VAR20;
reg VAR6;
wire VAR9;
reg VAR29;
wire VAR16;
reg VAR24;
wire VAR15;
wire VAR17;
reg [ 3-1:0] VAR26;
reg VAR11=0;
wire VAR8;
reg [ 4-1:0] VAR2=1;
reg VAR4=0;
reg [12-1:0] VAR18;
assign VAR32 = (VAR25) ? 1'VAR34 : 1'b0;
assign VAR22 = (VAR21) ? 1'VAR34 : 1'b0;
always @ (posedge clk) begin
VAR33[1:0] <= {VAR33[0], VAR22};
VAR3[2:0] <= {VAR3[1:0], VAR32};
end
assign VAR20 = VAR3[2] & !VAR3[1];
always @ (posedge clk) begin
if (VAR6)
VAR23[10:0] <= 11'b11111111111;
end
else if (VAR20)
VAR23[10:0] <= {VAR33[1],VAR23[10:1]};
end
assign VAR9 = !VAR23[0];
always @ (posedge clk) begin
if (reset)
VAR2 <= 4'd0;
end
else if (VAR4 && !VAR8)
VAR2 <= VAR2 + 4'd1;
end
assign VAR8 = (VAR2 == 4'd9);
always @ begin
VAR25 = 1'b1;
VAR24 = 1'b1;
VAR6 = 1'b0;
VAR29 = 1'b0;
VAR26 = 3'd0;
VAR4 = 1'b0;
case(VAR28)
0 : begin
VAR24=1;
VAR7=1;
end
1 : begin
VAR25=0;
VAR24=0;
VAR29=1;
if (VAR17) begin
VAR7=2;
end else begin
VAR7=1;
end
end
2 : begin
VAR6=1;
VAR24=0;
if (VAR16) begin
VAR4 = 1;
case (VAR2)
0 : VAR7 = 4;
1 : VAR7 = 6;
2 : VAR7 = 6;
3 : VAR7 = 6;
4 : VAR7 = 6;
5 : VAR7 = 6;
6 : VAR7 = 6;
7 : VAR7 = 5;
8 : VAR7 = 6;
default : VAR7 = 6;
endcase
end else begin
VAR7=2;
end
end
3 : begin
VAR24=1;
if (VAR9) begin
VAR26=1;
VAR6=1;
VAR7=4;
end else begin
VAR7=3;
end
end
4 : begin
VAR24=1;
if (VAR9) begin
VAR26=2;
VAR6=1;
VAR7=5;
end else begin
VAR7=4;
end
end
5 : begin
VAR24=1;
if (VAR9) begin
VAR26=3;
VAR6=1;
VAR7 = (VAR11 || !VAR8) ? 6 : 3;
end else begin
VAR7=5;
end
end
6 : begin
VAR24=1;
if (VAR9) begin
VAR26 = (VAR2 == 8) ? 5 : 4;
VAR6=1;
VAR7 = !VAR8 ? 0 : 3;
end else begin
VAR7=6;
end
end
default : begin
VAR25=1'VAR1;
VAR6=1'VAR1;
VAR24=1'VAR1;
VAR29=1'VAR1;
VAR26=2'VAR27;
VAR7=0;
end
endcase
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.blackbox.v
| 1,550 |
module MODULE1 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR5,
VAR4 ,
VAR7 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR3 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/fill/sky130_fd_sc_ms__fill.functional.pp.v
| 1,147 |
module MODULE1 (
VAR3,
VAR4,
VAR2 ,
VAR1
);
input VAR3;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule
|
apache-2.0
|
kwantam/multiexp-a5gx
|
verilog/table_control.v
| 4,503 |
module MODULE1 #( parameter VAR33 = 40
)
( input clk
, input VAR29
, input [26:0] VAR37 , input [14:0] VAR4
, input [2:0] VAR44
, output [26:0] VAR15
, output [26:0] VAR22
, output [26:0] VAR13
, input [1:0] VAR16
, output VAR45
);
localparam VAR43 = VAR6(VAR33);
wire [26:0] VAR32 [2:0];
assign VAR15 = VAR32[0];
assign VAR22 = VAR32[1];
assign VAR13 = VAR32[2];
reg [14:0] VAR5, VAR20;
reg VAR24, VAR40;
reg [VAR43-1:0] VAR30, VAR36;
reg VAR14, VAR2;
localparam VAR11 = 1'b0;
localparam VAR38 = 1'b1;
wire VAR3 = VAR14 == VAR11;
wire VAR35 = VAR14 == VAR38;
localparam VAR19 = 2'b01;
localparam VAR27 = 2'b10;
localparam VAR31 = 2'b11;
wire VAR28 = VAR16 == VAR31;
wire [14:0] VAR41 = VAR5 + {{(15-VAR43){1'b0}},VAR30};
wire VAR39 = VAR30 == (VAR33 - 1);
assign VAR45 = VAR3;
VAR8 begin
VAR20 = VAR5;
VAR40 = VAR24;
VAR36 = VAR30;
VAR2 = VAR14;
case (VAR14)
VAR11: begin
if (~VAR24) begin
case (VAR16)
VAR27: begin
VAR20 = '0;
VAR40 = '0;
VAR36 = '0;
end
VAR19: begin
VAR40 = '1;
VAR36 = '0;
end
default: VAR2 = VAR11;
endcase
end else begin
VAR2 = VAR38;
VAR36 = VAR30 + 1'b1;
end
end
VAR38: begin
if (VAR39 | VAR28) begin
VAR40 = '0;
VAR36 = '0;
VAR20 = VAR5 + VAR33;
VAR2 = VAR11;
end else begin
VAR36 = VAR30 + 1'b1;
end
end
endcase
end
VAR12 @(posedge clk or negedge VAR29) begin
if (~VAR29) begin
VAR5 <= '0;
VAR24 <= '0;
VAR30 <= '0;
VAR14 <= '0;
end else begin
VAR5 <= VAR20;
VAR24 <= VAR40;
VAR30 <= VAR36;
VAR14 <= VAR2;
end
end
genvar VAR21;
generate for(VAR21=0; VAR21<3; VAR21++) begin: VAR18
VAR17 VAR23( .VAR1 (~VAR29)
, .VAR34 (clk)
, .VAR10 (VAR37)
, .VAR25 (VAR4)
, .VAR42 (VAR44[VAR21])
, .VAR7 (VAR24)
, .VAR9 (VAR41)
, .VAR26 (VAR32[VAR21])
);
end
endgenerate
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v
| 1,399 |
module MODULE1 (
VAR5 ,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR1;
wire VAR3;
not VAR4 (VAR3, VAR1 );
and VAR6 (VAR5 , VAR2, VAR3 );
endmodule
|
apache-2.0
|
alexforencich/verilog-ethernet
|
rtl/eth_phy_10g_tx_if.v
| 5,257 |
module MODULE1 #
(
parameter VAR7 = 64,
parameter VAR6 = 2,
parameter VAR1 = 0,
parameter VAR4 = 0,
parameter VAR2 = 0,
parameter VAR3 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR7-1:0] VAR10,
input wire [VAR6-1:0] VAR9,
output wire [VAR7-1:0] VAR5,
output wire [VAR6-1:0] VAR11,
input wire VAR8
);
|
mit
|
KorotkiyEugene/Netmaker_vc_router_syn_quartus
|
NW_matrix_arbiter.v
| 6,604 |
module MODULE2 (state, VAR21, VAR28);
parameter VAR15=4;
input [VAR15*VAR15-1:0] state;
input [VAR15-1:0] VAR21;
output [VAR15*VAR15-1:0] VAR28;
genvar VAR10,VAR26;
generate
for (VAR10=0; VAR10<VAR15; VAR10=VAR10+1) begin:VAR3
for (VAR26=0; VAR26<VAR15; VAR26=VAR26+1) begin:VAR17
assign VAR28[VAR26*VAR15+VAR10]= (state[VAR26*VAR15+VAR10]&&!VAR21[VAR26])||(VAR21[VAR10]);
end
end
endgenerate
endmodule
module MODULE1 (request, VAR14, VAR24, VAR21, VAR6, clk, VAR9);
parameter VAR15= 4;
parameter VAR27 = 0;
parameter VAR23 = 0;
parameter VAR4 = 0;
input [VAR15-1:0] request;
input VAR18 VAR14 [VAR15-1:0];
output VAR18 VAR24;
output [VAR15-1:0] VAR21;
input VAR6;
input clk, VAR9;
genvar VAR10,VAR26;
logic [VAR15-1:0] req;
logic [VAR15-1:0] VAR13;
logic [VAR15*VAR15-1:0] VAR2, VAR12;
logic [VAR15-1:0] VAR7 [VAR15-1:0];
logic [VAR15*VAR15-1:0] VAR28;
logic [VAR15*VAR15-1:0] state;
logic VAR22;
genvar VAR16;
integer VAR11;
VAR18 VAR8;
assign VAR24 = VAR8;
VAR5
begin
if (VAR4) begin
VAR8='0;
for (VAR11=0; VAR11<VAR15; VAR11++) begin
if (request[VAR11] && (VAR14[VAR11]>VAR8)) VAR8=VAR14[VAR11];
end
end
end
generate
if (VAR4) begin
for (VAR16=0; VAR16<VAR15; VAR16++) begin:VAR20
assign req[VAR16]=request[VAR16] && (VAR14[VAR16]>=VAR8);
end
end else begin assign req=request;
end
endgenerate
generate
for (VAR10=0; VAR10<VAR15; VAR10=VAR10+1) begin:VAR1
for (VAR26=0; VAR26<VAR15; VAR26=VAR26+1) begin:VAR19
if (VAR26==VAR10)
assign VAR7[VAR10][VAR26]=req[VAR10];
end
else
if (VAR26>VAR10)
assign VAR7[VAR10][VAR26]=!(req[VAR26]&&state[VAR26*VAR15+VAR10]);
end
else
assign VAR7[VAR10][VAR26]=!(req[VAR26]&&!state[VAR10*VAR15+VAR26]);
end
assign VAR21[VAR10]=&VAR7[VAR10];
end
endgenerate
generate
if (VAR27==2) begin
assign state = VAR6 ? VAR2 : VAR12;
end else begin
assign state = VAR12;
end
endgenerate
MODULE2 #(VAR15) VAR25 (.*);
always@(posedge clk) begin
if (!VAR9) begin
VAR12<='1; VAR2<='1; end else begin
if (VAR27==2) begin
VAR22<=|req;
if (|req) begin
VAR2 <= VAR28;
end
if (VAR22) begin
VAR12 <= state;
end
end else begin
if ((VAR27==1)&!VAR6) begin
end else begin
if (|req) begin
VAR12<=VAR28;
end
end
end
end
end
endmodule
|
gpl-2.0
|
P3Stor/P3Stor
|
pcie/core/gtx_rx_valid_filter_v6.v
| 11,721 |
module MODULE1 #(
parameter VAR21 = 28
)
(
output [1:0] VAR15,
output [15:0] VAR33,
output VAR39,
output VAR18,
output [ 2:0] VAR71,
output VAR30,
input [1:0] VAR3,
input [15:0] VAR58,
input VAR72,
input VAR20,
input [ 2:0] VAR44,
input VAR34,
input VAR74,
input VAR54,
input VAR12,
input VAR2
);
parameter VAR4 = 1;
parameter VAR63 = 5'b00001;
parameter VAR52 = 5'b00010;
parameter VAR31 = 5'b00100;
parameter VAR73 = 5'b01000;
parameter VAR53 = 5'b10000;
parameter VAR14 = 8'hBC;
parameter VAR22 = 8'h7C;
parameter VAR50 = 8'hBC;
parameter VAR62 = 8'h3C;
reg [4:0] VAR47;
wire [4:0] VAR36;
reg VAR55;
wire VAR5;
reg VAR26;
wire VAR69;
parameter VAR46 = 4'b0001;
parameter VAR48 = 4'b0010;
parameter VAR67 = 4'b0100;
parameter VAR1 = 4'b1000;
reg [3:0] VAR16;
wire [3:0] VAR9;
reg [4:0] VAR57;
wire [4:0] VAR65;
reg [3:0] VAR35;
wire [3:0] VAR8;
reg [1:0] VAR56;
reg [15:0] VAR68;
reg VAR61;
reg VAR19;
reg VAR13;
reg [ 2:0] VAR27;
reg VAR17;
reg VAR64;
reg VAR6;
always @(posedge VAR12) begin
if (VAR2) begin
end else begin
if (VAR3[0] && VAR58[7:0] == VAR62)
end
else
if (VAR3[1] && VAR58[15:8] == VAR62)
end
else
case ( VAR36 )
VAR63 : begin
if ((VAR56[0]) && (VAR68[7:0] == VAR14) &&
(VAR56[1]) && (VAR68[15:8] == VAR22)) begin
end else if ((VAR56[1]) && (VAR68[15:8] == VAR14))
end
else
end
VAR52 : begin
if ((VAR56[0] && (VAR68[7:0] == VAR22)) &&
(VAR56[1] && (VAR68[15:8] == VAR22)))
end
else
end
VAR31 : begin
if ((VAR56[0] && (VAR68[7:0] == VAR22)) &&
(VAR56[1] && (VAR68[15:8] == VAR22))) begin
end else
end
VAR73 : begin
if ((VAR56[0]) && (VAR68[7:0] == VAR22))
end
else
end
VAR53 : begin
end
endcase
end
end
assign VAR36 = VAR47;
assign VAR5 = VAR55;
assign VAR69 = VAR26;
always @(posedge VAR12) begin
if (VAR2) begin
end else begin
case ( VAR9 )
VAR46 : begin
if (VAR5)
end
else
end
VAR48 : begin
if (!VAR61)
end
else if (VAR8 == 4'b1111)
end
else
end
VAR67 : begin
if (VAR61)
end
else if (!VAR74)
else
end
VAR1 : begin
if (VAR65 > VAR21)
end
else
end
endcase
end
end
assign VAR9 = VAR16;
always @(posedge VAR12) begin
if (VAR2) begin
end else begin
if ((VAR61) && (VAR9 == VAR1))
end
else
end
end
assign VAR65 = VAR57;
always @(posedge VAR12) begin
if (VAR2) begin
end else begin
if (VAR9 == VAR48)
end
else
end
end
assign VAR8 = VAR35;
VAR43 #(.VAR29(0)) VAR70 (.VAR40(VAR18),
.VAR75(VAR19),
.VAR37(VAR12),
.VAR49(1'b1), .VAR28(1'b1),.VAR41(1'b1),.VAR59(1'b1),.VAR60(1'b1));
reg VAR42 = 1'b0;
reg VAR25 = 1'b0;
reg [3:0] VAR23 = 4'b0000;
wire VAR11 = VAR72 & (VAR56[0] && (VAR68[7:0] == VAR14));
wire VAR51 = VAR72 & (VAR56[1] && (VAR68[15:8] == VAR14));
wire VAR45 = (VAR11 || VAR51) && ~VAR25;
wire VAR32 = VAR42 && (VAR23[3:0] >= 4'hb);
wire VAR7 = (~VAR19 && VAR13) || VAR54;
wire VAR10 = VAR7 || (~VAR32 && VAR42);
wire [3:0] VAR24 = VAR23[3:0] + 4'b0001;
wire [3:0] VAR38 = (~VAR42) ? 4'b0000 :
(VAR7) ? 4'b0000 :
(VAR25) ? VAR24[3:0] :
VAR23[3:0];
wire VAR66 = ~VAR2;
always @(posedge VAR12) begin
end
assign VAR39 = ((VAR9 == VAR46) && ~VAR42) ? VAR61 : 1'b0;
assign VAR15[0] = VAR39 ? VAR56[0] : 1'b0;
assign VAR15[1] = (VAR39 && !VAR69) ? VAR56[1] : 1'b0;
assign VAR33[7:0] = (VAR64) ? VAR50 : VAR68[7:0];
assign VAR33[15:8] = (VAR6) ? VAR50 : VAR68[15:8];
assign VAR71 = (VAR9 == VAR46) ? VAR27 : 3'b000;
assign VAR30 = VAR17;
endmodule
|
gpl-2.0
|
KorotkiyEugene/LAG_sv_syn_quartus
|
LAG_pl_input_port.v
| 3,474 |
module MODULE1(VAR28, VAR7, VAR17, VAR21, VAR2,
VAR24, VAR22,
VAR27, VAR11,
clk, VAR10);
parameter VAR19 = 4;
parameter VAR13 = 8;
input clk, VAR10;
input [VAR19-1:0] VAR28;
input [VAR19-1:0] VAR7;
input VAR8 VAR17 [VAR19-1:0];
output VAR8 VAR21 [VAR19-1:0];
output VAR1 VAR2 [VAR19-1:0];
output [VAR19-1:0] VAR24 [VAR19-1:0];
output [VAR19-1:0] VAR22;
input [VAR19-1:0][VAR19-1:0] VAR27;
input [VAR19-1:0] VAR11;
logic [VAR19-1:0] VAR5 [VAR19-1:0];
logic [VAR19-1:0] VAR22;
VAR8 VAR18 [VAR19-1:0];
VAR8 VAR23 [VAR19-1:0];
logic VAR29;
logic [VAR19-1:0] VAR6, VAR16;
integer VAR4;
genvar VAR12;
VAR20 #(.VAR26(VAR13),
.VAR3(VAR19)) VAR9
(.VAR28(VAR28), .VAR7(VAR7), .VAR17(VAR17),
.VAR21(VAR18),
.VAR2(VAR2), .clk, .VAR10);
generate
for (VAR12=0; VAR12<VAR19; VAR12++) begin:VAR25
assign VAR24[VAR12] = VAR5[VAR12];
assign VAR21[VAR12] = VAR18[VAR12];
end
endgenerate
always@(posedge clk) begin
if (!VAR10) begin
for (VAR4=0; VAR4<VAR19; VAR4++) begin
VAR22[VAR4]<=1'b0;
end
end else begin
for (VAR4=0; VAR4<VAR19; VAR4++) begin
if (VAR18[VAR4].VAR14.VAR15 && VAR7[VAR4]) begin
VAR22[VAR4]<=1'b0;
VAR5[VAR4]<='0;
end else begin
if (VAR11[VAR4]) begin
VAR22[VAR4]<=1'b1;
VAR5[VAR4]<=VAR27[VAR4];
end
assert (VAR27[VAR4]!='0) else begin
end
end
end
end
end end
endmodule
|
gpl-2.0
|
manu3193/ControladorElevadorTDD
|
Temporizador.v
| 4,172 |
module MODULE1( clk, VAR4, VAR1, VAR2);
input clk, VAR4, VAR1;
output VAR2;
reg[3:0] VAR5 = 4'b0; localparam VAR3=7; reg VAR2=0;
always @(posedge clk) begin
VAR2<=0;
if(VAR1)
VAR5 <=0;
end
else begin
if (VAR4) begin
if(VAR5==VAR3-1) begin
VAR2<=1'b1;
VAR5 <=0;
end
else begin
VAR5 <= VAR5+1;
end
end
end
end
endmodule
|
mit
|
takeshineshiro/fpga_linear_128
|
CoarseDelay_bb.v
| 5,130 |
module MODULE1 (
address,
VAR2,
VAR1);
input [2:0] address;
input VAR2;
output [63:0] VAR1;
endmodule
|
mit
|
Canaan-Creative/MM
|
verilog/superkdf9/components/lm32_top/lm32_interrupt.v
| 10,925 |
module MODULE1 (
VAR36,
VAR6,
VAR12,
VAR37,
VAR28,
VAR16,
VAR13,
VAR4,
VAR31,
VAR1,
VAR17,
VAR38,
VAR26,
VAR33
);
parameter VAR39 = VAR29;
input VAR36; input VAR6;
input [VAR39-1:0] VAR12;
input VAR37;
input VAR28; input VAR16; else
input VAR13; VAR5
input VAR4; VAR9 VAR30
input VAR31; VAR5
input [VAR8] VAR1; input [VAR14] VAR17; input VAR38;
output VAR26; wire VAR26;
output [VAR14] VAR33; reg [VAR14] VAR33;
wire [VAR39-1:0] VAR10; wire [VAR39-1:0] VAR27;
reg VAR34; reg VAR23; VAR9 VAR30
reg VAR15; VAR5
reg [VAR39-1:0] VAR7; reg [VAR39-1:0] VAR25;
assign VAR27 = VAR7 & VAR25;
assign VAR26 = (|VAR27) & VAR34;
assign VAR10 = VAR7 | ~VAR12;
assign VAR35 = {{VAR11-3{1'b0}},
VAR15,
1'b0,
VAR23,
VAR34
};
assign VAR19 = VAR7;
assign VAR3 = VAR25;
generate
if (VAR39 > 1)
begin
always @
begin
case (VAR1)
VAR15,
1'b0,
VAR23,
VAR34
};
default: VAR33 = {VAR11{1'VAR2}};
endcase
end
end
endgenerate
generate
if (VAR39 > 1)
begin
always @(posedge VAR36 VAR21)
begin
if (VAR6 == VAR32)
begin
VAR34 <= VAR18;
VAR23 <= VAR18;
VAR15 <= VAR18;
VAR25 <= {VAR39{1'b0}};
VAR7 <= {VAR39{1'b0}};
end
else
begin
VAR7 <= VAR10;
if (VAR28 == VAR32)
begin
VAR23 <= VAR34;
VAR34 <= VAR18;
end
else if (VAR16 == VAR32)
begin
VAR15 <= VAR34;
VAR34 <= VAR18;
end
if (VAR13 == VAR32)
begin
VAR23 <= VAR34;
VAR34 <= VAR18;
end
else if (VAR37 == VAR18)
begin
if (VAR4 == VAR32)
VAR34 <= VAR23;
end
else if (VAR31 == VAR32)
VAR34 <= VAR15;
end
else if (VAR38 == VAR32)
begin
if (VAR1 == VAR20)
begin
VAR34 <= VAR17[0];
VAR23 <= VAR17[1];
VAR15 <= VAR17[2];
end
if (VAR1 == VAR24)
VAR25 <= VAR17[VAR39-1:0];
if (VAR1 == VAR22)
VAR7 <= VAR10 & ~VAR17[VAR39-1:0];
end
end
end
end
end
else
begin
always @(posedge VAR36 VAR21)
begin
if (VAR6 == VAR32)
begin
VAR34 <= VAR18;
VAR23 <= VAR18;
VAR15 <= VAR18;
VAR7 <= {VAR39{1'b0}};
end
else
begin
VAR7 <= VAR10;
if (VAR28 == VAR32)
begin
VAR23 <= VAR34;
VAR34 <= VAR18;
end
else if (VAR16 == VAR32)
begin
VAR15 <= VAR34;
VAR34 <= VAR18;
end
if (VAR13 == VAR32)
begin
VAR23 <= VAR34;
VAR34 <= VAR18;
end
else if (VAR37 == VAR18)
begin
if (VAR4 == VAR32)
VAR34 <= VAR23;
end
else if (VAR31 == VAR32)
VAR34 <= VAR15;
end
else if (VAR38 == VAR32)
begin
if (VAR1 == VAR20)
begin
VAR34 <= VAR17[0];
VAR23 <= VAR17[1];
VAR15 <= VAR17[2];
end
if (VAR1 == VAR22)
VAR7 <= VAR10 & ~VAR17[VAR39-1:0];
end
end
end
end
end
endgenerate
endmodule
|
unlicense
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh.functional.v
| 1,278 |
module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
buf VAR3 (VAR1 , VAR2 );
endmodule
|
apache-2.0
|
GREO/GNU-Radio
|
usrp/fpga/sdr_lib/cordic_stage.v
| 1,799 |
module MODULE1( VAR9, reset, enable, VAR4,VAR8,VAR3,VAR12,VAR11,VAR2,VAR1);
parameter VAR7 = 16;
parameter VAR6 = 16;
parameter VAR5 = 1;
input VAR9;
input reset;
input enable;
input [VAR7-1:0] VAR4,VAR8;
input [VAR6-1:0] VAR3;
input [VAR6-1:0] VAR12;
output [VAR7-1:0] VAR11,VAR2;
output [VAR6-1:0] VAR1;
wire VAR10 = ~VAR3[VAR6-1];
reg [VAR7-1:0] VAR11,VAR2;
reg [VAR6-1:0] VAR1;
always @(posedge VAR9)
if(reset)
begin
VAR11 <= 0;
VAR2 <= 0;
VAR1 <= 0;
end
else if(enable)
begin
VAR11 <= VAR10 ?
VAR4 - {{VAR5+1{VAR8[VAR7-1]}},VAR8[VAR7-2:VAR5]} :
VAR4 + {{VAR5+1{VAR8[VAR7-1]}},VAR8[VAR7-2:VAR5]};
VAR2 <= VAR10 ?
VAR8 + {{VAR5+1{VAR4[VAR7-1]}},VAR4[VAR7-2:VAR5]} :
VAR8 - {{VAR5+1{VAR4[VAR7-1]}},VAR4[VAR7-2:VAR5]};
VAR1 <= VAR10 ?
VAR3 - VAR12 :
VAR3 + VAR12;
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/buf/sky130_fd_sc_hd__buf.symbol.v
| 1,236 |
module MODULE1 (
input VAR5,
output VAR3
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch3/FSM_input_enable.v
| 3,813 |
module MODULE1(
input wire clk,
input wire rst,
input wire VAR9,
output reg VAR12,
output wire VAR2,
output reg VAR1
);
parameter [3:0] VAR6 = 3'd0,
VAR7 = 3'd1,
VAR4 = 3'd2,
VAR14 = 3'd3,
VAR8 = 3'd4,
VAR3= 3'd5,
VAR11 = 3'd6,
VAR5 = 3'd7;
reg [2:0] VAR10, VAR13;
always @(posedge clk, posedge rst)
if(rst)
VAR10 <= VAR6;
else
VAR10 <= VAR13;
always @*
begin
VAR13 = VAR10;
VAR12=1; VAR1 = 0;
case(VAR10)
VAR6:
begin
if(VAR9)
end
VAR13 = VAR7; else begin
VAR13 = VAR6; end
end
VAR7:
begin
VAR12=1;
VAR1 = 1;
VAR13 = VAR11;
end
VAR11:
begin
VAR12=1;
VAR1 = 1;
VAR13 = VAR4;
end
VAR4:
begin
VAR12=1;
VAR1 = 1;
VAR13 = VAR14;
end
VAR14:
begin
VAR12=0;
VAR1 = 1;
VAR13 = VAR8;
end
VAR8:
begin
VAR12=0;
VAR1 = 1;
VAR13 = VAR3;
end
VAR3:
begin
VAR12=0;
VAR1 = 1;
if (VAR9) begin
VAR13 = VAR7;
end else begin
VAR13 = VAR6;
end
end
default:
begin
VAR13 =VAR6;
end
endcase
end
assign VAR2 = VAR12 & VAR9;
endmodule
|
gpl-3.0
|
deepakcu/maestro
|
fpga/DE4_Ethernet_0/master_0.v
| 1,780 |
module MODULE1 (
input wire VAR8, input wire VAR11, output wire [31:0] VAR10, input wire [31:0] VAR15, output wire VAR2, output wire VAR12, output wire [31:0] VAR9, input wire VAR6, input wire VAR3, output wire [3:0] VAR4, output wire VAR5 );
VAR13 #(
.VAR1 (0),
.VAR7 (50000),
.VAR14 (2)
) VAR16 (
.VAR8 (VAR8), .VAR11 (VAR11), .VAR10 (VAR10), .VAR15 (VAR15), .VAR2 (VAR2), .VAR12 (VAR12), .VAR9 (VAR9), .VAR6 (VAR6), .VAR3 (VAR3), .VAR4 (VAR4), .VAR5 (VAR5) );
endmodule
|
apache-2.0
|
open-fpga-nvm/open-nvm-source
|
fpga/NAND/uart_rx.v
| 3,889 |
module MODULE1(
input clk,
input rst,
input VAR7,
output [7:0] VAR13,
output VAR11
);
reg [8:0] VAR4;
assign VAR13[7:0] = VAR4[8:1];
reg VAR10;
assign VAR11 = VAR10;
reg [9:0] VAR2;
reg [3:0] VAR5;
reg VAR1;
reg [9:0] VAR12;
reg [9:0] VAR3;
always@(posedge clk) begin
if(rst)
begin
VAR1 <= VAR6;
VAR10 <= 0;
end
else
begin
case(VAR1)
begin
VAR5 <= 0;
VAR2 <= 0;
VAR12 <= 0;
VAR3 <= 0;
if( VAR7 == 0 )
begin
VAR1 <= VAR9;
end
else
VAR1 <= VAR6;
end
begin
if (VAR2 == VAR8-1)
begin
VAR2 <= 0;
VAR12 <= 0;
VAR3 <= 0;
if (VAR5 == 4'd9-1)
begin
VAR10 <= 1;
VAR1 <= VAR6;
end
else
begin
VAR10 <= 0;
VAR5 <= VAR5 + 1'b1;
VAR1 <= VAR9;
end
end
else
begin
if(VAR7 == 0)
VAR12 <= VAR12 + 1'b1;
end
else
VAR3 <= VAR3 + 1'b1;
if( VAR12 > VAR3 )
VAR4[VAR5] <= 0;
end
else
VAR4[VAR5] <= 1;
VAR2 <= VAR2 + 1'b1;
VAR1 <= VAR9;
end
end
default :
begin
VAR1 <= VAR6;
VAR10 <= 0;
end
endcase
end
end
endmodule
|
gpl-2.0
|
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_0_axi4_tg.v
| 18,550 |
module MODULE1 #(
parameter VAR1 = 4, parameter VAR104 = 32, parameter VAR13 = 32,
parameter VAR96 = 0, parameter VAR68 = 0,
parameter VAR60 = 0,
parameter VAR102 = 32'hFFFFFFFF,
parameter VAR63 = 32'hFFFFD000,
parameter VAR16 = 32'h00002000,
parameter VAR14 = 40,
parameter VAR46 = 40,
parameter VAR99 = 0,
parameter VAR79 = 8'h11,
parameter VAR9 = 0,
parameter VAR41 = 3'b000
)
(
input VAR69, input VAR32,
input VAR39, input VAR25, input VAR85, input VAR88,
input VAR10, output [VAR1-1:0] VAR12, output [VAR104-1:0] VAR49, output [7:0] VAR111, output [2:0] VAR48, output [1:0] VAR31, output [1:0] VAR30, output [3:0] VAR53, output [2:0] VAR6, output VAR26,
input VAR78, output [VAR1-1:0] VAR105, output [VAR13-1:0] VAR37, output [VAR13/8-1:0] VAR77, output VAR29, output VAR22,
input [VAR1-1:0] VAR11, input [1:0] VAR35, input VAR19, output VAR4,
input VAR62, output [VAR1-1:0] VAR91, output [VAR104-1:0] VAR80, output [7:0] VAR98, output [2:0] VAR44, output [1:0] VAR106, output [1:0] VAR33, output [3:0] VAR20, output [2:0] VAR71, output VAR76,
input [VAR1-1:0] VAR42, input [1:0] VAR2, input VAR87, input [VAR13-1:0] VAR73, input VAR66, output VAR81,
output VAR108, output VAR94, output VAR56, output VAR45, output VAR67, output VAR114, output VAR83, output reg VAR40,
output VAR109,
output [VAR13-1:0] VAR82, output [VAR13-1:0] VAR34, output VAR43, output [VAR14-1:0] VAR90, output VAR101, output [VAR46-1:0] VAR57 );
localparam VAR75 = 3; localparam VAR17 = 16; localparam VAR23 = 11;
localparam VAR64 = 16;
wire VAR36;
wire [2:0] VAR59;
wire [7:0] VAR28;
wire [31:0] addr;
wire [VAR75-1:0] VAR95;
wire VAR5;
wire VAR107;
wire [VAR13-1:0] VAR74;
wire [VAR13/8-1:0] VAR65;
wire VAR110;
wire VAR113;
wire VAR103;
wire [VAR64-1:0] VAR54;
wire VAR70;
wire VAR93;
wire [VAR13-1:0] VAR92;
wire [VAR13/8-1:0] VAR8;
wire VAR51;
wire [VAR17-1:0] VAR61;
reg VAR112;
reg VAR97;
VAR27 #
(
.VAR1 (VAR1),
.VAR104 (VAR104),
.VAR13 (VAR13),
.VAR96 (VAR96),
.VAR60 (VAR60),
.VAR102 (VAR102),
.VAR75 (VAR75),
.VAR64 (VAR64),
.VAR17 (VAR17),
.VAR9 (VAR9),
.VAR23 (VAR23)
) VAR47
(
.VAR69 (VAR69),
.VAR32 (VAR32),
.VAR36 (VAR36),
.VAR59 (VAR59),
.VAR28 (VAR28),
.addr (addr),
.VAR95 (VAR95),
.VAR85 (VAR85),
.VAR5 (VAR5),
.VAR107 (VAR107),
.VAR74 (VAR74),
.VAR65 (VAR65),
.VAR110 (VAR110),
.VAR113 (VAR113),
.VAR103 (VAR103),
.VAR54 (VAR54),
.VAR70 (VAR70),
.VAR93 (VAR93),
.VAR92 (VAR92),
.VAR8 (VAR8),
.VAR51 (VAR51),
.VAR61 (VAR61),
.VAR10 (VAR10),
.VAR12 (VAR12),
.VAR49 (VAR49),
.VAR111 (VAR111),
.VAR48 (VAR48),
.VAR31 (VAR31),
.VAR30 (VAR30),
.VAR53 (VAR53),
.VAR6 (VAR6),
.VAR26 (VAR26),
.VAR78 (VAR78),
.VAR105 (VAR105),
.VAR37 (VAR37),
.VAR77 (VAR77),
.VAR29 (VAR29),
.VAR22 (VAR22),
.VAR11 (VAR11),
.VAR35 (VAR35),
.VAR19 (VAR19),
.VAR4 (VAR4),
.VAR62 (VAR62),
.VAR91 (VAR91),
.VAR80 (VAR80),
.VAR98 (VAR98),
.VAR44 (VAR44),
.VAR106 (VAR106),
.VAR33 (VAR33),
.VAR20 (VAR20),
.VAR71 (VAR71),
.VAR76 (VAR76),
.VAR42 (VAR42),
.VAR2 (VAR2),
.VAR87 (VAR87),
.VAR73 (VAR73),
.VAR66 (VAR66),
.VAR81 (VAR81)
);
VAR89 #
(
.VAR104 (VAR104),
.VAR13 (VAR13),
.VAR96 (VAR96),
.VAR60 (VAR60),
.VAR102 (VAR102),
.VAR68 (VAR68),
.VAR75 (VAR75),
.VAR64 (VAR64),
.VAR17 (VAR17),
.VAR14 (VAR14),
.VAR46 (VAR46),
.VAR99 (VAR99),
.VAR79 (VAR79),
.VAR63 (VAR63),
.VAR16 (VAR16),
.VAR41 (VAR41)
) VAR50
(
.clk (VAR69),
.VAR7 (VAR32),
.VAR39 (VAR39),
.VAR25 (VAR25),
.VAR88 (VAR88),
.VAR5 (VAR5),
.VAR36 (VAR36),
.VAR59 (VAR59),
.VAR28 (VAR28),
.addr (addr),
.VAR95 (VAR95),
.VAR72 (VAR113),
.VAR15 (VAR107),
.VAR52 (VAR110),
.VAR38 (VAR74),
.VAR55 (VAR65),
.VAR21 (VAR103),
.VAR18 (VAR54),
.VAR84 (VAR93),
.VAR100 (VAR92),
.VAR3 (VAR8),
.VAR86 (VAR51),
.VAR24 (VAR61),
.VAR58 (VAR70),
.VAR108 (VAR108),
.VAR94 (VAR94),
.VAR56 (VAR56),
.VAR45 (VAR45),
.VAR67 (VAR67),
.VAR114 (VAR114),
.VAR83 (VAR83),
.VAR109 (VAR109),
.VAR34 (VAR34),
.VAR43 (VAR43),
.VAR90 (VAR90),
.VAR101 (VAR101),
.VAR57 (VAR57)
);
assign VAR82 = VAR74;
always @(posedge VAR69)
if (!VAR32)
VAR112 <= 1'b0;
else if (VAR114)
VAR112 <= 1'b1;
always @(posedge VAR69)
if (!VAR32)
VAR97 <= 1'b0;
else if (VAR83)
VAR97 <= 1'b1;
always @(posedge VAR69)
if (!VAR32)
VAR40 <= 1'b0;
else if (VAR112 & VAR97)
VAR40 <= 1'b1;
endmodule
|
mit
|
yunqu/PYNQ
|
boards/ip/boolean_generator_1.1/src/input_mux.v
| 1,808 |
module MODULE1 # (parameter VAR1 = 24) (
input [4:0] sel,
input [VAR1-1:0] VAR3,
output reg VAR2
);
always @(sel, VAR3)
case(sel)
5'h00 : VAR2 = VAR3[0];
5'h01 : VAR2 = VAR3[1];
5'h02 : VAR2 = VAR3[2];
5'h03 : VAR2 = VAR3[3];
5'h04 : VAR2 = VAR3[4];
5'h05 : VAR2 = VAR3[5];
5'h06 : VAR2 = VAR3[6];
5'h07 : VAR2 = VAR3[7];
5'h08 : VAR2 = VAR3[8];
5'h09 : VAR2 = VAR3[9];
5'h0A : VAR2 = VAR3[10];
5'h0B : VAR2 = VAR3[11];
5'h0C : VAR2 = VAR3[12];
5'h0D : VAR2 = VAR3[13];
5'h0E : VAR2 = VAR3[14];
5'h0F : VAR2 = VAR3[15];
5'h10 : VAR2 = VAR3[16];
5'h11 : VAR2 = VAR3[17];
5'h12 : VAR2 = VAR3[18];
5'h13 : VAR2 = VAR3[19];
5'h14 : VAR2 = VAR3[20];
5'h15 : VAR2 = VAR3[21];
5'h16 : VAR2 = VAR3[22];
5'h17 : VAR2 = VAR3[23];
5'h18 : VAR2 = VAR3[24];
5'h19 : VAR2 = VAR3[25];
5'h1A : VAR2 = VAR3[26];
5'h1B : VAR2 = VAR3[27];
5'h1C : VAR2 = VAR3[28];
5'h1D : VAR2 = VAR3[29];
default : VAR2 = 1'b0;
endcase
endmodule
|
bsd-3-clause
|
cheehieu/qm-fir-digital-filter-core
|
ISAAC/qmfir_documentation/v/firdecim_m2_n50.v
| 25,329 |
module MODULE1
(
VAR8, VAR35,
VAR73, VAR6, VAR68, VAR64
);
parameter VAR93 = 16;
parameter VAR77 = 32;
parameter VAR86 = 32;
output reg signed [(VAR77-1):0] VAR8;
output reg VAR35;
input VAR73; input VAR6;
input VAR68;
input signed [(VAR93-1):0] VAR64;
reg [5:0] VAR17;
reg [5:0] VAR45;
reg [4:0] VAR36;
reg [4:0] VAR43;
reg VAR54;
reg VAR9;
reg signed [(VAR93-1):0] VAR91;
reg signed [(VAR93-1):0] VAR46;
reg signed [(VAR86-1):0] VAR60;
reg signed [(VAR86-1):0] VAR31; reg signed [(VAR86-1):0] VAR74; reg signed [(VAR86-1):0] VAR67; reg signed [(VAR86-1):0] VAR34; reg signed [(VAR86-1):0] VAR15; reg signed [(VAR86-1):0] VAR22; reg signed [(VAR86-1):0] VAR51; reg signed [(VAR86-1):0] VAR79; reg signed [(VAR86-1):0] VAR47; reg signed [(VAR86-1):0] VAR25; reg signed [(VAR86-1):0] VAR82; reg signed [(VAR86-1):0] VAR89; reg signed [(VAR86-1):0] VAR90; reg signed [(VAR86-1):0] VAR66; reg signed [(VAR86-1):0] VAR5; reg signed [(VAR86-1):0] VAR85; reg signed [(VAR86-1):0] VAR56; reg signed [(VAR86-1):0] VAR63; reg signed [(VAR86-1):0] VAR37; reg signed [(VAR86-1):0] VAR65; reg signed [(VAR86-1):0] VAR26; reg signed [(VAR86-1):0] VAR30; reg signed [(VAR86-1):0] VAR4; reg signed [(VAR86-1):0] VAR33; reg signed [(VAR86-1):0] VAR27;
reg signed [15:0] VAR87;
wire [5:0] VAR88;
wire valid;
wire VAR24;
wire VAR1;
wire VAR11;
wire VAR49;
wire VAR42;
wire VAR59;
wire VAR38;
wire VAR16;
wire VAR57;
wire VAR29;
wire VAR28;
wire VAR40;
wire VAR32;
wire VAR7;
wire VAR50;
wire VAR72;
wire VAR61;
wire VAR53;
wire VAR18;
wire VAR81;
wire VAR48;
wire VAR23;
wire VAR92;
wire VAR44;
wire VAR80;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
begin
VAR54 <= 1'b0 ;
VAR9 <= 1'b0 ;
end
else
begin
VAR54 <= VAR9;
VAR9 <= VAR68 ;
end
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
begin
VAR91[(VAR93-1):0] <= {(VAR93){1'b0}} ;
VAR46[(VAR93-1):0] <= {(VAR93){1'b0}};
end
else
begin
VAR46[(VAR93-1):0] <= VAR64[(VAR93-1):0];
VAR91[(VAR93-1):0] <= VAR46[(VAR93-1):0];
end
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
begin
VAR87[15:0] <= 16'd0;
end
else
begin
case (VAR88[5:0])
6'b000000: VAR87[15:0] <= 16'VAR75; 6'b000001: VAR87[15:0] <= 16'VAR95; 6'b000010: VAR87[15:0] <= 16'VAR52; 6'b000011: VAR87[15:0] <= 16'VAR94; 6'b000100: VAR87[15:0] <= 16'VAR21; 6'b000101: VAR87[15:0] <= 16'VAR78; 6'b000110: VAR87[15:0] <= 16'VAR55; 6'b000111: VAR87[15:0] <= 16'VAR84; 6'b001000: VAR87[15:0] <= 16'VAR12; 6'b001001: VAR87[15:0] <= 16'VAR70; 6'b001010: VAR87[15:0] <= 16'VAR13; 6'b001011: VAR87[15:0] <= 16'VAR20; 6'b001100: VAR87[15:0] <= 16'VAR41; 6'b001101: VAR87[15:0] <= 16'VAR39; 6'b001110: VAR87[15:0] <= 16'VAR69; 6'b001111: VAR87[15:0] <= 16'VAR76; 6'b010000: VAR87[15:0] <= 16'VAR83; 6'b010001: VAR87[15:0] <= 16'VAR3; 6'b010010: VAR87[15:0] <= 16'VAR2; 6'b010011: VAR87[15:0] <= 16'VAR10; 6'b010100: VAR87[15:0] <= 16'VAR14; 6'b010101: VAR87[15:0] <= 16'VAR62; 6'b010110: VAR87[15:0] <= 16'VAR58; 6'b010111: VAR87[15:0] <= 16'VAR71; 6'b011000: VAR87[15:0] <= 16'VAR19; 6'b011001: VAR87[15:0] <= 16'VAR19; 6'b011010: VAR87[15:0] <= 16'VAR71; 6'b011011: VAR87[15:0] <= 16'VAR58; 6'b011100: VAR87[15:0] <= 16'VAR62; 6'b011101: VAR87[15:0] <= 16'VAR14; 6'b011110: VAR87[15:0] <= 16'VAR10; 6'b011111: VAR87[15:0] <= 16'VAR2; 6'b100000: VAR87[15:0] <= 16'VAR3; 6'b100001: VAR87[15:0] <= 16'VAR83; 6'b100010: VAR87[15:0] <= 16'VAR76; 6'b100011: VAR87[15:0] <= 16'VAR69; 6'b100100: VAR87[15:0] <= 16'VAR39; 6'b100101: VAR87[15:0] <= 16'VAR41; 6'b100110: VAR87[15:0] <= 16'VAR20; 6'b100111: VAR87[15:0] <= 16'VAR13; 6'b101000: VAR87[15:0] <= 16'VAR70; 6'b101001: VAR87[15:0] <= 16'VAR12; 6'b101010: VAR87[15:0] <= 16'VAR84; 6'b101011: VAR87[15:0] <= 16'VAR55; 6'b101100: VAR87[15:0] <= 16'VAR78; 6'b101101: VAR87[15:0] <= 16'VAR21; 6'b101110: VAR87[15:0] <= 16'VAR94; 6'b101111: VAR87[15:0] <= 16'VAR52; 6'b110000: VAR87[15:0] <= 16'VAR95; 6'b110001: VAR87[15:0] <= 16'VAR75;
default: VAR87[15:0] <= 16'VAR75; endcase
end
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
begin
VAR45[5:0] <= {(6){1'b0}} ;
end
else if (VAR68 & ~VAR9)
begin
VAR45[5:0] <= (VAR17[5:0] == 49) ? 0
: VAR17[5:0] + 1 ;
end
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
begin
VAR43[4:0] <= {(5){1'b0}} ;
VAR36[4:0] <= {(5){1'b0}} ;
VAR17[5:0] <= {(6){1'b0}} ;
end
else
begin
VAR43[4:0] <= (VAR68 & ~VAR54) ? 0:
(VAR43 == 26) ? (26)
: VAR43[4:0] + 1 ;
VAR36[4:0] <= VAR43[4:0] ;
VAR17[5:0] <= VAR45[5:0] ;
end
assign VAR88[5:0] = VAR45[5:0] == 0 ?
2*VAR43[4:0] -1:
(VAR45[5:0] + 2*VAR43[4:0] - 1) > 49 ?
VAR45[5:0] + 2*VAR43[4:0] - 51 :
VAR45[5:0] + 2*VAR43[4:0] - 1;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
begin
VAR60[(VAR86-1):0] <= {(VAR86){1'b0}};
end
else
begin
VAR60[(VAR86-1):0] <= VAR87 * VAR91; end
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR31[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 1)
VAR31[(VAR86-1):0] <= (VAR17 == 1) ? VAR60
: VAR60[(VAR86-1):0] + VAR31[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR74[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 2)
VAR74[(VAR86-1):0] <= (VAR17 == 49) ? VAR60
: VAR60[(VAR86-1):0] + VAR74[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR67[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 3)
VAR67[(VAR86-1):0] <= (VAR17 == 47) ? VAR60
: VAR60[(VAR86-1):0] + VAR67[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR34[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 4)
VAR34[(VAR86-1):0] <= (VAR17 == 45) ? VAR60
: VAR60[(VAR86-1):0] + VAR34[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR15[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 5)
VAR15[(VAR86-1):0] <= (VAR17 == 43) ? VAR60
: VAR60[(VAR86-1):0] + VAR15[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR22[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 6)
VAR22[(VAR86-1):0] <= (VAR17 == 41) ? VAR60
: VAR60[(VAR86-1):0] + VAR22[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR51[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 7)
VAR51[(VAR86-1):0] <= (VAR17 == 39) ? VAR60
: VAR60[(VAR86-1):0] + VAR51[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR79[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 8)
VAR79[(VAR86-1):0] <= (VAR17 == 37) ? VAR60
: VAR60[(VAR86-1):0] + VAR79[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR47[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] ==9)
VAR47[(VAR86-1):0] <= (VAR17 == 35) ? VAR60
: VAR60[(VAR86-1):0] + VAR47[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR25[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] ==10)
VAR25[(VAR86-1):0] <= (VAR17 == 33) ? VAR60
: VAR60[(VAR86-1):0] + VAR25[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR82[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 11)
VAR82[(VAR86-1):0] <= (VAR17 == 31) ? VAR60
: VAR60[(VAR86-1):0] + VAR82[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR89[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 12)
VAR89[(VAR86-1):0] <= (VAR17 == 29) ? VAR60
: VAR60[(VAR86-1):0] + VAR89[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR90[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 13)
VAR90[(VAR86-1):0] <= (VAR17 == 27) ? VAR60
: VAR60[(VAR86-1):0] + VAR90[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR66[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 14)
VAR66[(VAR86-1):0] <= (VAR17 == 25) ? VAR60
: VAR60[(VAR86-1):0] + VAR66[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR5[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 15)
VAR5[(VAR86-1):0] <= (VAR17 == 23) ? VAR60
: VAR60[(VAR86-1):0] + VAR5[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR85[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 16)
VAR85[(VAR86-1):0] <= (VAR17 == 21) ? VAR60
: VAR60[(VAR86-1):0] + VAR85[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR56[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 17)
VAR56[(VAR86-1):0] <= (VAR17 == 19) ? VAR60
: VAR60[(VAR86-1):0] + VAR56[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR63[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] ==18)
VAR63[(VAR86-1):0] <= (VAR17 == 17) ? VAR60
: VAR60[(VAR86-1):0] + VAR63[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR37[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 19)
VAR37[(VAR86-1):0] <= (VAR17 == 15) ? VAR60
: VAR60[(VAR86-1):0] + VAR37[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR65[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 20)
VAR65[(VAR86-1):0] <= (VAR17 == 13) ? VAR60
: VAR60[(VAR86-1):0] + VAR65[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR26[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 21)
VAR26[(VAR86-1):0] <= (VAR17 == 11) ? VAR60
: VAR60[(VAR86-1):0] + VAR26[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR30[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 22)
VAR30[(VAR86-1):0] <= (VAR17 == 9) ? VAR60
: VAR60[(VAR86-1):0] + VAR30[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR4[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 23)
VAR4[(VAR86-1):0] <= (VAR17 == 7) ? VAR60
: VAR60[(VAR86-1):0] + VAR4[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR33[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 24)
VAR33[(VAR86-1):0] <= (VAR17 == 5) ? VAR60
: VAR60[(VAR86-1):0] + VAR33[(VAR86-1):0] ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR27[(VAR86-1):0] <= {(VAR86){1'b0}} ;
else if (VAR36[4:0] == 0)
VAR27[(VAR86-1):0] <= (VAR17 == 4) ? VAR60
: VAR60[(VAR86-1):0] + VAR27[(VAR86-1):0] ;
assign VAR24 = (VAR17[5:0] == 1) & (VAR36 == 1) ;
assign VAR1 = (VAR17[5:0] == 49) & (VAR36 == 1) ;
assign VAR11 = (VAR17[5:0] == 47) & (VAR36 == 1) ;
assign VAR49 = (VAR17[5:0] == 45) & (VAR36 == 1) ;
assign VAR42 = (VAR17[5:0] == 43) & (VAR36 == 1) ;
assign VAR59 = (VAR17[5:0] == 41) & (VAR36 == 1) ;
assign VAR38 = (VAR17[5:0] == 39) & (VAR36 == 1) ;
assign VAR16 = (VAR17[5:0] == 37) & (VAR36 == 1) ;
assign VAR57 = (VAR17[5:0] == 35) & (VAR36 == 1) ;
assign VAR29 = (VAR17[5:0] == 33) & (VAR36 == 1) ;
assign VAR28 = (VAR17[5:0] == 31) & (VAR36 == 1) ;
assign VAR40 = (VAR17[5:0] == 29) & (VAR36 == 1) ;
assign VAR32 = (VAR17[5:0] == 27) & (VAR36 == 1) ;
assign VAR7 = (VAR17[5:0] == 25) & (VAR36 == 1) ;
assign VAR50 = (VAR17[5:0] == 23) & (VAR36 == 1) ;
assign VAR72 = (VAR17[5:0] == 21) & (VAR36 == 1) ;
assign VAR61 = (VAR17[5:0] == 19) & (VAR36 == 1) ;
assign VAR53 = (VAR17[5:0] == 17) & (VAR36 == 1) ;
assign VAR18 = (VAR17[5:0] == 15) & (VAR36 == 1) ;
assign VAR81 = (VAR17[5:0] == 13) & (VAR36 == 1) ;
assign VAR48 = (VAR17[5:0] == 11) & (VAR36 == 1) ;
assign VAR23 = (VAR17[5:0] == 9) & (VAR36 == 1) ;
assign VAR92 = (VAR17[5:0] == 7) & (VAR36 == 1) ;
assign VAR44 = (VAR17[5:0] == 5) & (VAR36 == 1) ;
assign VAR80 = (VAR17[5:0] == 3) & (VAR36 == 1) ;
assign valid = VAR24 | VAR1 | VAR11 | VAR49 | VAR42 | VAR59 |
VAR38 | VAR16 | VAR57 | VAR29 | VAR28 | VAR40 |
VAR32 | VAR7 | VAR50 | VAR72 | VAR61 | VAR53 |
VAR18 | VAR81 | VAR48 | VAR23 | VAR92 | VAR44 |
VAR80;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6)
VAR8[(VAR77-1):0] <= {(VAR77){1'b0}} ;
else if (valid)
VAR8[(VAR77-1):0] <= (VAR31[(VAR86-1):0] & {(VAR77){ VAR24 }}) |
(VAR74[(VAR86-1):0] & {(VAR77){ VAR1 }}) |
(VAR67[(VAR86-1):0] & {(VAR77){ VAR11 }}) |
(VAR34[(VAR86-1):0] & {(VAR77){ VAR49 }}) |
(VAR15[(VAR86-1):0] & {(VAR77){ VAR42 }}) |
(VAR22[(VAR86-1):0] & {(VAR77){ VAR59 }}) |
(VAR51[(VAR86-1):0] & {(VAR77){ VAR38 }}) |
(VAR79[(VAR86-1):0] & {(VAR77){ VAR16 }}) |
(VAR47[(VAR86-1):0] & {(VAR77){ VAR57 }}) |
(VAR25[(VAR86-1):0] & {(VAR77){ VAR29 }}) |
(VAR82[(VAR86-1):0] & {(VAR77){ VAR28 }}) |
(VAR89[(VAR86-1):0] & {(VAR77){ VAR40 }}) |
(VAR90[(VAR86-1):0] & {(VAR77){ VAR32 }}) |
(VAR66[(VAR86-1):0] & {(VAR77){ VAR7 }}) |
(VAR5[(VAR86-1):0] & {(VAR77){ VAR50 }}) |
(VAR85[(VAR86-1):0] & {(VAR77){ VAR72 }}) |
(VAR56[(VAR86-1):0] & {(VAR77){ VAR61 }}) |
(VAR63[(VAR86-1):0] & {(VAR77){ VAR53 }}) |
(VAR37[(VAR86-1):0] & {(VAR77){ VAR18 }}) |
(VAR65[(VAR86-1):0] & {(VAR77){ VAR81 }}) |
(VAR26[(VAR86-1):0] & {(VAR77){ VAR48 }}) |
(VAR30[(VAR86-1):0] & {(VAR77){ VAR23 }}) |
(VAR4[(VAR86-1):0] & {(VAR77){ VAR92 }}) |
(VAR33[(VAR86-1):0] & {(VAR77){ VAR44 }}) |
(VAR27[(VAR86-1):0] & {(VAR77){ VAR80 }}) ;
always @ (posedge VAR73 or posedge VAR6)
if (VAR6) VAR35 <= 1'b0 ;
else VAR35 <= valid;
endmodule MODULE1
|
gpl-2.0
|
cpulabs/mist1032isa
|
src/mist1032isa.v
| 19,115 |
module MODULE1(
input wire VAR287,
input wire VAR1,
input wire VAR19,
input wire VAR37,
output wire VAR211,
input wire VAR202,
output wire VAR191,
input wire VAR240,
output wire [1:0] VAR102, output wire [3:0] VAR84,
output wire VAR158, output wire [31:0] VAR224,
output wire [31:0] VAR238,
input wire VAR4,
output wire VAR245,
input wire [63:0] VAR277,
output wire VAR248, input wire VAR184,
output wire VAR260, output wire [31:0] VAR63,
output wire [31:0] VAR143,
input wire VAR94, output wire VAR51,
input wire [31:0] VAR174,
input wire VAR23,
input wire [5:0] VAR182,
output wire VAR80,
output wire VAR209,
output wire [5:0] VAR177,
output wire VAR155,
output wire VAR114,
output wire [1:0] VAR26,
output wire [31:0] VAR293,
output wire [31:0] VAR30,
input wire VAR186,
output wire VAR24,
input wire VAR296,
output wire VAR109,
input wire [7:0] VAR14,
input wire [31:0] VAR271,
output wire VAR197,
input wire VAR129,
output wire VAR61,
output wire [31:0] VAR212
);
wire VAR254;
wire VAR176;
wire VAR239;
wire [1:0] VAR153;
wire [2:0] VAR190;
wire [31:0] VAR110;
wire [13:0] VAR253;
wire [31:0] VAR107;
wire VAR196;
wire VAR67;
wire [63:0] VAR193;
wire [23:0] VAR39;
wire VAR68;
wire VAR264;
wire [1:0] VAR247;
wire [3:0] VAR41;
wire VAR82; wire [13:0] VAR214;
wire [1:0] VAR115;
wire [2:0] VAR221;
wire [31:0] VAR47;
wire [31:0] VAR121;
wire [31:0] VAR151;
wire VAR140;
wire VAR222;
wire [63:0] VAR85;
wire [23:0] VAR105;
wire VAR226;
wire [31:0] VAR124;
wire VAR279;
wire VAR18;
wire [1:0] VAR104;
wire VAR118;
wire [31:0] VAR281;
wire [31:0] VAR90;
wire VAR175;
wire [31:0] VAR16;
wire VAR99;
wire VAR210;
wire [5:0] VAR227;
wire VAR178;
wire VAR256;
wire VAR56;
wire [31:0] VAR265;
wire [31:0] VAR147;
wire VAR3;
wire [31:0] VAR208;
wire VAR278;
wire [5:0] VAR69;
wire VAR36;
wire VAR55;
wire VAR198;
wire [1:0] VAR165;
wire [3:0] VAR233;
wire VAR75;
wire [31:0] VAR142;
wire [31:0] VAR122;
wire VAR62;
wire VAR10;
wire [63:0] VAR157;
wire VAR144 = VAR198;
wire VAR71;
wire VAR29;
wire [3:0] VAR126;
wire [7:0] VAR283;
wire [31:0] VAR27;
wire VAR241;
wire VAR228;
wire [31:0] VAR231;
reg VAR42;
assign VAR191 = VAR55;
assign VAR102 = VAR165;
assign VAR84 = VAR233;
assign VAR158 = VAR75;
assign VAR224 = VAR142;
assign VAR238 = VAR122;
assign VAR245 = VAR10;
assign VAR198 = VAR240;
assign VAR62 = VAR4;
assign VAR157 = VAR277;
wire VAR163;
wire [5:0] VAR169;
wire VAR207;
wire VAR154;
wire [1:0] VAR15;
assign VAR209 = VAR163;
assign VAR177 = VAR169;
assign VAR155 = VAR207;
assign VAR114 = VAR154;
assign VAR26 = VAR15;
VAR162 #(32'h0) VAR152(
.VAR31(VAR287),
.VAR37(VAR37),
.VAR200(VAR254),
.VAR209(VAR163),
.VAR177(VAR169),
.VAR155(VAR207),
.VAR114(VAR154),
.VAR26(VAR15),
.VAR166(VAR176),
.VAR252(VAR239),
.VAR77(VAR153),
.VAR120(VAR190),
.VAR237(VAR110),
.VAR220(VAR253),
.VAR25(VAR107),
.VAR213(VAR196),
.VAR167(VAR67),
.VAR2(VAR193),
.VAR229(VAR39),
.VAR168(VAR68),
.VAR261(VAR264),
.VAR116(VAR247), .VAR12(VAR41),
.VAR194(VAR82), .VAR76(VAR214),
.VAR161(VAR115),
.VAR40(VAR221),
.VAR223(VAR47),
.VAR150(VAR121),
.VAR205(VAR151),
.VAR6(VAR140),
.VAR286(VAR85),
.VAR206(VAR105),
.VAR156(VAR279),
.VAR280(VAR18),
.VAR285(VAR104), .VAR225(VAR118), .VAR272(VAR281),
.VAR135(VAR90),
.VAR111(VAR175 || VAR42),
.VAR101(VAR16),
.VAR53(VAR99),
.VAR13(VAR210),
.VAR137(VAR227),
.VAR128(VAR226),
.VAR188(VAR124),
.VAR293(VAR293),
.VAR8(VAR71),
.VAR96(VAR29),
.VAR103(VAR126),
.VAR180(VAR283),
.VAR60(VAR27),
.VAR246(VAR241),
.VAR7(VAR228),
.VAR138(VAR231)
);
assign VAR30 = 32'h0;
VAR50 VAR249(
.VAR31(VAR287),
.VAR37(VAR37),
.VAR81(VAR71),
.VAR44(VAR29),
.VAR58(VAR126),
.VAR22(VAR283),
.VAR138(VAR27),
.VAR45(VAR241),
.VAR297(VAR228),
.VAR60(VAR231),
.VAR186(VAR186),
.VAR24(VAR24),
.VAR296(VAR296),
.VAR109(VAR109),
.VAR14(VAR14),
.VAR271(VAR271),
.VAR197(VAR197),
.VAR129(VAR129),
.VAR61(VAR61),
.VAR212(VAR212)
);
wire VAR295;
wire VAR59;
wire VAR274;
wire [1:0] VAR32;
wire [2:0] VAR125;
wire [31:0] VAR189;
wire [13:0] VAR52;
wire [1:0] VAR34;
wire [3:0] VAR127;
wire VAR294;
wire [31:0] VAR100;
wire [31:0] VAR20;
wire VAR282;
wire VAR108;
wire VAR74;
wire [63:0] VAR73;
wire [23:0] VAR86;
VAR185 VAR266(
.VAR31(VAR1),
.VAR37(VAR37),
.VAR66(VAR68),
.VAR259(VAR264),
.VAR132(VAR247),
.VAR250(VAR41),
.VAR49(VAR82),
.VAR275(VAR214),
.VAR33(VAR115),
.VAR79(VAR221),
.VAR263(VAR47),
.VAR290(VAR121),
.VAR286(VAR151),
.VAR168(VAR140),
.VAR91(1'b0),
.VAR205(VAR85),
.VAR9(VAR105),
.VAR54(VAR176),
.VAR201(VAR239),
.VAR48(VAR153),
.VAR173(VAR190),
.VAR289(VAR110),
.VAR106(VAR253),
.VAR267(VAR107),
.VAR166(VAR196),
.VAR232(VAR67),
.VAR236(VAR193),
.VAR131(VAR39),
.VAR191(VAR295),
.VAR240(VAR59),
.VAR242(VAR274),
.VAR88(VAR32),
.VAR21(VAR125),
.VAR65(VAR189),
.VAR187(VAR52),
.VAR102(VAR34),
.VAR84(VAR127),
.VAR158(VAR294),
.VAR224(VAR100),
.VAR238(VAR20),
.VAR4(VAR282),
.VAR245(VAR108),
.VAR270(VAR74),
.VAR277(VAR73),
.VAR148(VAR86)
);
wire [3:0] VAR276;
wire [31:0] VAR134;
wire [63:0] VAR273;
VAR268 VAR117(
.VAR31(VAR1),
.VAR37(VAR37),
.VAR230(VAR254),
.VAR136(VAR295),
.VAR258(VAR59),
.VAR43(VAR274),
.VAR87(VAR32), .VAR251(VAR125),
.VAR203(VAR189), .VAR172(VAR52),
.VAR92(VAR34),
.VAR95(VAR127),
.VAR164(VAR294),
.VAR218(VAR100),
.VAR72(VAR20),
.VAR269(VAR282),
.VAR28(VAR108),
.VAR217(VAR74),
.VAR219(VAR73),
.VAR183(VAR86),
.VAR191(VAR55),
.VAR240(VAR198),
.VAR102(VAR165),
.VAR84(VAR276),
.VAR158(VAR75),
.VAR224(VAR142),
.VAR238(VAR134),
.VAR113(VAR62),
.VAR288(VAR10),
.VAR277(VAR273)
);
VAR292 VAR215(
.VAR181(VAR276),
.VAR38(VAR134),
.VAR83(VAR233),
.VAR139(VAR122)
);
VAR292 VAR17(
.VAR181(4'hf),
.VAR38(VAR157[31:0]),
.VAR83(),
.VAR139(VAR273[31:0])
);
VAR292 VAR133(
.VAR181(4'hf),
.VAR38(VAR157[63:32]),
.VAR83(),
.VAR139(VAR273[63:32])
);
VAR57 VAR257(
.VAR31(VAR1),
.VAR37(VAR37),
.VAR170(VAR226),
.VAR130(VAR124),
.VAR146(VAR279),
.VAR70(VAR18),
.VAR98(VAR104), .VAR171(VAR118), .VAR35(VAR281),
.VAR101(VAR90),
.VAR284(VAR175),
.VAR280(1'b0),
.VAR135(VAR16),
.VAR141(VAR99),
.VAR179(VAR210),
.VAR243(VAR227),
.VAR255(VAR178), .VAR262(VAR256),
.VAR46(VAR56), .VAR149(VAR265),
.VAR192(VAR147),
.VAR235(VAR3),
.VAR199(),
.VAR145(VAR208),
.VAR11(VAR278),
.VAR234(VAR69),
.VAR159(VAR36),
.VAR248(VAR248),
.VAR184(VAR184),
.VAR260(VAR260), .VAR63(VAR63),
.VAR143(VAR143),
.VAR94(VAR94),
.VAR51(VAR51),
.VAR174(VAR174),
.VAR23(VAR23),
.VAR182(VAR182),
.VAR80(VAR80)
);
wire [5:0] VAR78 = VAR169 - 6'd36;
VAR291 VAR97( .VAR31(VAR1),
.VAR160(VAR19), .VAR37(VAR37),
.VAR216(VAR163 && (VAR169 == 6'd36 || VAR169 == 6'd37)),
.VAR123(VAR78[1:0]),
.VAR64(VAR207),
.VAR204(VAR154),
.VAR5(VAR15),
.VAR235(VAR178),
.VAR199(VAR256),
.VAR89(VAR56), .VAR93(VAR265),
.VAR145(VAR147),
.VAR244(VAR3),
.VAR192(VAR208),
.VAR195(VAR278),
.VAR112(VAR69),
.VAR119(VAR36),
.VAR211(VAR211),
.VAR202(VAR202)
);
always@(posedge VAR1 or negedge VAR37)begin
if(!VAR37)begin
VAR42 <= 1'b0;
end
else begin
case(VAR42)
1'b0:
begin
if(!VAR18 && VAR279 && VAR118)begin
VAR42 <= 1'b1;
end
end
1'b1:
begin
VAR42 <= 1'b0;
end
endcase
end
end
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
models/udp_isolatch_pp_pkg_s/sky130_fd_sc_hs__udp_isolatch_pp_pkg_s.symbol.v
| 1,479 |
module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR4,
input VAR3 ,
input VAR2 ,
input VAR5
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.symbol.v
| 1,355 |
module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
markusC64/1541ultimate2
|
fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_nios2_gen2_0.v
| 5,779 |
module MODULE1 (
input wire clk, input wire VAR25, input wire VAR23, output wire [31:0] VAR21, output wire [3:0] VAR14, output wire VAR1, input wire [31:0] VAR7, input wire VAR11, output wire VAR20, output wire [31:0] VAR3, output wire VAR26, output wire [29:0] VAR24, output wire VAR10, input wire [31:0] VAR8, input wire VAR16, input wire [31:0] irq, output wire VAR12, input wire [8:0] VAR5, input wire [3:0] VAR15, input wire VAR18, input wire VAR19, output wire [31:0] VAR2, output wire VAR6, input wire VAR13, input wire [31:0] VAR4, output wire VAR22 );
VAR17 VAR9 (
.clk (clk), .VAR25 (VAR25), .VAR23 (VAR23), .VAR21 (VAR21), .VAR14 (VAR14), .VAR1 (VAR1), .VAR7 (VAR7), .VAR11 (VAR11), .VAR20 (VAR20), .VAR3 (VAR3), .VAR26 (VAR26), .VAR24 (VAR24), .VAR10 (VAR10), .VAR8 (VAR8), .VAR16 (VAR16), .irq (irq), .VAR12 (VAR12), .VAR5 (VAR5), .VAR15 (VAR15), .VAR18 (VAR18), .VAR19 (VAR19), .VAR2 (VAR2), .VAR6 (VAR6), .VAR13 (VAR13), .VAR4 (VAR4), .VAR22 (VAR22) );
endmodule
|
gpl-3.0
|
martinmiranda14/Digitales
|
Lab_6/project_5/project_5.srcs/sources_1/new/teclado.v
| 5,484 |
module MODULE1(
input [7:0] VAR12,
output reg [4:0] VAR18,
output reg [2:0] VAR21,
output [7:0] VAR1
);
localparam VAR17 = 3'd1;
localparam VAR25 = 3'd2;
localparam VAR9 = 3'd3;
localparam VAR24 = 3'd4;
localparam VAR23 = 8'h45;
localparam VAR19 = 8'h16;
localparam VAR11 = 8'h1E;
localparam VAR4 = 8'h26;
localparam VAR16 = 8'h25;
localparam VAR5 = 8'h2E;
localparam VAR33 = 8'h36;
localparam VAR14 = 8'h3D;
localparam VAR8 = 8'h3E;
localparam VAR20 = 8'h46;
localparam VAR22 = 8'h1C;
localparam VAR30 = 8'h32;
localparam VAR7 = 8'h21;
localparam VAR2 = 8'h23;
localparam VAR26 = 8'h24;
localparam VAR6 = 8'h2B;
localparam VAR3 = 8'h44;
localparam VAR27 = 8'h35;
localparam VAR29 = 8'h1B;
localparam VAR28 = 8'h2D;
localparam VAR13 = 8'h3A;
localparam VAR35 = 8'h5A;
localparam VAR15 =8'h75;
localparam VAR34 =8'h72;
localparam VAR10 =8'h6B;
localparam VAR32 =8'h74;
wire VAR31;
assign VAR1[4:0]= VAR18;
assign VAR1[7:5]= VAR21;
always @(*) begin
case(VAR12)
VAR23: begin
VAR18=5'd0;
VAR21=VAR17;
end
VAR19: begin
VAR18=5'd1;
VAR21=VAR17;
end
VAR11:begin
VAR18=5'd2;
VAR21=VAR17;
end
VAR4:begin
VAR18=5'd3;
VAR21=VAR17;
end
VAR16:begin
VAR18=5'd4;
VAR21=VAR17;
end
VAR5:begin
VAR18=5'd5;
VAR21=VAR17;
end
VAR33:begin
VAR18=5'd6;
VAR21=VAR17;
end
VAR14:begin
VAR18=5'd7;
VAR21=VAR17;
end
VAR8:begin
VAR18=5'd8;
VAR21=VAR17;
end
VAR20:begin
VAR18=5'd9;
VAR21=VAR17;
end
VAR22:begin
VAR18=5'd10;
VAR21=VAR17;
end
VAR30:begin
VAR18=5'd11;
VAR21=VAR17;
end
VAR7:begin
VAR18=5'd12;
VAR21=VAR17;
end
VAR2:begin
VAR18=5'd13;
VAR21=VAR17;
end
VAR26:begin
VAR18=5'd14;
VAR21=VAR17;
end
VAR6:begin
VAR18=5'd15;
VAR21=VAR17;
end
VAR29:begin
VAR18=5'd21;
VAR21=VAR24;
end
VAR28:begin
VAR18=5'd22;
VAR21=VAR24;
end
VAR13:begin
VAR18=5'd23;
VAR21=VAR24;
end
VAR27:begin
VAR18=5'd24;
VAR21=VAR24;
end
VAR3:begin
VAR18=5'd25;
VAR21=VAR24;
end
VAR35:begin
VAR18 =5'd16;
VAR21 =VAR25;
end
VAR15:begin
VAR18=5'd19;
VAR21=VAR9;
end
VAR34:begin
VAR18=5'd20;
VAR21=VAR9;
end
VAR10:begin
VAR18=5'd17;
VAR21=VAR9;
end
VAR32:begin
VAR18=5'd18;
VAR21=VAR9;
end
default: begin
VAR18=5'd0;
VAR21=3'd0;
end
endcase
end
endmodule
|
apache-2.0
|
borti4938/sd2snes
|
verilog/sd2snes_gsu/gsu_umult.v
| 4,361 |
module MODULE1 (
VAR4,
VAR19,
VAR11);
input [7:0] VAR4;
input [7:0] VAR19;
output [15:0] VAR11;
wire [15:0] VAR17;
wire [15:0] VAR11 = VAR17[15:0];
VAR1 VAR2 (
.VAR4 (VAR4),
.VAR19 (VAR19),
.VAR11 (VAR17),
.VAR8 (1'b0),
.VAR7 (1'b1),
.VAR6 (1'b0),
.VAR5 (1'b0),
.sum (1'b0));
VAR2.VAR13 = "VAR16=5",
VAR2.VAR10 = "VAR15",
VAR2.VAR9 = "VAR18",
VAR2.VAR12 = 8,
VAR2.VAR14 = 8,
VAR2.VAR3 = 16;
endmodule
|
gpl-2.0
|
twlostow/dsi-shield
|
hdl/rtl/hpdmc/ddram_controller.v
| 2,492 |
module MODULE1 #(
parameter VAR13 = 4'h0
) (
input VAR32,
input VAR14,
input VAR4,
input [13:0] VAR40,
input VAR5,
input [31:0] VAR46,
output [31:0] VAR34,
input [VAR2-1:0] VAR35,
input VAR22,
input VAR25,
output VAR19,
input [3:0] VAR1,
input [31:0] VAR28,
output [31:0] VAR23,
output VAR3,
output VAR18,
output VAR38,
output VAR27,
output VAR39,
output VAR44,
output VAR8,
output [12:0] VAR29,
output [1:0] VAR45,
output [1:0] VAR20,
inout [31:0] VAR47,
inout [1:0] VAR6
);
VAR42 #(
.VAR12("VAR16"),
.VAR43(1'b0),
.VAR41("VAR33")
) VAR36 (
.VAR11(VAR3),
.VAR17(VAR32),
.VAR31(VAR14),
.VAR48(1'b1),
.VAR15(1'b1),
.VAR24(1'b0),
.VAR9(1'b0),
.VAR21(1'b0)
);
VAR42 #(
.VAR12("VAR16"),
.VAR43(1'b0),
.VAR41("VAR33")
) VAR10 (
.VAR11(VAR18),
.VAR17(VAR32),
.VAR31(VAR14),
.VAR48(1'b1),
.VAR15(1'b0),
.VAR24(1'b1),
.VAR9(1'b0),
.VAR21(1'b0)
);
VAR30 #(
.VAR13(VAR13),
.VAR7(VAR2),
.VAR26(VAR37)
) VAR30 (
.VAR32(VAR32),
.VAR14(VAR14),
.VAR4(VAR4),
.VAR40(VAR40),
.VAR5(VAR5),
.VAR46(VAR46),
.VAR34(VAR34),
.VAR35(VAR35),
.VAR22(VAR22),
.VAR25(VAR25),
.VAR19(VAR19),
.VAR1(VAR1),
.VAR28(VAR28),
.VAR23(VAR23),
.VAR38(VAR38),
.VAR27(VAR27),
.VAR39(VAR39),
.VAR44(VAR44),
.VAR8(VAR8),
.VAR20(VAR20),
.VAR29(VAR29),
.VAR45(VAR45),
.VAR47(VAR47),
.VAR6(VAR6)
);
endmodule
|
lgpl-3.0
|
Tao-J/nexys3MIPSSoC
|
Counter_3channel.v
| 1,133 |
module MODULE1(input clk,
input rst,
input VAR10,
input VAR2,
input VAR5,
input VAR3,
input [31:0] VAR9,
input [1:0] VAR8,
output VAR1,
output VAR4,
output VAR6,
output [31:0] VAR7
);
endmodule
|
gpl-3.0
|
DeadWitcher/amber-de0-nano
|
hw/vlog/system/timer_module.v
| 15,776 |
module MODULE1 #(
parameter VAR41 = 32,
parameter VAR57 = 4
)(
input VAR64,
input [31:0] VAR1,
input [VAR57-1:0] VAR63,
input VAR16,
output [VAR41-1:0] VAR9,
input [VAR41-1:0] VAR60,
input VAR6,
input VAR54,
output VAR29,
output VAR12,
output [2:0] VAR34
);
reg [15:0] VAR30 = 'd0; reg [15:0] VAR47 = 'd0; reg [15:0] VAR55 = 'd0; reg [23:0] VAR65 = 24'hffffff; reg [23:0] VAR49 = 24'hffffff; reg [23:0] VAR50 = 24'hffffff; reg [7:0] VAR24 = 'd0; reg [7:0] VAR44 = 'd0; reg [7:0] VAR51 = 'd0; reg VAR3 = 'd0; reg VAR26 = 'd0; reg VAR5 = 'd0;
reg [31:0] VAR53 = 'd0;
wire VAR18;
wire VAR48;
reg VAR39 = 'd0;
wire [31:0] VAR40;
assign VAR18 = VAR54 && VAR16 && !VAR39;
assign VAR48 = VAR54 && !VAR16 && !VAR29;
always @( posedge VAR64 )
VAR39 <= VAR48;
assign VAR12 = 1'd0;
assign VAR29 = VAR54 && ( VAR18 || VAR39 );
generate
if (VAR41 == 128)
begin : VAR62
assign VAR40 = VAR1[3:2] == 2'd3 ? VAR60[127:96] :
VAR1[3:2] == 2'd2 ? VAR60[ 95:64] :
VAR1[3:2] == 2'd1 ? VAR60[ 63:32] :
VAR60[ 31: 0] ;
assign VAR9 = {4{VAR53}};
end
else
begin : VAR42
assign VAR40 = VAR60;
assign VAR9 = VAR53;
end
endgenerate
assign VAR34 = { VAR5,
VAR26,
VAR3 };
always @( posedge VAR64 )
begin
if ( VAR18 )
case ( VAR1[15:0] )
VAR20: VAR24 <= VAR60[7:0];
VAR8: VAR44 <= VAR60[7:0];
VAR2: VAR51 <= VAR60[7:0];
endcase
if ( VAR18 && VAR1[15:0] == VAR7 )
begin
VAR65 <= {VAR60[15:0], 8'd0};
VAR30 <= VAR60[15:0];
end
else if ( VAR24[7] ) begin
if ( VAR65 == 24'd0 )
begin
if ( VAR24[6] ) VAR65 <= {VAR30, 8'd0};
end
else
VAR65 <= 24'hffffff;
end
else
case ( VAR24[3:2] )
2'b00: VAR65 <= (VAR65 & 24'hffff00) - 9'd256;
2'b01: VAR65 <= (VAR65 & 24'hfffff0) - 9'd16;
2'b10: VAR65 <= VAR65 - 1'd1;
default:
begin
("VAR21 VAR32 VAR10 VAR23 VAR45 %VAR36 for VAR32 0",
VAR24[3:2]);
end
endcase
end
if ( VAR18 && VAR1[15:0] == VAR25 )
begin
VAR49 <= {VAR60[15:0], 8'd0};
VAR47 <= VAR60[15:0];
end
else if ( VAR44[7] ) begin
if ( VAR49 == 24'd0 )
begin
if ( VAR44[6] ) VAR49 <= {VAR47, 8'd0};
end
else
VAR49 <= 24'hffffff;
end
else
case ( VAR44[3:2] )
2'b00: VAR49 <= (VAR49 & 24'hffff00) - 9'd256;
2'b01: VAR49 <= (VAR49 & 24'hfffff0) - 9'd16;
2'b10: VAR49 <= VAR49 - 1'd1;
default:
begin
("VAR21 VAR32 VAR10 VAR23 VAR45 %VAR36 for VAR32 1",
VAR44[3:2]);
end
endcase
end
if ( VAR18 && VAR1[15:0] == VAR59 )
begin
VAR50 <= {VAR60[15:0], 8'd0};
VAR55 <= VAR60[15:0];
end
else if ( VAR51[7] ) begin
if ( VAR50 == 24'd0 )
begin
if ( VAR51[6] ) VAR50 <= {VAR55, 8'd0};
end
else
VAR50 <= 24'hffffff;
end
else
case ( VAR51[3:2] )
2'b00: VAR50 <= (VAR50 & 24'hffff00) - 9'd256;
2'b01: VAR50 <= (VAR50 & 24'hfffff0) - 9'd16;
2'b10: VAR50 <= VAR50 - 1'd1;
default:
begin
("VAR21 VAR32 VAR10 VAR23 VAR45 %VAR36 for VAR32 2",
VAR51[3:2]);
end
endcase
end
if ( VAR18 && VAR1[15:0] == VAR33 )
VAR3 <= 1'd0;
else if ( VAR65 == 24'd0 )
VAR3 <= 1'd1;
if ( VAR18 && VAR1[15:0] == VAR58)
VAR26 <= 1'd0;
else if ( VAR49 == 24'd0 )
VAR26 <= 1'd1;
if ( VAR18 && VAR1[15:0] == VAR27)
VAR5 <= 1'd0;
else if ( VAR50 == 24'd0 )
VAR5 <= 1'd1;
end
always @( posedge VAR64 )
if ( VAR48 )
case ( VAR1[15:0] )
VAR7: VAR53 <= {16'd0, VAR30};
VAR25: VAR53 <= {16'd0, VAR47};
VAR59: VAR53 <= {16'd0, VAR55};
VAR20: VAR53 <= {24'd0,
VAR24[7:6],
2'd0,
VAR24[3:2],
2'd0
};
VAR8: VAR53 <= {24'd0,
VAR44[7:6],
2'd0,
VAR44[3:2],
2'd0
};
VAR2: VAR53 <= {24'd0,
VAR51[7:6],
2'd0,
VAR51[3:2],
2'd0
};
VAR67: VAR53 <= {16'd0, VAR65[23:8]};
VAR56: VAR53 <= {16'd0, VAR49[23:8]};
VAR66: VAR53 <= {16'd0, VAR50[23:8]};
default: VAR53 <= 32'h66778899;
endcase
reg VAR46;
reg VAR37;
reg VAR17;
wire VAR4 = VAR54 && !VAR16 && VAR29;
always @(posedge VAR64)
if ( VAR4 || VAR18 )
begin
if ( VAR18 )
("VAR19 0x%08x VAR43 ", VAR60);
end
else
("VAR31 0x%08x VAR52 ", VAR9);
case ( VAR1[15:0] )
VAR7:
(" VAR32 VAR10 VAR32 0 VAR11");
VAR25:
(" VAR32 VAR10 VAR32 1 VAR11");
VAR59:
(" VAR32 VAR10 VAR32 2 VAR11");
VAR20:
(" VAR32 VAR10 VAR32 0 VAR28");
VAR8:
(" VAR32 VAR10 VAR32 1 VAR28");
VAR2:
(" VAR32 VAR10 VAR32 2 VAR28");
VAR67:
(" VAR32 VAR10 VAR32 0 VAR45");
VAR56:
(" VAR32 VAR10 VAR32 1 VAR45");
VAR66:
(" VAR32 VAR10 VAR32 2 VAR45");
VAR33:
(" VAR32 VAR10 VAR32 0 VAR15");
VAR58:
(" VAR32 VAR10 VAR32 1 VAR15");
VAR27:
(" VAR32 VAR10 VAR32 2 VAR15");
default:
begin
(" VAR21 VAR13 VAR61 VAR22 VAR38");
(", VAR35 0x%08h\VAR14", VAR1);
end
endcase
(", VAR35 0x%08h\VAR14", VAR1);
end
always @(posedge VAR64)
begin
VAR46 <= VAR3;
VAR37 <= VAR26;
VAR17 <= VAR5;
if ( VAR3 && !VAR46 )
begin
end
if ( VAR26 && !VAR37 )
begin
end
if ( VAR5 && !VAR17 )
begin
end
end
endmodule
|
lgpl-2.1
|
rohit91/novena-sd-fpga
|
novena-sd.srcs/sources_1/ip/clk_wiz_v3_5_0/bclk_dll/example_design/bclk_dll_exdes.v
| 5,155 |
module MODULE1
parameter VAR16 = 100
)
( input VAR14,
input VAR8,
output [1:1] VAR12,
output VAR22,
input VAR5,
output VAR19
);
localparam VAR10 = 16;
wire VAR7 = !VAR19 || VAR5 || VAR8;
reg VAR18;
reg VAR20;
reg VAR1;
reg VAR17;
wire VAR9;
wire clk;
reg [VAR10-1:0] counter;
VAR6 VAR13
(.VAR11 (VAR13),
.VAR4 (VAR14));
VAR2 VAR21
( .VAR15 (VAR13),
.VAR3 (VAR9),
.VAR5 (VAR5),
.VAR19 (VAR19));
assign VAR12[1] = VAR9;
assign clk = VAR9;
always @(posedge VAR7 or posedge clk) begin
if (VAR7) begin
VAR18 <= 1'b1;
VAR20 <= 1'b1;
VAR1 <= 1'b1;
VAR17 <= 1'b1;
end
else begin
VAR18 <= 1'b0;
VAR20 <= VAR18;
VAR1 <= VAR20;
VAR17 <= VAR1;
end
end
always @(posedge clk or posedge VAR17) begin
if (VAR17) begin
end else begin
end
end
assign VAR22 = counter[VAR10-1];
endmodule
|
apache-2.0
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_1/affine_block_ieee754_fp_multiplier_1_1_stub.v
| 1,338 |
module MODULE1(VAR1, VAR3, VAR2)
;
input [31:0]VAR1;
input [31:0]VAR3;
output [31:0]VAR2;
endmodule
|
mit
|
ipburbank/Raster-Laser-Projector
|
src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Framebuffer.v
| 4,275 |
module MODULE1 (
address,
VAR34,
VAR16,
VAR46,
clk,
VAR30,
VAR54,
VAR1,
reset,
VAR29,
write,
VAR20,
VAR23,
VAR35,
VAR25,
VAR43
)
;
output [ 7: 0] VAR25;
output [ 7: 0] VAR43;
input [ 18: 0] address;
input [ 18: 0] VAR34;
input VAR16;
input VAR46;
input clk;
input VAR30;
input VAR54;
input VAR1;
input reset;
input VAR29;
input write;
input VAR20;
input [ 7: 0] VAR23;
input [ 7: 0] VAR35;
wire VAR50;
wire VAR12;
wire VAR55;
wire [ 7: 0] VAR25;
wire [ 7: 0] VAR43;
wire VAR26;
wire VAR17;
assign VAR26 = VAR16 & write & VAR30;
assign VAR12 = ~VAR30;
assign VAR55 = ~VAR54;
assign VAR50 = ~VAR29;
assign VAR17 = VAR46 & VAR20 & VAR54;
VAR45 VAR38
(
.VAR36 (address),
.VAR31 (VAR34),
.VAR27 (VAR12),
.VAR9 (VAR55),
.VAR51 (clk),
.VAR50 (VAR50),
.VAR53 (VAR23),
.VAR48 (VAR35),
.VAR8 (VAR25),
.VAR41 (VAR43),
.VAR33 (VAR26),
.VAR37 (VAR17)
);
VAR38.VAR24 = 8,
VAR38.VAR39 = "VAR18",
VAR38.VAR28 = "VAR18",
VAR38.VAR52 = "VAR5",
VAR38.VAR21 = "VAR45",
VAR38.VAR7 = 307200,
VAR38.VAR22 = 307200,
VAR38.VAR14 = 307200,
VAR38.VAR47 = "VAR42",
VAR38.VAR32 = "VAR44",
VAR38.VAR11 = "VAR44",
VAR38.VAR19 = "VAR6",
VAR38.VAR2 = "VAR49",
VAR38.VAR40 = 8,
VAR38.VAR4 = 8,
VAR38.VAR15 = 19,
VAR38.VAR3 = 19,
VAR38.VAR10 = "VAR18";
endmodule
|
gpl-3.0
|
SI-RISCV/e200_opensource
|
rtl/e203/core/e203_lsu_ctrl.v
| 35,288 |
module MODULE1(
input VAR8,
input VAR27,
output VAR103,
output VAR144, input VAR25, output [VAR209-1:0] VAR168,
output [VAR137 -1:0] VAR9,
output VAR124 , output VAR200, output [VAR142 -1:0] VAR85,
output VAR255,
output VAR65,
input VAR33, output VAR222, input [VAR142-1:0] VAR62, input VAR75, input [VAR209-1:0] VAR147,
input [VAR209/8-1:0] VAR194,
input VAR133,
input VAR251,
input [1:0] VAR4,
input VAR127,
input VAR239,
input [VAR137 -1:0] VAR184,
output VAR157, input VAR2, output VAR63 , output VAR104, output [VAR209-1:0] VAR172,
input VAR17,
input VAR181,
output VAR158,
input [VAR142-1:0] VAR268,
input VAR71,
input [VAR209-1:0] VAR64,
input [VAR209/8-1:0] VAR186,
input VAR180,
input VAR183,
input [1:0] VAR256,
output VAR212,
input VAR105,
output VAR155 ,
output VAR177,
output [VAR209-1:0] VAR188,
input VAR116,
output [VAR142-1:0] VAR39,
output VAR29,
output [VAR209-1:0] VAR175,
output [VAR209/8-1:0] VAR171,
output VAR125,
output VAR246,
output [1:0] VAR32,
input VAR154,
output VAR121,
input VAR123 ,
output VAR55,
input [VAR209-1:0] VAR19,
input VAR197,
output [VAR136-1:0] VAR99,
output VAR151,
output [VAR209-1:0] VAR149,
output [VAR209/8-1:0] VAR219,
output VAR120,
output VAR238,
output [1:0] VAR179,
input VAR90,
output VAR132,
input VAR26 ,
input VAR21,
input [VAR209-1:0] VAR84,
input VAR72,
output [VAR257-1:0] VAR1,
output VAR94,
output [VAR209-1:0] VAR101,
output [VAR209/8-1:0] VAR272,
output VAR23,
output VAR69,
output [1:0] VAR110,
input VAR119,
output VAR267,
input VAR182 ,
input VAR80 ,
input [VAR209-1:0] VAR225,
output VAR176,
input VAR275,
output [VAR142-1:0] VAR166,
output VAR134,
output [VAR209-1:0] VAR223,
output [VAR209/8-1:0] VAR102,
output VAR140,
output VAR216,
output [1:0] VAR195,
input VAR262,
output VAR70,
input VAR108 ,
input VAR45 ,
input [VAR209-1:0] VAR237,
input clk,
input VAR276
);
wire VAR143;
wire VAR191;
assign VAR143 = (~VAR17) & VAR33;
assign VAR222 = (~VAR17) & VAR191;
localparam VAR68 = 2;
localparam VAR131 = 1;
VAR81 VAR67 VAR178 VAR249 VAR230 VAR228?
wire VAR253;
wire VAR264 ;
wire VAR58;
wire [VAR209-1:0] VAR227;
wire VAR96;
wire VAR211;
wire VAR258;
wire VAR138;
wire [2-1:0] VAR114;
wire [VAR137 -1:0] VAR36;
wire [VAR142-1:0] VAR156;
localparam VAR232 = (VAR137+6+VAR142);
localparam VAR122 = 0; wire [VAR232-1:0] VAR217 =
{
VAR127
,VAR239
,VAR75
,VAR4
,VAR184
,VAR62
,VAR251
};
wire [VAR232-1:0] VAR229 = {VAR232-1{1'b0}};
wire [VAR232-1:0] VAR231 = {VAR232-1{1'b0}};
wire [VAR232-1:0] VAR199;
assign
{
VAR96
,VAR211
,VAR258
,VAR114
,VAR36
,VAR156
,VAR138
} = VAR199;
wire [VAR232-1:0] VAR56;
wire [VAR232-1:0] VAR185;
wire VAR278;
wire VAR109;
wire [VAR142-1:0] VAR97;
wire VAR152;
wire [VAR209-1:0] VAR269;
wire [VAR209/8-1:0] VAR42;
wire VAR153;
wire VAR250;
wire [1:0] VAR53;
wire [1:0] VAR86;
wire [1:0] VAR18;
wire [VAR232-1:0] VAR76;
wire VAR3;
wire VAR236;
wire VAR115;
wire VAR165;
wire [VAR209-1:0] VAR208;
wire [VAR232-1:0] VAR254;
wire [VAR68*1-1:0] VAR265;
wire [VAR68*1-1:0] VAR100;
wire [VAR68*VAR142-1:0] VAR215;
wire [VAR68*1-1:0] VAR210;
wire [VAR68*VAR209-1:0] VAR30;
wire [VAR68*VAR209/8-1:0] VAR54;
wire [VAR68*1-1:0] VAR244;
wire [VAR68*1-1:0] VAR277;
wire [VAR68*2-1:0] VAR12;
wire [VAR68*VAR232-1:0] VAR66;
wire [VAR68*2-1:0] VAR20;
wire [VAR68*2-1:0] VAR14;
wire [VAR68*1-1:0] VAR11;
wire [VAR68*1-1:0] VAR6;
wire [VAR68*1-1:0] VAR51;
wire [VAR68*1-1:0] VAR261;
wire [VAR68*VAR209-1:0] VAR190;
wire [VAR68*VAR232-1:0] VAR77;
wire [VAR68*1-1:0] VAR130;
assign VAR130 =
{
VAR33
, VAR181
} ;
assign VAR265 =
{
VAR143
, VAR181
} ;
assign VAR215 =
{
VAR62
, VAR268
} ;
assign VAR210 =
{
VAR75
, VAR71
} ;
assign VAR30 =
{
VAR147
, VAR64
} ;
assign VAR54 =
{
VAR194
, VAR186
} ;
assign VAR244 =
{
VAR133
, VAR180
} ;
assign VAR20 =
{
2'b0
, 2'b0
} ;
assign VAR14 =
{
1'b0
, 1'b0
} ;
assign VAR277 =
{
VAR251
, VAR183
} ;
assign VAR12 =
{
VAR4
, VAR256
} ;
assign VAR66 =
{
VAR217
, VAR229
} ;
assign {
VAR191
, VAR158
} = VAR100;
assign {
VAR57
, VAR212
} = VAR11;
assign {
VAR264
, VAR155
} = VAR51;
assign {
VAR58
, VAR177
} = VAR261;
assign {
VAR227
, VAR188
} = VAR190;
assign {
VAR199
, VAR56
} = VAR77;
assign VAR6 = {
VAR253
, VAR105
};
VAR187 # (
.VAR193 (0), .VAR112 (0), .VAR213 (VAR16),
.VAR40 (0),
.VAR203 (VAR68),
.VAR59 (VAR131),
.VAR232 (VAR232),
.VAR220 (VAR142),
.VAR252 (VAR209)
) VAR174(
.VAR150 (VAR278 ) ,
.VAR88 (VAR109 ) ,
.VAR61 (VAR152 ) ,
.VAR10 (VAR97 ) ,
.VAR226 (VAR269 ) ,
.VAR271 (VAR42) ,
.VAR204 (VAR86) ,
.VAR95 (VAR18 ) ,
.VAR160 (VAR250 ) ,
.VAR35 (VAR153 ) ,
.VAR89 (VAR53 ) ,
.VAR260 (VAR76 ) ,
.VAR241 (VAR3 ) ,
.VAR235 (VAR236 ) ,
.VAR5 (VAR115) ,
.VAR128 (VAR165) ,
.VAR98 (VAR208 ) ,
.VAR117 (VAR254 ) ,
.VAR242 (VAR100 ) ,
.VAR192 (VAR265 ) ,
.VAR49 (VAR210 ) ,
.VAR170 (VAR215 ) ,
.VAR243 (VAR30 ) ,
.VAR41 (VAR54) ,
.VAR162 (VAR20) ,
.VAR198 (VAR14 ) ,
.VAR47 (VAR277 ) ,
.VAR107 (VAR244 ) ,
.VAR189 (VAR12 ) ,
.VAR205 (VAR66 ) ,
.VAR34 (VAR11 ) ,
.VAR218 (VAR6 ) ,
.VAR126 (VAR51) ,
.VAR221 (VAR261),
.VAR73 (VAR190 ) ,
.VAR7 (VAR77) ,
.clk (clk ),
.VAR276 (VAR276)
);
wire VAR247 = (~VAR141) & (~VAR82) & (~VAR43);
wire VAR13 = VAR278 & VAR109;
wire VAR146 = VAR3 & VAR236;
wire VAR15;
wire [VAR142-1:0] VAR233;
wire VAR113 = (VAR97 == VAR233);
wire VAR28 = VAR13 & VAR76[VAR122] & VAR152 & VAR250;
wire VAR46 = (VAR13 & (~VAR152) & VAR113 & VAR15)
| VAR27 | VAR8;
wire VAR145 = VAR28 | VAR46;
wire VAR24 = VAR28 | (~VAR46);
VAR248 #(1) VAR92 (VAR145, VAR24, VAR15, clk, VAR276);
wire VAR263 = VAR28;
wire [VAR142-1:0] VAR106 = VAR97;
VAR248 #(VAR142) VAR111 (VAR263, VAR106, VAR233, clk, VAR276);
wire VAR135 = VAR76[VAR122] & (~VAR152);
wire VAR50 = VAR135 & VAR113 & VAR15;
wire VAR245;
wire VAR201 = VAR13;
wire VAR44 = (~VAR245);
wire VAR78;
wire VAR83 = VAR146;
wire VAR273 = (~VAR78);
wire VAR79;
wire VAR202;
wire VAR173;
wire VAR169;
wire VAR196;
wire [VAR209/8-1:0] VAR214 =
(VAR135 & (~VAR50)) ? {VAR209/8{1'b0}} : VAR42;
wire [VAR209/8-1:0] VAR214 = VAR42;
wire [VAR60-1:0] VAR163;
wire [VAR60-1:0] VAR234;
assign VAR163 = {
VAR247,
VAR43,
VAR82,
VAR141,
};
assign
{
VAR79,
VAR202,
VAR173,
VAR169,
} = VAR234 & {VAR60{VAR78}};
.VAR31(0),
.VAR91(1),
.VAR252(VAR60)
) VAR270 (
.VAR167 (VAR201),
.VAR164 (VAR245),
.VAR161 (VAR163 ),
.VAR48 (VAR78),
.VAR38 (VAR83),
.VAR224 (VAR234 ),
.clk (clk),
.VAR276(VAR276)
);
.VAR31 (0), .VAR139 (0),
.VAR91 (VAR16),
.VAR252 (VAR60) ) VAR274 (
.VAR167 (VAR201),
.VAR164 (VAR245),
.VAR161 (VAR163 ),
.VAR48 (VAR78),
.VAR38 (VAR83),
.VAR224 (VAR234 ),
.clk (clk),
.VAR276(VAR276)
);
(~({VAR247, VAR43, VAR82, VAR141}
== {VAR79, VAR202, VAR173, VAR169}));
wire VAR148 = (~VAR44) & (~VAR159);
wire VAR266;
wire VAR240 = VAR148 & VAR278;
assign VAR109 = VAR148 & VAR266;
wire VAR87;
wire VAR118;
wire VAR259;
wire VAR22;
wire VAR93;
assign VAR39 = VAR97 ;
assign VAR29 = VAR152 ;
assign VAR175 = VAR269;
assign VAR171 = VAR214;
assign VAR125 = VAR153 ;
assign VAR246 = VAR250 ;
assign VAR32 = VAR53 ;
assign VAR99 = VAR97 [VAR136-1:0];
assign VAR151 = VAR152 ;
assign VAR149 = VAR269;
assign VAR219 = VAR214;
assign VAR120 = VAR153 ;
assign VAR238 = VAR250 ;
assign VAR179 = VAR53 ;
assign VAR1 = VAR97 [VAR257-1:0];
assign VAR94 = VAR152 ;
assign VAR101 = VAR269;
assign VAR272 = VAR214;
assign VAR23 = VAR153 ;
assign VAR69 = VAR250 ;
assign VAR110 = VAR53 ;
assign VAR176 = VAR240 & VAR247 & VAR118;
assign VAR166 = VAR97 ;
assign VAR134 = VAR152 ;
assign VAR223 = VAR269;
assign VAR102 = VAR214;
assign VAR140 = VAR153 ;
assign VAR216 = VAR250 ;
assign VAR195 = VAR53 ;
assign VAR87 =
(VAR275 )
assign VAR118 =
1'b1
assign VAR259 =
(VAR275 )
assign VAR22 =
(VAR275 )
assign VAR93 =
(VAR275 )
assign VAR266 = VAR87;
assign {
VAR3
, VAR115
, VAR165
, VAR208
} =
({VAR209+3{VAR79}} &
{ VAR262
, VAR108
, VAR45
, VAR237
}
)
{ VAR154
, VAR123
, VAR55
, VAR19
}
)
{ VAR90
, VAR26
, VAR21
, VAR84
}
)
{ VAR119
, VAR182
, VAR80
, VAR225
}
)
assign VAR70 = VAR79 & VAR236;
assign VAR144 = VAR57 & (~VAR96);
assign VAR157 = VAR57 & VAR96;
assign VAR253 =
VAR96 ? VAR2 : VAR25;
assign VAR63 = VAR264 ;
assign VAR104 = VAR58 ;
assign VAR172 = VAR227;
assign VAR9 = VAR36;
wire [VAR209-1:0] VAR52 =
(VAR227 >> {VAR156[1:0],3'b0});
wire VAR37 = (VAR114 == 2'b00) & (VAR211 == 1'b1);
wire VAR129 = (VAR114 == 2'b00) & (VAR211 == 1'b0);
wire VAR279 = (VAR114 == 2'b01) & (VAR211 == 1'b1);
wire VAR206 = (VAR114 == 2'b01) & (VAR211 == 1'b0);
wire VAR74 = (VAR114 == 2'b10);
assign VAR168 = ((~VAR258) & VAR138) ? VAR207 :
( ({VAR209{VAR37}} & {{24{ 1'b0}}, VAR52[ 7:0]})
| ({VAR209{VAR129 }} & {{24{VAR52[ 7]}}, VAR52[ 7:0]})
| ({VAR209{VAR279}} & {{16{ 1'b0}}, VAR52[15:0]})
| ({VAR209{VAR206 }} & {{16{VAR52[15]}}, VAR52[15:0]})
| ({VAR209{VAR74 }} & VAR52[31:0]));
assign VAR124 = VAR264;
assign VAR200 = VAR264; assign VAR85 = VAR156;
assign VAR255= VAR258;
assign VAR65= ~VAR258;
assign VAR103 = (|VAR130) | VAR78;
endmodule
|
apache-2.0
|
FAST-Switch/fast
|
projects/SDTS/example/hw-src/cdp/ddio_out_1.v
| 4,804 |
module MODULE1 (
VAR10,
VAR24,
VAR19,
VAR6,
VAR15);
input VAR10;
input VAR24;
input VAR19;
input VAR6;
output VAR15;
tri0 VAR10;
wire [0:0] VAR17;
wire [0:0] VAR5 = VAR17[0:0];
wire VAR15 = VAR5;
wire VAR1 = VAR24;
wire VAR18 = VAR1;
wire VAR3 = VAR19;
wire VAR14 = VAR3;
VAR4 VAR2 (
.VAR6 (VAR6),
.VAR24 (VAR18),
.VAR10 (VAR10),
.VAR19 (VAR14),
.VAR15 (VAR17),
.VAR27 (1'b0),
.VAR12 (1'b1),
.VAR9 (),
.VAR25 (1'b1),
.VAR28 (1'b0),
.VAR8 (1'b0));
VAR2.VAR26 = "VAR21",
VAR2.VAR16 = "VAR23 VAR13 VAR11",
VAR2.VAR7 = "VAR4",
VAR2.VAR20 = "VAR21",
VAR2.VAR22 = 1;
endmodule
|
apache-2.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v
| 27,569 |
module MODULE4 (
clk,
reset,
VAR64,
VAR188,
VAR116,
VAR81,
VAR132
);
parameter VAR71 = 18;
parameter VAR183 = 38;
parameter VAR113 = 19;
localparam VAR85 = 45;
input clk;
input reset;
input VAR64;
input VAR188;
input [VAR71-1:0] VAR116; output VAR81;
output [VAR71-1:0] VAR132;
localparam VAR26 = 18; localparam VAR118 = 36; localparam VAR147 = 17;
localparam VAR221 = 38;
reg [VAR71-1:0] VAR41;
reg [VAR71-1:0] VAR167;
reg [VAR71-1:0] VAR164;
reg [VAR71-1:0] VAR24;
reg [VAR71-1:0] VAR148;
reg [VAR71-1:0] VAR186;
reg [VAR71-1:0] VAR208;
reg [VAR71-1:0] VAR227;
reg [VAR71-1:0] VAR150;
reg [VAR71-1:0] VAR211;
reg [VAR71-1:0] VAR72;
reg [VAR71-1:0] VAR48;
reg [VAR71-1:0] VAR222;
reg [VAR71-1:0] VAR15;
reg [VAR71-1:0] VAR160;
reg [VAR71-1:0] VAR130;
reg [VAR71-1:0] VAR194;
reg [VAR71-1:0] VAR156;
reg [VAR71-1:0] VAR145;
always@(posedge clk) begin
VAR41 <= 18'd88;
VAR167 <= 18'd0;
VAR164 <= -18'd97;
VAR24 <= -18'd197;
VAR148 <= -18'd294;
VAR186 <= -18'd380;
VAR208 <= -18'd447;
VAR227 <= -18'd490;
VAR150 <= -18'd504;
VAR211 <= -18'd481;
VAR72 <= -18'd420;
VAR48 <= -18'd319;
VAR222 <= -18'd178;
VAR15 <= 18'd0;
VAR160 <= 18'd212;
VAR130 <= 18'd451;
VAR194 <= 18'd710;
VAR156 <= 18'd980;
VAR145 <= 18'd1252;
end
reg [VAR85-1:0] VAR13;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR13 <= 0;
end else begin
if(VAR64) begin
VAR13 <= {VAR13[VAR85-2:0], VAR188};
end else begin
VAR13 <= VAR13;
end
end
end
wire [VAR71-1:0] VAR78;
wire [VAR71-1:0] VAR87;
wire [VAR71-1:0] VAR74;
wire [VAR71-1:0] VAR202;
wire [VAR71-1:0] VAR190;
wire [VAR71-1:0] VAR47;
wire [VAR71-1:0] VAR59;
wire [VAR71-1:0] VAR107;
wire [VAR71-1:0] VAR209;
wire [VAR71-1:0] VAR165;
wire [VAR71-1:0] VAR77;
wire [VAR71-1:0] VAR90;
wire [VAR71-1:0] VAR103;
wire [VAR71-1:0] VAR91;
wire [VAR71-1:0] VAR6;
wire [VAR71-1:0] VAR2;
wire [VAR71-1:0] VAR216;
wire [VAR71-1:0] VAR204;
wire [VAR71-1:0] VAR68;
wire [VAR71-1:0] VAR117;
wire [VAR71-1:0] VAR185;
wire [VAR71-1:0] VAR55;
wire [VAR71-1:0] VAR171;
wire [VAR71-1:0] VAR127;
wire [VAR71-1:0] VAR198;
wire [VAR71-1:0] VAR189;
wire [VAR71-1:0] VAR44;
wire [VAR71-1:0] VAR162;
wire [VAR71-1:0] VAR105;
wire [VAR71-1:0] VAR31;
wire [VAR71-1:0] VAR30;
wire [VAR71-1:0] VAR212;
wire [VAR71-1:0] VAR65;
wire [VAR71-1:0] VAR11;
wire [VAR71-1:0] VAR124;
wire [VAR71-1:0] VAR82;
wire [VAR71-1:0] VAR76;
wire [VAR71-1:0] VAR106;
MODULE5 MODULE19(
.clk(clk), .VAR64(VAR64),
.VAR100(VAR116),
.VAR134(VAR78),
.VAR80(VAR87),
.VAR111(VAR74),
.VAR138(VAR202),
.VAR141(VAR190),
.VAR32(VAR47),
.VAR43(VAR59),
.VAR170(VAR107),
.VAR54(VAR209),
.VAR180(VAR165),
.VAR109(VAR77),
.VAR79(VAR90),
.VAR37(VAR103),
.VAR53(VAR91),
.VAR195(VAR6),
.VAR191(VAR2),
.VAR205(VAR216),
.VAR18(VAR204),
.VAR178(VAR68),
.VAR169(VAR117),
.VAR73(VAR185),
.VAR184(VAR55),
.VAR166(VAR171),
.VAR75(VAR127),
.VAR223(VAR198),
.VAR215(VAR189),
.VAR35(VAR44),
.VAR61(VAR162),
.VAR133(VAR105),
.VAR16(VAR31),
.VAR179(VAR30),
.VAR143(VAR212),
.VAR231(VAR65),
.VAR126(VAR11),
.VAR29(VAR124),
.VAR144(VAR82),
.VAR135(VAR76),
.VAR142(VAR106),
.reset(reset) );
wire [VAR71-1:0] VAR218;
wire [VAR71-1:0] VAR84;
wire [VAR71-1:0] VAR110;
wire [VAR71-1:0] VAR123;
wire [VAR71-1:0] VAR7;
wire [VAR71-1:0] VAR157;
wire [VAR71-1:0] VAR176;
wire [VAR71-1:0] VAR193;
wire [VAR71-1:0] VAR177;
wire [VAR71-1:0] VAR62;
wire [VAR71-1:0] VAR25;
wire [VAR71-1:0] VAR40;
wire [VAR71-1:0] VAR228;
wire [VAR71-1:0] VAR52;
wire [VAR71-1:0] VAR104;
wire [VAR71-1:0] VAR214;
wire [VAR71-1:0] VAR38;
wire [VAR71-1:0] VAR98;
wire [VAR71-1:0] VAR28;
MODULE1 VAR97(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR78),
.VAR175 (VAR106),
.VAR159(VAR218)
);
MODULE1 VAR102(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR87),
.VAR175 (VAR76),
.VAR159(VAR84)
);
MODULE1 VAR42(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR74),
.VAR175 (VAR82),
.VAR159(VAR110)
);
MODULE1 VAR1(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR202),
.VAR175 (VAR124),
.VAR159(VAR123)
);
MODULE1 VAR12(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR190),
.VAR175 (VAR11),
.VAR159(VAR7)
);
MODULE1 VAR39(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR47),
.VAR175 (VAR65),
.VAR159(VAR157)
);
MODULE1 VAR69(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR59),
.VAR175 (VAR212),
.VAR159(VAR176)
);
MODULE1 VAR153(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR107),
.VAR175 (VAR30),
.VAR159(VAR193)
);
MODULE1 VAR151(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR209),
.VAR175 (VAR31),
.VAR159(VAR177)
);
MODULE1 VAR155(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR165),
.VAR175 (VAR105),
.VAR159(VAR62)
);
MODULE1 VAR199(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR77),
.VAR175 (VAR162),
.VAR159(VAR25)
);
MODULE1 VAR88(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR90),
.VAR175 (VAR44),
.VAR159(VAR40)
);
MODULE1 VAR33(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR103),
.VAR175 (VAR189),
.VAR159(VAR228)
);
MODULE1 VAR181(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR91),
.VAR175 (VAR198),
.VAR159(VAR52)
);
MODULE1 VAR50(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR6),
.VAR175 (VAR127),
.VAR159(VAR104)
);
MODULE1 VAR174(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR2),
.VAR175 (VAR171),
.VAR159(VAR214)
);
MODULE1 VAR131(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR216),
.VAR175 (VAR55),
.VAR159(VAR38)
);
MODULE1 VAR158(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR204),
.VAR175 (VAR185),
.VAR159(VAR98)
);
MODULE1 VAR45(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR68),
.VAR175 (VAR117),
.VAR159(VAR28)
);
wire [VAR71-1:0] VAR182;
wire [VAR71-1:0] VAR230;
wire [VAR71-1:0] VAR115;
wire [VAR71-1:0] VAR112;
wire [VAR71-1:0] VAR3;
wire [VAR71-1:0] VAR197;
wire [VAR71-1:0] VAR232;
wire [VAR71-1:0] VAR163;
wire [VAR71-1:0] VAR99;
wire [VAR71-1:0] VAR119;
wire [VAR71-1:0] VAR140;
wire [VAR71-1:0] VAR21;
wire [VAR71-1:0] VAR66;
wire [VAR71-1:0] VAR226;
wire [VAR71-1:0] VAR187;
wire [VAR71-1:0] VAR114;
wire [VAR71-1:0] VAR161;
wire [VAR71-1:0] VAR217;
wire [VAR71-1:0] VAR27;
MODULE2 VAR70(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR218),
.VAR175 (VAR41),
.VAR159(VAR182)
);
MODULE2 VAR225(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR84),
.VAR175 (VAR167),
.VAR159(VAR230)
);
MODULE2 VAR56(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR110),
.VAR175 (VAR164),
.VAR159(VAR115)
);
MODULE2 VAR10(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR123),
.VAR175 (VAR24),
.VAR159(VAR112)
);
MODULE2 VAR200(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR7),
.VAR175 (VAR148),
.VAR159(VAR3)
);
MODULE2 VAR233(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR157),
.VAR175 (VAR186),
.VAR159(VAR197)
);
MODULE2 VAR203(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR176),
.VAR175 (VAR208),
.VAR159(VAR232)
);
MODULE2 VAR128(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR193),
.VAR175 (VAR227),
.VAR159(VAR163)
);
MODULE2 VAR168(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR177),
.VAR175 (VAR150),
.VAR159(VAR99)
);
MODULE2 VAR83(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR62),
.VAR175 (VAR211),
.VAR159(VAR119)
);
MODULE2 VAR17(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR25),
.VAR175 (VAR72),
.VAR159(VAR140)
);
MODULE2 VAR60(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR40),
.VAR175 (VAR48),
.VAR159(VAR21)
);
MODULE2 VAR122(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR228),
.VAR175 (VAR222),
.VAR159(VAR66)
);
MODULE2 VAR201(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR52),
.VAR175 (VAR15),
.VAR159(VAR226)
);
MODULE2 VAR149(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR104),
.VAR175 (VAR160),
.VAR159(VAR187)
);
MODULE2 VAR121(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR214),
.VAR175 (VAR130),
.VAR159(VAR114)
);
MODULE2 VAR137(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR38),
.VAR175 (VAR194),
.VAR159(VAR161)
);
MODULE2 VAR20(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR98),
.VAR175 (VAR156),
.VAR159(VAR217)
);
MODULE2 VAR96(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR28),
.VAR175 (VAR145),
.VAR159(VAR27)
);
wire [VAR71-1:0] VAR207;
wire [VAR71-1:0] VAR210;
wire [VAR71-1:0] VAR206;
wire [VAR71-1:0] VAR229;
wire [VAR71-1:0] VAR146;
wire [VAR71-1:0] VAR34;
wire [VAR71-1:0] VAR58;
wire [VAR71-1:0] VAR23;
wire [VAR71-1:0] VAR196;
wire [VAR71-1:0] VAR213;
MODULE1 VAR63(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR182),
.VAR175 (VAR230),
.VAR159(VAR207)
);
MODULE1 VAR67(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR115),
.VAR175 (VAR112),
.VAR159(VAR210)
);
MODULE1 VAR51(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR3),
.VAR175 (VAR197),
.VAR159(VAR206)
);
MODULE1 VAR4(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR232),
.VAR175 (VAR163),
.VAR159(VAR229)
);
MODULE1 VAR173(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR99),
.VAR175 (VAR119),
.VAR159(VAR146)
);
MODULE1 VAR86(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR140),
.VAR175 (VAR21),
.VAR159(VAR34)
);
MODULE1 VAR125(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR66),
.VAR175 (VAR226),
.VAR159(VAR58)
);
MODULE1 VAR9(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR187),
.VAR175 (VAR114),
.VAR159(VAR23)
);
MODULE1 VAR92(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR161),
.VAR175 (VAR217),
.VAR159(VAR196)
);
MODULE3 VAR94(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR27),
.VAR159(VAR213)
);
wire [VAR71-1:0] VAR172;
wire [VAR71-1:0] VAR57;
wire [VAR71-1:0] VAR19;
wire [VAR71-1:0] VAR219;
wire [VAR71-1:0] VAR101;
MODULE1 VAR93(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR207),
.VAR175 (VAR210),
.VAR159(VAR172)
);
MODULE1 VAR136(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR206),
.VAR175 (VAR229),
.VAR159(VAR57)
);
MODULE1 VAR5(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR146),
.VAR175 (VAR34),
.VAR159(VAR19)
);
MODULE1 VAR220(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR58),
.VAR175 (VAR23),
.VAR159(VAR219)
);
MODULE1 VAR192(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR196),
.VAR175 (VAR213),
.VAR159(VAR101)
);
wire [VAR71-1:0] VAR224;
wire [VAR71-1:0] VAR8;
wire [VAR71-1:0] VAR89;
MODULE1 VAR46(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR172),
.VAR175 (VAR57),
.VAR159(VAR224)
);
MODULE1 VAR154(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR19),
.VAR175 (VAR219),
.VAR159(VAR8)
);
MODULE3 VAR49(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR101),
.VAR159(VAR89)
);
wire [VAR71-1:0] VAR36;
wire [VAR71-1:0] VAR95;
MODULE1 VAR108(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR224),
.VAR175 (VAR8),
.VAR159(VAR36)
);
MODULE3 VAR152(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR89),
.VAR159(VAR95)
);
wire [VAR71-1:0] VAR14;
MODULE1 VAR120(
.clk(clk), .VAR64(VAR64),
.VAR22 (VAR36),
.VAR175 (VAR95),
.VAR159(VAR14)
);
assign VAR132 = VAR14;
assign VAR81 = VAR13[VAR85-1];
endmodule
module MODULE5 (
clk,
VAR64,
VAR100,
VAR134,
VAR80,
VAR111,
VAR138,
VAR141,
VAR32,
VAR43,
VAR170,
VAR54,
VAR180,
VAR109,
VAR79,
VAR37,
VAR53,
VAR195,
VAR191,
VAR205,
VAR18,
VAR178,
VAR169,
VAR73,
VAR184,
VAR166,
VAR75,
VAR223,
VAR215,
VAR35,
VAR61,
VAR133,
VAR16,
VAR179,
VAR143,
VAR231,
VAR126,
VAR29,
VAR144,
VAR135,
VAR142,
reset);
parameter VAR139 = 1;
input clk;
input VAR64;
input [VAR139-1:0] VAR100;
output [VAR139-1:0] VAR134;
output [VAR139-1:0] VAR80;
output [VAR139-1:0] VAR111;
output [VAR139-1:0] VAR138;
output [VAR139-1:0] VAR141;
output [VAR139-1:0] VAR32;
output [VAR139-1:0] VAR43;
output [VAR139-1:0] VAR170;
output [VAR139-1:0] VAR54;
output [VAR139-1:0] VAR180;
output [VAR139-1:0] VAR109;
output [VAR139-1:0] VAR79;
output [VAR139-1:0] VAR37;
output [VAR139-1:0] VAR53;
output [VAR139-1:0] VAR195;
output [VAR139-1:0] VAR191;
output [VAR139-1:0] VAR205;
output [VAR139-1:0] VAR18;
output [VAR139-1:0] VAR178;
output [VAR139-1:0] VAR169;
output [VAR139-1:0] VAR73;
output [VAR139-1:0] VAR184;
output [VAR139-1:0] VAR166;
output [VAR139-1:0] VAR75;
output [VAR139-1:0] VAR223;
output [VAR139-1:0] VAR215;
output [VAR139-1:0] VAR35;
output [VAR139-1:0] VAR61;
output [VAR139-1:0] VAR133;
output [VAR139-1:0] VAR16;
output [VAR139-1:0] VAR179;
output [VAR139-1:0] VAR143;
output [VAR139-1:0] VAR231;
output [VAR139-1:0] VAR126;
output [VAR139-1:0] VAR29;
output [VAR139-1:0] VAR144;
output [VAR139-1:0] VAR135;
output [VAR139-1:0] VAR142;
reg [VAR139-1:0] VAR134;
reg [VAR139-1:0] VAR80;
reg [VAR139-1:0] VAR111;
reg [VAR139-1:0] VAR138;
reg [VAR139-1:0] VAR141;
reg [VAR139-1:0] VAR32;
reg [VAR139-1:0] VAR43;
reg [VAR139-1:0] VAR170;
reg [VAR139-1:0] VAR54;
reg [VAR139-1:0] VAR180;
reg [VAR139-1:0] VAR109;
reg [VAR139-1:0] VAR79;
reg [VAR139-1:0] VAR37;
reg [VAR139-1:0] VAR53;
reg [VAR139-1:0] VAR195;
reg [VAR139-1:0] VAR191;
reg [VAR139-1:0] VAR205;
reg [VAR139-1:0] VAR18;
reg [VAR139-1:0] VAR178;
reg [VAR139-1:0] VAR169;
reg [VAR139-1:0] VAR73;
reg [VAR139-1:0] VAR184;
reg [VAR139-1:0] VAR166;
reg [VAR139-1:0] VAR75;
reg [VAR139-1:0] VAR223;
reg [VAR139-1:0] VAR215;
reg [VAR139-1:0] VAR35;
reg [VAR139-1:0] VAR61;
reg [VAR139-1:0] VAR133;
reg [VAR139-1:0] VAR16;
reg [VAR139-1:0] VAR179;
reg [VAR139-1:0] VAR143;
reg [VAR139-1:0] VAR231;
reg [VAR139-1:0] VAR126;
reg [VAR139-1:0] VAR29;
reg [VAR139-1:0] VAR144;
reg [VAR139-1:0] VAR135;
reg [VAR139-1:0] VAR142;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR134 <= 0;
VAR80 <= 0;
VAR111 <= 0;
VAR138 <= 0;
VAR141 <= 0;
VAR32 <= 0;
VAR43 <= 0;
VAR170 <= 0;
VAR54 <= 0;
VAR180 <= 0;
VAR109 <= 0;
VAR79 <= 0;
VAR37 <= 0;
VAR53 <= 0;
VAR195 <= 0;
VAR191 <= 0;
VAR205 <= 0;
VAR18 <= 0;
VAR178 <= 0;
VAR169 <= 0;
VAR73 <= 0;
VAR184 <= 0;
VAR166 <= 0;
VAR75 <= 0;
VAR223 <= 0;
VAR215 <= 0;
VAR35 <= 0;
VAR61 <= 0;
VAR133 <= 0;
VAR16 <= 0;
VAR179 <= 0;
VAR143 <= 0;
VAR231 <= 0;
VAR126 <= 0;
VAR29 <= 0;
VAR144 <= 0;
VAR135 <= 0;
VAR142 <= 0;
end else begin
if(VAR64) begin
VAR134 <= VAR100;
VAR80 <= VAR134;
VAR111 <= VAR80;
VAR138 <= VAR111;
VAR141 <= VAR138;
VAR32 <= VAR141;
VAR43 <= VAR32;
VAR170 <= VAR43;
VAR54 <= VAR170;
VAR180 <= VAR54;
VAR109 <= VAR180;
VAR79 <= VAR109;
VAR37 <= VAR79;
VAR53 <= VAR37;
VAR195 <= VAR53;
VAR191 <= VAR195;
VAR205 <= VAR191;
VAR18 <= VAR205;
VAR178 <= VAR18;
VAR169 <= VAR178;
VAR73 <= VAR169;
VAR184 <= VAR73;
VAR166 <= VAR184;
VAR75 <= VAR166;
VAR223 <= VAR75;
VAR215 <= VAR223;
VAR35 <= VAR215;
VAR61 <= VAR35;
VAR133 <= VAR61;
VAR16 <= VAR133;
VAR179 <= VAR16;
VAR143 <= VAR179;
VAR231 <= VAR143;
VAR126 <= VAR231;
VAR29 <= VAR126;
VAR144 <= VAR29;
VAR135 <= VAR144;
VAR142 <= VAR135;
end end
end
endmodule
module MODULE1 (
clk,
VAR64,
VAR22,
VAR175,
VAR159);
input clk;
input VAR64;
input [17:0] VAR22;
input [17:0] VAR175;
output [17:0] VAR159;
reg [17:0] VAR159;
always @(posedge clk) begin
if(VAR64) begin
VAR159 <= VAR22 + VAR175;
end
end
endmodule
module MODULE2 (
clk,
VAR64,
VAR22,
VAR175,
VAR159);
input clk;
input VAR64;
input [17:0] VAR22;
input [17:0] VAR175;
output [17:0] VAR159;
reg [17:0] VAR159;
always @(posedge clk) begin
if(VAR64) begin
VAR159 <= VAR22 * VAR175;
end
end
endmodule
module MODULE3 (
clk,
VAR64,
VAR22,
VAR159);
input clk;
input VAR64;
input [17:0] VAR22;
output [17:0] VAR159;
reg [17:0] VAR159;
always @(posedge clk) begin
if(VAR64) begin
VAR159 <= VAR22;
end
end
endmodule
|
mit
|
wgml/sysrek
|
rgb2hsv/ipcore_dir/mul10.v
| 26,635 |
module MODULE1 (
clk, VAR58, VAR48, VAR32
);
input clk;
input [9 : 0] VAR58;
input [9 : 0] VAR48;
output [19 : 0] VAR32;
wire \VAR96/VAR42 ;
wire \VAR96/VAR95 ;
wire \VAR33/VAR13 ;
wire \VAR33/VAR50 ;
wire \VAR33/VAR97<17>VAR20 ;
wire \VAR33/VAR97<16>VAR20 ;
wire \VAR33/VAR97<15>VAR20 ;
wire \VAR33/VAR97<14>VAR20 ;
wire \VAR33/VAR97<13>VAR20 ;
wire \VAR33/VAR97<12>VAR20 ;
wire \VAR33/VAR97<11>VAR20 ;
wire \VAR33/VAR97<10>VAR20 ;
wire \VAR33/VAR97<9>VAR20 ;
wire \VAR33/VAR97<8>VAR20 ;
wire \VAR33/VAR97<7>VAR20 ;
wire \VAR33/VAR97<6>VAR20 ;
wire \VAR33/VAR97<5>VAR20 ;
wire \VAR33/VAR97<4>VAR20 ;
wire \VAR33/VAR97<3>VAR20 ;
wire \VAR33/VAR97<2>VAR20 ;
wire \VAR33/VAR97<1>VAR20 ;
wire \VAR33/VAR97<0>VAR20 ;
wire \VAR33/VAR10<47>VAR20 ;
wire \VAR33/VAR10<46>VAR20 ;
wire \VAR33/VAR10<45>VAR20 ;
wire \VAR33/VAR10<44>VAR20 ;
wire \VAR33/VAR10<43>VAR20 ;
wire \VAR33/VAR10<42>VAR20 ;
wire \VAR33/VAR10<41>VAR20 ;
wire \VAR33/VAR10<40>VAR20 ;
wire \VAR33/VAR10<39>VAR20 ;
wire \VAR33/VAR10<38>VAR20 ;
wire \VAR33/VAR10<37>VAR20 ;
wire \VAR33/VAR10<36>VAR20 ;
wire \VAR33/VAR10<35>VAR20 ;
wire \VAR33/VAR10<34>VAR20 ;
wire \VAR33/VAR10<33>VAR20 ;
wire \VAR33/VAR10<32>VAR20 ;
wire \VAR33/VAR10<31>VAR20 ;
wire \VAR33/VAR10<30>VAR20 ;
wire \VAR33/VAR10<29>VAR20 ;
wire \VAR33/VAR10<28>VAR20 ;
wire \VAR33/VAR10<27>VAR20 ;
wire \VAR33/VAR10<26>VAR20 ;
wire \VAR33/VAR10<25>VAR20 ;
wire \VAR33/VAR10<24>VAR20 ;
wire \VAR33/VAR10<23>VAR20 ;
wire \VAR33/VAR10<22>VAR20 ;
wire \VAR33/VAR10<21>VAR20 ;
wire \VAR33/VAR10<20>VAR20 ;
wire \VAR33/VAR10<19>VAR20 ;
wire \VAR33/VAR10<18>VAR20 ;
wire \VAR33/VAR10<17>VAR20 ;
wire \VAR33/VAR10<16>VAR20 ;
wire \VAR33/VAR10<15>VAR20 ;
wire \VAR33/VAR10<14>VAR20 ;
wire \VAR33/VAR10<13>VAR20 ;
wire \VAR33/VAR10<12>VAR20 ;
wire \VAR33/VAR10<11>VAR20 ;
wire \VAR33/VAR10<10>VAR20 ;
wire \VAR33/VAR10<9>VAR20 ;
wire \VAR33/VAR10<8>VAR20 ;
wire \VAR33/VAR10<7>VAR20 ;
wire \VAR33/VAR10<6>VAR20 ;
wire \VAR33/VAR10<5>VAR20 ;
wire \VAR33/VAR10<4>VAR20 ;
wire \VAR33/VAR10<3>VAR20 ;
wire \VAR33/VAR10<2>VAR20 ;
wire \VAR33/VAR10<1>VAR20 ;
wire \VAR33/VAR10<0>VAR20 ;
wire \VAR33/VAR21<47>VAR20 ;
wire \VAR33/VAR21<46>VAR20 ;
wire \VAR33/VAR21<45>VAR20 ;
wire \VAR33/VAR21<44>VAR20 ;
wire \VAR33/VAR21<43>VAR20 ;
wire \VAR33/VAR21<42>VAR20 ;
wire \VAR33/VAR21<41>VAR20 ;
wire \VAR33/VAR21<40>VAR20 ;
wire \VAR33/VAR21<39>VAR20 ;
wire \VAR33/VAR21<38>VAR20 ;
wire \VAR33/VAR21<37>VAR20 ;
wire \VAR33/VAR21<36>VAR20 ;
wire \VAR33/VAR21<35>VAR20 ;
wire \VAR33/VAR21<34>VAR20 ;
wire \VAR33/VAR21<33>VAR20 ;
wire \VAR33/VAR21<32>VAR20 ;
wire \VAR33/VAR21<31>VAR20 ;
wire \VAR33/VAR21<30>VAR20 ;
wire \VAR33/VAR21<29>VAR20 ;
wire \VAR33/VAR21<28>VAR20 ;
wire \VAR33/VAR21<27>VAR20 ;
wire \VAR33/VAR21<26>VAR20 ;
wire \VAR33/VAR21<25>VAR20 ;
wire \VAR33/VAR21<24>VAR20 ;
wire \VAR33/VAR21<23>VAR20 ;
wire \VAR33/VAR21<22>VAR20 ;
wire \VAR33/VAR21<21>VAR20 ;
wire \VAR33/VAR21<20>VAR20 ;
wire \VAR33/VAR21<19>VAR20 ;
wire \VAR33/VAR21<18>VAR20 ;
wire \VAR33/VAR21<17>VAR20 ;
wire \VAR33/VAR21<16>VAR20 ;
wire \VAR33/VAR21<15>VAR20 ;
wire \VAR33/VAR21<14>VAR20 ;
wire \VAR33/VAR21<13>VAR20 ;
wire \VAR33/VAR21<12>VAR20 ;
wire \VAR33/VAR21<11>VAR20 ;
wire \VAR33/VAR21<10>VAR20 ;
wire \VAR33/VAR21<9>VAR20 ;
wire \VAR33/VAR21<8>VAR20 ;
wire \VAR33/VAR21<7>VAR20 ;
wire \VAR33/VAR21<6>VAR20 ;
wire \VAR33/VAR21<5>VAR20 ;
wire \VAR33/VAR21<4>VAR20 ;
wire \VAR33/VAR21<3>VAR20 ;
wire \VAR33/VAR21<2>VAR20 ;
wire \VAR33/VAR21<1>VAR20 ;
wire \VAR33/VAR21<0>VAR20 ;
wire \VAR33/VAR43<47>VAR20 ;
wire \VAR33/VAR43<46>VAR20 ;
wire \VAR33/VAR43<45>VAR20 ;
wire \VAR33/VAR43<44>VAR20 ;
wire \VAR33/VAR43<43>VAR20 ;
wire \VAR33/VAR43<42>VAR20 ;
wire \VAR33/VAR43<41>VAR20 ;
wire \VAR33/VAR43<40>VAR20 ;
wire \VAR33/VAR43<39>VAR20 ;
wire \VAR33/VAR43<38>VAR20 ;
wire \VAR33/VAR43<37>VAR20 ;
wire \VAR33/VAR43<36>VAR20 ;
wire \VAR33/VAR43<35>VAR20 ;
wire \VAR33/VAR43<34>VAR20 ;
wire \VAR33/VAR43<33>VAR20 ;
wire \VAR33/VAR43<32>VAR20 ;
wire \VAR33/VAR43<31>VAR20 ;
wire \VAR33/VAR43<30>VAR20 ;
wire \VAR33/VAR43<29>VAR20 ;
wire \VAR33/VAR43<28>VAR20 ;
wire \VAR33/VAR43<27>VAR20 ;
wire \VAR33/VAR43<26>VAR20 ;
wire \VAR33/VAR43<25>VAR20 ;
wire \VAR33/VAR43<24>VAR20 ;
wire \VAR33/VAR43<23>VAR20 ;
wire \VAR33/VAR43<22>VAR20 ;
wire \VAR33/VAR43<21>VAR20 ;
wire \VAR33/VAR43<20>VAR20 ;
wire \VAR33/VAR43<19>VAR20 ;
wire \VAR33/VAR43<18>VAR20 ;
wire \VAR33/VAR43<17>VAR20 ;
wire \VAR33/VAR43<16>VAR20 ;
wire \VAR33/VAR43<15>VAR20 ;
wire \VAR33/VAR43<14>VAR20 ;
wire \VAR33/VAR43<13>VAR20 ;
wire \VAR33/VAR43<12>VAR20 ;
wire \VAR33/VAR43<11>VAR20 ;
wire \VAR33/VAR43<10>VAR20 ;
wire \VAR33/VAR43<9>VAR20 ;
wire \VAR33/VAR43<8>VAR20 ;
wire \VAR33/VAR43<7>VAR20 ;
wire \VAR33/VAR43<6>VAR20 ;
wire \VAR33/VAR43<5>VAR20 ;
wire \VAR33/VAR43<4>VAR20 ;
wire \VAR33/VAR43<3>VAR20 ;
wire \VAR33/VAR43<2>VAR20 ;
wire \VAR33/VAR43<1>VAR20 ;
wire \VAR33/VAR43<0>VAR20 ;
wire \VAR33/VAR6<35>VAR20 ;
wire \VAR33/VAR6<34>VAR20 ;
wire \VAR33/VAR6<33>VAR20 ;
wire \VAR33/VAR6<32>VAR20 ;
wire \VAR33/VAR6<31>VAR20 ;
wire \VAR33/VAR6<30>VAR20 ;
wire \VAR33/VAR6<29>VAR20 ;
wire \VAR33/VAR6<28>VAR20 ;
wire \VAR33/VAR6<27>VAR20 ;
wire \VAR33/VAR6<26>VAR20 ;
wire \VAR33/VAR6<25>VAR20 ;
wire \VAR33/VAR6<24>VAR20 ;
wire \VAR33/VAR6<23>VAR20 ;
wire \VAR33/VAR6<22>VAR20 ;
wire \VAR33/VAR6<21>VAR20 ;
wire \VAR33/VAR6<20>VAR20 ;
VAR99 #(
.VAR40 ( "VAR80" ),
.VAR5 ( 0 ),
.VAR93 ( 1 ),
.VAR56 ( 1 ),
.VAR7 ( 0 ),
.VAR29 ( 0 ),
.VAR76 ( 1 ),
.VAR77 ( 0 ),
.VAR18 ( 0 ),
.VAR75 ( 0 ),
.VAR36 ( 0 ),
.VAR49 ( "VAR26" ),
.VAR38 ( 0 ))
\VAR96/VAR94 (
.VAR66(\VAR96/VAR42 ),
.VAR15(\VAR96/VAR42 ),
.VAR23(\VAR96/VAR42 ),
.VAR39(\VAR96/VAR42 ),
.VAR1(\VAR96/VAR42 ),
.VAR25(\VAR96/VAR42 ),
.VAR98(\VAR96/VAR42 ),
.VAR67(\VAR33/VAR13 ),
.VAR54(\VAR96/VAR42 ),
.VAR79(\VAR96/VAR42 ),
.VAR17(clk),
.VAR63(\VAR96/VAR42 ),
.VAR73(\VAR96/VAR95 ),
.VAR4(\VAR96/VAR95 ),
.VAR2(\VAR96/VAR42 ),
.VAR74(\VAR96/VAR42 ),
.VAR37(\VAR96/VAR95 ),
.VAR41(\VAR33/VAR50 ),
.VAR65(\VAR96/VAR42 ),
.VAR30(\VAR96/VAR42 ),
.VAR16({VAR58[9], VAR58[9], VAR58[9], VAR58[9], VAR58[9], VAR58[9], VAR58[9], VAR58[9], VAR58[9], VAR58[8], VAR58[7], VAR58[6], VAR58[5], VAR58[4], VAR58[3], VAR58[2], VAR58[1], VAR58[0]}),
.VAR68({\VAR33/VAR97<17>VAR20 , \VAR33/VAR97<16>VAR20 ,
\VAR33/VAR97<15>VAR20 , \VAR33/VAR97<14>VAR20 ,
\VAR33/VAR97<13>VAR20 , \VAR33/VAR97<12>VAR20 ,
\VAR33/VAR97<11>VAR20 , \VAR33/VAR97<10>VAR20 ,
\VAR33/VAR97<9>VAR20 , \VAR33/VAR97<8>VAR20 ,
\VAR33/VAR97<7>VAR20 , \VAR33/VAR97<6>VAR20 ,
\VAR33/VAR97<5>VAR20 , \VAR33/VAR97<4>VAR20 ,
\VAR33/VAR97<3>VAR20 , \VAR33/VAR97<2>VAR20 ,
\VAR33/VAR97<1>VAR20 , \VAR33/VAR97<0>VAR20 }),
.VAR59({\VAR33/VAR10<47>VAR20 , \VAR33/VAR10<46>VAR20 ,
\VAR33/VAR10<45>VAR20 , \VAR33/VAR10<44>VAR20 ,
\VAR33/VAR10<43>VAR20 , \VAR33/VAR10<42>VAR20 ,
\VAR33/VAR10<41>VAR20 , \VAR33/VAR10<40>VAR20 ,
\VAR33/VAR10<39>VAR20 , \VAR33/VAR10<38>VAR20 ,
\VAR33/VAR10<37>VAR20 , \VAR33/VAR10<36>VAR20 ,
\VAR33/VAR10<35>VAR20 , \VAR33/VAR10<34>VAR20 ,
\VAR33/VAR10<33>VAR20 , \VAR33/VAR10<32>VAR20 ,
\VAR33/VAR10<31>VAR20 , \VAR33/VAR10<30>VAR20 ,
\VAR33/VAR10<29>VAR20 , \VAR33/VAR10<28>VAR20 ,
\VAR33/VAR10<27>VAR20 , \VAR33/VAR10<26>VAR20 ,
\VAR33/VAR10<25>VAR20 , \VAR33/VAR10<24>VAR20 ,
\VAR33/VAR10<23>VAR20 , \VAR33/VAR10<22>VAR20 ,
\VAR33/VAR10<21>VAR20 , \VAR33/VAR10<20>VAR20 ,
\VAR33/VAR10<19>VAR20 , \VAR33/VAR10<18>VAR20 ,
\VAR33/VAR10<17>VAR20 , \VAR33/VAR10<16>VAR20 ,
\VAR33/VAR10<15>VAR20 , \VAR33/VAR10<14>VAR20 ,
\VAR33/VAR10<13>VAR20 , \VAR33/VAR10<12>VAR20 ,
\VAR33/VAR10<11>VAR20 , \VAR33/VAR10<10>VAR20 ,
\VAR33/VAR10<9>VAR20 , \VAR33/VAR10<8>VAR20 ,
\VAR33/VAR10<7>VAR20 , \VAR33/VAR10<6>VAR20 ,
\VAR33/VAR10<5>VAR20 , \VAR33/VAR10<4>VAR20 ,
\VAR33/VAR10<3>VAR20 , \VAR33/VAR10<2>VAR20 ,
\VAR33/VAR10<1>VAR20 , \VAR33/VAR10<0>VAR20 }),
.VAR78({\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 }),
.VAR62({\VAR33/VAR21<47>VAR20 , \VAR33/VAR21<46>VAR20 ,
\VAR33/VAR21<45>VAR20 , \VAR33/VAR21<44>VAR20 , \VAR33/VAR21<43>VAR20 ,
\VAR33/VAR21<42>VAR20 , \VAR33/VAR21<41>VAR20 , \VAR33/VAR21<40>VAR20 ,
\VAR33/VAR21<39>VAR20 , \VAR33/VAR21<38>VAR20 , \VAR33/VAR21<37>VAR20 ,
\VAR33/VAR21<36>VAR20 , \VAR33/VAR21<35>VAR20 , \VAR33/VAR21<34>VAR20 ,
\VAR33/VAR21<33>VAR20 , \VAR33/VAR21<32>VAR20 , \VAR33/VAR21<31>VAR20 ,
\VAR33/VAR21<30>VAR20 , \VAR33/VAR21<29>VAR20 , \VAR33/VAR21<28>VAR20 ,
\VAR33/VAR21<27>VAR20 , \VAR33/VAR21<26>VAR20 , \VAR33/VAR21<25>VAR20 ,
\VAR33/VAR21<24>VAR20 , \VAR33/VAR21<23>VAR20 , \VAR33/VAR21<22>VAR20 ,
\VAR33/VAR21<21>VAR20 , \VAR33/VAR21<20>VAR20 , \VAR33/VAR21<19>VAR20 ,
\VAR33/VAR21<18>VAR20 , \VAR33/VAR21<17>VAR20 , \VAR33/VAR21<16>VAR20 ,
\VAR33/VAR21<15>VAR20 , \VAR33/VAR21<14>VAR20 , \VAR33/VAR21<13>VAR20 ,
\VAR33/VAR21<12>VAR20 , \VAR33/VAR21<11>VAR20 , \VAR33/VAR21<10>VAR20 ,
\VAR33/VAR21<9>VAR20 , \VAR33/VAR21<8>VAR20 , \VAR33/VAR21<7>VAR20 ,
\VAR33/VAR21<6>VAR20 , \VAR33/VAR21<5>VAR20 , \VAR33/VAR21<4>VAR20 ,
\VAR33/VAR21<3>VAR20 , \VAR33/VAR21<2>VAR20 , \VAR33/VAR21<1>VAR20 ,
\VAR33/VAR21<0>VAR20 }),
.VAR9({\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR95 }),
.VAR3({\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 ,
\VAR96/VAR42 , \VAR96/VAR42 , \VAR96/VAR42 }),
.VAR61({\VAR33/VAR43<47>VAR20 , \VAR33/VAR43<46>VAR20 ,
\VAR33/VAR43<45>VAR20 , \VAR33/VAR43<44>VAR20 ,
\VAR33/VAR43<43>VAR20 , \VAR33/VAR43<42>VAR20 ,
\VAR33/VAR43<41>VAR20 , \VAR33/VAR43<40>VAR20 ,
\VAR33/VAR43<39>VAR20 , \VAR33/VAR43<38>VAR20 ,
\VAR33/VAR43<37>VAR20 , \VAR33/VAR43<36>VAR20 ,
\VAR33/VAR43<35>VAR20 , \VAR33/VAR43<34>VAR20 ,
\VAR33/VAR43<33>VAR20 , \VAR33/VAR43<32>VAR20 ,
\VAR33/VAR43<31>VAR20 , \VAR33/VAR43<30>VAR20 ,
\VAR33/VAR43<29>VAR20 , \VAR33/VAR43<28>VAR20 ,
\VAR33/VAR43<27>VAR20 , \VAR33/VAR43<26>VAR20 ,
\VAR33/VAR43<25>VAR20 , \VAR33/VAR43<24>VAR20 ,
\VAR33/VAR43<23>VAR20 , \VAR33/VAR43<22>VAR20 ,
\VAR33/VAR43<21>VAR20 , \VAR33/VAR43<20>VAR20 ,
\VAR33/VAR43<19>VAR20 , \VAR33/VAR43<18>VAR20 ,
\VAR33/VAR43<17>VAR20 , \VAR33/VAR43<16>VAR20 ,
\VAR33/VAR43<15>VAR20 , \VAR33/VAR43<14>VAR20 ,
\VAR33/VAR43<13>VAR20 , \VAR33/VAR43<12>VAR20 ,
\VAR33/VAR43<11>VAR20 , \VAR33/VAR43<10>VAR20 ,
\VAR33/VAR43<9>VAR20 , \VAR33/VAR43<8>VAR20 ,
\VAR33/VAR43<7>VAR20 , \VAR33/VAR43<6>VAR20 ,
\VAR33/VAR43<5>VAR20 , \VAR33/VAR43<4>VAR20 ,
\VAR33/VAR43<3>VAR20 , \VAR33/VAR43<2>VAR20 ,
\VAR33/VAR43<1>VAR20 , \VAR33/VAR43<0>VAR20 }),
.VAR47({VAR48[9], VAR48[9], VAR48[9], VAR48[9], VAR48[9], VAR48[9], VAR48[9], VAR48[9], VAR48[9], VAR48[8], VAR48[7], VAR48[6], VAR48[5], VAR48[4], VAR48[3], VAR48[2], VAR48[1], VAR48[0]}),
.VAR34({\VAR33/VAR6<35>VAR20 , \VAR33/VAR6<34>VAR20 ,
\VAR33/VAR6<33>VAR20 , \VAR33/VAR6<32>VAR20 , \VAR33/VAR6<31>VAR20 ,
\VAR33/VAR6<30>VAR20 , \VAR33/VAR6<29>VAR20 , \VAR33/VAR6<28>VAR20 ,
\VAR33/VAR6<27>VAR20 , \VAR33/VAR6<26>VAR20 , \VAR33/VAR6<25>VAR20 ,
\VAR33/VAR6<24>VAR20 , \VAR33/VAR6<23>VAR20 , \VAR33/VAR6<22>VAR20 ,
\VAR33/VAR6<21>VAR20 , \VAR33/VAR6<20>VAR20 , VAR32[19], VAR32[18], VAR32[17], VAR32[16], VAR32[15], VAR32[14], VAR32[13],
VAR32[12], VAR32[11], VAR32[10], VAR32[9], VAR32[8], VAR32[7], VAR32[6], VAR32[5], VAR32[4], VAR32[3], VAR32[2], VAR32[1], VAR32[0]})
);
VAR64 \VAR96/VAR45 (
.VAR87(\VAR96/VAR42 )
);
VAR27 \VAR96/VAR44 (
.VAR62(\VAR96/VAR95 )
);
endmodule
module MODULE2 ();
parameter VAR57 = 100000;
parameter VAR51 = 0;
wire VAR85;
wire VAR14;
wire VAR28;
wire VAR90;
tri1 VAR89;
tri (weak1, strong0) VAR52 = VAR89;
wire VAR70;
wire VAR82;
reg VAR69;
reg VAR92;
reg VAR55;
wire VAR53;
wire VAR71;
wire VAR11;
wire VAR81;
wire VAR91;
reg VAR86;
reg VAR19;
reg VAR12;
reg VAR35;
reg VAR22;
reg VAR8 = 0;
reg VAR83 = 0 ;
reg VAR88 = 0;
reg VAR84 = 0;
reg VAR60 = 1'VAR46;
reg VAR72 = 1'VAR46;
reg VAR31 = 1'VAR46;
reg VAR24 = 1'VAR46;
assign (weak1, weak0) VAR85 = VAR69;
assign (weak1, weak0) VAR14 = VAR92;
assign (weak1, weak0) VAR90 = VAR55;
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/lsbuf/sky130_fd_sc_lp__lsbuf.functional.v
| 1,522 |
module MODULE1 (
VAR7,
VAR1
);
output VAR7;
input VAR1;
wire VAR4;
wire VAR2 ;
wire VAR5 ;
buf VAR3 (VAR4, VAR1 );
VAR6 VAR8 (VAR7 , VAR4, VAR2, VAR5);
endmodule
|
apache-2.0
|
Saucyz/explode
|
Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ob_de2_70.v
| 7,267 |
module MODULE1 (
VAR8,
VAR17
);
parameter VAR9 = 9'h01A;
parameter VAR18 = 9'h01A;
parameter VAR4 = 9'h07B;
parameter VAR16 = 9'h07B;
parameter VAR2 = 9'h0F8;
parameter VAR6 = 9'h006;
parameter VAR5 = 9'h000;
parameter VAR15 = 9'h001;
parameter VAR7 = 9'h002;
parameter VAR1 = 9'h001;
input [ 5: 0] VAR8;
output [26: 0] VAR17;
wire [26: 0] VAR11;
wire [26: 0] VAR13;
assign VAR17 = VAR11 | VAR13;
VAR14 VAR3 (
.VAR8 (VAR8),
.VAR17 (VAR11)
);
VAR3.VAR9 = VAR9,
VAR3.VAR18 = VAR18,
VAR3.VAR4 = VAR4,
VAR3.VAR16 = VAR16,
VAR3.VAR2 = VAR2,
VAR3.VAR6 = VAR6,
VAR3.VAR5 = VAR5,
VAR3.VAR15 = VAR15,
VAR3.VAR7 = VAR7,
VAR3.VAR1 = VAR1;
VAR12 VAR10 (
.VAR8 (VAR8),
.VAR17 (VAR13)
);
endmodule
|
mit
|
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