repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/mux2/sky130_fd_sc_hs__mux2.behavioral.v
| 1,771 |
module MODULE1 (
VAR10 ,
VAR13 ,
VAR6 ,
VAR8 ,
VAR11,
VAR2
);
output VAR10 ;
input VAR13 ;
input VAR6 ;
input VAR8 ;
input VAR11;
input VAR2;
wire VAR1 ;
wire VAR12;
VAR5 VAR4 (VAR1 , VAR13, VAR6, VAR8 );
VAR9 VAR7 (VAR12, VAR1, VAR11, VAR2);
buf VAR3 (VAR10 , VAR12 );
endmodule
|
apache-2.0
|
rohit91/HDMI2USB
|
hdl/hdmi/dvi_decoder.v
| 8,346 |
module MODULE1 (
input wire VAR79, input wire VAR56, input wire VAR34, input wire VAR67, input wire VAR83, input wire VAR48, input wire VAR19, input wire VAR101, input wire VAR64,
output wire reset, output wire VAR94, output wire VAR85, output wire VAR91, output wire VAR4, output wire VAR60, output wire VAR22,
output wire VAR33, output wire VAR28, output wire VAR70,
output wire VAR50, output wire VAR6, output wire VAR16,
output wire VAR82,
output wire VAR9,
output wire VAR31,
output wire VAR77,
output wire VAR1,
output wire VAR81,
output wire VAR35,
output wire [29:0] VAR26,
output wire [7:0] VAR71, output wire [7:0] VAR105, output wire [7:0] VAR27);
wire [9:0] VAR29, VAR13, VAR8;
assign VAR26 = {VAR8[9:5], VAR13[9:5], VAR29[9:5],
VAR8[4:0], VAR13[4:0], VAR29[4:0]};
wire VAR17, VAR96, VAR104;
assign VAR16 = VAR17;
wire VAR39, VAR37, VAR61;
wire VAR36;
VAR2 #(.VAR14("VAR88"), .VAR20("VAR23")
) VAR21 (.VAR95(VAR79), .VAR11(VAR56), .VAR84(VAR36));
wire VAR24;
VAR30 #(.VAR89("VAR53"), .VAR18(1))
VAR42 (.VAR66(VAR24), .VAR57(), .VAR99(), .VAR95(VAR36));
VAR62 VAR87 (.VAR95(VAR24), .VAR84(VAR70));
VAR98 # (
.VAR93(10),
.VAR32(10), .VAR40(1),
.VAR58(10),
.VAR55(5),
.VAR92("VAR103")
) VAR74 (
.VAR5(VAR54),
.VAR15(VAR4),
.VAR65(VAR60),
.VAR47(VAR22),
.VAR3(),
.VAR10(),
.VAR12(),
.VAR90(VAR33),
.VAR46(VAR54),
.VAR7(VAR24),
.VAR100(VAR64)
);
VAR62 VAR86 (.VAR95(VAR60), .VAR84(VAR94));
VAR62 VAR73 (.VAR95(VAR22), .VAR84(VAR85));
wire VAR63;
VAR69 #(.VAR18(5)) VAR43 (.VAR25(VAR4), .VAR78(VAR85), .VAR90(VAR33),
.VAR57(VAR91), .VAR99(VAR28), .VAR44(VAR63));
assign reset = ~VAR63;
VAR97 VAR52 (
.reset (reset),
.VAR94 (VAR94),
.VAR85 (VAR85),
.VAR91 (VAR91),
.VAR28 (VAR28),
.VAR75 (VAR34),
.VAR76 (VAR48),
.VAR38(VAR1),
.VAR51(VAR81),
.VAR59(VAR9),
.VAR49(VAR31),
.VAR80 (VAR82),
.VAR68 (VAR77),
.VAR35 (VAR39),
.VAR45 (VAR50),
.VAR102 (VAR6),
.VAR16 (VAR17),
.VAR26 (VAR29),
.dout (VAR27)) ;
VAR97 VAR72 (
.reset (reset),
.VAR94 (VAR94),
.VAR85 (VAR85),
.VAR91 (VAR91),
.VAR28 (VAR28),
.VAR75 (VAR67),
.VAR76 (VAR19),
.VAR38(VAR77),
.VAR51(VAR81),
.VAR59(VAR82),
.VAR49(VAR31),
.VAR80 (VAR9),
.VAR68 (VAR1),
.VAR35 (VAR37),
.VAR45 (),
.VAR102 (),
.VAR16 (VAR96),
.VAR26 (VAR13),
.dout (VAR105)) ;
VAR97 VAR41 (
.reset (reset),
.VAR94 (VAR94),
.VAR85 (VAR85),
.VAR91 (VAR91),
.VAR28 (VAR28),
.VAR75 (VAR83),
.VAR76 (VAR101),
.VAR38(VAR77),
.VAR51(VAR1),
.VAR59(VAR82),
.VAR49(VAR9),
.VAR80 (VAR31),
.VAR68 (VAR81),
.VAR35 (VAR61),
.VAR45 (),
.VAR102 (),
.VAR16 (VAR104),
.VAR26 (VAR8),
.dout (VAR71)) ;
assign VAR35 = VAR61 | VAR39 | VAR37;
endmodule
|
bsd-2-clause
|
eckucukoglu/basic-vending-machine
|
src/Board232.v
| 3,766 |
module MODULE3 (
input VAR6,
input [3:0] VAR1,
input [7:0] VAR2,
output [7:0] VAR25,
output reg [6:0] VAR30,
output reg [3:0] VAR32,
output VAR29,
output [2:1] VAR15,
output [2:0] VAR35,
output [2:0] VAR31,
output VAR24,
output VAR5
);
assign VAR29 = 1'b1;
assign VAR25[7] = VAR1[3]; assign VAR25[6] = 1'b0;
wire [7:0] VAR3;
VAR18 VAR7(
VAR2[2:0], VAR2[7:6], VAR1[3], VAR1[0], VAR3, VAR25[5:0] );
reg [18:0] VAR27;
VAR12 VAR27<= 0;
always @(posedge VAR6) VAR27 = VAR27+1;
wire [3:0] VAR37;
wire [3:0] VAR19;
wire [3:0] VAR39;
MODULE2 MODULE2(VAR3, VAR37, VAR19, VAR39);
reg [3:0] VAR36;
always @(VAR27[18:17])
begin
case (VAR27[18:17])
2'b00:
begin
VAR32 = 4'b1110;
VAR36 = VAR37;
end
2'b01:
begin
VAR32 = 4'b1101;
VAR36 = VAR19;
end
2'b10:
begin
VAR32 = 4'b1011;
VAR36 = VAR39;
end
default:
begin
VAR32 = 4'b0111;
VAR36 = 0;
end
endcase
case (VAR36)
4'd0: VAR30 <= ~7'h3F;
4'd1: VAR30 <= ~7'h06;
4'd2: VAR30 <= ~7'h5B;
4'd3: VAR30 <= ~7'h4F;
4'd4: VAR30 <= ~7'h66;
4'd5: VAR30 <= ~7'h6D;
4'd6: VAR30 <= ~7'h7D;
4'd7: VAR30 <= ~7'h07;
4'd8: VAR30 <= ~7'h7F;
4'd9: VAR30 <= ~7'h6F;
default: VAR30 <= ~7'b1111000;
endcase
end
assign VAR15 = 0;
assign VAR35 = 0;
assign VAR31 = 0;
assign VAR24 = 0;
assign VAR5 = 0;
endmodule
module MODULE2(VAR40,VAR8,VAR4,VAR13);
input [7:0] VAR40;
output [3:0] VAR8, VAR4, VAR13;
wire [3:0] VAR28,VAR33,VAR14,VAR20,VAR21,VAR9,VAR38;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,VAR40[7:5]};
assign d2 = {VAR28[2:0],VAR40[4]};
assign d3 = {VAR33[2:0],VAR40[3]};
assign d4 = {VAR14[2:0],VAR40[2]};
assign d5 = {VAR20[2:0],VAR40[1]};
assign d6 = {1'b0,VAR28[3],VAR33[3],VAR14[3]};
assign d7 = {VAR9[2:0],VAR20[3]};
MODULE1 MODULE3(d1,VAR28);
MODULE1 MODULE1(d2,VAR33);
MODULE1 MODULE5(d3,VAR14);
MODULE1 MODULE8(d4,VAR20);
MODULE1 MODULE4(d5,VAR21);
MODULE1 MODULE6(d6,VAR9);
MODULE1 MODULE7(d7,VAR38);
assign VAR8 = {VAR21[2:0],VAR40[0]};
assign VAR4 = {VAR38[2:0],VAR21[3]};
assign VAR13 = {0,0,VAR9[3],VAR38[3]};
endmodule
module MODULE1(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/fill/sky130_fd_sc_lp__fill_4.v
| 1,840 |
module MODULE2 (
VAR2,
VAR1,
VAR4 ,
VAR6
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR6 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
VAR3 VAR5 ();
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o41ai/sky130_fd_sc_hs__o41ai.behavioral.pp.v
| 1,960 |
module MODULE1 (
VAR9,
VAR15,
VAR6 ,
VAR10 ,
VAR12 ,
VAR11 ,
VAR5 ,
VAR4
);
input VAR9;
input VAR15;
output VAR6 ;
input VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR5 ;
input VAR4 ;
wire VAR5 VAR1 ;
wire VAR7 ;
wire VAR2;
or VAR13 (VAR1 , VAR5, VAR11, VAR12, VAR10 );
nand VAR3 (VAR7 , VAR4, VAR1 );
VAR16 VAR8 (VAR2, VAR7, VAR9, VAR15);
buf VAR14 (VAR6 , VAR2 );
endmodule
|
apache-2.0
|
kyzhai/NUNY
|
src/hardware/nine_new2_bb.v
| 5,018 |
module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule
|
gpl-2.0
|
atalbb/sha1
|
SHA1_core.srcs/sources_1/new/Initial_hash.v
| 1,559 |
module MODULE1(input clk,
input rst,
input VAR5,
input [31:0]VAR3,
output reg VAR2,
output reg [159:0]VAR4
);
reg [2:0]VAR1;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
VAR2 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end else begin
if(VAR5)
if(VAR1 < 6)
VAR1 <= VAR1 + 1;
end
end
always@(VAR1) begin
if(VAR1 == 1) begin
VAR4[159:128] = VAR3;
end
else if(VAR1 == 2)
VAR4[127:96] = VAR3;
end
else if(VAR1 == 3)
VAR4[95:64] = VAR3;
end
else if(VAR1 == 4)
VAR4[63:32] = VAR3;
else if(VAR1 == 5)
VAR4[31:0] = VAR3;
else if (VAR1 == 6) begin
VAR2 = 1;
end
else begin end
end
endmodule
|
apache-2.0
|
franmolinaca/papiGB
|
rtl/dzcpu_ucode_lut.v
| 27,341 |
module MODULE3
(
input wire[7:0] VAR60,
output reg [8:0] VAR15
);
always @ ( VAR60 )
begin
case ( VAR60 )
default:
VAR15 = 9'd278;
endcase
end
endmodule
module MODULE1
(
input wire[7:0] VAR60,
output reg [8:0] VAR15
);
always @ ( VAR60 )
begin
case ( VAR60 )
8'h7C: VAR15 = 9'd16; 8'h11: VAR15 = 9'd69; 8'h38: VAR15 = 9'd477;
default:
VAR15 = 9'd0;
endcase
end
endmodule
module MODULE2
(
input wire[8:0] VAR28,
output reg [13:0] VAR56
);
always @ ( VAR28 )
begin
case ( VAR28 )
0: VAR56 = { VAR51, VAR18 , VAR17 };
1: VAR56 = { VAR38, VAR30, VAR36 };
2: VAR56 = { VAR38, VAR34, null };
3: VAR56 = { VAR54 , VAR25, VAR43 };
4: VAR56 = { VAR1 , VAR25, VAR16 };
5: VAR56 = { VAR38, VAR30, VAR36 };
6: VAR56 = { VAR38, VAR34, null };
7: VAR56 = { VAR54 , VAR25, VAR12 };
8: VAR56 = { VAR1 , VAR25, VAR42 };
9: VAR56 = { VAR54, VAR30, VAR58 };
10: VAR56 = { VAR54, VAR8, VAR17 };
11: VAR56 = { VAR38, VAR30, VAR36 };
12: VAR56 = { VAR48, VAR57, VAR58 };
13: VAR56 = { VAR38, VAR30, VAR36 };
14: VAR56 = { VAR54, VAR34, null };
15: VAR56 = { VAR38, VAR26, null };
16: VAR56 = { VAR3, bit, null };
17: VAR56 = { VAR38, VAR30, VAR36 };
18: VAR56 = { VAR54, VAR34, null };
19: VAR56 = { VAR9, VAR25, VAR19 }; 20: VAR56 = { VAR54, VAR29, VAR36 }; 21: VAR56 = { VAR54,VAR49, VAR19 }; 22: VAR56 = { VAR48, VAR4, VAR47 }; 23: VAR56 = {VAR38, VAR30, VAR36};
24: VAR56 = { VAR38, VAR34, null };
25: VAR56 = {VAR48, VAR25, VAR23 };
26: VAR56 = {VAR38, VAR30, VAR36};
27: VAR56 = { VAR38, VAR34, null };
28: VAR56 = {VAR48, VAR25, VAR17 };
29: VAR56 = {VAR54, VAR30, VAR59 };
30: VAR56 = {VAR54, VAR8, VAR17 };
31: VAR56 = {VAR1, VAR30, VAR36 };
32: VAR56 = {VAR51, VAR24, VAR23 };
33: VAR56 = {VAR38, VAR30, VAR58 };
34: VAR56 = {VAR54, VAR8, VAR17 };
35: VAR56 = {VAR48, VAR30, VAR36 };
36: VAR56 = { VAR38, VAR30, VAR36 };
37: VAR56 = { VAR54 ,VAR32, VAR23 };
38: VAR56 = { VAR54 ,VAR25, VAR23 };
39: VAR56 = { VAR54, VAR30, VAR59 };
40: VAR56 = { VAR54, VAR8, VAR17 };
41: VAR56 = { VAR38, VAR21, VAR23 };
42: VAR56 = { VAR48, VAR30, VAR36 };
43: VAR56 = { VAR38, VAR30, VAR36 };
44: VAR56 = { VAR38, VAR34, null };
45: VAR56 = { VAR54 , VAR25, VAR46 };
46: VAR56 = { VAR1 , VAR25, VAR44 };
47: VAR56 = { VAR51, VAR57, VAR17 };
48: VAR56 = { VAR51, VAR57, VAR23 };
49: VAR56 = { VAR38, VAR57, VAR13 };
50: VAR56 = { VAR38, VAR29, VAR58 };
51: VAR56 = { VAR54 , VAR25, VAR12 }; 52: VAR56 = { VAR38, VAR25, VAR42 }; 53: VAR56 = { VAR54, VAR30, VAR13 };
54: VAR56 = { VAR54, VAR8, VAR11 }; 55: VAR56 = { VAR54, VAR57, VAR13 };
56: VAR56 = { VAR54 , VAR8, VAR36 }; 57: VAR56 = { VAR54 , VAR4, VAR58 };
58: VAR56 = { VAR54, VAR33, VAR58 };
59: VAR56 = { VAR48 ,VAR30, VAR36 };
60: VAR56 = { VAR38, VAR30, VAR36 };
61: VAR56 = { VAR38, VAR34, null };
62: VAR56 = { VAR48 , VAR25, VAR20 };
63: VAR56 = { VAR54, VAR57, VAR13 };
64: VAR56 = { VAR54, VAR30, VAR13 };
65: VAR56 = { VAR54 ,VAR8, VAR20 };
66: VAR56 = { VAR54, VAR57, VAR13 };
67: VAR56 = { VAR54 ,VAR8, VAR23 };
68: VAR56 = { VAR1 ,VAR30,VAR36 };
69: VAR56 = { VAR3, VAR41, null };
70: VAR56 = { VAR51, VAR41, null };
71: VAR56 = { VAR54, VAR30, VAR13 };
72: VAR56 = { VAR54 ,VAR24, VAR13 };
73: VAR56 = { VAR54 ,VAR25, VAR23 };
74: VAR56 = { VAR54 ,VAR25, VAR20 };
75: VAR56 = { VAR38 ,VAR24, VAR13 };
76: VAR56 = { VAR48, VAR30, VAR36 };
77: VAR56 = { VAR51, VAR57, VAR20 };
78: VAR56 = {VAR54, VAR30, VAR58 };
79: VAR56 = {VAR54, VAR8, VAR17 };
80: VAR56 = { VAR38 ,VAR24, VAR58 };
81: VAR56 = {VAR48, VAR30, VAR36 };
82: VAR56 = { VAR1 ,VAR24, VAR58 };
83: VAR56 = { VAR1 ,VAR24, VAR55 }; 84: VAR56 = { VAR1, VAR34, null };
85: VAR56 = { VAR38, VAR30, VAR36 };
86: VAR56 = { VAR54, VAR34 , null };
87: VAR56 = { VAR50 ,VAR40, VAR45 };
88: VAR56 = { VAR1 ,VAR34, null };
89: VAR56 = { VAR1, VAR24, VAR14 };
90: VAR56 = { VAR38, VAR29, VAR17 };
91: VAR56 = { VAR54, VAR34, null };
92: VAR56 = { VAR54, VAR25, VAR19 };
93: VAR56 = { VAR51, VAR2, VAR19 }; 94: VAR56 = {VAR38, VAR30, VAR14 };
95: VAR56 = {VAR54, VAR34, null };
96: VAR56 = {VAR54, VAR25, VAR17 };
97: VAR56 = {VAR48, VAR30, VAR36 };
98: VAR56 = {VAR38, VAR29, VAR58 };
99: VAR56 = {VAR38, VAR30, VAR36 };
100: VAR56 = {VAR54, VAR25, VAR12 };
101: VAR56 = {VAR54, VAR25, VAR42 };
102: VAR56 = {VAR54, VAR30, VAR58 };
103: VAR56 = {VAR54, VAR8, VAR17 };
104: VAR56 = {VAR38, VAR30, VAR36 };
105: VAR56 = {VAR48, VAR33, VAR58 };
106: VAR56 = { VAR38, VAR30, VAR36 };
107: VAR56 = { VAR54, VAR34, null };
108: VAR56 = { VAR22, VAR25, VAR19 }; 109: VAR56 = { VAR54, VAR29, VAR36 }; 110: VAR56 = { VAR54,VAR49, VAR19 }; 111: VAR56 = { VAR48, VAR4, VAR47 }; 112: VAR56 = {VAR38, VAR30, VAR36 };
113: VAR56 = { VAR38, VAR34, null };
114: VAR56 = {VAR48, VAR25, VAR12 };
115: VAR56 = { VAR38, VAR30, VAR36 };
116: VAR56 = { VAR54, VAR34, null };
117: VAR56 = { VAR38, VAR25, VAR19 };
118: VAR56 = { VAR54, VAR29, VAR36 }; 119: VAR56 = { VAR54,VAR49, VAR19 }; 120: VAR56 = { VAR48, VAR4, VAR47 }; 121: VAR56 = {VAR38, VAR30, VAR36 };
122: VAR56 = { VAR38, VAR34, null };
123: VAR56 = {VAR48, VAR25, VAR46 };
124: VAR56 = { VAR38, VAR32, VAR23 };
125: VAR56 = { VAR54, VAR34, null };
126: VAR56 = { VAR54, VAR25, VAR23 };
127: VAR56 = { VAR54, VAR30, VAR59 };
128: VAR56 = { VAR54, VAR25, VAR17 };
129: VAR56 = { VAR54, VAR21, VAR23 };
130: VAR56 = { VAR1, VAR30, VAR36 };
131: VAR56 = { VAR54, VAR34, null };
132: VAR56 = { VAR54, VAR29, VAR17 };
133: VAR56 = { VAR50, VAR2, VAR20 };
134: VAR56 = { VAR1, VAR33, VAR17 };
135: VAR56 = { VAR51, VAR57, VAR44 };
136: VAR56 = {VAR38, VAR30, VAR36 };
137: VAR56 = { VAR38, VAR34, null };
138: VAR56 = {VAR48, VAR25, VAR44 };
139: VAR56 = {VAR54, VAR29, VAR58 };
140: VAR56 = {VAR38, VAR30, VAR36 };
141: VAR56 = {VAR38, VAR34, null };
142: VAR56 = {VAR38, VAR25, VAR12 };
143: VAR56 = {VAR54, VAR25, VAR42 };
144: VAR56 = {VAR54, VAR4, VAR58 };
145: VAR56 = {VAR48, VAR33, VAR58 };
146: VAR56 = {VAR38, VAR30, VAR36 };
147: VAR56 = { VAR38, VAR34, null };
148: VAR56 = {VAR48, VAR25, VAR42 };
149: VAR56 = {VAR54, VAR30, VAR58 };
150: VAR56 = {VAR54, VAR34, null };
151: VAR56 = {VAR54, VAR25, VAR17 };
152: VAR56 = { VAR38 ,VAR24, VAR58 };
153: VAR56 = {VAR48, VAR30, VAR36 };
154: VAR56 = {VAR38, VAR30, VAR36 };
155: VAR56 = {VAR54, VAR34, null };
156: VAR56 = {VAR54, VAR25, VAR19 };
157: VAR56 = {VAR54, VAR30, VAR58 };
158: VAR56 = {VAR54, VAR34, null };
159: VAR56 = {VAR54, VAR8, VAR19 };
160: VAR56 = {VAR1, VAR30, VAR36 };
161: VAR56 = {VAR51, VAR24, VAR20 };
162: VAR56 = { VAR1, VAR34, null };
163: VAR56 = { VAR1, VAR35, null }; 164: VAR56 = { VAR50, VAR24, VAR44 };
165: VAR56 = { VAR1, VAR34, null };
166: VAR56 = { VAR50, VAR57, VAR46 };
167: VAR56 = { VAR1, VAR34, null };
168: VAR56 = { VAR1, VAR57, VAR14 };
169: VAR56 = { VAR1, VAR57, VAR55};
170: VAR56 = { VAR50, VAR57, VAR42 };
171: VAR56 = { VAR1, VAR34, null };
172: VAR56 = { VAR1, VAR57, VAR58 };
173: VAR56 = { VAR1, VAR34, null };
174: VAR56 = { VAR1, VAR34, null };
175: VAR56 = { VAR54, VAR29, VAR17 };
176: VAR56 = { VAR50, VAR37, VAR17 };
177: VAR56 = { VAR1, VAR33, VAR17 };
178: VAR56 = { VAR54, VAR29, VAR17 };
179: VAR56 = { VAR50, VAR37, VAR20 };
180: VAR56 = { VAR1, VAR33, VAR17 };
181: VAR56 = { VAR54, VAR29, VAR17 };
182: VAR56 = { VAR50, VAR2, VAR23 };
183: VAR56 = { VAR1, VAR33, VAR17 };
184: VAR56 = { VAR54, VAR29, VAR17 };
185: VAR56 = { VAR50, VAR37, VAR23 };
186: VAR56 = { VAR1, VAR33, VAR17 };
187: VAR56 = { VAR54, VAR29, VAR17 };
188: VAR56 = { VAR50, VAR37, VAR44 };
189: VAR56 = { VAR1, VAR33, VAR17 };
190: VAR56 = { VAR54, VAR29, VAR17 };
191: VAR56 = { VAR50, VAR37, VAR46 };
192: VAR56 = { VAR1, VAR33, VAR17 };
193: VAR56 = { VAR54, VAR29, VAR17 };
194: VAR56 = { VAR50, VAR37, VAR42 };
195: VAR56 = { VAR1, VAR33, VAR17 };
196: VAR56 = { VAR54, VAR29, VAR17 };
197: VAR56 = { VAR50, VAR37, VAR12 };
198: VAR56 = { VAR1, VAR33, VAR17 };
199: VAR56 = { VAR54, VAR29, VAR17 };
200: VAR56 = { VAR50, VAR2, VAR44 };
201: VAR56 = { VAR1, VAR33, VAR17 };
202: VAR56 = { VAR54, VAR29, VAR17 };
203: VAR56 = { VAR50, VAR2, VAR46 };
204: VAR56 = { VAR1, VAR33, VAR17 };
205: VAR56 = { VAR54, VAR29, VAR17 };
206: VAR56 = { VAR50, VAR2, VAR42 };
207: VAR56 = { VAR1, VAR33, VAR17 };
208: VAR56 = { VAR54, VAR29, VAR17 };
209: VAR56 = { VAR50, VAR2, VAR12 };
210: VAR56 = { VAR1, VAR33, VAR17 };
211: VAR56 = { VAR54, VAR29, VAR17 };
212: VAR56 = { VAR50, VAR2, VAR17 };
213: VAR56 = { VAR1, VAR33, VAR17 };
214: VAR56 = { VAR54, VAR57, VAR13 };
215: VAR56 = { VAR54, VAR30, VAR13 };
216: VAR56 = { VAR54 ,VAR8, VAR44 };
217: VAR56 = { VAR54, VAR57, VAR13 };
218: VAR56 = { VAR54 ,VAR8, VAR46 };
219: VAR56 = { VAR1 ,VAR30,VAR36 };
220: VAR56 = { VAR54, VAR57, VAR13 };
221: VAR56 = { VAR54, VAR30, VAR13 };
222: VAR56 = { VAR54 ,VAR8, VAR42 };
223: VAR56 = { VAR54, VAR57, VAR13 };
224: VAR56 = { VAR54 ,VAR8, VAR12 };
225: VAR56 = { VAR1 ,VAR30,VAR36 };
226: VAR56 = { VAR54, VAR30, VAR13 };
227: VAR56 = { VAR54 ,VAR24, VAR13 };
228: VAR56 = { VAR54 ,VAR25, VAR46 };
229: VAR56 = { VAR54 ,VAR25, VAR44 };
230: VAR56 = { VAR38 ,VAR24, VAR13 };
231: VAR56 = { VAR48, VAR30, VAR36 };
232: VAR56 = { VAR54, VAR30, VAR13 };
233: VAR56 = { VAR54 ,VAR24, VAR13 };
234: VAR56 = { VAR54 ,VAR25, VAR12 };
235: VAR56 = { VAR54 ,VAR25, VAR42 };
236: VAR56 = { VAR38 ,VAR24, VAR13 };
237: VAR56 = { VAR48, VAR30, VAR36 };
238: VAR56 = {VAR38, VAR30, VAR58 };
239: VAR56 = {VAR54, VAR8, VAR20 };
240: VAR56 = {VAR48, VAR30, VAR36 };
241: VAR56 = {VAR38, VAR30, VAR58 };
242: VAR56 = {VAR54, VAR8, VAR23 };
243: VAR56 = {VAR48, VAR30, VAR36 };
244: VAR56 = {VAR38, VAR30, VAR58 };
245: VAR56 = {VAR54, VAR8, VAR44 };
246: VAR56 = {VAR48, VAR30, VAR36 };
247: VAR56 = {VAR54, VAR30, VAR14 };
248: VAR56 = {VAR54, VAR8, VAR17 };
249: VAR56 = {VAR1, VAR30, VAR36 };
250: VAR56 = { VAR50, VAR24, VAR46 };
251: VAR56 = { VAR1, VAR34, null };
252: VAR56 = {VAR54 ,VAR30, VAR13 };
253: VAR56 = {VAR54, VAR29, VAR58 };
254: VAR56 = {VAR54, VAR24, VAR13 };
255: VAR56 = {VAR54, VAR25, VAR12 };
256: VAR56 = {VAR54, VAR25, VAR42 };
257: VAR56 = {VAR54, VAR4, VAR58 };
258: VAR56 = {VAR54, VAR33, VAR58 };
259: VAR56 = {VAR54, VAR24, VAR13 };
260: VAR56 = { VAR48 ,VAR30, VAR36 };
261: VAR56 = { VAR54, VAR57, VAR13 };
262: VAR56 = { VAR54, VAR30, VAR13 };
263: VAR56 = { VAR54 ,VAR8, VAR17 };
264: VAR56 = { VAR54, VAR57, VAR13 };
265: VAR56 = { VAR54 ,VAR8, VAR39 };
266: VAR56 = { VAR1 ,VAR30,VAR36 };
267: VAR56 = { VAR54, VAR30, VAR13 };
268: VAR56 = { VAR54 ,VAR24, VAR13 };
269: VAR56 = { VAR54 ,VAR25, VAR39 };
270: VAR56 = { VAR54 ,VAR25, VAR17 };
271: VAR56 = { VAR38 ,VAR24, VAR13 };
272: VAR56 = { VAR48, VAR30, VAR36 };
273: VAR56 = { VAR38, VAR30, VAR36 };
274: VAR56 = { VAR38, VAR34, null };
275: VAR56 = { VAR54 , VAR25, VAR23 };
276: VAR56 = { VAR1 , VAR25, VAR20 };
277: VAR56 = { VAR1 ,VAR24, VAR55 };
278: VAR56 = { VAR50, VAR18 , VAR17 };
279: VAR56 = { VAR1, VAR34 , null };
280: VAR56 = { VAR38, VAR29, VAR58 };
281: VAR56 = { VAR38, VAR30 , VAR36 };
282: VAR56 = { VAR54 ,VAR25, VAR12 };
283: VAR56 = { VAR54 ,VAR25, VAR42 };
284: VAR56 = { VAR54, VAR30 , VAR58 };
285: VAR56 = { VAR54, VAR34 , null }; 286: VAR56 = { VAR54 ,VAR25, VAR17 };
287: VAR56 = { VAR54, VAR33, VAR58 };
288: VAR56 = { VAR1, VAR30 , VAR36 };
289: VAR56 = { VAR38, VAR34, null };
290: VAR56 = { VAR38, VAR34, null };
291: VAR56 = { VAR54 , VAR25, VAR31 }; 292: VAR56 = { VAR9, VAR25, VAR19 }; 293: VAR56 = { VAR54, VAR30, VAR13 };
294: VAR56 = { VAR54, VAR8, VAR11 }; 295: VAR56 = { VAR54, VAR57, VAR13 };
296: VAR56 = { VAR54 , VAR8, VAR36 }; 297: VAR56 = { VAR54, VAR57, VAR13 };
298: VAR56 = { VAR54 , VAR4, VAR10 };
299: VAR56 = { VAR48 ,VAR30, VAR36 };
300: VAR56 = { VAR50, VAR57, VAR20 };
301: VAR56 = { VAR1, VAR34, null};
302: VAR56 = { VAR50, VAR24, VAR17 };
303: VAR56 = { VAR1, VAR34, null};
304: VAR56 = { VAR54, VAR24, VAR13 }; 305: VAR56 = { VAR1, VAR34, null};
306: VAR56 = { VAR1, VAR57, VAR13 };
307: VAR56 = { VAR1, VAR34, null};
308: VAR56 = { VAR50, VAR24, VAR12 };
309: VAR56 = { VAR1, VAR34, null};
310: VAR56 = { VAR50, VAR57, VAR12 };
311: VAR56 = { VAR1, VAR34, null};
312: VAR56 = { VAR50, VAR24, VAR42 };
313: VAR56 = { VAR1, VAR34, null};
314: VAR56 = { VAR38, VAR30, VAR36 };
315: VAR56 = { VAR54, VAR34, null };
316: VAR56 = { VAR54, VAR25, VAR47 };
317: VAR56 = { VAR50, VAR37, VAR17 };
318: VAR56 = { VAR1, VAR33, VAR17};
319: VAR56 = { VAR38, VAR30, VAR36 };
320: VAR56 = { VAR54, VAR34, null };
321: VAR56 = { VAR54, VAR25, VAR47 };
322: VAR56 = { VAR50, VAR2, VAR17 };
323: VAR56 = { VAR1, VAR33, VAR17};
324: VAR56 = { VAR54, VAR29, VAR17 };
325: VAR56 = { VAR50, VAR2, VAR23 };
326: VAR56 = { VAR1, VAR34, null};
327: VAR56 = { VAR54, VAR30, VAR58 };
328: VAR56 = { VAR54, VAR34, null };
329: VAR56 = { VAR54, VAR25, VAR20 };
330: VAR56 = { VAR1, VAR30, VAR36};
331: VAR56 = { VAR54, VAR30, VAR58 };
332: VAR56 = { VAR54, VAR34, null };
333: VAR56 = { VAR54, VAR25, VAR23 };
334: VAR56 = { VAR1, VAR30, VAR36};
335: VAR56 = { VAR54, VAR30, VAR58 };
336: VAR56 = { VAR54, VAR34, null };
337: VAR56 = { VAR54, VAR25, VAR44 };
338: VAR56 = { VAR1, VAR30, VAR36};
339: VAR56 = { VAR54, VAR30, VAR58 };
340: VAR56 = { VAR54, VAR34, null };
341: VAR56 = { VAR54, VAR25, VAR47 };
342: VAR56 = { VAR50, VAR6, VAR17};
343: VAR56 = { VAR54, VAR33, VAR17};
344: VAR56 = { VAR1, VAR30, VAR36};
345: VAR56 = { VAR38, VAR30, VAR36 };
346: VAR56 = { VAR54, VAR34, null };
347: VAR56 = { VAR54, VAR25, VAR47 };
348: VAR56 = { VAR54, VAR49, VAR17 };
349: VAR56 = { VAR50, VAR49, VAR27 };
350: VAR56 = { VAR1, VAR30, VAR36};
351: VAR56 = { VAR38, VAR29, VAR58 };
352: VAR56 = { VAR50, VAR49, VAR14 };
353: VAR56 = { VAR48, VAR33, VAR58 };
354: VAR56 = { VAR38, VAR30, VAR36 };
355: VAR56 = { VAR54, VAR6, VAR47 };
356: VAR56 = { VAR50, VAR49, VAR27 };
357: VAR56 = { VAR22, VAR25, VAR47 };
358: VAR56 = { VAR48, VAR49, VAR47 };
359: VAR56 = { VAR38, VAR30, VAR36 };
360: VAR56 = { VAR54, VAR29 , VAR17 };
361: VAR56 = { VAR50 ,VAR6, VAR45 };
362: VAR56 = { VAR1 ,VAR33, VAR17 };
363: VAR56 = { VAR50, VAR5, null };
364: VAR56 = { VAR1, VAR34, null };
365: VAR56 = { VAR54, VAR6, VAR47 };
366: VAR56 = { VAR50, VAR49, VAR27 };
367: VAR56 = { VAR22, VAR25, VAR47 };
368: VAR56 = {VAR54 ,VAR30, VAR13 };
369: VAR56 = {VAR54, VAR29, VAR58 };
370: VAR56 = {VAR54, VAR24, VAR13 };
371: VAR56 = {VAR54, VAR25, VAR12 };
372: VAR56 = {VAR54, VAR25, VAR42 };
373: VAR56 = {VAR54, VAR4, VAR58 };
374: VAR56 = {VAR54, VAR33, VAR58 };
375: VAR56 = {VAR54, VAR24, VAR13 };
376: VAR56 = { VAR48 ,VAR30, VAR36 };
377: VAR56 = { VAR9, VAR34, null };
378: VAR56 = {VAR54 ,VAR30, VAR13 };
379: VAR56 = {VAR54, VAR29, VAR58 };
380: VAR56 = {VAR54, VAR24, VAR13 };
381: VAR56 = {VAR54, VAR25, VAR12 };
382: VAR56 = {VAR54, VAR25, VAR42 };
383: VAR56 = {VAR54, VAR4, VAR58 };
384: VAR56 = {VAR54, VAR33, VAR58 };
385: VAR56 = {VAR54, VAR24, VAR13 };
386: VAR56 = { VAR48 ,VAR30, VAR36 };
387: VAR56 = {VAR54 ,VAR30, VAR58 };
388: VAR56 = {VAR54, VAR34, null };
389: VAR56 = {VAR50, VAR53, VAR45 };
390: VAR56 = { VAR1 ,VAR30, VAR36 };
391: VAR56 = {VAR54 ,VAR30, VAR58 };
392: VAR56 = {VAR54, VAR34, null };
393: VAR56 = {VAR54, VAR25, VAR47 };
394: VAR56 = {VAR50, VAR57, VAR47 };
395: VAR56 = {VAR34, VAR8, VAR47 };
396: VAR56 = {VAR1, VAR30, VAR36 };
397: VAR56 = {VAR54 ,VAR30, VAR58 };
398: VAR56 = {VAR54, VAR34, null };
399: VAR56 = {VAR54, VAR25, VAR12 };
400: VAR56 = {VAR1, VAR30, VAR36 };
401: VAR56 = { VAR22, VAR34, null };
402: VAR56 = {VAR54 ,VAR30, VAR13 };
403: VAR56 = {VAR54, VAR29, VAR58 };
404: VAR56 = {VAR54, VAR24, VAR13 };
405: VAR56 = {VAR54, VAR25, VAR12 };
406: VAR56 = {VAR54, VAR25, VAR42 };
407: VAR56 = {VAR54, VAR4, VAR58 };
408: VAR56 = {VAR54, VAR33, VAR58 };
409: VAR56 = {VAR54, VAR24, VAR13 };
410: VAR56 = { VAR48 ,VAR30, VAR36 };
411: VAR56 = {VAR54, VAR29, VAR58 };
412: VAR56 = {VAR50, VAR7, VAR47 };
413: VAR56 = {VAR1, VAR33, VAR58 };
414: VAR56 = { VAR38, VAR30, VAR36 };
415: VAR56 = { VAR54, VAR6, VAR47 };
416: VAR56 = { VAR50, VAR49, VAR27 };
417: VAR56 = { VAR22, VAR25, VAR47 };
418: VAR56 = { VAR34, VAR49, VAR36 };
419: VAR56 = { VAR48, VAR4, VAR47 };
420: VAR56 = { VAR38, VAR30, VAR58 };
421: VAR56 = { VAR54, VAR34 , null };
422: VAR56 = { VAR50 ,VAR40, VAR45 };
423: VAR56 = { VAR1 ,VAR34, null };
424: VAR56 = {VAR38, VAR30, VAR58 };
425: VAR56 = {VAR54, VAR8, VAR46 };
426: VAR56 = {VAR48, VAR30, VAR36 };
427: VAR56 = {VAR38, VAR30, VAR58 };
428: VAR56 = {VAR54, VAR8, VAR42 };
429: VAR56 = {VAR48, VAR30, VAR36 };
430: VAR56 = {VAR38, VAR30, VAR58 };
431: VAR56 = {VAR54, VAR8, VAR12 };
432: VAR56 = {VAR48, VAR30, VAR36 };
433: VAR56 = {VAR38, VAR30, VAR55 };
434: VAR56 = {VAR54, VAR34, null };
435: VAR56 = {VAR54, VAR25, VAR17 };
436: VAR56 = {VAR48, VAR30, VAR36 };
437: VAR56 = {VAR38, VAR30, VAR58 };
438: VAR56 = {VAR54, VAR34, null };
439: VAR56 = {VAR54, VAR25, VAR17 };
440: VAR56 = {VAR48, VAR30, VAR36 };
441: VAR56 = {VAR38, VAR30, VAR58 };
442: VAR56 = {VAR54, VAR34, null };
443: VAR56 = {VAR54, VAR25, VAR46 };
444: VAR56 = {VAR48, VAR30, VAR36 };
445: VAR56 = {VAR38, VAR30, VAR58 };
446: VAR56 = {VAR54, VAR34, null };
447: VAR56 = {VAR54, VAR25, VAR42 };
448: VAR56 = {VAR48, VAR30, VAR36 };
449: VAR56 = { VAR54, VAR29, VAR17 };
450: VAR56 = { VAR54, VAR49, VAR27 };
451: VAR56 = { VAR50, VAR49, VAR17};
452: VAR56 = { VAR1, VAR33, VAR17 };
453: VAR56 = { VAR54, VAR29, VAR17 };
454: VAR56 = { VAR54, VAR49, VAR27 };
455: VAR56 = { VAR50, VAR49, VAR20};
456: VAR56 = { VAR1, VAR33, VAR17 };
457: VAR56 = { VAR54, VAR29, VAR17 };
458: VAR56 = { VAR54, VAR49, VAR27 };
459: VAR56 = { VAR50, VAR49, VAR23};
460: VAR56 = { VAR1, VAR33, VAR17 };
461: VAR56 = { VAR54, VAR29, VAR17 };
462: VAR56 = { VAR54, VAR49, VAR27 };
463: VAR56 = { VAR50, VAR49, VAR44};
464: VAR56 = { VAR1, VAR33, VAR17 };
465: VAR56 = { VAR54, VAR29, VAR17 };
466: VAR56 = { VAR54, VAR49, VAR27 };
467: VAR56 = { VAR50, VAR49, VAR46};
468: VAR56 = { VAR1, VAR33, VAR17 };
469: VAR56 = { VAR54, VAR29, VAR17 };
470: VAR56 = { VAR54, VAR49, VAR27 };
471: VAR56 = { VAR50, VAR49, VAR42};
472: VAR56 = { VAR1, VAR33, VAR17 };
473: VAR56 = { VAR54, VAR29, VAR17 };
474: VAR56 = { VAR54, VAR49, VAR27 };
475: VAR56 = { VAR50, VAR49, VAR12};
476: VAR56 = { VAR1, VAR33, VAR17 };
477: VAR56 = { VAR50, VAR52, null };
478: VAR56 = { VAR1, VAR34, null };
default:
VAR56 = {VAR54, VAR34, null };
endcase
end
endmodule
|
gpl-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/dma_engine_alignment.v
| 11,144 |
module MODULE1 (
input [VAR9-1:0] VAR12,
input VAR2,
input VAR13,
input [31:0] VAR7, output VAR10,
input VAR16,
output [VAR9 - 1 : 0] VAR8, output [VAR9 - 1 : 0] VAR32,
input VAR24,
input VAR20, input VAR25, input VAR22,
input VAR33,
input VAR30,
output reg VAR3, output VAR36,
input [1:0] VAR18,
output VAR38,
input VAR17,
input [8:0] VAR40, input [8:0] VAR31,
input VAR23,
input reset,
input clk
);
reg VAR35;
wire [VAR9-1:0] VAR28;
wire [31:0] VAR39;
wire VAR11;
reg [55:0] VAR21, VAR34;
reg VAR29;
reg VAR15;
reg VAR19;
reg VAR37;
reg [VAR9 - 1 : 0] VAR26;
reg [VAR9 - 1 : 0] VAR5;
reg VAR27;
reg [8:0] VAR6;
reg [8:0] VAR4;
wire VAR1;
wire VAR14;
assign VAR28 = VAR13 ?
{VAR12[7:0], VAR12[15:8], VAR12[23:16], VAR12[31:24]} :
VAR12;
always @(posedge clk)
begin
if (reset || VAR23)
begin
VAR3 <= 1'b0;
VAR29 <= 1'b0;
VAR15 <= 1'b0;
end
else
begin
if ((VAR2 && !VAR24) ||
(VAR29 && !VAR15 ))
VAR21 <= {VAR21[31:0], VAR28};
if (VAR2 && !VAR24)
VAR3 <= (VAR18 == 2'b00) || !VAR25;
end
else if (VAR3 || VAR29)
VAR3 <= VAR29 && !VAR15 &&
(!VAR3 || !VAR1);
if (VAR2 && !VAR24)
VAR29 <= VAR20;
if (VAR2 && !VAR24 || VAR3)
VAR15 <= VAR1 || (VAR15 && VAR3);
end
end
always @(posedge clk)
begin
if (reset || VAR23)
begin
VAR27 <= 1'b0;
VAR19 <= 1'b0;
end
else
begin
if (VAR11 || VAR36)
case (VAR18)
2'b01 : VAR34 <= {VAR34[23:0], VAR39};
2'b10 : VAR34 <= {VAR34[23:8], VAR39, 8'b0};
2'b11 : VAR34 <= {VAR34[23:16], VAR39, 16'b0};
default : VAR34 <= {VAR39, 24'b0};
endcase
if (VAR11)
VAR27 <= 1'b1;
end
else if (VAR36)
VAR27 <= VAR19 && !VAR37 &&
(!VAR27 || !VAR14);
if (VAR11)
VAR19 <= VAR22;
if (VAR11 || VAR36)
VAR37 <= VAR14 || (VAR36 && VAR37);
end
end
always @*
begin
case (VAR18)
2'b00 : VAR26 <= VAR21[31:0];
2'b01 : VAR26 <= VAR21[39:8];
2'b10 : VAR26 <= VAR21[47:16];
default : VAR26 <= VAR21[55:24];
endcase
end
assign VAR8 = {VAR26[7:0],
VAR26[15:8],
VAR26[23:16],
VAR26[31:24]};
always @*
VAR5 <= VAR34[55:24];
assign VAR32 = VAR13 ?
{VAR5[7:0],
VAR5[15:8],
VAR5[23:16],
VAR5[31:24]} :
VAR5;
assign VAR39 = {
VAR7[7:0],
VAR7[15:8],
VAR7[23:16],
VAR7[31:24]
};
always @(posedge clk)
begin
if (reset || VAR23)
VAR6 <= 'h0;
end
else if (VAR17)
VAR6 <= VAR31;
else if (VAR3)
VAR6 <= VAR6 - 'h1;
end
always @(posedge clk)
begin
if (reset || VAR23)
VAR4 <= 'h0;
end
else if (VAR17)
VAR4 <= VAR40;
else if (VAR36)
VAR4 <= VAR4 - 'h1;
end
assign VAR1 = VAR6 == 'h1;
assign VAR14 = VAR4 == 'h1;
always @(posedge clk)
begin
if (reset || VAR23)
VAR35 <= 1'b0;
end
else if (VAR10)
VAR35 <= 1'b1;
else if (VAR36 || VAR30)
VAR35 <= 1'b0;
end
assign VAR11 = VAR35 && !VAR30 && !VAR33;
assign VAR38 = VAR11;
assign VAR36 = VAR27 && !VAR33;
assign VAR10 = !VAR16 &&
(!VAR35 || VAR30 || VAR11);
endmodule
|
mit
|
scalable-networks/ext
|
uhd/fpga/usrp2/sdr_lib/hb/mult.v
| 1,047 |
module MODULE1 (input VAR2, input signed [15:0] VAR4, input signed [15:0] VAR3, output reg signed [30:0] VAR5,
input VAR1, output reg VAR6 );
always @(posedge VAR2)
if(VAR1)
VAR5 <= VAR4*VAR3;
else
VAR5 <= 31'd0;
always @(posedge VAR2)
VAR6 <= VAR1;
endmodule
|
gpl-2.0
|
jairov4/accel-oil
|
solution_virtex5_plb/syn/verilog/nfa_accept_samples_generic_hw_result.v
| 1,448 |
module MODULE2 (VAR14, VAR6, VAR1, VAR11, VAR8, clk);
parameter VAR12 = 1;
parameter VAR3 = 4;
parameter VAR13 = 16;
input[VAR3-1:0] VAR14;
input VAR6;
input[VAR12-1:0] VAR1;
input VAR11;
output reg[VAR12-1:0] VAR8;
input clk;
reg [VAR12-1:0] VAR5[VAR13-1:0];
always @(posedge clk)
begin
if (VAR6)
begin
if (VAR11)
begin
VAR5[VAR14] <= VAR1;
VAR8 <= VAR1;
end
else
VAR8 <= VAR5[VAR14];
end
end
endmodule
module MODULE1(
reset,
clk,
VAR9,
VAR6,
VAR11,
VAR1,
VAR8);
parameter VAR7 = 32'd1;
parameter VAR10 = 32'd16;
parameter VAR2 = 32'd4;
input reset;
input clk;
input[VAR2 - 1:0] VAR9;
input VAR6;
input VAR11;
input[VAR7 - 1:0] VAR1;
output[VAR7 - 1:0] VAR8;
MODULE2 VAR4(
.clk( clk ),
.VAR14( VAR9 ),
.VAR6( VAR6 ),
.VAR1( VAR1 ),
.VAR11( VAR11 ),
.VAR8( VAR8 ));
endmodule
|
lgpl-3.0
|
Cosmos-OpenSSD/Cosmos-OpenSSD-plus
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_auto_us_cc_df_1/synth/OpenSSD2_auto_us_cc_df_1.v
| 14,826 |
module MODULE1 (
VAR57,
VAR92,
VAR53,
VAR27,
VAR85,
VAR91,
VAR78,
VAR39,
VAR18,
VAR33,
VAR22,
VAR30,
VAR10,
VAR2,
VAR42,
VAR88,
VAR96,
VAR87,
VAR12,
VAR60,
VAR26,
VAR98,
VAR76,
VAR36,
VAR43,
VAR89,
VAR8,
VAR20,
VAR13,
VAR5,
VAR64,
VAR97,
VAR25,
VAR9,
VAR46,
VAR72,
VAR1,
VAR44,
VAR23,
VAR68,
VAR48,
VAR83,
VAR11,
VAR67,
VAR47,
VAR40,
VAR37,
VAR54,
VAR63,
VAR90,
VAR51,
VAR15,
VAR71,
VAR74,
VAR50,
VAR66,
VAR49,
VAR77,
VAR56,
VAR4,
VAR79,
VAR17,
VAR69,
VAR70,
VAR24,
VAR29,
VAR55,
VAR3,
VAR95,
VAR65,
VAR45,
VAR6,
VAR80,
VAR58
);
input wire VAR57;
input wire VAR92;
input wire [31 : 0] VAR53;
input wire [7 : 0] VAR27;
input wire [2 : 0] VAR85;
input wire [1 : 0] VAR91;
input wire [0 : 0] VAR78;
input wire [3 : 0] VAR39;
input wire [2 : 0] VAR18;
input wire [3 : 0] VAR33;
input wire [3 : 0] VAR22;
input wire VAR30;
output wire VAR10;
input wire [31 : 0] VAR2;
input wire [3 : 0] VAR42;
input wire VAR88;
input wire VAR96;
output wire VAR87;
output wire [1 : 0] VAR12;
output wire VAR60;
input wire VAR26;
input wire [31 : 0] VAR98;
input wire [7 : 0] VAR76;
input wire [2 : 0] VAR36;
input wire [1 : 0] VAR43;
input wire [0 : 0] VAR89;
input wire [3 : 0] VAR8;
input wire [2 : 0] VAR20;
input wire [3 : 0] VAR13;
input wire [3 : 0] VAR5;
input wire VAR64;
output wire VAR97;
output wire [31 : 0] VAR25;
output wire [1 : 0] VAR9;
output wire VAR46;
output wire VAR72;
input wire VAR1;
input wire VAR44;
input wire VAR23;
output wire [31 : 0] VAR68;
output wire [7 : 0] VAR48;
output wire [2 : 0] VAR83;
output wire [1 : 0] VAR11;
output wire [0 : 0] VAR67;
output wire [3 : 0] VAR47;
output wire [2 : 0] VAR40;
output wire [3 : 0] VAR37;
output wire [3 : 0] VAR54;
output wire VAR63;
input wire VAR90;
output wire [63 : 0] VAR51;
output wire [7 : 0] VAR15;
output wire VAR71;
output wire VAR74;
input wire VAR50;
input wire [1 : 0] VAR66;
input wire VAR49;
output wire VAR77;
output wire [31 : 0] VAR56;
output wire [7 : 0] VAR4;
output wire [2 : 0] VAR79;
output wire [1 : 0] VAR17;
output wire [0 : 0] VAR69;
output wire [3 : 0] VAR70;
output wire [2 : 0] VAR24;
output wire [3 : 0] VAR29;
output wire [3 : 0] VAR55;
output wire VAR3;
input wire VAR95;
input wire [63 : 0] VAR65;
input wire [1 : 0] VAR45;
input wire VAR6;
input wire VAR80;
output wire VAR58;
VAR73 #(
.VAR34("VAR35"),
.VAR52(0),
.VAR62(1),
.VAR19(0),
.VAR82(32),
.VAR41(32),
.VAR32(64),
.VAR31(1),
.VAR59(1),
.VAR86(2),
.VAR14(1),
.VAR81(2),
.VAR7(1),
.VAR38(16),
.VAR84(1),
.VAR93(3)
) VAR94 (
.VAR57(VAR57),
.VAR92(VAR92),
.VAR28(1'VAR21),
.VAR53(VAR53),
.VAR27(VAR27),
.VAR85(VAR85),
.VAR91(VAR91),
.VAR78(VAR78),
.VAR39(VAR39),
.VAR18(VAR18),
.VAR33(VAR33),
.VAR22(VAR22),
.VAR30(VAR30),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR42(VAR42),
.VAR88(VAR88),
.VAR96(VAR96),
.VAR87(VAR87),
.VAR16(),
.VAR12(VAR12),
.VAR60(VAR60),
.VAR26(VAR26),
.VAR75(1'VAR21),
.VAR98(VAR98),
.VAR76(VAR76),
.VAR36(VAR36),
.VAR43(VAR43),
.VAR89(VAR89),
.VAR8(VAR8),
.VAR20(VAR20),
.VAR13(VAR13),
.VAR5(VAR5),
.VAR64(VAR64),
.VAR97(VAR97),
.VAR61(),
.VAR25(VAR25),
.VAR9(VAR9),
.VAR46(VAR46),
.VAR72(VAR72),
.VAR1(VAR1),
.VAR44(VAR44),
.VAR23(VAR23),
.VAR68(VAR68),
.VAR48(VAR48),
.VAR83(VAR83),
.VAR11(VAR11),
.VAR67(VAR67),
.VAR47(VAR47),
.VAR40(VAR40),
.VAR37(VAR37),
.VAR54(VAR54),
.VAR63(VAR63),
.VAR90(VAR90),
.VAR51(VAR51),
.VAR15(VAR15),
.VAR71(VAR71),
.VAR74(VAR74),
.VAR50(VAR50),
.VAR66(VAR66),
.VAR49(VAR49),
.VAR77(VAR77),
.VAR56(VAR56),
.VAR4(VAR4),
.VAR79(VAR79),
.VAR17(VAR17),
.VAR69(VAR69),
.VAR70(VAR70),
.VAR24(VAR24),
.VAR29(VAR29),
.VAR55(VAR55),
.VAR3(VAR3),
.VAR95(VAR95),
.VAR65(VAR65),
.VAR45(VAR45),
.VAR6(VAR6),
.VAR80(VAR80),
.VAR58(VAR58)
);
endmodule
|
gpl-3.0
|
aj-michael/Digital-Systems
|
Pong/Phase2/vsyncModule.v
| 1,275 |
module MODULE1(VAR2, VAR8, VAR12, VAR4, VAR7, VAR9, VAR5, reset, VAR1);
parameter VAR11=10;
input [VAR11-1:0] VAR8, VAR12, VAR4, VAR7;
input reset, VAR1, VAR2;
output VAR9;
output reg [VAR11-1:0] VAR5;
wire [VAR11-1:0] VAR14;
VAR17 VAR10(VAR2, VAR13, reset, VAR1);
assign VAR9 = ~((VAR14 > VAR4+VAR12) && (VAR14 <= VAR4+VAR12+VAR8));
always@(VAR14, VAR8, VAR7, VAR4, VAR12)
VAR5<=VAR14;
wire [VAR11-1:0] VAR16 = VAR8 + VAR12 + VAR4 + VAR7;
assign VAR15 = VAR14 == VAR16;
VAR6 VAR3(10'd0,10'd0, VAR16, VAR14, VAR15,VAR15||VAR13, , reset, VAR1) ;
endmodule
|
mit
|
mbus/mbus
|
mbus/verilog/mbus_addr_rf.v
| 1,371 |
module MODULE1(
input VAR3,
input VAR1,
output reg [VAR10-1:0] VAR2,
input [VAR10-1:0] VAR7,
output reg VAR6,
input VAR8,
input VAR4
);
wire VAR5 = (VAR3 & VAR4);
wire VAR9 = (VAR8 & (~VAR1));
wire VAR9 = VAR8;
always @ (posedge VAR9 or negedge VAR5)
begin
if (~VAR5)
begin
VAR2 <= {VAR10{1'b1}};
VAR6 <= 0;
end
else
begin
VAR2 <= VAR7;
VAR6 <= 1;
end
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/einvp/sky130_fd_sc_ls__einvp_1.v
| 2,130 |
module MODULE2 (
VAR3 ,
VAR8 ,
VAR5 ,
VAR4,
VAR6,
VAR9 ,
VAR2
);
output VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR9 ;
input VAR2 ;
VAR7 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR8 ,
VAR5
);
output VAR3 ;
input VAR8 ;
input VAR5;
supply1 VAR4;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR2 ;
VAR7 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
skatpgusskat/KoreaUnivHomework_2015_1
|
Computer Architecture/Homework/Lab10/kustar.v
| 6,182 |
module MODULE1;
reg VAR48, VAR33;
wire VAR78;
reg [31:0] VAR64;
reg [31:0] VAR67;
reg [31:0] VAR49;
reg [31:0] VAR75;
reg [31:0] VAR18;
reg [31:0] VAR27;
reg [4:0] VAR3;
reg [4:0] VAR26;
reg [8:0] VAR30;
reg [31:0] VAR81;
reg VAR36;
reg [31:0] VAR13;
reg [31:0] VAR62;
reg [4:0] VAR38;
reg [4:0] VAR12;
reg [31:0] VAR31;
reg [31:0] VAR52;
reg [4:0] VAR44;
reg [2:0] VAR57;
wire [31:0] VAR55, VAR70, VAR61, VAR34, VAR20;
wire [31:0] VAR46, VAR40, VAR15, VAR54, VAR10, VAR53;
wire [31:0] VAR2;
wire [4:0] VAR80;
wire [31:0] VAR63, VAR51, VAR14, VAR24;
wire [2:0] VAR84;
wire [31:0] VAR69;
wire VAR76, VAR45, VAR60, VAR43, VAR39, VAR22, VAR17;
wire [1:0] VAR29;
wire VAR1;
reg [31:0] VAR7;
reg VAR50;
reg VAR68;
reg [31:0] VAR79;
VAR74 VAR6 (VAR61, VAR81, VAR53, VAR53, VAR55, {VAR1,{VAR12[4] & VAR36}});
VAR4 VAR35 (VAR55, VAR70, VAR48, VAR33, VAR50);
VAR8 VAR47 (VAR70, VAR7, VAR61);
VAR65 VAR41 (VAR70, VAR79, VAR34, VAR68, VAR50, VAR48);
VAR72 VAR23 (VAR67, VAR10);
VAR5 VAR9 (VAR10, VAR70, VAR53);
VAR11 VAR73 ({VAR67[25:21]}, VAR46, {VAR67[20:16]}, VAR40, VAR44, VAR15, VAR48, VAR68, VAR57[1]);
VAR58 VAR37 ({VAR67[15:0]}, VAR54);
VAR21 VAR82 (VAR48, VAR33, {VAR67[31:26]},
VAR76, VAR45, VAR60, VAR29, VAR43, VAR39, VAR22, VAR17,
VAR1);
VAR25 VAR66 (VAR18, VAR27, VAR63, {VAR30[6]});
VAR42 VAR83 (VAR3, VAR26, VAR80, VAR30[5]);
VAR72 VAR32 (VAR27, VAR51);
VAR8 VAR16 (VAR49, VAR51, VAR14);
VAR28 VAR19 (VAR75, VAR63, VAR84, VAR24, VAR78);
VAR77 VAR59 (VAR27[5:0], VAR30[8:7], VAR84);
VAR65 VAR71 (VAR13, VAR62, VAR69, VAR12[2], VAR12[1], VAR48);
VAR25 VAR56 (VAR52, VAR31, VAR15, VAR57[0]);
begin
begin
|
mit
|
lkesteloot/alice
|
alice4/fpga/Alice4-DE0/SDRAM_clock_bb.v
| 11,181 |
module MODULE1 (
VAR4,
VAR2,
VAR3,
VAR1);
input VAR4;
input VAR2;
output VAR3;
output VAR1;
tri0 VAR4;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.v
| 2,398 |
module MODULE2 (
VAR11 ,
VAR5,
VAR1,
VAR6 ,
VAR7 ,
VAR4,
VAR3,
VAR2 ,
VAR8
);
output VAR11 ;
input VAR5;
input VAR1;
input VAR6 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR8 ;
VAR9 VAR10 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR11 ,
VAR5,
VAR1,
VAR6 ,
VAR7
);
output VAR11 ;
input VAR5;
input VAR1;
input VAR6 ;
input VAR7 ;
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR8 ;
VAR9 VAR10 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/util_upack/util_upack.v
| 10,703 |
module MODULE1 (
VAR60,
VAR18,
VAR36,
VAR69,
VAR23,
VAR37,
VAR67,
VAR39,
VAR53,
VAR74,
VAR15,
VAR32,
VAR71,
VAR11,
VAR1,
VAR8,
VAR47,
VAR7,
VAR43,
VAR76,
VAR34,
VAR46,
VAR56,
VAR20,
VAR17,
VAR72,
VAR40,
VAR14,
VAR49,
VAR68,
VAR27,
VAR52,
VAR9,
VAR57,
VAR19,
VAR22,
VAR10,
VAR58);
parameter VAR6 = 32;
parameter VAR54 = 8;
localparam VAR2 = 8;
localparam VAR12 = VAR54;
localparam VAR65 = VAR6/16;
localparam VAR3 = VAR6*VAR2;
localparam VAR55 = VAR6*VAR12;
input VAR60;
input VAR18;
input VAR36;
output [(VAR6-1):0] VAR69;
output VAR23;
input VAR37;
input VAR67;
output [(VAR6-1):0] VAR39;
output VAR53;
input VAR74;
input VAR15;
output [(VAR6-1):0] VAR32;
output VAR71;
input VAR11;
input VAR1;
output [(VAR6-1):0] VAR8;
output VAR47;
input VAR7;
input VAR43;
output [(VAR6-1):0] VAR76;
output VAR34;
input VAR46;
input VAR56;
output [(VAR6-1):0] VAR20;
output VAR17;
input VAR72;
input VAR40;
output [(VAR6-1):0] VAR14;
output VAR49;
input VAR68;
input VAR27;
output [(VAR6-1):0] VAR52;
output VAR9;
input VAR57;
output VAR19;
output VAR22;
output VAR10;
input [((VAR54*VAR6)-1):0] VAR58;
reg VAR22 = 'd0;
reg VAR10 = 'd0;
reg [(VAR3-1):0] VAR75 = 'd0;
reg [ 7:0] VAR63 = 'd0;
reg VAR48;
reg VAR33;
reg VAR38;
reg VAR29;
reg VAR4;
reg VAR19;
wire VAR5;
wire VAR66[(VAR2-1):0];
wire VAR41[(VAR2-1):0];
wire [(VAR3-1):0] VAR30[(VAR2-1):0];
wire [(VAR65-1):0] VAR70;
wire [(VAR65-1):0] VAR26;
wire [(VAR65-1):0] VAR61;
wire [(VAR65-1):0] VAR42;
wire [(VAR65-1):0] VAR50;
wire [(VAR65-1):0] VAR73;
wire [(VAR65-1):0] VAR13;
wire [(VAR65-1):0] VAR28;
genvar VAR24;
assign VAR5 = VAR27 | VAR40 | VAR56 | VAR43 |
VAR1 | VAR15 | VAR67 | VAR36;
assign VAR23 = | VAR63 & VAR18 & VAR19;
assign VAR53 = | VAR63 & VAR37 & VAR19;
assign VAR71 = | VAR63 & VAR74 & VAR19;
assign VAR47 = | VAR63 & VAR11 & VAR19;
assign VAR34 = | VAR63 & VAR7 & VAR19;
assign VAR17 = | VAR63 & VAR46 & VAR19;
assign VAR49 = | VAR63 & VAR72 & VAR19;
assign VAR9 = | VAR63 & VAR68 & VAR19;
always @(posedge VAR60) begin
VAR48 <= VAR57;
VAR33 <= VAR48;
VAR38 <= VAR33;
VAR29 <= VAR38;
VAR4 <= VAR29;
if (VAR63[VAR12-1] == 1'b1) begin
VAR19 <= VAR29;
end else begin
VAR19 <= VAR4;
end
end
always @(posedge VAR60) begin
VAR22 <= VAR66[7] | VAR66[6] |
VAR66[5] | VAR66[4] |
VAR66[3] | VAR66[2] |
VAR66[1] | VAR66[0];
VAR10 <= VAR41[7] | VAR41[6] |
VAR41[5] | VAR41[4] |
VAR41[3] | VAR41[2] |
VAR41[1] | VAR41[0];
VAR75 <= VAR30[7] | VAR30[6] |
VAR30[5] | VAR30[4] |
VAR30[3] | VAR30[2] |
VAR30[1] | VAR30[0];
VAR63[7] <= | VAR70;
VAR63[6] <= | VAR26;
VAR63[5] <= | VAR61;
VAR63[4] <= | VAR42;
VAR63[3] <= | VAR50;
VAR63[2] <= | VAR73;
VAR63[1] <= | VAR13;
VAR63[0] <= | VAR28;
end
generate
if (VAR12 < VAR2) begin
for (VAR24 = VAR12; VAR24 < VAR2; VAR24 = VAR24 + 1) begin: VAR35
assign VAR66[VAR24] = 'd0;
assign VAR41[VAR24] = 'd0;
assign VAR30[VAR24] = 'd0;
end
end
for (VAR24 = 0; VAR24 < VAR12; VAR24 = VAR24 + 1) begin: VAR44
VAR25 #(
.VAR12 (VAR12),
.VAR2 (VAR2),
.VAR6 (VAR6),
.VAR21 ((VAR24+1)))
VAR45 (
.VAR60 (VAR60),
.VAR22 (VAR5),
.VAR58 (VAR58),
.VAR63 (VAR63[VAR24]),
.VAR64 (VAR66[VAR24]),
.VAR59 (VAR41[VAR24]),
.VAR75 (VAR30[VAR24]));
end
endgenerate
generate
for (VAR24 = 0; VAR24 < VAR65; VAR24 = VAR24 + 1) begin: VAR51
VAR62 VAR31 (
.VAR60 (VAR60),
.VAR16 ({VAR68, VAR72, VAR46, VAR7,
VAR11, VAR74, VAR37, VAR18}),
.VAR69 (VAR69[((16*VAR24)+15):(16*VAR24)]),
.VAR39 (VAR39[((16*VAR24)+15):(16*VAR24)]),
.VAR32 (VAR32[((16*VAR24)+15):(16*VAR24)]),
.VAR8 (VAR8[((16*VAR24)+15):(16*VAR24)]),
.VAR76 (VAR76[((16*VAR24)+15):(16*VAR24)]),
.VAR20 (VAR20[((16*VAR24)+15):(16*VAR24)]),
.VAR14 (VAR14[((16*VAR24)+15):(16*VAR24)]),
.VAR52 (VAR52[((16*VAR24)+15):(16*VAR24)]),
.VAR63 ({VAR70[VAR24], VAR26[VAR24],
VAR61[VAR24], VAR42[VAR24],
VAR50[VAR24], VAR73[VAR24],
VAR13[VAR24], VAR28[VAR24]}),
.VAR75 (VAR75[((VAR2*16*(VAR24+1))-1):(VAR2*16*VAR24)]));
end
endgenerate
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/mux4/sky130_fd_sc_lp__mux4_1.v
| 2,444 |
module MODULE1 (
VAR10 ,
VAR5 ,
VAR12 ,
VAR7 ,
VAR11 ,
VAR9 ,
VAR3 ,
VAR6,
VAR13,
VAR8 ,
VAR1
);
output VAR10 ;
input VAR5 ;
input VAR12 ;
input VAR7 ;
input VAR11 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR13;
input VAR8 ;
input VAR1 ;
VAR2 VAR4 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR13(VAR13),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR10 ,
VAR5,
VAR12,
VAR7,
VAR11,
VAR9,
VAR3
);
output VAR10 ;
input VAR5;
input VAR12;
input VAR7;
input VAR11;
input VAR9;
input VAR3;
supply1 VAR6;
supply0 VAR13;
supply1 VAR8 ;
supply0 VAR1 ;
VAR2 VAR4 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/xor3/sky130_fd_sc_hs__xor3.symbol.v
| 1,273 |
module MODULE1 (
input VAR5,
input VAR6,
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR1;
endmodule
|
apache-2.0
|
deepakcu/maestro
|
fpga/DE4_Ethernet_0/lfsr.v
| 6,680 |
module MODULE1 #(
parameter VAR2=8,
parameter VAR10=256
) (
VAR7,
VAR9,
VAR5,
enable,
clk,
reset
);
output wire [31:0] VAR9;
output reg [31:0] VAR5;
wire [31:0] VAR1;
input [31:0] VAR7;
input enable, clk, reset;
reg [31:0] out;
wire VAR4;
wire [31:0] VAR6;
reg state, VAR11;
reg [5:0] select;
wire [31:0] VAR3;
localparam VAR12=0;
localparam VAR8=1;
assign VAR9 = (state==VAR12)?(out&VAR3):32'b1;
assign VAR1 = VAR5;
assign VAR3 = ~(~0<<select);
assign VAR4 =
(select==2) ? !(out[1] ^ out[0]): (select==3) ? !(out[2] ^ out[1]): (select==4) ? !(out[3] ^ out[2]): (select==5) ? !(out[4] ^ out[2]): (select==6) ? !(out[5] ^ out[4]): (select==7) ? !(out[6] ^ out[5]): (select==8) ? !(out[7] ^ out[5] ^ out[4] ^ out[3]): (select==9) ? !(out[8] ^ out[4]): (select==10) ? !(out[9] ^ out[6]): (select==11) ? !(out[8] ^ out[10]): (select==12) ? !(out[11] ^ out[10] ^ out[9] ^ out[3]): (select==13) ? !(out[12] ^ out[11] ^ out[10] ^ out[7]): (select==14) ? !(out[13] ^ out[12] ^ out[11] ^ out[1]): (select==15) ? !(out[14] ^ out[13]): (select==16) ? !(out[15] ^ out[13] ^ out[12] ^ out[10]): (select==17) ? !(out[16] ^ out[13]): (select==18) ? !(out[17] ^ out[10]): (select==19) ? !(out[18] ^ out[17] ^ out[16] ^ out[13]): (select==20) ? !(out[19] ^ out[16]): (select==21) ? !(out[20] ^ out[18]): (select==22) ? !(out[21] ^ out[20]): (select==23) ? !(out[22] ^ out[17]): !(out[0] ^ out[1]);
always@ begin
VAR11 = state;
case(state)
VAR12: begin
if(VAR6==0)
VAR11 = (enable)?VAR8:VAR12;
end
VAR8: begin
VAR11 = (enable)?VAR12:VAR8;
end
default: VAR11 = VAR12;
endcase
end
always@(posedge clk or posedge reset) begin
if(reset)
end
VAR5 <= VAR6; else
VAR5 <= VAR1;
end
always@(posedge clk or posedge reset) begin
if(reset)
state <= VAR12;
end
else
state <= VAR11;
end
endmodule
|
apache-2.0
|
sergev/vak-opensource
|
hardware/s3esk-openrisc/or1200/or1200_ic_ram.v
| 5,719 |
module MODULE1(
clk, rst,
VAR19, VAR16, VAR12,
addr, en, VAR3, VAR14, VAR6
);
parameter VAR7 = VAR2;
parameter VAR1 = VAR15;
input clk;
input rst;
input [VAR1-1:0] addr;
input en;
input [3:0] VAR3;
input [VAR7-1:0] VAR14;
output [VAR7-1:0] VAR6;
input VAR19;
input [VAR11 - 1:0] VAR12;
output VAR16;
assign VAR6 = {VAR7{1'b0}};
assign VAR16 = VAR19;
VAR4 VAR18(
VAR13 VAR18(
VAR9 VAR18(
.VAR19(VAR19),
.VAR16(VAR16),
.VAR12(VAR12),
.clk(clk),
.rst(rst),
.VAR17(en),
.VAR3(VAR3[0]),
.VAR5(1'b1),
.addr(addr),
.VAR8(VAR14),
.VAR10(VAR6)
);
endmodule
|
apache-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/lib/verilog/core/bin_cam/src/decoder.v
| 4,309 |
module MODULE1 (
VAR1,
VAR5
);
parameter VAR2 = 64;
parameter VAR8 = VAR4(VAR2);
input [VAR8-1:0] VAR1;
output [VAR2-1:0] VAR5;
reg [VAR2-1:0] VAR5;
integer VAR6;
always @(*)
begin
VAR5 = 0;
VAR5 = VAR5 + 2**(VAR1);
end
function integer VAR4;
input [32:0] VAR7;
integer VAR3;
begin
VAR4 = 1;
for (VAR3=0; 2**VAR3 < VAR7; VAR3=VAR3+1)
VAR4 = VAR3 + 1;
end
endfunction
endmodule
|
mit
|
audiocircuit/NCSU-Low-Power-RFID
|
Memory/slave.v
| 8,001 |
module MODULE1(
input wire [6:0] VAR2,
input wire [7:0] VAR12,
input wire en,
input wire reset,
input wire VAR15,
inout wire VAR9
);
reg VAR7, VAR8, VAR10;
reg [7:0] VAR6;
reg [6:0] VAR3;
reg [2:0] state;
reg [4:0] counter;
reg VAR13, VAR1;
reg VAR5, VAR4;
assign #(1) VAR9 = (VAR5) ? ( VAR13 ) ? 1'VAR11 : 1'b0 : 1'VAR11;
assign VAR14 = VAR9;
always@( negedge VAR15 or negedge reset )
begin
if( !reset )
begin
VAR5 <= 0;
VAR13 <= 0;
end
else
begin
VAR5 <= VAR4;
VAR13 <= VAR1;
end
end
always@( negedge VAR9 )
begin
if( VAR15 )
begin
VAR8 <= 1;
end
else
begin
VAR8 <= 0;
end
end
always@( posedge VAR9 )
begin
if( VAR15 )
begin
VAR7 <= 1;
end
else
begin
VAR7 <= 0;
end
end
always@(posedge VAR15 or negedge reset)
begin
if( ~reset )
begin
state <= 0;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
else
begin
case( state )
0:
begin
if( VAR8 && en )
begin
state <=1;
VAR3 <= {VAR3, VAR9};
counter <= 1;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
else
begin
state <= 0;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
end
1:
begin
if(counter < 7 )
begin
state <= 1;
VAR3 <= {VAR3, VAR9};
counter <= counter +1;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
else
begin
if(VAR3 == VAR2)
begin
if( VAR9 )
begin
state <= 2;
VAR3 <= 0;
counter <= 0;
VAR10 <= VAR9;
VAR6 <= 0;
VAR4 <= 1;
VAR1 <= 0;
end
else
begin
state <= 5;
VAR3 <= 0;
counter <= 0;
VAR10 <= VAR9;
VAR6 <= 0;
VAR4 <= 1;
VAR1 <= 0;
end
end
else
begin
state <= 0;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
end
end
2:
begin
if( !VAR7 )
begin
if( counter < 8 )
begin
state <= 2;
VAR3 <= 0;
counter <= counter + 1;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 1;
VAR1 <= VAR12[7 - counter];
end
else
begin
state <= 4;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
end
else
begin
state <= 0;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
end
3:
begin
if( !VAR7 )
begin
if( counter < 7 )
begin
state <= 3;
VAR3 <= 0;
counter <= counter + 1;
VAR10 <= 0;
VAR6 <= {VAR6, VAR9};
VAR4 <= 0;
VAR1 <= 0;
end
else if(counter == 7)
begin
state <= 3;
VAR3 <= 0;
counter <= counter +1;
VAR10 <= 0;
VAR6 <= {VAR6,VAR9};
VAR4 <= 0;
VAR1 <= 0;
end
else
begin
state <= 3;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= {VAR6,VAR9};
VAR4 <= 1;
VAR1 <= 0;
end
end
else
begin
state <= 0;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
end
4:
begin
if( VAR9 )
begin
state <= 0;
VAR3 <= 0;
counter <= 0;
VAR10 <= 0;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
else
begin
state <= 2;
VAR3 <= 0;
counter <= counter + 1;
VAR10 <= VAR10;
VAR6 <= 0;
VAR4 <= 1;
VAR1 <= VAR12[7 - counter];
end
end
5:
begin
state <= 3;
VAR3 <= 0;
counter <= 0;
VAR10 <= VAR10;
VAR6 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end
endcase
end
end
endmodule
|
gpl-3.0
|
m-labs/milkymist
|
cores/vgafb/rtl/vgafb_fifo64to16.v
| 1,817 |
module MODULE1(
input VAR10,
input VAR7,
input VAR9,
input [63:0] VAR8,
output VAR1,
output VAR6,
output reg [15:0] do,
input VAR2
);
reg [63:0] VAR12[0:7];
reg [2:0] VAR4;
reg [4:0] VAR5;
reg [5:0] VAR3;
wire [63:0] VAR11;
assign VAR11 = VAR12[VAR5[4:2]];
always @(*) begin
case(VAR5[1:0])
2'd0: do <= VAR11[63:48];
2'd1: do <= VAR11[47:32];
2'd2: do <= VAR11[31:16];
2'd3: do <= VAR11[15:0];
endcase
end
always @(posedge VAR10) begin
if(VAR7) begin
VAR4 = 3'd0;
VAR5 = 5'd0;
VAR3 = 6'd0;
end else begin
if(VAR9) begin
VAR12[VAR4] = VAR8;
VAR4 = VAR4 + 3'd1;
VAR3 = VAR3 + 6'd4;
end
if(VAR2) begin
VAR5 = VAR5 + 5'd1;
VAR3 = VAR3 - 6'd1;
end
end
end
assign VAR6 = ~(VAR3 == 6'd0);
assign VAR1 = VAR3 <= 6'd16;
endmodule
|
lgpl-3.0
|
UCLONG/NetEmulation
|
BEE3_top/C3D_original_code/b2b/src/aur1_error_detect.v
| 9,432 |
module MODULE1
(
VAR3,
VAR17,
VAR7,
VAR1,
VAR13,
VAR15,
VAR4,
VAR12,
VAR16,
VAR6
);
input VAR3;
output VAR17;
output VAR7;
output VAR1;
input VAR13;
input [1:0] VAR15;
input [1:0] VAR4;
input VAR12;
input VAR16;
input VAR6;
reg VAR1;
reg VAR7;
reg [0:1] VAR5;
reg VAR10;
reg [0:1] VAR18;
reg [0:1] VAR14;
reg VAR9; reg VAR8;
always @(posedge VAR6)
if(VAR3)
begin
VAR18[0] <= VAR11 VAR15[1]|VAR4[1];
VAR18[1] <= VAR11 VAR15[0]|VAR4[0];
end
else
begin
VAR18[0] <= VAR11 1'b0;
VAR18[1] <= VAR11 1'b0;
end
always @(posedge VAR6)
begin
VAR9 <= VAR11 |VAR18;
VAR7 <= VAR11 VAR9;
end
always @(posedge VAR6)
if(VAR3)
begin
VAR8 <= VAR11 (VAR13 | VAR12 |
VAR16 | VAR10);
VAR1 <= VAR11 VAR8;
end
else
begin
VAR8 <= VAR11 1'b0;
VAR1 <= VAR11 1'b0;
end
assign VAR17 = VAR8;
always @(posedge VAR6)
if(!VAR3) VAR14 <= VAR11 2'b00;
else
begin
casez({VAR18, VAR14})
4'b0000 : VAR14 <= VAR11 2'b10;
4'b0001 : VAR14 <= VAR11 2'b11;
4'b0010 : VAR14 <= VAR11 2'b00;
4'b0011 : VAR14 <= VAR11 2'b01;
4'VAR2?1?? : VAR14 <= VAR11 2'b00;
4'b10?? : VAR14 <= VAR11 2'b01;
default : VAR14 <= VAR11 VAR14;
endcase
end
always @(posedge VAR6)
if(!VAR3) VAR5 <= VAR11 2'b00;
else
begin
casez({VAR18,VAR14,VAR5})
6'b000??? : VAR5 <= VAR11 VAR5;
6'b001?00 : VAR5 <= VAR11 2'b00;
6'b001?01 : VAR5 <= VAR11 2'b00;
6'b001?10 : VAR5 <= VAR11 2'b01;
6'b001?11 : VAR5 <= VAR11 2'b10;
6'b010000 : VAR5 <= VAR11 2'b01;
6'b010100 : VAR5 <= VAR11 2'b01;
6'b011000 : VAR5 <= VAR11 2'b01;
6'b011100 : VAR5 <= VAR11 2'b00;
6'b010001 : VAR5 <= VAR11 2'b10;
6'b010101 : VAR5 <= VAR11 2'b10;
6'b011001 : VAR5 <= VAR11 2'b10;
6'b011101 : VAR5 <= VAR11 2'b01;
6'b010010 : VAR5 <= VAR11 2'b11;
6'b010110 : VAR5 <= VAR11 2'b11;
6'b011010 : VAR5 <= VAR11 2'b11;
6'b011110 : VAR5 <= VAR11 2'b10;
6'b01??11 : VAR5 <= VAR11 2'b11;
6'b10??00 : VAR5 <= VAR11 2'b01;
6'b10??01 : VAR5 <= VAR11 2'b10;
6'b10??10 : VAR5 <= VAR11 2'b11;
6'b10??11 : VAR5 <= VAR11 2'b11;
6'b11??00 : VAR5 <= VAR11 2'b10;
6'b11??01 : VAR5 <= VAR11 2'b11;
6'b11??10 : VAR5 <= VAR11 2'b11;
6'b11??11 : VAR5 <= VAR11 2'b11;
endcase
end
always @(posedge VAR6)
if(!VAR3) VAR10 <= VAR11 1'b0;
else
begin
casez({VAR18, VAR14, VAR5})
6'b010011 : VAR10 <= VAR11 1'b1;
6'b010111 : VAR10 <= VAR11 1'b1;
6'b011011 : VAR10 <= VAR11 1'b1;
6'b10??11 : VAR10 <= VAR11 1'b1;
6'b11??1? : VAR10 <= VAR11 1'b1;
default : VAR10 <= VAR11 1'b0;
endcase
end
endmodule
|
gpl-3.0
|
bfarago/xmos_cpld_slice
|
altera/concept/xmos_cpld_slice.v
| 11,565 |
module MODULE1
(
VAR100,
VAR47,
VAR36,
VAR81,
VAR83,
VAR11,
VAR78,
VAR23,
VAR119,
VAR72,
VAR76,
VAR98,
VAR21,
VAR3,
VAR63,
VAR12,
VAR94,
VAR18,
VAR37,
VAR73,
VAR42,
VAR58,
VAR104,
VAR9,
VAR52,
VAR61,
VAR101,
VAR107,
VAR54,
VAR48,
VAR35,
VAR120,
VAR5,
VAR15,
VAR124,
VAR59,
VAR67,
VAR93,
VAR39,
VAR49,
VAR10,
VAR86,
VAR122,
VAR106,
VAR121,
VAR125,
VAR57,
VAR41,
VAR75,
VAR88,
VAR26,
VAR2,
VAR68,
VAR110
);
input VAR100;
input VAR47;
inout VAR36;
inout VAR81;
inout VAR83;
inout VAR11;
inout VAR78;
inout VAR23;
inout VAR119;
inout VAR72;
inout VAR76;
inout VAR98;
inout VAR21;
inout VAR3;
inout VAR63;
inout VAR12;
inout VAR94;
inout VAR18;
inout VAR37;
inout VAR73;
inout VAR42;
inout VAR58;
inout VAR104;
inout VAR9;
inout VAR52;
inout VAR61;
inout VAR101;
inout VAR107;
inout VAR54;
inout VAR48;
inout VAR35;
inout VAR120;
inout VAR5;
inout VAR15;
inout VAR124;
inout VAR59;
inout VAR67;
inout VAR93;
inout VAR39;
inout VAR49;
inout VAR10;
inout VAR86;
inout VAR122;
inout VAR106;
inout VAR121;
inout VAR125;
inout VAR57;
inout VAR41;
inout VAR75;
inout VAR88;
inout VAR26;
inout VAR2;
inout VAR68;
inout VAR110;
localparam VAR71 =25;
localparam VAR55 =0;
reg [VAR71-1:0] VAR99;
wire [VAR71-1:0] VAR4;
wire [VAR71-1:0] VAR38;
reg [VAR71-1:0] VAR117;
reg [1:0] state;
reg [8:0] VAR77;
wire [2:0] VAR108;
assign VAR108 ={VAR4[2], VAR4[1], VAR4[0]};
wire VAR44;
wire VAR70;
assign VAR44 = VAR4[2];
assign VAR70 = VAR4[1];
wire VAR80;
assign VAR80= VAR4[9];
VAR16 VAR111 (.VAR79(VAR99[ 0]), .VAR97(VAR117[ 0]), .VAR114(VAR4[ 0]),.VAR34(VAR21));
VAR16 VAR89 (.VAR79(VAR99[ 1]), .VAR97(VAR117[ 1]), .VAR114(VAR4[ 1]),.VAR34(VAR76));
VAR16 VAR40 (.VAR79(VAR99[ 2]), .VAR97(VAR117[ 2]), .VAR114(VAR4[ 2]),.VAR34(VAR119));
VAR16 VAR116 (.VAR79(VAR99[ 3]), .VAR97(VAR117[ 3]), .VAR114(VAR4[ 3]),.VAR34(VAR78));
VAR16 VAR112 (.VAR79(VAR99[ 4]), .VAR97(VAR117[ 4]), .VAR114(VAR4[ 4]),.VAR34(VAR83));
VAR16 VAR65 (.VAR79(VAR99[ 5]), .VAR97(VAR117[ 5]), .VAR114(VAR4[ 5]),.VAR34(VAR36));
VAR16 VAR115 (.VAR79(VAR99[ 6]), .VAR97(VAR117[ 6]), .VAR114(VAR4[ 6]),.VAR34(VAR68));
VAR16 VAR28 (.VAR79(VAR99[ 7]), .VAR97(VAR117[ 7]), .VAR114(VAR4[ 7]),.VAR34(VAR26));
VAR16 VAR74 (.VAR79(VAR99[ 8]), .VAR97(VAR117[ 8]), .VAR114(VAR4[ 8]),.VAR34(VAR75));
VAR16 VAR7 (.VAR79(VAR99[ 9]), .VAR97(VAR117[ 9]), .VAR114(VAR4[ 9]),.VAR34(VAR125));
VAR16 VAR66 (.VAR79(VAR99[10]), .VAR97(VAR117[10]), .VAR114(VAR4[10]),.VAR34(VAR106));
VAR16 VAR27 (.VAR79(VAR99[11]), .VAR97(VAR117[11]), .VAR114(VAR4[11]),.VAR34(VAR86));
VAR16 VAR25 (.VAR79(VAR99[12]), .VAR97(VAR117[12]), .VAR114(VAR4[12]),.VAR34(VAR63));
VAR16 VAR13 (.VAR79(VAR99[13]), .VAR97(VAR117[13]), .VAR114(VAR4[13]),.VAR34(VAR98));
VAR16 VAR123 (.VAR79(VAR99[14]), .VAR97(VAR117[14]), .VAR114(VAR4[14]),.VAR34(VAR72));
VAR16 VAR1 (.VAR79(VAR99[15]), .VAR97(VAR117[15]), .VAR114(VAR4[15]),.VAR34(VAR23));
VAR16 VAR8 (.VAR79(VAR99[16]), .VAR97(VAR117[16]), .VAR114(VAR4[16]),.VAR34(VAR11));
VAR16 VAR30 (.VAR79(VAR99[17]), .VAR97(VAR117[17]), .VAR114(VAR4[17]),.VAR34(VAR81));
VAR16 VAR69 (.VAR79(VAR99[18]), .VAR97(VAR117[18]), .VAR114(VAR4[18]),.VAR34(VAR110));
VAR16 VAR109 (.VAR79(VAR99[19]), .VAR97(VAR117[19]), .VAR114(VAR4[19]),.VAR34(VAR2));
VAR16 VAR95 (.VAR79(VAR99[20]), .VAR97(VAR117[20]), .VAR114(VAR4[20]),.VAR34(VAR88));
VAR16 VAR31 (.VAR79(VAR99[21]), .VAR97(VAR117[21]), .VAR114(VAR4[21]),.VAR34(VAR41));
VAR16 VAR32 (.VAR79(VAR99[22]), .VAR97(VAR117[22]), .VAR114(VAR4[22]),.VAR34(VAR121));
VAR16 VAR19 (.VAR79(VAR99[23]), .VAR97(VAR117[23]), .VAR114(VAR4[23]),.VAR34(VAR122));
VAR16 VAR17 (.VAR79(VAR99[24]), .VAR97(VAR117[24]), .VAR114(VAR4[24]),.VAR34(VAR10));
VAR16 VAR92 (.VAR79(VAR99[ 0]), .VAR97(~VAR117[ 0]), .VAR114(VAR38[ 0]),.VAR34(VAR94));
VAR16 VAR126 (.VAR79(VAR99[ 1]), .VAR97(~VAR117[ 1]), .VAR114(VAR38[ 1]),.VAR34(VAR37));
VAR16 VAR82 (.VAR79(VAR99[ 2]), .VAR97(~VAR117[ 2]), .VAR114(VAR38[ 2]),.VAR34(VAR42));
VAR16 VAR14 (.VAR79(VAR99[ 3]), .VAR97(~VAR117[ 3]), .VAR114(VAR38[ 3]),.VAR34(VAR104));
VAR16 VAR64 (.VAR79(VAR99[ 4]), .VAR97(~VAR117[ 4]), .VAR114(VAR38[ 4]),.VAR34(VAR52));
VAR16 VAR33 (.VAR79(VAR99[ 5]), .VAR97(~VAR117[ 5]), .VAR114(VAR38[ 5]),.VAR34(VAR101));
VAR16 VAR84 (.VAR79(VAR99[ 6]), .VAR97(~VAR117[ 6]), .VAR114(VAR38[ 6]),.VAR34(VAR54));
VAR16 VAR105 (.VAR79(VAR99[ 7]), .VAR97(~VAR117[ 7]), .VAR114(VAR38[ 7]),.VAR34(VAR35));
VAR16 VAR46 (.VAR79(VAR99[ 8]), .VAR97(~VAR117[ 8]), .VAR114(VAR38[ 8]),.VAR34(VAR5));
VAR16 VAR113 (.VAR79(VAR99[ 9]), .VAR97(~VAR117[ 9]), .VAR114(VAR38[ 9]),.VAR34(VAR124));
VAR16 VAR29 (.VAR79(VAR99[10]), .VAR97(~VAR117[10]), .VAR114(VAR38[10]),.VAR34(VAR67));
VAR16 VAR60 (.VAR79(VAR99[11]), .VAR97(~VAR117[11]), .VAR114(VAR38[11]),.VAR34(VAR39));
VAR16 VAR20 (.VAR79(VAR99[12]), .VAR97(~VAR117[12]), .VAR114(VAR38[12]),.VAR34(VAR12));
VAR16 VAR45 (.VAR79(VAR99[13]), .VAR97(~VAR117[13]), .VAR114(VAR38[13]),.VAR34(VAR18));
VAR16 VAR43 (.VAR79(VAR99[14]), .VAR97(~VAR117[14]), .VAR114(VAR38[14]),.VAR34(VAR73));
VAR16 VAR87 (.VAR79(VAR99[15]), .VAR97(~VAR117[15]), .VAR114(VAR38[15]),.VAR34(VAR58));
VAR16 VAR118 (.VAR79(VAR99[16]), .VAR97(~VAR117[16]), .VAR114(VAR38[16]),.VAR34(VAR9));
VAR16 VAR22 (.VAR79(VAR99[17]), .VAR97(~VAR117[17]), .VAR114(VAR38[17]),.VAR34(VAR61));
VAR16 VAR96 (.VAR79(VAR99[18]), .VAR97(~VAR117[18]), .VAR114(VAR38[18]),.VAR34(VAR107));
VAR16 VAR90 (.VAR79(VAR99[19]), .VAR97(~VAR117[19]), .VAR114(VAR38[19]),.VAR34(VAR48));
VAR16 VAR53 (.VAR79(VAR99[20]), .VAR97(~VAR117[20]), .VAR114(VAR38[20]),.VAR34(VAR120));
VAR16 VAR91 (.VAR79(VAR99[21]), .VAR97(~VAR117[21]), .VAR114(VAR38[21]),.VAR34(VAR15));
VAR16 VAR51 (.VAR79(VAR99[22]), .VAR97(~VAR117[22]), .VAR114(VAR38[22]),.VAR34(VAR59));
VAR16 VAR62 (.VAR79(VAR99[23]), .VAR97(~VAR117[23]), .VAR114(VAR38[23]),.VAR34(VAR93));
VAR16 VAR50 (.VAR79(VAR99[24]), .VAR97(~VAR117[24]), .VAR114(VAR38[24]),.VAR34(VAR49));
genvar VAR56;
generate
for (VAR56=VAR55; VAR56<VAR71; VAR56=VAR56+1)
begin : VAR24
end
endgenerate
integer VAR79;
always @(posedge VAR100 or negedge VAR47) begin
if (~VAR47) begin
VAR117 = 'b0000000000000000000000000; VAR99=0;
VAR77= 255; state= VAR85;
end
else
begin
for (VAR79=VAR55; VAR79<VAR71; VAR79=VAR79+1)
begin
VAR99[VAR79] = VAR117[VAR79]?VAR38[VAR79]:VAR4[VAR79];
end
case (state)
begin
if (VAR77 == 0)
begin
state= VAR103; end
if (VAR44)
begin
state= VAR6;
end
end
if (~VAR44)
begin
state= VAR70 ? VAR102 : VAR103 ;
end
VAR117 = 'b0001001010101010111100000;
if (VAR108 == 3'b111)
begin
state= VAR85;
VAR77= 255;
end
end
VAR117 = 'b0111001000101010111100000;
if (VAR108 == 3'b111)
begin
state= VAR85;
VAR77= 255;
end
VAR117[11]=VAR80;
end
endcase
if (VAR77)
begin
VAR77=VAR77 - 1;
end
end
end
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/or2b/sky130_fd_sc_ms__or2b.behavioral.v
| 1,442 |
module MODULE1 (
VAR7 ,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR1;
supply1 VAR2;
supply0 VAR12;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR8 ;
wire VAR3;
not VAR11 (VAR8 , VAR1 );
or VAR9 (VAR3, VAR8, VAR6 );
buf VAR10 (VAR7 , VAR3 );
endmodule
|
apache-2.0
|
aap/pdp6
|
verilog/dly_50.v
| 7,972 |
module MODULE12(input clk, input reset, input in, output VAR2);
reg [2-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 2'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 2;
endmodule
module MODULE26(input clk, input reset, input in, output VAR2);
reg [2-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 2'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 3;
endmodule
module MODULE4(input clk, input reset, input in, output VAR2);
reg [3-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 3'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 5;
endmodule
module MODULE7(input clk, input reset, input in, output VAR2);
reg [3-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 3'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 7;
endmodule
module MODULE25(input clk, input reset, input in, output VAR2);
reg [4-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 4'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 10;
endmodule
module MODULE28(input clk, input reset, input in, output VAR2);
reg [4-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 4'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 12;
endmodule
module MODULE3(input clk, input reset, input in, output VAR2);
reg [4-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 4'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 15;
endmodule
module MODULE2(input clk, input reset, input in, output VAR2);
reg [5-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 5'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 20;
endmodule
module MODULE20(input clk, input reset, input in, output VAR2);
reg [5-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 5'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 22;
endmodule
module MODULE23(input clk, input reset, input in, output VAR2);
reg [5-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 5'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 25;
endmodule
module MODULE9(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [5-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 5'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 25;
endmodule
module MODULE6(input clk, input reset, input in, output VAR2);
reg [5-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 5'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 27;
endmodule
module MODULE14(input clk, input reset, input in, output VAR2);
reg [6-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 6'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 37;
endmodule
module MODULE19(input clk, input reset, input in, output VAR2);
reg [6-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 6'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 40;
endmodule
module MODULE10(input clk, input reset, input in, output VAR2);
reg [6-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 6'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 50;
endmodule
module MODULE24(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [6-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 6'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 50;
endmodule
module MODULE13(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [7-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 7'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 75;
endmodule
module MODULE22(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [7-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 7'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 100;
endmodule
module MODULE17(input clk, input reset, input in, output VAR2);
reg [8-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 8'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 140;
endmodule
module MODULE21(input clk, input reset, input in, output VAR2);
reg [11-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 11'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 1750;
endmodule
module MODULE11(input clk, input reset, input in, output VAR2);
reg [13-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 13'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 5000;
endmodule
module MODULE27(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [13-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 13'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 5000;
endmodule
module MODULE1(input clk, input reset, input in, output VAR2);
reg [17-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 17'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 105000;
endmodule
module MODULE8(input clk, input reset, input in, output VAR2);
reg [17-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 17'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 125000;
endmodule
module MODULE15(input clk, input reset, input in, output VAR2);
reg [18-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 18'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 250000;
endmodule
module MODULE16(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [18-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 18'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 250000;
endmodule
module MODULE18(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [26-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 26'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 50000000;
endmodule
module MODULE5(input clk, input reset, input in, output VAR2, output reg VAR3);
reg [28-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR1 <= 0;
VAR3 <= 0;
end else begin
if(VAR1)
VAR1 <= VAR1 + 28'b1;
if(in) begin
VAR1 <= 1;
VAR3 <= 1;
end
if(VAR2) begin
VAR1 <= 0;
VAR3 <= 0;
end
end
end
assign VAR2 = VAR1 == 250000000;
endmodule
|
mit
|
lloves/Sora
|
FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_128.v
| 2,234 |
module MODULE1(
input clk,
input rst,
input VAR1,
input VAR2,
output reg [6:0] VAR3
);
wire [6:0] VAR4;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1)
VAR3 = 7'h00;
end
else begin
case({VAR1,VAR2})
2'b00: VAR3 = 7'h00;
2'b01: VAR3 = VAR4;
2'b10: VAR3 = VAR4 - 1;
2'b11: VAR3 = VAR4 + 1;
default: VAR3 = 7'h00;
endcase
end
end
assign VAR4 = VAR3;
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o21a/sky130_fd_sc_hd__o21a.pp.blackbox.v
| 1,351 |
module MODULE1 (
VAR6 ,
VAR1 ,
VAR2 ,
VAR4 ,
VAR7,
VAR3,
VAR8 ,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR8 ;
input VAR5 ;
endmodule
|
apache-2.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/sparc/exu/rtl/sparc_exu_eclccr.v
| 11,115 |
module MODULE1 (
VAR28, VAR69, VAR20, VAR54,
VAR105,
clk, VAR66, VAR47, VAR42, VAR77, VAR16, VAR53,
VAR65, VAR83, VAR57, VAR43, VAR48,
VAR55, VAR36, VAR31,
VAR71, VAR21, VAR13,
VAR73, VAR80, VAR26, VAR46
) ;
input clk;
input VAR66;
input [3:0] VAR47; input [3:0] VAR42;
input [1:0] VAR77; input [3:0] VAR16; input VAR53;
input VAR65;
input [1:0] VAR83;
input [3:0] VAR57; input VAR43;
input VAR48;
input [7:0] VAR55; input VAR36; input VAR31;
input [7:0] VAR71;
input [1:0] VAR21;
input VAR13;
input [7:0] VAR73;
input VAR80;
input VAR26;
input VAR46;
output [7:0] VAR28; output [7:0] VAR69;
output [7:0] VAR20;
output [7:0] VAR54;
output [7:0] VAR105;
wire [7:0] VAR99; wire [7:0] VAR35; wire [7:0] VAR15; wire [7:0] VAR49;
wire [7:0] VAR100; wire VAR56; wire VAR44;
wire VAR58;
wire VAR62; wire VAR70;
wire VAR6;
wire VAR39;
wire [7:0] VAR72;
wire [7:0] VAR19;
wire [7:0] VAR4;
wire [7:0] VAR78;
wire [7:0] VAR79;
wire [7:0] VAR104;
wire [7:0] VAR12;
wire [7:0] VAR63;
wire [7:0] VAR32;
wire VAR64;
wire VAR86;
wire VAR2;
wire VAR67;
wire VAR74;
wire [1:0] VAR89;
wire VAR65;
wire VAR97;
wire [1:0] VAR87;
wire VAR8;
wire VAR96;
wire VAR14;
wire VAR68;
wire VAR88; wire VAR59;
wire VAR84;
wire VAR23;
wire VAR17;
wire VAR25;
wire VAR29;
wire VAR27;
wire VAR1; wire VAR95;
wire VAR33;
wire VAR51;
wire VAR60;
wire [7:0] VAR7;
VAR40 VAR76(.din(VAR48), .clk(clk), .VAR75(VAR56),
.VAR66(VAR66), .VAR85(), .VAR93());
assign VAR35 = {VAR47, VAR42};
assign VAR62 = VAR56 & ~VAR43;
VAR40 #(8) VAR98(.din(VAR35[7:0]), .clk(clk), .VAR75(VAR15[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
VAR40 VAR34(.din(VAR62), .clk(clk), .VAR75(VAR44),
.VAR66(VAR66), .VAR85(), .VAR93());
assign VAR70 = VAR44 | VAR13;
VAR10 #(8) VAR102(.dout(VAR7[7:0]),
.VAR91(VAR15[7:0]),
.VAR61(VAR73[7:0]),
.VAR90(~VAR13),
.VAR9(VAR13));
VAR40 #(8) VAR92(.din(VAR7[7:0]), .clk(clk), .VAR75(VAR49[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
VAR40 VAR82(.din(VAR70), .clk(clk), .VAR75(VAR58),
.VAR66(VAR66), .VAR85(), .VAR93());
assign VAR60 = VAR80 & VAR58;
assign VAR6 = ~VAR26 & ~VAR46 & VAR80 & (VAR58 | VAR36);
assign VAR64 = ~(VAR36);
VAR10 #(8) VAR94(.dout(VAR100[7:0]), .VAR90(VAR36),
.VAR9(VAR64),
.VAR91(VAR55[7:0]),
.VAR61(VAR49[7:0]));
VAR40 #(3) VAR50 (.din({VAR31, VAR21[1:0]}), .clk(clk),
.VAR75({VAR39, VAR87[1:0]}),
.VAR66(VAR66), .VAR85(), .VAR93());
assign VAR8 = ~VAR87[1] & ~VAR87[0];
assign VAR88 = (VAR57[0] & VAR6 & ~VAR59);
assign VAR59 = VAR8 & VAR39;
assign VAR1 = ~(VAR88 | VAR59);
VAR37 #(8) VAR38(.dout(VAR72[7:0]), .VAR90(VAR88),
.VAR9(VAR59), .VAR52(VAR1),
.VAR91(VAR100[7:0]),
.VAR61(VAR71[7:0]), .VAR45(VAR104[7:0]));
VAR40 #(8) VAR106(.din(VAR72[7:0]), .clk(clk), .VAR75(VAR104[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
assign VAR79[7:0] = VAR104[7:0];
assign VAR8 = ~VAR87[1] & ~VAR87[0];
assign VAR96 = ~VAR87[1] & VAR87[0];
assign VAR14 = VAR87[1] & ~VAR87[0];
assign VAR68 = VAR87[1] & VAR87[0];
assign VAR88 = (VAR57[0] & VAR6 & ~VAR59);
assign VAR59 = VAR8 & VAR39;
assign VAR1 = ~(VAR88 | VAR59);
assign VAR84 = (VAR57[1] & VAR6 & ~VAR23);
assign VAR23 = (VAR96 & VAR39);
assign VAR95 = ~(VAR84 | VAR23);
assign VAR17 = (VAR57[2] & VAR6 & ~VAR25);
assign VAR25 = (VAR14 & VAR39);
assign VAR33 = ~(VAR17 | VAR25);
assign VAR29 = (VAR57[3] & VAR6 & ~VAR27);
assign VAR27 = (VAR68 & VAR39);
assign VAR51 = ~(VAR29 | VAR27);
VAR37 #(8) VAR38(.dout(VAR72[7:0]), .VAR90(VAR88),
.VAR9(VAR59), .VAR52(VAR1),
.VAR91(VAR100[7:0]),
.VAR61(VAR71[7:0]), .VAR45(VAR104[7:0]));
VAR37 #(8) VAR5(.dout(VAR19[7:0]), .VAR90(VAR84),
.VAR9(VAR23), .VAR52(VAR95),
.VAR91(VAR100[7:0]),
.VAR61(VAR71[7:0]), .VAR45(VAR12[7:0]));
VAR37 #(8) VAR41(.dout(VAR4[7:0]), .VAR90(VAR17),
.VAR9(VAR25), .VAR52(VAR33),
.VAR91(VAR100[7:0]),
.VAR61(VAR71[7:0]), .VAR45(VAR63[7:0]));
VAR37 #(8) VAR101(.dout(VAR78[7:0]), .VAR90(VAR29),
.VAR9(VAR27), .VAR52(VAR51),
.VAR91(VAR100[7:0]),
.VAR61(VAR71[7:0]), .VAR45(VAR32[7:0]));
VAR40 #(8) VAR106(.din(VAR72[7:0]), .clk(clk), .VAR75(VAR104[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
VAR40 #(8) VAR22(.din(VAR19[7:0]), .clk(clk), .VAR75(VAR12[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
VAR40 #(8) VAR24(.din(VAR4[7:0]), .clk(clk), .VAR75(VAR63[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
VAR40 #(8) VAR11(.din(VAR78[7:0]), .clk(clk), .VAR75(VAR32[7:0]),
.VAR66(VAR66), .VAR85(), .VAR93());
VAR103 #(8) VAR81(.dout(VAR79[7:0]), .VAR90(VAR16[0]),
.VAR9(VAR16[1]), .VAR52(VAR16[2]),
.VAR18(VAR16[3]), .VAR91(VAR104[7:0]),
.VAR61(VAR12[7:0]), .VAR45(VAR63[7:0]),
.VAR3(VAR32[7:0]));
assign VAR28[7:0] = (VAR2)? VAR35[7:0]: VAR99[7:0];
VAR37 #(8) VAR30(.dout(VAR99[7:0]),
.VAR90(VAR86),
.VAR9(VAR67),
.VAR52(VAR74),
.VAR91(VAR79[7:0]),
.VAR61(VAR15[7:0]),
.VAR45(VAR49[7:0]));
assign VAR2 = VAR62 & VAR65;
assign VAR67 = VAR44 & VAR53;
assign VAR74 = VAR60 & VAR97 & ~VAR67;
assign VAR86 = ~(VAR67 | VAR74);
assign VAR89 = VAR83 ^ VAR77;
assign VAR97 = ~(VAR89[1] | VAR89[0]);
assign VAR69[7:0] = VAR104[7:0];
assign VAR20[7:0] = VAR12[7:0];
assign VAR54[7:0] = VAR63[7:0];
assign VAR105[7:0] = VAR32[7:0];
endmodule
|
gpl-2.0
|
BilkentCompGen/GateKeeper
|
FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_qpll_reset.v
| 14,594 |
module MODULE1 #
(
parameter VAR6 = "VAR38", parameter VAR30 = "VAR22", parameter VAR2 = 1, parameter VAR27 = 1
)
(
input VAR26,
input VAR31,
input VAR37,
input [VAR2-1:0] VAR47,
input [(VAR2-1)>>2:0]VAR8,
input [(VAR2-1)>>2:0]VAR40,
input [ 1:0] VAR29,
input [VAR2-1:0] VAR21,
input [VAR2-1:0] VAR9,
output VAR28,
output VAR33,
output VAR35,
output VAR4,
output VAR46,
output [11:0] VAR10
);
reg VAR7;
reg [VAR2-1:0] VAR14;
reg [(VAR2-1)>>2:0]VAR44;
reg [(VAR2-1)>>2:0]VAR43;
reg [ 1:0] VAR17;
reg [VAR2-1:0] VAR3;
reg [VAR2-1:0] VAR16;
reg VAR39;
reg [VAR2-1:0] VAR41;
reg [(VAR2-1)>>2:0]VAR11;
reg [(VAR2-1)>>2:0]VAR1;
reg [ 1:0] VAR34;
reg [VAR2-1:0] VAR13;
reg [VAR2-1:0] VAR5;
reg VAR24 = 1'd0;
reg VAR20 = 1'd1;
reg VAR48 = 1'd0;
reg [11:0] fsm = 12'd2;
localparam VAR49 = 12'b000000000001;
localparam VAR12 = 12'b000000000010;
localparam VAR18 = 12'b000000000100;
localparam VAR32 = 12'b000000001000;
localparam VAR52 = 12'b000000010000;
localparam VAR42 = 12'b000000100000;
localparam VAR50 = 12'b000001000000;
localparam VAR51 = 12'b000010000000;
localparam VAR36 = 12'b000100000000;
localparam VAR45 = 12'b001000000000;
localparam VAR25 = 12'b010000000000;
localparam VAR23 = 12'b100000000000;
always @ (posedge VAR26)
begin
if (!VAR31)
begin
VAR7 <= 1'd0;
VAR14 <= {VAR2{1'd1}};
VAR44 <= {(((VAR2-1)>>2)+1){1'd0}};
VAR43 <= {(((VAR2-1)>>2)+1){1'd0}};
VAR17 <= 2'd0;
VAR3 <= {VAR2{1'd1}};
VAR16 <= {VAR2{1'd0}};
VAR39 <= 1'd0;
VAR41 <= {VAR2{1'd1}};
VAR11 <= {(((VAR2-1)>>2)+1){1'd0}};
VAR1 <= {(((VAR2-1)>>2)+1){1'd0}};
VAR34 <= 2'd0;
VAR13 <= {VAR2{1'd1}};
VAR5 <= {VAR2{1'd0}};
end
else
begin
VAR7 <= VAR37;
VAR14 <= VAR47;
VAR44 <= VAR8;
VAR43 <= VAR40;
VAR17 <= VAR29;
VAR3 <= VAR21;
VAR16 <= VAR9;
VAR39 <= VAR7;
VAR41 <= VAR14;
VAR11 <= VAR44;
VAR1 <= VAR43;
VAR34 <= VAR17;
VAR13 <= VAR3;
VAR5 <= VAR16;
end
end
always @ (posedge VAR26)
begin
if (!VAR31)
begin
fsm <= VAR12;
VAR24 <= 1'd0;
VAR20 <= 1'd1;
VAR48 <= 1'd0;
end
else
begin
case (fsm)
VAR49 :
begin
if (!VAR31)
begin
fsm <= VAR12;
VAR24 <= 1'd0;
VAR20 <= 1'd1;
VAR48 <= 1'd0;
end
else
begin
fsm <= VAR49;
VAR24 <= VAR24;
VAR20 <= &VAR13;
VAR48 <= &VAR5;
end
end
VAR12 :
begin
fsm <= ((&(~VAR41)) && (&(~VAR1)) ? VAR18 : VAR12);
VAR24 <= VAR24;
VAR20 <= VAR20;
VAR48 <= VAR48;
end
VAR18 :
begin
fsm <= ((VAR39 && (&VAR41)) ? VAR32 : VAR18);
VAR24 <= VAR24;
VAR20 <= VAR20;
VAR48 <= VAR48;
end
VAR32:
begin
fsm <= (&(~VAR11) ? VAR52 : VAR32);
VAR24 <= VAR24;
VAR20 <= VAR20;
VAR48 <= VAR48;
end
VAR52 :
begin
fsm <= (&VAR11 ? VAR42 : VAR52);
VAR24 <= VAR24;
VAR20 <= VAR20;
VAR48 <= VAR48;
end
VAR42 :
begin
fsm <= (&VAR1 ? ((VAR27 == 1) ? VAR25 : VAR50) : VAR42);
VAR24 <= VAR24;
VAR20 <= 1'd0;
VAR48 <= VAR48;
end
VAR50:
begin
fsm <= (&(~VAR11) ? VAR51 : VAR50);
VAR24 <= 1'd1;
VAR20 <= VAR20;
VAR48 <= VAR48;
end
VAR51 :
begin
if (&VAR11)
begin
fsm <= ((VAR6 == "VAR15") ? VAR36 : VAR25);
VAR24 <= VAR24;
VAR20 <= (VAR6 == "VAR15");
VAR48 <= VAR48;
end
else
begin
fsm <= VAR51;
VAR24 <= VAR24;
VAR20 <= VAR20;
VAR48 <= VAR48;
end
end
VAR36 :
begin
fsm <= (&(~VAR1) ? VAR45 : VAR36);
VAR24 <= VAR24;
VAR20 <= 1'd1;
VAR48 <= 1'd0;
end
VAR45 :
begin
fsm <= (&VAR1 ? VAR49 : VAR45);
VAR24 <= VAR24;
VAR20 <= 1'd0;
VAR48 <= 1'd0;
end
VAR25 :
begin
fsm <= VAR23;
VAR24 <= VAR24;
VAR20 <= (VAR6 == "VAR38") ? (VAR34 != 2'd2) : 1'd0;
VAR48 <= VAR48;
end
VAR23 :
begin
fsm <= VAR49;
VAR24 <= VAR24;
VAR20 <= VAR20;
VAR48 <= (VAR6 == "VAR38") ? (VAR34 != 2'd2) : 1'd0;
end
default :
begin
fsm <= VAR12;
VAR24 <= 1'd0;
VAR20 <= 1'd0;
VAR48 <= 1'd0;
end
endcase
end
end
assign VAR28 = VAR24;
assign VAR33 = (fsm == VAR32) || (fsm == VAR50);
assign VAR35 = VAR20;
assign VAR4 = ((VAR30 == "VAR19") ? 1'd0 : VAR48);
assign VAR46 = (fsm == VAR49);
assign VAR10 = fsm;
endmodule
|
gpl-3.0
|
tuura/fantasi
|
dependencies/Altera_DE4/niosII/synthesis/submodules/system1_mm_interconnect_0_avalon_st_adapter.v
| 6,174 |
module MODULE1 #(
parameter VAR4 = 34,
parameter VAR20 = 0,
parameter VAR23 = 34,
parameter VAR17 = 0,
parameter VAR2 = 0,
parameter VAR13 = 0,
parameter VAR6 = 1,
parameter VAR19 = 1,
parameter VAR16 = 0,
parameter VAR15 = 34,
parameter VAR21 = 0,
parameter VAR11 = 1,
parameter VAR7 = 0,
parameter VAR25 = 1,
parameter VAR9 = 1,
parameter VAR3 = 0
) (
input wire VAR10, input wire VAR5, input wire [33:0] VAR24, input wire VAR12, output wire VAR14, output wire [33:0] VAR22, output wire VAR1, input wire VAR8, output wire [0:0] VAR18 );
generate
if (VAR4 != 34)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/conb/sky130_fd_sc_hs__conb.behavioral.pp.v
| 1,580 |
module MODULE1 (
VAR5,
VAR8,
VAR7 ,
VAR6
);
input VAR5;
input VAR8;
output VAR7 ;
output VAR6 ;
wire VAR9;
pullup VAR3 (VAR9);
VAR2 VAR4 (VAR7 , VAR9, VAR5, VAR8);
pulldown VAR1 (VAR6 );
endmodule
|
apache-2.0
|
cafe-alpha/wascafe
|
v11/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_wrapper.v
| 9,436 |
module MODULE1 (
VAR31,
VAR53,
clk,
VAR40,
VAR38,
VAR42,
VAR3,
VAR32,
VAR9,
VAR21,
VAR24,
VAR16,
VAR43,
VAR37,
VAR25,
VAR51,
VAR34,
VAR17,
VAR56,
VAR14,
VAR4,
VAR2,
VAR29,
VAR1,
VAR12,
VAR36,
VAR45,
VAR49,
VAR33,
VAR22,
VAR55,
VAR47,
VAR50
)
;
output [ 37: 0] VAR4;
output VAR2;
output VAR29;
output VAR1;
output VAR12;
output VAR36;
output VAR45;
output VAR49;
output VAR33;
output VAR22;
output VAR55;
output VAR47;
output VAR50;
input [ 31: 0] VAR31;
input [ 31: 0] VAR53;
input clk;
input VAR40;
input VAR38;
input VAR42;
input VAR3;
input VAR32;
input VAR9;
input VAR21;
input VAR24;
input VAR16;
input VAR43;
input [ 35: 0] VAR37;
input VAR25;
input [ 6: 0] VAR51;
input VAR34;
input VAR17;
input VAR56;
input VAR14;
wire [ 37: 0] VAR4;
wire VAR2;
wire [ 37: 0] VAR7;
wire VAR29;
wire VAR1;
wire VAR12;
wire VAR36;
wire VAR45;
wire VAR49;
wire VAR33;
wire VAR22;
wire VAR55;
wire VAR47;
wire VAR50;
wire VAR13;
wire [ 1: 0] VAR18;
wire [ 1: 0] VAR48;
wire VAR20;
wire VAR27;
wire VAR11;
wire VAR57;
wire VAR46;
wire VAR23;
wire VAR44;
VAR10 VAR26
(
.VAR31 (VAR31),
.VAR53 (VAR53),
.VAR40 (VAR40),
.VAR38 (VAR38),
.VAR42 (VAR42),
.VAR3 (VAR3),
.VAR32 (VAR32),
.VAR52 (VAR18),
.VAR39 (VAR48),
.VAR2 (VAR2),
.VAR41 (VAR20),
.VAR9 (VAR9),
.VAR21 (VAR21),
.VAR24 (VAR24),
.VAR16 (VAR16),
.VAR7 (VAR7),
.VAR29 (VAR29),
.VAR5 (VAR11),
.VAR15 (VAR57),
.VAR30 (VAR46),
.VAR43 (VAR43),
.VAR37 (VAR37),
.VAR25 (VAR25),
.VAR51 (VAR51),
.VAR34 (VAR34),
.VAR17 (VAR17),
.VAR56 (VAR56),
.VAR14 (VAR14),
.VAR35 (VAR13),
.VAR8 (VAR27),
.VAR19 (VAR44)
);
VAR28 VAR54
(
.clk (clk),
.VAR52 (VAR18),
.VAR4 (VAR4),
.VAR7 (VAR7),
.VAR1 (VAR1),
.VAR12 (VAR12),
.VAR36 (VAR36),
.VAR45 (VAR45),
.VAR49 (VAR49),
.VAR33 (VAR33),
.VAR22 (VAR22),
.VAR55 (VAR55),
.VAR47 (VAR47),
.VAR50 (VAR50),
.VAR6 (VAR23),
.VAR19 (VAR44)
);
assign VAR11 = 1'b0;
assign VAR57 = 1'b0;
assign VAR27 = 1'b0;
assign VAR13 = 1'b0;
assign VAR20 = 1'b0;
assign VAR44 = 1'b0;
assign VAR23 = 1'b0;
assign VAR18 = 2'b0;
endmodule
|
gpl-2.0
|
fallen/milkymist-mmu
|
cores/dmx/rtl/dmx_rx.v
| 5,307 |
module MODULE1 #(
parameter VAR16 = 4'h0,
parameter VAR46 = 100000000
) (
input VAR49,
input VAR4,
input [13:0] VAR13,
input VAR6,
input [31:0] VAR51,
output [31:0] VAR8,
input VAR53
);
wire VAR28 = VAR13[13:10] == VAR16;
wire [7:0] VAR15;
reg [8:0] VAR18;
reg VAR11;
reg [7:0] VAR1;
VAR26 VAR37(
.clk(VAR49),
.VAR42(VAR13[8:0]),
.VAR21(1'b0),
.VAR19(8'VAR29),
.do(VAR15),
.VAR56(VAR18),
.VAR14(VAR11),
.VAR52(VAR1),
.VAR12()
);
always @(posedge VAR49) begin
if(VAR11)
end
reg VAR23;
always @(posedge VAR49)
VAR23 <= VAR28;
assign VAR8 = {24'h000000, VAR23 ? VAR15 : 8'h00};
reg VAR5;
reg VAR3;
always @(posedge VAR49) begin
VAR5 <= VAR53;
VAR3 <= VAR5;
end
parameter VAR10 = VAR46/250000;
parameter VAR7 = VAR46/500000;
reg VAR30;
reg VAR33;
reg [8:0] VAR50;
always @(posedge VAR49) begin
if(VAR30) begin
VAR33 <= 1'b0;
VAR50 <= VAR7-1;
end else begin
if(VAR50 == 9'd0) begin
VAR33 <= 1'b1;
VAR50 <= VAR10-1;
end else begin
VAR33 <= 1'b0;
VAR50 <= VAR50 - 9'd1;
end
end
end
reg VAR54;
reg VAR48;
always @(posedge VAR49) begin
if(VAR54)
VAR18 <= 9'd0;
end
else if(VAR48)
VAR18 <= VAR18 + 9'd1;
end
reg VAR17;
reg [2:0] VAR39;
always @(posedge VAR49) begin
if(VAR17)
VAR1[VAR39] <= VAR3;
end
parameter VAR20 = VAR46/11364;
reg [12:0] VAR35;
wire break = VAR35 == 13'd0;
always @(posedge VAR49) begin
if(VAR4|VAR3)
VAR35 <= VAR20;
end
else if(~break)
VAR35 <= VAR35 - 13'd1;
end
reg [3:0] state;
reg [3:0] VAR38;
parameter VAR45 = 4'd0;
parameter VAR43 = 4'd1;
parameter VAR22 = 4'd2;
parameter VAR40 = 4'd3;
parameter VAR24 = 4'd4;
parameter VAR36 = 4'd5;
parameter VAR31 = 4'd6;
parameter VAR47 = 4'd7;
parameter VAR44 = 4'd8;
parameter VAR55 = 4'd9;
parameter VAR9 = 4'd10;
parameter VAR34 = 4'd11;
parameter VAR41 = 4'd12;
parameter VAR27 = 4'd13;
always @(posedge VAR49) begin
if(VAR4)
state <= VAR45;
end
else
state <= VAR38;
end
reg VAR2;
reg VAR32;
always @(posedge VAR49)
VAR2 <= VAR32;
always @(*) begin
VAR30 = 1'b0;
VAR54 = 1'b0;
VAR48 = 1'b0;
VAR11 = 1'b0;
VAR17 = 1'b0;
VAR39 = 3'VAR25;
VAR38 = state;
VAR32 = VAR2;
case(state)
VAR45: begin
VAR30 = 1'b1;
VAR54 = 1'b1;
VAR32 = 1'b1;
if(break)
VAR38 = VAR43;
end
VAR43: begin
VAR30 = 1'b1;
VAR54 = 1'b1;
if(VAR3)
VAR38 = VAR22;
end
VAR22: begin
VAR30 = 1'b1;
if(~VAR3)
VAR38 = VAR40;
end
VAR40: begin
if(VAR33) begin
if(VAR3)
VAR38 = VAR45;
end
else
VAR38 = VAR24;
end
end
VAR24: begin
VAR17 = 1'b1;
VAR39 = 3'd0;
if(VAR33)
VAR38 = VAR36;
end
VAR36: begin
VAR17 = 1'b1;
VAR39 = 3'd1;
if(VAR33)
VAR38 = VAR31;
end
VAR31: begin
VAR17 = 1'b1;
VAR39 = 3'd2;
if(VAR33)
VAR38 = VAR47;
end
VAR47: begin
VAR17 = 1'b1;
VAR39 = 3'd3;
if(VAR33)
VAR38 = VAR44;
end
VAR44: begin
VAR17 = 1'b1;
VAR39 = 3'd4;
if(VAR33)
VAR38 = VAR55;
end
VAR55: begin
VAR17 = 1'b1;
VAR39 = 3'd5;
if(VAR33)
VAR38 = VAR9;
end
VAR9: begin
VAR17 = 1'b1;
VAR39 = 3'd6;
if(VAR33)
VAR38 = VAR34;
end
VAR34: begin
VAR17 = 1'b1;
VAR39 = 3'd7;
if(VAR33)
VAR38 = VAR41;
end
VAR41: begin
if(VAR33) begin
if(VAR3)
VAR38 = VAR27;
end
else
VAR38 = VAR45;
end
end
VAR27: begin
if(VAR33) begin
if(VAR3) begin
VAR32 = 1'b0;
if(~VAR2) begin
VAR11 = 1'b1;
VAR48 = 1'b1;
end
VAR38 = VAR22;
end else
VAR38 = VAR45;
end
end
endcase
end
endmodule
|
lgpl-3.0
|
onchipuis/mriscv_vivado
|
mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v
| 10,963 |
module MODULE1 #
(parameter VAR48 = 10,
parameter VAR45 = "VAR9",
parameter VAR56 = 100,
parameter VAR32 = 8,
parameter VAR17 = 2,
parameter VAR11 = 7,
parameter VAR12 = 112)
(
VAR59, VAR24, VAR19, VAR53, VAR8, VAR28,
VAR49, VAR27, VAR37, VAR14, VAR30, VAR41, VAR26,
VAR18, clk, VAR43, VAR29, VAR7, rst,
VAR6
);
function integer VAR2 (input integer VAR35); begin
VAR35 = VAR35 - 1;
for (VAR2=1; VAR35>1; VAR2=VAR2+1)
VAR35 = VAR35 >> 1;
end
endfunction
input VAR18;
input clk;
input [VAR32:0] VAR43, VAR29;
input VAR7;
input rst;
localparam VAR22 = 1;
localparam VAR46 = VAR2(VAR48);
reg [VAR46-1:0] VAR58, VAR52;
reg VAR39;
wire VAR10 = VAR45 == "VAR51" ? VAR39 : VAR18;
output VAR59;
assign VAR59 = 1'b1;
output VAR24;
reg VAR31;
assign VAR24 = VAR31;
reg [VAR11-1:0] VAR42;
reg [VAR11-1:0] VAR36;
output [VAR11-1:0] VAR19;
assign VAR19 = VAR42;
output VAR53;
reg VAR47;
assign VAR53 = VAR47;
output VAR8;
reg VAR23, VAR33;
always @ begin
VAR54 = VAR1;
VAR13 = VAR21;
VAR54 = VAR50 >= VAR29;
VAR13 = VAR5 >= VAR29;
end wire VAR25 = VAR57 ^ VAR16;
input VAR6;
always @(*) begin
if (rst == 1'b1) begin
VAR31 = 1'b0;
VAR44 = 2'd0;
VAR57 = 1'b0;
VAR36 = {VAR11{1'b0}};
VAR47 = 1'b0;
VAR15 = {VAR32{1'b0}};
VAR20 = {VAR32+1{1'b0}};
VAR34 = {VAR11{1'b0}};
VAR58 = VAR48[VAR46-1:0];
VAR38 = {VAR32+1{1'b0}};
end else begin
VAR31 = 1'b0;
VAR44 = VAR4;
VAR57 = VAR16;
VAR36 = VAR42;
VAR47 = 1'b0;
VAR15 = VAR40;
VAR20 = VAR5;
VAR34 = VAR55;
VAR58 = VAR52;
if (|VAR52) VAR58 = VAR52 - VAR22[VAR46-1:0];
VAR38 = VAR3;
case (VAR4)
2'd0: begin
if (~|VAR52 && VAR6 | VAR45 == "VAR51") begin
if (VAR45 == "VAR51") VAR58 = VAR22[VAR46-1:0];
if ({1'b0, VAR40} == VAR43) VAR44 = 2'd1;
VAR20 = VAR5 + {{VAR32{1'b0}}, VAR10};
VAR15 = VAR40 + VAR22[VAR32-1:0];
end
end
2'd1:begin
VAR44 = 2'd2;
end
2'd2:begin
VAR44 = 2'd3;
VAR31 = 1'b1;
VAR15 = {VAR32{1'b0}};
VAR20 = {VAR32+1{1'b0}};
VAR38 = VAR5;
VAR34 = (VAR55 < VAR12[VAR11-1:0] - VAR22[VAR11-1:0])
? VAR55 + VAR22[VAR11-1:0]
: {VAR11{1'b0}};
if (VAR16) begin
if (VAR1) VAR57 = 1'b0;
end else begin
if (VAR21) VAR57 = 1'b1;
end
if (VAR25) begin
VAR36 ={VAR11{1'b0}};
VAR47 = 1'b1;
end else VAR36 = VAR42 + VAR22[VAR11-1:0];
end
2'd3:begin
VAR58 = VAR48[VAR46-1:0] - VAR22[VAR46-1:0];
if (VAR7) VAR44 = 2'd0;
end
endcase end end
endmodule
|
mit
|
hightoon/Sora
|
FPGA/SISO/ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_14/source/endpoint_blk_plus_v1_14.v
| 19,616 |
module MODULE1 # (
parameter VAR114 = "VAR3",
parameter VAR192 = 0,
parameter VAR174 = 4,
parameter VAR12 = 1,
parameter VAR33 = 0,
parameter VAR169 = 64,
parameter VAR153 = 8,
parameter VAR130 = 4,
parameter VAR154 = 7,
parameter VAR74 = 8,
parameter VAR151 = 12,
parameter VAR9 = 32,
parameter VAR185 = 10,
parameter VAR55 = 48,
parameter VAR41 = 8,
parameter VAR28 = 5,
parameter VAR18 = 3,
parameter VAR148 = 16,
parameter VAR155 = 1024,
parameter VAR190 = 32'h000010EE,
parameter VAR177 = VAR190[15 : 0],
parameter VAR179 = 16'h4250,
parameter VAR135 = 8'h02,
parameter VAR42 = 24'h0B4000,
parameter VAR6 = 32'hFFFFC000,
parameter VAR31 = 32'h00000000,
parameter VAR89 = 32'h00000000,
parameter VAR171 = 32'h00000000,
parameter VAR137 = 32'h00000000,
parameter VAR139 = 32'h00000000,
parameter VAR71 = 32'h00000000,
parameter VAR65 = 32'h000010EE,
parameter VAR104 = 32'h00004250,
parameter VAR134 = VAR65[15 : 0],
parameter VAR178 = VAR104[15 : 0],
parameter VAR73 = 32'hFFF00001,
parameter VAR67 = 5'b00000,
parameter VAR113 = 0,
parameter VAR37 = 4'b0000,
parameter VAR72 = 4'h1,
parameter VAR75 = 2'b00,
parameter VAR23 = 8'h00,
parameter VAR195 = 0,
parameter VAR15 = 0,
parameter VAR186 = 0,
parameter VAR40 = 3'b111,
parameter VAR193 = 3'b111,
parameter VAR25 = 1,
parameter VAR78 = 2'b01,
parameter VAR182 = 3'b010,
parameter VAR1 = 3'b111,
parameter VAR170 = 3'b111,
parameter VAR132 = 2'b01,
parameter VAR128 = 6'b100,
parameter VAR2 = 4'b1,
parameter VAR61 = 16'h0204,
parameter VAR96 = 16'h060d,
parameter VAR200 = 4'b0000,
parameter VAR205 = 0,
parameter VAR194 = 0,
parameter VAR91 = 0,
parameter VAR180 = 0,
parameter VAR99 = 0,
parameter VAR95 = 5'h0,
parameter VAR70 = 0,
parameter VAR122 = 0,
parameter VAR32 = 3'b000,
parameter VAR133 = 0,
parameter VAR48 = 0,
parameter VAR187 = 3'b010,
parameter VAR53 = 8'h0,
parameter VAR108 = 8'h0,
parameter VAR60 = 8'h0,
parameter VAR158 = 8'h0,
parameter VAR191 = 8'h0,
parameter VAR85 = 8'h0,
parameter VAR159 = 8'h0,
parameter VAR143 = 8'h0,
parameter VAR24 = 8'h0,
parameter VAR147 = 8'h0,
parameter VAR112 = 8'h0,
parameter VAR66 = 8'h0,
parameter VAR97 = 8'h0,
parameter VAR49 = 8'h0,
parameter VAR156 = 8'h0,
parameter VAR109 = 8'h0,
parameter VAR202 = 0,
parameter VAR90 = 0,
parameter VAR39 = "VAR26",
parameter VAR144 = 1,
parameter VAR116 = 1,
parameter VAR196 = 1,
parameter VAR161 = "VAR26",
parameter VAR58 = "VAR26",
parameter VAR84 = 3'b100,
parameter VAR181 = 3'b100,
parameter VAR79 = 3'b111,
parameter VAR166 = 0,
parameter VAR131 = 0
)
(
output [VAR174-1 : 0] VAR127,
output [VAR174-1 : 0] VAR8,
input [VAR174-1 : 0] VAR106,
input [VAR174-1 : 0] VAR204,
output VAR172,
output VAR201,
output VAR136,
input [VAR169-1 : 0] VAR102,
input [VAR153-1 : 0] VAR16,
input VAR5,
input VAR69,
input VAR157,
output VAR29,
output VAR11,
input VAR168,
input VAR38,
output [VAR130-1:0] VAR21,
output [VAR169-1 : 0] VAR124,
output [VAR153-1 : 0] VAR125,
output VAR45,
output VAR57,
output VAR100,
output VAR86,
input VAR92,
output VAR162,
input VAR93,
output [VAR154-1 : 0] VAR165,
output [VAR74-1 : 0] VAR87,
output [VAR151-1 : 0] VAR62,
output [VAR74-1 : 0] VAR110,
output [VAR151-1 : 0] VAR150,
input VAR82,
output [VAR9-1 : 0] VAR68,
output VAR183,
input [VAR9-1 : 0] VAR36,
input [VAR9/8-1 : 0] VAR126,
input [VAR185-1 : 0] VAR20,
input VAR163,
input VAR149,
input VAR59,
input VAR173,
input VAR138,
input VAR54,
input VAR101,
input VAR140,
input VAR14,
input [VAR55-1 : 0] VAR164,
output VAR34,
input VAR199,
input VAR7,
output VAR142,
input VAR105,
input [7 : 0] VAR4,
output [7 : 0] VAR63,
output [2 : 0] VAR88,
output VAR203,
output VAR47,
input VAR76,
output [2 : 0] VAR111,
input VAR121,
output [VAR41-1 : 0] VAR80,
output [VAR28-1 : 0] VAR77,
output [VAR18-1 : 0] VAR43,
input [63 : 0] VAR94,
output [VAR148-1 : 0] VAR123,
output [VAR148-1 : 0] VAR118,
output [VAR148-1 : 0] VAR184,
output [VAR148-1 : 0] VAR115,
output [VAR148-1 : 0] VAR44,
output [VAR148-1 : 0] VAR19,
input VAR145,
input VAR64,
output VAR98,
input VAR83
);
wire [4*16-1 : 0] VAR189;
wire [4-1 : 0] VAR51;
VAR10 #(
.VAR192 ( VAR192),
.VAR160 ( VAR12),
.VAR120 ( VAR33),
.VAR177 ( VAR177),
.VAR179 ( VAR179),
.VAR135 ( VAR135),
.VAR42 ( VAR42),
.VAR6 ( VAR6),
.VAR31 ( VAR31),
.VAR89 ( VAR89),
.VAR171 ( VAR171),
.VAR137 ( VAR137),
.VAR139 ( VAR139),
.VAR71 ( VAR71),
.VAR134 ( VAR134),
.VAR178 ( VAR178),
.VAR73 ( VAR73),
.VAR67 ( VAR67),
.VAR113 ( VAR113),
.VAR37 ( VAR37),
.VAR72 ( VAR72),
.VAR75 ( VAR75),
.VAR23 ( VAR23),
.VAR195 ( VAR195),
.VAR15 ( VAR15),
.VAR186 ( VAR186),
.VAR40 ( VAR40),
.VAR193 ( VAR193),
.VAR25 ( VAR25),
.VAR78 ( VAR78),
.VAR182 ( VAR182),
.VAR1 ( VAR1),
.VAR170 ( VAR170),
.VAR132 ( VAR132),
.VAR128 ( VAR128),
.VAR2 ( VAR2),
.VAR91 ( VAR91),
.VAR180 ( VAR180),
.VAR39 ( VAR39),
.VAR144 ( VAR144),
.VAR116 ( VAR116),
.VAR196 ( VAR196),
.VAR81 ( VAR161),
.VAR95 ( VAR95),
.VAR70 ( VAR70),
.VAR122 ( VAR122),
.VAR32 ( VAR32),
.VAR133 ( VAR133),
.VAR48 ( VAR48),
.VAR187 ( VAR187),
.VAR35 ( VAR200[2:0]),
.VAR52 ( VAR200[3]),
.VAR53 ( VAR53),
.VAR108 ( VAR108),
.VAR60 ( VAR60),
.VAR158 ( VAR158),
.VAR191 ( VAR191),
.VAR85 ( VAR85),
.VAR159 ( VAR159),
.VAR143 ( VAR143),
.VAR24 ( VAR24),
.VAR147 ( VAR147),
.VAR112 ( VAR112),
.VAR66 ( VAR66),
.VAR97 ( VAR97),
.VAR49 ( VAR49),
.VAR156 ( VAR156),
.VAR109 ( VAR109),
.VAR58 ( VAR58),
.VAR131 ( VAR131)
)
VAR146 (
.VAR127 ( VAR127),
.VAR8 ( VAR8),
.VAR106 ( VAR106),
.VAR204 ( VAR204),
.VAR30(VAR30),
.VAR27(VAR27),
.VAR176(VAR176),
.VAR107(VAR107),
.VAR17(VAR17),
.VAR129(VAR129),
.VAR56(VAR56),
.VAR117 ( VAR84),
.VAR198 ( VAR84),
.VAR197 ( VAR181),
.VAR103 ( VAR181),
.VAR141 ( VAR79),
.VAR175 ( VAR79),
.VAR13 ( 1'b0),
.VAR188 ( 0),
.VAR46 ( 0),
.VAR167 ( 0),
.VAR22 ( 0),
.VAR50 ( VAR189),
.VAR119 ( VAR51),
.VAR172 ( VAR172),
.VAR201 ( VAR201),
.VAR136 ( VAR136),
.VAR102 ( VAR102),
.VAR16 ( VAR16),
.VAR5 ( VAR5),
.VAR69 ( VAR69),
.VAR157 ( VAR157),
.VAR29 ( VAR29),
.VAR11 ( VAR11),
.VAR168 ( VAR168),
.VAR38 ( VAR38),
.VAR21 ( VAR21),
.VAR124 ( VAR124),
.VAR125 ( VAR125),
.VAR45 ( VAR45),
.VAR57 ( VAR57),
.VAR100 ( VAR100),
.VAR86 ( VAR86),
.VAR92 ( VAR92),
.VAR162 ( VAR162),
.VAR93 ( VAR93),
.VAR165 ( VAR165),
.VAR87 ( VAR87),
.VAR62 ( VAR62),
.VAR110 ( VAR110),
.VAR150 ( VAR150),
.VAR82 ( VAR82),
.VAR68 ( VAR68),
.VAR183 ( VAR183),
.VAR36 ( VAR36),
.VAR126 ( VAR126),
.VAR20 ( VAR20),
.VAR163 ( VAR163),
.VAR149 ( VAR149),
.VAR59 ( VAR59),
.VAR173 ( VAR173),
.VAR138 ( VAR138),
.VAR54 ( VAR54),
.VAR101 ( VAR101),
.VAR140 ( VAR140),
.VAR14 ( VAR14),
.VAR199 ( VAR199),
.VAR164 ( VAR164),
.VAR34 ( VAR34),
.VAR7 ( VAR7),
.VAR142 ( VAR142),
.VAR105 ( VAR105),
.VAR4 ( VAR4),
.VAR63 ( VAR63),
.VAR88 ( VAR88),
.VAR203 ( VAR203),
.VAR152 ( 1'b1),
.VAR47 ( VAR47),
.VAR76 ( VAR76),
.VAR111 ( VAR111),
.VAR121 ( VAR121),
.VAR80 ( VAR80),
.VAR77 ( VAR77),
.VAR43 ( VAR43),
.VAR94 ( VAR94),
.VAR123 ( VAR123),
.VAR118 ( VAR118),
.VAR184 ( VAR184),
.VAR115 ( VAR115),
.VAR44 ( VAR44),
.VAR19 ( VAR19),
.VAR64 ( VAR64),
.VAR98 ( VAR98),
.VAR83 ( VAR83),
.VAR145 ( VAR145)
);
endmodule
|
bsd-2-clause
|
ankitshah009/High-Radix-Adaptive-CORDIC
|
HCORDIC_Verilog/AddState.v
| 2,418 |
module MODULE1(
input [1:0] VAR9,
input [35:0] VAR15,
input [35:0] VAR12,
input [31:0] VAR8,
input [1:0] VAR27,
input VAR5,
input VAR3,
input [7:0] VAR11,
input VAR20,
output reg [1:0] VAR14,
output reg [31:0] VAR16,
output reg [1:0] VAR22,
output reg VAR24,
output reg VAR2,
output reg [27:0] VAR18,
output reg [7:0] VAR4
);
parameter VAR26 =2'b01,
VAR10 =2'b00,
VAR7=2'b11;
parameter VAR21 = 2'b00,
VAR28 = 2'b01,
VAR13 = 2'b10;
wire VAR23;
wire [7:0] VAR25;
wire [26:0] VAR17;
wire VAR6;
wire [7:0] VAR1;
wire [26:0] VAR19;
assign VAR23 = VAR12[35];
assign VAR25 = VAR12[34:27] - 127;
assign VAR17 = {VAR12[26:0]};
assign VAR6 = VAR15[35];
assign VAR1 = VAR15[34:27] - 127;
assign VAR19 = {VAR15[26:0]};
always @ (posedge VAR20)
begin
VAR4 <= VAR11;
VAR14 <= VAR9;
VAR22 <= VAR27;
VAR24 <= VAR5;
VAR2 <= VAR3;
if (VAR9 != VAR13) begin
VAR16[30:23] <= VAR1;
VAR16[22:0] <= 0;
if (VAR6 == VAR23) begin
VAR18 <= VAR19 + VAR17;
VAR16[31] <= VAR6;
end else begin
if (VAR19 >= VAR17) begin
VAR18 <= VAR19 - VAR17;
VAR16[31] <= VAR6;
end else begin
VAR18 <= VAR17 - VAR19;
VAR16[31] <= VAR23;
end
end
end
else begin
VAR16 <= VAR8;
VAR18 <= 0;
end
end
endmodule
|
apache-2.0
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/iface/ip/Write_Master/ST_to_MM_Adapter.v
| 5,150 |
module MODULE1 (
clk,
reset,
enable,
address,
VAR10,
VAR11,
VAR12,
VAR20,
VAR17,
VAR9,
VAR8
);
parameter VAR16 = 32;
parameter VAR21 = 2;
parameter VAR4 = 32;
parameter VAR18 = 0; localparam VAR22 = VAR21 + 1;
input clk;
input reset;
input enable; input [VAR4-1:0] address;
input VAR10; input VAR11;
input VAR12;
output wire [VAR16-1:0] VAR20;
input [VAR16-1:0] VAR17;
input VAR9;
output wire VAR8;
wire [VAR22-1:0] VAR3;
wire [VAR16-1:0] VAR13;
wire [VAR16-1:0] VAR19;
reg [VAR16-1:0] VAR14;
wire [VAR16-1:0] VAR2; wire [VAR22-2:0] VAR5; reg [VAR22-2:0] VAR15;
wire [VAR16-1:0] VAR1 [0:((VAR16/8)-1)]; wire [VAR16-1:0] VAR23 [0:((VAR16/8)-1)];
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR15 <= 0;
end
else if (VAR10)
begin
VAR15 <= VAR5;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR14 <= 0;
end
else
begin
if (VAR10 == 1)
begin
VAR14 <= 0;
end
else if (VAR8 == 1)
begin
VAR14 <= VAR19;
end
end
end
assign VAR3 = (VAR16/8) - address[VAR21-1:0]; assign VAR5 = VAR3 - 1;
assign VAR2 = VAR13 | VAR14;
generate
genvar VAR6;
for(VAR6 = 0; VAR6 < (VAR16/8); VAR6 = VAR6 + 1)
begin: VAR7
assign VAR1[VAR6] = VAR17 << (8 * ((VAR16/8)-(VAR6+1)));
assign VAR23[VAR6] = VAR17 >> (8 * (VAR6 + 1));
end
endgenerate
assign VAR13 = VAR1[VAR15];
assign VAR19 = VAR23[VAR15];
generate
if (VAR18 == 1)
begin
assign VAR8 = (VAR9 == 0) & (VAR12 == 0) & (VAR11 == 0) & (enable == 1) & (VAR10 == 0);
assign VAR20 = VAR2;
end
else
begin
assign VAR8 = (VAR9 == 0) & (VAR12 == 0) & (VAR11 == 0) & (enable == 1);
assign VAR20 = VAR17;
end
endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.functional.pp.v
| 1,867 |
module MODULE1 (
VAR12 ,
VAR5 ,
VAR9,
VAR4,
VAR6 ,
VAR1
);
output VAR12 ;
input VAR5 ;
input VAR9;
input VAR4;
input VAR6 ;
input VAR1 ;
wire VAR3 ;
wire VAR7;
not VAR2 (VAR3 , VAR5 );
VAR11 VAR10 (VAR7, VAR3, VAR9, VAR4);
buf VAR8 (VAR12 , VAR7 );
endmodule
|
apache-2.0
|
jhoward321/pacman
|
usb_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
| 7,553 |
module MODULE1
parameter VAR38 = 8,
VAR43 = 8,
VAR6 = 0,
VAR23 = 0,
VAR25 = 1,
VAR39 = 0,
VAR45 = 1,
VAR16 = 2,
VAR20 = 2,
VAR7 = 1,
VAR17 = VAR38 / VAR43,
VAR27 = VAR36(VAR17)
)
(
input VAR35,
input VAR28,
input VAR29,
input VAR42,
output VAR34,
input VAR11,
input [VAR38 - 1 : 0] VAR26,
input [VAR25 - 1 : 0] VAR30,
input [VAR45 - 1 : 0] VAR10,
input VAR15,
input VAR4,
input [(VAR27 ? (VAR27 - 1) : 0) : 0] VAR13,
input VAR9,
output VAR19,
output [VAR38 - 1 : 0] VAR1,
output [VAR25 - 1 : 0] VAR32,
output [VAR45 - 1 : 0] VAR2,
output VAR44,
output VAR41,
output [(VAR27 ? (VAR27 - 1) : 0) : 0] VAR21
);
localparam VAR31 = (VAR6) ? 2 + VAR27 : 0;
localparam VAR5 = (VAR23) ? VAR25 : 0;
localparam VAR3 = (VAR39) ? VAR45 : 0;
localparam VAR8 = VAR38 +
VAR31 +
VAR5 +
VAR27 +
VAR3;
wire [VAR8 - 1: 0] VAR14;
wire [VAR8 - 1: 0] VAR33;
assign VAR14[VAR38 - 1 : 0] = VAR26;
generate
if (VAR31) begin
assign VAR14[
VAR38 + VAR31 - 1 :
VAR38
] = {VAR15, VAR4};
end
if (VAR23) begin
assign VAR14[
VAR38 + VAR31 + VAR5 - 1 :
VAR38 + VAR31
] = VAR30;
end
if (VAR27) begin
assign VAR14[
VAR38 + VAR31 + VAR5 + VAR27 - 1 :
VAR38 + VAR31 + VAR5
] = VAR13;
end
if (VAR39) begin
assign VAR14[
VAR38 + VAR31 + VAR5 + VAR27 + VAR3 - 1 :
VAR38 + VAR31 + VAR5 + VAR27
] = VAR10;
end
endgenerate
VAR40
.VAR17 (1),
.VAR43 (VAR8),
.VAR37 (VAR16),
.VAR12 (VAR20),
.VAR7 (VAR7)
) VAR18 (
.VAR35 (VAR35 ),
.VAR28 (VAR28 ),
.VAR34 (VAR34 ),
.VAR11 (VAR11 ),
.VAR26 (VAR14 ),
.VAR29 (VAR29 ),
.VAR42 (VAR42 ),
.VAR9 (VAR9 ),
.VAR19 (VAR19 ),
.VAR1 (VAR33 )
);
assign VAR1 = VAR33[VAR38 - 1 : 0];
generate
if (VAR6) begin
assign {VAR44, VAR41} =
VAR33[VAR38 + VAR31 - 1 : VAR38];
end else begin
assign {VAR44, VAR41} = 2'b0;
end
if (VAR23) begin
assign VAR32 = VAR33[
VAR38 + VAR31 + VAR5 - 1 :
VAR38 + VAR31
];
end else begin
assign VAR32 = 1'b0;
end
if (VAR27) begin
assign VAR21 = VAR33[
VAR38 + VAR31 + VAR5 + VAR27 - 1 :
VAR38 + VAR31 + VAR5
];
end else begin
assign VAR21 = 1'b0;
end
if (VAR39) begin
assign VAR2 = VAR33[
VAR38 + VAR31 + VAR5 + VAR27 + VAR3 - 1 :
VAR38 + VAR31 + VAR5 + VAR27
];
end else begin
assign VAR2 = 1'b0;
end
endgenerate
function integer VAR36;
input integer VAR22;
integer VAR24;
begin
VAR24 = 1;
VAR36 = 0;
while (VAR24 < VAR22) begin
VAR36 = VAR36 + 1;
VAR24 = VAR24 << 1;
end
end
endfunction
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/or2/sky130_fd_sc_ms__or2_4.v
| 2,075 |
module MODULE1 (
VAR6 ,
VAR2 ,
VAR1 ,
VAR5,
VAR8,
VAR9 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR5;
input VAR8;
input VAR9 ;
input VAR7 ;
VAR3 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR2,
VAR1
);
output VAR6;
input VAR2;
input VAR1;
supply1 VAR5;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR7 ;
VAR3 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
alexforencich/xfcp
|
lib/eth/lib/axis/rtl/axis_tap.v
| 11,847 |
module MODULE1 #
(
parameter VAR13 = 8,
parameter VAR57 = (VAR13>8),
parameter VAR52 = (VAR13/8),
parameter VAR47 = 0,
parameter VAR65 = 8,
parameter VAR33 = 0,
parameter VAR31 = 8,
parameter VAR10 = 1,
parameter VAR6 = 1,
parameter VAR44 = 1'b1,
parameter VAR50 = 1'b1
)
(
input wire clk,
input wire rst,
input wire [VAR13-1:0] VAR29,
input wire [VAR52-1:0] VAR67,
input wire VAR60,
input wire VAR35,
input wire VAR21,
input wire [VAR65-1:0] VAR7,
input wire [VAR31-1:0] VAR4,
input wire [VAR6-1:0] VAR1,
output wire [VAR13-1:0] VAR62,
output wire [VAR52-1:0] VAR37,
output wire VAR8,
input wire VAR40,
output wire VAR20,
output wire [VAR65-1:0] VAR24,
output wire [VAR31-1:0] VAR54,
output wire [VAR6-1:0] VAR43
);
reg VAR16;
reg [VAR65-1:0] VAR28 = {VAR65{1'b0}};
reg [VAR31-1:0] VAR53 = {VAR31{1'b0}};
reg [VAR6-1:0] VAR14 = {VAR6{1'b0}};
reg [VAR13-1:0] VAR56;
reg [VAR52-1:0] VAR45;
reg VAR9;
reg VAR36 = 1'b0;
reg VAR34;
reg [VAR65-1:0] VAR30;
reg [VAR31-1:0] VAR19;
reg [VAR6-1:0] VAR17;
wire VAR2;
localparam [1:0]
VAR66 = 2'd0,
VAR61 = 2'd1,
VAR11 = 2'd2,
VAR63 = 2'd3;
reg [1:0] VAR42 = VAR66, VAR38;
reg VAR3 = 1'b0, VAR39;
always @* begin
VAR38 = VAR66;
VAR16 = 1'b0;
VAR39 = VAR3;
VAR56 = {VAR13{1'b0}};
VAR45 = {VAR52{1'b0}};
VAR9 = 1'b0;
VAR34 = 1'b0;
VAR30 = {VAR65{1'b0}};
VAR19 = {VAR31{1'b0}};
VAR17 = {VAR6{1'b0}};
if (VAR35 && VAR60) begin
VAR39 = !VAR21;
end
case (VAR42)
VAR66: begin
if (VAR35 && VAR60) begin
if (VAR36) begin
VAR56 = VAR29;
VAR45 = VAR67;
VAR9 = VAR60 && VAR35;
VAR34 = VAR21;
VAR30 = VAR7;
VAR19 = VAR4;
VAR17 = VAR1;
if (VAR21) begin
VAR38 = VAR66;
end else begin
VAR38 = VAR61;
end
end else begin
VAR38 = VAR63;
end
end else begin
VAR38 = VAR66;
end
end
VAR61: begin
if (VAR35 && VAR60) begin
if (VAR36) begin
VAR56 = VAR29;
VAR45 = VAR67;
VAR9 = VAR60 && VAR35;
VAR34 = VAR21;
VAR30 = VAR7;
VAR19 = VAR4;
VAR17 = VAR1;
if (VAR21) begin
VAR38 = VAR66;
end else begin
VAR38 = VAR61;
end
end else begin
VAR16 = 1'b1;
VAR38 = VAR11;
end
end else begin
VAR38 = VAR61;
end
end
VAR11: begin
if (VAR36) begin
VAR56 = {VAR13{1'b0}};
VAR45 = {{VAR52-1{1'b0}}, 1'b1};
VAR9 = 1'b1;
VAR34 = 1'b1;
VAR30 = VAR28;
VAR19 = VAR53;
VAR17 = (VAR14 & ~VAR50) | (VAR44 & VAR50);
if (VAR39) begin
VAR38 = VAR63;
end else begin
VAR38 = VAR66;
end
end else begin
VAR38 = VAR11;
end
end
VAR63: begin
if (VAR35 && VAR60) begin
if (VAR21) begin
VAR38 = VAR66;
end else begin
VAR38 = VAR63;
end
end else begin
VAR38 = VAR63;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
VAR42 <= VAR66;
VAR3 <= 1'b0;
end else begin
VAR42 <= VAR38;
VAR3 <= VAR39;
end
if (VAR16) begin
VAR28 <= VAR7;
VAR53 <= VAR4;
VAR14 <= VAR1;
end
end
reg [VAR13-1:0] VAR41 = {VAR13{1'b0}};
reg [VAR52-1:0] VAR49 = {VAR52{1'b0}};
reg VAR12 = 1'b0, VAR59;
reg VAR64 = 1'b0;
reg [VAR65-1:0] VAR15 = {VAR65{1'b0}};
reg [VAR31-1:0] VAR32 = {VAR31{1'b0}};
reg [VAR6-1:0] VAR25 = {VAR6{1'b0}};
reg [VAR13-1:0] VAR18 = {VAR13{1'b0}};
reg [VAR52-1:0] VAR22 = {VAR52{1'b0}};
reg VAR27 = 1'b0, VAR58;
reg VAR48 = 1'b0;
reg [VAR65-1:0] VAR5 = {VAR65{1'b0}};
reg [VAR31-1:0] VAR51 = {VAR31{1'b0}};
reg [VAR6-1:0] VAR46 = {VAR6{1'b0}};
reg VAR23;
reg VAR26;
reg VAR55;
assign VAR62 = VAR41;
assign VAR37 = VAR57 ? VAR49 : {VAR52{1'b1}};
assign VAR8 = VAR12;
assign VAR20 = VAR64;
assign VAR24 = VAR47 ? VAR15 : {VAR65{1'b0}};
assign VAR54 = VAR33 ? VAR32 : {VAR31{1'b0}};
assign VAR43 = VAR10 ? VAR25 : {VAR6{1'b0}};
assign VAR2 = VAR40 || (!VAR27 && (!VAR12 || !VAR9));
always @* begin
VAR59 = VAR12;
VAR58 = VAR27;
VAR23 = 1'b0;
VAR26 = 1'b0;
VAR55 = 1'b0;
if (VAR36) begin
if (VAR40 || !VAR12) begin
VAR59 = VAR9;
VAR23 = 1'b1;
end else begin
VAR58 = VAR9;
VAR26 = 1'b1;
end
end else if (VAR40) begin
VAR59 = VAR27;
VAR58 = 1'b0;
VAR55 = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
VAR12 <= 1'b0;
VAR36 <= 1'b0;
VAR27 <= 1'b0;
end else begin
VAR12 <= VAR59;
VAR36 <= VAR2;
VAR27 <= VAR58;
end
if (VAR23) begin
VAR41 <= VAR56;
VAR49 <= VAR45;
VAR64 <= VAR34;
VAR15 <= VAR30;
VAR32 <= VAR19;
VAR25 <= VAR17;
end else if (VAR55) begin
VAR41 <= VAR18;
VAR49 <= VAR22;
VAR64 <= VAR48;
VAR15 <= VAR5;
VAR32 <= VAR51;
VAR25 <= VAR46;
end
if (VAR26) begin
VAR18 <= VAR56;
VAR22 <= VAR45;
VAR48 <= VAR34;
VAR5 <= VAR30;
VAR51 <= VAR19;
VAR46 <= VAR17;
end
end
endmodule
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.behavioral.v
| 1,718 |
module MODULE1( VAR4, VAR5, VAR6 );
input VAR5, VAR4;
output VAR6;
reg VAR3;
VAR7 VAR9(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3));
VAR7 VAR10(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3));
not VAR8(VAR1,VAR5);
buf VAR11(VAR2,VAR5);
|
apache-2.0
|
tmatsuya/milkymist-ml401
|
cores/ac97/rtl/ac97.v
| 5,027 |
module MODULE1 #(
parameter VAR29 = 4'h0
) (
input VAR37,
input VAR69,
input VAR43,
input VAR14,
input VAR39,
output VAR67,
output VAR4,
input [13:0] VAR51,
input VAR64,
input [31:0] VAR26,
output [31:0] VAR48,
output VAR3,
output VAR20,
output VAR27,
output VAR8,
output [31:0] VAR76,
output [2:0] VAR58,
output VAR32,
output VAR35,
output VAR47,
input VAR46,
input [31:0] VAR17,
output [31:0] VAR50
);
wire VAR30;
wire VAR65;
wire VAR10;
wire VAR57;
wire VAR25;
wire VAR66;
wire VAR19;
wire VAR28;
VAR1 VAR15(
.VAR37(VAR37),
.VAR69(VAR69),
.VAR43(VAR43),
.VAR14(VAR14),
.VAR39(VAR39),
.VAR67(VAR67),
.VAR4(VAR4),
.VAR30(VAR30),
.VAR65(VAR65),
.VAR10(VAR10),
.VAR77(VAR57),
.VAR25(VAR25),
.VAR66(VAR66),
.VAR19(VAR19),
.VAR36(VAR28)
);
wire VAR49;
wire VAR13;
wire VAR61;
wire [19:0] VAR63;
wire VAR41;
wire [19:0] VAR36;
wire VAR9;
wire [19:0] VAR16;
wire VAR52;
wire [19:0] VAR5;
VAR68 VAR71(
.VAR37(VAR37),
.VAR69(VAR69),
.VAR25(VAR25),
.VAR66(VAR66),
.VAR19(VAR19),
.VAR36(VAR28),
.en(VAR49),
.VAR38(VAR13),
.VAR62(VAR61),
.addr(VAR63),
.VAR18(VAR41),
.VAR53(VAR36),
.VAR73(VAR9),
.VAR54(VAR16),
.VAR56(VAR52),
.VAR34(VAR5)
);
wire VAR60;
wire VAR59;
wire VAR42;
wire VAR12;
wire [19:0] VAR80;
wire VAR40;
wire [19:0] VAR77;
wire VAR75;
wire [19:0] VAR22;
wire VAR45;
wire [19:0] VAR6;
VAR70 VAR23(
.VAR37(VAR37),
.VAR69(VAR69),
.VAR30(VAR30),
.VAR65(VAR65),
.VAR10(VAR10),
.VAR77(VAR57),
.en(VAR60),
.VAR38(VAR59),
.VAR44(VAR42),
.VAR62(VAR12),
.addr(VAR80),
.VAR18(VAR40),
.VAR53(VAR77),
.VAR73(VAR75),
.VAR54(VAR22),
.VAR56(VAR45),
.VAR34(VAR6)
);
wire VAR7;
wire [29:0] VAR33;
wire [15:0] VAR78;
wire VAR72;
wire VAR11;
wire [29:0] VAR21;
wire [15:0] VAR55;
wire VAR24;
VAR2 #(
.VAR29(VAR29)
) VAR74 (
.VAR37(VAR37),
.VAR69(VAR69),
.VAR51(VAR51),
.VAR64(VAR64),
.VAR26(VAR26),
.VAR48(VAR48),
.VAR3(VAR3),
.VAR20(VAR20),
.VAR27(VAR27),
.VAR8(VAR8),
.VAR49(VAR49),
.VAR13(VAR13),
.VAR61(VAR61),
.VAR63(VAR63),
.VAR41(VAR41),
.VAR36(VAR36),
.VAR60(VAR60),
.VAR59(VAR59),
.VAR42(VAR42),
.VAR12(VAR12),
.VAR80(VAR80),
.VAR40(VAR40),
.VAR77(VAR77),
.VAR7(VAR7),
.VAR33(VAR33),
.VAR78(VAR78),
.VAR72(VAR72),
.VAR11(VAR11),
.VAR21(VAR21),
.VAR55(VAR55),
.VAR24(VAR24)
);
VAR79 VAR31(
.VAR37(VAR37),
.VAR69(VAR69),
.VAR76(VAR76),
.VAR58(VAR58),
.VAR32(VAR32),
.VAR35(VAR35),
.VAR47(VAR47),
.VAR46(VAR46),
.VAR17(VAR17),
.VAR50(VAR50),
.VAR49(VAR49),
.VAR13(VAR13),
.VAR9(VAR9),
.VAR16(VAR16),
.VAR52(VAR52),
.VAR5(VAR5),
.VAR60(VAR60),
.VAR59(VAR59),
.VAR42(VAR42),
.VAR75(VAR75),
.VAR22(VAR22),
.VAR45(VAR45),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR33(VAR33),
.VAR78(VAR78),
.VAR72(VAR72),
.VAR11(VAR11),
.VAR21(VAR21),
.VAR55(VAR55),
.VAR24(VAR24)
);
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.v
| 2,128 |
module MODULE1 (
VAR8 ,
VAR9 ,
VAR4 ,
VAR5,
VAR3,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR5;
input VAR3;
input VAR7 ;
input VAR6 ;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8 ,
VAR9,
VAR4
);
output VAR8 ;
input VAR9;
input VAR4 ;
supply1 VAR5;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR6 ;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
cpulabs/mist1032isa
|
src/core/l1_instruction/l1_inst_cache_64entry_4way_line64b_bus_8b_disable_cache.v
| 1,457 |
module MODULE1(
input wire VAR15,
input wire VAR12,
input wire VAR4,
input wire VAR16,
input wire VAR5,
output wire VAR8,
input wire [31:0] VAR2, output wire VAR13,
output wire VAR17,
input wire VAR7,
output wire [63:0] VAR11,
output wire [23:0] VAR6,
input wire VAR14,
output wire VAR10,
input wire [31:0] VAR9, input wire [511:0] VAR1,
input wire [255:0] VAR18
);
assign VAR8 = 1'b0;
reg VAR3;
always@(posedge VAR15 or negedge VAR12)begin
if(!VAR12)begin
VAR3 <= 1'b0;
end
else if(VAR4)begin
VAR3 <= 1'b0;
end
else if(VAR16)begin
VAR3 <= 1'b0;
end
else begin
VAR3 <= VAR5;
end
end
assign VAR13 = VAR3;
assign VAR17 = 1'b0;
assign VAR11 = 64'h0;
assign VAR6 = 23'h0;
assign VAR10 = 1'b0;
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dlrtn/sky130_fd_sc_hd__dlrtn.pp.blackbox.v
| 1,385 |
module MODULE1 (
VAR8 ,
VAR6,
VAR5 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR6;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
endmodule
|
apache-2.0
|
christakissgeo/Matrix-Vector-Multiplication
|
Libraries/NangateOpenCellLibrary.v
| 220,307 |
module MODULE1 (VAR1, VAR2, VAR3);
input VAR1;
input VAR2;
output VAR3;
and(VAR3, VAR1, VAR2);
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/ucore/bypass.v
| 9,242 |
module MODULE1
(
VAR33,VAR48,
VAR25,VAR17,VAR5,VAR16,
VAR32,VAR31,
VAR27,VAR37,VAR8,VAR28,
VAR26,VAR15,VAR19,VAR13,
VAR34,VAR47,
VAR20,VAR50,VAR44,
VAR2,VAR46,VAR45,VAR18,
VAR42,VAR29,VAR9,
VAR36,VAR38,VAR35,
VAR30,VAR11,VAR24,
VAR49,VAR1,VAR51,
VAR6,VAR7,VAR43,
VAR3,VAR40,
VAR21
);
input VAR33;
input VAR48;
input [VAR4-1:0] VAR25; input VAR17; input [VAR4-1:0] VAR5; input VAR16;
input VAR32;
input VAR31;
input VAR27;
input VAR37;
input VAR28;
input [31:0] VAR8;
input VAR26;
input VAR15;
input VAR13;
input [31:0] VAR19;
input VAR34;
input VAR47;
input [VAR4-1:0] VAR50; input VAR20; input [31:0] VAR44;
output [VAR4-1:0] VAR2; output [VAR4-1:0] VAR46; output VAR45; output VAR18;
input [VAR4-1-1:0] VAR42;
input [31:0] VAR29;
input VAR9;
input [VAR4-1-1:0] VAR36;
output [31:0] VAR38;
input VAR35;
output [31:0] VAR30; output [VAR4-1:0] VAR11; output VAR24;
output VAR49;
output [VAR4-1:0] VAR1; input [31:0] VAR51;
output VAR6;
output [VAR4-1:0] VAR7; input [31:0] VAR43;
output [31:0] VAR3;
output [31:0] VAR40;
output VAR21;
assign VAR2 = VAR25;
assign VAR45 = VAR17;
assign VAR46 = VAR5;
assign VAR18 = VAR16;
assign VAR24 = VAR9? 1:VAR20;
assign VAR30 = VAR9? VAR29:VAR44;
assign VAR11 = VAR9? {1'b1,VAR42}:VAR50;
assign VAR49 = VAR17 ;
assign VAR1 = VAR25;
assign VAR6 = VAR35? 1 : VAR16 ;
assign VAR7 = VAR35? {1'b1,VAR36} : VAR5;
assign VAR38 = VAR43;
assign VAR3 = VAR27 ? VAR8 :
VAR26 ? VAR19 :
VAR34 ? VAR44 : VAR51;
assign VAR40 = VAR37 ? VAR8 :
VAR15 ? VAR19 :
VAR47 ? VAR44 : VAR43;
wire VAR41,VAR14,VAR39,VAR23;
wire VAR22,VAR52,VAR10,VAR12;
assign VAR22 = 0;
assign VAR52 = VAR28 ;
assign VAR10 = VAR13;
assign VAR12 = 1;
assign VAR41 = (VAR32 | VAR31 ) ;
assign VAR14 = (VAR27 | VAR37 ) & !VAR52;
assign VAR39 = (VAR26 | VAR15) & !VAR10;
assign VAR23 = 0;
assign VAR21 = VAR41 | VAR14 | VAR39 ;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o32ai/sky130_fd_sc_hs__o32ai_2.v
| 2,314 |
module MODULE1 (
VAR5 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR9 ,
VAR3 ,
VAR6,
VAR1
);
output VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR1;
VAR8 VAR2 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5 ,
VAR10,
VAR7,
VAR4,
VAR9,
VAR3
);
output VAR5 ;
input VAR10;
input VAR7;
input VAR4;
input VAR9;
input VAR3;
supply1 VAR6;
supply0 VAR1;
VAR8 VAR2 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sregsbp/sky130_fd_sc_lp__sregsbp.blackbox.v
| 1,381 |
module MODULE1 (
VAR6 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR3
);
output VAR6 ;
output VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR3;
supply1 VAR10;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
glennchid/font5-firmware
|
src/verilog/synthesis/FFControl.v
| 9,909 |
module MODULE1 (
input clk,
input VAR28,
input VAR8,
input VAR4,
input [9:0] VAR56,
input [9:0] VAR39,
input [4:0] VAR51,
input [4:0] VAR37,
input [1:0] VAR46, input signed [12:0] VAR62,
input signed [12:0] VAR10,
input signed [12:0] VAR43,
input signed [12:0] VAR42,
input signed [6:0] VAR55,
input signed [6:0] VAR36,
input VAR53,
input VAR1,
input VAR54,
input signed [6:0] VAR61, VAR25,
output reg VAR31 = 1'b0,
output signed [12:0] VAR15,
output signed [12:0] VAR20,
output VAR11,
output VAR17
);
wire signed [17:0] VAR29;
reg signed [17:0] VAR66 = 18'VAR57;
reg signed [24:0] VAR41 = 25'VAR57, VAR23 = 25'VAR57, VAR30 = 25'VAR57;
reg signed [43:0] VAR13 = 44'VAR57, VAR19 = 44'VAR57; parameter VAR60 = 3'd6;
VAR38 VAR59(
.VAR2(clk),
.VAR33(VAR43),
.VAR58(VAR29)
);
reg VAR35 = 1'b1, VAR21 = 1'b1;
reg VAR67 = 1'b1, VAR3 = 1'b1;
reg [9:0] VAR63 = 10'd0, VAR34 = 10'd0;
reg [9:0] VAR12 = 10'd164, VAR52 = 10'd164;
reg [4:0] VAR44 = 5'd0, VAR65 = 5'd0;
reg [4:0] VAR6 = 5'd0, VAR40= 5'd0;
reg [1:0] VAR24 = 2'd0, VAR48 = 2'd0;
reg signed [12:0] VAR49 = 13'd0, VAR47 = 13'd0;
reg signed [12:0] VAR5 = 13'd0, VAR7 = 13'd0;
reg signed [6:0] VAR22 = 7'd32, VAR16 = 7'd32;
reg signed [6:0] VAR27 = 7'd32, VAR50 = 7'd32;
reg VAR45 = 1'b0, VAR64 = 1'b0;
reg VAR14 = 1'b0, VAR18 = 1'b0;
reg VAR35 = 1'b0, VAR21 = 1'b0;
reg VAR67 = 1'b0, VAR3 = 1'b0;
reg [9:0] VAR63 = 10'd0, VAR34 = 10'd0;
reg [9:0] VAR12 = 10'd0, VAR52 = 10'd0;
reg [4:0] VAR44 = 5'd0, VAR65 = 5'd0;
reg [4:0] VAR6 = 5'd0, VAR40= 5'd0;
reg [1:0] VAR24 = 2'd0, VAR48 = 2'd0;
reg signed [12:0] VAR49 = 13'd0, VAR47 = 13'd0;
reg signed [12:0] VAR5 = 13'd0, VAR7 = 13'd0;
reg signed [6:0] VAR22 = 7'd0, VAR16 = 7'd0;
reg signed [6:0] VAR27 = 7'd0, VAR50 = 7'd0;
reg VAR45 = 1'b0, VAR64 = 1'b0;
reg VAR14 = 1'b0, VAR18 = 1'b0;
always @(posedge clk) begin
VAR35 <= VAR21;
VAR21 <= VAR8;
VAR67 <= VAR3;
VAR3 <= VAR4;
VAR63 <= VAR34;
VAR34 <= VAR56;
VAR12 <= VAR52;
VAR52 <= VAR39;
VAR44 <= VAR65;
VAR65 <= VAR51;
VAR6 <= VAR40;
VAR40 <= VAR37;
VAR24 <= VAR48;
VAR48 <= VAR46;
VAR49 <= VAR47;
VAR47 <= VAR62;
VAR5 <= VAR7;
VAR7 <= VAR10;
VAR22 <= VAR16;
VAR16 <= VAR55;
VAR27 <= VAR50;
VAR50 <= VAR36;
VAR45 <= VAR64;
VAR64 <= VAR53;
VAR14 <= VAR18;
VAR18 <= VAR1;
end
always @(posedge clk) begin
VAR30 <= VAR23; VAR23 <= VAR41;
VAR41 <= (VAR42 <<< VAR60); VAR66 <= VAR29; VAR13 <= (VAR30 * VAR66);
VAR19 <= VAR13;
if (VAR31 && VAR54) VAR31 <= 1'b0;
end
else if (!(&VAR19[43:29] || &(~VAR19[43:29]))) VAR31 <= 1'b1; else VAR31 <= VAR31;
end
VAR9 VAR26(clk, VAR28, VAR35, VAR67, VAR63, VAR12, VAR44, VAR24, VAR49, VAR19[29:5], VAR22, VAR45, VAR61, VAR15, VAR11);VAR9 VAR32(clk, VAR28, VAR35, VAR67, VAR63, VAR12, VAR6, VAR24, VAR5, VAR19[29:5], VAR27, VAR14, VAR25, VAR20, VAR17);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a221o/sky130_fd_sc_ls__a221o.behavioral.v
| 1,662 |
module MODULE1 (
VAR4 ,
VAR17,
VAR10,
VAR16,
VAR1,
VAR15
);
output VAR4 ;
input VAR17;
input VAR10;
input VAR16;
input VAR1;
input VAR15;
supply1 VAR11;
supply0 VAR14;
supply1 VAR8 ;
supply0 VAR6 ;
wire VAR13 ;
wire VAR2 ;
wire VAR7;
and VAR3 (VAR13 , VAR16, VAR1 );
and VAR5 (VAR2 , VAR17, VAR10 );
or VAR12 (VAR7, VAR2, VAR13, VAR15);
buf VAR9 (VAR4 , VAR7 );
endmodule
|
apache-2.0
|
mistryalok/Zedboard
|
learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_src_cols_V_2_loc_channel1.v
| 3,047 |
module MODULE2 (
clk,
VAR3,
VAR21,
VAR23,
VAR18);
parameter VAR11 = 32'd12;
parameter VAR10 = 32'd2;
parameter VAR6 = 32'd3;
input clk;
input [VAR11-1:0] VAR3;
input VAR21;
input [VAR10-1:0] VAR23;
output [VAR11-1:0] VAR18;
reg[VAR11-1:0] VAR14 [0:VAR6-1];
integer VAR27;
always @ (posedge clk)
begin
if (VAR21)
begin
for (VAR27=0;VAR27<VAR6-1;VAR27=VAR27+1)
VAR14[VAR27+1] <= VAR14[VAR27];
VAR14[0] <= VAR3;
end
end
assign VAR18 = VAR14[VAR23];
endmodule
module MODULE1 (
clk,
reset,
VAR2,
VAR17,
VAR9,
VAR19,
VAR16,
VAR1,
VAR20,
VAR13);
parameter VAR25 = "VAR26";
parameter VAR11 = 32'd12;
parameter VAR10 = 32'd2;
parameter VAR6 = 32'd3;
input clk;
input reset;
output VAR2;
input VAR17;
input VAR9;
output[VAR11 - 1:0] VAR19;
output VAR16;
input VAR1;
input VAR20;
input[VAR11 - 1:0] VAR13;
wire[VAR10 - 1:0] VAR8 ;
wire[VAR11 - 1:0] VAR22, VAR5;
reg[VAR10:0] VAR4 = {(VAR10+1){1'b1}};
reg VAR15 = 0, VAR7 = 1;
assign VAR2 = VAR15;
assign VAR16 = VAR7;
assign VAR22 = VAR13;
assign VAR19 = VAR5;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR4 <= ~{VAR10+1{1'b0}};
VAR15 <= 1'b0;
VAR7 <= 1'b1;
end
else begin
if (((VAR9 & VAR17) == 1 & VAR15 == 1) &&
((VAR20 & VAR1) == 0 | VAR7 == 0))
begin
VAR4 <= VAR4 -1;
if (VAR4 == 0)
VAR15 <= 1'b0;
VAR7 <= 1'b1;
end
else if (((VAR9 & VAR17) == 0 | VAR15 == 0) &&
((VAR20 & VAR1) == 1 & VAR7 == 1))
begin
VAR4 <= VAR4 +1;
VAR15 <= 1'b1;
if (VAR4 == VAR6-2)
VAR7 <= 1'b0;
end
end
end
assign VAR8 = VAR4[VAR10] == 1'b0 ? VAR4[VAR10-1:0]:{VAR10{1'b0}};
assign VAR12 = (VAR20 & VAR1) & VAR7;
MODULE2
.VAR11(VAR11),
.VAR10(VAR10),
.VAR6(VAR6))
VAR24 (
.clk(clk),
.VAR3(VAR22),
.VAR21(VAR12),
.VAR23(VAR8),
.VAR18(VAR5));
endmodule
|
gpl-3.0
|
JakeMercer/mac
|
crc.v
| 4,790 |
module MODULE1 #(
parameter VAR18 = 5'b00101,
parameter VAR20 = 8,
parameter VAR15 = 5,
parameter VAR12 = 0,
parameter VAR13 = 0,
parameter VAR14 = 1
)(
input [VAR20-1:0] VAR6,
input VAR7,
output reg [VAR15-1:0] VAR4,
input VAR3,
input VAR11,
input reset
);
function automatic VAR17;
input integer VAR10;
input integer VAR8;
input [VAR20-1:0] VAR6;
input [VAR15-1:0] MODULE1;
begin
if (VAR18[VAR8])
begin
if (VAR10)
begin
if (VAR8)
begin
if (VAR13)
?VAR8-1:VAR15-1, VAR15-1, VAR20 - 1 - VAR10);
VAR17 = VAR17(VAR10-1, (VAR8)?VAR8-1:VAR15-1, VAR6, MODULE1) ^ VAR17(VAR10-1, VAR15-1, VAR6, MODULE1) ^ VAR6[VAR20-1-VAR10];
end
else
begin
if (VAR13)
VAR17 = VAR17(VAR10-1, VAR15-1, VAR6, MODULE1) ^ VAR6[VAR20-1-VAR10];
end
end
else
begin
if (VAR8)
begin
if (VAR13)
VAR1("VAR16 %0d | MODULE1[%0d] = MODULE1[%0d] ^ MODULE1[%0d] ^ VAR6[%0d] VAR17 = MODULE1[VAR8-1-:1] ^ MODULE1[VAR15-1-:1] ^ VAR6[VAR20-1-VAR10];
end
else
begin
if (VAR13)
VAR1("VAR16 %0d | MODULE1[%0d] = MODULE1[%0d] ^ VAR6[%0d] VAR17 = MODULE1[VAR15-1-:1] ^ VAR6[VAR20-1-VAR10];
end
end
end
else
begin
if (VAR10)
begin
if (VAR8)
begin
if (VAR13)
VAR17 = VAR17(VAR10-1, VAR8-1, VAR6, MODULE1);
end
else
begin
if (VAR13)
VAR17 = VAR17(VAR10-1, VAR15-1, VAR6, MODULE1) ^ VAR6[VAR20-1-VAR10];
end
end
else
begin
if (VAR8)
begin
if (VAR13)
VAR1("VAR16 %0d | MODULE1[%0d] = MODULE1[%0d] VAR17 = MODULE1[VAR8-1-:1];
end
else
begin
if (VAR13)
VAR1("VAR16 %0d | MODULE1[%0d] = MODULE1[%0d] ^ VAR6[%0d] VAR17 = MODULE1[VAR15-1-:1] ^ VAR6[VAR20-1-VAR10];
end
end
end
end
endfunction
wire [VAR20-1:0] VAR5;
genvar VAR2;
generate
if (VAR14)
begin
for (VAR2 = VAR20-1; VAR2 >= 0; VAR2 = VAR2 - 1)
begin : VAR21
assign VAR5[VAR20-1-VAR2] = VAR6[VAR2];
end
end
else
begin
assign VAR5 = VAR6;
end
endgenerate
genvar VAR19;
generate
for(VAR19 = 0; VAR19 < VAR15; VAR19= VAR19 + 1)
begin : VAR9
always @(posedge VAR11)
begin
if (reset)
begin
VAR4[VAR19+:1] = VAR12[VAR19+:1];
end
else if (VAR3)
begin
VAR4[VAR19+:1] = VAR12[VAR19+:1];
end
else if (VAR7)
begin
if (VAR13)
VAR4[VAR19+:1] <= VAR17(VAR20-1,VAR19,VAR5,VAR4);
end
end
end
endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/bufinv/sky130_fd_sc_hd__bufinv.pp.symbol.v
| 1,272 |
module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR5 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/or3b/sky130_fd_sc_lp__or3b_m.v
| 2,206 |
module MODULE1 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR7 ,
VAR10,
VAR5,
VAR1 ,
VAR2
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR10;
input VAR5;
input VAR1 ;
input VAR2 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR7
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR7;
supply1 VAR10;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR2 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
ychaim/FPGA-Litecoin-Miner
|
experimental/CM1/main_dcm.v
| 5,673 |
module MODULE1
( input VAR13,
output VAR17,
input VAR23,
input VAR32,
input VAR22,
output VAR18,
input VAR1,
output VAR24
);
parameter VAR35 = 10;
parameter VAR21 = 60;
VAR19 VAR14
(.VAR38 (VAR9),
.VAR12 (VAR13));
wire VAR27;
wire [2:1] VAR39;
wire VAR25;
wire VAR31;
wire VAR3;
VAR29
.VAR15 (VAR21),
.VAR30 ("VAR36"),
.VAR37 ("VAR20"),
.VAR4 (40.000),
.VAR8 (0.000))
VAR26
(.VAR10 (VAR9),
.VAR33 (VAR3),
.VAR5 (VAR31),
.VAR7 (VAR25), .VAR23 (VAR23),
.VAR32 (VAR32),
.VAR22 (VAR22),
.VAR18 (VAR18),
.VAR6 (1'b0),
.VAR11 (VAR27),
.VAR2 (VAR39),
.VAR34 (VAR1));
assign VAR24 = ( ( VAR27 == 1'VAR16 1 ) && ( VAR39[2] == 1'VAR16 0 ) );
VAR19 VAR28
(.VAR38 (VAR17),
.VAR12 (VAR25));
endmodule
|
gpl-3.0
|
zeruniverse/Single-cycle_CPU
|
ISE project/CPU_CTR.v
| 1,152 |
module MODULE1(
input [5:0]VAR1,
output wire VAR20,VAR3,VAR17,VAR6,VAR8,VAR11,VAR21,VAR19,VAR14 );
wire VAR5,VAR15,VAR4,VAR16,VAR18;
and VAR7(VAR14,~VAR1[5],~VAR1[4],~VAR1[3],~VAR1[2],VAR1[1],~VAR1[0]),
VAR2(VAR15,~VAR1[5],~VAR1[4],~VAR1[3],~VAR1[2],~VAR1[1],~VAR1[0]),
VAR13(VAR4,VAR1[5],~VAR1[4],~VAR1[3],~VAR1[2],VAR1[1],VAR1[0]),
VAR9(VAR16,VAR1[5],~VAR1[4],VAR1[3],~VAR1[2],VAR1[1],VAR1[0]),
VAR22(VAR18,~VAR1[5],~VAR1[4],~VAR1[3],VAR1[2],~VAR1[1],~VAR1[0]);
or VAR10(VAR3,VAR4,VAR16),
VAR12(VAR6,VAR15,VAR4);
assign VAR20=VAR15;
assign VAR17=VAR4;
assign VAR8=VAR16;
assign VAR11=VAR18;
assign VAR21=VAR15;
assign VAR19=VAR18;
endmodule
|
gpl-3.0
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_bif.v
| 5,708 |
module MODULE1(
output wire VAR11 ,
output wire VAR4 ,
output reg VAR13 ,
output reg [ 3 : 0] VAR12 ,
output wire [31 : 0] VAR21 ,
output wire [31 : 0] VAR7 ,
input wire [31 : 0] VAR24 ,
output wire VAR22 ,
input wire VAR26 ,
input wire [31 : 0] VAR29 ,
input wire VAR8 ,
output wire VAR31 ,
output wire [31 : 0] VAR25 ,
input wire VAR1 ,
output reg VAR14 ,
output reg VAR23 ,
input wire VAR17 ,
input wire [23 : 0] VAR32 ,
input wire [23 : 0] VAR3 ,
input wire [23 : 0] VAR30 ,
input wire VAR5 ,
input wire VAR6
);
localparam VAR9 = 5'b10000; localparam VAR15 = 5'b01000; localparam VAR18 = 5'b00100; localparam VAR27 = 5'b00010; localparam VAR28 = 5'b00001;
reg [ 4 : 0] state ;
reg [15 : 0] VAR16 ;
wire VAR20 ;
wire [23 : 0] VAR10 ;
wire [23 : 0] VAR2 ;
wire [23 : 0] VAR19 ;
assign VAR10 = (VAR32);
assign VAR2 = (VAR3);
assign VAR19 = VAR10 + VAR2;
assign VAR20 = (VAR16 == VAR19 ? 1'b1 : 1'b0);
assign VAR11 = VAR5 ;
assign VAR4 = ~VAR6 ;
assign VAR7 = VAR29 ;
assign VAR25 = VAR24 ;
assign VAR21 = VAR16 << 32'd2;
assign VAR31 = (state == VAR18) ;
assign VAR22 = (state == VAR28);
always @(posedge VAR5) begin
if ((state == VAR9) & (VAR1 == 0)) begin
VAR16 <= VAR10;
end
else if ((state == VAR15 | state == VAR27) & (VAR20 != 1)) begin
VAR16 <= VAR16 + 1;
end
end
always @(state or VAR20) begin
if ((VAR1 != 1) & (state == VAR9)) begin
VAR23 = 1;
end
else begin
VAR23 = 0;
end
end
always @(state or VAR20) begin
if (VAR1 == 1 & VAR3 == 24'd0) begin
VAR14 = 1;
end
else if ((state == VAR15 | state == VAR28) & (VAR20 == 1)) begin
VAR14 = 1;
end
else begin
VAR14 = 0;
end
end
always @(state or VAR14) begin
if ((state == VAR15 | state == VAR28) & (VAR14 != 1)) begin
VAR13 = 1;
end
else begin
VAR13 = 0;
end
end
always @(state or VAR14) begin
if (state == VAR28 & VAR14 != 1) begin
VAR12 = 4'hF;
end
else begin
VAR12 = 4'h0;
end
end
always @(posedge VAR5) begin
if (!VAR6) begin
state <= VAR9;
end
else begin
case (state)
VAR9: begin
if (VAR1) begin
if (!VAR17) begin
state <= VAR15;
end
else begin
state <= VAR28;
end
end
end
VAR15: begin
if (VAR20 != 1) begin
state <= VAR18;
end
else begin
state <= VAR9;
end
end
VAR18: begin
if (VAR8 == 1) begin
state <= VAR15;
end
else begin
state <= VAR18;
end
end
VAR28: begin
if (VAR20 != 1) begin
if (VAR26 == 1) begin
state <= VAR27;
end
else begin
state <= VAR28;
end
end
else begin
state <= VAR9;
end
end
VAR27: begin
state <= VAR28;
end
endcase
end
end
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
models/udp_dff_nr_pp_pkg_s/sky130_fd_sc_hs__udp_dff_nr_pp_pkg_s.blackbox.v
| 1,463 |
module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR6 ,
VAR3,
VAR5 ,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR3;
input VAR5 ;
input VAR2 ;
input VAR4 ;
endmodule
|
apache-2.0
|
rkrajnc/minimig-mist
|
rtl/ctrl/qmem_sram_longcycles.v
| 5,602 |
module MODULE1 #(
parameter VAR37 = 32,
parameter VAR9 = 32,
parameter VAR11 = VAR9/8
)(
input wire VAR35,
input wire VAR13,
input wire rst,
input wire [VAR37-1:0] VAR31,
input wire VAR30,
input wire VAR10,
input wire [VAR11-1:0] sel,
input wire [VAR9-1:0] VAR18,
output reg [VAR9-1:0] VAR5,
output wire ack,
output wire VAR36,
output wire [18-1:0] VAR27,
output wire VAR19,
output wire VAR4,
output wire VAR26,
output wire VAR16,
output wire VAR15,
output wire [16-1:0] VAR29,
input wire [16-1:0] VAR20
);
localparam VAR24 = 3'b000; localparam VAR38 = 3'b011; localparam VAR2 = 3'b111;
localparam VAR34 = 3'b010; localparam VAR39 = 3'b110;
localparam VAR23 = 3'b001;
reg [2:0] state, VAR12;
always @ (*)
begin
case (state)
end
VAR24 : begin if (VAR30) VAR12 = VAR38; else VAR12 = VAR24; end
VAR38 : begin if (VAR30) VAR12 = VAR2; else VAR12 = VAR24; end
VAR2 : begin if (VAR30) VAR12 = VAR34; else VAR12 = VAR24; end
VAR34 : begin if (VAR30) VAR12 = VAR39; else VAR12 = VAR24; end
VAR39 : begin if (VAR30) VAR12 = VAR23; else VAR12 = VAR24; end
VAR23 : begin VAR12 = VAR24; end
default : begin VAR12 = VAR24; end
endcase
end
always @ (posedge VAR13 or posedge rst)
begin
if (rst)
state <= VAR24;
end
else
state <= VAR12;
end
reg [17:0] VAR22;
always @ (posedge VAR13)
begin
if (VAR12 == VAR38)
VAR22 <= {VAR31[18:2], 1'b0};
end
else if (VAR12 == VAR34)
VAR22 <= {VAR31[18:2], 1'b1};
end
reg VAR6;
always @ (posedge VAR13 or posedge rst)
begin
if (rst)
VAR6 <= 1'b1;
end
else if ((VAR12 == VAR38) || (VAR12 == VAR2) || (VAR12 == VAR34) || (VAR12 == VAR39))
VAR6 <= 1'b0;
end
else
VAR6 <= 1'b1;
end
reg VAR32;
always @ (posedge VAR13)
begin
if ((VAR12 == VAR38) || (VAR12 == VAR2) || (VAR12 == VAR34) || (VAR12 == VAR39))
VAR32 <= !VAR10;
end
reg VAR8, VAR33;
always @ (posedge VAR13)
begin
if (VAR12 == VAR38)
{VAR8, VAR33} <= {!sel[3], !sel[2]};
end
else if (VAR12 == VAR34)
{VAR8, VAR33} <= {!sel[1], !sel[0]};
end
reg VAR1;
always @ (posedge VAR13)
begin
if ((VAR12 == VAR38) || (VAR12 == VAR2) || (VAR12 == VAR34) || (VAR12 == VAR39))
VAR1 <= VAR10;
end
else
VAR1 <= 1'b0;
end
reg [15:0] VAR28;
always @ (posedge VAR13)
begin
if (VAR12 == VAR38)
VAR28 <= VAR18[31:16];
end
else if (VAR12 == VAR34)
VAR28 <= VAR18[15:0];
end
reg [31:0] VAR14;
always @ (posedge VAR13)
begin
if ((VAR12 == VAR34) && !VAR10)
VAR5[31:16] <= VAR20;
end
else if ((VAR12 == VAR23) && !VAR10)
VAR5[15: 0] <= VAR20;
end
reg VAR25;
always @ (posedge VAR13 or posedge rst)
begin
if (rst)
VAR25 <= 1'b0;
end
else if ((state == VAR39) || (state == VAR23))
VAR25 <= 1'b1;
else
VAR25 <= 1'b0;
end
assign VAR27 = VAR22;
assign VAR19 = VAR6;
assign VAR4 = VAR32;
assign VAR26 = VAR8;
assign VAR16 = VAR33;
assign VAR15 = VAR1;
assign VAR29 = VAR28;
assign ack = VAR25;
assign VAR36 = 1'b0;
reg [ VAR37-1:0] VAR17;
wire VAR21;
reg VAR3;
reg [ 16-1:0] VAR7;
always @ (posedge VAR35) VAR17 <= VAR31;
assign VAR21 = (VAR31 != VAR17);
always @ (posedge VAR35 or posedge rst)
begin
if (rst)
VAR3 <= 1'b0;
end
else if (VAR21)
VAR3 <= 1'b0;
else if (VAR30)
VAR3 <= !VAR3;
end
always @ (posedge VAR35) if (VAR30 && !VAR3 && !VAR10) VAR7 <= VAR20;
always @ (posedge VAR35) if (VAR30 && VAR3 && !VAR10) VAR5 <= {VAR20, VAR7};
assign ack = VAR3;
assign VAR36 = 1'b0;
assign VAR27 = (!VAR3) ? {VAR31[18:2], 1'b0} : {VAR31[18:2], 1'b1};
assign VAR19 = !VAR30;
assign VAR4 = !VAR10;
assign VAR26 = !((!VAR3) ? sel[1] : sel[3]);
assign VAR16 = !((!VAR3) ? sel[0] : sel[2]);
assign VAR15 = VAR10;
assign VAR29 = (!VAR3) ? VAR18[15:0] : VAR18[31:16];
endmodule
|
gpl-3.0
|
azonenberg/antikernel-ipcores
|
noc/rpcv3/RPCv3RouterReceiver_expanding.v
| 8,426 |
module MODULE1
parameter VAR1 = 32,
parameter VAR2 = 16
)
(
input wire clk,
input wire VAR5,
input wire[VAR2-1:0] VAR9,
output reg VAR8 = 0,
input wire VAR3,
output wire VAR6,
output reg VAR10 = 0,
output reg[VAR1-1:0] VAR7 = 0,
output reg VAR4 = 0
);
|
bsd-3-clause
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.functional.pp.v
| 1,410 |
module MODULE1( VAR14, VAR13, VAR10, VAR16, VAR17, VAR4, VAR21, VAR2, VAR6 );
input VAR21, VAR4, VAR14, VAR10, VAR13, VAR17;
inout VAR2, VAR6;
output VAR16;
wire VAR19;
not VAR12( VAR19, VAR13 );
wire VAR18;
not VAR9( VAR18, VAR17 );
wire VAR20;
and VAR22( VAR20, VAR19, VAR18, VAR21 );
wire VAR11;
and VAR15( VAR11, VAR18, VAR4, VAR13 );
wire VAR8;
and VAR7( VAR8, VAR19, VAR14, VAR17 );
wire VAR5;
and VAR1( VAR5, VAR10, VAR13, VAR17 );
or VAR3( VAR16, VAR20, VAR11, VAR8, VAR5 );
endmodule
|
apache-2.0
|
saisrivathsa/Image-Watermarking
|
ipcore_dir/Bmul.v
| 3,628 |
module MODULE2 (
VAR12, VAR27
);
output [7 : 0] VAR12;
input [7 : 0] VAR27;
wire [7 : 1] VAR31;
assign
VAR12[6] = VAR31[7],
VAR12[5] = VAR31[6],
VAR12[4] = VAR31[5],
VAR12[3] = VAR31[4],
VAR12[2] = VAR31[3],
VAR12[1] = VAR31[2],
VAR12[0] = VAR31[1],
VAR31[7] = VAR27[7],
VAR31[6] = VAR27[6],
VAR31[5] = VAR27[5],
VAR31[4] = VAR27[4],
VAR31[3] = VAR27[3],
VAR31[2] = VAR27[2],
VAR31[1] = VAR27[1];
VAR22 \VAR24/VAR14 (
.VAR16(VAR12[7])
);
endmodule
module MODULE1 ();
parameter VAR8 = 100000;
parameter VAR13 = 0;
wire VAR29;
wire VAR34;
wire VAR10;
wire VAR5;
tri1 VAR2;
tri (weak1, strong0) VAR1 = VAR2;
wire VAR23;
wire VAR36;
reg VAR21;
reg VAR4;
reg VAR7;
wire VAR38;
wire VAR37;
wire VAR28;
wire VAR33;
wire VAR39;
reg VAR32;
reg VAR3;
reg VAR18;
reg VAR9;
reg VAR26;
reg VAR30 = 0;
reg VAR6 = 0 ;
reg VAR19 = 0;
reg VAR11 = 0;
reg VAR20 = 1'VAR25;
reg VAR15 = 1'VAR25;
reg VAR35 = 1'VAR25;
reg VAR17 = 1'VAR25;
assign (weak1, weak0) VAR29 = VAR21;
assign (weak1, weak0) VAR34 = VAR4;
assign (weak1, weak0) VAR5 = VAR7;
|
mit
|
Obijuan/open-fpga-verilog-tutorial
|
tutorial/Alhambra_II/T09-inicializador/init.v
| 1,067 |
module MODULE1(input wire clk, output VAR1);
reg VAR1 = 0;
always @(posedge(clk))
VAR1 <= 1;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/and3b/sky130_fd_sc_hd__and3b.blackbox.v
| 1,295 |
module MODULE1 (
VAR7 ,
VAR1,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR1;
input VAR4 ;
input VAR2 ;
supply1 VAR3;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.behavioral.pp.v
| 18,950 |
module MODULE1( VAR52, VAR190, VAR245, VAR197, VAR222, VAR74, VAR2, VAR68 );
input VAR197, VAR245, VAR52, VAR222, VAR190;
inout VAR2, VAR68;
output VAR74;
reg VAR289;
VAR298 VAR230(.VAR52(VAR52),.VAR190(VAR190),.VAR245(VAR245),.VAR197(VAR197),.VAR222(VAR222),.VAR74(VAR74),.VAR2(VAR2),.VAR68(VAR68),.VAR289(VAR289));
VAR298 VAR11(.VAR52(VAR52),.VAR190(VAR190),.VAR245(VAR245),.VAR197(VAR197),.VAR222(VAR222),.VAR74(VAR74),.VAR2(VAR2),.VAR68(VAR68),.VAR289(VAR289));
not VAR195(VAR88,VAR245);
not VAR214(VAR140,VAR52);
and VAR120(VAR108,VAR140,VAR88);
and VAR109(VAR310,VAR222,VAR108);
not VAR1(VAR235,VAR190);
and VAR182(VAR168,VAR235,VAR310);
not VAR137(VAR77,VAR245);
not VAR213(VAR42,VAR52);
and VAR254(VAR41,VAR42,VAR77);
and VAR278(VAR194,VAR222,VAR41);
and VAR13(VAR143,VAR190,VAR194);
not VAR171(VAR189,VAR245);
and VAR264(VAR6,VAR52,VAR189);
and VAR46(VAR297,VAR222,VAR6);
not VAR304(VAR193,VAR190);
and VAR4(VAR128,VAR193,VAR297);
not VAR30(VAR218,VAR245);
and VAR238(VAR5,VAR52,VAR218);
and VAR287(VAR208,VAR222,VAR5);
and VAR97(VAR167,VAR190,VAR208);
not VAR301(VAR252,VAR52);
and VAR85(VAR115,VAR252,VAR245);
and VAR187(VAR71,VAR222,VAR115);
not VAR35(VAR220,VAR190);
and VAR186(VAR285,VAR220,VAR71);
not VAR19(VAR299,VAR52);
and VAR248(VAR154,VAR299,VAR245);
and VAR49(VAR47,VAR222,VAR154);
and VAR86(VAR225,VAR190,VAR47);
and VAR15(VAR3,VAR52,VAR245);
and VAR23(VAR291,VAR222,VAR3);
not VAR217(VAR267,VAR190);
and VAR56(VAR184,VAR267,VAR291);
and VAR37(VAR282,VAR52,VAR245);
and VAR129(VAR94,VAR222,VAR282);
and VAR89(VAR175,VAR190,VAR94);
not VAR286(VAR100,VAR52);
and VAR203(VAR283,VAR222,VAR100);
not VAR177(VAR24,VAR190);
and VAR76(VAR44,VAR24,VAR283);
not VAR253(VAR79,VAR52);
and VAR274(VAR261,VAR222,VAR79);
and VAR232(VAR215,VAR190,VAR261);
not VAR27(VAR40,VAR245);
and VAR91(VAR250,VAR222,VAR40);
and VAR219(VAR57,VAR190,VAR250);
and VAR242(VAR227,VAR222,VAR245);
not VAR311(VAR295,VAR190);
and VAR110(VAR118,VAR295,VAR227);
not VAR132(VAR270,VAR245);
not VAR241(VAR288,VAR52);
and VAR229(VAR59,VAR288,VAR270);
not VAR70(VAR126,VAR190);
and VAR39(VAR185,VAR126,VAR59);
not VAR266(VAR104,VAR245);
not VAR303(VAR69,VAR52);
and VAR62(VAR251,VAR69,VAR104);
and VAR153(VAR169,VAR190,VAR251);
not VAR113(VAR43,VAR245);
and VAR122(VAR275,VAR52,VAR43);
not VAR66(VAR300,VAR190);
and VAR204(VAR101,VAR300,VAR275);
and VAR14(VAR164,VAR52,VAR245);
not VAR290(VAR176,VAR190);
and VAR276(VAR22,VAR176,VAR164);
not VAR202(VAR209,VAR197);
not VAR152(VAR166,VAR245);
and VAR271(VAR12,VAR166,VAR209);
not VAR51(VAR192,VAR52);
and VAR83(VAR125,VAR192,VAR12);
not VAR151(VAR224,VAR190);
and VAR243(VAR292,VAR224,VAR125);
not VAR201(VAR279,VAR197);
not VAR92(VAR228,VAR245);
and VAR178(VAR135,VAR228,VAR279);
not VAR183(VAR38,VAR52);
and VAR53(VAR60,VAR38,VAR135);
and VAR119(VAR199,VAR190,VAR60);
not VAR139(VAR45,VAR197);
not VAR148(VAR234,VAR245);
and VAR259(VAR10,VAR234,VAR45);
and VAR136(VAR75,VAR52,VAR10);
not VAR9(VAR123,VAR190);
and VAR131(VAR307,VAR123,VAR75);
not VAR134(VAR121,VAR197);
not VAR117(VAR87,VAR245);
and VAR72(VAR99,VAR87,VAR121);
and VAR81(VAR223,VAR52,VAR99);
and VAR306(VAR293,VAR190,VAR223);
not VAR211(VAR96,VAR197);
and VAR16(VAR226,VAR245,VAR96);
not VAR17(VAR20,VAR52);
and VAR64(VAR73,VAR20,VAR226);
not VAR155(VAR26,VAR190);
and VAR239(VAR8,VAR26,VAR73);
not VAR161(VAR112,VAR197);
and VAR95(VAR206,VAR245,VAR112);
not VAR173(VAR210,VAR52);
and VAR103(VAR31,VAR210,VAR206);
and VAR170(VAR141,VAR190,VAR31);
not VAR180(VAR281,VAR197);
and VAR269(VAR244,VAR245,VAR281);
and VAR67(VAR157,VAR52,VAR244);
not VAR29(VAR294,VAR190);
and VAR65(VAR212,VAR294,VAR157);
not VAR308(VAR84,VAR197);
and VAR247(VAR284,VAR245,VAR84);
and VAR165(VAR256,VAR52,VAR284);
and VAR48(VAR277,VAR190,VAR256);
not VAR172(VAR144,VAR245);
and VAR138(VAR236,VAR144,VAR197);
not VAR107(VAR296,VAR52);
and VAR255(VAR145,VAR296,VAR236);
not VAR272(VAR237,VAR190);
and VAR98(VAR61,VAR237,VAR145);
not VAR156(VAR179,VAR245);
and VAR142(VAR130,VAR179,VAR197);
not VAR105(VAR36,VAR52);
and VAR249(VAR196,VAR36,VAR130);
and VAR312(VAR162,VAR190,VAR196);
not VAR33(VAR207,VAR245);
and VAR149(VAR90,VAR207,VAR197);
and VAR257(VAR50,VAR52,VAR90);
not VAR233(VAR198,VAR190);
and VAR159(VAR163,VAR198,VAR50);
not VAR280(VAR146,VAR245);
and VAR150(VAR18,VAR146,VAR197);
and VAR7(VAR78,VAR52,VAR18);
and VAR231(VAR200,VAR190,VAR78);
and VAR80(VAR111,VAR245,VAR197);
not VAR58(VAR260,VAR52);
and VAR309(VAR127,VAR260,VAR111);
not VAR263(VAR25,VAR190);
and VAR21(VAR63,VAR25,VAR127);
and VAR160(VAR268,VAR245,VAR197);
not VAR147(VAR240,VAR52);
and VAR106(VAR158,VAR240,VAR268);
and VAR32(VAR191,VAR190,VAR158);
and VAR116(VAR246,VAR245,VAR197);
and VAR28(VAR205,VAR52,VAR246);
not VAR188(VAR216,VAR190);
and VAR302(VAR273,VAR216,VAR205);
and VAR174(VAR181,VAR245,VAR197);
and VAR265(VAR34,VAR52,VAR181);
and VAR102(VAR133,VAR190,VAR34);
not VAR93(VAR262,VAR245);
and VAR55(VAR54,VAR52,VAR262);
and VAR82(VAR221,VAR222,VAR54);
and VAR124(VAR305,VAR52,VAR245);
and VAR258(VAR114,VAR222,VAR305);
|
apache-2.0
|
asicguy/gplgpu
|
hdl/altera_ddr3_128/alt_mem_ddrx_addr_cmd_wrap.v
| 50,200 |
module MODULE1
VAR109 = 2,
VAR81 = 2, VAR194 = 16, VAR180 = 16, VAR182 = 12, VAR132 = 3, VAR35 = 1,
VAR123 = 3,
VAR136 = 2,
VAR112 = 2,
VAR154 = 8,
VAR40 = 4,
VAR6 = 4,
VAR71 = 1,
VAR75 = 2,
VAR94 = 5,
VAR11 = 5,
VAR167 = 5,
VAR196 = 4,
VAR76 = 4,
VAR80 = 1
)
(
VAR3,
VAR26,
VAR193,
VAR93,
VAR124,
VAR103,
VAR22,
VAR70,
VAR173,
VAR138,
VAR171,
VAR89,
VAR153,
VAR41,
VAR74,
VAR32,
VAR44,
VAR13,
VAR159,
VAR142,
VAR18,
VAR186,
VAR158,
VAR48,
VAR106,
VAR19,
VAR135,
VAR121,
VAR63,
VAR183,
VAR149,
VAR96,
VAR36, VAR115,
VAR52,
VAR116,
VAR84,
VAR140,
VAR176,
VAR161,
VAR198,
VAR64,
VAR47,
VAR82,
VAR62,
VAR46,
VAR69
);
localparam VAR125 = 2;
input VAR3 ;
input VAR26 ;
input VAR193 ;
input [VAR123 - 1 : 0] VAR93 ;
input [VAR11 - 1 : 0] VAR124 ;
input [VAR94 - 1 : 0] VAR103 ;
input [VAR167 - 1 : 0] VAR22 ;
input [VAR196 - 1 : 0] VAR70 ;
input [VAR76 - 1 : 0] VAR173 ;
input [4:0] VAR138 ;
input [VAR80 - 1 : 0] VAR171;
input [VAR112 - 1 : 0] VAR89 ;
input [VAR112 - 1 : 0] VAR153 ;
input [VAR112 - 1 : 0] VAR41 ;
input [VAR112 - 1 : 0] VAR74 ;
input [VAR112 - 1 : 0] VAR32 ;
input [VAR112 - 1 : 0] VAR48 ;
input [VAR112 - 1 : 0] VAR106 ;
input [VAR112 - 1 : 0] VAR44 ;
input [VAR112 - 1 : 0] VAR13 ;
input [(VAR112 * VAR109) - 1 : 0] VAR159 ;
input [(VAR112 * VAR109) - 1 : 0] VAR142 ;
input [(VAR112 * VAR109) - 1 : 0] VAR18 ;
input [(VAR112 * VAR109) - 1 : 0] VAR186 ;
input [(VAR112 * VAR109) - 1 : 0] VAR158 ;
input [(VAR112 * VAR109) - 1 : 0] VAR121 ;
input [VAR112 - 1 : 0] VAR63 ;
input [(VAR112 * VAR109) - 1 : 0] VAR36 ;
input [(VAR112 * VAR132) - 1 : 0] VAR115 ;
input [(VAR112 * VAR180) - 1 : 0] VAR52 ;
input [(VAR112 * VAR182) - 1 : 0] VAR116 ;
input VAR19 ;
input VAR135 ;
input [7:0] VAR84 ;
input [VAR154 - 1 : 0] VAR183 ;
input [VAR40 - 1 : 0] VAR149 ;
input [VAR6 - 1 : 0] VAR96 ;
input [VAR194-1:0] VAR140 ;
output [(VAR81 * (VAR136/2)) - 1:0] VAR176 ;
output [(VAR109 * (VAR136/2)) - 1:0] VAR161 ;
output [(VAR136/2) - 1:0] VAR198 ;
output [(VAR136/2) - 1:0] VAR64 ;
output [(VAR136/2) - 1:0] VAR47 ;
output [(VAR132 * (VAR136/2)) - 1:0] VAR82 ;
output [(VAR194 * (VAR136/2)) - 1:0] VAR62 ;
output [(VAR136/2) - 1:0] VAR46 ;
output [(VAR75 * (VAR136/2)) - 1:0] VAR69 ;
reg [(VAR81 * (VAR136/2)) - 1:0] VAR176 ;
reg [(VAR109 * (VAR136/2)) - 1:0] VAR161 ;
reg [(VAR136/2) - 1:0] VAR198 ;
reg [(VAR136/2) - 1:0] VAR64 ;
reg [(VAR136/2) - 1:0] VAR47 ;
reg [(VAR132 * (VAR136/2)) - 1:0] VAR82 ;
reg [(VAR194 * (VAR136/2)) - 1:0] VAR62 ;
reg [(VAR136/2) - 1:0] VAR46 ;
reg [(VAR75 * (VAR136/2)) - 1:0] VAR69 ;
reg [(VAR136/2) - 1:0] VAR181 ;
reg [(VAR136/2) - 1:0] VAR25 ;
wire [VAR81- 1:0] VAR79 [(VAR136/2)-1:0];
wire [VAR109- 1:0] VAR160 [(VAR136/2)-1:0];
wire VAR190 [(VAR136/2)-1:0];
wire VAR83 [(VAR136/2)-1:0];
wire VAR10 [(VAR136/2)-1:0];
wire [VAR132 - 1:0] VAR15 [(VAR136/2)-1:0];
wire [VAR194:0] VAR68 [(VAR136/2)-1:0];
wire VAR37 [(VAR136/2)-1:0];
wire VAR91 [(VAR136/2)-1:0];
wire VAR8 [(VAR136/2)-1:0];
reg [(VAR81 * (VAR125/2)) - 1:0] VAR187 [VAR112-1:0];
reg [(VAR109 * (VAR125/2)) - 1:0] VAR23 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR122 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR14 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR49 [VAR112-1:0];
reg [(VAR132 * (VAR125/2)) - 1:0] VAR97 [VAR112-1:0];
reg [(VAR194 * (VAR125/2)) - 1:0] VAR90 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR117 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR156 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR29 [VAR112-1:0];
wire [(VAR81 * (VAR125/2)) - 1:0] VAR98 [VAR112-1:0];
wire [(VAR109 * (VAR125/2)) - 1:0] VAR31 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR56 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR38 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR43 [VAR112-1:0];
wire [(VAR132 * (VAR125/2)) - 1:0] VAR188 [VAR112-1:0];
wire [(VAR194 * (VAR125/2)) - 1:0] VAR185 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR77 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR139 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR152 [VAR112-1:0];
wire [(VAR81 * (VAR125/2)) - 1:0] VAR107 [VAR112-1:0];
wire [(VAR109 * (VAR125/2)) - 1:0] VAR177 [VAR112-1:0];
wire [(VAR194 * (VAR125/2)) - 1:0] VAR184 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR199 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR175 [VAR112-1:0];
reg [(VAR125/2) - 1:0] VAR197 [VAR112-1:0];
wire [(VAR81 * (VAR125/2)) - 1:0] VAR21 [VAR112-1:0];
wire [(VAR109 * (VAR125/2)) - 1:0] VAR53 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR33 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR118 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR164 [VAR112-1:0];
wire [(VAR132 * (VAR125/2)) - 1:0] VAR24 [VAR112-1:0];
wire [(VAR194 * (VAR125/2)) - 1:0] VAR163 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR42 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR146 [VAR112-1:0];
wire [(VAR125/2) - 1:0] VAR102 [VAR112-1:0];
wire [(VAR81 * (VAR125/2)) - 1:0] VAR148 ;
wire [(VAR109 * (VAR125/2)) - 1:0] VAR143 ;
wire [(VAR125/2) - 1:0] VAR126 ;
wire [(VAR125/2) - 1:0] VAR111 ;
wire [(VAR125/2) - 1:0] VAR172 ;
wire [(VAR132 * (VAR125/2)) - 1:0] VAR170 ;
wire [(VAR194 * (VAR125/2)) - 1:0] VAR144 ;
wire [(VAR125/2) - 1:0] VAR133 ;
wire [(VAR125/2) - 1:0] VAR120 ;
wire [(VAR125/2) - 1:0] VAR86 ;
wire [(VAR81 * (VAR136/2)) - 1:0] VAR88;
wire [(VAR109 * (VAR136/2)) - 1:0] VAR129;
wire [(VAR136/2) - 1:0] VAR201;
wire [(VAR136/2) - 1:0] VAR128;
wire [(VAR136/2) - 1:0] VAR57;
wire [(VAR132 * (VAR136/2)) - 1:0] VAR30;
wire [(VAR194 * (VAR136/2)) - 1:0] VAR137;
wire [(VAR136/2) - 1:0] VAR16;
reg [VAR112 - 1 : 0] VAR157 ;
reg [VAR112 - 1 : 0] VAR5 ;
reg [VAR112 - 1 : 0] VAR20 ;
reg [VAR112 - 1 : 0] VAR60 ;
reg [VAR112 - 1 : 0] VAR28 ;
reg [VAR112 - 1 : 0] VAR113 ;
reg [VAR112 - 1 : 0] VAR150 ;
reg [VAR112 - 1 : 0] VAR147 ;
reg [VAR112 - 1 : 0] VAR145 ;
reg [VAR112 - 1 : 0] VAR105 ;
reg [VAR112 - 1 : 0] VAR192 ;
reg [VAR109 - 1 : 0] VAR202 [VAR112-1:0];
reg [VAR109 - 1 : 0] VAR39 [VAR112-1:0];
reg [VAR109 - 1 : 0] VAR51 [VAR112-1:0];
reg [VAR109 - 1 : 0] VAR108 [VAR112-1:0];
reg [VAR109 - 1 : 0] VAR151 [VAR112-1:0];
reg [VAR109 - 1 : 0] VAR4 [VAR112-1:0];
reg [VAR112 - 1 : 0] VAR54 ;
reg [VAR109 -1:0] VAR203 [VAR112-1:0];
reg [VAR132 -1:0] VAR34 [VAR112-1:0];
reg [VAR180 -1:0] VAR7 [VAR112-1:0];
reg [VAR182 -1:0] VAR85 [VAR112-1:0];
reg [VAR154 - 1 : 0] VAR168;
reg [VAR40 - 1 : 0] VAR99;
reg [VAR6 - 1 : 0] VAR72;
reg VAR104;
reg VAR200;
wire [(VAR75*(VAR136/2)) - 1 : 0] VAR101 [VAR112-1:0];
wire [(VAR75*(VAR136/2)) - 1 : 0] VAR165 [VAR112-1:0];
reg [VAR112 - 1 : 0] VAR61;
reg [(VAR112 * VAR109) - 1 : 0] VAR92;
reg [(VAR112 * VAR109) - 1 : 0] VAR191;
wire VAR100 = 1'b1;
wire VAR195 = 1'b0;
genvar VAR12, VAR59;
generate
for (VAR59 = 0; VAR59 < (VAR136/2); VAR59 = VAR59 + 1'b1)
begin : VAR189
always @
begin
VAR157 [VAR9] = VAR89 [VAR9];
VAR5 [VAR9] = VAR153 [VAR9];
VAR20 [VAR9] = VAR41 [VAR9];
VAR60 [VAR9] = VAR74 [VAR9];
VAR28 [VAR9] = VAR32 [VAR9];
VAR113 [VAR9] = VAR48 [VAR9];
VAR150 [VAR9] = VAR106 [VAR9];
VAR147 [VAR9] = VAR44 [VAR9];
VAR145 [VAR9] = VAR13 [VAR9];
VAR203 [VAR9] = VAR36 [(((VAR9+1)*VAR109 )-1):(VAR9*VAR109 )];
VAR34 [VAR9] = VAR115 [(((VAR9+1)*VAR132 )-1):(VAR9*VAR132 )];
VAR7 [VAR9] = VAR52 [(((VAR9+1)*VAR180)-1):(VAR9*VAR180)];
VAR85 [VAR9] = VAR116 [(((VAR9+1)*VAR182)-1):(VAR9*VAR182)];
end
if (VAR136 == 2) begin
always @
begin
VAR61 [VAR9] = VAR100;
end
end
else begin
always @
begin
VAR61 [VAR9] = ((VAR9 % VAR112) == 1) ? VAR100 : VAR195;
end
end
VAR65 # (
.VAR123 ( VAR123 ),
.VAR80 ( VAR80 ),
.VAR109 ( VAR109 ),
.VAR81 ( VAR81 ),
.VAR194 ( VAR194 ),
.VAR180 ( VAR180 ),
.VAR182 ( VAR182 ),
.VAR132 ( VAR132 ),
.VAR136 ( VAR125 )
) VAR50 (
.VAR3 ( VAR3 ),
.VAR26 ( VAR26 ),
.VAR193 ( VAR193 ),
.VAR93 ( VAR93 ),
.VAR55 ( VAR171 ),
.VAR61 ( VAR61 [VAR9] ),
.VAR89 ( VAR157 [VAR9] ),
.VAR153 ( VAR5 [VAR9] ),
.VAR32 ( VAR28 [VAR9] ),
.VAR41 ( VAR20 [VAR9] ),
.VAR44 ( VAR147 [VAR9] ),
.VAR13 ( VAR145 [VAR9] ),
.VAR142 ( VAR39 [VAR9] ),
.VAR186 ( VAR108 [VAR9] ),
.VAR18 ( VAR51 [VAR9] ),
.VAR63 ( VAR54 [VAR9] ),
.VAR159 ( VAR202 [VAR9] ),
.VAR121 ( VAR4 [VAR9] ),
.VAR158 ( VAR151 [VAR9] ),
.VAR74 ( VAR60 [VAR9] ),
.VAR36 ( VAR203 [VAR9] ),
.VAR115 ( VAR34 [VAR9] ),
.VAR52 ( VAR7 [VAR9] ),
.VAR116 ( VAR85 [VAR9] ),
.VAR84 ( ),
.VAR140 ( VAR140 ),
.VAR176 ( VAR98 [VAR9] ),
.VAR161 ( VAR31 [VAR9] ),
.VAR198 ( VAR56 [VAR9] ),
.VAR64 ( VAR38 [VAR9] ),
.VAR47 ( VAR43 [VAR9] ),
.VAR82 ( VAR188 [VAR9] ),
.VAR62 ( VAR185 [VAR9] ),
.VAR46 ( VAR77 [VAR9] )
);
if (VAR35)
begin
VAR78 # (
.VAR80 (VAR80 ),
.VAR109 (VAR109 ),
.VAR81 (VAR81 ),
.VAR194 (VAR194 ),
.VAR180 (VAR180 ),
.VAR182 (VAR182 ),
.VAR132 (VAR132 ),
.VAR136 (VAR125 )
) VAR179 (
.VAR3 (VAR3 ),
.VAR26 (VAR26 ),
.VAR193 (VAR193 ),
.VAR55 (VAR171 ),
.VAR17 (VAR157 [VAR9] ),
.VAR174 (VAR5 [VAR9] ),
.VAR73 (VAR28 [VAR9] ),
.VAR155 (VAR147 [VAR9] ),
.VAR67 (VAR145 [VAR9] ),
.VAR45 (VAR39 [VAR9] ),
.VAR58 (VAR108 [VAR9] ),
.VAR110 (VAR51 [VAR9] ),
.VAR114 (VAR54 [VAR9] ),
.VAR169 (VAR202 [VAR9] ),
.VAR95 (VAR151 [VAR9] ),
.VAR1 (VAR60 [VAR9] ),
.VAR178 (VAR104 ),
.VAR131 (VAR200 ),
.VAR127 (VAR203 [VAR9] ),
.VAR166 (VAR34 [VAR9] ),
.VAR130 (VAR7 [VAR9] ),
.VAR66 (VAR85 [VAR9] ),
.VAR134 ( ),
.VAR140 (VAR140[7:0] ),
.VAR176 (VAR107 [VAR9] ),
.VAR161 (VAR177 [VAR9] ),
.VAR62 (VAR184 [VAR9] ),
.VAR46 (VAR199 [VAR9] )
);
end
else
begin
assign VAR107 [VAR9] = {(VAR81 * (VAR125/2)) {1'b0}};
assign VAR177 [VAR9] = {(VAR109 * (VAR125/2)) {1'b0}};
assign VAR184 [VAR9] = {(VAR194 * (VAR125/2)) {1'b0}};
assign VAR199 [VAR9] = { (VAR125/2) {1'b0}};
end
always @
begin
if (VAR171)
begin
VAR156[VAR9] = VAR105 [VAR9];
VAR29[VAR9] = VAR192 [VAR9];
end
else
begin
VAR156[VAR9] = VAR113 [VAR9];
VAR29[VAR9] = VAR150 [VAR9];
end
end
VAR141 #
(
.VAR136 (VAR136 ),
.VAR71 (VAR71 ),
.VAR109 (VAR109 ),
.VAR75 (VAR75 ),
.VAR94 (VAR94 ),
.VAR11 (VAR11 ),
.VAR167 (VAR167 ),
.VAR123 (VAR123 ),
.VAR196 (VAR196 ),
.VAR76 (VAR76 ),
.VAR80 (VAR80 )
)
VAR119
(
.VAR3 (VAR3 ),
.VAR26 (VAR26 ),
.VAR93 (VAR93 ),
.VAR124 (VAR124 ),
.VAR103 (VAR103 ),
.VAR22 (VAR22 ),
.VAR70 (VAR70 ),
.VAR173 (VAR173 ),
.VAR138 (VAR138 ),
.VAR55 (VAR171 ),
.VAR153 (VAR5 [VAR9]),
.VAR89 (VAR157 [VAR9]),
.VAR41 (VAR20 [VAR9]),
.VAR36 (VAR203 [VAR9]),
.VAR69 (VAR101 [VAR9])
);
end
always @
begin
VAR69 = VAR165 [VAR112-1];
end
assign VAR165 [0] = VAR101 [0];
genvar VAR2;
generate
for (VAR2 = 1; VAR2 < VAR112; VAR2 = VAR2 + 1)
begin : VAR27
assign VAR165 [VAR2] = VAR165 [VAR2-1] | VAR101 [VAR2];
end
endgenerate
assign VAR21 [0] = VAR187 [0];
assign VAR53 [0] = VAR23 [0];
assign VAR33 [0] = VAR122 [0];
assign VAR118 [0] = VAR14 [0];
assign VAR164 [0] = VAR49 [0];
assign VAR24 [0] = VAR97 [0];
assign VAR163 [0] = VAR90 [0];
assign VAR42 [0] = VAR117 [0];
assign VAR146 [0] = VAR156 [0];
assign VAR102 [0] = VAR29 [0];
genvar VAR87;
generate
for (VAR87 = 1; VAR87 < VAR112; VAR87 = VAR87 + 1)
begin : VAR162
assign VAR21 [VAR87] = VAR21 [(VAR87-1)] & VAR187 [VAR87];
assign VAR53 [VAR87] = VAR53 [(VAR87-1)] & VAR23 [VAR87];
assign VAR33 [VAR87] = VAR33 [(VAR87-1)] & VAR122 [VAR87];
assign VAR118 [VAR87] = VAR118 [(VAR87-1)] & VAR14 [VAR87];
assign VAR164 [VAR87] = VAR164 [(VAR87-1)] & VAR49 [VAR87];
assign VAR24 [VAR87] = VAR24 [(VAR87-1)] | VAR97 [VAR87];
assign VAR163 [VAR87] = VAR163 [(VAR87-1)] | VAR90 [VAR87];
assign VAR42 [VAR87] = VAR42 [(VAR87-1)] | VAR117 [VAR87];
assign VAR146 [VAR87] = VAR146 [(VAR87-1)] | VAR156 [VAR87];
assign VAR102 [VAR87] = VAR102 [(VAR87-1)] | VAR29 [VAR87];
end
endgenerate
assign VAR148 = VAR21 [VAR112-1];
assign VAR143 = VAR53 [VAR112-1];
assign VAR126 = VAR33 [VAR112-1];
assign VAR111 = VAR118 [VAR112-1];
assign VAR172 = VAR164 [VAR112-1];
assign VAR170 = VAR24 [VAR112-1];
assign VAR144 = VAR163 [VAR112-1];
assign VAR133 = VAR42 [VAR112-1];
assign VAR120 = VAR146 [VAR112-1];
assign VAR86 = VAR102 [VAR112-1];
always @ (posedge VAR3 or negedge VAR26)
begin
if (!VAR26)
begin
VAR92 <= 0;
VAR191 <= 0;
end
else
begin
VAR92 <= VAR18;
VAR191 <= VAR158;
end
end
endmodule
|
gpl-3.0
|
velizarefremov/MIPS
|
Part 2/Verilog Code/decoderparam.v
| 1,127 |
module MODULE1
( output reg [2**VAR7-1 : 0] VAR4,
input [VAR7-1 : 0] VAR6,
input VAR5
);
localparam VAR8 = VAR7;
integer VAR2, VAR3, VAR9;
reg [(VAR8+1)*(2**VAR8):0] VAR1;
always @(VAR6, VAR1, VAR5) begin
VAR1[VAR8*(2**VAR8)] <= VAR5;
for(VAR3=VAR8; VAR3 > 0; VAR3 = VAR3 - 1) begin
for (VAR9 = 0; VAR9 < 2**(VAR8 - VAR3); VAR9 = VAR9 + 1) begin
VAR1[(VAR3-1)*(2**VAR8) + 2*VAR9] <= !VAR6[VAR3-1] && VAR1[VAR3*(2**VAR8)+VAR9];
VAR1[(VAR3-1)*(2**VAR8) + 2*VAR9+1] <= VAR6[VAR3-1] && VAR1[VAR3*(2**VAR8)+VAR9];
end
end
for (VAR2=0; VAR2 < 2**VAR8; VAR2 = VAR2 + 1) begin
VAR4[VAR2] <= VAR1[VAR2];
end
end
endmodule
|
gpl-2.0
|
davidjabon/Verilog
|
Seven_Segment_LED_drivers/seven_segment_leds_x_4.v
| 2,090 |
module MODULE1(
input [15:0] VAR3,
input [3:0] VAR5,
input clk,
output reg [6:0] VAR6,
output reg VAR1,
output reg [3:0] VAR4
);
wire [1:0] counter;
reg [3:0] VAR7;
reg [19:0] VAR2;
assign counter = VAR2[19:18];
always @(posedge clk)
case(counter)
0: {VAR7, VAR1} = {VAR3[3:0], VAR5[0]};
1: {VAR7, VAR1} = {VAR3[7:4], VAR5[1]};
2: {VAR7, VAR1} = {VAR3[11:8], VAR5[2]};
3: {VAR7, VAR1} = {VAR3[15:12], VAR5[3]};
endcase
always @(posedge clk)
case(VAR7)
0: VAR6 = 7'b0000001;
1: VAR6 = 7'b1001111;
2: VAR6 = 7'b0010010;
3: VAR6 = 7'b0000110;
4: VAR6 = 7'b1001100;
5: VAR6 = 7'b0100100;
6: VAR6 = 7'b0100000;
7: VAR6 = 7'b0001111;
8: VAR6 = 7'b0000000;
9: VAR6 = 7'b0000100;
default: VAR6 = 7'b0000001; endcase
always @(posedge clk)
case(counter)
0: VAR4 = 4'b1110;
1: VAR4 = 4'b1101;
2: VAR4 = 4'b1011;
3: VAR4 = 4'b0111;
default: VAR4 = 4'b1111; endcase
always @ (posedge clk)
begin
VAR2 <= VAR2 + 20'b1;
end
endmodule
|
gpl-2.0
|
sabertazimi/hust-lab
|
architecture/design/fpga/src/alu.v
| 1,655 |
module MODULE1
(
input [VAR8-1:0] VAR1,
input [VAR8-1:0] VAR3,
input [3:0] VAR7,
output reg [VAR8-1:0] VAR6,
output VAR11,
output VAR5,
output VAR2
);
wire signed [VAR8-1:0] VAR10;
wire signed [VAR8-1:0] VAR9;
assign VAR10 = (VAR1);
assign VAR9 = (VAR3);
always @ ( * ) begin
case (VAR7)
4'd0: VAR6 <= VAR1 << VAR3;
4'd1: VAR6 <= VAR10 >>> VAR3;
4'd2: VAR6 <= VAR1 >> VAR3;
4'd3: VAR6 <= VAR1 * VAR3;
4'd4: VAR6 <= VAR1 / VAR3;
4'd5: VAR6 <= VAR1 + VAR3; 4'd6: VAR6 <= VAR1 - VAR3;
4'd7: VAR6 <= VAR1 & VAR3;
4'd8: VAR6 <= VAR1 | VAR3;
4'd9: VAR6 <= VAR1 ^ VAR3;
4'd10: VAR6 <= ~(VAR1 | VAR3);
4'd11: VAR6 <= (VAR10 < VAR9) ? 1 : 0;
4'd12: VAR6 <= (VAR1 < VAR3) ? 1 : 0;
default: VAR6 <= 0;
endcase
end
VAR4 #(
.VAR8(VAR8)
) VAR12 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
|
mit
|
AmeerAbdelhadi/Switched-Multiported-RAM
|
smpram.v
| 11,221 |
module MODULE1
localparam VAR7 = VAR34+VAR8 ; localparam VAR11 = VAR15+VAR40 ; localparam VAR41 = VAR5(VAR30);
localparam VAR26 = VAR5(VAR7) ;
localparam VAR4 = VAR37*(VAR7-1) ;
localparam VAR44 = VAR26*(VAR7+VAR11-1);
localparam VAR14 = (VAR7-1)*(VAR11+1) ;
localparam VAR21 = (VAR30<=1024 ) ? "VAR13" :
( (VAR30<=2048 ) ? "VAR10" :
( ((VAR8==0)&(VAR4<VAR14)&(VAR4<VAR44)) ? "VAR23" :
( (VAR14<=VAR44 ) ? "VAR28" : "VAR19" )));
localparam VAR20 = ((VAR9!="VAR13")&&(VAR9!="VAR23")&&(VAR9!="VAR10")&&(VAR9!="VAR19")&&(VAR9!="VAR28")) ? VAR21 : VAR9;
localparam VAR46 = VAR1!="VAR32" ; localparam VAR36 = (VAR1=="VAR22")||(VAR1=="VAR27"); localparam VAR2 = VAR1=="VAR27" ;
generate
if (VAR7==1) begin
VAR24 #( .VAR30 (VAR30 ), .VAR37 (VAR37 ), .VAR42 (VAR11 ), .VAR1 (VAR2?2:VAR36), .VAR31 (VAR31 )) VAR6 ( .clk (clk ), .VAR39 (VAR39 ), .VAR29 (VAR29 ), .VAR45 (VAR45 ), .VAR47 (VAR47 ), .VAR16 (VAR16 )); end
else if (VAR20=="VAR13" ) begin
VAR43 #( .VAR30 (VAR30 ), .VAR37 (VAR37 ), .VAR42 (VAR11 ), .VAR33 (VAR7 ), .VAR2 (VAR2 ), .VAR31 (VAR31 )) VAR35 ( .clk (clk ), .VAR39 (VAR39 ), .VAR29 (VAR29), .VAR45 (VAR45), .VAR47 (VAR47), .VAR16 (VAR16)); end
else if (VAR20=="VAR23" ) begin
VAR12 #( .VAR30 (VAR30 ), .VAR37 (VAR37 ), .VAR42 (VAR11 ), .VAR33 (VAR7 ), .VAR46 (VAR46 ), .VAR36 (VAR36 ), .VAR2 (VAR2 ), .VAR31 (VAR31 )) VAR3 ( .clk (clk ), .VAR39 (VAR39 ), .VAR29 (VAR29), .VAR45 (VAR45), .VAR47 (VAR47), .VAR16 (VAR16)); end
else begin
VAR17 #( .VAR30 (VAR30 ), .VAR37 (VAR37 ), .VAR15 (VAR15 ), .VAR34 (VAR34 ), .VAR40 (VAR40 ), .VAR8 (VAR8 ), .VAR25 (VAR20), .VAR46 (VAR46 ), .VAR36 (VAR36 ), .VAR2 (VAR2 ), .VAR31 (VAR31 )) VAR18 ( .clk (clk ), .VAR38 (VAR38 ), .VAR39 (VAR39 ), .VAR29 (VAR29), .VAR45 (VAR45), .VAR47 (VAR47), .VAR16 (VAR16)); end
endgenerate
endmodule
|
bsd-3-clause
|
secworks/sha256
|
src/rtl/sha256_w_mem.v
| 8,495 |
module MODULE1(
input wire clk,
input wire VAR32,
input wire [511 : 0] VAR39,
input wire VAR30,
input wire VAR13,
output wire [31 : 0] VAR22
);
reg [31 : 0] VAR37 [0 : 15];
reg [31 : 0] VAR11;
reg [31 : 0] VAR5;
reg [31 : 0] VAR34;
reg [31 : 0] VAR16;
reg [31 : 0] VAR10;
reg [31 : 0] VAR19;
reg [31 : 0] VAR4;
reg [31 : 0] VAR3;
reg [31 : 0] VAR33;
reg [31 : 0] VAR21;
reg [31 : 0] VAR17;
reg [31 : 0] VAR29;
reg [31 : 0] VAR23;
reg [31 : 0] VAR20;
reg [31 : 0] VAR15;
reg [31 : 0] VAR1;
reg VAR24;
reg [5 : 0] VAR27;
reg [5 : 0] VAR36;
reg VAR12;
reg [31 : 0] VAR2;
reg [31 : 0] VAR6;
assign VAR22 = VAR2;
always @ (posedge clk or negedge VAR32)
begin : VAR38
integer VAR31;
if (!VAR32)
begin
for (VAR31 = 0 ; VAR31 < 16 ; VAR31 = VAR31 + 1)
VAR37[VAR31] <= 32'h0;
VAR27 <= 6'h0;
end
else
begin
if (VAR24)
begin
VAR37[00] <= VAR11;
VAR37[01] <= VAR5;
VAR37[02] <= VAR34;
VAR37[03] <= VAR16;
VAR37[04] <= VAR10;
VAR37[05] <= VAR19;
VAR37[06] <= VAR4;
VAR37[07] <= VAR3;
VAR37[08] <= VAR33;
VAR37[09] <= VAR21;
VAR37[10] <= VAR17;
VAR37[11] <= VAR29;
VAR37[12] <= VAR23;
VAR37[13] <= VAR20;
VAR37[14] <= VAR15;
VAR37[15] <= VAR1;
end
if (VAR12)
VAR27 <= VAR36;
end
end
always @*
begin : VAR26
if (VAR27 < 16)
VAR2 = VAR37[VAR27[3 : 0]];
end
else
VAR2 = VAR6;
end
always @*
begin : VAR35
reg [31 : 0] VAR28;
reg [31 : 0] VAR14;
reg [31 : 0] VAR18;
reg [31 : 0] VAR9;
reg [31 : 0] VAR7;
reg [31 : 0] VAR25;
VAR11 = 32'h0;
VAR5 = 32'h0;
VAR34 = 32'h0;
VAR16 = 32'h0;
VAR10 = 32'h0;
VAR19 = 32'h0;
VAR4 = 32'h0;
VAR3 = 32'h0;
VAR33 = 32'h0;
VAR21 = 32'h0;
VAR17 = 32'h0;
VAR29 = 32'h0;
VAR23 = 32'h0;
VAR20 = 32'h0;
VAR15 = 32'h0;
VAR1 = 32'h0;
VAR24 = 0;
VAR28 = VAR37[0];
VAR14 = VAR37[1];
VAR18 = VAR37[9];
VAR9 = VAR37[14];
VAR7 = {VAR14[6 : 0], VAR14[31 : 7]} ^
{VAR14[17 : 0], VAR14[31 : 18]} ^
{3'b000, VAR14[31 : 3]};
VAR25 = {VAR9[16 : 0], VAR9[31 : 17]} ^
{VAR9[18 : 0], VAR9[31 : 19]} ^
{10'b0000000000, VAR9[31 : 10]};
VAR6 = VAR25 + VAR18 + VAR7 + VAR28;
if (VAR30)
begin
VAR11 = VAR39[511 : 480];
VAR5 = VAR39[479 : 448];
VAR34 = VAR39[447 : 416];
VAR16 = VAR39[415 : 384];
VAR10 = VAR39[383 : 352];
VAR19 = VAR39[351 : 320];
VAR4 = VAR39[319 : 288];
VAR3 = VAR39[287 : 256];
VAR33 = VAR39[255 : 224];
VAR21 = VAR39[223 : 192];
VAR17 = VAR39[191 : 160];
VAR29 = VAR39[159 : 128];
VAR23 = VAR39[127 : 96];
VAR20 = VAR39[95 : 64];
VAR15 = VAR39[63 : 32];
VAR1 = VAR39[31 : 0];
VAR24 = 1;
end
if (VAR13 && (VAR27 > 15))
begin
VAR11 = VAR37[01];
VAR5 = VAR37[02];
VAR34 = VAR37[03];
VAR16 = VAR37[04];
VAR10 = VAR37[05];
VAR19 = VAR37[06];
VAR4 = VAR37[07];
VAR3 = VAR37[08];
VAR33 = VAR37[09];
VAR21 = VAR37[10];
VAR17 = VAR37[11];
VAR29 = VAR37[12];
VAR23 = VAR37[13];
VAR20 = VAR37[14];
VAR15 = VAR37[15];
VAR1 = VAR6;
VAR24 = 1;
end
end
always @*
begin : VAR8
VAR36 = 6'h0;
VAR12 = 1'h0;
if (VAR30)
begin
VAR36 = 6'h0;
VAR12 = 1'h1;
end
if (VAR13)
begin
VAR36 = VAR27 + 6'h01;
VAR12 = 1'h1;
end
end endmodule
|
bsd-2-clause
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.behavioral.v
| 3,431 |
module MODULE1( VAR8, VAR3, VAR5, VAR7, VAR1, VAR6 );
input VAR5, VAR3, VAR8, VAR6, VAR1;
output VAR7;
VAR4 VAR2(.VAR8(VAR8),.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6));
VAR4 VAR9(.VAR8(VAR8),.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6));
|
apache-2.0
|
alan4186/16bit-Processor
|
main_memory.v
| 7,215 |
module MODULE1 (
address,
VAR32,
VAR48,
VAR29,
VAR15);
input [7:0] address;
input VAR32;
input [15:0] VAR48;
input VAR29;
output [15:0] VAR15;
tri1 VAR32;
wire [15:0] VAR22;
wire [15:0] VAR15 = VAR22[15:0];
VAR43 VAR38 (
.VAR12 (address),
.VAR45 (VAR32),
.VAR52 (VAR48),
.VAR18 (VAR29),
.VAR50 (VAR22),
.VAR28 (1'b0),
.VAR26 (1'b0),
.VAR10 (1'b1),
.VAR6 (1'b0),
.VAR2 (1'b0),
.VAR3 (1'b1),
.VAR7 (1'b1),
.VAR54 (1'b1),
.VAR25 (1'b1),
.VAR34 (1'b1),
.VAR16 (1'b1),
.VAR41 (1'b1),
.VAR20 (1'b1),
.VAR37 (),
.VAR49 (),
.VAR27 (1'b1),
.VAR31 (1'b1),
.VAR42 (1'b0));
VAR38.VAR13 = "VAR24",
VAR38.VAR57 = "VAR24",
VAR38.VAR39 = "VAR14.VAR11",
VAR38.VAR9 = "VAR46 VAR21 VAR51",
VAR38.VAR53 = "VAR30=VAR35",
VAR38.VAR17 = "VAR43",
VAR38.VAR56 = 256,
VAR38.VAR36 = "VAR40",
VAR38.VAR58 = "VAR5",
VAR38.VAR55 = "VAR1",
VAR38.VAR23 = "VAR44",
VAR38.VAR33 = "VAR4",
VAR38.VAR19 = 8,
VAR38.VAR8 = 16,
VAR38.VAR47 = 1;
endmodule
|
mit
|
liuyenting/CA-Project
|
src/L1_Cache_Controller_rework.v
| 4,058 |
module MODULE1 (
input clk,
input rst,
input VAR4,
input VAR10,
output VAR9,
input VAR2,
output reg VAR1,
input VAR14,
input VAR16,
output reg VAR12,
output reg VAR7,
output reg VAR6,
output reg VAR5,
input VAR17
);
reg [3:0] state;
reg [3:0] VAR3;
reg VAR11; reg VAR13;
reg VAR8;
reg VAR15;
begin
end
begin
end
begin
end
begin
begin
begin
end
begin
begin
end
begin
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o21a/sky130_fd_sc_hd__o21a_4.v
| 2,248 |
module MODULE1 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR9,
VAR7,
VAR4 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR9;
input VAR7;
input VAR4 ;
input VAR5 ;
VAR10 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR3 ,
VAR1,
VAR2,
VAR6
);
output VAR3 ;
input VAR1;
input VAR2;
input VAR6;
supply1 VAR9;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR5 ;
VAR10 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.v
| 1,992 |
module MODULE1 (
VAR4 ,
VAR2 ,
VAR1,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR1;
input VAR5;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR5;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
gbraad/minimig-de1
|
rtl/audio/audio_top.v
| 1,614 |
module MODULE1 (
input wire clk,
input wire VAR15,
input wire VAR14,
input wire [ 15-1:0] VAR19,
input wire [ 15-1:0] VAR4,
input wire VAR13,
output wire VAR11,
output wire VAR18,
output wire VAR9,
output wire VAR5,
output wire VAR7,
inout VAR1
);
VAR16 VAR16 (
.clk (clk ),
.VAR2 (VAR15 ),
.VAR14 (VAR14 ),
.VAR19 (VAR19 ),
.VAR4 (VAR4 ),
.VAR13 (VAR13 ),
.VAR11 (VAR11 ),
.VAR18 (VAR18 ),
.VAR9 (VAR9 ),
.VAR5 (VAR5 )
);
VAR17 VAR6 (
.VAR3 (clk ),
.VAR12 (VAR15 ),
.VAR10 (VAR7 ),
.VAR8 (VAR1 )
);
endmodule
|
gpl-3.0
|
vvk/sysrek
|
skin_color_segm/src/common/DRAM16XN.v
| 1,616 |
module MODULE1 #(parameter VAR1 = 20)
(
VAR13,
VAR23,
VAR2,
VAR18,
VAR10,
VAR17,
VAR7);
input [VAR1-1:0]VAR13;
input [3:0] VAR23;
input [3:0] VAR2;
input VAR18;
input VAR10;
output [VAR1-1:0]VAR7;
output [VAR1-1:0]VAR17;
genvar VAR21;
generate
for(VAR21 = 0 ; VAR21 < VAR1 ; VAR21 = VAR21 + 1) begin : VAR25
VAR12 VAR6(
.VAR3(VAR13[VAR21]), .VAR5(VAR18), .VAR24(VAR10), .VAR15(VAR23[0]), .VAR9(VAR23[1]), .VAR4(VAR23[2]), .VAR11(VAR23[3]), .VAR8(VAR2[0]), .VAR22(VAR2[1]), .VAR16(VAR2[2]), .VAR14(VAR2[3]), .VAR20(VAR17[VAR21]), .VAR19(VAR7[VAR21]) );
end
endgenerate
endmodule
|
gpl-2.0
|
YuxuanLing/trunk
|
trunk/references/h265enc_v1.0/rtl/tq/butterfly1_8.v
| 2,072 |
module MODULE1(
enable,
VAR10,
VAR3,
VAR1,
VAR12,
VAR7,
VAR11,
VAR9,
VAR8,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7
);
input enable;
input signed [17:0] VAR10;
input signed [17:0] VAR3;
input signed [17:0] VAR1;
input signed [17:0] VAR12;
input signed [17:0] VAR7;
input signed [17:0] VAR11;
input signed [17:0] VAR9;
input signed [17:0] VAR8;
output signed [18:0] o0;
output signed [18:0] o1;
output signed [18:0] o2;
output signed [18:0] o3;
output signed [18:0] o4;
output signed [18:0] o5;
output signed [18:0] o6;
output signed [18:0] o7;
wire signed [18:0] b0;
wire signed [18:0] b1;
wire signed [18:0] VAR2;
wire signed [18:0] VAR4;
wire signed [18:0] VAR14;
wire signed [18:0] VAR6;
wire signed [18:0] VAR13;
wire signed [18:0] VAR5;
assign b0=VAR10+VAR8;
assign b1=VAR3+VAR9;
assign VAR2=VAR1+VAR11;
assign VAR4=VAR12+VAR7;
assign VAR14=VAR12-VAR7;
assign VAR6=VAR1-VAR11;
assign VAR13=VAR3-VAR9;
assign VAR5=VAR10-VAR8;
assign o0=enable?b0:VAR10;
assign o1=enable?b1:VAR3;
assign o2=enable?VAR2:VAR1;
assign o3=enable?VAR4:VAR12;
assign o4=enable?VAR14:VAR7;
assign o5=enable?VAR6:VAR11;
assign o6=enable?VAR13:VAR9;
assign o7=enable?VAR5:VAR8;
endmodule
|
gpl-3.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v
| 34,794 |
module MODULE5 (
clk,
reset,
VAR131,
VAR9,
VAR42,
VAR28,
VAR149
);
parameter VAR241 = 18;
parameter VAR261 = 50;
parameter VAR132 = 25;
localparam VAR146 = 57;
input clk;
input reset;
input VAR131;
input VAR9;
input [VAR241-1:0] VAR42; output VAR28;
output [VAR241-1:0] VAR149;
localparam VAR95 = 18; localparam VAR119 = 36; localparam VAR129 = 17;
localparam VAR290 = 50;
reg [VAR241-1:0] VAR6;
reg [VAR241-1:0] VAR58;
reg [VAR241-1:0] VAR56;
reg [VAR241-1:0] VAR213;
reg [VAR241-1:0] VAR221;
reg [VAR241-1:0] VAR292;
reg [VAR241-1:0] VAR206;
reg [VAR241-1:0] VAR40;
reg [VAR241-1:0] VAR8;
reg [VAR241-1:0] VAR32;
reg [VAR241-1:0] VAR203;
reg [VAR241-1:0] VAR244;
reg [VAR241-1:0] VAR259;
reg [VAR241-1:0] VAR31;
reg [VAR241-1:0] VAR139;
reg [VAR241-1:0] VAR294;
reg [VAR241-1:0] VAR209;
reg [VAR241-1:0] VAR256;
reg [VAR241-1:0] VAR91;
reg [VAR241-1:0] VAR143;
reg [VAR241-1:0] VAR198;
reg [VAR241-1:0] VAR202;
reg [VAR241-1:0] VAR215;
reg [VAR241-1:0] VAR85;
reg [VAR241-1:0] VAR217;
always@(posedge clk) begin
VAR6 <= 18'd88;
VAR58 <= 18'd0;
VAR56 <= -18'd97;
VAR213 <= -18'd197;
VAR221 <= -18'd294;
VAR292 <= -18'd380;
VAR206 <= -18'd447;
VAR40 <= -18'd490;
VAR8 <= -18'd504;
VAR32 <= -18'd481;
VAR203 <= -18'd420;
VAR244 <= -18'd319;
VAR259 <= -18'd178;
VAR31 <= 18'd0;
VAR139 <= 18'd212;
VAR294 <= 18'd451;
VAR209 <= 18'd710;
VAR256 <= 18'd980;
VAR91 <= 18'd1252;
VAR143 <= 18'd1514;
VAR198 <= 18'd1756;
VAR202 <= 18'd1971;
VAR215 <= 18'd2147;
VAR85 <= 18'd2278;
VAR217 <= 18'd2360;
end
reg [VAR146-1:0] VAR162;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR162 <= 0;
end else begin
if(VAR131) begin
VAR162 <= {VAR162[VAR146-2:0], VAR9};
end else begin
VAR162 <= VAR162;
end
end
end
wire [VAR241-1:0] VAR251;
wire [VAR241-1:0] VAR262;
wire [VAR241-1:0] VAR181;
wire [VAR241-1:0] VAR13;
wire [VAR241-1:0] VAR279;
wire [VAR241-1:0] VAR113;
wire [VAR241-1:0] VAR126;
wire [VAR241-1:0] VAR130;
wire [VAR241-1:0] VAR267;
wire [VAR241-1:0] VAR178;
wire [VAR241-1:0] VAR99;
wire [VAR241-1:0] VAR61;
wire [VAR241-1:0] VAR29;
wire [VAR241-1:0] VAR50;
wire [VAR241-1:0] VAR266;
wire [VAR241-1:0] VAR86;
wire [VAR241-1:0] VAR185;
wire [VAR241-1:0] VAR64;
wire [VAR241-1:0] VAR33;
wire [VAR241-1:0] VAR226;
wire [VAR241-1:0] VAR4;
wire [VAR241-1:0] VAR97;
wire [VAR241-1:0] VAR82;
wire [VAR241-1:0] VAR68;
wire [VAR241-1:0] VAR228;
wire [VAR241-1:0] VAR16;
wire [VAR241-1:0] VAR22;
wire [VAR241-1:0] VAR121;
wire [VAR241-1:0] VAR87;
wire [VAR241-1:0] VAR25;
wire [VAR241-1:0] VAR231;
wire [VAR241-1:0] VAR27;
wire [VAR241-1:0] VAR170;
wire [VAR241-1:0] VAR158;
wire [VAR241-1:0] VAR192;
wire [VAR241-1:0] VAR12;
wire [VAR241-1:0] VAR75;
wire [VAR241-1:0] VAR171;
wire [VAR241-1:0] VAR89;
wire [VAR241-1:0] VAR271;
wire [VAR241-1:0] VAR54;
wire [VAR241-1:0] VAR20;
wire [VAR241-1:0] VAR14;
wire [VAR241-1:0] VAR142;
wire [VAR241-1:0] VAR48;
wire [VAR241-1:0] VAR34;
wire [VAR241-1:0] VAR283;
wire [VAR241-1:0] VAR135;
wire [VAR241-1:0] VAR285;
wire [VAR241-1:0] VAR291;
MODULE4 MODULE24(
.clk(clk), .VAR131(VAR131),
.VAR287(VAR42),
.VAR163(VAR251),
.VAR296(VAR262),
.VAR96(VAR181),
.VAR214(VAR13),
.VAR167(VAR279),
.VAR57(VAR113),
.VAR233(VAR126),
.VAR208(VAR130),
.VAR227(VAR267),
.VAR169(VAR178),
.VAR153(VAR99),
.VAR258(VAR61),
.VAR172(VAR29),
.VAR39(VAR50),
.VAR10(VAR266),
.VAR298(VAR86),
.VAR53(VAR185),
.VAR44(VAR64),
.VAR278(VAR33),
.VAR250(VAR226),
.VAR2(VAR4),
.VAR30(VAR97),
.VAR273(VAR82),
.VAR125(VAR68),
.VAR110(VAR228),
.VAR74(VAR16),
.VAR224(VAR22),
.VAR263(VAR121),
.VAR147(VAR87),
.VAR237(VAR25),
.VAR281(VAR231),
.VAR7(VAR27),
.VAR152(VAR170),
.VAR282(VAR158),
.VAR156(VAR192),
.VAR80(VAR12),
.VAR218(VAR75),
.VAR19(VAR171),
.VAR225(VAR89),
.VAR47(VAR271),
.VAR67(VAR54),
.VAR136(VAR20),
.VAR253(VAR14),
.VAR78(VAR142),
.VAR65(VAR48),
.VAR77(VAR34),
.VAR62(VAR283),
.VAR293(VAR135),
.VAR245(VAR285),
.VAR157(VAR291),
.reset(reset) );
wire [VAR241-1:0] VAR289;
wire [VAR241-1:0] VAR255;
wire [VAR241-1:0] VAR46;
wire [VAR241-1:0] VAR104;
wire [VAR241-1:0] VAR90;
wire [VAR241-1:0] VAR93;
wire [VAR241-1:0] VAR117;
wire [VAR241-1:0] VAR247;
wire [VAR241-1:0] VAR72;
wire [VAR241-1:0] VAR17;
wire [VAR241-1:0] VAR183;
wire [VAR241-1:0] VAR260;
wire [VAR241-1:0] VAR190;
wire [VAR241-1:0] VAR100;
wire [VAR241-1:0] VAR195;
wire [VAR241-1:0] VAR49;
wire [VAR241-1:0] VAR229;
wire [VAR241-1:0] VAR277;
wire [VAR241-1:0] VAR159;
wire [VAR241-1:0] VAR254;
wire [VAR241-1:0] VAR106;
wire [VAR241-1:0] VAR201;
wire [VAR241-1:0] VAR45;
wire [VAR241-1:0] VAR188;
wire [VAR241-1:0] VAR123;
MODULE3 VAR18(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR251),
.VAR161 (VAR291),
.VAR70(VAR289)
);
MODULE3 VAR168(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR262),
.VAR161 (VAR285),
.VAR70(VAR255)
);
MODULE3 VAR182(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR181),
.VAR161 (VAR135),
.VAR70(VAR46)
);
MODULE3 VAR83(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR13),
.VAR161 (VAR283),
.VAR70(VAR104)
);
MODULE3 VAR36(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR279),
.VAR161 (VAR34),
.VAR70(VAR90)
);
MODULE3 VAR11(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR113),
.VAR161 (VAR48),
.VAR70(VAR93)
);
MODULE3 VAR197(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR126),
.VAR161 (VAR142),
.VAR70(VAR117)
);
MODULE3 VAR268(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR130),
.VAR161 (VAR14),
.VAR70(VAR247)
);
MODULE3 VAR175(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR267),
.VAR161 (VAR20),
.VAR70(VAR72)
);
MODULE3 VAR234(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR178),
.VAR161 (VAR54),
.VAR70(VAR17)
);
MODULE3 VAR239(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR99),
.VAR161 (VAR271),
.VAR70(VAR183)
);
MODULE3 VAR51(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR61),
.VAR161 (VAR89),
.VAR70(VAR260)
);
MODULE3 VAR69(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR29),
.VAR161 (VAR171),
.VAR70(VAR190)
);
MODULE3 VAR280(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR50),
.VAR161 (VAR75),
.VAR70(VAR100)
);
MODULE3 VAR55(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR266),
.VAR161 (VAR12),
.VAR70(VAR195)
);
MODULE3 VAR210(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR86),
.VAR161 (VAR192),
.VAR70(VAR49)
);
MODULE3 VAR248(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR185),
.VAR161 (VAR158),
.VAR70(VAR229)
);
MODULE3 VAR199(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR64),
.VAR161 (VAR170),
.VAR70(VAR277)
);
MODULE3 VAR98(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR33),
.VAR161 (VAR27),
.VAR70(VAR159)
);
MODULE3 VAR102(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR226),
.VAR161 (VAR231),
.VAR70(VAR254)
);
MODULE3 VAR216(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR4),
.VAR161 (VAR25),
.VAR70(VAR106)
);
MODULE3 VAR196(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR97),
.VAR161 (VAR87),
.VAR70(VAR201)
);
MODULE3 VAR212(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR82),
.VAR161 (VAR121),
.VAR70(VAR45)
);
MODULE3 VAR176(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR68),
.VAR161 (VAR22),
.VAR70(VAR188)
);
MODULE3 VAR236(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR228),
.VAR161 (VAR16),
.VAR70(VAR123)
);
wire [VAR241-1:0] VAR191;
wire [VAR241-1:0] VAR269;
wire [VAR241-1:0] VAR101;
wire [VAR241-1:0] VAR151;
wire [VAR241-1:0] VAR24;
wire [VAR241-1:0] VAR177;
wire [VAR241-1:0] VAR133;
wire [VAR241-1:0] VAR222;
wire [VAR241-1:0] VAR105;
wire [VAR241-1:0] VAR243;
wire [VAR241-1:0] VAR295;
wire [VAR241-1:0] VAR154;
wire [VAR241-1:0] VAR66;
wire [VAR241-1:0] VAR120;
wire [VAR241-1:0] VAR189;
wire [VAR241-1:0] VAR155;
wire [VAR241-1:0] VAR223;
wire [VAR241-1:0] VAR249;
wire [VAR241-1:0] VAR270;
wire [VAR241-1:0] VAR264;
wire [VAR241-1:0] VAR299;
wire [VAR241-1:0] VAR200;
wire [VAR241-1:0] VAR184;
wire [VAR241-1:0] VAR5;
wire [VAR241-1:0] VAR211;
MODULE2 VAR41(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR289),
.VAR161 (VAR6),
.VAR70(VAR191)
);
MODULE2 VAR284(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR255),
.VAR161 (VAR58),
.VAR70(VAR269)
);
MODULE2 VAR81(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR46),
.VAR161 (VAR56),
.VAR70(VAR101)
);
MODULE2 VAR127(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR104),
.VAR161 (VAR213),
.VAR70(VAR151)
);
MODULE2 VAR164(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR90),
.VAR161 (VAR221),
.VAR70(VAR24)
);
MODULE2 VAR114(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR93),
.VAR161 (VAR292),
.VAR70(VAR177)
);
MODULE2 VAR137(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR117),
.VAR161 (VAR206),
.VAR70(VAR133)
);
MODULE2 VAR230(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR247),
.VAR161 (VAR40),
.VAR70(VAR222)
);
MODULE2 VAR257(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR72),
.VAR161 (VAR8),
.VAR70(VAR105)
);
MODULE2 VAR272(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR17),
.VAR161 (VAR32),
.VAR70(VAR243)
);
MODULE2 VAR84(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR183),
.VAR161 (VAR203),
.VAR70(VAR295)
);
MODULE2 VAR148(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR260),
.VAR161 (VAR244),
.VAR70(VAR154)
);
MODULE2 VAR193(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR190),
.VAR161 (VAR259),
.VAR70(VAR66)
);
MODULE2 VAR116(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR100),
.VAR161 (VAR31),
.VAR70(VAR120)
);
MODULE2 VAR240(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR195),
.VAR161 (VAR139),
.VAR70(VAR189)
);
MODULE2 VAR235(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR49),
.VAR161 (VAR294),
.VAR70(VAR155)
);
MODULE2 VAR124(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR229),
.VAR161 (VAR209),
.VAR70(VAR223)
);
MODULE2 VAR252(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR277),
.VAR161 (VAR256),
.VAR70(VAR249)
);
MODULE2 VAR38(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR159),
.VAR161 (VAR91),
.VAR70(VAR270)
);
MODULE2 VAR204(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR254),
.VAR161 (VAR143),
.VAR70(VAR264)
);
MODULE2 VAR174(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR106),
.VAR161 (VAR198),
.VAR70(VAR299)
);
MODULE2 VAR297(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR201),
.VAR161 (VAR202),
.VAR70(VAR200)
);
MODULE2 VAR274(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR45),
.VAR161 (VAR215),
.VAR70(VAR184)
);
MODULE2 VAR79(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR188),
.VAR161 (VAR85),
.VAR70(VAR5)
);
MODULE2 VAR288(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR123),
.VAR161 (VAR217),
.VAR70(VAR211)
);
wire [VAR241-1:0] VAR140;
wire [VAR241-1:0] VAR122;
wire [VAR241-1:0] VAR63;
wire [VAR241-1:0] VAR144;
wire [VAR241-1:0] VAR160;
wire [VAR241-1:0] VAR150;
wire [VAR241-1:0] VAR242;
wire [VAR241-1:0] VAR276;
wire [VAR241-1:0] VAR35;
wire [VAR241-1:0] VAR26;
wire [VAR241-1:0] VAR111;
wire [VAR241-1:0] VAR186;
wire [VAR241-1:0] VAR88;
MODULE3 VAR52(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR191),
.VAR161 (VAR269),
.VAR70(VAR140)
);
MODULE3 VAR1(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR101),
.VAR161 (VAR151),
.VAR70(VAR122)
);
MODULE3 VAR109(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR24),
.VAR161 (VAR177),
.VAR70(VAR63)
);
MODULE3 VAR166(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR133),
.VAR161 (VAR222),
.VAR70(VAR144)
);
MODULE3 VAR92(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR105),
.VAR161 (VAR243),
.VAR70(VAR160)
);
MODULE3 VAR112(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR295),
.VAR161 (VAR154),
.VAR70(VAR150)
);
MODULE3 VAR173(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR66),
.VAR161 (VAR120),
.VAR70(VAR242)
);
MODULE3 VAR220(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR189),
.VAR161 (VAR155),
.VAR70(VAR276)
);
MODULE3 VAR275(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR223),
.VAR161 (VAR249),
.VAR70(VAR35)
);
MODULE3 VAR118(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR270),
.VAR161 (VAR264),
.VAR70(VAR26)
);
MODULE3 VAR103(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR299),
.VAR161 (VAR200),
.VAR70(VAR111)
);
MODULE3 VAR205(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR184),
.VAR161 (VAR5),
.VAR70(VAR186)
);
MODULE1 VAR43(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR211),
.VAR70(VAR88)
);
wire [VAR241-1:0] VAR107;
wire [VAR241-1:0] VAR194;
wire [VAR241-1:0] VAR180;
wire [VAR241-1:0] VAR134;
wire [VAR241-1:0] VAR60;
wire [VAR241-1:0] VAR21;
wire [VAR241-1:0] VAR207;
MODULE3 VAR37(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR140),
.VAR161 (VAR122),
.VAR70(VAR107)
);
MODULE3 VAR115(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR63),
.VAR161 (VAR144),
.VAR70(VAR194)
);
MODULE3 VAR23(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR160),
.VAR161 (VAR150),
.VAR70(VAR180)
);
MODULE3 VAR15(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR242),
.VAR161 (VAR276),
.VAR70(VAR134)
);
MODULE3 VAR108(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR35),
.VAR161 (VAR26),
.VAR70(VAR60)
);
MODULE3 VAR286(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR111),
.VAR161 (VAR186),
.VAR70(VAR21)
);
MODULE1 VAR71(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR88),
.VAR70(VAR207)
);
wire [VAR241-1:0] VAR165;
wire [VAR241-1:0] VAR145;
wire [VAR241-1:0] VAR128;
wire [VAR241-1:0] VAR246;
MODULE3 VAR187(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR107),
.VAR161 (VAR194),
.VAR70(VAR165)
);
MODULE3 VAR73(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR180),
.VAR161 (VAR134),
.VAR70(VAR145)
);
MODULE3 VAR238(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR60),
.VAR161 (VAR21),
.VAR70(VAR128)
);
MODULE1 VAR138(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR207),
.VAR70(VAR246)
);
wire [VAR241-1:0] VAR232;
wire [VAR241-1:0] VAR179;
MODULE3 VAR59(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR165),
.VAR161 (VAR145),
.VAR70(VAR232)
);
MODULE3 VAR265(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR128),
.VAR161 (VAR246),
.VAR70(VAR179)
);
wire [VAR241-1:0] VAR94;
MODULE3 VAR76(
.clk(clk), .VAR131(VAR131),
.VAR3 (VAR232),
.VAR161 (VAR179),
.VAR70(VAR94)
);
assign VAR149 = VAR94;
assign VAR28 = VAR162[VAR146-1];
endmodule
module MODULE4 (
clk,
VAR131,
VAR287,
VAR163,
VAR296,
VAR96,
VAR214,
VAR167,
VAR57,
VAR233,
VAR208,
VAR227,
VAR169,
VAR153,
VAR258,
VAR172,
VAR39,
VAR10,
VAR298,
VAR53,
VAR44,
VAR278,
VAR250,
VAR2,
VAR30,
VAR273,
VAR125,
VAR110,
VAR74,
VAR224,
VAR263,
VAR147,
VAR237,
VAR281,
VAR7,
VAR152,
VAR282,
VAR156,
VAR80,
VAR218,
VAR19,
VAR225,
VAR47,
VAR67,
VAR136,
VAR253,
VAR78,
VAR65,
VAR77,
VAR62,
VAR293,
VAR245,
VAR157,
reset);
parameter VAR219 = 1;
input clk;
input VAR131;
input [VAR219-1:0] VAR287;
output [VAR219-1:0] VAR163;
output [VAR219-1:0] VAR296;
output [VAR219-1:0] VAR96;
output [VAR219-1:0] VAR214;
output [VAR219-1:0] VAR167;
output [VAR219-1:0] VAR57;
output [VAR219-1:0] VAR233;
output [VAR219-1:0] VAR208;
output [VAR219-1:0] VAR227;
output [VAR219-1:0] VAR169;
output [VAR219-1:0] VAR153;
output [VAR219-1:0] VAR258;
output [VAR219-1:0] VAR172;
output [VAR219-1:0] VAR39;
output [VAR219-1:0] VAR10;
output [VAR219-1:0] VAR298;
output [VAR219-1:0] VAR53;
output [VAR219-1:0] VAR44;
output [VAR219-1:0] VAR278;
output [VAR219-1:0] VAR250;
output [VAR219-1:0] VAR2;
output [VAR219-1:0] VAR30;
output [VAR219-1:0] VAR273;
output [VAR219-1:0] VAR125;
output [VAR219-1:0] VAR110;
output [VAR219-1:0] VAR74;
output [VAR219-1:0] VAR224;
output [VAR219-1:0] VAR263;
output [VAR219-1:0] VAR147;
output [VAR219-1:0] VAR237;
output [VAR219-1:0] VAR281;
output [VAR219-1:0] VAR7;
output [VAR219-1:0] VAR152;
output [VAR219-1:0] VAR282;
output [VAR219-1:0] VAR156;
output [VAR219-1:0] VAR80;
output [VAR219-1:0] VAR218;
output [VAR219-1:0] VAR19;
output [VAR219-1:0] VAR225;
output [VAR219-1:0] VAR47;
output [VAR219-1:0] VAR67;
output [VAR219-1:0] VAR136;
output [VAR219-1:0] VAR253;
output [VAR219-1:0] VAR78;
output [VAR219-1:0] VAR65;
output [VAR219-1:0] VAR77;
output [VAR219-1:0] VAR62;
output [VAR219-1:0] VAR293;
output [VAR219-1:0] VAR245;
output [VAR219-1:0] VAR157;
reg [VAR219-1:0] VAR163;
reg [VAR219-1:0] VAR296;
reg [VAR219-1:0] VAR96;
reg [VAR219-1:0] VAR214;
reg [VAR219-1:0] VAR167;
reg [VAR219-1:0] VAR57;
reg [VAR219-1:0] VAR233;
reg [VAR219-1:0] VAR208;
reg [VAR219-1:0] VAR227;
reg [VAR219-1:0] VAR169;
reg [VAR219-1:0] VAR153;
reg [VAR219-1:0] VAR258;
reg [VAR219-1:0] VAR172;
reg [VAR219-1:0] VAR39;
reg [VAR219-1:0] VAR10;
reg [VAR219-1:0] VAR298;
reg [VAR219-1:0] VAR53;
reg [VAR219-1:0] VAR44;
reg [VAR219-1:0] VAR278;
reg [VAR219-1:0] VAR250;
reg [VAR219-1:0] VAR2;
reg [VAR219-1:0] VAR30;
reg [VAR219-1:0] VAR273;
reg [VAR219-1:0] VAR125;
reg [VAR219-1:0] VAR110;
reg [VAR219-1:0] VAR74;
reg [VAR219-1:0] VAR224;
reg [VAR219-1:0] VAR263;
reg [VAR219-1:0] VAR147;
reg [VAR219-1:0] VAR237;
reg [VAR219-1:0] VAR281;
reg [VAR219-1:0] VAR7;
reg [VAR219-1:0] VAR152;
reg [VAR219-1:0] VAR282;
reg [VAR219-1:0] VAR156;
reg [VAR219-1:0] VAR80;
reg [VAR219-1:0] VAR218;
reg [VAR219-1:0] VAR19;
reg [VAR219-1:0] VAR225;
reg [VAR219-1:0] VAR47;
reg [VAR219-1:0] VAR67;
reg [VAR219-1:0] VAR136;
reg [VAR219-1:0] VAR253;
reg [VAR219-1:0] VAR78;
reg [VAR219-1:0] VAR65;
reg [VAR219-1:0] VAR77;
reg [VAR219-1:0] VAR62;
reg [VAR219-1:0] VAR293;
reg [VAR219-1:0] VAR245;
reg [VAR219-1:0] VAR157;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR163 <= 0;
VAR296 <= 0;
VAR96 <= 0;
VAR214 <= 0;
VAR167 <= 0;
VAR57 <= 0;
VAR233 <= 0;
VAR208 <= 0;
VAR227 <= 0;
VAR169 <= 0;
VAR153 <= 0;
VAR258 <= 0;
VAR172 <= 0;
VAR39 <= 0;
VAR10 <= 0;
VAR298 <= 0;
VAR53 <= 0;
VAR44 <= 0;
VAR278 <= 0;
VAR250 <= 0;
VAR2 <= 0;
VAR30 <= 0;
VAR273 <= 0;
VAR125 <= 0;
VAR110 <= 0;
VAR74 <= 0;
VAR224 <= 0;
VAR263 <= 0;
VAR147 <= 0;
VAR237 <= 0;
VAR281 <= 0;
VAR7 <= 0;
VAR152 <= 0;
VAR282 <= 0;
VAR156 <= 0;
VAR80 <= 0;
VAR218 <= 0;
VAR19 <= 0;
VAR225 <= 0;
VAR47 <= 0;
VAR67 <= 0;
VAR136 <= 0;
VAR253 <= 0;
VAR78 <= 0;
VAR65 <= 0;
VAR77 <= 0;
VAR62 <= 0;
VAR293 <= 0;
VAR245 <= 0;
VAR157 <= 0;
end else begin
if(VAR131) begin
VAR163 <= VAR287;
VAR296 <= VAR163;
VAR96 <= VAR296;
VAR214 <= VAR96;
VAR167 <= VAR214;
VAR57 <= VAR167;
VAR233 <= VAR57;
VAR208 <= VAR233;
VAR227 <= VAR208;
VAR169 <= VAR227;
VAR153 <= VAR169;
VAR258 <= VAR153;
VAR172 <= VAR258;
VAR39 <= VAR172;
VAR10 <= VAR39;
VAR298 <= VAR10;
VAR53 <= VAR298;
VAR44 <= VAR53;
VAR278 <= VAR44;
VAR250 <= VAR278;
VAR2 <= VAR250;
VAR30 <= VAR2;
VAR273 <= VAR30;
VAR125 <= VAR273;
VAR110 <= VAR125;
VAR74 <= VAR110;
VAR224 <= VAR74;
VAR263 <= VAR224;
VAR147 <= VAR263;
VAR237 <= VAR147;
VAR281 <= VAR237;
VAR7 <= VAR281;
VAR152 <= VAR7;
VAR282 <= VAR152;
VAR156 <= VAR282;
VAR80 <= VAR156;
VAR218 <= VAR80;
VAR19 <= VAR218;
VAR225 <= VAR19;
VAR47 <= VAR225;
VAR67 <= VAR47;
VAR136 <= VAR67;
VAR253 <= VAR136;
VAR78 <= VAR253;
VAR65 <= VAR78;
VAR77 <= VAR65;
VAR62 <= VAR77;
VAR293 <= VAR62;
VAR245 <= VAR293;
VAR157 <= VAR245;
end end
end
endmodule
module MODULE3 (
clk,
VAR131,
VAR3,
VAR161,
VAR70);
input clk;
input VAR131;
input [17:0] VAR3;
input [17:0] VAR161;
output [17:0] VAR70;
reg [17:0] VAR70;
always @(posedge clk) begin
if(VAR131) begin
VAR70 <= VAR3 + VAR161;
end
end
endmodule
module MODULE2 (
clk,
VAR131,
VAR3,
VAR161,
VAR70);
input clk;
input VAR131;
input [17:0] VAR3;
input [17:0] VAR161;
output [17:0] VAR70;
reg [17:0] VAR70;
always @(posedge clk) begin
if(VAR131) begin
VAR70 <= VAR3 * VAR161;
end
end
endmodule
module MODULE1 (
clk,
VAR131,
VAR3,
VAR70);
input clk;
input VAR131;
input [17:0] VAR3;
output [17:0] VAR70;
reg [17:0] VAR70;
always @(posedge clk) begin
if(VAR131) begin
VAR70 <= VAR3;
end
end
endmodule
|
mit
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v
| 3,789 |
module MODULE1 #(parameter VAR37(VAR28)
, parameter VAR37(VAR4)
, parameter VAR37(VAR27)
, VAR5 = 0
, VAR19 = 0
, VAR33 = 4
, VAR6 = VAR34(VAR4+1)
, VAR30 = VAR6+VAR28
, VAR26 = VAR34(VAR27+1)
)
(input VAR16
, input VAR3
, input [VAR30-1:0] VAR8
, input VAR12
, output VAR2
, output [VAR4-1:0][VAR28-1:0] VAR7
, output [VAR4-1:0] VAR24
, input [VAR4-1:0] VAR21
, output [VAR4-1:0][VAR26-1:0] VAR31
, output VAR32
, output [VAR4-1:0][VAR26-1:0] VAR18
, input VAR14
);
logic VAR22;
logic [VAR28-1:0] VAR20;
VAR41 #(.VAR28 (VAR28)
,.VAR23 (VAR4+1 )
,.VAR40 (VAR27)
,.VAR11 (1 << VAR4 )
,.VAR5(VAR5)
,.VAR19(VAR19)
)
VAR38
(.VAR16
,.VAR3
,.VAR12 (VAR12)
,.VAR35 (VAR8[VAR28+:VAR6])
,.VAR8(VAR8[0+:VAR28])
,.VAR2
,.VAR24 ( {VAR22, VAR24} )
,.VAR7 ( {VAR20 , VAR7 } )
,.VAR21 ( { 1'b0, VAR21 } )
);
assign VAR31 = VAR20[0+:VAR4*VAR26];
assign VAR32 = VAR22;
wire [VAR4-1:0] VAR1 = VAR24 & VAR21;
genvar VAR36;
for (VAR36 = 0; VAR36 < VAR4; VAR36=VAR36+1)
begin: VAR10
VAR25 #(.VAR29 (VAR27)
,.VAR13(0)
) VAR39
(.VAR16
,.VAR3
,.VAR9 (VAR14 )
,.VAR15 (VAR1[VAR36] )
,.VAR17 (VAR18[VAR36])
);
end
endmodule
|
bsd-3-clause
|
mrehkopf/sd2snes
|
verilog/sd2snes_obc1/msu.v
| 5,513 |
module MODULE1(
input VAR31,
input enable,
input [13:0] VAR37,
input [7:0] VAR46,
input VAR21,
input [2:0] VAR36,
input [7:0] VAR12,
output [7:0] VAR4,
input VAR39,
input VAR20,
input VAR16,
output [7:0] VAR44,
output [7:0] VAR3,
output VAR30,
output [31:0] VAR1,
output [15:0] VAR24,
input [5:0] VAR14,
input [5:0] VAR5,
input VAR11,
input [13:0] VAR18,
input VAR23,
output VAR35,
output VAR32,
output VAR34,
output [13:0] VAR2,
output VAR22
);
reg [1:0] VAR41;
always @(posedge VAR31) VAR41 = {VAR41[0], VAR11};
wire VAR25 = (VAR41 == 2'b01);
reg [13:0] VAR26;
wire [13:0] VAR15 = VAR26;
VAR17 VAR26 = 13'b0;
wire [7:0] VAR29;
reg [7:0] VAR6;
reg [2:0] VAR40;
always @(posedge VAR31)
VAR40 <= {VAR40[1:0], VAR23};
wire VAR28 = (VAR40[2:1] == 2'b01);
reg [31:0] VAR42;
assign VAR1 = VAR42;
reg [15:0] VAR27;
assign VAR24 = VAR27;
reg [7:0] VAR9;
assign VAR3 = VAR9;
reg VAR7;
assign VAR30 = VAR7;
reg VAR19;
reg VAR8;
reg VAR45;
reg VAR10;
reg VAR33;
reg VAR13;
reg [2:0] VAR38;
reg [1:0] VAR43;
|
gpl-2.0
|
borti4938/sd2snes
|
verilog/sd2snes_cx4/cx4_datrom.v
| 6,427 |
module MODULE1 (
address,
VAR24,
VAR38);
input [9:0] address;
input VAR24;
output [23:0] VAR38;
tri1 VAR24;
wire [23:0] VAR45;
wire [23:0] VAR38 = VAR45[23:0];
VAR32 VAR40 (
.VAR10 (address),
.VAR8 (VAR24),
.VAR31 (VAR45),
.VAR22 (1'b0),
.VAR30 (1'b0),
.VAR49 (1'b1),
.VAR25 (1'b0),
.VAR41 (1'b0),
.VAR15 (1'b1),
.VAR48 (1'b1),
.VAR1 (1'b1),
.VAR14 (1'b1),
.VAR27 (1'b1),
.VAR50 (1'b1),
.VAR34 (1'b1),
.VAR19 ({24{1'b1}}),
.VAR42 (1'b1),
.VAR52 (),
.VAR26 (),
.VAR21 (1'b1),
.VAR20 (1'b1),
.VAR37 (1'b0),
.VAR17 (1'b0));
VAR40.VAR13 = "VAR3",
VAR40.VAR18 = "VAR36",
VAR40.VAR44 = "VAR36",
VAR40.VAR47 = "MODULE1.VAR33",
VAR40.VAR5 = "VAR9 VAR11 VAR4",
VAR40.VAR23 = "VAR51=VAR29",
VAR40.VAR28 = "VAR32",
VAR40.VAR43 = 1024,
VAR40.VAR35 = "VAR16",
VAR40.VAR46 = "VAR3",
VAR40.VAR39 = "VAR6",
VAR40.VAR2 = 10,
VAR40.VAR7 = 24,
VAR40.VAR12 = 1;
endmodule
|
gpl-2.0
|
SeanZarzycki/openSPARC-FPU
|
project/src/fpu_out_dp.v
| 6,147 |
module MODULE1 (
VAR3,
VAR37,
VAR39,
VAR45,
VAR14,
VAR6,
VAR23,
VAR17,
VAR11,
VAR26,
VAR31,
VAR20,
VAR19,
VAR1,
VAR32,
VAR24,
VAR4,
VAR13,
VAR36,
VAR35,
VAR40,
VAR8,
VAR18,
VAR41,
VAR9,
VAR30,
VAR5,
VAR7,
VAR27,
VAR34
);
input [2:0] VAR3; input [1:0] VAR37; input [4:0] VAR39; input VAR45; input VAR14; input VAR6; input [10:0] VAR23; input [51:0] VAR17; input [4:0] VAR11; input VAR26; input VAR31; input VAR20; input [10:0] VAR19; input [51:0] VAR1; input [4:0] VAR32; input VAR24; input [1:0] VAR4; input [1:0] VAR13; input VAR36; input VAR35; input VAR40; input VAR8; input VAR18; input [10:0] VAR41; input [63:0] VAR9; input VAR30;
output [144:0] VAR5;
input VAR7; input VAR27; output VAR34;
wire [63:0] VAR12;
wire [63:0] VAR38;
wire [63:0] VAR15;
wire [7:0] VAR25;
wire [76:0] VAR29;
wire [7:0] VAR44;
wire [76:0] VAR28;
wire [144:0] VAR5;
wire sel;
assign sel = ~VAR7;
VAR10 VAR2 (
.clk(clk),
.VAR30(VAR30),
.VAR22(1'b0),
.VAR33(sel)
);
assign VAR12[63:0]= ({64{VAR36}}
& {VAR18, VAR41[10:0],
VAR9[62:11]})
| ({64{VAR35}}
& {VAR18, VAR41[7:0],
VAR9[62:40], 32'b0})
| ({64{VAR40}}
& VAR9[63:0])
| ({64{VAR8}}
& {VAR9[63:32], 32'b0});
assign VAR38[63:0]= ({64{VAR26}}
& {VAR20, VAR19[10:0],
VAR1[51:0]})
| ({64{VAR31}}
& {VAR20, VAR19[7:0],
VAR1[51:29], 32'b0});
assign VAR15[63:0]= ({64{VAR45}}
& {VAR6, VAR23[10:0],
VAR17[51:0]})
| ({64{VAR14}}
& {VAR6, VAR23[7:0],
VAR17[51:29], 32'b0});
assign VAR25[7:0]= ({8{(|VAR3)}}
& {1'b1, 4'b1000, 1'b0, VAR37[1:0]});
assign VAR29[76:0]= ({77{VAR3[2]}}
& {VAR39[4:0], 8'b0, VAR15[63:0]})
| ({77{VAR3[1]}}
& {VAR11[4:0], 8'b0, VAR38[63:0]})
| ({77{VAR3[0]}}
& {VAR32[4:0], 2'b0, VAR24,
VAR4[1:0], VAR13[1:0], 1'b0,
VAR12[63:0]});
VAR16 #(8) VAR42 (
.din (VAR25[7:0]),
.clk (clk),
.VAR21 (VAR44[7:0]),
.VAR7 (VAR7),
.VAR27 (),
.VAR34 ()
);
VAR16 #(77) VAR43 (
.din (VAR29[76:0]),
.clk (clk),
.VAR21 (VAR28[76:0]),
.VAR7 (VAR7),
.VAR27 (),
.VAR34 ()
);
assign VAR5[144:0]= {VAR44[7:3],
3'b0,
VAR44[2:0],
57'b0,
VAR28[76:0]};
endmodule
|
gpl-3.0
|
marco-c/leon-nexys2
|
grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_mult_mac.v
| 12,399 |
module MODULE1(
clk, rst,
VAR18, VAR6, VAR17, VAR43, VAR4, VAR37, VAR10, VAR39, VAR22,
VAR29, VAR46, VAR12, VAR40, VAR1
);
parameter VAR30 = VAR26;
input clk;
input rst;
input VAR18;
input VAR6;
input VAR17;
input [VAR30-1:0] VAR43;
input [VAR30-1:0] VAR4;
input [VAR14-1:0] VAR37;
input [VAR20-1:0] VAR10;
output [VAR30-1:0] VAR39;
output VAR22;
input VAR29;
input VAR46;
input [31:0] VAR12;
input [31:0] VAR40;
output [31:0] VAR1;
reg [VAR30-1:0] VAR39;
reg [2*VAR30-1:0] VAR45;
wire [VAR30-1:0] VAR39;
wire [2*VAR30-1:0] VAR45;
wire [2*VAR30-1:0] VAR32;
wire [VAR14-1:0] VAR37;
reg [VAR14-1:0] VAR13;
reg [VAR14-1:0] VAR42;
reg [VAR14-1:0] VAR19;
reg VAR22;
reg [2*VAR30-1:0] VAR35;
wire [VAR14-1:0] VAR13;
wire [VAR14-1:0] VAR42;
wire [VAR14-1:0] VAR19;
wire VAR22;
wire [2*VAR30-1:0] VAR35;
wire [VAR30-1:0] VAR41;
wire [VAR30-1:0] VAR44;
wire VAR16;
wire VAR48;
wire VAR11;
wire VAR33;
reg VAR34;
wire [VAR30-1:0] VAR38;
reg [5:0] VAR7;
assign VAR16 = VAR29 & VAR46 & VAR12[VAR21];
assign VAR48 = VAR29 & VAR46 & !VAR12[VAR21];
assign VAR1 = VAR12[VAR21] ? VAR35[31:0] : VAR35[63:32];
assign VAR16 = 1'b0;
assign VAR48 = 1'b0;
assign VAR1 = 32'h00000000;
assign VAR41 = (VAR33 & VAR43[31]) ? ~VAR43 + 1'b1 : VAR11 | (VAR10 == VAR15) | (|VAR37) ? VAR43 : 32'h00000000;
assign VAR44 = (VAR33 & VAR4[31]) ? ~VAR4 + 1'b1 : VAR11 | (VAR10 == VAR15) | (|VAR37) ? VAR4 : 32'h00000000;
assign VAR41 = VAR33 & VAR43[31] ? ~VAR43 + 32'b1 : VAR43;
assign VAR44 = VAR33 & VAR4[31] ? ~VAR4 + 32'b1 : VAR4;
assign VAR33 = (VAR10 == VAR28);
assign VAR11 = VAR33 | (VAR10 == VAR3);
assign VAR38 = VAR45[63:32] - VAR44;
assign VAR33 = 1'b0;
assign VAR11 = 1'b0;
always @(VAR10 or VAR45 or VAR35 or VAR43 or VAR4)
casex(VAR10) VAR31 VAR2
VAR39 = VAR43[31] ^ VAR4[31] ? ~VAR45[31:0] + 1'b1 : VAR45[31:0];
VAR39 = VAR45[31:0];
end
default:
VAR39 = VAR35[VAR25+31:VAR25];
VAR39 = VAR35[31:0];
endcase
VAR47 VAR47(
.VAR36(VAR41),
.VAR9(VAR44),
.VAR23(rst),
.VAR27(clk),
.VAR5(VAR32)
);
.VAR36(VAR41),
.VAR9(VAR44),
.VAR23(rst),
.VAR27(clk),
.VAR5(VAR32)
);
always @(posedge rst or posedge clk)
if (rst) begin
VAR45 <= 64'h0000000000000000;
VAR34 <= 1'b1;
VAR7 <= 6'b000000;
end
else if (|VAR7) begin
if (VAR38[31])
VAR45 <= {VAR45[62:0], 1'b0};
end
else
VAR45 <= {VAR38[30:0], VAR45[31:0], 1'b1};
VAR7 <= VAR7 - 1'b1;
end
else if (VAR11 && VAR34) begin
VAR45 <= {31'b0, VAR41[31:0], 1'b0};
VAR7 <= 6'b100000;
VAR34 <= 1'b0;
end
VAR45 <= VAR32[63:0];
VAR34 <= 1'b1;
end
assign VAR32 = {2*VAR30{1'b0}};
assign VAR45 = {2*VAR30{1'b0}};
always @(posedge clk or posedge rst)
if (rst)
VAR13 <= VAR14'b0;
else
VAR13 <= VAR37;
always @(posedge clk or posedge rst)
if (rst)
VAR42 <= VAR14'b0;
else
VAR42 <= VAR13;
always @(posedge clk or posedge rst)
if (rst)
VAR19 <= VAR14'b0;
else
VAR19 <= VAR42;
always @(posedge rst or posedge clk)
if (rst)
VAR35 <= 64'h0000000000000000;
else if (VAR16)
VAR35[31:0] <= VAR40;
else if (VAR48)
VAR35[63:32] <= VAR40;
else if (VAR19 == VAR8)
VAR35 <= VAR35 + VAR45;
else if (VAR19 == VAR24)
VAR35 <= VAR35 - VAR45;
else if (VAR17 & !VAR18)
VAR35 <= 64'h0000000000000000;
always @(posedge rst or posedge clk)
if (rst)
VAR22 <= 1'b0;
else
VAR22 <= (|VAR37 | (|VAR13) | (|VAR42)) & VAR6
| (|VAR7)
;
assign VAR35 = {2*VAR30{1'b0}};
assign VAR13 = VAR14'b0;
assign VAR42 = VAR14'b0;
assign VAR19 = VAR14'b0;
endmodule
|
gpl-2.0
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/synth/daala_zynq_auto_pc_121.v
| 12,253 |
module MODULE1 (
VAR59,
VAR7,
VAR29,
VAR63,
VAR17,
VAR45,
VAR56,
VAR83,
VAR27,
VAR87,
VAR107,
VAR57,
VAR113,
VAR104,
VAR26,
VAR60,
VAR61,
VAR108,
VAR20,
VAR97,
VAR89,
VAR32,
VAR91,
VAR101,
VAR40,
VAR98,
VAR68,
VAR73,
VAR43,
VAR55,
VAR53,
VAR71,
VAR90,
VAR13,
VAR3,
VAR79,
VAR52,
VAR69,
VAR99,
VAR103,
VAR16,
VAR76,
VAR38,
VAR102,
VAR12,
VAR46,
VAR66,
VAR74,
VAR2,
VAR21,
VAR58,
VAR80,
VAR30,
VAR82
);
input VAR59;
input VAR7;
input [31 : 0] VAR29;
input [3 : 0] VAR63;
input [2 : 0] VAR17;
input [1 : 0] VAR45;
input [1 : 0] VAR56;
input [3 : 0] VAR83;
input [2 : 0] VAR27;
input [3 : 0] VAR87;
input VAR107;
output VAR57;
input [31 : 0] VAR113;
input [3 : 0] VAR104;
input VAR26;
input VAR60;
output VAR61;
output [1 : 0] VAR108;
output VAR20;
input VAR97;
input [31 : 0] VAR89;
input [3 : 0] VAR32;
input [2 : 0] VAR91;
input [1 : 0] VAR101;
input [1 : 0] VAR40;
input [3 : 0] VAR98;
input [2 : 0] VAR68;
input [3 : 0] VAR73;
input VAR43;
output VAR55;
output [31 : 0] VAR53;
output [1 : 0] VAR71;
output VAR90;
output VAR13;
input VAR3;
output [31 : 0] VAR79;
output [2 : 0] VAR52;
output VAR69;
input VAR99;
output [31 : 0] VAR103;
output [3 : 0] VAR16;
output VAR76;
input VAR38;
input [1 : 0] VAR102;
input VAR12;
output VAR46;
output [31 : 0] VAR66;
output [2 : 0] VAR74;
output VAR2;
input VAR21;
input [31 : 0] VAR58;
input [1 : 0] VAR80;
input VAR30;
output VAR82;
VAR31 #(
.VAR44("VAR86"),
.VAR111(2),
.VAR11(1),
.VAR64(1),
.VAR75(1),
.VAR9(32),
.VAR35(32),
.VAR85(1),
.VAR24(1),
.VAR92(0),
.VAR49(1),
.VAR96(1),
.VAR28(1),
.VAR36(1),
.VAR65(1),
.VAR19(2)
) VAR112 (
.VAR59(VAR59),
.VAR7(VAR7),
.VAR23(1'VAR81),
.VAR29(VAR29),
.VAR63(VAR63),
.VAR17(VAR17),
.VAR45(VAR45),
.VAR56(VAR56),
.VAR83(VAR83),
.VAR27(VAR27),
.VAR51(4'VAR81),
.VAR87(VAR87),
.VAR67(1'VAR81),
.VAR107(VAR107),
.VAR57(VAR57),
.VAR70(1'VAR81),
.VAR113(VAR113),
.VAR104(VAR104),
.VAR26(VAR26),
.VAR110(1'VAR81),
.VAR60(VAR60),
.VAR61(VAR61),
.VAR105(),
.VAR108(VAR108),
.VAR48(),
.VAR20(VAR20),
.VAR97(VAR97),
.VAR34(1'VAR81),
.VAR89(VAR89),
.VAR32(VAR32),
.VAR91(VAR91),
.VAR101(VAR101),
.VAR40(VAR40),
.VAR98(VAR98),
.VAR68(VAR68),
.VAR41(4'VAR81),
.VAR73(VAR73),
.VAR1(1'VAR81),
.VAR43(VAR43),
.VAR55(VAR55),
.VAR94(),
.VAR53(VAR53),
.VAR71(VAR71),
.VAR90(VAR90),
.VAR100(),
.VAR13(VAR13),
.VAR3(VAR3),
.VAR33(),
.VAR79(VAR79),
.VAR62(),
.VAR106(),
.VAR54(),
.VAR14(),
.VAR10(),
.VAR52(VAR52),
.VAR50(),
.VAR72(),
.VAR109(),
.VAR69(VAR69),
.VAR99(VAR99),
.VAR6(),
.VAR103(VAR103),
.VAR16(VAR16),
.VAR18(),
.VAR39(),
.VAR76(VAR76),
.VAR38(VAR38),
.VAR77(1'VAR81),
.VAR102(VAR102),
.VAR4(1'VAR81),
.VAR12(VAR12),
.VAR46(VAR46),
.VAR8(),
.VAR66(VAR66),
.VAR84(),
.VAR42(),
.VAR25(),
.VAR47(),
.VAR78(),
.VAR74(VAR74),
.VAR5(),
.VAR95(),
.VAR37(),
.VAR2(VAR2),
.VAR21(VAR21),
.VAR93(1'VAR81),
.VAR58(VAR58),
.VAR80(VAR80),
.VAR22(1'VAR88),
.VAR15(1'VAR81),
.VAR30(VAR30),
.VAR82(VAR82)
);
endmodule
|
bsd-2-clause
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_adc_dma.v
| 16,314 |
module MODULE1 (
VAR81,
VAR88,
VAR32,
VAR44,
VAR8,
VAR6,
VAR41,
VAR57,
VAR4,
VAR39,
VAR77,
VAR13,
VAR80,
VAR7,
VAR21,
VAR87,
VAR9,
VAR51,
VAR49);
input VAR81;
input VAR88;
input [63:0] VAR32;
input VAR44;
output VAR8;
output [63:0] VAR6;
output [ 7:0] VAR41;
output VAR57;
input VAR4;
output VAR39;
output VAR77;
output VAR13;
input VAR80;
input VAR7;
input [29:0] VAR21;
output [63:0] VAR87;
output [ 7:0] VAR9;
output [63:0] VAR51;
output [ 7:0] VAR49;
reg VAR75 = 'd0;
reg VAR73 = 'd0;
reg VAR92 = 'd0;
reg VAR1 = 'd0;
reg [ 5:0] VAR53 = 'd0;
reg VAR47 = 'd0;
reg VAR60 = 'd0;
reg VAR68 = 'd0;
reg [ 5:0] VAR71 = 'd0;
reg [ 5:0] VAR31 = 'd0;
reg [ 5:0] VAR18 = 'd0;
reg [ 5:0] VAR24 = 'd0;
reg [ 5:0] VAR56 = 'd0;
reg [ 5:0] VAR10 = 'd0;
reg VAR89 = 'd0;
reg VAR74 = 'd0;
reg [64:0] VAR5 = 'd0;
reg [ 1:0] VAR64 = 'd0;
reg VAR63 = 'd0;
reg [64:0] VAR62 = 'd0;
reg VAR34 = 'd0;
reg [64:0] VAR12 = 'd0;
reg VAR25 = 'd0;
reg [64:0] VAR29 = 'd0;
reg VAR11 = 'd0;
reg [64:0] VAR86 = 'd0;
reg [ 1:0] VAR23 = 'd0;
reg VAR8 = 'd0;
reg [ 7:0] VAR41 = 'd0;
reg VAR57 = 'd0;
reg [63:0] VAR6 = 'd0;
reg VAR67 = 'd0;
reg VAR19 = 'd0;
reg [ 4:0] VAR33 = 'd0;
reg VAR39 = 'd0;
reg [ 4:0] VAR38 = 'd0;
reg VAR77 = 'd0;
reg VAR13 = 'd0;
reg VAR69 = 'd0;
reg VAR93 = 'd0;
reg VAR37 = 'd0;
reg VAR83 = 'd0;
reg VAR91 = 'd0;
reg [30:0] VAR22 = 'd0;
reg [30:0] VAR79 = 'd0;
reg [ 3:0] VAR78 = 'd0;
reg VAR55 = 'd0;
reg [ 5:0] VAR40 = 'd0;
reg VAR52 = 'd0;
reg [ 5:0] VAR26 = 'd0;
reg VAR61 = 'd0;
reg [ 5:0] VAR59 = 'd0;
reg [ 5:0] VAR84 = 'd0;
reg [64:0] VAR17 = 'd0;
wire VAR54;
wire VAR20;
wire [ 6:0] VAR43;
wire VAR82;
wire VAR3;
wire VAR72;
wire VAR90;
wire VAR76;
wire [64:0] VAR46;
wire VAR65;
wire VAR70;
wire VAR27;
function [5:0] VAR58;
input [5:0] VAR2;
reg [5:0] VAR16;
begin
VAR16[5] = VAR2[5];
VAR16[4] = VAR2[5] ^ VAR2[4];
VAR16[3] = VAR2[4] ^ VAR2[3];
VAR16[2] = VAR2[3] ^ VAR2[2];
VAR16[1] = VAR2[2] ^ VAR2[1];
VAR16[0] = VAR2[1] ^ VAR2[0];
VAR58 = VAR16;
end
endfunction
function [5:0] VAR42;
input [5:0] VAR16;
reg [5:0] VAR2;
begin
VAR2[5] = VAR16[5];
VAR2[4] = VAR2[5] ^ VAR16[4];
VAR2[3] = VAR2[4] ^ VAR16[3];
VAR2[2] = VAR2[3] ^ VAR16[2];
VAR2[1] = VAR2[2] ^ VAR16[1];
VAR2[0] = VAR2[1] ^ VAR16[0];
VAR42 = VAR2;
end
endfunction
assign VAR9[7] = VAR77;
assign VAR9[6] = VAR39;
assign VAR9[5] = VAR20;
assign VAR9[4] = VAR54;
assign VAR9[3] = VAR13;
assign VAR9[2] = VAR4;
assign VAR9[1] = VAR57;
assign VAR9[0] = VAR8;
assign VAR87[63:61] = 'd0;
assign VAR87[60:53] = VAR6[7:0];
assign VAR87[52:45] = VAR5[7:0];
assign VAR87[44:44] = VAR72;
assign VAR87[43:43] = VAR90;
assign VAR87[42:42] = VAR19;
assign VAR87[41:41] = VAR67;
assign VAR87[40:34] = VAR43;
assign VAR87[33:28] = VAR71;
assign VAR87[27:27] = VAR77;
assign VAR87[26:26] = VAR39;
assign VAR87[25:24] = VAR64;
assign VAR87[23:22] = VAR23;
assign VAR87[21:16] = VAR24;
assign VAR87[15:10] = VAR10;
assign VAR87[ 9: 9] = VAR20;
assign VAR87[ 8: 8] = VAR54;
assign VAR87[ 7: 7] = VAR82;
assign VAR87[ 6: 6] = VAR74;
assign VAR87[ 5: 5] = VAR89;
assign VAR87[ 4: 4] = VAR3;
assign VAR87[ 3: 3] = VAR13;
assign VAR87[ 2: 2] = VAR4;
assign VAR87[ 1: 1] = VAR57;
assign VAR87[ 0: 0] = VAR8;
assign VAR49[7] = VAR27;
assign VAR49[6] = VAR61;
assign VAR49[5] = VAR55;
assign VAR49[4] = VAR52;
assign VAR49[3] = VAR70;
assign VAR49[2] = VAR65;
assign VAR49[1] = VAR65;
assign VAR49[0] = VAR65;
assign VAR51[63:63] = VAR70;
assign VAR51[62:62] = VAR70;
assign VAR51[61:61] = VAR70;
assign VAR51[60:60] = VAR65;
assign VAR51[59:59] = VAR65;
assign VAR51[58:58] = VAR52;
assign VAR51[57:57] = VAR52;
assign VAR51[56:56] = VAR55;
assign VAR51[55:50] = VAR26;
assign VAR51[49:44] = VAR59;
assign VAR51[43:43] = VAR61;
assign VAR51[42:42] = VAR17[64];
assign VAR51[41: 0] = VAR17[41:0];
assign VAR54 = VAR92 ^ VAR73;
assign VAR20 = VAR68 ^ VAR60;
assign VAR43 = {1'b1, VAR24} - VAR10;
always @(posedge VAR44) begin
VAR75 <= VAR55;
VAR73 <= VAR75;
VAR92 <= VAR73;
VAR1 <= VAR54;
if (VAR54 == 1'b1) begin
VAR53 <= VAR40;
end
VAR47 <= VAR52;
VAR60 <= VAR47;
VAR68 <= VAR60;
if (VAR20 == 1'b1) begin
VAR71 <= VAR26;
end
VAR31 <= VAR84;
VAR18 <= VAR31;
VAR24 <= VAR42(VAR18);
VAR56 <= VAR43[5:0];
end
assign VAR82 = VAR4 | ~VAR8;
assign VAR3 = (VAR71 == VAR10) ? 1'b0 : VAR4;
always @(posedge VAR44) begin
if (VAR1 == 1'b1) begin
VAR10 <= VAR53;
end else if (VAR3 == 1'b1) begin
VAR10 <= VAR10 + 1'b1;
end
VAR89 <= VAR3;
VAR74 <= VAR89;
VAR5 <= VAR46;
end
always @(posedge VAR44) begin
if (VAR74 == 1'b1) begin
VAR64 <= VAR64 + 1'b1;
end
if ((VAR64 == 2'd0) && (VAR74 == 1'b1)) begin
VAR63 <= 1'b1;
VAR62 <= VAR5;
end else if ((VAR23 == 2'd0) && (VAR82 == 1'b1)) begin
VAR63 <= 1'b0;
VAR62 <= 65'd0;
end
if ((VAR64 == 2'd1) && (VAR74 == 1'b1)) begin
VAR34 <= 1'b1;
VAR12 <= VAR5;
end else if ((VAR23 == 2'd1) && (VAR82 == 1'b1)) begin
VAR34 <= 1'b0;
VAR12 <= 65'd0;
end
if ((VAR64 == 2'd2) && (VAR74 == 1'b1)) begin
VAR25 <= 1'b1;
VAR29 <= VAR5;
end else if ((VAR23 == 2'd2) && (VAR82 == 1'b1)) begin
VAR25 <= 1'b0;
VAR29 <= 65'd0;
end
if ((VAR64 == 2'd3) && (VAR74 == 1'b1)) begin
VAR11 <= 1'b1;
VAR86 <= VAR5;
end else if ((VAR23 == 2'd3) && (VAR82 == 1'b1)) begin
VAR11 <= 1'b0;
VAR86 <= 65'd0;
end
if ((VAR23 != VAR64) && (VAR4 == 1'b1)) begin
VAR23 <= VAR23 + 1'b1;
end
if ((VAR8 == 1'b0) || (VAR4 == 1'b1)) begin
case (VAR23)
2'd3: begin
VAR8 <= VAR11;
VAR41 <= 8'hff;
VAR57 <= VAR86[64] & VAR11;
VAR6 <= VAR86[63:0];
end
2'd2: begin
VAR8 <= VAR25;
VAR41 <= 8'hff;
VAR57 <= VAR29[64] & VAR25;
VAR6 <= VAR29[63:0];
end
2'd1: begin
VAR8 <= VAR34;
VAR41 <= 8'hff;
VAR57 <= VAR12[64] & VAR34;
VAR6 <= VAR12[63:0];
end
default: begin
VAR8 <= VAR63;
VAR41 <= 8'hff;
VAR57 <= VAR62[64] & VAR63;
VAR6 <= VAR62[63:0];
end
endcase
end
end
assign VAR72 = (VAR56 < 3) ? VAR67 : 1'b0;
assign VAR90 = (VAR56 > 60) ? VAR19 : 1'b0;
always @(posedge VAR44) begin
VAR67 = (VAR56 > 60) ? 1'b1 : 1'b0;
VAR19 = (VAR56 < 3) ? 1'b1 : 1'b0;
if (VAR72 == 1'b1) begin
VAR33 <= 5'h10;
end else if (VAR33[4] == 1'b1) begin
VAR33 <= VAR33 + 1'b1;
end
VAR39 <= VAR33[4];
if (VAR90 == 1'b1) begin
VAR38 <= 5'h10;
end else if (VAR38[4] == 1'b1) begin
VAR38 <= VAR38 + 1'b1;
end
VAR77 <= VAR38[4];
end
assign VAR76 = VAR8 & VAR4 & VAR57;
always @(posedge VAR44) begin
if (VAR1 == 1'b1) begin
VAR13 <= 1'b1;
end else if (VAR76 == 1'b1) begin
VAR13 <= 1'b0;
end
end
assign VAR65 = (VAR79[29:0] == 'd0) ? VAR79[30] : 1'b0;
assign VAR70 = (VAR78 == 4'hf) ? VAR88 : 1'b0;
assign VAR27 = VAR93 & ~VAR37;
always @(posedge VAR81) begin
VAR69 <= VAR80;
VAR93 <= VAR69;
VAR37 <= VAR93;
VAR83 <= VAR27;
if (VAR27 == 1'b1) begin
VAR91 <= VAR7;
VAR22 <= {1'd1, VAR21};
end
if ((VAR79[30] == 1'b1) && (VAR88 == 1'b1)) begin
if ((VAR65 == 1'b1) && (VAR91 == 1'b1)) begin
VAR79 <= VAR22;
end else begin
VAR79 <= VAR79 - 1'b1;
end
end else if (VAR83 == 1'b1) begin
VAR79 <= VAR22;
end
if (VAR88 == 1'b1) begin
VAR78 <= VAR78 + 1'b1;
end else if (VAR83 == 1'b1) begin
VAR78 <= 4'd0;
end
end
always @(posedge VAR81) begin
if (VAR83 == 1'b1) begin
VAR55 <= ~VAR55;
VAR40 <= VAR59;
end
if (VAR70 == 1'b1) begin
VAR52 <= ~VAR52;
VAR26 <= VAR59;
end
end
always @(posedge VAR81) begin
VAR61 <= VAR79[30] & VAR88;
if (VAR61 == 1'b1) begin
VAR59 <= VAR59 + 1'b1;
end
VAR84 <= VAR58(VAR59);
VAR17 <= {VAR65, VAR32};
end
VAR50 #(.VAR15(65), .VAR66(6)) VAR14 (
.VAR35 (VAR81),
.VAR36 (VAR61),
.VAR28 (VAR59),
.VAR48 (VAR17),
.VAR85 (VAR44),
.VAR30 (VAR10),
.VAR45 (VAR46));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/bufinv/sky130_fd_sc_lp__bufinv.pp.blackbox.v
| 1,259 |
module MODULE1 (
VAR4 ,
VAR3 ,
VAR2,
VAR1,
VAR6 ,
VAR5
);
output VAR4 ;
input VAR3 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR5 ;
endmodule
|
apache-2.0
|
jaechoon2/FPGA-Imaging-Library
|
LocalFilter/MatchTemplateBin/HDL/MatchTemplateBin.srcs/sources_1/new/MatchTemplateBin.v
| 2,847 |
module MODULE1(
clk,
VAR5,
VAR9,
VAR7,
VAR10,
VAR1,
VAR4);
parameter[0 : 0] VAR8 = 0;
parameter[3 : 0] VAR3 = 3;
input clk;
input VAR5;
input[VAR3 * VAR3 - 1 : 0] VAR9;
input VAR7;
input [VAR3 * VAR3 - 1 : 0] VAR10;
output VAR1;
output VAR4;
reg VAR6;
reg VAR2;
generate
always @(posedge clk or negedge VAR5 or negedge VAR7) begin
if(~VAR5 || ~VAR7) begin
VAR2 <= 0;
end else begin
VAR2 <= 1;
end
end
assign VAR1 = VAR2;
if(VAR8 == 0) begin
always @(posedge clk)
VAR6 <= VAR10 == VAR9 ? 1 : 0;
end else begin
always @(posedge VAR7)
VAR6 <= VAR10 == VAR9 ? 1 : 0;
end
assign VAR4 = VAR1 ? VAR6 : 0;
endgenerate
endmodule
|
lgpl-2.1
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.symbol.v
| 1,451 |
module MODULE1 (
input VAR5,
input VAR6,
input VAR8 ,
input VAR7 ,
output VAR2
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
cospan/prometheus_fpga
|
rtl/top.v
| 5,510 |
module MODULE1(
input VAR45,
input VAR73,
output [3:0] VAR86,
input [3:0] VAR41,
input [1:0] VAR85,
inout [31:0] VAR37,
output VAR62,
output VAR83,
output VAR76,
output VAR70,
output VAR77,
input VAR84,
input VAR24,
input VAR42,
input VAR64,
output [1:0] VAR9
);
wire rst;
wire clk;
reg [3:0] VAR14;
reg [31:0] VAR71;
wire [31:0] VAR33;
wire VAR65;
wire [7:0] VAR8;
wire [7:0] VAR91;
wire [31:0] VAR82;
wire [31:0] VAR18;
wire VAR40;
wire [7:0] VAR60;
wire [31:0] VAR7;
wire VAR17;
wire [31:0] VAR31;
wire VAR43;
wire VAR78;
wire [23:0] VAR54;
wire [31:0] VAR61;
wire VAR63;
wire [1:0] VAR1;
wire [1:0] VAR27;
wire [23:0] VAR32;
wire [31:0] VAR50;
wire VAR13;
VAR22 VAR69 (
.clk (clk ),
.rst (rst ),
.VAR19 (VAR37 ),
.VAR38 (VAR83 ),
.VAR12 (VAR70 ),
.VAR57 (VAR76 ),
.VAR49 (VAR77 ),
.VAR80 (VAR84 ),
.VAR90 (VAR24 ),
.VAR75 (VAR42 ),
.VAR23 (VAR64 ),
.VAR58 (VAR9 ),
.VAR25 (VAR65 ),
.VAR87 (VAR8 ),
.VAR67 (VAR91 ),
.VAR34 (VAR82 ),
.VAR29 (VAR18 ),
.VAR53 (VAR40 ),
.VAR89 (VAR60 ),
.VAR59 (VAR7 ),
.VAR16 (VAR17 ),
.VAR39 (VAR31 ),
.VAR48 (VAR43 ),
.VAR30 (VAR78 ),
.VAR11 (VAR54 ),
.VAR26 (VAR61 ),
.VAR10 (VAR63 ),
.VAR56 (VAR1 ),
.VAR55 (VAR27 ),
.VAR79 (VAR32 ),
.VAR72 (VAR50 ),
.VAR88 (VAR13 )
);
VAR21 VAR66 (
.clk (clk ),
.rst (rst ),
.VAR3 (VAR65 ),
.VAR81 (VAR8 ),
.VAR2 (VAR91 ),
.VAR5 (VAR82 ),
.VAR39 (VAR18 ),
.VAR28 (VAR40 ),
.VAR4 (VAR60 ),
.VAR36 (VAR7 ),
.VAR20 (VAR17 ),
.VAR29 (VAR31 ),
.VAR51 (VAR43 ),
.VAR68 (VAR78 ),
.VAR92 (VAR54 ),
.VAR44 (VAR61 ),
.VAR6 (VAR63 ),
.VAR15 (VAR1 ),
.VAR35 (VAR27 ),
.VAR47 (VAR32 ),
.VAR46 (VAR50 ),
.VAR74 (VAR13 )
);
assign clk = VAR45;
assign rst = VAR73;
assign VAR86 = ~VAR14;
assign VAR62= clk;
assign VAR33 = 128;
always @ (posedge VAR45) begin
if (!rst) begin
VAR14[0] <= 0;
VAR14[1] <= 0;
VAR14[2] <= 0;
VAR14[3] <= 0;
VAR71 <= 0;
end
else begin
if (VAR71 < VAR52) begin
VAR71 <= VAR71 + 1;
end
else begin
VAR71 <= 0;
VAR14[0] <= ~VAR14[0];
end
if (VAR41[1]) begin
VAR14[0] <= 1;
VAR14[1] <= 1;
VAR14[2] <= 1;
VAR14[3] <= 1;
end
end
end
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.behavioral.v
| 1,620 |
module MODULE1( VAR7, VAR4, VAR6, VAR1 );
input VAR1, VAR4, VAR6;
output VAR7;
VAR2 VAR3(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1));
VAR2 VAR5(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1));
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Lundgren FPU/branches/avendor/pipeline/fpu_addsub.v
| 20,865 |
module MODULE1( clk, rst, enable, VAR200, VAR153, VAR133, VAR198, out, ready);
input clk;
input rst;
input enable;
input VAR200;
input [1:0] VAR153;
input [63:0] VAR133, VAR198;
output [63:0] out;
output ready;
reg [63:0] VAR195, out;
reg [1:0] VAR176, VAR144, VAR146, VAR96, VAR36, VAR175, VAR41, VAR203, VAR48;
reg [1:0] VAR119, VAR89, VAR187, VAR73, VAR60, VAR99, VAR201;
reg VAR191, VAR141, VAR129, VAR115, VAR169, VAR173, VAR1;
reg VAR125, VAR59, VAR33, VAR213, VAR55, VAR181, VAR9, VAR39, VAR80;
reg VAR26, VAR162, VAR34, VAR118, VAR93, VAR117;
reg VAR178, VAR108, VAR58, VAR29, VAR159;
reg VAR130, VAR155, VAR19, VAR98, VAR52, VAR40, VAR2, VAR17, VAR57;
reg VAR4, VAR6, VAR3, VAR84, VAR38, VAR163;
reg VAR5, VAR15, VAR182, VAR199, VAR123, VAR51, VAR21;
reg [10:0] VAR157, VAR140, VAR102, VAR113, VAR64, VAR14;
reg [51:0] VAR22, VAR137, VAR190, VAR97, VAR138, VAR143;
reg VAR171, VAR81, VAR121, VAR136, VAR204, VAR46, VAR161;
reg VAR31, VAR122, VAR179, VAR82, VAR107, VAR63, VAR126, VAR124;
reg VAR8, VAR87, VAR127, VAR23, VAR128, VAR194, VAR88;
reg VAR206, VAR37, VAR185, VAR189, VAR62;
reg [10:0] VAR27, VAR90, VAR86, VAR75, VAR11;
reg [10:0] VAR49, VAR71, VAR54, VAR166, VAR156, VAR211, VAR188;
reg [51:0] VAR184, VAR114;
reg [51:0] VAR76, VAR7;
reg [51:0] VAR134, VAR154;
reg VAR83, VAR30, VAR78, VAR85;
reg [10:0] VAR209, VAR56, VAR72;
reg [107:0] VAR28, VAR12;
reg VAR20;
reg [55:0] VAR61, VAR207, VAR25, VAR174;
reg [55:0] VAR165, VAR67, VAR197, VAR79;
reg [55:0] VAR53, VAR66;
reg VAR77;
reg VAR132, VAR205, VAR183;
reg VAR135;
wire [55:0] VAR110 = { 55'b0, 1'b1 };
reg [55:0] sum, VAR32, VAR101, VAR111, VAR149;
reg [55:0] VAR95, VAR164, VAR150, VAR18, VAR13, VAR112;
reg VAR24, VAR147, VAR94, VAR158;
reg [10:0] VAR196, VAR74, VAR104, VAR50;
reg [10:0] VAR91, VAR43, VAR69, VAR210, VAR167;
reg [10:0] VAR16, VAR186, VAR106, VAR145, VAR70;
reg [10:0] VAR212, VAR68, VAR152;
reg [5:0] VAR35, VAR192;
reg [55:0] VAR44, VAR10, VAR100, VAR120, VAR65;
reg [55:0] VAR139, VAR151, VAR148, VAR172, VAR131, VAR47;
reg VAR177, VAR180, VAR116;
reg VAR45, VAR193, VAR214;
reg VAR105, VAR42;
reg VAR142, VAR160, VAR168;
reg VAR103, VAR208, VAR92;
reg ready, VAR109, VAR202;
reg [4:0] VAR170;
always @(posedge clk)
begin
if (rst) begin
VAR115 <= 0; VAR1 <= 0; VAR169 <= 0;
VAR173 <= 0; VAR125 <= 0; VAR59 <= 0; VAR33 <= 0;
VAR213 <= 0; VAR55 <= 0; VAR181 <= 0; VAR9 <= 0; VAR39 <= 0;
VAR80 <= 0; VAR26 <= 0; VAR162 <= 0; VAR34 <= 0; VAR118 <= 0;
VAR93 <= 0; VAR117 <= 0; VAR178 <= 0; VAR108 <= 0; VAR58 <= 0;
VAR29 <= 0; VAR159 <= 0;
VAR176 <= 0; VAR144 <= 0; VAR146 <= 0; VAR96 <= 0; VAR36 <= 0;
VAR175 <= 0; VAR41 <= 0; VAR203 <= 0; VAR48 <= 0; VAR119 <= 0; VAR89 <= 0;
VAR187 <= 0; VAR73 <= 0; VAR60 <= 0; VAR99 <= 0; VAR201 <= 0; VAR141 <= 0;
VAR129 <= 0; VAR130 <= 0; VAR19 <= 0; VAR155 <= 0; VAR98 <= 0;
VAR157 <= 0; VAR140 <= 0; VAR102 <= 0; VAR64 <= 0;
VAR113 <= 0; VAR14 <= 0; VAR22 <= 0; VAR137 <= 0; VAR190 <= 0; VAR97 <= 0;
VAR138 <= 0; VAR143 <= 0; VAR171 <= 0; VAR81 <= 0;
VAR121 <= 0; VAR136 <= 0; VAR204 <= 0; VAR46 <= 0; VAR161 <= 0;
VAR31 <= 0; VAR122 <= 0; VAR179 <= 0; VAR82 <= 0; VAR107 <= 0;
VAR63 <= 0; VAR126 <= 0; VAR124 <= 0; VAR8 <= 0; VAR87 <= 0;
VAR127 <= 0; VAR23 <= 0; VAR128 <= 0; VAR194 <= 0; VAR88 <= 0;
VAR206 <= 0; VAR37 <= 0; VAR185 <= 0; VAR189 <= 0;
VAR62 <= 0; VAR191 <= 0; VAR52 <= 0; VAR40 <= 0; VAR2 <= 0; VAR17 <= 0;
VAR57 <= 0; VAR4 <= 0; VAR6 <= 0; VAR3 <= 0;
VAR84 <= 0; VAR38 <= 0; VAR163 <= 0; VAR5 <= 0; VAR15 <= 0;
VAR182 <= 0; VAR199 <= 0; VAR123 <= 0; VAR51 <= 0; VAR21 <= 0;
VAR27 <= 0; VAR90 <= 0; VAR86 <= 0;
VAR75 <= 0; VAR11 <= 0; VAR49 <= 0; VAR71 <= 0; VAR54 <= 0;
VAR166 <= 0; VAR156 <= 0; VAR211 <= 0; VAR188 <= 0;
VAR83 <= 0; VAR30 <= 0;
VAR78 <= 0; VAR85 <= 0;
VAR184 <= 0; VAR114 <= 0;
VAR76 <= 0; VAR7 <= 0;
VAR134 <= 0; VAR154 <= 0;
VAR209 <= 0; VAR56 <= 0; VAR72 <= 0;
VAR28 <= 0;
VAR12 <= 0; VAR20 <= 0;
VAR61 <= 0; VAR207 <= 0;
VAR25 <= 0; VAR53 <= 0; VAR66 <= 0; VAR174 <= 0;
VAR165 <= 0; VAR67 <= 0; VAR197 <= 0;
VAR79 <= 0; VAR77 <= 0;
VAR132 <= 0; VAR205 <= 0; VAR183 <= 0;
VAR135 <= 0;
sum <= 0; VAR32 <= 0; VAR24 <= 0; VAR101 <= 0; VAR111 <= 0;
VAR149 <= 0; VAR95 <= 0; VAR164 <= 0; VAR150 <= 0; VAR18 <= 0; VAR13 <= 0;
VAR112 <= 0; VAR147 <= 0; VAR94 <= 0; VAR158 <= 0;
VAR196 <= 0; VAR74 <= 0; VAR186 <= 0; VAR106 <= 0;
VAR145 <= 0; VAR70 <= 0; VAR212 <= 0; VAR68 <= 0;
VAR152 <= 0; VAR192 <= 0; VAR44 <= 0;
VAR177 <= 0; VAR180 <= 0; VAR10 <= 0;
VAR100 <= 0; VAR120 <= 0; VAR65 <= 0; VAR139 <= 0; VAR151 <= 0; VAR148 <= 0;
VAR172 <= 0; VAR131 <= 0;
VAR47 <= 0; VAR116 <= 0; VAR104 <= 0;
VAR50 <= 0; VAR91 <= 0; VAR43 <= 0; VAR69 <= 0;
VAR210 <= 0; VAR167 <= 0; VAR16 <= 0; VAR195 <= 0;
VAR45 <= 0; VAR193 <= 0; VAR214 <= 0; VAR105 <= 0;
VAR42 <= 0; VAR142 <= 0; VAR160 <= 0; VAR168 <= 0;
VAR103 <= 0; VAR208 <= 0; VAR92 <= 0;
end
else if (enable) begin
VAR115 <= VAR200; VAR1 <= VAR115 ^ (VAR141 ^ VAR129);
VAR125 <= VAR1; VAR59 <= VAR125; VAR33 <= VAR59;
VAR213 <= VAR33; VAR55 <= VAR213; VAR181 <= VAR55; VAR9 <= VAR181;
VAR39 <= VAR9; VAR80 <= VAR39; VAR26 <= VAR80; VAR162 <= VAR26;
VAR34 <= VAR162; VAR118 <= VAR34; VAR93 <= VAR118;
VAR117 <= VAR93; VAR178 <= VAR117; VAR108 <= VAR178;
VAR58 <= VAR108; VAR29 <= VAR58; VAR159 <= VAR29;
VAR169 <= VAR115; VAR173 <= VAR169;
VAR176 <= VAR153; VAR144 <= VAR176; VAR146 <= VAR144; VAR96 <= VAR146;
VAR36 <= VAR96; VAR175 <= VAR36; VAR41 <= VAR175; VAR203 <= VAR41; VAR48 <= VAR203;
VAR119 <= VAR48; VAR89 <= VAR119; VAR187 <= VAR89; VAR73 <= VAR187;
VAR60 <= VAR73; VAR99 <= VAR60; VAR201 <= VAR99;
VAR141 <= VAR133[63]; VAR129 <= VAR198[63]; VAR130 <= VAR141;
VAR19 <= VAR129; VAR155 <= VAR130; VAR98 <= VAR19;
VAR157 <= VAR133[62:52]; VAR102 <= VAR157; VAR64 <= VAR102;
VAR140 <= VAR198[62:52]; VAR113 <= VAR140; VAR14 <= VAR113;
VAR22 <= VAR133[51:0]; VAR190 <= VAR22; VAR97 <= VAR190;
VAR137 <= VAR198[51:0]; VAR138 <= VAR137; VAR143 <= VAR138;
VAR171 <= VAR157 == 2047;
VAR81 <= VAR140 == 2047;
VAR121 <= VAR171 | VAR81; VAR136 <= VAR121;
VAR204 <= VAR136; VAR46 <= VAR204; VAR161 <= VAR46; VAR31 <= VAR161;
VAR122 <= VAR31; VAR179 <= VAR122; VAR82 <= VAR179; VAR107 <= VAR82;
VAR63 <= VAR107; VAR126 <= VAR63; VAR124 <= VAR126;
VAR8 <= VAR124; VAR87 <= VAR8; VAR127 <= VAR87;
VAR23 <= VAR127; VAR128 <= VAR23; VAR194 <= VAR128;
VAR88 <= VAR194; VAR206 <= VAR88;
VAR37 <= VAR157 > VAR140;
VAR185 <= VAR157 == VAR140;
VAR189 <= VAR22 >= VAR137;
VAR62 <= VAR37 | (VAR185 & VAR189);
VAR191 <= VAR62 ? VAR155 :!VAR98 ^ (VAR173 == 0);
VAR52 <= VAR191; VAR40 <= VAR52; VAR2 <= VAR40; VAR17 <= VAR2;
VAR57 <= VAR17; VAR4 <= VAR57; VAR6 <= VAR4; VAR3 <= VAR6;
VAR84 <= VAR3; VAR38 <= VAR84; VAR163 <= VAR38;
VAR5 <= VAR163; VAR15 <= VAR5; VAR182 <= VAR15;
VAR199 <= VAR182; VAR123 <= VAR199; VAR51 <= VAR123;
VAR21 <= VAR51;
VAR27 <= VAR62 ? VAR14 : VAR64;
VAR90 <= VAR62 ? VAR64 : VAR14;
VAR86 <= VAR90; VAR75 <= VAR86; VAR11 <= VAR75;
VAR49 <= VAR11; VAR71 <= VAR49; VAR54 <= VAR71; VAR166 <= VAR54;
VAR156 <= VAR166; VAR211 <= VAR156; VAR188 <= VAR211;
VAR83 <= VAR27 == 0;
VAR30 <= VAR90 == 0;
VAR78 <= VAR83;
VAR85 <= VAR30;
VAR184 <= VAR62 ? VAR143 : VAR97;
VAR114 <= VAR62 ? VAR97 : VAR143;
VAR76 <= VAR184;
VAR7 <= VAR114;
VAR134 <= VAR83 ? 0 : VAR76;
VAR154 <= VAR30 ? 0 : VAR7;
VAR209 <= VAR90 - VAR27;
VAR56 <= VAR209;
VAR72 <= VAR56;
VAR28 <= VAR83 ? 108'b0 : { 1'b1, VAR76, 55'b0 };
VAR12 <= VAR28 >> VAR56;
VAR20 <= |VAR12[52:0];
VAR61 <= { 1'b0, !VAR85, VAR154, 2'b0};
VAR207 <= VAR61; VAR25 <= VAR207;
VAR53 <= VAR25; VAR66 <= VAR53;
VAR174 <= { 1'b0, !VAR78, VAR134, 2'b0};
VAR165 <= VAR174 >> VAR72;
VAR67 <= { VAR165[55:1], (VAR20 | VAR165[0]) };
VAR197 <= VAR67;
VAR135 <= VAR183 & !VAR77;
VAR79 <= VAR135 ? VAR110 : VAR197;
VAR77 <= |VAR165[54:0];
VAR132 <= !VAR78;
VAR205 <= VAR132; VAR183 <= VAR205;
sum <= VAR66 + VAR79;
VAR24 <= sum[55];
VAR32 <= sum; VAR94 <= sum[0];
VAR101 <= VAR24 ? VAR32 >> 1 : VAR32; VAR158 <= VAR94;
VAR111 <= { VAR101[55:1], VAR158 | VAR101[0] };
VAR149 <= VAR111; VAR95 <= VAR149; VAR164 <= VAR95; VAR150 <= VAR164;
VAR196 <= VAR24 ? VAR211 + 1: VAR211;
VAR74 <= VAR196;
VAR192 <= VAR35;
VAR44 <= VAR66 - VAR79; VAR10 <= VAR44; VAR100 <= VAR10;
VAR177 <= VAR35 > VAR211;
VAR180 <= VAR192 == 55;
VAR120 <= VAR177 ? VAR100 << VAR188 : VAR100 << VAR192;
VAR65 <= VAR120; VAR139 <= VAR65; VAR151 <= VAR139; VAR148 <= VAR151;
VAR104 <= VAR177 ? 0 : (VAR188 - VAR192);
VAR50 <= VAR180 ? 0 : VAR104;
VAR45 <= VAR201 == 2'b00;
VAR193 <= VAR201 == 2'b10;
VAR214 <= VAR201 == 2'b11;
VAR105 <= VAR93 ? VAR65[1] : VAR149[1];
VAR42 <= VAR93 ? !VAR65[0] & !VAR65[2] : !VAR149[0] & !VAR149[2];
VAR142 <= VAR45 & VAR105 & !VAR42;
VAR160 <= VAR93 ? |VAR65[1:0] & !VAR5 : |VAR149[1:0] & !VAR5;
VAR168 <= VAR193 & VAR160;
VAR103 <= VAR93 ? |VAR65[1:0] & VAR5 : |VAR149[1:0] & VAR5;
VAR208 <= VAR214 & VAR103;
VAR92 <= VAR168 | VAR208 | VAR142;
VAR18 <= VAR92 ? VAR150 + 4 : VAR150;
VAR147 <= VAR18[55]; VAR13 <= VAR18;
VAR112 <= VAR147 ? VAR13 >> 1 : VAR13;
VAR172 <= VAR92 ? VAR148 + 4 : VAR148;
VAR116 <= VAR172[55]; VAR131 <= VAR172;
VAR47 <= VAR116 ? VAR131 >> 1 : VAR131;
VAR186 <= VAR74; VAR106 <= VAR186; VAR145 <= VAR106;
VAR70 <= VAR145; VAR212 <= VAR70; VAR68 <= VAR212;
VAR152 <= VAR147 ? VAR68 + 1 : VAR68;
VAR91 <= VAR50; VAR43 <= VAR91; VAR69 <= VAR43;
VAR210 <= VAR69; VAR167 <= VAR210;
VAR16 <= VAR116 ? VAR167 + 1 : VAR167;
VAR195 <= VAR159 ? {VAR21, VAR16, VAR47[53:2]} : {VAR21, VAR152, VAR112[53:2]};
end
end
always @(posedge clk)
casex(VAR44[54:0])
55'b1??????????????????????????????????????????????????????: VAR35 <= 0;
55'b01?????????????????????????????????????????????????????: VAR35 <= 1;
55'b001????????????????????????????????????????????????????: VAR35 <= 2;
55'b0001???????????????????????????????????????????????????: VAR35 <= 3;
55'b00001??????????????????????????????????????????????????: VAR35 <= 4;
55'b000001?????????????????????????????????????????????????: VAR35 <= 5;
55'b0000001????????????????????????????????????????????????: VAR35 <= 6;
55'b00000001???????????????????????????????????????????????: VAR35 <= 7;
55'b000000001??????????????????????????????????????????????: VAR35 <= 8;
55'b0000000001?????????????????????????????????????????????: VAR35 <= 9;
55'b00000000001????????????????????????????????????????????: VAR35 <= 10;
55'b000000000001???????????????????????????????????????????: VAR35 <= 11;
55'b0000000000001??????????????????????????????????????????: VAR35 <= 12;
55'b00000000000001?????????????????????????????????????????: VAR35 <= 13;
55'b000000000000001????????????????????????????????????????: VAR35 <= 14;
55'b0000000000000001???????????????????????????????????????: VAR35 <= 15;
55'b00000000000000001??????????????????????????????????????: VAR35 <= 16;
55'b000000000000000001?????????????????????????????????????: VAR35 <= 17;
55'b0000000000000000001????????????????????????????????????: VAR35 <= 18;
55'b00000000000000000001???????????????????????????????????: VAR35 <= 19;
55'b000000000000000000001??????????????????????????????????: VAR35 <= 20;
55'b0000000000000000000001?????????????????????????????????: VAR35 <= 21;
55'b00000000000000000000001????????????????????????????????: VAR35 <= 22;
55'b000000000000000000000001???????????????????????????????: VAR35 <= 23;
55'b0000000000000000000000001??????????????????????????????: VAR35 <= 24;
55'b00000000000000000000000001?????????????????????????????: VAR35 <= 25;
55'b000000000000000000000000001????????????????????????????: VAR35 <= 26;
55'b0000000000000000000000000001???????????????????????????: VAR35 <= 27;
55'b00000000000000000000000000001??????????????????????????: VAR35 <= 28;
55'b000000000000000000000000000001?????????????????????????: VAR35 <= 29;
55'b0000000000000000000000000000001????????????????????????: VAR35 <= 30;
55'b00000000000000000000000000000001???????????????????????: VAR35 <= 31;
55'b000000000000000000000000000000001??????????????????????: VAR35 <= 32;
55'b0000000000000000000000000000000001?????????????????????: VAR35 <= 33;
55'b00000000000000000000000000000000001????????????????????: VAR35 <= 34;
55'b000000000000000000000000000000000001???????????????????: VAR35 <= 35;
55'b0000000000000000000000000000000000001??????????????????: VAR35 <= 36;
55'b00000000000000000000000000000000000001?????????????????: VAR35 <= 37;
55'b000000000000000000000000000000000000001????????????????: VAR35 <= 38;
55'b0000000000000000000000000000000000000001???????????????: VAR35 <= 39;
55'b00000000000000000000000000000000000000001??????????????: VAR35 <= 40;
55'b000000000000000000000000000000000000000001?????????????: VAR35 <= 41;
55'b0000000000000000000000000000000000000000001????????????: VAR35 <= 42;
55'b00000000000000000000000000000000000000000001???????????: VAR35 <= 43;
55'b000000000000000000000000000000000000000000001??????????: VAR35 <= 44;
55'b0000000000000000000000000000000000000000000001?????????: VAR35 <= 45;
55'b00000000000000000000000000000000000000000000001????????: VAR35 <= 46;
55'b000000000000000000000000000000000000000000000001???????: VAR35 <= 47;
55'b0000000000000000000000000000000000000000000000001??????: VAR35 <= 48;
55'b00000000000000000000000000000000000000000000000001?????: VAR35 <= 49;
55'b000000000000000000000000000000000000000000000000001????: VAR35 <= 50;
55'b0000000000000000000000000000000000000000000000000001???: VAR35 <= 51;
55'b00000000000000000000000000000000000000000000000000001??: VAR35 <= 52;
55'b000000000000000000000000000000000000000000000000000001?: VAR35 <= 53;
55'b0000000000000000000000000000000000000000000000000000001: VAR35 <= 54;
55'b0000000000000000000000000000000000000000000000000000000: VAR35 <= 55;
endcase
always @(posedge clk)
begin
if (rst) begin
ready <= 0;
VAR202 <= 0;
VAR109 <= 0;
end
else if (enable) begin
ready <= VAR109;
VAR202 <= VAR170 == 21;
VAR109 <= VAR170 == 22;
end
end
always @(posedge clk)
begin
if (rst)
VAR170 <= 0;
end
else if (enable & !VAR202 & !VAR109)
VAR170 <= VAR170 + 1;
end
always @(posedge clk)
begin
if (rst)
out <= 0;
end
else if (enable & VAR109)
out <= VAR206 ? { VAR195[63], 11'b11111111111, 52'b0 } : VAR195;
end
endmodule
|
gpl-3.0
|
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