repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/or2/sky130_fd_sc_ms__or2_1.v
| 2,075 |
module MODULE2 (
VAR1 ,
VAR8 ,
VAR2 ,
VAR3,
VAR5,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR4 ;
VAR9 VAR6 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR8,
VAR2
);
output VAR1;
input VAR8;
input VAR2;
supply1 VAR3;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR4 ;
VAR9 VAR6 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.functional.pp.v
| 2,230 |
module MODULE1 (
VAR10,
VAR8 ,
VAR13,
VAR14 ,
VAR23,
VAR4,
VAR1 ,
VAR16
);
output VAR10;
input VAR8 ;
input VAR13;
input VAR14 ;
input VAR23;
input VAR4;
input VAR1 ;
input VAR16 ;
wire VAR22 ;
wire VAR12 ;
wire VAR18 ;
wire VAR15 ;
wire VAR19 ;
wire VAR17 ;
wire VAR11;
wire VAR2 ;
not VAR3 (VAR12 , VAR22 );
not VAR6 (VAR18 , VAR14 );
nor VAR9 (VAR2, VAR13, VAR8 );
VAR21 VAR20 VAR7 (VAR22 , VAR2, VAR18, , VAR23, VAR4);
and VAR5 (VAR10 , VAR12, VAR14 );
endmodule
|
apache-2.0
|
dimitdim/pineapple
|
veriloge/inputconditioner.v
| 2,798 |
module MODULE1(clk, VAR9, VAR8, VAR13, VAR14);
output reg VAR8 = 0;
output reg VAR13 = 0;
output reg VAR14 = 0;
input clk, VAR9;
parameter VAR6 = 5;
parameter VAR1 = 10;
reg[VAR6-1:0] counter = 0;
reg VAR3 = 0;
reg VAR10 = 0;
always @(posedge clk) begin
if (VAR8 == VAR10) begin
counter <= 0;
VAR13 <= 0;
VAR14 <= 0;
end else begin
if (counter == VAR1) begin
counter <= 0;
VAR8 <= VAR10;
if (VAR10 == 1) begin
VAR13 <= 1;
end else begin
VAR14 <= 1;
end
end else begin
counter <= counter + 1;
end
end
VAR10 = VAR3;
VAR3 = VAR9;
end
endmodule
module MODULE2;
wire VAR8;
wire VAR2;
wire VAR12;
reg VAR7, clk;
reg VAR4;
always @(posedge clk) VAR4=VAR2;
MODULE1 MODULE1(clk, VAR7, VAR8, VAR2, VAR12);
VAR5 clk=0;
always clk=!clk;
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/and4/sky130_fd_sc_hd__and4.symbol.v
| 1,288 |
module MODULE1 (
input VAR7,
input VAR6,
input VAR9,
input VAR4,
output VAR5
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.functional.pp.v
| 1,868 |
module MODULE1 (
VAR4 ,
VAR3 ,
VAR9,
VAR12,
VAR8 ,
VAR7
);
output VAR4 ;
input VAR3 ;
input VAR9;
input VAR12;
input VAR8 ;
input VAR7 ;
wire VAR10 ;
wire VAR1;
buf VAR5 (VAR10 , VAR3 );
VAR6 VAR11 (VAR1, VAR10, VAR9, VAR12);
buf VAR2 (VAR4 , VAR1 );
endmodule
|
apache-2.0
|
ptracton/wb_soc_template
|
rtl/wb_ram/rtl/verilog/wb_ram_xilinx.v
| 2,089 |
module MODULE1 (
dout,
clk, rst, VAR1, din, VAR3, VAR2
) ;
input clk;
input rst;
input [3:0] VAR1;
input [31:0] din;
input [14:0] VAR3;
input [14:0] VAR2;
output wire [31:0] dout;
|
mit
|
linuxbest/lzs
|
common/synchronizer_flop.v
| 5,230 |
module MODULE1 (
VAR6, VAR1, VAR3, VAR2
);
parameter VAR4 = 1 ;
parameter VAR5 = 0 ;
input [VAR4-1:0] VAR6;
input VAR1;
output [VAR4-1:0] VAR3;
input VAR2;
reg [VAR4-1:0] VAR3;
always @(posedge VAR1 or posedge VAR2)
begin
if (VAR2 == 1'b1)
begin
VAR3 <= VAR5;
end
else
begin
VAR3 <= VAR6;
end
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.v
| 2,034 |
module MODULE2 (
VAR2 ,
VAR3 ,
VAR7,
VAR4,
VAR5 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR7;
input VAR4;
input VAR5 ;
input VAR1 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR7;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
markusC64/1541ultimate2
|
fpga/nios_dut/nios_dut/synthesis/submodules/descriptor_buffers.v
| 18,736 |
module MODULE1 (
clk,
reset,
VAR17,
write,
VAR57,
VAR73,
VAR5,
VAR60,
VAR55,
VAR9,
VAR28,
VAR79,
VAR81,
VAR62,
VAR80,
VAR93,
VAR21,
VAR50,
VAR22,
VAR84,
VAR91,
VAR52,
VAR31,
VAR11,
VAR69
);
parameter VAR26 = 0;
parameter VAR88 = 256;
parameter VAR76 = 32;
parameter VAR70 = 128;
parameter VAR96 = 7;
input clk;
input reset;
input [VAR88-1:0] VAR17;
input write;
input [VAR76-1:0] VAR57;
output wire VAR73;
output wire VAR5;
input VAR60;
output wire [255:0] VAR55;
output wire VAR9;
output wire VAR28;
output wire [VAR96:0] VAR79;
output wire VAR81;
input VAR62;
output wire [255:0] VAR80;
output wire VAR93;
output wire VAR21;
output wire [VAR96:0] VAR50;
input VAR22;
input VAR84;
input VAR91;
output wire [31:0] VAR52;
output wire VAR31;
output wire VAR11;
output wire [7:0] VAR69;
reg VAR14;
reg VAR75;
reg VAR25;
reg VAR85;
wire VAR86;
wire VAR83;
wire VAR2;
wire VAR74;
wire VAR27;
wire VAR24;
wire VAR94; wire VAR54;
wire VAR49; wire [VAR88-1:0] VAR68;
wire [VAR88-1:0] VAR53;
wire [15:0] VAR13;
reg [15:0] VAR63;
wire [15:0] VAR95;
reg [15:0] VAR66;
wire VAR15;
reg VAR18;
wire VAR90;
reg VAR34;
wire VAR20;
reg VAR3;
wire [7:0] VAR89;
reg [7:0] VAR40;
wire VAR71; wire VAR29; wire VAR7;
wire [63:0] VAR77;
wire [31:0] VAR23;
wire [7:0] VAR32;
wire VAR58;
wire VAR45;
wire [7:0] VAR56;
wire [15:0] VAR67;
wire [7:0] VAR35;
wire VAR10;
wire [63:0] VAR12;
wire [31:0] VAR8;
wire VAR30;
wire [7:0] VAR59;
wire [15:0] VAR82;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR63 <= 0;
VAR34 <= 0;
VAR3 <= 0;
VAR40 <= 0;
end
else if (VAR71) begin
VAR63 <= VAR13;
VAR34 <= VAR90;
VAR3 <= VAR20;
VAR40 <= VAR89;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR66 <= 0;
VAR18 <= 0;
end
else if (VAR29) begin
VAR66 <= VAR95;
VAR18 <= VAR15;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR14 <= 0;
VAR75 <= 0;
VAR25 <= 0;
VAR85 <= 0;
end
else
begin
VAR14 <= VAR93;
VAR75 <= VAR14;
VAR25 <= VAR9;
VAR85 <= VAR25;
end
end
VAR43 VAR78 (
.VAR1 (VAR68),
.VAR16 (VAR80),
.VAR12 (VAR12),
.VAR8 (VAR8),
.VAR54 (VAR54),
.VAR30 (VAR30),
.VAR90 (VAR90),
.VAR20 (VAR20),
.VAR89 (VAR89),
.VAR59 (VAR59),
.VAR82 (VAR82),
.VAR13 (VAR13),
.VAR46 (VAR84),
.VAR64 (VAR91)
);
VAR51 VAR4 (
.VAR87 (VAR53),
.VAR6 (VAR55),
.VAR77 (VAR77),
.VAR23 (VAR23),
.VAR32 (VAR32),
.VAR58 (VAR58),
.VAR45 (VAR45),
.VAR24 (VAR24),
.VAR15 (VAR15),
.VAR56 (VAR56),
.VAR67 (VAR67),
.VAR95 (VAR95),
.VAR35 (VAR35),
.VAR10 (VAR10),
.VAR37 (VAR84),
.VAR65 (VAR91)
);
VAR33 VAR48 (
.clk (clk),
.VAR92 (reset),
.VAR42 (VAR91),
.VAR17 (VAR17),
.VAR19 (VAR57),
.write (VAR7),
.VAR41 (VAR2),
.VAR61 (VAR53),
.VAR38 (VAR74),
.VAR36 (VAR79), .VAR47 (VAR28),
.VAR72 (VAR9)
);
VAR33 VAR39 (
.clk (clk),
.VAR92 (reset),
.VAR42 (VAR91),
.VAR17 (VAR17),
.VAR19 (VAR57),
.write (VAR7),
.VAR41 (VAR86),
.VAR61 (VAR68),
.VAR38 (VAR83),
.VAR36 (VAR50), .VAR47 (VAR21),
.VAR72 (VAR93)
);
generate if (VAR26 == 0) begin
assign VAR73 = (VAR28 == 1) | (VAR21 == 1) | (VAR91 == 1);
assign VAR52 = {VAR63, VAR66};
assign VAR31 = VAR34;
assign VAR11 = 1'b0;
assign VAR69 = 8'h00;
assign VAR2 = VAR27;
assign VAR94 = (VAR24 == 1) & (VAR79 == 1); assign VAR5 = (VAR84 == 0) & (VAR91 == 0) & (VAR22 == 0) &
(VAR9 == 0) & (VAR25 == 0) & (VAR85 == 0); assign VAR29 = (VAR5 == 1) & (VAR60 == 1);
assign VAR74 = (VAR29 == 1) & (VAR94 == 0);
assign VAR86 = VAR27;
assign VAR49 = (VAR54 == 1) & (VAR50 == 1); assign VAR81 = (VAR84 == 0) & (VAR91 == 0) & (VAR22 == 0) &
(VAR93 == 0) & (VAR14 == 0) & (VAR75 == 0); assign VAR71 = (VAR81 == 1) & (VAR62 == 1);
assign VAR83 = (VAR71 == 1) & (VAR49 == 0); end
else if (VAR26 == 1) begin
assign VAR52 = {16'h0000, VAR66};
assign VAR31 = VAR18;
assign VAR11 = 1'b0;
assign VAR69 = 8'h00;
assign VAR73 = (VAR28 == 1) | (VAR91 == 1);
assign VAR2 = VAR27;
assign VAR94 = (VAR24 == 1) & (VAR79 == 1); assign VAR5 = (VAR84 == 0) & (VAR91 == 0) & (VAR22 == 0) &
(VAR9 == 0) & (VAR25 == 0) & (VAR85 == 0); assign VAR29 = (VAR5 == 1) & (VAR60 == 1);
assign VAR74 = (VAR29 == 1) & (VAR94 == 0);
assign VAR86 = 0;
assign VAR49 = 0;
assign VAR81 = 0;
assign VAR71 = 0;
assign VAR83 = 0;
end
else begin
assign VAR52 = {VAR63, 16'h0000};
assign VAR31 = VAR34;
assign VAR11 = VAR3;
assign VAR69 = VAR40;
assign VAR73 = (VAR21 == 1) | (VAR91 == 1);
assign VAR2 = 0;
assign VAR94 = 0;
assign VAR5 = 0;
assign VAR29 = 0;
assign VAR74 = 0;
assign VAR86 = VAR27;
assign VAR49 = (VAR54 == 1) & (VAR50 == 1); assign VAR81 = (VAR84 == 0) & (VAR91 == 0) & (VAR22 == 0) &
(VAR93 == 0) & (VAR14 == 0) & (VAR75 == 0); assign VAR71 = (VAR81 == 1) & (VAR62 == 1);
assign VAR83 = (VAR71 == 1) & (VAR49 == 0); end
endgenerate
generate if (VAR88 == 256)
begin
assign VAR27 = (VAR17[255] == 1) & (write == 1) & (VAR57[31] == 1) & (VAR73 == 0);
end
else
begin
assign VAR27 = (VAR17[127] == 1) & (write == 1) & (VAR57[15] == 1) & (VAR73 == 0);
end
endgenerate
assign VAR7 = (write == 1) & (VAR73 == 0);
endmodule
|
gpl-3.0
|
HeTpro/Verilog
|
S4/S4L2.v
| 1,988 |
module MODULE1(VAR14, VAR3, VAR2, VAR6,VAR5);
input VAR14; output reg VAR3;
output reg [6:0] VAR2 = 7'h3F; output reg VAR6 = 0; output reg [3:0] VAR5 = 0; reg [25:0] VAR15 = 0; parameter [6:0] VAR12 = ~7'h3F;
parameter [6:0] VAR11 = ~7'h06;
parameter [6:0] VAR16 = ~7'h5B;
parameter [6:0] VAR9 = ~7'h4F;
parameter [6:0] VAR13 = ~7'h66;
parameter [6:0] VAR4 = ~7'h6D;
parameter [6:0] VAR8 = ~7'h7D;
parameter [6:0] VAR10 = ~7'h07;
parameter [6:0] VAR7 = ~7'h7F;
parameter [6:0] VAR1 = ~7'h6F;
parameter [6:0] ha = ~7'h77;
parameter [6:0] hb = ~7'h7C;
parameter [6:0] hc = ~7'h39;
parameter [6:0] hd = ~7'h5E;
parameter [6:0] he = ~7'h79;
parameter [6:0] hf = ~7'h71;
always @(posedge VAR14)
begin
VAR15 = VAR15 + 1;
if(VAR15 == 25000000)
begin
VAR3 = ~VAR3; VAR15 = 0; end
end
always @(posedge VAR3)
begin
case(VAR5)
0: VAR5 <= 1;
1: VAR5 <= 2;
2: VAR5 <= 3;
3: VAR5 <= 4;
4: VAR5 <= 5;
5: VAR5 <= 6;
6: VAR5 <= 7;
7: VAR5 <= 8;
8: VAR5 <= 9;
9: VAR5 <= 10;
10: VAR5 <= 11;
11: VAR5 <= 12;
12: VAR5 <= 13;
13: VAR5 <= 14;
14: VAR5 <= 15;
15: VAR5 <= 0;
endcase
end
always @(VAR5)
begin
case(VAR5)
0: VAR2 = VAR12;
1: VAR2 = VAR11;
2: VAR2 = VAR16;
3: VAR2 = VAR9;
4: VAR2 = VAR13;
5: VAR2 = VAR4;
6: VAR2 = VAR8;
7: VAR2 = VAR10;
8: VAR2 = VAR7;
9: VAR2 = VAR1;
10: VAR2 = ha;
11: VAR2 = hb;
12: VAR2 = hc;
13: VAR2 = hd;
14: VAR2 = he;
15: VAR2 = hf;
endcase
end
endmodule
|
unlicense
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.v
| 2,437 |
module MODULE2 (
VAR7 ,
VAR9 ,
VAR5 ,
VAR11 ,
VAR10 ,
VAR3 ,
VAR8 ,
VAR6,
VAR2
);
output VAR7 ;
output VAR9 ;
input VAR5 ;
input VAR11 ;
input VAR10 ;
input VAR3 ;
input VAR8 ;
input VAR6;
input VAR2;
VAR4 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR7 ,
VAR9,
VAR5,
VAR11 ,
VAR10 ,
VAR3,
VAR8
);
output VAR7 ;
output VAR9;
input VAR5;
input VAR11 ;
input VAR10 ;
input VAR3;
input VAR8;
supply1 VAR6;
supply0 VAR2;
VAR4 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
tommythorn/yari
|
shared/rtl/target/niosdevkit-1c20/pll.v
| 16,155 |
module MODULE1 (
VAR37,
VAR17,
VAR65,
VAR80);
input VAR37;
output VAR17;
output VAR65;
output VAR80;
wire [5:0] VAR25;
wire VAR30;
wire [3:0] VAR48;
wire [0:0] VAR60 = 1'h0;
wire [0:0] VAR79 = VAR25[0:0];
wire VAR17 = VAR79;
wire VAR80 = VAR30;
wire [0:0] VAR22 = VAR48[0:0];
wire VAR65 = VAR22;
wire VAR11 = VAR37;
wire [1:0] VAR77 = {VAR60, VAR11};
VAR58 VAR92 (
.VAR93 (VAR77),
.clk (VAR25),
.VAR80 (VAR30),
.VAR66 (VAR48),
.VAR2 (),
.VAR31 (1'b0),
.VAR64 (),
.VAR101 ({6{1'b1}}),
.VAR14 (),
.VAR6 (1'b0),
.VAR72 (1'b0),
.VAR50 (),
.VAR49 (),
.VAR57 ({4{1'b1}}),
.VAR42 (1'b1),
.VAR41 (),
.VAR97 (),
.VAR28 (1'b1),
.VAR8 ({4{1'b1}}),
.VAR82 (),
.VAR7 (1'b1),
.VAR54 (1'b1),
.VAR20 (1'b1),
.VAR81 (1'b0),
.VAR26 (1'b0),
.VAR100 (1'b1),
.VAR52 (1'b0),
.VAR84 (),
.VAR63 (),
.VAR9 (1'b0),
.VAR96 (1'b0),
.VAR71 (),
.VAR73 (),
.VAR35 (),
.VAR33 ());
VAR92.VAR12 = 10,
VAR92.VAR69 = 50,
VAR92.VAR43 = 9,
VAR92.VAR10 = "0",
VAR92.VAR24 = "VAR34",
VAR92.VAR90 = 2,
VAR92.VAR5 = 50,
VAR92.VAR99 = 1,
VAR92.VAR107 = "0",
VAR92.VAR59 = 20000,
VAR92.VAR19 = "VAR62",
VAR92.VAR98 = 5,
VAR92.VAR70 = "VAR58",
VAR92.VAR15 = "VAR91",
VAR92.VAR86 = "VAR38",
VAR92.VAR13 = "VAR45",
VAR92.VAR102 = "VAR45",
VAR92.VAR21 = "VAR45",
VAR92.VAR104 = "VAR45",
VAR92.VAR1 = "VAR45",
VAR92.VAR56 = "VAR45",
VAR92.VAR75 = "VAR45",
VAR92.VAR40 = "VAR45",
VAR92.VAR32 = "VAR4",
VAR92.VAR74 = "VAR45",
VAR92.VAR108 = "VAR4",
VAR92.VAR78 = "VAR45",
VAR92.VAR3 = "VAR45",
VAR92.VAR18 = "VAR45",
VAR92.VAR103 = "VAR45",
VAR92.VAR36 = "VAR45",
VAR92.VAR55 = "VAR45",
VAR92.VAR53 = "VAR45",
VAR92.VAR85 = "VAR45",
VAR92.VAR39 = "VAR45",
VAR92.VAR94 = "VAR45",
VAR92.VAR95 = "VAR45",
VAR92.VAR27 = "VAR45",
VAR92.VAR76 = "VAR45",
VAR92.VAR44 = "VAR45",
VAR92.VAR83 = "VAR4",
VAR92.VAR51 = "VAR45",
VAR92.VAR16 = "VAR45",
VAR92.VAR89 = "VAR45",
VAR92.VAR68 = "VAR45",
VAR92.VAR46 = "VAR45",
VAR92.VAR67 = "VAR45",
VAR92.VAR61 = "VAR45",
VAR92.VAR23 = "VAR45",
VAR92.VAR47 = "VAR45",
VAR92.VAR105 = "VAR4",
VAR92.VAR106 = "VAR45",
VAR92.VAR87 = "VAR45",
VAR92.VAR29 = "VAR45",
VAR92.VAR88 = 1;
endmodule
|
gpl-2.0
|
Saucyz/explode
|
Hardware/Mod2/nios_system/synthesis/submodules/nios_system_audio_config.v
| 16,103 |
module MODULE1 (
clk,
reset,
address,
VAR28,
read,
write,
VAR56,
VAR60,
VAR16,
VAR37,
irq,
VAR62,
VAR72
);
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] VAR28;
input read;
input write;
input [31: 0] VAR56;
inout VAR60;
output reg [31: 0] VAR16;
output VAR37;
output irq;
output VAR62;
output VAR72;
localparam VAR41 = 26;
localparam VAR45 = 8'h02;
localparam VAR13 = {8'h00, 1'b1, 8'hFF, 1'b0, 8'h00, 1'b1};
localparam VAR66 = {8'h00, 1'b1, 8'h00, 1'b1, 8'h00, 1'b1};
localparam VAR24 = 'h9;
localparam VAR63 = 50; localparam VAR17 = 5;
localparam VAR55 = 9'h01A;
localparam VAR18 = 9'h01A;
localparam VAR39 = 9'h07B;
localparam VAR50 = 9'h07B;
localparam VAR9 = 9'd149;
localparam VAR69 = 9'h006;
localparam VAR34 = 9'h000;
localparam VAR59 = 9'd65;
localparam VAR76 = 9'd24;
localparam VAR47 = 9'h001;
localparam VAR53 = 4; localparam VAR2 = 11;
localparam VAR31 = 3'h0,
VAR30 = 3'h1,
VAR77 = 3'h2,
VAR19 = 3'h3,
VAR29 = 3'h4,
VAR64 = 3'h5,
VAR74 = 3'h6;
wire VAR46;
wire [VAR17:0] VAR10;
wire [VAR41: 0] VAR68;
wire ack;
wire [VAR41: 0] VAR49;
wire VAR48;
wire VAR38;
wire VAR20;
wire [VAR41: 0] VAR11;
wire [VAR41: 0] VAR40;
wire [VAR41: 0] VAR23;
wire [VAR41: 0] VAR6;
wire VAR35;
wire VAR32;
reg [31: 0] VAR15;
reg [31: 0] VAR65;
reg [31: 0] VAR43;
reg VAR26;
reg VAR73;
reg [ 7: 0] VAR54;
reg [ 1: 0] VAR42;
reg [ 2: 0] VAR36;
reg [ 2: 0] VAR71;
always @(posedge clk)
begin
if (VAR46)
VAR71 <= VAR31;
end
else
VAR71 <= VAR36;
end
always @(*)
begin
VAR36 = VAR31;
case (VAR71)
VAR31:
begin
if (VAR32 | ~VAR38)
VAR36 = VAR31;
end
else if (write & (address == 2'h3))
VAR36 = VAR30;
end
else if (read & (address == 2'h3))
begin
if (VAR15[17:16] == 2'h0)
VAR36 = VAR74;
end
else
VAR36 = VAR29;
end
else
VAR36 = VAR31;
end
VAR30:
begin
VAR36 = VAR77;
end
VAR77:
begin
if (VAR32)
VAR36 = VAR19;
end
else
VAR36 = VAR77;
end
VAR19:
begin
VAR36 = VAR31;
end
VAR29:
begin
VAR36 = VAR64;
end
VAR64:
begin
if (VAR32)
VAR36 = VAR74;
end
else
VAR36 = VAR64;
end
VAR74:
begin
VAR36 = VAR31;
end
default:
begin
VAR36 = VAR31;
end
endcase
end
always @(posedge clk)
begin
if (VAR46)
VAR16 <= 32'h00000000;
end
else if (read)
begin
if (address == 2'h0)
VAR16 <= VAR15;
end
else if (address == 2'h1)
begin
VAR16 <= {8'h00, VAR45, 7'h00,
VAR38 & ~VAR20, 6'h00,
~VAR26 & VAR38,
ack};
end
else if (address == 2'h2)
VAR16 <= VAR65;
else if (VAR15[17:16] == 2'h0)
VAR16 <= {23'h000000,
VAR6[10],
VAR6[ 8: 1]};
else
VAR16 <= {24'h000000, VAR6[ 8: 1]};
end
end
always @(posedge clk)
begin
if (VAR46)
begin
VAR15 <= 32'h00000000;
VAR65 <= 32'h00000000;
VAR43 <= 32'h00000000;
end
else if (write & ~VAR37)
begin
if ((address == 2'h0) & VAR28[0])
VAR15[ 2: 1] <= VAR56[ 2: 1];
if ((address == 2'h0) & VAR28[2])
VAR15[17:16] <= VAR56[17:16];
if ((address == 2'h2) & VAR28[0])
VAR65[ 7: 0] <= VAR56[ 7: 0];
if ((address == 2'h3) & VAR28[0])
VAR43[ 7: 0] <= VAR56[ 7: 0];
if ((address == 2'h3) & VAR28[1])
VAR43[15: 8] <= VAR56[15: 8];
if ((address == 2'h3) & VAR28[2])
VAR43[23:16] <= VAR56[23:16];
if ((address == 2'h3) & VAR28[3])
VAR43[31:24] <= VAR56[31:24];
end
end
always @(posedge clk)
begin
if (VAR46)
begin
VAR26 <= 1'b0;
VAR73 <= 1'b0;
VAR54 <= 8'h00;
VAR42 <= 2'h0;
end
else if (VAR32)
begin
VAR26 <= 1'b0;
VAR73 <= 1'b0;
VAR54 <= 8'h00;
end
else if (VAR71 == VAR30)
begin
VAR26 <= 1'b1;
VAR73 <= 1'b0;
VAR54 <= VAR65[7:0];
VAR42 <= VAR15[17:16];
end
else if (VAR71 == VAR29)
begin
VAR26 <= 1'b1;
VAR73 <= 1'b1;
VAR54 <= VAR65[7:0];
VAR42 <= VAR15[17:16];
end
end
assign VAR37 =
((address == 2'h3) & write & (VAR71 != VAR30)) |
((address == 2'h3) & read & (VAR71 != VAR74));
assign irq = VAR15[1] & ~VAR26 & VAR38;
assign VAR46 = reset |
((address == 2'h0) & write & VAR28[0] & VAR56[0]);
assign VAR11 = VAR66;
assign VAR40 =
(~VAR38) ?
VAR49 :
(VAR42 == 2'h0) ?
{8'h34, 1'b0,
VAR54[6:0], VAR43[8], 1'b0,
VAR43[7:0], 1'b0} :
(VAR42 == 2'h1) ?
{8'h40, 1'b0,
VAR54[7:0], VAR73,
VAR43[7:0], 1'b0} :
{8'h42, 1'b0,
VAR54[7:0], VAR73,
VAR43[7:0], 1'b0};
assign VAR23 =
(VAR42 == 2'h1) ?
{8'h41, 1'b0, 8'h00, 1'b0, 8'h00, ack} :
{8'h43, 1'b0, 8'h00, 1'b0, 8'h00, ack};
assign VAR35 = (VAR38) ?
VAR26 :
VAR48;
assign ack = VAR6[18] |
VAR6[ 9] |
VAR6[ 0];
VAR25 VAR3 (
.clk (clk),
.reset (VAR46),
.VAR67 (1'b0),
.ack (ack),
.VAR32 (VAR32),
.VAR68 (VAR68),
.VAR22 (VAR49),
.VAR14 (VAR48),
.VAR10 (VAR10),
.VAR38 (VAR38),
.VAR20 (VAR20)
);
VAR3.VAR61 = VAR63,
VAR3.VAR70 = VAR17,
VAR3.VAR41 = VAR41;
VAR52 VAR57 (
.VAR10 (VAR10),
.VAR68 (VAR68)
);
VAR57.VAR55 = VAR55,
VAR57.VAR18 = VAR18,
VAR57.VAR39 = VAR39,
VAR57.VAR50 = VAR50,
VAR57.VAR9 = VAR9,
VAR57.VAR69 = VAR69,
VAR57.VAR34 = VAR34,
VAR57.VAR59 = VAR59,
VAR57.VAR76 = VAR76,
VAR57.VAR47 = VAR47;
VAR57.VAR21 = 16'h0040,
VAR57.VAR8 = 16'h2df4,
VAR57.VAR44 = 16'h2e00;
VAR33 VAR5 (
.clk (clk),
.reset (VAR46),
.VAR35 (VAR35),
.VAR51 (VAR40),
.VAR11 (VAR11),
.VAR7 (VAR24),
.VAR75 (VAR23),
.VAR4 (VAR13),
.VAR1 (VAR60),
.VAR58 (VAR72),
.VAR27 (VAR62),
.VAR22 (VAR6),
.VAR32 (VAR32)
);
VAR5.VAR41 = VAR41,
VAR5.VAR12 = VAR53,
VAR5.VAR2 = VAR2;
endmodule
|
mit
|
darrylring/verilog
|
phase_ramp.v
| 1,312 |
module MODULE1 #
(
parameter integer VAR4 = 16,
parameter integer VAR13 = 13
)
(
input wire VAR9,
input wire VAR14,
input wire VAR12,
input wire [VAR13-1:0] VAR3,
output wire [VAR4-1:0] VAR1,
input wire VAR6,
output wire VAR5
);
reg [VAR13:0] VAR7;
reg [VAR13:0] VAR10;
reg VAR11, VAR2, VAR8;
reg reset;
always @(posedge VAR14) begin
if (~VAR12) begin
reset <= 1'b1;
VAR11 <= 1;
VAR2 <= 1;
VAR8 <= 1;
end else begin
VAR11 <= VAR9;
VAR2 <= VAR11;
VAR8 <= VAR2;
end
end
always @(posedge VAR9) begin
if (reset) begin
VAR7 <= {(VAR13){1'b0}};
VAR10 <= VAR3;
reset <= 1'b0;
end else begin
VAR7 <= VAR10;
VAR10 <= VAR10 + VAR3;
end
end
assign VAR5 = VAR2 && !VAR8;
assign VAR1 = {{(VAR4 - VAR13 - 1){VAR7[VAR13]}}, VAR7};
endmodule
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/small_async_fifo.v
| 6,565 |
module MODULE3
parameter VAR19 = 8,
parameter VAR25 = 3,
parameter VAR27 = 5,
parameter VAR40 = 3
)
(
output VAR6,
output VAR36,
input [VAR19-1:0] VAR26,
input VAR37, VAR29, VAR5,
output [VAR19-1:0] VAR20,
output VAR32,
output VAR1,
input VAR14, VAR18, VAR44
);
wire [VAR25-1:0] VAR12, VAR42;
wire [VAR25:0] VAR35, VAR30, VAR38, VAR8;
MODULE5 #(VAR25) MODULE5 (.VAR38(VAR38), .VAR30(VAR30),
.VAR29(VAR29), .VAR5(VAR5));
MODULE6 #(VAR25) MODULE6 (.VAR8(VAR8), .VAR35(VAR35),
.VAR18(VAR18), .VAR44(VAR44));
MODULE1 #(VAR19, VAR25) MODULE1
(.VAR20(VAR20), .VAR26(VAR26),
.VAR12(VAR12), .VAR42(VAR42),
.VAR15(VAR37), .VAR6(VAR6),
.VAR29(VAR29));
MODULE4 #(.VAR9(VAR25), .VAR40(VAR40))
MODULE4
(.VAR32(VAR32),
.VAR1(VAR1),
.VAR42(VAR42),
.VAR30(VAR30),
.VAR8(VAR8),
.VAR14(VAR14),
.VAR18(VAR18),
.VAR44(VAR44));
MODULE2 #(.VAR9(VAR25), .VAR27(VAR27))
MODULE2
(.VAR6(VAR6),
.VAR36(VAR36),
.VAR12(VAR12),
.VAR35(VAR35),
.VAR38(VAR38),
.VAR37(VAR37),
.VAR29(VAR29),
.VAR5(VAR5));
endmodule
module MODULE5 #(parameter VAR9 = 3)
(output reg [VAR9:0] VAR38,
input [VAR9:0] VAR30,
input VAR29, VAR5);
reg [VAR9:0] VAR21;
always @(posedge VAR29 or negedge VAR5)
if (!VAR5) {VAR38,VAR21} <= 0;
else {VAR38,VAR21} <= {VAR21,VAR30};
endmodule
module MODULE6 #(parameter VAR9 = 3)
(output reg [VAR9:0] VAR8,
input [VAR9:0] VAR35,
input VAR18, VAR44);
reg [VAR9:0] VAR16;
always @(posedge VAR18 or negedge VAR44)
if (!VAR44) {VAR8,VAR16} <= 0;
else {VAR8,VAR16} <= {VAR16,VAR35};
endmodule
module MODULE4
parameter VAR40=3)
(output reg VAR32,
output reg VAR1,
output [VAR9-1:0] VAR42,
output reg [VAR9 :0] VAR30,
input [VAR9 :0] VAR8,
input VAR14, VAR18, VAR44);
reg [VAR9:0] VAR17;
wire [VAR9:0] VAR2, VAR31;
reg [VAR9 :0] VAR34;
integer VAR10;
always @(posedge VAR18 or negedge VAR44)
if (!VAR44) {VAR17, VAR30} <= 0;
else {VAR17, VAR30} <= {VAR31, VAR2};
assign VAR42 = VAR17[VAR9-1:0];
assign VAR31 = VAR17 + (VAR14 & ~VAR32);
assign VAR2 = (VAR31>>1) ^ VAR31;
wire VAR3 = (VAR2 == VAR8);
always @(VAR8)
for (VAR10=0; VAR10<(VAR9+1); VAR10=VAR10+1)
VAR34[VAR10] = ^ (VAR8 >> VAR10);
wire [VAR9:0] VAR39 = (VAR31 + VAR40)-VAR34;
wire VAR28 = ~VAR39[VAR9];
always @(posedge VAR18 or negedge VAR44)
if (!VAR44) begin
VAR32 <= 1'b1;
VAR1 <= 1'VAR7 1;
end
else begin
VAR32 <= VAR3;
VAR1 <= VAR28;
end
endmodule
module MODULE2
parameter VAR27=5
)
(output reg VAR6,
output reg VAR36,
output [VAR9-1:0] VAR12,
output reg [VAR9 :0] VAR35,
input [VAR9 :0] VAR38,
input VAR37, VAR29, VAR5);
reg [VAR9:0] VAR11;
wire [VAR9:0] VAR4, VAR13;
reg [VAR9 :0] VAR24;
integer VAR10;
always @(posedge VAR29 or negedge VAR5)
if (!VAR5) {VAR11, VAR35} <= 0;
else {VAR11, VAR35} <= {VAR13, VAR4};
assign VAR12 = VAR11[VAR9-1:0];
assign VAR13 = VAR11 + (VAR37 & ~VAR6);
assign VAR4 = (VAR13>>1) ^ VAR13;
wire VAR43 = (VAR4 ==
{~VAR38[VAR9:VAR9-1],VAR38[VAR9-2:0]});
always @(VAR38)
for (VAR10=0; VAR10<(VAR9+1); VAR10=VAR10+1)
VAR24[VAR10] = ^ (VAR38 >> VAR10);
wire [VAR9 :0] VAR39 = VAR13 - VAR24 - VAR27;
wire VAR22 = ~VAR39[VAR9];
always @(posedge VAR29 or negedge VAR5)
if (!VAR5) begin
VAR6 <= 1'b0;
VAR36 <= 1'VAR7 0;
end
else begin
VAR6 <= VAR43;
VAR36 <= VAR22;
end
endmodule
module MODULE1 #(parameter VAR41 = 8, parameter VAR9 = 3)
(output [VAR41-1:0] VAR20,
input [VAR41-1:0] VAR26,
input [VAR9-1:0] VAR12, VAR42,
input VAR15, VAR6, VAR29);
localparam VAR33 = 1<<VAR9;
reg [VAR41-1:0] VAR23 [0:VAR33-1];
assign VAR20 = VAR23[VAR42];
always @(posedge VAR29)
if (VAR15 && !VAR6) VAR23[VAR12] <= VAR26;
endmodule
|
mit
|
mbuesch/toprammer
|
libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.v
| 8,960 |
module MODULE1(VAR16, VAR10, write, read, VAR22, VAR2);
inout [7:0] VAR16;
input VAR10;
input write;
input read;
input VAR22;
inout [48:1] VAR2;
wire VAR11;
reg [7:0] address;
reg [7:0] VAR26;
wire VAR13, VAR37;
assign VAR13 = 0;
assign VAR37 = 1;
reg [1:0] VAR3;
reg [3:0] VAR39;
reg [3:0] VAR15;
reg [16:0] VAR28;
parameter VAR6 = 128;
reg [7:0] VAR33[0:VAR6-1];
reg [7:0] VAR20;
reg [7:0] VAR4;
parameter VAR17 = 6;
reg [7:0] VAR36[0:VAR17-1];
reg [7:0] VAR14[0:VAR17-1];
reg [0:0] VAR32[0:VAR17-1];
reg [7:0] VAR18[0:VAR17-1];
reg [2:0] VAR8;
reg [2:0] VAR30;
reg VAR23;
reg [16:0] VAR31;
reg [16:0] VAR40;
wire [16:0] VAR38;
reg [7:0] VAR29;
reg [7:0] VAR7;
wire [7:0] VAR25;
reg VAR19;
reg VAR12;
reg VAR1;
parameter VAR21 = 1;
reg [15:0] VAR27;
wire VAR24;
VAR9 VAR34(.VAR5(VAR22), .VAR35(VAR24));
|
gpl-2.0
|
cr88192/bgbtech_bjx1core
|
bjx1c32b/ExShad32.v
| 4,449 |
module MODULE1(
VAR25, reset,
VAR7, VAR41,
VAR23, VAR46
);
input VAR25;
input reset;
input[31:0] VAR7;
input[ 7:0] VAR41;
input[ 2:0] VAR46;
output[31:0] VAR23;
reg[31:0] VAR49;
assign VAR23 = VAR49;
reg[31:0] VAR8;
reg[31:0] VAR12;
reg[ 7:0] VAR22;
always @*
begin
VAR8=0;
VAR12=0;
VAR49 = 0;
VAR22 = 0;
case(VAR46)
3'h0: begin
end
3'h1: begin VAR8=0;
VAR12=0;
VAR22 = VAR41;
end
3'h2: begin VAR8=0;
VAR12=VAR7[31] ? 32'hFFFFFFFF : 32'h00000000;
VAR22 = VAR41;
end
3'h3: begin VAR8=0;
VAR12=0;
VAR22 = -VAR41;
end
3'h4: begin VAR8=0;
VAR12=VAR7[31] ? 32'hFFFFFFFF : 32'h00000000;
VAR22 = -VAR41;
end
default:
begin
end
endcase
casez(VAR22)
8'VAR3: VAR49 = VAR7;
8'VAR65: VAR49 = { VAR7[30:0], VAR8[31 ] };
8'VAR33: VAR49 = { VAR7[29:0], VAR8[31:30] };
8'VAR26: VAR49 = { VAR7[28:0], VAR8[31:29] };
8'VAR11: VAR49 = { VAR7[27:0], VAR8[31:28] };
8'VAR9: VAR49 = { VAR7[26:0], VAR8[31:27] };
8'VAR61: VAR49 = { VAR7[25:0], VAR8[31:26] };
8'VAR20: VAR49 = { VAR7[24:0], VAR8[31:25] };
8'VAR47: VAR49 = { VAR7[23:0], VAR8[31:24] };
8'VAR31: VAR49 = { VAR7[22:0], VAR8[31:23] };
8'VAR34: VAR49 = { VAR7[21:0], VAR8[31:22] };
8'VAR15: VAR49 = { VAR7[20:0], VAR8[31:21] };
8'VAR66: VAR49 = { VAR7[19:0], VAR8[31:20] };
8'VAR57: VAR49 = { VAR7[18:0], VAR8[31:19] };
8'VAR21: VAR49 = { VAR7[17:0], VAR8[31:18] };
8'VAR4: VAR49 = { VAR7[16:0], VAR8[31:17] };
8'VAR55: VAR49 = { VAR7[15:0], VAR8[31:16] };
8'VAR54: VAR49 = { VAR7[14:0], VAR8[31:15] };
8'VAR14: VAR49 = { VAR7[13:0], VAR8[31:14] };
8'VAR38: VAR49 = { VAR7[12:0], VAR8[31:13] };
8'VAR36: VAR49 = { VAR7[11:0], VAR8[31:12] };
8'VAR16: VAR49 = { VAR7[10:0], VAR8[31:11] };
8'VAR29: VAR49 = { VAR7[ 9:0], VAR8[31:10] };
8'VAR27: VAR49 = { VAR7[ 8:0], VAR8[31: 9] };
8'VAR28: VAR49 = { VAR7[ 7:0], VAR8[31: 8] };
8'VAR45: VAR49 = { VAR7[ 6:0], VAR8[31: 7] };
8'VAR37: VAR49 = { VAR7[ 5:0], VAR8[31: 6] };
8'VAR56: VAR49 = { VAR7[ 4:0], VAR8[31: 5] };
8'VAR39: VAR49 = { VAR7[ 3:0], VAR8[31: 4] };
8'VAR63: VAR49 = { VAR7[ 2:0], VAR8[31: 3] };
8'VAR62: VAR49 = { VAR7[ 1:0], VAR8[31: 2] };
8'VAR1: VAR49 = { VAR7[ 0], VAR8[31: 1] };
8'VAR35: VAR49 = { VAR12[ 0 ], VAR7[31: 1] };
8'VAR50: VAR49 = { VAR12[ 1:0], VAR7[31: 2] };
8'VAR19: VAR49 = { VAR12[ 2:0], VAR7[31: 3] };
8'VAR70: VAR49 = { VAR12[ 3:0], VAR7[31: 4] };
8'VAR68: VAR49 = { VAR12[ 4:0], VAR7[31: 5] };
8'VAR18: VAR49 = { VAR12[ 5:0], VAR7[31: 6] };
8'VAR5: VAR49 = { VAR12[ 6:0], VAR7[31: 7] };
8'VAR32: VAR49 = { VAR12[ 7:0], VAR7[31: 8] };
8'VAR13: VAR49 = { VAR12[ 8:0], VAR7[31: 9] };
8'VAR6: VAR49 = { VAR12[ 9:0], VAR7[31:10] };
8'VAR53: VAR49 = { VAR12[10:0], VAR7[31:11] };
8'VAR48: VAR49 = { VAR12[11:0], VAR7[31:12] };
8'VAR17: VAR49 = { VAR12[12:0], VAR7[31:13] };
8'VAR24: VAR49 = { VAR12[13:0], VAR7[31:14] };
8'VAR60: VAR49 = { VAR12[14:0], VAR7[31:15] };
8'VAR73: VAR49 = { VAR12[15:0], VAR7[31:16] };
8'VAR67: VAR49 = { VAR12[16:0], VAR7[31:17] };
8'VAR40: VAR49 = { VAR12[17:0], VAR7[31:18] };
8'VAR10: VAR49 = { VAR12[18:0], VAR7[31:19] };
8'VAR72: VAR49 = { VAR12[19:0], VAR7[31:20] };
8'VAR51: VAR49 = { VAR12[20:0], VAR7[31:21] };
8'VAR71: VAR49 = { VAR12[21:0], VAR7[31:22] };
8'VAR52: VAR49 = { VAR12[22:0], VAR7[31:23] };
8'VAR2: VAR49 = { VAR12[23:0], VAR7[31:24] };
8'VAR69: VAR49 = { VAR12[24:0], VAR7[31:25] };
8'VAR59: VAR49 = { VAR12[25:0], VAR7[31:26] };
8'VAR64: VAR49 = { VAR12[26:0], VAR7[31:27] };
8'VAR43: VAR49 = { VAR12[27:0], VAR7[31:28] };
8'VAR44: VAR49 = { VAR12[28:0], VAR7[31:29] };
8'VAR58: VAR49 = { VAR12[29:0], VAR7[31:30] };
8'VAR30: VAR49 = { VAR12[30:0], VAR7[31 ] };
8'VAR42: VAR49 = VAR12;
endcase
end
endmodule
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.behavioral.v
| 1,093 |
module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR4 VAR2(.VAR1(VAR1),.VAR3(VAR3));
VAR4 VAR5(.VAR1(VAR1),.VAR3(VAR3));
|
apache-2.0
|
impedimentToProgress/ProbableCause
|
ddr2/cores/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
| 20,617 |
module MODULE1(
VAR49,
VAR41,
VAR29,
VAR21,
VAR58,
VAR35,
VAR7,
VAR69,
VAR57,
VAR45,
VAR61,
VAR48,
VAR68,
VAR14,
VAR23,
VAR36,
VAR26,
VAR67, VAR25, VAR20 );
input VAR49; input VAR41; input VAR29; input VAR21; output VAR58; output VAR35;
output VAR7;
output VAR69;
output VAR57;
output VAR45;
output VAR61;
output VAR48;
output VAR68;
output VAR14;
output VAR23;
output VAR36;
output VAR26;
input VAR67; input VAR25; input VAR20;
reg VAR65;
reg VAR62;
reg VAR55;
reg VAR44;
reg VAR54;
reg VAR9;
reg VAR74;
reg VAR19;
reg VAR5;
reg VAR38;
reg VAR34;
reg VAR75;
reg VAR13;
reg VAR40;
reg VAR31;
reg VAR60;
reg VAR42;
reg VAR8;
reg VAR64;
reg VAR72;
reg VAR4;
reg VAR53;
reg VAR58;
reg VAR35;
assign VAR26 = VAR21;
assign VAR7 = VAR65;
assign VAR69 = VAR62;
assign VAR57 = VAR54;
assign VAR45 = VAR74;
assign VAR61 = VAR5;
assign VAR48 = VAR44;
assign VAR68 = VAR42;
assign VAR14 = VAR8;
assign VAR23 = VAR72;
assign VAR36 = VAR4;
reg [3:0] VAR39 = VAR30; reg [3:0] VAR63;
always @ (posedge VAR41 or negedge VAR29)
begin
if(VAR29 == 0)
VAR39 = VAR30;
end
else
VAR39 = VAR63;
end
always @ (VAR39 or VAR49)
begin
case(VAR39)
begin
if(VAR49) VAR63 = VAR30;
end
else VAR63 = VAR43;
end
begin
if(VAR49) VAR63 = VAR24;
end
else VAR63 = VAR43;
end
begin
if(VAR49) VAR63 = VAR3;
end
else VAR63 = VAR66;
end
begin
if(VAR49) VAR63 = VAR1;
end
else VAR63 = VAR10;
end
begin
if(VAR49) VAR63 = VAR1;
end
else VAR63 = VAR10;
end
begin
if(VAR49) VAR63 = VAR33;
end
else VAR63 = VAR70;
end
begin
if(VAR49) VAR63 = VAR18;
end
else VAR63 = VAR70;
end
begin
if(VAR49) VAR63 = VAR33;
end
else VAR63 = VAR10;
end
begin
if(VAR49) VAR63 = VAR24;
end
else VAR63 = VAR43;
end
begin
if(VAR49) VAR63 = VAR30;
end
else VAR63 = VAR32;
end
begin
if(VAR49) VAR63 = VAR2;
end
else VAR63 = VAR17;
end
begin
if(VAR49) VAR63 = VAR2;
end
else VAR63 = VAR17;
end
begin
if(VAR49) VAR63 = VAR52;
end
else VAR63 = VAR27;
end
begin
if(VAR49) VAR63 = VAR37;
end
else VAR63 = VAR27;
end
begin
if(VAR49) VAR63 = VAR52;
end
else VAR63 = VAR17;
end
begin
if(VAR49) VAR63 = VAR24;
end
else VAR63 = VAR43;
end
default: VAR63 = VAR30; endcase
end
always @ (VAR39)
begin
VAR65 = 1'b0;
VAR62 = 1'b0;
VAR55 = 1'b0;
VAR44 = 1'b0;
VAR54 = 1'b0;
VAR9 = 1'b0;
VAR74 = 1'b0;
VAR19 = 1'b0;
VAR5 = 1'b0;
VAR38 = 1'b0;
VAR34 = 1'b0;
VAR75 = 1'b0;
VAR13 = 1'b0;
VAR40 = 1'b0;
VAR31 = 1'b0;
VAR60 = 1'b0;
case(VAR39)
default: ;
endcase
end
reg [VAR51-1:0] VAR16; reg [VAR51-1:0] VAR50; wire VAR46;
always @ (posedge VAR41 or negedge VAR29)
begin
if(VAR29 == 0)
VAR16[VAR51-1:0] <= VAR51'b0;
end
else if (VAR65 == 1)
VAR16[VAR51-1:0] <= VAR51'b0;
else if(VAR34)
VAR16 <= 4'b0101; else if(VAR75)
VAR16[VAR51-1:0] <= {VAR21, VAR16[VAR51-1:1]};
end
assign VAR46 = VAR16[0];
always @ (negedge VAR41 or negedge VAR29)
begin
if(VAR29 == 0)
end
VAR50 <=VAR12; else if (VAR65)
VAR50 <=VAR12; else if(VAR60)
VAR50 <=VAR16;
end
reg [31:0] VAR6;
wire VAR11;
always @ (posedge VAR41 or negedge VAR29)
begin
if(VAR29 == 0)
end
VAR6 <=VAR22; else if (VAR65)
VAR6 <=VAR22; else if(VAR64 & VAR44)
VAR6 <= VAR22;
else if(VAR64 & VAR54)
VAR6 <= {VAR21, VAR6[31:1]};
end
assign VAR11 = VAR6[0];
wire VAR47;
reg VAR73;
always @ (posedge VAR41 or negedge VAR29)
begin
if (VAR29 == 0)
VAR73 <= 1'b0;
end
else if (VAR65 == 1)
VAR73 <= 1'b0;
else if (VAR53 & VAR44)
VAR73<=1'b0;
else if(VAR53 & VAR54)
VAR73<=VAR21;
end
assign VAR47 = VAR73;
always @ (VAR50)
begin
VAR42 = 1'b0;
VAR8 = 1'b0;
VAR64 = 1'b0;
VAR72 = 1'b0;
VAR4 = 1'b0;
VAR53 = 1'b0;
case(VAR50)
end
reg VAR59;
always @ (VAR75 or VAR46 or VAR50 or VAR11 or
VAR67 or VAR25 or VAR20 or VAR47 or
VAR25)
begin
if(VAR75)
VAR59 = VAR46;
end
else
begin
case(VAR50) VAR12: VAR59 = VAR11; VAR15: VAR59 = VAR67; VAR28: VAR59 = VAR25; VAR56: VAR59 = VAR25; VAR71: VAR59 = VAR20; default: VAR59 = VAR47; endcase
end
end
always @ (negedge VAR41)
begin
VAR58 = VAR59;
end
always @ (posedge VAR41)
begin
VAR35 <= VAR75 | VAR54;
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a32o/sky130_fd_sc_hs__a32o.symbol.v
| 1,388 |
module MODULE1 (
input VAR5,
input VAR7,
input VAR4,
input VAR3,
input VAR8,
output VAR2
);
supply1 VAR1;
supply0 VAR6;
endmodule
|
apache-2.0
|
jcowgill/BfProcessor
|
data_ram.v
| 2,262 |
module MODULE1(VAR5, clk, address, VAR4, write);
parameter VAR8 = 8;
parameter VAR1 = 15;
parameter VAR6 = 1;
output [VAR8 - 1:0] VAR5;
input clk;
input [VAR1 - 1:0] address; input [VAR8 - 1:0] VAR4; input write;
reg [VAR8 - 1:0] VAR3[0:(1 << VAR1) - 1];
reg [VAR8 - 1:0] VAR7;
assign VAR5 = VAR7;
integer VAR2;
begin
begin
begin
begin
end
begin
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/ebufn/sky130_fd_sc_lp__ebufn.pp.blackbox.v
| 1,287 |
module MODULE1 (
VAR1 ,
VAR4 ,
VAR7,
VAR5,
VAR6,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR7;
input VAR5;
input VAR6;
input VAR2 ;
input VAR3 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/inv/sky130_fd_sc_hd__inv.functional.pp.v
| 1,748 |
module MODULE1 (
VAR7 ,
VAR5 ,
VAR3,
VAR1,
VAR12 ,
VAR10
);
output VAR7 ;
input VAR5 ;
input VAR3;
input VAR1;
input VAR12 ;
input VAR10 ;
wire VAR2 ;
wire VAR4;
not VAR8 (VAR2 , VAR5 );
VAR6 VAR11 (VAR4, VAR2, VAR3, VAR1);
buf VAR9 (VAR7 , VAR4 );
endmodule
|
apache-2.0
|
YuxuanLing/trunk
|
trunk/references/h265enc_v1.0/rtl/fme/fme_satd_gen.v
| 27,839 |
module MODULE1 (
clk ,
VAR17 ,
VAR77 ,
VAR113 ,
VAR49 ,
VAR99 ,
VAR40 ,
VAR38 ,
VAR104 ,
VAR9 ,
VAR73 ,
VAR118 ,
VAR82 ,
VAR80 ,
VAR5 ,
VAR95 ,
VAR31 ,
VAR69 ,
VAR24 ,
VAR83 ,
VAR106 ,
VAR128 ,
VAR15 ,
VAR10 ,
VAR61 ,
VAR67 ,
VAR33 ,
VAR102 ,
VAR98 ,
VAR103 ,
VAR116 ,
VAR48 ,
VAR109 ,
VAR108 ,
VAR126 ,
VAR71 ,
VAR7 ,
VAR70 ,
VAR41 ,
VAR111 ,
VAR54 ,
VAR23 ,
VAR74 ,
VAR36 ,
VAR117 ,
VAR85 ,
VAR84
);
parameter VAR90 = VAR105 + 10;
input [1-1:0] clk ; input [1-1:0] VAR17 ; input [1-1:0] VAR77 ; input [6-1:0] VAR113 ; input [1-1:0] VAR49 ; input [VAR81-1:0] VAR99 ; input [VAR81-1:0] VAR40 ; output [VAR81-1:0] VAR38 ; output [VAR81-1:0] VAR104 ; output [1-1:0] VAR73 ; output [6-1:0] VAR9 ; input [1-1:0] VAR118 ; input [1-1:0] VAR82 ;
output [1-1:0] VAR80 ; output [1-1:0] VAR5 ; output [4-1:0] VAR31 ; output [4-1:0] VAR69 ; output [5-1:0] VAR95 ; input [32*VAR105-1:0] VAR24 ;
input [1-1:0] VAR83 ; input [1-1:0] VAR106 ; input [1-1:0] VAR128 ; input [1-1:0] VAR15 ; input [1-1:0] VAR10 ; input [1-1:0] VAR61 ; input [1-1:0] VAR67 ; input [1-1:0] VAR33 ; input [1-1:0] VAR102 ; input [VAR105*8-1:0] VAR98 ; input [VAR105*8-1:0] VAR103 ; input [VAR105*8-1:0] VAR116 ; input [VAR105*8-1:0] VAR48 ; input [VAR105*8-1:0] VAR109 ; input [VAR105*8-1:0] VAR108 ; input [VAR105*8-1:0] VAR126 ; input [VAR105*8-1:0] VAR71 ; input [VAR105*8-1:0] VAR7 ;
output [VAR90-1 :0] VAR70 ; output [VAR90-1 :0] VAR41 ; output [VAR90-1 :0] VAR111 ; output [VAR90-1 :0] VAR54 ; output [VAR90-1 :0] VAR23 ; output [VAR90-1 :0] VAR74 ; output [VAR90-1 :0] VAR36 ; output [VAR90-1 :0] VAR117 ; output [VAR90-1 :0] VAR85 ; output [1-1:0] VAR84 ;
reg [VAR81-1: 0] VAR38; reg [VAR81-1: 0] VAR104;
reg [1-1: 0] VAR73;
reg [1-1: 0] VAR80;
reg [1-1: 0] VAR47;
reg [6-1: 0] VAR53;
reg [6-1: 0] VAR120;
wire [6-1: 0] VAR19 ;
reg VAR92;
reg VAR93;
wire [8*VAR105-1:0] VAR78;
wire [8*VAR105-1:0] VAR89;
wire [8*VAR105-1:0] VAR59;
wire [8*VAR105-1:0] VAR100;
wire [8*VAR105-1:0] VAR79;
wire [8*VAR105-1:0] VAR30;
wire [8*VAR105-1:0] VAR121;
wire [8*VAR105-1:0] VAR2;
reg [32*VAR105-1:0] VAR63;
reg [32*VAR105-1:0] VAR45;
reg VAR20;
reg [8*VAR105-1 :0] VAR18;
reg [8*VAR105-1 :0] VAR26;
reg [8*VAR105-1 :0] VAR123;
reg [8*VAR105-1 :0] VAR13;
reg [8*VAR105-1 :0] VAR110;
reg [8*VAR105-1 :0] VAR34;
reg [8*VAR105-1 :0] VAR35;
reg [8*VAR105-1 :0] VAR43;
reg [8*VAR105-1 :0] VAR62;
reg [3-1 :0] VAR88;
reg [3-1 :0] VAR127;
reg [3-1 :0] VAR1;
reg [3-1 :0] VAR91;
reg [3-1 :0] VAR72;
reg [3-1 :0] VAR114;
reg [3-1 :0] VAR52;
reg [3-1 :0] VAR97;
reg [3-1 :0] VAR39;
wire [VAR90-1 :0] VAR65;
wire [VAR90-1 :0] VAR25;
wire [VAR90-1 :0] VAR64;
wire [VAR90-1 :0] VAR112;
wire [VAR90-1 :0] VAR96;
wire [VAR90-1 :0] VAR101;
wire [VAR90-1 :0] VAR76;
wire [VAR90-1 :0] VAR4;
wire [VAR90-1 :0] VAR11;
wire [2-1 :0] VAR68, VAR22, VAR119;
wire [3-1 :0] VAR44, VAR3;
wire [6-1 :0] VAR125;
assign VAR2 = VAR45[1*8*VAR105-1:0*8*VAR105];
assign VAR121 = VAR45[2*8*VAR105-1:1*8*VAR105];
assign VAR30 = VAR45[3*8*VAR105-1:2*8*VAR105];
assign VAR79 = VAR45[4*8*VAR105-1:3*8*VAR105];
assign VAR100 = VAR63[1*8*VAR105-1:0*8*VAR105];
assign VAR59 = VAR63[2*8*VAR105-1:1*8*VAR105];
assign VAR89 = VAR63[3*8*VAR105-1:2*8*VAR105];
assign VAR78 = VAR63[4*8*VAR105-1:3*8*VAR105];
assign VAR5 = VAR118;
assign VAR31 = {VAR44,1'b0};
assign VAR69 = {VAR3,1'b0};
assign VAR95 = {2'b0,VAR47,2'b0};
assign VAR70 = VAR65;
assign VAR41 = VAR25;
assign VAR111 = VAR64;
assign VAR54 = VAR112;
assign VAR23 = VAR96;
assign VAR74 = VAR101;
assign VAR36 = VAR76;
assign VAR117 = VAR4;
assign VAR85 = VAR11;
assign VAR19 = (VAR93) ? VAR120 : VAR53;
assign VAR125 = (VAR92 ) ? VAR53 : VAR120;
assign VAR68 = VAR125[5:4];
assign VAR22 = VAR125[3:2];
assign VAR119 = VAR125[1:0];
assign VAR44 = {VAR68[0],VAR22[0],VAR119[0]};
assign VAR3 = {VAR68[1],VAR22[1],VAR119[1]};
assign VAR9 = VAR19;
always @ (posedge clk or negedge VAR17) begin
if (~VAR17) begin
VAR38 <= 'd0;
VAR104 <= 'd0;
VAR73 <= 1'b0;
end
else if (VAR82) begin
VAR38 <= VAR99;
VAR104 <= VAR40;
VAR73 <= VAR49;
end
end
always @ (posedge clk or negedge VAR17) begin
if (~VAR17) begin
VAR80 <= 1'b0;
end
else begin
VAR80 <= VAR82;
end
end
always @ (posedge clk or negedge VAR17) begin
if (~VAR17) begin
VAR92 <= 1'b0;
VAR53 <= 'd0;
VAR120 <= 'd0;
end
else if (VAR77) begin
VAR92 <= ~VAR92;
if(~VAR92)
VAR53 <= VAR113;
end
else
VAR120 <= VAR113;
end
end
always @ (posedge clk or negedge VAR17) begin
if (~VAR17) begin
VAR93 <= 1'd0;
end
else if (VAR84) begin
VAR93 <= ~VAR93;
end
end
always @ (posedge clk or negedge VAR17) begin
if (~VAR17) begin
VAR47 <= 1'b0;
VAR20 <= 1'b0;
end
else if(VAR5) begin
VAR47 <= ~VAR47;
VAR20 <= 1'b1;
end
else begin
VAR47 <= VAR47;
VAR20 <= 1'b0;
end
end
always @ (posedge clk or negedge VAR17) begin
if (~VAR17) begin
VAR63 <= 'b0;
VAR45 <= 'b0;
end
else if(VAR20) begin
if(VAR47)
VAR63 <= VAR24;
end
else
VAR45 <= VAR24;
end
end
always @ (posedge clk or negedge VAR17) begin
if(~VAR17) begin
VAR88 <= 'd0;
end
else if (VAR77) begin
VAR88 <= 'd0;
end
else if (VAR83) begin
VAR88 <= VAR88 + 'd1;
end
end
always @ begin
case(VAR127)
3'd0: VAR26 = VAR78;
3'd1: VAR26 = VAR89;
3'd2: VAR26 = VAR59;
3'd3: VAR26 = VAR100;
3'd4: VAR26 = VAR79;
3'd5: VAR26 = VAR30;
3'd6: VAR26 = VAR121;
3'd7: VAR26 = VAR2;
endcase
end
VAR87 VAR94(
.clk (clk),
.VAR17 (VAR17),
.VAR55(VAR26[8*VAR105-1:7*VAR105]),
.VAR21(VAR26[7*VAR105-1:6*VAR105]),
.VAR27(VAR26[6*VAR105-1:5*VAR105]),
.VAR6(VAR26[5*VAR105-1:4*VAR105]),
.VAR32(VAR26[4*VAR105-1:3*VAR105]),
.VAR50(VAR26[3*VAR105-1:2*VAR105]),
.VAR28(VAR26[2*VAR105-1:1*VAR105]),
.VAR42(VAR26[1*VAR105-1:0*VAR105]),
.VAR75(VAR106),
.VAR56(VAR103[8*VAR105-1:7*VAR105]),
.VAR124(VAR103[7*VAR105-1:6*VAR105]),
.VAR107(VAR103[6*VAR105-1:5*VAR105]),
.VAR115(VAR103[5*VAR105-1:4*VAR105]),
.VAR29(VAR103[4*VAR105-1:3*VAR105]),
.VAR86(VAR103[3*VAR105-1:2*VAR105]),
.VAR16(VAR103[2*VAR105-1:1*VAR105]),
.VAR57(VAR103[1*VAR105-1:0*VAR105]),
.VAR66(VAR25),
.VAR12(VAR46)
);
always @ (posedge clk or negedge VAR17) begin
if(~VAR17) begin
VAR1 <= 'd0;
end
else if (VAR77) begin
VAR1 <= 'd0;
end
else if (VAR128) begin
VAR1 <= VAR1 + 'd1;
end
end
always @ begin
case(VAR91)
3'd0: VAR13 = VAR78;
3'd1: VAR13 = VAR89;
3'd2: VAR13 = VAR59;
3'd3: VAR13 = VAR100;
3'd4: VAR13 = VAR79;
3'd5: VAR13 = VAR30;
3'd6: VAR13 = VAR121;
3'd7: VAR13 = VAR2;
endcase
end
VAR87 VAR58(
.clk (clk),
.VAR17 (VAR17),
.VAR55(VAR13[8*VAR105-1:7*VAR105]),
.VAR21(VAR13[7*VAR105-1:6*VAR105]),
.VAR27(VAR13[6*VAR105-1:5*VAR105]),
.VAR6(VAR13[5*VAR105-1:4*VAR105]),
.VAR32(VAR13[4*VAR105-1:3*VAR105]),
.VAR50(VAR13[3*VAR105-1:2*VAR105]),
.VAR28(VAR13[2*VAR105-1:1*VAR105]),
.VAR42(VAR13[1*VAR105-1:0*VAR105]),
.VAR75(VAR15),
.VAR56(VAR48[8*VAR105-1:7*VAR105]),
.VAR124(VAR48[7*VAR105-1:6*VAR105]),
.VAR107(VAR48[6*VAR105-1:5*VAR105]),
.VAR115(VAR48[5*VAR105-1:4*VAR105]),
.VAR29(VAR48[4*VAR105-1:3*VAR105]),
.VAR86(VAR48[3*VAR105-1:2*VAR105]),
.VAR16(VAR48[2*VAR105-1:1*VAR105]),
.VAR57(VAR48[1*VAR105-1:0*VAR105]),
.VAR66(VAR112),
.VAR12(VAR122)
);
always @ (posedge clk or negedge VAR17) begin
if(~VAR17) begin
VAR72 <= 'd0;
end
else if (VAR77) begin
VAR72 <= 'd0;
end
else if (VAR10) begin
VAR72 <= VAR72 + 'd1;
end
end
always @ begin
case(VAR114)
3'd0: VAR34 = VAR78;
3'd1: VAR34 = VAR89;
3'd2: VAR34 = VAR59;
3'd3: VAR34 = VAR100;
3'd4: VAR34 = VAR79;
3'd5: VAR34 = VAR30;
3'd6: VAR34 = VAR121;
3'd7: VAR34 = VAR2;
endcase
end
VAR87 VAR60(
.clk (clk),
.VAR17 (VAR17),
.VAR55(VAR34[8*VAR105-1:7*VAR105]),
.VAR21(VAR34[7*VAR105-1:6*VAR105]),
.VAR27(VAR34[6*VAR105-1:5*VAR105]),
.VAR6(VAR34[5*VAR105-1:4*VAR105]),
.VAR32(VAR34[4*VAR105-1:3*VAR105]),
.VAR50(VAR34[3*VAR105-1:2*VAR105]),
.VAR28(VAR34[2*VAR105-1:1*VAR105]),
.VAR42(VAR34[1*VAR105-1:0*VAR105]),
.VAR75(VAR61),
.VAR56(VAR108[8*VAR105-1:7*VAR105]),
.VAR124(VAR108[7*VAR105-1:6*VAR105]),
.VAR107(VAR108[6*VAR105-1:5*VAR105]),
.VAR115(VAR108[5*VAR105-1:4*VAR105]),
.VAR29(VAR108[4*VAR105-1:3*VAR105]),
.VAR86(VAR108[3*VAR105-1:2*VAR105]),
.VAR16(VAR108[2*VAR105-1:1*VAR105]),
.VAR57(VAR108[1*VAR105-1:0*VAR105]),
.VAR66(VAR101),
.VAR12(VAR51)
);
always @ (posedge clk or negedge VAR17) begin
if(~VAR17) begin
VAR52 <= 'd0;
end
else if (VAR77) begin
VAR52 <= 'd0;
end
else if (VAR67) begin
VAR52 <= VAR52 + 'd1;
end
end
always @ begin
case(VAR97)
3'd0: VAR43 = VAR78;
3'd1: VAR43 = VAR89;
3'd2: VAR43 = VAR59;
3'd3: VAR43 = VAR100;
3'd4: VAR43 = VAR79;
3'd5: VAR43 = VAR30;
3'd6: VAR43 = VAR121;
3'd7: VAR43 = VAR2;
endcase
end
VAR87 VAR37(
.clk (clk),
.VAR17 (VAR17),
.VAR55(VAR43[8*VAR105-1:7*VAR105]),
.VAR21(VAR43[7*VAR105-1:6*VAR105]),
.VAR27(VAR43[6*VAR105-1:5*VAR105]),
.VAR6(VAR43[5*VAR105-1:4*VAR105]),
.VAR32(VAR43[4*VAR105-1:3*VAR105]),
.VAR50(VAR43[3*VAR105-1:2*VAR105]),
.VAR28(VAR43[2*VAR105-1:1*VAR105]),
.VAR42(VAR43[1*VAR105-1:0*VAR105]),
.VAR75(VAR33),
.VAR56(VAR71[8*VAR105-1:7*VAR105]),
.VAR124(VAR71[7*VAR105-1:6*VAR105]),
.VAR107(VAR71[6*VAR105-1:5*VAR105]),
.VAR115(VAR71[5*VAR105-1:4*VAR105]),
.VAR29(VAR71[4*VAR105-1:3*VAR105]),
.VAR86(VAR71[3*VAR105-1:2*VAR105]),
.VAR16(VAR71[2*VAR105-1:1*VAR105]),
.VAR57(VAR71[1*VAR105-1:0*VAR105]),
.VAR66(VAR4),
.VAR12(VAR8)
);
always @ (posedge clk or negedge VAR17) begin
if(~VAR17) begin
VAR39 <= 'd0;
end
else if (VAR77) begin
VAR39 <= 'd0;
end
else if (VAR102) begin
VAR39 <= VAR39 + 'd1;
end
end
always @(*) begin
case(VAR39)
3'd0: VAR62 = VAR78;
3'd1: VAR62 = VAR89;
3'd2: VAR62 = VAR59;
3'd3: VAR62 = VAR100;
3'd4: VAR62 = VAR79;
3'd5: VAR62 = VAR30;
3'd6: VAR62 = VAR121;
3'd7: VAR62 = VAR2;
endcase
end
VAR87 VAR14(
.clk (clk),
.VAR17 (VAR17),
.VAR55(VAR62[8*VAR105-1:7*VAR105]),
.VAR21(VAR62[7*VAR105-1:6*VAR105]),
.VAR27(VAR62[6*VAR105-1:5*VAR105]),
.VAR6(VAR62[5*VAR105-1:4*VAR105]),
.VAR32(VAR62[4*VAR105-1:3*VAR105]),
.VAR50(VAR62[3*VAR105-1:2*VAR105]),
.VAR28(VAR62[2*VAR105-1:1*VAR105]),
.VAR42(VAR62[1*VAR105-1:0*VAR105]),
.VAR75(VAR102),
.VAR56(VAR7[8*VAR105-1:7*VAR105]),
.VAR124(VAR7[7*VAR105-1:6*VAR105]),
.VAR107(VAR7[6*VAR105-1:5*VAR105]),
.VAR115(VAR7[5*VAR105-1:4*VAR105]),
.VAR29(VAR7[4*VAR105-1:3*VAR105]),
.VAR86(VAR7[3*VAR105-1:2*VAR105]),
.VAR16(VAR7[2*VAR105-1:1*VAR105]),
.VAR57(VAR7[1*VAR105-1:0*VAR105]),
.VAR66(VAR11),
.VAR12(VAR84)
);
endmodule
|
gpl-3.0
|
intelligenttoasters/CPC2.0
|
FPGA/rtl/cpc/romsel.v
| 1,079 |
module MODULE1(
input [3:0] VAR7,
output [7:0] do,
input [7:0] VAR12,
input [7:0] VAR5,
input [7:0] VAR14,
input [7:0] VAR2,
input [7:0] VAR9,
input [7:0] VAR1,
input [7:0] VAR3,
input [7:0] VAR13,
input [7:0] VAR8,
input [7:0] VAR16,
input [7:0] VAR11,
input [7:0] VAR6,
input [7:0] VAR17,
input [7:0] VAR10,
input [7:0] VAR4,
input [7:0] VAR15
);
assign do =
(VAR7 == 4'd1) ? VAR5 :
(VAR7 == 4'd2) ? VAR14 :
(VAR7 == 4'd3) ? VAR2 :
(VAR7 == 4'd4) ? VAR9 :
(VAR7 == 4'd5) ? VAR1 :
(VAR7 == 4'd6) ? VAR3 :
(VAR7 == 4'd7) ? VAR13 :
(VAR7 == 4'd8) ? VAR8 :
(VAR7 == 4'd9) ? VAR16 :
(VAR7 == 4'd10) ? VAR11 :
(VAR7 == 4'd11) ? VAR6 :
(VAR7 == 4'd12) ? VAR17 :
(VAR7 == 4'd13) ? VAR10 :
(VAR7 == 4'd14) ? VAR4 :
(VAR7 == 4'd15) ? VAR15 :
VAR12;
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.behavioral.v
| 3,306 |
module MODULE1( VAR4, VAR9, VAR3, VAR5, VAR8, VAR6 );
input VAR8, VAR6, VAR5, VAR3, VAR9;
output VAR4;
VAR2 VAR7(.VAR4(VAR4),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR6(VAR6));
VAR2 VAR1(.VAR4(VAR4),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR6(VAR6));
|
apache-2.0
|
Jside/pdp1
|
pdp1_sbs16.v
| 1,856 |
module MODULE1(VAR13, VAR9,
VAR10, VAR12, VAR3, VAR4, VAR2,
VAR6, VAR5);
input VAR13;
input VAR9;
output VAR10;
output VAR12;
output VAR3;
output VAR4;
input VAR2;
input VAR6;
input [0:11] VAR5;
wire [0:5] VAR7;
wire [0:5] VAR1;
assign VAR7 = VAR5[0:5];
assign VAR1 = VAR5[6:11];
reg [0:15] VAR11;
reg [0:15] VAR8;
always @(posedge VAR13) begin
if(VAR9) begin
VAR11 <= 16'h0000;
VAR8 <= 16'h0000;
end
else begin
if(VAR6) begin
case(VAR1)
VAR11[VAR7] <= 1'b1;
VAR11[VAR7] <= 1'b0;
VAR8[VAR7] <= 1'b1;
VAR11 <= 16'h0000;
endcase end
end
end
endmodule
|
gpl-3.0
|
rkrajnc/minimig-mist
|
rtl/minimig/denise_sprites_shifter.v
| 3,610 |
module MODULE1
(
input clk, input VAR6,
input reset, input VAR20, input [1:0] address, input [8:0] VAR8, input [15:0] VAR14,
input VAR19,
input [48-1:0] VAR13,
input [15:0] VAR9, output [1:0] VAR15, output reg VAR12 );
parameter VAR10 = 2'b00;
parameter VAR3 = 2'b01;
parameter VAR7 = 2'b10;
parameter VAR16 = 2'b11;
reg [63:0] VAR4; reg [63:0] VAR22; reg [63:0] VAR2; reg [63:0] VAR17; reg [8:0] VAR18; reg VAR11; reg VAR21; reg VAR1;
reg [64-1:0] VAR5;
always @ (*) begin
case(VAR14[3:2])
2'b00 : VAR5 = {VAR9, 48'h000000000000};
2'b11 : VAR5 = {VAR9, VAR13[47:0]};
default : VAR5 = {VAR9, VAR13[47:32], 32'h00000000};
endcase
end
always @(posedge clk)
if (VAR6) begin
if (reset) VAR11 <= 0;
end
else if (VAR20 && address==VAR3) VAR11 <= 0;
else if (VAR20 && address==VAR7) VAR11 <= 1;
end
always @(posedge clk)
if (VAR6) begin
VAR21 <= VAR11 && (VAR8[7:0] == VAR18[7:0]) && (VAR14[15] || (VAR8[8] == VAR18[8])) ? 1'b1 : 1'b0;
end
always @(posedge clk)
if (VAR6) begin
VAR1 <= VAR21;
end
always @(posedge clk)
if (VAR6) begin
if (VAR20 && address==VAR10)
VAR18[8:1] <= VAR9[7:0];
end
always @(posedge clk)
if (VAR6) begin
if (VAR20 && address==VAR3)
{VAR12,VAR18[0]} <= {VAR9[7],VAR9[0]};
end
always @(posedge clk)
if (VAR6) begin
if (VAR20 && address==VAR7)
VAR4[63:0] <= VAR5;
end
always @(posedge clk)
if (VAR6) begin
if (VAR20 && address==VAR16)
VAR22[63:0] <= VAR5;
end
always @(posedge clk)
if (VAR6 && VAR1) begin
VAR2[63:0] <= VAR4[63:0];
VAR17[63:0] <= VAR22[63:0];
end
else if (VAR19)
begin
VAR2[63:0] <= {VAR2[62:0],1'b0};
VAR17[63:0] <= {VAR17[62:0],1'b0};
end
assign VAR15[1:0] = {VAR17[63],VAR2[63]};
endmodule
|
gpl-3.0
|
myriadrf/A2300
|
hdl/wca/WcaPortWrite.v
| 3,053 |
module MODULE1(
input wire reset,
input wire VAR8,
input wire VAR1, input wire VAR5, input wire [31:0] VAR14,
output wire VAR10, output wire VAR23,
output wire VAR4, output wire VAR15,
inout [31:0] VAR17, input wire [(VAR11+2):0] VAR9, output wire [1:0] VAR7
);
parameter VAR2 = 0;
parameter VAR11 = 2;
parameter VAR19 = 0;
wire [31:0] dout;
wire VAR12 = (VAR2 == VAR9[VAR11+2:3]);
wire VAR21 = VAR12 & VAR9[1];
assign VAR7 = (VAR12) ? ((VAR15 & VAR8) ? VAR13 : VAR3) : 2'VAR18;
VAR20 VAR22 (
.rst(reset), .VAR1(VAR1), .VAR6(VAR9[0]), .din(VAR14), .VAR5(VAR5 & VAR8), .VAR21(VAR21), .dout(dout), .VAR23(VAR23), .VAR10(VAR10), .VAR15(VAR15), .VAR4(VAR4) );
generate if( VAR19 == 1)
begin
assign VAR17 = ( VAR21 ) ? VAR16 : 32'VAR18;
reg [31:0] VAR16;
always @(posedge VAR9[0])
begin
if( reset)
VAR16 <= 32'h0;
end
else if( VAR21 )
VAR16 <= VAR16 + 32'h1;
end
end
else
begin
assign VAR17 = ( VAR21 ) ? dout : 32'VAR18;
end
endgenerate
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc_8.v
| 2,319 |
module MODULE2 (
VAR6 ,
VAR5,
VAR7 ,
VAR9 ,
VAR4 ,
VAR8 ,
VAR3
);
output VAR6 ;
input VAR5;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR3 ;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR5,
VAR7
);
output VAR6 ;
input VAR5;
input VAR7 ;
supply1 VAR9;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR3 ;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.behavioral.pp.v
| 6,220 |
module MODULE1( VAR6, VAR25, VAR57, VAR53, VAR48, VAR1, VAR9 );
input VAR57, VAR6, VAR25, VAR53;
inout VAR1, VAR9;
output VAR48;
reg VAR64;
VAR26 VAR60(.VAR6(VAR6),.VAR25(VAR25),.VAR57(VAR57),.VAR53(VAR53),.VAR48(VAR48),.VAR1(VAR1),.VAR9(VAR9),.VAR64(VAR64));
VAR26 VAR12(.VAR6(VAR6),.VAR25(VAR25),.VAR57(VAR57),.VAR53(VAR53),.VAR48(VAR48),.VAR1(VAR1),.VAR9(VAR9),.VAR64(VAR64));
and VAR8(VAR31,VAR53,VAR25);
not VAR49(VAR42,VAR57);
and VAR40(VAR51,VAR25,VAR42);
and VAR30(VAR44,VAR53,VAR51);
and VAR18(VAR59,VAR25,VAR57);
and VAR50(VAR39,VAR53,VAR59);
buf VAR41(VAR28,VAR53);
not VAR32(VAR17,VAR57);
not VAR29(VAR47,VAR6);
and VAR22(VAR65,VAR47,VAR17);
and VAR2(VAR24,VAR53,VAR65);
not VAR34(VAR45,VAR6);
and VAR15(VAR19,VAR45,VAR57);
and VAR14(VAR43,VAR53,VAR19);
not VAR33(VAR63,VAR57);
not VAR10(VAR54,VAR6);
and VAR3(VAR38,VAR54,VAR63);
not VAR61(VAR56,VAR6);
and VAR62(VAR11,VAR56,VAR57);
buf VAR23(VAR35,VAR25);
not VAR7(VAR5,VAR57);
not VAR27(VAR4,VAR6);
and VAR46(VAR58,VAR4,VAR5);
and VAR52(VAR20,VAR25,VAR58);
not VAR36(VAR16,VAR6);
and VAR21(VAR13,VAR16,VAR57);
and VAR55(VAR37,VAR25,VAR13);
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlrbn/sky130_fd_sc_lp__dlrbn.behavioral.pp.v
| 2,608 |
module MODULE1 (
VAR1 ,
VAR15 ,
VAR2,
VAR3 ,
VAR10 ,
VAR13 ,
VAR24 ,
VAR7 ,
VAR6
);
output VAR1 ;
output VAR15 ;
input VAR2;
input VAR3 ;
input VAR10 ;
input VAR13 ;
input VAR24 ;
input VAR7 ;
input VAR6 ;
wire VAR17 ;
wire VAR26 ;
reg VAR23 ;
wire VAR16 ;
wire VAR22 ;
wire VAR19 ;
wire VAR11;
wire VAR12 ;
wire VAR18 ;
wire VAR20 ;
wire VAR14 ;
not VAR8 (VAR17 , VAR11 );
not VAR9 (VAR26, VAR22 );
VAR4 VAR21 (VAR12 , VAR16, VAR26, VAR17, VAR23, VAR13, VAR24);
assign VAR18 = ( VAR13 === 1'b1 );
assign VAR20 = ( VAR18 && ( VAR11 === 1'b1 ) );
assign VAR14 = ( VAR18 && ( VAR2 === 1'b1 ) );
buf VAR5 (VAR1 , VAR12 );
not VAR25 (VAR15 , VAR12 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o21ai/sky130_fd_sc_hs__o21ai.functional.v
| 1,929 |
module MODULE1 (
VAR1,
VAR11,
VAR4 ,
VAR7 ,
VAR14 ,
VAR3
);
input VAR1;
input VAR11;
output VAR4 ;
input VAR7 ;
input VAR14 ;
input VAR3 ;
wire VAR2 ;
wire VAR13 ;
wire VAR8;
or VAR10 (VAR2 , VAR14, VAR7 );
nand VAR12 (VAR13 , VAR3, VAR2 );
VAR9 VAR6 (VAR8, VAR13, VAR1, VAR11);
buf VAR5 (VAR4 , VAR8 );
endmodule
|
apache-2.0
|
tmatsuya/milkymist-ml401
|
cores/lm32/rtl/lm32_jtag.v
| 16,400 |
module MODULE1 (
VAR60,
VAR9,
VAR31,
VAR50,
VAR55,
VAR14,
VAR48,
VAR22,
VAR58,
VAR39,
VAR68,
VAR5,
VAR24,
VAR1,
VAR17,
VAR13,
VAR36,
VAR56,
VAR16,
VAR35,
VAR59,
VAR7,
VAR15,
VAR46,
VAR52,
VAR18
);
parameter VAR54 = VAR65;
input VAR60; input VAR9;
input VAR31; input VAR50; input [VAR11] VAR55; input [2:0] VAR14;
input [VAR53] VAR48; input VAR22; input [VAR28] VAR58; input VAR39; VAR4
input [VAR11] VAR68; input VAR5; VAR4
input VAR24; VAR4
output [VAR28] VAR1; wire [VAR28] VAR1;
output [VAR28] VAR17; wire [VAR28] VAR17;
output VAR13; reg VAR13;
output [VAR28] VAR36; wire [VAR28] VAR36;
output [VAR53] VAR56; wire [VAR53] VAR56;
output VAR16; reg VAR16;
output VAR35; reg VAR35;
output [VAR11] VAR59; wire [VAR11] VAR59;
output [VAR28] VAR7; wire [VAR28] VAR7;
output VAR15; reg VAR15;
output VAR46; reg VAR46;
output [VAR11] VAR52;
reg [VAR11] VAR52;
output [2:0] VAR18;
wire [2:0] VAR18;
reg VAR38; reg VAR34; reg VAR3; reg VAR6;
reg [VAR11] VAR25;
reg [2:0] VAR64;
reg [VAR11] VAR8; reg VAR29; reg [VAR11] VAR62; reg VAR41; VAR4
reg [VAR2] VAR51; VAR49 VAR40
reg [VAR11] VAR67; reg [VAR11] VAR20;
reg [VAR11] VAR43;
reg [VAR11] VAR12;
reg [VAR11] VAR37;
reg VAR63; VAR4
reg [VAR19] state;
assign VAR36 = {VAR67, VAR20, VAR43, VAR12};
assign VAR56 = VAR37[VAR53];
assign VAR7 = {VAR67, VAR20, VAR43, VAR12};
assign VAR59 = VAR37;
assign VAR18[1:0] = {VAR41, VAR29};
assign VAR18[1:0] = 2'b00;
assign VAR18[2] = VAR63;
assign VAR18[2] = 1'b0;
assign VAR1 = {{VAR47-9{1'b0}}, VAR29, 8'h00};
assign VAR17 = {{VAR47-9{1'b0}}, VAR41, VAR62};
always @(negedge VAR50 VAR23)
begin
if (VAR9 == VAR57)
VAR38 <= 1'b0;
end
else
VAR38 <= ~VAR38;
end
always @(*)
begin
VAR25 = VAR55;
VAR64 = VAR14;
end
always @(posedge VAR60 VAR23)
begin
if (VAR9 == VAR57)
begin
VAR34 <= 1'b0;
VAR3 <= 1'b0;
VAR6 <= 1'b0;
end
else
begin
VAR34 <= VAR38;
VAR3 <= VAR34;
VAR6 <= VAR3;
end
end
always @(posedge VAR60 VAR23)
begin
if (VAR9 == VAR57)
begin
state <= VAR44;
VAR51 <= 4'b0000;
VAR52 <= 8'h00;
VAR63 <= VAR33;
VAR13 <= VAR33;
VAR16 <= VAR33;
VAR35 <= VAR33;
VAR15 <= VAR33;
VAR46 <= VAR33;
VAR8 <= 8'h00;
VAR29 <= VAR33;
VAR62 <= 8'h00;
VAR41 <= VAR33;
end
else
begin
if ((VAR22 == VAR57) && (VAR39 == VAR33))
begin
case (VAR48)
begin
VAR8 <= VAR58[VAR32];
VAR29 <= VAR57;
end
begin
VAR41 <= VAR33;
end
endcase
end
if (VAR24 == VAR57)
begin
VAR15 <= VAR33;
VAR46 <= VAR33;
end
case (state)
begin
if (VAR3 != VAR6)
begin
VAR51 <= VAR25[7:4];
case (VAR64)
begin
case (VAR25[7:4])
state <= VAR21;
begin
{VAR43, VAR12} <= {VAR43, VAR12} + 1'b1;
state <= VAR26;
end
state <= VAR21;
begin
{VAR43, VAR12} <= {VAR43, VAR12} + 1'b1;
state <= 5;
end
state <= VAR21;
begin
VAR41 <= VAR33;
VAR29 <= VAR33;
VAR15 <= VAR57;
end
begin
VAR41 <= VAR33;
VAR29 <= VAR33;
VAR46 <= VAR57;
end
endcase
end
begin
VAR62 <= VAR25;
VAR41 <= VAR57;
end
begin
VAR52 <= VAR8;
VAR29 <= VAR33;
end
default:
;
endcase
end
end
begin
if (VAR3 != VAR6)
begin
VAR67 <= VAR25;
state <= VAR10;
end
end
begin
if (VAR3 != VAR6)
begin
VAR20 <= VAR25;
state <= VAR45;
end
end
begin
if (VAR3 != VAR6)
begin
VAR43 <= VAR25;
state <= VAR30;
end
end
begin
if (VAR3 != VAR6)
begin
VAR12 <= VAR25;
if (VAR51 == VAR42)
state <= VAR26;
end
else
state <= VAR66;
end
end
begin
if (VAR3 != VAR6)
begin
VAR37 <= VAR25;
state <= VAR26;
end
end
begin
case (VAR51)
begin
VAR16 <= VAR57;
VAR63 <= VAR57;
state <= VAR61;
end
begin
VAR35 <= VAR57;
VAR63 <= VAR57;
state <= VAR61;
end
begin
VAR13 <= VAR57;
VAR63 <= VAR57;
state <= VAR27;
end
endcase
end
begin
if (VAR5 == VAR57)
begin
VAR16 <= VAR33;
VAR52 <= VAR68;
VAR35 <= VAR33;
VAR63 <= VAR33;
state <= VAR44;
end
end
begin
VAR13 <= VAR33;
VAR63 <= VAR33;
state <= VAR44;
end
endcase
end
end
endmodule
|
lgpl-3.0
|
lvd2/ngs
|
fpga/obsolete/fpgaE_dma/interrupts/interrupts.v
| 1,303 |
module MODULE1(
VAR12,
VAR9,
VAR8,
VAR10,
VAR2
);
parameter VAR13 = 100;
input VAR12;
input VAR9;
input VAR8;
input VAR10;
output reg VAR2;
reg [9:0] VAR3;
reg VAR11;
reg VAR1,VAR5,VAR14;
reg VAR6,VAR7;
reg VAR4;
always @(posedge VAR12)
begin
if( VAR3 == 10'd639 )
VAR3 <= 10'd0;
end
else
VAR3 <= VAR3 + 10'd1;
if( VAR3 == 10'd0 )
VAR11 <= 1'b1;
else if( VAR3 == VAR13 )
VAR11 <= 1'b0;
end
always @(negedge VAR9)
begin
VAR14 <= VAR5;
VAR5 <= VAR1;
VAR1 <= VAR11;
VAR6 <= ~(VAR8 | VAR10);
VAR7 <= VAR6;
if( VAR7 || ( VAR14 && (!VAR5) ) )
VAR4 <= 1'b0;
end
else if( (!VAR14) && VAR5 )
VAR4 <= 1'b1;
end
always @(posedge VAR9)
begin
VAR2 <= ~VAR4;
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/and4b/sky130_fd_sc_ls__and4b.functional.v
| 1,412 |
module MODULE1 (
VAR9 ,
VAR3,
VAR7 ,
VAR10 ,
VAR4
);
output VAR9 ;
input VAR3;
input VAR7 ;
input VAR10 ;
input VAR4 ;
wire VAR5 ;
wire VAR1;
not VAR6 (VAR5 , VAR3 );
and VAR2 (VAR1, VAR5, VAR7, VAR10, VAR4);
buf VAR8 (VAR9 , VAR1 );
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.functional.v
| 1,046 |
module MODULE1( VAR7, VAR8, VAR1 );
input VAR8, VAR7;
output VAR1;
wire VAR4;
not VAR2( VAR4, VAR8 );
wire VAR3;
not VAR6( VAR3, VAR7 );
or VAR5( VAR1, VAR4, VAR3 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/clkbuf/sky130_fd_sc_lp__clkbuf.behavioral.v
| 1,345 |
module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR2;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR6 ;
wire VAR1;
buf VAR8 (VAR1, VAR4 );
buf VAR9 (VAR5 , VAR1 );
endmodule
|
apache-2.0
|
argonnexraydetector/RoachFirmPy
|
ANLYellowBlocks/mkid_dacadc_4x/ise/mkiddac/ipcore_dir/mmcm_mkid.v
| 7,527 |
module MODULE1
( input VAR63,
input VAR23,
output VAR82,
output VAR15,
output VAR79,
output VAR72,
output VAR61,
output VAR7
);
VAR26 VAR70
(.VAR58 (VAR16),
.VAR45 (VAR63));
wire [15:0] VAR35;
wire VAR60;
wire VAR52;
wire VAR3;
wire VAR53;
wire VAR55;
wire VAR69;
wire VAR41;
wire VAR86;
wire VAR54;
wire VAR17;
wire VAR34;
wire VAR84;
wire VAR20;
VAR49
.VAR22 ("VAR32"),
.VAR6 ("VAR32"),
.VAR38 ("VAR78"),
.VAR1 ("VAR32"),
.VAR2 (1),
.VAR21 (8.000),
.VAR44 (0.000),
.VAR59 ("VAR32"),
.VAR77 (8.000),
.VAR9 (0.000),
.VAR13 (0.500),
.VAR33 ("VAR32"),
.VAR74 (8),
.VAR27 (90.000),
.VAR30 (0.500),
.VAR43 ("VAR32"),
.VAR57 (8),
.VAR12 (180.000),
.VAR75 (0.500),
.VAR19 ("VAR32"),
.VAR11 (8),
.VAR36 (270.000),
.VAR25 (0.500),
.VAR66 ("VAR32"),
.VAR5 (7.812),
.VAR42 (0.010))
VAR51
(.VAR61 (VAR3),
.VAR8 (VAR53),
.VAR80 (VAR10),
.VAR81 (VAR55),
.VAR82 (VAR28),
.VAR24 (VAR69),
.VAR15 (VAR68),
.VAR14 (VAR41),
.VAR79 (VAR48),
.VAR65 (VAR86),
.VAR72 (VAR54),
.VAR64 (VAR17),
.VAR31 (VAR34),
.VAR23 (VAR23),
.VAR63 (VAR16),
.VAR50 (1'b0),
.VAR73 (1'b1),
.VAR62 (7'h0),
.VAR39 (1'b0),
.VAR46 (1'b0),
.VAR4 (16'h0),
.VAR56 (VAR35),
.VAR40 (VAR60),
.VAR29 (1'b0),
.VAR18 (1'b0),
.VAR83 (1'b0),
.VAR67 (1'b0),
.VAR76 (VAR52),
.VAR7 (VAR7),
.VAR85 (VAR20),
.VAR71 (VAR84),
.VAR37 (1'b0),
.VAR47 (1'b0));
assign VAR61 = VAR3;
assign VAR82 = VAR10;
assign VAR15 = VAR28;
assign VAR79 = VAR68;
assign VAR72 = VAR48;
endmodule
|
gpl-2.0
|
sergev/vak-opensource
|
hardware/s3esk-openrisc/or1200/or1200_wbmux.v
| 5,879 |
module MODULE1(
clk, rst,
VAR8, VAR4,
VAR13, VAR1, VAR2, VAR11,
VAR7, VAR9, VAR12
);
parameter VAR10 = VAR5;
input clk;
input rst;
input VAR8;
input [VAR3-1:0] VAR4;
input [VAR10-1:0] VAR13;
input [VAR10-1:0] VAR1;
input [VAR10-1:0] VAR2;
input [VAR10-1:0] VAR11;
output [VAR10-1:0] VAR7;
output [VAR10-1:0] VAR9;
output VAR12;
reg [VAR10-1:0] VAR7;
reg [VAR10-1:0] VAR9;
reg VAR12;
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR9 <= 32'd0;
VAR12 <= 1'b0;
end
else if (!VAR8) begin
VAR9 <= VAR7;
VAR12 <= VAR4[0];
end
end
always @(VAR13 or VAR1 or VAR2 or VAR11 or VAR4) begin
end
case(VAR4[VAR3-1:1]) else
case(VAR4[VAR3-1:1]) VAR6
2'b00: VAR7 = VAR13;
2'b01: begin
VAR7 = VAR1;
end
2'b10: begin
VAR7 = VAR2;
end
2'b11: begin
VAR7 = VAR11 + 32'h8;
end
endcase
end
endmodule
|
apache-2.0
|
The-OpenROAD-Project/asap7
|
asap7sc6t_26/Verilog/asap7sc6t_OA_SRAM_FF_210930.v
| 242,336 |
module MODULE1 (VAR11, VAR2, VAR9, VAR7, VAR13, VAR10);
output VAR11;
input VAR2, VAR9, VAR7, VAR13, VAR10;
wire VAR8, VAR1, VAR5;
wire VAR12, VAR3, VAR6;
wire VAR4;
not (VAR3, VAR10);
not (VAR12, VAR13);
not (VAR5, VAR7);
and (VAR6, VAR5, VAR12);
not (VAR1, VAR9);
not (VAR8, VAR2);
and (VAR4, VAR8, VAR1, VAR12);
or (VAR11, VAR4, VAR6, VAR3);
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/conb/sky130_fd_sc_lp__conb_1.v
| 2,042 |
module MODULE1 (
VAR7 ,
VAR4 ,
VAR8,
VAR1,
VAR3 ,
VAR6
);
output VAR7 ;
output VAR4 ;
input VAR8;
input VAR1;
input VAR3 ;
input VAR6 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7,
VAR4
);
output VAR7;
output VAR4;
supply1 VAR8;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR6 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_abot/niosii/synthesis/submodules/niosii_nios2_gen2_0.v
| 5,770 |
module MODULE1 (
input wire clk, input wire VAR13, input wire VAR17, output wire [22:0] VAR3, output wire [3:0] VAR4, output wire VAR16, input wire [31:0] VAR10, input wire VAR20, output wire VAR14, output wire [31:0] VAR2, output wire VAR6, output wire [22:0] VAR9, output wire VAR25, input wire [31:0] VAR1, input wire VAR21, input wire [31:0] irq, output wire VAR22, input wire [8:0] VAR11, input wire [3:0] VAR5, input wire VAR26, input wire VAR23, output wire [31:0] VAR8, output wire VAR19, input wire VAR24, input wire [31:0] VAR7, output wire VAR12 );
VAR18 VAR15 (
.clk (clk), .VAR13 (VAR13), .VAR17 (VAR17), .VAR3 (VAR3), .VAR4 (VAR4), .VAR16 (VAR16), .VAR10 (VAR10), .VAR20 (VAR20), .VAR14 (VAR14), .VAR2 (VAR2), .VAR6 (VAR6), .VAR9 (VAR9), .VAR25 (VAR25), .VAR1 (VAR1), .VAR21 (VAR21), .irq (irq), .VAR22 (VAR22), .VAR11 (VAR11), .VAR5 (VAR5), .VAR26 (VAR26), .VAR23 (VAR23), .VAR8 (VAR8), .VAR19 (VAR19), .VAR24 (VAR24), .VAR7 (VAR7), .VAR12 (VAR12) );
endmodule
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v
| 3,360 |
module MODULE1(
VAR58,
VAR34,
VAR65,
VAR40,
VAR17,
VAR48,
VAR5,
VAR66,
VAR11,
VAR26,
VAR61,
VAR49,
VAR8,
VAR13,
VAR39,
VAR53,
VAR19,
VAR32,
VAR51,
VAR18,
VAR9,
VAR56,
VAR6,
VAR1,
VAR20,
VAR15,
VAR63,
VAR64,
VAR42,
VAR59,
VAR27,
VAR21,
VAR7,
VAR67,
VAR30,
VAR50,
VAR55,
VAR43
);
input VAR58;
input VAR34;
input [VAR2-1:0] VAR65;
input [VAR2-1:0] VAR40;
input [VAR2-1:0] VAR17;
input [VAR2-1:0] VAR48;
input [VAR2-1:0] VAR27;
input [VAR2-1:0] VAR21;
output VAR5;
input [VAR3-1:0] VAR66;
input [VAR62-1:0] VAR11;
input [VAR12:0] VAR26;
output VAR61;
input VAR49;
input [VAR62-1:0] VAR8;
input [VAR12:0] VAR13;
output [VAR3-1:0] VAR39;
output VAR53;
output VAR19;
input [VAR3-1:0] VAR32;
input [VAR62-1:0] VAR51;
input [VAR12:0] VAR18;
output VAR9;
input VAR56;
input [VAR62-1:0] VAR6;
input [VAR12:0] VAR1;
output [VAR3-1:0] VAR20;
output VAR15;
input VAR63;
output VAR64;
output [VAR62-1:0]VAR7;
output [VAR3-1:0]VAR67;
output [VAR12:0]VAR30;
input VAR59;
input [VAR3-1:0] VAR55;
output VAR42;
output [VAR62-1:0] VAR50;
output [VAR12:0] VAR43;
VAR4 VAR23(
.VAR34(VAR34),
.VAR58(VAR58),
.VAR57(VAR65),
.VAR38(VAR17),
.VAR52(VAR61),
.VAR54(VAR9),
.VAR44(VAR66),
.VAR46(VAR32),
.VAR35(VAR11),
.VAR37(VAR51),
.VAR14(VAR26),
.VAR29(VAR18),
.VAR22(VAR5),
.VAR33(VAR19),
.VAR41(VAR64),
.VAR16(VAR21),
.VAR24(VAR67),
.VAR28(VAR7),
.VAR31(VAR30),
.VAR60(VAR63)
);
VAR45 VAR47(
.VAR34(VAR34),
.VAR58(VAR58),
.VAR57(VAR40),
.VAR38(VAR48),
.VAR36(VAR49),
.VAR25(VAR56),
.VAR44(VAR39),
.VAR46(VAR20),
.VAR35(VAR8),
.VAR37(VAR6),
.VAR14(VAR13),
.VAR29(VAR1),
.VAR52(VAR53),
.VAR54(VAR15),
.VAR16(VAR27),
.VAR41(VAR42),
.VAR24(VAR55),
.VAR28(VAR50),
.VAR31(VAR43),
.VAR10(VAR59)
);
endmodule
|
mit
|
velizarefremov/MIPS
|
Part 2/Verilog Code/muxparam.v
| 1,559 |
module MODULE1
parameter VAR9 = 16)
( output [(VAR9-1):0] VAR11,
input [(VAR9*VAR2-1):0] VAR7,
input [(VAR10(VAR2)-1):0] sel
);
localparam VAR12 = VAR10(VAR2);
integer VAR3, VAR5, VAR1;
wire [(VAR9-1):0] VAR4 [(VAR2-1):0];
reg [(VAR9-1):0] VAR6 [VAR12:0][(2**VAR12-1):0];
genvar VAR13;
generate
for (VAR13=0; VAR13 < VAR2; VAR13=VAR13+1) begin : VAR8
assign VAR4[VAR13] = VAR7[((VAR13+1)*VAR9-1) : VAR13*VAR9];
end
endgenerate
always @(VAR4, sel, VAR6) begin
for(VAR3=0; VAR3< 2**VAR12; VAR3 = VAR3 + 1) begin
if(VAR3 < VAR2)
VAR6[VAR12][VAR3] <= VAR4[VAR3];
end
else
VAR6[VAR12][VAR3] <= 0;
end
for(VAR5=(VAR12-1); VAR5 >= 0; VAR5 = VAR5 - 1) begin
for(VAR1=0; VAR1 < 2**VAR5; VAR1 = VAR1 + 1) begin
if(sel[(VAR12-1)-VAR5] == 0)
VAR6[VAR5][VAR1] <= VAR6[VAR5+1][2*VAR1];
end
else
VAR6[VAR5][VAR1] <= VAR6[VAR5+1][2*VAR1+1];
end
end
end
assign VAR11 = VAR6[0][0];
endmodule
|
gpl-2.0
|
iafnan/es2-hardwaresecurity
|
or1200/rtl/verilog/or1200/or1200_spram_128x32.v
| 7,515 |
module MODULE1(
VAR5, VAR8, VAR2,
clk, rst, VAR22, VAR15, VAR25, addr, VAR26, VAR6
);
parameter VAR20 = 7;
parameter VAR12 = 32;
input VAR5;
input [VAR17 - 1:0] VAR2;
output VAR8;
input clk; input rst; input VAR22; input VAR15; input VAR25; input [VAR20-1:0] addr; input [VAR12-1:0] VAR26; output [VAR12-1:0] VAR6;
VAR9 VAR14(
.VAR11(clk),
.VAR4(rst),
.VAR24({1'b0, addr}),
.VAR18(VAR26[15:0]),
.VAR16(VAR22),
.VAR1(VAR15),
.VAR27(VAR6[15:0])
);
VAR9 VAR3(
.VAR11(clk),
.VAR4(rst),
.VAR24({1'b0, addr}),
.VAR18(VAR26[31:16]),
.VAR16(VAR22),
.VAR1(VAR15),
.VAR27(VAR6[31:16])
);
VAR10 VAR21(
.VAR11(clk),
.VAR28(rst),
.VAR24({2'b00, addr}),
.VAR18(VAR26),
.VAR13(4'h0),
.VAR16(VAR22),
.VAR1(VAR15),
.VAR27(VAR6),
.VAR19()
);
reg [VAR12-1:0] VAR7 [(1<<VAR20)-1:0]; reg [VAR20-1:0] VAR23;
assign VAR6 = (VAR25) ? VAR7[VAR23] : {VAR12{1'b0}};
always @(posedge clk or posedge rst)
if (rst)
VAR23 <= {VAR20{1'b0}};
else if (VAR22)
VAR23 <= addr;
always @(posedge clk)
if (VAR22 && VAR15)
VAR7[addr] <= VAR26;
endmodule
|
gpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/src/stubs/hdl/PLLE2_BASE.v
| 1,589 |
module MODULE1 (
VAR19, VAR4, VAR15, VAR14, VAR12, VAR9, VAR3,
VAR21,
VAR20, VAR17, VAR16, VAR37
);
parameter VAR27 = 0;
parameter VAR26 = 0;
parameter VAR22 = 0;
parameter VAR25 = 0;
parameter VAR11 = 0;
parameter VAR7 = 0;
parameter VAR1 = 0;
parameter VAR8 = 0;
parameter VAR5 = 0;
parameter VAR31 = 0;
parameter VAR34 = 0;
parameter VAR6 = 0;
parameter VAR35 = 0;
parameter VAR28 = 0;
parameter VAR30 = 0;
parameter VAR38 = 0;
parameter VAR2 = 0;
parameter VAR36 = 0;
parameter VAR13 = 0;
parameter VAR29 = 0;
parameter VAR32 = 0;
parameter VAR24 = 0;
parameter VAR10 = 0;
parameter VAR33 = 0;
parameter VAR23 = 0;
parameter VAR18 = 0;
input VAR20;
input VAR17;
input VAR16;
input VAR37;
output VAR19;
output VAR4;
output VAR15;
output VAR14;
output VAR12;
output VAR9;
output VAR3;
output VAR21;
assign VAR21=VAR20;
assign VAR19=1'b0;
assign VAR4=VAR20;
assign VAR15=VAR20;
assign VAR14=VAR20;
assign VAR12=VAR20;
assign VAR9=VAR20;
assign VAR3=VAR20;
assign VAR21=VAR20;
endmodule
|
gpl-3.0
|
olajep/oh
|
src/elink/hdl/erx_clocks.v
| 7,275 |
module MODULE1 (
VAR24, VAR36, VAR106, VAR50, VAR45,
VAR40, VAR34, VAR44, VAR29, VAR69
);
parameter VAR14 = 300;
parameter VAR19 = 200;
parameter VAR85 = 0; parameter VAR57 = 4; parameter VAR83 = VAR13; parameter VAR39 = VAR35;
parameter VAR8 = 4; else
parameter VAR8 = 8; VAR20
localparam real VAR6 = 1000.000000 / VAR14; localparam integer VAR84 = VAR57 * VAR14 / VAR19;
localparam integer VAR71 = VAR57;
input VAR40; input VAR34; input VAR44;
input VAR29; input VAR69;
output VAR24; output VAR36;
output VAR106; output VAR50; output VAR45;
wire VAR48;
wire VAR22; wire VAR46;
wire VAR30;
wire VAR5;
wire VAR94;
wire VAR68;
wire VAR74;
reg [VAR8:0] VAR111 = 'b0; reg VAR113;
wire VAR79;
reg [2:0] VAR43;
wire VAR99;
reg VAR98;
wire VAR81;
assign VAR74 = VAR40 & VAR44;
always @ (posedge VAR29)
begin
VAR111[VAR8-1:0] <= VAR111[VAR8-1:0]+1'b1;
VAR113 <= ~(|VAR111[VAR8-1:0]);
end
always @ (posedge VAR29 or negedge VAR74)
if(!VAR74)
VAR43[2:0] <= VAR107;
else if(VAR113)
case(VAR43[2:0])
if(~VAR34)
VAR43[2:0] <= VAR31;
if(VAR79 & VAR22)
VAR43[2:0] <= VAR97;
if(VAR34)
VAR43[2:0] <= VAR107; endcase
assign VAR99 = (VAR43[2:0]==VAR107);
assign VAR48 = (VAR43[2:0]==VAR107);
always @ (posedge VAR29)
VAR98 <= ~(VAR43[2:0] != VAR97);
assign VAR106 = (VAR43[2:0] == VAR97);
VAR86 VAR80 ( .VAR55 (VAR45),
.clk (VAR24),
.VAR47 (VAR98)
);
VAR86 VAR32 ( .VAR55 (VAR50),
.clk (VAR36),
.VAR47 (VAR98)
);
generate
if(VAR83=="VAR26")
begin
VAR105
.VAR108("VAR112"),
.VAR102(VAR57),
.VAR41(0.0),
.VAR33(VAR6),
.VAR110(128),
.VAR18(128),
.VAR67(128),
.VAR53(VAR84), .VAR10(VAR71), .VAR75(VAR71*4), .VAR62(0.5),
.VAR38(0.5),
.VAR104(0.5),
.VAR63(0.5),
.VAR89(0.5),
.VAR78(0.5),
.VAR12(0.0),
.VAR77(0.0),
.VAR96(0.0),
.VAR115(0.0),
.VAR114(0.0), .VAR37(0.0), .VAR2(1.0),
.VAR100(0.01),
.VAR82("VAR90")
) VAR95
(
.VAR54(),
.VAR87(),
.VAR17(),
.VAR51(VAR94),
.VAR92(VAR30),
.VAR101(VAR5),
.VAR88(1'b0),
.VAR60(VAR99),
.VAR9(VAR68),
.VAR109(VAR68),
.VAR11(VAR69),
.VAR64(1'b0),
.VAR3(1'b1),
.VAR65(7'b0),
.VAR56(1'b0),
.VAR7(1'b0),
.VAR70(16'b0),
.VAR21(1'b0),
.VAR15(), .VAR103(), .VAR52(VAR81)
);
VAR93 VAR42 (.VAR58(VAR30), .VAR4(VAR24)); VAR93 VAR91 (.VAR58(VAR5), .VAR4(VAR36));
VAR93 VAR76 (.VAR58(VAR94),.VAR4(VAR46));
VAR27 VAR23 (.dout (VAR79),
.clk (VAR29),
.VAR72 (1'b1),
.din (VAR81)
);
if(VAR39=="VAR61")
begin : VAR49
assign VAR22 = 'b1;
VAR66
.VAR59("VAR28")
) VAR16
(
.VAR1(VAR22), .VAR25(VAR46), .VAR60(VAR48)
);
end else begin: VAR73
VAR66 VAR16
(
.VAR1(VAR22), .VAR25(VAR46), .VAR60(VAR48));
end
end endgenerate
endmodule
|
mit
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_qpll_reset.v
| 13,712 |
module MODULE1 #
(
parameter VAR27 = "VAR17", parameter VAR12 = "VAR15", parameter VAR40 = 1, parameter VAR7 = 1
)
(
input VAR6,
input VAR50,
input VAR43,
input [VAR40-1:0] VAR41,
input [(VAR40-1)>>2:0]VAR39,
input [(VAR40-1)>>2:0]VAR36,
input [ 1:0] VAR2,
input [VAR40-1:0] VAR14,
input [VAR40-1:0] VAR29,
output VAR37,
output VAR31,
output VAR48,
output VAR44,
output VAR9,
output [11:0] VAR47
);
reg VAR23;
reg [VAR40-1:0] VAR18;
reg [(VAR40-1)>>2:0]VAR4;
reg [(VAR40-1)>>2:0]VAR45;
reg [ 1:0] VAR24;
reg [VAR40-1:0] VAR42;
reg [VAR40-1:0] VAR13;
reg VAR21;
reg [VAR40-1:0] VAR25;
reg [(VAR40-1)>>2:0]VAR10;
reg [(VAR40-1)>>2:0]VAR26;
reg [ 1:0] VAR32;
reg [VAR40-1:0] VAR5;
reg [VAR40-1:0] VAR19;
reg VAR20 = 1'd0;
reg VAR8 = 1'd1;
reg VAR34 = 1'd0;
reg [11:0] fsm = 12'd2;
localparam VAR1 = 12'b000000000001;
localparam VAR33 = 12'b000000000010;
localparam VAR30 = 12'b000000000100;
localparam VAR49 = 12'b000000001000;
localparam VAR51 = 12'b000000010000;
localparam VAR11 = 12'b000000100000;
localparam VAR46 = 12'b000001000000;
localparam VAR3 = 12'b000010000000;
localparam VAR16 = 12'b000100000000;
localparam VAR28 = 12'b001000000000;
localparam VAR38 = 12'b010000000000;
localparam VAR22 = 12'b100000000000;
always @ (posedge VAR6)
begin
if (!VAR50)
begin
VAR23 <= 1'd0;
VAR18 <= {VAR40{1'd1}};
VAR4 <= {(((VAR40-1)>>2)+1){1'd0}};
VAR45 <= {(((VAR40-1)>>2)+1){1'd0}};
VAR24 <= 2'd0;
VAR42 <= {VAR40{1'd1}};
VAR13 <= {VAR40{1'd0}};
VAR21 <= 1'd0;
VAR25 <= {VAR40{1'd1}};
VAR10 <= {(((VAR40-1)>>2)+1){1'd0}};
VAR26 <= {(((VAR40-1)>>2)+1){1'd0}};
VAR32 <= 2'd0;
VAR5 <= {VAR40{1'd1}};
VAR19 <= {VAR40{1'd0}};
end
else
begin
VAR23 <= VAR43;
VAR18 <= VAR41;
VAR4 <= VAR39;
VAR45 <= VAR36;
VAR24 <= VAR2;
VAR42 <= VAR14;
VAR13 <= VAR29;
VAR21 <= VAR23;
VAR25 <= VAR18;
VAR10 <= VAR4;
VAR26 <= VAR45;
VAR32 <= VAR24;
VAR5 <= VAR42;
VAR19 <= VAR13;
end
end
always @ (posedge VAR6)
begin
if (!VAR50)
begin
fsm <= VAR33;
VAR20 <= 1'd0;
VAR8 <= 1'd1;
VAR34 <= 1'd0;
end
else
begin
case (fsm)
VAR1 :
begin
if (!VAR50)
begin
fsm <= VAR33;
VAR20 <= 1'd0;
VAR8 <= 1'd1;
VAR34 <= 1'd0;
end
else
begin
fsm <= VAR1;
VAR20 <= VAR20;
VAR8 <= &VAR5;
VAR34 <= &VAR19;
end
end
VAR33 :
begin
fsm <= ((&(~VAR25)) && (&(~VAR26)) ? VAR30 : VAR33);
VAR20 <= VAR20;
VAR8 <= VAR8;
VAR34 <= VAR34;
end
VAR30 :
begin
fsm <= ((VAR21 && (&VAR25)) ? VAR49 : VAR30);
VAR20 <= VAR20;
VAR8 <= VAR8;
VAR34 <= VAR34;
end
VAR49:
begin
fsm <= (&(~VAR10) ? VAR51 : VAR49);
VAR20 <= VAR20;
VAR8 <= VAR8;
VAR34 <= VAR34;
end
VAR51 :
begin
fsm <= (&VAR10 ? VAR11 : VAR51);
VAR20 <= VAR20;
VAR8 <= VAR8;
VAR34 <= VAR34;
end
VAR11 :
begin
fsm <= (&VAR26 ? ((VAR7 == 1) ? VAR38 : VAR46) : VAR11);
VAR20 <= VAR20;
VAR8 <= 1'd0;
VAR34 <= VAR34;
end
VAR46:
begin
fsm <= (&(~VAR10) ? VAR3 : VAR46);
VAR20 <= 1'd1;
VAR8 <= VAR8;
VAR34 <= VAR34;
end
VAR3 :
begin
if (&VAR10)
begin
fsm <= ((VAR27 == "VAR52") ? VAR16 : VAR38);
VAR20 <= VAR20;
VAR8 <= (VAR27 == "VAR52");
VAR34 <= VAR34;
end
else
begin
fsm <= VAR3;
VAR20 <= VAR20;
VAR8 <= VAR8;
VAR34 <= VAR34;
end
end
VAR16 :
begin
fsm <= (&(~VAR26) ? VAR28 : VAR16);
VAR20 <= VAR20;
VAR8 <= 1'd1;
VAR34 <= 1'd0;
end
VAR28 :
begin
fsm <= (&VAR26 ? VAR1 : VAR28);
VAR20 <= VAR20;
VAR8 <= 1'd0;
VAR34 <= 1'd0;
end
VAR38 :
begin
fsm <= VAR22;
VAR20 <= VAR20;
VAR8 <= (VAR27 == "VAR17") ? (VAR32 != 2'd2) : 1'd0;
VAR34 <= VAR34;
end
VAR22 :
begin
fsm <= VAR1;
VAR20 <= VAR20;
VAR8 <= VAR8;
VAR34 <= (VAR27 == "VAR17") ? (VAR32 != 2'd2) : 1'd0;
end
default :
begin
fsm <= VAR33;
VAR20 <= 1'd0;
VAR8 <= 1'd0;
VAR34 <= 1'd0;
end
endcase
end
end
assign VAR37 = VAR20;
assign VAR31 = (fsm == VAR49) || (fsm == VAR46);
assign VAR48 = VAR8;
assign VAR44 = ((VAR12 == "VAR35") ? 1'd0 : VAR34);
assign VAR9 = (fsm == VAR1);
assign VAR47 = fsm;
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dfrtn/sky130_fd_sc_hd__dfrtn.behavioral.pp.v
| 2,391 |
module MODULE1 (
VAR2 ,
VAR14 ,
VAR12 ,
VAR17,
VAR23 ,
VAR21 ,
VAR10 ,
VAR16
);
output VAR2 ;
input VAR14 ;
input VAR12 ;
input VAR17;
input VAR23 ;
input VAR21 ;
input VAR10 ;
input VAR16 ;
wire VAR11 ;
wire VAR9 ;
wire VAR19 ;
reg VAR15 ;
wire VAR1 ;
wire VAR20;
wire VAR6 ;
wire VAR4 ;
wire VAR8 ;
wire VAR7 ;
not VAR22 (VAR9 , VAR20 );
not VAR5 (VAR19, VAR6 );
VAR3 VAR13 (VAR11 , VAR1, VAR19, VAR9, VAR15, VAR23, VAR21);
assign VAR4 = ( VAR23 === 1'b1 );
assign VAR8 = ( VAR4 && ( VAR20 === 1'b1 ) );
assign VAR7 = ( VAR4 && ( VAR17 === 1'b1 ) );
buf VAR18 (VAR2 , VAR11 );
endmodule
|
apache-2.0
|
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/clk_bluetooth/clk_bluetooth_stub.v
| 1,286 |
module MODULE1(VAR1, VAR2, VAR3, VAR5, VAR4)
;
output VAR1;
output VAR2;
input VAR3;
output VAR5;
input VAR4;
endmodule
|
gpl-3.0
|
hydai/Verilog-Practice
|
DigitalDesign/Final/final/final_101062124/risc_t.v
| 3,734 |
module MODULE1;
parameter VAR27 = 32;
parameter VAR16 = 32;
parameter VAR35 = 2048;
parameter VAR18 = 7;
parameter VAR54 = 5;
parameter VAR63 = 15;
parameter period = 20;
parameter delay = 1;
parameter VAR55 = "03division-VAR13.VAR15";
parameter VAR8 = "03division-VAR33.VAR15";
parameter VAR67 = "VAR59.VAR47";
parameter VAR25 = "VAR26.VAR60";
parameter VAR37 = "VAR38.VAR60";
parameter VAR34 = "VAR26.VAR68";
parameter VAR11 = "VAR38.VAR68";
parameter VAR7 = 20;
parameter VAR46 = 32'b11111111111111111111111111111111;
reg clk;
reg VAR65;
wire [31:0] VAR2, VAR44, VAR70;
wire VAR1, VAR19;
reg VAR51;
reg VAR30;
reg [10:0] VAR20;
reg [31:0] VAR6;
reg VAR50;
wire [31:0] VAR14;
reg VAR41;
reg VAR45;
reg [10:0] VAR23;
reg [31:0] VAR48;
reg VAR49;
wire [31:0] VAR32;
reg [VAR27 - 1:0] VAR3;
reg [VAR27 - 1:0] VAR4;
reg [VAR27 - 1:0] VAR24;
reg [VAR18 - 1:0] VAR61;
reg [VAR54 - 1:0] VAR31, VAR22, VAR64, VAR28;
reg signed [VAR63 - 1:0] VAR62;
VAR71 #(
.VAR5(VAR55)
) VAR43 (
.VAR29(VAR14),
.VAR58(clk),
.VAR21(VAR51),
.VAR69(VAR30),
.VAR17(VAR20),
.VAR57(VAR6),
.VAR52(VAR50)
);
VAR71 #(
.VAR5(VAR8)
) VAR9 (
.VAR29(VAR32),
.VAR58(clk),
.VAR21(VAR41),
.VAR69(VAR45),
.VAR17(VAR23),
.VAR57(VAR48),
.VAR52(VAR49)
);
VAR10 VAR53 (
.VAR36(VAR2),
.VAR42(VAR44),
.address(VAR70),
.VAR66(VAR1),
.VAR12(VAR19),
.VAR56(VAR14),
.VAR39(VAR32),
.clk(clk),
.VAR40(VAR65)
);
always #(period/2) clk = ~clk;
begin
begin
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.behavioral.v
| 1,620 |
module MODULE1( VAR3, VAR7, VAR2, VAR6 );
input VAR6, VAR7, VAR2;
output VAR3;
VAR4 VAR5(.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6));
VAR4 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6));
|
apache-2.0
|
asicguy/gplgpu
|
hdl/ramdac_sp/pix_pll.v
| 14,492 |
module MODULE1
(
input VAR46,
input VAR79,
input [2:0] VAR53,
input [1:0] VAR94,
input VAR41,
input [7:0] VAR13, VAR25,
input [7:0] VAR30, VAR69,
input [7:0] VAR85, VAR15,
input [7:0] VAR67, VAR20,
input VAR87,
output reg [6:0] VAR97,
output reg [5:0] VAR98,
output reg [2:0] VAR31,
output reg VAR39,
output reg VAR52,
output reg [3:0] VAR12,
output reg [2:0] VAR16,
output reg [8:0] VAR9,
output reg VAR50,
output reg VAR57
);
reg VAR60;
reg VAR77, VAR80;
reg [1:0] VAR21;
reg VAR93, VAR23;
reg [21:0] VAR19; reg VAR75;
reg VAR18;
reg [4:0] VAR96;
enum {
VAR63 = 4'h0,
VAR35 = 4'h1,
VAR82 = 4'h2,
VAR89 = 4'h3,
VAR22 = 4'h4,
VAR54 = 4'h5,
VAR104 = 4'h6,
VAR3 = 4'h7,
VAR43 = 4'h8,
VAR10 = 4'h9,
VAR58 = 4'hA,
VAR68 = 4'hB,
VAR88 = 4'hC,
VAR11 = 4'hD,
VAR8 = 4'hE,
VAR42 = 4'hF
} VAR45;
parameter
VAR63 = 4'h0,
VAR35 = 4'h1,
VAR82 = 4'h2,
VAR89 = 4'h3,
VAR22 = 4'h4,
VAR54 = 4'h5,
VAR104 = 4'h6,
VAR3 = 4'h7,
VAR43 = 4'h8,
VAR10 = 4'h9,
VAR58 = 4'hA,
VAR68 = 4'hB,
VAR88 = 4'hC,
VAR11 = 4'hD,
VAR8 = 4'hE,
VAR42 = 4'hF;
reg [3:0] VAR45;
wire VAR28;
wire [8:0] VAR27;
reg [8:0] VAR33;
wire [8:0] VAR81;
reg [9:0] VAR62;
wire [9:0] VAR4;
wire [21:0] VAR101;
wire [9:0] VAR24;
reg [6:0] VAR59;
assign VAR101 = {VAR31, VAR97, VAR98};
assign VAR28 = (VAR19 != VAR101);
always @(posedge VAR46 or negedge VAR79)
if (!VAR79) begin
VAR75 <= 1'b0;
VAR60 <= 1'b0;
VAR39 <= 1'b0;
VAR80 <= 1'b0;
VAR77 <= 1'b0;
VAR19 <= VAR101;
end else begin
VAR60 <= VAR41;
VAR39 <= VAR60;
VAR80 <= VAR18;
VAR77 <= VAR80;
if (VAR75) VAR75 <= ~(VAR77 & ~VAR80);
end
else if (VAR28) begin
VAR19 <= {VAR31, VAR97, VAR98};
VAR75 <= 1'b1;
end
end
always @* begin
casex({VAR39, VAR94, VAR53})
6'VAR91: VAR97[6:0] <= VAR13[5:0] + 7'd65; 6'VAR17: VAR97[6:0] <= VAR30[5:0] + 7'd65; 6'VAR73: VAR97[6:0] <= VAR13[5:0] + 7'd65;
6'VAR99: VAR97[6:0] <= VAR30[5:0] + 7'd65;
6'VAR92: VAR97[6:0] <= VAR85[5:0] + 7'd65;
6'VAR1: VAR97[6:0] <= VAR67[5:0] + 7'd65;
6'VAR32: VAR97[6:0] <= VAR13[6:0] + 7'h1;
6'VAR100: VAR97[6:0] <= VAR85[6:0] + 7'h1;
6'VAR65: VAR97[6:0] <= VAR13[6:0] + 7'h1;
default: VAR97[6:0] <= VAR85[6:0] + 7'h1;
endcase
end
always @* begin
casex({VAR39, VAR94, VAR53})
6'VAR91: VAR21[1:0] <= VAR13[7:6] ;
6'VAR17: VAR21[1:0] <= VAR30[7:6] ;
6'VAR73: VAR21[1:0] <= VAR13[7:6] ;
6'VAR99: VAR21[1:0] <= VAR30[7:6] ;
6'VAR92: VAR21[1:0] <= VAR85[7:6] ;
default: VAR21[1:0] <= VAR67[7:6] ;
endcase
end
always @* begin
casex({VAR21, VAR39, VAR94, VAR53})
8'VAR44: VAR98[5:0] <= {1'b0, VAR25[4:0]};
8'VAR71: VAR98[5:0] <= { VAR25[4:0], 1'b0}; 8'VAR61: VAR98[5:0] <= { VAR25[4:0], 1'b0}; 8'VAR70: VAR98[5:0] <= { VAR25[4:0], 1'b0};
8'VAR64: VAR98[5:0] <= {1'b0, VAR69[4:0]};
8'VAR36: VAR98[5:0] <= { VAR69[4:0], 1'b0}; 8'VAR34: VAR98[5:0] <= { VAR69[4:0], 1'b0}; 8'VAR86: VAR98[5:0] <= { VAR69[4:0], 1'b0};
8'VAR14: VAR98[5:0] <= {1'b0, VAR25[4:0]};
8'VAR29: VAR98[5:0] <= { VAR25[4:0], 1'b0}; 8'VAR47: VAR98[5:0] <= { VAR25[4:0], 1'b0}; 8'VAR83: VAR98[5:0] <= { VAR25[4:0], 1'b0};
8'VAR74: VAR98[5:0] <= {1'b0, VAR69[4:0]};
8'VAR51: VAR98[5:0] <= { VAR69[4:0], 1'b0}; 8'VAR6: VAR98[5:0] <= { VAR69[4:0], 1'b0}; 8'VAR40: VAR98[5:0] <= { VAR69[4:0], 1'b0};
8'VAR56: VAR98[5:0] <= {1'b0, VAR15[4:0]};
8'VAR49: VAR98[5:0] <= { VAR15[4:0], 1'b0}; 8'VAR5: VAR98[5:0] <= { VAR15[4:0], 1'b0}; 8'VAR7: VAR98[5:0] <= { VAR15[4:0], 1'b0};
8'VAR2: VAR98[5:0] <= {1'b0, VAR20[4:0]}; 8'VAR48: VAR98[5:0] <= { VAR20[4:0], 1'b0}; 8'VAR76: VAR98[5:0] <= { VAR20[4:0], 1'b0}; 8'VAR95: VAR98[5:0] <= { VAR20[4:0], 1'b0};
8'VAR37: VAR98[5:0] <= VAR25[5:0] + 6'h1;
8'VAR102: VAR98[5:0] <= VAR15[5:0] + 6'h1;
8'VAR78: VAR98[5:0] <= VAR25[5:0] + 6'h1;
default: VAR98[5:0] <= VAR15[5:0] + 6'h1;
endcase
end
always @* begin
casex({VAR21, VAR39, VAR94, VAR53})
8'VAR72: VAR31[2:0] <= 3'b010; 8'VAR84: VAR31[2:0] <= 3'b001; 8'VAR66: VAR31[2:0] <= 3'b000; 8'VAR38: VAR31[2:0] <= 3'b000; 8'VAR55: VAR31[2:0] <= 3'b010; 8'VAR103: VAR31[2:0] <= 3'b001; 8'VAR26: VAR31[2:0] <= 3'b000; 8'VAR90: VAR31[2:0] <= 3'b000; 8'VAR37: VAR31[2:0] <= VAR30[2:0];
8'VAR102: VAR31[2:0] <= VAR67[2:0];
8'VAR78: VAR31[2:0] <= VAR30[2:0];
default: VAR31[2:0] <= VAR67[2:0];
endcase
end
always @* begin
case(VAR96)
4'h0: begin VAR12 = 4'b0000; VAR16 = 3'h4; VAR9 = {8'h0, (~|VAR98[5:1] & VAR98[0])}; end
4'h1: begin VAR12 = 4'b0000; VAR16 = 3'h5; VAR9 = {8'h0, VAR98[0]}; end
4'h2: begin VAR12 = 4'b0000; VAR16 = 3'h7; VAR9 = {3'h0, VAR98}; end
4'h3: begin VAR12 = 4'b0001; VAR16 = 3'h4; VAR9 = 9'h0; end
4'h4: begin VAR12 = 4'b0001; VAR16 = 3'h5; VAR9 = 9'h0; end
4'h5: begin VAR12 = 4'b0001; VAR16 = 3'h7; VAR9 = {VAR97, 2'b00}; end
4'h6: begin VAR12 = 4'b0010; VAR16 = 3'h0; VAR9 = 9'd1; end 4'h7: begin VAR12 = 4'b0010; VAR16 = 3'h1; VAR9 = 9'd24; end 4'h8: begin VAR12 = 4'b0010; VAR16 = 3'h2; VAR9 = 9'd0; end 4'h9: begin VAR12 = 4'b0011; VAR16 = 3'h0; VAR9 = 9'h0; end
4'hA: begin VAR12 = 4'b0100; VAR16 = 3'h0; VAR9 = {4'h0, VAR31, 2'b00}; end
4'hB: begin VAR12 = 4'b0100; VAR16 = 3'h1; VAR9 = {4'h0, VAR31, 2'b00}; end
4'hC: begin VAR12 = 4'b0100; VAR16 = 3'h4; VAR9 = {8'h0, ~|VAR31}; end
4'hD: begin VAR12 = 4'b0100; VAR16 = 3'h5; VAR9 = 9'h0; end
4'hE: begin VAR12 = VAR59[6:3]; VAR16 = VAR59[2:0]; VAR9 = 9'h0; end
default: begin VAR12 = 4'b0000; VAR16 = 3'h4; VAR9 = 9'h0; end
endcase
end
always @(posedge VAR46, negedge VAR79) begin
if(!VAR79) begin
VAR52 <= 1'b0;
VAR96 <= 4'h0;
VAR50 <= 1'b0;
VAR18 <= 1'b0;
VAR45 <= VAR63;
VAR57 <= 1'b0;
end
else begin
VAR50 <= 1'b0;
VAR52 <= 1'b0;
VAR18 <= 1'b0;
VAR57 <= 1'b0;
case (VAR45)
VAR63: begin
if(VAR28) begin
VAR96 <= 4'b1110;
VAR59 <= 7'h0;
VAR45 <= VAR35;
end
else VAR45 <= VAR63;
end
VAR35: begin
if(!VAR87) begin
VAR52 <= 1'b1;
VAR45 <= VAR82;
end
else VAR45 <= VAR35;
end
VAR82: begin
VAR52 <= 1'b0;
if(~&VAR59) begin
VAR59 <= VAR59 + 7'h1;
VAR45 <= VAR35;
end
else begin
VAR96 <= 4'b0000;
VAR45 <= VAR89;
end
end
VAR89: begin
if(!VAR87) begin
VAR52 <= 1'b1;
VAR45 <= VAR22;
end
else VAR45 <= VAR89;
end
VAR22: VAR45 <= VAR54;
VAR54: begin
if(!VAR87 & (VAR96 == 4'hD)) begin
VAR45 <= VAR104;
VAR96 <= 4'b0000;
end
else if(!VAR87) begin
VAR96 <= VAR96 + 4'b0001;
VAR45 <= VAR89;
end
else VAR45 <= VAR54;
end
VAR104: VAR45 <= VAR3;
VAR3: begin
if(!VAR87) begin
VAR50 <= 1'b1;
VAR45 <= VAR43;
end
else VAR45 <= VAR3;
end
VAR43: VAR45 <= VAR10;
VAR10: begin
if(!VAR87) begin
VAR45 <= VAR58;
VAR18 <= 1'b1;
end
else VAR45 <= VAR10;
end
VAR58: begin VAR45 <= VAR68; VAR57 <= 1'b1; end
VAR68: begin VAR45 <= VAR88; VAR57 <= 1'b1; end
VAR88: begin VAR45 <= VAR11; VAR57 <= 1'b1; end
VAR11: begin VAR45 <= VAR8; VAR57 <= 1'b1; end
VAR8: begin VAR45 <= VAR42; VAR57 <= 1'b1; end
VAR42: VAR45 <= VAR63;
endcase
end
end
endmodule
|
gpl-3.0
|
CospanDesign/nysa-verilog
|
verilog/axi/slave/axi_on_screen_display/rtl/character_buffer.v
| 21,113 |
module MODULE1 #(
parameter VAR60 = 12,
parameter VAR53 = 5,
parameter VAR62 = 8,
parameter VAR84 = 80,
parameter VAR75 = 34,
parameter VAR45 = VAR84 * VAR75
)(
input clk,
input rst,
input VAR20,
input VAR42,
input [2:0] VAR68,
input VAR54,
input [7:0] VAR56,
output VAR83,
input VAR31,
input VAR73,
output reg VAR79,
output [7:0] VAR74,
input VAR33,
input VAR1,
input VAR47
);
localparam VAR58 = 0;
localparam VAR34 = 1;
localparam VAR72 = 2;
localparam VAR69 = 3;
localparam VAR25 = 4;
localparam VAR5 = 5;
localparam VAR71 = 6;
localparam VAR57 = 7;
localparam VAR21 = 8;
localparam VAR22 = 9;
localparam VAR76 = 10;
localparam VAR17 = 1;
localparam VAR7 = 2;
localparam VAR11 = 3;
localparam VAR35 = 4;
localparam VAR87 = (1 << VAR60);
localparam VAR14 = VAR87 / VAR84;
reg [3:0] VAR26;
reg [3:0] VAR8;
reg VAR30;
reg VAR52;
reg [VAR60 :0] VAR66;
wire [VAR60 - 1:0] VAR24;
reg [VAR60 - 1:0] VAR28;
reg [VAR60 - 1:0] VAR51;
wire [VAR60 - 1:0] VAR15;
reg [VAR60 - 1:0] VAR50;
reg [7:0] VAR37;
reg [2:0] VAR2;
wire [7:0] VAR44;
wire VAR9;
wire [VAR60 - 1: 0] VAR23;
reg [VAR60 - 1: 0] VAR38;
reg [VAR60 - 1: 0] VAR67;
reg [VAR60 - 1: 0] VAR86;
reg [VAR60 : 0] VAR64;
wire [VAR60 - 1: 0] VAR4;
reg [VAR60 : 0] VAR61;
wire [VAR60 - 1: 0] VAR46;
reg [VAR60 : 0] VAR40;
wire [VAR60 - 1: 0] VAR81;
reg VAR80;
reg VAR12;
reg VAR41;
reg VAR3;
wire VAR82;
wire VAR77;
wire VAR65;
wire VAR18;
reg [3:0] VAR63;
reg [7:0] VAR49;
reg VAR48;
wire VAR6;
wire [VAR60 - 1: 0] VAR32 = (VAR87 - VAR84);
wire [VAR60 - 1: 0] VAR59 = VAR84;
wire [VAR60 - 1: 0] VAR55 = VAR75;
wire [VAR60 - 1: 0] VAR36 = VAR45;
wire [VAR60 : 0] VAR29 = VAR87;
wire [VAR60 - 1: 0] VAR39 = VAR14;
assign VAR4 = VAR64;
assign VAR46 = VAR61;
assign VAR81 = VAR40;
assign VAR6 = (VAR50 >= VAR75);
VAR19 #(
.VAR70 (8 ),
.VAR10 (VAR60 ) ) VAR13 (
.clk (clk ),
.rst (rst ),
.en (1'b1 ),
.VAR85 (VAR30 ),
.VAR43 (VAR24 ),
.VAR78 (VAR37 ),
.VAR27 (VAR23 ),
.VAR16 (VAR74 )
);
assign VAR82 = (VAR26 != VAR58);
assign VAR83 = !VAR82;
assign VAR77 = (VAR8 != VAR58);
assign VAR9 = (VAR24 == VAR51);
assign VAR15 = VAR51 + 1;
assign VAR23 = VAR18 ? VAR24 : VAR38;
assign VAR24 = VAR66;
assign VAR65 = ((VAR26 == VAR22) ||
(VAR26 == VAR76));
assign VAR18 = ((VAR26 == VAR69) ||
(VAR26 == VAR71) ||
(VAR26 == VAR25) ||
(VAR26 == VAR5));
always @ (posedge clk) begin
VAR30 <= 0;
VAR80 <= 0;
VAR12 <= 0;
VAR41 <= 0;
VAR3 <= 0;
if (rst) begin
VAR37 <= 0;
VAR66 <= 0;
VAR28 <= 0;
VAR51 <= (VAR87 - 1);
VAR2 <= 0;
VAR64 <= VAR32;
VAR61 <= 0;
VAR40 <= VAR84;
VAR26 <= VAR22;
VAR48 <= 0;
VAR50 <= 0;
VAR52 <= 0;
end
else begin
case (VAR26)
VAR58: begin
VAR52 <= 0;
VAR2 <= 0;
if (VAR48 && (VAR8 == VAR58)) begin
VAR48 <= 0;
VAR30 <= 1;
VAR37 <= 0;
VAR66 <= 0;
VAR51 <= ((VAR87) - 1);
VAR26 <= VAR22;
VAR50 <= 0;
end
else if (VAR54) begin
if (VAR20) begin
VAR30 <= 1;
VAR37 <= VAR56;
VAR26 <= VAR34;
end
else begin
case (VAR56)
VAR26 <= VAR72;
end
VAR30 <= 1;
VAR26 <= VAR21;
end
VAR30 <= 1;
VAR26 <= VAR57;
end
VAR30 <= 1;
VAR26 <= VAR57;
end
default: begin
VAR37 <= VAR56;
VAR30 <= 1;
VAR26 <= VAR34;
end
endcase
end
end
end
VAR34: begin
if (VAR9) begin
VAR51 <= VAR51 + 1;
end
VAR66 <= VAR66 + 1;
VAR26 <= VAR58;
end
VAR72: begin
if (!VAR77) begin
VAR26 <= VAR25;
end
end
VAR69: begin
if (VAR52 && (VAR24 == VAR46)) begin
VAR26 <= VAR58;
end
else if (VAR66 != VAR15) begin
VAR66 <= VAR66 - 1;
VAR26 <= VAR25;
end
else begin
VAR26 <= VAR58;
end
end
VAR25: begin
VAR26 <= VAR5;
end
VAR5: begin
VAR26 <= VAR71;
end
VAR71: begin
if (VAR74 == 0) begin
VAR26 <= VAR69;
end
else begin
VAR37 <= 0;
VAR30 <= 1;
VAR26 <= VAR58;
end
end
VAR57: begin
if (VAR66 < VAR40) begin
if (VAR30) begin
VAR66 <= VAR66 + 1;
end
VAR37 <= 0;
VAR30 <= 1;
end
else begin
VAR26 <= VAR76;
end
end
VAR21: begin
if (VAR2 < VAR68) begin
VAR2 <= VAR2 + 1;
VAR37 <= 0;
VAR30 <= 1;
if (VAR9) begin
VAR51 <= VAR51 + 1;
end
VAR66 <= VAR66 + 1;
end
else begin
VAR26 <= VAR58;
end
end
VAR22: begin
VAR64 <= VAR32;
VAR61 <= 0;
VAR40 <= VAR84;
if (!VAR9) begin
VAR30 <= 1;
if (VAR30) begin
VAR37 <= 0;
VAR66 <= VAR66 + 1;
end
end
else begin
VAR37 <= 0;
VAR66 <= 0;
VAR51 <= ((VAR87) - 1);
VAR2 <= 0;
VAR26 <= VAR58;
end
end
default: begin
VAR26 <= VAR58;
end
VAR76: begin
if (VAR66 < VAR40) begin
if (VAR30) begin
VAR66 <= VAR66 + 1;
end
if (VAR9) begin
VAR51 <= VAR51 + 1;
end
VAR37 <= 0;
VAR30 <= 1;
end
else begin
VAR66 <= VAR61;
VAR26 <= VAR58;
end
end
endcase
if (!VAR65) begin
if (VAR66 >= VAR40) begin
VAR41 <= 1;
if (VAR50 < VAR14) begin
VAR50 <= VAR50 + 1;
end
if ((VAR66 > VAR84) &&
(VAR64 > VAR87)) begin
VAR80 <= 1;
VAR64 <= VAR64 + (VAR84 - VAR87);
end
else begin
VAR64 <= VAR64 + VAR84;
end
if ((VAR61 > VAR87) &&
(VAR40 > VAR87)) begin
VAR61 <= VAR61 + (VAR84 - VAR87);
VAR40 <= VAR40 + (VAR84 - VAR87);
VAR66[VAR60] <= 0;
VAR12 <= 1;
end
else begin
VAR40 <= VAR40 + VAR84;
VAR61 <= VAR61 + VAR84;
end
end
else if (VAR18 && (VAR66 < VAR61)) begin
VAR52 <= 1;
if (VAR50 > 0) begin
VAR50 <= VAR50 - 1;
end
if (VAR64 < VAR84) begin
VAR64 <= VAR64 + (VAR87 - VAR84);
end
else begin
VAR64 <= VAR64 - VAR84;
end
if (VAR61 < (2 * VAR84)) begin
VAR61 <= VAR61 + (VAR87 - VAR84);
VAR66 <= VAR66 + VAR87;
end
else begin
VAR61 <= VAR64;
end
if (VAR40 < (3 * VAR84)) begin
VAR40 <= VAR40 + (VAR87 - VAR84);
end
else begin
VAR40 <= VAR61;
end
end
end
if (VAR42) begin
VAR48 <= 1;
end
end
end
always @ (posedge clk) begin
VAR79 <= 0;
if (rst) begin
VAR38 <= 0;
VAR67 <= 0;
VAR49 <= 0;
VAR86 <= 0;
VAR8 <= VAR58;
VAR63 <= 0;
VAR79 <= 0;
end
else begin
case (VAR8)
VAR58: begin
VAR79 <= 0;
VAR63 <= 0;
if (VAR31) begin
VAR8 <= VAR17;
end
end
VAR17: begin
VAR79 <= 0;
VAR63 <= 0;
if (!VAR82) begin
VAR67 <= 0;
VAR38 <= VAR86;
VAR8 <= VAR7;
end
end
VAR7: begin
VAR8 <= VAR11;
end
VAR11: begin
if (VAR73) begin
VAR79 <= 1;
if (VAR49 < (VAR84 - 1)) begin
VAR49 <= VAR49 + 1;
VAR38 <= VAR38 + 1;
end
else begin
VAR49 <= 0;
if (VAR63 < (VAR62 - 1)) begin
VAR63 <= VAR63 + 1;
VAR38 <= VAR38 - (VAR84 - 1);
end
else begin
VAR38 <= VAR38 + 1;
VAR63 <= 0;
VAR67 <= VAR67 + VAR84;
end
end
VAR8 <= VAR35;
end
end
VAR35: begin
if (VAR67 < VAR45) begin
VAR8 <= VAR11;
end
else begin
VAR8 <= VAR58;
end
end
default: begin
end
endcase
if (VAR26 == VAR22) begin
VAR86 <= VAR61;
end
if (VAR6) begin
VAR86 <= (VAR81 - VAR45);
end
if (VAR31) begin
VAR8 <= VAR17;
end
end
end
endmodule
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_0_stub.v
| 4,089 |
module MODULE1(VAR27, VAR35, VAR10,
VAR17, VAR33, VAR39, VAR29, VAR49, VAR25,
VAR30, VAR50, VAR34, VAR7, VAR48, VAR2,
VAR41, VAR51, VAR23, VAR18, VAR36, VAR37, VAR46,
VAR28, VAR22, VAR9, VAR26, VAR45, VAR42,
VAR47, VAR4, VAR13, VAR8, VAR15, VAR43, VAR3,
VAR5, VAR14, VAR24, VAR12, VAR6, VAR32, VAR11,
VAR38, VAR40, VAR16, VAR19, VAR20, VAR44, VAR1,
VAR21, VAR31)
;
input VAR27;
input VAR35;
input [11:0]VAR10;
input [15:0]VAR17;
input [7:0]VAR33;
input [2:0]VAR39;
input [1:0]VAR29;
input VAR49;
input [3:0]VAR25;
input [2:0]VAR30;
input VAR50;
output VAR34;
input [31:0]VAR7;
input [3:0]VAR48;
input VAR2;
input VAR41;
output VAR51;
output [11:0]VAR23;
output [1:0]VAR18;
output VAR36;
input VAR37;
input [11:0]VAR46;
input [15:0]VAR28;
input [7:0]VAR22;
input [2:0]VAR9;
input [1:0]VAR26;
input VAR45;
input [3:0]VAR42;
input [2:0]VAR47;
input VAR4;
output VAR13;
output [11:0]VAR8;
output [31:0]VAR15;
output [1:0]VAR43;
output VAR3;
output VAR5;
input VAR14;
output VAR24;
output VAR12;
output VAR6;
output [3:0]VAR32;
output [15:0]VAR11;
output [31:0]VAR38;
input [31:0]VAR40;
output VAR16;
output VAR19;
output VAR20;
output [3:0]VAR44;
output [15:0]VAR1;
output [31:0]VAR21;
input [31:0]VAR31;
endmodule
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.functional.v
| 1,778 |
module MODULE1( VAR16, VAR1, VAR19, VAR8, VAR7 );
input VAR8, VAR7, VAR1, VAR16;
output VAR19;
wire VAR15;
not VAR22( VAR15, VAR8 );
wire VAR3;
not VAR18( VAR3, VAR1 );
wire VAR12;
and VAR2( VAR12, VAR15, VAR3 );
wire VAR6;
not VAR20( VAR6, VAR16 );
wire VAR11;
and VAR14( VAR11, VAR15, VAR6 );
wire VAR4;
not VAR13( VAR4, VAR7 );
wire VAR5;
and VAR17( VAR5, VAR4, VAR3 );
wire VAR21;
and VAR10( VAR21, VAR4, VAR6 );
or VAR9( VAR19, VAR12, VAR11, VAR5, VAR21 );
endmodule
|
apache-2.0
|
secworks/sha512
|
src/rtl/sha512_w_mem.v
| 8,594 |
module MODULE1(
input wire clk,
input wire VAR30,
input wire [1023 : 0] VAR8,
input wire VAR19,
input wire VAR38,
output wire [63 : 0] VAR36
);
reg [63 : 0] VAR17 [0 : 15];
reg [63 : 0] VAR29;
reg [63 : 0] VAR26;
reg [63 : 0] VAR11;
reg [63 : 0] VAR22;
reg [63 : 0] VAR9;
reg [63 : 0] VAR5;
reg [63 : 0] VAR14;
reg [63 : 0] VAR12;
reg [63 : 0] VAR20;
reg [63 : 0] VAR23;
reg [63 : 0] VAR27;
reg [63 : 0] VAR16;
reg [63 : 0] VAR10;
reg [63 : 0] VAR3;
reg [63 : 0] VAR35;
reg [63 : 0] VAR31;
reg VAR25;
reg [6 : 0] VAR13;
reg [6 : 0] VAR39;
reg VAR32;
reg [63 : 0] VAR2;
reg [63 : 0] VAR6;
assign VAR36 = VAR2;
always @ (posedge clk or negedge VAR30)
begin : VAR34
integer VAR7;
if (!VAR30)
begin
for (VAR7 = 0; VAR7 < 16; VAR7 = VAR7 + 1)
VAR17[VAR7] <= 64'h0;
VAR13 <= 7'h0;
end
else
begin
if (VAR25)
begin
VAR17[00] <= VAR29;
VAR17[01] <= VAR26;
VAR17[02] <= VAR11;
VAR17[03] <= VAR22;
VAR17[04] <= VAR9;
VAR17[05] <= VAR5;
VAR17[06] <= VAR14;
VAR17[07] <= VAR12;
VAR17[08] <= VAR20;
VAR17[09] <= VAR23;
VAR17[10] <= VAR27;
VAR17[11] <= VAR16;
VAR17[12] <= VAR10;
VAR17[13] <= VAR3;
VAR17[14] <= VAR35;
VAR17[15] <= VAR31;
end
if (VAR32)
VAR13 <= VAR39;
end
end
always @*
begin : VAR15
if (VAR13 < 16)
VAR2 = VAR17[VAR13[3 : 0]];
end
else
VAR2 = VAR6;
end
always @*
begin : VAR37
reg [63 : 0] VAR28;
reg [63 : 0] VAR4;
reg [63 : 0] VAR21;
reg [63 : 0] VAR1;
reg [63 : 0] VAR18;
reg [63 : 0] VAR24;
VAR29 = 64'h0;
VAR26 = 64'h0;
VAR11 = 64'h0;
VAR22 = 64'h0;
VAR9 = 64'h0;
VAR5 = 64'h0;
VAR14 = 64'h0;
VAR12 = 64'h0;
VAR20 = 64'h0;
VAR23 = 64'h0;
VAR27 = 64'h0;
VAR16 = 64'h0;
VAR10 = 64'h0;
VAR3 = 64'h0;
VAR35 = 64'h0;
VAR31 = 64'h0;
VAR25 = 0;
VAR28 = VAR17[0];
VAR4 = VAR17[1];
VAR21 = VAR17[9];
VAR1 = VAR17[14];
VAR18 = {VAR4[0], VAR4[63 : 1]} ^ {VAR4[7 : 0], VAR4[63 : 8]} ^ {7'b0000000, VAR4[63 : 7]};
VAR24 = {VAR1[18 : 0], VAR1[63 : 19]} ^ {VAR1[60 : 0], VAR1[63 : 61]} ^ {6'b000000, VAR1[63 : 6]};
VAR6 = VAR28 + VAR18 + VAR21 + VAR24;
if (VAR19)
begin
VAR29 = VAR8[1023 : 960];
VAR26 = VAR8[959 : 896];
VAR11 = VAR8[895 : 832];
VAR22 = VAR8[831 : 768];
VAR9 = VAR8[767 : 704];
VAR5 = VAR8[703 : 640];
VAR14 = VAR8[639 : 576];
VAR12 = VAR8[575 : 512];
VAR20 = VAR8[511 : 448];
VAR23 = VAR8[447 : 384];
VAR27 = VAR8[383 : 320];
VAR16 = VAR8[319 : 256];
VAR10 = VAR8[255 : 192];
VAR3 = VAR8[191 : 128];
VAR35 = VAR8[127 : 64];
VAR31 = VAR8[63 : 0];
VAR25 = 1;
end
if (VAR38 && (VAR13 > 15))
begin
VAR29 = VAR17[01];
VAR26 = VAR17[02];
VAR11 = VAR17[03];
VAR22 = VAR17[04];
VAR9 = VAR17[05];
VAR5 = VAR17[06];
VAR14 = VAR17[07];
VAR12 = VAR17[08];
VAR20 = VAR17[09];
VAR23 = VAR17[10];
VAR27 = VAR17[11];
VAR16 = VAR17[12];
VAR10 = VAR17[13];
VAR3 = VAR17[14];
VAR35 = VAR17[15];
VAR31 = VAR6;
VAR25 = 1;
end
end
always @*
begin : VAR33
VAR39 = 7'h0;
VAR32 = 1'h0;
if (VAR19)
begin
VAR39 = 7'h00;
VAR32 = 1'h1;
end
if (VAR38)
begin
VAR39 = VAR13 + 7'h01;
VAR32 = 1'h1;
end
end
endmodule
|
bsd-2-clause
|
vad-rulezz/megabot
|
minsoc/rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
| 17,128 |
module MODULE1 (VAR47, VAR24, VAR5, VAR42, VAR49, VAR39, VAR12,
VAR73, VAR78, VAR15, VAR37, VAR86, VAR31, VAR88, VAR14, VAR38,
VAR30, VAR25, VAR2, VAR43, VAR50, VAR64,
VAR53, VAR81, VAR66, VAR29, VAR80, VAR67, VAR3, VAR16,
VAR85, VAR41, VAR4, VAR1, VAR75,
VAR21, VAR74, VAR59, VAR40
);
input VAR47; input VAR24; input VAR5; input VAR42; input VAR49; input [7:0] VAR39; input VAR12; input VAR73; input VAR78; input VAR15; input VAR37; input VAR86; input VAR31; input [15:0] VAR88; input [15:0] VAR14; input [6:0] VAR38; input [6:0] VAR30; input [6:0] VAR25; input [5:0] VAR2; input [3:0] VAR43; input VAR50; input VAR64;
output [3:0] VAR53; output VAR81; output VAR66; output VAR29; output VAR80; output VAR67; output VAR3; output VAR16; output VAR85; output [3:0] VAR41; output VAR4;
output VAR1;
output VAR75;
output VAR21;
output VAR74;
output VAR59;
output [1:0] VAR40;
reg [3:0] VAR53;
reg VAR81;
reg VAR66;
reg VAR29;
reg VAR80;
reg VAR67;
reg VAR3;
reg VAR16;
reg VAR26;
reg VAR28;
reg [3:0] VAR41;
reg [3:0] VAR79;
reg VAR20;
reg VAR22;
reg VAR58;
wire VAR77;
wire VAR60;
wire VAR13;
wire [1:0] VAR10;
wire VAR94;
wire VAR91;
wire VAR19;
wire VAR34;
wire VAR46;
wire VAR17;
wire VAR69;
wire VAR33;
wire VAR82;
wire VAR44;
wire VAR93;
wire VAR61;
wire VAR7;
wire VAR72;
wire VAR76;
wire VAR27;
wire [31:0] VAR89;
wire VAR23;
wire [2:0] VAR18;
wire [15:0] VAR56;
wire VAR84;
wire VAR68;
wire VAR71;
wire VAR35;
wire [15:0] VAR63;
wire VAR83;
wire VAR92;
wire VAR90;
wire VAR32;
wire VAR11;
assign VAR85 = ~(VAR59 | (|VAR40) | VAR33 | VAR82);
assign VAR77 = VAR5 & VAR46 & VAR35 & ~VAR28;
assign VAR4 = ~VAR73 & (VAR82 & VAR84 | VAR40[1] & VAR42 & (~VAR78 | VAR78 & VAR71) & ~VAR15);
assign VAR76 = VAR40[0] & VAR49 & ~VAR73;
assign VAR27 = ~VAR73 & VAR83 & (VAR40[0] & ~VAR49 | VAR82);
assign VAR72 = VAR91 & (VAR26 & ~VAR92) & ~VAR76;
assign VAR21 = VAR91 & ~VAR26 & ~VAR76;
assign VAR75 = VAR91 & VAR26 & VAR92;
assign VAR7 = VAR59 & VAR68;
assign VAR1 = VAR27 | VAR76 | VAR77 | VAR21 | VAR75;
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR28 <= 1'b0;
end
else
begin
if(~VAR5)
VAR28 <= 1'b0;
end
else
if(VAR77)
VAR28 <= 1'b1;
end
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR26 <= 1'b1;
end
else
begin
if(~VAR73 & VAR63[5:0] == VAR2[5:0] & (VAR40[1] | VAR33 & VAR56[0] | VAR82 & VAR56[0]))
VAR26 <= 1'b0;
end
else
if(VAR69 | VAR17)
VAR26 <= 1'b1;
end
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR20 <= 1'b0;
end
else
begin
if(~VAR5)
VAR20 <= 1'b0;
end
else
if(VAR77 | VAR69)
VAR20 <= 1'b1;
end
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR3 <= 1'b0;
end
else
VAR3 <= |VAR10;
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR29 <= 1'b0;
end
else
begin
if(VAR5 & ~VAR20)
VAR29 <= 1'b0;
end
else
if(VAR4)
VAR29 <= 1'b1;
end
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR80 <= 1'b0;
end
else
begin
if(VAR5 & ~VAR20)
VAR80 <= 1'b0;
end
else
if(VAR72)
VAR80 <= 1'b1;
end
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR67 <= 1'b0;
end
else
begin
if(VAR5 & ~VAR20 & ~VAR77)
VAR67 <= 1'b0;
end
else
if(VAR1)
VAR67 <= 1'b1;
end
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR41[3:0] <= 4'h0;
end
else
begin
if(VAR77 | VAR76 | VAR27 | VAR4 | VAR49
| VAR44 & VAR84 & (~VAR26 | VAR92))
VAR41[3:0] <= 4'h0;
end
else
if(VAR44 & VAR84 & VAR26 & (VAR90 | VAR50) | VAR61 & VAR32)
VAR41[3:0] <= VAR41[3:0] + 1;
end
end
assign VAR92 = VAR41[3:0] == VAR43[3:0];
always @ (VAR59 or VAR40 or VAR40 or VAR82 or VAR44 or VAR7 or VAR39 or
VAR89 or VAR68)
begin
if(VAR40[0])
end
VAR79[3:0] = VAR39[3:0]; else
if(VAR40[1])
VAR79[3:0] = VAR39[7:4]; else
if(VAR82)
VAR79[3:0] = {~VAR89[28], ~VAR89[29], ~VAR89[30], ~VAR89[31]}; else
if(VAR44)
VAR79[3:0] = 4'h9; else
if(VAR59)
if(VAR68)
VAR79[3:0] = 4'hd; else
VAR79[3:0] = 4'h5; else
VAR79[3:0] = 4'h0;
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR81 <= 1'b0;
end
else
VAR81 <= VAR59 | (|VAR40) | VAR33 | VAR82 | VAR44;
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR53[3:0] <= 4'h0;
end
else
VAR53[3:0] <= VAR79[3:0];
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR66 <= 1'b0;
end
else
VAR66 <= VAR27 | VAR76;
end
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
VAR16 <= 1'b0;
end
else
VAR16 <= VAR13 | VAR59 | (|VAR40) | VAR33 | VAR82 | VAR44;
end
assign VAR11 = VAR4 | VAR27 | VAR76 | VAR21 | VAR75 | VAR77;
always @ (posedge VAR47 or posedge VAR24)
begin
if(VAR24)
begin
VAR58 <= 1'b0;
VAR22 <= 1'b0;
end
else
begin
VAR58 <= VAR11;
VAR22 <= VAR58;
end
end
VAR87 VAR48 (.VAR59(VAR59), .VAR17(VAR17), .VAR40(VAR40),
.VAR33(VAR33), .VAR82(VAR82), .VAR44(VAR44), .VAR61(VAR61),
.VAR46(VAR46), .VAR69(VAR69), .VAR19(VAR19), .VAR60(VAR60),
.VAR94(VAR94), .VAR91(VAR91), .VAR5(VAR5), .VAR47(VAR47),
.VAR24(VAR24), .VAR88(VAR88), .VAR14(VAR14), .VAR86(VAR86), .VAR64(VAR64),
.VAR22(VAR22), .VAR31(VAR31), .VAR34(VAR34),
.VAR7(VAR7), .VAR63(VAR63), .VAR56(VAR56), .VAR35(VAR35),
.VAR84(VAR84), .VAR68(VAR68), .VAR83(VAR83), .VAR71(VAR71),
.VAR18(VAR18)
);
VAR62 VAR52 (.VAR47(VAR47), .VAR24(VAR24), .VAR35(VAR35), .VAR12(VAR12),
.VAR56(VAR56[6:0]), .VAR38(VAR38), .VAR30(VAR30), .VAR25(VAR25), .VAR37(VAR37),
.VAR5(VAR5), .VAR42(VAR42), .VAR49(VAR49), .VAR73(VAR73),
.VAR76(VAR76), .VAR4(VAR4), .VAR27(VAR27), .VAR84(VAR84),
.VAR68(VAR68), .VAR83(VAR83), .VAR78(VAR78), .VAR15(VAR15),
.VAR71(VAR71), .VAR90(VAR90), .VAR26(VAR26), .VAR92(VAR92),
.VAR50(VAR50), .VAR32(VAR32), .VAR69(VAR69),
.VAR17(VAR17), .VAR59(VAR59), .VAR40(VAR40), .VAR33(VAR33),
.VAR82(VAR82), .VAR44(VAR44), .VAR93(VAR93), .VAR61(VAR61),
.VAR46(VAR46), .VAR94(VAR94), .VAR91(VAR91), .VAR34(VAR34),
.VAR19(VAR19), .VAR74(VAR74), .VAR13(VAR13), .VAR10(VAR10), .VAR60(VAR60)
);
wire VAR55;
wire [3:0] VAR36;
wire VAR57;
assign VAR55 = ~VAR82;
assign VAR36[0] = VAR40[0]? VAR39[3] : VAR40[1]? VAR39[7] : 1'b0;
assign VAR36[1] = VAR40[0]? VAR39[2] : VAR40[1]? VAR39[6] : 1'b0;
assign VAR36[2] = VAR40[0]? VAR39[1] : VAR40[1]? VAR39[5] : 1'b0;
assign VAR36[3] = VAR40[0]? VAR39[0] : VAR40[1]? VAR39[4] : 1'b0;
assign VAR57 = VAR69 | VAR59 | (|VAR18);
VAR51 VAR65 (.VAR70(VAR47), .VAR24(VAR24), .VAR8(VAR36), .VAR45(VAR55), .VAR54(VAR57),
.VAR89(VAR89), .VAR23(VAR23)
);
VAR9 VAR6 (.VAR47(VAR47), .VAR24(VAR24), .VAR44(VAR44), .VAR93(VAR93), .VAR41(VAR41),
.VAR56(VAR56), .VAR63(VAR63[9:0]), .VAR90(VAR90), .VAR32(VAR32));
endmodule
|
gpl-2.0
|
Tao-J/nexys3MIPSSoC
|
ctrl.v
| 8,729 |
module MODULE1(clk,
reset,
VAR48,
VAR23,
VAR5,
VAR26,
VAR51,
VAR10,
VAR6,
VAR32,
VAR47,
VAR17,
VAR2,
VAR1,
VAR27,
VAR21,
VAR11,
VAR20,
VAR7,
VAR18,
VAR14,
VAR38,
VAR53,
VAR56,
VAR24,
VAR34,
VAR25,
VAR45,
VAR8
);
input clk,reset;
input VAR23,VAR5,VAR26,VAR25,VAR8;
input [31:0] VAR48;
output [2:0] VAR6,VAR21,VAR7;
output VAR47,VAR51,VAR10,VAR17,VAR2,VAR27,VAR11,VAR18,VAR14,VAR38,VAR53,VAR56,VAR24,VAR45,VAR34;
output [4:0] VAR32;
output [1:0] VAR1,VAR20;
wire [4:0] VAR32;
wire reset,VAR26,VAR25,VAR8;
reg VAR47,VAR51,VAR10,VAR17,VAR2,VAR27,VAR11,VAR18,VAR14,VAR38,VAR53,VAR24,VAR45,VAR34;
reg [1:0] VAR1,VAR20,VAR56;
reg [2:0] VAR6, VAR21, VAR7;
reg [4:0] state;
parameter VAR44 = 5'b00000, VAR16=5'b00001, VAR29= 5'b00010, VAR28=5'b00011, VAR31=5'b00100,
VAR46=5'b00101, VAR50=5'b00110, VAR33= 5'b00111, VAR4= 5'b01000, VAR39=5'b01001,
VAR54 = 5'b01010, VAR41=5'b01011, VAR30= 5'b01100, VAR57= 5'b01101, VAR52=5'b01110,
VAR49=5'b01111, VAR19=5'b10000, VAR42=5'b10001, VAR35=5'b10010, VAR40=5'b11111;
parameter VAR3=3'b000, VAR37=3'b001, VAR43=3'b010, VAR9=3'b110, VAR55=3'b100, VAR36=3'b111, VAR22=3'b011, VAR15=3'b101;
assign VAR32=state;
always @ (posedge clk or posedge reset)
if (reset==1) begin
state <= VAR44;
VAR45 <= 0;
end
else begin
VAR45 <= 0;
case (state)
VAR44: begin
if(VAR26) begin
if(VAR25)begin
VAR45 <= 1;
VAR6<=VAR9;
state <= VAR42;
end else begin
VAR6<=VAR43;
state <= VAR16;
end
end else begin
state <=VAR44;
end
end
VAR16: if (!VAR8) begin
VAR6<=VAR43;
state <= VAR16;
end else begin
case (VAR48[31:26])
6'b000000:begin VAR12<=VAR13'h00010;
state <= VAR29;
case (VAR48[5:0])
6'b100000: VAR6<=VAR43;
6'b100010: VAR6<=VAR9;
6'b100100: VAR6<=VAR3;
6'b100101: VAR6<=VAR37;
6'b100111: VAR6<=VAR55;
6'b101010: VAR6<=VAR36;
6'b000010: VAR6<=VAR15; 6'b000000: VAR6<=VAR22;
6'b001000: begin
VAR6<=VAR43; state <= VAR4; end
6'b001001:begin
default: VAR6 <= VAR43;
endcase
end
6'b100011:begin VAR12<=VAR13'h00050;
VAR6<=VAR43;
state <= VAR28;
end
6'b101011:begin VAR12<=VAR13'h00050;
VAR6<=VAR43;
state <= VAR28;
end
6'b000010:begin VAR12<=VAR13'h10160;
state <= VAR54;
end
6'b000100:begin VAR12<=VAR13'h08090; VAR38<=1;
VAR6<= VAR9; state <= VAR50; end
6'b000101:begin VAR12<=VAR13'h08090; VAR38<=0;
VAR6<= VAR9; state <= VAR33; end
6'b000011:begin VAR12<=VAR13'h1076c;
state <= VAR39;
end
6'b001000:begin VAR12<=VAR13'h00050;
VAR6 <= VAR43;
state <= VAR31;
end
6'b001100:begin VAR12<=VAR13'h00050;
VAR6 <= VAR3;
state <= VAR31;
end
6'b001101:begin VAR12<=VAR13'h00050;
VAR6 <= VAR37;
state <= VAR31;
end
6'b001110:begin VAR12<=VAR13'h00050;
VAR6 <= VAR22;
state <= VAR31;
end
6'b001010:begin VAR12<=VAR13'h00050;
VAR6 <= VAR36;
state <= VAR31;
end
6'b001111:begin VAR12<=VAR13'h00468;
state <= VAR46;
end
6'b010000: if(VAR48[25]) begin case (VAR48[5:0])
6'b011000: begin
state <= VAR35;
end
default: begin
state <= VAR40;
end
endcase
end
default: begin
state <= VAR40;
end
endcase
end
VAR19:begin
VAR6<=VAR43; state <= VAR4;
end
VAR28:begin
if(VAR48[31:26]==6'b100011)begin
end
else if(VAR48[31:26]==6'b101011)begin
end
VAR41:begin
if(VAR26)begin
end
else begin
state <=VAR41; VAR12<=VAR13'h06050; end
end
VAR30:begin
if(VAR26)begin
VAR6<=VAR43; state <= VAR44; end
else begin
state <=VAR30; VAR12<=VAR13'h05050; end
end
VAR49:begin
VAR6<=VAR43; state <=VAR44; end
VAR29:begin
VAR31:begin
VAR57:begin
VAR6<=VAR43; state <= VAR44; end
VAR52:begin
VAR6<=VAR43; state <= VAR44; end
VAR54:begin
VAR6<=VAR43; state <= VAR44; end
VAR33:begin
VAR6<=VAR43; state <= VAR44; end
VAR50:begin
VAR6<=VAR43; state <= VAR44; end
VAR4:begin
VAR6<=VAR43; state <= VAR44; end
VAR39:begin
VAR6<=VAR43; state <= VAR44; end
VAR46:begin
VAR6<=VAR43; state <= VAR44; end
VAR42:begin
VAR6<=VAR43; state <= VAR44; end
VAR35:begin
VAR6<=VAR43; state <= VAR44; end
VAR40: state <= VAR40;
default: begin
VAR6<=VAR43; state <= VAR40; end
endcase
end
endmodule
|
gpl-3.0
|
AnttiLukats/orp
|
hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/sha256_W.v
| 3,360 |
module MODULE1 (
input clk,
input VAR17,
input VAR9,
input [511:0] VAR21,
output [31:0] VAR12
);
reg [31:0] VAR29[15:0];
reg [31:0] VAR6, VAR28, VAR24, VAR18, VAR4, VAR20, VAR26, VAR27;
reg [31:0] VAR7, VAR10, VAR15, VAR22, VAR19, VAR5, VAR25, VAR13;
reg [31:0] VAR2;
reg [31:0] h0, h1, VAR14, VAR30;
always @(posedge clk)
begin
VAR29[ 0] <= VAR6;
VAR29[ 1] <= VAR28;
VAR29[ 2] <= VAR24;
VAR29[ 3] <= VAR18;
VAR29[ 4] <= VAR4;
VAR29[ 5] <= VAR20;
VAR29[ 6] <= VAR26;
VAR29[ 7] <= VAR27;
VAR29[ 8] <= VAR7;
VAR29[ 9] <= VAR10;
VAR29[10] <= VAR15;
VAR29[11] <= VAR22;
VAR29[12] <= VAR19;
VAR29[13] <= VAR5;
VAR29[14] <= VAR25;
VAR29[15] <= VAR13;
h0 <= VAR14;
h1 <= VAR30;
end
assign VAR12 = VAR29[0];
always @*
begin : VAR8
reg [31:0] VAR31, VAR16, VAR11, VAR32, VAR23, VAR1;
VAR6 = 0;
VAR28 = 0;
VAR24 = 0;
VAR18 = 0;
VAR4 = 0;
VAR20 = 0;
VAR26 = 0;
VAR27 = 0;
VAR7 = 0;
VAR10 = 0;
VAR15 = 0;
VAR22 = 0;
VAR19 = 0;
VAR5 = 0;
VAR25 = 0;
VAR13 = 0;
VAR31 = VAR29[1];
VAR16 = VAR29[2];
VAR11 = VAR29[10];
VAR32 = VAR29[15];
VAR2 = h0 + h1;
if(VAR17)
begin
VAR6 = VAR3( 0);
VAR28 = VAR3( 1);
VAR24 = VAR3( 2);
VAR18 = VAR3( 3);
VAR4 = VAR3( 4);
VAR20 = VAR3( 5);
VAR26 = VAR3( 6);
VAR27 = VAR3( 7);
VAR7 = VAR3( 8);
VAR10 = VAR3( 9);
VAR15 = VAR3(10);
VAR22 = VAR3(11);
VAR19 = VAR3(12);
VAR5 = VAR3(13);
VAR25 = VAR3(14);
VAR13 = VAR3(15);
VAR31 = VAR3(0);
VAR16 = VAR3(1);
VAR11 = VAR3(9);
VAR32 = VAR3(14);
end
else if(VAR9)
begin
VAR6 = VAR29[ 1];
VAR28 = VAR29[ 2];
VAR24 = VAR29[ 3];
VAR18 = VAR29[ 4];
VAR4 = VAR29[ 5];
VAR20 = VAR29[ 6];
VAR26 = VAR29[ 7];
VAR27 = VAR29[ 8];
VAR7 = VAR29[ 9];
VAR10 = VAR29[10];
VAR15 = VAR29[11];
VAR22 = VAR29[12];
VAR19 = VAR29[13];
VAR5 = VAR29[14];
VAR25 = VAR29[15];
VAR13 = VAR2;
end
VAR23 = {VAR16[ 6: 0], VAR16[31: 7]} ^ {VAR16[17: 0], VAR16[31:18]} ^ {3'h0, VAR16[31: 3]};
VAR1 = {VAR32[16: 0], VAR32[31:17]} ^ {VAR32[18: 0], VAR32[31:19]} ^ {10'h0, VAR32[31:10]};
VAR14 = VAR23 + VAR31;
VAR30 = VAR1 + VAR11;
end
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.functional.v
| 1,734 |
module MODULE1( VAR21, VAR9, VAR24, VAR11, VAR20, VAR23, VAR5 );
input VAR11, VAR24, VAR21, VAR20, VAR9, VAR5;
output VAR23;
not VAR13( VAR19, VAR20 );
wire VAR12;
not VAR1( VAR12, VAR24 );
wire VAR7;
not VAR17( VAR7, VAR21 );
wire VAR3;
and VAR10( VAR3, VAR12, VAR7 );
wire VAR14;
not VAR25( VAR14, VAR9 );
wire VAR4;
and VAR6( VAR4, VAR12, VAR14 );
wire VAR18;
and VAR22( VAR18, VAR14, VAR21 );
or VAR15( VAR2, VAR3, VAR4, VAR18 );
VAR16( VAR26, VAR19, 1'b0, VAR11, VAR2, VAR5 );
not VAR8( VAR23, VAR26 );
endmodule
|
apache-2.0
|
laoreja/MineSweeperM
|
code/vga_640_480_stripes.v
| 2,036 |
module MODULE1(
input wire clk,
input wire VAR1,
output reg VAR4,
output reg VAR12,
output reg [9:0] hc,
output reg [9:0] VAR5,
output reg VAR11
);
parameter VAR10 = 10'b1100100000, VAR7 = 10'b1000001001, VAR2 = 10'b0010010000, VAR6 = 10'b1100010000, VAR9 = 10'b0000011111, VAR3 = 10'b0111111111;
reg VAR8;
always @(posedge clk or posedge VAR1)
begin
if(VAR1==1)
hc<=0;
end
else
begin
if(hc==VAR10-1)
begin hc<=0;
VAR8 <=1; end
else
begin
hc<=hc+1;
VAR8 <= 0;
end
end
end
always @
begin
if(VAR5<2)
VAR12=0;
end
else
VAR12=1;
end
always@(*)
begin
if((hc<VAR6)&&(hc>VAR2)&&(VAR5<VAR3)&&(VAR5>VAR9))
VAR11 = 1;
end
else
VAR11 = 0;
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/or4b/sky130_fd_sc_ms__or4b.pp.symbol.v
| 1,318 |
module MODULE1 (
input VAR9 ,
input VAR2 ,
input VAR6 ,
input VAR8 ,
output VAR1 ,
input VAR3 ,
input VAR5,
input VAR4,
input VAR7
);
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
libsrc/hdl/vhd/mkBiasWorker4B.v
| 3,766 |
module MODULE1(
input VAR57,
input VAR24,
input [2 : 0] VAR7,
input VAR27,
input [3 : 0] VAR23,
input [31 : 0] VAR1,
input [31 : 0] VAR9,
output [1 : 0] VAR62,
output [31 : 0] VAR49,
output VAR65,
output [1 : 0] VAR22,
input [1 : 0] VAR42,
input [2 : 0] VAR15,
input VAR45,
input VAR46,
input [11 : 0] VAR41,
input [31 : 0] VAR44,
input [3 : 0] VAR58,
input [7 : 0] VAR13,
output VAR48,
output VAR50,
input VAR20,
output [2 : 0] VAR31,
output VAR5,
output VAR19,
output [11 : 0] VAR64,
output [31 : 0] VAR51,
output [3 : 0] VAR40,
output [7 : 0] VAR16,
input VAR3,
output VAR43,
input VAR35 );
VAR59 VAR52(
.VAR33 (VAR57), .VAR34 (VAR1[4:0]), .VAR38 (VAR27), .VAR12 (VAR7), .VAR36 (VAR9), .VAR39 (VAR42), .VAR37 (VAR24), .VAR2 (VAR49), .VAR17 (VAR22), .VAR25 (VAR62), .VAR55 (VAR65),
.VAR18 (VAR41), .VAR14 (VAR58), .VAR61 (VAR15), .VAR26 (VAR44), .VAR53 (VAR46), .VAR63 (VAR13), .VAR56 (VAR45), .VAR30 (VAR20), .VAR28 (VAR50), .VAR4 (VAR48),
.VAR60 (VAR35), .VAR6 (VAR3), .VAR29 (VAR64), .VAR21 (VAR40), .VAR54 (VAR31), .VAR8 (VAR51), .VAR11 (VAR19), .VAR47 (VAR16), .VAR32 (VAR5), .VAR10 (VAR43) );
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.functional.pp.v
| 2,257 |
module MODULE1 (
VAR18 ,
VAR14 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR13 ,
VAR19 ,
VAR16,
VAR20,
VAR17 ,
VAR21
);
output VAR18 ;
output VAR14 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR13 ;
input VAR19 ;
input VAR16;
input VAR20;
input VAR17 ;
input VAR21 ;
wire VAR8 ;
wire VAR11;
wire VAR4 ;
VAR22 VAR12 (VAR11, VAR4, VAR13, VAR19 );
VAR22 VAR6 (VAR4 , VAR8, VAR2, VAR10 );
VAR7 VAR1 VAR9 (VAR8 , VAR11, VAR5, , VAR16, VAR20);
buf VAR3 (VAR18 , VAR8 );
not VAR15 (VAR14 , VAR8 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nand2b/sky130_fd_sc_hdll__nand2b_2.v
| 2,163 |
module MODULE2 (
VAR9 ,
VAR7 ,
VAR3 ,
VAR4,
VAR1,
VAR2 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR8 ;
VAR5 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR9 ,
VAR7,
VAR3
);
output VAR9 ;
input VAR7;
input VAR3 ;
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR8 ;
VAR5 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.v
| 2,065 |
module MODULE2 (
VAR6 ,
VAR2 ,
VAR3,
VAR4,
VAR1 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR7 ;
VAR8 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR7 ;
VAR8 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
lokisz/openzcore
|
pippo-riscv/rtl/verilog/pippo_operandmuxes.v
| 2,196 |
module MODULE1(
VAR11, VAR4, VAR1, VAR12,
VAR3, VAR5,
VAR10, VAR6
);
parameter VAR9 = VAR7;
input [VAR9-1:0] VAR11;
input [VAR9-1:0] VAR4;
input [VAR9-1:0] VAR1;
input [VAR9-1:0] VAR12;
input [VAR2-1:0] VAR3;
input [VAR2-1:0] VAR5;
output [VAR9-1:0] VAR10;
output [VAR9-1:0] VAR6;
reg [VAR9-1:0] VAR10;
reg [VAR9-1:0] VAR6;
always @(VAR1 or VAR11 or VAR3) begin
end
casex (VAR3) else
casex (VAR3) VAR8
VAR10 = VAR1;
VAR10 = VAR11;
default:
VAR10 = VAR11;
endcase
end
always @(VAR12 or VAR1 or VAR4 or VAR5) begin
end
casex (VAR5) else
casex (VAR5) VAR8
VAR6 = VAR12;
VAR6 = VAR1;
VAR6 = VAR4;
default:
VAR6 = VAR4;
endcase
end
endmodule
|
gpl-2.0
|
skyfex/svo-raycaster
|
raycaster2/raycaster_cache_mem.v
| 6,365 |
module MODULE1(
VAR4,
VAR10,
VAR6,
VAR5,
VAR11,
VAR3,
VAR1,
VAR2,
VAR8,
VAR7
);
input VAR4;
input [0 : 0] VAR10;
input [8 : 0] VAR6;
input [31 : 0] VAR5;
output reg [31 : 0] VAR11;
input VAR3;
input [0 : 0] VAR1;
input [8 : 0] VAR2;
input [31 : 0] VAR8;
output reg [31 : 0] VAR7;
reg [31:0] VAR9[0:511];
always @(posedge VAR4)
begin
if (VAR10)
VAR9[VAR6] <= VAR5;
VAR11 <= VAR9[VAR6];
end
always @(posedge VAR3)
begin
if (VAR1)
VAR9[VAR6] <= VAR8;
VAR7 <= VAR9[VAR2];
end
endmodule
|
mit
|
vad-rulezz/megabot
|
minsoc/rtl/verilog/minsoc_top.v
| 21,120 |
module MODULE1 (
clk,reset
, VAR259,VAR433,VAR451,
VAR161,VAR85,VAR235
, VAR316, VAR432, VAR59, VAR453
, VAR288,VAR184
, VAR271, VAR179, VAR180, VAR100,
VAR201, VAR382, VAR132, VAR358,
VAR363, VAR472, VAR75, VAR79,
VAR205, VAR135
);
input clk;
input reset;
output VAR316;
input VAR432;
output VAR59;
output [1:0] VAR453;
output VAR288;
input VAR184;
output VAR382;
input VAR100;
output VAR201;
output [3:0] VAR132;
input VAR472;
input VAR358;
input VAR363;
input [3:0] VAR75;
input VAR271;
input VAR179;
output VAR180;
input VAR79;
inout VAR135;
output VAR205;
input VAR259;
input VAR433;
input VAR451;
output VAR161;
output VAR85;
output VAR235;
assign VAR85 = 1'b1;
assign VAR235 = 1'b0;
wire VAR343;
assign VAR343 = ~reset;
assign VAR343 = reset;
wire [31:0] VAR446;
wire [31:0] VAR370;
wire [31:0] VAR234;
wire [3:0] VAR212;
wire VAR36;
wire VAR2;
wire VAR97;
wire VAR368;
wire VAR157;
wire [31:0] VAR302;
wire [31:0] VAR249;
wire [31:0] VAR371;
wire [3:0] VAR112;
wire VAR210;
wire VAR307;
wire VAR20;
wire VAR156;
wire VAR331;
wire [3:0] VAR264;
wire [1:0] VAR419;
wire [10:0] VAR149;
wire VAR260;
wire [31:0] VAR406;
wire [31:0] VAR41;
wire [31:0] VAR127;
wire VAR436;
wire VAR5;
wire VAR394;
wire VAR323;
wire VAR45;
wire [31:0] VAR244;
wire VAR265;
wire [31:0] VAR346;
wire [31:0] VAR176;
wire [3:0] VAR301;
wire VAR277;
wire VAR107;
wire VAR8 = 1'b0;
wire VAR204;
wire VAR438;
wire [31:0] VAR163;
wire VAR90;
wire [31:0] VAR123;
wire VAR253;
wire [31:0] VAR114;
wire [31:0] VAR82;
wire [3:0] VAR117;
wire VAR359;
wire VAR269;
wire VAR134 = 1'b0;
wire VAR279;
wire VAR153;
wire [VAR190-1:0] VAR378;
wire [31:0] VAR268;
wire [31:0] VAR220;
wire [31:0] VAR476;
wire [3:0] VAR13;
wire VAR24;
wire VAR327;
wire VAR398;
wire VAR305;
wire VAR243;
wire [31:0] VAR481;
wire [31:0] VAR407;
wire [31:0] VAR239;
wire [3:0] VAR126;
wire VAR51;
wire VAR344;
wire VAR105;
wire VAR313;
wire VAR70;
wire VAR316;
wire VAR432;
wire VAR59;
wire [1:0] VAR453;
wire [31:0] VAR129;
wire [31:0] VAR16;
wire [31:0] VAR104;
wire [3:0] VAR338;
wire VAR372;
wire VAR119;
wire VAR200;
wire VAR240;
wire VAR142;
wire [31:0] VAR369;
wire [31:0] VAR356;
wire [31:0] VAR354;
wire [3:0] VAR469;
wire VAR483;
wire VAR456;
wire VAR216;
wire VAR457;
wire VAR7;
wire [31:0] VAR342;
wire [31:0] VAR420;
wire [31:0] VAR280;
wire [3:0] VAR275;
wire VAR84;
wire VAR467;
wire VAR22;
wire VAR426;
wire VAR92;
wire VAR278;
wire VAR19;
wire [31:0] VAR87;
wire [31:0] VAR423;
wire [31:0] VAR452;
wire [3:0] VAR206;
wire VAR393;
wire VAR311;
wire VAR295;
wire VAR477;
wire VAR290;
wire VAR288;
wire VAR184;
reg VAR35;
reg VAR297;
wire VAR312;
always @(posedge VAR312 or negedge VAR343)
if (~VAR343)
VAR35 <= 1'b1;
else
VAR35 <= 1'b0;
always @(posedge VAR312)
VAR297 <= VAR35;
VAR325 #
(
.VAR351(VAR319)
)
VAR247 (
.VAR167(clk),
.VAR76(VAR312)
);
assign VAR290 = 1'b0;
assign VAR243 = 1'b0;
assign VAR70 = 1'b0;
assign VAR378[VAR166] = 'b0;
assign VAR378[VAR47] = 'b0;
assign VAR378[VAR350] = 'b0;
assign VAR378[VAR231] = 'b0;
assign VAR135 = VAR19 ? VAR278 : 1'VAR143;
assign VAR180 = VAR421;
reg VAR99;
reg [3:0] VAR424;
reg [31:0] VAR141;
reg VAR103;
always @(posedge VAR312 or negedge VAR343)
begin
if (!VAR343) begin
VAR99 <= 1'b1;
VAR424 <= 4'h0;
VAR103 <= 1'b0;
end
else begin
VAR103 <= 1'b0;
if (VAR265 && (VAR244[31:32-VAR361] == VAR465))
VAR99 <= 1'b0;
if ( VAR99 == 1'b1 ) begin
if ( VAR265 && VAR438 && ~VAR204 )
VAR103 <= 1'b1;
if ( VAR103 == 1'b1 ) begin
VAR424 <= VAR424 + 1'b1;
VAR103 <= 1'b0;
end
end
end
end
always @ (VAR424)
begin
case ( VAR424 )
4'h0: VAR141 = { VAR409 , 5'h01 , 4'h0 , 1'b0 , VAR465 , 8'h00 };
4'h1: VAR141 = { VAR211 , 5'h01 , 5'h01 , 16'h0000 };
4'h2: VAR141 = { VAR242 , 10'h000 , 5'h01 , 11'h000 };
4'h3: VAR141 = { VAR168 , 10'h000 , 16'h0000 };
default: VAR141 = 32'h00000000;
endcase
end
assign VAR163 = VAR99 ? VAR141 : VAR346;
assign VAR90 = VAR99 ? VAR103 : VAR277;
assign VAR163 = VAR346;
assign VAR90 = VAR277;
wire VAR451;
wire VAR155;
wire VAR198;
wire VAR374;
wire VAR14;
wire VAR130;
wire VAR293;
wire VAR357;
wire VAR109;
VAR78 VAR27 (
.VAR447 ( VAR451 ),
.VAR480 ( VAR155 ),
.VAR230 ( VAR198 ),
.VAR222 ( VAR109 ),
.VAR56 ( VAR374 ),
.VAR304 ( VAR14 ),
.VAR61 ( VAR130 ),
.VAR164 ( VAR293 ),
.VAR208( VAR357 ),
.VAR444 ( VAR312 ),
.VAR80 ( VAR446 ),
.VAR181 ( VAR370 ),
.VAR86 ( VAR234 ),
.VAR403 ( VAR212 ),
.VAR318 ( VAR36 ),
.VAR98 ( VAR2 ),
.VAR4 ( VAR97 ),
.VAR64 ( VAR368 ),
.VAR28 ( VAR157 ),
.VAR322 ( ),
.VAR46 ( ),
.VAR289 ( VAR312 ),
.VAR68 ( VAR127 ),
.VAR332 ( VAR41 ),
.VAR58 ( VAR406 ),
.VAR285 ( VAR260 ),
.VAR160( VAR5 ),
.VAR83 ( VAR323 ),
.VAR362 ( VAR394 ),
.VAR53 ( VAR45 ),
.VAR427 ( ),
.VAR371 ( VAR371[31:0] ),
.VAR302 ( VAR302[31:0] ),
.VAR249 ( VAR249[31:0] ),
.VAR210 ( VAR210 ),
.VAR20 ( VAR20 ),
.VAR307 ( VAR307 ),
.VAR156 ( VAR156 ),
.VAR112 ( VAR112[3:0] ),
.VAR228 ( 1'b0 ),
.VAR57 ( 3'b0 ),
.VAR113 ( 2'b0 ),
.VAR347 ( VAR378[VAR435] )
);
assign VAR331 = 1'b0;
VAR462 VAR462(
.VAR3(VAR433),
.VAR341(VAR451),
.VAR274(VAR343),
.VAR428(VAR259),
.VAR429(VAR161),
.VAR250( ),
.VAR158( VAR109 ),
.VAR1(),
.VAR296(VAR14),
.VAR287(VAR130),
.VAR108(VAR293),
.VAR395(VAR374),
.VAR258(),
.VAR408(),
.VAR133(),
.VAR65(VAR357),
.VAR490(VAR155),
.VAR373(VAR198), .VAR125(1'b0), .VAR189(1'b0) );
VAR195 VAR462(
.VAR376(VAR451),
.VAR373(VAR198),
.VAR490(VAR155),
.VAR158(VAR109),
.VAR1(),
.VAR296(VAR14),
.VAR395(VAR374),
.VAR287(VAR130),
.VAR108(VAR293),
.VAR65(VAR357)
);
VAR225 VAR462(
.VAR376( VAR451 ),
.VAR373( VAR198 ),
.VAR490( VAR155 ),
.VAR158( VAR109 ),
.VAR1( ),
.VAR296( VAR14 ),
.VAR395( VAR374 ),
.VAR287( VAR130 ),
.VAR108( VAR293 ),
.VAR65( VAR357 )
);
VAR349 VAR349 (
.VAR222 ( VAR297 ),
.VAR167 ( VAR312 ),
.VAR431 ( 2'b01 ),
.VAR431 ( 2'b11 ),
.VAR431 ( 2'b00 ),
.VAR402 ( VAR312 ),
.VAR461 ( VAR297 ),
.VAR335 ( VAR265 ),
.VAR396 ( VAR244 ),
.VAR9 ( VAR163 ),
.VAR11 ( VAR176 ),
.VAR236 ( VAR301 ),
.VAR229 ( VAR90 ),
.VAR188 ( VAR107 ),
.VAR463 ( VAR8 ),
.VAR487 ( VAR204 ),
.VAR193 ( VAR438 ),
.VAR194 ( VAR312 ),
.VAR283 ( VAR297 ),
.VAR430 ( VAR253 ),
.VAR213 ( VAR123 ),
.VAR162 ( VAR114 ),
.VAR54 ( VAR82 ),
.VAR67 ( VAR117 ),
.VAR95 ( VAR359 ),
.VAR207 ( VAR269 ),
.VAR367 ( VAR134 ),
.VAR410 ( VAR279 ),
.VAR400 ( VAR153 ),
.VAR375 ( VAR5 ),
.VAR366 ( VAR406 ),
.VAR88 ( VAR127 ),
.VAR44 ( 1'b0 ),
.VAR384 ( VAR264 ),
.VAR466 ( VAR419 ),
.VAR191 ( VAR149 ),
.VAR246 ( VAR260 ),
.VAR491 ( VAR41 ),
.VAR69 ( VAR45 ),
.VAR63 ( VAR323 ),
.VAR252 ( VAR394 ),
.VAR115 ( ),
.VAR411 ( 1'b0 ),
.VAR317 ( ),
.VAR386 ( ),
.VAR219 ( ),
.VAR12 ( ),
.VAR94 ( ),
.VAR329 ( ),
.VAR224 ( ),
.VAR324 ( ),
.VAR185 ( VAR378 )
);
VAR485 VAR248
(
.VAR34(VAR476[6:2]),
.VAR25(VAR398),
.VAR203(VAR327),
.VAR86(VAR220),
.VAR321(VAR305),
.VAR312(VAR312),
.VAR297(VAR297)
);
VAR387 #
(
.VAR77(0),
.VAR440(2)
)
VAR488
(
.VAR444(VAR312),
.VAR71(VAR297),
.VAR34(VAR239[4:2]),
.VAR181(VAR481),
.VAR86(VAR407),
.VAR233(VAR126),
.VAR241(VAR51),
.VAR25(VAR105),
.VAR203(VAR344),
.VAR321(VAR313),
.VAR473(VAR316),
.VAR42(VAR432),
.VAR214(VAR59),
.VAR379(VAR453)
);
assign VAR220 = 32'h00000000;
assign VAR305 = 1'b0;
assign VAR407 = 32'h00000000;
assign VAR313 = 1'b0;
VAR238 #
VAR272 #
(
.VAR218(VAR328) )
VAR102 (
.VAR444 ( VAR312 ),
.VAR71 ( VAR297 ),
.VAR181 ( VAR129 ),
.VAR86 ( VAR16 ),
.VAR34 ( VAR104 ),
.VAR233 ( VAR338 ),
.VAR241 ( VAR372 ),
.VAR203 ( VAR119 ),
.VAR25 ( VAR200 ),
.VAR321 ( VAR240 ),
.VAR18 ( VAR142 )
);
VAR131 VAR131 (
.VAR444 ( VAR312 ),
.VAR71 ( VAR297 ),
.VAR34 ( VAR452[4:0] ),
.VAR181 ( VAR87 ),
.VAR86 ( VAR423 ),
.VAR241 ( VAR393 ),
.VAR25 ( VAR295 ),
.VAR203 ( VAR311 ),
.VAR321 ( VAR477 ),
.VAR233 ( VAR206 ),
.VAR347 ( VAR378[VAR91] ),
.VAR492 ( VAR288 ),
.VAR183 ( VAR184 ),
.VAR455 ( ),
.VAR261 ( 1'b0 ),
.VAR267 ( ),
.VAR401 ( 1'b0 ),
.VAR399 ( 1'b0 ),
.VAR415 ( 1'b0 )
);
assign VAR423 = 32'h00000000;
assign VAR477 = 1'b0;
assign VAR378[VAR91] = 1'b0;
VAR479 VAR479 (
.VAR444 ( VAR312 ),
.VAR71 ( VAR297 ),
.VAR181 ( VAR342 ),
.VAR86 ( VAR420 ),
.VAR34 ( VAR280[11:2] ),
.VAR233 ( VAR275 ),
.VAR241 ( VAR84 ),
.VAR203 ( VAR467 ),
.VAR25 ( VAR22 ),
.VAR321 ( VAR426 ),
.VAR18 ( VAR92 ),
.VAR17 ( VAR369 ),
.VAR23 ( VAR469 ),
.VAR140 ( VAR483 ),
.VAR309 ( VAR354 ),
.VAR93 ( VAR356 ),
.VAR348 ( VAR216 ),
.VAR32 ( VAR456 ),
.VAR52 ( VAR457 ),
.VAR118 ( VAR7 ),
.VAR294 ( VAR100 ),
.VAR460 ( VAR132 ),
.VAR237 ( VAR201 ),
.VAR337 ( VAR382 ),
.VAR336 ( VAR358 ),
.VAR392 ( VAR75 ),
.VAR148 ( VAR363 ),
.VAR413 ( VAR472 ),
.VAR30 ( VAR271 ),
.VAR391 ( VAR179 ),
.VAR443 ( VAR205 ),
.VAR493 ( VAR135 ),
.VAR254 ( VAR278 ),
.VAR263 ( VAR19 ),
.VAR347 ( VAR378[VAR360] )
);
assign VAR420 = 32'h00000000;
assign VAR426 = 1'b0;
assign VAR92 = 1'b0;
assign VAR369 = 32'h00000000;
assign VAR469 = 4'h0;
assign VAR483 = 1'b0;
assign VAR354 = 32'h00000000;
assign VAR216 = 1'b0;
assign VAR456 = 1'b0;
assign VAR378[VAR360] = 1'b0;
VAR175 #(VAR361,
) VAR417 (
.VAR444 ( VAR312 ),
.VAR71 ( VAR297 ),
.VAR37 ( 1'b0 ),
.VAR414 ( 1'b0 ),
.VAR106 ( 32'h00000000 ),
.VAR21 ( 4'b0000 ),
.VAR330 ( 1'b0 ),
.VAR150 ( 32'h00000000 ),
.VAR381 ( ),
.VAR270 ( ),
.VAR48 ( ),
.VAR74 ( VAR216 ),
.VAR352 ( VAR456 ),
.VAR340 ( VAR369 ),
.VAR482 ( VAR469 ),
.VAR202 ( VAR483 ),
.VAR314 ( VAR354 ),
.VAR291 ( VAR356 ),
.VAR458 ( VAR457 ),
.VAR232 ( VAR7 ),
.VAR40 ( 1'b0 ),
.VAR172 ( 1'b0 ),
.VAR266 ( 32'h00000000 ),
.VAR187 ( 4'b0000 ),
.VAR146 ( 1'b0 ),
.VAR353 ( 32'h00000000 ),
.VAR442 ( ),
.VAR111 ( ),
.VAR416 ( ),
.VAR226 ( VAR97 ),
.VAR182 ( VAR2 ),
.VAR110 ( VAR446 ),
.VAR459 ( VAR212 ),
.VAR486 ( VAR36 ),
.VAR223 ( VAR234 ),
.VAR6 ( VAR370 ),
.VAR441 ( VAR368 ),
.VAR137 ( VAR157 ),
.VAR43 ( VAR253 ),
.VAR405 ( VAR153 ),
.VAR173 ( VAR123 ),
.VAR174 ( VAR117 ),
.VAR221 ( VAR279 ),
.VAR144 ( VAR82 ),
.VAR72 ( VAR114 ),
.VAR89 ( VAR359 ),
.VAR169 ( VAR269 ),
.VAR196 ( VAR265 ),
.VAR262 ( VAR438 ),
.VAR388 ( VAR244 ),
.VAR339 ( VAR301 ),
.VAR390 ( VAR204 ),
.VAR199 ( VAR176 ),
.VAR448 ( VAR346 ),
.VAR31 ( VAR277 ),
.VAR345 ( VAR107 ),
.VAR151 ( 1'b0 ),
.VAR484 ( 1'b0 ),
.VAR145 ( 32'h00000000 ),
.VAR464 ( 4'b0000 ),
.VAR256 ( 1'b0 ),
.VAR300 ( 32'h00000000 ),
.VAR333 ( ),
.VAR412 ( ),
.VAR385 ( ),
.VAR215 ( 1'b0 ),
.VAR255 ( 1'b0 ),
.VAR120 ( 32'h00000000 ),
.VAR450 ( 4'b0000 ),
.VAR121 ( 1'b0 ),
.VAR474 ( 32'h00000000 ),
.VAR326 ( ),
.VAR276 ( ),
.VAR159 ( ),
.VAR299 ( VAR119 ),
.VAR122 ( VAR200 ),
.VAR418 ( VAR104 ),
.VAR139 ( VAR338 ),
.VAR154 ( VAR372 ),
.VAR468 ( VAR129 ),
.VAR470 ( VAR16 ),
.VAR404 ( VAR240 ),
.VAR192 ( VAR142 ),
.VAR49 ( VAR327 ),
.VAR62 ( VAR398 ),
.VAR439 ( VAR476 ),
.VAR422 ( VAR13 ),
.VAR10 ( VAR24 ),
.VAR397 ( VAR268 ),
.VAR66 ( VAR220 ),
.VAR454 ( VAR305 ),
.VAR170 ( VAR243 ),
.VAR284 ( VAR344 ),
.VAR315 ( VAR105 ),
.VAR489 ( VAR239 ),
.VAR227 ( VAR126 ),
.VAR303 ( VAR51 ),
.VAR434 ( VAR481 ),
.VAR494 ( VAR407 ),
.VAR380 ( VAR313 ),
.VAR96 ( VAR70 ),
.VAR364 ( VAR467 ),
.VAR425 ( VAR22 ),
.VAR178 ( VAR280 ),
.VAR245 ( VAR275 ),
.VAR39 ( VAR84 ),
.VAR334 ( VAR342 ),
.VAR257 ( VAR420 ),
.VAR471 ( VAR426 ),
.VAR116 ( VAR92 ),
.VAR306 ( ),
.VAR186 ( ),
.VAR101 ( ),
.VAR251 ( ),
.VAR15 ( ),
.VAR197 ( ),
.VAR124 ( 32'h00000000 ),
.VAR73 ( 1'b0 ),
.VAR209 ( 1'b1 ),
.VAR147 ( VAR311 ),
.VAR383 ( VAR295 ),
.VAR26 ( VAR452 ),
.VAR50 ( VAR206 ),
.VAR81 ( VAR393 ),
.VAR60 ( VAR87 ),
.VAR389 ( VAR423 ),
.VAR273 ( VAR477 ),
.VAR475 ( VAR290 ),
.VAR449 ( ),
.VAR282 ( ),
.VAR445 ( ),
.VAR320 ( ),
.VAR38 ( ),
.VAR138 ( ),
.VAR171 ( 32'h00000000 ),
.VAR355 ( 1'b0 ),
.VAR292 ( 1'b1 ),
.VAR281 (VAR307 ),
.VAR177 (VAR20 ),
.VAR165 (VAR371 ),
.VAR437 (VAR112 ),
.VAR55 ( VAR210 ),
.VAR286 (VAR302 ),
.VAR478 ( VAR249 ),
.VAR377 (VAR156 ),
.VAR217 ( VAR331 ),
.VAR310 ( ),
.VAR298 ( ),
.VAR152 ( ),
.VAR33 ( ),
.VAR128 ( ),
.VAR365 ( ),
.VAR29 ( 32'h00000000 ),
.VAR308 ( 1'b0 ),
.VAR136 ( 1'b1 )
);
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dfbbn/sky130_fd_sc_hd__dfbbn_1.v
| 2,601 |
module MODULE2 (
VAR3 ,
VAR2 ,
VAR12 ,
VAR9 ,
VAR4 ,
VAR11,
VAR6 ,
VAR7 ,
VAR8 ,
VAR10
);
output VAR3 ;
output VAR2 ;
input VAR12 ;
input VAR9 ;
input VAR4 ;
input VAR11;
input VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR10 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR3 ,
VAR2 ,
VAR12 ,
VAR9 ,
VAR4 ,
VAR11
);
output VAR3 ;
output VAR2 ;
input VAR12 ;
input VAR9 ;
input VAR4 ;
input VAR11;
supply1 VAR6;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR10 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/clkinv/sky130_fd_sc_hd__clkinv.behavioral.pp.v
| 1,774 |
module MODULE1 (
VAR5 ,
VAR6 ,
VAR12,
VAR3,
VAR10 ,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR12;
input VAR3;
input VAR10 ;
input VAR2 ;
wire VAR4 ;
wire VAR1;
not VAR7 (VAR4 , VAR6 );
VAR11 VAR9 (VAR1, VAR4, VAR12, VAR3);
buf VAR8 (VAR5 , VAR1 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/mux4/sky130_fd_sc_hd__mux4_4.v
| 2,444 |
module MODULE2 (
VAR2 ,
VAR10 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR12,
VAR7,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR12;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR13 VAR11 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2 ,
VAR10,
VAR9,
VAR6,
VAR1,
VAR3,
VAR4
);
output VAR2 ;
input VAR10;
input VAR9;
input VAR6;
input VAR1;
input VAR3;
input VAR4;
supply1 VAR12;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR8 ;
VAR13 VAR11 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/dlxtn/sky130_fd_sc_hdll__dlxtn.functional.v
| 1,599 |
module MODULE1 (
VAR4 ,
VAR7 ,
VAR9
);
output VAR4 ;
input VAR7 ;
input VAR9;
wire VAR3 ;
wire VAR2;
not VAR6 (VAR3 , VAR9 );
VAR1 VAR5 (VAR2 , VAR7, VAR3 );
buf VAR8 (VAR4 , VAR2 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.pp.blackbox.v
| 1,234 |
module MODULE1 (
VAR1,
VAR3,
VAR2 ,
VAR4
);
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
endmodule
|
apache-2.0
|
Progressive-Learning-Platform/progressive-learning-platform
|
reference/hw/verilog/cpu_id.v
| 4,702 |
module MODULE1(rst, clk, VAR33, VAR46, VAR51, VAR22,
VAR52, VAR13, VAR15, VAR29, VAR19,
VAR40, VAR6, VAR32, VAR39, VAR18,
VAR9, VAR44, VAR36, VAR47, VAR17,
VAR12, VAR25, VAR28, VAR21, VAR34, VAR4, VAR49);
input rst, clk, VAR33;
input [31:0] VAR46;
input [31:0] VAR51;
input VAR22;
input [4:0] VAR52;
input [31:0] VAR13;
input VAR49;
output reg [31:0] VAR15;
output reg [31:0] VAR29;
output reg [31:0] VAR19;
output reg [4:0] VAR40;
output reg [5:0] VAR6;
output reg [4:0] VAR32;
output reg VAR39;
output reg [1:0] VAR18;
output reg [1:0] VAR9;
output reg [5:0] VAR44;
output reg VAR36;
output reg VAR47;
output reg VAR17;
output reg [25:0] VAR12;
output reg [31:0] VAR25;
output reg VAR28;
output reg [4:0] VAR21;
output reg [4:0] VAR34;
output VAR4;
reg [31:0] VAR38 [31:1];
wire [5:0] VAR2 = VAR51[31:26];
wire [4:0] VAR20 = VAR51[25:21];
wire [4:0] VAR23 = VAR51[20:16];
wire [4:0] VAR30 = VAR51[15:11];
wire [15:0] VAR3 = VAR51[15:0];
wire [4:0] VAR24 = VAR51[10:6];
wire [5:0] VAR11 = VAR51[5:0];
wire [25:0] VAR41 = VAR51[25:0];
wire [31:0] VAR16 = VAR20 == 0 ? 0 : VAR38[VAR20];
wire [31:0] VAR37 = VAR23 == 0 ? 0 : VAR38[VAR23];
wire VAR1 = (VAR39 & (VAR44 == 6'h23) & ((VAR34 == VAR20) | (VAR34 == VAR23)) & (VAR34 != 0) & (VAR2 != 6'h2b));
assign VAR4 = VAR1;
wire VAR7 = (
VAR2 != 6'h04 &&
VAR2 != 6'h05 &&
VAR2 != 6'h2b &&
VAR2 != 6'h02 &&
!VAR1);
wire [1:0] VAR14 =
(VAR2 == 6'h23) ? 2'h1 :
(VAR2 == 6'h03) ? 2'h2 :
(VAR2 == 6'h00 && VAR11 == 6'h09) ? 2'h2 : 0;
wire [1:0] VAR5 = (VAR2 == 6'h2b && !VAR1) ? 2'b01 :
(VAR2 == 6'h23 && !VAR1) ? 2'b10 : 2'b00;
wire [5:0] VAR31 = VAR2;
wire VAR42 = (VAR2 == 6'h0c || VAR2 == 6'h0d) ? 0 : 1;
wire VAR48 = (VAR2 == 6'h00 || VAR2 == 6'h04 || VAR2 == 6'h05) ? 0 : 1;
wire VAR35 =
VAR2 == 6'h02 ? 0 :
VAR2 == 6'h03 ? 0 : 1;
wire [1:0] VAR50 =
(VAR2 == 6'h03) ? 2'b10 :
(VAR2 == 6'h00) ? 2'b00 : 2'b01;
wire [31:0] VAR26 = {{16{VAR3[15]}},VAR3};
wire [31:0] VAR10 = {{16{1'b0}},VAR3};
wire [31:0] VAR45 = VAR42 ? VAR26 : VAR10;
wire [4:0] VAR43 =
(VAR50 == 2'b00) ? VAR30 :
(VAR50 == 2'b01) ? VAR23 :
(VAR50 == 2'b10) ? 5'b11111 : VAR30;
wire VAR8 =
((VAR2 == 6'h02) ||
(VAR2 == 6'h03) ||
(VAR2 == 6'h00 && VAR11 == 6'h08) ||
(VAR2 == 6'h00 && VAR11 == 6'h09)) && !VAR1;
wire VAR27 = ((VAR2 == 6'h04) || (VAR2 == 6'h05)) && !VAR1;
always @(posedge clk) begin
if (!VAR33) begin
if (rst || VAR49) begin
VAR15 <= 0;
VAR29 <= 0;
VAR40 <= 0;
VAR6 <= 0;
VAR32 <= 0;
VAR39 <= 0;
VAR18 <= 0;
VAR9 <= 0;
VAR44 <= 0;
VAR36 <= 0;
VAR47 <= 0;
VAR17 <= 0;
VAR12 <= 0;
VAR25 <= 0;
VAR28 <= 0;
VAR21 <= 0;
VAR34 <= 0;
VAR19 <= 0;
end else begin
VAR15 <= VAR16;
VAR29 <= VAR37;
VAR40 <= VAR24;
VAR6 <= VAR11;
VAR32 <= VAR43;
VAR39 <= VAR7;
VAR18 <= VAR14;
VAR9 <= VAR5;
VAR44 <= VAR31;
VAR36 <= VAR8;
VAR47 <= VAR27;
VAR17 <= VAR35;
VAR12 <= VAR41;
VAR25 <= VAR46;
VAR28 <= VAR48;
VAR21 <= VAR20;
VAR34 <= VAR23;
VAR19 <= VAR45;
end
end
end
always @(negedge clk) begin
if (VAR22 && VAR52 != 5'd0) begin
VAR38[VAR52] <= VAR13;
end
end
endmodule
|
gpl-3.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/flow_classification.v
| 8,725 |
module MODULE1
(
input VAR76,
output [63:0] VAR41,
output [23:0] VAR84,
output VAR19,
output reg VAR38,
input VAR64,
output VAR37,
output VAR63,
output [63:0] VAR14,
output [23:0] VAR13,
output VAR56,
output reg VAR75,
input VAR34,
output VAR10,
output VAR5,
output [63:0] VAR74,
output [23:0] VAR73,
output VAR72,
output reg VAR28,
input VAR81,
output VAR7,
output VAR83,
output [63:0] VAR62,
output [23:0] VAR52,
output VAR40,
output reg VAR11,
input VAR32,
output VAR8,
output VAR49,
input [63:0] VAR1,
input [7:0] VAR44,
input VAR42,
output VAR59,
input VAR30,
input VAR18,
input VAR26,
input [VAR9-1:0] VAR31,
input [VAR79-1:0] VAR61,
input [1:0] VAR4,
output VAR43,
output VAR36,
output VAR6,
output [VAR9-1:0] VAR53,
output [VAR79-1:0] VAR51,
output [1:0] VAR50,
input clk,
input reset,
output VAR69,
output VAR20
);
assign VAR43 = VAR30;
assign VAR36 = VAR18;
assign VAR6 = VAR26;
assign VAR53 = VAR31;
assign VAR51 = VAR61;
assign VAR50 = VAR4;
reg [63:0] VAR55[3:0];
reg [23:0] VAR48[3:0];
reg [3:0] VAR57;
reg [3:0] VAR66;
reg [3:0] VAR21;
reg [3:0] VAR23;
assign VAR41 = VAR55[0];
assign VAR14 = VAR55[1];
assign VAR74 = VAR55[2];
assign VAR62 = VAR55[3];
assign VAR84 = VAR48[0];
assign VAR13 = VAR48[1];
assign VAR73 = VAR48[2];
assign VAR52 = VAR48[3];
assign VAR19 = VAR57[0];
assign VAR56 = VAR57[1];
assign VAR72 = VAR57[2];
assign VAR40 = VAR57[3];
assign VAR37 = VAR23[0];
assign VAR10 = VAR23[1];
assign VAR7 = VAR23[2];
assign VAR8 = VAR23[3];
reg VAR60;
assign VAR59 = VAR60;
reg VAR25;
reg VAR70;
wire VAR78;
assign VAR78 = ((VAR25 == 0) && (VAR70 != 0)) ? 1 : 0;
reg [2:0] VAR35;
reg [2:0] VAR29;
parameter VAR27 =3'b000,
VAR39= 3'b001,
VAR15= 3'b010,
VAR58= 3'b011,
VAR80 = 3'b100;
reg [7:0] VAR82;
reg VAR12;
reg VAR47;
reg [3:0] VAR16;
reg [2:0] state;
reg [2:0] VAR65;
parameter VAR45 = 3'b001,
VAR77 = 3'b010,
VAR33 = 3'b011,
VAR22 = 3'b100,
VAR71 = 3'b101,
VAR67 = 3'b110,
VAR68 = 3'b111;
reg [1:0] VAR46;
wire [1:0] VAR54;
assign VAR54 = (VAR46 == 2'b11) ? 0 : VAR46 + 1;
reg [1:0] VAR17;
reg VAR24;
assign VAR69 = VAR24;
always @begin
VAR29 = VAR35;
case(VAR35)
VAR27: begin
if(VAR12)
VAR29 = VAR39;
end
else
VAR29 = VAR27;
end
VAR39: begin
if(VAR42)
VAR29 = VAR15;
end
VAR15: begin
VAR29 = VAR58;
end
VAR58: begin
VAR29 = VAR80;
end
VAR80: begin
VAR82[7:0] = VAR1[7:0];
VAR29 = VAR27;
if(VAR76 == 1'b1) begin
VAR47 = 1'b0;
VAR16[0] = 1'b1;
VAR16[1] = 1'b1;
VAR16[2] = 1'b0;
VAR16[3] = 1'b0;
VAR24 = 1'b0;
end
else begin
VAR47 = 1'b1; VAR16[0] = 1'b1;
VAR16[1] = 1'b1;
VAR16[2] = 1'b1;
VAR16[3] = 1'b0;
VAR24 = 1'b1;
end
end
endcase
end
assign VAR20 = VAR47;
always @(posedge clk) begin
if(reset) begin
VAR35 <= 0;
end else begin
VAR35 <= VAR29;
end
end
assign VAR63 = VAR16[0];
assign VAR5 = VAR16[1];
assign VAR83 = VAR16[2];
assign VAR49 = VAR16[3];
wire [35:0] VAR3;
wire [239:0] VAR2;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/and3b/sky130_fd_sc_lp__and3b_4.v
| 2,218 |
module MODULE1 (
VAR8 ,
VAR6 ,
VAR10 ,
VAR3 ,
VAR4,
VAR7,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR3 ;
input VAR4;
input VAR7;
input VAR1 ;
input VAR2 ;
VAR9 VAR5 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8 ,
VAR6,
VAR10 ,
VAR3
);
output VAR8 ;
input VAR6;
input VAR10 ;
input VAR3 ;
supply1 VAR4;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
VAR9 VAR5 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
cheehieu/qm-fir-digital-filter-core
|
ISAAC/qmfir_documentation/v/BLK_MEM_GEN_V2_8.v
| 49,479 |
module MODULE1
parameter VAR5 = 0,
parameter VAR12 = "0",
parameter VAR11 = 0,
parameter VAR24 = 0,
parameter VAR21 = 0,
parameter VAR10 = "VAR6",
parameter VAR20 = "VAR6",
parameter VAR22 = 0,
parameter VAR25 = 0,
parameter VAR15 = 1,
parameter VAR8 = 100)
(input VAR4,
input VAR23,
input VAR1,
input VAR7,
input [VAR14-1:0] VAR16,
output reg [VAR14-1:0] VAR17);
localparam VAR19 = (VAR15 == 0) ? 0 : VAR15-1;
reg [VAR14*VAR19-1:0] VAR2;
reg [VAR14*8-1:0] VAR18 = VAR12;
reg [VAR14-1:0] VAR3;
wire VAR9;
wire VAR27;
wire VAR13;
assign VAR9 = (VAR24==0 || VAR7)
|| (VAR21 && VAR10=="VAR26");
assign VAR27 = ((VAR11==1) && VAR1) ||
((VAR11==0) && (VAR24==0 || VAR7))
|| (VAR21 && VAR10=="VAR26");
assign VAR13 = (VAR5==1) && VAR23;
begin
begin
begin
begin
begin
begin
begin
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/probec_p/sky130_fd_sc_hd__probec_p.functional.pp.v
| 1,793 |
module MODULE1 (
VAR5 ,
VAR9 ,
VAR6,
VAR8 ,
VAR7 ,
VAR11
);
output VAR5 ;
input VAR9 ;
input VAR6;
input VAR8 ;
input VAR7 ;
input VAR11;
wire VAR10 ;
wire VAR1;
buf VAR2 (VAR10 , VAR9 );
VAR12 VAR3 (VAR1, VAR10, VAR11, VAR6);
buf VAR4 (VAR5 , VAR1 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.pp.symbol.v
| 1,521 |
module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR4,
input VAR10 ,
input VAR3 ,
input VAR5 ,
input VAR6 ,
input VAR2 ,
input VAR9 ,
input VAR8
);
endmodule
|
apache-2.0
|
gbraad/minimig-de1
|
rtl/sdram/sdram_ctrl.v
| 18,802 |
module MODULE1(
input wire VAR50,
input wire VAR13,
input wire VAR17,
input wire VAR47,
output wire VAR27,
input wire VAR71,
output reg [ 12-1:0] VAR56,
output reg [ 4-1:0] VAR35,
output reg [ 2-1:0] VAR40,
output reg VAR68,
output reg VAR2,
output reg VAR39,
output reg [ 2-1:0] VAR8,
inout wire [ 16-1:0] VAR95,
input wire VAR28,
input wire [ 24-1:0] VAR88,
input wire VAR82,
input wire [ 2-1:0] VAR23,
input wire [ 16-1:0] VAR109,
output reg [ 16-1:0] VAR42,
output wire VAR6,
input wire [23:1] VAR46,
input wire VAR49,
input wire VAR18,
input wire VAR59,
input wire VAR32,
input wire [ 16-1:0] VAR70,
output reg [ 16-1:0] VAR10,
input wire [24:1] VAR93,
input wire [ 6-1:0] VAR75,
input wire VAR104,
input wire VAR34,
input wire VAR29,
input wire [ 16-1:0] VAR43,
output wire [ 16-1:0] VAR101,
output reg VAR64,
output reg VAR36,
output reg VAR73,
output wire VAR97
);
localparam [3:0]
VAR107 = 0,
VAR65 = 1,
VAR21 = 2,
VAR20 = 3,
VAR61 = 4,
VAR77 = 5,
VAR110 = 6,
VAR48 = 7,
VAR44 = 8,
VAR80 = 9,
VAR24 = 10,
VAR54 = 11,
VAR1 = 12,
VAR9 = 13,
VAR85 = 14,
VAR3 = 15;
parameter [1:0]
VAR60 = 0,
VAR67 = 1,
VAR86 = 2;
reg [ 4-1:0] VAR5;
reg [ 4-1:0] VAR25;
reg VAR30;
reg VAR22;
reg VAR113;
reg [ 2-1:0] VAR112;
reg VAR84;
reg [ 16-1:0] VAR81;
reg [ 25-1:0] VAR7;
reg VAR105;
reg [ 16-1:0] VAR16;
reg VAR78;
reg VAR87;
reg VAR58;
reg [ 64-1:0] VAR76;
reg [ 25-1:0] VAR53;
reg VAR41;
reg VAR63;
reg [ 4-1:0] VAR66;
wire VAR51;
reg [ 2-1:0] VAR14;
reg [ 16-1:0] VAR37;
reg [ 8-1:0] VAR92;
reg reset;
reg VAR111;
reg VAR91;
reg VAR103;
reg VAR45;
reg VAR90;
reg VAR4;
reg [ 4-1:0] VAR89;
wire [ 2-1:0] VAR94;
wire [ 4-1:0] VAR100;
wire [ 4-1:0] VAR33;
always @ (posedge VAR50 or negedge VAR17) begin
if (~VAR17) begin
VAR92 <= 8'b00000000;
reset <= 1'b0;
VAR111 <= 1'b0;
end else begin
if (VAR92 == 8'b00101010) begin
VAR111 <= 1'b1;
end
if (VAR92 == 8'b10101010) begin
if (VAR89 == VAR3) begin
reset <= 1'b1;
end
end else begin
VAR92 <= VAR92 + 8'd1;
reset <= 1'b0;
end
end
end
assign VAR27 = VAR84;
assign VAR6 = VAR87;
always @ (posedge VAR50 or negedge reset) begin
if (~reset) begin
VAR87 <= 1'b0;
end else begin
if (VAR64 && VAR87) begin
VAR87 <= 1'b0;
end
if ((VAR89 == VAR54) && VAR78) begin
if ((VAR88 == VAR7[23:0]) && !VAR22) begin
VAR87 <= 1'b1;
end
end
end
end
always @ (posedge VAR50) begin
if ((VAR89 == VAR80) && VAR78) begin
VAR42 <= VAR16;
end
end
reg [24:1] VAR106 = 0;
reg [ 6-1:0] VAR102 = 0;
reg VAR12 = 0;
reg VAR52 = 0;
reg VAR69 = 0;
reg [ 16-1:0] VAR31 = 0;
always @ (posedge VAR50) begin
VAR31 <= VAR43;
end
wire VAR83;
assign VAR97 = VAR83 || (VAR75[1:0] == 2'b01);
VAR98 VAR98 (
.clk (VAR50 ),
.rst (!(reset && VAR47)),
.VAR71 (VAR71 ),
.VAR75 (VAR75 ),
.VAR62 (VAR93 ),
.VAR99 ({VAR34, VAR104} ),
.VAR55 (VAR43 ),
.VAR19 (VAR101 ),
.VAR38 (VAR83 ),
.VAR114 (VAR89 ),
.VAR15 (VAR7 ),
.VAR96 (VAR90 ),
.VAR11 (VAR22 ),
.VAR72 ( ),
.VAR26 (VAR16 ),
.VAR108 ( )
);
reg [ 16-1:0] VAR74;
always @ (posedge VAR50) begin
if ((VAR89 == VAR80) && VAR4)
VAR74 <= VAR16;
end
always @ (*) begin
VAR10 = VAR74;
end
always @ (negedge VAR50) begin
VAR91 <= VAR13;
end
always @ (posedge VAR50) begin
VAR103 <= VAR91;
VAR45 <= VAR91 & ~VAR103;
end
assign VAR95 = (VAR105) ? VAR81 : 16'VAR79;
always @ (posedge VAR50) begin
VAR16 <= VAR95;
end
always @ (posedge VAR50) begin
if (VAR89 == VAR21) begin
if (VAR4) begin
VAR81 <= VAR70;
end else if (VAR90) begin
VAR81 <= VAR43;
end else begin
VAR81 <= VAR109;
end
end
end
always @ (posedge VAR50 or negedge VAR111) begin
if (~VAR111) begin
VAR105 <= 1'b0;
VAR64 <= 1'b0;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end else begin
case (VAR89) VAR21 : begin
VAR105 <= 1'b1;
VAR64 <= 1'b1;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end
VAR20 : begin
VAR105 <= 1'b1;
VAR64 <= 1'b0;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end
VAR61 : begin
VAR105 <= 1'b1;
VAR64 <= 1'b0;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end
VAR77 : begin
VAR105 <= 1'b1;
VAR64 <= 1'b0;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end
VAR110 : begin
VAR105 <= 1'b0;
VAR64 <= 1'b1;
VAR36 <= 1'b1;
VAR73 <= 1'b0;
end
VAR24 : begin
VAR105 <= 1'b0;
VAR64 <= 1'b1;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end
VAR85 : begin
VAR105 <= 1'b0;
VAR64 <= 1'b1;
VAR36 <= 1'b0;
VAR73 <= 1'b1;
end
default : begin
VAR105 <= 1'b0;
VAR64 <= 1'b0;
VAR36 <= 1'b0;
VAR73 <= 1'b0;
end
endcase
end
end
always @ (posedge VAR50 or negedge reset) begin
if (~reset) begin
VAR5 <= {4{1'b0}};
VAR84 <= 1'b0;
end else begin
case (VAR89) VAR3 : begin
if (VAR5 != 4'b1111) begin
VAR5 <= VAR5 + 4'd1;
end else begin
VAR84 <= 1'b1;
end
end
default : begin
end
endcase
end
end
always @ (posedge VAR50) begin
if (VAR45) begin
VAR89 <= VAR21;
end else begin
case (VAR89) VAR107 : begin
VAR89 <= VAR65;
end
VAR65 : begin
VAR89 <= VAR21;
end
VAR21 : begin
VAR89 <= VAR20;
end
VAR20 : begin
VAR89 <= VAR61;
end
VAR61 : begin
VAR89 <= VAR77;
end
VAR77 : begin
VAR89 <= VAR110;
end
VAR110 : begin
VAR89 <= VAR48;
end
VAR48 : begin
VAR89 <= VAR44;
end
VAR44 : begin
VAR89 <= VAR80;
end
VAR80 : begin
VAR89 <= VAR24;
end
VAR24 : begin
VAR89 <= VAR54;
end
VAR54 : begin
VAR89 <= VAR1;
end
VAR1 : begin
VAR89 <= VAR9;
end
VAR9 : begin
VAR89 <= VAR85;
end
VAR85 : begin
VAR89 <= VAR3;
end
default : begin
VAR89 <= VAR107;
end
endcase
end
end
always @ (posedge VAR50) begin
VAR35 <= 4'b1111;
VAR2 <= 1'b1;
VAR39 <= 1'b1;
VAR68 <= 1'b1;
VAR56 <= 12'VAR57;
VAR40 <= 2'b00;
VAR8 <= 2'b00;
if (!VAR84) begin
if (VAR89 == VAR65) begin
case (VAR5)
4'b0010 : begin
VAR56[10] <= 1'b1;
VAR35 <= 4'b0000;
VAR2 <= 1'b0;
VAR39 <= 1'b1;
VAR68 <= 1'b0;
end
4'b0011,4'b0100,4'b0101,4'b0110,4'b0111,4'b1000,4'b1001,4'b1010,4'b1011,4'b1100 : begin
VAR35 <= 4'b0000;
VAR2 <= 1'b0;
VAR39 <= 1'b0;
VAR68 <= 1'b1;
end
4'b1101 : begin
VAR35 <= 4'b0000;
VAR2 <= 1'b0;
VAR39 <= 1'b0;
VAR68 <= 1'b0;
VAR56 <= 12'b001000110010; end
default : begin
end
endcase
end
end else begin
if (VAR89 == VAR65) begin
VAR90 <= 1'b0;
VAR4 <= 1'b0;
VAR78 <= 1'b0;
VAR25 <= 4'b1110;
VAR30 <= 1'b1;
VAR22 <= 1'b1;
VAR113 <= 1'b1;
if (!VAR32 || !VAR59) begin
VAR4 <= 1'b1;
VAR56 <= VAR46[20:9];
VAR40 <= VAR46[22:21];
VAR112 <= {VAR18,VAR49};
VAR35 <= 4'b1110; VAR2 <= 1'b0;
VAR7 <= {1'b0,VAR46,1'b0};
VAR22 <= 1'b0;
VAR113 <= VAR59;
end else if (!VAR75[2] && !VAR75[5]) begin
VAR90 <= 1'b1;
VAR56 <= VAR93[20:9];
VAR40 <= VAR93[22:21];
VAR112 <= {VAR34,VAR104};
VAR35 <= 4'b1110; VAR2 <= 1'b0;
VAR7 <= {VAR93[24:1],1'b0};
VAR22 <= 1'b0;
VAR113 <= ~VAR75[1] | ~VAR75[0];
end else if (VAR28 && !VAR6) begin
VAR78 <= 1'b1;
VAR56 <= VAR88[20:9];
VAR40 <= VAR88[22:21];
VAR112 <= ~VAR23;
VAR35 <= 4'b1110; VAR2 <= 1'b0;
VAR7 <= {1'b0, VAR88};
VAR22 <= 1'b0;
VAR113 <= !VAR82;
end else begin
VAR35 <= 4'b0000; VAR2 <= 1'b0;
VAR39 <= 1'b0;
end
end
if (VAR89 == VAR61) begin
VAR56 <= {1'b0,1'b1,1'b0,VAR7[23],VAR7[8:1]}; VAR40 <= VAR7[22:21];
VAR35 <= VAR25;
VAR8 <= (!VAR113) ? VAR112 : 2'b00;
VAR2 <= VAR30;
VAR39 <= VAR22;
VAR68 <= VAR113;
end
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o32ai/sky130_fd_sc_hd__o32ai_4.v
| 2,441 |
module MODULE2 (
VAR5 ,
VAR11 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR12 ,
VAR7,
VAR8,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR11 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR12 ;
input VAR7;
input VAR8;
input VAR2 ;
input VAR1 ;
VAR9 VAR10 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR11,
VAR4,
VAR3,
VAR6,
VAR12
);
output VAR5 ;
input VAR11;
input VAR4;
input VAR3;
input VAR6;
input VAR12;
supply1 VAR7;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR1 ;
VAR9 VAR10 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR12(VAR12)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/nand4b/sky130_fd_sc_hs__nand4b.pp.symbol.v
| 1,297 |
module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR1 ,
input VAR6 ,
output VAR4 ,
input VAR3,
input VAR2
);
endmodule
|
apache-2.0
|
impedimentToProgress/ProbableCause
|
ddr2/cores/ethmac/ethmac.v
| 33,872 |
module MODULE1 (
VAR159, VAR4, VAR237, VAR161,
VAR95, VAR9, VAR43, VAR235, VAR32, VAR3, VAR206,
VAR258, VAR125, VAR83,
VAR135, VAR279, VAR234,
VAR109, VAR251, VAR221,
VAR208, VAR186,
VAR165, VAR150, VAR56, VAR12,
VAR156, VAR19, VAR146, VAR87, VAR72,
VAR288,
VAR97, VAR178, VAR256, VAR23,
VAR55
,
VAR74, VAR115, VAR93 VAR116
);
input VAR159; input VAR4; input [31:0] VAR237; output [31:0] VAR161; output VAR206;
input [11:2] VAR95; input [3:0] VAR9; input VAR43; input VAR235; input VAR32; output VAR3;
output [31:0] VAR258;
output [3:0] VAR125;
output VAR83;
input [31:0] VAR279;
output [31:0] VAR135;
output VAR234;
output VAR109;
input VAR251;
input VAR221;
wire [29:0] VAR132;
output [2:0] VAR208; output [1:0] VAR186; VAR116
input VAR165; output [3:0] VAR150; output VAR56; output VAR12;
input VAR156; input [3:0] VAR19; input VAR146; input VAR87;
input VAR72; input VAR288;
input VAR178; output VAR97; output VAR256; output VAR23;
output VAR55;
input VAR74; output VAR115; input [VAR245 - 1:0] VAR93; VAR116
wire [31:0] VAR78;
wire [7:0] VAR92;
wire VAR140;
wire [15:0] VAR134;
wire [4:0] VAR15;
wire [4:0] VAR204;
wire VAR85;
wire VAR276;
wire VAR170;
wire VAR39;
wire VAR147;
wire VAR250;
wire [15:0] VAR201; wire VAR26;
wire VAR225;
wire VAR90;
wire VAR94;
wire VAR275;
wire VAR76;
wire [7:0] VAR8;
wire VAR169;
wire VAR40;
wire VAR144;
wire VAR271;
reg VAR153;
reg VAR6;
reg VAR217;
reg VAR163;
reg VAR185;
reg VAR282;
reg VAR10;
reg VAR61;
VAR188 VAR192
(
.VAR238(VAR159),
.VAR248(VAR4),
.VAR262(VAR92),
.VAR267(VAR140),
.VAR212(VAR134),
.VAR17(VAR204),
.VAR246(VAR15),
.VAR68(VAR85),
.VAR69(VAR276),
.VAR236(VAR170),
.VAR174(VAR178),
.VAR65(VAR256),
.VAR226(VAR23),
.VAR291(VAR97),
.VAR20(VAR147),
.VAR201(VAR201),
.VAR250(VAR250),
.VAR88(VAR39),
.VAR26(VAR26),
.VAR225(VAR225),
.VAR90(VAR90)
);
wire [3:0] VAR129; wire [31:0] VAR128; wire VAR133; wire VAR198; wire VAR189; wire VAR33;
wire VAR44; wire VAR28; wire [3:0] VAR16; wire VAR214; wire VAR143; wire VAR249; wire [15:0] VAR283;
wire [15:0] VAR67; wire VAR13;
wire VAR151; wire VAR152; wire [47:0] VAR244; wire VAR182; wire [31:0] VAR142; wire [31:0] VAR285; wire [7:0] VAR243; wire [6:0] VAR187; wire [6:0] VAR274; wire [6:0] VAR57; wire [5:0] VAR160; wire [15:0] VAR168; wire VAR173;
wire [3:0] VAR269; wire VAR30; wire VAR5; wire VAR209; wire VAR252;
wire VAR81; wire VAR183; wire VAR266; wire VAR101; wire VAR89;
wire VAR241;
wire VAR35;
wire [31:0] VAR70; wire [3:0] VAR98; wire VAR154; wire VAR107;
wire VAR104;
wire VAR64;
wire VAR260;
wire VAR219;
wire VAR240;
wire VAR52;
wire VAR11;
wire VAR270;
wire VAR59;
wire VAR117;
wire VAR264;
wire VAR120;
wire VAR166;
wire VAR25;
wire VAR114;
wire VAR96;
wire VAR184;
wire VAR53;
wire VAR27;
wire VAR273;
wire VAR213;
wire VAR38;
wire VAR46;
wire VAR1;
wire VAR118;
wire VAR29;
wire VAR197;
wire VAR51;
wire VAR175;
wire [31:0] VAR137;
wire VAR79;
reg VAR126;
reg [31:0] VAR37;
reg VAR77;
assign VAR241 = |VAR9;
assign VAR129[3] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & ~VAR95[10] & VAR9[3]; assign VAR129[2] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & ~VAR95[10] & VAR9[2]; assign VAR129[1] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & ~VAR95[10] & VAR9[1]; assign VAR129[0] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & ~VAR95[10] & VAR9[0]; assign VAR98[3] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & VAR95[10] & VAR9[3]; assign VAR98[2] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & VAR95[10] & VAR9[2]; assign VAR98[1] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & VAR95[10] & VAR9[1]; assign VAR98[0] = VAR32 & VAR235 & VAR241 & ~VAR95[11] & VAR95[10] & VAR9[0]; assign VAR154 = VAR32 & VAR235 & VAR241 & VAR95[11]; assign VAR137 = ((|VAR129) & ~VAR43)? VAR128 : VAR70;
assign VAR79 = VAR32 & VAR235 & (~VAR241 | VAR154);
assign VAR3 = VAR126;
assign VAR161[31:0] = VAR37;
assign VAR206 = VAR77;
assign VAR3 = VAR175;
assign VAR161[31:0] = VAR137;
assign VAR206 = VAR79;
assign VAR175 = (|VAR129) | VAR35 | VAR154;
always @ (posedge VAR159 or posedge VAR4)
begin
if(VAR4)
begin
VAR126 <= 1'b0;
VAR37 <= 32'h0;
VAR77 <= 1'b0;
end
else
begin
VAR126 <= VAR175 & ~VAR126;
VAR37 <= VAR137;
VAR77 <= VAR79 & ~VAR77;
end
end
VAR124 VAR47
(
.VAR139(VAR237),
.VAR54(VAR95[9:2]),
.VAR7(VAR43),
.VAR200(VAR129),
.VAR238(VAR159),
.VAR248(VAR4),
.VAR172(VAR128),
.VAR133(VAR133),
.VAR107(VAR107),
.VAR143(VAR143),
.VAR104(VAR104),
.VAR249(VAR249),
.VAR64(VAR64),
.VAR5(VAR5),
.VAR30(VAR30),
.VAR198(VAR198),
.VAR252(VAR252),
.VAR260(VAR260),
.VAR62(),
.VAR219(VAR219),
.VAR240(VAR240),
.VAR189(VAR189),
.VAR33(VAR33),
.VAR89(VAR89),
.VAR101(VAR101),
.VAR266(VAR266),
.VAR183(VAR183),
.VAR81(VAR81),
.VAR187(VAR187),
.VAR274(VAR274),
.VAR57(VAR57),
.VAR67(VAR67),
.VAR283(VAR283),
.VAR269(VAR269),
.VAR160(VAR160),
.VAR209(VAR209),
.VAR52(VAR52),
.VAR11(VAR11),
.VAR140(VAR140),
.VAR92(VAR92),
.VAR85(VAR85),
.VAR276(VAR276),
.VAR170(VAR170),
.VAR204(VAR204),
.VAR15(VAR15),
.VAR134(VAR134),
.VAR39(VAR39),
.VAR147(VAR147),
.VAR250(VAR250),
.VAR244(VAR244),
.VAR26(VAR26),
.VAR225(VAR225),
.VAR90(VAR90),
.VAR201(VAR201),
.VAR243(VAR243),
.VAR55(VAR55),
.VAR142(VAR142),
.VAR285(VAR285),
.VAR173(VAR173),
.VAR168(VAR168),
.VAR163(VAR163),
.VAR270(VAR270),
.VAR59(VAR59),
.VAR194(VAR165),
.VAR292(VAR156),
.VAR121(VAR78),
.VAR117(VAR117)
);
wire [7:0] VAR119;
wire VAR265;
wire VAR268;
wire VAR179;
wire VAR31;
wire VAR247; wire VAR210; wire [7:0] VAR34; wire VAR284;
wire VAR231;
wire VAR228;
wire VAR261;
wire VAR112;
wire VAR257;
wire VAR202;
wire [3:0] VAR105;
wire [3:0] VAR86;
wire VAR148;
wire VAR255;
wire VAR259;
wire VAR232;
wire [1:0] VAR45;
VAR155 VAR84
(
.VAR211(VAR165),
.VAR61(VAR61),
.VAR18(VAR168),
.VAR199(VAR8),
.VAR66(VAR94),
.VAR196(VAR275),
.VAR264(VAR264),
.VAR120(VAR120),
.VAR166(VAR166),
.VAR108(VAR156),
.VAR119(VAR119),
.VAR265(VAR265),
.VAR268(VAR268),
.VAR179(VAR179),
.VAR231(VAR231),
.VAR228(VAR228),
.VAR242(VAR209),
.VAR220(VAR52),
.VAR102(VAR249),
.VAR100(VAR244),
.VAR63(VAR107 | VAR25),
.VAR114(VAR114),
.VAR91(VAR104 | VAR96),
.VAR184(VAR184),
.VAR233(VAR4),
.VAR99(VAR4),
.VAR261(VAR261),
.VAR34(VAR34),
.VAR53(VAR53),
.VAR27(VAR27),
.VAR254(VAR76),
.VAR111(VAR271),
.VAR230(VAR40),
.VAR284(VAR284),
.VAR270(VAR270),
.VAR273(VAR273),
.VAR213(VAR213),
.VAR117(VAR117),
.VAR38(VAR38),
.VAR11(VAR11)
);
wire VAR103; wire VAR80;
reg VAR41;
reg VAR127;
reg VAR290;
reg VAR287;
reg VAR162; reg VAR158;
reg VAR113;
assign VAR44 = VAR198? VAR56 : VAR146 & VAR162;
assign VAR28 = VAR198? VAR12 : VAR87 & VAR162;
assign VAR16[3:0] = VAR198? VAR150[3:0] : VAR19[3:0];
VAR171 VAR207
(
.VAR211(VAR165),
.VAR248(VAR4),
.VAR164(VAR103),
.VAR80(VAR80),
.VAR8(VAR34),
.VAR94(VAR53),
.VAR144(VAR144),
.VAR275(VAR27),
.VAR239(VAR114),
.VAR73(VAR67),
.VAR281(VAR184),
.VAR280(VAR64),
.VAR2(VAR143),
.VAR102(VAR249),
.VAR289(VAR187),
.VAR253(VAR274),
.VAR58(VAR57),
.VAR203(VAR160),
.VAR141(VAR269),
.VAR145(VAR30),
.VAR278(VAR5),
.VAR48(VAR283),
.VAR224(VAR56),
.VAR177(VAR150),
.VAR191(VAR12),
.VAR76(VAR264),
.VAR271(VAR120),
.VAR169(VAR169),
.VAR40(VAR166),
.VAR247(VAR247),
.VAR210(VAR210),
.VAR86(VAR86),
.VAR59(VAR59),
.VAR148(VAR148),
.VAR255(VAR255),
.VAR46(VAR46),
.VAR1(VAR1),
.VAR232(VAR232),
.VAR45(VAR45)
);
wire [15:0] VAR218;
wire VAR82;
wire VAR22;
wire VAR229;
wire VAR49;
wire VAR157;
wire VAR167;
wire VAR193;
wire [1:0] VAR50;
wire VAR190;
VAR60 VAR122
(
.VAR108(VAR156),
.VAR181(VAR44),
.VAR293(VAR16),
.VAR214(VAR214),
.VAR2(VAR143),
.VAR102(VAR249),
.VAR48(VAR283),
.VAR252(VAR252),
.VAR248(VAR4),
.VAR119(VAR119),
.VAR265(VAR265),
.VAR268(VAR268),
.VAR179(VAR179),
.VAR75(VAR218),
.VAR215(VAR82),
.VAR277(VAR22),
.VAR216(VAR229),
.VAR110(VAR49),
.VAR272(VAR157),
.VAR232(VAR167),
.VAR180(VAR193),
.VAR45(VAR50),
.VAR100(VAR244),
.VAR260(VAR260),
.VAR219(VAR219),
.VAR142(VAR142),
.VAR285(VAR285),
.VAR31(VAR31),
.VAR190(VAR190),
.VAR176(VAR11),
.VAR213(VAR213)
);
always @ (posedge VAR165 or posedge VAR4)
begin
if(VAR4)
begin
VAR41 <= 1'b0;
VAR127 <= 1'b0;
end
else
begin
VAR41 <= VAR288;
VAR127 <= VAR41;
end
end
assign VAR103 = ~VAR64 & VAR127;
always @ (posedge VAR165 or posedge VAR4)
begin
if(VAR4)
begin
VAR290 <= 1'b0;
VAR287 <= 1'b0;
end
else
begin
VAR290 <= VAR72;
if(VAR210)
VAR287 <= 1'b0;
end
else
if(VAR290)
VAR287 <= 1'b1;
end
end
assign VAR80 = ~VAR64 & VAR287;
always @ (posedge VAR156)
begin
VAR158 <= VAR247;
VAR113 <= VAR158;
end
assign VAR214 = ~VAR64 & VAR113;
always @ (posedge VAR156 or posedge VAR4)
begin
if(VAR4)
VAR162 <= 1'b0;
end
else
if(~VAR146)
VAR162 <= VAR33;
end
always @ (posedge VAR159 or posedge VAR4)
begin
if(VAR4)
VAR153 <= 1'b0;
end
else
VAR153 <= VAR284;
end
always @ (posedge VAR159 or posedge VAR4)
begin
if(VAR4)
VAR6 <= 1'b0;
end
else
VAR6 <= VAR153;
end
always @ (posedge VAR159 or posedge VAR4)
begin
if(VAR4)
VAR217 <= 1'b0;
end
else
VAR217 <= VAR6;
end
always @ (posedge VAR159 or posedge VAR4)
begin
if(VAR4)
VAR163 <= 1'b0;
end
else
VAR163 <= VAR6 &
~VAR217;
end
always @ (posedge VAR165 or posedge VAR4)
begin
if(VAR4)
begin
VAR185 <= 1'b0;
VAR282 <= 1'b0;
VAR10 <= 1'b0;
end
else
begin
VAR185 <= (VAR173 & VAR209);
VAR282 <= VAR185;
VAR10 <= VAR282;
end
end
always @ (posedge VAR165 or posedge VAR4)
begin
if(VAR4)
VAR61 <= 1'b0;
end
else
VAR61 <= VAR282 & (~VAR10);
end
wire VAR195;
reg VAR223;
reg VAR222;
reg VAR149;
reg VAR24;
reg VAR286;
always @ (posedge VAR156 or posedge VAR4)
begin
if(VAR4)
VAR223 <= 1'b0;
end
else if(VAR31 | (VAR13 & ~VAR133) | VAR195 &
~VAR112 | (VAR273 & (~VAR11)))
VAR223 <= 1'b1;
else if(VAR286)
VAR223 <= 1'b0;
end
always @ (posedge VAR159 or posedge VAR4)
begin
if(VAR4)
begin
VAR222 <= 1'b0;
VAR149 <= 1'b0;
VAR149 <= 1'b0;
end
else
begin
VAR222 <= VAR223;
VAR149 <= VAR222;
end
end
always @ (posedge VAR156 or posedge VAR4)
begin
if(VAR4)
begin
VAR24 <= 1'b0;
VAR286 <= 1'b0;
end
else
begin
VAR24 <= VAR149;
VAR286 <= VAR24;
end
end
VAR205 VAR136
(
.VAR71(VAR159),
.VAR106(VAR237),
.VAR36(VAR70),
.VAR130(VAR95[9:2]),
.VAR42(VAR43),
.VAR98(VAR98),
.VAR138(VAR35),
.VAR248(VAR4),
.VAR258(VAR132),
.VAR125(VAR125),
.VAR83(VAR83),
.VAR279(VAR279),
.VAR135(VAR135),
.VAR234(VAR234),
.VAR109(VAR109),
.VAR251(VAR251),
.VAR221(VAR221),
.VAR208(VAR208),
.VAR186(VAR186),
.VAR211(VAR165),
.VAR94(VAR94),
.VAR275(VAR275),
.VAR76(VAR76),
.VAR8(VAR8),
.VAR169(VAR169),
.VAR40(VAR40),
.VAR144(VAR144),
.VAR271(VAR271),
.VAR96(VAR96),
.VAR25(VAR25),
.VAR189(VAR189),
.VAR33(VAR33),
.VAR243(VAR243),
.VAR52(VAR52),
.VAR11(VAR11),
.VAR108(VAR156),
.VAR119(VAR119),
.VAR265(VAR265),
.VAR268(VAR268),
.VAR179(VAR179),
.VAR89(VAR89),
.VAR101(VAR101),
.VAR266(VAR266),
.VAR183(VAR183),
.VAR81(VAR81),
.VAR31(VAR149),
.VAR38(VAR38),
.VAR112(VAR112),
.VAR257(VAR257),
.VAR14(VAR218),
.VAR202(VAR202),
.VAR13(VAR13),
.VAR151(VAR151),
.VAR152(VAR152),
.VAR182(VAR182),
.VAR105(VAR105),
.VAR259(VAR259),
.VAR118(VAR118),
.VAR29(VAR29),
.VAR197(VAR197),
.VAR51(VAR51),
.VAR228(VAR228),
.VAR190(VAR190),
.VAR273(VAR273)
,
.VAR74 (VAR74),
.VAR115 (VAR115),
.VAR93 (VAR93)
,
.VAR263(VAR78)
);
assign VAR258 = {VAR132, 2'h0};
VAR21 VAR131
(
.VAR108(VAR156),
.VAR248(VAR4),
.VAR231(VAR231),
.VAR228(VAR228),
.VAR261(VAR261),
.VAR49(VAR49),
.VAR227(VAR28),
.VAR181(VAR44),
.VAR193(VAR193),
.VAR50(VAR50),
.VAR167(VAR167),
.VAR157(VAR157),
.VAR214(VAR214),
.VAR218(VAR218),
.VAR82(VAR82),
.VAR22(VAR22),
.VAR229(VAR229),
.VAR112(VAR112),
.VAR293(VAR16),
.VAR257(VAR257),
.VAR80(VAR72),
.VAR203(VAR160),
.VAR202(VAR202),
.VAR133(VAR133),
.VAR67(VAR67),
.VAR283(VAR283),
.VAR13(VAR13),
.VAR151(VAR151),
.VAR152(VAR152),
.VAR143(VAR143),
.VAR182(VAR182),
.VAR86(VAR86),
.VAR59(VAR59),
.VAR148(VAR148),
.VAR105(VAR105),
.VAR211(VAR165),
.VAR255(VAR255),
.VAR259(VAR259),
.VAR46(VAR46),
.VAR118(VAR118),
.VAR1(VAR1),
.VAR29(VAR29),
.VAR197(VAR197),
.VAR94(VAR53),
.VAR232(VAR232),
.VAR45(VAR45),
.VAR164(VAR127),
.VAR51(VAR51),
.VAR76(VAR264),
.VAR195(VAR195),
.VAR123(VAR198),
.VAR64(VAR64)
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfbbn/sky130_fd_sc_ms__dfbbn.pp.blackbox.v
| 1,481 |
module MODULE1 (
VAR10 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR8,
VAR3 ,
VAR9 ,
VAR4 ,
VAR7
);
output VAR10 ;
output VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR8;
input VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR7 ;
endmodule
|
apache-2.0
|
mcoughli/root_of_trust
|
operational_os/hls/contact_discovery_axi_experimental/solution1/impl/ip/hdl/verilog/contact_discoverybkb.v
| 1,801 |
module MODULE1 (VAR10, VAR1, VAR5, VAR12, VAR8, VAR6, VAR3, VAR7, clk);
parameter VAR9 = 512;
parameter VAR11 = 7;
parameter VAR4 = 128;
input[VAR11-1:0] VAR10;
input VAR1;
input[VAR9-1:0] VAR5;
input VAR12;
output reg[VAR9-1:0] VAR8;
input[VAR11-1:0] VAR6;
input VAR3;
output reg[VAR9-1:0] VAR7;
input clk;
reg [VAR9-1:0] VAR2[0:VAR4-1];
begin
begin
begin
end
begin
begin
|
gpl-3.0
|
kielfriedt/ece472
|
lab3/ALU4_LA.v
| 1,372 |
module MODULE1(VAR1, VAR12, VAR16, VAR13, VAR4, sel, out, VAR9, VAR6);
input VAR4;
input [3:0] VAR1, VAR12;
input [2:0] sel;
input VAR16;
output [3:0] out;
output VAR9,VAR6;
output VAR13;
wire [2:0] VAR8;
wire [3:0] VAR2, VAR14;
VAR7 VAR11(VAR1[0], VAR12[0], VAR16, VAR4, sel, out[0], VAR2[0], VAR14[0]);
VAR7 VAR15(VAR1[1], VAR12[1], VAR8[0], 1'b0, sel, out[1], VAR2[1], VAR14[1]);
VAR7 VAR3(VAR1[2], VAR12[2], VAR8[1], 1'b0, sel, out[2], VAR2[2], VAR14[2]);
VAR7 VAR10(VAR1[3], VAR12[3], VAR8[2], 1'b0, sel, out[3], VAR2[3], VAR14[3]);
VAR17 VAR5(VAR16, VAR13, VAR8, VAR2, VAR14, VAR9, VAR6);
endmodule
|
gpl-3.0
|
bunnie/novena-gpbb-fpga
|
novena-gpbb.srcs/sources_1/imports/imports/i2c_slave.v
| 23,666 |
module MODULE1 (
input wire VAR36, input wire VAR37,
output reg VAR50,
input wire clk, input wire VAR35, input wire [7:0] VAR34,
output wire [7:0] VAR6, output wire [7:0] VAR65,
input wire [7:0] VAR41, input wire [7:0] VAR10,
input wire [7:0] VAR44,
input wire [7:0] VAR52, input wire [7:0] VAR45,
input wire [7:0] VAR16,
input wire [7:0] VAR53
);
wire reset;
VAR42 VAR21(
.clk(clk),
.VAR35(VAR35),
.reset(reset) );
parameter VAR7 = 5'd4;
parameter VAR61 = 14'b1 << 0; parameter VAR38 = 14'b1 << 1;
parameter VAR66 = 14'b1 << 2;
parameter VAR17 = 14'b1 << 3;
parameter VAR12 = 14'b1 << 4;
parameter VAR56 = 14'b1 << 5;
parameter VAR59 = 14'b1 << 6;
parameter VAR19 = 14'b1 << 7;
parameter VAR4 = 14'b1 << 8;
parameter VAR55 = 14'b1 << 9;
parameter VAR60 = 14'b1 << 10;
parameter VAR31 = 14'b1 << 11;
parameter VAR54 = 14'b1 << 12;
parameter VAR49 = 14'b1 << 13;
parameter VAR13 = 14;
reg [(VAR13-1):0] VAR58 = {{(VAR13-1){1'b0}}, 1'b1}; reg [(VAR13-1):0] VAR40;
reg [8*20:1] VAR57 = "VAR61 ";
always @(VAR58) begin
if (VAR58 == VAR61) VAR57 <= "VAR61 ";
end
else if (VAR58 == VAR38) VAR57 <= "VAR38 ";
else if (VAR58 == VAR66) VAR57 <= "VAR66 ";
else if (VAR58 == VAR17) VAR57 <= "VAR17 ";
else if (VAR58 == VAR12) VAR57 <= "VAR12 ";
else if (VAR58 == VAR56) VAR57 <= "VAR56 ";
else if (VAR58 == VAR59) VAR57 <= "VAR59 ";
else if (VAR58 == VAR19) VAR57 <= "VAR19 ";
else if (VAR58 == VAR4) VAR57 <= "VAR4 ";
else if (VAR58 == VAR55) VAR57 <= "VAR55 ";
else if (VAR58 == VAR60) VAR57 <= "VAR60 ";
else if (VAR58 == VAR31) VAR57 <= "VAR31 ";
else if (VAR58 == VAR54) VAR57 <= "VAR54 ";
else if (VAR58 == VAR49) VAR57 <= "VAR49 ";
else VAR57 <= "VAR62 ";
end
reg [3:0] VAR9;
reg [7:0] VAR14;
reg [7:0] VAR46;
reg [7:0] VAR18;
reg [7:0] VAR29;
reg VAR25;
parameter VAR24 = 8;
parameter VAR22 = 6;
reg [VAR24-1:0] VAR2 [(2**VAR22)-1:0];
reg [VAR24-1:0] VAR47;
wire [VAR22-1:0] VAR20;
always @ (posedge clk) begin
if (reset || ((VAR63 == VAR8) && (VAR5 == VAR39))) VAR58 <= VAR61;
end
else
VAR58 <= VAR40;
end
always @ begin
case (VAR14[7:0])
8'h40: begin
VAR47 = VAR41;
end
8'h41: begin
VAR47 = VAR10;
end
8'h42: begin
VAR47 = VAR44;
end
8'hfc: begin
VAR47 = VAR52;
end
8'hfd: begin
VAR47 = VAR45;
end
8'hfe: begin
VAR47 = VAR16;
end
8'hff: begin
VAR47 = VAR53;
end
default: begin
VAR47 = VAR2[VAR20];
end
endcase end
parameter VAR8 = 4'b1 << 0; parameter VAR33 = 4'b1 << 1;
parameter VAR43 = 4'b1 << 2;
parameter VAR11 = 4'b1 << 3;
parameter VAR15 = 4;
reg [(VAR15-1):0] VAR63 = {{(VAR15-1){1'b0}}, 1'b1}; reg [(VAR15-1):0] VAR28;
reg [8*20:1] VAR1 = "VAR8 ";
always @(VAR63) begin
if (VAR63 == VAR8) VAR1 <= "VAR8 ";
end
else if (VAR63 == VAR33) VAR1 <= "VAR33 ";
else if (VAR63 == VAR43 ) VAR1 <= "VAR43 ";
else if (VAR63 == VAR11) VAR1 <= "VAR11 ";
else VAR1 <= "VAR62 ";
end
reg [4:0] VAR32;
reg VAR48, VAR30;
reg VAR27, VAR64;
always @ (posedge clk) begin
if (reset)
end
VAR63 <= VAR8; else
VAR63 <= VAR28;
end
always @ begin
case (VAR5) VAR51: begin
VAR26 = ((VAR3 > VAR7) && (VAR64 == 1'b0)) ? VAR23 : VAR51;
end
VAR23: begin
VAR26 = VAR67;
end
VAR67: begin
VAR26 = ((VAR3 > VAR7) && (VAR64 == 1'b1)) ? VAR39 : VAR67;
end
VAR39: begin
VAR26 = VAR51;
end
endcase end
always @ (posedge clk) begin
if( reset ) begin
VAR3 <= 5'b0;
end else begin
case (VAR5) VAR51: begin
if( VAR64 == 1'b1 ) begin
VAR3 <= 5'b0;
end else begin
VAR3 <= VAR3 + 5'b1;
end
end
VAR23: begin
VAR3 <= 5'b0;
end
VAR67: begin
if( VAR64 == 1'b0 ) begin
VAR3 <= 5'b0;
end else begin
VAR3 <= VAR3 + 5'b1;
end
end
VAR39: begin
VAR3 <= 5'b0;
end
endcase end end
always @ (posedge clk) begin
VAR48 <= VAR36;
VAR30 <= VAR48;
VAR27 <= VAR37;
VAR64 <= VAR27;
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21oi/sky130_fd_sc_hdll__a21oi.functional.pp.v
| 2,026 |
module MODULE1 (
VAR16 ,
VAR12 ,
VAR15 ,
VAR4 ,
VAR8,
VAR5,
VAR3 ,
VAR7
);
output VAR16 ;
input VAR12 ;
input VAR15 ;
input VAR4 ;
input VAR8;
input VAR5;
input VAR3 ;
input VAR7 ;
wire VAR2 ;
wire VAR9 ;
wire VAR14;
and VAR10 (VAR2 , VAR12, VAR15 );
nor VAR11 (VAR9 , VAR4, VAR2 );
VAR1 VAR13 (VAR14, VAR9, VAR8, VAR5);
buf VAR6 (VAR16 , VAR14 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.functional.v
| 1,429 |
module MODULE1 (
VAR4 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR5;
input VAR3 ;
wire VAR7 ;
wire VAR1;
not VAR2 (VAR7 , VAR5 );
and VAR8 (VAR1, VAR7, VAR3 );
buf VAR6 (VAR4 , VAR1 );
endmodule
|
apache-2.0
|
Elphel/x353
|
compressor/csconvert_mono.v
| 10,819 |
module MODULE1 (en,
clk,
din,
VAR31,
VAR15,
VAR21,
VAR26,
VAR14);
input en;
input clk; input [7:0] din; input VAR31; output [7:0] VAR15; output [7:0] VAR21; output VAR26; output VAR14;
wire VAR14= VAR31;
wire [7:0] VAR15= {~din[7],din[6:0]};
reg [7:0] VAR21;
reg VAR26;
always @ (posedge clk) begin
VAR26 <= en & (VAR31 || (VAR26 && (VAR21[7:0] !=8'hff)));
if (!en || VAR31) VAR21[7:0] <= 8'h0;
end
else if (VAR26) VAR21[7:0] <= VAR21[7:0] + 1;
end
endmodule
module MODULE3 (en,
clk,
din,
VAR31,
VAR15,
VAR21,
VAR26,
VAR14);
input en;
input clk; input [7:0] din; input VAR31; output [7:0] VAR15; output [7:0] VAR21; output VAR26; output VAR14;
wire VAR14= VAR31;
wire [7:0] VAR15= {~din[7],din[6:0]};
reg [7:0] VAR38;
reg VAR26;
wire [7:0] VAR21= {VAR38[4],VAR38[7:5],VAR38[0],VAR38[3:1]};
always @ (posedge clk) begin
VAR26 <= en & (VAR31 || (VAR26 && (VAR21[7:0] !=8'hff)));
if (!en || VAR31) VAR38[7:0] <= 8'h0;
end
else if (VAR26) VAR38[7:0] <= VAR38[7:0] + 1;
end
endmodule
module MODULE2 (en,
clk,
VAR23, VAR25, din,
VAR31,
VAR15,
VAR21,
VAR26,
VAR14,
VAR17);
input en;
input clk; input VAR23;
input VAR25;
input [7:0] din; input VAR31; output [8:0] VAR15; output [7:0] VAR21; output VAR26; output VAR14;
input [1:0] VAR17;
reg VAR14;
reg [2:0] VAR37;
reg [8:0] VAR15;
reg [8:0] VAR30;
reg [7:0] VAR38;
reg [7:0] VAR5;
reg [7:0] VAR41;
reg VAR26;
reg [2:0] VAR35;
reg [7:0] VAR21;
reg VAR19;
reg [14:0] VAR16;
reg VAR11;
wire VAR6=VAR17[1]?(VAR17[0]?VAR11: VAR16[14]):(VAR17[0]?VAR19:VAR31);
reg [7:0] VAR29;
reg VAR22;
reg [1:0] VAR33;
reg [2:0] VAR7;
reg VAR40;
reg [1:0] VAR24;
reg [1:0] VAR8;
reg [7:0] VAR12;
reg [7:0] VAR18;
reg [7:0] VAR1;
reg [7:0] VAR28;
wire [7:0] VAR2;
reg [7:0] VAR20;
reg [14:0] VAR10,VAR39,VAR27,VAR13,VAR34,VAR3,VAR4,VAR32;
wire [8:0] VAR9= (VAR24[1])? +{VAR30[8],VAR30[8:1]}: VAR30[8:0];
assign VAR2[7:0]={VAR32[14],VAR4[14],VAR3[14],VAR34[14],VAR13[14],VAR27[14],VAR39[14],VAR10[14]};
always @ (posedge clk) begin
VAR19 <= VAR31;
VAR11 <= VAR16[14];
VAR16[14:0] <= {VAR16[13:0],VAR19};
VAR37[2:0]<= {VAR37[1:0], VAR6};
VAR14<= VAR37[2];
VAR22 <= en & (VAR6 || (VAR22 && (VAR29[7:0]!=8'hff)));
VAR35[2:0] <= {VAR35[1:0],VAR22};
VAR26 <= VAR35[2];
if (!en || VAR6) VAR29[7:0] <= 8'h0;
end
else if (VAR22) VAR29[7:0] <= VAR29[7:0] + 1;
VAR41[7:0] <= VAR29[7:0];
VAR5 [7:0] <= VAR41[7:0];
VAR38[7:0] <= VAR5[7:0];
VAR21[7:0] <= {VAR38[4],VAR38[7:5],VAR38[0],VAR38[3:1]};
case ({VAR17[1:0],VAR29[4],VAR29[0]} )
4'b0000: begin VAR33 <= 2'h0; VAR7 <= 3'h4; VAR40 <=1'h0; end
4'b0001: begin VAR33 <= 2'h0; VAR7 <= 3'h1; VAR40 <=1'h0; end
4'b0010: begin VAR33 <= 2'h0; VAR7 <= 3'h2; VAR40 <=1'h0; end
4'b0011: begin VAR33 <= 2'h0; VAR7 <= 3'h3; VAR40 <=1'h1; end
4'b0100: begin VAR33 <= 2'h1; VAR7 <= 3'h0; VAR40 <=1'h0; end
4'b0101: begin VAR33 <= 2'h1; VAR7 <= 3'h4; VAR40 <=1'h0; end
4'b0110: begin VAR33 <= 2'h1; VAR7 <= 3'h2; VAR40 <=1'h1; end
4'b0111: begin VAR33 <= 2'h1; VAR7 <= 3'h3; VAR40 <=1'h0; end
4'b1000: begin VAR33 <= 2'h2; VAR7 <= 3'h0; VAR40 <=1'h0; end
4'b1001: begin VAR33 <= 2'h2; VAR7 <= 3'h1; VAR40 <=1'h1; end
4'b1010: begin VAR33 <= 2'h2; VAR7 <= 3'h4; VAR40 <=1'h0; end
4'b1011: begin VAR33 <= 2'h2; VAR7 <= 3'h3; VAR40 <=1'h0; end
4'b1100: begin VAR33 <= 2'h3; VAR7 <= 3'h0; VAR40 <=1'h1; end
4'b1101: begin VAR33 <= 2'h3; VAR7 <= 3'h1; VAR40 <=1'h0; end
4'b1110: begin VAR33 <= 2'h3; VAR7 <= 3'h2; VAR40 <=1'h0; end
4'b1111: begin VAR33 <= 2'h3; VAR7 <= 3'h4; VAR40 <=1'h0; end
endcase
if (VAR35[0]) case (VAR33[1:0])
2'h0: VAR12[7:0] <= VAR1 [7:0];
2'h1: VAR12[7:0] <= VAR28 [7:0];
2'h2: VAR12[7:0] <= VAR2[7:0];
2'h3: VAR12[7:0] <= VAR20[7:0];
endcase
if (VAR35[0]) casex ({VAR7[2] | (VAR40 & VAR25), VAR7[1:0]})
3'h0: VAR18[7:0] <= VAR1 [7:0];
3'h1: VAR18[7:0] <= VAR28 [7:0];
3'h2: VAR18[7:0] <= VAR2[7:0];
3'h3: VAR18[7:0] <= VAR20[7:0];
3'VAR36: VAR18[7:0] <= 8'h0;
endcase
VAR8[1:0] <= {VAR8[0], ~(VAR7[2] | (VAR40 & VAR25))}; VAR24[1:0] <= {VAR24[0], ~(VAR7[2] | (VAR40 & VAR25)) & VAR23}; if (VAR35[1]) VAR30[8:0] <= {1'b0,VAR12[7:0]} - {1'b0,VAR18[7:0]};
VAR15[8:0] <= VAR9[8:0] - {1'h0, ~VAR8[1],7'h0}; VAR1[7:0] <= din [7:0];
VAR28[7:0] <= VAR1 [7:0];
VAR10[14:0] <= {VAR10[13:0],VAR28[0]};
VAR39[14:0] <= {VAR39[13:0],VAR28[1]};
VAR27[14:0] <= {VAR27[13:0],VAR28[2]};
VAR13[14:0] <= {VAR13[13:0],VAR28[3]};
VAR34[14:0] <= {VAR34[13:0],VAR28[4]};
VAR3[14:0] <= {VAR3[13:0],VAR28[5]};
VAR4[14:0] <= {VAR4[13:0],VAR28[6]};
VAR32[14:0] <= {VAR32[13:0],VAR28[7]};
VAR20[7:0] <= VAR2 [7:0];
end
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.behavioral.pp.v
| 1,784 |
module MODULE1( VAR4, VAR1, VAR12, VAR11, VAR9 );
input VAR1, VAR4;
inout VAR11, VAR9;
output VAR12;
reg VAR3;
VAR8 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR12(VAR12),.VAR11(VAR11),.VAR9(VAR9),.VAR3(VAR3));
VAR8 VAR13(.VAR4(VAR4),.VAR1(VAR1),.VAR12(VAR12),.VAR11(VAR11),.VAR9(VAR9),.VAR3(VAR3));
not VAR5(VAR7,VAR1);
buf VAR10(VAR6,VAR1);
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_reset.v
| 4,353 |
if (VAR6 && VAR11==VAR13) \
begin: VAR5 \
VAR12 VAR10(.VAR1 \
,.VAR9 \
,.VAR2(~VAR8) \
,.VAR3); \
end
module MODULE1 #(VAR11=-1, VAR6=1)
(input VAR1
,input VAR8
,input [VAR11-1:0] VAR9
,output [VAR11-1:0] VAR3
);
else VAR4(89)
else VAR4(88)
else VAR4(87)
else VAR4(86)
else VAR4(85)
else VAR4(84)
else VAR4(83)
else VAR4(82)
else VAR4(81)
else VAR4(80)
else VAR4(79)
else VAR4(78)
else VAR4(77)
else VAR4(76)
else VAR4(75)
else VAR4(74)
else VAR4(73)
else VAR4(72)
else VAR4(71)
else VAR4(70)
else VAR4(69)
else VAR4(68)
else VAR4(67)
else VAR4(66)
else VAR4(65)
else VAR4(64)
else VAR4(63)
else VAR4(62)
else VAR4(61)
else VAR4(60)
else VAR4(59)
else VAR4(58)
else VAR4(57)
else VAR4(56)
else VAR4(55)
else VAR4(54)
else VAR4(53)
else VAR4(52)
else VAR4(51)
else VAR4(50)
else VAR4(49)
else VAR4(48)
else VAR4(47)
else VAR4(46)
else VAR4(45)
else VAR4(44)
else VAR4(43)
else VAR4(42)
else VAR4(41)
else VAR4(40)
else VAR4(39)
else VAR4(38)
else VAR4(37)
else VAR4(36)
else VAR4(35)
else VAR4(34)
else VAR4(33)
else VAR4(32)
else VAR4(31)
else VAR4(30)
else VAR4(29)
else VAR4(28)
else VAR4(27)
else VAR4(26)
else VAR4(25)
else VAR4(24)
else VAR4(23)
else VAR4(22)
else VAR4(21)
else VAR4(20)
else VAR4(19)
else VAR4(18)
else VAR4(17)
else VAR4(16)
else VAR4(15)
else VAR4(14)
else VAR4(13)
else VAR4(12)
else VAR4(11)
else VAR4(10)
else VAR4(9)
else VAR4(8)
else VAR4(7)
else VAR4(6)
else VAR4(5)
else VAR4(4)
else VAR4(3)
else
begin: VAR14
reg [VAR11-1:0] VAR7;
assign VAR3 = VAR7;
always @(posedge VAR1)
begin
if (VAR8)
VAR7 <= VAR11 ' (0);
end
else
VAR7 <= VAR9;
end
end
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.v
| 2,030 |
module MODULE1 (
VAR7 ,
VAR2 ,
VAR6,
VAR4,
VAR3 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR3 ;
input VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR6;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.blackbox.v
| 1,305 |
module MODULE1 (
VAR5,
VAR6,
VAR4
);
output VAR5;
input [15:0] VAR6;
input [15:0] VAR4;
supply1 VAR2;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
hoglet67/CoPro6502
|
src/m32632/example_mods.v
| 10,516 |
module MODULE1( VAR5, VAR15, VAR19, VAR23, VAR9, VAR10, VAR26, VAR7, VAR24,
VAR14, VAR8, VAR2, VAR3, VAR22 );
input VAR5;
input VAR15;
input VAR23,VAR9;
input [31:28] VAR10;
input [3:0] VAR26;
input [31:0] VAR2;
input [7:0] VAR8;
input [31:0] VAR3;
output reg [31:0] VAR7;
output reg VAR19;
output reg VAR22;
output VAR24;
output VAR14;
reg VAR20;
reg [3:0] VAR27;
always @(posedge VAR5) VAR20 <= VAR9 & ~VAR20;
assign VAR24 = VAR23 | VAR20;
always @(VAR10 or VAR2 or VAR8 or VAR3)
casex({VAR10})
4'VAR12 : VAR7 = VAR2; 4'b0010 : VAR7 = {24'd0,VAR8};
4'b0011 : VAR7 = VAR3;
default : VAR7 = 32'VAR1;
endcase
assign VAR14 = VAR23 & (VAR10 == 4'h2) & VAR26[0];
always @(posedge VAR5 or negedge VAR15)
if (!VAR15) VAR27 <= 4'h0;
else VAR27 <= VAR27 + 4'h1;
always @(posedge VAR5 or negedge VAR15)
if (!VAR15) VAR19 <= 1'b0;
else
if (VAR27 == 4'hF) VAR19 <= 1'b1;
always @(posedge VAR5) VAR22 <= (VAR22 | (VAR9 & (VAR10 == 4'h1))) & VAR19;
endmodule
module MODULE4( VAR5, VAR6, VAR8);
parameter VAR25 = 7;
input VAR5;
input [VAR25:0] VAR6;
output reg [VAR25:0] VAR8;
reg [VAR25:0] VAR11;
always @(posedge VAR5)
begin
VAR11 <= VAR6;
VAR8 <= VAR11;
end
endmodule
module MODULE2( VAR5, VAR14, VAR16, VAR17);
parameter VAR13 = 7;
input VAR5;
input VAR14;
input [31:0] VAR16;
output reg [VAR13:0] VAR17;
always @(posedge VAR5) if (VAR14) VAR17 <= VAR16[VAR13:0];
endmodule
module MODULE3( VAR5, VAR18, VAR21);
input VAR5;
input [9:2] VAR18;
output reg [31:0] VAR21;
reg [31:0] VAR4 [0:255];
begin
begin
begin
|
gpl-3.0
|
UCR-CS179-SUMMER2014/NES_FPGA
|
source/NES_FPGA/nios_system/synthesis/submodules/nios_system_jtag_uart.v
| 23,341 |
module MODULE2 (
clk,
VAR63,
VAR4,
valid
)
;
input clk;
input [ 7: 0] VAR63;
input VAR4;
input valid;
reg [31:0] VAR76; VAR58 VAR76 =
always @(posedge clk) begin
if (valid && VAR4) begin
("%VAR62", ((VAR63 == 8'hd) ? 8'ha : VAR63));
VAR7 (VAR76);
end
end
endmodule
module MODULE5 (
clk,
VAR52,
VAR12,
VAR46,
VAR27,
VAR31,
VAR67
)
;
output VAR46;
output [ 7: 0] VAR27;
output VAR31;
output [ 5: 0] VAR67;
input clk;
input [ 7: 0] VAR52;
input VAR12;
wire VAR46;
wire [ 7: 0] VAR27;
wire VAR31;
wire [ 5: 0] VAR67;
MODULE2 MODULE4
(
.clk (clk),
.VAR63 (VAR52),
.VAR4 (VAR12),
.valid (VAR12)
);
assign VAR67 = {6{1'b0}};
assign VAR27 = {8{1'b0}};
assign VAR46 = 1'b0;
assign VAR31 = 1'b1;
endmodule
module MODULE3 (
clk,
VAR66,
VAR52,
VAR12,
VAR73,
VAR46,
VAR27,
VAR31,
VAR67
)
;
output VAR46;
output [ 7: 0] VAR27;
output VAR31;
output [ 5: 0] VAR67;
input clk;
input VAR66;
input [ 7: 0] VAR52;
input VAR12;
input VAR73;
wire VAR46;
wire [ 7: 0] VAR27;
wire VAR31;
wire [ 5: 0] VAR67;
MODULE5 MODULE5
(
.clk (clk),
.VAR46 (VAR46),
.VAR52 (VAR52),
.VAR12 (VAR12),
.VAR27 (VAR27),
.VAR31 (VAR31),
.VAR67 (VAR67)
);
endmodule
module MODULE6 (
clk,
VAR41,
VAR61,
VAR59,
VAR80,
VAR2,
VAR39
)
;
parameter VAR79 = 100;
output VAR59;
output [ 31: 0] VAR80;
output [ 7: 0] VAR2;
output VAR39;
input clk;
input VAR41;
input VAR61;
reg [ 11: 0] address;
reg VAR55;
reg VAR20;
reg VAR68;
reg VAR6;
reg VAR21;
reg VAR60;
reg VAR47;
reg VAR28;
reg VAR3;
reg [ 7: 0] VAR74 [2047: 0];
reg [ 31: 0] VAR13 [ 1: 0];
reg VAR59;
wire [ 31: 0] VAR80;
reg VAR78;
wire [ 7: 0] VAR2;
wire VAR39;
assign VAR2 = VAR74[address];
always @(posedge clk or negedge VAR61)
begin
if (VAR61 == 0)
begin
VAR55 <= 0;
VAR20 <= 0;
VAR68 <= 0;
VAR6 <= 0;
VAR21 <= 0;
VAR60 <= 0;
VAR47 <= 0;
VAR28 <= 0;
VAR3 <= 0;
VAR59 <= 0;
end
else
begin
VAR55 <= VAR78;
VAR20 <= VAR55;
VAR68 <= VAR20;
VAR6 <= VAR68;
VAR21 <= VAR6;
VAR60 <= VAR21;
VAR47 <= VAR60;
VAR28 <= VAR47;
VAR3 <= VAR28;
VAR59 <= VAR3;
end
end
assign VAR80 = VAR13[1];
reg VAR69;
reg [31:0] VAR37;
reg [31:0] VAR32;
wire VAR17 = 1'b0 ; assign VAR39 = (address < VAR13[1]);
VAR58 VAR37 = VAR79;
always @(posedge clk or negedge VAR61) begin
if (VAR61 !== 1) begin
VAR69 <= 0;
end else begin
VAR69 <= VAR39;
end
end
always @(posedge clk or negedge VAR61) begin
if (VAR61 !== 1) begin address <= 0;
VAR74[0] <= 0;
VAR13[0] <= 0;
VAR13[1] <= 0;
VAR78 <= 0;
end else begin VAR78 <= 0;
if (VAR41 && VAR39) address <= address + 1;
if (VAR13[0] && !VAR39 && VAR69) begin
if (VAR17) begin
VAR32 =
VAR45 (VAR32, "0");
end else begin
wait (!VAR61);
end
end if (VAR37 < VAR79) begin VAR37 = VAR37 + 1;
end else begin VAR37 = 0;
if (VAR32) begin
end
if (VAR13[0] && !VAR39) begin
VAR13[1] <= VAR13[0];
address <= 0;
VAR78 <= -1;
end end end end
endmodule
module MODULE1 (
clk,
VAR44,
VAR54,
VAR57,
VAR81,
VAR83,
VAR64
)
;
output VAR57;
output [ 7: 0] VAR81;
output VAR83;
output [ 5: 0] VAR64;
input clk;
input VAR44;
input VAR54;
reg [ 31: 0] VAR15;
wire VAR57;
reg VAR35;
wire [ 7: 0] VAR81;
wire VAR59;
wire [ 31: 0] VAR80;
wire [ 6: 0] VAR56;
wire VAR83;
wire [ 5: 0] VAR64;
wire VAR39;
MODULE6 MODULE6
(
.clk (clk),
.VAR41 (VAR35),
.VAR59 (VAR59),
.VAR80 (VAR80),
.VAR2 (VAR81),
.VAR61 (VAR54),
.VAR39 (VAR39)
);
always @(posedge clk or negedge VAR54)
begin
if (VAR54 == 0)
begin
VAR15 <= 32'h0;
VAR35 <= 1'b0;
end
else
begin
VAR35 <= VAR44;
if (VAR35)
VAR15 <= VAR15 - 1'b1;
if (VAR59)
VAR15 <= VAR80;
end
end
assign VAR57 = VAR15 == 32'b0;
assign VAR83 = VAR15 > 7'h40;
assign VAR56 = (VAR83) ? 7'h40 : VAR15;
assign VAR64 = VAR56[5 : 0];
endmodule
module MODULE7 (
clk,
VAR66,
VAR44,
VAR54,
VAR77,
VAR18,
VAR57,
VAR81,
VAR83,
VAR64
)
;
output VAR57;
output [ 7: 0] VAR81;
output VAR83;
output [ 5: 0] VAR64;
input clk;
input VAR66;
input VAR44;
input VAR54;
input [ 7: 0] VAR77;
input VAR18;
wire VAR57;
wire [ 7: 0] VAR81;
wire VAR83;
wire [ 5: 0] VAR64;
MODULE1 MODULE1
(
.clk (clk),
.VAR57 (VAR57),
.VAR44 (VAR44),
.VAR81 (VAR81),
.VAR83 (VAR83),
.VAR64 (VAR64),
.VAR54 (VAR54)
);
endmodule
module MODULE4 (
VAR30,
VAR36,
VAR72,
VAR51,
VAR65,
clk,
VAR54,
VAR29,
VAR84,
VAR9,
VAR34,
VAR43
)
;
output VAR29;
output [ 31: 0] VAR84;
output VAR9;
output VAR34;
output VAR43;
input VAR30;
input VAR36;
input VAR72;
input VAR51;
input [ 31: 0] VAR65;
input clk;
input VAR54;
reg VAR23;
wire VAR11;
wire VAR29;
wire [ 31: 0] VAR84;
reg VAR9;
reg VAR34;
reg VAR70;
reg VAR40;
wire VAR57;
wire VAR46;
wire VAR66;
wire VAR44;
wire [ 7: 0] VAR81;
wire [ 7: 0] VAR52;
reg VAR12;
reg VAR8;
reg VAR16;
wire VAR1;
wire VAR24;
reg VAR10;
wire [ 7: 0] VAR27;
wire VAR5;
reg VAR25;
wire VAR73;
reg VAR50;
reg VAR43;
wire VAR83;
wire [ 5: 0] VAR64;
reg VAR26;
reg VAR33;
reg VAR48;
reg VAR71;
reg VAR14;
wire [ 7: 0] VAR77;
reg VAR75;
wire VAR53;
wire VAR22;
wire VAR31;
wire [ 5: 0] VAR67;
reg VAR49;
wire VAR18;
assign VAR73 = VAR5 & ~VAR31;
assign VAR18 = VAR53 & ~VAR83;
assign VAR66 = ~VAR54;
MODULE3 MODULE3
(
.clk (clk),
.VAR46 (VAR46),
.VAR66 (VAR66),
.VAR52 (VAR52),
.VAR12 (VAR12),
.VAR27 (VAR27),
.VAR73 (VAR73),
.VAR31 (VAR31),
.VAR67 (VAR67)
);
MODULE7 MODULE2
(
.clk (clk),
.VAR57 (VAR57),
.VAR66 (VAR66),
.VAR44 (VAR44),
.VAR81 (VAR81),
.VAR83 (VAR83),
.VAR64 (VAR64),
.VAR54 (VAR54),
.VAR77 (VAR77),
.VAR18 (VAR18)
);
assign VAR1 = VAR8 & VAR70;
assign VAR24 = VAR16 & (VAR10 | VAR40);
assign VAR29 = VAR1 | VAR24;
assign VAR11 = VAR22 | VAR53;
always @(posedge clk or negedge VAR54)
begin
if (VAR54 == 0)
VAR10 <= 1'b0;
end
else if (VAR22 & ~VAR57)
VAR10 <= 1'b1;
end
else if (VAR50)
VAR10 <= 1'b0;
end
always @(posedge clk or negedge VAR54)
begin
if (VAR54 == 0)
begin
VAR25 <= 1'b0;
VAR75 <= 1'b1;
end
else
begin
VAR25 <= VAR5 & ~VAR31;
VAR75 <= ~VAR83;
end
end
always @(posedge clk or negedge VAR54)
begin
if (VAR54 == 0)
begin
VAR70 <= 1'b0;
VAR40 <= 1'b0;
VAR12 <= 1'b0;
VAR26 <= 1'b0;
VAR50 <= 1'b0;
VAR8 <= 1'b0;
VAR16 <= 1'b0;
VAR23 <= 1'b0;
VAR49 <= 1'b0;
VAR9 <= 1'b1;
end
else
begin
VAR70 <= {VAR46,VAR67} <= 8;
VAR40 <= (7'h40 - {VAR83,VAR64}) <= 8;
VAR12 <= 1'b0;
VAR50 <= 1'b0;
VAR9 <= ~(VAR36 & (~VAR51 | ~VAR72) & VAR9);
if (VAR11)
VAR23 <= 1'b1;
if (VAR36 & ~VAR51 & VAR9)
if (VAR30)
begin
VAR16 <= VAR65[0];
VAR8 <= VAR65[1];
if (VAR65[10] & ~VAR11)
VAR23 <= 1'b0;
end
else
begin
VAR12 <= ~VAR46;
VAR49 <= VAR46;
end
if (VAR36 & ~VAR72 & VAR9)
begin
if (~VAR30)
VAR26 <= ~VAR57;
VAR50 <= ~VAR30;
end
end
end
assign VAR52 = VAR65[7 : 0];
assign VAR44 = (VAR36 & ~VAR72 & VAR9 & ~VAR30) ? ~VAR57 : 1'b0;
assign VAR84 = VAR50 ? { {9{1'b0}},VAR83,VAR64,VAR26,VAR49,~VAR46,~VAR57,1'b0,VAR23,VAR1,VAR24,VAR81 } : { {9{1'b0}},(7'h40 - {VAR46,VAR67}),VAR26,VAR49,~VAR46,~VAR57,1'b0,VAR23,VAR1,VAR24,{6{1'b0}},VAR8,VAR16 };
always @(posedge clk or negedge VAR54)
begin
if (VAR54 == 0)
VAR43 <= 0;
end
else
VAR43 <= ~VAR46;
end
always @(posedge clk)
begin
VAR14 <= 1'b0;
VAR71 <= 1'b0;
VAR48 <= VAR75 ? VAR27 : {8{VAR25}};
VAR33 <= 1'b0;
end
assign VAR5 = VAR33;
assign VAR53 = VAR71;
assign VAR77 = VAR48;
assign VAR22 = VAR14;
always @(VAR57)
begin
VAR34 = ~VAR57;
end
endmodule
|
mit
|
olajep/oh
|
src/adi/hdl/library/axi_dmac/axi_register_slice.v
| 4,022 |
module MODULE1 #(
parameter VAR1 = 32,
parameter VAR8 = 0,
parameter VAR2 = 0)(
input clk,
input VAR5,
input VAR9,
output VAR3,
input [VAR1-1:0] VAR14,
output VAR10,
input VAR11,
output [VAR1-1:0] VAR17
);
wire [VAR1-1:0] VAR16;
wire VAR12;
wire VAR19;
wire [VAR1-1:0] VAR6;
wire VAR15;
wire VAR7;
generate if (VAR8 == 1) begin
reg VAR4 = 1'b0;
reg [VAR1-1:0] VAR13 = 'h00;
assign VAR7 = ~VAR4 | VAR11;
assign VAR15 = VAR4;
assign VAR6 = VAR13;
always @(posedge clk) begin
if (~VAR4 | VAR11)
VAR13 <= VAR16;
end
always @(posedge clk) begin
if (VAR5 == 1'b0) begin
VAR4 <= 1'b0;
end else begin
if (VAR12)
VAR4 <= 1'b1;
end
else if (VAR11)
VAR4 <= 1'b0;
end
end
end else begin
assign VAR6 = VAR16;
assign VAR15 = VAR12;
assign VAR7 = VAR11;
end
endgenerate
generate if (VAR2 == 1) begin
reg VAR20 = 1'b1;
reg [VAR1-1:0] VAR18 = 'h00;
assign VAR12 = ~VAR20 | VAR9;
assign VAR16 = VAR20 ? VAR14 : VAR18;
assign VAR19 = VAR20;
always @(posedge clk) begin
if (VAR20)
VAR18 <= VAR14;
end
always @(posedge clk) begin
if (VAR5 == 1'b0) begin
VAR20 <= 1'b1;
end else begin
if (VAR7)
VAR20 <= 1'b1;
end
else if (VAR9)
VAR20 <= 1'b0;
end
end
end else begin
assign VAR12 = VAR9;
assign VAR16 = VAR14;
assign VAR19 = VAR7;
end endgenerate
assign VAR17 = VAR6;
assign VAR10 = VAR15;
assign VAR3 = VAR19;
endmodule
|
mit
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.