repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/mux2/sky130_fd_sc_lp__mux2_0.v
| 2,187 |
module MODULE1 (
VAR7 ,
VAR3 ,
VAR4 ,
VAR9 ,
VAR8,
VAR10,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR8;
input VAR10;
input VAR6 ;
input VAR1 ;
VAR2 VAR5 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7 ,
VAR3,
VAR4,
VAR9
);
output VAR7 ;
input VAR3;
input VAR4;
input VAR9 ;
supply1 VAR8;
supply0 VAR10;
supply1 VAR6 ;
supply0 VAR1 ;
VAR2 VAR5 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
|
apache-2.0
|
mistryalok/Zedboard
|
learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_src_data_stream_0_V.v
| 3,017 |
module MODULE2 (
clk,
VAR27,
VAR20,
VAR21,
VAR10);
parameter VAR8 = 32'd8;
parameter VAR9 = 32'd1;
parameter VAR22 = 32'd2;
input clk;
input [VAR8-1:0] VAR27;
input VAR20;
input [VAR9-1:0] VAR21;
output [VAR8-1:0] VAR10;
reg[VAR8-1:0] VAR23 [0:VAR22-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR20)
begin
for (VAR13=0;VAR13<VAR22-1;VAR13=VAR13+1)
VAR23[VAR13+1] <= VAR23[VAR13];
VAR23[0] <= VAR27;
end
end
assign VAR10 = VAR23[VAR21];
endmodule
module MODULE1 (
clk,
reset,
VAR24,
VAR3,
VAR6,
VAR1,
VAR16,
VAR4,
VAR25,
VAR26);
parameter VAR19 = "VAR5";
parameter VAR8 = 32'd8;
parameter VAR9 = 32'd1;
parameter VAR22 = 32'd2;
input clk;
input reset;
output VAR24;
input VAR3;
input VAR6;
output[VAR8 - 1:0] VAR1;
output VAR16;
input VAR4;
input VAR25;
input[VAR8 - 1:0] VAR26;
wire[VAR9 - 1:0] VAR15 ;
wire[VAR8 - 1:0] VAR11, VAR2;
reg[VAR9:0] VAR12 = {(VAR9+1){1'b1}};
reg VAR7 = 0, VAR17 = 1;
assign VAR24 = VAR7;
assign VAR16 = VAR17;
assign VAR11 = VAR26;
assign VAR1 = VAR2;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR12 <= ~{VAR9+1{1'b0}};
VAR7 <= 1'b0;
VAR17 <= 1'b1;
end
else begin
if (((VAR6 & VAR3) == 1 & VAR7 == 1) &&
((VAR25 & VAR4) == 0 | VAR17 == 0))
begin
VAR12 <= VAR12 -1;
if (VAR12 == 0)
VAR7 <= 1'b0;
VAR17 <= 1'b1;
end
else if (((VAR6 & VAR3) == 0 | VAR7 == 0) &&
((VAR25 & VAR4) == 1 & VAR17 == 1))
begin
VAR12 <= VAR12 +1;
VAR7 <= 1'b1;
if (VAR12 == VAR22-2)
VAR17 <= 1'b0;
end
end
end
assign VAR15 = VAR12[VAR9] == 1'b0 ? VAR12[VAR9-1:0]:{VAR9{1'b0}};
assign VAR14 = (VAR25 & VAR4) & VAR17;
MODULE2
.VAR8(VAR8),
.VAR9(VAR9),
.VAR22(VAR22))
VAR18 (
.clk(clk),
.VAR27(VAR11),
.VAR20(VAR14),
.VAR21(VAR15),
.VAR10(VAR2));
endmodule
|
gpl-3.0
|
theapi/de0-nano
|
keyboard/ps2controller_0.v
| 2,389 |
module MODULE1 (
input clk,
input reset,
input VAR4,
input VAR1,
output VAR2,
output [7:0] VAR5
);
reg [9:0] buffer;
reg [3:0] counter;
reg VAR8;
reg VAR7;
reg [31:0] VAR6;
reg ready;
wire VAR3;
assign VAR5 = buffer[9:2];
assign VAR3 = buffer[1];
assign VAR2 = ready;
always @(negedge VAR4) begin
VAR8 <= 1;
VAR7 <= 0;
end
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR8 <= 0;
VAR6 <= 0;
VAR7 <= 0;
end else begin
if (VAR8) begin
if (VAR6 == 32'b1000) begin
VAR8 <= 0;
VAR6 <= 0;
VAR7 <= 1;
end else begin
VAR6 <= VAR6 + 32'b1;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
buffer <= 8'b0;
counter <= 4'd0;
end else begin
if (VAR7) begin
buffer <= {buffer[8:0], VAR1}; VAR7 <= 0;
if (counter == 4'd11) begin
counter <= 4'd0;
buffer <= 8'b0;
end else begin
counter <= counter + 4'd1;
end
end
end
end
always @(posedge clk) begin
if (counter == 4'd11) begin
if (!VAR3 == ^VAR5) begin ready <= 1'b1;
end
end else begin
ready <= 1'b0;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o22ai/sky130_fd_sc_hdll__o22ai.behavioral.pp.v
| 2,181 |
module MODULE1 (
VAR5 ,
VAR10 ,
VAR1 ,
VAR3 ,
VAR14 ,
VAR17,
VAR11,
VAR9 ,
VAR19
);
output VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR3 ;
input VAR14 ;
input VAR17;
input VAR11;
input VAR9 ;
input VAR19 ;
wire VAR13 ;
wire VAR8 ;
wire VAR12 ;
wire VAR6;
nor VAR7 (VAR13 , VAR3, VAR14 );
nor VAR18 (VAR8 , VAR10, VAR1 );
or VAR2 (VAR12 , VAR8, VAR13 );
VAR15 VAR4 (VAR6, VAR12, VAR17, VAR11);
buf VAR16 (VAR5 , VAR6 );
endmodule
|
apache-2.0
|
franmolinaca/papiGB
|
rtl/io.v
| 2,732 |
module MODULE1
(
input wire VAR25,
input wire VAR16,
input wire [5:0] VAR8, output wire [5:0] VAR10, output wire VAR1 );
wire [5:0] VAR5;
wire [5:0] VAR20;
wire [5:0] VAR2;
wire [5:0] VAR17;
wire [5:0] VAR26;
wire [5:0] VAR7;
wire [5:0] VAR15;
reg [5:0] VAR24;
assign VAR10 = VAR24;
VAR11 # ( 6 ) VAR3
(
.VAR25(VAR25),
.VAR16(VAR16),
.VAR21(1'b1),
.VAR27(VAR10),
.VAR12(VAR20)
);
VAR11 # ( 6 ) VAR9
(
.VAR25(VAR25),
.VAR16(VAR16),
.VAR21(1'b1),
.VAR27(VAR8),
.VAR12(VAR5)
);
VAR18 # ( 6 ) VAR4
(
.VAR14(VAR8),
.VAR19(VAR20),
.out(VAR2)
);
VAR18 # ( 6 ) VAR13
(
.VAR14(VAR8),
.VAR19(VAR5),
.out(VAR17)
);
VAR22 # ( 6 ) VAR23
(
.select(&VAR8),
.VAR14(VAR2),
.VAR19(VAR8),
.out(VAR7)
);
VAR22 # ( 6 ) VAR22
(
.select(&VAR2),
.VAR14(VAR7),
.VAR19(VAR8),
.out(VAR15)
);
VAR22 # ( 1 ) VAR6
(
.select(&VAR10),
.VAR14(1),
.VAR19(0),
.out(VAR1)
);
always @ ( * )
begin
case (VAR15)
6'b101110, 6'b101101, 6'b101011, 6'b100111, 6'b011110, 6'b011101, 6'b011011, 6'b010111:
begin
VAR24 <= VAR15;
if (&VAR17 == 0)
VAR24 <= VAR15;
end
else
VAR24 <= VAR20;
end
6'b011111,6'b101111:
begin
VAR24 <= VAR15;
if (&VAR17 == 0)
VAR24 <= {VAR15[5:4],VAR20[3:0]};
end
else
VAR24 <= VAR20;
end
6'b111110,6'b111101,6'b111011,6'b110111:
begin
VAR24 <= VAR15;
if (&VAR17 == 0)
VAR24 <= {VAR20[5:4],VAR15[3:0]};
end
else
VAR24 <= VAR20;
end
default:
begin
VAR24 <= 6'b111111;
end
endcase
end
endmodule
|
gpl-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.behavioral.v
| 3,306 |
module MODULE1( VAR7, VAR8, VAR6, VAR4, VAR3, VAR9 );
input VAR3, VAR9, VAR4, VAR6, VAR8;
output VAR7;
VAR1 VAR5(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9));
VAR1 VAR2(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3_1.v
| 2,135 |
module MODULE1 (
VAR1 ,
VAR8 ,
VAR7,
VAR2,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR8 ;
input VAR7;
input VAR2;
input VAR3 ;
input VAR4 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1,
VAR8
);
output VAR1;
input VAR8;
supply1 VAR7;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
GSejas/Karatsuba_FPU
|
FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/FPU_Add_Subtract_Function.v
| 12,654 |
module MODULE1
wire [VAR20-1:0] VAR9;
assign VAR9 = ~VAR8;
VAR13 #(.VAR20(VAR20),.VAR11(VAR11)) VAR16 (
.clk(clk),
.rst(VAR6),
.VAR36(VAR19),
.VAR38(VAR9),
.VAR21(VAR17)
);
VAR28 VAR25(
.clk(clk),
.VAR15(VAR10[1:0]),
.VAR37(VAR34),
.VAR31(VAR7),
.VAR29(VAR5)
);
VAR1 #(.VAR14(VAR14),.VAR32(VAR32),.VAR23(VAR23)) VAR2(
.clk(clk),
.rst(VAR6),
.VAR36(VAR35),
.VAR18(VAR24),
.VAR22(VAR4),
.VAR27(VAR7),
.VAR30(VAR26),
.VAR12(VAR10[VAR20-2:2]),
.VAR33(VAR3)
);
endmodule
|
gpl-3.0
|
alanachtenberg/CSCE-350
|
Lab6/lab6_5mux.v
| 1,473 |
module MODULE1(VAR4, VAR15, VAR6);
output VAR4; reg VAR4;
input [3:0] VAR15; input [1:0] VAR6;
always @ (VAR15 or VAR6)
case (VAR6)
2'b00: VAR4=VAR15[0];
2'b01: VAR4=VAR15[1];
2'b10: VAR4=VAR15[2];
2'b11: VAR4=VAR15[3];
endcase
endmodule
module MODULE2(VAR7, VAR2,VAR8,VAR1,VAR12);
input VAR8, VAR1;
input VAR12;
output VAR7;
output VAR2;
reg [3:0] VAR16, VAR13;
reg [1:0] VAR11,VAR5;
always @ (VAR8 or VAR1 or VAR12) begin
VAR16[0]=VAR8;
VAR16[1]=~VAR8;
VAR16[2]=~VAR8;
VAR16[3]=VAR8;
VAR11[0]=VAR12;
VAR11[1]=VAR1;
VAR13[0]=1'b0;
VAR13[1]=VAR8;
VAR13[2]=VAR8;
VAR13[3]=1'b1;
VAR5[0]=VAR12;
VAR5[1]=VAR1;
end
MODULE1 MODULE1(VAR7, VAR16, VAR11);
MODULE1 MODULE2(VAR2, VAR13, VAR11);
endmodule
module MODULE3();
reg VAR3, VAR14, VAR10;
wire VAR7, VAR2;
|
gpl-2.0
|
mfkiwl/parallella-platform
|
hdl/pulse2pulse.v
| 1,697 |
module MODULE1(
out,
VAR1, VAR7, in, reset
);
input VAR1;
input VAR7;
input in;
output out;
input reset;
wire VAR6;
wire VAR5;
VAR2 VAR2(
.out (VAR6),
.clk (VAR1),
.in (in),
.reset (reset));
VAR3 #(1) VAR3(
.out (VAR5),
.in (VAR6),
.clk (VAR7),
.reset (reset));
VAR4 VAR4(
.out (out),
.clk (VAR7),
.in (VAR5),
.reset (reset));
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/xor3/sky130_fd_sc_hdll__xor3_4.v
| 2,215 |
module MODULE1 (
VAR2 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR10,
VAR7,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR10;
input VAR7;
input VAR4 ;
input VAR8 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2,
VAR5,
VAR1,
VAR3
);
output VAR2;
input VAR5;
input VAR1;
input VAR3;
supply1 VAR10;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR8 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.behavioral.pp.v
| 1,244 |
module MODULE1( VAR1, VAR2, VAR5, VAR3, VAR7 );
input VAR2, VAR1;
inout VAR3, VAR7;
output VAR5;
VAR6 VAR8(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7));
VAR6 VAR4(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7));
|
apache-2.0
|
johan92/altera_opencl_sandbox
|
vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_hps.v
| 16,152 |
module MODULE1 #(
parameter VAR69 = 0,
parameter VAR79 = 0
) (
output wire VAR34, input wire VAR6, output wire [11:0] VAR23, output wire [20:0] VAR85, output wire [3:0] VAR58, output wire [2:0] VAR77, output wire [1:0] VAR56, output wire [1:0] VAR71, output wire [3:0] VAR48, output wire [2:0] VAR36, output wire VAR32, input wire VAR25, output wire [11:0] VAR54, output wire [31:0] VAR3, output wire [3:0] VAR91, output wire VAR86, output wire VAR30, input wire VAR57, input wire [11:0] VAR80, input wire [1:0] VAR82, input wire VAR42, output wire VAR73, output wire [11:0] VAR27, output wire [20:0] VAR70, output wire [3:0] VAR39, output wire [2:0] VAR4, output wire [1:0] VAR41, output wire [1:0] VAR8, output wire [3:0] VAR93, output wire [2:0] VAR1, output wire VAR67, input wire VAR12, input wire [11:0] VAR65, input wire [31:0] VAR28, input wire [1:0] VAR63, input wire VAR16, input wire VAR14, output wire VAR22, input wire [26:0] VAR52, input wire [7:0] VAR26, output wire VAR2, output wire [255:0] VAR60, output wire VAR19, input wire VAR59, input wire [255:0] VAR13, input wire [31:0] VAR92, input wire VAR88, input wire VAR61, input wire [31:0] VAR75, input wire [31:0] VAR17, output wire [14:0] VAR5, output wire [2:0] VAR33, output wire VAR55, output wire VAR31, output wire VAR9, output wire VAR10, output wire VAR35, output wire VAR51, output wire VAR64, output wire VAR53, inout wire [31:0] VAR40, inout wire [3:0] VAR38, inout wire [3:0] VAR11, output wire VAR78, output wire [3:0] VAR81, input wire VAR43, output wire VAR68, output wire VAR21, output wire VAR83, output wire VAR87, output wire VAR20, input wire VAR50, inout wire VAR62, output wire VAR84, input wire VAR90, output wire VAR74, input wire VAR49, input wire VAR24, input wire VAR18, input wire VAR44, inout wire VAR15, inout wire VAR46, inout wire VAR37, output wire VAR7, inout wire VAR45, inout wire VAR47, input wire VAR76, output wire VAR29, inout wire VAR72, inout wire VAR66, inout wire VAR89 );
generate
if (VAR69 != 0)
begin
begin
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a22oi/sky130_fd_sc_hdll__a22oi.functional.pp.v
| 2,186 |
module MODULE1 (
VAR5 ,
VAR7 ,
VAR8 ,
VAR4 ,
VAR13 ,
VAR12,
VAR1,
VAR19 ,
VAR18
);
output VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR13 ;
input VAR12;
input VAR1;
input VAR19 ;
input VAR18 ;
wire VAR2 ;
wire VAR17 ;
wire VAR6 ;
wire VAR3;
nand VAR9 (VAR2 , VAR8, VAR7 );
nand VAR16 (VAR17 , VAR13, VAR4 );
and VAR10 (VAR6 , VAR2, VAR17 );
VAR11 VAR14 (VAR3, VAR6, VAR12, VAR1);
buf VAR15 (VAR5 , VAR3 );
endmodule
|
apache-2.0
|
sergev/vak-opensource
|
hardware/s3esk-openrisc/or1200/or1200_ic_top.v
| 10,356 |
module MODULE1(
clk, rst,
VAR17, VAR73, VAR68, VAR57, VAR47, VAR39, VAR10,
VAR35, VAR30, VAR8,
VAR56,
VAR32, VAR13, VAR71,
VAR2, VAR49,
VAR1, VAR24, VAR65, VAR19, VAR46,
VAR3, VAR21, VAR40,
VAR60, VAR43, VAR62
);
parameter VAR53 = VAR69;
input clk;
input rst;
output [VAR53-1:0] VAR17;
output [31:0] VAR73;
output VAR68;
output VAR57;
output VAR47;
output [3:0] VAR39;
output VAR10;
input [VAR53-1:0] VAR35;
input VAR30;
input VAR8;
input VAR56;
input [31:0] VAR32;
input VAR13;
input VAR71;
input [3:0] VAR2;
input [3:0] VAR49;
output [VAR53-1:0] VAR1;
output VAR24;
output VAR65;
output VAR19;
output [3:0] VAR46;
input VAR3;
input [VAR44 - 1:0] VAR40;
output VAR21;
input VAR60;
input VAR43;
input [31:0] VAR62;
wire VAR52;
wire [VAR5-2:0] VAR41;
wire [VAR53-1:0] VAR7;
wire [VAR53-1:0] VAR72;
wire [31:0] VAR28;
wire [3:0] VAR61;
wire VAR15;
wire [31:0] VAR9;
wire VAR22;
reg VAR67;
wire [VAR25:VAR33] VAR6;
wire VAR31;
wire VAR51;
wire VAR27;
wire VAR18;
wire VAR58;
wire VAR64;
wire VAR37;
wire VAR29;
wire VAR20;
wire VAR50;
wire VAR26 = VAR3;
wire VAR38 = VAR20;
assign VAR21 = VAR50;
assign VAR73 = VAR9;
assign VAR27 = VAR60 & VAR43;
assign VAR15 = VAR29 | VAR27;
assign VAR6 = VAR27 ? VAR62[VAR25:VAR33] : VAR9[VAR25:VAR33];
assign VAR31 = VAR27 | VAR56;
assign VAR51 = ~VAR27;
assign VAR17 = 32'h00000000;
assign VAR68 = (VAR56) ? VAR22 : VAR13;
assign VAR57 = (VAR56) ? VAR22 : VAR13;
assign VAR47 = 1'b0;
assign VAR39 = (VAR56 & VAR22) ? 4'b1111 : VAR2;
assign VAR10 = (VAR56) ? VAR37 : 1'b0;
assign VAR65 = ~VAR24 & ~VAR19;
assign VAR46 = VAR19 ? VAR54 : VAR49;
assign VAR24 = VAR56 ? (VAR18 | VAR58) : VAR30;
assign VAR19 = VAR56 ? VAR64 : VAR8;
assign VAR9 = (VAR22) ? VAR28 : VAR32;
assign VAR7 = VAR35;
assign VAR1 = VAR58 | !VAR56 ? VAR35 : VAR72;
always @(VAR41 or VAR28 or VAR52) begin
if ((VAR41 != VAR28[31:VAR16]) || !VAR52)
VAR67 = 1'b1;
end
else
VAR67 = 1'b0;
end
VAR23 VAR23(
.clk(clk),
.rst(rst),
.VAR56(VAR56),
.VAR13(VAR13),
.VAR71(VAR71),
.VAR67(VAR67),
.VAR14(VAR30),
.VAR55(VAR8),
.VAR42(VAR32),
.VAR28(VAR28),
.VAR61(VAR61),
.VAR63(VAR22),
.VAR45(VAR18),
.VAR34(VAR58),
.VAR70(VAR64),
.VAR4(VAR37),
.VAR66(VAR29)
);
VAR12 VAR12(
.clk(clk),
.rst(rst),
.VAR3(VAR26),
.VAR21(VAR20),
.VAR40(VAR40),
.addr(VAR9[VAR25:2]),
.en(VAR56),
.VAR11(VAR61),
.VAR48(VAR7),
.VAR59(VAR72)
);
VAR36 VAR36(
.clk(clk),
.rst(rst),
.VAR3(VAR38),
.VAR21(VAR50),
.VAR40(VAR40),
.addr(VAR6),
.en(VAR31),
.VAR11(VAR15),
.VAR48({VAR9[31:VAR16], VAR51}),
.VAR52(VAR52),
.VAR41(VAR41)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nor3b/sky130_fd_sc_lp__nor3b_4.v
| 2,254 |
module MODULE2 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR9,
VAR6,
VAR8 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR9;
input VAR6;
input VAR8 ;
input VAR1 ;
VAR10 VAR3 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2;
supply1 VAR9;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR1 ;
VAR10 VAR3 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
jeremyherbert/real_time_stdev
|
sqrt_remainder/hdl/sqrt_remainder.v
| 4,013 |
module MODULE1
parameter VAR5 = 8,
parameter VAR8 = 3
)
(
input wire [VAR13-1:0] VAR22,
input wire [VAR1-1:0] VAR7,
input wire [(VAR21-1 + VAR23):0] VAR11,
output reg [VAR3-1:0] VAR18,
output reg signed [VAR20-1:0] VAR4,
output reg [VAR2-1:0] VAR12,
input wire reset,
input wire clk
);
reg VAR19;
wire signed [VAR20-1:0] VAR17;
assign VAR17 = {
VAR7[VAR1-2:0], VAR22[{VAR8, 1'b1}], VAR22[{VAR8, 1'b0}] };
wire signed [VAR20-1:0] VAR16;
wire signed [VAR20-1:0] VAR10;
assign VAR16 = {VAR11, 2'b01};
assign VAR10 = {VAR11, 2'b11};
reg signed [VAR20-1:0] VAR15;
reg [VAR13-1:0] VAR14;
reg [(VAR21-1 + VAR23):0] VAR6;
always @(posedge clk) begin
if (VAR7[VAR1-1] == 1'b0) begin VAR15 <= VAR17 - VAR16;
end else begin
VAR15 <= VAR17 + VAR10;
end
VAR4 <= VAR15;
VAR14 <= VAR22[(VAR3-1 + VAR9):0];
VAR18 <= VAR14;
VAR6 <= VAR11;
if (VAR15[VAR20-1] != 1'b1) begin VAR12 <= {VAR6, 1'b1};
end else begin
VAR12 <= {VAR6, 1'b0};
if (VAR9) VAR4 <= VAR15 + {VAR6, 2'b01};
end
end
endmodule
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_chbond_count_dec.v
| 2,629 |
module MODULE1 (
VAR2,
VAR1,
VAR4
);
parameter VAR3 = 6'b100111;
input [5:0] VAR2;
output VAR1;
input VAR4;
reg VAR1;
always @(posedge VAR4)
VAR1 <= (VAR2 == VAR3);
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o22a/sky130_fd_sc_hs__o22a.pp.blackbox.v
| 1,332 |
module MODULE1 (
VAR1 ,
VAR7 ,
VAR2 ,
VAR3 ,
VAR6 ,
VAR5,
VAR4
);
output VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR5;
input VAR4;
endmodule
|
apache-2.0
|
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_data_stream_2_V.v
| 2,997 |
module MODULE1 (
clk,
VAR8,
VAR3,
VAR21,
VAR10);
parameter VAR5 = 32'd8;
parameter VAR25 = 32'd1;
parameter VAR16 = 32'd2;
input clk;
input [VAR5-1:0] VAR8;
input VAR3;
input [VAR25-1:0] VAR21;
output [VAR5-1:0] VAR10;
reg[VAR5-1:0] VAR23 [0:VAR16-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR3)
begin
for (VAR11=0;VAR11<VAR16-1;VAR11=VAR11+1)
VAR23[VAR11+1] <= VAR23[VAR11];
VAR23[0] <= VAR8;
end
end
assign VAR10 = VAR23[VAR21];
endmodule
module MODULE2 (
clk,
reset,
VAR27,
VAR7,
VAR12,
VAR26,
VAR18,
VAR13,
VAR1,
VAR24);
parameter VAR15 = "VAR17";
parameter VAR5 = 32'd8;
parameter VAR25 = 32'd1;
parameter VAR16 = 32'd2;
input clk;
input reset;
output VAR27;
input VAR7;
input VAR12;
output[VAR5 - 1:0] VAR26;
output VAR18;
input VAR13;
input VAR1;
input[VAR5 - 1:0] VAR24;
wire[VAR25 - 1:0] VAR19 ;
wire[VAR5 - 1:0] VAR4, VAR2;
reg[VAR25:0] VAR9 = {(VAR25+1){1'b1}};
reg VAR14 = 0, VAR6 = 1;
assign VAR27 = VAR14;
assign VAR18 = VAR6;
assign VAR4 = VAR24;
assign VAR26 = VAR2;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR9 <= ~{VAR25+1{1'b0}};
VAR14 <= 1'b0;
VAR6 <= 1'b1;
end
else begin
if (((VAR12 & VAR7) == 1 & VAR14 == 1) &&
((VAR1 & VAR13) == 0 | VAR6 == 0))
begin
VAR9 <= VAR9 -1;
if (VAR9 == 0)
VAR14 <= 1'b0;
VAR6 <= 1'b1;
end
else if (((VAR12 & VAR7) == 0 | VAR14 == 0) &&
((VAR1 & VAR13) == 1 & VAR6 == 1))
begin
VAR9 <= VAR9 +1;
VAR14 <= 1'b1;
if (VAR9 == VAR16-2)
VAR6 <= 1'b0;
end
end
end
assign VAR19 = VAR9[VAR25] == 1'b0 ? VAR9[VAR25-1:0]:{VAR25{1'b0}};
assign VAR20 = (VAR1 & VAR13) & VAR6;
MODULE1
.VAR5(VAR5),
.VAR25(VAR25),
.VAR16(VAR16))
VAR22 (
.clk(clk),
.VAR8(VAR4),
.VAR3(VAR20),
.VAR21(VAR19),
.VAR10(VAR2));
endmodule
|
gpl-2.0
|
intelligenttoasters/CPC2.0
|
FPGA/rtl/cpc/fdc.v
| 17,750 |
module MODULE1 (
input VAR8,
input VAR67,
input VAR6,
input [7:0] VAR99,
output [7:0] VAR70,
input VAR104, input VAR71,
input VAR39,
output VAR49,
input VAR21,
input VAR59,
input [3:0] VAR1,
input [7:0] VAR100,
output [7:0] VAR54,
input VAR17,
input VAR56,
input VAR76,
output VAR38 );
parameter VAR92 = 6'd0, VAR16 = 6'd1, VAR95 = 6'd2, VAR102 = 6'd3, VAR46 = 6'd4, VAR85 = 6'd5, VAR48 = 6'd6;
parameter VAR52 = 18;
parameter VAR15 = 22;
wire VAR34, VAR22, VAR27, VAR96;
wire [4:0] VAR108;
wire [3:0] VAR88;
wire [1:0] VAR91; wire [2:0] VAR13; wire [0:VAR52-1] VAR64;
wire [7:0] VAR47;
wire VAR74, VAR80;
wire VAR75, VAR2;
wire VAR107, VAR68;
wire VAR78, VAR14;
wire [7:0] VAR45, VAR57, VAR20, VAR3;
wire VAR29 = (VAR1 == 4'd0);
wire VAR25;
reg [7:0] VAR82 = 0, VAR110 = 0, VAR28 = 0, VAR53 = 0;
reg [4:0] VAR79;
reg VAR55, VAR72;
reg [5:0] state, VAR42; reg [0:VAR52-1] VAR44;
reg [9:0] VAR103 = 0;
reg [VAR15-1:0] VAR69 = 0;
reg [4:0] VAR98;
reg [1:0] VAR65 = 0, VAR50 = 0;
reg [1:0] VAR7 = 0, VAR86 = 0;
reg [3:0] VAR63 = 0, VAR40 = 0;
reg VAR66 = 0; reg VAR73 = 0; wire VAR101 = (VAR66 != VAR73);
reg [1:0] VAR84 = 0;
always @(posedge VAR8) VAR84 <= {VAR84[0],VAR107};
reg [7:0] VAR23 = 8'VAR105, VAR109 = 8'd0, VAR43 = 8'd0, VAR26 = 8'd0, VAR60 = 8'h0, VAR97 = 8'h0, VAR35 = 8'h0, VAR61 = 8'he5, VAR33 = 0, VAR94 = 0;
reg [7:0] VAR12 = 0;
reg [7:0] VAR93 = 0, VAR83 = 0, VAR32 = 0, VAR5 = 0;
function [0:VAR52-1] VAR31 (
input [4:0] VAR87
);
case( VAR87 )
5'h02: VAR31 = { 1'b0, 5'd8, 1'b1, 1'b0, 4'd7, 1'b1, 3'd0, 2'd0 }; 5'h03: VAR31 = { 1'b0, 5'd2, 1'b0, 1'b0, 4'd0, 1'b0, 3'd1, 2'd0 };
5'h04: VAR31 = { 1'b0, 5'd1, 1'b0, 1'b0, 4'd1, 1'b0, 3'd2, 2'd1 };
5'h05: VAR31 = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h06: VAR31 = { 1'b0, 5'd8, 1'b1, 1'b0, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h07: VAR31 = { 1'b0, 5'd1, 1'b0, 1'b0, 4'd0, 1'b0, 3'd2, 2'd0 };
5'h08: VAR31 = { 1'b0, 5'd0, 1'b0, 1'b0, 4'd2, 1'b0, 3'd7, 2'd3 };
5'h09: VAR31 = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h0a: VAR31 = { 1'b0, 5'd1, 1'b0, 1'b0, 4'd7, 1'b0, 3'd2, 2'd2 };
5'h0c: VAR31 = { 1'b0, 5'd8, 1'b1, 1'b0, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h0d: VAR31 = { 1'b0, 5'd5, 1'b0, 1'b1, 4'd7, 1'b0, 3'd4, 2'd2 };
5'h0f: VAR31 = { 1'b0, 5'd2, 1'b0, 1'b0, 4'd0, 1'b0, 3'd5, 2'd0 };
5'h11: VAR31 = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b0, 3'd3, 2'd2 };
5'h19: VAR31 = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b0, 3'd3, 2'd2 };
5'h1d: VAR31 = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b0, 3'd3, 2'd2 };
5'h1f: VAR31 = { 1'b1, 5'd0, 1'b0, 1'b0, 4'd1, 1'b0, 3'd7, 2'd0 }; default: VAR31 = ((2**VAR52)-1); endcase
endfunction
function [0:31] VAR51 (
input [2:0] VAR81
);
case( VAR81 )
3'd0 : VAR51 = {4'd2, 4'd4, 4'd3, 4'hf, 4'hf, 4'd12, 4'hf, 4'hf};
3'd2 : VAR51 = {4'd2, 28'b1111111111111111111111111111};
3'd3 : VAR51 = {4'd2, 4'd4, 4'd3, 4'd5, 4'hf, 4'd6, 4'hf, 4'hf};
3'd4 : VAR51 = {4'd2, 4'hf, 4'd12, 4'hf, 4'd7, 12'b111111111111};
3'd5 : VAR51 = {4'd2, 4'd13, 24'b111111111111111111111111};
default: VAR51 = 32'hffffffff;
endcase
endfunction
function [0:27] VAR58 (
input [1:0] VAR81
);
case( VAR81 )
2'd0: VAR58 = {4'd8, 4'd9, 4'd10, 4'd04, 4'd03, 4'd12, 4'd00};
2'd1: VAR58 = {4'd11, 4'd15, 4'd15, 4'd15, 4'd15, 4'd15, 4'd15};
2'd2: VAR58 = {4'd8, 4'd9, 4'd10, 4'd04, 4'd03, 4'd6, 4'd00};
2'd3: VAR58 = {4'd8, 4'd13, 4'd15, 4'd15, 4'd15, 4'd15, 4'd15};
endcase
endfunction
task VAR36(
input [3:0] register,
input [7:0] VAR90
);
case( register )
4'd02 : VAR23 <= VAR90;
4'd03 : VAR43 <= VAR90;
4'd04 : VAR109 <= VAR90;
4'd05 : VAR35 <= VAR90;
4'd06 : VAR60 <= VAR90;
4'd07 : VAR61 <= VAR90;
4'd08 : VAR82 <= VAR90;
4'd09 : VAR110 <= VAR90;
4'd10 : VAR28 <= VAR90;
4'd11 : VAR53 <= VAR90;
4'd12 : VAR26 <= VAR90;
4'd13 : VAR97 <= VAR90;
endcase
endtask
function [7:0] VAR77(
input [3:0] register
);
case( register )
4'd00 : VAR77 = 2'd2; 4'd01 : VAR77 = VAR45;
4'd02 : VAR77 = VAR23;
4'd03 : VAR77 = VAR43;
4'd04 : VAR77 = VAR109;
4'd05 : VAR77 = VAR35;
4'd06 : VAR77 = VAR60;
4'd07 : VAR77 = VAR61;
4'd08 : VAR77 = VAR82;
4'd09 : VAR77 = VAR110;
4'd10 : VAR77 = VAR28;
4'd11 : VAR77 = VAR53;
4'd12 : VAR77 = VAR26;
4'd13 : VAR77 = VAR97;
4'd14 : VAR77 = VAR33;
default: VAR77 = 8'hff;
endcase
endfunction
function [3:0] VAR41(
input [0:31] VAR9,
input [2:0] VAR4
);
case( VAR4 )
3'd0 : VAR41 = VAR9[0:3];
3'd1 : VAR41 = VAR9[4:7];
3'd2 : VAR41 = VAR9[8:11];
3'd3 : VAR41 = VAR9[12:15];
3'd4 : VAR41 = VAR9[16:19];
3'd5 : VAR41 = VAR9[20:23];
3'd6 : VAR41 = VAR9[24:27];
3'd7 : VAR41 = VAR9[28:31];
endcase
endfunction
assign VAR70 = !VAR104 ? VAR47 :
(state == VAR102) ? ((VAR84 == 2'b11) ? 8'hff : VAR20) :
(state == VAR85) ? VAR12 :
8'hff;
assign VAR49 = (state == VAR95) && VAR101;
assign VAR64 = VAR31( VAR99[4:0] );
assign {VAR34, VAR108, VAR22, VAR27, VAR88, VAR96, VAR13, VAR91} = (state == VAR92) ? VAR64 : VAR44;
assign VAR45 = {VAR21, VAR101, VAR72, VAR79};
assign VAR47 = {
((state == VAR92) || (state == VAR16) || (state == VAR102) || (state == VAR85)),
(state == VAR85) || ((state == VAR102) & VAR22),
(state == VAR102),
(state != VAR92),
VAR63};
assign VAR74 = (VAR65 == 2'b01);
assign VAR80 = (VAR50 == 2'b01);
assign VAR75 = (VAR7 == 2'b01);
assign VAR2 = (VAR86 == 2'b01);
assign VAR54 = (VAR1 == 4'd0) ? VAR3 : VAR77(VAR1);
assign VAR25 = (VAR23[1:0] == 2'd0) ? (VAR93 == 8'd0) :
(VAR23[1:0] == 2'd1) ? (VAR83 == 8'd0) :
(VAR23[1:0] == 2'd2) ? (VAR32 == 8'd0) :
(VAR23[1:0] == 2'd3) ? (VAR5 == 8'd0) : 1'b0;
VAR37 #(
.VAR19(9), .VAR30(8)
) VAR62 (
.VAR10(~VAR67 && (state > VAR92)), .VAR18(VAR59), .VAR99(VAR100),
.VAR39(VAR2 ), .VAR106(VAR8), .VAR70(VAR20),
.VAR71(VAR74 && (state == VAR102)), .VAR24(VAR107),
.VAR11(VAR68)
);
VAR37 #(
.VAR19(9), .VAR30(8)
) VAR89 (
.VAR10(~VAR67 && (state > VAR92)), .VAR18(VAR8), .VAR99(VAR99),
.VAR39(VAR80 && (state == VAR102)),
.VAR106(VAR59), .VAR70(VAR3),
.VAR71(VAR75),
.VAR24(VAR78),
.VAR11(VAR14)
);
always @(posedge VAR8)
begin
if( VAR67 )
begin
state <= VAR92;
VAR73 <= 0;
end
else case( state )
VAR92: if ( VAR80 ) begin
VAR79 <= VAR99[4:0]; VAR55 <= VAR99[7]; VAR72 <= VAR99[5];
VAR44 <= VAR64; VAR98 <= 1'b0; if ( ~VAR34 )
begin
if( VAR108 > 0 )
begin
VAR42 <= VAR108; state <= VAR16;
end
else begin VAR42 <= VAR88; state <= VAR95; end
VAR103 <= (VAR22|VAR27) ? 10'd512 : 1'b0; VAR69 <= ((2**VAR15)-1);
end
else state <= VAR46;
end
VAR16: begin
if( VAR80 & VAR6 & VAR104) begin
VAR36( VAR41( VAR51( VAR13 ), VAR98 ), VAR99 );
if( VAR42 == 1 ) begin
if( ~VAR101 & ~VAR27 ) VAR73 <= ~VAR73; state <= VAR27 ? VAR102 : VAR95;
end
else begin
VAR42 <= VAR42 - 1'b1;
VAR98 <= VAR98 + 1'b1;
end
end
end
VAR95:
begin if( ( VAR69 == 0 ) || ~VAR101 )
begin
if( VAR22 )
begin
state <= VAR102;
end
else state <= VAR46;
end
else VAR69 <= VAR69 - 1'b1;
end
VAR102: begin
if( VAR103 == 0 ) begin
state <= VAR27 ? VAR95 : VAR46; if( ~VAR101 & VAR27 ) VAR73 <= ~VAR73; end
else if( VAR74 | VAR80 ) VAR103 <= VAR103 - 1'b1;
end
VAR46:
begin
if( VAR88 > 0 )
state <= VAR85;
end
else
state <= VAR92;
VAR42 <= (~VAR34) ? VAR88 : 1'd1; VAR98 <= 1'b0;
if( ( VAR79 == 5'h0f ) || ( VAR79 == 5'h07 ) )
begin
VAR109 <= ( VAR79[3] ) ? VAR97 : 8'd0;
VAR40 <= 1'b1;
case( VAR23[1:0] )
2'd00: begin
VAR63[0] <= 1;
if( VAR79[3] ) VAR93 <= VAR97;
end
else
VAR93 <= 8'd0;
end
2'd01: begin
VAR63[1] <= 1;
if( VAR79[3] ) VAR83 <= VAR97;
end
else
VAR83 <= 8'd0;
end
2'd02: begin
VAR63[2] <= 1;
if( VAR79[3] ) VAR32 <= VAR97;
end
else
VAR32 <= 8'd0;
end
2'd03: begin
VAR63[3] <= 1;
if( VAR79[3] ) VAR5 <= VAR97;
end
else
VAR5 <= 8'd0;
end
endcase
end
if( VAR79 == 5'h08 ) VAR63 <= 4'd0;
if( VAR79 == 5'h0a )
begin
VAR60 <= VAR94;
VAR109 <= 8'd0;
VAR43 <= 8'd0;
end
VAR82 <= {
VAR34 ? 2'b10 : VAR33[0] ? 2'b11 : VAR96 ? 2'd01 : 2'd0, (VAR40) ? 1'b1 : ((VAR79 == 5'h08)||(VAR79 == 5'h0a)) ? 1'b0 : VAR82[5],
VAR33[1],
VAR33[0],
VAR23[2:0]
};
VAR110 <= {(VAR22|VAR27), 4'd0, VAR33[2], VAR33[3], VAR33[2]};
VAR28 <= 8'd0; VAR53 <= {1'b0, VAR33[3], 1'b1, VAR25, 1'b0, VAR23[2:0]};
end
VAR85:
begin
VAR40 <= 0;
if( VAR74 ) begin
VAR12 <= VAR77( VAR41( {VAR58( VAR91 ),4'd0}, VAR98 ) );
if( VAR42 != 0 ) begin
VAR42 <= VAR42 - 1'b1;
VAR98 <= VAR98 + 1'b1;
end
end
else
if( VAR42 == 0 ) begin
state <= VAR92; end
end
default: state <= VAR92;
endcase
end
always @(posedge VAR59)
begin
if( VAR67 )
VAR66 <= 0;
end
else
if( (VAR1 == 4'd1) && VAR100[0] && VAR56 && VAR76 && VAR101 )
VAR66 <= ~VAR66;
end
always @(negedge VAR8)
begin
VAR65 <= {VAR65[0], VAR6 & VAR104 & VAR71};
VAR50 <= {VAR50[0], VAR6 & VAR104 & VAR39};
end
always @(negedge VAR59)
begin
VAR7 <= {VAR7[0], VAR76 & VAR29 & VAR17};
VAR86 <= {VAR86[0], VAR76 & VAR29 & VAR56};
end
always @(posedge VAR59)
begin
if( (VAR1 == 4'd14) && VAR56 && VAR76) VAR33 <= VAR100;
end
always @(posedge VAR59)
begin
if( (VAR1 == 4'd15) && VAR56 && VAR76) VAR94 <= VAR100;
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/fah/sky130_fd_sc_ms__fah.blackbox.v
| 1,297 |
module MODULE1 (
VAR9,
VAR8 ,
VAR7 ,
VAR1 ,
VAR5
);
output VAR9;
output VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
nikhilghanathe/HLS-for-EMTF
|
verilog/sp_mux_128to1_sel7_6_1.v
| 18,745 |
module MODULE1 #(
parameter
VAR272 = 0,
VAR288 = 1,
VAR50 = 32,
VAR299 = 32,
VAR4 = 32,
VAR125 = 32,
VAR90 = 32,
VAR87 = 32,
VAR22 = 32,
VAR242 = 32,
VAR249 = 32,
VAR207 = 32,
VAR11 = 32,
VAR54 = 32,
VAR172 = 32,
VAR328 = 32,
VAR132 = 32,
VAR38 = 32,
VAR37 = 32,
VAR106 = 32,
VAR367 = 32,
VAR8 = 32,
VAR320 = 32,
VAR312 = 32,
VAR46 = 32,
VAR282 = 32,
VAR379 = 32,
VAR346 = 32,
VAR110 = 32,
VAR224 = 32,
VAR169 = 32,
VAR195 = 32,
VAR121 = 32,
VAR81 = 32,
VAR319 = 32,
VAR298 = 32,
VAR302 = 32,
VAR233 = 32,
VAR218 = 32,
VAR149 = 32,
VAR246 = 32,
VAR277 = 32,
VAR198 = 32,
VAR10 = 32,
VAR385 = 32,
VAR268 = 32,
VAR208 = 32,
VAR338 = 32,
VAR285 = 32,
VAR157 = 32,
VAR311 = 32,
VAR18 = 32,
VAR118 = 32,
VAR103 = 32,
VAR304 = 32,
VAR205 = 32,
VAR83 = 32,
VAR108 = 32,
VAR356 = 32,
VAR102 = 32,
VAR251 = 32,
VAR342 = 32,
VAR58 = 32,
VAR43 = 32,
VAR317 = 32,
VAR189 = 32,
VAR160 = 32,
VAR343 = 32,
VAR39 = 32,
VAR128 = 32,
VAR175 = 32,
VAR82 = 32,
VAR289 = 32,
VAR156 = 32,
VAR321 = 32,
VAR258 = 32,
VAR186 = 32,
VAR124 = 32,
VAR354 = 32,
VAR2 = 32,
VAR170 = 32,
VAR115 = 32,
VAR253 = 32,
VAR62 = 32,
VAR117 = 32,
VAR33 = 32,
VAR25 = 32,
VAR309 = 32,
VAR196 = 32,
VAR261 = 32,
VAR380 = 32,
VAR12 = 32,
VAR27 = 32,
VAR290 = 32,
VAR91 = 32,
VAR197 = 32,
VAR146 = 32,
VAR336 = 32,
VAR284 = 32,
VAR104 = 32,
VAR378 = 32,
VAR368 = 32,
VAR191 = 32,
VAR353 = 32,
VAR20 = 32,
VAR97 = 32,
VAR202 = 32,
VAR99 = 32,
VAR212 = 32,
VAR203 = 32,
VAR219 = 32,
VAR47 = 32,
VAR173 = 32,
VAR76 = 32,
VAR129 = 32,
VAR150 = 32,
VAR264 = 32,
VAR19 = 32,
VAR49 = 32,
VAR68 = 32,
VAR7 = 32,
VAR201 = 32,
VAR232 = 32,
VAR69 = 32,
VAR351 = 32,
VAR247 = 32,
VAR5 = 32,
VAR3 = 32,
VAR59 = 32,
VAR16 = 32,
VAR386 = 32,
VAR221 = 32
)(
input [5 : 0] VAR55,
input [5 : 0] VAR130,
input [5 : 0] VAR279,
input [5 : 0] VAR194,
input [5 : 0] VAR322,
input [5 : 0] VAR126,
input [5 : 0] VAR256,
input [5 : 0] VAR209,
input [5 : 0] VAR120,
input [5 : 0] VAR31,
input [5 : 0] VAR227,
input [5 : 0] VAR206,
input [5 : 0] VAR332,
input [5 : 0] VAR184,
input [5 : 0] VAR266,
input [5 : 0] VAR138,
input [5 : 0] VAR259,
input [5 : 0] VAR348,
input [5 : 0] VAR276,
input [5 : 0] VAR162,
input [5 : 0] VAR107,
input [5 : 0] VAR373,
input [5 : 0] VAR152,
input [5 : 0] VAR165,
input [5 : 0] VAR217,
input [5 : 0] VAR140,
input [5 : 0] VAR383,
input [5 : 0] VAR21,
input [5 : 0] VAR229,
input [5 : 0] VAR281,
input [5 : 0] VAR72,
input [5 : 0] VAR245,
input [5 : 0] VAR200,
input [5 : 0] VAR257,
input [5 : 0] VAR318,
input [5 : 0] VAR34,
input [5 : 0] VAR85,
input [5 : 0] VAR109,
input [5 : 0] VAR254,
input [5 : 0] VAR63,
input [5 : 0] VAR315,
input [5 : 0] VAR66,
input [5 : 0] VAR57,
input [5 : 0] VAR363,
input [5 : 0] VAR101,
input [5 : 0] VAR301,
input [5 : 0] VAR286,
input [5 : 0] VAR204,
input [5 : 0] VAR240,
input [5 : 0] VAR360,
input [5 : 0] VAR28,
input [5 : 0] VAR141,
input [5 : 0] VAR345,
input [5 : 0] VAR183,
input [5 : 0] VAR142,
input [5 : 0] VAR135,
input [5 : 0] VAR29,
input [5 : 0] VAR96,
input [5 : 0] VAR52,
input [5 : 0] VAR15,
input [5 : 0] VAR151,
input [5 : 0] VAR382,
input [5 : 0] VAR95,
input [5 : 0] VAR362,
input [5 : 0] VAR131,
input [5 : 0] VAR119,
input [5 : 0] VAR340,
input [5 : 0] VAR237,
input [5 : 0] VAR78,
input [5 : 0] VAR80,
input [5 : 0] VAR316,
input [5 : 0] VAR100,
input [5 : 0] VAR238,
input [5 : 0] VAR79,
input [5 : 0] VAR325,
input [5 : 0] VAR361,
input [5 : 0] VAR372,
input [5 : 0] VAR339,
input [5 : 0] VAR75,
input [5 : 0] VAR225,
input [5 : 0] VAR148,
input [5 : 0] VAR275,
input [5 : 0] VAR1,
input [5 : 0] VAR323,
input [5 : 0] VAR94,
input [5 : 0] VAR324,
input [5 : 0] VAR214,
input [5 : 0] VAR211,
input [5 : 0] VAR352,
input [5 : 0] VAR77,
input [5 : 0] VAR376,
input [5 : 0] VAR248,
input [5 : 0] VAR262,
input [5 : 0] VAR220,
input [5 : 0] VAR271,
input [5 : 0] VAR381,
input [5 : 0] VAR213,
input [5 : 0] VAR387,
input [5 : 0] VAR210,
input [5 : 0] VAR305,
input [5 : 0] VAR161,
input [5 : 0] VAR36,
input [5 : 0] VAR9,
input [5 : 0] VAR113,
input [5 : 0] VAR294,
input [5 : 0] VAR333,
input [5 : 0] VAR185,
input [5 : 0] VAR370,
input [5 : 0] VAR228,
input [5 : 0] VAR98,
input [5 : 0] VAR215,
input [5 : 0] VAR307,
input [5 : 0] VAR145,
input [5 : 0] VAR164,
input [5 : 0] VAR241,
input [5 : 0] VAR283,
input [5 : 0] VAR349,
input [5 : 0] VAR269,
input [5 : 0] VAR291,
input [5 : 0] VAR231,
input [5 : 0] VAR111,
input [5 : 0] VAR239,
input [5 : 0] VAR236,
input [5 : 0] VAR371,
input [5 : 0] VAR41,
input [5 : 0] VAR287,
input [5 : 0] VAR64,
input [5 : 0] VAR255,
input [6 : 0] VAR139,
output [5 : 0] dout);
wire [6 : 0] sel;
wire [5 : 0] VAR347;
wire [5 : 0] VAR44;
wire [5 : 0] VAR174;
wire [5 : 0] VAR355;
wire [5 : 0] VAR274;
wire [5 : 0] VAR357;
wire [5 : 0] VAR337;
wire [5 : 0] VAR153;
wire [5 : 0] VAR92;
wire [5 : 0] VAR335;
wire [5 : 0] VAR93;
wire [5 : 0] VAR177;
wire [5 : 0] VAR51;
wire [5 : 0] VAR65;
wire [5 : 0] VAR24;
wire [5 : 0] VAR235;
wire [5 : 0] VAR6;
wire [5 : 0] VAR384;
wire [5 : 0] VAR53;
wire [5 : 0] VAR61;
wire [5 : 0] VAR181;
wire [5 : 0] VAR17;
wire [5 : 0] VAR136;
wire [5 : 0] VAR74;
wire [5 : 0] VAR168;
wire [5 : 0] VAR163;
wire [5 : 0] VAR364;
wire [5 : 0] VAR310;
wire [5 : 0] VAR216;
wire [5 : 0] VAR166;
wire [5 : 0] VAR40;
wire [5 : 0] VAR327;
wire [5 : 0] VAR35;
wire [5 : 0] VAR123;
wire [5 : 0] VAR13;
wire [5 : 0] VAR30;
wire [5 : 0] VAR147;
wire [5 : 0] VAR187;
wire [5 : 0] VAR292;
wire [5 : 0] VAR42;
wire [5 : 0] VAR267;
wire [5 : 0] VAR190;
wire [5 : 0] VAR193;
wire [5 : 0] VAR260;
wire [5 : 0] VAR296;
wire [5 : 0] VAR344;
wire [5 : 0] VAR171;
wire [5 : 0] VAR89;
wire [5 : 0] VAR278;
wire [5 : 0] VAR326;
wire [5 : 0] VAR122;
wire [5 : 0] VAR167;
wire [5 : 0] VAR388;
wire [5 : 0] VAR14;
wire [5 : 0] VAR127;
wire [5 : 0] VAR234;
wire [5 : 0] VAR300;
wire [5 : 0] VAR144;
wire [5 : 0] VAR377;
wire [5 : 0] VAR297;
wire [5 : 0] VAR230;
wire [5 : 0] VAR280;
wire [5 : 0] VAR222;
wire [5 : 0] VAR331;
wire [5 : 0] VAR329;
wire [5 : 0] VAR226;
wire [5 : 0] VAR134;
wire [5 : 0] VAR48;
wire [5 : 0] VAR116;
wire [5 : 0] VAR369;
wire [5 : 0] VAR70;
wire [5 : 0] VAR179;
wire [5 : 0] VAR23;
wire [5 : 0] VAR374;
wire [5 : 0] VAR133;
wire [5 : 0] VAR223;
wire [5 : 0] VAR60;
wire [5 : 0] VAR32;
wire [5 : 0] VAR45;
wire [5 : 0] VAR314;
wire [5 : 0] VAR293;
wire [5 : 0] VAR158;
wire [5 : 0] VAR365;
wire [5 : 0] VAR73;
wire [5 : 0] VAR366;
wire [5 : 0] VAR176;
wire [5 : 0] VAR88;
wire [5 : 0] VAR341;
wire [5 : 0] VAR56;
wire [5 : 0] VAR114;
wire [5 : 0] VAR86;
wire [5 : 0] VAR67;
wire [5 : 0] VAR159;
wire [5 : 0] VAR308;
wire [5 : 0] VAR270;
wire [5 : 0] VAR137;
wire [5 : 0] VAR154;
wire [5 : 0] VAR295;
wire [5 : 0] VAR180;
wire [5 : 0] VAR84;
wire [5 : 0] VAR359;
wire [5 : 0] VAR334;
wire [5 : 0] VAR313;
wire [5 : 0] VAR358;
wire [5 : 0] VAR244;
wire [5 : 0] VAR188;
wire [5 : 0] VAR306;
wire [5 : 0] VAR143;
wire [5 : 0] VAR252;
wire [5 : 0] VAR182;
wire [5 : 0] VAR250;
wire [5 : 0] VAR273;
wire [5 : 0] VAR178;
wire [5 : 0] VAR375;
wire [5 : 0] VAR199;
wire [5 : 0] VAR192;
wire [5 : 0] VAR263;
wire [5 : 0] VAR303;
wire [5 : 0] VAR71;
wire [5 : 0] VAR243;
wire [5 : 0] VAR26;
wire [5 : 0] VAR105;
wire [5 : 0] VAR155;
wire [5 : 0] VAR112;
wire [5 : 0] VAR350;
wire [5 : 0] VAR330;
wire [5 : 0] VAR265;
assign sel = VAR139;
assign VAR347 = (sel[0] == 0)? VAR55 : VAR130;
assign VAR44 = (sel[0] == 0)? VAR279 : VAR194;
assign VAR174 = (sel[0] == 0)? VAR322 : VAR126;
assign VAR355 = (sel[0] == 0)? VAR256 : VAR209;
assign VAR274 = (sel[0] == 0)? VAR120 : VAR31;
assign VAR357 = (sel[0] == 0)? VAR227 : VAR206;
assign VAR337 = (sel[0] == 0)? VAR332 : VAR184;
assign VAR153 = (sel[0] == 0)? VAR266 : VAR138;
assign VAR92 = (sel[0] == 0)? VAR259 : VAR348;
assign VAR335 = (sel[0] == 0)? VAR276 : VAR162;
assign VAR93 = (sel[0] == 0)? VAR107 : VAR373;
assign VAR177 = (sel[0] == 0)? VAR152 : VAR165;
assign VAR51 = (sel[0] == 0)? VAR217 : VAR140;
assign VAR65 = (sel[0] == 0)? VAR383 : VAR21;
assign VAR24 = (sel[0] == 0)? VAR229 : VAR281;
assign VAR235 = (sel[0] == 0)? VAR72 : VAR245;
assign VAR6 = (sel[0] == 0)? VAR200 : VAR257;
assign VAR384 = (sel[0] == 0)? VAR318 : VAR34;
assign VAR53 = (sel[0] == 0)? VAR85 : VAR109;
assign VAR61 = (sel[0] == 0)? VAR254 : VAR63;
assign VAR181 = (sel[0] == 0)? VAR315 : VAR66;
assign VAR17 = (sel[0] == 0)? VAR57 : VAR363;
assign VAR136 = (sel[0] == 0)? VAR101 : VAR301;
assign VAR74 = (sel[0] == 0)? VAR286 : VAR204;
assign VAR168 = (sel[0] == 0)? VAR240 : VAR360;
assign VAR163 = (sel[0] == 0)? VAR28 : VAR141;
assign VAR364 = (sel[0] == 0)? VAR345 : VAR183;
assign VAR310 = (sel[0] == 0)? VAR142 : VAR135;
assign VAR216 = (sel[0] == 0)? VAR29 : VAR96;
assign VAR166 = (sel[0] == 0)? VAR52 : VAR15;
assign VAR40 = (sel[0] == 0)? VAR151 : VAR382;
assign VAR327 = (sel[0] == 0)? VAR95 : VAR362;
assign VAR35 = (sel[0] == 0)? VAR131 : VAR119;
assign VAR123 = (sel[0] == 0)? VAR340 : VAR237;
assign VAR13 = (sel[0] == 0)? VAR78 : VAR80;
assign VAR30 = (sel[0] == 0)? VAR316 : VAR100;
assign VAR147 = (sel[0] == 0)? VAR238 : VAR79;
assign VAR187 = (sel[0] == 0)? VAR325 : VAR361;
assign VAR292 = (sel[0] == 0)? VAR372 : VAR339;
assign VAR42 = (sel[0] == 0)? VAR75 : VAR225;
assign VAR267 = (sel[0] == 0)? VAR148 : VAR275;
assign VAR190 = (sel[0] == 0)? VAR1 : VAR323;
assign VAR193 = (sel[0] == 0)? VAR94 : VAR324;
assign VAR260 = (sel[0] == 0)? VAR214 : VAR211;
assign VAR296 = (sel[0] == 0)? VAR352 : VAR77;
assign VAR344 = (sel[0] == 0)? VAR376 : VAR248;
assign VAR171 = (sel[0] == 0)? VAR262 : VAR220;
assign VAR89 = (sel[0] == 0)? VAR271 : VAR381;
assign VAR278 = (sel[0] == 0)? VAR213 : VAR387;
assign VAR326 = (sel[0] == 0)? VAR210 : VAR305;
assign VAR122 = (sel[0] == 0)? VAR161 : VAR36;
assign VAR167 = (sel[0] == 0)? VAR9 : VAR113;
assign VAR388 = (sel[0] == 0)? VAR294 : VAR333;
assign VAR14 = (sel[0] == 0)? VAR185 : VAR370;
assign VAR127 = (sel[0] == 0)? VAR228 : VAR98;
assign VAR234 = (sel[0] == 0)? VAR215 : VAR307;
assign VAR300 = (sel[0] == 0)? VAR145 : VAR164;
assign VAR144 = (sel[0] == 0)? VAR241 : VAR283;
assign VAR377 = (sel[0] == 0)? VAR349 : VAR269;
assign VAR297 = (sel[0] == 0)? VAR291 : VAR231;
assign VAR230 = (sel[0] == 0)? VAR111 : VAR239;
assign VAR280 = (sel[0] == 0)? VAR236 : VAR371;
assign VAR222 = (sel[0] == 0)? VAR41 : VAR287;
assign VAR331 = (sel[0] == 0)? VAR64 : VAR255;
assign VAR329 = (sel[1] == 0)? VAR347 : VAR44;
assign VAR226 = (sel[1] == 0)? VAR174 : VAR355;
assign VAR134 = (sel[1] == 0)? VAR274 : VAR357;
assign VAR48 = (sel[1] == 0)? VAR337 : VAR153;
assign VAR116 = (sel[1] == 0)? VAR92 : VAR335;
assign VAR369 = (sel[1] == 0)? VAR93 : VAR177;
assign VAR70 = (sel[1] == 0)? VAR51 : VAR65;
assign VAR179 = (sel[1] == 0)? VAR24 : VAR235;
assign VAR23 = (sel[1] == 0)? VAR6 : VAR384;
assign VAR374 = (sel[1] == 0)? VAR53 : VAR61;
assign VAR133 = (sel[1] == 0)? VAR181 : VAR17;
assign VAR223 = (sel[1] == 0)? VAR136 : VAR74;
assign VAR60 = (sel[1] == 0)? VAR168 : VAR163;
assign VAR32 = (sel[1] == 0)? VAR364 : VAR310;
assign VAR45 = (sel[1] == 0)? VAR216 : VAR166;
assign VAR314 = (sel[1] == 0)? VAR40 : VAR327;
assign VAR293 = (sel[1] == 0)? VAR35 : VAR123;
assign VAR158 = (sel[1] == 0)? VAR13 : VAR30;
assign VAR365 = (sel[1] == 0)? VAR147 : VAR187;
assign VAR73 = (sel[1] == 0)? VAR292 : VAR42;
assign VAR366 = (sel[1] == 0)? VAR267 : VAR190;
assign VAR176 = (sel[1] == 0)? VAR193 : VAR260;
assign VAR88 = (sel[1] == 0)? VAR296 : VAR344;
assign VAR341 = (sel[1] == 0)? VAR171 : VAR89;
assign VAR56 = (sel[1] == 0)? VAR278 : VAR326;
assign VAR114 = (sel[1] == 0)? VAR122 : VAR167;
assign VAR86 = (sel[1] == 0)? VAR388 : VAR14;
assign VAR67 = (sel[1] == 0)? VAR127 : VAR234;
assign VAR159 = (sel[1] == 0)? VAR300 : VAR144;
assign VAR308 = (sel[1] == 0)? VAR377 : VAR297;
assign VAR270 = (sel[1] == 0)? VAR230 : VAR280;
assign VAR137 = (sel[1] == 0)? VAR222 : VAR331;
assign VAR154 = (sel[2] == 0)? VAR329 : VAR226;
assign VAR295 = (sel[2] == 0)? VAR134 : VAR48;
assign VAR180 = (sel[2] == 0)? VAR116 : VAR369;
assign VAR84 = (sel[2] == 0)? VAR70 : VAR179;
assign VAR359 = (sel[2] == 0)? VAR23 : VAR374;
assign VAR334 = (sel[2] == 0)? VAR133 : VAR223;
assign VAR313 = (sel[2] == 0)? VAR60 : VAR32;
assign VAR358 = (sel[2] == 0)? VAR45 : VAR314;
assign VAR244 = (sel[2] == 0)? VAR293 : VAR158;
assign VAR188 = (sel[2] == 0)? VAR365 : VAR73;
assign VAR306 = (sel[2] == 0)? VAR366 : VAR176;
assign VAR143 = (sel[2] == 0)? VAR88 : VAR341;
assign VAR252 = (sel[2] == 0)? VAR56 : VAR114;
assign VAR182 = (sel[2] == 0)? VAR86 : VAR67;
assign VAR250 = (sel[2] == 0)? VAR159 : VAR308;
assign VAR273 = (sel[2] == 0)? VAR270 : VAR137;
assign VAR178 = (sel[3] == 0)? VAR154 : VAR295;
assign VAR375 = (sel[3] == 0)? VAR180 : VAR84;
assign VAR199 = (sel[3] == 0)? VAR359 : VAR334;
assign VAR192 = (sel[3] == 0)? VAR313 : VAR358;
assign VAR263 = (sel[3] == 0)? VAR244 : VAR188;
assign VAR303 = (sel[3] == 0)? VAR306 : VAR143;
assign VAR71 = (sel[3] == 0)? VAR252 : VAR182;
assign VAR243 = (sel[3] == 0)? VAR250 : VAR273;
assign VAR26 = (sel[4] == 0)? VAR178 : VAR375;
assign VAR105 = (sel[4] == 0)? VAR199 : VAR192;
assign VAR155 = (sel[4] == 0)? VAR263 : VAR303;
assign VAR112 = (sel[4] == 0)? VAR71 : VAR243;
assign VAR350 = (sel[5] == 0)? VAR26 : VAR105;
assign VAR330 = (sel[5] == 0)? VAR155 : VAR112;
assign VAR265 = (sel[6] == 0)? VAR350 : VAR330;
assign dout = VAR265;
endmodule
|
apache-2.0
|
queq/just-stuff
|
pov/TopMobile/LEDS/top_RAM.v
| 1,424 |
module MODULE1( clk, VAR14, VAR16, VAR37,VAR25,VAR27,VAR9);
input clk;
input VAR14; input [15:0] VAR25;
input VAR9;
input VAR16;
output [15:0] VAR37;
output [7:0] VAR27;
wire rst;
wire VAR29;
wire VAR21;
wire VAR38;
wire VAR2;
wire VAR28;
wire VAR31;
wire VAR3;
wire VAR5;
wire VAR32;
wire VAR7;
wire VAR36;
wire VAR8;
wire [2:0] VAR33;
wire [3:0] VAR13;
VAR10 VAR15( .clk(clk),.VAR8(VAR8),.VAR23(VAR25),.VAR37(VAR37),.VAR13(VAR13));
VAR22 VAR12(.VAR3(VAR3),.VAR7(VAR7), .VAR36(VAR36), .VAR27(VAR27), .VAR5(VAR5), .VAR32(VAR32));
VAR6 VAR26(.rst(rst),.clk(clk),.VAR3(VAR3));
VAR4 VAR17 (.VAR33(VAR33), .clk(clk), .VAR29(VAR29),.VAR21(VAR21));
VAR11 VAR18 (.VAR13(VAR13), .clk(clk), .VAR38(VAR38), .VAR2(VAR2));
VAR24 VAR39 (.VAR33(VAR33), .VAR28(VAR28));
VAR30 VAR1 (.VAR13(VAR13), .VAR31(VAR31));
VAR19 VAR20(.clk(clk),.VAR35(VAR14),.VAR16(VAR16),.VAR29(VAR29),.VAR38(VAR38),.VAR21(VAR21),.VAR2(VAR2),.VAR28(VAR28),.VAR31(VAR31),.VAR7(VAR7),.VAR36(VAR36),.VAR5(VAR5),.VAR32(VAR32),.VAR34(VAR8),.rst(rst),.VAR9(VAR9));
endmodule
|
mit
|
toomij/DE2Labs
|
Lab4/counter_16bit.v
| 1,315 |
module MODULE1 (VAR15, VAR9, VAR7, VAR12);
input VAR15, VAR9, VAR7;
output [15:0] VAR12;
wire [15:0] VAR19, VAR3;
VAR16 VAR8 (VAR15, VAR9, VAR7, VAR3[0]);
assign VAR19[0] = VAR15 & VAR3[0];
VAR16 VAR13 (VAR19[0], VAR9, VAR7, VAR3[1]);
assign VAR19[1] = VAR19[0] & VAR3[1];
VAR16 VAR20 (VAR19[1], VAR9, VAR7, VAR3[2]);
assign VAR19[2] = VAR19[1] & VAR3[2];
VAR16 VAR10 (VAR19[2], VAR9, VAR7, VAR3[3]);
assign VAR19[3] = VAR19[2] & VAR3[3];
VAR16 VAR18 (VAR19[3], VAR9, VAR7, VAR3[4]);
assign VAR19[4] = VAR19[3] & VAR3[4];
VAR16 VAR6 (VAR19[4], VAR9, VAR7, VAR3[5]);
assign VAR19[5] = VAR19[4] & VAR3[5];
VAR16 VAR4 (VAR19[5], VAR9, VAR7, VAR3[6]);
assign VAR19[6] = VAR19[5] & VAR3[6];
VAR16 VAR5 (VAR19[6], VAR9, VAR7, VAR3[7]);
assign VAR19[7] = VAR19[6] & VAR3[7];
VAR16 VAR23 (VAR19[7], VAR9, VAR7, VAR3[8]);
assign VAR19[8] = VAR19[7] & VAR3[8];
VAR16 VAR11 (VAR19[8], VAR9, VAR7, VAR3[9]);
assign VAR19[9] = VAR19[8] & VAR3[9];
VAR16 VAR14 (VAR19[9], VAR9, VAR7, VAR3[10]);
assign VAR19[10] = VAR19[9] & VAR3[10];
VAR16 VAR22 (VAR19[10], VAR9, VAR7, VAR3[11]);
assign VAR19[11] = VAR19[10] & VAR3[11];
VAR16 VAR21 (VAR19[11], VAR9, VAR7, VAR3[12]);
assign VAR19[12] = VAR19[11] & VAR3[12];
VAR16 VAR2 (VAR19[12], VAR9, VAR7, VAR3[13]);
assign VAR19[13] = VAR19[12] & VAR3[13];
VAR16 VAR1 (VAR19[13], VAR9, VAR7, VAR3[14]);
assign VAR19[14] = VAR19[13] & VAR3[14];
VAR16 VAR17 (VAR19[14], VAR9, VAR7, VAR3[15]);
assign VAR12 = VAR3;
endmodule
|
gpl-2.0
|
mindrobots/P8X32A_Emulation
|
P8X32A_Pipistrello/src/hub_mem.v
| 2,847 |
module MODULE1
(
input VAR11,
input VAR6,
input VAR5,
input [3:0] VAR7,
input [13:0] VAR2,
input [31:0] VAR10,
output [31:0] VAR1
);
reg [7:0] VAR3 [16*1024-1:0]; reg [7:0] VAR4 [16*1024-1:0];
reg [7:0] VAR9 [16*1024-1:0];
reg [7:0] VAR8 [16*1024-1:0];
begin
begin
begin
begin
begin
|
gpl-3.0
|
bluecmd/mexiko
|
rtl/gic/gic_slave.v
| 6,096 |
module MODULE1 #(
parameter VAR1 = 4'b1111
) (
output [31:0] VAR5,
output VAR38,
output VAR9,
output [3:0] VAR2,
output VAR20,
output [2:0] VAR31,
output [1:0] VAR16,
output [31:0] VAR30,
input VAR21,
input VAR11,
input [31:0] VAR19,
input VAR43,
input VAR23,
input VAR12,
input [3:0] VAR36,
output [3:0] VAR41
);
localparam VAR32 = 4'b1010;
localparam VAR7 = 4'b0101;
localparam VAR17 = 0;
localparam VAR33 = 1;
localparam VAR18 = 2;
localparam VAR15 = 3;
localparam VAR39 = 4;
localparam VAR4 = 5;
localparam VAR35 = 6;
localparam VAR42 = 7;
localparam VAR22 = 8;
localparam VAR25 = 9;
reg [3:0] VAR8 = VAR17;
reg [3:0] VAR28 = VAR17;
reg [2:0] VAR3 = 0;
reg [3:0] VAR14 = 0;
reg [3:0] VAR37 = 0;
reg VAR6 = 1'b0;
reg VAR26 = 1'b0;
reg [31:0] VAR44 = 0;
reg [31:0] VAR13 = 0;
reg [31:0] VAR10 = 0;
reg [3:0] VAR34 = 0;
reg VAR40 = 1'b0;
wire [3:0] VAR27 = (VAR3 == 0) ? 4'b1100 : 4'b0000;
assign VAR5 = VAR44;
assign VAR30 = VAR13;
assign VAR20 = VAR26;
assign VAR38 = VAR40 & VAR6;
assign VAR9 = VAR40 & VAR6;
assign VAR2 = VAR34;
assign VAR31 = 3'b000; assign VAR31 = 3'b000;
assign VAR16 = 2'b00;
wire VAR29 = VAR11 | VAR21 | VAR43;
assign VAR41 = VAR14;
always @(posedge VAR23)
begin
if (VAR12) begin
VAR8 <= VAR17;
end else begin
VAR8 <= VAR28;
end
end
always @(posedge VAR23)
begin
if (VAR12) begin
VAR3 <= 7;
end else begin
VAR3 <= 7;
if ((VAR8 == VAR15) | (VAR8 == VAR39) |
(VAR8 == VAR22)) begin
VAR3 <= VAR3 - 1;
end
end
end
always @(posedge VAR23)
begin
VAR37 <= VAR37;
case (VAR8)
VAR18:
VAR37 <= VAR36;
VAR15 | VAR39:
VAR37 <= VAR37 ^ VAR36 ^ VAR27;
VAR42:
VAR37 <= 0;
VAR22:
VAR37 <= VAR37 ^ VAR10[VAR3*4+:4] ^ VAR27;
endcase
end
always @(VAR8)
begin
VAR6 <= 1'b1;
end
always @(VAR8 or VAR3 or VAR29)
begin
VAR14 <= VAR1;
case (VAR8)
VAR35:
if (VAR29)
VAR14 <= VAR7;
VAR42:
VAR14 <= 4'VAR24;
VAR22:
VAR14 <= VAR10[VAR3*4+:4];
VAR25:
VAR14 <= VAR37;
endcase
end
always @(posedge VAR23)
begin
VAR44 <= VAR44;
VAR13 <= VAR13;
VAR34 <= VAR34;
VAR40 <= VAR40;
VAR26 <= VAR26;
case (VAR8)
VAR33:
VAR26 <= VAR36[3];
VAR18:
VAR34 <= VAR36;
VAR15:
VAR44[VAR3*4+:4] <= VAR36;
VAR39:
VAR13[VAR3*4+:4] <= VAR36;
VAR4:
VAR40 <= 1'b1;
VAR35:
VAR40 <= ~VAR29;
endcase
end
always @(posedge VAR23)
begin
VAR10 <= VAR10;
case (VAR8)
VAR35:
if (VAR29)
VAR10 <= VAR19;
endcase
end
always @(VAR8 or VAR3 or VAR29)
begin
VAR28 <= VAR8;
case (VAR8)
VAR17:
if (VAR36 == VAR32)
VAR28 <= VAR33;
VAR33:
VAR28 <= VAR18;
VAR18:
VAR28 <= VAR15;
VAR15:
if (VAR3 == 0)
VAR28 <= VAR26 ? VAR39 : VAR4;
VAR39:
if (VAR3 == 0)
VAR28 <= VAR4;
VAR4:
VAR28 <= VAR35;
VAR35:
if (VAR29)
VAR28 <= VAR42;
VAR42:
VAR28 <= VAR26 ? VAR17 : VAR22;
VAR22:
if (VAR3 == 0)
VAR28 <= VAR25;
VAR25:
VAR28 <= VAR17;
endcase
end
always @(posedge VAR23)
begin
if (VAR29 & (VAR8 == VAR35)) begin
end else if (VAR8 == VAR22) begin
end else if (VAR8 == VAR25) begin
end
end
endmodule
|
gpl-3.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/DE4_SOPC_burst_3.v
| 15,486 |
module MODULE1 (
clk,
VAR1,
VAR9,
VAR35,
VAR37,
VAR55,
VAR23,
VAR34,
VAR13,
VAR46,
VAR59,
VAR3,
VAR22,
VAR67,
VAR17,
VAR24,
VAR21,
VAR66,
VAR15,
VAR61,
VAR29,
VAR31,
VAR4,
VAR39,
VAR16
)
;
output [ 13: 0] VAR67;
output [ 10: 0] VAR17;
output VAR24;
output [ 3: 0] VAR21;
output VAR66;
output [ 13: 0] VAR15;
output VAR61;
output VAR29;
output [ 31: 0] VAR31;
output [ 31: 0] VAR4;
output VAR39;
output VAR16;
input clk;
input [ 31: 0] VAR1;
input VAR9;
input VAR35;
input VAR37;
input [ 15: 0] VAR55;
input [ 9: 0] VAR23;
input [ 3: 0] VAR34;
input VAR13;
input [ 13: 0] VAR46;
input VAR59;
input VAR3;
input [ 31: 0] VAR22;
wire [ 9: 0] VAR20;
reg VAR44;
wire [ 15: 0] VAR49;
wire [ 9: 0] VAR8;
wire VAR56;
wire VAR65;
reg [ 10: 0] VAR62;
wire [ 10: 0] VAR38;
wire [ 13: 0] VAR67;
wire [ 15: 0] VAR12;
wire [ 10: 0] VAR17;
wire VAR24;
wire VAR30;
wire [ 3: 0] VAR21;
wire VAR66;
wire [ 13: 0] VAR15;
reg VAR61;
wire VAR29;
reg VAR43;
wire [ 31: 0] VAR31;
wire VAR52;
wire VAR64;
wire VAR33;
wire VAR45;
wire VAR5;
wire VAR27;
wire VAR26;
wire VAR41;
wire VAR25;
reg VAR57;
wire VAR68;
reg VAR10;
reg [ 9: 0] VAR6;
wire VAR53;
wire [ 10: 0] VAR54;
reg [ 10: 0] VAR18;
reg [ 15: 0] VAR42;
reg [ 9: 0] VAR48;
reg [ 3: 0] VAR19;
reg [ 13: 0] VAR28;
reg VAR50;
reg VAR11;
reg VAR7;
reg VAR36;
wire VAR51;
wire [ 10: 0] VAR63;
reg [ 10: 0] VAR2;
wire VAR32;
wire VAR40;
wire VAR60;
wire [ 31: 0] VAR4;
wire VAR39;
wire VAR16;
wire VAR47;
reg [ 9: 0] VAR14;
wire VAR58;
assign VAR51 = |VAR46;
assign VAR40 = VAR56 ? (VAR63 == VAR24) & VAR61 & ~VAR35 : (VAR63 == (VAR44 + 1)) & VAR29 & ~VAR35;
assign VAR45 = VAR44 + (VAR61 ? VAR24 : 1);
assign VAR30 = (VAR61 | VAR29) & ~VAR35 & (VAR45 == VAR24);
assign VAR38 = VAR41 ? VAR54 : VAR18;
assign VAR54 = {VAR23,
1'b0};
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR18 <= 0;
end
else if (VAR41)
VAR18 <= VAR54;
end
assign VAR26 = VAR36 & ~VAR59 & ~VAR3 | VAR7 & (VAR62 == 0) & VAR5 & ~VAR25 & ~VAR68;
assign VAR27 = VAR36 & (VAR59 | VAR3) | VAR7 & (~(VAR62 == 0) | ~VAR5 | VAR25 | VAR68);
assign VAR52 = ~(VAR61 | VAR29) | ~VAR35;
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR57 <= 0;
end
else if (VAR59 & VAR36)
VAR57 <= -1;
else if (VAR40)
VAR57 <= 0;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR10 <= 0;
end
else if (VAR40)
VAR10 <= 0;
else if (VAR3 & (VAR36 | ~VAR16))
VAR10 <= -1;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR36 <= 1;
end
else if (VAR52)
VAR36 <= VAR26;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR7 <= 0;
end
else if (VAR52)
VAR7 <= VAR27;
end
assign VAR25 = VAR57;
assign VAR68 = VAR10 & ~VAR40;
assign VAR41 = VAR36 | ((VAR59 | VAR3) & ~VAR16);
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR50 <= 0;
end
else if (VAR41)
VAR50 <= VAR59;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR11 <= 0;
end
else if (VAR41)
VAR11 <= VAR3;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR48 <= 0;
end
else if (VAR41)
VAR48 <= VAR23;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR42 <= 0;
end
else if (VAR41)
VAR42 <= VAR55;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR28 <= 0;
end
else if (VAR41)
VAR28 <= VAR46;
end
assign VAR56 = VAR50 & !VAR29;
assign VAR65 = VAR11;
assign VAR49 = VAR42;
assign VAR8 = VAR41 ? VAR23 : VAR48;
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR44 <= 0;
end
else if ((VAR61 | VAR29) & ~VAR35)
VAR44 <= VAR30 ? 0 : VAR45;
end
assign VAR53 = VAR56 & ~VAR35;
assign VAR58 = VAR65 & VAR29 & VAR30;
assign VAR32 = VAR53 | VAR58;
assign VAR63 = (VAR36 & (VAR59 | VAR3)) ? VAR38 : VAR2;
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR2 <= 0;
end
else
VAR2 <= (VAR36 & (VAR59 | VAR3)) ? VAR38 : VAR32 ? VAR2 - VAR24 : VAR2;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR62 <= 0;
end
else
VAR62 <= VAR36 & VAR59 & ~VAR16 ? VAR38 : VAR9 ? VAR62 - 1 : VAR62;
end
assign VAR33 = 1;
assign VAR24 = (VAR63 > VAR33) ? VAR33 : VAR63;
assign VAR17 = VAR56 ? (VAR38) : VAR38;
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR14 <= 0;
end
else
VAR14 <= VAR36 & VAR3 ? 0 : ((VAR29 & ~VAR35 & VAR30)) ? VAR14 + VAR24 : VAR14;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR6 <= 0;
end
else
VAR6 <= VAR36 & VAR59 ? 0 : (VAR61 & ~VAR35) ? VAR6 + VAR24 : VAR6;
end
assign VAR15 = VAR28 >> 3;
assign VAR20 = VAR56 ? VAR6 : VAR14;
assign VAR12 = {VAR49[15 : 3], 3'b000};
assign VAR67 = VAR12 + {VAR20, 2'b00};
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR61 <= 0;
end
else if (~VAR61 | ~VAR35)
VAR61 <= VAR36 & VAR59 ? 1 : (VAR63 == VAR24) ? 0 : VAR61;
end
assign VAR39 = VAR9;
assign VAR4 = VAR1;
assign VAR64 = 1;
assign VAR5 = 1;
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR43 <= 0;
end
else if (~VAR43 | ~VAR35)
VAR43 <= VAR36 & VAR3 ? 1 : ((VAR63 == VAR24) & VAR30) ? 0 : VAR43;
end
always @(posedge clk or negedge VAR37)
begin
if (VAR37 == 0)
VAR19 <= 4'b1111;
end
else if (VAR41)
VAR19 <= VAR34;
end
assign VAR29 = VAR43 & VAR3 & !VAR61;
assign VAR21 = VAR43 ? VAR34 : VAR19;
assign VAR31 = VAR22;
assign VAR60 = VAR36 & VAR59;
assign VAR47 = VAR7 & VAR3 & ~VAR35 & !VAR61;
assign VAR16 = (VAR59 | VAR56) ? ~VAR60 : VAR65 ? ~VAR47 : 1;
assign VAR66 = VAR13;
endmodule
|
mit
|
YuxuanLing/trunk
|
trunk/references/h265enc_v1.0/rtl/pre_i/counter.v
| 9,007 |
module MODULE1(
VAR31,
clk,
VAR66,
VAR12,
VAR9,
VAR2,
VAR10,
VAR25,
VAR47,
VAR34,
VAR16,
VAR62,
VAR28,
VAR30,
VAR29,
VAR18,
VAR67,
VAR41,
VAR64,
VAR42,
VAR65,
VAR40,
VAR36,
VAR6,
VAR61,
VAR11,
VAR22,
VAR1,
VAR15,
VAR54,
VAR27,
VAR37,
VAR55,
VAR3,
VAR32,
VAR19,
VAR50,
VAR59
);
parameter VAR21=21;
input VAR31;
input clk;
input VAR66;
input VAR12;
input signed [10:0] VAR9;
input signed [10:0] VAR2;
output [VAR21:0] VAR10;
output [VAR21:0] VAR25;
output [VAR21:0] VAR47;
output [VAR21:0] VAR34;
output [VAR21:0] VAR16;
output [VAR21:0] VAR62;
output [VAR21:0] VAR28;
output [VAR21:0] VAR30;
output [VAR21:0] VAR29;
output [VAR21:0] VAR18;
output [VAR21:0] VAR67;
output [VAR21:0] VAR41;
output [VAR21:0] VAR64;
output [VAR21:0] VAR42;
output [VAR21:0] VAR65;
output [VAR21:0] VAR40;
output [VAR21:0] VAR36;
output [VAR21:0] VAR6;
output [VAR21:0] VAR61;
output [VAR21:0] VAR11;
output [VAR21:0] VAR22;
output [VAR21:0] VAR1;
output [VAR21:0] VAR15;
output [VAR21:0] VAR54;
output [VAR21:0] VAR27;
output [VAR21:0] VAR37;
output [VAR21:0] VAR55;
output [VAR21:0] VAR3;
output [VAR21:0] VAR32;
output [VAR21:0] VAR19;
output [VAR21:0] VAR50;
output [VAR21:0] VAR59;
reg signed [VAR21:0] VAR57;
reg signed [VAR21:0] VAR45;
reg signed [VAR21:0] VAR26;
reg signed [VAR21:0] VAR58;
reg signed [VAR21:0] VAR63;
reg signed [VAR21:0] VAR60;
reg signed [VAR21:0] VAR48;
reg signed [VAR21:0] VAR70;
reg signed [VAR21:0] VAR52;
reg signed [VAR21:0] VAR33;
reg signed [VAR21:0] VAR14;
reg signed [VAR21:0] VAR24;
reg signed [VAR21:0] VAR38;
reg signed [VAR21:0] VAR8;
reg signed [VAR21:0] VAR43;
reg signed [VAR21:0] VAR17;
reg signed [VAR21:0] VAR53;
reg signed [VAR21:0] VAR69;
reg signed [VAR21:0] VAR4;
reg signed [VAR21:0] VAR46;
reg signed [VAR21:0] VAR49;
reg signed [VAR21:0] VAR44;
reg signed [VAR21:0] VAR39;
reg signed [VAR21:0] VAR13;
reg signed [VAR21:0] VAR56;
reg signed [VAR21:0] VAR51;
reg signed [VAR21:0] VAR68;
reg signed [VAR21:0] VAR7;
reg signed [VAR21:0] VAR5;
reg signed [VAR21:0] VAR23;
reg signed [VAR21:0] VAR35;
reg signed [VAR21:0] VAR20;
always@(posedge clk or negedge VAR31)
if(!VAR31)
begin
VAR57<='d0;
VAR45<='d0;
VAR26<='d0;
VAR58<='d0;
VAR63<='d0;
VAR60<='d0;
VAR48<='d0;
VAR70<='d0;
VAR52<= 'd0;
VAR33<= 'd0;
VAR14<= 'd0;
VAR24<= 'd0;
VAR38<= 'd0;
VAR8<= 'd0;
VAR43<= 'd0;
VAR17<= 'd0;
VAR53<= 'd0;
VAR69<= 'd0;
VAR4<= 'd0;
VAR46<= 'd0;
VAR49<= 'd0;
VAR44<= 'd0;
VAR39<= 'd0;
VAR13<= 'd0;
VAR56<= 'd0;
VAR51<= 'd0;
VAR68<= 'd0;
VAR7<= 'd0;
VAR5<= 'd0;
VAR23<= 'd0;
VAR35<= 'd0;
VAR20<= 'd0;
end
else if(VAR66)
begin
VAR57<=90*VAR9+90*VAR2;
VAR45<=99*VAR9+81*VAR2;
VAR26<=107*VAR9+70*VAR2;
VAR58<=113*VAR9+60*VAR2;
VAR63<=118*VAR9+48*VAR2;
VAR60<=123*VAR9+35*VAR2;
VAR48<=126*VAR9+20*VAR2;
VAR70<=127*VAR9+8*VAR2;
VAR52<=128*VAR9;
VAR33<=127*VAR9-8*VAR2;
VAR14<=126*VAR9-20*VAR2;
VAR24<=123*VAR9-35*VAR2;
VAR38<=118*VAR9-48*VAR2;
VAR8<=113*VAR9-60*VAR2;
VAR43<=107*VAR9-70*VAR2;
VAR17<=99*VAR9-81*VAR2;
VAR53<=90*VAR9-90*VAR2;
VAR69<=81*VAR9-99*VAR2;
VAR4<=70*VAR9-107*VAR2;
VAR46<=60*VAR9-113*VAR2;
VAR49<=48*VAR9-118*VAR2;
VAR44<=35*VAR9-123*VAR2;
VAR39<=20*VAR9-126*VAR2;
VAR13<=8*VAR9-127*VAR2;
VAR56<=128*VAR2;
VAR51<=8*VAR9+127*VAR2;
VAR68<=20*VAR9+126*VAR2;
VAR7<=35*VAR9+123*VAR2;
VAR5<=48*VAR9+118*VAR2;
VAR23<=60*VAR9+113*VAR2;
VAR35<=70*VAR9+107*VAR2;
VAR20<=81*VAR9+99*VAR2;
end
reg [VAR21:0] VAR10;
reg [VAR21:0] VAR25;
reg [VAR21:0] VAR47;
reg [VAR21:0] VAR34;
reg [VAR21:0] VAR16;
reg [VAR21:0] VAR62;
reg [VAR21:0] VAR28;
reg [VAR21:0] VAR30;
reg [VAR21:0] VAR29;
reg [VAR21:0] VAR18;
reg [VAR21:0] VAR67;
reg [VAR21:0] VAR41;
reg [VAR21:0] VAR64;
reg [VAR21:0] VAR42;
reg [VAR21:0] VAR65;
reg [VAR21:0] VAR40;
reg [VAR21:0] VAR36;
reg [VAR21:0] VAR6;
reg [VAR21:0] VAR61;
reg [VAR21:0] VAR11;
reg [VAR21:0] VAR22;
reg [VAR21:0] VAR1;
reg [VAR21:0] VAR15;
reg [VAR21:0] VAR54;
reg [VAR21:0] VAR27;
reg [VAR21:0] VAR37;
reg [VAR21:0] VAR55;
reg [VAR21:0] VAR3;
reg [VAR21:0] VAR32;
reg [VAR21:0] VAR19;
reg [VAR21:0] VAR50;
reg [VAR21:0] VAR59;
always@(posedge clk or negedge VAR31)
if(!VAR31)
begin
VAR10 <= 'd0;
VAR25 <= 'd0;
VAR47 <= 'd0;
VAR34 <= 'd0;
VAR16 <= 'd0;
VAR62 <= 'd0;
VAR28 <= 'd0;
VAR30 <= 'd0;
VAR29 <= 'd0;
VAR18 <= 'd0;
VAR67 <= 'd0;
VAR41 <= 'd0;
VAR64 <= 'd0;
VAR42 <= 'd0;
VAR65 <= 'd0;
VAR40 <= 'd0;
VAR36 <= 'd0;
VAR6 <= 'd0;
VAR61 <= 'd0;
VAR11 <= 'd0;
VAR22 <= 'd0;
VAR1 <= 'd0;
VAR15 <= 'd0;
VAR54 <= 'd0;
VAR27 <= 'd0;
VAR37 <= 'd0;
VAR55 <= 'd0;
VAR3 <= 'd0;
VAR32 <= 'd0;
VAR19 <= 'd0;
VAR50 <= 'd0;
VAR59 <= 'd0;
end
else if(VAR12)
begin
VAR10 <= VAR10+((VAR57[VAR21]) ? (-VAR57) : (VAR57));
VAR25 <= VAR25+((VAR45[VAR21]) ? (-VAR45) : (VAR45));
VAR47 <= VAR47+((VAR26[VAR21]) ? (-VAR26) : (VAR26));
VAR34 <= VAR34+((VAR58[VAR21]) ? (-VAR58) : (VAR58));
VAR16 <= VAR16+((VAR63[VAR21]) ? (-VAR63) : (VAR63));
VAR62 <= VAR62+((VAR60[VAR21]) ? (-VAR60) : (VAR60));
VAR28 <= VAR28+((VAR48[VAR21]) ? (-VAR48) : (VAR48));
VAR30 <= VAR30+((VAR70[VAR21]) ? (-VAR70) : (VAR70));
VAR29 <= VAR29+((VAR52[VAR21]) ? (-VAR52) : (VAR52));
VAR18 <= VAR18+((VAR33[VAR21]) ? (-VAR33) : (VAR33));
VAR67 <= VAR67+((VAR14[VAR21]) ? (-VAR14) : (VAR14));
VAR41 <= VAR41+((VAR24[VAR21]) ? (-VAR24) : (VAR24));
VAR64 <= VAR64+((VAR38[VAR21]) ? (-VAR38) : (VAR38));
VAR42 <= VAR42+((VAR8[VAR21]) ? (-VAR8) : (VAR8));
VAR65 <= VAR65+((VAR43[VAR21]) ? (-VAR43) : (VAR43));
VAR40 <= VAR40+((VAR17[VAR21]) ? (-VAR17) : (VAR17));
VAR36 <= VAR36+((VAR53[VAR21]) ? (-VAR53) : (VAR53));
VAR6 <= VAR6+((VAR69[VAR21]) ? (-VAR69) : (VAR69));
VAR61 <= VAR61+((VAR4[VAR21]) ? (-VAR4) : (VAR4));
VAR11 <= VAR11+((VAR46[VAR21]) ? (-VAR46) : (VAR46));
VAR22 <= VAR22+((VAR49[VAR21]) ? (-VAR49) : (VAR49));
VAR1 <= VAR1+((VAR44[VAR21]) ? (-VAR44) : (VAR44));
VAR15 <= VAR15+((VAR39[VAR21]) ? (-VAR39) : (VAR39));
VAR54 <= VAR54+((VAR13[VAR21]) ? (-VAR13) : (VAR13));
VAR27 <= VAR27+((VAR56[VAR21]) ? (-VAR56) : (VAR56));
VAR37 <= VAR37+((VAR51[VAR21]) ? (-VAR51) : (VAR51));
VAR55 <= VAR55+((VAR68[VAR21]) ? (-VAR68) : (VAR68));
VAR3 <= VAR3+((VAR7[VAR21]) ? (-VAR7) : (VAR7));
VAR32 <= VAR32+((VAR5[VAR21]) ? (-VAR5) : (VAR5));
VAR19 <= VAR19+((VAR23[VAR21]) ? (-VAR23) : (VAR23));
VAR50 <= VAR50+((VAR35[VAR21]) ? (-VAR35) : (VAR35));
VAR59 <= VAR59+((VAR20[VAR21]) ? (-VAR20) : (VAR20));
end
else if(VAR66)
begin
VAR10 <= 'd0;
VAR25 <= 'd0;
VAR47 <= 'd0;
VAR34 <= 'd0;
VAR16 <= 'd0;
VAR62 <= 'd0;
VAR28 <= 'd0;
VAR30 <= 'd0;
VAR29 <= 'd0;
VAR18 <= 'd0;
VAR67 <= 'd0;
VAR41 <= 'd0;
VAR64 <= 'd0;
VAR42 <= 'd0;
VAR65 <= 'd0;
VAR40 <= 'd0;
VAR36 <= 'd0;
VAR6 <= 'd0;
VAR61 <= 'd0;
VAR11 <= 'd0;
VAR22 <= 'd0;
VAR1 <= 'd0;
VAR15 <= 'd0;
VAR54 <= 'd0;
VAR27 <= 'd0;
VAR37 <= 'd0;
VAR55 <= 'd0;
VAR3 <= 'd0;
VAR32 <= 'd0;
VAR19 <= 'd0;
VAR50 <= 'd0;
VAR59 <= 'd0;
end
endmodule
|
gpl-3.0
|
vad-rulezz/megabot
|
minsoc/rtl/verilog/ethmac/bench/verilog/wb_master_behavioral.v
| 23,268 |
module MODULE1
(
VAR42,
VAR16,
VAR58,
VAR36,
VAR57,
VAR34,
VAR21,
VAR32,
VAR27,
VAR47,
VAR33,
VAR17,
VAR40,
VAR43,
VAR46
);
input VAR42;
input VAR16;
input VAR49 VAR58;
output VAR49 VAR36;
input VAR57;
output VAR25 VAR34;
output VAR21;
input VAR12 VAR32;
output VAR12 VAR27;
input VAR47;
input VAR33;
output VAR64 VAR17;
output VAR40;
output VAR43;
output VAR46;
VAR66 VAR28
(
.VAR42(VAR42),
.VAR16(VAR16),
.VAR58(VAR58),
.VAR36(VAR36),
.VAR57(VAR57),
.VAR34(VAR34),
.VAR21(VAR21),
.VAR32(VAR32),
.VAR27(VAR27),
.VAR47(VAR47),
.VAR33(VAR33),
.VAR17(VAR17),
.VAR40(VAR40),
.VAR43(VAR43),
.VAR46(VAR46)
) ;
reg VAR11 VAR6 [0:(VAR45 - 1)] ;
reg VAR72 VAR54 [0:(VAR45 - 1)] ;
reg VAR38 VAR48 [0:(VAR45 - 1)] ;
task VAR14 ;
input VAR11 VAR5 ;
input VAR37 VAR24 ;
inout VAR31 return ;
reg VAR2 ;
reg VAR51 ;
reg VAR29 ;
integer VAR55 ;
integer VAR1 ;
reg VAR68 ;
begin:VAR70
VAR4 = 1'b0 ;
VAR51 = 0 ;
VAR22 = 0 ;
VAR1 = 0 ;
if ( VAR2 === 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR2 = 1 ;
VAR68 = 1 ;
while (VAR68 === 1)
begin
@(posedge VAR42) ;
VAR28.VAR23(VAR51, 1'b1, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR55 = VAR39 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR59(VAR5, return) ;
if ( VAR52 === 0 && VAR13 === 0 && VAR53 === 1 && VAR65 === 1 && VAR4 === 0)
begin
if ( VAR1 === VAR69 )
begin
;
VAR68 = 0 ;
end
else
begin
VAR68 = 1 ;
VAR1 = VAR1 + 1 ;
end
end
else
VAR68 = 0 ;
if ( VAR4 !== 0 )
begin
@(posedge VAR42) ;
VAR28.VAR71 ;
disable VAR70 ;
end
VAR55 = VAR35 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR71 ;
end
VAR2 = 0 ;
end endtask
task VAR18 ;
input VAR72 VAR60 ;
input VAR37 VAR44 ;
inout VAR38 return ;
reg VAR2 ;
reg VAR51 ;
reg VAR29 ;
integer VAR55 ;
integer VAR1 ;
reg VAR68 ;
begin:VAR70
VAR4 = 1'b0 ;
VAR51 = 0 ;
VAR1 = 0 ;
VAR22 = 0 ;
if ( VAR2 === 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR2 = 1 ;
VAR68 = 1 ;
while (VAR68 === 1)
begin
@(posedge VAR42) ;
VAR28.VAR23(VAR51, 1'b0, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR55 = VAR67 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR8(VAR60, return) ;
if ( VAR52 === 0 && VAR13 === 0 && VAR53 === 1 && VAR30 === 1 && VAR4 === 0)
begin
if ( VAR1 === VAR69 )
begin
;
VAR68 = 0 ;
end
else
begin
VAR68 = 1 ;
VAR1 = VAR1 + 1 ;
end
end
else
begin
VAR68 = 0 ;
end
if ( VAR4 !== 0 )
begin
@(posedge VAR42) ;
VAR28.VAR71 ;
disable VAR70 ;
end
VAR55 = VAR73 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR71 ;
end
VAR2 = 0 ;
end endtask
task VAR9 ;
input VAR72 VAR60 ;
input VAR37 VAR44 ;
inout VAR38 return ;
reg VAR2 ;
reg VAR51 ;
reg VAR29 ;
integer VAR55 ;
integer VAR1 ;
reg VAR68 ;
begin:VAR70
VAR4 = 1'b0 ;
VAR51 = 0 ;
VAR1 = 0 ;
VAR22 = 0 ;
if ( VAR2 === 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR2 = 1 ;
VAR68 = 1 ;
while (VAR68 === 1)
begin
@(posedge VAR42) ;
VAR28.VAR23(VAR51, 1'b0, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR55 = VAR67 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR8(VAR60, return) ;
if ( VAR52 === 0 && VAR13 === 0 && VAR53 === 1 && VAR30 === 1 && VAR4 === 0)
begin
if ( VAR1 === VAR69 )
begin
;
VAR68 = 0 ;
end
else
begin
VAR68 = 1 ;
VAR1 = VAR1 + 1 ;
end
end
else
begin
VAR68 = 0 ;
end
if ( VAR4 !== 0 )
begin
@(posedge VAR42) ;
VAR28.VAR71 ;
disable VAR70 ;
end
VAR55 = VAR73 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
if (VAR68 === 1)
VAR28.VAR71 ;
end
else
VAR28.VAR61 ;
end
VAR2 = 0 ;
end endtask
task VAR20 ;
input VAR11 VAR5 ;
input VAR37 VAR24 ;
inout VAR31 return ;
reg VAR2 ;
reg VAR51 ;
reg VAR29 ;
integer VAR55 ;
integer VAR1 ;
reg VAR68 ;
begin:VAR70
VAR4 = 1'b0 ;
VAR51 = 0 ;
VAR22 = 0 ;
VAR1 = 0 ;
if ( VAR2 === 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR2 = 1 ;
VAR68 = 1 ;
while (VAR68 === 1)
begin
VAR29 = 1 ;
if (VAR1 !== 0)
VAR28.VAR23(VAR51, 1'b1, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR55 = VAR39 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR59(VAR5, return) ;
if ( VAR52 === 0 && VAR13 === 0 && VAR53 === 1 && VAR65 === 1 && VAR4 === 0)
begin
if ( VAR1 === VAR69 )
begin
;
VAR68 = 0 ;
end
else
begin
VAR68 = 1 ;
VAR1 = VAR1 + 1 ;
end
end
else
VAR68 = 0 ;
if ( VAR4 !== 0 )
begin
@(posedge VAR42) ;
VAR28.VAR71 ;
disable VAR70 ;
end
VAR55 = VAR35 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR28.VAR71 ;
end
VAR2 = 0 ;
end endtask
task VAR50 ;
input VAR37 VAR24 ;
inout VAR31 return ;
reg VAR2 ;
reg VAR11 VAR19 ;
reg VAR51 ;
reg VAR29 ;
integer VAR55 ;
integer VAR1 ;
reg VAR62 ;
begin:VAR70
VAR22 = 0 ;
VAR1 = 0 ;
if ( VAR2 === 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
if (VAR41 > VAR45)
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR2 = 1 ;
@(posedge VAR42) ;
VAR51 = VAR10 ;
VAR28.VAR23(VAR51, 1'b1, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR55 = VAR39 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR62 = 0 ;
while (VAR62 === 0)
begin
VAR19 = VAR6[VAR22] ;
VAR28.VAR59(VAR19, return) ;
if (VAR4 !== 0)
begin
@(posedge VAR42) ;
VAR28.VAR71 ;
disable VAR70 ;
end
if (VAR52 !== 0)
VAR62 = 1 ;
if (
(VAR53 !== 0) && (VAR53 !== 1) ||
(VAR13 !== 0) && (VAR13 !== 1) ||
(VAR52 !== 0) && (VAR52 !== 1)
)
begin
VAR62 = 1 ;
;
;
end
if ((VAR53 === 1) && (VAR65 !== 1))
VAR62 = 1 ;
if ((VAR53 === 1) && (VAR65 === 1))
begin
if ( VAR1 === VAR69 )
begin
;
VAR62 = 1 ;
end
else
begin
VAR1 = VAR1 + 1 ;
end
end
else
VAR1 = 0 ;
if (VAR26 === 0)
VAR62 = 1 ;
if (VAR22 === VAR41)
VAR62 = 1 ;
if ( VAR62 === 0 )
begin
VAR55 = VAR35 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
end
if ( (VAR62 === 0) && (VAR53 === 1) )
begin
VAR28.VAR71 ;
@(posedge VAR42) ;
VAR28.VAR23(VAR51, 1'b1, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
VAR62 = 1 ;
end
end
end
VAR28.VAR71 ;
VAR2 = 0 ;
end endtask
task VAR15 ;
input VAR37 VAR44 ;
inout VAR38 return ;
reg VAR2 ;
reg VAR72 VAR3 ;
reg VAR51 ;
reg VAR29 ;
integer VAR55 ;
integer VAR1 ;
reg VAR62 ;
integer VAR7 ;
begin:VAR70
VAR22 = 0 ;
VAR7 = 0 ;
VAR1 = 0 ;
if ( VAR2 === 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
if (VAR63 > VAR45)
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR2 = 1 ;
@(posedge VAR42) ;
VAR51 = VAR56 ;
VAR28.VAR23(VAR51, 1'b0, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
disable VAR70 ;
end
VAR55 = VAR67 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
VAR62 = 0 ;
while (VAR62 === 0)
begin
VAR3 = VAR54[VAR22] ;
VAR28.VAR8(VAR3, return) ;
if ( VAR7 !== VAR22 )
begin
VAR48[VAR7] = return ;
VAR7 = VAR22 ;
end
if (VAR4 !== 0)
begin
@(posedge VAR42) ;
VAR28.VAR71 ;
disable VAR70 ;
end
if (VAR52 !== 0)
VAR62 = 1 ;
if (
(VAR53 !== 0) && (VAR53 !== 1) ||
(VAR13 !== 0) && (VAR13 !== 1) ||
(VAR52 !== 0) && (VAR52 !== 1)
)
begin
VAR62 = 1 ;
;
;
end
if ((VAR53 === 1) && (VAR30 !== 1))
VAR62 = 1 ;
if ((VAR53 === 1) && (VAR30 === 1))
begin
if ( VAR1 === VAR69 )
begin
;
VAR62 = 1 ;
end
else
begin
VAR1 = VAR1 + 1 ;
end
end
else
VAR1 = 0 ;
if (VAR26 === 0)
VAR62 = 1 ;
if (VAR22 === VAR63)
VAR62 = 1 ;
if ( VAR62 === 0 )
begin
VAR55 = VAR73 ;
while ( VAR55 > 0 )
begin
@(posedge VAR42) ;
VAR55 = VAR55 - 1 ;
end
end
if ( (VAR62 === 0) && (VAR53 === 1) )
begin
VAR28.VAR71 ;
@(posedge VAR42) ;
VAR28.VAR23(VAR51, 1'b0, VAR29) ;
if ( VAR29 !== 1 )
begin
;
VAR4 = 1'b1 ;
VAR62 = 1 ;
end
end
end
VAR28.VAR71 ;
VAR2 = 0 ;
end endtask
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.blackbox.v
| 1,613 |
module MODULE1 (
VAR8 ,
VAR5 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR6,
VAR7 ,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR6;
input VAR7 ;
input VAR2 ;
input VAR4 ;
endmodule
|
apache-2.0
|
aj-michael/Digital-Systems
|
Lab2-Part2-Controller7SegmentDisplayKeypadScanner/Clock50MHz.v
| 5,606 |
module MODULE1
( input VAR27,
output VAR12,
output VAR46
);
VAR3 VAR39
(.VAR30 (VAR28),
.VAR15 (VAR27));
wire VAR24;
wire VAR22;
wire [7:0] VAR16;
wire VAR34;
wire VAR11;
wire VAR14;
VAR17
.VAR18 (1),
.VAR26 (4),
.VAR20 ("VAR23"),
.VAR33 (10.0),
.VAR31 ("VAR1"),
.VAR5 ("1X"),
.VAR8 ("VAR32"),
.VAR35 (0),
.VAR48 ("VAR23"))
VAR38
(.VAR7 (VAR28),
.VAR2 (VAR34),
.VAR6 (VAR11),
.VAR21 (),
.VAR29 (),
.VAR10 (),
.VAR47 (),
.VAR44 (),
.VAR4 (),
.VAR19 (),
.VAR42 (VAR14),
.VAR25 (1'b0),
.VAR13 (1'b0),
.VAR43 (1'b0),
.VAR36 (),
.VAR46 (VAR22),
.VAR9 (VAR16),
.VAR40 (1'b0),
.VAR45 (1'b0));
assign VAR46 = VAR22;
VAR41 VAR49
(.VAR30 (VAR34),
.VAR15 (VAR11));
VAR41 VAR37
(.VAR30 (VAR12),
.VAR15 (VAR14));
endmodule
|
mit
|
xuwenyihust/MapReduce_NoC
|
RTL/mapper_noc.v
| 5,250 |
module MODULE1(clk, rst, VAR24, VAR26, VAR17, VAR14, VAR36);
parameter VAR30 = 4'b0000;
parameter VAR22 = 4'b1111;
parameter VAR39 = 4'b0001;
parameter VAR28 = 4'b0010;
parameter VAR19 = 4'b0011;
parameter VAR7 = 10;
input clk;
input rst;
input [31:0] VAR24;
input VAR26;
input VAR17;
output reg [31:0] VAR14;
output reg VAR36;
reg [31:0] VAR33;
wire [31:0] VAR38;
reg [31:0] VAR34;
wire [31:0] VAR21;
wire VAR15;
reg VAR37;
reg [127:0] VAR32 [VAR7-1:0]; reg [4:0] VAR13; reg [4:0] VAR8;
reg [4:0] VAR27;
reg [2:0] VAR12;
reg [2:0] VAR10;
reg [3:0] VAR29;
reg [3:0] VAR2;
reg [2:0] VAR1;
reg VAR25;
reg VAR9;
reg [127:0] VAR35 [128:0];
reg [31:0] VAR4;
reg [31:0] VAR23;
reg VAR20;
reg [2:0] VAR3;
always@(posedge clk or negedge rst)
if(!rst) begin
VAR14 <= 0;
VAR36 <= 0;
VAR27 <= 0;
VAR10 <= 0;
end
else if(VAR27<VAR8 && VAR17==1) begin
VAR36 <= 1;
case(VAR10)
0: begin
VAR14 <= VAR32[VAR27][31:0];
VAR10 <= 1;
end
1: begin
VAR14 <= VAR32[VAR27][63:32];
VAR10 <= 2;
end
2: begin
VAR14 <= VAR32[VAR27][95:64];
VAR10 <= 3;
end
3: begin
VAR14 <= VAR32[VAR27][127:96];
VAR27 <= VAR27 + 1;
VAR10 <= 0;
end
default: begin
end
endcase
end
else begin
VAR36 <= 0;
VAR14 <= 0;
end
always@(posedge clk or negedge rst)
if(!rst)
VAR37 <= 0;
else
VAR37 <= VAR15;
always@(posedge clk or negedge rst)
if(!rst) begin
for(VAR13=0; VAR13<VAR7; VAR13=VAR13+1)
VAR32[VAR13] <= 0;
VAR12 <= 0;
VAR8 <= 0;
end
else if(VAR37 == 1) begin
case(VAR12)
0: begin
VAR32[VAR8][31:0] <= VAR21;
VAR12 <= 1;
end
1: begin
VAR32[VAR8][63:32] <= VAR21;
VAR12 <= 2;
end
2: begin
VAR32[VAR8][95:64] <= VAR21;
VAR12 <= 3;
end
3: begin
VAR32[VAR8][127:96] <= VAR21;
VAR12 <= 0;
VAR8 <= VAR8 + 1;
end
default: begin
VAR32[VAR8] <= VAR32[VAR8];
end
endcase
end
else
VAR32[VAR8] <= VAR32[VAR8];
assign VAR38 = (VAR25 == 1'b1)?VAR34:32'VAR5;
always@(posedge clk or negedge rst)
if(!rst)
VAR29 <= VAR30;
else
VAR29 <= VAR2;
always@*
case(VAR29)
VAR30: begin
if(VAR26 == 1'b1) VAR2 = VAR22;
end
else VAR2 = VAR30;
end
VAR22: begin
VAR2 = VAR39;
end
VAR39: begin
if(VAR1 == 3) VAR2 = VAR28;
end
else VAR2 = VAR39;
end
VAR28: begin
if( VAR23==VAR4 && VAR4!=0 ) VAR2 = VAR19;
end
else VAR2 = VAR28;
end
VAR19: begin
end
default: begin
VAR2 = VAR30;
end
endcase
always@(posedge clk)
case(VAR29)
VAR30: begin
VAR1 <= 0;
VAR25 <= 0;
VAR9 <= 0;
VAR4 <= 0;
VAR23 <= 0;
VAR3 <= 0;
end
VAR22: begin
end
VAR39: begin
VAR1 <= VAR1 + 1'd1;
VAR25 <= 1;
VAR34 <= VAR24[31:0];
end
VAR28: begin
VAR25 <= 0;
VAR9 <= 1;
if(VAR26 == 1)
VAR35[VAR4] <= VAR24;
end
else begin
end
if(VAR26==1 && VAR4 < 1024) begin
VAR4 <= VAR4 + 1;
end
else if(VAR4 < 1024) begin
VAR4 <= VAR4;
end
else begin
VAR4 <= 0;
end
if(VAR3 == 6) begin
VAR3 <=0;
end
else if(VAR3 == 1) begin
VAR20 <= 1'b1;
VAR3 <= VAR3 + 1;
VAR33 <= VAR35[VAR23];
VAR23 <= VAR23 + 1;
end
else if(VAR3 == 2) begin
VAR20 <= 1'b0;
VAR3 <= VAR3 + 1;
end
else
VAR3 <= VAR3 + 1;
end
default: begin
end
endcase
VAR16 VAR31(
.clk(clk),
.rst(rst),
.VAR6(VAR33),
.VAR11(VAR38),
.VAR25(VAR25),
.VAR20(VAR20),
.VAR18(),
.VAR21(VAR21),
.VAR15(VAR15));
endmodule
|
mit
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_port_channel_gate_32.v
| 7,035 |
module MODULE1 #(
parameter VAR38 = 9'd32,
parameter VAR30 = 8,
parameter VAR14 = VAR38+1
)
(
input VAR40,
input VAR37, output [VAR14-1:0] VAR8, output VAR29, input VAR27,
input VAR41, input VAR42, output VAR35, input VAR19, input [31:0] VAR22, input [30:0] VAR23, input [VAR38-1:0] VAR32, input VAR6, output VAR2 );
reg [1:0] VAR28=VAR25, VAR28=VAR25;
reg VAR36=0, VAR36=0;
reg [VAR14-1:0] VAR20=0, VAR20=0;
wire VAR9;
reg VAR5=0, VAR5=0;
reg VAR1=0, VAR1=0;
reg [31:0] VAR15=0, VAR15=0;
reg [30:0] VAR10=0, VAR10=0;
reg VAR12=0, VAR12=0;
reg VAR4=0, VAR4=0;
reg VAR13=0, VAR13=0;
assign VAR35 = VAR12;
assign VAR2 = (VAR28[1] & !VAR28[0] & !VAR9);
always @ (posedge VAR41) begin
VAR5 <= (VAR40 ? 1'd0 : VAR5);
VAR1 <= VAR1;
VAR15 <= VAR15;
VAR10 <= VAR10;
end
always @
VAR34 #(.VAR3(VAR14), .VAR31(VAR30)) VAR11 (
.VAR21(VAR41),
.VAR24(VAR40),
.VAR33(VAR36),
.VAR17(VAR20),
.VAR7(VAR9),
.VAR37(VAR37),
.VAR16(VAR40),
.VAR27(VAR27),
.VAR8(VAR8),
.VAR29(VAR29)
);
always @ (posedge VAR41) begin
VAR28 <= (VAR40 ? VAR25 : VAR28);
VAR36 <= (VAR40 ? 1'd0 : VAR36);
VAR20 <= VAR20;
VAR12 <= (VAR40 ? 1'd0 : VAR12);
VAR4 <= (VAR40 ? 1'd0 : VAR4);
VAR13 <= (VAR40 ? 1'd0 : VAR13);
end
always @ (*) begin
VAR28 = VAR28;
VAR36 = VAR36;
VAR20 = VAR20;
VAR4 = VAR4;
VAR12 = VAR12;
VAR13 = VAR13;
case (VAR28)
VAR13 = 0;
if (!VAR9) begin
VAR36 = VAR5;
VAR20 = {1'd1, VAR15};
if (VAR5)
VAR28 = VAR39;
end
end
if (!VAR9) begin
VAR12 = VAR5;
VAR20 = {1'd1, VAR10, VAR1};
if (VAR13 | !VAR5)
VAR28 = VAR18;
end
else
VAR28 = VAR26;
end
end
if (!VAR9) begin
VAR36 = VAR6; VAR20 = {1'd0, VAR32}; end
if (!VAR5)
VAR28 = VAR18;
end
if (!VAR9) begin
VAR4 = 1;
VAR36 = 1;
VAR20 = {1'd1, {VAR38{1'd0}}};
if (VAR4)
VAR28 = VAR25;
end
end
endcase
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.v
| 2,246 |
module MODULE2 (
VAR4 ,
VAR5 ,
VAR8 ,
VAR6 ,
VAR2,
VAR7 ,
VAR3
);
input VAR4 ;
input VAR5 ;
output VAR8 ;
output VAR6 ;
input VAR2;
input VAR7 ;
input VAR3 ;
VAR1 VAR9 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4 ,
VAR5 ,
VAR8 ,
VAR6 ,
VAR2
);
input VAR4 ;
input VAR5 ;
output VAR8 ;
output VAR6 ;
input VAR2;
supply1 VAR7;
supply0 VAR3;
VAR1 VAR9 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.symbol.v
| 1,315 |
module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR3,
input VAR2
);
endmodule
|
apache-2.0
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_hps_hps_io.v
| 6,777 |
module MODULE1 (
output wire [14:0] VAR12, output wire [2:0] VAR13, output wire VAR23, output wire VAR43, output wire VAR24, output wire VAR22, output wire VAR26, output wire VAR5, output wire VAR34, output wire VAR2, inout wire [31:0] VAR1, inout wire [3:0] VAR36, inout wire [3:0] VAR9, output wire VAR16, output wire [3:0] VAR10, input wire VAR39, output wire VAR3, output wire VAR31, output wire VAR25, output wire VAR19, output wire VAR15, input wire VAR14, inout wire VAR29, output wire VAR30, input wire VAR35, output wire VAR28, input wire VAR4, input wire VAR38, input wire VAR18, input wire VAR41, inout wire VAR7, inout wire VAR6, inout wire VAR8, output wire VAR32, inout wire VAR37, inout wire VAR33, input wire VAR42, output wire VAR20, inout wire VAR27, inout wire VAR21, inout wire VAR11 );
VAR17 VAR40 (
.VAR12 (VAR12), .VAR13 (VAR13), .VAR23 (VAR23), .VAR43 (VAR43), .VAR24 (VAR24), .VAR22 (VAR22), .VAR26 (VAR26), .VAR5 (VAR5), .VAR34 (VAR34), .VAR2 (VAR2), .VAR1 (VAR1), .VAR36 (VAR36), .VAR9 (VAR9), .VAR16 (VAR16), .VAR10 (VAR10), .VAR39 (VAR39), .VAR3 (VAR3), .VAR31 (VAR31), .VAR25 (VAR25), .VAR19 (VAR19), .VAR15 (VAR15), .VAR14 (VAR14), .VAR29 (VAR29), .VAR30 (VAR30), .VAR35 (VAR35), .VAR28 (VAR28), .VAR4 (VAR4), .VAR38 (VAR38), .VAR18 (VAR18), .VAR41 (VAR41), .VAR7 (VAR7), .VAR6 (VAR6), .VAR8 (VAR8), .VAR32 (VAR32), .VAR37 (VAR37), .VAR33 (VAR33), .VAR42 (VAR42), .VAR20 (VAR20), .VAR27 (VAR27), .VAR21 (VAR21), .VAR11 (VAR11) );
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.pp.blackbox.v
| 1,363 |
module MODULE1 (
VAR4 ,
VAR3,
VAR5 ,
VAR6 ,
VAR2 ,
VAR7 ,
VAR1
);
output VAR4 ;
input VAR3;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR1 ;
endmodule
|
apache-2.0
|
varunnagpaal/Digital-Hardware-Modelling
|
xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_pointer_basic_0_1/synth/design_1_pointer_basic_0_1.v
| 9,882 |
module MODULE1 (
VAR19,
VAR17,
VAR14,
VAR21,
VAR20,
VAR7,
VAR4,
VAR9,
VAR8,
VAR1,
VAR5,
VAR3,
VAR2,
VAR10,
VAR6,
VAR13,
VAR23,
VAR16,
VAR22,
interrupt
);
input wire [4 : 0] VAR19;
input wire VAR17;
output wire VAR14;
input wire [31 : 0] VAR21;
input wire [3 : 0] VAR20;
input wire VAR7;
output wire VAR4;
output wire [1 : 0] VAR9;
output wire VAR8;
input wire VAR1;
input wire [4 : 0] VAR5;
input wire VAR3;
output wire VAR2;
output wire [31 : 0] VAR10;
output wire [1 : 0] VAR6;
output wire VAR13;
input wire VAR23;
input wire VAR16;
input wire VAR22;
output wire interrupt;
VAR11 #(
.VAR12(5),
.VAR15(32)
) VAR18 (
.VAR19(VAR19),
.VAR17(VAR17),
.VAR14(VAR14),
.VAR21(VAR21),
.VAR20(VAR20),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR13(VAR13),
.VAR23(VAR23),
.VAR16(VAR16),
.VAR22(VAR22),
.interrupt(interrupt)
);
endmodule
|
mit
|
asicguy/gplgpu
|
hdl/altera_ddr3_128/alt_mem_ddrx_timing_param.v
| 65,943 |
module MODULE1 #
( parameter
VAR188 = 2,
VAR121 = "VAR69",
VAR64 = 3,
VAR178 = 5,
VAR37 = 4, VAR141 = 3, VAR27 = 4, VAR3 = 4, VAR103 = 6, VAR76 = 8, VAR87 = 13, VAR99 = 4, VAR90 = 4, VAR2 = 4, VAR23 = 4, VAR25 = 4, VAR175 = 5, VAR124 = 6, VAR95 = 3, VAR185 = 3, VAR114 = 10, VAR145 = 4, VAR80 = 16, VAR97 = 4,
VAR44 = 4,
VAR142 = 4,
VAR51 = 4,
VAR40 = 4,
VAR5 = 4,
VAR32 = 4,
VAR94 = 4,
VAR125 = 4,
VAR107 = 4,
VAR184 = 4,
VAR131 = 4,
VAR146 = 4,
VAR117 = 4,
VAR48 = 4,
VAR148 = 4,
VAR35 = 4,
VAR61 = 4,
VAR143 = 4,
VAR19 = 4,
VAR163 = 4,
VAR187 = 4,
VAR77 = 4,
VAR170 = 4,
VAR11 = 4,
VAR39 = 4,
VAR161 = 4,
VAR134 = 4,
VAR158 = 6, VAR122 = 6, VAR38 = 6, VAR65 = 6, VAR58 = 6, VAR172 = 6, VAR179 = 6, VAR109 = 6, VAR59 = 6, VAR116 = 6, VAR165 = 6, VAR108 = 6, VAR173 = 6, VAR15 = 6, VAR113 = 6, VAR160 = 6, VAR81 = 6, VAR9 = 6, VAR137 = 6, VAR46 = 6, VAR153 = 6, VAR12 = 8, VAR182 = 6, VAR119 = 10, VAR36 = 10, VAR6 = 13, VAR43 = 16, VAR17 = 6 )
(
VAR144,
VAR74,
VAR7,
VAR26,
VAR151,
VAR166,
VAR41,
VAR73,
VAR164,
VAR63,
VAR98,
VAR21,
VAR177,
VAR181,
VAR136,
VAR156,
VAR53,
VAR29,
VAR129,
VAR62,
VAR47,
VAR174,
VAR93,
VAR28,
VAR84,
VAR168,
VAR13,
VAR52,
VAR8,
VAR133,
VAR57,
VAR31,
VAR112,
VAR171,
VAR71,
VAR115,
VAR85,
VAR30,
VAR162,
VAR79,
VAR100,
VAR72,
VAR167,
VAR50,
VAR70,
VAR180,
VAR186,
VAR127,
VAR176,
VAR60,
VAR132,
VAR92,
VAR55,
VAR169,
VAR49,
VAR104,
VAR56,
VAR183,
VAR14,
VAR96,
VAR86,
VAR1,
VAR157,
VAR101,
VAR128,
VAR54,
VAR159,
VAR110,
VAR89,
VAR82,
VAR75,
VAR147,
VAR105,
VAR126,
VAR22,
VAR10,
VAR155,
VAR102,
VAR88
);
input VAR144;
input VAR74;
input [VAR178 - 1 : 0] VAR7;
input [VAR64 - 1 : 0] VAR26;
input [VAR37 - 1 : 0] VAR151;
input [VAR141 - 1 : 0] VAR166;
input [VAR27 - 1 : 0] VAR41;
input [VAR3 - 1 : 0] VAR73;
input [VAR103 - 1 : 0] VAR164;
input [VAR76 - 1 : 0] VAR63;
input [VAR87 - 1 : 0] VAR98;
input [VAR99 - 1 : 0] VAR21;
input [VAR90 - 1 : 0] VAR177;
input [VAR2 - 1 : 0] VAR181;
input [VAR23 - 1 : 0] VAR136;
input [VAR25 - 1 : 0] VAR156;
input [VAR175 - 1 : 0] VAR53;
input [VAR124 - 1 : 0] VAR29;
input [VAR95 - 1 : 0] VAR129;
input [VAR185 - 1 : 0] VAR62;
input [VAR114 - 1 : 0] VAR47;
input [VAR145 - 1 : 0] VAR174;
input [VAR80 - 1 : 0] VAR93;
input [VAR97 - 1 : 0] VAR28;
input [VAR44 - 1 : 0] VAR84;
input [VAR142 - 1 : 0] VAR168;
input [VAR51 - 1 : 0] VAR13;
input [VAR40 - 1 : 0] VAR52;
input [VAR5 - 1 : 0] VAR8;
input [VAR32 - 1 : 0] VAR133;
input [VAR94 - 1 : 0] VAR57;
input [VAR125 - 1 : 0] VAR31;
input [VAR107 - 1 : 0] VAR112;
input [VAR184 - 1 : 0] VAR171;
input [VAR131 - 1 : 0] VAR71;
input [VAR146 - 1 : 0] VAR115;
input [VAR117 - 1 : 0] VAR85;
input [VAR48 - 1 : 0] VAR30;
input [VAR148 - 1 : 0] VAR162;
input [VAR35 - 1 : 0] VAR79;
input [VAR61 - 1 : 0] VAR100;
input [VAR143 - 1 : 0] VAR72;
input [VAR19 - 1 : 0] VAR167;
input [VAR163 - 1 : 0] VAR50;
input [VAR187 - 1 : 0] VAR70;
input [VAR77 - 1 : 0] VAR180;
input [VAR170 - 1 : 0] VAR186;
input [VAR11 - 1 : 0] VAR127;
input [VAR39 - 1 : 0] VAR176;
input [VAR161 - 1 : 0] VAR60;
input [VAR134 - 1 : 0] VAR132;
output [VAR158 - 1 : 0] VAR92;
output [VAR122 - 1 : 0] VAR55;
output [VAR38 - 1 : 0] VAR169;
output [VAR65 - 1 : 0] VAR49;
output [VAR58 - 1 : 0] VAR104;
output [VAR172 - 1 : 0] VAR56;
output [VAR179 - 1 : 0] VAR183;
output [VAR109 - 1 : 0] VAR14;
output [VAR59 - 1 : 0] VAR96;
output [VAR116 - 1 : 0] VAR86;
output [VAR165 - 1 : 0] VAR1;
output [VAR108 - 1 : 0] VAR157;
output [VAR173 - 1 : 0] VAR101;
output [VAR15 - 1 : 0] VAR128;
output [VAR113 - 1 : 0] VAR54;
output [VAR160 - 1 : 0] VAR159;
output [VAR81 - 1 : 0] VAR110;
output [VAR9 - 1 : 0] VAR89;
output [VAR137 - 1 : 0] VAR82;
output [VAR46 - 1 : 0] VAR75;
output [VAR153 - 1 : 0] VAR147;
output [VAR12 - 1 : 0] VAR105;
output [VAR182 - 1 : 0] VAR126;
output [VAR119 - 1 : 0] VAR22;
output [VAR36 - 1 : 0] VAR10;
output [VAR6 - 1 : 0] VAR155;
output [VAR43 - 1 : 0] VAR102;
output [VAR17 - 1 : 0] VAR88;
reg [VAR158 - 1 : 0] VAR92;
reg [VAR122 - 1 : 0] VAR55;
reg [VAR38 - 1 : 0] VAR169;
reg [VAR65 - 1 : 0] VAR49;
reg [VAR58 - 1 : 0] VAR104;
reg [VAR172 - 1 : 0] VAR56;
reg [VAR179 - 1 : 0] VAR183;
reg [VAR109 - 1 : 0] VAR14;
reg [VAR59 - 1 : 0] VAR96;
reg [VAR116 - 1 : 0] VAR86;
reg [VAR165 - 1 : 0] VAR1;
reg [VAR108 - 1 : 0] VAR157;
reg [VAR173 - 1 : 0] VAR101;
reg [VAR15 - 1 : 0] VAR128;
reg [VAR113 - 1 : 0] VAR54;
reg [VAR160 - 1 : 0] VAR159;
reg [VAR81 - 1 : 0] VAR110;
reg [VAR9 - 1 : 0] VAR89;
reg [VAR137 - 1 : 0] VAR82;
reg [VAR46 - 1 : 0] VAR75;
reg [VAR153 - 1 : 0] VAR147;
reg [VAR12 - 1 : 0] VAR105;
reg [VAR182 - 1 : 0] VAR126;
reg [VAR119 - 1 : 0] VAR22;
reg [VAR36 - 1 : 0] VAR10;
reg [VAR6 - 1 : 0] VAR155;
reg [VAR43 - 1 : 0] VAR102;
reg [VAR17 - 1 : 0] VAR88;
localparam VAR18 = VAR188 / 2;
localparam VAR34 = VAR18;
localparam VAR152 = VAR18;
localparam VAR135 = VAR18;
localparam VAR83 = (
(VAR188 == 2 || VAR188 == 8) ?
(
VAR18 ) :
(
(VAR188 == 4) ?
(
(VAR121 == "VAR69") ? VAR18 : 1 ) :
(
VAR18 )
)
);
localparam VAR154 = (
(VAR188 == 2 || VAR188 == 8) ?
(
VAR18 ) :
(
(VAR188 == 4) ?
(
(VAR121 == "VAR138") ? VAR18 : 1 ) :
(
VAR18 )
)
);
localparam VAR67 = VAR154;
localparam VAR16 = 0;
localparam VAR123 = 0;
localparam VAR4 = 0;
localparam VAR118 = (VAR188 == 8) ? 2 : 0;
localparam VAR20 = (VAR188 == 8) ? 2 : 0;
localparam VAR68 = VAR20;
localparam VAR66 = 0;
localparam VAR140 = 0;
localparam VAR139 = 0;
localparam VAR33 = (
(VAR188 == 2) ?
(
0 ) :
(
(VAR121 == "VAR69") ? 0 : 1 )
);
localparam VAR42 = (
(VAR188 == 2) ?
(
0 ) :
(
(VAR121 == "VAR138") ? 0 : 1 )
);
localparam VAR111 = VAR42;
always @ (posedge VAR144 or negedge VAR74)
begin
if (!VAR74)
begin
VAR92 <= 0;
VAR55 <= 0;
VAR169 <= 0;
VAR89 <= 0;
VAR75 <= 0;
VAR147 <= 0;
VAR105 <= 0;
VAR126 <= 0;
VAR22 <= 0;
VAR155 <= 0;
VAR102 <= 0;
VAR88 <= 0;
end
else
begin
if (VAR166 >= (VAR21 - 1))
VAR92 <= 0 + VAR33 + VAR84 ;
end
else
VAR92 <= ((VAR21 - VAR166) / VAR18) + (((VAR21 - VAR166) % VAR83) > VAR118 ? 1 : 0) + VAR33 + VAR84 ;
VAR55 <= (VAR53 / VAR18) + ((VAR53 % VAR34) > VAR16 ? 1 : 0) + VAR66 + VAR168 ; VAR169 <= (VAR29 / VAR18) + ((VAR29 % VAR34) > VAR16 ? 1 : 0) + VAR66 + VAR13 ;
VAR89 <= (VAR177 / VAR18) + ((VAR177 % VAR34) > VAR16 ? 1 : 0) + VAR66 + VAR72 ;
VAR75 <= (VAR73 / VAR18) + ((VAR73 % VAR34) > VAR16 ? 1 : 0) + VAR66 + VAR50; VAR147 <= (VAR164 / VAR18) + ((VAR164 % VAR34) > VAR16 ? 1 : 0) + VAR66 + VAR70 ;
VAR105 <= (VAR63 / VAR18) + ((VAR63 % VAR67 ) > VAR16 ? 1 : 0) + VAR111 + VAR180 ; VAR126 <= (VAR174 / VAR18) + ((VAR174 % VAR67 ) > VAR16 ? 1 : 0) + VAR111 + VAR186 ; VAR22 <= (VAR47 / VAR18) + ((VAR47 % VAR67 ) > VAR16 ? 1 : 0) + VAR111 + VAR127 ;
VAR155 <= (VAR98 / VAR18) + ((VAR98 % VAR135 ) > VAR4 ? 1 : 0) + VAR139 + VAR60 ; VAR102 <= VAR93 + VAR139 + VAR132 ;
VAR88 <= (VAR28 / VAR18) + ((VAR28 % VAR135 ) > VAR4 ? 1 : 0) + VAR139 ; end
end
always @ (posedge VAR144 or negedge VAR74)
begin
if (!VAR74)
begin
VAR49 <= 0;
VAR104 <= 0;
VAR56 <= 0;
VAR183 <= 0;
VAR14 <= 0;
VAR96 <= 0;
VAR86 <= 0;
VAR1 <= 0;
VAR157 <= 0;
VAR101 <= 0;
VAR128 <= 0;
VAR54 <= 0;
VAR159 <= 0;
VAR110 <= 0;
VAR82 <= 0;
VAR10 <= 0;
end
else
begin
if (VAR26 == VAR130)
begin
VAR49 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR52 ; VAR104 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR8; VAR56 <= (((VAR7 / 2) + VAR41) / VAR18) + ((((VAR7 / 2) + VAR41) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR133 ; VAR183 <= 0 + VAR140 + VAR57 ; VAR14 <= (((VAR7 / 2) + 2) / VAR18) + ((((VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR31; VAR96 <= ((VAR7 / 2) / VAR18) + (((VAR7 / 2) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR112 ; VAR86 <= (((VAR7 / 2) + VAR177) / VAR18) + ((((VAR7 / 2) + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR171 ;
VAR1 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR71 ; VAR157 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR115; VAR101 <= ((1 + (VAR7 / 2) + VAR136) / VAR18) + (((1 + (VAR7 / 2) + VAR136) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR85 ; VAR128 <= 0 + VAR140 + VAR30 ; VAR54 <= (((VAR7 / 2) + 3) / VAR18) + ((((VAR7 / 2) + 3) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR162; VAR159 <= ((1 + (VAR7 / 2) + VAR181) / VAR18) + (((1 + (VAR7 / 2) + VAR181) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR79 ; VAR110 <= ((1 + (VAR7 / 2) + VAR181 + VAR177) / VAR18) + (((1 + (VAR7 / 2) + VAR181 + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR100 ;
VAR82 <= ((VAR177 + 1) / VAR18) + (((VAR177 + 1) % VAR67 ) > VAR68 ? 1 : 0) + VAR111 + VAR167 ;
VAR10 <= 0 + VAR139 + VAR176 ; end
else if (VAR26 == VAR78)
begin
VAR49 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR52 ; VAR104 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR8; VAR56 <= (((VAR7 / 2) + 2) / VAR18) + ((((VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR133 ; VAR183 <= 0 + VAR140 + VAR57 ; VAR14 <= (((VAR7 / 2) + 2) / VAR18) + ((((VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR31; VAR96 <= ((VAR166 + (VAR7 / 2) - 2 + VAR45(VAR156, 2)) / VAR18) + (((VAR166 + (VAR7 / 2) - 2 + VAR45(VAR156, 2)) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR112 ; VAR86 <= ((VAR166 + (VAR7 / 2) - 2 + VAR45(VAR156, 2) + VAR177) / VAR18) + (((VAR166 + (VAR7 / 2) - 2 + VAR45(VAR156, 2) + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR171 ;
VAR1 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR71 ; VAR157 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR115; VAR101 <= ((VAR41 - 1 + (VAR7 / 2) + VAR136) / VAR18) + (((VAR41 - 1 + (VAR7 / 2) + VAR136) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR85 ; VAR128 <= 0 + VAR140 + VAR30 ; VAR54 <= (((VAR7 / 2) + 1) / VAR18) + ((((VAR7 / 2) + 1) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR162; VAR159 <= ((VAR166 + VAR41 - 1 + (VAR7 / 2) + VAR181) / VAR18) + (((VAR166 + VAR41 - 1 + (VAR7 / 2) + VAR181) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR79 ; VAR110 <= ((VAR166 + VAR41 - 1 + (VAR7 / 2) + VAR181 + VAR177) / VAR18) + (((VAR166 + VAR41 - 1 + (VAR7 / 2) + VAR181 + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR100 ;
VAR82 <= ((VAR177 + 1) / VAR18) + (((VAR177 + 1) % VAR67 ) > VAR68 ? 1 : 0) + VAR111 + VAR167 ;
VAR10 <= 0 + VAR139 + VAR176 ; end
else if (VAR26 == VAR150)
begin
VAR49 <= ((VAR7 / 2) / VAR18) + VAR140 + VAR52 ; VAR104 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR8; VAR56 <= ((VAR41 - VAR151 + (VAR7 / 2) + 2) / VAR18) + (((VAR41 - VAR151 + (VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR133 ; VAR183 <= ((VAR41 - VAR151 + (VAR7 / 4) + 2) / VAR18) + (((VAR41 - VAR151 + (VAR7 / 4) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR57 ; VAR14 <= ((VAR41 - VAR151 + (VAR7 / 2) + 2) / VAR18) + (((VAR41 - VAR151 + (VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR31; VAR96 <= ((VAR166 + VAR45(VAR156, 4)) / VAR18) + (((VAR166 + VAR45(VAR156, 4)) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR112 ; VAR86 <= ((VAR166 + VAR45(VAR156, 4) + VAR177) / VAR18) + (((VAR166 + VAR45(VAR156, 4) + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR171 ;
VAR1 <= ((VAR7 / 2) / VAR18) + VAR140 + VAR71 ; VAR157 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR115; VAR101 <= ((VAR151 + (VAR7 / 2) + VAR45(VAR136, 4)) / VAR18) + (((VAR151 + (VAR7 / 2) + VAR45(VAR136, 4)) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR85 ; VAR128 <= ((VAR151 + (VAR7 / 2) + VAR45(VAR136, 4)) / VAR18) + (((VAR151 + (VAR7 / 2) + VAR45(VAR136, 4)) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR30 ; VAR54 <= (((VAR151 - VAR41) + (VAR7 / 2) + 2) / VAR18) + ((((VAR151 - VAR41) + (VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR162; VAR159 <= ((VAR166 + VAR151 + (VAR7 / 2) + VAR181) / VAR18) + (((VAR166 + VAR151 + (VAR7 / 2) + VAR181) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR79 ; VAR110 <= ((VAR166 + VAR151 + (VAR7 / 2) + VAR181 + VAR177) / VAR18) + (((VAR166 + VAR151 + (VAR7 / 2) + VAR181 + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR100 ;
VAR82 <= (VAR177 / VAR18) + ((VAR177 % VAR67 ) > VAR68 ? 1 : 0) + VAR111 + VAR167 ;
VAR10 <= ((VAR47 / 2) / VAR18) + VAR139 + VAR176 ; end
else if (VAR26 == VAR149)
begin
VAR49 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR52 ; VAR104 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR8; VAR56 <= (((VAR7 / 2) + VAR41) / VAR18) + ((((VAR7 / 2) + VAR41) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR133 ; VAR183 <= 0 + VAR140 + VAR57 ; VAR14 <= (((VAR7 / 2) + 2) / VAR18) + ((((VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR31; VAR96 <= ((VAR7 / 2) / VAR18) + (((VAR7 / 2) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR112 ; VAR86 <= (((VAR7 / 2) + VAR177) / VAR18) + ((((VAR7 / 2) + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR171 ;
VAR1 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR71 ; VAR157 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR115; VAR101 <= ((1 + (VAR7 / 2) + VAR136) / VAR18) + (((1 + (VAR7 / 2) + VAR136) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR85 ; VAR128 <= 0 + VAR140 + VAR30 ; VAR54 <= (((VAR7 / 2) + 3) / VAR18) + ((((VAR7 / 2) + 3) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR162; VAR159 <= ((1 + (VAR7 / 2) + VAR181) / VAR18) + (((1 + (VAR7 / 2) + VAR181) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR79 ; VAR110 <= ((1 + (VAR7 / 2) + VAR181 + VAR177) / VAR18) + (((1 + (VAR7 / 2) + VAR181 + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR100 ;
VAR82 <= ((VAR177 + 1) / VAR18) + (((VAR177 + 1) % VAR67 ) > VAR68 ? 1 : 0) + VAR111 + VAR167 ;
VAR10 <= 0 + VAR139 + VAR176 ; end
else if (VAR26 == VAR91)
begin
VAR49 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR52 ; VAR104 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR8; VAR56 <= ((VAR41 - VAR151 + (VAR7 / 2) + 1) / VAR18) + (((VAR41 - VAR151 + (VAR7 / 2) + 1) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR133 ; VAR183 <= 0 + VAR140 + VAR57 ; VAR14 <= ((VAR41 - VAR151 + (VAR7 / 2) + 1) / VAR18) + (((VAR41 - VAR151 + (VAR7 / 2) + 1) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR31; VAR96 <= ((VAR166 + (VAR7 / 2) - VAR129 + VAR45(VAR156, 2)) / VAR18) + (((VAR166 + (VAR7 / 2) - VAR129 + VAR45(VAR156, 2)) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR112 ; VAR86 <= ((VAR166 + (VAR7 / 2) - VAR129 + VAR45(VAR156, 2) + VAR177) / VAR18) + (((VAR166 + (VAR7 / 2) - VAR129 + VAR45(VAR156, 2) + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR171 ;
VAR1 <= (VAR129 / VAR18) + ((VAR129 % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR71 ; VAR157 <= (((VAR7 / 2) + 2) / VAR18) + VAR140 + VAR115; VAR101 <= ((VAR151 + (VAR7 / 2) + VAR45(VAR136, 2) + 1) / VAR18) + (((VAR151 + (VAR7 / 2) + VAR45(VAR136, 2) + 1) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR85 ; VAR128 <= 0 + VAR140 + VAR30 ; VAR54 <= (((VAR151 - VAR41) + (VAR7 / 2) + 2) / VAR18) + ((((VAR151 - VAR41) + (VAR7 / 2) + 2) % VAR152) > VAR123 ? 1 : 0) + VAR140 + VAR162; VAR159 <= ((VAR166 + VAR151 + (VAR7 / 2) + VAR181 + 1) / VAR18) + (((VAR166 + VAR151 + (VAR7 / 2) + VAR181 + 1) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR79 ; VAR110 <= ((VAR166 + VAR151 + (VAR7 / 2) + VAR181 + 1 + VAR177) / VAR18) + (((VAR166 + VAR151 + (VAR7 / 2) + VAR181 + 1 + VAR177) % VAR154) > VAR20 ? 1 : 0) + VAR42 + VAR100 ;
VAR82 <= ((VAR177 + 1) / VAR18) + (((VAR177 + 1) % VAR67 ) > VAR68 ? 1 : 0) + VAR111 + VAR167 ;
VAR10 <= 0 + VAR139 + VAR176 ; end
end
end
localparam VAR120 = (VAR25 > VAR23) ? VAR25 : VAR23;
function [VAR120 - 1 : 0] VAR45;
input [VAR120 - 1 : 0] VAR24;
input [VAR120 - 1 : 0] VAR106;
begin
if (VAR24 > VAR106)
VAR45 = VAR24;
end
else
VAR45 = VAR106;
end
endfunction
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/buf/sky130_fd_sc_hvl__buf.blackbox.v
| 1,206 |
module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/or4/sky130_fd_sc_hdll__or4.blackbox.v
| 1,277 |
module MODULE1 (
VAR8,
VAR9,
VAR5,
VAR2,
VAR6
);
output VAR8;
input VAR9;
input VAR5;
input VAR2;
input VAR6;
supply1 VAR7;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
cwilkens/ecen4024-microphone-array
|
microphone-array/microphone-array.srcs/sources_1/new/main_array.v
| 21,707 |
module MODULE1(
input clk,
output reg VAR22,
output VAR6,
input [12:0] VAR38,
input [15:0] VAR55,
output reg [15:0] VAR88,
output VAR87,
output VAR77,
output reg [11:0] VAR18,
output VAR57,
output VAR56,
output VAR90,
output [7:0] VAR29,
output [7:0] VAR24,
output VAR69
);
assign VAR69 = VAR12[0];
assign VAR57 = 1'b0;
assign VAR6 = VAR22;
wire VAR3;
reg VAR74;
wire VAR33;
VAR14 VAR89(.VAR72(clk), .VAR50(VAR3), .reset(1'b0));
VAR65 VAR81(.VAR72(clk), .VAR50(VAR33), .reset(1'b0));
parameter signed VAR58 = 17;
parameter VAR17 = 13;
reg signed [6:0] VAR91; reg signed [5:0] VAR84; reg [15:0] VAR54; reg [2:0] VAR8;
reg signed [5:0] VAR31; reg signed [5:0] VAR66; reg signed [47:0] VAR5;
reg signed [47:0] VAR28;
reg signed [5:0] VAR82; reg signed [5:0] VAR11;
VAR10(.clk(VAR22), .VAR84(VAR82), .VAR45(VAR11), .VAR76(VAR29), .VAR40(VAR24));
wire VAR92;
wire signed [11:0] VAR60, VAR71;
VAR2(.rst(1'b0), .VAR59(VAR33), .VAR78(VAR87), .VAR51(VAR77), .VAR60(VAR60[10:0]), .VAR71(VAR71[10:0]), .VAR92(VAR92));
reg signed [19:0] VAR62; reg signed [19:0] VAR85; reg signed [15:0] VAR63;
reg [7:0] VAR32[0:VAR17];
wire VAR37[0:VAR17];
wire VAR61[0:VAR17];
wire VAR42[0:VAR17];
wire VAR53[0:VAR17];
wire VAR36[0:VAR17];
wire VAR12[0:VAR17];
wire VAR48[0:VAR17];
wire [23:0] VAR68[0:VAR17];
wire [23:0] VAR75[0:VAR17];
wire [23:0] VAR73[0:VAR17];
wire [15:0] VAR44[0:VAR17];
wire signed [15:0] VAR1[0:VAR17];
reg signed [6:0] VAR15[0:VAR17];
reg signed [47:0] VAR41[0:VAR58*2]; reg signed [47:0] VAR46[0:VAR58*2]; reg signed [47:0] VAR35[0:VAR58*2]; reg signed [47:0] VAR30[0:VAR58*2];
genvar VAR67;
integer VAR70;
generate
for(VAR67 = 0; VAR67 < VAR17; VAR67 = VAR67+1) begin
VAR27 VAR80(.VAR79(VAR22),
.VAR9(VAR32[VAR67]),
.VAR20(1'b1),
.VAR16(VAR37[VAR67]),
.VAR47(VAR68[VAR67]),
.VAR4(VAR61[VAR67])
);
VAR64 VAR13(.VAR79(VAR22),
.VAR9(VAR68[VAR67]),
.VAR20(VAR61[VAR67]),
.VAR16(VAR42[VAR67]),
.VAR47(VAR75[VAR67]),
.VAR4(VAR53[VAR67])
);
VAR83 VAR23(.VAR79(VAR22),
.VAR9(VAR75[VAR67]),
.VAR20(VAR53[VAR67]),
.VAR16(VAR36[VAR67]),
.VAR47(VAR73[VAR67]),
.VAR4(VAR12[VAR67])
);
VAR86 VAR26(.VAR43(VAR22),
.VAR52(1'b0),
.VAR34(VAR12[VAR67]),
.VAR19(VAR73[VAR67][16:1]),
.VAR21(VAR44[VAR67])
);
VAR7 VAR39(.clk(VAR22),
.VAR25(VAR91),
.VAR19(VAR44[VAR67]),
.VAR49(VAR15[VAR67]),
.VAR21(VAR1[VAR67])
);
end
endgenerate
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dfstp/sky130_fd_sc_ls__dfstp.symbol.v
| 1,387 |
module MODULE1 (
input VAR7 ,
output VAR8 ,
input VAR2,
input VAR1
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.functional.v
| 1,158 |
module MODULE1( VAR5, VAR1, VAR12 );
input VAR1, VAR5;
output VAR12;
wire VAR2;
and VAR11( VAR2, VAR1, VAR5 );
wire VAR3;
not VAR4( VAR3, VAR1 );
wire VAR8;
not VAR9( VAR8, VAR5 );
wire VAR7;
and VAR10( VAR7, VAR3, VAR8 );
or VAR6( VAR12, VAR2, VAR7 );
endmodule
|
apache-2.0
|
revaldinho/opc
|
system/src/uart.v
| 2,104 |
module MODULE1 ( input[15:0] din, output[15:0] dout, input VAR12, input VAR9, input clk, input VAR3, input VAR13, input VAR8, output VAR1);
parameter VAR18 = 32000000;
parameter VAR19 = 115200;
parameter VAR4 = VAR18 / VAR19;
reg [15:0] VAR10 = 0;
reg [15:0] VAR6;
reg [10:0] VAR5;
reg [9:0] VAR14;
reg VAR7;
reg VAR2;
reg VAR15 = 1'b0;
reg [7:0] VAR17;
wire VAR11;
wire VAR16;
assign VAR11 = VAR14 != 10'b1111111111;
assign VAR16 = VAR5 != 11'b1;
assign VAR1 = VAR5[0];
assign dout = VAR12 ? {8'h00, VAR17} : { VAR16, VAR15, 14'b0};
always @ (posedge clk) begin
VAR7 <= VAR8;
VAR2 <= VAR7;
if (!VAR13 && VAR9 && VAR12) begin
VAR15 <= 1'b0;
end
if (!VAR3) begin
VAR14 <= 10'b1111111111;
end else if (!VAR14[0]) begin
VAR14 <= 10'b1111111111;
VAR17 <= VAR14[9:2];
VAR15 <= 1;
end else if (VAR11) begin
if (VAR10 == 0) begin
VAR10 <= VAR4;
VAR14 <= {VAR7 , VAR14[9:1]};
end else begin
VAR10 <= VAR10 - 1;
end
end else if (!VAR7 && VAR2) begin
VAR14 <= 10'b0111111111;
VAR10 <= VAR4 >> 1;
end
end
always @ (posedge clk)
if (!VAR3) begin
VAR5 <= 11'b1;
end else if (VAR16) begin
if (VAR6 == 0) begin
VAR5 <= {1'b0 , VAR5[10:1]};
VAR6 <= VAR4 - 1;
end else begin
VAR6 <= VAR6 - 1;
end
end else if (!VAR13 && !VAR9 && VAR12) begin
VAR5 <= {2'b11, din[7:0], 1'b0};
VAR6 <= VAR4 - 1;
end
endmodule
|
gpl-3.0
|
parallella/oh
|
common/hdl/oh_add.v
| 1,181 |
module MODULE1 #(parameter VAR7 = 1 )
(
input [VAR7-1:0] VAR4, input [VAR7-1:0] VAR9, input VAR2, input VAR5, output [VAR7-1:0] sum, output VAR8, output VAR3, output neg, output VAR6 );
wire [VAR7-1:0] VAR1;
assign VAR1[VAR7-1:0] = {(VAR7){VAR2}} ^ VAR9[VAR7-1:0];
assign {VAR8,sum[VAR7-1:0]} = VAR4[VAR7-1:0] +
VAR1[VAR7-1:0] +
VAR2 +
VAR5;
endmodule
|
mit
|
Canaan-Creative/MM
|
verilog/superkdf9/components/alink/txc.v
| 4,559 |
module MODULE1(
input clk ,
input rst ,
input VAR11 ,
input [VAR16-1:0] VAR13 ,
input VAR20 ,
input [31:0] VAR4 ,
input VAR9 ,
output VAR1,
output reg [VAR16-1:0]VAR5 ,
input VAR10 ,
output reg [1:0] VAR6 ,
output reg [1:0] VAR17 ,
output [32*VAR16-1:0] VAR21 ,output [VAR16-1:0] VAR3
);
parameter VAR15 = 2'b00 ;
parameter VAR19 = 2'b01 ;
parameter VAR12 = 2'b10 ;
wire [VAR16-1:0] VAR7 ;
wire [VAR16-1:0] VAR8 ;
assign VAR1 = VAR6 == VAR19 && VAR17 == VAR12 ;
genvar VAR18 ;
generate
for( VAR18=0 ; VAR18 < VAR16 ; VAR18 = VAR18 + 1 ) begin : VAR2
assign VAR7[VAR18] = VAR20 & VAR5[VAR18] ;
VAR14 VAR14(
.clk (clk ) ,
.rst (rst ) ,
.VAR11 (VAR11 ) ,
.VAR4 (VAR4 ) ,
.VAR7 (VAR7[VAR18] ) ,
.VAR8 (VAR8[VAR18] ) ,
.VAR21 (VAR21[VAR18*32+32-1:VAR18*32] )
);
assign VAR3[VAR18] = VAR7[VAR18] | VAR8[VAR18] ;
end
endgenerate
always @ ( posedge clk ) begin
if( rst || VAR11 )
VAR6 <= VAR15 ;
end
else
VAR6 <= VAR17 ;
end
always @ ( * ) begin
VAR17 = VAR6 ;
case( VAR6 )
VAR15: if( |VAR5 ) VAR17 = VAR19 ;
VAR19 : if( VAR9 ) VAR17 = VAR12 ;
VAR12: if( VAR10 ) VAR17 = VAR15 ;
default : VAR17 = VAR15 ;
endcase
end
always @ ( posedge clk ) begin
if( rst || VAR11 || (VAR6 == VAR12 && VAR17 == VAR15))
VAR5 <= 32'b0 ;
end
else if( VAR6 == VAR15 ) begin
if( ~VAR3[0 ]&&VAR13[0 ] ) VAR5 <= 32'b1<<0 ;
end
else if( ~VAR3[1 ]&&VAR13[1 ] ) VAR5 <= 32'b1<<1 ;
else if( ~VAR3[2 ]&&VAR13[2 ] ) VAR5 <= 32'b1<<2 ;
else if( ~VAR3[3 ]&&VAR13[3 ] ) VAR5 <= 32'b1<<3 ;
else if( ~VAR3[4 ]&&VAR13[4 ] ) VAR5 <= 32'b1<<4 ;
else if( ~VAR3[5 ]&&VAR13[5 ] ) VAR5 <= 32'b1<<5 ;
else if( ~VAR3[6 ]&&VAR13[6 ] ) VAR5 <= 32'b1<<6 ;
else if( ~VAR3[7 ]&&VAR13[7 ] ) VAR5 <= 32'b1<<7 ;
else if( ~VAR3[8 ]&&VAR13[8 ] ) VAR5 <= 32'b1<<8 ;
else if( ~VAR3[9 ]&&VAR13[9 ] ) VAR5 <= 32'b1<<9 ;
else if( ~VAR3[10]&&VAR13[10] ) VAR5 <= 32'b1<<10 ;
else if( ~VAR3[11]&&VAR13[11] ) VAR5 <= 32'b1<<11 ;
else if( ~VAR3[12]&&VAR13[12] ) VAR5 <= 32'b1<<12 ;
else if( ~VAR3[13]&&VAR13[13] ) VAR5 <= 32'b1<<13 ;
else if( ~VAR3[14]&&VAR13[14] ) VAR5 <= 32'b1<<14 ;
else if( ~VAR3[15]&&VAR13[15] ) VAR5 <= 32'b1<<15 ;
else if( ~VAR3[16]&&VAR13[16] ) VAR5 <= 32'b1<<16 ;
else if( ~VAR3[17]&&VAR13[17] ) VAR5 <= 32'b1<<17 ;
else if( ~VAR3[18]&&VAR13[18] ) VAR5 <= 32'b1<<18 ;
else if( ~VAR3[19]&&VAR13[19] ) VAR5 <= 32'b1<<19 ;
else if( ~VAR3[20]&&VAR13[20] ) VAR5 <= 32'b1<<20 ;
else if( ~VAR3[21]&&VAR13[21] ) VAR5 <= 32'b1<<21 ;
else if( ~VAR3[22]&&VAR13[22] ) VAR5 <= 32'b1<<22 ;
else if( ~VAR3[23]&&VAR13[23] ) VAR5 <= 32'b1<<23 ;
else if( ~VAR3[24]&&VAR13[24] ) VAR5 <= 32'b1<<24 ;
else if( ~VAR3[25]&&VAR13[25] ) VAR5 <= 32'b1<<25 ;
else if( ~VAR3[26]&&VAR13[26] ) VAR5 <= 32'b1<<26 ;
else if( ~VAR3[27]&&VAR13[27] ) VAR5 <= 32'b1<<27 ;
else if( ~VAR3[28]&&VAR13[28] ) VAR5 <= 32'b1<<28 ;
else if( ~VAR3[29]&&VAR13[29] ) VAR5 <= 32'b1<<29 ;
else if( ~VAR3[30]&&VAR13[30] ) VAR5 <= 32'b1<<30 ;
else if( ~VAR3[31]&&VAR13[31] ) VAR5 <= 32'b1<<31 ;
else VAR5 <= 32'b0 ;
end
end
endmodule
|
unlicense
|
MegaShow/college-programming
|
Homework/Computer Organization and Interfacing/Multi Cycle CPU/Multi Cycle CPU.srcs/sources_1/new/CPU.v
| 4,842 |
module MODULE1(
input clk,
input reset,
output wire [2:0] state,
output wire [31:0] VAR57,
output wire [31:0] VAR72,
output wire [31:0] VAR95,
output wire [31:0] VAR1,
output wire [31:0] VAR23,
output wire [31:0] VAR31,
output wire [31:0] VAR45,
output wire [31:0] VAR30
);
reg VAR20;
wire [31:0] VAR87;
wire [31:0] VAR42, VAR2;
wire [31:0] VAR82, VAR95, VAR81;
wire [31:0] VAR86, VAR13, VAR51;
wire [31:0] VAR50;
wire [31:0] VAR80;
wire [4:0] VAR59;
wire [31:0] VAR73, VAR54, VAR90, VAR75;
wire VAR26, VAR71;
wire VAR97;
wire [1:0] VAR55;
wire VAR48;
wire VAR16, VAR88;
wire [2:0] VAR84;
wire VAR65, VAR78, VAR74, VAR49, VAR6;
wire VAR28, VAR44;
wire [1:0] VAR12;
assign VAR57 = (VAR81[31:26] == 6'VAR19 ? VAR72 : VAR86);
assign VAR82 = 32'VAR85;
VAR61 VAR9(
.VAR34(32'VAR24),
.VAR67(VAR72),
.VAR76(VAR13)
);
VAR61 VAR3(
.VAR34(VAR13),
.VAR67({ VAR50[29:0], 2'VAR85 }),
.VAR76(VAR51)
);
VAR52 alu(
.VAR34(VAR42),
.VAR67(VAR2),
.VAR58(VAR84),
.VAR26(VAR26),
.VAR71(VAR71),
.VAR76(VAR45)
);
VAR29 VAR89(
.VAR58(VAR81[31:26]),
.clk(clk),
.rst(reset),
.state(state),
.VAR26(VAR26),
.VAR71(VAR71),
.VAR97(VAR97),
.VAR55(VAR55),
.VAR48(VAR48),
.VAR16(VAR16),
.VAR88(VAR88),
.VAR84(VAR84),
.VAR65(VAR65),
.VAR78(VAR78),
.VAR74(VAR74),
.VAR49(VAR49),
.VAR6(VAR6),
.VAR28(VAR28),
.VAR44(VAR44),
.VAR12(VAR12)
);
VAR53 VAR98(
.VAR10(VAR74),
.VAR37(VAR49),
.address(VAR73),
.VAR22(VAR75),
.VAR35(VAR30)
);
VAR47 VAR17(
.clk(clk),
.VAR22(VAR1),
.VAR35(VAR90)
);
VAR47 VAR70(
.clk(clk),
.VAR22(VAR23),
.VAR35(VAR75)
);
VAR47 VAR7(
.clk(clk),
.VAR22(VAR45),
.VAR35(VAR73)
);
VAR47 VAR63(
.clk(clk),
.VAR22(VAR54),
.VAR35(VAR31)
);
VAR93 VAR40(
.VAR41(VAR97),
.VAR22(VAR81[15:0]),
.VAR35(VAR50)
);
VAR83 VAR36(
.VAR25(VAR65),
.address(VAR72),
.VAR22(VAR82),
.VAR35(VAR95)
);
VAR27 VAR92(
.clk(clk),
.VAR78(VAR78),
.VAR22(VAR95),
.VAR35(VAR81)
);
VAR46 VAR39(
.clk(clk),
.reset(reset),
.VAR37(VAR48),
.VAR96(VAR86),
.VAR43(VAR72)
);
VAR4 VAR91(
.clk(clk),
.VAR20(VAR20),
.VAR37(VAR28),
.VAR79(VAR81[25:21]),
.VAR66(VAR81[20:16]),
.VAR94(VAR59),
.VAR38(VAR80),
.VAR69(VAR1),
.VAR15(VAR23)
);
VAR62 VAR5(
.VAR41(VAR16),
.VAR21(VAR90),
.VAR77({ 27'VAR85, VAR81[10:6] }),
.VAR35(VAR42)
);
VAR62 VAR11(
.VAR41(VAR88),
.VAR21(VAR75),
.VAR77(VAR50),
.VAR35(VAR2)
);
VAR62 VAR32(
.VAR41(VAR6),
.VAR21(VAR45),
.VAR77(VAR30),
.VAR35(VAR54)
);
VAR62 VAR18(
.VAR41(VAR44),
.VAR21(VAR13),
.VAR77(VAR31),
.VAR35(VAR80)
);
VAR14 VAR33(
.VAR41(VAR12),
.VAR21({ 27'VAR85, 5'VAR8 }),
.VAR77({ 27'VAR85, VAR81[20:16] }),
.VAR64({ 27'VAR85, VAR81[15:11] }),
.VAR56(32'VAR68),
.VAR35({ VAR87[31:5] , VAR59 })
);
VAR14 VAR60(
.VAR41(VAR55),
.VAR21(VAR13),
.VAR77(VAR51),
.VAR64(VAR1),
.VAR56({ VAR13[31:28], VAR81[25:0], 2'VAR85 }),
.VAR35(VAR86)
);
|
mit
|
eda-globetrotter/PicenoDecoders
|
extra_credit/syn/netlist/ham_15_11_decoder.syn.v
| 1,230 |
module MODULE1 ( VAR4, VAR37 );
input [10:0] VAR4;
output [14:0] VAR37;
wire VAR24, VAR18, VAR14, VAR38, VAR13, VAR26, VAR20, VAR7, VAR25, VAR27, VAR17, VAR36, VAR16, VAR15;
assign VAR37[14] = VAR4[10];
assign VAR37[13] = VAR4[9];
assign VAR37[12] = VAR4[8];
assign VAR37[11] = VAR4[7];
assign VAR37[10] = VAR4[6];
assign VAR37[9] = VAR4[5];
assign VAR37[8] = VAR4[4];
assign VAR37[6] = VAR4[3];
assign VAR37[5] = VAR4[2];
assign VAR37[4] = VAR4[1];
assign VAR37[2] = VAR4[0];
VAR30 VAR39 ( .VAR9(VAR24), .VAR10(VAR18), .VAR8(VAR37[7]) );
VAR30 VAR22 ( .VAR9(VAR4[7]), .VAR10(VAR14), .VAR8(VAR18) );
VAR30 VAR31 ( .VAR9(VAR38), .VAR10(VAR13), .VAR8(VAR37[3]) );
VAR30 VAR6 ( .VAR9(VAR26), .VAR10(VAR20), .VAR8(VAR13) );
VAR30 VAR21 ( .VAR9(VAR4[2]), .VAR10(VAR4[10]), .VAR8(VAR20) );
VAR30 VAR11 ( .VAR9(VAR4[7]), .VAR10(VAR7), .VAR8(VAR38) );
VAR30 VAR12 ( .VAR9(VAR4[9]), .VAR10(VAR4[8]), .VAR8(VAR7) );
VAR30 VAR32 ( .VAR9(VAR25), .VAR10(VAR27), .VAR8(VAR37[1]) );
VAR30 VAR33 ( .VAR9(VAR14), .VAR10(VAR17), .VAR8(VAR27) );
VAR30 VAR1 ( .VAR9(VAR4[9]), .VAR10(VAR4[5]), .VAR8(VAR14) );
VAR30 VAR2 ( .VAR9(VAR4[0]), .VAR10(VAR36), .VAR8(VAR25) );
VAR30 VAR23 ( .VAR9(VAR4[3]), .VAR10(VAR4[2]), .VAR8(VAR36) );
VAR30 VAR5 ( .VAR9(VAR26), .VAR10(VAR16), .VAR8(VAR37[0]) );
VAR30 VAR29 ( .VAR9(VAR4[0]), .VAR10(VAR24), .VAR8(VAR16) );
VAR19 VAR28 ( .VAR9(VAR15), .VAR10(VAR17), .VAR8(VAR24) );
VAR30 VAR35 ( .VAR9(VAR4[10]), .VAR10(VAR4[6]), .VAR8(VAR17) );
VAR19 VAR34 ( .VAR9(VAR4[8]), .VAR10(VAR4[4]), .VAR8(VAR15) );
VAR30 VAR3 ( .VAR9(VAR4[3]), .VAR10(VAR4[1]), .VAR8(VAR26) );
endmodule
|
mit
|
marqs85/ossc
|
ip/i2c_opencores/i2c_master_byte_ctrl.v
| 12,096 |
module MODULE1 (
clk, rst, VAR41, VAR32, VAR7, VAR6, VAR23, read, write, VAR22, VAR25, din,
VAR39, VAR2, dout, VAR3, VAR46, VAR30, VAR48, VAR42, VAR49, VAR19, VAR44, VAR38 );
parameter VAR35 = 0;
input clk; input rst; input VAR41; input VAR32;
input [15:0] VAR7;
input VAR6;
input VAR23;
input read;
input write;
input VAR22;
input VAR25;
input [7:0] din;
output VAR39;
reg VAR39;
output VAR2;
reg VAR2;
output VAR3;
output VAR46;
output [7:0] dout;
input VAR30;
output VAR48;
output VAR42;
input VAR49;
output VAR19;
output VAR44;
input VAR38;
parameter [6:0] VAR50 = 7'b0000000;
parameter [6:0] VAR5 = 7'b0000001;
parameter [6:0] VAR21 = 7'b0000010;
parameter [6:0] VAR13 = 7'b0000100;
parameter [6:0] VAR37 = 7'b0001000;
parameter [6:0] VAR11 = 7'b0010000;
parameter [6:0] VAR1 = 7'b0100000;
parameter [6:0] VAR47 = 7'b1000000;
reg [5:0] VAR8;
reg VAR29;
wire VAR10, VAR40;
reg [7:0] VAR17; reg VAR14, VAR12;
wire VAR4;
reg [2:0] VAR24;
wire VAR31;
VAR27 #(.VAR35(VAR35)) VAR34 (
.clk ( clk ),
.rst ( rst ),
.VAR41 ( VAR41 ),
.VAR32 ( VAR32 ),
.VAR7 ( VAR7 ),
.VAR26 ( VAR8 ),
.VAR39 ( VAR10 ),
.VAR28 ( VAR3 ),
.VAR45 ( VAR46 ),
.din ( VAR29 ),
.dout ( VAR40 ),
.VAR30 ( VAR30 ),
.VAR48 ( VAR48 ),
.VAR42 ( VAR42 ),
.VAR49 ( VAR49 ),
.VAR19 ( VAR19 ),
.VAR44 ( VAR44 ),
.VAR38 (VAR38)
);
assign VAR4 = (read | write | VAR23) & ~VAR39;
assign dout = VAR17;
always @(posedge clk or negedge VAR41)
if (!VAR41)
VAR17 <= 8'h0;
else if (rst)
VAR17 <= 8'h0;
else if (VAR12)
VAR17 <= din;
else if (VAR14)
VAR17 <= {VAR17[6:0], VAR40};
always @(posedge clk or negedge VAR41)
if (!VAR41)
VAR24 <= 3'h0;
else if (rst)
VAR24 <= 3'h0;
else if (VAR12)
VAR24 <= 3'h7;
else if (VAR14)
VAR24 <= VAR24 - 3'h1;
assign VAR31 = ~(|VAR24);
reg [6:0] VAR33;
always @(posedge clk or negedge VAR41)
if (!VAR41)
begin
VAR8 <= VAR36;
VAR29 <= 1'b0;
VAR14 <= 1'b0;
VAR12 <= 1'b0;
VAR39 <= 1'b0;
VAR33 <= VAR50;
VAR2 <= 1'b0;
end
else if (rst | VAR46)
begin
VAR8 <= VAR36;
VAR29 <= 1'b0;
VAR14 <= 1'b0;
VAR12 <= 1'b0;
VAR39 <= 1'b0;
VAR33 <= VAR50;
VAR2 <= 1'b0;
end
else
begin
VAR29 <= VAR17[7];
VAR14 <= 1'b0;
VAR12 <= 1'b0;
VAR39 <= 1'b0;
case (VAR33) VAR50:
if (VAR4)
begin
if (VAR6)
begin
VAR33 <= VAR5;
VAR8 <= VAR43;
end
else if (read)
begin
VAR33 <= VAR25 ? VAR1 : VAR21;
VAR8 <= VAR25 ? VAR20 : VAR18;
end
else if (write)
begin
VAR33 <= VAR25 ? VAR47 : VAR13;
VAR8 <= VAR25 ? VAR16 : VAR9;
end
else begin
VAR33 <= VAR11;
VAR8 <= VAR15;
end
VAR12 <= 1'b1;
end
VAR5:
if (VAR10)
begin
if (read)
begin
VAR33 <= VAR21;
VAR8 <= VAR18;
end
else
begin
VAR33 <= VAR13;
VAR8 <= VAR9;
end
VAR12 <= 1'b1;
end
VAR13:
if (VAR10)
if (VAR31)
begin
VAR33 <= VAR37;
VAR8 <= VAR18;
end
else
begin
VAR33 <= VAR13; VAR8 <= VAR9; VAR14 <= 1'b1;
end
VAR21:
if (VAR10)
begin
if (VAR31)
begin
VAR33 <= VAR37;
VAR8 <= VAR9;
end
else
begin
VAR33 <= VAR21; VAR8 <= VAR18; end
VAR14 <= 1'b1;
VAR29 <= VAR22;
end
VAR37:
if (VAR10)
begin
if (VAR23)
begin
VAR33 <= VAR11;
VAR8 <= VAR15;
end
else
begin
VAR33 <= VAR50;
VAR8 <= VAR36;
VAR39 <= 1'b1;
end
VAR2 <= VAR40;
VAR29 <= 1'b1;
end
else
VAR29 <= VAR22;
VAR11:
if (VAR10)
begin
VAR33 <= VAR50;
VAR8 <= VAR36;
VAR39 <= 1'b1;
end
VAR47:
if (VAR10)
if (VAR31)
begin
VAR33 <= VAR50;
VAR8 <= VAR36;
VAR39 <= 1'b1;
end
else
begin
VAR33 <= VAR47; VAR8 <= VAR16; VAR14 <= 1'b1;
end
VAR1:
if (VAR10)
begin
if (VAR31)
begin
VAR33 <= VAR50;
VAR8 <= VAR36;
VAR39 <= 1'b1;
end
else
begin
VAR33 <= VAR1; VAR8 <= VAR20; end
VAR14 <= 1'b1;
VAR29 <= VAR22;
end
endcase
end
endmodule
|
gpl-3.0
|
sergev/vak-opensource
|
hardware/s3esk-openrisc/mem_if/onchip_ram_top.v
| 4,332 |
module MODULE1 (
input VAR12,
input VAR18,
input [31:0] VAR15,
output [31:0] VAR5,
input [31:0] VAR30,
input [3:0] VAR8,
input VAR26,
input VAR32,
input VAR6,
output VAR7,
output VAR3
);
parameter VAR23 = 12;
wire VAR27;
wire [3:0] VAR4;
reg VAR28;
reg VAR1;
assign VAR7 = VAR1 | VAR28;
assign VAR3 = VAR32 & VAR6 & (| VAR30[23:VAR23+2]);
assign VAR27 = VAR32 & VAR6 & VAR26 & (| VAR8[3:0]);
assign VAR4 = (VAR32 & VAR6) * VAR8;
always @ (negedge VAR12 or posedge VAR18)
begin
if (VAR18)
VAR28 <= 1'b0;
end
else
if (VAR32 & VAR6 & VAR26 & ~VAR28)
VAR28 <= 1'b1;
else
VAR28 <= 1'b0;
end
always @ (posedge VAR12 or posedge VAR18)
begin
if (VAR18)
VAR1 <= 1'b0;
end
else
if (VAR32 & VAR6 & ~VAR3 & ~VAR26 & ~VAR1)
VAR1 <= 1'b1;
else
VAR1 <= 1'b0;
end
VAR2 VAR13 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [3 : 0]),
.VAR9 (VAR5 [3 : 0]),
.VAR22 (VAR4 [0]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR25 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [7 : 4]),
.VAR9 (VAR5 [7 : 4]),
.VAR22 (VAR4 [0]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR16 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [11 : 8]),
.VAR9 (VAR5 [11 : 8]),
.VAR22 (VAR4 [1]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR24 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [15 : 12]),
.VAR9 (VAR5 [15 : 12]),
.VAR22 (VAR4 [1]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR21 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [19 : 16]),
.VAR9 (VAR5 [19 : 16]),
.VAR22 (VAR4 [2]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR20 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [23 : 20]),
.VAR9 (VAR5 [23 : 20]),
.VAR22 (VAR4 [2]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR17 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [27 : 24]),
.VAR9 (VAR5 [27 : 24]),
.VAR22 (VAR4 [3]),
.VAR19 (VAR27),
.VAR11 (0));
VAR2 VAR31 (
.VAR10 (VAR30 [VAR23+1 : 2]),
.VAR29 (VAR12),
.VAR14 (VAR15 [31 : 28]),
.VAR9 (VAR5 [31 : 28]),
.VAR22 (VAR4 [3]),
.VAR19 (VAR27),
.VAR11 (0));
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.pp.symbol.v
| 1,523 |
module MODULE1 (
input VAR5 ,
output VAR1 ,
output VAR7 ,
input VAR9,
input VAR6 ,
input VAR4 ,
input VAR8 ,
input VAR11 ,
input VAR3 ,
input VAR2 ,
input VAR10
);
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/de/der_rdmux.v
| 10,120 |
module MODULE1
(
input [8:2] VAR57, input [1:0] VAR53, input [1:0] VAR4, input [4:0] VAR13, input VAR41, input [14:0] VAR10, input [31:0] VAR14, input [31:0] VAR2, input [11:0] VAR52, input [11:0] VAR54, input [3:0] VAR46, input [3:0] VAR18, input [4:0] VAR51, input [3:0] VAR9, input [2:0] hdf1, input [2:0] VAR32, input [31:0] VAR6, input [31:0] VAR44, input [3:0] VAR37, input [23:0] VAR35, input [31:0] VAR11, input [15:0] VAR38, input [31:0] VAR39, input [31:0] VAR43, input [31:0] VAR1, input [31:0] VAR21, input [31:0] VAR30, input [31:0] VAR19, input [31:0] VAR28, input [15:0] VAR33, input [17:0] VAR8, input [15:0] VAR7, input [53:0] VAR3, input [1:0] VAR31,
input [6:0] VAR22, input [3:0] VAR12,
output [31:0] VAR55 );
parameter
VAR48 = 6'b000000, VAR15 = 6'b000001, VAR24 = 6'b000011, VAR45 = 6'b000100,
VAR40 = 6'b000101,
VAR29 = 6'b001000,
VAR49 = 6'b001001,
VAR23 = 6'b001010,
VAR56 = 6'b001011,
VAR17 = 6'b001100,
VAR25 = 6'b001101,
VAR36 = 6'b001110,
VAR42 = 6'b001111,
VAR47 = 6'b010000,
VAR50 = 6'b010001,
VAR16 = 6'b010010,
VAR20 = 6'b010011,
VAR5 = 6'b011111,
VAR26 = 6'b100101,
VAR34 = 6'b101101;
reg [63:0] VAR27;
always @* begin
VAR27 = 64'h0;
case (VAR57[8:3]) VAR48: begin
VAR27[1:0] = VAR4;
VAR27[33:32] = VAR53;
end
VAR15: begin
VAR27[4:0] = VAR13;
VAR27[32] = VAR41;
end
VAR24:
VAR27[63:60] = VAR12;
VAR45: begin
VAR27[2:0] = VAR10[2:0];
VAR27[5] = VAR10[3];
VAR27[7:6] = VAR31;
VAR27[8] = VAR10[13];
VAR27[15] = VAR10[4];
VAR27[23:22] = VAR10[6:5];
VAR27[27:24] = VAR10[10:7];
VAR27[31:29] = {VAR10[14],VAR10[12:11]};
VAR27[63:57] = VAR22;
end
VAR40: begin
VAR27[7:0] = VAR14[7:0];
VAR27[15:8] = VAR14[15:8];
VAR27[23:16] = VAR14[23:16];
VAR27[31:24] = VAR14[31:24];
VAR27[39:32] = VAR2[7:0];
VAR27[47:40] = VAR2[15:8];
VAR27[55:48] = VAR2[23:16];
VAR27[63:56] = VAR2[31:24];
end
VAR29: begin
VAR27[7:4] = VAR52[3:0];
VAR27[15:8] = VAR52[11:4];
VAR27[39:36] = VAR54[3:0];
VAR27[47:40] = VAR54[11:4];
end
VAR49: begin
VAR27[3:0] = VAR46;
VAR27[11:8] = VAR18;
VAR27[20:16] = VAR51;
VAR27[23:21] = VAR32;
VAR27[27:24] = VAR9;
VAR27[30:28] = hdf1;
end
VAR23: begin
VAR27[3:0] = VAR46;
VAR27[35:32] = VAR18;
end
VAR56: begin
VAR27[4:0] = VAR51;
VAR27[35:32] = VAR9;
end
VAR17: begin
VAR27[2:0] = VAR32;
VAR27[34:32] = hdf1;
end
VAR25: begin
VAR27[7:0] = VAR6[7:0];
VAR27[15:8] = VAR6[15:8];
VAR27[23:16] = VAR6[23:16];
VAR27[31:24] = VAR6[31:24];
VAR27[39:32] = VAR44[7:0];
VAR27[47:40] = VAR44[15:8];
VAR27[55:48] = VAR44[23:16];
VAR27[63:56] = VAR44[31:24];
end
VAR36: begin
VAR27[7:0] = {8{VAR37[0]}};
VAR27[15:8] = {8{VAR37[1]}};
VAR27[23:16] = {8{VAR37[2]}};
VAR27[31:24] = {8{VAR37[3]}};
VAR27[39:32] = VAR35[7:0];
VAR27[47:40] = VAR35[15:8];
VAR27[55:48] = VAR35[23:16];
end
VAR42: begin
VAR27[7:0] = VAR11[7:0];
VAR27[15:8] = VAR11[15:8];
VAR27[23:16] = VAR11[23:16];
VAR27[31:24] = VAR11[31:24];
VAR27[39:32] = VAR38[7:0];
VAR27[47:40] = VAR38[15:8];
VAR27[55:48] = VAR7[7:0];
VAR27[63:56] = VAR7[15:8];
end
VAR47: begin
VAR27[7:0] = VAR39[7:0];
VAR27[15:8] = VAR39[15:8];
VAR27[23:16] = VAR39[23:16];
VAR27[31:24] = VAR39[31:24];
VAR27[39:32] = VAR43[7:0];
VAR27[47:40] = VAR43[15:8];
VAR27[55:48] = VAR43[23:16];
VAR27[63:56] = VAR43[31:24];
end
VAR50: begin
VAR27[7:0] = VAR1[7:0];
VAR27[15:8] = VAR1[15:8];
VAR27[23:16] = VAR1[23:16];
VAR27[31:24] = VAR1[31:24];
VAR27[39:32] = VAR21[7:0];
VAR27[47:40] = VAR21[15:8];
VAR27[55:48] = VAR21[23:16];
VAR27[63:56] = VAR21[31:24];
end
VAR16: begin
VAR27[7:0] = VAR30[7:0];
VAR27[15:8] = VAR30[15:8];
VAR27[23:16] = VAR30[23:16];
VAR27[31:24] = VAR30[31:24];
VAR27[39:32] = VAR19[7:0];
VAR27[47:40] = VAR19[15:8];
VAR27[55:48] = VAR19[23:16];
VAR27[63:56] = VAR19[31:24];
end
VAR20: begin
VAR27[7:0] = VAR28[7:0];
VAR27[15:8] = VAR28[15:8];
VAR27[23:16] = VAR28[23:16];
VAR27[31:24] = VAR28[31:24];
end
VAR5: begin
VAR27[7:4] = VAR3[3:0];
VAR27[15:8] = VAR3[11:4];
VAR27[23:16] = VAR3[19:12];
VAR27[27:24] = {VAR3[53:51],VAR3[20]};
VAR27[31:30] = VAR3[22:21];
VAR27[39:36] = VAR3[26:23];
VAR27[47:40] = VAR3[34:27];
VAR27[55:48] = VAR3[42:35];
VAR27[56] = VAR3[43];
VAR27[63:60] = VAR3[47:44];
end
VAR26: begin
VAR27[7:0] = VAR33[7:0];
VAR27[15:8] = VAR33[15:8];
end
VAR34: begin
VAR27[3:0] = VAR46;
VAR27[11:8] = VAR18;
VAR27[20:16] = VAR51;
VAR27[23:21] = VAR32;
VAR27[27:24] = VAR9;
VAR27[30:28] = hdf1;
VAR27[39:32] = VAR8[7:0];
VAR27[42:40] = {VAR8[10:8]};
VAR27[51:48] = {VAR8[14:11]};
VAR27[58:56] = {VAR8[17:15]};
end
default: VAR27 = 64'h0;
endcase
end
assign VAR55 = (VAR57[2]) ? VAR27[63:32] : VAR27[31:0];
endmodule
|
gpl-3.0
|
htuNCSU/MmcCommunicationVerilog
|
DE2_115_MASTER/source_code/freedm_bus/fb_slave_statem.v
| 3,202 |
module MODULE1 (VAR17, VAR19, VAR8, VAR10, VAR25, VAR14
VAR13, VAR15, VAR6, VAR4, VAR22,
VAR24, VAR12, VAR23, VAR16, VAR7,
VAR5, VAR11
);
input VAR17;
input VAR19;
input VAR8;
input VAR25;
input VAR10;
input VAR14; input VAR13; input VAR15;
input VAR6;
input VAR4; input VAR22;
output VAR24;
output VAR23;
output VAR12;
output VAR16;
output VAR7;
output VAR5;
output VAR11;
reg VAR24;
reg VAR23;
reg VAR12;
reg VAR16;
reg VAR7;
reg VAR5;
reg VAR11;
wire VAR2;
wire VAR21;
wire VAR9;
wire VAR3;
wire VAR1;
wire VAR26;
wire VAR20;
assign VAR2 = ~VAR8 & ( VAR12 | VAR23 ) | (VAR11 & VAR22);
assign VAR21 = VAR8 & ~VAR25 & VAR24;
assign VAR9 = VAR8 & VAR25 & (VAR24 | VAR23);
assign VAR3 = (VAR8 & VAR12 & VAR10)|(VAR5 & VAR15 & ~VAR6);
assign VAR1[0] = VAR16 & VAR14 | VAR7[1] & ~VAR13;;
assign VAR1[1] = VAR7[0];
assign VAR26 = VAR7[1] & VAR13;
assign VAR20 = VAR5 & VAR15 & VAR6 | VAR16 & VAR4;
always @ (posedge VAR17 or posedge VAR19)
begin
if(VAR19)
begin
VAR24 <= 1'b1;
VAR23 <= 1'b0;
VAR12 <= 1'b0;
VAR16 <= 1'b0;
VAR18 <= 1'b0;
VAR5 <= 1'b0;
VAR11 <= 1'b0;
end
else
begin
if(VAR9 | VAR21)
VAR24 <= 1'b0;
end
else
if(VAR2)
VAR24 <= 1'b1;
if(VAR9 | VAR2)
VAR23 <= 1'b0;
end
else
if(VAR21)
VAR23 <= 1'b1;
if(VAR3)
VAR12 <= 1'b0;
else
if(VAR9)
VAR12 <= 1'b1;
if(VAR1 | VAR20)
VAR16 <= 1'b0;
else
if(VAR3)
VAR16 <= 1'b1;
if(VAR26)
VAR7 <= 1'b0;
else
if(VAR1)
VAR7 <= 1'b1;
if(VAR3 | VAR20)
VAR5 <= 1'b0;
else
if(VAR26)
VAR5 <= 1'b1;
if(VAR2)
VAR11 <= 1'b0;
else
if(VAR20)
VAR11 <= 1'b1;
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/mux2/sky130_fd_sc_lp__mux2.behavioral.pp.v
| 1,902 |
module MODULE1 (
VAR13 ,
VAR8 ,
VAR15 ,
VAR12 ,
VAR1,
VAR4,
VAR14 ,
VAR5
);
output VAR13 ;
input VAR8 ;
input VAR15 ;
input VAR12 ;
input VAR1;
input VAR4;
input VAR14 ;
input VAR5 ;
wire VAR3 ;
wire VAR9;
VAR10 VAR6 (VAR3 , VAR8, VAR15, VAR12 );
VAR7 VAR11 (VAR9, VAR3, VAR1, VAR4);
buf VAR2 (VAR13 , VAR9 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.functional.pp.v
| 2,072 |
module MODULE1 (
VAR1,
VAR9,
VAR4 ,
VAR2,
VAR10,
VAR5 ,
VAR7
);
input VAR1;
input VAR9;
output VAR4 ;
input VAR2;
input VAR10;
input VAR5 ;
input VAR7 ;
wire VAR7 VAR13 ;
wire VAR7 VAR12 ;
wire VAR16 ;
wire VAR6;
nand VAR15 (VAR13 , VAR10, VAR2 );
or VAR14 (VAR12 , VAR7, VAR5 );
and VAR17 (VAR16 , VAR13, VAR12 );
VAR8 VAR3 (VAR6, VAR16, VAR1, VAR9);
buf VAR11 (VAR4 , VAR6 );
endmodule
|
apache-2.0
|
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/verilog/fifo_w16_d1_A.v
| 2,973 |
module MODULE2 (
clk,
VAR10,
VAR3,
VAR22,
VAR20);
parameter VAR15 = 32'd16;
parameter VAR13 = 32'd1;
parameter VAR21 = 32'd2;
input clk;
input [VAR15-1:0] VAR10;
input VAR3;
input [VAR13-1:0] VAR22;
output [VAR15-1:0] VAR20;
reg[VAR15-1:0] VAR24 [0:VAR21-1];
integer VAR2;
always @ (posedge clk)
begin
if (VAR3)
begin
for (VAR2=0;VAR2<VAR21-1;VAR2=VAR2+1)
VAR24[VAR2+1] <= VAR24[VAR2];
VAR24[0] <= VAR10;
end
end
assign VAR20 = VAR24[VAR22];
endmodule
module MODULE1 (
clk,
reset,
VAR16,
VAR18,
VAR6,
VAR12,
VAR4,
VAR17,
VAR19,
VAR1);
parameter VAR11 = "VAR8";
parameter VAR15 = 32'd16;
parameter VAR13 = 32'd1;
parameter VAR21 = 32'd2;
input clk;
input reset;
output VAR16;
input VAR18;
input VAR6;
output[VAR15 - 1:0] VAR12;
output VAR4;
input VAR17;
input VAR19;
input[VAR15 - 1:0] VAR1;
wire[VAR13 - 1:0] VAR5 ;
wire[VAR15 - 1:0] VAR7, VAR27;
wire VAR9;
reg[VAR13:0] VAR26 = {(VAR13+1){1'b1}};
reg VAR14 = 0, VAR25 = 1;
assign VAR16 = VAR14;
assign VAR4 = VAR25;
assign VAR7 = VAR1;
assign VAR12 = VAR27;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR26 <= ~{VAR13+1{1'b0}};
VAR14 <= 1'b0;
VAR25 <= 1'b1;
end
else begin
if (((VAR6 & VAR18) == 1 & VAR14 == 1) &&
((VAR19 & VAR17) == 0 | VAR25 == 0))
begin
VAR26 <= VAR26 - 1;
if (VAR26 == 0)
VAR14 <= 1'b0;
VAR25 <= 1'b1;
end
else if (((VAR6 & VAR18) == 0 | VAR14 == 0) &&
((VAR19 & VAR17) == 1 & VAR25 == 1))
begin
VAR26 <= VAR26 + 1;
VAR14 <= 1'b1;
if (VAR26 == VAR21 - 2)
VAR25 <= 1'b0;
end
end
end
assign VAR5 = VAR26[VAR13] == 1'b0 ? VAR26[VAR13-1:0]:{VAR13{1'b0}};
assign VAR9 = (VAR19 & VAR17) & VAR25;
MODULE2
.VAR15(VAR15),
.VAR13(VAR13),
.VAR21(VAR21))
VAR23 (
.clk(clk),
.VAR10(VAR7),
.VAR3(VAR9),
.VAR22(VAR5),
.VAR20(VAR27));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.symbol.v
| 1,284 |
module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
models/udp_mux_4to2/sky130_fd_sc_hd__udp_mux_4to2.blackbox.v
| 1,298 |
module MODULE1 (
VAR3 ,
VAR2,
VAR6,
VAR5,
VAR1,
VAR7,
VAR4
);
output VAR3 ;
input VAR2;
input VAR6;
input VAR5;
input VAR1;
input VAR7;
input VAR4;
endmodule
|
apache-2.0
|
SymbiFlow/yosys
|
techlibs/ice40/abc9_model.v
| 3,717 |
module \VAR16 (
output VAR5,
output VAR6,
input VAR14, VAR12,
input VAR4,
input VAR7, VAR3
);
parameter VAR13 = 0;
parameter VAR8 = 0;
wire VAR18 = VAR8 ? VAR4 : VAR3;
VAR2 VAR1 (
.VAR7(VAR14),
.VAR9(VAR12),
.VAR4(VAR4),
.VAR5(VAR5)
);
VAR10 #(
.VAR17(VAR13)
) VAR11 (
.VAR7(VAR7),
.VAR9(VAR14),
.VAR15(VAR12),
.VAR3(VAR18),
.VAR6(VAR6)
);
|
isc
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/xnor3/sky130_fd_sc_hs__xnor3.behavioral.pp.v
| 1,725 |
module MODULE1 (
VAR8 ,
VAR11 ,
VAR12 ,
VAR1 ,
VAR5,
VAR9
);
output VAR8 ;
input VAR11 ;
input VAR12 ;
input VAR1 ;
input VAR5;
input VAR9;
wire VAR6 ;
wire VAR3;
xnor VAR2 (VAR6 , VAR11, VAR12, VAR1 );
VAR4 VAR7 (VAR3, VAR6, VAR5, VAR9);
buf VAR10 (VAR8 , VAR3 );
endmodule
|
apache-2.0
|
skatpgusskat/KoreaUnivHomework_2015_1
|
Computer Architecture/Homework/Lab/components.v
| 3,907 |
module MODULE2(VAR3, VAR7, clk, VAR6, VAR5);
input [31:0] VAR3;
output [31:0] VAR7;
input clk, VAR6, VAR5;
reg [31:0] register;
always @(posedge clk or posedge VAR6)
begin
if(VAR6)
register = 0;
end
else
if(VAR5 == 1)
register = VAR3;
end
assign VAR7 = register;
endmodule
module MODULE1;
reg [31:0] VAR4;
wire [31:0] VAR2;
reg clk, VAR6, VAR5;
MODULE2 VAR1(VAR4,VAR2, clk, VAR6, VAR5);
begin
begin
begin
begin
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/ha/sky130_fd_sc_ls__ha.symbol.v
| 1,274 |
module MODULE1 (
input VAR6 ,
input VAR5 ,
output VAR4,
output VAR1
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a222oi/sky130_fd_sc_hs__a222oi_2.v
| 2,415 |
module MODULE1 (
VAR11 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR1,
VAR9
);
output VAR11 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR9;
VAR5 VAR10 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR11 ,
VAR8,
VAR3,
VAR6,
VAR2,
VAR4,
VAR7
);
output VAR11 ;
input VAR8;
input VAR3;
input VAR6;
input VAR2;
input VAR4;
input VAR7;
supply1 VAR1;
supply0 VAR9;
VAR5 VAR10 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
htuNCSU/MmcCommunicationVerilog
|
DE2_115_MASTER/source_code/phyInitial.v
| 7,821 |
module MODULE1 (
input clk,reset,
input VAR22,
input [3:0]VAR55,
input [31:0] VAR65,
input [15:0]VAR63,
inout VAR51,
inout VAR43,
output VAR25,
output reg [3: 0] VAR58,
output reg VAR35,
output reg [12:0]VAR31,
output [15:0]VAR40,
output VAR38,
output VAR19
);
wire VAR68;
wire VAR10, VAR18, VAR4, VAR21;
wire [15:0] VAR48;
wire [15:0] VAR36;
wire [15:0] VAR61;
assign VAR38 = VAR68;
assign VAR19 = VAR10;
reg VAR45 ;
reg [3:0]VAR11;
always @ (posedge clk)
begin
if (reset) begin
VAR11<= 4'b0;
end
else begin
if (VAR45) begin
if (VAR11 < 4'b1110)
VAR11 <= VAR11 + 1'b1;
end
end
end
VAR13 VAR2(
.VAR5(VAR36),
.VAR12(VAR11),
.VAR15(VAR55),
.VAR6(VAR45),
.VAR60(1'b0),
.clk(clk),
.VAR30(VAR40)
);
wire [4:0] VAR7;
wire [4:0] VAR20;
wire VAR49;
assign VAR49 = VAR65[31];
assign VAR7 = VAR65[30:26];
assign VAR20 = VAR65[25:21];
assign VAR48 = VAR65[15:0];
assign VAR61 = VAR63;
wire [15: 0] VAR16;
assign VAR16 = (VAR36 | VAR48) & VAR61;
reg VAR3,VAR34;
wire VAR66, VAR57,VAR59, VAR47;
assign VAR51 = VAR47 ;
assign VAR43 = VAR47 ;
assign VAR47 = VAR66? VAR57:1'VAR39;
assign VAR59 = (VAR7==5'b10000)? VAR51 : VAR43;
reg VAR56, VAR32;
VAR41 VAR29 (
.VAR42(clk),
.VAR69(reset),
.VAR1(8'd50),
.VAR67(1'b0),
.VAR27(VAR16),
.VAR26(VAR20),
.VAR8(VAR7),
.VAR3(VAR3),
.VAR34(VAR34),
.VAR46(1'b0),
.VAR50(VAR59),
.VAR70(VAR57),
.VAR54(VAR66),
.VAR33(VAR25),
.VAR68(VAR68),
.VAR62(VAR36),
.VAR21(VAR21),
.VAR10(VAR10),
.VAR18(VAR18),
.VAR4(VAR4)
);
always @ (posedge clk)
begin
if (VAR56) begin
VAR58 <= 4'b0;
end
else begin
if (VAR32 ) VAR58 <= VAR58 + 4'b1;
end
end
reg [3:0]state, VAR24;
parameter VAR52 = 0, VAR9 = 1, VAR64 = 2, VAR28 = 3, VAR14= 4, VAR37 = 5 , VAR23 = 6, VAR17=7, VAR53=8, VAR44=9 ;
always @ (posedge clk ) begin
if (reset)
state <= VAR52;
end
else
state <= VAR24;
end
always @ (state or VAR22 or VAR4 or VAR65 or VAR68 or VAR18 or VAR10)
begin
VAR24 = state;
VAR3 = 1'b0;
VAR34 = 1'b0;
VAR32 = 0;
VAR56 = 0;
VAR31=0;
VAR45 = 0;
VAR35 = 0 ;
case (state)
VAR52:
begin
VAR56 = 1;
if (VAR22) begin
VAR24 = VAR9;
end
else begin
VAR24 = VAR52;
end
end
VAR9:
begin
if ( |VAR65 & ~VAR68) begin
VAR24 = VAR64; VAR31=1;
end
else if ( ~(|VAR65) & ~VAR68) begin
VAR24 = VAR9;
VAR35 = 1;
end
else begin
VAR24 = VAR9; VAR31=2;
end
end
VAR64:
begin
VAR3 = 1'b0;
VAR34 = 1'b1;
if ( VAR18 ) begin
VAR24 = VAR28;VAR31=4;
end
else begin
VAR24 = VAR64;VAR31=8;
end
end
VAR28:
begin
VAR3 = 1'b0;
VAR34 = 1'b1;
if (VAR4) begin
VAR24 = VAR14;VAR31=16;
VAR45 = 1;
end
else begin
VAR24 = VAR28;VAR31=32;
end
end
VAR14:
begin
VAR3 = 1'b0;
VAR34 = 1'b0;
if (~VAR68) begin
VAR24 = VAR37;
end
else begin
VAR24 = VAR14;VAR31=1024;
end
end
VAR37:
begin
VAR3 = 1'b1;
VAR34 = 1'b0;
if ( VAR10 ) begin
VAR24 = VAR23; VAR31=64;
end
else begin
VAR24 = VAR37;VAR31=128;
end
end
VAR23:
begin
VAR3 = 1'b0;
VAR34 = 1'b0;
if ( ~VAR68 ) begin
VAR24 = VAR17;VAR31=256;
VAR32 = 1;
end
else begin
VAR24 = VAR23;VAR31=512;
end
end
VAR17:
begin
VAR24 = VAR53;
end
VAR53:
begin
VAR24 = VAR44;
end
VAR44:
begin
VAR24 = VAR9;
end
endcase
end
endmodule
|
gpl-3.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/sctag/rtl/sctag_oqdp.v
| 29,789 |
module MODULE1(
VAR6, VAR92, VAR173, VAR108,
VAR157, VAR44, VAR125,
VAR29, VAR42, VAR75,
VAR101, VAR128, VAR24,
VAR100, VAR119, VAR25,
VAR115, VAR46, VAR70,
VAR104, VAR18, VAR48,
VAR40, VAR140, VAR33,
VAR15, VAR83, VAR175, VAR97,
VAR74, VAR87, VAR1,
VAR117, VAR131, VAR78, VAR11,
VAR137, VAR93, VAR86,
VAR53, VAR61, VAR81,
VAR174, VAR156, VAR17, VAR27
);
input [1:0] VAR157 ;
input [2:1] VAR44; input [1:0] VAR125;
input VAR29;
input [2:0] VAR42 ;
input [3:0] VAR75;
input [2:0] VAR101;
input VAR128;
input [17:0] VAR24;
input VAR100;
input VAR119 ;
input VAR25;
input [11:6] VAR115;
input VAR46;
input [127:0] VAR70;
input [2:0] VAR104;
input [111:0] VAR18;
input [38:0] VAR48 ;
input [27:0] VAR40;
input [33:0] VAR140;
input [VAR99-1:0] VAR33 ;
input VAR15; input VAR83;
input VAR175;
input VAR97 ;
input VAR74;
input VAR87; input VAR1;
input [3:0] VAR117; input VAR131; input VAR78;
input VAR11; input [2:0] VAR137; input [2:0] VAR93;
input [5:4] VAR86; input VAR53; input VAR61;
input [63:0] VAR81;
input VAR174 ;
input VAR156;
output VAR6;
input VAR17, VAR27;
output [VAR99-1:0] VAR92 ;
output [VAR99-1:0] VAR173;
output [4:0] VAR108 ;
wire [VAR99-12:0] VAR68;
wire [VAR99-12:0] VAR66;
wire [VAR99-1:0] VAR34;
wire [VAR99-1:0] VAR31;
wire [1:0] VAR172;
wire VAR139;
wire [1:0] VAR63;
wire VAR84 ;
wire [1:0] VAR105;
wire VAR166 ;
wire [3:0] VAR57;
wire [2:0] VAR50;
wire [2:0] VAR123;
wire [VAR99-1:0] VAR149;
wire [VAR99-1:0] VAR59;
wire [38:0] VAR58 ;
wire VAR26;
wire [127:0] VAR3;
wire [2:0] VAR103 ;
wire [1:0] VAR165;
wire VAR41 ;
wire [2:0] VAR91;
wire [2:0] VAR38;
wire [2:0] VAR16;
wire [5:0] VAR158;
wire [5:0] VAR19;
wire [63:0] VAR162;
wire [2:0] VAR9;
wire [2:0] VAR52;
wire [2:0] VAR45;
wire [2:0] VAR153;
wire [2:0] VAR72;
wire [2:0] VAR62;
wire [2:0] VAR169;
wire [1:0] VAR2;
wire [VAR99-1:0] VAR28;
wire [2:0] VAR43;
wire [2:0] VAR13;
wire [2:0] VAR5;
wire [VAR99-1:0] VAR60;
wire [3:0] VAR142 ;
wire [3:0] VAR138 ;
wire [3:0] VAR14;
wire VAR32;
wire VAR36;
wire VAR23 ;
wire VAR124 ;
wire [2:0] VAR22 ;
wire [2:0] VAR35 ;
wire [2:0] VAR90 ;
wire [2:0] VAR159 ;
assign VAR41 = (VAR46 | VAR74) ;
VAR120 #(2) VAR114
(.VAR21 (VAR172[1:0]),
.din (VAR125[1:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(2) VAR132
(.dout (VAR63[1:0]),
.VAR94 (VAR125[1:0]), .VAR64 (~VAR41),
.VAR171 (VAR172[1:0]), .VAR102 (VAR41)
) ;
VAR120 #(2) VAR118
(.VAR21 (VAR105[1:0]),
.din (VAR63[1:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(1) VAR54
(.VAR21 (VAR139),
.din (VAR29),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(1) VAR136
(.dout (VAR84),
.VAR94 (VAR29), .VAR64 (~VAR41),
.VAR171 (VAR139), .VAR102 (VAR41)
) ;
VAR120 #(1) VAR85
(.VAR21 (VAR166),
.din (VAR84),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(4) VAR130
(.VAR21 (VAR57[3:0]),
.din (VAR75[3:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(2) VAR4
(.VAR21 (VAR165[1:0]),
.din (VAR157[1:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(2) VAR141
(.dout (VAR2[1:0]),
.VAR94 (VAR157[1:0]), .VAR64 (~VAR41),
.VAR171 (VAR165[1:0]), .VAR102 (VAR41)
) ;
assign VAR103[2] = VAR2[0] ;
assign VAR103[1] = VAR175 ; assign VAR103[0] = 1'b0;
VAR168 #(3) VAR107
(.dout (VAR50[2:0]),
.VAR94 (VAR103[2:0]), .VAR64 (~VAR128),
.VAR171 ({VAR2[1:0],1'b0}), .VAR102 (VAR128)
) ;
VAR120 #(3) VAR145
(.VAR21 (VAR123[2:0]),
.din (VAR50[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR52[2] = VAR44[2] & VAR97 ;
assign VAR52[1] = (VAR44[1] & VAR97) |
VAR175 ;
assign VAR52[0] = VAR15 ;
VAR120 #(3) VAR167
(.VAR21 (VAR45[2:0]),
.din (VAR52[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(3) VAR116
(.VAR21 (VAR91[2:0]),
.din (VAR42[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(3) VAR79
(.dout (VAR38[2:0]),
.VAR94 (VAR42[2:0]), .VAR64 (~VAR41),
.VAR171 (VAR91[2:0]), .VAR102 (VAR41)
) ;
VAR168 #(3) VAR95
(.dout (VAR3[120:118]),
.VAR94 (VAR38[2:0]), .VAR64 (~VAR124),
.VAR171 (VAR3[56:54]), .VAR102 (VAR124)
) ;
VAR120 #(3) VAR170
(.VAR21 (VAR68[120:118]),
.din (VAR3[120:118]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR16[2:0] = VAR68[120:118] ;
assign VAR108 = {VAR16[2:0], VAR105[1:0]} ;
VAR168 #(3) VAR135
(.dout (VAR153[2:0]),
.VAR94 ({2'b0,VAR2[1]}), .VAR64 (~VAR119),
.VAR171 (VAR38[2:0]), .VAR102 (VAR119)
) ;
VAR120 #(3) VAR129
(.VAR21 (VAR62[2:0]),
.din (VAR153[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(3) VAR88
(.dout (VAR72[2:0]),
.VAR94 (VAR101[2:0]), .VAR64 (~VAR119),
.VAR171 (VAR38[2:0]), .VAR102 (VAR119)
) ;
VAR120 #(3) VAR49
(.VAR21 (VAR169[2:0]),
.din (VAR72[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(6) VAR161
(.VAR21 (VAR158[5:0]),
.din (VAR115[11:6]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(6) VAR155
(.dout (VAR19[5:0]),
.VAR94 (VAR115[11:6]), .VAR64 (~VAR41),
.VAR171 (VAR158[5:0]), .VAR102 (VAR41)
) ;
VAR168 #(6) VAR65
(.dout (VAR3[117:112]),
.VAR94 (VAR19[5:0]), .VAR64 (~VAR124),
.VAR171 (VAR3[53:48]), .VAR102 (VAR124)
) ;
VAR120 #(6) VAR151
(.VAR21 (VAR68[117:112]),
.din (VAR3[117:112]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR142 = {VAR61, VAR53, VAR86} ;
VAR120 #(4) VAR147
(.VAR21 (VAR138[3:0]),
.din (VAR142[3:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(4) VAR39
(.dout (VAR14[3:0]),
.VAR94 (VAR142[3:0]), .VAR64 (~VAR41),
.VAR171 (VAR138[3:0]), .VAR102 (VAR41)
) ;
VAR168 #(4) VAR133
(.dout (VAR3[124:121]),
.VAR94 (VAR14[3:0]), .VAR64 (~VAR124),
.VAR171 (VAR3[60:57]), .VAR102 (VAR124)
) ;
VAR120 #(4) VAR7
(.VAR21 (VAR68[124:121]),
.din (VAR3[124:121]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(1) VAR12 (.VAR21 (VAR32),
.din (VAR83),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(1) VAR80 (.dout (VAR36),
.VAR94 (VAR83), .VAR64 (~VAR41),
.VAR171 (VAR32), .VAR102 (VAR41)
) ;
VAR168 #(1) VAR148
(.dout (VAR3[125]),
.VAR94 (VAR36), .VAR64 (~VAR124),
.VAR171 (VAR3[61]), .VAR102 (VAR124)
) ;
VAR120 #(1) VAR122
(.VAR21 (VAR68[125]),
.din (VAR3[125]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR9 = {VAR174,
VAR1, VAR87} ;
assign VAR43[2] = (VAR9[2]) ;
assign VAR43[1] = (VAR9[1] |
(VAR104[1] & VAR46)) ;
assign VAR43[0] = (VAR9[0]) ;
VAR120 #(3) VAR109
(.VAR21 (VAR13[2:0]),
.din (VAR43[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR5 = VAR13 | VAR104 ;
assign VAR26 = (VAR117[0] | VAR117[1] |
VAR117[2] | VAR25) ;
VAR67 #(39) VAR69
(.dout (VAR58[38:0]),
.VAR94 (VAR48[38:0]), .VAR64 (VAR117[0]),
.VAR171 ({11'b0, VAR40[27:0]}), .VAR102 (VAR117[1]),
.VAR113 ({5'b0, VAR140[33:0]}), .VAR51 (VAR117[2]),
.VAR143 ({21'b0, VAR24[17:0]}), .VAR20 (VAR117[3])
) ;
VAR168 #(64) VAR8
(.dout (VAR162[63:0]),
.VAR94 (VAR18[63:0]), .VAR64 (~VAR78),
.VAR171 (VAR81[63:0]), .VAR102 (VAR78)
) ;
VAR168 #(64) VAR150
(.dout (VAR3[63:0]),
.VAR94 (VAR162[63:0]), .VAR64 (~VAR26),
.VAR171 ({25'b0, VAR58[38:0]}), .VAR102 (VAR26)
) ;
VAR120 #(64) VAR152
(.VAR21 (VAR68[63:0]),
.din (VAR3[63:0]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR23 = ( VAR26 | VAR78) ;
assign VAR124 = (~VAR26 & VAR78) ;
VAR168 #(48) VAR160
(.dout (VAR3[111:64]),
.VAR94 (VAR18[111:64]), .VAR64 (~VAR23),
.VAR171 (VAR3[47:0]), .VAR102 (VAR23)
) ;
VAR120 #(48) VAR76
(.VAR21 (VAR68[111:64]),
.din (VAR3[111:64]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR66[VAR146:VAR55] = VAR169 ; assign VAR66[VAR110:VAR82] = VAR45 ; assign VAR66[127:0] = VAR70 ;
assign VAR68[VAR146:VAR55] = VAR62 ; assign VAR68[VAR110:VAR82] = VAR123 ;
VAR168 #(2) VAR71
(.dout (VAR3[127:126]),
.VAR94 (2'b0), .VAR64 (~VAR124),
.VAR171 (VAR3[63:62]), .VAR102 (VAR124)
) ;
VAR120 #(2) VAR154
(.VAR21 (VAR68[127:126]),
.din (VAR3[127:126]),
.clk (VAR156),
.VAR27 (VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(1) VAR127
(.VAR21 (VAR96),
.din (VAR11),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR92[VAR144] = 1'b1 ; assign VAR92[VAR126:VAR134] = VAR57 ; assign VAR92[VAR56:VAR77] = VAR5 ; assign VAR92[VAR163] = VAR166 ; assign VAR92[VAR112:VAR98] = VAR105 ;
VAR168 #(VAR99-11) VAR121
( .dout (VAR92[VAR99-12:0]), .VAR94 (VAR68[VAR99-12:0]), .VAR64 (VAR96),
.VAR171 (VAR66[VAR99-12:0]), .VAR102 (~VAR96)
) ;
VAR120 #(VAR99) VAR106
(.VAR21 (VAR34[VAR99-1:0]),
.din (VAR92[VAR99-1:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR168 #(VAR99) VAR30
( .dout (VAR149[VAR99-1:0]), .VAR94 (VAR33[VAR99-1:0]), .VAR64 (~VAR131),
.VAR171 (VAR34[VAR99-1:0]), .VAR102 (VAR131)
) ;
VAR120 #(VAR99) VAR111
(.VAR21 (VAR59[VAR99-1:0]),
.din (VAR149[VAR99-1:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(VAR99) VAR10
(.VAR21 (VAR31[VAR99-1:0]),
.din (VAR60[VAR99-1:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
VAR120 #(3) VAR73
(.VAR21 (VAR35[2:0]),
.din (VAR137[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR22[0] = VAR35[0] & ~VAR100 ;
assign VAR22[1] = VAR35[1] & ~VAR100 ;
assign VAR22[2] = VAR35[2] | VAR100 ;
VAR47 #(VAR99) VAR37
(.dout (VAR28[VAR99-1:0]),
.VAR94 (VAR34[VAR99-1:0]), .VAR64 (VAR22[2]), .VAR171 (VAR59[VAR99-1:0]), .VAR102 (VAR22[1]), .VAR113 (VAR31[VAR99-1:0]), .VAR51 (VAR22[0]) ) ;
VAR120 #(3) VAR164
(.VAR21 (VAR159[2:0]),
.din (VAR93[2:0]),
.clk (VAR156),
.VAR27(VAR27), .VAR17 (), .VAR6 ()
) ;
assign VAR90[0] = VAR159[0] & ~VAR100 ;
assign VAR90[1] = VAR159[1] & ~VAR100 ;
assign VAR90[2] = VAR159[2] | VAR100 ;
VAR47 #(VAR99) VAR89
(.dout (VAR60[VAR99-1:0]),
.VAR94 (VAR28[VAR99-1:0]),
.VAR64 (VAR90[0]), .VAR171 ({VAR92[VAR144:VAR98], VAR68[VAR99-12:0]}),
.VAR102 (VAR90[1]), .VAR113 ({VAR92[VAR144:VAR98], VAR66[VAR99-12:0]}),
.VAR51 (VAR90[2]) ) ;
assign VAR173 = VAR60 ;
endmodule
|
gpl-2.0
|
rkrajnc/minimig-de1
|
rtl/soc/minimig_mist_top.v
| 14,284 |
module MODULE1 (
input wire [ 2-1:0] VAR181, input wire [ 2-1:0] VAR199, input wire [ 2-1:0] VAR179, output wire VAR90, output wire VAR32, input wire VAR175, output wire VAR85, output wire VAR28, output wire [ 6-1:0] VAR71, output wire [ 6-1:0] VAR123, output wire [ 6-1:0] VAR157, inout wire [ 16-1:0] VAR225, output wire [ 13-1:0] VAR35, output wire VAR197, output wire VAR217, output wire VAR74, output wire VAR201, output wire VAR212, output wire VAR92, output wire [ 2-1:0] VAR174, output wire VAR118, output wire VAR200, output wire VAR43, output wire VAR187, inout wire VAR53, input wire VAR8,
input wire VAR51,
input wire VAR131, input wire VAR83, input wire VAR82, input wire VAR203 );
wire VAR27;
wire VAR62;
wire VAR65;
wire VAR204;
wire VAR139;
wire VAR182;
wire VAR190;
wire VAR44;
wire VAR58;
wire VAR169;
wire [ 10-1:0] VAR45;
wire VAR143;
wire VAR5;
wire VAR133;
wire VAR210;
wire VAR171;
wire VAR167;
wire VAR54;
wire VAR191;
wire [ 16-1:0] VAR226;
wire [ 16-1:0] VAR154;
wire [ 32-1:0] VAR202;
wire [ 3-1:0] VAR119;
wire VAR208;
wire VAR121;
wire VAR206;
wire VAR98;
wire VAR104;
wire VAR165;
wire VAR194;
wire VAR86;
wire [ 16-1:0] VAR55;
wire VAR152;
wire [ 2-1:0] VAR221;
wire [ 6-1:0] VAR6;
wire [ 32-1:0] VAR106;
wire [ 6-1:0] VAR127;
wire VAR198;
wire VAR9;
wire VAR124;
wire VAR150;
wire [ 16-1:0] VAR125; wire [ 16-1:0] VAR94; wire [ 22-1:1] VAR40; wire VAR218; wire VAR151; wire VAR3; wire VAR109; wire 15khz; wire VAR162; wire VAR50; wire [ 15-1:0] VAR153; wire [ 15-1:0] VAR177; wire VAR1;
wire VAR59;
wire VAR168;
wire [ 4-1:0] VAR100;
wire [ 2-1:0] VAR29;
wire [ 2-1:0] VAR192;
assign VAR200 = 1'b1;
assign VAR118 = VAR204;
assign VAR92 = VAR100[0];
assign VAR197 = VAR29[0];
assign VAR217 = VAR29[1];
assign VAR174 = VAR192;
assign VAR35[12] = 1'b0;
assign VAR27 = VAR199[0];
assign VAR143 = 1'b0; assign VAR5 = VAR139;
assign 15khz = 1'b1; assign VAR162 = 1'b1;
assign VAR90 = ~VAR150;
assign VAR71[1:0] = VAR71[5:4];
assign VAR123[1:0] = VAR123[5:4];
assign VAR157[1:0] = VAR157[5:4];
VAR2 VAR2 (
.rst (VAR143 ), .VAR69 (VAR27 ), .VAR62 (VAR62 ), .VAR204 (VAR204 ), .VAR65 (VAR65 ), .VAR182 (VAR182 ), .VAR190 (VAR190 ), .VAR44 (VAR44 ), .VAR58 (VAR58 ), .VAR169 (VAR169 ), .VAR45 (VAR45 ), .VAR207 (VAR139 ) );
VAR66 VAR144 (
.clk (VAR62 ),
.reset (VAR191 ),
.VAR148 (1'b1 ),
.VAR41 (VAR119 ),
.VAR25 (VAR208 ),
.VAR111 (1'b1 ),
.VAR188 (1'b1 ),
.addr (VAR202 ),
.VAR120 (VAR226 ),
.VAR149 (VAR154 ),
.VAR220 (VAR121 ),
.VAR22 (VAR206 ),
.VAR48 (VAR98 ),
.VAR140 (VAR104 ),
.VAR108 ( ),
.VAR75 ( ),
.VAR159 ( ),
.VAR156 (VAR165 ),
.VAR47 (VAR194 ),
.VAR183 (VAR86 ),
.VAR189 (VAR55 ),
.VAR185 (VAR152 ),
.VAR158 (VAR221 ),
.VAR6 (VAR6 ),
.VAR20 (VAR106 ),
.VAR33 (VAR127 ),
.VAR222 ( ),
.VAR57 ( ),
.VAR116 (VAR198 ),
.VAR164 (VAR9 ),
.VAR102 (VAR124 )
);
VAR88 VAR224 (
.VAR24 (3'b111 ),
.VAR180 (VAR225 ),
.VAR113 (VAR35[11:0] ),
.VAR135 (VAR29 ),
.VAR160 (VAR100 ),
.VAR145 (VAR192 ),
.VAR219 (VAR74 ),
.VAR15 (VAR212 ),
.VAR142 (VAR201 ),
.VAR52 (VAR62 ),
.VAR60 (VAR5 ),
.VAR19 (16'h0 ),
.VAR70 (24'h0 ),
.VAR205 ({1'b0, 2'b01} ),
.VAR107 (1'b1 ),
.VAR117 (1'b1 ),
.VAR49 (VAR154 ),
.VAR147 (VAR106[24:1] ),
.VAR42 (VAR124 ),
.VAR17 (VAR9 ),
.VAR33 (VAR127 ),
.VAR46 (VAR198 ),
.VAR84 (VAR125 ),
.VAR37 ({2'b00, VAR40[21:1]}),
.VAR80 (VAR218 ),
.VAR112 (VAR151 ),
.VAR137 (VAR3 ),
.VAR141 (VAR109 ),
.VAR196 (VAR182 ),
.VAR132 ( ),
.VAR114 ( ),
.VAR95 (VAR55 ),
.VAR11 (VAR152 ),
.VAR68 (VAR94 ),
.VAR168 (VAR168 ),
.VAR183 (VAR86 ),
.VAR156 (VAR165 ),
.VAR47 (VAR194 )
);
assign VAR53 = (VAR203 == 1'b0)?VAR129:
(((VAR131 == 1'b0)|| (VAR83 == 1'b0))?VAR12:1'VAR138);
wire VAR129;
wire VAR12;
wire [5:0] VAR61;
wire [5:0] VAR216;
wire [7:0] VAR195;
wire VAR30;
wire [1:0] VAR105;
wire [2:0] VAR146;
VAR73 VAR73(
.VAR215(VAR51),
.VAR31(VAR203),
.VAR170(VAR129),
.VAR161(VAR8),
.VAR213(VAR61),
.VAR7(VAR216),
.VAR96(VAR146),
.VAR39(VAR195),
.VAR103(VAR105),
.VAR166(VAR30),
.VAR134(8'ha1) );
VAR172 VAR63 (
.VAR4 (VAR202[23:1] ), .VAR163 (VAR226 ), .VAR101 (VAR154 ), .VAR214 (VAR119 ), .VAR91 (VAR121 ), .VAR18 (VAR206 ), .VAR211 (VAR98 ), .VAR16 (VAR104 ), .VAR97 (VAR208 ), .VAR72 (VAR191 ), .VAR77 (VAR182 ), .VAR125 (VAR125 ), .VAR94 (VAR94 ), .VAR40 (VAR40[21:1]), .VAR193 ( ), .VAR218 (VAR218 ), .VAR151 (VAR151 ), .VAR3 (VAR3 ), .VAR109 (VAR109 ), .VAR176 (VAR65 ), .clk (VAR182 ), .VAR190 (VAR190 ), .VAR44 (VAR44 ), .VAR58 (VAR58 ), .VAR169 (VAR169 ), .VAR45 (VAR45 ), .VAR93 (VAR175 ), .VAR87 (VAR32 ), .VAR178 (1'b0 ), .VAR23 ( ), .VAR209 (~VAR61 ), .VAR26 (~VAR216 ), .VAR173 (1'b1 ), .VAR130 (1'b1 ), .VAR128 (VAR146 ), .VAR195 (VAR195 ), .VAR105 (VAR105 ), .VAR30 (VAR30), .VAR162 (VAR162 ), .15khz (15khz ), .VAR76 (VAR150 ), .VAR56 ( ), .VAR36 ( ), .VAR81 ( ), .VAR21 ( ), .VAR126 ( {VAR82,VAR83,VAR131} ), .VAR89 (VAR53 ), .VAR186 (VAR8 ), .VAR50 (VAR12 ), .VAR122 (VAR51 ), .VAR136 (VAR85 ), .VAR155 (VAR28 ), .VAR14 (VAR71[5:2] ), .VAR10 (VAR123[5:2] ), .VAR67 (VAR157[5:2] ), .VAR64 (VAR43 ), .VAR115 (VAR187 ), .VAR153 ( ), .VAR177 ( ), .VAR184 ( ), .VAR221 (VAR221 ), .VAR6 (VAR6 ), .VAR110 ( ), .VAR13 ( ), .VAR38 ( ), .VAR79 ( ), .VAR99 ( ), .VAR78 ( ), .VAR34 ( ), .VAR223 ( ) );
endmodule
|
gpl-3.0
|
tofuman/nand-proz
|
Prozessor/ALU.v
| 1,039 |
module MODULE1 (VAR2, VAR7, VAR6, VAR8, VAR4, enable);
input wire [7:0] VAR2, VAR7;
output reg [7:0] VAR6;
input wire [4:0] VAR4;
output reg [2:0] VAR8;
input wire enable;
wire [8:0] VAR1, VAR5, VAR3;
always @ (posedge enable )
begin
case (VAR4)
2'b00000 :begin
VAR1 = {1'b0, VAR2};
VAR5 = {1'b0, VAR7};
VAR3 = VAR1 + VAR5;
VAR6 = VAR3[7:0];
VAR8[0] = VAR3[8];
end
2'b00001 : VAR6 = VAR2 - VAR7;
2'b00010 : VAR6 = VAR2 | VAR7;
2'b00011 : VAR6 = VAR2 & VAR7;
2'b00100 : VAR6 = VAR2 ^ VAR7;
2'b00101 : VAR6 = ~VAR7;
2'b00110 : VAR6 = VAR2 << VAR7;
2'b00111 : VAR6 = VAR2 >> VAR7;
2'b01000 : VAR6 = VAR2 >>> VAR7;
2'b01001 : VAR6 = (VAR2 << VAR7) | (VAR2 >> (8-VAR7));
2'b01010 : VAR6 = (VAR2 >> VAR7) | (VAR2 >> (8-VAR7));
2'b01011 : VAR6 = VAR7;
2'b01100 : VAR6 = 2'b00000000;
2'b01101 : VAR6 = 2'b00000000;
2'b01110 : VAR6 = 2'b00000000;
2'b01111 : VAR6 = VAR7 + VAR2 + VAR8[0];
2'b10000 : VAR6 = VAR7 - VAR2 - VAR8[0];
default : VAR6 = 2'b00000000;
endcase
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/xor2/sky130_fd_sc_hd__xor2.pp.blackbox.v
| 1,291 |
module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR7,
VAR2,
VAR5 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR7;
input VAR2;
input VAR5 ;
input VAR4 ;
endmodule
|
apache-2.0
|
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM
|
tdpram.v
| 4,639 |
module MODULE1
integer VAR6;
reg [VAR15-1:0] VAR12 [0:VAR14-1]; VAR8
if (VAR7)
for (VAR6=0; VAR6<VAR14; VAR6=VAR6+1) VAR12[VAR6] = {VAR15{1'b0}};
else
if (VAR9 != "")
always @(posedge clk) begin
if (VAR5) begin
VAR12[VAR11] <= VAR2; VAR13 <= VAR2; end else
VAR13 <= VAR12[VAR11]; end
always @(posedge clk) begin
if (VAR3) begin
VAR12[VAR1] <= VAR4; VAR10 <= VAR4; end else
VAR10 <= VAR12[VAR1]; end
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o41a/sky130_fd_sc_lp__o41a.functional.pp.v
| 2,047 |
module MODULE1 (
VAR13 ,
VAR17 ,
VAR11 ,
VAR16 ,
VAR14 ,
VAR12 ,
VAR15,
VAR18,
VAR8 ,
VAR4
);
output VAR13 ;
input VAR17 ;
input VAR11 ;
input VAR16 ;
input VAR14 ;
input VAR12 ;
input VAR15;
input VAR18;
input VAR8 ;
input VAR4 ;
wire VAR2 ;
wire VAR3 ;
wire VAR1;
or VAR5 (VAR2 , VAR14, VAR16, VAR11, VAR17 );
and VAR10 (VAR3 , VAR2, VAR12 );
VAR7 VAR9 (VAR1, VAR3, VAR15, VAR18);
buf VAR6 (VAR13 , VAR1 );
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mig_37.v
| 34,114 |
module MODULE1 #
(
parameter VAR175 = 200,
parameter VAR31 = "VAR127",
parameter VAR140 = "VAR224",
parameter VAR80 = 6,
parameter VAR142 = 2,
parameter VAR255 = 3,
parameter VAR69 = 2,
parameter VAR254 = 2500,
parameter VAR11 = "VAR93",
parameter VAR246 = "VAR65",
parameter VAR14 = 1,
parameter VAR199 = 3,
parameter VAR227 = 1,
parameter VAR159 = 3,
parameter VAR144 = 1,
parameter VAR151 = 1,
parameter VAR217 = 10,
parameter VAR92 = 1,
parameter VAR107 = 8,
parameter VAR116 = 64,
parameter VAR191 = 8,
parameter VAR212 = 13,
parameter VAR91 = "8",
parameter VAR233 = 2,
parameter VAR16 = "1T" ,
parameter VAR228 = "VAR152",
parameter VAR99 = "VAR93",
parameter VAR234 = "VAR93",
parameter VAR19 = "60",
parameter VAR73 = "VAR65",
parameter VAR139 = "VAR136",
parameter VAR169 = "VAR65",
parameter VAR168 = 6,
parameter VAR2 = 2,
parameter VAR10 = 0,
parameter VAR39 = 0,
parameter VAR216 = 48'h050403020100,
parameter VAR132 = 16'h0706,
parameter VAR130 = 0,
parameter VAR230 = 0,
parameter VAR204 = 1000000,
parameter VAR205 = 7800000,
parameter VAR70 = 128000000,
parameter VAR206 = 27,
parameter VAR190 = "VAR65",
parameter VAR50 = 100,
parameter VAR147 = 64,
parameter VAR26 = (VAR190 == "VAR65") ? VAR147 : VAR116,
parameter VAR131 = 1,
parameter VAR71 = "VAR84",
parameter VAR58 = 2
)
(
input VAR173, input VAR9,
input VAR85, input VAR177,
inout [VAR116-1:0] VAR157,
output [VAR212-1:0] VAR48,
output [VAR159-1:0] VAR53,
output VAR34,
output VAR81,
output VAR187,
output VAR90,
output [(VAR92*VAR14)-1:0] VAR25,
output [(VAR92*VAR14)-1:0] VAR143,
output [VAR151-1:0] VAR178,
output [VAR107-1:0] VAR134,
inout [VAR191-1:0] VAR3,
inout [VAR191-1:0] VAR207,
output [VAR144-1:0] VAR188,
output [VAR144-1:0] VAR114,
inout VAR165,
output VAR15,
input VAR60,
input [(4*VAR26)-1:0] VAR249,
input [(4*VAR26)/8-1:0] VAR12,
input VAR163,
input [VAR206-1:0] VAR63,
input [2:0] VAR158,
input VAR194,
output VAR166,
output VAR250,
output [(4*VAR26)-1:0] VAR46,
output VAR179,
output VAR29,
output VAR252,
output VAR148,
input VAR97 );
localparam VAR183 = VAR254 * VAR69;
localparam VAR115 = VAR26 * 4;
localparam VAR189 = VAR115 / 8;
wire VAR82;
wire VAR201;
wire VAR4;
wire VAR113;
wire VAR30;
wire VAR237;
wire rst;
wire clk;
wire VAR96;
wire VAR160;
wire VAR146;
wire VAR49;
wire VAR197;
wire [(VAR233)-1:0] VAR219;
wire VAR103;
wire VAR122;
wire VAR42;
wire [3:0] VAR66;
wire [47:0] VAR101;
wire [47:0] VAR118;
wire [5*VAR191-1:0] VAR36;
wire [5*VAR191-1:0] VAR89;
wire [5*VAR191-1:0] VAR176;
wire VAR222;
wire VAR133;
wire VAR248;
wire [5*VAR191-1:0] VAR111;
wire [5*VAR191-1:0] VAR218;
wire VAR145;
wire [VAR199-1:0] VAR64;
wire VAR123;
wire VAR20;
wire VAR21;
wire VAR75;
wire VAR28;
wire VAR72;
wire [4:0] VAR195;
wire [3*VAR191-1:0] VAR79;
wire [2*VAR191-1:0] VAR86;
wire [4*VAR116-1:0] VAR22;
wire [1:0] VAR137;
wire [1:0] VAR141;
wire [1:0] VAR215;
wire [VAR191-1:0] VAR33;
wire [5*VAR191-1:0] VAR245;
wire [5*VAR191-1:0] VAR37;
wire [2*VAR191-1:0] VAR40;
wire [5*VAR191-1:0] VAR109;
wire [5*VAR191-1:0] VAR153;
wire VAR126;
wire VAR45;
wire VAR119;
wire VAR154;
wire VAR238;
wire VAR244;
wire VAR32;
wire VAR57;
wire VAR210;
wire VAR202;
wire VAR88;
wire VAR18;
wire VAR253;
wire VAR239;
wire VAR61;
wire VAR95;
wire VAR193;
wire VAR247;
wire [4:0] VAR231;
wire [19:0] VAR242;
wire [255:0] VAR59;
wire [255:0] VAR106;
wire [255:0] VAR108;
wire [255:0] VAR121;
wire [3:0] VAR236;
wire [VAR191-1:0] VAR110;
wire [VAR199-1:0] VAR94;
wire [VAR199-1:0] VAR7;
wire [VAR199-1:0] VAR208;
wire VAR44;
wire [35:0] VAR203;
wire [383:0] VAR181;
wire [7:0] VAR13;
wire [255:0] VAR161;
wire [35:0] VAR170;
wire [255:0] VAR68;
wire [35:0] VAR196;
wire [255:0] VAR135;
wire [35:0] VAR67;
wire VAR220;
wire [35:0] VAR184;
wire [31:0] VAR240;
assign VAR42 = 1'b0;
assign VAR252 = clk;
assign VAR29 = rst;
VAR120 VAR225
(
.VAR185 (VAR15),
.VAR155 (VAR237),
.VAR52 (1'b0),
.VAR56 (1'b1)
);
VAR120 VAR62
(
.VAR185 (VAR165),
.VAR155 (VAR30),
.VAR52 (1'b0),
.VAR56 (1'b1)
);
assign VAR82 = 1'b0;
assign VAR201 = 1'b0;
VAR221 #
(
.VAR50 (VAR50),
.VAR31 (VAR31),
.VAR71 (VAR71),
.VAR131 (VAR131)
)
VAR171
(
.VAR85 (VAR85),
.VAR177 (VAR177),
.VAR82 (VAR82),
.VAR97 (VAR97),
.VAR113 (VAR113)
);
VAR8 #
(
.VAR71 (VAR71)
)
VAR83
(
.VAR173 (VAR173),
.VAR9 (VAR9),
.VAR201 (VAR201),
.VAR4 (VAR4)
);
VAR129 #
(
.VAR50 (VAR50),
.VAR23 (VAR183),
.VAR69 (VAR69),
.VAR140 (VAR140),
.VAR80 (VAR80),
.VAR142 (VAR142),
.VAR255 (VAR255),
.VAR131 (VAR131)
)
VAR251
(
.VAR96 (VAR96),
.clk (clk),
.VAR160 (VAR160),
.VAR167 (rst),
.VAR4 (VAR4),
.VAR97 (VAR97),
.VAR113 (VAR113),
.VAR180 (VAR146),
.VAR112 (VAR49),
.VAR213 (VAR197)
);
VAR124 #
(
.VAR16 (VAR16),
.VAR159 (VAR159),
.VAR144 (VAR144),
.VAR151 (VAR151),
.VAR69 (VAR69),
.VAR217 (VAR217),
.VAR92 (VAR92),
.VAR107 (VAR107),
.VAR14 (VAR14),
.VAR11 (VAR11),
.VAR31 (VAR31),
.VAR116 (VAR116),
.VAR191 (VAR191),
.VAR199 (VAR199),
.VAR228 (VAR228),
.VAR139 (VAR139),
.VAR234 (VAR234),
.VAR227 (VAR227),
.VAR175 (VAR175),
.VAR169 (VAR169),
.VAR212 (VAR212),
.VAR19 (VAR19),
.VAR73 (VAR73),
.VAR246 (VAR246),
.VAR99 (VAR99),
.VAR168 (VAR168),
.VAR2 (VAR2),
.VAR10 (VAR10),
.VAR39 (VAR39),
.VAR216 (VAR216),
.VAR132 (VAR132),
.VAR130 (VAR130),
.VAR230 (VAR230),
.VAR204 (VAR204),
.VAR205 (VAR205),
.VAR70 (VAR70),
.VAR91 (VAR91),
.VAR233 (VAR233),
.VAR254 (VAR254),
.VAR206 (VAR206),
.VAR50 (VAR50),
.VAR190 (VAR190),
.VAR26 (VAR26)
)
VAR192
(
.clk (clk),
.VAR96 (VAR96),
.VAR160 (VAR160),
.rst (rst),
.VAR209 (VAR48),
.VAR17 (VAR53),
.VAR243 (VAR81),
.VAR24 (VAR114),
.VAR149 (VAR188),
.VAR100 (VAR178),
.VAR5 (VAR25),
.VAR125 (VAR134),
.VAR87 (VAR143),
.VAR1 (VAR34),
.VAR186 (VAR90),
.VAR150 (VAR103),
.VAR98 (VAR187),
.VAR211 (VAR157),
.VAR6 (VAR207),
.VAR241 (VAR3),
.VAR49 (VAR49),
.VAR197 (VAR197),
.VAR146 (VAR146),
.VAR148 (VAR148),
.VAR219 (VAR219),
.VAR47 (VAR66),
.VAR46 (VAR46),
.VAR122 (VAR122),
.VAR179 (VAR179),
.VAR166 (VAR166),
.VAR250 (VAR250),
.VAR63 (VAR63),
.VAR158 (VAR158),
.VAR194 (VAR194),
.VAR42 (VAR42),
.VAR51 (1'b1),
.VAR249 (VAR249),
.VAR163 (VAR163),
.VAR12 (VAR12),
.VAR60 (VAR60),
.VAR153 (VAR153),
.VAR109 (VAR109),
.VAR126 (VAR126),
.VAR247 (VAR247),
.VAR95 (VAR95),
.VAR193 (VAR193),
.VAR33 (VAR33),
.VAR40 (VAR40),
.VAR37 (VAR37),
.VAR245 (VAR245),
.VAR215 (VAR215),
.VAR137 (VAR137),
.VAR141 (VAR141),
.VAR176 (VAR176),
.VAR36 (VAR36),
.VAR89 (VAR89),
.VAR79 (VAR79),
.VAR86 (VAR86),
.VAR195 (VAR195),
.VAR75 (VAR75),
.VAR28 (VAR28),
.VAR72 (VAR72),
.VAR145 (VAR145),
.VAR222 (VAR222),
.VAR123 (VAR123),
.VAR133 (VAR133),
.VAR64 (VAR64),
.VAR20 (VAR20),
.VAR248 (VAR248),
.VAR218 (VAR218),
.VAR111 (VAR111),
.VAR22 (VAR22)
);
generate
if (VAR11 == "VAR65") begin: VAR164
assign VAR153 = 'b0;
assign VAR109 = 'b0;
assign VAR126 = 1'b0;
assign VAR75 = 1'b0;
assign VAR28 = 1'b0;
assign VAR72 = 1'b0;
assign VAR21 = 1'b0;
assign VAR145 = 1'b0;
assign VAR222 = 1'b0;
assign VAR123 = 1'b0;
assign VAR133 = 1'b0;
assign VAR64 = 'b0;
assign VAR20 = 1'b0;
assign VAR236 = 'b0 ;
assign VAR94 = 'b0 ;
assign VAR7 = 'b0 ;
assign VAR208 = 'b0 ;
assign VAR248 = 1'b0;
end
endgenerate
generate
if (VAR11 == "VAR93") begin: VAR105
assign VAR153 = 'b0;
assign VAR109 = 'b0;
assign VAR126 = 1'b0;
assign VAR20 = 1'b0;
assign VAR248 = 1'b0;
assign VAR44 = clk;
assign VAR13[1:0] = VAR137;
assign VAR13[3:2] = VAR141;
assign VAR13[4] = VAR148;
assign VAR13[5] = 1'b0; assign VAR13[7:5] = 'b0;
if (VAR116 <= 72) begin: VAR104
assign VAR181[4*VAR116-1:0] = VAR22;
end else begin: VAR232
assign VAR181[287:0] = VAR22[287:0];
end
assign VAR181[289:288] = VAR137;
assign VAR181[291:290] = VAR141;
assign VAR181[292] = VAR148;
assign VAR181[293] = 1'b0; assign VAR181[383:294] = 'b0;
if (VAR191 <= 18) begin: VAR55
assign VAR161[5*VAR191-1:0] = VAR245;
assign VAR161[5*VAR191+89:90] = VAR37;
assign VAR161[VAR191+179:180] = VAR33;
assign VAR161[2*VAR191+197:198] = VAR40;
end else begin: VAR198
assign VAR161[89:0] = VAR245[89:0];
assign VAR161[179:90] = VAR37[89:0];
assign VAR161[197:180] = VAR33[17:0];
assign VAR161[233:198] = VAR40[35:0];
end
assign VAR161[235:234] = VAR137[1:0];
assign VAR161[237:236] = VAR141[1:0];
assign VAR161[238] = VAR148;
assign VAR161[239] = 1'b0; assign VAR161[240] = 1'b0; assign VAR161[255:241] = 'b0;
if (VAR191 <= 18) begin: VAR76
assign VAR68[5*VAR191-1:0] = VAR176;
assign VAR68[5*VAR191+89:90] = 'b0;
assign VAR68[3*VAR191+179:180] = VAR79;
end else begin: VAR138
assign VAR68[89:0] = VAR176[89:0];
assign VAR68[179:90] = 'b0;
assign VAR68[233:180] = VAR79[53:0];
end
assign VAR68[238:234] = VAR195;
assign VAR68[255:239] = 'b0;
if (VAR191 <= 18) begin: VAR156
assign VAR135[5*VAR191-1:0] = VAR36;
assign VAR135[5*VAR191+89:90] = VAR89;
assign VAR135[2*VAR191+179:180] = VAR86;
end else begin: VAR35
assign VAR135[89:0] = VAR36[89:0];
assign VAR135[179:90] = VAR89[89:0];
assign VAR135[215:180] = VAR86[35:0];
end
assign VAR135[255:216] = 'b0;
assign VAR220 = clk;
assign VAR75 = VAR240[0];
assign VAR28 = VAR240[1];
assign VAR72 = VAR240[2];
assign VAR21 = VAR240[3];
assign VAR145 = VAR240[4];
assign VAR222 = VAR240[5];
assign VAR123 = VAR240[6];
assign VAR133 = VAR240[7];
assign VAR64 = VAR240[VAR199+7:8];
VAR182 VAR41
(
.VAR223 (VAR203),
.VAR77 (VAR170),
.VAR174 (VAR196),
.VAR226 (VAR67),
.VAR78 (VAR184)
);
VAR128 VAR117
(
.VAR74 (VAR44),
.VAR43 (VAR181),
.VAR38 (VAR13),
.VAR27 (VAR203)
);
VAR172 VAR235
(
.VAR200 (VAR161),
.VAR27 (VAR170)
);
VAR172 VAR54
(
.VAR200 (VAR68),
.VAR27 (VAR196)
);
VAR172 VAR229
(
.VAR200 (VAR135),
.VAR27 (VAR67)
);
VAR162 VAR214
(
.VAR102 (VAR240),
.VAR74 (VAR220),
.VAR27 (VAR184)
);
end
endgenerate
endmodule
|
lgpl-3.0
|
ChrisPVille/RL02
|
FPGA/driveControl.v
| 9,879 |
module MODULE1(
input clk,
input rst,
input [15:0] VAR2,
input VAR6,
input VAR7,
input [5:0] VAR16,
input [8:0] VAR39,
input VAR14,
input VAR28,
input VAR44,
input VAR20,
input VAR29,
input VAR15,
input VAR43,
output reg VAR4,
output reg VAR12,
output reg VAR41,
output reg VAR40,
output reg VAR27,
output VAR35
);
reg [3:0] VAR26;
reg [15:0] VAR31;
reg [3:0] VAR38;
reg [15:0] VAR25;
reg [4:0] VAR19;
reg VAR9;
reg [3:0] VAR46;
reg VAR33;
reg [3:0] VAR21;
reg [8:0] VAR3;
reg [5:0] VAR18;
reg [15:0] VAR10;
reg [3:0] VAR45;
reg [3:0] VAR24;
parameter [3:0]
VAR22 = 4'b0000, VAR8 = 4'b0001, VAR11 = 4'b0010, VAR47 = 4'b0011, VAR34 = 4'b0100, VAR30 = 4'b0101, VAR36 = 4'b0110, VAR37 = 4'b0111, VAR32 = 4'b1000, VAR5 = 4'b1001;
assign VAR35 = VAR46[3];
always @(posedge clk) begin
if(rst) begin
VAR46 <= 0;
VAR33 <= 0;
end else begin
VAR46 <= VAR46 + 1;
if(VAR46 == 0) begin
VAR33 <= 1;
end else begin
VAR33 <= 0;
end
end
end
always @(posedge clk) begin
if(rst) begin
VAR26 <= VAR22;
VAR24 <= VAR8;
VAR4 <= 0;
VAR31 <= 16'b0;
VAR25 <= 16'b0;
VAR19 <= 5'b0;
VAR9 <= 0;
VAR41 <= 0;
VAR45 <= 4'b0;
VAR10 <= 16'b1111111111111111;
VAR21 <= 4'b0;
VAR18 <= 6'b0;
VAR3 <= 8'b0;
VAR38 <= 4'b0;
VAR40 <= 0;
VAR27 <= 0;
VAR12 <= 0;
end else begin
VAR4 <= 0;
case (VAR26)
VAR22:
begin
if(VAR29) begin
VAR25[3] <= 1; VAR25[1] <= 0; VAR25[0] <= 1; VAR24 <= VAR8;
VAR26 <= VAR34;
end
end
VAR8:
begin
if(~VAR6) begin
VAR31 <= VAR2;
VAR26 <= VAR11;
VAR4 <= 1;
end
end
VAR11:
begin
VAR26 <= VAR8;
case (VAR31[15:13])
3'b001:
begin
VAR26 <= VAR47;
end
3'b010:
begin
VAR26 <= VAR37;
end
endcase
end
VAR47:
begin
VAR12 <= 1;
VAR24 <= VAR36;
VAR26 <= VAR34; VAR25[4] <= VAR31[10]; VAR25[3] <= 0; VAR25[1] <= 0; VAR25[0] <= 1;
VAR25[2] <= VAR31[9]; VAR25[15:7] <= VAR31[8:0]; end
VAR34:
begin
if(VAR7) begin
VAR26 <= VAR30;
end
end
VAR30:
begin
if(~VAR7 | VAR9) begin
VAR9 <= 1;
if(VAR33) begin
if(VAR19 < 16) begin VAR19 <= VAR19 + 1;
VAR27 <= VAR25[0];
VAR25 <= {1'b0, VAR25[15:1]};
end else begin
VAR27 <= 0;
VAR19 <= 5'b0;
VAR25 <= 16'b0;
VAR9 <= 0;
VAR26 <= VAR24; end
end
end
end
VAR36:
begin
if(VAR29 & VAR7) begin
VAR26 <= VAR8;
VAR12 <= 0;
end
end
VAR37: begin
if(~VAR6) begin
VAR18 <= VAR2[5:0];
VAR4 <= 1;
VAR26 <= VAR32;
end
end
VAR32: begin if(VAR43) begin if(VAR14) begin if(VAR18 == VAR16) begin if(VAR15) begin VAR12 <= 1;
VAR26 <= VAR5;
end
end
end
end
end
VAR5: begin
if(VAR38 == 15) begin
VAR4 <= 1; end
VAR45 <= VAR45 + 1;
VAR41 <= VAR10[15];
if(VAR45 == 0) begin
VAR3 <= VAR3 + 1;
VAR21 <= {VAR21[2:0], VAR2[VAR38]};
VAR38 <= VAR38 + 1;
casez (VAR21) 4'b0000:
if(VAR2[VAR38]) begin VAR10 <= 16'b0000111111111110; end else begin
VAR10 <= 16'b0000111111111111; end
4'b0001:
VAR10 <= 16'b0000111111111111; 4'VAR42:
VAR10 <= 16'b1111111100001111; 4'VAR23:
VAR10 <= 16'b1111111110000111; 4'VAR1:
VAR10 <= 16'b1111111111111111; 4'VAR13:
VAR10 <= 16'b1111111000011111; 4'VAR17:
VAR10 <= 16'b1111111100001111; 4'b1000:
if(VAR2[VAR38]) begin VAR10 <= 16'b1000011111111110; end else begin
VAR10 <= 16'b1000011111111111; end
4'b1001:
VAR10 <= 16'b0000111111111111; endcase
end else begin
VAR10 <= VAR10<<1;
end
if(VAR3 > 133) begin
VAR3 <= 8'b0;
VAR4 <= 0;
VAR38 <= 4'b0;
VAR40 <= 0;
VAR10 <= 16'b1111111111111111;
VAR12 <= 0;
VAR26 <= VAR8;
end
end
default:
VAR26 <= VAR8;
endcase
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dlxbn/sky130_fd_sc_ls__dlxbn.blackbox.v
| 1,339 |
module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR7
);
output VAR4 ;
output VAR1 ;
input VAR2 ;
input VAR7;
supply1 VAR8;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
alexforencich/xfcp
|
lib/eth/rtl/axis_xgmii_rx_32.v
| 11,996 |
module MODULE1 #
(
parameter VAR16 = 32,
parameter VAR7 = (VAR16/8),
parameter VAR14 = (VAR16/8),
parameter VAR17 = 0,
parameter VAR11 = 96,
parameter VAR4 = (VAR17 ? VAR11 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR16-1:0] VAR6,
input wire [VAR14-1:0] VAR2,
output wire [VAR16-1:0] VAR8,
output wire [VAR7-1:0] VAR15,
output wire VAR3,
output wire VAR5,
output wire [VAR4-1:0] VAR9,
input wire [VAR11-1:0] VAR1,
output wire VAR13,
output wire VAR12,
output wire VAR10
);
|
mit
|
jotego/jt12
|
hdl/mixer/jt12_comb.v
| 1,627 |
module MODULE1 #(parameter
VAR1=16, VAR5=1 )(
input rst,
input clk,
input VAR9,
input signed [VAR1-1:0] VAR3,
output reg signed [VAR1-1:0] VAR6
);
wire signed [VAR1-1:0] VAR8;
generate
genvar VAR2;
reg signed [VAR1-1:0] VAR7[0:VAR5-1];
assign VAR8=VAR7[VAR5-1];
for(VAR2=0;VAR2<VAR5;VAR2=VAR2+1) begin : VAR4
always @(posedge clk)
if(rst) begin
VAR7[VAR2] <= {VAR1{1'b0}};
end else if(VAR9) begin
VAR7[VAR2] <= VAR2==0 ? VAR3 : VAR7[VAR2-1];
end
end
endgenerate
always @(posedge clk)
if(rst) begin
VAR6 <= {VAR1{1'b0}};
end else if(VAR9) begin
VAR6 <= VAR3 - VAR8;
end
endmodule MODULE1
|
gpl-3.0
|
chahuja/hilbert-fpga
|
mpuc1307.v
| 1,784 |
module MODULE1 ( VAR10,VAR19 ,VAR12, VAR22,VAR18,VAR11 ,VAR8 ,VAR21 );
parameter VAR2 = 32;
input VAR10 ;
wire VAR10 ;
input VAR19 ;
wire VAR19 ;
input VAR12; input VAR22 ; wire VAR22 ;
input [VAR2-1:0] VAR18 ;
wire signed [VAR2-1:0] VAR18 ;
input [VAR2-1:0] VAR11 ;
wire signed [VAR2-1:0] VAR11 ;
output [VAR2:0] VAR8 ;
reg [VAR2:0] VAR8 ;
output [VAR2:0] VAR21 ;
reg [VAR2:0] VAR21 ;
reg signed [VAR2+2 :0] VAR16;
reg signed [VAR2-1 :0] VAR6;
reg signed [VAR2-1 :0] VAR20;
reg signed [VAR2 : 0] VAR23;
wire signed [VAR2+3 : 0] VAR14;
wire signed [VAR2+3 : 0] VAR17;
reg VAR3,VAR7, VAR15; reg VAR4,VAR13,VAR9;
reg [VAR2:0] VAR5 ;
reg [VAR2:0] VAR1 ;
always @(posedge VAR10)
begin
if (VAR12) begin
VAR3<=VAR19;
VAR7<=VAR3;
VAR15<=VAR7;
VAR4<=VAR22;
VAR13<=VAR4;
VAR9<=VAR13; if (VAR19) begin VAR16<=VAR18+(VAR18 <<2); VAR6<=VAR18-(VAR18>>>3); VAR23<=VAR18;
VAR20<=VAR11;
end
else begin
VAR16<=VAR20+(VAR20 <<2); VAR6<=VAR20-(VAR20>>>3); VAR23<=VAR20;
end
VAR5<=VAR17 >>>3;
VAR1<=VAR5;
if (VAR15)
if (VAR9) begin
VAR8<=VAR5;
VAR21<= - VAR1; end
else begin
VAR8<=VAR1;
VAR21<= VAR5; end
end
end
assign VAR14=(VAR16<<1)+(VAR6>>>1);
assign VAR17= (VAR14+(VAR23>>>6) -(VAR16>>>13));
endmodule
|
gpl-2.0
|
m-labs/milkymist
|
cores/ac97/rtl/ac97_ctlif.v
| 4,605 |
module MODULE1 #(
parameter VAR17 = 4'h0
) (
input VAR18,
input VAR5,
input [13:0] VAR7,
input VAR16,
input [31:0] VAR10,
output reg [31:0] VAR20,
output reg VAR32,
output reg VAR38,
output reg VAR29,
output reg VAR2,
input VAR3,
input VAR33,
output reg VAR30,
output reg [19:0] VAR15,
output reg VAR11,
output reg [19:0] VAR19,
input VAR26,
input VAR8,
input VAR41,
input VAR39,
input [19:0] VAR40,
input VAR24,
input [19:0] VAR14,
output reg VAR34,
output reg [29:0] VAR42,
output reg [15:0] VAR35,
input VAR9,
output reg VAR13,
output reg [29:0] VAR23,
output reg [15:0] VAR31,
input VAR4
);
wire VAR36 = VAR35 == 16'd0;
reg VAR22;
always @(posedge VAR18) begin
if(VAR5)
VAR22 <= 1'b1;
end
else
VAR22 <= VAR36;
end
wire VAR1 = VAR31 == 16'd0;
reg VAR28;
always @(posedge VAR18) begin
if(VAR5)
VAR28 <= 1'b1;
end
else
VAR28 <= VAR1;
end
wire VAR12 = VAR7[13:10] == VAR17;
reg VAR6;
reg VAR21;
reg [6:0] VAR37;
reg [15:0] VAR27;
reg [15:0] VAR25;
always @(posedge VAR18) begin
if(VAR5) begin
VAR20 <= 32'd0;
VAR6 <= 1'b0;
VAR21 <= 1'b0;
VAR37 <= 7'd0;
VAR27 <= 16'd0;
VAR30 <= 1'b0;
VAR11 <= 1'b0;
VAR34 <= 1'b0;
VAR42 <= 30'd0;
VAR35 <= 16'd0;
VAR13 <= 1'b0;
VAR23 <= 30'd0;
VAR31 <= 16'd0;
VAR32 <= 1'b0;
VAR38 <= 1'b0;
VAR29 <= 1'b0;
VAR2 <= 1'b0;
end else begin
VAR32 <= 1'b0;
VAR38 <= 1'b0;
VAR29 <= 1'b0;
VAR2 <= 1'b0;
if(VAR3 & VAR33) begin
VAR30 <= VAR6;
VAR15 <= {20{VAR6}} & {~VAR21, VAR37, 12'd0};
VAR11 <= VAR6 & VAR21;
VAR19 <= {20{VAR6 & VAR21}} & {VAR27, 4'd0};
VAR6 <= 1'b0;
if(VAR6)
VAR32 <= 1'b1;
end
if(VAR26 & VAR8) begin
if(VAR41 & VAR39 & VAR24) begin
VAR38 <= 1'b1;
VAR25 <= VAR14[19:4];
end
end
if(VAR9) begin
VAR42 <= VAR42 + 30'd1;
VAR35 <= VAR35 - 16'd1;
end
if(VAR4) begin
VAR23 <= VAR23 + 30'd1;
VAR31 <= VAR31 - 16'd1;
end
if(VAR36 & ~VAR22)
VAR29 <= 1'b1;
if(VAR1 & ~VAR28)
VAR2 <= 1'b1;
VAR20 <= 32'd0;
if(VAR12) begin
if(VAR16) begin
case(VAR7[3:0])
4'b0000: begin
VAR6 <= VAR10[0];
VAR21 <= VAR10[1];
end
4'b0001: VAR37 <= VAR10[6:0];
4'b0010: VAR27 <= VAR10[15:0];
4'b0100: VAR34 <= VAR10[0];
4'b0101: VAR42 <= VAR10[31:2];
4'b0110: VAR35 <= VAR10[17:2];
4'b1000: VAR13 <= VAR10[0];
4'b1001: VAR23 <= VAR10[31:2];
4'b1010: VAR31 <= VAR10[17:2];
endcase
end
case(VAR7[3:0])
4'b0000: VAR20 <= {VAR21, VAR6};
4'b0001: VAR20 <= VAR37;
4'b0010: VAR20 <= VAR27;
4'b0011: VAR20 <= VAR25;
4'b0100: VAR20 <= VAR34;
4'b0101: VAR20 <= {VAR42, 2'b00};
4'b0110: VAR20 <= {VAR35, 2'b00};
4'b1000: VAR20 <= VAR13;
4'b1001: VAR20 <= {VAR23, 2'b00};
4'b1010: VAR20 <= {VAR31, 2'b00};
endcase
end
end
end
endmodule
|
lgpl-3.0
|
Jesus89/open-fpga-verilog-tutorial
|
tutorial/ICESTICK/T29-tristate/tristate2.v
| 1,852 |
module MODULE1 (
input wire clk, output wire VAR8);
parameter VAR6 = VAR7;
wire VAR1;
wire VAR4;
reg VAR11 = 0;
reg [3:0] VAR12;
reg VAR2;
always @(posedge clk)
VAR2 <= 1'b1;
reg VAR13;
always @(posedge clk)
VAR13 <= 1'b0;
reg VAR3;
always @(posedge clk)
VAR3 <= 1'b1;
assign VAR4 = (VAR12[0]) ? VAR2 : 1'VAR5;
assign VAR4 = (VAR12[1]) ? VAR13 : 1'VAR5;
assign VAR4 = (VAR12[2]) ? VAR3 : 1'VAR5;
assign VAR8 = VAR4;
always @(posedge clk)
if (!VAR11)
VAR12 <= 4'b0001;
else if (VAR1)
VAR12 <= {VAR12[2:0],VAR12[3]};
always @(posedge clk)
VAR11 <= 1'b1;
VAR10 #(VAR6)
VAR14 (
.clk(clk),
.VAR9(VAR1)
);
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.v
| 2,678 |
module MODULE2 (
VAR6 ,
VAR12 ,
VAR5 ,
VAR9 ,
VAR11 ,
VAR10,
VAR3 ,
VAR7 ,
VAR1 ,
VAR13 ,
VAR8
);
output VAR6 ;
input VAR12 ;
input VAR5 ;
input VAR9 ;
input VAR11 ;
input VAR10;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR13 ;
input VAR8 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR13(VAR13),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR6 ,
VAR12 ,
VAR5 ,
VAR9 ,
VAR11 ,
VAR10
);
output VAR6 ;
input VAR12 ;
input VAR5 ;
input VAR9 ;
input VAR11 ;
input VAR10;
supply1 VAR3;
supply1 VAR7 ;
supply0 VAR1 ;
supply1 VAR13 ;
supply0 VAR8 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR10(VAR10)
);
endmodule
|
apache-2.0
|
joaocarlos/udlx-verilog
|
rtl/common/mux_sdram.v
| 1,024 |
module MODULE1
parameter VAR4 = 32,
parameter VAR3 = 32
)
(
input VAR5,
input [VAR4-1:0] VAR6,
input [VAR3-1:0] VAR2,
output reg [VAR4-1:0] VAR8,
output reg VAR1,
output reg [VAR4-1:0] VAR7,
output reg VAR9
);
always @(*) begin
if (VAR5) begin
if(VAR2[VAR3-1]==1) begin
VAR8 = VAR6;
VAR1 =1;
VAR9 = 0;
VAR7 = {VAR4{1'b0}};
end
else begin
VAR8 = {VAR4{1'b0}};
VAR1 = 0;
VAR9 = 1;
VAR7 = VAR6;
end
end
else begin
VAR8 = {VAR4{1'b0}};
VAR9 = 0;
VAR7 = {VAR4{1'b0}};
VAR1 = 0;
end
end
endmodule
|
lgpl-3.0
|
stevenokm/mor1kx
|
rtl/verilog/mor1kx_fetch_prontoespresso.v
| 18,958 |
module MODULE1
(
VAR89, VAR10, VAR95, VAR93, VAR17,
VAR26, VAR47, VAR76, VAR53,
VAR81, VAR2, VAR96,
VAR34, VAR59, VAR21,
clk, rst, VAR14, VAR24, VAR48, VAR77, VAR51,
VAR86, VAR66, VAR8, VAR79,
VAR13, VAR58, VAR46,
VAR42, VAR7, VAR25, VAR11, VAR50,
VAR3, VAR29, VAR4, VAR75
);
parameter VAR33 = 32;
parameter VAR20 = 5;
parameter VAR71 = {{(VAR33-13){1'b0}},
parameter VAR98 = "VAR73";
parameter VAR60 = 3; parameter VAR91 = "VAR73";
input clk, rst;
output [VAR33-1:0] VAR89;
output VAR10;
output VAR95;
input VAR14;
input VAR24;
input [VAR74-1:0] VAR48;
input VAR77;
input VAR51;
output reg [VAR74-1:0] VAR93;
output [VAR33-1:0] VAR17;
output VAR26;
output [VAR20-1:0] VAR47;
output [VAR20-1:0] VAR76;
output VAR53;
output [VAR33-1:0] VAR81;
input VAR86;
input [VAR33-1:0] VAR66;
input VAR8;
input VAR79;
input [VAR33-1:0] VAR13;
input VAR58;
input VAR46;
input VAR42;
input VAR7;
input VAR25, VAR11, VAR50;
output reg VAR2;
output VAR96;
output VAR34;
input [15:0] VAR3;
input VAR29;
input VAR4;
input [VAR33-1:0] VAR75;
output [VAR33-1:0] VAR59;
output VAR21;
reg [VAR33-1:0] VAR32;
reg [VAR33-1:0] VAR72;
reg VAR63;
reg VAR18;
reg VAR27;
reg VAR55;
reg VAR94;
reg [1:0] VAR37;
reg VAR70;
reg VAR68;
reg VAR92;
reg VAR1;
reg VAR28;
reg VAR40;
reg VAR80;
reg VAR67;
reg VAR36;
reg VAR82;
wire [VAR74-1:0] VAR39;
wire VAR22;
wire [VAR33-1:0] VAR6;
wire [VAR33-1:0] VAR88;
wire [VAR33-1:0] VAR90;
wire VAR84;
wire VAR5;
wire [VAR54-1:0] VAR61;
wire VAR15;
wire VAR16;
wire VAR19;
wire [VAR74-1:0] VAR85;
wire VAR30;
wire VAR44;
assign VAR88 = VAR32 + 4;
assign VAR6 = VAR27 ?
VAR90 : VAR88;
assign VAR89 = VAR32;
assign VAR10 = (VAR63 & !(VAR58)
& !(VAR46 & VAR63)
& !VAR19) |
VAR40;
assign VAR95 = 0;
assign VAR26 = VAR22 | VAR55 | VAR14;
assign VAR81 = VAR6;
assign VAR39 = VAR16 ? VAR85 : VAR48;
assign VAR22 = VAR16 | VAR24;
assign VAR47 = VAR22 ? VAR39[VAR45] : 0;
assign VAR76 = VAR22 ? VAR39[VAR52] : 0;
assign VAR53 = VAR22 & (VAR51 | VAR7) &
!(VAR80 | VAR30);
assign VAR61 = VAR39[VAR69];
assign VAR90 = {VAR33{VAR27}} &
({{4{VAR39[25]}},
VAR39[VAR64],
2'b00} + VAR32);
assign VAR15 = VAR27 &
(VAR90 == VAR32);
assign VAR96 = VAR28;
assign VAR84 = VAR70 & !VAR51 & VAR63 & !VAR68;
assign VAR5 = !VAR70 & VAR51;
assign VAR30 = (VAR5 &
VAR16 & VAR92 &
!VAR67 &
VAR37[1]) ||
VAR82;
always @*
if (VAR22)
case (VAR61)
VAR27 = 1;
VAR18 = 1;
VAR80 = 1;
end
VAR27 = 0;
VAR18 = 1;
VAR80 = 0;
end
VAR27 = !(VAR25 | VAR50) | VAR11;
VAR18 = !(VAR25 | VAR50) | VAR11;
VAR80 = 1;
end
VAR27 = !(!VAR25 | VAR11) |VAR50;
VAR18 = !(!VAR25 | VAR11) |VAR50;
VAR80 = 1;
end
VAR27 = 0;
VAR18 = 1;
VAR80 = 1;
end
default: begin
VAR27 = 0;
VAR18 = 0;
VAR80 = 0;
end
endcase else
begin
VAR27 = 0;
VAR18 = 0;
VAR80 = 0;
end
always @(posedge clk VAR65)
if (rst)
begin
VAR32 <= VAR71;
VAR72 <= VAR71;
end
else if (VAR86 & !VAR94)
begin
VAR32 <= VAR66;
end
else if (VAR58 & !VAR42)
begin
VAR32 <= VAR66;
end
else if (VAR22 & (VAR51 | VAR7) &
!VAR30)
begin
VAR32 <= VAR81;
VAR72 <= VAR32;
end
else if (VAR79)
begin
VAR32 <= VAR13;
end
else if (VAR58 & VAR42)
begin
VAR32 <= VAR13;
end
always @(posedge clk VAR65)
if (rst)
VAR67 <= 0;
else if (VAR86 & !VAR94)
VAR67 <= !VAR22;
else if (VAR22 & (VAR51 | VAR7) & !VAR84)
VAR67 <= 0;
assign VAR17 = VAR72;
assign VAR44 = VAR22 &
(VAR51 | VAR7) &
!VAR84 &
!VAR30 &
!((VAR86 & VAR51 &
!VAR94) |
VAR58);
always @(posedge clk VAR65)
if (rst)
VAR93 <= {VAR35,26'd0};
else if (VAR28 | VAR42)
VAR93 <= {VAR35,26'd0};
else if (VAR44)
VAR93 <= VAR39;
else if (VAR86 & VAR51)
VAR93 <= {VAR35,26'd0};
else if (VAR58)
VAR93 <= {VAR35,26'd0};
else if (VAR94)
VAR93 <= {VAR35,26'd0};
else if (VAR8 & !VAR22)
VAR93 <= {VAR35,26'd0};
always @(posedge clk VAR65)
if (rst)
VAR63 <= 1'b1;
else if (VAR63 & VAR7 & VAR22)
VAR63 <= 1'b0;
else if (!VAR63 & VAR42)
VAR63 <= 1'b0;
else if (VAR14)
VAR63 <= 1'b0;
else if (VAR28)
VAR63 <= 1'b0;
else if (VAR18)
VAR63 <= 1'b0;
else if (VAR46)
VAR63 <= 1'b0;
else if (VAR84)
VAR63 <= 1'b0;
else if (VAR19)
VAR63 <= 1'b0;
else
VAR63 <= 1'b1;
always @(posedge clk VAR65)
if (rst)
VAR36 <= 0;
else if (VAR51)
VAR36 <= VAR94 & VAR16 &
!VAR58;
else if (VAR8)
VAR36 <= 0;
always @(posedge clk VAR65)
if (rst)
VAR82 <= 0;
else if (VAR92 | VAR51)
VAR82 <= VAR36 &
!VAR26;
else if (VAR8)
VAR82 <= 0;
always @(posedge clk VAR65)
if (rst)
VAR55 <= 0;
else if (VAR28)
VAR55 <= 0;
else if (!VAR55 & VAR18 & VAR22 & VAR51)
VAR55 <= 1;
else
VAR55 <= 0;
always @(posedge clk VAR65)
if (rst)
VAR94 <= 0;
else if (VAR28)
VAR94 <= 0;
else if (VAR18 & VAR27 & VAR51)
VAR94 <= 1;
else
VAR94 <= 0;
always @(posedge clk VAR65)
if (rst)
VAR37 <= 0;
else
VAR37 <= {VAR37[0], VAR94};
always @(posedge clk)
VAR70 <= VAR51;
always @(posedge clk)
begin
VAR68 <= (VAR86 | VAR58) &
VAR26;
VAR92 <= VAR68;
end
always @(posedge clk VAR65)
if (rst)
VAR2 <= 0;
else if ((VAR51 | VAR58) &
VAR86 | VAR42)
VAR2 <= 0;
else if (VAR63)
VAR2 <= VAR14;
always @(posedge clk VAR65)
if (rst)
VAR28 <= 1'b0;
else if (VAR58 | VAR42)
VAR28 <= 1'b0;
else if (VAR15 & !VAR7)
VAR28 <= 1'b1;
always @(posedge clk VAR65)
if (rst)
VAR40 <= 0;
else if (VAR63 & VAR84 & !VAR22)
VAR40 <= 1;
else if (VAR22 & VAR40)
VAR40 <= 0;
genvar VAR78;
generate
if (VAR98 != "VAR43")
begin : VAR97
assign VAR16 = 0;
assign VAR19 = 0;
assign VAR85 = {VAR74{1'b0}};
assign VAR34 = 0;
end
else
begin : VAR49
localparam VAR41 = (1<<VAR60);
localparam VAR9 = VAR60+2;
reg VAR57 [0:VAR41-1];
wire VAR83;
wire VAR87;
reg [VAR74-1:0] VAR49 [0:VAR41-1];
reg [VAR33-1:VAR9] VAR31 [0:VAR41-1];
wire [VAR33-1:VAR9] VAR62;
wire [VAR60-1:0] VAR23;
wire [VAR74-1:0] VAR12;
assign VAR23 = VAR32[VAR60+1:2];
assign VAR62 = VAR32[VAR33-1:VAR9];
assign VAR19 = VAR57[VAR23] &
VAR31[VAR23]==VAR62;
assign VAR16 = VAR19 & !VAR68 &
!VAR58;
assign VAR85 = VAR49[VAR23];
assign VAR83 = VAR24 & !VAR14 &
!VAR15;
assign VAR87 = VAR4 & VAR29 &
(VAR3 == VAR56);
assign VAR34 = VAR68 & VAR16;
assign VAR21 = 1'b1;
for (VAR78=0;VAR78<VAR41;VAR78=VAR78+1)
begin : VAR38
always @(posedge clk VAR65)
if (rst)
begin
VAR31[VAR78] <= 'd0;
VAR57[VAR78] <= 1'b0;
end
else if (VAR87 | VAR42)
begin
VAR57[VAR78] <= 1'b0;
end
else if (VAR83 &
VAR23==VAR78[VAR60-1:0])
begin
VAR31[VAR78] <= VAR62;
VAR57[VAR78] <= 1'b1;
VAR49[VAR78] <= VAR48;
end
end
end endgenerate
assign VAR21 = 1'b1;
assign VAR59 = {VAR33{1'b0}};
endmodule
|
mpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.pp.symbol.v
| 1,336 |
module MODULE1 (
input VAR8 ,
input VAR7 ,
input VAR1,
output VAR2,
input VAR3 ,
input VAR6,
input VAR4,
input VAR5
);
endmodule
|
apache-2.0
|
GSejas/Karatsuba_FPU
|
Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/addsub/FPU_ADD_Substract_PIPELINED.v
| 24,837 |
module MODULE1
/*#(parameter VAR120 = 32, parameter VAR25 = 8, parameter VAR101 = 23,
parameter VAR155=26, parameter VAR149 = 5)
parameter VAR155 = 55, parameter VAR149 = 6) (
input wire clk,
input wire rst,
input wire VAR38,
input wire [VAR120-1:0] VAR141,
input wire [VAR120-1:0] VAR1,
input wire VAR81,
output wire VAR11,
output wire VAR36,
output wire VAR166,
output wire VAR145,
output wire ready,
output wire [VAR120-1:0] VAR117
);
wire VAR74;
wire VAR121;
wire [6:0] VAR13;
wire VAR49;
wire VAR165;
VAR164 VAR198 (
.clk (clk),
.rst (rst),
.VAR128 (VAR38),
.VAR21 (VAR121),
.VAR74 (VAR74),
.VAR165 (VAR165)
);
VAR160 #(.VAR120(7)) VAR78 (
.clk(clk),
.rst(rst),
.VAR187 (VAR165),
.VAR51 (VAR121),
.VAR82(VAR13));
wire VAR171;
wire [VAR120-1:0] VAR162, VAR124; wire VAR69;
wire VAR177;
wire VAR62, VAR137;
wire VAR3, VAR170;
wire [VAR120-2:0] VAR84, VAR184;
wire VAR127, VAR196, VAR52, VAR57;
wire [VAR120-2:0] VAR130, VAR35;
wire [VAR25-1:0] VAR151, VAR105;
wire [VAR101-1:0] VAR119, VAR186;
wire [VAR25-1:0] VAR15;
wire [VAR155-1:0]VAR192;
wire VAR100, VAR95, VAR116, VAR180;
wire [VAR120-2:0] VAR45;
wire [VAR101-1:0] VAR98;
wire [VAR149-1:0] VAR185;
wire [VAR149-1:0] VAR33;
wire VAR16;
wire VAR139;
wire [VAR155-1:0] VAR159; wire [VAR155-1:0] VAR7;
wire [VAR149-1:0] VAR79; wire [VAR155-1:0] VAR129[VAR149+1:0];
wire VAR68, VAR161, VAR194, VAR133;
wire [VAR120-2:0]VAR158;
wire [VAR149-1:0] VAR93;
wire VAR181;
wire VAR183;
wire [VAR155-1:0] VAR71; wire [VAR155-1:0] VAR30;
wire VAR91, VAR163;
wire [VAR25-1:0]VAR193;
reg [VAR25:0] VAR195;
wire [VAR25-1:0] VAR190;
wire [VAR25-1:0]VAR77;
wire VAR44, VAR10;
wire VAR59, VAR132, VAR43, VAR56;
wire VAR27;
wire [VAR155-1:0] VAR54;
wire [VAR155-1:0] VAR108;
wire [VAR25-1:0] VAR65;
reg VAR178;
reg [VAR155-1:0] VAR90;
wire [VAR120-2:0] VAR50;
wire VAR131, VAR28, VAR125, VAR140;
wire [VAR25-1:0]VAR153;
wire [VAR155-1:0] VAR48;
wire [VAR155-1:0] VAR103;
wire [VAR25-1:0] VAR66;
wire [VAR149-1:0] VAR110;
wire [VAR149-1:0] VAR143;
wire [VAR25-VAR149-1:0] VAR182;
wire VAR106, VAR167;
wire [VAR120-1:0] VAR89;
VAR22 #(.VAR120(VAR120)) VAR96 (
.clk(clk),
.rst(rst),
.VAR187(VAR74),
.VAR39(VAR141),
.VAR82(VAR162));
VAR22 #(.VAR120(VAR120)) VAR6 (
.clk(clk),
.rst(rst),
.VAR187(VAR74),
.VAR39(VAR1),
.VAR82(VAR124));
VAR22 #(.VAR120(1)) VAR118 (
.clk(clk),
.rst(rst),
.VAR187(VAR74),
.VAR39(VAR81),
.VAR82(VAR69));
VAR58 #(.VAR120(VAR120-1)) VAR189 (
.VAR75(VAR162[VAR120-2:0]),
.VAR32(VAR124[VAR120-2:0]),
.VAR73(VAR62),
.VAR67(VAR137)
);
VAR114 #(.VAR120(VAR120-1)) VAR175 (
.select(VAR62),
.VAR29(VAR162[VAR120-2:0]),
.VAR156(VAR124[VAR120-2:0]),
.VAR70(VAR84),
.VAR34(VAR184)
);
VAR99 #(.VAR120(VAR120)) VAR20 (
.VAR72(VAR162[VAR120-1]), .VAR176(VAR124[VAR120-1]), .VAR23(VAR69), .VAR76(VAR3)
);
VAR122 VAR150 (
.VAR94(VAR69),
.VAR31(VAR162[VAR120-1]),
.VAR88(VAR124[VAR120-1]),
.VAR154(VAR62),
.VAR83(VAR137),
.VAR2(VAR170)
);
assign VAR171 = VAR3 & VAR137;
VAR22 #(.VAR120(VAR120-1)) VAR19 (
.clk(clk),
.rst(rst),
.VAR187(VAR177),
.VAR39(VAR84),
.VAR82(VAR130));
VAR22 #(.VAR120(VAR120-1)) VAR8 (
.clk(clk),
.rst(rst),
.VAR187(VAR177),
.VAR39(VAR184),
.VAR82(VAR35));
VAR22 #(.VAR120(3)) VAR37 (
.clk(clk),
.rst(rst),
.VAR187(VAR177),
.VAR39({VAR170, VAR3, VAR171}),
.VAR82({VAR127 , VAR196 , VAR52}));
assign VAR151 = VAR130[VAR120-2:VAR120-VAR25-1]; assign VAR105 = VAR35[VAR120-2:VAR120-VAR25-1]; assign VAR119 = VAR130[VAR101-1:0];
assign VAR15 = VAR130[VAR120-2:VAR101] - VAR35[VAR120-2:VAR101];
assign VAR186 = VAR35[VAR101-1:0];
VAR22 #(.VAR120(VAR120-1)) VAR4 (
.clk(clk),
.rst(rst),
.VAR187(VAR57),
.VAR39(VAR130),
.VAR82(VAR45));
VAR22 #(.VAR120(VAR101)) VAR169 (
.clk(clk),
.rst(rst),
.VAR187(VAR57),
.VAR39(VAR186),
.VAR82(VAR98));
VAR22 #(.VAR120(VAR149)) VAR5 (
.clk(clk),
.rst(rst),
.VAR187(VAR57),
.VAR39(VAR15[VAR149-1:0]),
.VAR82(VAR185));
VAR22 #(.VAR120(3)) VAR17 (
.clk(clk),
.rst(rst),
.VAR187(VAR57),
.VAR39({VAR127 , VAR196 , VAR52}),
.VAR82({VAR100, VAR95, VAR116}));
generate
case(VAR25)
8:begin
assign VAR192 = 5'd1;
end
default:begin
assign VAR192 = 6'd1;
end
endcase
endgenerate
generate
case(VAR25)
8:begin
assign VAR182 =3'd0;
assign VAR193 = 8'd1;
end
default:begin
assign VAR182 =5'd0;
assign VAR193 = 11'd1;
end
endcase
endgenerate
assign VAR79 = (VAR131) ? VAR192 : VAR143;
assign VAR33 = (VAR140) ? VAR79 : VAR185;
assign VAR16 = (VAR140)&(~VAR131);
assign VAR139 = (VAR140)&(VAR131);
VAR53 #(.VAR120(VAR155)) VAR147 (
.VAR174(VAR140 ),
.VAR197 ({1'b1,VAR98,2'b00}),
.VAR135 (VAR103 ),
.VAR115 (VAR159 )
);
genvar VAR40;
VAR109 #(.VAR155(VAR155)) VAR142(
.VAR179 (VAR159),
.VAR113(VAR16),
.VAR172 (VAR129 [0][VAR155-1:0])
);
generate for (VAR40=0; VAR40 < 2; VAR40=VAR40+1) begin : VAR55
VAR41 #(.VAR155(VAR155), .VAR47(VAR40)) VAR41(
.VAR179 (VAR129[VAR40]),
.VAR113 (VAR33[VAR40]),
.VAR97(VAR139),
.VAR172 (VAR129[VAR40+1])
);
end
endgenerate
assign VAR7 = VAR129[2];
assign VAR129[3] = VAR71;
VAR22 #(.VAR120(VAR120-1)) VAR126 (
.clk(clk),
.rst(rst),
.VAR187(VAR180),
.VAR39(VAR45),
.VAR82(VAR158));
VAR22 #(.VAR120(VAR155)) VAR138 (
.clk(clk),
.rst(rst),
.VAR187((VAR180|VAR140)),
.VAR39(VAR7),
.VAR82(VAR71));
VAR22 #(.VAR120(VAR149)) VAR80 (
.clk(clk),
.rst(rst),
.VAR187(VAR180|VAR140),
.VAR39({VAR33}),
.VAR82({VAR93}));
VAR22 #(.VAR120(2)) VAR200 (
.clk(clk),
.rst(rst),
.VAR187(VAR180|VAR140),
.VAR39({VAR16,VAR139}),
.VAR82({VAR181, VAR183}));
VAR22 #(.VAR120(3)) VAR157 (
.clk(clk),
.rst(rst),
.VAR187(VAR180),
.VAR39({VAR100, VAR95, VAR116}),
.VAR82({VAR68, VAR161, VAR194}));
VAR22 #(.VAR120(VAR149+VAR25)) VAR144(
.clk(clk),
.rst(rst),
.VAR187(VAR140),
.VAR39({VAR143 , VAR153 }),
.VAR82({VAR110, VAR77})
);
VAR22 #(.VAR120(3)) VAR104 (
.clk(clk),
.rst(rst),
.VAR187(VAR140),
.VAR39({VAR131 , VAR28 , VAR125 }),
.VAR82({VAR91, VAR44, VAR10}));
generate for (VAR40=2; VAR40 < VAR149; VAR40=VAR40+1) begin : VAR60
VAR41 #(.VAR155(VAR155), .VAR47(VAR40)) VAR41(
.VAR179(VAR129[VAR40+1]),
.VAR113(VAR93[VAR40]),
.VAR97(VAR183),
.VAR172(VAR129[VAR40+2])
);
end
endgenerate
VAR109 #(.VAR155(VAR155)) VAR111(
.VAR179(VAR129[VAR149+1]),
.VAR113(VAR181),
.VAR172(VAR30)
);
assign VAR66 = {VAR182, VAR110};
assign VAR190 = (VAR91) ? VAR193 : VAR66;
always @* begin
if (VAR91) begin
VAR195 = VAR77 + VAR190;
end
else begin
VAR195 = VAR77 - VAR190;
end
end
VAR61 #(.VAR25(VAR25+1)) VAR199(
.VAR148(VAR195),
.VAR24 (VAR106),
.VAR168(VAR167));
VAR22 #(.VAR120(VAR120-1)) VAR102 (
.clk(clk),
.rst(rst),
.VAR187((VAR133&~VAR163)),
.VAR39(VAR158),
.VAR82(VAR50));
VAR22 #(.VAR120(VAR155)) VAR112 (
.clk(clk),
.rst(rst),
.VAR187(VAR133&~VAR163),
.VAR39(VAR30),
.VAR82(VAR54));
VAR22 #(.VAR120(3)) VAR107 (
.clk(clk),
.rst(rst),
.VAR187(VAR133&~VAR163),
.VAR39({VAR68,VAR161, VAR194}),
.VAR82({VAR59 , VAR132, VAR43 }));
assign VAR108 = {1'b1,VAR50[VAR101-1:0],2'b00};
assign VAR65 = VAR50[VAR120-2:VAR101];
always @* begin : VAR18
case (VAR132)
1'b0 : begin
{VAR178, VAR90} = VAR108 + VAR54;
end
1'b1 : begin
{VAR178, VAR90} = VAR108 - VAR54;
end
default: begin
{VAR178, VAR90} = VAR108 + VAR54;
end
endcase
end
assign VAR27 = VAR178&(~VAR132);
VAR22 #(.VAR120(VAR155)) VAR146 (
.clk(clk),
.rst(rst),
.VAR187(VAR56),
.VAR39(VAR90),
.VAR82(VAR103));
VAR22 #(.VAR120(VAR25)) VAR42 (
.clk(clk),
.rst(rst),
.VAR187(VAR56),
.VAR39(VAR65),
.VAR82(VAR153));
VAR22 #(.VAR120(3)) VAR14 (
.clk(clk),
.rst(rst),
.VAR187(VAR56),
.VAR39({VAR27, VAR59, VAR43}),
.VAR82({VAR131, VAR28, VAR125}));
assign VAR48 = ~VAR103;
generate
case (VAR155)
26:begin : VAR123
VAR173 VAR9(
.VAR188(VAR48),
.VAR46(VAR143)
);
end
55:begin : VAR191
VAR86 VAR92(
.VAR188(VAR48),
.VAR46(VAR143)
);
end
endcase
endgenerate
VAR134 #(.VAR120(VAR120),.VAR25(VAR25),.VAR101(VAR101)) VAR63 (
.VAR36 (VAR106 ),
.VAR166 (VAR167),
.VAR12 (VAR44),
.VAR85 (VAR195[VAR25-1:0]),
.VAR26 (VAR30[VAR155-2:2]),
.VAR64 (VAR89)
);
assign {VAR177,
VAR57,
VAR180,
VAR133,
VAR56,
VAR140,
VAR163} = VAR13;
assign VAR11 = VAR180;
VAR22 #(.VAR120(VAR120)) VAR87 (
.clk(clk),
.rst(rst),
.VAR187(VAR163),
.VAR39(VAR89),
.VAR82(VAR117)
);
VAR22 #(.VAR120(3)) VAR152 (
.clk(clk),
.rst(rst),
.VAR187(VAR163),
.VAR39({VAR106,VAR167, VAR10}),
.VAR82({VAR36 , VAR166 , VAR145 })
);
VAR22 #(.VAR120(1)) VAR136 (
.clk(clk),
.rst(rst),
.VAR187(1),
.VAR39(VAR163),
.VAR82(ready));
endmodule
|
gpl-3.0
|
peteg944/music-fpga
|
Microphone code (not used)/Microphone.v
| 2,865 |
module MODULE1(
output VAR20, output VAR19, output reg VAR30, input VAR9, input clk,
input rst,
input VAR24, output reg VAR16, output reg [9:0] VAR22
);
reg VAR1;
reg [9:0] VAR8;
reg VAR14, VAR29;
reg VAR2;
reg [7:0] VAR13, VAR6;
wire [7:0] VAR17;
wire VAR15;
VAR12 #(6) VAR4(clk, rst, VAR9, VAR19, VAR20, VAR14, VAR13, VAR17, , VAR15);
reg [3:0] state, VAR31; reg [3:0] VAR21, VAR23; localparam VAR28 = 4'd0,
VAR10 = 4'd1,
VAR7 = 4'd2,
VAR11 = 4'd3,
VAR5 = 4'd4,
VAR27 = 4'd5,
VAR18 = 4'd6,
VAR26 = 4'd7,
VAR3 = 4'd8,
VAR25 = 4'd9;
always @ (posedge clk) begin
if(rst) begin
VAR22 <= 10'b0;
VAR16 <= 1'b0;
VAR14 <= 1'b0;
VAR30 <= 1'b1;
VAR13 <= 8'b0;
state <= VAR7;
VAR21 <= VAR7;
end else begin
VAR22 <= VAR8;
VAR16 <= VAR1;
VAR14 <= VAR29;
VAR30 <= VAR2;
VAR13 <= VAR6;
state <= VAR31;
VAR21 <= VAR23;
end
end
always @ (*) begin
VAR8 = VAR22;
VAR1 = 1'b0;
VAR29 = 1'b0;
VAR2 = VAR30;
VAR6 = VAR13;
VAR31 = state;
VAR23 = VAR21;
case(state)
VAR7: begin
if(VAR24 == 1'b1) begin
VAR2 = 1'b0; VAR31 = VAR5;
end
end
VAR5: begin
VAR6 = 8'h01;
VAR31 = VAR28;
VAR23 = VAR27;
end
VAR27: begin
VAR6 = 8'h00; VAR31 = VAR28;
VAR23 = VAR18;
end
VAR18: begin
VAR8[9:8] = VAR17[1:0];
VAR31 = VAR26;
end
VAR26: begin
VAR6 = 8'h00; VAR31 = VAR28;
VAR23 = VAR3;
end
VAR3: begin
VAR8[7:0] = VAR17;
VAR31 = VAR7;
VAR1 = 1'b1;
VAR2 = 1'b1; end
VAR28: begin
VAR29 = 1'b1;
VAR31 = VAR10;
end
VAR10: begin
if(VAR15)
VAR31 = VAR21; end
endcase
end
endmodule
|
mit
|
fabianmcg/usbc_tcpc
|
src/tcpci.v
| 3,680 |
module MODULE1(output wire VAR6,
output wire VAR26,
output wire VAR29,
output wire VAR24,
output wire VAR36,
output wire VAR50,
output wire VAR52,
output wire VAR37,
output wire VAR22,
output wire VAR23,
output wire VAR40,
output wire VAR48,
output wire VAR21,
output wire [7:0] VAR10,
output wire [7:0] VAR44,
output wire [7:0] VAR47,
output wire [7:0] VAR4,
output wire [7:0] VAR15,
output wire [7:0] VAR32,
input wire VAR41,
input wire VAR28,
input wire VAR9,
input wire VAR41,
input wire VAR38,
input wire VAR2,
input wire VAR49,
input wire VAR39,
input wire VAR5,
input wire VAR54,
input wire VAR46,
input wire [7:0] VAR25,
input wire [7:0] VAR1,
input wire VAR45,
input wire reset,
input wire clk);
localparam VAR19 = 8'h10;
localparam VAR42 = 1'h1;
reg VAR56, VAR35, VAR34;
wire [7:0] VAR43, VAR33, VAR14,VAR3, VAR30, VAR53, VAR27;
reg [7:0] VAR16, VAR7, VAR12;
wire VAR31,VAR57;
wire VAR51,VAR11;
assign VAR34=0;
assign VAR12=8'h00;
VAR17 VAR55(VAR15, VAR32, VAR14, VAR3, VAR30, VAR53, VAR27, VAR1, VAR19, VAR12, VAR25, VAR16, VAR7, VAR45, VAR42, VAR34, reset, clk);
VAR13 VAR8( VAR51, VAR31, VAR40, VAR48, VAR21, VAR10, VAR44, VAR47, VAR4, VAR52, VAR37, VAR22, VAR23, VAR3 [2:0], VAR38, VAR2, VAR49, VAR39, VAR5, VAR54, VAR46, VAR30, VAR53, VAR27, clk, reset);
VAR18 VAR20(VAR6, VAR26, VAR29, VAR24, VAR36, VAR50, VAR57, VAR11, VAR3[2:0], VAR41, VAR28, VAR9, VAR41, reset, clk);
always @(VAR31,VAR57, VAR51, VAR11)
begin
VAR16={VAR32[7:7],VAR57+VAR31,VAR32[5:5],VAR11
+VAR51,VAR32[3:0]};
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a211oi/sky130_fd_sc_hd__a211oi_1.v
| 2,361 |
module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR11 ,
VAR7 ,
VAR8,
VAR10,
VAR2 ,
VAR6
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR11 ;
input VAR7 ;
input VAR8;
input VAR10;
input VAR2 ;
input VAR6 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR4 ,
VAR1,
VAR3,
VAR11,
VAR7
);
output VAR4 ;
input VAR1;
input VAR3;
input VAR11;
input VAR7;
supply1 VAR8;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR6 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_decerr_slave.v
| 9,276 |
module MODULE1 #
(
parameter integer VAR21 = 1,
parameter integer VAR9 = 32,
parameter integer VAR44 = 1,
parameter integer VAR30 = 1,
parameter integer VAR41 = 0,
parameter integer VAR37 = 2'b11
)
(
input wire VAR7,
input wire VAR47,
input wire [(VAR21-1):0] VAR36,
input wire VAR33,
output wire VAR15,
input wire VAR34,
input wire VAR3,
output wire VAR31,
output wire [(VAR21-1):0] VAR40,
output wire [1:0] VAR38,
output wire [VAR44-1:0] VAR46,
output wire VAR51,
input wire VAR50,
input wire [(VAR21-1):0] VAR10,
input wire [7:0] VAR42,
input wire VAR17,
output wire VAR25,
output wire [(VAR21-1):0] VAR8,
output wire [(VAR9-1):0] VAR20,
output wire [1:0] VAR32,
output wire [VAR30-1:0] VAR48,
output wire VAR49,
output wire VAR22,
input wire VAR11
);
reg VAR1;
reg VAR2;
reg VAR14;
reg VAR27;
reg VAR26;
localparam VAR29 = 2'b00;
localparam VAR12 = 2'b01;
localparam VAR18 = 2'b10;
localparam VAR4 = 1'b0;
localparam VAR24 = 1'b1;
localparam integer VAR39 = 0;
localparam integer VAR5 = 1;
localparam integer VAR19 = 2;
assign VAR38 = VAR37;
assign VAR32 = VAR37;
assign VAR20 = {VAR9{1'b0}};
assign VAR46 = {VAR44{1'b0}};
assign VAR48 = {VAR30{1'b0}};
assign VAR15 = VAR1;
assign VAR31 = VAR2;
assign VAR51 = VAR14;
assign VAR25 = VAR27;
assign VAR22 = VAR26;
generate
if (VAR41 == VAR19) begin : VAR45
assign VAR49 = 1'b1;
assign VAR40 = 0;
assign VAR8 = 0;
always @(posedge VAR7) begin
if (VAR47) begin
VAR1 <= 1'b0;
VAR2 <= 1'b0;
VAR14 <= 1'b0;
end else begin
if (VAR14) begin
if (VAR50) begin
VAR14 <= 1'b0;
end
end else if (VAR33 & VAR3) begin
if (VAR1) begin
VAR1 <= 1'b0;
VAR2 <= 1'b0;
VAR14 <= 1'b1;
end else begin
VAR1 <= 1'b1;
VAR2 <= 1'b1;
end
end
end
end
always @(posedge VAR7) begin
if (VAR47) begin
VAR27 <= 1'b0;
VAR26 <= 1'b0;
end else begin
if (VAR26) begin
if (VAR11) begin
VAR26 <= 1'b0;
end
end else if (VAR17 & VAR27) begin
VAR27 <= 1'b0;
VAR26 <= 1'b1;
end else begin
VAR27 <= 1'b1;
end
end
end
end else begin : VAR6
reg VAR23;
reg [(VAR21-1):0] VAR13;
reg [(VAR21-1):0] VAR28;
reg [7:0] VAR35;
reg [1:0] VAR43;
reg [0:0] VAR16;
assign VAR49 = VAR23;
assign VAR40 = VAR13;
assign VAR8 = VAR28;
always @(posedge VAR7) begin
if (VAR47) begin
VAR43 <= VAR29;
VAR1 <= 1'b0;
VAR2 <= 1'b0;
VAR14 <= 1'b0;
VAR13 <= 0;
end else begin
case (VAR43)
VAR29:
begin
if (VAR33 & VAR1) begin
VAR1 <= 1'b0;
VAR13 <= VAR36;
VAR2 <= 1'b1;
VAR43 <= VAR12;
end else begin
VAR1 <= 1'b1;
end
end
VAR12:
begin
if (VAR3 & VAR34) begin
VAR2 <= 1'b0;
VAR14 <= 1'b1;
VAR43 <= VAR18;
end
end
VAR18:
begin
if (VAR50) begin
VAR14 <= 1'b0;
VAR1 <= 1'b1;
VAR43 <= VAR29;
end
end
endcase
end
end
always @(posedge VAR7) begin
if (VAR47) begin
VAR16 <= VAR4;
VAR27 <= 1'b0;
VAR26 <= 1'b0;
VAR23 <= 1'b0;
VAR28 <= 0;
VAR35 <= 0;
end else begin
case (VAR16)
VAR4:
begin
if (VAR17 & VAR27) begin
VAR27 <= 1'b0;
VAR28 <= VAR10;
VAR35 <= VAR42;
VAR26 <= 1'b1;
if (VAR42 == 0) begin
VAR23 <= 1'b1;
end else begin
VAR23 <= 1'b0;
end
VAR16 <= VAR24;
end else begin
VAR27 <= 1'b1;
end
end
VAR24:
begin
if (VAR11) begin
if (VAR35 == 0) begin
VAR26 <= 1'b0;
VAR23 <= 1'b0;
VAR27 <= 1'b1;
VAR16 <= VAR4;
end else begin
if (VAR35 == 1) begin
VAR23 <= 1'b1;
end
VAR35 <= VAR35 - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
|
gpl-3.0
|
CospanDesign/python
|
game/panda/panda_path/example_project/rtl/dependencies/uart_fifo.v
| 4,519 |
module MODULE1 (
clk,
rst,
VAR9,
VAR29,
VAR31,
VAR15,
VAR6,
VAR26,
VAR14,
VAR27,
VAR22,
VAR32,
VAR28
);
parameter VAR20 = 10;
input clk;
input rst;
output wire [31:0] VAR9;
input VAR29;
output wire [31:0] VAR31;
input [7:0] VAR15;
input VAR6;
output reg [31:0] VAR26;
output wire [7:0] VAR14;
output reg VAR27;
output reg VAR22;
output VAR32;
output VAR28;
reg [VAR20 - 1: 0] VAR16;
reg [VAR20 - 1: 0] VAR30;
VAR23 #(
.VAR2(8),
.VAR24(VAR20),
.VAR19("VAR1"),
.VAR11(0)
) VAR25 (
.VAR17(clk),
.VAR3(VAR29),
.VAR12(VAR16),
.VAR7(VAR15),
.VAR21(clk),
.VAR8(0),
.VAR18(VAR30),
.VAR10(0),
.VAR5(VAR14)
);
wire [VAR20 - 1: 0] VAR13;
assign VAR9 = 1 << VAR20;
assign VAR13 = (VAR30 - 1);
assign VAR32 = (VAR16 == VAR13);
assign VAR28 = (VAR26 == 0);
assign VAR31 = VAR9 - VAR26;
integer VAR4;
always @ (posedge clk) begin
if (rst) begin
VAR26 <= 0;
VAR16 <= 0;
VAR30 <= 0;
VAR27 <= 0;
VAR22 <= 0;
end
else begin
VAR27 <= 0;
VAR22 <= 0;
if (VAR29) begin
if (VAR32 && !VAR6) begin
VAR30 <= VAR30 + 1;
VAR27 <= 1;
end
else begin
if (!VAR6) begin
VAR26 <= VAR26 + 1;
end
end
VAR16 <= VAR16 + 1;
end
if (VAR6) begin
if (VAR28) begin
VAR22 <= 1;
end
else begin
if (VAR32 && VAR29) begin
VAR27 <= 0;
end
else begin
if (!VAR29) begin
VAR26 <= VAR26 - 1;
end
VAR30 <= VAR30 + 1;
end
end
end
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/and4b/sky130_fd_sc_lp__and4b_1.v
| 2,300 |
module MODULE1 (
VAR3 ,
VAR11 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR2,
VAR10,
VAR4 ,
VAR6
);
output VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR10;
input VAR4 ;
input VAR6 ;
VAR7 VAR9 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3 ,
VAR11,
VAR1 ,
VAR8 ,
VAR5
);
output VAR3 ;
input VAR11;
input VAR1 ;
input VAR8 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR10;
supply1 VAR4 ;
supply0 VAR6 ;
VAR7 VAR9 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.behavioral.v
| 1,262 |
module MODULE1( VAR4, VAR3, VAR2, VAR7 );
input VAR7, VAR2, VAR3;
output VAR4;
VAR5 VAR1(.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7));
VAR5 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7));
|
apache-2.0
|
skarpenko/ultiparc
|
rtl/src/cpu/uparc_ifu.v
| 3,426 |
module MODULE1(
clk,
VAR5,
addr,
VAR7,
VAR1,
VAR2,
VAR4,
VAR8,
VAR16,
VAR14,
VAR3,
VAR17,
VAR12
);
localparam VAR6 = 1'b0;
localparam VAR11 = 1'b1;
input wire clk;
input wire VAR5;
input wire [VAR15-1:0] addr;
output wire [VAR10-1:0] VAR7;
input wire VAR1;
output wire VAR2;
output wire VAR4;
output wire VAR8;
output reg [VAR15-1:0] VAR16;
output reg VAR14;
input wire [VAR10-1:0] VAR3;
input wire VAR17;
input wire VAR12;
assign VAR4 = (VAR1 == 1'b1 && addr[1:0] != 2'b0);
wire VAR9 = (!VAR4 && !VAR12 && VAR1 == 1'b1);
assign VAR2 = ((VAR9 || (state == VAR11)) && !VAR17);
assign VAR8 = VAR12;
always @(*)
begin
VAR16 = 32'b0;
VAR14 = 1'b0;
if(VAR9)
begin
VAR16 = addr;
VAR14 = 1'b1;
end
end
reg [VAR10-1:0] VAR13;
reg state;
always @(posedge clk or negedge VAR5)
begin
if(!VAR5)
begin
state <= VAR6;
VAR13 <= {(VAR10){1'b0}};
end
else
begin
if(state == VAR6 && (VAR9 && VAR17))
begin
VAR13 <= VAR3;
end
else if(state == VAR6 && (VAR9 && !VAR17))
begin
state <= !VAR12 ? VAR11 : VAR6;
end
else if(state == VAR11 && VAR17)
begin
state <= VAR6;
VAR13 <= VAR3;
end
end
end
assign VAR7 = (VAR9 || state == VAR11) ? VAR3 : VAR13;
endmodule
|
bsd-2-clause
|
BilkentCompGen/GateKeeper
|
FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_data_shift.v
| 13,735 |
module MODULE1
parameter VAR1 = 1,
parameter VAR19 = 1,
parameter VAR71 = 128,
parameter VAR17 = "VAR77"
)
(
input VAR47,
input VAR70,
input VAR75,
input [VAR71-1:0] VAR80,
input VAR37,
input [VAR61(VAR71/32)-1:0] VAR26,
input VAR60,
input [VAR61(VAR71/32)-1:0] VAR35,
output VAR69,
input VAR39,
output [VAR71-1:0] VAR28,
output VAR65,
output [(VAR71/32)-1:0] VAR27,
output [(VAR71/32)-1:0] VAR43,
output VAR23
);
localparam VAR14 = VAR61(VAR71/32);
localparam VAR66 = (VAR71/32);
localparam VAR81 = VAR71/32;
localparam VAR3 = VAR71/32;
localparam VAR53 = VAR71;
genvar VAR40;
wire VAR76;
wire [VAR71-1:0] VAR44;
wire VAR49;
wire [VAR61(VAR71/32)-1:0] VAR86;
wire VAR2;
wire [VAR61(VAR71/32)-1:0] VAR25;
wire [(VAR71/32)-1:0] VAR16;
wire [(VAR71/32)-1:0] VAR45;
wire VAR32;
wire VAR12;
wire [VAR71-1:0] VAR21;
wire VAR72;
wire [(VAR71/32)-1:0] VAR57;
wire [(VAR71/32)-1:0] VAR85;
wire [(VAR71/32)-1:0] VAR11;
wire [(VAR71/32)-1:0] VAR8;
wire VAR79;
wire [VAR81-1:0] VAR7[VAR66-1:0];
wire [VAR81-1:0] VAR33[VAR66-1:0];
reg [VAR81-1:0] VAR10[VAR66-1:0],VAR10[VAR66-1:0];
reg [VAR61(VAR71/32)-1:0] VAR67,VAR67;
assign VAR32 = VAR12;
assign VAR11 = VAR49 ?
{(VAR71/32){1'b1}} >> VAR86:
{(VAR71/32){1'b1}};
assign VAR85 = VAR8 & VAR11;
assign VAR72 = VAR49;
assign VAR79 = VAR76;
generate
for (VAR40 = 0; VAR40 < VAR66; VAR40 = VAR40 + 1) begin : VAR51
assign VAR7[VAR40] = (1 << VAR40);
end
endgenerate
always @ begin
VAR10[VAR40] = VAR33[VAR40];
end
always @(posedge VAR47) begin
if(VAR69 & VAR37) begin
VAR10[VAR40] <= VAR10[VAR40];
end
end
end
endgenerate
VAR42
.VAR62 (0),
.VAR5 (VAR19?1:0)
)
VAR50
(
.VAR38 (VAR69),
.VAR58 ({VAR44,VAR49,VAR86,VAR2,VAR25}),
.VAR84 (VAR76),
.VAR55 ({VAR80,VAR37,VAR26,
VAR60,VAR35}),
.VAR52 (VAR75),
.VAR41 (VAR32),
.VAR47 (VAR47),
.VAR70 (VAR70));
VAR42
.VAR62 (0),
.VAR5 ((VAR1 > 1) ? 1 : 0)
)
VAR34
(
.VAR38 (VAR12),
.VAR58 ({VAR28,VAR65,
VAR43,VAR27}),
.VAR84 (VAR23),
.VAR55 ({VAR21,VAR72,
VAR57,VAR85}),
.VAR52 (VAR79),
.VAR41 (VAR39),
.VAR47 (VAR47),
.VAR70 (VAR70));
VAR22
.VAR36 (0),
.VAR3 (VAR3))
VAR63
(
.VAR83 (VAR16),
.VAR30 (VAR2),
.VAR6 (VAR25)
);
VAR48
.VAR20 ("VAR31"),
.VAR29 (VAR71/32)
)
VAR73
(
.VAR58 (VAR8),
.VAR55 (VAR16),
.VAR64 (VAR67[VAR61(VAR71/32)-1:0])
);
VAR54
.VAR29 (VAR71/32)
)
VAR15
(
.VAR24 (VAR45),
.VAR82 (VAR25[VAR61(VAR71/32)-1:0]),
.VAR68 (VAR2)
);
VAR48
.VAR20 ("VAR31"),
.VAR29 (VAR71/32)
)
VAR18
(
.VAR58 (VAR57),
.VAR55 (VAR45),
.VAR64 (VAR67[VAR61(VAR71/32)-1:0])
);
generate
for (VAR40 = 0; VAR40 < VAR66; VAR40 = VAR40 + 1) begin : VAR4
VAR48
.VAR20 ("VAR87"),
.VAR29 ((VAR71/32))
)
VAR74
(
.VAR58 (VAR33[VAR40]),
.VAR55 (VAR7[VAR40]),
.VAR64 (VAR26[VAR14-1:0])
);
end
endgenerate
generate
for (VAR40 = 0; VAR40 < VAR71/32; VAR40 = VAR40 + 1) begin : VAR56
VAR59
.VAR71 (32),
.VAR81 (VAR81),
.VAR53 (VAR53))
VAR13
(
.VAR46 (VAR10[VAR40]),
.VAR78 (VAR21[32*VAR40 +: 32]),
.VAR9 (VAR44)
);
end
endgenerate
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o221ai/sky130_fd_sc_hdll__o221ai.functional.v
| 1,600 |
module MODULE1 (
VAR10 ,
VAR6,
VAR9,
VAR1,
VAR11,
VAR12
);
output VAR10 ;
input VAR6;
input VAR9;
input VAR1;
input VAR11;
input VAR12;
wire VAR3 ;
wire VAR7 ;
wire VAR13;
or VAR5 (VAR3 , VAR11, VAR1 );
or VAR8 (VAR7 , VAR9, VAR6 );
nand VAR4 (VAR13, VAR7, VAR3, VAR12);
buf VAR2 (VAR10 , VAR13 );
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/altera_ddr3_128/ddr3_int_bb.v
| 3,233 |
module MODULE1 (
VAR19,
VAR8,
VAR36,
VAR14,
VAR13,
VAR5,
VAR18,
VAR37,
VAR2,
VAR33,
VAR21,
VAR17,
VAR16,
VAR31,
VAR1,
VAR34,
VAR20,
VAR26,
VAR23,
VAR25,
VAR10,
VAR28,
VAR6,
VAR32,
VAR35,
VAR27,
VAR22,
VAR11,
VAR7,
VAR4,
VAR9,
VAR30,
VAR3,
VAR29,
VAR12,
VAR24,
VAR15);
input [23:0] VAR19;
input VAR8;
input VAR36;
input VAR14;
input [255:0] VAR13;
input [31:0] VAR5;
input [4:0] VAR18;
input VAR37;
input VAR2;
input VAR33;
output VAR21;
output [255:0] VAR17;
output VAR16;
output VAR31;
output VAR1;
output VAR34;
output VAR20;
output [5:0] VAR26;
output [0:0] VAR23;
output [0:0] VAR25;
output [0:0] VAR10;
output [12:0] VAR28;
output [2:0] VAR6;
output VAR32;
output VAR35;
output VAR27;
output [7:0] VAR22;
output VAR11;
output VAR7;
output VAR4;
output VAR9;
output VAR30;
inout [0:0] VAR3;
inout [0:0] VAR29;
inout [63:0] VAR12;
inout [7:0] VAR24;
inout [7:0] VAR15;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.functional.pp.v
| 1,899 |
module MODULE1 (
VAR7 ,
VAR10 ,
VAR13,
VAR12 ,
VAR1 ,
VAR2 ,
VAR8
);
output VAR7 ;
input VAR10 ;
input VAR13;
input VAR12 ;
input VAR1 ;
input VAR2 ;
input VAR8 ;
wire VAR3 ;
wire VAR11;
not VAR4 (VAR3 , VAR13 );
or VAR5 (VAR11, VAR10, VAR3 );
VAR9 VAR6 (VAR7 , VAR11, VAR12, VAR1);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.pp.symbol.v
| 1,474 |
module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR5,
input VAR8 ,
input VAR1 ,
input VAR2 ,
input VAR7 ,
input VAR3
);
endmodule
|
apache-2.0
|
tmolteno/TART
|
hardware/FPGA/ddrmem/ddr_dq_iobs.v
| 3,770 |
module MODULE1 (
VAR5,
VAR13,
VAR18,
VAR3,
VAR8,
VAR16,
VAR17,
VAR1
);
input VAR5;
input VAR13;
input VAR18;
input VAR3;
input VAR8;
inout [7:0] VAR16;
input [15:0] VAR17;
output [15:0] VAR1;
VAR15 VAR20 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [8], VAR17 [0]}),
.VAR1 ({VAR1 [8], VAR1 [0]}),
.VAR15 (VAR16 [0])
);
VAR15 VAR12 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [9], VAR17 [1]}),
.VAR1 ({VAR1 [9], VAR1 [1]}),
.VAR15 (VAR16 [1])
);
VAR15 VAR7 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [10], VAR17 [2]}),
.VAR1 ({VAR1 [10], VAR1 [2]}),
.VAR15 (VAR16 [2])
);
VAR15 VAR21 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [11], VAR17 [3]}),
.VAR1 ({VAR1 [11], VAR1 [3]}),
.VAR15 (VAR16 [3])
);
VAR15 VAR2 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [12], VAR17 [4]}),
.VAR1 ({VAR1 [12], VAR1 [4]}),
.VAR15 (VAR16 [4])
);
VAR15 VAR14 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [13], VAR17 [5]}),
.VAR1 ({VAR1 [13], VAR1 [5]}),
.VAR15 (VAR16 [5])
);
VAR15 VAR11 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [14], VAR17 [6]}),
.VAR1 ({VAR1 [14], VAR1 [6]}),
.VAR15 (VAR16 [6])
);
VAR15 VAR19 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [15], VAR17 [7]}),
.VAR1 ({VAR1 [15], VAR1 [7]}),
.VAR15 (VAR16 [7])
);
endmodule
|
lgpl-3.0
|
jhennessy/parallella-hw-old
|
fpga/hdl/parallella-I/parallella_z7_top.v
| 36,165 |
module MODULE1 (
VAR261,
VAR133, VAR56, VAR12,
VAR148, VAR157, VAR32, VAR14, VAR237,
VAR114, VAR62, VAR41, VAR205, VAR242,
VAR91, VAR238,
VAR274, VAR81,
VAR96, VAR140,
VAR146, VAR250,
VAR116, VAR110,
VAR124, VAR135,
VAR94, VAR172,
VAR117, VAR121,
VAR248, VAR226, VAR76,
VAR90, VAR147,
VAR190,
VAR34, VAR270, VAR150, VAR258, VAR78,
VAR53, VAR4, VAR266, VAR204,
VAR29,VAR278, VAR136,
VAR85, VAR83, VAR38, VAR217, VAR23, VAR1,
VAR277,VAR84,VAR138
);
parameter VAR39 = 12; parameter VAR123 = 32; parameter VAR106 = 32; parameter VAR276 = 6; parameter VAR72 = 32; parameter VAR13 = 64; parameter VAR198 = 8; parameter VAR154 = 20;
inout [53:0] VAR91;
input VAR90;
input VAR147;
input VAR190;
inout VAR238;
inout VAR274;
inout VAR81;
inout VAR96;
inout VAR140;
inout VAR146;
output VAR261;
inout [2:0] VAR250;
inout [14:0] VAR116;
inout VAR110;
inout VAR124;
inout [31:0] VAR135;
inout [3:0] VAR94;
inout [3:0] VAR172;
inout [3:0] VAR117;
inout VAR121;
inout VAR248;
output [23:8] VAR85;
output VAR83;
output VAR38;
output VAR217;
output VAR23;
output VAR1;
input VAR277;
input VAR278;
input VAR136;
inout VAR84;
inout VAR138;
inout [VAR156-1:0] VAR226;
inout [VAR156-1:0] VAR76;
input [7:0] VAR34;
input [7:0] VAR270;
input VAR150;
input VAR258;
input VAR78;
input VAR53;
input VAR4;
input VAR266;
input VAR204;
output [7:0] VAR133;
output [7:0] VAR56;
output VAR12;
output VAR148;
output VAR157;
output VAR32;
output VAR14;
output VAR237;
output VAR114;
output VAR62;
output VAR41;
output VAR205;
output VAR242;
input VAR29;
wire VAR80; wire VAR260; wire VAR269; wire VAR181; wire [31:0] VAR221; wire [1:0] VAR9; wire [3:0] VAR137; wire VAR24; wire [11:0] VAR139; wire [3:0] VAR3; wire [1:0] VAR143; wire [2:0] VAR280; wire [3:0] VAR108; wire VAR49; wire [2:0] VAR256; wire VAR99; wire [31:0] VAR176; wire [1:0] VAR275; wire [3:0] VAR215; wire [11:0] VAR252; wire [3:0] VAR209; wire [1:0] VAR236; wire [2:0] VAR36; wire [3:0] VAR50; wire VAR206; wire [2:0] VAR231; wire VAR166; wire [VAR39-1:0] VAR211; wire VAR220; wire [1:0] VAR232; wire VAR164; wire [VAR106-1:0] VAR93; wire [VAR39-1:0] VAR48; wire VAR30; wire VAR60; wire [1:0] VAR214; wire VAR239; wire [31:0] VAR82; wire [11:0] VAR173; wire VAR247; wire VAR70; wire [3:0] VAR55; wire VAR8; wire [VAR72-1:0] VAR46; wire [1:0] VAR73; wire [3:0] VAR151; wire VAR183; wire [VAR276-1:0] VAR71; wire [3:0] VAR45; wire [1:0] VAR125; wire [2:0] VAR16; wire [3:0] VAR222; wire VAR127; wire [2:0] VAR54; wire VAR169; wire [VAR72-1:0] VAR187; wire [1:0] VAR68; wire [3:0] VAR111; wire [VAR276-1:0] VAR246; wire [3:0] VAR101; wire [1:0] VAR28; wire [2:0] VAR51; wire [3:0] VAR165; wire VAR132; wire [2:0] VAR182; wire VAR11; wire [5:0] VAR5; wire VAR184; wire [1:0] VAR103; wire VAR31; wire [63:0] VAR141; wire [5:0] VAR63; wire VAR35; wire VAR66; wire [1:0] VAR19; wire VAR174; wire [VAR13-1:0] VAR208; wire [VAR276-1:0] VAR57; wire VAR98; wire VAR243; wire [VAR198-1:0] VAR109; wire VAR89; wire VAR224; wire VAR195;
wire [47:0] VAR119;
wire [47:0] VAR196;
wire [47:0] VAR158;
assign VAR158 = 47'hFFFFFFFFFFFF;
reg [19:0] VAR228;
reg VAR115;
wire VAR128;
wire VAR20;
wire VAR69;
wire [15:0] VAR233;
wire VAR207;
wire VAR259;
wire VAR163;
wire VAR199;
wire VAR92;
wire [7:0] VAR153;
wire [7:0] VAR282;
wire VAR202;
wire VAR126;
wire VAR95;
wire VAR104;
wire VAR257;
wire VAR225;
wire VAR192;
wire VAR197;
wire [7:0] VAR170;
wire [7:0] VAR161;
wire VAR44;
wire VAR193;
wire VAR279;
wire VAR179;
wire VAR230;
wire VAR97;
wire VAR245;
wire VAR267;
wire VAR10;
wire [1:0] VAR134;
VAR79 VAR79
(
.VAR119(VAR119),
.VAR226(VAR226),
.VAR76(VAR76),
.VAR196(VAR196),
.VAR158(VAR158)
);
assign VAR85 = VAR233;
assign VAR83 = VAR207;
assign VAR38 = VAR259;
assign VAR217 = VAR163;
assign VAR23 = VAR199;
assign VAR1 = VAR92;
assign VAR233 = 16'd0;
assign VAR207 = 1'b0;
assign VAR259 = 1'b0;
assign VAR163 = 1'b0;
assign VAR199 = 1'b0;
assign VAR92 = 1'b0;
assign VAR128 = VAR181;
assign VAR20 = ~VAR24;
assign VAR153 = VAR34;
assign VAR282 = VAR270;
assign VAR202 = VAR150;
assign VAR126 = VAR258;
assign VAR95 = VAR78;
assign VAR104 = VAR53;
assign VAR257 = VAR4;
assign VAR225 = VAR266;
assign VAR192 = VAR204; assign VAR197 = 1'b0;
assign VAR133 = VAR170;
assign VAR56 = VAR161;
assign VAR12 = VAR44;
assign VAR148 = VAR193;
assign VAR157 = VAR279;
assign VAR32 = VAR179;
assign VAR14 = VAR230;
assign VAR237 = VAR97;
assign VAR114 = VAR245;
assign VAR62 = VAR267;
assign VAR242 = VAR10;
always @ (posedge VAR128)
begin
if (VAR228[19:0] == 20'hff13f) begin
VAR115 <= 1'b0;
end
else begin
VAR115 <= 1'b1;
VAR228[19:0] <= VAR228[19:0] + 20'd1;
end
end
assign VAR69 = VAR115 | VAR20 | VAR195;
assign VAR10 = ~(VAR115 | VAR224);
VAR272 VAR272(
.VAR260 (VAR260),
.VAR80 (VAR80),
.VAR224 (VAR224),
.VAR195 (VAR195),
.VAR170 (VAR170[7:0]),
.VAR161 (VAR161[7:0]),
.VAR44 (VAR44),
.VAR193 (VAR193),
.VAR279 (VAR279),
.VAR179 (VAR179),
.VAR230 (VAR230),
.VAR97 (VAR97),
.VAR245 (VAR245),
.VAR267 (VAR267),
.VAR271 (VAR41), .VAR229 (VAR205), .VAR145 (VAR246[VAR276-1:0]), .VAR65 (VAR187[VAR72-1:0]), .VAR180 (VAR101[3:0]), .VAR253 (VAR182[2:0]), .VAR254 (VAR68[1:0]), .VAR213 (VAR28[1:0]), .VAR87 (VAR111[3:0]), .VAR18 (VAR51[2:0]), .VAR22 (VAR11), .VAR189 (VAR206), .VAR75 (VAR57[VAR276-1:0]), .VAR159 (VAR208[VAR13-1:0]), .VAR200 (VAR109[VAR198-1:0]), .VAR37 (VAR98), .VAR131 (VAR89), .VAR194 (VAR70), .VAR175 (VAR184), .VAR218 (VAR211[VAR39-1:0]), .VAR264 (VAR232[1:0]), .VAR120 (VAR164), .VAR47 (VAR71[VAR276-1:0]), .VAR33 (VAR46[VAR72-1:0]), .VAR144 (VAR45[3:0]), .VAR61 (VAR54[2:0]), .VAR212 (VAR73[1:0]), .VAR191 (VAR125[1:0]), .VAR255 (VAR151[3:0]), .VAR42 (VAR16[2:0]), .VAR88 (VAR169), .VAR171 (VAR49), .VAR21 (VAR66), .VAR25 (VAR48[VAR39-1:0]), .VAR74 (VAR93[VAR106-1:0]), .VAR185 (VAR214[1:0]), .VAR7 (VAR30), .VAR167 (VAR239), .VAR273 (VAR165[3:0]), .VAR149 (VAR222[3:0]), .VAR52 (VAR269), .VAR240 (VAR181), .VAR201 (VAR181), .reset (VAR69), .VAR241 (VAR24), .VAR112 (VAR183), .VAR113 (1'b0), .VAR153 (VAR153[7:0]),
.VAR282 (VAR282[7:0]),
.VAR202 (VAR202),
.VAR126 (VAR126),
.VAR95 (VAR95),
.VAR104 (VAR104),
.VAR257 (VAR257),
.VAR225 (VAR225),
.VAR192 (VAR192),
.VAR197 (VAR197),
.VAR152 (VAR132), .VAR27 (VAR252[VAR39-1:0]), .VAR235 (VAR176[VAR72-1:0]), .VAR177 (VAR209[3:0]), .VAR249 (VAR231[2:0]), .VAR210 (VAR275[1:0]), .VAR203 (VAR236[1:0]), .VAR67 (VAR215[3:0]), .VAR188 (VAR36[2:0]), .VAR142 (VAR166), .VAR155 (VAR243), .VAR122 (VAR173[VAR39-1:0]), .VAR130 (VAR82[VAR106-1:0]), .VAR40 (VAR55[3:0]), .VAR265 (VAR247), .VAR100 (VAR8), .VAR6 (VAR5[VAR276-1:0]), .VAR2 (VAR103[1:0]), .VAR17 (VAR31), .VAR223 (VAR220), .VAR268 (VAR127), .VAR77 (VAR139[VAR39-1:0]), .VAR26 (VAR221[VAR72-1:0]), .VAR58 (VAR3[3:0]), .VAR219 (VAR256[2:0]), .VAR262 (VAR9[1:0]), .VAR105 (VAR143[1:0]), .VAR64 (VAR137[3:0]), .VAR59 (VAR280[2:0]), .VAR162 (VAR99), .VAR43 (VAR63[VAR276-1:0]), .VAR86 (VAR141[VAR13-1:0]), .VAR244 (VAR19[1:0]), .VAR160 (VAR35), .VAR281 (VAR174), .VAR251 (VAR60), .VAR107 (VAR50[3:0]), .VAR178 (VAR108[3:0]));
VAR118 VAR118(
.VAR227(VAR181),
.VAR263(VAR181),
.VAR186(VAR84),
.VAR168(),
.VAR234(),
.VAR216(VAR138),
.VAR102(),
.VAR129(),
.VAR207(VAR207),
.VAR233(VAR233),
.VAR259(VAR259),
.VAR163(VAR163),
.VAR199(VAR199),
.VAR15(VAR92),
.VAR119(VAR119),
.VAR196(VAR196),
.VAR158(VAR158),
.VAR261(VAR261),
.VAR24(VAR24),
.VAR183(VAR183),
.VAR181(VAR181),
.VAR269(VAR269),
.VAR99(VAR99),
.VAR166(VAR166),
.VAR220(VAR220),
.VAR60(VAR60),
.VAR247(VAR247),
.VAR8(VAR8),
.VAR139(VAR139[11:0]),
.VAR252(VAR252[11:0]),
.VAR173(VAR173[11:0]),
.VAR9(VAR9[1:0]),
.VAR143(VAR143[1:0]),
.VAR256(VAR256[2:0]),
.VAR275(VAR275[1:0]),
.VAR236(VAR236[1:0]),
.VAR231(VAR231[2:0]),
.VAR280(VAR280[2:0]),
.VAR36(VAR36[2:0]),
.VAR221(VAR221[31:0]),
.VAR176(VAR176[31:0]),
.VAR82(VAR82[31:0]),
.VAR137(VAR137[3:0]),
.VAR3(VAR3[3:0]),
.VAR108(VAR108[3:0]),
.VAR215(VAR215[3:0]),
.VAR209(VAR209[3:0]),
.VAR50(VAR50[3:0]),
.VAR55(VAR55[3:0]),
.VAR127(VAR127),
.VAR132(VAR132),
.VAR31(VAR31),
.VAR35(VAR35),
.VAR174(VAR174),
.VAR243(VAR243),
.VAR103(VAR103[1:0]),
.VAR19(VAR19[1:0]),
.VAR5(VAR5[5:0]),
.VAR63(VAR63[5:0]),
.VAR141(VAR141[63:0]),
.VAR91(VAR91[53:0]),
.VAR238(VAR238),
.VAR274(VAR274),
.VAR81(VAR81),
.VAR96(VAR96),
.VAR140(VAR140),
.VAR146(VAR146),
.VAR250(VAR250[2:0]),
.VAR116(VAR116[14:0]),
.VAR110(VAR110),
.VAR124(VAR124),
.VAR135(VAR135[31:0]),
.VAR94(VAR94[3:0]),
.VAR172(VAR172[3:0]),
.VAR117(VAR117[3:0]),
.VAR121(VAR121),
.VAR248(VAR248),
.VAR90(VAR90),
.VAR147(VAR147),
.VAR190(VAR190),
.VAR49(VAR49),
.VAR206(VAR206),
.VAR164(VAR164),
.VAR30(VAR30),
.VAR239(VAR239),
.VAR70(VAR70),
.VAR211(VAR211[11:0]),
.VAR48(VAR48[11:0]),
.VAR232(VAR232[1:0]),
.VAR214(VAR214[1:0]),
.VAR93(VAR93[31:0]),
.VAR169(VAR169),
.VAR11(VAR11),
.VAR184(VAR184),
.VAR66(VAR66),
.VAR98(VAR98),
.VAR89(VAR89),
.VAR73(VAR73[1:0]),
.VAR125(VAR125[1:0]),
.VAR54(VAR54[2:0]),
.VAR68(VAR68[1:0]),
.VAR28(VAR28[1:0]),
.VAR182(VAR182[2:0]),
.VAR16(VAR16[2:0]),
.VAR51(VAR51[2:0]),
.VAR46(VAR46[31:0]),
.VAR187(VAR187[31:0]),
.VAR151(VAR151[3:0]),
.VAR45(VAR45[3:0]),
.VAR222(VAR222[3:0]),
.VAR111(VAR111[3:0]),
.VAR101(VAR101[3:0]),
.VAR165(VAR165[3:0]),
.VAR71(VAR71[5:0]),
.VAR246(VAR246[5:0]),
.VAR57(VAR57[5:0]),
.VAR208(VAR208[63:0]),
.VAR109(VAR109[7:0]));
endmodule
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gpl-3.0
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