repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
SymbiFlow/yosys
|
techlibs/ecp5/dsp_map.v
| 1,436 |
module \VAR24 (input [17:0] VAR80, input [17:0] VAR53, output [35:0] VAR98);
parameter VAR66 = 18;
parameter VAR14 = 18;
parameter VAR71 = 36;
parameter VAR12 = 0;
parameter VAR3 = 0;
VAR69 VAR56 (
.VAR75(VAR80[0]), .VAR23(VAR80[1]), .VAR91(VAR80[2]), .VAR103(VAR80[3]), .VAR48(VAR80[4]), .VAR83(VAR80[5]), .VAR76(VAR80[6]), .VAR28(VAR80[7]), .VAR77(VAR80[8]), .VAR90(VAR80[9]), .VAR4(VAR80[10]), .VAR35(VAR80[11]), .VAR54(VAR80[12]), .VAR45(VAR80[13]), .VAR2(VAR80[14]), .VAR34(VAR80[15]), .VAR104(VAR80[16]), .VAR82(VAR80[17]),
.VAR37(VAR53[0]), .VAR19(VAR53[1]), .VAR18(VAR53[2]), .VAR62(VAR53[3]), .VAR47(VAR53[4]), .VAR11(VAR53[5]), .VAR52(VAR53[6]), .VAR95(VAR53[7]), .VAR99(VAR53[8]), .VAR59(VAR53[9]), .VAR43(VAR53[10]), .VAR6(VAR53[11]), .VAR88(VAR53[12]), .VAR44(VAR53[13]), .VAR39(VAR53[14]), .VAR40(VAR53[15]), .VAR36(VAR53[16]), .VAR25(VAR53[17]),
.VAR63(1'b0), .VAR32(1'b0), .VAR85(1'b0), .VAR87(1'b0), .VAR22(1'b0), .VAR96(1'b0), .VAR105(1'b0), .VAR93(1'b0), .VAR27(1'b0), .VAR13(1'b0), .VAR79(1'b0), .VAR70(1'b0), .VAR86(1'b0), .VAR8(1'b0), .VAR26(1'b0), .VAR92(1'b0), .VAR60(1'b0), .VAR55(1'b0),
.VAR1(VAR12 ? 1'b1 : 1'b0), .VAR74(VAR3 ? 1'b1 : 1'b0), .VAR5(1'b0), .VAR68(1'b0),
.VAR15(VAR98[0]), .VAR51(VAR98[1]), .VAR46(VAR98[2]), .VAR9(VAR98[3]), .VAR78(VAR98[4]), .VAR38(VAR98[5]), .VAR84(VAR98[6]), .VAR10(VAR98[7]), .VAR21(VAR98[8]), .VAR49(VAR98[9]), .VAR102(VAR98[10]), .VAR65(VAR98[11]), .VAR61(VAR98[12]), .VAR42(VAR98[13]), .VAR29(VAR98[14]), .VAR30(VAR98[15]), .VAR100(VAR98[16]), .VAR94(VAR98[17]), .VAR58(VAR98[18]), .VAR73(VAR98[19]), .VAR67(VAR98[20]), .VAR33(VAR98[21]), .VAR17(VAR98[22]), .VAR97(VAR98[23]), .VAR7(VAR98[24]), .VAR72(VAR98[25]), .VAR16(VAR98[26]), .VAR101(VAR98[27]), .VAR41(VAR98[28]), .VAR20(VAR98[29]), .VAR31(VAR98[30]), .VAR81(VAR98[31]), .VAR50(VAR98[32]), .VAR89(VAR98[33]), .VAR57(VAR98[34]), .VAR64(VAR98[35])
);
endmodule
|
isc
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/mux2/sky130_fd_sc_hdll__mux2_8.v
| 2,203 |
module MODULE1 (
VAR5 ,
VAR10 ,
VAR9 ,
VAR8 ,
VAR3,
VAR4,
VAR1 ,
VAR6
);
output VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR8 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR6 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR5 ,
VAR10,
VAR9,
VAR8
);
output VAR5 ;
input VAR10;
input VAR9;
input VAR8 ;
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/SCFIFO_40x64_withCount.v
| 2,693 |
module MODULE1
(
input VAR9 ,
input VAR12 ,
input [39:0] VAR1 ,
input VAR16 ,
output VAR11 ,
output [39:0] VAR14 ,
input VAR13 ,
output VAR3 ,
output [5:0] VAR7
);
VAR2
VAR4
(
.clk (VAR9 ),
.VAR15 (VAR12 ),
.din (VAR1 ),
.VAR5 (VAR16 ),
.VAR17 (VAR11 ),
.dout (VAR14 ),
.VAR10 (VAR13 ),
.VAR8 (VAR3 ),
.VAR6 (VAR7 )
);
endmodule
|
gpl-3.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S4_2_altera_bb.v
| 7,842 |
module MODULE1 (
VAR4,
VAR5,
VAR6,
VAR2,
VAR1,
VAR3);
input VAR4;
input [3:0] VAR5;
input [11:0] VAR6;
input [11:0] VAR2;
input VAR1;
output [3:0] VAR3;
tri1 VAR4;
tri0 VAR1;
endmodule
|
mit
|
cliffordwolf/yosys
|
techlibs/nexus/arith_map.v
| 2,804 |
module MODULE1(
module 80nexusalu (VAR6, VAR42, VAR40, VAR34, VAR21, VAR5, VAR16);
parameter VAR4 = 0;
parameter VAR41 = 0;
parameter VAR13 = 1;
parameter VAR37 = 1;
parameter VAR15 = 1;
input [VAR13-1:0] VAR6;
input [VAR37-1:0] VAR42;
output [VAR15-1:0] VAR21, VAR5;
input VAR40, VAR34;
output [VAR15-1:0] VAR16;
wire VAR35 = VAR15 <= 4;
wire [VAR15-1:0] VAR43, VAR20;
\pos #(.VAR4(VAR4), .VAR13(VAR13), .VAR15(VAR15)) VAR12 (.VAR6(VAR6), .VAR5(VAR43));
\pos #(.VAR4(VAR41), .VAR13(VAR37), .VAR15(VAR15)) VAR30 (.VAR6(VAR42), .VAR5(VAR20));
function integer VAR27;
input integer VAR45;
begin
VAR27 = ((VAR45 + 1) / 2) * 2;
end
endfunction
localparam VAR23 = VAR27(VAR15);
wire [VAR23-1:0] VAR36 = VAR43;
wire [VAR23-1:0] VAR17 = VAR34 ? ~VAR20 : VAR20;
wire [VAR23-1:0] VAR32 = VAR20;
wire [VAR23+1:0] VAR33, VAR18;
genvar VAR31;
VAR44 #(
.VAR9("0xFFFF"),
.VAR29("0x00AA"),
.VAR2("VAR25")
) VAR24 (
.VAR22(1'b1), .VAR28(1'b1), .VAR19(1'b1), .VAR38(1'b1),
.VAR10(VAR40), .VAR8(1'b1), .VAR11(1'b1), .VAR1(1'b1),
.VAR7(VAR33[0])
);
generate for (VAR31 = 0; VAR31 < VAR23; VAR31 = VAR31 + 2) begin:VAR3
VAR44 #(
.VAR9("0x96AA"),
.VAR29("0x96AA"),
.VAR2("VAR25")
) VAR24 (
.VAR39(VAR33[VAR31]),
.VAR22(VAR36[VAR31]), .VAR28(VAR32[VAR31]), .VAR19(VAR34), .VAR38(1'b1),
.VAR10(VAR36[VAR31+1]), .VAR8(VAR32[VAR31+1]), .VAR11(VAR34), .VAR1(1'b1),
.VAR14(VAR5[VAR31]), .VAR26(VAR18[VAR31]),
.VAR7(VAR33[VAR31+2])
);
assign VAR16[VAR31] = (VAR36[VAR31] && VAR17[VAR31]) || ((VAR5[VAR31] ^ VAR36[VAR31] ^ VAR17[VAR31]) && (VAR36[VAR31] || VAR17[VAR31]));
if (VAR31+1 < VAR15) begin
assign VAR16[VAR31 + 1] = (VAR36[VAR31 + 1] && VAR17[VAR31 + 1]) || ((VAR5[VAR31 + 1] ^ VAR36[VAR31 + 1] ^ VAR17[VAR31 + 1]) && (VAR36[VAR31 + 1] || VAR17[VAR31 + 1]));
assign VAR5[VAR31+1] = VAR18[VAR31];
end
end endgenerate
assign VAR21 = VAR36 ^ VAR17;
endmodule
|
isc
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/iobdg/common/rtl/iobdg_jbus_mondo_buf.v
| 4,483 |
module MODULE1 (
VAR24, VAR13, VAR20, VAR11, VAR6,
VAR10, clk, VAR18, VAR26, VAR21
);
input VAR10;
input clk;
input VAR18;
input [VAR4-1:0] VAR26;
output VAR24;
output [63:0] VAR13;
output [63:0] VAR20;
output [VAR14-1:0] VAR11;
output [VAR7-1:0] VAR6;
input VAR21;
wire [VAR5-1:0] VAR1;
wire [VAR5-1:0] VAR22;
wire [VAR4*VAR5-1:0] VAR9;
wire [VAR4*VAR5-1:0] VAR3;
wire VAR19;
assign VAR1 = {VAR22[VAR5-2:0],VAR18};
VAR16 #(VAR5) VAR23 (.din(VAR1),
.VAR10(VAR10),
.en(VAR19),
.clk(clk),
.VAR12(VAR22));
assign VAR9 = {VAR3[VAR4*(VAR5-1)-1:0],
VAR26};
VAR16 #(VAR4*VAR5) VAR2 (.din(VAR9),
.en(VAR19),
.clk(clk),
.VAR10(VAR10),
.VAR12(VAR3));
assign VAR19 = ~&VAR22 | VAR21;
assign VAR24 = &VAR22;
assign VAR11 = VAR3[VAR8+128:VAR15+128];
assign VAR6 = VAR3[VAR25+128:VAR17+128];
assign VAR13 = VAR3[127:64];
assign VAR20 = VAR3[63:0];
endmodule
|
gpl-2.0
|
secworks/mkmif
|
src/rtl/mkmif.v
| 8,193 |
module MODULE1(
input wire clk,
input wire VAR11,
output wire VAR29,
output wire VAR48,
input wire VAR35,
output wire VAR37,
input wire VAR22,
input wire VAR6,
input wire [7 : 0] address,
input wire [31 : 0] VAR2,
output wire [31 : 0] VAR10
);
localparam VAR14 = 8'h00;
localparam VAR47 = 8'h01;
localparam VAR15 = 8'h02;
localparam VAR23 = 8'h08;
localparam VAR26 = 0;
localparam VAR30 = 1;
localparam VAR19 = 2;
localparam VAR42 = 8'h09;
localparam VAR21 = 0;
localparam VAR46 = 1;
localparam VAR20 = 8'h0a;
localparam VAR27 = 8'h10;
localparam VAR44 = 8'h20;
localparam VAR8 = 16'h0020;
localparam VAR36 = 32'h6d6b6d69; localparam VAR33 = 32'h66202020; localparam VAR17 = 32'h302e3130;
reg VAR31;
reg VAR3;
reg VAR18;
reg VAR24;
reg VAR9;
reg VAR4;
reg [15 : 0] VAR5;
reg VAR28;
reg [15 : 0] VAR1;
reg VAR25;
reg [31 : 0] VAR39;
reg VAR13;
wire VAR49;
wire VAR34;
wire [31 : 0] VAR38;
reg [31 : 0] VAR12;
assign VAR10 = VAR12;
VAR40 VAR41(
.clk(clk),
.VAR11(VAR11),
.VAR29(VAR29),
.VAR48(VAR48),
.VAR35(VAR35),
.VAR37(VAR37),
.VAR45(VAR31),
.VAR7(VAR18),
.VAR16(VAR9),
.ready(VAR49),
.valid(VAR34),
.VAR43(VAR1),
.addr(VAR5),
.VAR2(VAR39),
.VAR10(VAR38)
);
always @ (posedge clk or negedge VAR11)
begin
if (!VAR11)
begin
VAR31 <= 1'h0;
VAR18 <= 1'h0;
VAR5 <= 16'h0;
VAR1 <= VAR8;
VAR39 <= 32'h0;
end
else
begin
VAR31 <= VAR3;
VAR18 <= VAR24;
VAR9 <= VAR4;
if (VAR25)
VAR1 <= VAR2[15 : 0];
if (VAR28)
VAR5 <= VAR2[15 : 0];
if (VAR13)
VAR39 <= VAR2;
end
end
always @*
begin : VAR32
VAR3 = 0;
VAR24 = 0;
VAR4 = 0;
VAR28 = 0;
VAR25 = 0;
VAR13 = 0;
VAR12 = 32'h00000000;
if (VAR22)
begin
if (VAR6)
begin
case (address)
VAR23:
begin
VAR3 = VAR2[VAR26];
VAR24 = VAR2[VAR30];
VAR4 = VAR2[VAR19];
end
VAR20:
VAR25 = 1;
VAR27:
VAR28 = 1;
VAR44:
VAR13 = 1;
default:
begin
end
endcase end
else
begin
case (address)
VAR14:
VAR12 = VAR36;
VAR47:
VAR12 = VAR33;
VAR15:
VAR12 = VAR17;
VAR42:
VAR12 = {30'h0, {VAR34, VAR49}};
VAR20:
VAR12 = {16'h0, VAR1};
VAR27:
VAR12 = {16'h0, VAR5};
VAR44:
begin
VAR12 = VAR38;
end
default:
begin
end
endcase end
end
end endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a222o/sky130_fd_sc_hs__a222o.behavioral.pp.v
| 2,290 |
module MODULE1 (
VAR8 ,
VAR9 ,
VAR21 ,
VAR19 ,
VAR13 ,
VAR3 ,
VAR10 ,
VAR5,
VAR1
);
output VAR8 ;
input VAR9 ;
input VAR21 ;
input VAR19 ;
input VAR13 ;
input VAR3 ;
input VAR10 ;
input VAR5;
input VAR1;
wire VAR13 VAR14 ;
wire VAR13 VAR18 ;
wire VAR13 VAR4 ;
wire VAR15 ;
wire VAR6;
and VAR12 (VAR14 , VAR19, VAR13 );
and VAR7 (VAR18 , VAR9, VAR21 );
and VAR2 (VAR4 , VAR3, VAR10 );
or VAR16 (VAR15 , VAR18, VAR14, VAR4);
VAR11 VAR17 (VAR6, VAR15, VAR5, VAR1 );
buf VAR20 (VAR8 , VAR6 );
endmodule
|
apache-2.0
|
emeb/iceRadio
|
FPGA/rxadc_2/verilog/src/cic_dec_3.v
| 2,370 |
module MODULE1 #(
parameter VAR6 = 4, VAR8 = 8, VAR7 = 10, VAR2 = (VAR7 + (VAR6 * VAR8)), VAR14 = VAR2 )
(
input clk, input reset, input VAR10, input signed [VAR7-1:0] VAR9, output signed [VAR14-1:0] VAR1, output valid );
wire signed [VAR2-1:0] VAR15 = {{VAR2-VAR7{VAR9[VAR7-1]}},VAR9};
reg signed [VAR2-1:0] VAR11[0:VAR6-1];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR11[0] <= {VAR2{1'b0}};
end
else
begin
VAR11[0] <= VAR11[0] + VAR15;
end
end
generate
genvar VAR13;
for(VAR13=1;VAR13<VAR6;VAR13=VAR13+1)
begin
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR11[VAR13] <= {VAR2{1'b0}};
end
else
begin
VAR11[VAR13] <= VAR11[VAR13] + VAR11[VAR13-1];
end
end
end
endgenerate
reg [VAR6:0] VAR5;
reg signed [VAR14-1:0] VAR12[0:VAR6];
reg signed [VAR14-1:0] VAR4[0:VAR6];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR5 <= {VAR6+2{1'b0}};
VAR12[0] <= {VAR14{1'b0}};
VAR4[0] <= {VAR14{1'b0}};
end
else
begin
if(VAR10 == 1'b1)
begin
VAR12[0] <= VAR11[VAR6-1]>>>(VAR2-VAR14);
VAR4[0] <= VAR12[0];
end
VAR5 <= {VAR5[VAR6:0],VAR10};
end
end
generate
genvar VAR3;
for(VAR3=1;VAR3<=VAR6;VAR3=VAR3+1)
begin
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR12[VAR3] <= {VAR14{1'b0}};
VAR4[VAR3] <= {VAR14{1'b0}};
end
else if(VAR5[VAR3-1] == 1'b1)
begin
VAR12[VAR3] <= VAR12[VAR3-1] - VAR4[VAR3-1];
VAR4[VAR3] <= VAR12[VAR3];
end
end
end
endgenerate
assign VAR1 = VAR12[VAR6];
assign valid = VAR5[VAR6];
endmodule
|
mit
|
Masahiro000Shimasaki/NeuralNetwork
|
Hardware/Perceptron_xor/fp_convert.v
| 29,289 |
module MODULE1
(
VAR6,
VAR8,
VAR17,
VAR13,
VAR10,
VAR2) ;
input VAR6;
input VAR8;
input VAR17;
input [31:0] VAR13;
input [4:0] VAR10;
output [31:0] VAR2;
tri0 VAR6;
tri1 VAR8;
tri0 VAR17;
reg [1:0] VAR16;
reg [31:0] VAR1;
reg [31:0] VAR7;
reg VAR3;
reg VAR4;
wire [5:0] VAR12;
wire VAR9;
wire [15:0] VAR15;
wire [191:0] VAR14;
wire [4:0] VAR5;
wire [159:0] VAR11;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab4/axi_interfaces_prj/solution2/syn/verilog/axi_interfaces.v
| 74,343 |
module MODULE1 (
VAR172,
VAR92,
VAR46,
VAR265,
VAR189,
VAR195,
VAR225,
VAR222,
VAR272,
VAR104,
VAR156,
VAR257,
VAR210,
VAR59,
VAR293,
VAR111,
VAR47,
VAR276,
VAR19,
VAR370,
VAR237,
VAR170,
VAR150,
VAR154,
VAR208,
VAR109,
VAR139,
VAR202,
VAR106,
VAR246,
VAR137,
VAR8,
VAR220,
VAR196,
VAR50,
VAR322,
VAR102,
VAR117,
VAR163,
VAR329,
VAR149,
VAR198,
VAR168,
VAR247,
VAR199,
VAR17,
VAR230,
VAR249,
VAR75,
VAR269,
VAR169,
VAR284,
VAR306,
VAR55,
VAR122,
VAR185,
VAR337,
VAR167,
VAR120,
VAR20,
VAR341,
VAR131,
VAR342,
VAR99,
VAR273,
VAR335,
VAR233,
interrupt
);
parameter VAR319 = 2'd1;
parameter VAR258 = 2'd2;
parameter VAR5 = 32;
parameter VAR360 = 4;
parameter VAR36 = 32;
parameter VAR240 = (32 / 8);
parameter VAR384 = (32 / 8);
input VAR172;
input VAR92;
input VAR46;
input VAR265;
input VAR189;
input VAR195;
input VAR225;
input VAR222;
input VAR272;
input VAR104;
output [15:0] VAR156;
output VAR257;
output [15:0] VAR210;
output VAR59;
output [15:0] VAR293;
output VAR111;
output [15:0] VAR47;
output VAR276;
output [15:0] VAR19;
output VAR370;
output [15:0] VAR237;
output VAR170;
output [15:0] VAR150;
output VAR154;
output [15:0] VAR208;
output VAR109;
input [15:0] VAR139;
input VAR202;
output VAR106;
input [15:0] VAR246;
input VAR137;
output VAR8;
input [15:0] VAR220;
input VAR196;
output VAR50;
input [15:0] VAR322;
input VAR102;
output VAR117;
input [15:0] VAR163;
input VAR329;
output VAR149;
input [15:0] VAR198;
input VAR168;
output VAR247;
input [15:0] VAR199;
input VAR17;
output VAR230;
input [15:0] VAR249;
input VAR75;
output VAR269;
input VAR169;
output VAR284;
input [VAR360 - 1:0] VAR306;
input VAR55;
output VAR122;
input [VAR5 - 1:0] VAR185;
input [VAR240 - 1:0] VAR337;
input VAR167;
output VAR120;
input [VAR360 - 1:0] VAR20;
output VAR341;
input VAR131;
output [VAR5 - 1:0] VAR342;
output [1:0] VAR99;
output VAR273;
input VAR335;
output [1:0] VAR233;
output interrupt;
reg VAR338;
wire VAR87;
reg VAR24;
reg VAR1;
reg [1:0] VAR211;
wire VAR235;
reg VAR82;
wire [0:0] VAR212;
wire VAR54;
wire VAR78;
wire VAR330;
wire VAR101;
wire VAR351;
wire VAR52;
wire VAR147;
wire VAR244;
wire VAR239;
wire VAR45;
wire VAR362;
reg VAR127;
wire VAR67;
wire VAR89;
wire VAR157;
wire VAR300;
wire VAR303;
wire VAR376;
wire VAR22;
wire VAR108;
reg VAR57;
reg VAR4;
reg VAR217;
reg VAR182;
reg VAR291;
reg VAR215;
reg [15:0] VAR324;
reg VAR6;
wire VAR70;
wire VAR374;
reg [15:0] VAR132;
reg [15:0] VAR121;
reg VAR124;
reg VAR7;
wire VAR125;
wire VAR248;
wire VAR2;
reg [1:0] VAR253;
wire VAR135;
reg [15:0] VAR371;
reg VAR134;
wire VAR3;
wire VAR336;
reg [15:0] VAR155;
reg [15:0] VAR58;
reg VAR191;
reg VAR350;
wire VAR359;
wire VAR38;
wire VAR214;
reg [1:0] VAR66;
wire VAR382;
reg [15:0] VAR90;
reg VAR313;
wire VAR18;
wire VAR138;
reg [15:0] VAR204;
reg [15:0] VAR354;
reg VAR77;
reg VAR148;
wire VAR80;
wire VAR292;
wire VAR227;
reg [1:0] VAR115;
wire VAR143;
reg [15:0] VAR81;
reg VAR254;
wire VAR35;
wire VAR31;
reg [15:0] VAR317;
reg [15:0] VAR62;
reg VAR39;
reg VAR30;
wire VAR85;
wire VAR280;
wire VAR363;
reg [1:0] VAR373;
wire VAR218;
reg [15:0] VAR25;
reg VAR113;
wire VAR369;
wire VAR61;
reg [15:0] VAR48;
reg [15:0] VAR53;
reg VAR310;
reg VAR378;
wire VAR344;
wire VAR152;
wire VAR178;
reg [1:0] VAR228;
wire VAR136;
reg [15:0] VAR44;
reg VAR264;
wire VAR69;
wire VAR256;
reg [15:0] VAR84;
reg [15:0] VAR229;
reg VAR314;
reg VAR297;
wire VAR343;
wire VAR201;
wire VAR339;
reg [1:0] VAR255;
wire VAR389;
reg [15:0] VAR93;
reg VAR184;
wire VAR353;
wire VAR287;
reg [15:0] VAR333;
reg [15:0] VAR94;
reg VAR40;
reg VAR290;
wire VAR71;
wire VAR119;
wire VAR348;
reg [1:0] VAR250;
wire VAR29;
reg [15:0] VAR261;
reg VAR311;
wire VAR51;
wire VAR107;
reg [15:0] VAR243;
reg [15:0] VAR180;
reg VAR177;
reg VAR226;
wire VAR277;
wire VAR315;
wire VAR43;
reg [1:0] VAR194;
wire VAR9;
reg [15:0] VAR320;
wire VAR308;
wire VAR386;
reg VAR187;
reg [15:0] VAR365;
reg [15:0] VAR207;
reg VAR142;
reg VAR260;
wire VAR364;
wire VAR252;
wire VAR219;
reg [1:0] VAR242;
wire VAR116;
reg [15:0] VAR34;
wire VAR41;
wire VAR241;
reg VAR266;
reg [15:0] VAR26;
reg [15:0] VAR352;
reg VAR323;
reg VAR286;
wire VAR355;
wire VAR88;
wire VAR289;
reg [1:0] VAR231;
wire VAR346;
reg [15:0] VAR64;
wire VAR262;
wire VAR301;
reg VAR176;
reg [15:0] VAR271;
reg [15:0] VAR33;
reg VAR263;
reg VAR153;
wire VAR173;
wire VAR160;
wire VAR380;
reg [1:0] VAR327;
wire VAR161;
reg [15:0] VAR110;
wire VAR309;
wire VAR73;
reg VAR123;
reg [15:0] VAR133;
reg [15:0] VAR151;
reg VAR68;
reg VAR10;
wire VAR144;
wire VAR72;
wire VAR74;
reg [1:0] VAR83;
wire VAR213;
reg [15:0] VAR312;
wire VAR14;
wire VAR146;
reg VAR130;
reg [15:0] VAR307;
reg [15:0] VAR21;
reg VAR275;
reg VAR278;
wire VAR126;
wire VAR356;
wire VAR221;
reg [1:0] VAR281;
wire VAR159;
reg [15:0] VAR383;
wire VAR331;
wire VAR216;
reg VAR294;
reg [15:0] VAR190;
reg [15:0] VAR174;
reg VAR205;
reg VAR340;
wire VAR100;
wire VAR162;
wire VAR103;
reg [1:0] VAR129;
wire VAR60;
reg [15:0] VAR91;
wire VAR105;
wire VAR114;
reg VAR118;
reg [15:0] VAR224;
reg [15:0] VAR296;
reg VAR164;
reg VAR192;
wire VAR63;
wire VAR209;
wire VAR318;
reg [1:0] VAR223;
wire VAR345;
reg [15:0] VAR86;
wire VAR95;
wire VAR166;
reg VAR141;
reg [15:0] VAR368;
reg [15:0] VAR305;
reg VAR375;
reg VAR298;
wire VAR96;
wire VAR304;
wire VAR193;
reg [1:0] VAR366;
wire VAR358;
reg [31:0] VAR197;
reg [31:0] VAR347;
reg [31:0] VAR128;
reg [31:0] VAR165;
reg [31:0] VAR387;
reg [31:0] VAR158;
reg [31:0] VAR326;
reg [31:0] VAR140;
reg VAR288;
wire VAR42;
reg VAR361;
reg VAR302;
reg VAR388;
reg VAR183;
reg VAR325;
reg VAR97;
reg VAR11;
reg VAR12;
reg VAR79;
reg VAR357;
reg VAR379;
reg VAR171;
reg VAR332;
reg VAR112;
reg VAR279;
reg [4:0] VAR27;
wire [4:0] VAR282;
reg [4:0] VAR334;
reg [0:0] VAR251;
reg [0:0] VAR381;
wire [15:0] VAR232;
wire [15:0] VAR299;
wire [15:0] VAR32;
wire [15:0] VAR179;
wire [15:0] VAR28;
wire [15:0] VAR203;
wire [15:0] VAR181;
wire [15:0] VAR367;
reg VAR16;
reg [4:0] VAR316;
wire [31:0] VAR200;
wire [31:0] VAR267;
wire [31:0] VAR76;
wire [31:0] VAR283;
wire [31:0] VAR321;
wire [31:0] VAR295;
wire [31:0] VAR285;
wire [31:0] VAR175;
reg VAR245;
wire [5:0] VAR186;
wire [5:0] VAR98;
wire signed [31:0] VAR234;
wire [15:0] VAR37;
wire signed [31:0] VAR349;
wire [15:0] VAR49;
wire signed [31:0] VAR259;
wire [15:0] VAR268;
wire signed [31:0] VAR372;
wire [15:0] VAR377;
wire signed [31:0] VAR206;
wire [15:0] VAR15;
wire signed [31:0] VAR270;
wire [15:0] VAR13;
wire signed [31:0] VAR188;
wire [15:0] VAR65;
wire signed [31:0] VAR56;
wire [15:0] VAR238;
reg [1:0] VAR274;
reg VAR145;
reg VAR385;
reg VAR23;
wire VAR236;
reg VAR328;
|
mit
|
kyzhai/NUNY
|
src/hardware/five_new2_bb.v
| 5,018 |
module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule
|
gpl-2.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_rdq_buf.v
| 3,034 |
module MODULE1(
VAR15,
clk, VAR4, VAR20, VAR18, VAR17, VAR6, VAR3,
VAR2, VAR22, VAR19
);
input clk;
input VAR4;
input VAR20;
input VAR18;
input VAR17;
input VAR6;
input VAR3;
input [VAR21-1:0] VAR2;
input [VAR21-1:0] VAR22;
input [VAR11-1:0] VAR19;
output [VAR11-1:0] VAR15;
wire [VAR11-1:0] VAR15;
wire [3:0] VAR10;
VAR16 VAR14
( .dout ( {VAR10[3:0],
VAR15} ),
.VAR7 (VAR4),
.VAR13 (VAR3),
.VAR5 (VAR22),
.VAR9 (clk),
.VAR8 (VAR6),
.VAR12 (VAR2),
.din ( {4'b0000,
VAR19} ),
.VAR1 (VAR20),
.VAR18 (VAR18),
.VAR23 (1'b1), .VAR17 (VAR17)
);
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/and4b/sky130_fd_sc_lp__and4b.functional.v
| 1,412 |
module MODULE1 (
VAR8 ,
VAR5,
VAR9 ,
VAR7 ,
VAR4
);
output VAR8 ;
input VAR5;
input VAR9 ;
input VAR7 ;
input VAR4 ;
wire VAR10 ;
wire VAR2;
not VAR6 (VAR10 , VAR5 );
and VAR3 (VAR2, VAR10, VAR9, VAR7, VAR4);
buf VAR1 (VAR8 , VAR2 );
endmodule
|
apache-2.0
|
davidkoltak/tawas-core
|
projects/de0_nano_soc/rtl/de0_nano_soc.v
| 3,517 |
module MODULE1
(
input VAR18,
input VAR1,
input VAR12,
input [1:0] VAR72,
input [3:0] VAR44,
output [7:0] VAR64,
output VAR52,
input VAR74,
output VAR38,
input VAR9
);
wire VAR7 = VAR18;
wire VAR59 = VAR1;
wire VAR2 = VAR72[0];
wire VAR43;
wire [23:0] VAR42;
wire [31:0] VAR31;
VAR83 VAR83
(
.clk(VAR7),
.addr(VAR42),
.VAR78(VAR43),
.dout(VAR31)
);
wire [31:0] VAR48;
wire VAR68;
wire VAR11;
wire [3:0] VAR30;
wire [31:0] VAR32;
wire [31:0] VAR56;
VAR36 VAR36
(
.clk(VAR7),
.addr(VAR48),
.VAR78(VAR68),
.wr(VAR11),
.VAR13(VAR30),
.din(VAR32),
.dout(VAR56)
);
wire [68:0] VAR8;
wire [68:0] VAR41;
wire [68:0] VAR63;
wire [68:0] VAR22;
wire [68:0] VAR77;
VAR71 #(.VAR81(0)) VAR71
(
.clk(VAR7),
.rst(!VAR2),
.VAR53(VAR43),
.VAR76(VAR42),
.VAR19(VAR31),
.VAR14(VAR68),
.VAR25(VAR11),
.VAR65(VAR48),
.VAR10(VAR30),
.dout(VAR32),
.din(VAR56),
.VAR49(VAR8),
.VAR33(VAR41)
);
wire [31:0] VAR17;
wire [31:0] VAR37;
wire [31:0] VAR45;
VAR62 #(.VAR55(24'hFFFFF0)) VAR82
(
.clk(VAR7),
.rst(!VAR2),
.VAR17(),
.VAR17(),
.VAR45(),
.VAR49(VAR41),
.VAR33(VAR63)
);
VAR4 #(.VAR55(24'hFE0000)) VAR61
(
.clk(VAR7),
.rst(!VAR2),
.VAR49(VAR63),
.VAR33(VAR22)
);
wire VAR3;
wire VAR54;
VAR73 #(.VAR55(24'hFFFFB8)) VAR51
(
.clk(VAR7),
.VAR7(VAR7),
.rst(!VAR2),
.VAR49(VAR22),
.VAR33(VAR77),
.VAR28(VAR3),
.VAR35(VAR54),
.VAR21(VAR52),
.VAR29(VAR74)
);
wire [68:0] VAR47;
wire [68:0] VAR6;
wire [68:0] VAR79;
VAR26 #(.VAR27(6'h3C), .VAR57(6'h08),
.VAR5(24'hF00000), .VAR55(24'h100000)) VAR60
(
.VAR69(VAR7),
.VAR24(!VAR2),
.VAR70(VAR59),
.VAR40(VAR77),
.VAR34(VAR8),
.VAR50(VAR47),
.VAR15(VAR6)
);
wire [31:0] VAR80;
assign VAR64[7:0] = VAR80[7:0];
VAR23 #(.VAR81(9)) VAR58
(
.clk(VAR59),
.VAR7(VAR7),
.rst(!VAR2),
.VAR49(VAR6),
.VAR33(VAR79),
.VAR67({28'd0, VAR44[3:0]}),
.VAR66(),
.VAR16(VAR80),
.VAR39(),
.VAR21(VAR38),
.VAR29(VAR9)
);
VAR75 #(.VAR55(24'h1FFFC0), .VAR81(8)) VAR20
(
.clk(VAR59),
.rst(!VAR2),
.VAR49(VAR79),
.VAR33(VAR47),
.req({VAR54, VAR3, 14'd1}),
.VAR46()
);
endmodule
|
mit
|
markusC64/1541ultimate2
|
fpga/nios/nios/synthesis/submodules/nios_nios2_gen2_0_cpu_debug_slave_wrapper.v
| 9,385 |
module MODULE1 (
VAR49,
VAR22,
clk,
VAR43,
VAR33,
VAR7,
VAR40,
VAR29,
VAR34,
VAR35,
VAR11,
VAR52,
VAR10,
VAR36,
VAR44,
VAR45,
VAR23,
VAR28,
VAR8,
VAR18,
VAR37,
VAR19,
VAR47,
VAR54,
VAR50,
VAR46,
VAR30,
VAR39,
VAR21,
VAR41,
VAR12,
VAR24,
VAR15
)
;
output [ 37: 0] VAR37;
output VAR19;
output VAR47;
output VAR54;
output VAR50;
output VAR46;
output VAR30;
output VAR39;
output VAR21;
output VAR41;
output VAR12;
output VAR24;
output VAR15;
input [ 31: 0] VAR49;
input [ 31: 0] VAR22;
input clk;
input VAR43;
input VAR33;
input VAR7;
input VAR40;
input VAR29;
input VAR34;
input VAR35;
input VAR11;
input VAR52;
input VAR10;
input [ 35: 0] VAR36;
input VAR44;
input [ 6: 0] VAR45;
input VAR23;
input VAR28;
input VAR8;
input VAR18;
wire [ 37: 0] VAR37;
wire VAR19;
wire [ 37: 0] VAR4;
wire VAR47;
wire VAR54;
wire VAR50;
wire VAR46;
wire VAR30;
wire VAR39;
wire VAR21;
wire VAR41;
wire VAR12;
wire VAR24;
wire VAR15;
wire VAR6;
wire [ 1: 0] VAR3;
wire [ 1: 0] VAR48;
wire VAR2;
wire VAR9;
wire VAR31;
wire VAR42;
wire VAR55;
wire VAR51;
wire VAR38;
VAR14 VAR16
(
.VAR49 (VAR49),
.VAR22 (VAR22),
.VAR43 (VAR43),
.VAR33 (VAR33),
.VAR7 (VAR7),
.VAR40 (VAR40),
.VAR29 (VAR29),
.VAR32 (VAR3),
.VAR1 (VAR48),
.VAR19 (VAR19),
.VAR53 (VAR2),
.VAR34 (VAR34),
.VAR35 (VAR35),
.VAR11 (VAR11),
.VAR52 (VAR52),
.VAR4 (VAR4),
.VAR47 (VAR47),
.VAR20 (VAR31),
.VAR27 (VAR42),
.VAR13 (VAR55),
.VAR10 (VAR10),
.VAR36 (VAR36),
.VAR44 (VAR44),
.VAR45 (VAR45),
.VAR23 (VAR23),
.VAR28 (VAR28),
.VAR8 (VAR8),
.VAR18 (VAR18),
.VAR26 (VAR6),
.VAR57 (VAR9),
.VAR56 (VAR38)
);
VAR25 VAR5
(
.clk (clk),
.VAR32 (VAR3),
.VAR37 (VAR37),
.VAR4 (VAR4),
.VAR54 (VAR54),
.VAR50 (VAR50),
.VAR46 (VAR46),
.VAR30 (VAR30),
.VAR39 (VAR39),
.VAR21 (VAR21),
.VAR41 (VAR41),
.VAR12 (VAR12),
.VAR24 (VAR24),
.VAR15 (VAR15),
.VAR17 (VAR51),
.VAR56 (VAR38)
);
assign VAR31 = 1'b0;
assign VAR42 = 1'b0;
assign VAR9 = 1'b0;
assign VAR6 = 1'b0;
assign VAR2 = 1'b0;
assign VAR38 = 1'b0;
assign VAR51 = 1'b0;
assign VAR3 = 2'b0;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nand2b/sky130_fd_sc_lp__nand2b_m.v
| 2,144 |
module MODULE2 (
VAR3 ,
VAR9 ,
VAR4 ,
VAR5,
VAR2,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR1 ;
VAR7 VAR6 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3 ,
VAR9,
VAR4
);
output VAR3 ;
input VAR9;
input VAR4 ;
supply1 VAR5;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR1 ;
VAR7 VAR6 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.behavioral.pp.v
| 2,820 |
module MODULE1( VAR20, VAR2, VAR21, VAR24, VAR6, VAR17 );
input VAR21, VAR2, VAR20;
inout VAR6, VAR17;
output VAR24;
reg VAR14;
VAR15 VAR13(.VAR20(VAR20),.VAR2(VAR2),.VAR21(VAR21),.VAR24(VAR24),.VAR6(VAR6),.VAR17(VAR17),.VAR14(VAR14));
VAR15 VAR25(.VAR20(VAR20),.VAR2(VAR2),.VAR21(VAR21),.VAR24(VAR24),.VAR6(VAR6),.VAR17(VAR17),.VAR14(VAR14));
not VAR7(VAR4,VAR2);
not VAR3(VAR16,VAR20);
and VAR11(VAR1,VAR16,VAR4);
not VAR9(VAR12,VAR2);
and VAR26(VAR22,VAR20,VAR12);
not VAR10(VAR18,VAR20);
and VAR19(VAR5,VAR18,VAR2);
and VAR23(VAR8,VAR20,VAR2);
|
apache-2.0
|
marmolejo/zet
|
cores/zet/rtl/zet_jmp_cond.v
| 2,051 |
module MODULE1 (
input [4:0] VAR6,
input [3:0] VAR5,
input VAR8,
input [15:0] VAR11,
output reg VAR2
);
wire VAR4, VAR10, VAR3, VAR1, VAR7;
wire VAR9;
assign VAR4 = VAR6[4];
assign VAR10 = VAR6[3];
assign VAR3 = VAR6[2];
assign VAR1 = VAR6[1];
assign VAR7 = VAR6[0];
assign VAR9 = ~(|VAR11);
always @(VAR5 or VAR8 or VAR9 or VAR3 or VAR4 or VAR7 or VAR10 or VAR1)
if (VAR8) case (VAR5)
4'b0000: VAR2 <= VAR9;
4'b0001: VAR2 <= ~VAR9;
4'b0010: VAR2 <= VAR3 & ~VAR9;
default: VAR2 <= ~VAR3 & ~VAR9;
endcase
else case (VAR5)
4'b0000: VAR2 <= VAR4;
4'b0001: VAR2 <= ~VAR4;
4'b0010: VAR2 <= VAR7;
4'b0011: VAR2 <= ~VAR7;
4'b0100: VAR2 <= VAR3;
4'b0101: VAR2 <= ~VAR3;
4'b0110: VAR2 <= VAR7 | VAR3;
4'b0111: VAR2 <= ~VAR7 & ~VAR3;
4'b1000: VAR2 <= VAR10;
4'b1001: VAR2 <= ~VAR10;
4'b1010: VAR2 <= VAR1;
4'b1011: VAR2 <= ~VAR1;
4'b1100: VAR2 <= (VAR10 ^ VAR4);
4'b1101: VAR2 <= (VAR10 ^~ VAR4);
4'b1110: VAR2 <= VAR3 | (VAR10 ^ VAR4);
4'b1111: VAR2 <= ~VAR3 & (VAR10 ^~ VAR4);
endcase
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o32ai/sky130_fd_sc_ls__o32ai.functional.pp.v
| 2,191 |
module MODULE1 (
VAR1 ,
VAR17 ,
VAR8 ,
VAR9 ,
VAR12 ,
VAR7 ,
VAR2,
VAR20,
VAR10 ,
VAR11
);
output VAR1 ;
input VAR17 ;
input VAR8 ;
input VAR9 ;
input VAR12 ;
input VAR7 ;
input VAR2;
input VAR20;
input VAR10 ;
input VAR11 ;
wire VAR3 ;
wire VAR6 ;
wire VAR5 ;
wire VAR16;
nor VAR15 (VAR3 , VAR9, VAR17, VAR8 );
nor VAR18 (VAR6 , VAR12, VAR7 );
or VAR14 (VAR5 , VAR6, VAR3 );
VAR19 VAR4 (VAR16, VAR5, VAR2, VAR20);
buf VAR13 (VAR1 , VAR16 );
endmodule
|
apache-2.0
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/iface/ip/SGDMA_dispatcher/fifo_with_byteenables.v
| 5,508 |
module MODULE1 (
clk,
VAR17,
VAR8,
VAR42,
VAR28,
write,
VAR11,
VAR10,
VAR37,
VAR27,
VAR23,
VAR41
);
parameter VAR43 = 32;
parameter VAR5 = 128;
parameter VAR38 = 7; parameter VAR13 = 1;
input clk;
input VAR17;
input VAR8;
input [VAR43-1:0] VAR42;
input [(VAR43/8)-1:0] VAR28;
input write;
input VAR11; output wire [VAR43-1:0] VAR10;
input VAR37; output wire [VAR38:0] VAR27;
output wire VAR23;
output wire VAR41;
reg [VAR38-1:0] VAR46;
reg [VAR38-1:0] VAR21;
reg [VAR38:0] VAR9;
wire VAR3;
wire VAR18;
always @ (posedge clk or posedge VAR17)
begin
if (VAR17)
begin
VAR46 <= 0;
end
else
begin
if (VAR8)
begin
VAR46 <= 0;
end
else if (VAR11 == 1)
begin
VAR46 <= VAR46 + 1'b1;
end
end
end
always @ (posedge clk or posedge VAR17)
begin
if (VAR17)
begin
VAR21 <= 0;
end
else
begin
if (VAR8)
begin
VAR21 <= 0;
end
else if (VAR37 == 1)
begin
VAR21 <= VAR21 + 1'b1;
end
end
end
VAR4 VAR44 (
.VAR16 (clk),
.VAR36 (write),
.VAR32 (VAR28),
.VAR30 (VAR42),
.VAR33 (VAR46),
.VAR45 (VAR10),
.VAR39 (VAR21)
);
always @ (posedge clk or posedge VAR17)
begin
if (VAR17)
begin
VAR9 <= 0;
end
else
begin
if (VAR8)
begin
VAR9 <= 0;
end
else
begin
case ({VAR11, VAR37})
2'b01: VAR9 <= VAR9 - 1'b1;
2'b10: VAR9 <= VAR9 + 1'b1;
default: VAR9 <= VAR9;
endcase
end
end
end
assign VAR18 = (VAR21 == VAR46) & (VAR9 == 0);
assign VAR3 = (VAR46 == VAR21) & (VAR9 != 0);
assign VAR27 = VAR9; assign VAR41 = VAR18; assign VAR23 = VAR3;
endmodule
|
mit
|
leaflabs/rhd2000_dm
|
rhd2000_dm.v
| 9,805 |
module MODULE1 #(
parameter VAR3 = 32,
parameter VAR13 = 1,
parameter VAR11 = 0,
parameter VAR9 = 1
)(
input [(16 * VAR3) - 1:0] VAR4,
input VAR1,
input VAR2,
input VAR5,
output reg VAR7,
output reg VAR8
);
reg [7:0] VAR12 [17:0];
reg [7:0] VAR10 [8:0];
integer address = 0;
reg [7:0] VAR6 = 0;
|
mit
|
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_clk_wiz_0_0/tutorial_clk_wiz_0_0_clk_wiz.v
| 6,474 |
module MODULE1
( input VAR38,
output VAR50
);
VAR20 VAR56
(.VAR30 (VAR79),
.VAR77 (VAR38));
wire [15:0] VAR73;
wire VAR62;
wire VAR3;
wire VAR70;
wire VAR28;
wire VAR31;
wire VAR66;
wire VAR47;
wire VAR67;
wire VAR41;
wire VAR40;
wire VAR63;
wire VAR4;
wire VAR64;
wire VAR49;
wire VAR42;
wire VAR35;
wire VAR9;
wire VAR34;
VAR74
.VAR25 ("VAR14"),
.VAR65 ("VAR51"),
.VAR60 ("VAR14"),
.VAR17 (4),
.VAR45 (37.125),
.VAR8 (0.000),
.VAR23 ("VAR14"),
.VAR32 (6.250),
.VAR72 (0.000),
.VAR26 (0.500),
.VAR55 ("VAR14"),
.VAR19 (10.0))
VAR58
(
.VAR53 (VAR28),
.VAR13 (VAR66),
.VAR21 (VAR43),
.VAR57 (VAR47),
.VAR15 (VAR67),
.VAR44 (VAR41),
.VAR7 (VAR40),
.VAR68 (VAR63),
.VAR22 (VAR4),
.VAR61 (VAR64),
.VAR46 (VAR49),
.VAR54 (VAR42),
.VAR24 (VAR35),
.VAR39 (VAR31),
.VAR75 (VAR79),
.VAR52 (1'b0),
.VAR78 (1'b1),
.VAR48 (7'h0),
.VAR33 (1'b0),
.VAR6 (1'b0),
.VAR18 (16'h0),
.VAR5 (VAR73),
.VAR69 (VAR62),
.VAR11 (1'b0),
.VAR59 (1'b0),
.VAR16 (1'b0),
.VAR37 (1'b0),
.VAR29 (VAR3),
.VAR10 (VAR70),
.VAR12 (VAR34),
.VAR1 (VAR9),
.VAR71 (1'b0),
.VAR2 (1'b0));
VAR27 VAR76
(.VAR30 (VAR31),
.VAR77 (VAR28));
VAR27 VAR36
(.VAR30 (VAR50),
.VAR77 (VAR43));
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.v
| 2,339 |
module MODULE2 (
VAR9 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR5,
VAR1
);
output VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR1;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR9 ,
VAR4,
VAR6 ,
VAR7 ,
VAR2,
VAR8
);
output VAR9 ;
input VAR4;
input VAR6 ;
input VAR7 ;
input VAR2;
input VAR8;
supply1 VAR5;
supply0 VAR1;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.behavioral.v
| 2,250 |
module MODULE1 (
VAR19 ,
VAR18 ,
VAR2 ,
VAR17 ,
VAR10 ,
VAR9,
VAR8
);
input VAR19 ;
input VAR18 ;
output VAR2 ;
input VAR17 ;
input VAR10 ;
input VAR9;
input VAR8;
wire VAR12 ;
wire VAR3 ;
reg VAR15 ;
wire VAR13 ;
wire VAR22;
wire VAR4;
wire VAR7;
wire VAR16 ;
wire VAR23 ;
wire VAR14 ;
wire VAR21 ;
VAR11 VAR1 (VAR3, VAR13, VAR22, VAR4 );
VAR6 VAR20 (VAR12 , VAR3, VAR7, VAR15, VAR9, VAR8);
assign VAR16 = ( VAR9 === 1'b1 );
assign VAR23 = ( ( VAR4 === 1'b0 ) && VAR16 );
assign VAR14 = ( ( VAR4 === 1'b1 ) && VAR16 );
assign VAR21 = ( ( VAR13 !== VAR22 ) && VAR16 );
buf VAR5 (VAR2 , VAR12 );
endmodule
|
apache-2.0
|
The-OpenROAD-Project/asap7
|
asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_SRAM_FF_210930.v
| 11,817 |
module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1);
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a21oi/sky130_fd_sc_ms__a21oi.behavioral.v
| 1,516 |
module MODULE1 (
VAR5 ,
VAR11,
VAR4,
VAR8
);
output VAR5 ;
input VAR11;
input VAR4;
input VAR8;
supply1 VAR12;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR1 ;
wire VAR2 ;
wire VAR7;
and VAR3 (VAR2 , VAR11, VAR4 );
nor VAR13 (VAR7, VAR8, VAR2 );
buf VAR10 (VAR5 , VAR7 );
endmodule
|
apache-2.0
|
jeichenhofer/chuck-light
|
SoC/soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v
| 4,868 |
module MODULE1 (
clk,
VAR4,
din,
dout
);
parameter VAR1 = 3;
input clk;
input VAR4;
input din;
output dout;
reg VAR3;
reg [VAR1-2:0] VAR2;
|
gpl-3.0
|
kernelpanics/Grad
|
CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/Coprocesador_CORDIC.v
| 9,151 |
module MODULE1 #(parameter VAR112 = 32, parameter VAR75=8, parameter VAR38=5, parameter VAR100 = 8, parameter VAR118 = 23,
parameter VAR32 = 9) (
input wire [31:0] VAR1,
input wire VAR15, input wire VAR106, input wire VAR5, input wire VAR123, input wire VAR109, input wire VAR105, input wire VAR25, input wire VAR22, input wire VAR28, input wire VAR27, input wire VAR4, input wire VAR16, input wire VAR107, input wire VAR7, input wire VAR52, input wire VAR30, input wire VAR121,
output wire VAR79, output wire VAR55, output wire VAR95, output wire VAR61, output wire VAR20, output wire VAR97, output wire VAR87, output wire VAR63, output wire VAR45, output wire [VAR112-1:0] VAR18, output wire [VAR38-1:0] VAR81 );
wire [VAR112-1:0] VAR21;
wire [VAR112-1:0] VAR119;
wire [VAR112-1:0] VAR88;
wire [VAR112-1:0] VAR77;
wire [VAR75-1:0] VAR65;
wire [VAR75-1:0] VAR101;
wire [VAR112-1:0] VAR93;
wire [VAR38-1:0] VAR103;
wire VAR128;
wire VAR17;
wire VAR49;
wire [VAR112-1:0] VAR3;
wire [VAR112-1:0] VAR37;
wire [VAR112-1:0] VAR39;
wire [VAR112-1:0] VAR44;
wire [VAR112-1:0] VAR69;
wire [VAR112-1:0] VAR96;
wire [VAR112-1:0] VAR98;
wire [VAR112-1:0] VAR41;
wire [VAR112-1:0] VAR111;
wire [VAR38-1:0] VAR84;
wire [VAR75-1:0] VAR6;
wire [VAR112-1:0] VAR127;
wire [VAR112-1:0] VAR42;
wire [VAR112-1:0] VAR58;
wire [VAR112-1:0] VAR56;
wire [VAR112-1:0] VAR126;
wire [VAR112-1:0] VAR26;
wire [VAR112-1:0] VAR2;
wire [VAR112-1:0] VAR110;
wire [VAR112-1:0] VAR29;
wire [VAR112-1:0] VAR90;
wire [VAR112-1:0] VAR48;
assign VAR81 = VAR103;
VAR13 #(.VAR112(VAR112)) VAR19 (
.VAR51(VAR5),
.VAR54(VAR48),
.VAR124(32'b00000000000000000000000000000000), .VAR129(VAR21)
);
VAR36 #(.VAR112(VAR112)) VAR116 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR27),
.VAR38(VAR29),
.VAR108(VAR119)
);
VAR36 #(.VAR112(VAR112)) VAR67 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR16),
.VAR38(VAR90),
.VAR108(VAR88)
);
VAR36 #(.VAR112(VAR112)) VAR91 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR4),
.VAR38(VAR21),
.VAR108(VAR77)
);
VAR36 #(.VAR112(VAR112)) VAR98 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR121),
.VAR38(VAR119),
.VAR108(VAR98)
);
VAR36 #(.VAR112(VAR112)) VAR41 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR121),
.VAR38(VAR88),
.VAR108(VAR41)
);
VAR36 #(.VAR112(VAR112)) VAR111 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR121),
.VAR38(VAR77),
.VAR108(VAR111)
);
VAR47 #(.VAR112(VAR38)) VAR24 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR30),
.VAR68(VAR103)
);
VAR78 #(.VAR112(VAR38)) VAR9 (
.VAR15(VAR15),
.VAR120(1'b1),
.VAR73(VAR103),
.VAR34(VAR84)
);
VAR125 #(.VAR112(VAR112),.VAR38(VAR38)) VAR80 ( .VAR15(VAR15),
.VAR120(1'b1),
.VAR73(VAR103),
.VAR34(VAR93)
);
VAR122 #(.VAR112(VAR75),.VAR89(5)) VAR31 (
.VAR82(VAR119[30:23]),
.VAR74(VAR84),
.VAR68(VAR65)
);
VAR122 #(.VAR112(VAR75),.VAR89(5)) VAR115 (
.VAR82(VAR88[30:23]),
.VAR74(VAR84),
.VAR68(VAR101)
);
VAR60 VAR35 (
.VAR43(VAR119[31]),
.VAR130(VAR88[31]),
.VAR102(VAR93[31]),
.VAR33(VAR128),
.VAR99(VAR17),
.VAR94(VAR49)
);
assign VAR3[31] = VAR17;
assign VAR3[30:23] = VAR101;
assign VAR3[22:0] = VAR88[22:0];
assign VAR37[31] = VAR128;
assign VAR37[30:23] = VAR65;
assign VAR37[22:0] = VAR119[22:0];
assign VAR39[31] = VAR49;
assign VAR39[30:0] = VAR93[30:0];
VAR36 #(.VAR112(VAR112)) VAR44 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR52),
.VAR38(VAR3),
.VAR108(VAR44)
);
VAR36 #(.VAR112(VAR112)) VAR69 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR52),
.VAR38(VAR37),
.VAR108(VAR69)
);
VAR36 #(.VAR112(VAR112)) VAR96 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR52),
.VAR38(VAR39),
.VAR108(VAR96)
);
VAR62 #(.VAR112(VAR75)) VAR104 ( .VAR82(VAR1[30:23]),
.VAR74(5'b00100),
.VAR68(VAR6)
);
assign VAR127 [31] = VAR1 [31];
assign VAR127[30:23] = VAR6;
assign VAR127[22:0] = VAR1[22:0];
VAR36 #(.VAR112(VAR112)) VAR42 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR123),
.VAR38(VAR127),
.VAR108(VAR42)
);
VAR13 #(.VAR112(VAR112)) VAR59 (
.VAR51(VAR107),
.VAR54(VAR98),
.VAR124(VAR42),
.VAR129(VAR58)
);
VAR13 #(.VAR112(VAR112)) VAR64 (
.VAR51(VAR107),
.VAR54(VAR44),
.VAR124(32'b00111111100000000000000000000000), .VAR129(VAR56)
);
VAR13 #(.VAR112(VAR112)) VAR57 (
.VAR51(VAR107),
.VAR54(VAR41),
.VAR124(VAR42),
.VAR129(VAR126)
);
VAR13 #(.VAR112(VAR112)) VAR8 (
.VAR51(VAR107),
.VAR54(VAR69),
.VAR124(32'b10111111100000000000000000000000), .VAR129(VAR26)
);
VAR13 #(.VAR112(VAR112)) VAR92 (
.VAR51(VAR7),
.VAR54(VAR111),
.VAR124(VAR77),
.VAR129(VAR2)
);
VAR13 #(.VAR112(VAR112)) VAR23 (
.VAR51(VAR7),
.VAR54(VAR96),
.VAR124(32'b11000000001100010111001000011000), .VAR129(VAR110)
);
VAR114 #(.VAR89(32),.VAR71(8),.VAR117(23),.VAR40(26), .VAR83(5)) VAR76(
.clk(VAR15),
.rst(VAR106),
.VAR85(VAR25),
.VAR72(VAR79),
.VAR10(VAR58),
.VAR46(VAR56),
.VAR53(VAR105),
.VAR66(2'b00),
.VAR50(VAR61),
.VAR14(VAR87),
.ready(VAR79),
.VAR86(VAR29)
);
VAR114 #(.VAR89(32),.VAR71(8),.VAR117(23),.VAR40(26), .VAR83(5)) VAR12(
.clk(VAR15),
.rst(VAR106),
.VAR85(VAR22),
.VAR72(VAR55),
.VAR10(VAR126),
.VAR46(VAR26),
.VAR53(VAR105),
.VAR66(2'b00),
.VAR50(VAR20),
.VAR14(VAR63),
.ready(VAR55),
.VAR86(VAR90)
);
VAR114 #(.VAR89(32),.VAR71(8),.VAR117(23),.VAR40(26), .VAR83(5)) VAR11(
.clk(VAR15),
.rst(VAR106),
.VAR85(VAR28),
.VAR72(VAR95),
.VAR10(VAR2),
.VAR46(VAR110),
.VAR53(VAR105),
.VAR66(2'b00),
.VAR50(VAR97),
.VAR14(VAR45),
.ready(VAR95),
.VAR86(VAR48)
);
VAR36 #(.VAR112(VAR112)) VAR70 (
.VAR15(VAR15),
.VAR106(VAR106),
.VAR113(VAR109),
.VAR38(VAR48),
.VAR108(VAR18)
);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dlrtn/sky130_fd_sc_hd__dlrtn.behavioral.v
| 2,404 |
module MODULE1 (
VAR12 ,
VAR7,
VAR22 ,
VAR20
);
output VAR12 ;
input VAR7;
input VAR22 ;
input VAR20 ;
supply1 VAR18;
supply0 VAR15;
supply1 VAR10 ;
supply0 VAR3 ;
wire VAR13 ;
wire VAR17 ;
reg VAR6 ;
wire VAR9 ;
wire VAR24 ;
wire VAR23 ;
wire VAR16;
wire VAR21 ;
wire VAR5 ;
wire VAR8 ;
wire VAR2 ;
not VAR4 (VAR13 , VAR16 );
not VAR1 (VAR17, VAR24 );
VAR14 VAR19 (VAR21 , VAR9, VAR17, VAR13, VAR6, VAR18, VAR15);
assign VAR5 = ( VAR18 === 1'b1 );
assign VAR8 = ( VAR5 && ( VAR16 === 1'b1 ) );
assign VAR2 = ( VAR5 && ( VAR7 === 1'b1 ) );
buf VAR11 (VAR12 , VAR21 );
endmodule
|
apache-2.0
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/cf_ddsv_intp.v
| 9,926 |
module MODULE1 (
VAR34,
VAR37,
VAR21,
VAR12,
VAR41,
VAR7,
VAR29,
VAR47,
VAR26,
VAR33,
VAR3,
VAR35,
VAR1,
VAR44,
VAR22,
VAR11,
VAR17,
VAR27,
VAR46,
VAR30);
input VAR34;
output VAR37;
input [95:0] VAR21;
output [13:0] VAR12;
output [13:0] VAR41;
output [13:0] VAR7;
output [13:0] VAR29;
output [13:0] VAR47;
output [13:0] VAR26;
output [13:0] VAR33;
output [13:0] VAR3;
output [13:0] VAR35;
output [13:0] VAR1;
output [13:0] VAR44;
output [13:0] VAR22;
input VAR11;
input [15:0] VAR17;
input [15:0] VAR27;
output [292:0] VAR46;
output [ 7:0] VAR30;
reg VAR15 = 'd0;
reg VAR45 = 'd0;
reg VAR40 = 'd0;
reg VAR8 = 'd0;
reg [15:0] VAR16 = 'd0;
reg [15:0] VAR24 = 'd0;
reg [ 2:0] VAR36 = 'd0;
reg VAR37 = 'd0;
reg [15:0] VAR39 = 'd0;
reg [15:0] VAR19 = 'd0;
reg [15:0] VAR14 = 'd0;
reg [15:0] VAR43 = 'd0;
reg [15:0] VAR4 = 'd0;
reg [15:0] VAR20 = 'd0;
reg [15:0] VAR32 = 'd0;
reg [15:0] VAR2 = 'd0;
reg [13:0] VAR12 = 'd0;
reg [13:0] VAR41 = 'd0;
reg [13:0] VAR7 = 'd0;
reg [13:0] VAR29 = 'd0;
reg [13:0] VAR47 = 'd0;
reg [13:0] VAR26 = 'd0;
reg [13:0] VAR33 = 'd0;
reg [13:0] VAR3 = 'd0;
reg [13:0] VAR35 = 'd0;
reg [13:0] VAR1 = 'd0;
reg [13:0] VAR44 = 'd0;
reg [13:0] VAR22 = 'd0;
wire [15:0] VAR31;
wire [15:0] VAR42;
wire [15:0] VAR28;
assign VAR30[7:5] = 'd0;
assign VAR30[4:4] = VAR8;
assign VAR30[3:3] = VAR37;
assign VAR30[2:0] = VAR36;
assign VAR46[292:292] = VAR8;
assign VAR46[291:291] = VAR37;
assign VAR46[290:288] = VAR36;
assign VAR46[287:272] = {VAR22, 2'd0};
assign VAR46[271:256] = {VAR44, 2'd0};
assign VAR46[255:240] = {VAR1, 2'd0};
assign VAR46[239:224] = {VAR35, 2'd0};
assign VAR46[223:208] = {VAR3, 2'd0};
assign VAR46[207:192] = {VAR33, 2'd0};
assign VAR46[191:176] = {VAR26, 2'd0};
assign VAR46[175:160] = {VAR47, 2'd0};
assign VAR46[159:144] = {VAR29, 2'd0};
assign VAR46[143:128] = {VAR7, 2'd0};
assign VAR46[127:112] = {VAR41, 2'd0};
assign VAR46[111: 96] = {VAR12, 2'd0};
assign VAR46[ 95: 0] = VAR21;
always @(posedge VAR34) begin
VAR15 <= VAR11;
VAR45 <= VAR15;
VAR40 <= VAR45;
VAR8 <= VAR40;
if ((VAR45 == 1'b1) && (VAR40 == 1'b0)) begin
VAR16 <= VAR17;
VAR24 <= VAR27;
end
end
always @(posedge VAR34) begin
if (VAR36 >= 3'b101) begin
VAR36 <= 3'b000;
VAR37 <= 1'b1;
end else begin
VAR36 <= VAR36 + 1'b1;
VAR37 <= ~VAR8;
end
if (VAR37 == 1'b1) begin
VAR39 <= VAR21[95:80];
VAR19 <= VAR21[79:64];
VAR14 <= VAR21[63:48];
VAR43 <= VAR21[47:32];
VAR4 <= VAR21[31:16];
VAR20 <= VAR21[15: 0];
end
end
always @(posedge VAR34) begin
case (VAR36)
3'b001: VAR32 <= VAR39;
3'b010: VAR32 <= VAR19;
3'b011: VAR32 <= VAR14;
3'b100: VAR32 <= VAR43;
3'b101: VAR32 <= VAR4;
default: VAR32 <= VAR20;
endcase
VAR2 <= VAR32;
end
always @(posedge VAR34) begin
if (VAR8 == 1'b1) begin
VAR12 <= {~VAR31[15], VAR31[14:2]};
VAR41 <= {~VAR31[15], VAR31[14:2]};
VAR7 <= {~VAR31[15], VAR31[14:2]};
VAR29 <= {~VAR31[15], VAR31[14:2]};
VAR47 <= {~VAR42[15], VAR42[14:2]};
VAR26 <= {~VAR42[15], VAR42[14:2]};
VAR33 <= {~VAR42[15], VAR42[14:2]};
VAR3 <= {~VAR42[15], VAR42[14:2]};
VAR35 <= {~VAR28[15], VAR28[14:2]};
VAR1 <= {~VAR28[15], VAR28[14:2]};
VAR44 <= {~VAR28[15], VAR28[14:2]};
VAR22 <= {~VAR28[15], VAR28[14:2]};
end else begin
VAR12 <= VAR39[15:2];
VAR41 <= VAR39[15:2];
VAR7 <= VAR19[15:2];
VAR29 <= VAR19[15:2];
VAR47 <= VAR14[15:2];
VAR26 <= VAR14[15:2];
VAR33 <= VAR43[15:2];
VAR3 <= VAR43[15:2];
VAR35 <= VAR4[15:2];
VAR1 <= VAR4[15:2];
VAR44 <= VAR20[15:2];
VAR22 <= VAR20[15:2];
end
end
VAR6 VAR23 (
.clk (VAR34),
.VAR18 (VAR2),
.VAR38 (VAR32),
.VAR25 (VAR16),
.VAR10 (VAR24),
.VAR13 (VAR31),
.VAR9 (VAR42));
VAR6 VAR5 (
.clk (VAR34),
.VAR18 (VAR2),
.VAR38 (VAR32),
.VAR25 (VAR24),
.VAR10 (VAR16),
.VAR13 (),
.VAR9 (VAR28));
endmodule
|
mit
|
vad-rulezz/megabot
|
fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_ddr3_odt_gen.v
| 17,824 |
module MODULE1
VAR1 = 2,
VAR5 = 1,
VAR31 = 4,
VAR43 = 4
)
(
VAR41,
VAR48,
VAR27,
VAR26,
VAR23,
VAR40,
VAR4,
VAR35,
VAR13,
VAR50,
VAR7,
VAR11
);
localparam integer VAR15 = 2**VAR31;
localparam integer VAR42 = 6; localparam integer VAR30 = 4; localparam integer VAR17 = VAR1 / 2;
input VAR41;
input VAR48;
input [VAR31-1:0] VAR27;
input [VAR43-1:0] VAR26;
input [VAR5-1:0] VAR23;
input VAR40;
input VAR4;
input VAR35;
output VAR13;
output VAR50;
output VAR7;
output VAR11;
wire VAR40;
reg VAR21;
reg VAR19;
reg VAR6;
reg VAR28;
reg VAR46;
wire [3:0] VAR52; reg [3:0] VAR18;
wire [3:0] VAR56;
reg [3:0] VAR38;
wire [3:0] VAR16;
reg [3:0] VAR20;
reg VAR39;
reg VAR10;
reg VAR2;
reg VAR12;
reg VAR8;
reg VAR24;
reg VAR3;
reg VAR51;
reg VAR33;
reg VAR44;
reg VAR45;
reg VAR47;
reg VAR29;
reg VAR49;
reg VAR36;
reg VAR54;
reg VAR57;
reg VAR53;
wire VAR13;
wire VAR50;
wire VAR7;
wire VAR11;
reg [3:0] VAR25;
reg [3:0] VAR37;
wire VAR34;
reg VAR55;
wire [3:0] VAR22;
wire [3:0] VAR14;
reg [VAR15 -1:0] VAR9;
reg [VAR15 -1:0] VAR32;
assign VAR52 = VAR27 - VAR26;
assign VAR56 = (VAR18 % VAR17);
assign VAR16 = (VAR18 / VAR17) + VAR39;
always @(posedge VAR41, negedge VAR48)
begin
if (!VAR48)
begin
VAR18 <= 0;
VAR38 <= 0;
VAR20 <= 0;
end
else
begin
VAR18 <= VAR52;
VAR38 <= VAR56;
VAR20 <= (VAR16 > 0) ? (VAR16 - 1'b1) : 0;
end
end
always @ (posedge VAR41 or negedge VAR48)
begin
if (!VAR48)
begin
VAR39 <= 1'b0;
VAR10 <= 1'b0;
VAR2 <= 1'b0;
VAR12 <= 1'b0;
end
else
begin
VAR39 <= |VAR38;
VAR10 <= (VAR38 == 1) ? 1'b1 : 1'b0;
VAR2 <= (VAR38 == 2) ? 1'b1 : 1'b0;
VAR12 <= (VAR38 == 3) ? 1'b1 : 1'b0;
end
end
always @
begin
if (VAR40 || VAR21)
begin
VAR51 = 1'b1;
end
else if (VAR25 > 0 || VAR37 > 0)
begin
VAR51 = 1'b1;
end
else
begin
VAR51 = 1'b0;
end
end
always @ (posedge VAR41 or negedge VAR48)
begin
if (~VAR48)
begin
VAR33 <= 1'b0;
end
else
begin
if (VAR21)
begin
VAR33 <= 1'b1;
end
else if ((VAR37 > 1 && ((VAR10 && VAR17 == 4) || VAR2)) || (VAR37 > 0 && ((VAR10 && VAR17 == 2) || VAR12)))
begin
VAR33 <= 1'b1;
end
else
begin
VAR33 <= 1'b0;
end
end
end
always @ (*)
begin
if (VAR39 & (VAR21|VAR55))
begin
VAR44 = VAR33;
end
else begin
VAR44 = VAR51;
end
end
always @ (posedge VAR41 or negedge VAR48)
begin
if (!VAR48)
begin
VAR8 <= 1'b0;
end
else
begin
if (VAR40 || (VAR21 && !VAR2 && !VAR12))
begin
VAR8 <= 1'b1;
end
else if (VAR25 > 0 || VAR37 > 0)
begin
VAR8 <= 1'b1;
end
else
begin
VAR8 <= 1'b0;
end
end
end
always @ (posedge VAR41 or negedge VAR48)
begin
if (!VAR48)
begin
VAR29 <= 1'b0;
end
else
begin
if (VAR40 || VAR21)
begin
VAR29 <= 1'b1;
end
else if (VAR25 > 1 || (VAR37 > 1 && !VAR39) || (VAR37 > 0 && VAR39))
begin
VAR29 <= 1'b1;
end
else
begin
VAR29 <= 1'b0;
end
end
end
always @ (posedge VAR41 or negedge VAR48)
begin
if (!VAR48)
begin
VAR49 <= 1'b0;
end
else
begin
if (VAR40 || VAR21)
begin
VAR49 <= 1'b1;
end
else if (VAR25 > 1 || (VAR37 > 1 && (!VAR39 || VAR10)) || (VAR37 > 0 && (VAR2 || VAR12)))
begin
VAR49 <= 1'b1;
end
else
begin
VAR49 <= 1'b0;
end
end
end
always @ (posedge VAR41 or negedge VAR48)
begin
if (!VAR48)
begin
VAR45 <= 1'b0;
VAR24 <= 1'b0;
VAR36 <= 1'b0;
VAR54 <= 1'b0;
VAR47 <= 1'b0;
VAR3 <= 1'b0;
VAR57 <= 1'b0;
VAR53 <= 1'b0;
end
else
begin
VAR45 <= VAR44;
VAR24 <= VAR8;
VAR36 <= VAR29;
VAR54 <= VAR49;
VAR47 <= VAR45;
VAR3 <= VAR24;
VAR57 <= VAR36;
VAR53 <= VAR54;
end
end
generate
if (VAR1 == 2) begin
assign VAR50 = (VAR23 == 2) ? VAR47 : ((VAR23 == 1) ? VAR45 : VAR44);
assign VAR13 = (VAR23 == 2) ? VAR47 : ((VAR23 == 1) ? VAR45 : VAR44);
assign VAR7 = 1'b0;
assign VAR11 = 1'b0;
end
else if (VAR1 == 4) begin
assign VAR50 = (VAR23 == 2) ? VAR47 : ((VAR23 == 1) ? VAR45 : VAR44);
assign VAR13 = (VAR23 == 2) ? VAR3 : ((VAR23 == 1) ? VAR24 : VAR8);
assign VAR7 = 1'b0;
assign VAR11 = 1'b0;
end
else if (VAR1 == 8) begin
assign VAR50 = (VAR23 == 2) ? VAR47 : ((VAR23 == 1) ? VAR45 : VAR44 );
assign VAR13 = (VAR23 == 2) ? VAR3 : ((VAR23 == 1) ? VAR24 : VAR8 );
assign VAR7 = (VAR23 == 2) ? VAR57 : ((VAR23 == 1) ? VAR36 : VAR29);
assign VAR11 = (VAR23 == 2) ? VAR53 : ((VAR23 == 1) ? VAR54 : VAR49);
end
endgenerate
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai.functional.v
| 1,578 |
module MODULE1 (
VAR10 ,
VAR12,
VAR8,
VAR3 ,
VAR11
);
output VAR10 ;
input VAR12;
input VAR8;
input VAR3 ;
input VAR11 ;
wire VAR9 ;
wire VAR1 ;
wire VAR5;
nand VAR2 (VAR9 , VAR8, VAR12 );
or VAR4 (VAR1 , VAR11, VAR3 );
nand VAR6 (VAR5, VAR9, VAR1);
buf VAR7 (VAR10 , VAR5 );
endmodule
|
apache-2.0
|
marco-c/leon-nexys2
|
grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_msel.v
| 9,501 |
module MODULE1(
VAR20, VAR22,
VAR12, req, sel, VAR21
);
parameter [1:0] VAR27 = 2'd0;
input VAR20, VAR22;
input [15:0] VAR12;
input [7:0] req;
output [2:0] sel;
input VAR21;
wire [1:0] VAR29, VAR2, VAR15, VAR10;
wire [1:0] VAR18, VAR24, VAR13, VAR31;
wire [1:0] VAR14;
reg [1:0] VAR6;
wire [7:0] VAR5, VAR16, VAR30, VAR32;
wire [2:0] VAR28, VAR3, VAR19, VAR4;
reg [2:0] VAR1, VAR9;
wire [2:0] sel;
assign VAR29[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[0];
assign VAR29[1] = (VAR27 == 2'd2) ? VAR12[1] : 1'b0;
assign VAR2[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[2];
assign VAR2[1] = (VAR27 == 2'd2) ? VAR12[3] : 1'b0;
assign VAR15[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[4];
assign VAR15[1] = (VAR27 == 2'd2) ? VAR12[5] : 1'b0;
assign VAR10[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[6];
assign VAR10[1] = (VAR27 == 2'd2) ? VAR12[7] : 1'b0;
assign VAR18[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[8];
assign VAR18[1] = (VAR27 == 2'd2) ? VAR12[9] : 1'b0;
assign VAR24[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[10];
assign VAR24[1] = (VAR27 == 2'd2) ? VAR12[11] : 1'b0;
assign VAR13[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[12];
assign VAR13[1] = (VAR27 == 2'd2) ? VAR12[13] : 1'b0;
assign VAR31[0] = (VAR27 == 2'd0) ? 1'b0 : VAR12[14];
assign VAR31[1] = (VAR27 == 2'd2) ? VAR12[15] : 1'b0;
VAR7 #(VAR27) VAR17(
.valid( req ),
.VAR29( VAR29 ),
.VAR2( VAR2 ),
.VAR15( VAR15 ),
.VAR10( VAR10 ),
.VAR18( VAR18 ),
.VAR24( VAR24 ),
.VAR13( VAR13 ),
.VAR31( VAR31 ),
.VAR6( VAR14 )
);
always @(posedge VAR20)
if(VAR22) VAR6 <= 2'h0;
else
if(VAR21) VAR6 <= VAR14;
assign VAR5[0] = req[0] & (VAR29 == 2'd0);
assign VAR5[1] = req[1] & (VAR2 == 2'd0);
assign VAR5[2] = req[2] & (VAR15 == 2'd0);
assign VAR5[3] = req[3] & (VAR10 == 2'd0);
assign VAR5[4] = req[4] & (VAR18 == 2'd0);
assign VAR5[5] = req[5] & (VAR24 == 2'd0);
assign VAR5[6] = req[6] & (VAR13 == 2'd0);
assign VAR5[7] = req[7] & (VAR31 == 2'd0);
assign VAR16[0] = req[0] & (VAR29 == 2'd1);
assign VAR16[1] = req[1] & (VAR2 == 2'd1);
assign VAR16[2] = req[2] & (VAR15 == 2'd1);
assign VAR16[3] = req[3] & (VAR10 == 2'd1);
assign VAR16[4] = req[4] & (VAR18 == 2'd1);
assign VAR16[5] = req[5] & (VAR24 == 2'd1);
assign VAR16[6] = req[6] & (VAR13 == 2'd1);
assign VAR16[7] = req[7] & (VAR31 == 2'd1);
assign VAR30[0] = req[0] & (VAR29 == 2'd2);
assign VAR30[1] = req[1] & (VAR2 == 2'd2);
assign VAR30[2] = req[2] & (VAR15 == 2'd2);
assign VAR30[3] = req[3] & (VAR10 == 2'd2);
assign VAR30[4] = req[4] & (VAR18 == 2'd2);
assign VAR30[5] = req[5] & (VAR24 == 2'd2);
assign VAR30[6] = req[6] & (VAR13 == 2'd2);
assign VAR30[7] = req[7] & (VAR31 == 2'd2);
assign VAR32[0] = req[0] & (VAR29 == 2'd3);
assign VAR32[1] = req[1] & (VAR2 == 2'd3);
assign VAR32[2] = req[2] & (VAR15 == 2'd3);
assign VAR32[3] = req[3] & (VAR10 == 2'd3);
assign VAR32[4] = req[4] & (VAR18 == 2'd3);
assign VAR32[5] = req[5] & (VAR24 == 2'd3);
assign VAR32[6] = req[6] & (VAR13 == 2'd3);
assign VAR32[7] = req[7] & (VAR31 == 2'd3);
VAR11 VAR8(
.clk( VAR20 ),
.rst( VAR22 ),
.req( VAR5 ),
.VAR33( VAR28 ),
.VAR21( 1'b0 )
);
VAR11 VAR25(
.clk( VAR20 ),
.rst( VAR22 ),
.req( VAR16 ),
.VAR33( VAR3 ),
.VAR21( 1'b0 )
);
VAR11 VAR26(
.clk( VAR20 ),
.rst( VAR22 ),
.req( VAR30 ),
.VAR33( VAR19 ),
.VAR21( 1'b0 )
);
VAR11 VAR23(
.clk( VAR20 ),
.rst( VAR22 ),
.req( VAR32 ),
.VAR33( VAR4 ),
.VAR21( 1'b0 )
);
always @(VAR6 or VAR28 or VAR3)
if(VAR6[0]) VAR1 = VAR3;
else VAR1 = VAR28;
always @(VAR6 or VAR28 or VAR3 or VAR19 or VAR4)
case(VAR6)
2'd0: VAR9 = VAR28;
2'd1: VAR9 = VAR3;
2'd2: VAR9 = VAR19;
2'd3: VAR9 = VAR4;
endcase
assign sel = (VAR27==2'd0) ? VAR28 : ( (VAR27==2'd1) ? VAR1 : VAR9 );
endmodule
|
gpl-2.0
|
GLADICOS/SPACEWIRESYSTEMC
|
altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_pll_0.v
| 2,073 |
module MODULE1(
input wire VAR36,
input wire rst,
output wire VAR64,
output wire VAR50
);
VAR2 #(
.VAR49("false"),
.VAR25("100.0 VAR17"),
.VAR21("VAR61"),
.VAR69(1),
.VAR10("100.000000 VAR17"),
.VAR58("0 VAR28"),
.VAR31(50),
.VAR72("0 VAR17"),
.VAR68("0 VAR28"),
.VAR65(50),
.VAR42("0 VAR17"),
.VAR55("0 VAR28"),
.VAR16(50),
.VAR41("0 VAR17"),
.VAR33("0 VAR28"),
.VAR34(50),
.VAR71("0 VAR17"),
.VAR56("0 VAR28"),
.VAR32(50),
.VAR5("0 VAR17"),
.VAR46("0 VAR28"),
.VAR51(50),
.VAR37("0 VAR17"),
.VAR30("0 VAR28"),
.VAR70(50),
.VAR19("0 VAR17"),
.VAR57("0 VAR28"),
.VAR11(50),
.VAR24("0 VAR17"),
.VAR14("0 VAR28"),
.VAR27(50),
.VAR3("0 VAR17"),
.VAR9("0 VAR28"),
.VAR13(50),
.VAR35("0 VAR17"),
.VAR23("0 VAR28"),
.VAR44(50),
.VAR67("0 VAR17"),
.VAR43("0 VAR28"),
.VAR63(50),
.VAR38("0 VAR17"),
.VAR53("0 VAR28"),
.VAR15(50),
.VAR8("0 VAR17"),
.VAR39("0 VAR28"),
.VAR40(50),
.VAR52("0 VAR17"),
.VAR1("0 VAR28"),
.VAR60(50),
.VAR22("0 VAR17"),
.VAR45("0 VAR28"),
.VAR62(50),
.VAR29("0 VAR17"),
.VAR6("0 VAR28"),
.VAR7(50),
.VAR47("0 VAR17"),
.VAR48("0 VAR28"),
.VAR20(50),
.VAR54("VAR12"),
.VAR4("VAR12")
) VAR59 (
.rst (rst),
.VAR26 ({VAR64}),
.VAR50 (VAR50),
.VAR66 ( ),
.VAR18 (1'b0),
.VAR36 (VAR36)
);
endmodule
|
gpl-3.0
|
walkthetalk/fsref
|
ip/step_motor/src/step_motor.v
| 28,405 |
module MODULE1 #(
parameter integer VAR211 = 0,
parameter integer VAR378 = 16,
parameter integer VAR394 = 16,
parameter integer VAR292 = 9,
parameter integer VAR200 = 3,
parameter integer VAR1 = 32, parameter integer VAR253 = 4,
parameter integer VAR154 = 32'hFFFFFFFF,
parameter integer VAR7 = 32'h0
)(
input clk,
input VAR101,
input wire VAR8,
input wire VAR43,
input wire [VAR394-1:0] VAR356,
output wire [VAR292:0] VAR387,
input wire VAR103, output wire VAR188,
output wire VAR174,
output wire [VAR200-1:0] VAR331,
output wire VAR229,
output wire VAR307,
input wire VAR344,
input wire VAR323,
input wire signed [VAR378-1:0] VAR22,
input wire signed [VAR378-1:0] VAR31,
input wire [VAR200-1:0] VAR376,
output wire VAR3,
output wire VAR362,
output wire VAR276,
output wire VAR65,
output wire [VAR394-1:0] VAR255,
output wire VAR410,
output wire signed [VAR378-1:0] VAR385,
input wire VAR432,
input wire VAR205,
input wire [VAR394-1:0] VAR28,
input wire signed [VAR378-1:0] VAR338,
input wire VAR399,
input wire VAR341,
output wire VAR330,
output wire VAR110,
output wire VAR214,
output wire VAR407,
output wire [VAR394-1:0] VAR220,
output wire VAR436,
output wire signed [VAR378-1:0] VAR83,
input wire VAR137,
input wire VAR234,
input wire [VAR394-1:0] VAR303,
input wire signed [VAR378-1:0] VAR170,
input wire VAR222,
input wire VAR329,
input wire signed [VAR378-1:0] VAR364,
input wire VAR300, output wire VAR175,
output wire VAR133,
output wire [VAR200-1:0] VAR217,
output wire VAR37,
output wire VAR266,
input wire VAR197,
input wire VAR384,
input wire signed [VAR378-1:0] VAR420,
input wire signed [VAR378-1:0] VAR6,
input wire [VAR200-1:0] VAR117,
output wire VAR165,
output wire VAR164,
output wire VAR391,
output wire VAR289,
output wire [VAR394-1:0] VAR42,
output wire VAR249,
output wire signed [VAR378-1:0] VAR450,
input wire VAR311,
input wire VAR47,
input wire [VAR394-1:0] VAR216,
input wire signed [VAR378-1:0] VAR367,
input wire VAR19,
input wire VAR156,
output wire VAR178,
output wire VAR277,
output wire VAR271,
output wire VAR120,
output wire [VAR394-1:0] VAR123,
output wire VAR233,
output wire signed [VAR378-1:0] VAR146,
input wire VAR355,
input wire VAR92,
input wire [VAR394-1:0] VAR442,
input wire signed [VAR378-1:0] VAR221,
input wire VAR203,
input wire VAR343,
input wire signed [VAR378-1:0] VAR235,
input wire VAR245, output wire VAR278,
output wire VAR76,
output wire [VAR200-1:0] VAR419,
output wire VAR301,
output wire VAR438,
input wire VAR269,
input wire VAR30,
input wire signed [VAR378-1:0] VAR184,
input wire signed [VAR378-1:0] VAR325,
input wire [VAR200-1:0] VAR116,
output wire VAR153,
output wire VAR27,
output wire VAR151,
output wire VAR105,
output wire [VAR394-1:0] VAR176,
output wire VAR148,
output wire signed [VAR378-1:0] VAR121,
input wire VAR35,
input wire VAR59,
input wire [VAR394-1:0] VAR259,
input wire signed [VAR378-1:0] VAR339,
input wire VAR201,
input wire VAR247,
output wire VAR408,
output wire VAR58,
output wire VAR404,
output wire VAR102,
output wire [VAR394-1:0] VAR91,
output wire VAR11,
output wire signed [VAR378-1:0] VAR135,
input wire VAR318,
input wire VAR52,
input wire [VAR394-1:0] VAR348,
input wire signed [VAR378-1:0] VAR396,
input wire VAR75,
input wire VAR334,
input wire signed [VAR378-1:0] VAR258,
input wire VAR24, output wire VAR140,
output wire VAR287,
output wire [VAR200-1:0] VAR371,
output wire VAR172,
output wire VAR219,
input wire VAR108,
input wire VAR191,
input wire signed [VAR378-1:0] VAR409,
input wire signed [VAR378-1:0] VAR377,
input wire [VAR200-1:0] VAR124,
output wire VAR134,
output wire VAR17,
output wire VAR429,
output wire VAR185,
output wire [VAR394-1:0] VAR265,
output wire VAR115,
output wire signed [VAR378-1:0] VAR321,
input wire VAR109,
input wire VAR264,
input wire [VAR394-1:0] VAR241,
input wire signed [VAR378-1:0] VAR400,
input wire VAR413,
input wire VAR365,
output wire VAR423,
output wire VAR182,
output wire VAR144,
output wire VAR128,
output wire [VAR394-1:0] VAR280,
output wire VAR129,
output wire signed [VAR378-1:0] VAR62,
input wire VAR223,
input wire VAR177,
input wire [VAR394-1:0] VAR149,
input wire signed [VAR378-1:0] VAR328,
input wire VAR347,
input wire VAR106,
input wire signed [VAR378-1:0] VAR187,
input wire VAR85, output wire VAR158,
output wire VAR173,
output wire [VAR200-1:0] VAR96,
output wire VAR401,
output wire VAR446,
input wire VAR352,
input wire VAR366,
input wire signed [VAR378-1:0] VAR125,
input wire signed [VAR378-1:0] VAR68,
input wire [VAR200-1:0] VAR406,
output wire VAR421,
output wire VAR368,
output wire VAR263,
output wire VAR337,
output wire [VAR394-1:0] VAR98,
output wire VAR44,
output wire signed [VAR378-1:0] VAR50,
input wire VAR114,
input wire VAR51,
input wire [VAR394-1:0] VAR267,
input wire signed [VAR378-1:0] VAR126,
input wire VAR437,
input wire VAR296,
output wire VAR166,
output wire VAR155,
output wire VAR248,
output wire VAR412,
output wire [VAR394-1:0] VAR79,
output wire VAR375,
output wire signed [VAR378-1:0] VAR324,
input wire VAR70,
input wire VAR449,
input wire [VAR394-1:0] VAR192,
input wire signed [VAR378-1:0] VAR12,
input wire VAR427,
input wire VAR13,
input wire signed [VAR378-1:0] VAR302,
input wire VAR262, output wire VAR395,
output wire VAR336,
output wire [VAR200-1:0] VAR95,
output wire VAR99,
output wire VAR304,
input wire VAR86,
input wire VAR314,
input wire signed [VAR378-1:0] VAR298,
input wire signed [VAR378-1:0] VAR82,
input wire [VAR200-1:0] VAR393,
output wire VAR360,
output wire VAR119,
output wire VAR40,
output wire VAR127,
output wire [VAR394-1:0] VAR317,
output wire VAR382,
output wire signed [VAR378-1:0] VAR434,
input wire VAR441,
input wire VAR209,
input wire [VAR394-1:0] VAR168,
input wire signed [VAR378-1:0] VAR361,
input wire VAR33,
input wire VAR390,
output wire VAR389,
output wire VAR150,
output wire VAR73,
output wire VAR167,
output wire [VAR394-1:0] VAR20,
output wire VAR418,
output wire signed [VAR378-1:0] VAR239,
input wire VAR25,
input wire VAR122,
input wire [VAR394-1:0] VAR312,
input wire signed [VAR378-1:0] VAR161,
input wire VAR430,
input wire VAR77,
input wire signed [VAR378-1:0] VAR426,
input wire VAR181, output wire VAR291,
output wire VAR81,
output wire [VAR200-1:0] VAR39,
output wire VAR118,
output wire VAR138,
input wire VAR309,
input wire VAR130,
input wire signed [VAR378-1:0] VAR87,
input wire signed [VAR378-1:0] VAR204,
input wire [VAR200-1:0] VAR297,
output wire VAR286,
output wire VAR5,
output wire VAR349,
output wire VAR84,
output wire [VAR394-1:0] VAR327,
output wire VAR260,
output wire signed [VAR378-1:0] VAR354,
input wire VAR160,
input wire VAR41,
input wire [VAR394-1:0] VAR4,
input wire signed [VAR378-1:0] VAR190,
input wire VAR132,
input wire VAR29,
output wire VAR64,
output wire VAR206,
output wire VAR414,
output wire VAR411,
output wire [VAR394-1:0] VAR243,
output wire VAR345,
output wire signed [VAR378-1:0] VAR305,
input wire VAR159,
input wire VAR111,
input wire [VAR394-1:0] VAR252,
input wire signed [VAR378-1:0] VAR369,
input wire VAR94,
input wire VAR261,
input wire signed [VAR378-1:0] VAR244,
input wire VAR195, output wire VAR48,
output wire VAR55,
output wire [VAR200-1:0] VAR342,
output wire VAR57,
output wire VAR275,
input wire VAR282,
input wire VAR435,
input wire signed [VAR378-1:0] VAR443,
input wire signed [VAR378-1:0] VAR333,
input wire [VAR200-1:0] VAR163,
output wire VAR340,
output wire VAR306,
output wire VAR142,
output wire VAR444,
output wire [VAR394-1:0] VAR112,
output wire VAR26,
output wire signed [VAR378-1:0] VAR104,
input wire VAR215,
input wire VAR113,
input wire [VAR394-1:0] VAR417,
input wire signed [VAR378-1:0] VAR268,
input wire VAR294,
input wire VAR23,
output wire VAR447,
output wire VAR60,
output wire VAR383,
output wire VAR78,
output wire [VAR394-1:0] VAR213,
output wire VAR326,
output wire signed [VAR378-1:0] VAR186,
input wire VAR171,
input wire VAR226,
input wire [VAR394-1:0] VAR350,
input wire signed [VAR378-1:0] VAR273,
input wire VAR80,
input wire VAR374,
input wire signed [VAR378-1:0] VAR335,
output [31:0] VAR97,
output [31:0] VAR370,
output [31:0] VAR285,
output [31:0] VAR145
);
function integer VAR363(input integer VAR224);
for(VAR363=0; VAR224>0; VAR363=VAR363+1) begin
VAR224 = VAR224>>1;
end
endfunction
function integer VAR403(input integer VAR319, input integer VAR237);
VAR403 = VAR237 * VAR319;
endfunction
function integer VAR218(input integer VAR319, input integer VAR237);
VAR218 = VAR237 * (VAR319+1) - 1;
endfunction
reg [VAR292-1:0] VAR179;
wire [VAR394-1:0] VAR227;
reg [VAR292-1:0] VAR15;
wire [VAR394-1:0] VAR34;
wire VAR359;
assign VAR359 = VAR8 && VAR43;
assign VAR387 = (2**VAR292);
reg [VAR292-1 : 0] VAR2;
reg [VAR292-1 : 0] VAR372;
wire [VAR292-1 : 0] VAR424;
assign VAR424 = VAR372;
VAR236 #(
.VAR88(VAR394),
.VAR199(VAR292)
) VAR18 (
.clk(clk),
.VAR380(VAR359),
.VAR180(VAR359 ? VAR2 : VAR179),
.VAR250(VAR356),
.VAR225(VAR227),
.VAR143(1'b0),
.VAR193({VAR394{1'b0}}),
.VAR373(VAR15),
.VAR425(VAR34)
);
always @ (posedge clk) begin
if (VAR101 == 1'b0) begin
VAR2 <= 0;
VAR372 <= 0;
end
else if (~VAR8)
VAR2 <= 0;
end
else if (VAR43) begin
VAR2 <= VAR2 + 1;
VAR372 <= VAR2;
end
end
reg [VAR1-1:0] VAR232;
always @ (posedge clk) begin
if (VAR101 == 1'b0) begin
VAR232 <= 1;
end
else begin
VAR232 <= {VAR232[VAR1-2:0], VAR232[VAR1-1]};
end
end
wire [VAR253-1:0] VAR32;
wire [VAR253-1:0] VAR274;
wire [VAR292-1:0] VAR254[VAR253-1:0];
wire [VAR292-1:0] VAR196[VAR253-1:0];
wire [VAR253-1:0] VAR381[VAR292-1:0];
wire [VAR253-1:0] VAR445[VAR292-1:0];
generate
genvar VAR319, VAR74;
for (VAR74=0; VAR74 < VAR253; VAR74 = VAR74 + 1) begin: VAR422
for (VAR319=0; VAR319 < VAR292; VAR319 = VAR319 + 1) begin: VAR90
assign VAR381[VAR319][VAR74] = VAR254[VAR74][VAR319];
assign VAR445[VAR319][VAR74] = VAR196[VAR74][VAR319];
end
end
for (VAR319 = 0; VAR319 < VAR292; VAR319 = VAR319+1) begin: VAR9
always @ (posedge clk) begin
VAR179[VAR319] <= ((VAR32 & VAR381[VAR319]) != 0);
VAR15[VAR319] <= ((VAR274 & VAR445[VAR319]) != 0);
end
end
endgenerate
wire VAR139 [VAR253-1:0];
wire VAR36 [VAR253-1:0];
wire VAR299 [VAR253-1:0];
wire [VAR200-1:0] VAR388 [VAR253-1:0];
wire VAR157 [VAR253-1:0];
wire VAR63 [VAR253-1:0];
wire VAR251 [VAR253-1:0];
wire VAR416 [VAR253-1:0];
wire signed [VAR378-1:0] VAR53 [VAR253-1:0];
wire signed [VAR378-1:0] VAR431 [VAR253-1:0];
wire [VAR200-1:0] VAR49 [VAR253-1:0];
wire VAR228 [VAR253-1:0];
wire VAR351 [VAR253-1:0];
wire VAR270 [VAR253-1:0];
wire VAR290 [VAR253-1:0];
wire [VAR394-1:0] VAR69 [VAR253-1:0];
wire VAR392 [VAR253-1:0];
wire signed [VAR378-1:0] VAR313 [VAR253-1:0];
wire VAR240 [VAR253-1:0];
wire VAR293 [VAR253-1:0];
wire [VAR394-1:0] VAR183 [VAR253-1:0];
wire signed [VAR378-1:0] VAR147 [VAR253-1:0];
wire VAR71 [VAR253-1:0];
wire VAR433 [VAR253-1:0];
wire VAR379 [VAR253-1:0];
wire VAR107 [VAR253-1:0];
wire VAR56 [VAR253-1:0];
wire VAR38 [VAR253-1:0];
wire [VAR394-1:0] VAR402 [VAR253-1:0];
wire VAR316 [VAR253-1:0];
wire signed [VAR378-1:0] VAR21 [VAR253-1:0];
wire VAR46 [VAR253-1:0];
wire VAR288 [VAR253-1:0];
wire [VAR394-1:0] VAR61 [VAR253-1:0];
wire signed [VAR378-1:0] VAR100 [VAR253-1:0];
wire VAR230 [VAR253-1:0];
wire VAR10[VAR253-1:0];
wire signed [VAR378-1:0] VAR212[VAR253-1:0];
if (VAR253 > VAR319) begin \
end \
else begin \
end
generate
endgenerate
wire [31:0] VAR405[VAR253-1:0];
wire [31:0] VAR283[VAR253-1:0];
wire [31:0] VAR136[VAR253-1:0];
wire [31:0] VAR202[VAR253-1:0];
assign VAR97 = VAR405[0];
assign VAR370 = VAR283[0];
assign VAR285 = VAR136[0];
assign VAR145 = VAR202[0];
generate
for (VAR319 = 0; VAR319 < VAR253; VAR319 = VAR319+1) begin: VAR448
VAR67 #(
.VAR211(VAR211),
.VAR378(VAR378),
.VAR394(VAR394),
.VAR292(VAR292),
.VAR200(VAR200),
.VAR284((VAR154 >> VAR319) & 1),
.VAR194((VAR7 >> VAR319) & 1)
) VAR439 (
.clk(clk),
.VAR101(VAR101),
.VAR232(VAR232[VAR319]),
.VAR372(VAR372),
.VAR424(VAR424),
.VAR93(VAR32[VAR319]),
.VAR189(VAR254[VAR319]),
.VAR207(VAR227),
.VAR308(VAR274[VAR319]),
.VAR14(VAR196[VAR319]),
.VAR89(VAR34),
.VAR272(VAR139[VAR319]), .VAR440(VAR36[VAR319]),
.VAR428(VAR299[VAR319]),
.VAR357(VAR388[VAR319]),
.VAR281(VAR157[VAR319]),
.VAR256(VAR63[VAR319]),
.VAR257 (VAR251[VAR319] ),
.VAR358 (VAR416[VAR319] ),
.VAR169(VAR53[VAR319]),
.VAR16(VAR431[VAR319]),
.VAR198 (VAR49[VAR319] ),
.VAR315 (VAR228 [VAR319]),
.VAR398 (VAR351 [VAR319]),
.VAR322 (VAR270 [VAR319]),
.VAR242 (VAR290 [VAR319]),
.VAR279(VAR69[VAR319]),
.VAR332 (VAR392 [VAR319]),
.VAR72(VAR313[VAR319]),
.VAR152 (VAR240 [VAR319]),
.VAR141 (VAR293 [VAR319]),
.VAR54 (VAR183 [VAR319]),
.VAR231 (VAR147 [VAR319]),
.VAR397 (VAR71 [VAR319]),
.VAR346 (VAR433 [VAR319]),
.VAR295 (VAR379 [VAR319]),
.VAR66 (VAR107 [VAR319]),
.VAR238 (VAR56 [VAR319]),
.VAR415 (VAR38 [VAR319]),
.VAR386(VAR402[VAR319]),
.VAR45 (VAR316 [VAR319]),
.VAR353(VAR21[VAR319]),
.VAR208 (VAR46 [VAR319]),
.VAR162 (VAR288 [VAR319]),
.VAR131 (VAR61 [VAR319]),
.VAR246 (VAR100 [VAR319]),
.VAR210 (VAR230 [VAR319]),
.VAR320(VAR10[VAR319]),
.VAR310(VAR212[VAR319]),
.VAR97(VAR405[VAR319]),
.VAR370(VAR283[VAR319]),
.VAR285(VAR136[VAR319]),
.VAR145(VAR202[VAR319])
);
end endgenerate
endmodule
|
gpl-3.0
|
merckhung/zet
|
cores/speaker/wm8731/speaker_iface.v
| 4,122 |
module MODULE1
(
input VAR6,
input VAR2,
input signed [15:0] VAR13,
input signed [15:0] VAR1,
output reg signed [15:0] VAR10,
output reg signed [15:0] VAR5,
output reg VAR3,
input VAR12,
input VAR18,
output reg VAR19,
input VAR11
);
reg VAR17;
reg VAR7;
reg VAR16;
reg VAR15;
reg VAR14;
reg VAR9;
reg [15:0] VAR8;
reg [15:0] VAR20;
reg VAR4;
always @(posedge VAR6 or posedge VAR2)
begin
if (VAR2)
begin
VAR17 <= 1'b0;
VAR7 <= 1'b0;
VAR16 <= 1'b0;
VAR15 <= 1'b0;
end
else
begin
VAR16 <= VAR12;
VAR15 <= VAR16;
if ((VAR16 == VAR15) && (VAR7 != VAR15))
begin
VAR7 <= VAR15;
if (VAR7 == 1'b1)
VAR17 <= 1'b1; end
if (VAR17)
VAR17 <= 1'b0; end
end
always @(posedge VAR6)
VAR9 <= VAR18;
always @(posedge VAR6)
begin
if (VAR17)
begin
VAR14 <= VAR9;
if (VAR9 != VAR14)
begin
VAR8 <= (VAR9) ? VAR1 : VAR13;
VAR19 <= 1'b0;
if (VAR9)
VAR10 <= VAR20;
end
else
VAR5 <= VAR20;
VAR20 <= 16'h0001;
VAR4 <= 1'b0;
VAR3 <= ~VAR9;
end
else
begin
{ VAR19, VAR8 } <= { VAR8, 1'b0 };
if (!VAR4)
{ VAR4, VAR20} <= { VAR20, VAR11 };
end
end
else if (VAR3)
VAR3 <= 1'b0; end
endmodule
|
gpl-3.0
|
kyzhai/NUNY
|
src/hardware/one_new2_bb.v
| 5,008 |
module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule
|
gpl-2.0
|
545/Atari7800
|
core/ag_6502/trunk/juke-box/ag_main.v
| 7,316 |
module MODULE1(input VAR1, input[10:0] VAR7, input VAR9, input VAR4, output[7:0] VAR5, input[7:0] VAR6);
reg[7:0] VAR2[0:2047];
reg[7:0] VAR8;
assign VAR5 = VAR9? VAR8: 8'VAR3;
|
gpl-2.0
|
azonenberg/antikernel-ipcores
|
noc/rpcv3/RPCv3Transceiver.v
| 16,445 |
module MODULE1
parameter VAR30 = 32,
parameter VAR23 = 1,
parameter VAR17 = 16'h8000,
parameter VAR1 = 1
) (
input wire clk,
output reg VAR8,
output reg[VAR30-1:0] VAR25,
input wire VAR10,
input wire VAR4,
input wire[VAR30-1:0] VAR3,
output reg VAR29,
input wire VAR2,
output reg VAR6,
input wire[15:0] VAR11,
input wire[15:0] VAR13,
input wire[7:0] VAR14,
input wire[2:0] VAR12,
input wire[20:0] VAR5,
input wire[31:0] VAR22,
input wire[31:0] VAR19,
output reg VAR20,
input wire VAR9,
output reg VAR27,
output reg VAR24 = 0,
output reg[15:0] VAR21 = 0,
output reg[15:0] VAR18 = 0,
output reg[7:0] VAR28 = 0,
output reg[2:0] VAR26 = 0,
output reg[20:0] VAR7 = 0,
output reg[31:0] VAR16 = 0,
output reg[31:0] VAR15 = 0
);
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/nor3/sky130_fd_sc_hd__nor3.pp.symbol.v
| 1,314 |
module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR2 ,
output VAR3 ,
input VAR1 ,
input VAR5,
input VAR7,
input VAR4
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/tap/sky130_fd_sc_hdll__tap.pp.blackbox.v
| 1,223 |
module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21boi/sky130_fd_sc_hdll__a21boi.blackbox.v
| 1,400 |
module MODULE1 (
VAR2 ,
VAR3 ,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR1;
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.behavioral.pp.v
| 3,372 |
module MODULE1( VAR4, VAR2, VAR5, VAR10, VAR11, VAR6, VAR3, VAR7 );
input VAR11, VAR6, VAR2, VAR5, VAR10;
inout VAR3, VAR7;
output VAR4;
VAR9 VAR1(.VAR4(VAR4),.VAR2(VAR2),.VAR5(VAR5),.VAR10(VAR10),.VAR11(VAR11),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7));
VAR9 VAR8(.VAR4(VAR4),.VAR2(VAR2),.VAR5(VAR5),.VAR10(VAR10),.VAR11(VAR11),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7));
|
apache-2.0
|
alexforencich/xfcp
|
example/S10MX_DK/fpga/rtl/fpga_core.v
| 17,214 |
module MODULE1
(
input wire clk,
input wire rst,
output wire [3:0] VAR178,
input wire VAR258,
input wire VAR158,
output wire [63:0] VAR229,
output wire [7:0] VAR255,
input wire VAR261,
input wire VAR124,
input wire [63:0] VAR205,
input wire [7:0] VAR3,
input wire VAR20,
input wire VAR95,
output wire [63:0] VAR37,
output wire [7:0] VAR279,
input wire VAR221,
input wire VAR32,
input wire [63:0] VAR8,
input wire [7:0] VAR99,
input wire VAR91,
input wire VAR185,
output wire [63:0] VAR162,
output wire [7:0] VAR262,
input wire VAR216,
input wire VAR254,
input wire [63:0] VAR46,
input wire [7:0] VAR167,
input wire VAR88,
input wire VAR93,
output wire [63:0] VAR159,
output wire [7:0] VAR220,
input wire VAR114,
input wire VAR156,
input wire [63:0] VAR223,
input wire [7:0] VAR33,
input wire VAR36,
input wire VAR175,
output wire [63:0] VAR246,
output wire [7:0] VAR242,
input wire VAR187,
input wire VAR139,
input wire [63:0] VAR123,
input wire [7:0] VAR138,
input wire VAR135,
input wire VAR201,
output wire [63:0] VAR151,
output wire [7:0] VAR189,
input wire VAR39,
input wire VAR144,
input wire [63:0] VAR152,
input wire [7:0] VAR141,
input wire VAR177,
input wire VAR113,
output wire [63:0] VAR89,
output wire [7:0] VAR271,
input wire VAR44,
input wire VAR171,
input wire [63:0] VAR278,
input wire [7:0] VAR122,
input wire VAR98,
input wire VAR38,
output wire [63:0] VAR231,
output wire [7:0] VAR55,
input wire VAR69,
input wire VAR238,
input wire [63:0] VAR233,
input wire [7:0] VAR249
);
wire [7:0] VAR70;
wire VAR190;
wire VAR92;
wire VAR54;
wire VAR17;
wire [7:0] VAR59;
wire VAR57;
wire VAR77;
wire VAR218;
wire VAR78;
wire [7:0] VAR140;
wire VAR25;
wire VAR212;
wire VAR195;
wire VAR232;
wire [7:0] VAR228;
wire VAR270;
wire VAR146;
wire VAR209;
wire VAR133;
wire [47:0] VAR219 = 48'h020000000000;
wire [31:0] VAR76 = {8'd192, 8'd168, 8'd1, 8'd128};
wire [15:0] VAR191 = 16'd14000;
wire [31:0] VAR198 = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] VAR16 = {8'd255, 8'd255, 8'd255, 8'd0};
assign VAR178 = 0;
VAR2 #(
.VAR222(8),
.VAR110(0),
.VAR40(1),
.VAR186(1),
.VAR267(1),
.VAR269(64),
.VAR169(4096),
.VAR161(1),
.VAR19(4096),
.VAR126(1)
)
VAR86 (
.VAR206(VAR261),
.VAR18(VAR124),
.VAR115(VAR258),
.VAR179(VAR158),
.VAR26(clk),
.VAR35(rst),
.VAR132(VAR228),
.VAR11(1'b1),
.VAR109(VAR270),
.VAR102(VAR146),
.VAR239(VAR209),
.VAR164(VAR133),
.VAR243(VAR140),
.VAR60(),
.VAR90(VAR25),
.VAR174(VAR212),
.VAR281(VAR195),
.VAR52(VAR232),
.VAR28(VAR205),
.VAR111(VAR3),
.VAR154(VAR229),
.VAR244(VAR255),
.VAR106(),
.VAR259(),
.VAR21(),
.VAR130(),
.VAR166(),
.VAR210(),
.VAR68(),
.VAR211(),
.VAR117(8'd12)
);
VAR217
VAR41 (
.clk(clk),
.rst(rst),
.VAR118(VAR140),
.VAR188(VAR25),
.VAR51(VAR212),
.VAR24(VAR195),
.VAR236(VAR232),
.VAR208(VAR228),
.VAR263(VAR270),
.VAR252(VAR146),
.VAR101(VAR209),
.VAR128(VAR133),
.VAR119(VAR59),
.VAR235(VAR57),
.VAR85(VAR77),
.VAR53(VAR218),
.VAR83(VAR78),
.VAR1(VAR70),
.VAR7(VAR190),
.VAR226(VAR92),
.VAR74(VAR54),
.VAR170(VAR17),
.VAR219(VAR219),
.VAR76(VAR76),
.VAR191(VAR191),
.VAR198(VAR198),
.VAR16(VAR16)
);
wire [7:0] VAR6;
wire VAR194;
wire VAR165;
wire VAR23;
wire VAR183;
wire [7:0] VAR155;
wire VAR56;
wire VAR163;
wire VAR82;
wire VAR272;
wire [7:0] VAR149;
wire VAR127;
wire VAR94;
wire VAR240;
wire VAR73;
wire [7:0] VAR62;
wire VAR215;
wire VAR43;
wire VAR125;
wire VAR225;
wire [7:0] VAR234;
wire VAR193;
wire VAR66;
wire VAR213;
wire VAR248;
wire [7:0] VAR80;
wire VAR84;
wire VAR168;
wire VAR202;
wire VAR108;
wire [7:0] VAR72;
wire VAR253;
wire VAR247;
wire VAR283;
wire VAR157;
wire [7:0] VAR203;
wire VAR27;
wire VAR176;
wire VAR148;
wire VAR58;
VAR237 #(
.VAR181(4),
.VAR49(16'h0100),
.VAR81("VAR129 VAR134"),
.VAR107(0),
.VAR120("VAR227 VAR97")
)
VAR34 (
.clk(clk),
.rst(rst),
.VAR224(VAR70),
.VAR116(VAR190),
.VAR214(VAR92),
.VAR13(VAR54),
.VAR150(VAR17),
.VAR64(VAR59),
.VAR30(VAR57),
.VAR245(VAR77),
.VAR277(VAR218),
.VAR143(VAR78),
.VAR119( {VAR203, VAR80, VAR62, VAR155 }),
.VAR235( {VAR27, VAR84, VAR215, VAR56 }),
.VAR85( {VAR176, VAR168, VAR43, VAR163 }),
.VAR53( {VAR148, VAR202, VAR125, VAR82 }),
.VAR83( {VAR58, VAR108, VAR225, VAR272 }),
.VAR1( {VAR72, VAR234, VAR149, VAR6 }),
.VAR7({VAR253, VAR193, VAR127, VAR194}),
.VAR226({VAR247, VAR66, VAR94, VAR165}),
.VAR74( {VAR283, VAR213, VAR240, VAR23 }),
.VAR170( {VAR157, VAR248, VAR73, VAR183 })
);
wire [7:0] VAR104;
wire [31:0] VAR180;
wire [31:0] VAR273;
wire VAR268;
wire [3:0] VAR12;
wire VAR184;
wire VAR79;
wire VAR207;
VAR147 #(
.VAR81("VAR129 VAR112 0"),
.VAR42(16),
.VAR173(32),
.VAR172(8),
.VAR50(4)
)
VAR153 (
.clk(clk),
.rst(rst),
.VAR224(VAR6),
.VAR116(VAR194),
.VAR214(VAR165),
.VAR13(VAR23),
.VAR150(VAR183),
.VAR64(VAR155),
.VAR30(VAR56),
.VAR245(VAR163),
.VAR277(VAR82),
.VAR143(VAR272),
.VAR47(VAR104),
.VAR121(VAR273),
.VAR96(VAR180),
.VAR204(VAR268),
.VAR160(VAR12),
.VAR142(VAR184),
.VAR100(VAR79),
.VAR63(1'b0),
.VAR103(VAR207)
);
VAR260 #(
.VAR9(32),
.VAR282(8),
.VAR105(4)
)
VAR276 (
.clk(clk),
.VAR196(VAR104),
.VAR257(VAR180),
.VAR200(VAR273),
.VAR67(VAR268),
.VAR266(VAR12),
.VAR29(VAR184),
.VAR4(VAR79),
.VAR256(VAR207)
);
wire [7:0] VAR251;
wire [31:0] VAR274;
wire [31:0] VAR182;
wire VAR10;
wire [3:0] VAR15;
wire VAR275;
wire VAR241;
wire VAR22;
VAR147 #(
.VAR81("VAR129 VAR112 1"),
.VAR42(16),
.VAR173(32),
.VAR172(8),
.VAR50(4)
)
VAR45 (
.clk(clk),
.rst(rst),
.VAR224(VAR149),
.VAR116(VAR127),
.VAR214(VAR94),
.VAR13(VAR240),
.VAR150(VAR73),
.VAR64(VAR62),
.VAR30(VAR215),
.VAR245(VAR43),
.VAR277(VAR125),
.VAR143(VAR225),
.VAR47(VAR251),
.VAR121(VAR182),
.VAR96(VAR274),
.VAR204(VAR10),
.VAR160(VAR15),
.VAR142(VAR275),
.VAR100(VAR241),
.VAR63(1'b0),
.VAR103(VAR22)
);
VAR260 #(
.VAR9(32),
.VAR282(8),
.VAR105(4)
)
VAR137 (
.clk(clk),
.VAR196(VAR251),
.VAR257(VAR274),
.VAR200(VAR182),
.VAR67(VAR10),
.VAR266(VAR15),
.VAR29(VAR275),
.VAR4(VAR241),
.VAR256(VAR22)
);
wire [7:0] VAR250;
wire [31:0] VAR192;
wire [31:0] VAR48;
wire VAR14;
wire [3:0] VAR145;
wire VAR75;
wire VAR31;
wire VAR280;
VAR147 #(
.VAR81("VAR129 VAR112 2"),
.VAR42(16),
.VAR173(32),
.VAR172(8),
.VAR50(4)
)
VAR5 (
.clk(clk),
.rst(rst),
.VAR224(VAR234),
.VAR116(VAR193),
.VAR214(VAR66),
.VAR13(VAR213),
.VAR150(VAR248),
.VAR64(VAR80),
.VAR30(VAR84),
.VAR245(VAR168),
.VAR277(VAR202),
.VAR143(VAR108),
.VAR47(VAR250),
.VAR121(VAR48),
.VAR96(VAR192),
.VAR204(VAR14),
.VAR160(VAR145),
.VAR142(VAR75),
.VAR100(VAR31),
.VAR63(1'b0),
.VAR103(VAR280)
);
VAR260 #(
.VAR9(32),
.VAR282(8),
.VAR105(4)
)
VAR131 (
.clk(clk),
.VAR196(VAR250),
.VAR257(VAR192),
.VAR200(VAR48),
.VAR67(VAR14),
.VAR266(VAR145),
.VAR29(VAR75),
.VAR4(VAR31),
.VAR256(VAR280)
);
wire [7:0] VAR199;
wire [31:0] VAR61;
wire [31:0] VAR265;
wire VAR71;
wire [3:0] VAR87;
wire VAR264;
wire VAR197;
wire VAR65;
VAR147 #(
.VAR81("VAR129 VAR112 3"),
.VAR42(16),
.VAR173(32),
.VAR172(8),
.VAR50(4)
)
VAR230 (
.clk(clk),
.rst(rst),
.VAR224(VAR72),
.VAR116(VAR253),
.VAR214(VAR247),
.VAR13(VAR283),
.VAR150(VAR157),
.VAR64(VAR203),
.VAR30(VAR27),
.VAR245(VAR176),
.VAR277(VAR148),
.VAR143(VAR58),
.VAR47(VAR199),
.VAR121(VAR265),
.VAR96(VAR61),
.VAR204(VAR71),
.VAR160(VAR87),
.VAR142(VAR264),
.VAR100(VAR197),
.VAR63(1'b0),
.VAR103(VAR65)
);
VAR260 #(
.VAR9(32),
.VAR282(8),
.VAR105(4)
)
VAR136 (
.clk(clk),
.VAR196(VAR199),
.VAR257(VAR61),
.VAR200(VAR265),
.VAR67(VAR71),
.VAR266(VAR87),
.VAR29(VAR264),
.VAR4(VAR197),
.VAR256(VAR65)
);
endmodule
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/jbi/jbi_mout/rtl/jbi_ncrd_timeout.v
| 6,427 |
module MODULE1 (
VAR15, VAR30, VAR8,
VAR38, VAR42, VAR21, VAR2, VAR33,
VAR17, VAR48, clk, VAR5
);
input VAR38;
input [3:0] VAR42;
input VAR21;
input [3:0] VAR2;
output VAR15;
output [3:0] VAR30;
input VAR33;
input VAR17;
output VAR8;
input [31:0] VAR48; input clk;
input VAR5;
wire VAR22, VAR24, VAR28;
wire [15:0] VAR14, VAR27, VAR37;
wire [31:0] VAR23;
wire [3:0] VAR35;
wire [31:0] VAR39 = (VAR22 || VAR24)? 1'b0: VAR23 + 1'b1;
VAR9 #(32) VAR4 (.din(VAR39), .VAR16(VAR23), .VAR5(VAR5), .clk(clk));
assign VAR22 = (VAR23 >= VAR48);
wire [15:0] VAR6 = {16{VAR38}} & VAR40(VAR42);
wire [15:0] VAR7 = ({16{VAR21}} & VAR40(VAR2)) | VAR37[15:0];
VAR32 VAR31 (.VAR6(VAR6[15]), .VAR7(VAR7[15]), .VAR27(VAR27[15]), .VAR14(VAR14[15]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR13 (.VAR6(VAR6[14]), .VAR7(VAR7[14]), .VAR27(VAR27[14]), .VAR14(VAR14[14]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR34 (.VAR6(VAR6[13]), .VAR7(VAR7[13]), .VAR27(VAR27[13]), .VAR14(VAR14[13]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR18 (.VAR6(VAR6[12]), .VAR7(VAR7[12]), .VAR27(VAR27[12]), .VAR14(VAR14[12]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR11 (.VAR6(VAR6[11]), .VAR7(VAR7[11]), .VAR27(VAR27[11]), .VAR14(VAR14[11]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR49 (.VAR6(VAR6[10]), .VAR7(VAR7[10]), .VAR27(VAR27[10]), .VAR14(VAR14[10]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR3 (.VAR6(VAR6[ 9]), .VAR7(VAR7[ 9]), .VAR27(VAR27[ 9]), .VAR14(VAR14[ 9]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR45 (.VAR6(VAR6[ 8]), .VAR7(VAR7[ 8]), .VAR27(VAR27[ 8]), .VAR14(VAR14[ 8]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR12 (.VAR6(VAR6[ 7]), .VAR7(VAR7[ 7]), .VAR27(VAR27[ 7]), .VAR14(VAR14[ 7]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR19 (.VAR6(VAR6[ 6]), .VAR7(VAR7[ 6]), .VAR27(VAR27[ 6]), .VAR14(VAR14[ 6]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR43 (.VAR6(VAR6[ 5]), .VAR7(VAR7[ 5]), .VAR27(VAR27[ 5]), .VAR14(VAR14[ 5]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR1 (.VAR6(VAR6[ 4]), .VAR7(VAR7[ 4]), .VAR27(VAR27[ 4]), .VAR14(VAR14[ 4]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR20 (.VAR6(VAR6[ 3]), .VAR7(VAR7[ 3]), .VAR27(VAR27[ 3]), .VAR14(VAR14[ 3]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR44 (.VAR6(VAR6[ 2]), .VAR7(VAR7[ 2]), .VAR27(VAR27[ 2]), .VAR14(VAR14[ 2]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR26 (.VAR6(VAR6[ 1]), .VAR7(VAR7[ 1]), .VAR27(VAR27[ 1]), .VAR14(VAR14[ 1]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
VAR32 VAR25 (.VAR6(VAR6[ 0]), .VAR7(VAR7[ 0]), .VAR27(VAR27[ 0]), .VAR14(VAR14[ 0]), .VAR22(VAR22), .clk(clk), .VAR5(VAR5));
assign VAR24 = (VAR27[15:0] == 16'b0);
wire VAR29 = (VAR14[15:0] != 16'b0);
wire [3:0] VAR41 = (!VAR29)? 1'b0:
(VAR28)? VAR35:
VAR35 + 1'b1;
VAR9 #(4) VAR10 (.din(VAR41), .VAR16(VAR35), .VAR5(VAR5), .clk(clk));
assign VAR28 = |(VAR40(VAR35) & VAR14[15:0]);
wire VAR36 = VAR28 && VAR17;
VAR46 VAR47 (.din(VAR36), .VAR16(VAR15), .clk(clk));
assign VAR30 = VAR35;
assign VAR8 = VAR33;
assign VAR37[15:0] = {16{VAR33}} & VAR40(VAR35);
endmodule
|
gpl-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dmc/bsg_dmc_phy.v
| 12,113 |
module MODULE5
(input VAR51
,input VAR39
,input [1:0] VAR61
,output logic VAR74
,output logic VAR57);
wire VAR50 = ~VAR51;
logic VAR36;
VAR12 @(posedge VAR50) begin
if(VAR39) begin
VAR36 <= ~VAR36;
if(VAR36) begin
VAR74 <= VAR61[1];
end
else begin
VAR74 <= VAR61[0];
end
VAR57 <= 1'b0;
end
else begin
VAR36 <= 1'b0;
VAR57 <= 1'b1;
end
end
endmodule
module MODULE2
(input VAR38
,input [1:0] VAR83
,input [1:0] VAR60
,input VAR34
,input VAR79
,input VAR13
,output logic VAR30
,output logic VAR2);
logic [3:0] VAR17, VAR25;
wire VAR40, VAR58;
VAR12 @(posedge VAR79) begin
VAR17[VAR83] <= VAR34;
end
VAR12 @(posedge VAR13) begin
VAR25[VAR83] <= VAR34;
end
assign VAR40 = VAR17[VAR60];
assign VAR58 = VAR25[VAR60];
VAR12 @(posedge VAR38) begin
VAR30 <= VAR40;
VAR2 <= VAR58;
end
endmodule
module MODULE3
(input VAR38
,input VAR51
,input VAR79
,input VAR13
,input VAR39
,input [1:0] VAR61
,output VAR74
,output VAR57
,input VAR34
,input [1:0] VAR83
,input [1:0] VAR60
,output VAR30
,output VAR2);
MODULE5 MODULE5
(.VAR51 ( VAR51 )
,.VAR39 ( VAR39 )
,.VAR61 ( VAR61 )
,.VAR74 ( VAR74 )
,.VAR57 ( VAR57 ));
MODULE2 MODULE3
(.VAR38 ( VAR38 )
,.VAR83 ( VAR83 )
,.VAR60 ( VAR60 )
,.VAR34 ( VAR34 )
,.VAR79 ( VAR79 )
,.VAR13 ( VAR13 )
,.VAR30 ( VAR30 )
,.VAR2 ( VAR2 ));
endmodule
module MODULE1
(input VAR73
,input VAR38
,input VAR51
,input VAR4
,input [15:0] VAR67
,input [1:0] VAR87
,output VAR94
,output VAR70
,output [7:0] VAR57
,output [7:0] VAR74
,output logic VAR21
,output logic VAR66
,output logic VAR29
,output logic VAR76
,input VAR88
,output [15:0] VAR89
,input [7:0] VAR34
,input VAR79
,input VAR13
);
wire VAR93 = VAR38;
wire VAR91 = VAR51;
wire VAR50 = ~VAR51;
logic VAR72, VAR80;
logic [15:0] VAR77, VAR47;
logic [1:0] VAR10, VAR32;
logic [1:0] VAR23, VAR24;
genvar VAR68;
VAR12 @(posedge VAR50) begin
VAR72 <= VAR4;
VAR77 <= VAR67;
VAR10 <= VAR87;
end
VAR12 @(posedge VAR91) begin
VAR80 <= VAR4;
end
VAR12 @(posedge VAR91) begin
VAR21 <= ~(VAR4 | VAR80);
VAR29 <= ~(VAR4 | VAR80);
end
VAR12 @(posedge VAR91) begin
if(VAR4 || VAR80) begin
VAR66 <= ~VAR66;
VAR76 <= ~VAR76;
end
else begin
VAR66 <= 1'b1;
VAR76 <= 1'b0;
end
end
VAR12 @(posedge VAR13 or posedge VAR73) begin
if(VAR73)
VAR23 <= 'b0;
end
else
VAR23 <= VAR23 + 1'b1;
end
VAR12 @(posedge VAR93) begin
if(VAR73)
VAR24 <= 'b0;
end
else if(VAR88)
VAR24 <= VAR24 + 1'b1;
end
for(VAR68=0;VAR68<8;VAR68++) begin: VAR90
MODULE3 MODULE2
(.VAR38 ( VAR38 )
,.VAR51 ( VAR51 )
,.VAR79 ( VAR79 )
,.VAR13 ( VAR13 )
,.VAR39 ( VAR72 )
,.VAR61 ( {VAR77[8+VAR68], VAR77[VAR68]} )
,.VAR74 ( VAR74[VAR68] )
,.VAR57 ( VAR57[VAR68] )
,.VAR34 ( VAR34[VAR68] )
,.VAR83 ( VAR23 )
,.VAR60 ( VAR24 )
,.VAR30 ( VAR89[VAR68] )
,.VAR2 ( VAR89[8+VAR68] ));
end
MODULE5 MODULE1
(.VAR51 ( VAR51 )
,.VAR39 ( VAR72 )
,.VAR61 ( VAR10 )
,.VAR74 ( VAR70 )
,.VAR57 ( VAR94 ));
endmodule
module MODULE4 #
(parameter VAR44( VAR22 )
,localparam VAR85 = VAR22 >> 3)
(input VAR75
,input VAR82
,input VAR26
,input [2:0] VAR101
,input [15:0] VAR78
,input VAR86
,input VAR69
,input VAR15
,input VAR102
,input VAR45
,input VAR96
,input VAR52
,input VAR46
,input [2*VAR22-1:0] VAR14
,input [2*VAR85-1:0] VAR16
,input VAR42
,output [2*VAR22-1:0] VAR31
,output logic VAR20
,output VAR5
,output VAR7
,output logic VAR1
,output logic [2:0] VAR71
,output logic [15:0] VAR11
,output logic VAR104
,output logic VAR81
,output logic VAR59
,output logic VAR99
,output logic VAR33
,output logic VAR62
,output [VAR85-1:0] VAR94
,output [VAR85-1:0] VAR70
,output [VAR85-1:0] VAR21
,output [VAR85-1:0] VAR105
,output [VAR85-1:0] VAR66
,input [VAR85-1:0] VAR79
,output [VAR85-1:0] VAR29
,output [VAR85-1:0] VAR28
,output [VAR85-1:0] VAR76
,input [VAR85-1:0] VAR13
,output [8*VAR85-1:0] VAR57
,output [8*VAR85-1:0] VAR74
,input [8*VAR85-1:0] VAR34
,input [2:0] VAR3);
wire VAR93 = VAR75;
wire VAR18 = ~VAR75;
wire VAR91 = VAR82;
wire VAR50 = ~VAR82;
logic [7:0][0:0] VAR84;
logic VAR103;
logic VAR37;
logic [VAR85-1:0] VAR92;
logic [VAR85-1:0] VAR55;
genvar VAR68;
VAR12 @(posedge VAR18) begin
if(VAR26) begin
VAR1 <= 1'b0;
VAR71 <= 3'b000;
VAR11 <= 16'h0;
VAR104 <= 1'b1;
VAR81 <= 1'b1;
VAR59 <= 1'b1;
VAR99 <= 1'b1;
VAR33 <= 1'b1;
VAR62 <= 1'b0;
end
else begin
VAR1 <= VAR86;
VAR71 <= VAR101;
VAR11 <= VAR78;
VAR104 <= VAR69;
VAR81 <= VAR15;
VAR59 <= VAR102;
VAR99 <= VAR45;
VAR33 <= VAR96;
VAR62 <= VAR52;
end
end
assign VAR84[0] = VAR42;
VAR12 @(posedge VAR50) begin
if(VAR26) begin
VAR84[1] <= 1'b0;
VAR84[3] <= 1'b0;
VAR84[5] <= 1'b0;
VAR84[7] <= 1'b0;
end
else begin
VAR84[1] <= VAR84[0];
VAR84[3] <= VAR84[2];
VAR84[5] <= VAR84[4];
VAR84[7] <= VAR84[6];
end
end
VAR12 @(posedge VAR91) begin
if(VAR26) begin
VAR84[2] <= 1'b0;
VAR84[4] <= 1'b0;
VAR84[6] <= 1'b0;
end
else begin
VAR84[2] <= VAR84[1];
VAR84[4] <= VAR84[3];
VAR84[6] <= VAR84[5];
end
end
VAR12 @(posedge VAR93) begin
if(VAR26)
VAR37 <= 1'b0;
end
else
VAR37 <= VAR103;
end
VAR49 #
(.VAR6 ( 1 )
,.VAR41 ( 8 ))
mux
(.VAR8 ( VAR84 )
,.VAR27 ( VAR3 )
,.VAR9 ( VAR103 ));
VAR12 @(posedge VAR93) begin
if(VAR26)
VAR20 <= 1'b0;
end
else
VAR20 <= VAR37;
end
assign VAR5 = VAR93;
assign VAR7 = VAR18;
assign VAR92 = ~{VAR85{VAR103}};
assign VAR55 = ~{VAR85{VAR103}};
assign VAR105 = VAR92;
assign VAR28 = VAR55;
logic [7:0] VAR19 [((VAR22>>3)<<1)-1:0];
logic [7:0] VAR48 [((VAR22>>3)<<1)-1:0];
VAR98 #
(.VAR6 (8)
,.VAR65 ((VAR22>>3)<<1))
VAR35
(.VAR68 (VAR14)
,.VAR43 (VAR19));
VAR56 #
(.VAR6 (8)
,.VAR65 ((VAR22>>3)<<1))
VAR53
(.VAR68 (VAR48)
,.VAR43 (VAR31));
for(VAR68=0;VAR68<VAR85;VAR68=VAR68+1) begin: VAR64
MODULE1 MODULE4
(.VAR73 ( VAR26 )
,.VAR38 ( VAR93 )
,.VAR51 ( VAR91 )
,.VAR4 ( VAR46 )
,.VAR67 ( {VAR19[VAR85+VAR68], VAR19[VAR68]} )
,.VAR87 ( {VAR16[VAR85+VAR68], VAR16[VAR68]} )
,.VAR94 ( VAR94[VAR68] )
,.VAR70 ( VAR70[VAR68] )
,.VAR57 ( VAR57[8*VAR68+:8] )
,.VAR74 ( VAR74[8*VAR68+:8] )
,.VAR21 ( VAR21[VAR68] )
,.VAR66 ( VAR66[VAR68] )
,.VAR29 ( VAR29[VAR68] )
,.VAR76 ( VAR76[VAR68] )
,.VAR88 ( VAR37 )
,.VAR89 ( {VAR48[VAR85+VAR68], VAR48[VAR68]} )
,.VAR34 ( VAR34[8*VAR68+:8] )
,.VAR79 ( VAR79[VAR68] )
,.VAR13 ( VAR13[VAR68] ));
end
endmodule
|
bsd-3-clause
|
lbl-cal/StanfordNoC
|
router/verif/router/ugal_sniffer.v
| 5,184 |
module MODULE1(
VAR35,
clk, reset, VAR15, VAR26
);
parameter VAR14 = 16;
parameter VAR32 = 1;
parameter VAR30 = 2;
localparam VAR39 = VAR32 * VAR30;
parameter VAR19 = 1;
localparam VAR17 = VAR39 * VAR19;
localparam VAR31 = VAR25(VAR17);
parameter VAR24 = VAR3;
localparam VAR27
= (VAR24 == VAR4) ?
(1 + VAR31 + 1 + 1) :
(VAR24 == VAR13) ?
(1 + VAR31 + 1) :
(VAR24 == VAR3) ?
(1 + VAR31 + 1) :
-1;
localparam VAR16 = 1 + VAR31;
parameter VAR29 = VAR1;
parameter VAR2 = VAR28;
parameter VAR37 = 64;
parameter VAR21 = 2;
parameter VAR8 = 4;
localparam VAR23
= (VAR37 + VAR8 - 1) / VAR8;
localparam VAR5 = VAR22(VAR23, VAR21);
localparam VAR41
= (VAR2 == VAR36) ?
2 :
(VAR2 == VAR28) ?
(VAR5 - 1) :
-1;
localparam VAR33
= VAR21 * VAR41 + VAR8;
localparam VAR20 = VAR25(VAR14)+1;
input clk;
input reset;
input [0:(VAR33-VAR8)*VAR27-1] VAR15;
input [0:(VAR33-VAR8)*VAR16-1] VAR26;
output [0:(VAR33-VAR8)*VAR20-1] VAR35;
generate
genvar VAR7;
for(VAR7 = 0; VAR7<VAR33-VAR8; VAR7=VAR7+1)
begin:VAR6
wire [0:VAR20-1] VAR12;
wire [0:VAR20-1] VAR18;
VAR10
.VAR11 (VAR20),
.VAR29 (VAR29))
VAR9
(
.VAR38 (VAR12[0:VAR20-1]),
.clk (clk),
.reset (reset),
.VAR40 (VAR40),
.VAR34 (VAR18[0:VAR20-1]));
assign VAR18 = VAR12
+VAR15[VAR7*VAR27]
-VAR26[VAR7*VAR16];
assign VAR35 [VAR7*VAR20:(VAR7+1)*VAR20-1] = VAR12[0:VAR20-1];
end
endgenerate
endmodule
|
bsd-2-clause
|
ankitshah009/High-Radix-Adaptive-CORDIC
|
HCORDIC_Verilog/NormaliseProdMult.v
| 2,223 |
module MODULE1(
input [32:0] VAR7,
input [49:0] VAR10,
input VAR4,
input VAR12,
output reg VAR11,
output reg [32:0] VAR9,
output reg [49:0] VAR6
);
parameter VAR1 = 1'b0,
VAR3 = 1'b1;
wire VAR8;
wire [7:0] VAR2;
wire [26:0] VAR5;
assign VAR8 = VAR7[32];
assign VAR2 = VAR7[31:24];
assign VAR5 = {VAR7[23:0]};
always @ (posedge VAR4) begin
VAR11 <= VAR12;
if (VAR12 == VAR1) begin
if ((VAR2) < -126) begin
VAR9[32] <= VAR8;
VAR9[31:24] <= VAR2 + 1;
VAR9[23:0] <= VAR5;
VAR6 <= VAR10 >> 1;
end
else if (VAR10[49] == 0) begin
VAR9[32] <= VAR8;
VAR9[31:24] <= VAR2 - 1;
VAR9[23:0] <= {VAR10[48:25]};
VAR6 <= VAR10 << 1;
end
else begin
VAR9[32] <= VAR8;
VAR9[31:24] <= VAR2;
VAR9[23:0] <= {VAR10[49:26]};
VAR6 <= VAR10;
end
end
else begin
VAR9 <= VAR7;
end
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o21ai/sky130_fd_sc_hdll__o21ai.pp.blackbox.v
| 1,367 |
module MODULE1 (
VAR4 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR1,
VAR3,
VAR8 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR3;
input VAR8 ;
input VAR6 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o41a/sky130_fd_sc_lp__o41a_lp.v
| 2,419 |
module MODULE1 (
VAR1 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR5,
VAR9,
VAR12 ,
VAR10
);
output VAR1 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR5;
input VAR9;
input VAR12 ;
input VAR10 ;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR10(VAR10)
);
endmodule
module MODULE1 (
VAR1 ,
VAR7,
VAR3,
VAR4,
VAR11,
VAR6
);
output VAR1 ;
input VAR7;
input VAR3;
input VAR4;
input VAR11;
input VAR6;
supply1 VAR5;
supply0 VAR9;
supply1 VAR12 ;
supply0 VAR10 ;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/cores/axis_lfsr_v1_0/src/axis_lfsr.v
| 1,110 |
module MODULE1 #
(
parameter integer VAR2 = 64
)
(
input wire VAR1,
input wire VAR3,
input wire VAR5,
output wire [VAR2-1:0] VAR7,
output wire VAR10
);
reg [VAR2-1:0] VAR9, VAR4;
reg VAR6, VAR8;
always @(posedge VAR1)
begin
if(~VAR3)
begin
VAR9 <= 64'h5555555555555555;
VAR6 <= 1'b0;
end
else
begin
VAR9 <= VAR4;
VAR6 <= VAR8;
end
end
always @*
begin
VAR4 = VAR9;
VAR8 = VAR6;
if(~VAR6)
begin
VAR8 = 1'b1;
end
if(VAR6 & VAR5)
begin
VAR4 = {VAR9[62:0], VAR9[62] ~^ VAR9[61]};
end
end
assign VAR7 = VAR9;
assign VAR10 = VAR6;
endmodule
|
gpl-3.0
|
skatpgusskat/KoreaUnivHomework_2015_1
|
Computer Architecture/Homework/Lab/alu_beh.v
| 1,472 |
module MODULE2(VAR3, VAR6, VAR8, VAR4, VAR1);
input [31:0] VAR3, VAR6;
input [2:0] VAR8;
output [31:0] VAR4;
reg [31:0] VAR4;
output VAR1;
reg VAR1;
always @(VAR3 or VAR6 or VAR8)
begin
casez(VAR8)
3'b110: VAR4 = VAR3 - VAR6;
3'b010: VAR4 = VAR3 + VAR6;
3'VAR2: VAR4 = VAR3 & VAR6;
3'VAR7?01: VAR4 = VAR3 | VAR6;
3'VAR7?11:
if ( VAR3 - VAR6 >= 0 )
VAR4 = 1;
end
else
VAR4 = 0;
endcase
if (VAR3 == VAR6)
VAR1 = 1;
else
VAR1 = 0;
end
endmodule
module MODULE1;
reg [31:0] VAR3, VAR6;
reg [2:0] VAR8;
wire [31:0] VAR4;
wire VAR1;
MODULE2 VAR5(VAR3, VAR6, VAR8, VAR4, VAR1);
|
mit
|
olajep/oh
|
src/adi/hdl/library/common/up_pmod.v
| 4,428 |
module MODULE1 #(
parameter VAR17 = 0) (
input VAR14,
output VAR7,
input [31:0] VAR22,
input VAR6,
input VAR3,
input VAR19,
input [13:0] VAR2,
input [31:0] VAR25,
output reg VAR8,
input VAR23,
input [13:0] VAR10,
output reg [31:0] VAR28,
output reg VAR29);
localparam VAR11 = 32'h00010001;
reg [31:0] VAR1 = 'd0;
reg VAR30 = 'd0;
wire [31:0] VAR20;
wire VAR24;
wire VAR16;
assign VAR24 = (VAR2[13:8] == 6'h00) ? VAR19 : 1'b0;
assign VAR16 = (VAR10[13:8] == 6'h00) ? VAR23 : 1'b0;
assign VAR27 = ~VAR30;
always @(negedge VAR6 or posedge VAR3) begin
if (VAR6 == 0) begin
VAR8 <= 'd0;
VAR1 <= 'd0;
VAR30 <= 'd0;
end else begin
VAR8 <= VAR24;
if ((VAR24 == 1'b1) && (VAR2[7:0] == 8'h02)) begin
VAR1 <= VAR25;
end
if ((VAR24 == 1'b1) && (VAR2[7:0] == 8'h10)) begin
VAR30 <= VAR25[0];
end
end
end
always @(negedge VAR6 or posedge VAR3) begin
if (VAR6 == 0) begin
VAR29 <= 'd0;
VAR28 <= 'd0;
end else begin
VAR29 <= VAR16;
if (VAR16 == 1'b1) begin
case (VAR10[7:0])
8'h00: VAR28 <= VAR11;
8'h01: VAR28 <= VAR17;
8'h02: VAR28 <= VAR1;
8'h03: VAR28 <= VAR20;
8'h10: VAR28 <= VAR30;
default: VAR28 <= 0;
endcase
end else begin
VAR28 <= 32'd0;
end
end
end
VAR5 VAR21 (.VAR12(VAR27), .clk(VAR14), .VAR9(), .rst(VAR7));
VAR31 #(.VAR26(32)) VAR15 (
.VAR6 (VAR6),
.VAR3 (VAR3),
.VAR13 (VAR20),
.VAR4 (VAR7),
.VAR18 (VAR14),
.VAR32 (VAR22));
endmodule
|
mit
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/reorder_queue.v
| 12,634 |
module MODULE1
parameter VAR82 = 9'd128,
parameter VAR48 = 4'd12,
parameter VAR29 = 512, parameter VAR25 = 5, parameter VAR86 = VAR82/32,
parameter VAR1 = VAR18(VAR86+1),
parameter VAR30 = 2**VAR25,
parameter VAR45 = VAR29/4,
parameter VAR52 = VAR7(VAR45+1),
parameter VAR59 = VAR7(VAR45/VAR86), parameter VAR10 = VAR25 + VAR59
)
(
input VAR14, input VAR24, input VAR16, input [VAR82-1:0] VAR91, input [(VAR82/32)-1:0] VAR12, input VAR21, input [VAR7(VAR82/32)-1:0] VAR76, input VAR87, input [VAR7(VAR82/32)-1:0] VAR6, input VAR13, input VAR68, input [VAR25-1:0] VAR5,
input [5:0] VAR64, input VAR40, output [VAR25-1:0] VAR42, output VAR69,
output [VAR82-1:0] VAR28, output [(VAR48*VAR1)-1:0] VAR63, output [VAR48-1:0] VAR85, output [VAR48-1:0] VAR41, output [(VAR48*VAR1)-1:0] VAR90, output [VAR48-1:0] VAR81, output [VAR48-1:0] VAR46, output [(VAR48*VAR1)-1:0] VAR56, output [VAR48-1:0] VAR60, output [VAR48-1:0] VAR37 );
wire [(VAR10*VAR86)-1:0] VAR54;
wire [VAR82-1:0] VAR57;
wire [VAR86-1:0] VAR62;
wire [VAR25-1:0] VAR19;
wire [VAR52-1:0] VAR9;
wire VAR58;
wire VAR35;
wire VAR74;
wire VAR78;
wire VAR51;
wire [VAR10-1:0] VAR36;
wire [VAR82-1:0] VAR22;
wire [VAR25-1:0] VAR92;
wire [(1+1+1+1+VAR52)-1:0] VAR53;
wire [5:0] VAR3;
wire [VAR30-1:0] VAR65;
wire [VAR30-1:0] VAR47;
reg [VAR25-1:0] VAR49=0;
reg VAR17=0;
reg [VAR30-1:0] VAR4=0;
reg [VAR30-1:0] VAR38=0;
reg [VAR30-1:0] VAR77=0;
assign VAR42 = VAR49;
assign VAR69 = VAR17;
always @ (posedge VAR14) begin
if (VAR24) begin
VAR49 <= 0;
VAR38 <= 0;
VAR17 <= 0;
end
else begin
if (VAR40 & VAR69) begin
VAR49 <= VAR49 + 1'd1;
VAR38 <= 1<<VAR49;
VAR17 <= !VAR77[VAR49 + 1'd1];
end
else begin
VAR38 <= 0;
VAR17 <= !VAR77[VAR49];
end
end
end
always @ (posedge VAR14) begin
if (VAR24) begin
VAR77 <= 0;
VAR4 <= 0;
end
else begin
VAR77 <= (VAR77 | VAR38) & ~VAR47;
VAR4 <= (VAR4 | VAR65) & ~VAR47;
end
end
genvar VAR71;
generate
for (VAR71 = 0; VAR71 < VAR86; VAR71 = VAR71 + 1) begin : VAR83
VAR79
.VAR89(VAR30*VAR45/VAR86)
)
VAR84
(
.VAR14(VAR14),
.VAR88(VAR54[VAR10*VAR71 +:VAR10]),
.VAR11(VAR62[VAR71]),
.VAR27(VAR57[32*VAR71 +:32]),
.VAR8(VAR36),
.VAR43(VAR22[32*VAR71 +:32])
);
end
endgenerate
VAR79
.VAR89(VAR30))
VAR70
(
.VAR14(VAR14),
.VAR88(VAR19),
.VAR11((VAR78 | VAR51) & VAR74),
.VAR27({VAR78, VAR51, VAR35, VAR58, VAR9}),
.VAR8(VAR92),
.VAR43(VAR53)
);
VAR79
.VAR89(VAR30))
VAR20
(
.VAR14(VAR14),
.VAR88(VAR49),
.VAR11(VAR40 & VAR69),
.VAR27(VAR64),
.VAR8(VAR92),
.VAR43(VAR3)
);
VAR66
.VAR82(VAR82),
.VAR25(VAR25),
.VAR52(VAR52),
.VAR59(VAR59),
.VAR10(VAR10)
)
VAR23
(
.VAR14(VAR14),
.VAR24(VAR24),
.VAR16(VAR16),
.VAR21 (VAR21),
.VAR76 (VAR76[VAR7(VAR82/32)-1:0]),
.VAR87 (VAR87),
.VAR6 (VAR6[VAR7(VAR82/32)-1:0]),
.VAR91 (VAR91),
.VAR12 (VAR12),
.VAR13(VAR13),
.VAR68(VAR68),
.VAR5(VAR5),
.VAR55(VAR65),
.VAR73(VAR47),
.VAR67(VAR54),
.VAR50(VAR57),
.VAR61(VAR62),
.VAR34(VAR74),
.VAR33(VAR19),
.VAR15(VAR9),
.VAR44(VAR58),
.VAR32(VAR35),
.VAR80(VAR78),
.VAR26(VAR51)
);
VAR72
.VAR82(VAR82),
.VAR48(VAR48),
.VAR25(VAR25),
.VAR52(VAR52),
.VAR59(VAR59),
.VAR10(VAR10)
)
VAR31
(
.VAR14(VAR14),
.VAR24(VAR24),
.VAR75(VAR36),
.VAR91(VAR22),
.VAR39(VAR4),
.VAR73(VAR47),
.VAR5(VAR92),
.VAR2(VAR3),
.VAR15(VAR53[0 +:VAR52]),
.VAR44(VAR53[VAR52]),
.VAR32(VAR53[VAR52+1]),
.VAR26(VAR53[VAR52+2]),
.VAR80(VAR53[VAR52+3]),
.VAR28(VAR28),
.VAR63(VAR63),
.VAR85(VAR85),
.VAR41(VAR41),
.VAR90(VAR90),
.VAR81(VAR81),
.VAR46(VAR46),
.VAR56(VAR56),
.VAR60(VAR60),
.VAR37(VAR37)
);
endmodule
|
gpl-3.0
|
nickdesaulniers/Omicron
|
control_unit.v
| 6,137 |
module MODULE1(
input clk,
input VAR33,
input [3:0] VAR11,
output reg VAR26, output reg VAR2, output reg [10:0] VAR6, output reg VAR13, output reg VAR4, output reg [1:0] VAR17 );
parameter VAR12 = 4'b0000;
parameter VAR28 = 4'b0001;
parameter VAR30 = 4'b0010;
parameter VAR21 = 4'b0011;
parameter VAR31 = 4'b0100;
parameter VAR20 = 4'b0101;
parameter VAR15 = 4'b0110;
parameter VAR25 = 4'b0111;
parameter VAR7 = 4'b1000;
parameter VAR9 = 4'b1001;
parameter VAR24 = 4'b1010;
parameter VAR19 = 4'b1011;
parameter VAR29 = 4'b1100;
parameter VAR27 = 4'b1101;
parameter VAR3 = 4'b1110;
parameter VAR18 = 4'b1111;
parameter VAR34 = 11'b00000000001;
parameter VAR10 = 11'b00000000010;
parameter VAR5 = 11'b00000000100;
parameter VAR35 = 11'b00000001000;
parameter VAR1 = 11'b00000010000;
parameter VAR8 = 11'b00000100000;
parameter VAR22 = 11'b00001000000;
parameter VAR23 = 11'b00010000000;
parameter VAR14 = 11'b00100000000;
parameter VAR32 = 11'b01000000000;
parameter VAR16 = 11'b10000000000;
always@(posedge clk or negedge VAR33) begin
if(!VAR33) begin
VAR6 <= VAR34;
VAR26 <= 1'b0;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end else begin
case(VAR11)
VAR12: begin
VAR6 <= VAR34;
VAR26 <= 1'b0;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR28: begin
VAR6 <= VAR10;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR30: begin
VAR6 <= VAR5;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR21: begin
VAR6 <= VAR35;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR31: begin
VAR6 <= VAR1;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR20: begin
VAR6 <= VAR8;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR15: begin
VAR6 <= VAR22;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR25: begin
VAR6 <= VAR23;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR7: begin
VAR6 <= VAR14;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR9: begin
VAR6 <= VAR32;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR24: begin
VAR6 <= VAR16;
VAR26 <= 1'b1;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR19: begin
VAR6 <= VAR35;
VAR26 <= 1'b0;
VAR4 <= 1'b0;
VAR17 <= 2'b01;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR29: begin
VAR6 <= VAR35;
VAR26 <= 1'b0;
VAR4 <= 1'b0;
VAR17 <= 2'b10;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
VAR27: begin
VAR6 <= VAR10;
VAR26 <= 1'b1;
VAR4 <= 1'b1;
VAR17 <= 2'b00;
VAR13 <= 1'b0;
VAR2 <= 1'b1;
end
VAR3: begin
VAR6 <= VAR10;
VAR26 <= 1'b0;
VAR4 <= 1'b0;
VAR17 <= 2'b00;
VAR13 <= 1'b1;
VAR2 <= 1'b1;
end
VAR18: begin
VAR6 <= VAR34;
VAR26 <= 1'b0;
VAR4 <= 1'b0;
VAR17 <= 2'b11;
VAR13 <= 1'b0;
VAR2 <= 1'b0;
end
endcase
end
end
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.functional.pp.v
| 1,611 |
module MODULE1( VAR8, VAR12, VAR19, VAR7, VAR13, VAR1, VAR15 );
input VAR12, VAR8, VAR7, VAR13;
inout VAR1, VAR15;
output VAR19;
wire VAR10;
not VAR9( VAR10, VAR12 );
wire VAR20;
not VAR5( VAR20, VAR7 );
wire VAR14;
not VAR4( VAR14, VAR13 );
wire VAR6;
and VAR17( VAR6, VAR10, VAR20, VAR14 );
wire VAR3;
not VAR16( VAR3, VAR8 );
wire VAR11;
and VAR2( VAR11, VAR3, VAR20, VAR14 );
or VAR18( VAR19, VAR6, VAR11 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a21oi/sky130_fd_sc_hs__a21oi.behavioral.v
| 1,927 |
module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR5,
VAR13
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR13;
wire VAR4 ;
wire VAR2 ;
wire VAR11;
and VAR9 (VAR4 , VAR7, VAR1 );
nor VAR8 (VAR2 , VAR3, VAR4 );
VAR12 VAR6 (VAR11, VAR2, VAR5, VAR13);
buf VAR14 (VAR10 , VAR11 );
endmodule
|
apache-2.0
|
donnaware/AGC
|
rtl/de0/modules/ng_PAR.v
| 3,612 |
module MODULE1(
input VAR10, input VAR1, input VAR18, input [100:0] VAR15, input [ 5:0] VAR31, input [ 15:0] VAR19, output VAR38, output VAR16 );
wire VAR24 = VAR15[85]; wire VAR4 = VAR15[VAR3(VAR4)]; wire VAR26 = VAR15[36]; wire VAR35 = VAR15[94]; wire VAR37 = VAR15[4]; wire VAR5 = VAR15[13]; wire VAR8 = VAR15[41]; wire VAR34 = VAR15[42]; wire VAR27 = VAR15[43]; wire VAR11 = VAR15[29]; wire VAR2 = VAR15[96]; wire VAR22 = VAR15[11];
wire VAR21 = VAR31[4];
wire VAR7 = !(!VAR24 & VAR10);
wire VAR30 = !(!VAR4 & VAR10);
wire VAR28 = !(!(VAR26 & VAR35 & VAR37 & VAR5) & VAR10);
wire VAR9 = !(!(VAR8 & VAR34) & VAR10);
wire VAR25 = !(!VAR27 & VAR10);
wire VAR36 = !(((VAR11 | VAR21 | !VAR20) | !VAR7) & VAR10);
wire VAR12 = !(!(!VAR5 & VAR33) & !(!VAR37 & VAR39) & !(!VAR35 & VAR18) & !(!VAR26 & VAR39));
wire VAR14 = !(!VAR6 & VAR22);
reg [ 15:0] VAR23; reg VAR29; reg VAR32; reg VAR17;
always @(negedge VAR25 or negedge VAR7) begin
if(!VAR7) VAR29 <= 1'b0;
end
else VAR29 <= VAR39;
end
wire VAR33 = VAR29;
always @(negedge VAR28 or negedge VAR30) begin
if(!VAR30) VAR32 <= 1'b0;
end
else VAR32 <= VAR12;
end
wire VAR6 = VAR32;
assign VAR38 = VAR2 ? 1'VAR13 : VAR6;
always @(negedge VAR36 or negedge VAR1) begin
if(!VAR1) VAR17 <= 1'b0;
end
else VAR17 <= VAR7 & VAR20;
end
assign VAR16 = VAR17;
always @(negedge VAR9 or negedge VAR7) begin
if(!VAR7) VAR23 <= 16'h0000;
end
else VAR23 <= {VAR14,VAR19[14:0]};
end
wire VAR39 = ^VAR23[14:0]; wire VAR20 = VAR39 ^ VAR23[15];
endmodule
|
gpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/syn/verilog/sample_iterator_next.v
| 11,284 |
module MODULE1 (
VAR19,
VAR17,
VAR39,
VAR52,
VAR34,
VAR60,
VAR33,
VAR49,
VAR11,
VAR21,
VAR44,
VAR59,
VAR42,
VAR57,
VAR18,
VAR56,
VAR1,
VAR28,
VAR37,
VAR53
);
parameter VAR12 = 1'b1;
parameter VAR45 = 1'b0;
parameter VAR47 = 1'b0;
parameter VAR2 = 32'b1;
parameter VAR55 = 32'b100000;
parameter VAR46 = 32'b101111;
parameter VAR32 = 17'b11111111111111111;
parameter VAR35 = 16'b1;
parameter VAR30 = 16'b0000000000000000;
parameter VAR7 = 56'b00000000000000000000000000000000000000000000000000000000;
parameter VAR6 = 1'b1;
input VAR19;
input VAR17;
input VAR39;
output VAR52;
output VAR34;
output VAR60;
output VAR33;
input VAR49;
output VAR11;
input VAR21;
output VAR44;
output [31:0] VAR59;
input [55:0] VAR42;
output [55:0] VAR57;
output [31:0] VAR18;
input VAR56;
input [15:0] VAR1;
input [15:0] VAR28;
output [15:0] VAR37;
output [15:0] VAR53;
reg VAR52;
reg VAR34;
reg VAR60;
reg VAR11;
reg VAR44;
reg [0:0] VAR26 = 1'b0;
wire VAR10;
reg VAR58 = 1'b0;
reg VAR8 = 1'b0;
reg VAR36 = 1'b0;
reg [15:0] VAR38;
reg [15:0] VAR14;
reg [15:0] VAR5;
reg [15:0] VAR4;
reg [15:0] VAR9;
reg [15:0] VAR27;
reg [15:0] VAR51;
wire [63:0] VAR15;
wire [16:0] VAR29;
wire [16:0] VAR13;
wire [17:0] VAR16;
wire [17:0] VAR40;
wire [0:0] VAR20;
wire [15:0] VAR3;
wire [15:0] VAR54;
wire [15:0] VAR24;
wire [15:0] VAR43;
reg [0:0] VAR22;
reg VAR25;
always @ (posedge VAR19)
begin : VAR23
if (VAR17 == 1'b1) begin
VAR26 <= VAR47;
end else begin
VAR26 <= VAR22;
end
end
always @ (posedge VAR19)
begin : VAR41
if (VAR17 == 1'b1) begin
VAR58 <= VAR45;
end else begin
if (((VAR47 == VAR26) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45)) | ~(VAR12 == VAR56)))) begin
VAR58 <= VAR10;
end
end
end
always @ (posedge VAR19)
begin : VAR50
if (VAR17 == 1'b1) begin
VAR8 <= VAR45;
end else begin
if (((VAR47 == VAR26) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45)) | ~(VAR12 == VAR56)))) begin
VAR8 <= VAR58;
end
end
end
always @ (posedge VAR19)
begin : VAR31
if (VAR17 == 1'b1) begin
VAR36 <= VAR45;
end else begin
if (((VAR47 == VAR26) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45)) | ~(VAR12 == VAR56)))) begin
VAR36 <= VAR8;
end
end
end
always @(posedge VAR19)
begin
if (((VAR47 == VAR26) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56))) begin
VAR9 <= VAR4;
VAR27 <= VAR9;
VAR14 <= VAR38;
VAR5 <= VAR14;
end
end
always @(posedge VAR19)
begin
if (((VAR47 == VAR26) & (VAR12 == VAR10) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56))) begin
VAR4 <= VAR1;
VAR38 <= VAR28;
end
end
always @(posedge VAR19)
begin
if (((VAR47 == VAR26) & (VAR12 == VAR8) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56))) begin
VAR51 <= {{VAR42[VAR46 : VAR55]}};
end
end
always @ (VAR39 or VAR26 or VAR10 or VAR8 or VAR36 or VAR21 or VAR56)
begin
if (((~(VAR12 == VAR39) & (VAR47 == VAR26) & (VAR12 == VAR10)) | ((VAR47 == VAR26) & (VAR12 == VAR36) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56)))) begin
VAR52 = VAR12;
end else begin
VAR52 = VAR45;
end
end
always @ (VAR39 or VAR26 or VAR10 or VAR58 or VAR8 or VAR36)
begin
if ((~(VAR12 == VAR39) & (VAR47 == VAR26) & (VAR45 == VAR10) & (VAR45 == VAR58) & (VAR45 == VAR8) & (VAR45 == VAR36))) begin
VAR34 = VAR12;
end else begin
VAR34 = VAR45;
end
end
always @ (VAR39 or VAR26 or VAR10 or VAR8 or VAR21 or VAR56)
begin
if (((VAR47 == VAR26) & (VAR12 == VAR10) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56))) begin
VAR60 = VAR12;
end else begin
VAR60 = VAR45;
end
end
always @ (VAR39 or VAR10 or VAR58 or VAR8)
begin
if (((VAR45 == VAR10) & (VAR45 == VAR58) & (VAR45 == VAR8) & (VAR45 == VAR39))) begin
VAR25 = VAR12;
end else begin
VAR25 = VAR45;
end
end
always @ (VAR39 or VAR26 or VAR10 or VAR8 or VAR21 or VAR56)
begin
if (((VAR47 == VAR26) & (VAR12 == VAR10) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56))) begin
VAR11 = VAR12;
end else begin
VAR11 = VAR45;
end
end
always @ (VAR39 or VAR26 or VAR10 or VAR8 or VAR21 or VAR56)
begin
if (((VAR47 == VAR26) & (VAR12 == VAR8) & ~(((VAR12 == VAR10) & (VAR39 == VAR45)) | ((VAR12 == VAR8) & (VAR21 == VAR45))) & (VAR12 == VAR56))) begin
VAR44 = VAR12;
end else begin
VAR44 = VAR45;
end
end
always @ (VAR39 or VAR26 or VAR10 or VAR8 or VAR21 or VAR56 or VAR25)
begin
case (VAR26)
VAR47 :
VAR22 = VAR47;
default :
VAR22 = 'VAR48;
endcase
end
assign VAR24 = ((VAR20)? VAR27: VAR54);
assign VAR43 = ((VAR20)? VAR3: VAR30);
assign VAR10 = VAR39;
assign VAR37 = VAR24;
assign VAR53 = VAR43;
assign VAR59 = VAR15;
assign VAR57 = VAR7;
assign VAR33 = VAR45;
assign VAR18 = VAR2;
assign VAR3 = (VAR5 + VAR35);
assign VAR54 = (VAR27 + VAR35);
assign VAR15 = (VAR1);
assign VAR29 = (VAR51);
assign VAR13 = (VAR29 + VAR32);
assign VAR16 = (VAR5);
assign VAR40 = (VAR13);
assign VAR20 = ((VAR16) < (VAR40)? 1'b1: 1'b0);
endmodule
|
lgpl-3.0
|
Monash-2015-Ultrasonic/Logs
|
Final System Code/SYSTEMV3/Source/IP/MULT/MULT_bb.v
| 3,474 |
module MODULE1 (
VAR2,
VAR1);
input [12:0] VAR2;
output [25:0] VAR1;
endmodule
|
gpl-2.0
|
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axisc_upsizer.v
| 14,845 |
module MODULE1 #
(
parameter VAR36 = "VAR41",
parameter integer VAR15 = 32,
parameter integer VAR7 = 96,
parameter integer VAR2 = 1,
parameter integer VAR40 = 1,
parameter integer VAR11 = 1,
parameter integer VAR32 = 3,
parameter [31:0] VAR44 = 32'hFF ,
parameter integer VAR55 = 3 )
(
input wire VAR48,
input wire VAR23,
input wire VAR18,
input wire VAR59,
output wire VAR20,
input wire [VAR15-1:0] VAR37,
input wire [VAR15/8-1:0] VAR57,
input wire [VAR15/8-1:0] VAR54,
input wire VAR42,
input wire [VAR2-1:0] VAR52,
input wire [VAR40-1:0] VAR17,
input wire [VAR11-1:0] VAR49,
output wire VAR45,
input wire VAR22,
output wire [VAR7-1:0] VAR56,
output wire [VAR7/8-1:0] VAR9,
output wire [VAR7/8-1:0] VAR58,
output wire VAR25,
output wire [VAR2-1:0] VAR39,
output wire [VAR40-1:0] VAR13,
output wire [VAR32-1:0] VAR46
);
localparam VAR60 = VAR44[0];
localparam VAR1 = VAR44[1];
localparam VAR47 = VAR44[2];
localparam VAR10 = VAR44[3];
localparam VAR21 = VAR44[4];
localparam VAR67 = VAR44[5];
localparam VAR30 = VAR44[6];
localparam VAR68 = VAR44[7];
localparam VAR31 = VAR15/8;
localparam VAR8 = VAR7/8;
localparam VAR26 = 3'b000; localparam VAR12 = 3'b001; localparam VAR62 = 3'b101; localparam VAR50 = 3'b011; localparam VAR43 = 3'b010;
reg [2:0] state;
reg [VAR7-1:0] VAR65;
reg [VAR8-1:0] VAR19;
reg [VAR8-1:0] VAR14;
reg VAR28;
reg [VAR2-1:0] VAR53;
reg [VAR40-1:0] VAR5;
reg [VAR32-1:0] VAR16;
wire [VAR55-1:0] VAR29;
reg [VAR55-1:0] VAR51;
wire VAR61;
reg [VAR15-1:0] VAR38;
reg [VAR31-1:0] VAR4;
reg [VAR31-1:0] VAR64;
reg VAR33;
reg [VAR2-1:0] VAR3;
reg [VAR40-1:0] VAR34;
reg [VAR11-1:0] VAR63;
wire VAR35;
wire VAR27;
wire VAR24;
assign VAR20 = state[0];
assign VAR45 = state[1];
always @(posedge VAR48) begin
if (VAR23) begin
state <= VAR26;
end else if (VAR18) begin
case (state)
VAR26: begin
state <= VAR12;
end
VAR12: begin
if (VAR59 & VAR24 & ~VAR51[0]) begin
state <= VAR43;
end
else if (VAR59 & VAR61) begin
state <= VAR50;
end
else if (VAR59) begin
state <= VAR62;
end
else begin
state <= VAR12;
end
end
VAR62: begin
if (VAR59 & (VAR24 | VAR33)) begin
state <= VAR43;
end
else if ((~VAR59 & VAR33) | (VAR59 & VAR61)) begin
state <= VAR50;
end
else if (VAR59 & ~VAR61) begin
state <= VAR62;
end
else begin
state <= VAR12;
end
end
VAR50: begin
if (VAR22 & VAR59) begin
state <= VAR62;
end
else if ( ~VAR22 & VAR59) begin
state <= VAR43;
end
else if ( VAR22 & ~VAR59) begin
state <= VAR12;
end
else begin
state <= VAR50;
end
end
VAR43: begin
if (VAR22) begin
state <= VAR62;
end
else begin
state <= VAR43;
end
end
default: begin
state <= VAR12;
end
endcase end
end
assign VAR56 = VAR65;
assign VAR9 = VAR19;
assign VAR58 = VAR14;
assign VAR46 = VAR16;
generate
genvar VAR6;
always @(posedge VAR48) begin
if (VAR18) begin
VAR65[0*VAR15+:VAR15] <= VAR29[0] ? VAR38
: VAR65[0*VAR15+:VAR15];
VAR16[0*VAR11+:VAR11] <= VAR29[0] ? VAR63
: VAR16[0*VAR11+:VAR11];
VAR19[0*VAR31+:VAR31] <= VAR29[0] ? VAR4
: VAR19[0*VAR31+:VAR31];
VAR14[0*VAR31+:VAR31] <= VAR29[0] ? VAR64
: VAR14[0*VAR31+:VAR31];
end
end
for (VAR6 = 1; VAR6 < VAR55-1; VAR6 = VAR6 + 1) begin : VAR66
always @(posedge VAR48) begin
if (VAR18) begin
VAR65[VAR6*VAR15+:VAR15] <= VAR29[VAR6] ? VAR38
: VAR65[VAR6*VAR15+:VAR15];
VAR16[VAR6*VAR11+:VAR11] <= VAR29[VAR6] ? VAR63
: VAR16[VAR6*VAR11+:VAR11];
VAR19[VAR6*VAR31+:VAR31] <= VAR29[0] ? {VAR31{1'b0}}
: VAR29[VAR6] ? VAR4 : VAR19[VAR6*VAR31+:VAR31];
VAR14[VAR6*VAR31+:VAR31] <= VAR29[0] ? {VAR31{1'b0}}
: VAR29[VAR6] ? VAR64 : VAR14[VAR6*VAR31+:VAR31];
end
end
end
always @(posedge VAR48) begin
if (VAR18) begin
VAR65[(VAR55-1)*VAR15+:VAR15] <= (state == VAR12) | (state == VAR62)
? VAR37 : VAR65[(VAR55-1)*VAR15+:VAR15];
VAR16[(VAR55-1)*VAR11+:VAR11] <= (state == VAR12) | (state == VAR62)
? VAR49 : VAR16[(VAR55-1)*VAR11+:VAR11];
VAR19[(VAR55-1)*VAR31+:VAR31] <= (VAR29[0] && VAR55 > 2) | (state == VAR62 & VAR33) | (VAR24 & (state == VAR62 | state == VAR12))
? {VAR31{1'b0}} : (state == VAR12) | (state == VAR62)
? VAR57 : VAR19[(VAR55-1)*VAR31+:VAR31];
VAR14[(VAR55-1)*VAR31+:VAR31] <= (VAR29[0] && VAR55 > 2) | (state == VAR62 & VAR33) | (VAR24 & (state == VAR62| state == VAR12))
? {VAR31{1'b0}} : (state == VAR12) | (state == VAR62)
? VAR54 : VAR14[(VAR55-1)*VAR31+:VAR31];
end
end
endgenerate
assign VAR29 = (state == VAR62) ? VAR51 : {VAR55{1'b0}};
always @(posedge VAR48) begin
if (VAR23) begin
VAR51[0] <= 1'b1;
VAR51[1+:VAR55-1] <= {VAR55{1'b0}};
end else if (VAR18) begin
VAR51[0] <= VAR45 & VAR22 ? 1'b1
: (state == VAR62) ? 1'b0 : VAR51[0];
VAR51[1+:VAR55-1] <= VAR45 & VAR22 ? {VAR55-1{1'b0}}
: (state == VAR62) ? VAR51[0+:VAR55-1] : VAR51[1+:VAR55-1];
end
end
assign VAR61 = (VAR51[VAR55-2] && (state == VAR62)) | VAR51[VAR55-1];
always @(posedge VAR48) begin
if (VAR18) begin
VAR38 <= VAR20 ? VAR37 : VAR38;
VAR4 <= VAR20 ? VAR57 : VAR4;
VAR64 <= VAR20 ? VAR54 : VAR64;
VAR33 <= (!VAR21) ? 1'b0 : VAR20 ? VAR42 : VAR33;
VAR3 <= (VAR20 & VAR59) ? VAR52 : VAR3;
VAR34 <= (VAR20 & VAR59) ? VAR17 : VAR34;
VAR63 <= VAR20 ? VAR49 : VAR63;
end
end
assign VAR25 = VAR28;
always @(posedge VAR48) begin
if (VAR18) begin
VAR28 <= (state == VAR50 | state == VAR43) ? VAR28 :
(state == VAR62 & VAR33 ) ? 1'b1 :
(VAR24 & (state == VAR12)) ? 1'b0 :
(VAR24 & (state == VAR62)) ? VAR33 :
VAR42;
end
end
assign VAR39 = VAR53;
assign VAR13 = VAR5;
always @(posedge VAR48) begin
if (VAR18) begin
VAR53 <= VAR29[0] ? VAR3 : VAR53;
VAR5 <= VAR29[0] ? VAR34 : VAR5;
end
end
assign VAR35 = VAR67 ? (VAR52 == VAR3) : 1'b1;
assign VAR27 = VAR30 ? (VAR17 == VAR34) : 1'b1;
assign VAR24 = (~VAR35 | ~VAR27) ? 1'b1 : 1'b0;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/xnor3/sky130_fd_sc_hs__xnor3.symbol.v
| 1,253 |
module MODULE1 (
input VAR2,
input VAR6,
input VAR4,
output VAR5
);
supply1 VAR1;
supply0 VAR3;
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ecc/ecc_merge_enc.v
| 5,931 |
module MODULE1
parameter VAR12 = 100,
parameter VAR3 = 64,
parameter VAR27 = 72,
parameter VAR6 = 4,
parameter VAR8 = 1,
parameter VAR1 = 64,
parameter VAR14 = 72,
parameter VAR19 = 8,
parameter VAR15 = 4
)
(
VAR10, VAR21,
clk, rst, VAR2, VAR20, VAR13, VAR9, VAR26
);
input clk;
input rst;
input [2*VAR15*VAR3-1:0] VAR2;
input [2*VAR15*VAR1/8-1:0] VAR20;
input [2*VAR15*VAR1-1:0] VAR13;
reg [2*VAR15*VAR3-1:0] VAR23;
reg [2*VAR15*VAR1/8-1:0] VAR29;
reg [2*VAR15*VAR1-1:0] VAR18;
wire [2*VAR15*VAR3-1:0] VAR11;
genvar VAR4;
genvar VAR5;
generate
for (VAR4=0; VAR4<2*VAR15; VAR4=VAR4+1) begin : VAR22
for (VAR5=0; VAR5<VAR1/8; VAR5=VAR5+1) begin : VAR28
assign VAR11[VAR4*VAR3+VAR5*8+:8] =
VAR20[VAR4*VAR1/8+VAR5]
? VAR13[VAR4*VAR1+VAR5*8+:8]
: VAR2[VAR4*VAR3+VAR5*8+:8];
end
if (VAR3 > VAR1)
assign VAR11[(VAR4+1)*VAR3-1-:VAR3-VAR1]=
VAR2[(VAR4+1)*VAR3-1-:VAR3-VAR1];
end
endgenerate
input [VAR27*VAR19-1:0] VAR9;
input [2*VAR15-1:0] VAR26;
reg [2*VAR15-1:0] VAR25;
output reg [2*VAR15*VAR14-1:0] VAR10;
reg [2*VAR15*VAR14-1:0] VAR17;
genvar VAR24;
integer VAR16;
generate
for (VAR24=0; VAR24<2*VAR15; VAR24=VAR24+1) begin : VAR7
always @(VAR9 or VAR11 or VAR25) begin
VAR17[VAR24*VAR14+:VAR14] =
{{VAR14-VAR3{1'b0}},
VAR11[VAR24*VAR3+:VAR3]};
for (VAR16=0; VAR16<VAR19; VAR16=VAR16+1)
if (~VAR25[VAR24])
VAR17[VAR24*VAR14+VAR27-VAR16-1] =
^(VAR11[VAR24*VAR3+:VAR1] &
VAR9[VAR16*VAR27+:VAR1]);
end
end
endgenerate
always @(posedge clk) VAR10 <= VAR17;
output wire[2*VAR15*VAR14/8-1:0] VAR21;
assign VAR21 = {2*VAR15*VAR14/8{1'b0}};
endmodule
|
lgpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.functional.v
| 1,390 |
module MODULE1( VAR13, VAR8, VAR12, VAR14, VAR5 );
input VAR14, VAR5, VAR13, VAR12;
output VAR8;
wire VAR7;
not VAR2( VAR7, VAR14 );
wire VAR9;
not VAR6( VAR9, VAR5 );
wire VAR3;
not VAR11( VAR3, VAR13 );
wire VAR10;
not VAR4( VAR10, VAR12 );
or VAR1( VAR8, VAR7, VAR9, VAR3, VAR10 );
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_trn_v5_gtp_x1_125/source/pcie_blk_ll_tx_arb.v
| 10,704 |
module MODULE1
(
input clk,
input VAR33,
output reg [63:0] VAR22,
output reg VAR38,
output reg VAR29,
output [7:0] VAR30,
output reg VAR26 = 1'b1,
output reg VAR11 = 1'b1,
input VAR31,
input [63:0] VAR9,
input [7:0] VAR25,
input VAR14,
input VAR6,
input VAR41,
input VAR8,
output reg VAR34 = 1'b1,
output VAR39,
input [63:0] VAR19,
input VAR20,
input VAR3,
input VAR28,
input VAR10,
output reg VAR7 = 1'b1
);
reg VAR16 = 1'b0;
reg VAR5 = 1'b0;
wire VAR23;
wire VAR36;
wire VAR32;
wire VAR2;
wire VAR4;
reg [63:0] VAR35;
reg VAR12;
reg VAR13;
reg VAR15 = 1'b1;
reg VAR21;
reg VAR24 = 1'b0;
wire VAR37;
wire VAR1;
wire VAR27;
reg VAR40;
assign VAR39 = 1'b1;
always @(posedge clk) begin
if (!VAR33) begin
VAR34 <= #VAR17 1'b1;
VAR7 <= #VAR17 1'b1;
end else begin
if (VAR16 || ((!VAR4 || VAR2) &&
!VAR10)) begin
VAR7 <= #VAR17 ((VAR24 && !VAR1) || VAR27);
VAR34 <= #VAR17 1'b1;
end else begin
VAR7 <= #VAR17 1'b1;
VAR34 <= #VAR17 ((VAR24 && !VAR1) || VAR27);
end
end
end
assign VAR32 = !VAR34 && !VAR41 && !VAR14;
assign VAR2 = !VAR34 && !VAR41 &&
(!VAR6 || !VAR8);
assign VAR4 = VAR5 ||
(!VAR34 && !VAR41 && !VAR14);
assign VAR23 = !VAR7 && !VAR10 && !VAR3;
assign VAR36 = !VAR7 && !VAR10 && !VAR28;
always @(posedge clk) begin
if (!VAR33) begin
VAR5 <= #VAR17 1'b0;
VAR16 <= #VAR17 1'b0;
end else begin
if (VAR32) begin
VAR5 <= #VAR17 1'b1;
end else if (VAR2) begin
VAR5 <= #VAR17 1'b0;
end
if (VAR23) begin
VAR16 <= #VAR17 1'b1;
end else if (VAR36) begin
VAR16 <= #VAR17 1'b0;
end
end
end
always @(posedge clk) begin
if (!VAR33) begin
VAR24 <= #VAR17 1'b0;
end else begin
if (!VAR34 && !VAR41 && VAR37) begin
VAR35 <= #VAR17 VAR9;
VAR12 <= #VAR17 VAR14;
VAR13 <= #VAR17 VAR6 && VAR8;
VAR15 <= #VAR17 VAR8;
VAR21 <= #VAR17 VAR25[0];
VAR24 <= #VAR17 VAR4;
end else if (!VAR7 && !VAR10 && VAR37) begin
VAR35 <= #VAR17 VAR19;
VAR12 <= #VAR17 VAR3;
VAR13 <= #VAR17 VAR28;
VAR15 <= #VAR17 1'b1;
VAR21 <= #VAR17 VAR20;
VAR24 <= #VAR17 1'b1;
end else if (VAR1) begin
VAR24 <= #VAR17 1'b0;
end
end
end
assign VAR37 = !VAR11 && VAR31;
assign VAR1 = VAR24 && !VAR11 && !VAR31;
assign VAR27 = VAR37 &&
((!VAR10 && !VAR7) ||
(!VAR41 && !VAR34));
always @(posedge clk) begin
if (!VAR33) begin
VAR11 <= #VAR17 1'b1;
end else begin
casex ({VAR1,
(!VAR10 && !VAR7 && !VAR37),
(!VAR41 && !VAR34 && !VAR37)})
3'VAR18: begin
VAR22 <= #VAR17 VAR35;
VAR38 <= #VAR17 VAR12;
VAR29 <= #VAR17 VAR13;
VAR26 <= #VAR17 VAR15;
VAR40 <= #VAR17 VAR21;
end
3'b010: begin
VAR22 <= #VAR17 VAR19;
VAR38 <= #VAR17 VAR3;
VAR29 <= #VAR17 VAR28;
VAR26 <= #VAR17 1'b1;
VAR40 <= #VAR17 VAR20;
end
3'b001: begin
VAR22 <= #VAR17 VAR9;
VAR38 <= #VAR17 VAR14;
VAR29 <= #VAR17 VAR6 && VAR8;
VAR26 <= #VAR17 VAR8;
VAR40 <= #VAR17 VAR25;
end
3'b000: ; default: begin
end
endcase
if (VAR1 || (!VAR10 && !VAR7) ||
(!VAR41 && !VAR34 && VAR4)) begin
VAR11 <= #VAR17 1'b0;
end else if (!VAR31) begin
VAR11 <= #VAR17 1'b1;
end
end
end
assign VAR30 = {4'b0000, {4{VAR40}}};
endmodule
|
lgpl-3.0
|
ineganov/bare_system
|
hard/alu.v
| 4,418 |
module MODULE1( input [6:0] VAR25,
input [31:0] VAR14,
input [31:0] VAR9,
input [4:0] VAR24,
output [31:0] VAR3,
output VAR26 );
wire VAR11 = VAR25[3]; wire [31:0] VAR12; wire [31:0] VAR28 = VAR14 + VAR12 + VAR11;
wire [31:0] VAR23;
VAR2 VAR4( .VAR17(VAR25[3]),
.VAR21( VAR9),
.VAR7(~VAR9),
.VAR3 (VAR12) );
wire [4:0] VAR22;
VAR2 #(5) VAR15( .VAR17 (VAR25[6]),
.VAR21(VAR24),
.VAR7(VAR14[4:0]),
.VAR3 (VAR22));
wire[31:0] VAR1;
MODULE2 MODULE1( .VAR17(VAR25[5:4]),
.VAR16( VAR22 ),
.VAR14( VAR9 ),
.VAR3( VAR1 ) );
assign VAR23 = {31'b0, VAR28[31]};
VAR13 VAR18( .VAR17 ( VAR25[2:0] ),
.VAR21( VAR14 & VAR12 ),
.VAR7( VAR14 | VAR12 ),
.VAR6( VAR14 ^ VAR12 ),
.VAR5(~(VAR14 | VAR12) ),
.VAR27( VAR28 ),
.VAR19( 0 ), .VAR8( VAR1 ),
.VAR10( VAR23 ),
.VAR3 ( VAR3 ) );
assign VAR26 = {VAR3 == 32'b0};
endmodule
module MODULE2( input [1:0] VAR17,
input [4:0] VAR16,
input signed [31:0] VAR14,
output [31:0] VAR3 );
assign VAR3 = VAR17[1] ? (VAR17[0] ? VAR14 >>> VAR16 : VAR14 <<< VAR16) :
(VAR17[0] ? VAR14 >> VAR16 : VAR14 << VAR16);
endmodule
|
gpl-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ui/ui_rd_data.v
| 18,487 |
module MODULE1 #
(
parameter VAR40 = 100,
parameter VAR9 = 256,
parameter VAR48 = "VAR78",
parameter VAR89 = 2 ,
parameter VAR53 = "VAR4"
)
(
VAR70, VAR95, VAR23, VAR82,
VAR16, VAR47, VAR57, VAR29,
rst, clk, VAR72, VAR32, VAR69, VAR22,
VAR88, VAR35, VAR38
);
input rst;
input clk;
output wire VAR70;
output wire [3:0] VAR95;
reg [5:0] VAR25;
reg VAR31;
assign VAR70 = VAR31;
wire VAR94;
wire VAR2;
reg [5:0] VAR51;
generate begin : VAR93
wire VAR21 = ~VAR31 || VAR94;
wire VAR75 =
~rst && (VAR31 || (VAR25[4:0] == 5'h1f));
always @(VAR25 or rst or VAR2
or VAR21) begin
VAR51 = VAR25;
if (rst) VAR51 = 6'b0;
end
else if (VAR21) VAR51 =
VAR25 + 6'h1 + VAR2;
end
end
endgenerate
assign VAR95 = VAR25[3:0];
input VAR72;
input [3:0] VAR32;
input VAR69;
input VAR22;
input [VAR9-1:0] VAR88;
output reg VAR23;
output reg VAR82;
output reg [VAR9-1:0] VAR16;
input [3:0] VAR35;
reg [2*VAR89-1:0] VAR62 = 'b0;
output wire [2*VAR89-1:0] VAR47;
assign VAR47 = VAR62;
input VAR38;
output wire VAR57;
output wire [3:0] VAR29;
localparam VAR71 = VAR9 + (VAR48 == "VAR78" ? 0 : 2*VAR89);
localparam VAR65 = (VAR71/6);
localparam VAR30 = VAR71 % 6;
localparam VAR24 = VAR65 + ((VAR30 == 0 ) ? 0 : 1);
localparam VAR76 = (VAR24*6);
generate
if (VAR53 == "VAR79") begin : VAR87
assign VAR94 = 1'b0;
assign VAR2 = 1'b0;
assign VAR57 = 1'b0;
reg [3:0] VAR52;
wire [3:0] VAR96 =
rst
? 4'b0
: VAR52 + {3'b0, VAR38};
always @(posedge clk) VAR52 <=
assign VAR29 = VAR96;
if (VAR48 == "VAR78") begin : VAR68
always @(VAR88) VAR16 = VAR88;
always @(VAR72) VAR23 = VAR72;
always @(VAR22) VAR82 = VAR22;
end
else begin : VAR6
end
end
else begin : VAR18
wire VAR28 = ~VAR31 || VAR72;
wire [4:0] VAR92 = {VAR32, VAR69};
wire [1:0] VAR8;
begin : VAR91
wire [4:0] VAR58 = VAR31
? VAR92
: VAR25[4:0];
reg [4:0] VAR45;
always @(posedge clk) VAR45 <=
wire [1:0] VAR97;
reg VAR37;
wire [1:0] VAR56 =
VAR31
? {VAR22, ~(VAR69
? VAR37
: VAR97[0])}
: 2'b0;
reg [1:0] VAR50;
always @(posedge clk) VAR50 <=
reg VAR77;
VAR55
.VAR5(64'h0000000000000000),
.VAR33(64'h0000000000000000),
.VAR54(64'h0000000000000000)
) VAR90 (
.VAR12(VAR8),
.VAR43(),
.VAR10(VAR97),
.VAR85(),
.VAR84(VAR50),
.VAR41(2'b0),
.VAR26(VAR50),
.VAR86(VAR50),
.VAR1(VAR25[4:0]),
.VAR83(5'b0),
.VAR7(VAR58),
.VAR27(VAR45),
.VAR63(VAR77),
.VAR39(clk)
);
end
wire [VAR76-1:0] VAR74;
begin : VAR60
wire [VAR76-1:0] VAR59;
if (VAR30 == 0)
if (VAR48 == "VAR78")
assign VAR59 = VAR88;
end
else
assign VAR59 = {VAR35, VAR88};
end
else
if (VAR48 == "VAR78")
assign VAR59 = {{6-VAR30{1'b0}}, VAR88};
else
assign VAR59 =
{{6-VAR30{1'b0}}, VAR35, VAR88};
reg [4:0] VAR20;
genvar VAR73;
for (VAR73=0; VAR73<VAR24; VAR73=VAR73+1) begin : VAR19
VAR55
.VAR5(64'h0000000000000000),
.VAR33(64'h0000000000000000),
.VAR54(64'h0000000000000000)
) VAR90 (
.VAR12(VAR74[((VAR73*6)+4)+:2]),
.VAR43(VAR74[((VAR73*6)+2)+:2]),
.VAR10(VAR74[((VAR73*6)+0)+:2]),
.VAR85(),
.VAR84(VAR59[((VAR73*6)+4)+:2]),
.VAR41(VAR59[((VAR73*6)+2)+:2]),
.VAR26(VAR59[((VAR73*6)+0)+:2]),
.VAR86(2'b0),
.VAR1(VAR20[4:0]),
.VAR83(VAR20[4:0]),
.VAR7(VAR20[4:0]),
.VAR27(VAR92),
.VAR63(VAR28),
.VAR39(clk)
);
end end
wire VAR44 = (VAR8[0] == VAR25[5]);
wire VAR66 = VAR72 && (VAR92[4:0] == VAR25[4:0]);
assign VAR94 =
VAR31 && (VAR66 || VAR44);
wire VAR36 = VAR66 ? VAR22 : VAR8[1];
assign VAR2 =
VAR94 && VAR36 && ~VAR25[0];
wire [VAR9-1:0] VAR80 =
VAR66
? VAR88
: VAR74[VAR9-1:0];
if (VAR48 != "VAR78") begin : VAR14
wire [3:0] VAR64 =
VAR66
? VAR35
: VAR74[VAR9+:4];
always @(posedge clk) VAR62 <=
end
reg VAR67;
wire VAR81 = VAR67 && VAR82; reg [4:0] VAR11;
wire [4:0] VAR49 = VAR11 - 5'b1;
wire [4:0] VAR15 = VAR11 + 5'b1;
begin : VAR13
reg [4:0] VAR42;
always @(VAR81 or VAR11 or VAR38 or rst or VAR49 or VAR15) begin
VAR42 = VAR11;
if (rst) VAR42 = 5'b0;
end
else case ({VAR38, VAR81})
2'b01 : VAR42 = VAR49;
2'b10 : VAR42 = VAR15;
endcase end
assign VAR57 = VAR42[4];
VAR34: cover property (@(posedge clk) (~rst && VAR57));
VAR17: cover property (@(posedge clk)
(~rst && VAR38 && VAR81 && (VAR11 == 5'hf)));
VAR3: assert property (@(posedge clk)
(rst || !((VAR11 == 5'b0) && (VAR42 == 5'h1f))));
VAR46: assert property (@(posedge clk)
(rst || !((VAR11 == 5'h10) && (VAR42 == 5'h11))));
end
reg [3:0] VAR52;
assign VAR29 = VAR52;
begin : VAR61
reg [3:0] VAR96;
always @(VAR38 or VAR52 or rst) begin
VAR96 = VAR52;
if (rst) VAR96 = 4'b0;
end
else if (VAR38) VAR96 =
VAR52 + 4'h1;
end
always @(posedge clk) VAR52 <=
end end endgenerate
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/maj3/sky130_fd_sc_ms__maj3.symbol.v
| 1,284 |
module MODULE1 (
input VAR7,
input VAR2,
input VAR5,
output VAR4
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
lvd2/zxevo
|
unsupported/solegstar/fpga/current/vga/vga_synch.v
| 1,234 |
module MODULE1(
input clk,
output reg VAR2,
output reg VAR5,
input wire VAR3
);
localparam VAR4 = 10'd106;
localparam VAR7 = 10'd159;
localparam VAR6 = 10'd896;
reg [9:0] VAR1;
begin
begin
end
begin
end
begin
end
|
gpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits_block.v
| 1,241 |
module MODULE1
(
VAR7,
VAR5
);
input [17:0] VAR7; output [8:0] VAR5;
wire [8:0] VAR1;
VAR6 VAR4 (.VAR3(VAR7), .VAR2(VAR1) );
assign VAR5 = VAR1;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfrbp/sky130_fd_sc_ms__dfrbp.behavioral.pp.v
| 2,354 |
module MODULE1 (
VAR1 ,
VAR21 ,
VAR19 ,
VAR11 ,
VAR14,
VAR2 ,
VAR9 ,
VAR22 ,
VAR8
);
output VAR1 ;
output VAR21 ;
input VAR19 ;
input VAR11 ;
input VAR14;
input VAR2 ;
input VAR9 ;
input VAR22 ;
input VAR8 ;
wire VAR5 ;
wire VAR13 ;
reg VAR17 ;
wire VAR23 ;
wire VAR6;
wire VAR15 ;
wire VAR12 ;
wire VAR20 ;
wire VAR10 ;
not VAR18 (VAR13 , VAR6 );
VAR3 VAR7 (VAR5 , VAR23, VAR15, VAR13, VAR17, VAR2, VAR9);
assign VAR20 = ( VAR12 && ( VAR6 === 1'b1 ) );
assign VAR10 = ( VAR12 && ( VAR14 === 1'b1 ) );
buf VAR16 (VAR1 , VAR5 );
not VAR4 (VAR21 , VAR5 );
endmodule
|
apache-2.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_multiplexer_128.v
| 16,560 |
module MODULE1
parameter VAR45 = 128,
parameter VAR49 = 12,
parameter VAR81 = 5, parameter VAR69 = "VAR105"
)
(
input VAR121,
input VAR20,
input [VAR49-1:0] VAR117, input [(VAR49*VAR77)-1:0] VAR106, input [(VAR49*VAR15)-1:0] VAR70, input [(VAR49*VAR45)-1:0] VAR108, output [VAR49-1:0] VAR47, output [VAR49-1:0] VAR2,
input [VAR49-1:0] VAR112, input [(VAR49*2)-1:0] VAR67, input [(VAR49*VAR77)-1:0] VAR71, input [(VAR49*VAR15)-1:0] VAR59, output [VAR49-1:0] VAR57,
output [5:0] VAR39, output VAR40, input [VAR81-1:0] VAR115, input VAR111,
output VAR90, input VAR1,
output VAR46,
output [VAR45-1:0] VAR6,
output VAR14,
output [VAR58(VAR45/32)-1:0] VAR22,
output VAR24,
output [VAR58(VAR45/32)-1:0] VAR95,
input VAR50,
output VAR78,
output [VAR32-1:0] VAR100,
output [VAR104-1:0] VAR3,
output [VAR77-1:0] VAR61,
output [VAR15-1:0] VAR62,
output [VAR88-1:0] VAR114,
output [VAR9-1:0] VAR120,
output [VAR35-1:0] VAR80,
output [VAR33-1:0] VAR13,
output VAR52,
input VAR68);
localparam VAR25 = 6;
reg VAR119=VAR64, VAR119=VAR64;
reg VAR34=0, VAR34=0;
reg [9:0] VAR17=0, VAR17=0;
reg [3:0] VAR43=0, VAR43=0;
reg [VAR81-1:0] VAR56=0, VAR56=0;
reg [61:0] VAR82=62'd0, VAR82=62'd0;
reg VAR53=0, VAR53=0;
reg [9:0] VAR98=0, VAR98=0;
reg VAR75=0, VAR75=0;
reg VAR63=0, VAR63=0;
reg VAR10=0, VAR10=0;
reg [VAR49-1:0] VAR84=0, VAR84=0;
reg VAR79, VAR79;
wire VAR93;
wire [3:0] VAR96;
wire VAR12;
wire [3:0] VAR99;
wire VAR113;
wire [3:0] VAR54;
wire [11:0] VAR37 = (VAR54*VAR45); wire [63:0] VAR38;
wire [9:0] VAR74;
wire [1:0] VAR48;
wire [63:0] VAR73;
wire [9:0] VAR72;
wire [VAR45-1:0] VAR29;
wire [VAR45-1:0] VAR110;
reg [3:0] VAR30=0, VAR30=0;
reg [61:0] VAR89=62'd0, VAR89=62'd0;
reg [9:0] VAR85=0, VAR85=0;
reg [1:0] VAR42=0, VAR42=0;
reg [3:0] VAR18=0, VAR18=0;
reg [61:0] VAR7=62'd0, VAR7=62'd0;
reg [9:0] VAR66=0, VAR66=0;
reg [VAR45-1:0] VAR36={VAR45{1'd0}}, VAR36={VAR45{1'd0}};
assign VAR38 = VAR71[VAR96 * VAR77 +: VAR77];
assign VAR74 = VAR59[VAR96 * VAR15 +: VAR15];
assign VAR48 = VAR67[VAR96 * 2 +: 2];
assign VAR73 = VAR106[VAR99 * VAR77 +: VAR77];
assign VAR72 = VAR70[VAR99 * VAR15 +: VAR15];
assign VAR29 = VAR108[VAR54 * VAR45 +: VAR45];
reg [3:0] VAR76=VAR94, VAR76=VAR94;
reg [VAR49-1:0] VAR26=0, VAR26=0;
reg [VAR49-1:0] VAR27=0, VAR27=0;
reg VAR103=0, VAR103=0;
reg [5:0] VAR5=0, VAR5=0;
reg [61:0] VAR65=62'd0, VAR65=62'd0;
reg VAR51=0, VAR51=0;
reg [9:0] VAR91=0, VAR91=0;
reg VAR83=0, VAR83=0;
reg VAR118=0, VAR118=0;
reg [VAR81-1:0] VAR11=0, VAR11=0;
reg [VAR25-1:0] VAR87=0, VAR87=0;
reg [(VAR25*4)-1:0] VAR28=0, VAR28=0;
reg [(VAR25*8)-1:0] VAR23=0, VAR23=0;
reg [(VAR25*62)-1:0] VAR31=0, VAR31=0;
reg [VAR25-1:0] VAR122=0, VAR122=0;
reg [(VAR25*10)-1:0] VAR41=0, VAR41=0;
reg [VAR25-1:0] VAR123=0, VAR123=0;
reg [VAR25-1:0] VAR19=0, VAR19=0;
reg [VAR25-1:0] VAR16=0, VAR16=0;
reg [VAR25-1:0] VAR97=0, VAR97=0;
assign VAR47 = VAR84;
assign VAR2 = VAR27;
assign VAR57 = VAR26;
assign VAR39 = {VAR42, VAR30};
assign VAR40 = VAR118;
assign VAR90 = VAR79;
assign VAR113 = (VAR93 & VAR111 & VAR1);
VAR101 #(.VAR49(VAR49)) VAR8 (.VAR116(VAR20), .VAR121(VAR121), .VAR44(VAR112), .VAR55(VAR93), .VAR21(VAR96));
VAR101 #(.VAR49(VAR49)) VAR60 (.VAR116(VAR20), .VAR121(VAR121), .VAR44(VAR117), .VAR55(VAR12), .VAR21(VAR99));
always @ (posedge VAR121) begin
VAR30 <= VAR30;
VAR89 <= VAR89;
VAR85 <= VAR85;
VAR42 <= VAR42;
VAR18 <= VAR18;
VAR7 <= VAR7;
VAR66 <= VAR66;
VAR36 <= VAR36;
end
always @ begin
VAR76 = VAR76;
VAR26 = VAR26;
VAR27 = VAR27;
VAR103 = VAR103;
VAR5 = VAR5;
VAR65 = VAR65;
VAR51 = VAR51;
VAR91 = VAR91;
VAR83 = VAR83;
VAR118 = VAR118;
VAR11 = VAR11;
VAR79 = VAR79;
case (VAR76)
VAR103 = !VAR93;
VAR26 = ((VAR113)<<VAR96);
VAR79 = VAR113;
VAR118 = VAR113;
VAR76 = (VAR113 ? VAR107 : VAR4);
end
VAR103 = VAR12;
VAR27 = (VAR12<<VAR99);
VAR76 = (VAR12 ? VAR107 : VAR94);
end
VAR79 = 0;
VAR26 = 0;
VAR27 = 0;
VAR83 = VAR103;
VAR118 = 0;
VAR11 = VAR115 ^ {VAR103,{(VAR81-1){1'b0}}};
if (VAR103) begin
VAR5 = {2'd0, VAR18};
VAR65 = VAR7;
VAR51 = (VAR7[61:30] != 0);
VAR91 = VAR66;
end
else begin
VAR5 = {VAR42, VAR30};
VAR65 = VAR89;
VAR51 = (VAR89[61:30] != 0);
VAR91 = VAR85;
end
VAR76 = VAR109;
end
if (VAR68 & !VAR119) begin VAR76 = (VAR4>>(VAR83)); end
end
default : begin
VAR76 = VAR94;
end
endcase
end
always @ (posedge VAR121) begin
VAR119 <= (VAR20 ? VAR64 : VAR119);
VAR34 <= VAR34;
VAR17 <= VAR17;
VAR43 <= VAR43;
VAR56 <= VAR56;
VAR82 <= VAR82;
VAR53 <= VAR53;
VAR98 <= VAR98;
VAR75 <= VAR75;
VAR63 <= VAR63;
VAR10 <= VAR10;
VAR84 <= VAR84;
end
always @ begin
VAR87 = {VAR87[((VAR25-1)*1)-1:0], VAR34};
VAR28 = {VAR28[((VAR25-1)*4)-1:0], VAR43};
VAR23 = {VAR23[((VAR25-1)*8)-1:0], (8'd0 | VAR56)};
VAR31 = {VAR31[((VAR25-1)*62)-1:0], VAR82};
VAR122 = {VAR122[((VAR25-1)*1)-1:0], VAR53};
VAR41 = {VAR41[((VAR25-1)*10)-1:0], VAR17};
VAR123 = {VAR123[((VAR25-1)*1)-1:0], (VAR17 == 10'd1)};
VAR19 = {VAR19[((VAR25-1)*1)-1:0], VAR10 & VAR34};
VAR16 = {VAR16[((VAR25-1)*1)-1:0], VAR75};
VAR97 = {VAR97[((VAR25-1)*1)-1:0], VAR63};
end
assign VAR6 = VAR36;
assign VAR46 = VAR19[(VAR25-1)*1 +:1];
assign VAR14 = VAR97[(VAR25-1)*1 +:1];
assign VAR22 = 0;
assign VAR24 = VAR16[(VAR25-1)*1 +:1];
assign VAR95 = VAR41[(VAR25-1)*10 +:VAR92] - 1;
assign VAR78 = VAR63;
assign VAR13 = VAR34 ? VAR86 : VAR102;
assign VAR61 = {VAR82,2'b00};
assign VAR62 = VAR17;
assign VAR3 = VAR17 == 10'd1 ? 0 : 4'b1111;
assign VAR100 = 4'b1111;
assign VAR114 = VAR56;
assign VAR52 = 1'b0;
assign VAR80 = 3'b110;
assign VAR120 = 0;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/probec_p/sky130_fd_sc_hvl__probec_p.pp.symbol.v
| 1,286 |
module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR3 ,
input VAR4,
input VAR6,
input VAR1
);
endmodule
|
apache-2.0
|
alexforencich/xfcp
|
lib/eth/rtl/arp_eth_tx.v
| 13,474 |
module MODULE1 #
(
parameter VAR16 = 8,
parameter VAR28 = (VAR16>8),
parameter VAR19 = (VAR16/8)
)
(
input wire clk,
input wire rst,
input wire VAR23,
output wire VAR21,
input wire [47:0] VAR17,
input wire [47:0] VAR9,
input wire [15:0] VAR6,
input wire [15:0] VAR20,
input wire [15:0] VAR11,
input wire [15:0] VAR14,
input wire [47:0] VAR30,
input wire [31:0] VAR25,
input wire [47:0] VAR18,
input wire [31:0] VAR4,
output wire VAR15,
input wire VAR13,
output wire [47:0] VAR7,
output wire [47:0] VAR26,
output wire [15:0] VAR2,
output wire [VAR16-1:0] VAR31,
output wire [VAR19-1:0] VAR12,
output wire VAR10,
input wire VAR24,
output wire VAR8,
output wire VAR22,
output wire VAR1
);
parameter VAR3 = (28+VAR19-1)/VAR19;
parameter VAR29 = VAR27(VAR3);
parameter VAR5 = 28 % VAR19;
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_muls.v
| 9,611 |
module MODULE1 (
clk,
VAR25,
VAR37,
VAR9,
VAR43,
VAR13);
parameter VAR15 = 16;
parameter VAR3 = VAR15 - 1;
input clk;
input [15:0] VAR25;
input [15:0] VAR37;
output [15:0] VAR9;
input [VAR3:0] VAR43;
output [VAR3:0] VAR13;
reg [VAR3:0] VAR39 = 'd0;
reg VAR26 = 'd0;
reg [14:0] VAR12 = 'd0;
reg [14:0] VAR19 = 'd0;
reg [VAR3:0] VAR34 = 'd0;
reg VAR17 = 'd0;
reg [29:0] VAR36 = 'd0;
reg [29:0] VAR29 = 'd0;
reg [29:0] VAR24 = 'd0;
reg [29:0] VAR1 = 'd0;
reg [29:0] VAR35 = 'd0;
reg [29:0] VAR42 = 'd0;
reg [29:0] VAR6 = 'd0;
reg [29:0] VAR7 = 'd0;
reg [VAR3:0] VAR18 = 'd0;
reg VAR11 = 'd0;
reg [29:0] VAR2 = 'd0;
reg [29:0] VAR23 = 'd0;
reg [29:0] VAR8 = 'd0;
reg [29:0] VAR14 = 'd0;
reg [VAR3:0] VAR31 = 'd0;
reg VAR21 = 'd0;
reg [29:0] VAR30 = 'd0;
reg [29:0] VAR38 = 'd0;
reg [VAR3:0] VAR33 = 'd0;
reg VAR28 = 'd0;
reg [29:0] VAR32 = 'd0;
reg [VAR3:0] VAR13 = 'd0;
reg [15:0] VAR9 = 'd0;
wire [15:0] VAR20;
wire [15:0] VAR16;
wire [15:0] VAR4;
wire [15:0] VAR40;
wire [29:0] VAR41;
wire [29:0] VAR10;
wire [29:0] VAR44;
wire [29:0] VAR22;
wire [15:0] VAR5;
wire [15:0] VAR27;
assign VAR20 = ~VAR25 + 1'b1;
assign VAR16 = ~VAR37 + 1'b1;
always @(posedge clk) begin
VAR39 <= VAR43;
VAR26 <= VAR25[15] ^ VAR37[15];
VAR12 <= (VAR25[15] == 1'b1) ? VAR20[14:0] : VAR25[14:0];
VAR19 <= (VAR37[15] == 1'b1) ? VAR16[14:0] : VAR37[14:0];
end
assign VAR4 = {1'b0, VAR12};
assign VAR40 = ~VAR4 + 1'b1;
assign VAR41 = {{14{VAR4[15]}}, VAR4};
assign VAR10 = {{14{VAR40[15]}}, VAR40};
assign VAR44 = {{13{VAR4[15]}}, VAR4, 1'b0};
assign VAR22 = {{13{VAR40[15]}}, VAR40, 1'b0};
always @(posedge clk) begin
VAR34 <= VAR39;
VAR17 <= VAR26;
case (VAR19[1:0])
2'b11: VAR36 <= VAR10;
2'b10: VAR36 <= VAR22;
2'b01: VAR36 <= VAR41;
default: VAR36 <= 30'd0;
endcase
case (VAR19[3:1])
3'b011: VAR29 <= {VAR44[27:0], 2'd0};
3'b100: VAR29 <= {VAR22[27:0], 2'd0};
3'b001: VAR29 <= {VAR41[27:0], 2'd0};
3'b010: VAR29 <= {VAR41[27:0], 2'd0};
3'b101: VAR29 <= {VAR10[27:0], 2'd0};
3'b110: VAR29 <= {VAR10[27:0], 2'd0};
default: VAR29 <= 30'd0;
endcase
case (VAR19[5:3])
3'b011: VAR24 <= {VAR44[25:0], 4'd0};
3'b100: VAR24 <= {VAR22[25:0], 4'd0};
3'b001: VAR24 <= {VAR41[25:0], 4'd0};
3'b010: VAR24 <= {VAR41[25:0], 4'd0};
3'b101: VAR24 <= {VAR10[25:0], 4'd0};
3'b110: VAR24 <= {VAR10[25:0], 4'd0};
default: VAR24 <= 30'd0;
endcase
case (VAR19[7:5])
3'b011: VAR1 <= {VAR44[23:0], 6'd0};
3'b100: VAR1 <= {VAR22[23:0], 6'd0};
3'b001: VAR1 <= {VAR41[23:0], 6'd0};
3'b010: VAR1 <= {VAR41[23:0], 6'd0};
3'b101: VAR1 <= {VAR10[23:0], 6'd0};
3'b110: VAR1 <= {VAR10[23:0], 6'd0};
default: VAR1 <= 30'd0;
endcase
case (VAR19[9:7])
3'b011: VAR35 <= {VAR44[21:0], 8'd0};
3'b100: VAR35 <= {VAR22[21:0], 8'd0};
3'b001: VAR35 <= {VAR41[21:0], 8'd0};
3'b010: VAR35 <= {VAR41[21:0], 8'd0};
3'b101: VAR35 <= {VAR10[21:0], 8'd0};
3'b110: VAR35 <= {VAR10[21:0], 8'd0};
default: VAR35 <= 30'd0;
endcase
case (VAR19[11:9])
3'b011: VAR42 <= {VAR44[19:0], 10'd0};
3'b100: VAR42 <= {VAR22[19:0], 10'd0};
3'b001: VAR42 <= {VAR41[19:0], 10'd0};
3'b010: VAR42 <= {VAR41[19:0], 10'd0};
3'b101: VAR42 <= {VAR10[19:0], 10'd0};
3'b110: VAR42 <= {VAR10[19:0], 10'd0};
default: VAR42 <= 30'd0;
endcase
case (VAR19[13:11])
3'b011: VAR6 <= {VAR44[17:0], 12'd0};
3'b100: VAR6 <= {VAR22[17:0], 12'd0};
3'b001: VAR6 <= {VAR41[17:0], 12'd0};
3'b010: VAR6 <= {VAR41[17:0], 12'd0};
3'b101: VAR6 <= {VAR10[17:0], 12'd0};
3'b110: VAR6 <= {VAR10[17:0], 12'd0};
default: VAR6 <= 30'd0;
endcase
case (VAR19[14:13])
2'b11: VAR7 <= {VAR44[15:0], 14'd0};
2'b01: VAR7 <= {VAR41[15:0], 14'd0};
2'b10: VAR7 <= {VAR41[15:0], 14'd0};
default: VAR7 <= 30'd0;
endcase
end
always @(posedge clk) begin
VAR18 <= VAR34;
VAR11 <= VAR17;
VAR2 <= VAR36 + VAR35;
VAR23 <= VAR29 + VAR42;
VAR8 <= VAR24 + VAR6;
VAR14 <= VAR1 + VAR7;
end
always @(posedge clk) begin
VAR31 <= VAR18;
VAR21 <= VAR11;
VAR30 <= VAR2 + VAR8;
VAR38 <= VAR23 + VAR14;
end
always @(posedge clk) begin
VAR33 <= VAR31;
VAR28 <= VAR21;
VAR32 <= VAR30 + VAR38;
end
assign VAR5 = {1'd0, VAR32[29:15]};
assign VAR27 = ~VAR5 + 1'b1;
always @(posedge clk) begin
VAR13 <= VAR33;
if (VAR28 == 1'b1) begin
VAR9 <= VAR27;
end else begin
VAR9 <= VAR5;
end
end
endmodule
|
mit
|
ShepardSiegel/ocpi
|
coregen/ddr3_s4_amphy/ddr3_s4_amphy_phy.v
| 33,505 |
module MODULE1 (
VAR133,
VAR125,
VAR27,
VAR107,
VAR121,
VAR73,
VAR48,
VAR45,
VAR49,
VAR68,
VAR115,
VAR1,
VAR82,
VAR116,
VAR100,
VAR56,
VAR134,
VAR117,
VAR76,
VAR57,
VAR94,
VAR103,
VAR20,
VAR41,
VAR58,
VAR36,
VAR43,
VAR89,
VAR104,
VAR124,
VAR25,
VAR122,
VAR17,
VAR38,
VAR55,
VAR131,
VAR9,
VAR105,
VAR83,
VAR92,
VAR50,
VAR5,
VAR60,
VAR96,
VAR62,
VAR37,
VAR98,
VAR119,
VAR112,
VAR120,
VAR32,
VAR111,
VAR127,
VAR18,
VAR79,
VAR24,
VAR30,
VAR65,
VAR118,
VAR26,
VAR101,
VAR8,
VAR10,
VAR14,
VAR128,
VAR90,
VAR35,
VAR7,
VAR31,
VAR71,
VAR16,
VAR109,
VAR87,
VAR15,
VAR74,
VAR44,
VAR110,
VAR102,
VAR3,
VAR129,
VAR72);
input VAR133;
input VAR125;
input VAR27;
input [1:0] VAR107;
input [1:0] VAR121;
input [31:0] VAR73;
input [3:0] VAR48;
input [25:0] VAR45;
input [5:0] VAR49;
input [1:0] VAR68;
input [1:0] VAR115;
input [1:0] VAR1;
input [1:0] VAR82;
input [1:0] VAR116;
input [1:0] VAR100;
input [1:0] VAR56;
input [1:0] VAR134;
input VAR117;
input [0:0] VAR76;
input VAR57;
input [0:0] VAR94;
input [13:0] VAR103;
input [13:0] VAR20;
input [5:0] VAR41;
input [5:0] VAR58;
input VAR36;
input VAR43;
input [12:0] VAR89;
input VAR104;
input VAR124;
input VAR25;
input [31:0] VAR122;
input VAR17;
input [3:0] VAR38;
input VAR55;
input VAR131;
input VAR9;
input [7:0] VAR105;
input [0:0] VAR83;
input [0:0] VAR92;
input [0:0] VAR50;
input [0:0] VAR5;
input [0:0] VAR60;
input VAR96;
output VAR62;
output VAR37;
output VAR98;
output [4:0] VAR119;
output [31:0] VAR112;
output [1:0] VAR120;
output [4:0] VAR32;
output VAR111;
output VAR127;
output VAR18;
output VAR79;
output VAR24;
output [12:0] VAR30;
output [2:0] VAR65;
output VAR118;
output [0:0] VAR26;
output [0:0] VAR101;
output [0:0] VAR8;
output [0:0] VAR10;
output VAR14;
output VAR128;
output VAR90;
output [5:0] VAR35;
output VAR7;
output VAR31;
output VAR71;
output VAR16;
output VAR109;
output [31:0] VAR87;
output VAR15;
output VAR74;
output [7:0] VAR44;
inout [0:0] VAR110;
inout [0:0] VAR102;
inout [7:0] VAR3;
inout [0:0] VAR129;
inout [0:0] VAR72;
VAR2 VAR6(
.VAR133(VAR133),
.VAR125(VAR125),
.VAR27(VAR27),
.VAR107(VAR107),
.VAR121(VAR121),
.VAR73(VAR73),
.VAR48(VAR48),
.VAR45(VAR45),
.VAR49(VAR49),
.VAR68(VAR68),
.VAR115(VAR115),
.VAR1(VAR1),
.VAR82(VAR82),
.VAR116(VAR116),
.VAR100(VAR100),
.VAR56(VAR56),
.VAR134(VAR134),
.VAR117(VAR117),
.VAR76(VAR76),
.VAR57(VAR57),
.VAR94(VAR94),
.VAR103(VAR103),
.VAR20(VAR20),
.VAR41(VAR41),
.VAR58(VAR58),
.VAR36(VAR36),
.VAR43(VAR43),
.VAR89(VAR89),
.VAR104(VAR104),
.VAR124(VAR124),
.VAR25(VAR25),
.VAR122(VAR122),
.VAR17(VAR17),
.VAR38(VAR38),
.VAR55(VAR55),
.VAR131(VAR131),
.VAR9(VAR9),
.VAR105(VAR105),
.VAR83(VAR83),
.VAR92(VAR92),
.VAR50(VAR50),
.VAR5(VAR5),
.VAR60(VAR60),
.VAR96(VAR96),
.VAR62(VAR62),
.VAR37(VAR37),
.VAR98(VAR98),
.VAR119(VAR119),
.VAR112(VAR112),
.VAR120(VAR120),
.VAR32(VAR32),
.VAR111(VAR111),
.VAR127(VAR127),
.VAR18(VAR18),
.VAR79(VAR79),
.VAR24(VAR24),
.VAR30(VAR30),
.VAR65(VAR65),
.VAR118(VAR118),
.VAR26(VAR26),
.VAR101(VAR101),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR14(VAR14),
.VAR128(VAR128),
.VAR90(VAR90),
.VAR35(VAR35),
.VAR7(VAR7),
.VAR31(VAR31),
.VAR71(VAR71),
.VAR16(VAR16),
.VAR109(VAR109),
.VAR87(VAR87),
.VAR15(VAR15),
.VAR74(VAR74),
.VAR44(VAR44),
.VAR110(VAR110),
.VAR102(VAR102),
.VAR3(VAR3),
.VAR129(VAR129),
.VAR72(VAR72));
VAR6.VAR113 = "VAR13 VAR42",
VAR6.VAR106 = "VAR84",
VAR6.VAR54 = "VAR67",
VAR6.VAR85 = 10,
VAR6.VAR47 = 6,
VAR6.VAR80 = "VAR33",
VAR6.VAR86 = 7200,
VAR6.VAR29 = 2,
VAR6.VAR28 = 4,
VAR6.VAR61 = 8,
VAR6.VAR108 = 13,
VAR6.VAR23 = 3,
VAR6.VAR53 = 1,
VAR6.VAR64 = 1,
VAR6.VAR132 = 1,
VAR6.VAR34 = 1,
VAR6.VAR93 = 8,
VAR6.VAR39 = 1,
VAR6.VAR52 = 0,
VAR6.VAR4 = 1,
VAR6.VAR99 = 3333,
VAR6.VAR75 = "3333 VAR66",
VAR6.VAR81 = 4689,
VAR6.VAR114 = 2,
VAR6.VAR21 = 16,
VAR6.VAR77 = 0,
VAR6.VAR11 = 40,
VAR6.VAR69 = 3,
VAR6.VAR70 = 1,
VAR6.VAR95 = "VAR12",
VAR6.VAR78 = 240,
VAR6.VAR130 = 0,
VAR6.VAR46 = 0,
VAR6.VAR59 = "VAR19",
VAR6.VAR22 = "VAR63",
VAR6.VAR97 = 0,
VAR6.VAR88 = "true",
VAR6.VAR51 = "true",
VAR6.VAR123 = "VAR126 VAR40",
VAR6.VAR91 = "0000000000000000000000000000000000000000000000000000000000000000";
endmodule
|
lgpl-3.0
|
bargei/NoC264
|
NoC264_3x3/mkOutPortFIFO.v
| 20,764 |
module MODULE1(VAR62,
VAR80,
VAR85,
VAR72,
VAR77,
VAR68,
VAR46,
VAR8,
VAR14,
VAR65,
VAR16,
VAR11,
VAR60,
VAR66,
VAR67,
VAR37,
VAR35);
input VAR62;
input VAR80;
input [2 : 0] VAR85;
input VAR72;
output VAR77;
input VAR68;
output VAR46;
output [2 : 0] VAR8;
output VAR14;
output VAR65;
output VAR16;
output VAR11;
output VAR60;
output [3 : 0] VAR66;
output VAR67;
input VAR37;
output VAR35;
reg [2 : 0] VAR8;
wire [3 : 0] VAR66;
wire VAR35,
VAR67,
VAR46,
VAR77,
VAR14,
VAR60,
VAR16,
VAR11,
VAR65;
reg VAR47;
wire VAR84,
VAR27;
reg [63 : 0] VAR24;
wire [63 : 0] VAR87;
wire VAR75;
reg VAR50;
wire VAR74, VAR82;
reg [63 : 0] VAR13;
wire [63 : 0] VAR45;
wire VAR21;
reg VAR33;
wire VAR32, VAR2;
reg [2 : 0] VAR31;
wire [2 : 0] VAR39;
wire VAR53;
reg [2 : 0] VAR10;
wire [2 : 0] VAR52;
wire VAR78;
reg [2 : 0] VAR90;
wire [2 : 0] VAR22;
wire VAR56;
reg [2 : 0] VAR81;
wire [2 : 0] VAR51;
wire VAR73;
reg [2 : 0] VAR23;
wire [2 : 0] VAR1;
wire VAR79;
reg [2 : 0] VAR83;
wire [2 : 0] VAR48;
wire VAR18;
reg [2 : 0] VAR64;
wire [2 : 0] VAR7;
wire VAR30;
reg [2 : 0] VAR9;
wire [2 : 0] VAR28;
wire VAR26;
reg [2 : 0] VAR57;
wire [2 : 0] VAR25;
wire VAR29;
reg [3 : 0] VAR86;
wire [3 : 0] VAR55;
wire VAR70;
reg [2 : 0] VAR3;
wire [2 : 0] VAR6;
wire VAR41;
wire VAR38;
wire [63 : 0] VAR89, VAR20;
wire [3 : 0] VAR54,
VAR15;
wire [2 : 0] VAR19,
VAR76;
wire VAR5,
VAR63,
VAR34,
VAR58,
VAR17,
VAR42,
VAR61,
VAR40;
assign VAR77 = 1'd1 ;
assign VAR46 = 1'd1 ;
always@(VAR31 or
VAR57 or
VAR10 or
VAR90 or
VAR81 or
VAR23 or
VAR83 or
VAR64 or VAR9)
begin
case (VAR31)
3'd0: VAR8 = VAR10;
3'd1: VAR8 = VAR90;
3'd2: VAR8 = VAR81;
3'd3: VAR8 = VAR23;
3'd4: VAR8 = VAR83;
3'd5: VAR8 = VAR64;
3'd6: VAR8 = VAR9;
3'd7: VAR8 = VAR57;
endcase
end
assign VAR14 = 1'd1 ;
assign VAR65 = !VAR33 ;
assign VAR16 = 1'd1 ;
assign VAR11 = !VAR50 ;
assign VAR60 = 1'd1 ;
assign VAR66 = VAR86 ;
assign VAR67 = 1'd1 ;
assign VAR35 = 1'd1 ;
assign VAR38 =
VAR50 &&
VAR13 != VAR24 ;
assign VAR84 =
!VAR37 &&
(VAR63 ||
VAR5) ;
assign VAR27 = 1'd1 ;
assign VAR87 = VAR37 ? 64'd0 : VAR89 ;
assign VAR75 = VAR37 || VAR68 ;
assign VAR74 =
VAR37 ||
VAR34 ;
assign VAR82 = 1'd1 ;
assign VAR45 = VAR37 ? 64'd0 : VAR20 ;
assign VAR21 = VAR37 || VAR72 ;
assign VAR32 =
!VAR37 &&
VAR5 ;
assign VAR2 = 1'd1 ;
assign VAR39 =
VAR37 ? 3'd0 : VAR19 ;
assign VAR53 = VAR37 || VAR68 ;
assign VAR52 = VAR85 ;
assign VAR78 =
!VAR37 && VAR72 && VAR3 == 3'd0 ;
assign VAR22 = VAR85 ;
assign VAR56 =
!VAR37 && VAR72 && VAR3 == 3'd1 ;
assign VAR51 = VAR85 ;
assign VAR73 =
!VAR37 && VAR72 && VAR3 == 3'd2 ;
assign VAR1 = VAR85 ;
assign VAR79 =
!VAR37 && VAR72 && VAR3 == 3'd3 ;
assign VAR48 = VAR85 ;
assign VAR18 =
!VAR37 && VAR72 && VAR3 == 3'd4 ;
assign VAR7 = VAR85 ;
assign VAR30 =
!VAR37 && VAR72 && VAR3 == 3'd5 ;
assign VAR28 = VAR85 ;
assign VAR26 =
!VAR37 && VAR72 && VAR3 == 3'd6 ;
assign VAR25 = VAR85 ;
assign VAR29 =
!VAR37 && VAR72 && VAR3 == 3'd7 ;
assign VAR55 =
VAR37 ?
4'd0 :
VAR54 ;
assign VAR70 = 1'd1 ;
assign VAR6 =
VAR37 ? 3'd0 : VAR76 ;
assign VAR41 = VAR37 || VAR72 ;
assign VAR5 =
(VAR68 && VAR72) ?
VAR33 :
!VAR68 &&
VAR42 ;
assign VAR63 =
(VAR68 && VAR72) ?
VAR47 :
VAR58 ;
assign VAR34 =
(VAR68 && VAR72) ?
VAR50 :
VAR17 ;
assign VAR54 =
(VAR68 && VAR72) ?
VAR86 :
VAR15 ;
assign VAR58 =
VAR68 ?
VAR3 == VAR31 :
VAR61 ;
assign VAR17 =
VAR68 ?
VAR19 ==
VAR3 :
!VAR72 && VAR50 ;
assign VAR15 =
VAR68 ?
VAR86 - 4'd1 :
(VAR72 ?
VAR86 + 4'd1 :
VAR86) ;
assign VAR42 =
VAR72 ?
VAR76 ==
VAR31 :
VAR33 ;
assign VAR61 =
VAR72 ?
VAR3 + 3'd2 == VAR31 :
VAR47 ;
assign VAR40 =
VAR50 ==
(VAR31 == VAR3 &&
!VAR33) ;
assign VAR19 =
VAR31 + 3'd1 ;
assign VAR76 =
VAR3 + 3'd1 ;
assign VAR89 = VAR24 + 64'd1 ;
assign VAR20 = VAR13 + 64'd1 ;
always@(posedge VAR62)
begin
if (!VAR80)
begin
VAR47 <= VAR43 1'd0;
VAR24 <= VAR43 64'd0;
VAR50 <= VAR43 1'd1;
VAR13 <= VAR43 64'd0;
VAR33 <= VAR43 1'd0;
VAR31 <= VAR43 3'd0;
VAR10 <= VAR43 3'd0;
VAR90 <= VAR43 3'd0;
VAR81 <= VAR43 3'd0;
VAR23 <= VAR43 3'd0;
VAR83 <= VAR43 3'd0;
VAR64 <= VAR43 3'd0;
VAR9 <= VAR43 3'd0;
VAR57 <= VAR43 3'd0;
VAR86 <= VAR43 4'd0;
VAR3 <= VAR43 3'd0;
end
else
begin
if (VAR27)
VAR47 <= VAR43
VAR84;
if (VAR75)
VAR24 <= VAR43
VAR87;
if (VAR82)
VAR50 <= VAR43
VAR74;
if (VAR21)
VAR13 <= VAR43
VAR45;
if (VAR2)
VAR33 <= VAR43
VAR32;
if (VAR53)
VAR31 <= VAR43
VAR39;
if (VAR78)
VAR10 <= VAR43
VAR52;
if (VAR56)
VAR90 <= VAR43
VAR22;
if (VAR73)
VAR81 <= VAR43
VAR51;
if (VAR79)
VAR23 <= VAR43
VAR1;
if (VAR18)
VAR83 <= VAR43
VAR48;
if (VAR30)
VAR64 <= VAR43
VAR7;
if (VAR26)
VAR9 <= VAR43
VAR28;
if (VAR29)
VAR57 <= VAR43
VAR25;
if (VAR70)
VAR86 <= VAR43
VAR55;
if (VAR41)
VAR3 <= VAR43
VAR6;
end
end
begin
VAR47 = 1'h0;
VAR24 = 64'hAAAAAAAAAAAAAAAA;
VAR50 = 1'h0;
VAR13 = 64'hAAAAAAAAAAAAAAAA;
VAR33 = 1'h0;
VAR31 = 3'h2;
VAR10 = 3'h2;
VAR90 = 3'h2;
VAR81 = 3'h2;
VAR23 = 3'h2;
VAR83 = 3'h2;
VAR64 = 3'h2;
VAR9 = 3'h2;
VAR57 = 3'h2;
VAR86 = 4'hA;
VAR3 = 3'h2;
end
always@(negedge VAR62)
begin
if (VAR80)
if (VAR72 && VAR33)
VAR59("VAR36 VAR44 VAR4: ",
"\"VAR88.VAR12\", VAR69 25, VAR49 33\VAR71");
if (VAR80)
if (VAR72 && VAR33)
if (VAR80) if (VAR72 && VAR33)
if (VAR80)
if (VAR68 && VAR50)
VAR59("VAR36 VAR44 VAR4: ",
"\"VAR88.VAR12\", VAR69 25, VAR49 33\VAR71");
if (VAR80)
if (VAR68 && VAR50)
if (VAR80) if (VAR68 && VAR50)
if (VAR80)
if (VAR38)
if (VAR80)
if (VAR38)
if (VAR80)
if (!VAR40)
if (VAR80)
if (!VAR40)
end
endmodule
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/pads/pad_ddr_common/rtl/dram_mclk_pad.v
| 4,607 |
module MODULE1(
VAR24, VAR22,
VAR21,
VAR19, VAR18, VAR17, VAR23, VAR8, VAR26,
VAR4, VAR3, VAR10, VAR2, VAR11, VAR13, VAR9
);
inout VAR21;
output VAR22; output VAR24;
input VAR9; input [8:1] VAR13; input [8:1] VAR11; input VAR2; input VAR10; input VAR3; input VAR4; input VAR26; input VAR8; input VAR23; input VAR17; input VAR18; input [7:0] VAR19;
wire VAR12; wire VAR20; wire VAR15; wire VAR5;
VAR16 VAR16(
.out(VAR5), .VAR21(VAR21),
.VAR19(VAR19[7:0]),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR11(VAR11[8:1]),
.VAR13(VAR13[8:1]),
.VAR25(VAR20), .VAR8(VAR12));
VAR14 VAR14(
.VAR24(VAR24),
.VAR20(VAR20),
.VAR8(VAR12), .VAR22(VAR22),
.VAR15(VAR15),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR23(VAR23),
.VAR17(VAR17),
.VAR1(VAR3),
.VAR7(VAR5), .VAR10(VAR10),
.VAR6(VAR8), .VAR26(VAR26));
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.v
| 2,234 |
module MODULE1 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR4 ,
VAR10,
VAR3,
VAR2 ,
VAR1
);
output VAR7 ;
output VAR6 ;
input VAR9 ;
input VAR4 ;
input VAR10;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7 ,
VAR6,
VAR9,
VAR4
);
output VAR7 ;
output VAR6;
input VAR9;
input VAR4 ;
supply1 VAR10;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
zYeoman/32BIT-MIPS-CPU
|
pipeline/IF.v
| 1,234 |
module MODULE1(
input clk, rst, VAR7,
input [31:0] VAR2,
input [2:0] VAR4,
input VAR3,
VAR8,
input [31:0] VAR9,
VAR5,
input [25:0] VAR1,
output reg [31:0] VAR6
);
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR6 <= 0;
end else if(VAR7)
VAR6 <= {VAR6[31], {31{1'b0}}};
end
else if (VAR3) begin
if(VAR8) begin
VAR6 <= VAR9;
end else case (VAR4) 3'h0: VAR6 <= VAR2+32'h4; 3'h1: VAR6 <= VAR2+32'h4;
3'h2: VAR6 <= {VAR2[31:28], VAR1, 2'b0};
3'h3: VAR6 <= VAR5; 3'h4: VAR6 <= 32'h80000004; 3'h5: VAR6 <= 32'h80000008; default: VAR6 <= 32'h80000008;
endcase
end else
VAR6 <= VAR6;
end
endmodule
|
gpl-2.0
|
Fabeltranm/FPGA-Game-D1
|
HW/RTL/011J1G2/hdl/periferico_BT/peripheral_bt.v
| 2,037 |
module MODULE1(clk , rst , din , VAR11 , addr , rd , wr, dout, VAR17, VAR5 );
input clk;
input rst;
input [15:0]din;
input VAR11;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
output VAR5;
output VAR17;
reg [5:0] VAR7;
reg VAR16;
reg [7:0] VAR10; wire [7:0] VAR12;
wire VAR3; wire VAR4;
wire VAR20;
VAR6 VAR1(.VAR9(VAR5), .VAR13(VAR20), .VAR18(clk), .reset(rst), .dout(VAR12), .din(VAR10), .enable(VAR16), .VAR15(VAR3), .VAR19(VAR4), .VAR8(VAR17));
always @(*) VAR14 (addr)
4'h0:begin VAR7 = (VAR11 && wr) ? 5'b00001 : 5'b00000 ;end 4'h2:begin VAR7 = (VAR11 && rd) ? 5'b00010 : 5'b00000 ;end 4'h4:begin VAR7 = (VAR11 && rd) ? 5'b00100 : 5'b00000 ;end 4'h6:begin VAR7 = (VAR11 && rd) ? 5'b01000 : 5'b00000 ;end 4'h8:begin VAR7 = (VAR11 && rd) ? 5'b10000 : 5'b00000 ;end default:begin VAR7=5'b00000 ; end
endcase
end
wire VAR2= (VAR3 | VAR16);
always @(negedge clk) begin
if (VAR7[0]==1) begin
VAR10<=din[7:0];
VAR16=1;
end
else begin
if (VAR3)
VAR16=0;
end
end
always @(negedge clk) VAR14 (VAR7)
5'b01000: dout[0]= VAR2;
5'b00010: dout[0]= VAR4;
5'b00100: dout[0]= VAR20;
5'b10000: dout[7:0] = VAR12;
default: dout=0;
endcase
end
endmodule
|
gpl-3.0
|
alexforencich/verilog-ethernet
|
example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v
| 2,604 |
module MODULE1 #(
parameter VAR4=1, parameter VAR2=3, parameter VAR3=125000 )(
input wire clk,
input wire rst,
input wire [VAR4-1:0] in,
output wire [VAR4-1:0] out
);
reg [23:0] VAR1 = 24'd0;
reg [VAR2-1:0] VAR6[VAR4-1:0];
reg [VAR4-1:0] state;
assign out = state;
integer VAR5;
always @(posedge clk) begin
if (rst) begin
VAR1 <= 0;
state <= 0;
for (VAR5 = 0; VAR5 < VAR4; VAR5 = VAR5 + 1) begin
VAR6[VAR5] <= 0;
end
end else begin
if (VAR1 < VAR3) begin
VAR1 <= VAR1 + 24'd1;
end else begin
VAR1 <= 24'd0;
end
if (VAR1 == 24'd0) begin
for (VAR5 = 0; VAR5 < VAR4; VAR5 = VAR5 + 1) begin
VAR6[VAR5] <= {VAR6[VAR5][VAR2-2:0], in[VAR5]};
end
end
for (VAR5 = 0; VAR5 < VAR4; VAR5 = VAR5 + 1) begin
if (|VAR6[VAR5] == 0) begin
state[VAR5] <= 0;
end else if (&VAR6[VAR5] == 1) begin
state[VAR5] <= 1;
end else begin
state[VAR5] <= state[VAR5];
end
end
end
end
endmodule
|
mit
|
yanhongwang/ColorImage
|
Divider/Divider.v
| 1,951 |
module MODULE2
(
input[ VAR9 - 1 : 0 ]VAR6,
input[ VAR9 - 1 : 0 ]VAR8,
output reg[ VAR9 - 1 : 0 ]VAR7, output reg[ VAR9 - 1 : 0 ]VAR3
);
integer VAR10;
reg[ VAR9 - 1 : 0 ]VAR4; reg[ VAR9 : 0 ]VAR2;
reg[ VAR9 - 1 : 0 ]VAR5;
always@( VAR6 or VAR8 )
begin
VAR4 = VAR6;
VAR5 = VAR8;
VAR2 = { VAR9'h00, 1'b0 };
for( VAR10 = 0; VAR10 < VAR9; VAR10 = VAR10 + 1 )
begin
VAR2 = { VAR2[ VAR9 - 1 : 0 ], VAR4[ VAR9 - 1 ] };
VAR4 = { VAR4[ VAR9 - 2 : 0 ], 1'b0 };
VAR2 = VAR2 + { ~{ 1'b0, VAR5 } + 1'b1 };
if( VAR2[ VAR9 ] == 1'b0 )
VAR4[ 0 ] = 1'b1;
end
else
begin
VAR2 = VAR2 + VAR5;
VAR4[ 0 ] = 1'b0;
end
end
VAR3 = VAR2[ VAR9 - 1 : 0 ];
if( VAR3 * 10 >= VAR8 * 5 )
VAR7 = VAR4 + 1;
else
VAR7 = VAR4;
end
endmodule
module MODULE1;
reg[ VAR9 - 1 : 0 ]VAR6;
reg[ VAR9 - 1 : 0 ]VAR8;
wire[ VAR9 - 1 : 0 ]VAR7;
wire[ VAR9 - 1 : 0 ]VAR3;
MODULE2 VAR1( VAR6, VAR8, VAR7, VAR3 );
begin
begin
begin
begin
|
mit
|
mistryalok/Zedboard
|
learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_dst_rows_V.v
| 2,987 |
module MODULE2 (
clk,
VAR18,
VAR19,
VAR1,
VAR16);
parameter VAR10 = 32'd12;
parameter VAR17 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input [VAR10-1:0] VAR18;
input VAR19;
input [VAR17-1:0] VAR1;
output [VAR10-1:0] VAR16;
reg[VAR10-1:0] VAR11 [0:VAR23-1];
integer VAR3;
always @ (posedge clk)
begin
if (VAR19)
begin
for (VAR3=0;VAR3<VAR23-1;VAR3=VAR3+1)
VAR11[VAR3+1] <= VAR11[VAR3];
VAR11[0] <= VAR18;
end
end
assign VAR16 = VAR11[VAR1];
endmodule
module MODULE1 (
clk,
reset,
VAR9,
VAR14,
VAR22,
VAR21,
VAR7,
VAR20,
VAR12,
VAR5);
parameter VAR6 = "VAR27";
parameter VAR10 = 32'd12;
parameter VAR17 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input reset;
output VAR9;
input VAR14;
input VAR22;
output[VAR10 - 1:0] VAR21;
output VAR7;
input VAR20;
input VAR12;
input[VAR10 - 1:0] VAR5;
wire[VAR17 - 1:0] VAR15 ;
wire[VAR10 - 1:0] VAR26, VAR25;
reg[VAR17:0] VAR8 = {(VAR17+1){1'b1}};
reg VAR24 = 0, VAR2 = 1;
assign VAR9 = VAR24;
assign VAR7 = VAR2;
assign VAR26 = VAR5;
assign VAR21 = VAR25;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR8 <= ~{VAR17+1{1'b0}};
VAR24 <= 1'b0;
VAR2 <= 1'b1;
end
else begin
if (((VAR22 & VAR14) == 1 & VAR24 == 1) &&
((VAR12 & VAR20) == 0 | VAR2 == 0))
begin
VAR8 <= VAR8 -1;
if (VAR8 == 0)
VAR24 <= 1'b0;
VAR2 <= 1'b1;
end
else if (((VAR22 & VAR14) == 0 | VAR24 == 0) &&
((VAR12 & VAR20) == 1 & VAR2 == 1))
begin
VAR8 <= VAR8 +1;
VAR24 <= 1'b1;
if (VAR8 == VAR23-2)
VAR2 <= 1'b0;
end
end
end
assign VAR15 = VAR8[VAR17] == 1'b0 ? VAR8[VAR17-1:0]:{VAR17{1'b0}};
assign VAR13 = (VAR12 & VAR20) & VAR2;
MODULE2
.VAR10(VAR10),
.VAR17(VAR17),
.VAR23(VAR23))
VAR4 (
.clk(clk),
.VAR18(VAR26),
.VAR19(VAR13),
.VAR1(VAR15),
.VAR16(VAR25));
endmodule
|
gpl-3.0
|
fisherdj/avgai
|
quartus/avgai/clocking.v
| 1,151 |
module MODULE2(input clk, VAR4, output reg VAR1);
reg [9:0] VAR3;
always @(posedge clk) begin
if (VAR1 == VAR4)
VAR3 <= 0;
end
else if (VAR3 != -10'b1)
VAR3 <= VAR3+1;
else if (VAR3 == -10'b1)
VAR1 <= VAR4;
end
endmodule
module MODULE1(input clk, output VAR5);
parameter VAR2 = 25;
reg [VAR2-1:0] VAR6 = 0;
assign VAR5 = VAR6[VAR2-1];
always @(posedge clk)
VAR6 <= VAR6 + 1;
endmodule
|
gpl-3.0
|
tmatsuya/milkymist-ml401
|
cores/minimac/rtl/minimac.v
| 3,135 |
module MODULE1 #(
parameter VAR42 = 4'h0
) (
input VAR49,
input VAR55,
input [13:0] VAR23,
input VAR26,
input [31:0] VAR51,
output [31:0] VAR47,
output VAR22,
output VAR41,
output [31:0] VAR56,
output [2:0] VAR37,
output VAR45,
output VAR15,
input VAR3,
output [31:0] VAR6,
output [31:0] VAR52,
output [2:0] VAR4,
output VAR9,
output VAR39,
input VAR50,
input [31:0] VAR35,
input VAR25,
output [3:0] VAR43,
output VAR53,
output VAR32,
input VAR17,
input [3:0] VAR33,
input VAR27,
input VAR10,
input VAR16,
input VAR13,
output VAR14,
inout VAR38
);
assign VAR37 = 3'd0;
assign VAR4 = 3'd0;
wire VAR54;
wire VAR29;
wire VAR7;
wire [29:0] VAR8;
wire VAR2;
wire VAR20;
wire VAR24;
wire VAR31;
wire VAR30;
wire [29:0] VAR1;
wire [1:0] VAR36;
wire VAR11;
VAR48 #(
.VAR42(VAR42)
) VAR44 (
.VAR49(VAR49),
.VAR55(VAR55),
.VAR23(VAR23),
.VAR26(VAR26),
.VAR51(VAR51),
.VAR47(VAR47),
.VAR22(VAR22),
.VAR41(VAR41),
.VAR54(VAR54),
.VAR29(VAR29),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR20(VAR20),
.VAR24(VAR24),
.VAR31(VAR31),
.VAR30(VAR30),
.VAR1(VAR1),
.VAR36(VAR36),
.VAR11(VAR11),
.VAR14(VAR14),
.VAR38(VAR38)
);
VAR21 VAR5(
.VAR49(VAR49),
.VAR55(VAR55),
.VAR54(VAR54),
.VAR40(VAR56),
.VAR19(VAR45),
.VAR46(VAR15),
.VAR18(VAR3),
.VAR28(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR20(VAR20),
.VAR24(VAR24),
.VAR31(VAR31),
.VAR17(VAR17),
.VAR33(VAR33),
.VAR27(VAR27),
.VAR10(VAR10)
);
VAR12 VAR34(
.VAR49(VAR49),
.VAR55(VAR55),
.VAR29(VAR29),
.VAR30(VAR30),
.VAR1(VAR1),
.VAR36(VAR36),
.VAR11(VAR11),
.VAR52(VAR52),
.VAR9(VAR9),
.VAR39(VAR39),
.VAR50(VAR50),
.VAR35(VAR35),
.VAR25(VAR25),
.VAR53(VAR53),
.VAR43(VAR43)
);
assign VAR32 = 1'b0;
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/clkbuf/sky130_fd_sc_hdll__clkbuf_8.v
| 2,050 |
module MODULE1 (
VAR1 ,
VAR5 ,
VAR8,
VAR4,
VAR7 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR8;
input VAR4;
input VAR7 ;
input VAR6 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR8;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/ACA_I_N32_Q8.v
| 2,190 |
module MODULE1(
input [31:0] VAR14,
input [31:0] VAR12,
output [32:0] VAR24
);
wire [8:0] VAR5,VAR3,VAR19,VAR17,VAR7,VAR16,VAR26,VAR1,VAR22,VAR10;
wire [8:0] VAR2,VAR9,VAR20,VAR28,VAR13,VAR18,VAR6,VAR4,VAR25;
wire [8:0] VAR15,VAR11,VAR8,VAR23,VAR21,VAR27;
assign VAR5[8:0] = VAR14[7:0] + VAR12[7:0];
assign VAR3[8:0] = VAR14[8:1] + VAR12[8:1];
assign VAR19[8:0] = VAR14[9:2] + VAR12[9:2];
assign VAR17[8:0] = VAR14[10:3] + VAR12[10:3];
assign VAR7[8:0] = VAR14[11:4] + VAR12[11:4];
assign VAR16[8:0] = VAR14[12:5] + VAR12[12:5];
assign VAR26[8:0] = VAR14[13:6] + VAR12[13:6];
assign VAR1[8:0] = VAR14[14:7] + VAR12[14:7];
assign VAR22[8:0] = VAR14[15:8] + VAR12[15:8];
assign VAR10[8:0] = VAR14[16:9] + VAR12[16:9];
assign VAR2[8:0] = VAR14[17:10] + VAR12[17:10];
assign VAR9[8:0] = VAR14[18:11] + VAR12[18:11];
assign VAR20[8:0] = VAR14[19:12] + VAR12[19:12];
assign VAR28[8:0] = VAR14[20:13] + VAR12[20:13];
assign VAR13[8:0] = VAR14[21:14] + VAR12[21:14];
assign VAR18[8:0] = VAR14[22:15] + VAR12[22:15];
assign VAR6[8:0] = VAR14[23:16] + VAR12[23:16];
assign VAR4[8:0] = VAR14[24:17] + VAR12[24:17];
assign VAR25[8:0] = VAR14[25:18] + VAR12[25:18];
assign VAR15[8:0] = VAR14[26:19] + VAR12[26:19];
assign VAR11[8:0] = VAR14[27:20] + VAR12[27:20];
assign VAR8[8:0] = VAR14[28:21] + VAR12[28:21];
assign VAR23[8:0] = VAR14[29:22] + VAR12[29:22];
assign VAR21[8:0] = VAR14[30:23] + VAR12[30:23];
assign VAR27[8:0] = VAR14[31:24] + VAR12[31:24];
assign VAR24[32:0] = {VAR27[8:7],VAR21[7],VAR23[7],VAR8[7],VAR11[7],VAR15[7],VAR25[7],VAR4[7],VAR6[7],VAR18[7],VAR13[7],VAR28[7],VAR20[7],VAR9[7],VAR2[7],VAR10[7],VAR22[7],VAR1[7],VAR26[7],VAR16[7],VAR7[7],VAR17[7],VAR19[7],VAR3[7],VAR5[7:0]};
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nand3/sky130_fd_sc_lp__nand3_4.v
| 2,175 |
module MODULE1 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR2 ,
VAR10,
VAR6,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR10;
input VAR6;
input VAR3 ;
input VAR7 ;
VAR8 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR5,
VAR4,
VAR9,
VAR2
);
output VAR5;
input VAR4;
input VAR9;
input VAR2;
supply1 VAR10;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR7 ;
VAR8 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.behavioral.v
| 1,121 |
module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR2 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR4(.VAR1(VAR1),.VAR3(VAR3));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a2111o/sky130_fd_sc_ms__a2111o.behavioral.v
| 1,585 |
module MODULE1 (
VAR3 ,
VAR15,
VAR6,
VAR11,
VAR14,
VAR1
);
output VAR3 ;
input VAR15;
input VAR6;
input VAR11;
input VAR14;
input VAR1;
supply1 VAR4;
supply0 VAR7;
supply1 VAR13 ;
supply0 VAR9 ;
wire VAR12 ;
wire VAR5;
and VAR10 (VAR12 , VAR15, VAR6 );
or VAR2 (VAR5, VAR14, VAR11, VAR12, VAR1);
buf VAR8 (VAR3 , VAR5 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a31oi/sky130_fd_sc_lp__a31oi.symbol.v
| 1,369 |
module MODULE1 (
input VAR7,
input VAR2,
input VAR3,
input VAR1,
output VAR9
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
wyvernSemi/lm32fpga
|
HDL/rtl/CMD_Decode.v
| 18,916 |
module MODULE1(
VAR105, VAR87, VAR66, VAR31, VAR99,
VAR29,VAR45,
VAR83, VAR72,
VAR57, VAR81, VAR104,
VAR18, VAR69, VAR14,
VAR92, VAR20, VAR65, VAR79, VAR27, VAR2,
VAR7, VAR22, VAR42, VAR17, VAR94, VAR95,
VAR10, VAR49, VAR3, VAR61, VAR48,
VAR103, VAR12,
VAR33, VAR8, VAR67,
VAR90, VAR56
);
input [7:0] VAR105;
input VAR66, VAR31;
output [7:0] VAR87;
output VAR99;
output reg [9:0] VAR29;
output reg [7:0] VAR45;
output reg [31:0] VAR83;
input [31:0] VAR72;
output reg [9:0] VAR81;
output reg [9:0] VAR104;
output reg [9:0] VAR18;
output reg [9:0] VAR69;
output reg [9:0] VAR14;
output reg [1:0] VAR57;
input [7:0] VAR20;
input VAR79;
output reg [21:0] VAR65;
output reg [7:0] VAR92;
output reg [2:0] VAR2;
output reg VAR27;
input [15:0] VAR22;
input VAR17;
output reg [21:0] VAR42;
output reg [15:0] VAR7;
output VAR95;
output VAR94;
input [15:0] VAR49;
output reg [15:0] VAR10;
output reg [17:0] VAR3;
output VAR48;
output VAR61;
input [7:0] VAR103;
input VAR12;
output reg [1:0] VAR33;
output reg [1:0] VAR8;
output reg [1:0] VAR67;
input VAR90;
input VAR56;
reg [63:0] VAR93;
reg [2:0] VAR30, VAR91, VAR85, VAR47, VAR19, VAR100;
reg VAR6, VAR32;
reg VAR59, VAR77;
reg VAR86, VAR15, VAR62, VAR26, VAR11, VAR64;
reg VAR34, VAR74, VAR102, VAR46, VAR80;
reg VAR76;
reg VAR58, VAR43, VAR25, VAR53, VAR101;
reg [7:0] VAR4, VAR78, VAR41, VAR39;
reg VAR40, VAR82, VAR24, VAR71, VAR98;
wire [7:0] VAR89 = VAR93[63:56];
wire [7:0] VAR106 = VAR93[55:48];
wire [23:0] VAR9 = VAR93[47:24];
wire [15:0] VAR1 = VAR93[23: 8];
wire [7:0] VAR63 = VAR93[ 7: 0];
wire [7:0] VAR84 = VAR93[47:40];
wire VAR13 = VAR86 | VAR15 | VAR62 | VAR26 | VAR11 | VAR64 |
VAR34 | VAR74 | VAR102 | VAR46 | VAR80;
wire VAR44 = VAR76 & ~VAR13;
assign VAR99 = VAR40 ? VAR58 :
VAR82 ? VAR43 :
VAR71 ? VAR53 :
VAR98 ? VAR101 :
VAR25;
assign VAR87 = VAR40 ? VAR4 :
VAR82 ? VAR78 :
VAR71 ? VAR39 :
VAR98 ? VAR83[7:0] :
VAR41;
always @(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR33 <= 2'b00;
VAR8 <= 2'b00;
VAR67 <= 2'b00;
VAR26 <= 1'b0;
VAR11 <= 1'b0;
VAR64 <= 1'b0;
end
else
begin
if (VAR66 == 1'b1)
begin
case (VAR84)
VAR54 : begin VAR26 <= 1'b1; end
VAR16 : begin VAR11 <= 1'b1; end
VAR23 : begin VAR64 <= 1'b1; end
endcase
end
if ((VAR89 == VAR36) && (VAR63 == VAR97) && (VAR9 == 24'h123456))
begin
if (VAR26)
begin
VAR33 <= VAR1[1:0];
end
else if (VAR11)
begin
VAR8 <= VAR1[1:0];
end
else if (VAR64)
begin
VAR67 <= VAR1[1:0];
end
end
if (VAR26)
begin
VAR26 <= 1'b0;
end
if (VAR11)
begin
VAR11 <= 1'b0;
end
if (VAR64)
begin
VAR64 <= 1'b0;
end
end
end
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR40 <= 1'b0;
VAR82 <= 1'b0;
VAR24 <= 1'b0;
VAR71 <= 1'b0;
VAR98 <= 1'b0;
VAR86 <= 1'b0;
end
else
begin
if (VAR66 && (VAR84 == VAR21))
begin
VAR86<=1;
end
if (VAR86)
begin
if ((VAR89 == VAR36) && (VAR63 == VAR97) && (VAR9 == 24'h123456))
begin
VAR40 <= 1'b0;
VAR82 <= 1'b0;
VAR24 <= 1'b0;
VAR71 <= 1'b0;
VAR98 <= 1'b0;
case(VAR1[7:0])
VAR55:
begin
VAR40 <= 1'b1;
end
VAR37:
begin
VAR82 <= 1'b1;
end
VAR28:
begin
VAR24 <= 1'b1;
end
VAR51:
begin
VAR71 <= 1'b1;
end
VAR60:
begin
VAR98 <= 1'b1;
end
endcase
end
VAR86 <= 0;
end
end
end
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR93 <= {64{1'b0}};
VAR76 <= 1'b0;
end
else
begin
VAR76 <= VAR13;
if (VAR66)
begin
VAR93 <= {VAR93[55:0], VAR105};
end
else if (VAR44)
begin
VAR93 <= {64{1'b0}};
end
end
end
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR29 <= {10{1'b0}};
VAR45 <= {8{1'b0}};
VAR15 <= 1'b0;
end
else
begin
if (VAR66 && (VAR84 == VAR96))
begin
VAR15 <= 1'b1;
end
if (VAR15)
begin
if ((VAR89 == VAR38) && (VAR63 == VAR70))
begin
VAR29 <= VAR9[9:0];
VAR45 <= VAR1[7:0];
end
VAR15 <= 1'b0;
end
end
end
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR83 <= {32{1'b0}};
VAR62 <= 1'b0;
VAR101 <= 1'b0;
VAR100 <= 3'b000;
end
else
begin
if (VAR66 && (VAR84 == VAR60) )
begin
VAR62 <= 1'b1;
end
if (VAR62)
begin
if ((VAR89 == VAR38) && (VAR63 == VAR70))
begin
VAR83 <= {VAR9[15:0], VAR1};
VAR62 <= 1'b0;
end
else if ((VAR89 == VAR68) && (VAR63 == VAR5))
begin
case(VAR100)
3'b000:
begin
VAR101 <= 1'b1;
VAR83 <= VAR72;
VAR100 <= 3'b001;
end
3'b001:
begin
if(VAR31)
begin
VAR101 <= 1'b0;
VAR100 <= 3'b010;
end
end
3'b010:
begin
VAR101 <= 1'b1;
VAR83 <= {8'h00, VAR72[31:8]};
VAR100 <= 3'b011;
end
3'b011:
begin
if(VAR31)
begin
VAR101 <= 1'b0;
VAR100 <= 3'b000;
VAR62 <= 1'b0;
end
end
endcase
end
else
begin
VAR62 <= 1'b0;
end
end
end
end
always@(posedge VAR90 or negedge VAR56)
begin
if(!VAR56)
begin
VAR58 <= 1'b0;
VAR27 <= 1'b0;
VAR34 <= 1'b0;
VAR30 <= 3'b000;
end
else
begin
if (VAR89 == VAR68)
begin
VAR2 <= VAR52;
end
else if (VAR89 == VAR38)
begin
VAR2 <= VAR50;
end
else if (VAR89 == VAR35)
begin
VAR2 <= VAR88;
end
else
begin
VAR2 <= 3'b000;
end
if (VAR66 && (VAR84 == VAR55))
begin
VAR34 <= 1'b1;
end
if (VAR34)
begin
case(VAR30)
3'b000:
begin
if ((VAR63 == VAR5) && (VAR106 == VAR55) && (VAR1[15:8] == 8'hFF))
begin
VAR65 <= VAR9[21:0];
VAR92 <= VAR1[7:0];
VAR27 <= 1'b1;
VAR30 <= 3'b001;
end
else
begin
VAR30 <= 3'b000;
VAR34 <= 1'b0;
end
end
3'b001:
begin
if (VAR79)
begin
VAR30 <= 3'b010;
VAR27 <= 1'b0;
end
end
3'b010:
begin
VAR27 <= 1'b1;
VAR30 <= 3'b011;
end
3'b011:
begin
if (VAR79)
begin
VAR30 <= 3'b100;
VAR27 <= 1'b0;
end
end
3'b100:
begin
VAR27 <= 1'b1;
VAR30 <= 3'b101;
end
3'b101:
begin
if (VAR79)
begin
if (VAR2 == VAR52)
begin
VAR30 <= 3'b110;
end
else
begin
VAR30 <= 3'b000;
VAR34 <= 1'b0;
end
VAR27 <= 1'b0;
end
end
3'b110:
begin
VAR4 <= VAR20;
VAR58 <= 1'b1;
VAR30 <= 3'b111;
end
3'b111:
begin
if (VAR31)
begin
VAR58 <= 1'b0;
VAR30 <= 3'b000;
VAR34 <= 1'b0;
end
end
endcase
end
end
end
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR25 <= 1'b0;
VAR102 <= 1'b0;
VAR85 <= 3'b000;
end
else
begin
if (VAR12 && VAR103!=8'h2e)
begin
VAR102 <= 1'b1;
VAR41 <= VAR103;
end
if (VAR102)
begin
case(VAR85)
3'b000:
begin
VAR25 <= 1'b1;
VAR85 <= 1'b1;
end
3'b001:
begin
if(VAR31)
begin
VAR25 <= 1'b0;
VAR85 <= 3'b000;
VAR102 <= 1'b0;
end
end
endcase
end
end
end
reg [15:0] VAR75;
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR43 <= 1'b0;
VAR6 <= 1'b0;
VAR32 <= 1'b0;
VAR74 <= 1'b0;
VAR91 <= 3'b000;
VAR42 <= 22'h000000;
end
else
begin
if (VAR89 == VAR68)
begin
VAR6 <= 1'b0;
end
else if( VAR89 == VAR38 )
begin
VAR6 <= 1'b1;
end
if (VAR66 && (VAR84 == VAR37))
begin
VAR74 <= 1'b1;
end
if (VAR74)
begin
case(VAR91)
3'b000:
begin
if ((VAR63 == VAR5) && (VAR106 == VAR37))
begin
VAR42 <= VAR9[21:0];
VAR7 <= VAR1;
VAR32 <= 1'b1;
VAR91 <= 3'b001;
end
else
begin
VAR91 <= 3'b000;
VAR74 <= 1'b0;
end
end
3'b001:
begin
if (VAR17)
begin
if (VAR6 == 1'b0)
begin
VAR91 <= 3'b010;
end
else
begin
VAR91 <= 3'b000;
VAR74 <= 1'b0;
VAR32 <= 1'b0;
end
end
else
VAR75 <= VAR22;
end
3'b010:
begin
VAR78 <= VAR75[7:0];
VAR43 <= 1'b1;
VAR91 <= 3'b011;
end
3'b011:
begin
if (VAR31)
begin
VAR43 <= 1'b0;
VAR91 <= 3'b100;
end
end
3'b100:
begin
VAR78 <= VAR75[15:8];
VAR43 <= 1'b1;
VAR91 <= 3'b101;
end
3'b101:
begin
if (VAR31)
begin
VAR32 <= 1'b0;
VAR43 <= 1'b0;
VAR91 <= 3'b000;
VAR74 <= 1'b0;
end
end
endcase
end
end
end
assign VAR94 = VAR6 & VAR32;
assign VAR95 = ~VAR6 & VAR32;
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR53 <= 1'b0;
VAR59 <= 1'b0;
VAR77 <= 1'b0;
VAR46 <= 1'b0;
VAR47 <= 3'b000;
end
else
begin
if (VAR89 == VAR68)
begin
VAR59 <= 1'b0;
end
else if (VAR89 == VAR38)
begin
VAR59 <= 1'b1;
end
if (VAR66 && (VAR84 == VAR51))
begin
VAR46 <= 1'b1;
end
if (VAR46)
begin
case(VAR47)
3'b000:
begin
if ((VAR63 == VAR5) && (VAR106 == VAR51))
begin
VAR3 <= VAR9[17:0];
VAR10 <= VAR1;
VAR77 <= 1'b1;
VAR47 <= 3'b001;
end
else
begin
VAR47 <= 3'b000;
VAR46 <= 1'b0;
end
end
3'b001:
begin
if (VAR59 == 1'b0)
begin
VAR47 <= 3'b010;
end
else
begin
VAR47 <= 3'b000;
VAR46 <= 1'b0;
VAR77 <= 1'b0;
end
end
3'b010:
begin
VAR39 <= VAR49[7:0];
VAR53 <= 1'b1;
VAR47 <= 3'b011;
end
3'b011:
begin
if (VAR31)
begin
VAR53 <= 1'b0;
VAR47 <= 3'b100;
end
end
3'b100:
begin
VAR39 <= VAR49[15:8];
VAR53 <= 1'b1;
VAR47 <= 3'b101;
end
3'b101:
begin
if (VAR31)
begin
VAR77 <= 1'b0;
VAR53 <= 1'b0;
VAR47 <= 3'b000;
VAR46 <= 1'b0;
end
end
endcase
end
end
end
assign VAR48 = VAR59;
assign VAR61 = ~(VAR59 & VAR77);
always@(posedge VAR90 or negedge VAR56)
begin
if (!VAR56)
begin
VAR81 <= {10{1'b0}};
VAR104 <= {10{1'b0}};
VAR18 <= {10{1'b0}};
VAR69 <= {10{1'b0}};
VAR14 <= {10{1'b0}};
VAR57 <= 2'b00;
VAR80 <= 1'b0;
end
else
begin
if (VAR66 && (VAR84 == VAR73))
begin
VAR80 <= 1'b1;
end
if (VAR80)
begin
if ((VAR89 == VAR38) && (VAR63 == VAR70))
begin
case(VAR9[2:0])
3'b000: VAR57 <= VAR1[1:0];
3'b001: VAR81 <= VAR1[9:0];
3'b010: VAR104 <= VAR1[9:0];
3'b011: VAR18 <= VAR1[9:0];
3'b100: VAR69 <= VAR1[9:0];
3'b101: VAR14 <= VAR1[9:0];
endcase
end
VAR80 <= 1'b0;
end
end
end
endmodule
|
gpl-3.0
|
linuxbest/lzs
|
jhash/rtl/verilog/jhash_core.v
| 4,478 |
module MODULE1(
VAR22, VAR16, VAR13, VAR5,
clk, rst, VAR21, VAR34, VAR23, VAR29,
VAR28, VAR20, VAR33
);
input clk, rst, VAR21;
input [31:0] VAR34,
VAR23,
VAR29;
input VAR28;
input VAR20;
input [1:0] VAR33;
output VAR22;
output [31:0] VAR16;
output VAR13;
output VAR5;
reg VAR13;
reg VAR22;
wire [31:0] VAR9; wire [31:0] VAR7; wire [31:0] VAR25;
parameter [1:0]
VAR17 = 2'b00,
VAR2 = 2'b01,
VAR1 = 2'b10,
VAR30 = 2'b11;
reg [1:0]
state, VAR32;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= VAR17;
end
else
state <= VAR32;
end
reg [2:0] VAR8;
reg VAR31, VAR3;
always @(posedge clk)
if (VAR31)
VAR8 <= 3'b000;
else if (VAR3)
VAR8 <= VAR8 + 1'b1;
reg [31:0] VAR10, VAR11,
VAR26, VAR4,
VAR15, VAR35;
reg [4:0] VAR19, VAR27;
reg VAR24, VAR18;
VAR12 VAR12 (
.VAR9 (VAR9[31:0]),
.VAR7 (VAR7[31:0]),
.VAR25 (VAR25[31:0]),
.VAR10 (VAR10[31:0]),
.VAR26 (VAR26[31:0]),
.VAR15 (VAR15[31:0]),
.clk (clk),
.VAR19 (VAR19[4:0]));
always @(posedge clk)
begin
VAR10 <= VAR11;
VAR26 <= VAR4;
VAR15 <= VAR35;
VAR19 <= VAR27;
VAR24<=VAR18;
end
always @(VAR9 or VAR7 or VAR25 or VAR10 or VAR26 or VAR15 or VAR24
or VAR8 or VAR19 or state or VAR34
or VAR23 or VAR29 or VAR20
or VAR33 or VAR28)
begin
VAR11 = VAR10;
VAR4 = VAR26;
VAR35 = VAR15;
VAR32 = state;
VAR22 = 1'b0;
VAR27 = VAR19;
VAR3 = 1'b0;
VAR31 = 1'b0;
VAR18 = VAR24;
case (state)
VAR17: begin
VAR11 = 32'h0;
VAR4 = 32'h0;
VAR35 = 32'h0;
VAR18 = 1'b0;
if (VAR28) begin
VAR32 = VAR2;
end
end
VAR2: if (VAR20 && 1'b0) begin
VAR31 = 1'b1;
VAR27 = 4;
VAR32 = VAR1;
VAR18 = 1'b1;
case (VAR33)
2'b00: VAR32 = VAR30;
2'b01: begin
VAR11 = VAR10 + VAR34;
end
2'b10: begin
VAR11 = VAR10 + VAR34;
VAR4 = VAR26 + VAR23;
end
2'b11: begin
VAR11 = VAR10 + VAR34;
VAR4 = VAR26 + VAR23;
VAR35 = VAR15 + VAR29;
end
endcase end else if (VAR28) begin
VAR11 = VAR10 + VAR34;
VAR4 = VAR26 + VAR23;
VAR35 = VAR15 + VAR29;
VAR32 = VAR1;
VAR27 = 4;
VAR22 = 1'b1;
VAR31 = 1'b1;
end
VAR1: begin
VAR11 = VAR7;
VAR4 = VAR25;
VAR35 = VAR9;
VAR3 = 1'b1;
case (VAR8)
3'b000:
VAR27 = 6;
3'b001:
VAR27 = 8;
3'b010:
VAR27 = 16;
3'b011:
VAR27 = 19;
3'b100:
VAR27 = 4;
3'b101: begin
if (VAR20)
VAR32 = VAR30;
end
else
VAR32 = VAR2;
end
endcase end
VAR30: ;
endcase end
always @(posedge clk)
VAR13 <= state == VAR30;
assign VAR5 = VAR21 ? ~VAR13 : 1'VAR6;
assign VAR16 = VAR21 ? VAR15 : 32'VAR14;
endmodule MODULE1
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/inv/sky130_fd_sc_lp__inv_8.v
| 1,995 |
module MODULE2 (
VAR8 ,
VAR3 ,
VAR7,
VAR5,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR7;
input VAR5;
input VAR2 ;
input VAR4 ;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR7;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR4 ;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
romovs/xula-lib-verilog
|
SdramCtrl.v
| 38,105 |
module MODULE1 (VAR68, VAR32, VAR49, VAR85, VAR56, VAR36, VAR122, VAR74, VAR97,
VAR17, VAR27, VAR71, VAR116, VAR125, VAR29, VAR95, VAR37, VAR80,
VAR128, VAR22, VAR89, VAR137, VAR113, VAR47);
parameter real VAR8 = 12.0; parameter VAR96 = 0;
localparam VAR4 = 1; localparam VAR53 = 10000; localparam VAR2 = 1;
localparam VAR135 = 1; else
localparam VAR135 = 0;
localparam VAR75 = 16;
localparam VAR46 = 4096; localparam VAR35 = 512; localparam VAR107 = 23; localparam VAR114 = 12; localparam VAR63 = 2; localparam real VAR6 = 200000.0; localparam real VAR58 = 42.0; localparam real VAR111 = 15.0; localparam real VAR109 = 64000000.0; localparam real VAR79 = 60.0; localparam real VAR123 = 15.0; localparam real VAR119 = 72.0;
input wire VAR68; input wire VAR32; input wire VAR49; input wire VAR85; input wire VAR56; output reg VAR36; output wire VAR122; output reg VAR74; output reg VAR97; output reg VAR17; input wire [VAR107-1:0] VAR27; input wire [VAR75-1:0] VAR71; output wire [VAR75-1:0] VAR116; output reg [3:0] VAR125;
output VAR29; output VAR95; output VAR37; output VAR80; output VAR128; output [VAR63-1:0] VAR22; output [VAR114-1:0] VAR89; inout [VAR75-1:0] VAR137; output VAR113; output VAR47;
localparam [0:0] VAR54 = 1; localparam [0:0] VAR76 = 0;
localparam [0:0] VAR55 = 0; localparam [0:0] VAR101 = 1; localparam [0:0] VAR1 = 1;
localparam VAR104 = VAR103(VAR6*VAR8/1000.0); localparam VAR48 = VAR103(VAR58*VAR8/1000.0); localparam VAR134 = VAR21(VAR103(VAR111*VAR8/1000.0)); localparam VAR52 = VAR103(VAR109*VAR8/1000.0/VAR46); localparam VAR92 = VAR103(VAR79*VAR8/1000.0); localparam VAR40 = VAR103(VAR123*VAR8/1000.0); localparam VAR50 = 2; localparam VAR133 = VAR103(VAR119*VAR8/1000.0); localparam VAR90 = 2; localparam VAR28 = 3; localparam VAR38 = 8;
reg [VAR99(VAR104):0] VAR20 = 0; reg [VAR99(VAR104):0] VAR41 = 0;
reg [VAR99(VAR48):0] VAR115 = 0; reg [VAR99(VAR48):0] VAR34 = 0;
reg [VAR99(VAR50):0] VAR83 = 0; reg [VAR99(VAR50):0] VAR19 = 0;
reg [VAR99(VAR52):0] VAR124 = VAR52; reg [VAR99(VAR52):0] VAR84 = VAR52;
reg [VAR99(VAR38):0] VAR14 = 0; reg [VAR99(VAR38):0] VAR7 = 0;
reg [VAR99(VAR53):0] VAR138 = 0; reg [VAR99(VAR53):0] VAR82 = 0;
reg VAR108;
localparam [2:0] VAR59 = 3'b000; localparam [2:0] VAR132 = 3'b001; localparam [2:0] VAR62 = 3'b010; localparam [2:0] VAR57 = 3'b011; localparam [2:0] VAR10 = 3'b100; localparam [2:0] VAR39 = 3'b101; localparam [2:0] VAR23 = 3'b110; localparam [2:0] VAR127 = 3'b111;
reg [2:0] VAR64 = VAR59; reg [2:0] VAR112 = VAR59;
localparam [5:0] VAR5 = 'b011100;
localparam [5:0] VAR15 = 'b001100;
localparam [5:0] VAR106 = 'b010100;
localparam [5:0] VAR118 = 'b010000;
localparam [5:0] VAR51 = 'b001000;
localparam [5:0] VAR3 = 'b000000;
localparam [5:0] VAR31 = 'b000100;
localparam [11:0] VAR33 = 'b000000110000;
localparam VAR11 = VAR99(VAR46); localparam VAR9 = VAR99(VAR35);
reg [VAR63-1:0] VAR87; reg [VAR11-1:0] VAR86; reg [VAR9-1:0] VAR60;
localparam VAR77 = (VAR135 == 0 ? 1 : 2**VAR63);
localparam VAR93 = (VAR135 == 0 ? 1 : VAR63);
reg [VAR11-1:0] VAR91 [VAR93-1:0];
reg [VAR11-1:0] VAR69 [VAR93-1:0];
reg [VAR77-1:0] VAR126 = 0; reg [VAR77-1:0] VAR81 = 0;
reg [VAR93-1:0] VAR43; reg [VAR63-1:0] VAR65; reg [VAR63-1:0] VAR98;
reg VAR67;
localparam VAR117 = 10; localparam [0:0] VAR72 = 1; localparam [0:0] VAR131 = 0; localparam VAR70 = 0; localparam VAR129 = 1;
reg VAR30; reg VAR105; reg VAR139;
reg [VAR28+1:0] VAR94 = 0;
reg [VAR28+1:0] VAR78 = 0; reg VAR100 = 0;
reg VAR121 = 0;
reg VAR24 = 0;
reg VAR26 = 0; reg [VAR75-1:0] VAR61 = 0;
reg [VAR75-1:0] VAR25 = 0; reg [VAR75-1:0] VAR42;
reg [VAR75-1:0] VAR120;
reg VAR44 = 0;
reg VAR102 = 0; reg [5:0] VAR18 = VAR5;
reg [5:0] VAR110 = VAR5; reg [VAR63-1:0] VAR45;
reg [VAR63-1:0] VAR66; reg [VAR114-1:0] VAR130 = 0;
reg [VAR114-1:0] VAR12 = 0; reg [VAR75-1:0] VAR73 = 0;
reg [VAR75-1:0] VAR16 = 0; reg VAR13 = VAR76;
reg VAR136 = VAR76;
assign {VAR95, VAR37, VAR80, VAR128, VAR113, VAR47} = VAR18; assign VAR29 = VAR44; assign VAR22 = VAR45; assign VAR89 = VAR130; assign VAR137 = (VAR13 == VAR54) ? VAR73 : 16'VAR88;
assign VAR116 = VAR61; assign VAR122 = VAR24;
always @(VAR85, VAR56, VAR27, VAR71, VAR61, VAR137, VAR64, VAR26, VAR126,
VAR65, VAR94, VAR100, VAR42, VAR138,
VAR32, VAR14, VAR20, VAR115, VAR83, VAR124, VAR18, VAR60, VAR45, VAR44,
VAR105, VAR139, VAR30, VAR67, VAR108,
VAR91[1], VAR91[0]
VAR91[0]
) begin
VAR26 = 0; VAR36 = VAR26;
VAR102 = 1; VAR110 = VAR5; VAR136 = VAR76; VAR16 = VAR71; VAR112 = VAR64; VAR81 = VAR126;
VAR69[0] = VAR91[0];
VAR69[1] = VAR91[1];
VAR69[0] = VAR91[0];
VAR98 = VAR65;
VAR7 = VAR14;
VAR66 = VAR27[VAR63 + VAR11 + VAR9 - 1 : VAR11 + VAR9];
if (VAR135 == 1) begin
VAR87 = 0;
VAR43 = VAR66;
end else begin
VAR87 = VAR66;
VAR43 = 0;
end
VAR86 = VAR27[VAR11 + VAR9 - 1 : VAR9];
VAR60[VAR9-1 : 0] = VAR27[VAR9-1 : 0];
VAR12 = {1'b0, VAR131, VAR60[VAR9-1 : 0]};
if (VAR94[VAR28+1 : 1] != 0) begin
VAR105 = 1;
end else begin
VAR105 = 0;
end
VAR74 = VAR105;
VAR78 = {VAR55, VAR94[VAR28+1 : 1]};
VAR121 = VAR55;
if (VAR94[1] == VAR101) begin
VAR120 = VAR137[VAR75-1:0]; if (VAR4 == 1) begin
VAR25 = VAR137[VAR75-1:0];
end else begin
VAR25 = VAR42[VAR75-1:0];
end
end else begin
VAR120 = VAR42;
VAR25 = VAR61;
end
VAR97 = VAR94[0] | VAR100; VAR17 = VAR94[0];
if ((VAR87 != VAR65) || (VAR86 != VAR91[VAR43]) || (VAR126[VAR43] == 0)) begin
VAR67 = 1;
end else begin
VAR67 = 0;
end
if (VAR85 == 1 || VAR56 == 1) begin
VAR82 = 0;
VAR108 = 0;
end else if (VAR138 != VAR53) begin
VAR82 = VAR138 + 1;
VAR108 = 0;
end else begin
VAR82 = VAR138;
VAR108 = 1;
end
if (VAR115 != 0) begin
VAR34 = VAR115 - 1;
VAR139 = 1;
end else begin
VAR34 = VAR115;
VAR139 = 0;
end
if (VAR83 != 0) begin
VAR19 = VAR83 - 1;
VAR30 = 1;
end else begin
VAR19 = VAR83;
VAR30 = 0;
end
if (VAR124 != 0) begin
VAR84 = VAR124 - 1;
end else begin
VAR84 = VAR52;
if (VAR2 == 1) begin
VAR7 = VAR14 + 1;
end else begin
VAR7 = 0; end
end
if (VAR20 != 0) begin
VAR41 = VAR20 - 1;
VAR125 = 'b0000;
end else begin
VAR41 = VAR20;
case (VAR64)
VAR59: begin
if (VAR32 == 1) begin
VAR41 = VAR104; VAR112 = VAR132;
end else begin
VAR102 = 0;
end
VAR125 = 'b0001;
end
VAR132: begin
VAR110 = VAR51;
VAR12[VAR117] = VAR129; VAR41 = VAR40; VAR7 = VAR38; VAR112 = VAR57;
VAR125 = 'b0010;
end
VAR57: begin
VAR110 = VAR31;
VAR41 = VAR92; VAR7 = VAR14 - 1; if (VAR14 == 1) begin
VAR112 = VAR62; end
VAR125 = 'b0011;
end
VAR62: begin
VAR110 = VAR3;
VAR12[11:0] = VAR33; VAR41 = VAR90; VAR112 = VAR10;
VAR125 = 'b0100;
end
VAR10: begin
if (VAR14 != 0) begin
if (VAR139 == 0 && VAR30 == 0 && VAR105 == 0) begin
VAR110 = VAR51; VAR12[VAR117] = VAR129; VAR41 = VAR40; VAR81 = 0; VAR112 = VAR23; end
VAR125 = 'b0101;
end else if (VAR85 == 1) begin
if (VAR66 == VAR45 || VAR135 == 0) begin
if (VAR67 == 1) begin
if (VAR139 == 0 && VAR30 == 0 && VAR105 == 0) begin
VAR110 = VAR51; VAR12[VAR117] = VAR70; VAR41 = VAR40; VAR81[VAR43] = 0; VAR112 = VAR39; end
end else if (VAR105 == 0 || VAR96 == 1) begin
VAR110 = VAR106; VAR78 = {VAR101, VAR94[VAR28+1 : 1]};
VAR26 = 1; end
end
VAR125 = 'b0110;
end else if (VAR56 == 1) begin
if ((VAR66 == VAR45) || (VAR135 == 0)) begin
if (VAR67 == 1) begin
if ((VAR139 == 0) && (VAR30 == 0) && (VAR105 == 0)) begin
VAR110 = VAR51; VAR12[VAR117] = VAR70; VAR41 = VAR40; VAR81[VAR43] = 0; VAR112 = VAR39; end
end else if (VAR105 == 0) begin
VAR110 = VAR118; VAR136 = VAR54; VAR19 = VAR50;
VAR121 = VAR1;
VAR26 = 1; end
end
VAR125 = 'b0111;
end else if (VAR108 == 1) begin
if ((VAR139 == 0) && (VAR30 == 0) && (VAR105 == 0)) begin
VAR110 = VAR51; VAR12[VAR117] = VAR129; VAR41 = VAR40; VAR81 = 0; VAR112 = VAR127; end
VAR125 = 'b1000;
end else begin
VAR112 = VAR10; VAR125 = 'b1001;
end
end
VAR39: begin
VAR110 = VAR15;
VAR12 = 0; VAR12[VAR11 - 1:0] = VAR86;
VAR98 = VAR87;
VAR69[VAR43] = VAR86; VAR81[VAR43] = 1; VAR34 = VAR48; VAR41 = VAR134; VAR112 = VAR10; VAR125 = 'b1010;
end
VAR23: begin
VAR110 = VAR31;
VAR41 = VAR92; VAR7 = VAR14 - 1; VAR112 = VAR10; VAR125 = 'b1011;
end
VAR127: begin
if (VAR108 == 1 || VAR32 == 0) begin
VAR110 = VAR31; VAR102 = 0; end else begin
VAR102 = 1; VAR7 = 0; VAR81 = 0; VAR41 = VAR133; VAR112 = VAR10;
end
VAR125 = 'b1100;
end
default: begin
VAR112 = VAR59; VAR125 = 'b1101;
end
endcase
end
end
always @(posedge VAR68 or posedge VAR49) begin
if (VAR49 == 1) begin
VAR64 <= VAR59;
VAR126 <= 0;
VAR14 <= 0;
VAR20 <= 0;
VAR124 <= VAR52;
VAR115 <= 0;
VAR83 <= 0;
VAR138 <= 0;
VAR24 <= 0;
VAR94 <= 0;
VAR100 <= 0;
VAR44 <= 0;
VAR18 <= VAR5;
VAR45 <= 0;
VAR130 <= 0;
VAR73 <= 0;
VAR13 <= VAR76;
VAR61 <= 0;
end else begin
VAR64 <= VAR112;
VAR65 <= VAR98;
VAR91[0] = VAR69[0];
VAR91[1] = VAR69[1];
VAR91[0] = VAR69[0];
VAR126 <= VAR81;
VAR14 <= VAR7;
VAR20 <= VAR41;
VAR124 <= VAR84;
VAR115 <= VAR34;
VAR83 <= VAR19;
VAR138 <= VAR82;
VAR24 <= VAR26;
VAR94 <= VAR78;
VAR100 <= VAR121;
VAR44 <= VAR102;
VAR18 <= VAR110;
VAR45 <= VAR66;
VAR130 <= VAR12;
VAR73 <= VAR16;
VAR13 <= VAR136;
VAR61 <= VAR25;
end
end
always @(negedge VAR68 or posedge VAR49) begin
if (VAR49 == 1) begin
VAR42 <= 0;
end else begin
VAR42 <= VAR120;
end
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/and2/sky130_fd_sc_hs__and2.symbol.v
| 1,224 |
module MODULE1 (
input VAR1,
input VAR2,
output VAR4
);
supply1 VAR5;
supply0 VAR3;
endmodule
|
apache-2.0
|
monotone-RK/FACE
|
IEICE-Trans/bandwidth/PCIe/src/ip_dram/phy/mig_7series_v2_3_ddr_mc_phy_wrapper.v
| 71,915 |
module MODULE1 #
(
parameter VAR213 = 100, parameter VAR356 = 2500, parameter VAR344 = "VAR291", parameter VAR218 = "VAR448", parameter VAR489 = "VAR454", parameter VAR176 = "VAR129",
parameter VAR393 = 1,
parameter VAR245 = 4, parameter VAR328 = 1, parameter VAR297 = 3, parameter VAR433 = 1, parameter VAR374 = 1, parameter VAR279 = 1, parameter VAR157 = 5, parameter VAR292 = "VAR303", parameter VAR457 = 8, parameter VAR447 = 16, parameter VAR95 = 3, parameter VAR190 = 8, parameter VAR73 = "VAR462", parameter VAR469 = 4, parameter VAR173 = 1, parameter VAR256 = "VAR16",
parameter VAR59 = "VAR269", parameter VAR187 = 16, parameter VAR153 = 1, parameter VAR28 = 1, parameter VAR34 = 1, parameter VAR107 = "VAR269", parameter VAR215 = 2,
parameter VAR357 = "VAR16",
parameter VAR161 = 4'hc,
parameter VAR77 = 4'hf,
parameter VAR112 = 4'hf,
parameter VAR185 = 4'hf,
parameter VAR336 = 4'hf,
parameter VAR325 = 4'b1111,
parameter VAR321 = 4'b0000,
parameter VAR217 = 4'b0000,
parameter VAR117 = 4'b0000,
parameter VAR181 = 4'b0000,
parameter VAR136 = 48'h000000000000,
parameter VAR365 = 48'h000000000000,
parameter VAR490 = 48'h000000000000,
parameter VAR239 = 3, parameter VAR249 = 12, parameter VAR491
= 144'h000000000000000000000000000000000000,
parameter VAR201
= 192'h000000000000000000000000000000000000000000000000,
parameter VAR178 = 36'h000000000,
parameter VAR317 = 12'h000,
parameter VAR48 = 8'h00,
parameter VAR116 = 96'h000000000000000000000000,
parameter VAR103 = 96'h000000000000000000000000,
parameter VAR359 = "VAR16",
parameter VAR478 = 120'h000000000000000000000000000000,
parameter VAR483 = 12'h000,
parameter VAR372 = 12'h000,
parameter VAR225 = 12'h000,
parameter VAR113
= 144'h000000000000000000000000000000000000,
parameter VAR197 = 96'h000000000000000000000000,
parameter VAR104 = 96'h000000000000000000000000,
parameter VAR51 = 96'h000000000000000000000000,
parameter VAR44 = 96'h000000000000000000000000,
parameter VAR369 = 96'h000000000000000000000000,
parameter VAR145 = 96'h000000000000000000000000,
parameter VAR299 = 96'h000000000000000000000000,
parameter VAR407 = 96'h000000000000000000000000,
parameter VAR300 = 96'h000000000000000000000000,
parameter VAR488 = 96'h000000000000000000000000,
parameter VAR24 = 96'h000000000000000000000000,
parameter VAR223 = 96'h000000000000000000000000,
parameter VAR18 = 96'h000000000000000000000000,
parameter VAR273 = 96'h000000000000000000000000,
parameter VAR115 = 96'h000000000000000000000000,
parameter VAR200 = 96'h000000000000000000000000,
parameter VAR55 = 96'h000000000000000000000000,
parameter VAR345 = 96'h000000000000000000000000,
parameter VAR183 = 108'h000000000000000000000000000,
parameter VAR131 = 108'h000000000000000000000000000,
parameter VAR15 = "VAR141",
parameter VAR255 = 1,
parameter VAR441 = 8
)
(
input rst,
input VAR149,
input clk,
input VAR250,
input VAR205,
input VAR123,
input VAR203,
input VAR106,
input VAR27,
input VAR229,
input VAR126,
input [31:0] VAR330,
input VAR23,
input VAR9,
input VAR33,
input [5:0] VAR293,
input [5:0] VAR146,
input [3:0] VAR486,
input [3:0] VAR465,
output [4:0] VAR263,
output [5:0] VAR120,
output VAR485,
output VAR151,
output VAR222,
output VAR380,
output VAR443,
output [(VAR279 * VAR215)-1:0] VAR29,
output VAR348,
input VAR163,
input VAR196,
input VAR235,
input [5:0] VAR1,
input [VAR95:0] VAR128,
input [VAR441-1:0] VAR450,
input VAR234,
input [VAR239-1:0] VAR121,
input [VAR239-1:0] VAR182,
input [2:0] VAR35,
input [2:0] VAR227,
input [2:0] VAR260,
input [2:0] VAR144,
input VAR56,
input VAR13,
input [2:0] VAR384,
input [8:0] VAR42,
output [8:0] VAR308,
output [5:0] VAR480,
input [VAR239-1:0] VAR387,
input VAR315,
input VAR86,
input VAR419,
input [5:0] VAR43,
input VAR468,
input VAR332,
input VAR66,
input VAR100,
output VAR99,
output VAR277,
output VAR172,
output VAR220,
output VAR102,
input VAR389,
input [VAR245*VAR187-1:0] VAR184,
input [VAR245*VAR297-1:0] VAR38,
input [VAR245-1:0] VAR413,
input [VAR374*VAR328*VAR245-1:0] VAR320,
input [VAR245-1:0] VAR408,
input [1:0] VAR26,
input [VAR245-1:0] VAR2,
input [VAR245-1:0] VAR394,
input [VAR245-1:0] VAR238,
input [2*VAR245*VAR447-1:0] VAR74,
input [2*VAR245*(VAR447/8)-1:0] VAR125,
input VAR92,
output [2*VAR245*VAR447-1:0] VAR71,
output [VAR187-1:0] VAR5,
output [VAR297-1:0] VAR331,
output VAR246,
output [VAR433-1:0] VAR164,
output [VAR374*VAR328-1:0] VAR233,
output [VAR457-1:0] VAR60,
output [VAR173-1:0] VAR96,
output VAR305,
output VAR423,
output VAR254,
output VAR214,
inout [VAR447-1:0] VAR363,
inout [VAR190-1:0] VAR289,
inout [VAR190-1:0] VAR360,
output VAR463
,input VAR403
,output VAR12
,input VAR437
,output [11:0] VAR156
,output [11:0] VAR494
);
function [71:0] VAR492;
input [143:0] VAR298;
integer VAR211 ;
begin
VAR492 = 'b0 ;
for (VAR211 = 0; VAR211 < VAR279; VAR211 = VAR211 + 1) begin
if ((VAR491[((VAR211*8)+4)+:4]) == 2)
VAR492[48+(4*VAR211)+1*(VAR491[(VAR211*8)+:4])] = 1'b1;
end
else if ((VAR491[((VAR211*8)+4)+:4]) == 1)
VAR492[24+(4*VAR211)+1*(VAR491[(VAR211*8)+:4])] = 1'b1;
end
else
VAR492[4*VAR211+1*(VAR491[(VAR211*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*VAR279*8)-1:0] VAR194;
input [143:0] VAR298;
integer VAR147;
begin
VAR194 = 'b0 ;
for(VAR147 = 0 ; VAR147 < VAR279 ; VAR147= VAR147 + 1) begin
VAR194[(VAR147*2*8)+:8] = (VAR298[(VAR147*8)+:4] == 4'd0) ? "VAR442" :
(VAR298[(VAR147*8)+:4] == 4'd1) ? "VAR8" :
(VAR298[(VAR147*8)+:4] == 4'd2) ? "VAR487" : "VAR306" ;
VAR194[(((VAR147*2)+1)*8)+:8] = (VAR298[((VAR147*8)+4)+:4] == 4'd0) ? "0" :
(VAR298[((VAR147*8)+4)+:4] == 4'd1) ? "1" : "2" ; end
end
endfunction
localparam VAR248
= (VAR107 == "VAR269") ? "VAR16" :
((VAR107 == "VAR454") ? "VAR270" : "VAR402");
localparam VAR242 = VAR447 / VAR190;
localparam VAR109 = 2*VAR245;
localparam VAR216 = 4 / VAR245;
localparam VAR329 = VAR356 * VAR245;
localparam VAR101 = {VAR345[12*VAR242-1:0],
VAR55[12*VAR242-1:0],
VAR200[12*VAR242-1:0],
VAR115[12*VAR242-1:0],
VAR273[12*VAR242-1:0],
VAR18[12*VAR242-1:0],
VAR223[12*VAR242-1:0],
VAR24[12*VAR242-1:0],
VAR488[12*VAR242-1:0],
VAR300[12*VAR242-1:0],
VAR407[12*VAR242-1:0],
VAR299[12*VAR242-1:0],
VAR145[12*VAR242-1:0],
VAR369[12*VAR242-1:0],
VAR44[12*VAR242-1:0],
VAR51[12*VAR242-1:0],
VAR104[12*VAR242-1:0],
VAR197[12*VAR242-1:0]};
localparam VAR137 = {VAR131, VAR183};
localparam VAR253 = VAR492(VAR491) ;
localparam VAR285 = VAR194(VAR491) ;
function [143:0] VAR21;
input [215:0] VAR326;
integer VAR310;
begin
VAR21 = 'b0;
if (VAR28 == 1)
for (VAR310 = 0; VAR310 < VAR457; VAR310 = VAR310 + 1)
VAR21[48*VAR326[(12*VAR310+8)+:3] +
12*VAR326[(12*VAR310+4)+:2] +
VAR326[12*VAR310+:4]] = 1'b1;
end
endfunction
localparam VAR334 = VAR21(VAR137);
localparam VAR472 = VAR334[47:0];
localparam VAR114 = VAR334[95:48];
localparam VAR461 = VAR334[143:96];
localparam VAR493
= (VAR48[7:4] == 4'h0) ? 0 :
((VAR48[7:4] == 4'h1) ? 1 :
((VAR48[7:4] == 4'h2) ? 2 :
((VAR48[7:4] == 4'h3) ? 3 :
((VAR48[7:4] == 4'h4) ? 4 : -1))));
localparam VAR25
= (VAR48[3:0] == 4'h0) ? "VAR442" :
((VAR48[3:0] == 4'h1) ? "VAR8" :
((VAR48[3:0] == 4'h2) ? "VAR487" :
((VAR48[3:0] == 4'h3) ? "VAR306" : "VAR402")));
localparam VAR240
= (VAR116[11:8] == 4'h0) ? 0 :
((VAR116[11:8] == 4'h1) ? 1 :
((VAR116[11:8] == 4'h2) ? 2 :
((VAR116[11:8] == 4'h3) ? 3 :
((VAR116[11:8] == 4'h4) ? 4 : -1))));
localparam VAR47
= (VAR116[7:4] == 4'h0) ? "VAR442" :
((VAR116[7:4] == 4'h1) ? "VAR8" :
((VAR116[7:4] == 4'h2) ? "VAR487" :
((VAR116[7:4] == 4'h3) ? "VAR306" : "VAR402")));
localparam VAR78 = (VAR359 == "VAR270") ? VAR493 : VAR240 ;
localparam VAR140 = (VAR359 == "VAR270") ? VAR25 : VAR47 ;
localparam VAR471 = (((VAR15 == "VAR141") && (VAR356 > 2500)) || (VAR356 >= 3333)) ? "VAR16" : "VAR270";
localparam VAR259 = VAR356 > 5000 ? "VAR80" :
VAR356 > 2500 ? "VAR79": "VAR141";
localparam VAR32 = (VAR259 == "VAR80" ? 4 :
VAR259 == "VAR79" ? 2 : 1);
localparam real VAR342 = 0.4392/VAR32 + 100.0/VAR356;
localparam real VAR281 = 0.5*(VAR471 == "VAR270" ? 1 : 0);
localparam real VAR169 = ((VAR471 == "VAR270" ? 1.25 : 0.25) -
(VAR342 + VAR281))
* 63 * VAR32;
localparam integer VAR470
= (VAR356 > 2273) ? 34 :
(VAR356 > 2000) ? 33 :
(VAR356 > 1724) ? 32 :
(VAR356 > 1515) ? 31 :
(VAR356 > 1315) ? 30 :
(VAR356 > 1136) ? 29 :
(VAR356 > 1021) ? 28 : 27;
localparam integer VAR280 = (VAR15 == "VAR141") ?
((VAR356 > 2500) ? 8 :
(VAR73 == "VAR462") ? VAR470 : 30) :
VAR169;
localparam VAR148 = (VAR15 != "VAR85") ? 0 :
(VAR356 < 1000) ? 0 :
(VAR356 < 1330) ? 0 :
(VAR356 < 2300) ? 0 :
(VAR356 < 2500) ? 2 : 0;
localparam VAR19 = 10;
localparam VAR7 = 10;
localparam VAR4 = 10;
localparam VAR64 = 10;
localparam VAR20 = (VAR245 == 4) ? 8 : 4;
localparam VAR155 = (VAR245 == 4) ? 8 : 4;
localparam VAR118 = (VAR245 == 4) ? 8 : 4;
localparam VAR237 = (VAR245 == 4) ? 8 : 4;
localparam VAR165 = 7;
localparam VAR373 = 7;
localparam VAR226 = 7;
localparam VAR67 = 7;
localparam VAR446 = (VAR59 == "VAR454") ? VAR157 + 1 : VAR157;
localparam VAR167 = (VAR245 == 4) ? (VAR446 % 2) ? 8 : 9 :
(VAR157 < 7) ?
4 + ((VAR446 % 2) ? 0 : 1) :
5 + ((VAR446 % 2) ? 0 : 1);
localparam VAR180 = (VAR245 == 4) ? "VAR270" : "VAR16";
wire [((VAR249+3)/4)*4-1:0] VAR412;
wire [VAR249-1:0] VAR333;
wire [VAR249-1:0] VAR340;
wire [VAR249-1:0] VAR343;
wire [VAR249*10-1:0] VAR367;
wire [VAR249*12-1:0] VAR282;
wire [VAR249*12-1:0] VAR427;
wire [VAR447-1:0] VAR482;
wire [VAR190-1:0] VAR186;
wire [VAR187-1:0] VAR89;
wire [VAR297-1:0] VAR264;
wire VAR247;
wire [VAR374*VAR328-1:0] VAR195;
wire [VAR457-1:0] VAR158;
wire [VAR173 -1:0] VAR322;
wire [VAR433 -1 :0] VAR456 ;
wire [VAR447-1:0] VAR267;
wire [VAR190-1:0] VAR392;
wire VAR319;
wire VAR122;
wire VAR22;
wire [VAR249*80-1:0] VAR133;
wire [VAR249*80-1:0] VAR386;
wire VAR45;
wire [VAR457-1:0] VAR39;
wire [VAR447-1:0] VAR421;
wire [VAR190-1:0] VAR440;
wire [VAR190-1:0] VAR83;
wire [VAR190-1:0] VAR53;
reg [31:0] VAR284;
reg [31:0] VAR6;
reg VAR199;
reg VAR314;
reg [5:0] VAR375;
reg [5:0] VAR275;
reg [5:0] VAR76;
reg [5:0] VAR476;
wire [31:0] VAR142;
wire VAR353;
wire [5:0] VAR391;
wire [5:0] VAR484;
wire [5:0] VAR258;
wire [5:0] VAR221;
wire [31:0] VAR286;
wire VAR138 ;
wire [3:0] VAR453;
wire VAR268;
reg [29:0] VAR341; reg VAR31;
wire [VAR95:0] VAR337;
assign VAR45 = !VAR485;
assign VAR263 = VAR148;
assign VAR120 = VAR280;
assign VAR268 = VAR489 == "VAR454" ? VAR100 : 1'b0;
generate
if(VAR359 == "VAR270")begin:VAR411
if (VAR433 == 1) begin : VAR316
VAR467 VAR388
(
.VAR174 (VAR412[4*VAR78]),
.VAR376 (VAR164)
);
end else begin: VAR399
VAR467 VAR204
(
.VAR174 (VAR412[4*VAR78]),
.VAR376 (VAR164[0])
);
VAR467 VAR395
(
.VAR174 (VAR412[4*VAR78+2]),
.VAR376 (VAR164[1])
);
end
end
endgenerate
generate
if(VAR359 == "VAR270")begin:VAR232
if (VAR34 == 1) begin : VAR135
VAR467 VAR397
(
.VAR174 (VAR412[4*VAR78+1]),
.VAR376 (VAR96[0])
);
if (VAR173 == 2 && VAR469 == 1) begin: VAR416
VAR467 VAR444
(
.VAR174 (VAR412[4*VAR78+2]),
.VAR376 (VAR96[1])
);
end else if (VAR173 == 2 && VAR469 == 2) begin: VAR91
VAR467 VAR444
(
.VAR174 (VAR412[4*VAR78+3]),
.VAR376 (VAR96[1])
);
end else if (VAR173 == 3 && VAR469 == 1) begin: VAR266
VAR467 VAR444
(
.VAR174 (VAR412[4*VAR78+2]),
.VAR376 (VAR96[1])
);
VAR467 VAR188
(
.VAR174 (VAR412[4*VAR78+3]),
.VAR376 (VAR96[2])
);
end
end else begin
assign VAR96 = 'b0;
end
end
endgenerate
generate
genvar VAR378, VAR477;
for (VAR378 = 0; VAR378 < VAR447; VAR378 = VAR378 + 1) begin: VAR154
for (VAR477 = 0; VAR477 < VAR109; VAR477 = VAR477 + 1) begin: VAR130
assign VAR71[VAR447*VAR477 + VAR378]
= VAR133[(320*VAR101[(12*VAR378+8)+:3]+
80*VAR101[(12*VAR378+4)+:2] +
8*VAR101[12*VAR378+:4]) + VAR477];
end
end
endgenerate
reg [11:0] VAR72;
reg [95:0] VAR355;
assign VAR337 = VAR128;
always @ (posedge clk) begin
end
always @ (posedge clk) begin
end
assign VAR247
= VAR282[48*VAR317[10:8] + 12*VAR317[5:4] + VAR317[3:0]];
generate
if (VAR317[3:0] < 4'hA) begin: VAR265
assign VAR386[(320*VAR317[10:8] + 80*VAR317[5:4] +
8*VAR317[3:0])+:4]
= {VAR413[3/VAR216], VAR413[2/VAR216],
VAR413[1/VAR216], VAR413[0]};
end else begin: VAR435
assign VAR386[(320*VAR317[10:8] + 80*VAR317[5:4] +
8*(VAR317[3:0]-5) + 4)+:4]
= {VAR413[3/VAR216], VAR413[2/VAR216],
VAR413[1/VAR216], VAR413[0]};
end
endgenerate
assign VAR122
= VAR282[48*VAR372[10:8] + 12*VAR372[5:4] + VAR372[3:0]];
generate
if (VAR372[3:0] < 4'hA) begin: VAR132
assign VAR386[(320*VAR372[10:8] + 80*VAR372[5:4] +
8*VAR372[3:0])+:4]
= {VAR408[3/VAR216], VAR408[2/VAR216],
VAR408[1/VAR216], VAR408[0]};
end else begin: VAR209
assign VAR386[(320*VAR372[10:8] + 80*VAR372[5:4] +
8*(VAR372[3:0]-5) + 4)+:4]
= {VAR408[3/VAR216], VAR408[2/VAR216],
VAR408[1/VAR216], VAR408[0]};
end
endgenerate
assign VAR22
= VAR282[48*VAR225[10:8] + 12*VAR225[5:4] + VAR225[3:0]];
generate
if (VAR225[3:0] < 4'hA) begin: VAR420
assign VAR386[(320*VAR225[10:8] + 80*VAR225[5:4] +
8*VAR225[3:0])+:4]
= {VAR394[3/VAR216], VAR394[2/VAR216],
VAR394[1/VAR216], VAR394[0]};
end else begin: VAR61
assign VAR386[(320*VAR225[10:8] + 80*VAR225[5:4] +
8*(VAR225[3:0]-5) + 4)+:4]
= {VAR394[3/VAR216], VAR394[2/VAR216],
VAR394[1/VAR216], VAR394[0]};
end
endgenerate
generate
if (VAR59 == "VAR454") begin: VAR262
assign VAR319
= VAR282[48*VAR483[10:8] + 12*VAR483[5:4] +
VAR483[3:0]];
if (VAR483[3:0] < 4'hA) begin: VAR361
assign VAR386[(320*VAR483[10:8] + 80*VAR483[5:4] +
8*VAR483[3:0])+:4]
= {VAR238[3/VAR216], VAR238[2/VAR216],
VAR238[1/VAR216], VAR238[0]};
end else begin: VAR88
assign VAR386[(320*VAR483[10:8] + 80*VAR483[5:4] +
8*(VAR483[3:0]-5) + 4)+:4]
= {VAR238[3/VAR216], VAR238[2/VAR216],
VAR238[1/VAR216], VAR238[0]};
end
end
endgenerate
generate
genvar VAR81, VAR401,VAR318;
for (VAR81 = 0; VAR81 < VAR187; VAR81 = VAR81 + 1) begin: VAR362
assign VAR89[VAR81]
= VAR282[48*VAR201[(12*VAR81+8)+:3] +
12*VAR201[(12*VAR81+4)+:2] +
VAR201[12*VAR81+:4]];
if (VAR201[12*VAR81+:4] < 4'hA) begin: VAR361
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR201[(12*VAR81+8)+:3] +
80*VAR201[(12*VAR81+4)+:2] +
8*VAR201[12*VAR81+:4] + VAR401]
= VAR184[VAR187*(VAR401/VAR216) + VAR81];
end
end else begin: VAR88
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR201[(12*VAR81+8)+:3] +
80*VAR201[(12*VAR81+4)+:2] +
8*(VAR201[12*VAR81+:4]-5) + 4 + VAR401]
= VAR184[VAR187*(VAR401/VAR216) + VAR81];
end
end
end
for (VAR81 = 0; VAR81 < VAR297; VAR81 = VAR81 + 1) begin: VAR406
assign VAR264[VAR81]
= VAR282[48*VAR178[(12*VAR81+8)+:3] +
12*VAR178[(12*VAR81+4)+:2] +
VAR178[12*VAR81+:4]];
if (VAR178[12*VAR81+:4] < 4'hA) begin: VAR361
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR178[(12*VAR81+8)+:3] +
80*VAR178[(12*VAR81+4)+:2] +
8*VAR178[12*VAR81+:4] + VAR401]
= VAR38[VAR297*(VAR401/VAR216) + VAR81];
end
end else begin: VAR88
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR178[(12*VAR81+8)+:3] +
80*VAR178[(12*VAR81+4)+:2] +
8*(VAR178[12*VAR81+:4]-5) + 4 + VAR401]
= VAR38[VAR297*(VAR401/VAR216) + VAR81];
end
end
end
if (VAR153 == 1) begin: VAR449
for (VAR81 = 0; VAR81 < VAR374*VAR328; VAR81 = VAR81 + 1) begin: VAR351
assign VAR195[VAR81]
= VAR282[48*VAR478[(12*VAR81+8)+:3] +
12*VAR478[(12*VAR81+4)+:2] +
VAR478[12*VAR81+:4]];
if (VAR478[12*VAR81+:4] < 4'hA) begin: VAR361
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR478[(12*VAR81+8)+:3] +
80*VAR478[(12*VAR81+4)+:2] +
8*VAR478[12*VAR81+:4] + VAR401]
= VAR320[VAR374*VAR328*(VAR401/VAR216) + VAR81];
end
end else begin: VAR88
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR478[(12*VAR81+8)+:3] +
80*VAR478[(12*VAR81+4)+:2] +
8*(VAR478[12*VAR81+:4]-5) + 4 + VAR401]
= VAR320[VAR374*VAR328*(VAR401/VAR216) + VAR81];
end
end
end
end
if(VAR359 == "VAR16") begin
wire [VAR173*VAR245 -1 :0] VAR290 ;
if(VAR469 == 1) begin
for(VAR318 =0 ; VAR318 < VAR245 ; VAR318 = VAR318+1) begin
assign VAR290[(VAR318*VAR173)+:VAR173] = {VAR173{VAR26[0]}} ;
end
end else begin
for(VAR318 =0 ; VAR318 < 2*VAR245 ; VAR318 = VAR318+2) begin
assign VAR290[(VAR318*VAR173/VAR469)+:VAR173/VAR469] = {VAR173/VAR469{VAR26[0]}} ;
assign VAR290[((VAR318*VAR173/VAR469)+(VAR173/VAR469))+:VAR173/VAR469] = {VAR173/VAR469{VAR26[1]}} ;
end
end
if (VAR34 == 1) begin: VAR82
for (VAR81 = 0; VAR81 < VAR173; VAR81 = VAR81 + 1) begin: VAR390
assign VAR322[VAR81]
= VAR282[48*VAR103[(12*VAR81+8)+:3] +
12*VAR103[(12*VAR81+4)+:2] +
VAR103[12*VAR81+:4]];
if (VAR103[12*VAR81+:4] < 4'hA) begin: VAR361
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR103[(12*VAR81+8)+:3] +
80*VAR103[(12*VAR81+4)+:2] +
8*VAR103[12*VAR81+:4] + VAR401]
= VAR290[VAR173*(VAR401/VAR216) + VAR81];
end
end else begin: VAR88
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR103[(12*VAR81+8)+:3] +
80*VAR103[(12*VAR81+4)+:2] +
8*(VAR103[12*VAR81+:4]-5) + 4 + VAR401]
= VAR290[VAR173*(VAR401/VAR216) + VAR81];
end
end
end
end
wire [VAR433*VAR245 -1:0] VAR428 ;
for(VAR318 = 0 ; VAR318 < VAR245 ; VAR318 = VAR318 +1) begin
assign VAR428[(VAR318*VAR433)+:VAR433] = {VAR433{VAR2[VAR318]}} ;
end
for (VAR81 = 0; VAR81 < VAR433; VAR81 = VAR81 + 1) begin: VAR17
assign VAR456[VAR81]
= VAR282[48*VAR116[(12*VAR81+8)+:3] +
12*VAR116[(12*VAR81+4)+:2] +
VAR116[12*VAR81+:4]];
if (VAR116[12*VAR81+:4] < 4'hA) begin: VAR361
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR116[(12*VAR81+8)+:3] +
80*VAR116[(12*VAR81+4)+:2] +
8*VAR116[12*VAR81+:4] + VAR401]
= VAR428[VAR433*(VAR401/VAR216) + VAR81];
end
end else begin: VAR88
for (VAR401 = 0; VAR401 < 4; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR116[(12*VAR81+8)+:3] +
80*VAR116[(12*VAR81+4)+:2] +
8*(VAR116[12*VAR81+:4]-5) + 4 + VAR401]
= VAR428[VAR433*(VAR401/VAR216) + VAR81];
end
end
end
end
if (VAR28 == 1) begin: VAR93
for (VAR81 = 0; VAR81 < VAR457; VAR81 = VAR81 + 1) begin: VAR93
assign VAR158[VAR81]
= VAR282[48*VAR137[(12*VAR81+8)+:3] +
12*VAR137[(12*VAR81+4)+:2] +
VAR137[12*VAR81+:4]];
assign VAR39[VAR81]
= VAR427[48*VAR137[(12*VAR81+8)+:3] +
12*VAR137[(12*VAR81+4)+:2] +
VAR137[12*VAR81+:4]];
for (VAR401 = 0; VAR401 < VAR109; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR137[(12*VAR81+8)+:3] +
80*VAR137[(12*VAR81+4)+:2] +
8*VAR137[12*VAR81+:4] + VAR401]
= VAR125[VAR457*VAR401 + VAR81];
end
end
end
for (VAR81 = 0; VAR81 < VAR447; VAR81 = VAR81 + 1) begin: VAR152
assign VAR367[40*VAR101[(12*VAR81+8)+:3] +
10*VAR101[(12*VAR81+4)+:2] +
VAR101[12*VAR81+:4]]
= VAR482[VAR81];
assign VAR267[VAR81]
= VAR282[48*VAR101[(12*VAR81+8)+:3] +
12*VAR101[(12*VAR81+4)+:2] +
VAR101[12*VAR81+:4]];
assign VAR421[VAR81]
= VAR427[48*VAR101[(12*VAR81+8)+:3] +
12*VAR101[(12*VAR81+4)+:2] +
VAR101[12*VAR81+:4]];
for (VAR401 = 0; VAR401 < VAR109; VAR401 = VAR401 + 1) begin: VAR346
assign VAR386[320*VAR101[(12*VAR81+8)+:3] +
80*VAR101[(12*VAR81+4)+:2] +
8*VAR101[12*VAR81+:4] + VAR401]
= VAR74[VAR447*VAR401 + VAR81];
end
end
for (VAR81 = 0; VAR81 < VAR190; VAR81 = VAR81 + 1) begin: VAR134
assign VAR333[4*VAR113[(8*VAR81+4)+:3] + VAR113[(8*VAR81)+:2]]
= VAR186[VAR81];
assign VAR392[VAR81]
= VAR340[4*VAR113[(8*VAR81+4)+:3] + VAR113[(8*VAR81)+:2]];
assign VAR440[VAR81]
= VAR343[4*VAR113[(8*VAR81+4)+:3] + VAR113[(8*VAR81)+:2]];
end
endgenerate
assign VAR463 = VAR53[VAR337];
VAR467 VAR236
(
.VAR174 (VAR247),
.VAR376 (VAR246)
);
VAR467 VAR381
(
.VAR174 (VAR122),
.VAR376 (VAR423)
);
VAR467 VAR52
(
.VAR174 (VAR22),
.VAR376 (VAR254)
);
generate
genvar VAR302;
for (VAR302 = 0; VAR302 < VAR187; VAR302 = VAR302 + 1) begin: VAR335
VAR467 VAR430
(
.VAR174 (VAR89[VAR302]),
.VAR376 (VAR5[VAR302])
);
end
for (VAR302 = 0; VAR302 < VAR297; VAR302 = VAR302 + 1) begin: VAR191
VAR467 VAR276
(
.VAR174 (VAR264[VAR302]),
.VAR376 (VAR331[VAR302])
);
end
if (VAR153 == 1) begin: VAR177
for (VAR302 = 0; VAR302 < VAR374*VAR328; VAR302 = VAR302 + 1) begin: VAR65
VAR467 VAR108
(
.VAR174 (VAR195[VAR302]),
.VAR376 (VAR233[VAR302])
);
end
end
if(VAR359 == "VAR16")begin:VAR189
if (VAR34== 1) begin: VAR166
for (VAR302 = 0; VAR302 < VAR173; VAR302 = VAR302 + 1) begin: VAR166
VAR467 VAR108
(
.VAR174 (VAR322[VAR302]),
.VAR376 (VAR96[VAR302])
);
end
end
for (VAR302 = 0; VAR302 < VAR433; VAR302 = VAR302 + 1) begin: VAR119
VAR467 VAR108
(
.VAR174 (VAR456[VAR302]),
.VAR376 (VAR164[VAR302])
);
end
end
if (VAR59 == "VAR454") begin: VAR94
VAR467 VAR366
(
.VAR174 (VAR319),
.VAR376 (VAR305)
);
end else begin: VAR10
assign VAR305 = 1'b0;
end
if ((VAR73 == "VAR462") || (VAR59 == "VAR454")) begin: VAR261
VAR467 VAR404
(
.VAR174 (VAR92),
.VAR376 (VAR214)
);
end else begin: VAR98
assign VAR214 = 1'b1;
end
if (VAR28 == 1) begin: VAR409
for (VAR302 = 0; VAR302 < VAR457; VAR302 = VAR302 + 1) begin: VAR192
VAR382 VAR90
(
.VAR174 (VAR158[VAR302]),
.VAR460 (VAR39[VAR302]),
.VAR376 (VAR60[VAR302])
);
end
end else begin: VAR429
assign VAR60 = 'b0;
end
if (VAR218 == "VAR451") begin: VAR405
for (VAR302 = 0; VAR302 < VAR447; VAR302 = VAR302 + 1) begin: VAR14
VAR87 #
(
.VAR248 (VAR248)
)
VAR30
(
.VAR496 (VAR268),
.VAR459 (VAR268),
.VAR174 (VAR267[VAR302]),
.VAR460 (VAR421[VAR302]),
.VAR376 (VAR482[VAR302]),
.VAR495 (VAR363[VAR302])
);
end
end else if (VAR218 == "VAR75") begin: VAR464
for (VAR302 = 0; VAR302 < VAR447; VAR302 = VAR302 + 1) begin: VAR14
VAR301 #
(
.VAR248 (VAR248)
)
VAR30
(
.VAR162 (VAR268),
.VAR459 (VAR268),
.VAR174 (VAR267[VAR302]),
.VAR460 (VAR421[VAR302]),
.VAR376 (VAR482[VAR302]),
.VAR495 (VAR363[VAR302])
);
end
end else begin: VAR46
for (VAR302 = 0; VAR302 < VAR447; VAR302 = VAR302 + 1) begin: VAR14
VAR212 #
(
.VAR248 (VAR248)
)
VAR30
(
.VAR174 (VAR267[VAR302]),
.VAR460 (VAR421[VAR302]),
.VAR376 (VAR482[VAR302]),
.VAR495 (VAR363[VAR302])
);
end
end
if ((VAR344 == "VAR291") || (VAR344 == "VAR70")) begin: VAR368
for (VAR302 = 0; VAR302 < VAR190; VAR302 = VAR302 + 1) begin: VAR312
if ((VAR73 == "VAR41") &&
(VAR292 != "VAR303")) begin: VAR124
VAR87 #
(
.VAR248 (VAR248)
)
VAR432
(
.VAR496 (VAR268),
.VAR459 (VAR268),
.VAR174 (VAR392[VAR302]),
.VAR460 (VAR440[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302])
);
assign VAR360[VAR302] = 1'b0;
assign VAR53[VAR302] = 1'b0;
end else if ((VAR73 == "VAR41") ||
(VAR356 > 2500)) begin : VAR324
VAR400 #
(
.VAR248 (VAR248),
.VAR3 ("VAR270")
)
VAR432
(
.VAR496 (VAR268),
.VAR459 (VAR268),
.VAR174 (VAR392[VAR302]),
.VAR460 (VAR440[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302]),
.VAR170 (VAR360[VAR302])
);
assign VAR53[VAR302] = 1'b0;
end else begin: VAR358
VAR481 #
(
.VAR248 (VAR248),
.VAR3 ("VAR270"),
.VAR431 ("7SERIES"),
.VAR241 ("VAR16")
)
VAR432
(
.VAR496 (VAR268),
.VAR174 (VAR392[VAR302]),
.VAR243 (VAR440[VAR302]),
.VAR327 (VAR440[VAR302]),
.VAR434 (VAR83[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302]),
.VAR170 (VAR360[VAR302])
);
VAR206 #
(
.VAR213 (VAR213),
.VAR256 (VAR256)
)
VAR202
(
.clk (clk),
.VAR149 (VAR149),
.VAR349 (VAR83[VAR302]),
.VAR106 (VAR106),
.VAR463 (VAR53[VAR302])
);
end
end
end else if ((VAR344 == "VAR36") || (VAR344 == "VAR455")) begin: VAR313
for (VAR302 = 0; VAR302 < VAR190; VAR302 = VAR302 + 1) begin: VAR312
if ((VAR73 == "VAR41") &&
(VAR292 != "VAR303")) begin: VAR124
VAR301 #
(
.VAR248 (VAR248)
)
VAR432
(
.VAR162 (VAR268),
.VAR459 (VAR268),
.VAR174 (VAR392[VAR302]),
.VAR460 (VAR440[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302])
);
assign VAR360[VAR302] = 1'b0;
assign VAR53[VAR302] = 1'b0;
end else if ((VAR73 == "VAR41") ||
(VAR356 > 2500)) begin: VAR324
VAR396 #
(
.VAR248 (VAR248),
.VAR3 ("VAR270")
)
VAR432
(
.VAR162 (VAR268),
.VAR459 (VAR268),
.VAR174 (VAR392[VAR302]),
.VAR460 (VAR440[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302]),
.VAR170 (VAR360[VAR302])
);
assign VAR53[VAR302] = 1'b0;
end else begin: VAR358
VAR252 #
(
.VAR248 (VAR248),
.VAR3 ("VAR270"),
.VAR431 ("7SERIES"),
.VAR241 ("VAR16")
)
VAR432
(
.VAR162 (VAR268),
.VAR174 (VAR392[VAR302]),
.VAR243 (VAR440[VAR302]),
.VAR327 (VAR440[VAR302]),
.VAR434 (VAR83[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302]),
.VAR170 (VAR360[VAR302])
);
VAR206 #
(
.VAR213 (VAR213),
.VAR256 (VAR256)
)
VAR202
(
.clk (clk),
.VAR149 (VAR149),
.VAR349 (VAR83[VAR302]),
.VAR106 (VAR106),
.VAR463 (VAR53[VAR302])
);
end
end
end else begin: VAR350
for (VAR302 = 0; VAR302 < VAR190; VAR302 = VAR302 + 1) begin: VAR312
if ((VAR73 == "VAR41") &&
(VAR292 != "VAR303")) begin: VAR124
VAR212 #
(
.VAR248 (VAR248)
)
VAR432
(
.VAR174 (VAR392[VAR302]),
.VAR460 (VAR440[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302])
);
assign VAR360[VAR302] = 1'b0;
assign VAR53[VAR302] = 1'b0;
end else begin: VAR358
VAR50 #
(
.VAR248 (VAR248),
.VAR3 ("VAR270")
)
VAR432
(
.VAR174 (VAR392[VAR302]),
.VAR460 (VAR440[VAR302]),
.VAR376 (VAR186[VAR302]),
.VAR495 (VAR289[VAR302]),
.VAR170 (VAR360[VAR302])
);
assign VAR53[VAR302] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
end
assign VAR142 = (VAR245 == 4) ? VAR6 : VAR286;
assign VAR353 = (VAR245 == 4) ? VAR314 : VAR138;
assign VAR391 = (VAR245 == 4) ? VAR275 : VAR258;
assign VAR484 = (VAR245 == 4) ? VAR476 : VAR221;
generate
begin
VAR479 #
(
.VAR213 (25),
.VAR110 (8),
.VAR377 (32)
)
VAR168
(
.clk (clk),
.rst (rst),
.VAR231 (VAR453[1]),
.VAR208 (VAR23),
.din (VAR330),
.VAR49 (VAR138),
.dout (VAR286)
);
VAR479 #
(
.VAR213 (25),
.VAR110 (8),
.VAR377 (6)
)
VAR364
(
.clk (clk),
.rst (rst),
.VAR231 (VAR453[2]),
.VAR208 (VAR23),
.din (VAR293),
.VAR49 (),
.dout (VAR258)
);
VAR479 #
(
.VAR213 (25),
.VAR110 (8),
.VAR377 (6)
)
VAR278
(
.clk (clk),
.rst (rst),
.VAR231 (VAR453[3]),
.VAR208 (VAR23),
.din (VAR146),
.VAR49 (),
.dout (VAR221)
);
end
endgenerate
assign VAR151 = VAR453[0];
VAR414 #
(
.VAR325 (VAR325),
.VAR321 (VAR321),
.VAR217 (VAR217),
.VAR117 (VAR117),
.VAR181 (VAR181),
.VAR161 (VAR161),
.VAR77 (VAR77),
.VAR112 (VAR112),
.VAR185 (VAR185),
.VAR336 (VAR336),
.VAR136 (VAR136),
.VAR365 (VAR365),
.VAR490 (VAR490),
.VAR472 (VAR472),
.VAR114 (VAR114),
.VAR461 (VAR461),
.VAR84 (VAR78),
.VAR150 (VAR140),
.VAR111 (VAR285),
.VAR473 (VAR253),
.VAR445 (VAR279),
.VAR215 (VAR215),
.VAR40 ("VAR16"),
.VAR357 ("VAR16"),
.VAR311 (VAR245),
.VAR255 (VAR255),
.VAR385 (63),
.VAR458 (18),
.VAR180 ("VAR16"), .VAR224 ("VAR16"),
.VAR370 ((VAR15 == "VAR141") ? "VAR270" : "VAR16"),
.VAR198 ("VAR270"), .VAR54 ("VAR16"),
.VAR259 (VAR259),
.VAR167 (VAR167), .VAR19 (VAR19),
.VAR7 (VAR7),
.VAR4 (VAR4),
.VAR64 (VAR64),
.VAR37 (6),
.VAR452 (6),
.VAR438 (6),
.VAR424 (6),
.VAR20 (VAR20),
.VAR155 (VAR155),
.VAR118 (VAR118),
.VAR237 (VAR237),
.VAR165 (VAR165),
.VAR373 (VAR373),
.VAR226 (VAR226),
.VAR67 (VAR67),
.VAR418 ((VAR469 == 1) ? 1 : 5),
.VAR280 (VAR280),
.VAR379 (VAR280),
.VAR417 (VAR280),
.VAR207 (VAR280),
.VAR352 (VAR471),
.VAR148 (VAR148),
.VAR307 (VAR148),
.VAR257 (VAR148),
.VAR475 (VAR148),
.VAR283 ("VAR16"),
.VAR11 (VAR280),
.VAR288 (VAR280),
.VAR57 (VAR280),
.VAR228 (VAR280),
.VAR160 (VAR148),
.VAR436 (VAR148),
.VAR422 (VAR148),
.VAR171 (VAR148),
.VAR295 ("VAR16"),
.VAR339 (VAR280),
.VAR219 (VAR280),
.VAR127 (VAR280),
.VAR347 (VAR280),
.VAR410 (VAR148),
.VAR193 (VAR148),
.VAR323 (VAR148),
.VAR230 (VAR148),
.VAR63 (VAR356),
.VAR271 (VAR176),
.VAR309 (VAR176),
.VAR439 (VAR176),
.VAR393 (VAR393),
.VAR344 (VAR344),
.VAR359 (VAR359)
)
VAR338
(
.rst (rst),
.VAR294 (1'b1),
.VAR354 (clk),
.VAR250 (VAR250),
.VAR205 (VAR205),
.VAR383 (clk),
.VAR123 (VAR123),
.VAR415 (),
.VAR203 (VAR203),
.VAR27 (),
.VAR386 (VAR386),
.VAR229 (VAR229),
.VAR126 (VAR126),
.VAR45 (VAR45),
.VAR330 (VAR142),
.VAR23 (VAR353),
.VAR426 (VAR9),
.VAR159 (VAR33),
.VAR272 ('b1),
.VAR486 (VAR486),
.VAR465 (VAR465),
.VAR293 (VAR391),
.VAR146 (VAR484),
.VAR62 (),
.VAR398 (),
.VAR485 (VAR485),
.VAR175 (),
.VAR274 (),
.VAR425 (),
.VAR371 (VAR222),
.VAR179 (),
.VAR244 (VAR443),
.VAR66 (VAR66),
.VAR468 (VAR468),
.VAR332 (VAR332),
.VAR105 (),
.VAR133 (VAR133),
.VAR68 (),
.VAR151 (VAR453),
.VAR282 (VAR282),
.VAR427 (VAR427),
.VAR367 (VAR367),
.VAR340 (VAR340),
.VAR343 (VAR343),
.VAR333 (VAR333),
.VAR412 (VAR412),
.VAR69 (),
.VAR139 (),
.VAR29 (VAR29),
.VAR210 (VAR348),
.VAR163 (VAR163),
.VAR196 (VAR196),
.VAR1 (VAR1),
.VAR235 (VAR235),
.VAR121 (VAR121),
.VAR182 (VAR182),
.VAR143 ('b0),
.VAR35 (VAR35),
.VAR227 (VAR227),
.VAR260 (VAR260),
.VAR144 (VAR144),
.VAR56 (VAR56),
.VAR384 (VAR384),
.VAR42 (VAR42),
.VAR13 (VAR13),
.VAR466 (),
.VAR58 (),
.VAR308 (VAR308),
.VAR387 (VAR387),
.VAR315 (VAR315),
.VAR86 (VAR86),
.VAR419 (VAR419),
.VAR296 (VAR403),
.VAR43 (VAR43),
.VAR304 (),
.VAR480 (VAR480),
.VAR99 (VAR99),
.VAR277 (VAR277),
.VAR172 (),
.VAR97 (VAR172),
.VAR220 (VAR220),
.VAR251 (VAR494),
.VAR102 (VAR102)
,.VAR12 (VAR12)
,.VAR287 (VAR156)
,.VAR474 (VAR341)
,.VAR234 (VAR31)
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.behavioral.pp.v
| 2,370 |
module MODULE1 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR14 ,
VAR10 ,
VAR4,
VAR9,
VAR20 ,
VAR23
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR14 ;
input VAR10 ;
input VAR4;
input VAR9;
input VAR20 ;
input VAR23 ;
wire VAR1 ;
wire VAR25 ;
reg VAR15 ;
wire VAR22 ;
wire VAR11;
wire VAR18;
wire VAR16;
wire VAR17 ;
wire VAR13 ;
wire VAR7 ;
wire VAR24 ;
VAR12 VAR6 (VAR25, VAR22, VAR11, VAR18 );
VAR21 VAR3 (VAR1 , VAR25, VAR16, VAR15, VAR4, VAR9);
assign VAR17 = ( VAR4 === 1'b1 );
assign VAR13 = ( ( VAR18 === 1'b0 ) && VAR17 );
assign VAR7 = ( ( VAR18 === 1'b1 ) && VAR17 );
assign VAR24 = ( ( VAR22 !== VAR11 ) && VAR17 );
buf VAR19 (VAR8 , VAR1 );
endmodule
|
apache-2.0
|
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