repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o41ai/sky130_fd_sc_hd__o41ai_2.v
| 2,424 |
module MODULE1 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR12 ,
VAR9 ,
VAR4 ,
VAR7,
VAR5,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR12 ;
input VAR9 ;
input VAR4 ;
input VAR7;
input VAR5;
input VAR8 ;
input VAR1 ;
VAR11 VAR10 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR6,
VAR2,
VAR12,
VAR9,
VAR4
);
output VAR3 ;
input VAR6;
input VAR2;
input VAR12;
input VAR9;
input VAR4;
supply1 VAR7;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR1 ;
VAR11 VAR10 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
FPGA1988/udp_ip_stack
|
Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/afifo.v
| 6,425 |
module MODULE1(
din,
VAR3,
VAR11,
VAR37,
VAR27,
VAR14,
dout,
VAR32,
VAR1,
VAR23,
VAR15,
VAR17,
VAR28,
VAR22);
parameter VAR30 =16;
parameter VAR4 =8;
parameter VAR29 =8;
parameter VAR16 =8;
input [VAR30-1:0] din;
input VAR3;
input VAR11;
input VAR37;
input VAR27;
input VAR14;
output [VAR30-1:0] dout;
output VAR32;
output VAR1;
output VAR23;
output [VAR29-1:0] VAR15 ;
output [VAR29-1:0] VAR17 ;
output VAR28;
output VAR22;
reg [VAR4-1:0] VAR19;
reg [VAR4-1:0] VAR2;
reg [VAR4-1:0] VAR20;
reg [VAR4-1:0] VAR34;
reg [VAR4-1:0] VAR10;
wire [VAR4-1:0] VAR39;
reg [VAR4-1:0] VAR13;
reg [VAR4-1:0] VAR12;
reg [VAR4-1:0] VAR26;
wire [VAR4-1:0] VAR35;
integer VAR5;
reg VAR32 ;
reg VAR23;
wire [VAR4-1:0] VAR6;
wire [VAR4-1:0] VAR24;
reg VAR28;
reg VAR8;
reg VAR1;
wire [VAR30-1:0] VAR40;
assign VAR22 =0;
assign VAR6 =VAR19-VAR26;
assign VAR15 =VAR6[VAR4-1:VAR4-VAR29];
always @ (posedge VAR14 or posedge VAR11)
if (VAR14)
VAR20 <=0;
else
begin
VAR20[VAR4-1] <=VAR19[VAR4-1];
for (VAR5=VAR4-2;VAR5>=0;VAR5=VAR5-1)
VAR20[VAR5] <=VAR19[VAR5+1]^VAR19[VAR5];
end
always @ (posedge VAR11 or posedge VAR14)
if (VAR14)
VAR12 <=0;
else
VAR12 <=VAR13;
always @ (posedge VAR11 or posedge VAR14)
if (VAR14)
VAR26 =0;
else
begin
VAR26[VAR4-1] =VAR12[VAR4-1];
for (VAR5=VAR4-2;VAR5>=0;VAR5=VAR5-1)
VAR26[VAR5] =VAR26[VAR5+1]^VAR12[VAR5];
end
assign VAR35=VAR19+1;
always @ (posedge VAR11 or posedge VAR14)
if (VAR14)
VAR32 <=0;
else if(VAR35==VAR26&&VAR3)
VAR32 <=1;
else if(VAR19!=VAR26)
VAR32 <=0;
always @ (posedge VAR11 or posedge VAR14)
if (VAR14)
VAR1 <=0;
else if (VAR15>=VAR16)
VAR1 <=1;
else
VAR1 <=0;
always @ (posedge VAR11 or posedge VAR14)
if (VAR14)
VAR19 <=0;
else if (VAR3&&!VAR32)
VAR19 <=VAR19 +1;
always @ (posedge VAR27 or posedge VAR14)
if (VAR14)
VAR28 <=0;
else if (VAR37&&!VAR23)
VAR28 <=1;
else
VAR28 <=0;
assign VAR24 =VAR2-VAR10;
assign VAR17 =VAR24[VAR4-1:VAR4-VAR29];
assign VAR39 =VAR10+1;
always @ (posedge VAR27 or posedge VAR14)
if (VAR14)
VAR10 <=0;
else if (VAR37&&!VAR23) VAR10 <=VAR10 + 1;
always @ (posedge VAR14 or posedge VAR27)
if (VAR14)
VAR13 <=0;
else
begin
VAR13[VAR4-1] <=VAR10[VAR4-1];
for (VAR5=VAR4-2;VAR5>=0;VAR5=VAR5-1)
VAR13[VAR5] <=VAR10[VAR5+1]^VAR10[VAR5];
end
always @ (posedge VAR27 or posedge VAR14)
if (VAR14)
VAR34 <=0;
else
VAR34 <=VAR20;
always @ (posedge VAR27 or posedge VAR14)
if (VAR14)
VAR2 =0;
else
begin
VAR2[VAR4-1] =VAR34[VAR4-1];
for (VAR5=VAR4-2;VAR5>=0;VAR5=VAR5-1)
VAR2[VAR5] =VAR2[VAR5+1]^VAR34[VAR5];
end
always @ (posedge VAR27 or posedge VAR14)
if (VAR14)
VAR23 <=1;
else if (VAR39==VAR2&&VAR37)
VAR23 <=1;
else if (VAR10!=VAR2)
VAR23 <=0;
VAR7 #(
VAR30,
VAR4
)
VAR31 (
.VAR18 (din ),
.VAR25 (VAR3 ),
.VAR33 (VAR19 ),
.VAR21 (VAR10 ),
.VAR38 (VAR11 ),
.VAR9 (VAR27 ),
.VAR36 (dout ));
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.functional.pp.v
| 3,028 |
module MODULE1( VAR25, VAR37, VAR36, VAR8, VAR6, VAR9, VAR10, VAR1, VAR5 );
input VAR10, VAR9, VAR8, VAR6, VAR36, VAR37;
inout VAR1, VAR5;
output VAR25;
wire VAR27;
not VAR13( VAR27, VAR10 );
wire VAR2;
not VAR14( VAR2, VAR8 );
wire VAR3;
not VAR15( VAR3, VAR36 );
wire VAR29;
and VAR12( VAR29, VAR27, VAR2, VAR3 );
wire VAR28;
not VAR34( VAR28, VAR37 );
wire VAR33;
and VAR32( VAR33, VAR27, VAR2, VAR28 );
wire VAR21;
not VAR7( VAR21, VAR6 );
wire VAR23;
and VAR17( VAR23, VAR27, VAR21, VAR3 );
wire VAR35;
and VAR11( VAR35, VAR27, VAR21, VAR28 );
wire VAR31;
not VAR18( VAR31, VAR9 );
wire VAR38;
and VAR16( VAR38, VAR31, VAR2, VAR3 );
wire VAR4;
and VAR20( VAR4, VAR31, VAR2, VAR28 );
wire VAR30;
and VAR22( VAR30, VAR31, VAR21, VAR3 );
wire VAR24;
and VAR19( VAR24, VAR31, VAR21, VAR28 );
or VAR26( VAR25, VAR29, VAR33, VAR23, VAR35, VAR38, VAR4, VAR30, VAR24 );
endmodule
|
apache-2.0
|
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping
|
bin2bcd16.v
| 3,173 |
module MODULE1 (
input [15:0] VAR1, output reg [19:0] VAR2 );
reg [35:0] VAR4;
integer VAR3;
always @(VAR1) begin
for(VAR3 = 0; VAR3 <= 35; VAR3 = VAR3+1) VAR4[VAR3] = 0;
VAR4[18:3] = VAR1;
for(VAR3 = 0; VAR3 <= 12; VAR3 = VAR3+1) begin
if(VAR4[19:16] > 4) VAR4[19:16] = VAR4[19:16] + 3;
if(VAR4[23:20] > 4) VAR4[23:20] = VAR4[23:20] + 3;
if(VAR4[27:24] > 4) VAR4[27:24] = VAR4[27:24] + 3;
if(VAR4[31:28] > 4) VAR4[31:28] = VAR4[31:28] + 3;
VAR4[35:1] = VAR4[34:0];
end
VAR2 = VAR4[35:16];
end
endmodule
|
bsd-3-clause
|
keith-epidev/VHDL-lib
|
top/mono_radio/ip/multi_QI/multi_QI_stub.v
| 1,200 |
module MODULE1(VAR2, VAR3, VAR4, VAR1)
;
input VAR2;
input [15:0]VAR3;
input [15:0]VAR4;
output [31:0]VAR1;
endmodule
|
gpl-2.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/fifo_packer_128.v
| 5,107 |
module MODULE1 (
input VAR18,
input VAR1,
input [127:0] VAR8, input [2:0] VAR15, input VAR16, input VAR5, input VAR20, output [127:0] VAR7, output VAR11, output VAR22, output VAR12, output VAR19 );
reg [2:0] VAR23=0, VAR23=0;
reg VAR24=0, VAR24=0;
reg VAR14=0, VAR14=0;
reg VAR6=0, VAR6=0;
reg VAR3=0, VAR3=0;
reg [223:0] VAR21=224'd0, VAR21=224'd0;
reg [127:0] VAR2=128'd0, VAR2=128'd0;
reg [2:0] VAR9=0, VAR9=0;
reg [127:0] VAR4=128'd0, VAR4=128'd0;
reg [2:0] VAR10=0, VAR10=0;
assign VAR7 = VAR21[127:0];
assign VAR11 = VAR23[2];
assign VAR22 = VAR24;
assign VAR12 = VAR14;
assign VAR19 = VAR3;
wire [127:0] VAR13 = {128{1'b1}}<<(32*VAR9);
wire [127:0] VAR17 = ~VAR13 & VAR2;
always @ (posedge VAR18) begin
VAR23 <= (VAR1 ? 3'd0 : VAR23);
VAR24 <= (VAR1 ? 1'd0 : VAR24);
VAR14 <= (VAR1 ? 1'd0 : VAR14);
VAR6 <= (VAR1 ? 1'd0 : VAR6);
VAR3 <= (VAR1 ? 1'd0 : VAR3);
VAR21 <= (VAR1 ? 224'd0 : VAR21);
VAR2 <= VAR2;
VAR9 <= (VAR1 ? 3'd0 : VAR9);
VAR4 <= VAR4;
VAR10 <= (VAR1 ? 3'd0 : VAR10);
end
always @ (*) begin
VAR2 = VAR8;
VAR9 = VAR15;
VAR4 = VAR17;
VAR10 = VAR9;
if (VAR6 && (VAR23[1] | VAR23[0]))
VAR23 = 4;
end
else
VAR23 = VAR23 + VAR10 - {VAR23[2], 2'd0};
if (VAR10 != 3'd0)
VAR21 = ((VAR21>>(32*{VAR23[2], 2'd0})) | (VAR4<<(32*VAR23[1:0])));
else
VAR21 = (VAR21>>(32*{VAR23[2], 2'd0}));
VAR24 = VAR16;
VAR14 = VAR5;
VAR6 = VAR20;
VAR3 = VAR6;
end
endmodule
|
gpl-3.0
|
asicguy/gplgpu
|
hdl/ramdac_sp/ram_ctl.v
| 3,653 |
module MODULE1
(
input VAR10,
input VAR14,
input VAR4,
input VAR16,
input [7:0] VAR8,
input [7:0] VAR2,
input [7:0] VAR3,
input [7:0] VAR17,
input [7:0] VAR9,
input [7:0] VAR13,
output reg [7:0] VAR7, output reg [7:0] VAR15, output reg [7:0] VAR1, output reg [7:0] VAR5,
output reg [7:0] VAR11,
output reg [7:0] VAR12
);
wire VAR6 = ! (VAR4 | VAR16);
always @( posedge VAR10 or negedge VAR14)
if (!VAR14) begin
VAR5 <= 8'b0;
VAR11 <= 8'b0;
VAR12 <= 8'b0;
end else begin
VAR5 <= VAR8;
VAR11 <= VAR2;
VAR12 <= VAR3;
end
always @( posedge VAR10 or negedge VAR14)
if (!VAR14) begin
VAR7 <= 8'b0;
VAR15 <= 8'b0;
VAR1 <= 8'b0;
end else begin
VAR7 <= VAR6 ? {VAR17[7:2] ,VAR17[7:6]} :
VAR17 ;
VAR15 <= VAR6 ? {VAR9[7:2] ,VAR9[7:6]} :
VAR9 ;
VAR1 <= VAR6 ? {VAR13[7:2] ,VAR13[7:6]} :
VAR13 ;
end
endmodule
|
gpl-3.0
|
ankitshah009/High-Radix-Adaptive-CORDIC
|
HCORDIC_Verilog/PackSum_y.v
| 1,928 |
module MODULE1(
input [1:0] VAR6,
input [31:0] VAR1,
input [1:0] VAR12,
input VAR3,
input [27:0] VAR11,
input [7:0] VAR5,
input VAR9,
output reg [31:0] VAR8,
output reg VAR17 = 1'b0
);
parameter VAR4 =2'b01,
VAR7 =2'b00,
VAR10=2'b11;
parameter VAR14 = 2'b00,
VAR16 = 2'b01,
VAR2 = 2'b10;
wire VAR15;
wire [7:0] VAR13;
assign VAR15 = VAR1[31];
assign VAR13 = VAR1[30:23];
always @ (posedge VAR9)
begin
if (VAR12 == VAR4) begin
VAR17 <= 1'b1;
end
if (VAR6 != VAR2) begin
VAR8[22:0] <= VAR11[25:3];
VAR8[30:23] <= VAR13 + 127;
VAR8[31] <= VAR15;
if ((VAR13) == -126 && VAR11[22] == 0) begin
VAR8[30 : 23] <= 0;
end
if ((VAR13) <= -126) begin
VAR8[30 : 23] <= 0;
VAR8[22:0] <= 0;
end
if ((VAR13) > 127) begin
VAR8[22 : 0] <= 0;
VAR8[30 : 23] <= 255;
VAR8[31] <= VAR15;
end
end
else begin
VAR8 <= VAR1;
end
end
endmodule
|
apache-2.0
|
bluespec/Flute
|
src_SSITH_P2/Verilog_RTL/mkCSR_MIE.v
| 5,900 |
module MODULE1(VAR6,
VAR2,
VAR13,
VAR9,
VAR36,
VAR17,
VAR7,
VAR8,
VAR3,
VAR16,
VAR12,
VAR27,
VAR32);
input VAR6;
input VAR2;
input VAR13;
output [63 : 0] VAR9;
input [27 : 0] VAR36;
input [63 : 0] VAR17;
input VAR7;
output [63 : 0] VAR8;
output [63 : 0] VAR3;
input [27 : 0] VAR16;
input [63 : 0] VAR12;
input VAR27;
output [63 : 0] VAR32;
wire [63 : 0] VAR32, VAR8, VAR9, VAR3;
reg [11 : 0] VAR21;
reg [11 : 0] VAR24;
wire VAR25;
wire VAR5,
VAR37,
VAR35,
VAR19,
VAR29,
VAR40;
wire [11 : 0] VAR4;
wire [11 : 0] VAR10, VAR18, VAR15;
wire VAR26,
VAR38,
VAR34,
VAR11,
VAR28,
VAR20,
VAR1,
VAR30,
VAR22,
VAR23,
VAR39,
VAR33;
assign VAR35 = 1'd1 ;
assign VAR40 = VAR13 ;
assign VAR9 = { 52'd0, VAR21 } ;
assign VAR8 = { 52'd0, VAR10 } ;
assign VAR37 = 1'd1 ;
assign VAR29 = VAR7 ;
assign VAR3 = { 52'd0, VAR18 } ;
assign VAR32 = { 52'd0, VAR15 } ;
assign VAR5 = 1'd1 ;
assign VAR19 = VAR27 ;
assign VAR4 =
{ VAR21[11],
1'b0,
VAR38,
VAR30,
VAR21[7],
1'b0,
VAR20,
VAR33,
VAR21[3],
1'b0,
VAR11,
VAR23 } ;
always@(VAR7 or
VAR10 or
VAR13 or VAR27 or VAR4)
case (1'b1)
VAR7: VAR24 = VAR10;
VAR13: VAR24 = 12'd0;
VAR27: VAR24 = VAR4;
default: VAR24 = 12'b101010101010 ;
endcase
assign VAR25 = VAR7 || VAR27 || VAR13 ;
assign VAR10 =
{ VAR17[11],
1'b0,
VAR26,
VAR1,
VAR17[7],
1'b0,
VAR28,
VAR39,
VAR17[3],
1'b0,
VAR34,
VAR22 } ;
assign VAR26 = VAR36[18] && VAR17[9] ;
assign VAR38 = VAR16[18] && VAR12[9] ;
assign VAR34 = VAR36[18] && VAR17[1] ;
assign VAR11 = VAR16[18] && VAR12[1] ;
assign VAR28 = VAR36[18] && VAR17[5] ;
assign VAR20 = VAR16[18] && VAR12[5] ;
assign VAR1 = VAR36[13] && VAR17[8] ;
assign VAR30 = VAR16[13] && VAR12[8] ;
assign VAR22 = VAR36[13] && VAR17[0] ;
assign VAR23 = VAR16[13] && VAR12[0] ;
assign VAR39 = VAR36[13] && VAR17[4] ;
assign VAR33 = VAR16[13] && VAR12[4] ;
assign VAR18 =
{ 2'd0, VAR21[9:8], 2'd0, VAR21[5:4], 2'd0, VAR21[1:0] } ;
assign VAR15 =
{ 2'd0,
VAR38,
VAR30,
2'd0,
VAR20,
VAR33,
2'd0,
VAR11,
VAR23 } ;
always@(posedge VAR6)
begin
if (VAR2 == VAR14)
begin
VAR21 <= VAR31 12'd0;
end
else
begin
if (VAR25) VAR21 <= VAR31 VAR24;
end
end
begin
VAR21 = 12'hAAA;
end
|
apache-2.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_6sig_x2.v
| 8,691 |
module MODULE1(VAR58 ,VAR6 ,VAR47 ,
VAR91 ,VAR2 ,VAR15 ,VAR123 ,VAR31 ,
VAR101 ,VAR32 ,VAR23 ,VAR92 ,VAR122 ,
VAR53 ,VAR67 ,VAR13 ,VAR20 ,VAR115 ,
VAR106 ,VAR55 ,VAR73 ,VAR69 ,VAR64 ,
VAR119 ,VAR29 ,VAR4 ,VAR63 ,
VAR83 ,VAR22 ,
VAR46 ,VAR104 ,VAR54 , VAR18,
VAR85 ,VAR51 ,VAR25 ,
VAR97 ,VAR9 ,VAR82 ,VAR11 ,VAR117 ,
VAR26 ,VAR35 ,VAR96 ,VAR78 ,VAR111 ,
VAR79 ,VAR14 ,VAR114 ,
VAR41 ,VAR105 ,VAR3 ,
VAR71 , VAR109, VAR118 ,VAR70 ,
VAR93 ,VAR24 ,VAR60 ,
VAR66 ,VAR42 ,VAR120 ,VAR72 ,VAR30 ,
VAR16 ,VAR52 ,VAR38 ,VAR43 ,VAR19 ,VAR121
);
output [7:0] VAR15 ;
output [7:0] VAR32 ;
output [7:0] VAR53 ;
output [7:0] VAR67 ;
input [7:0] VAR123 ;
input [7:0] VAR31 ;
input [7:0] VAR23 ;
input [7:0] VAR92 ;
input [7:0] VAR13 ;
input [7:0] VAR20 ;
input [4:0] VAR63 ;
input [1:0] VAR22 ;
input [1:0] VAR85 ;
input [1:0] VAR51 ;
input [8:1] VAR9 ;
input [8:1] VAR82 ;
input [4:0] VAR79 ;
input [1:0] VAR114 ;
input [1:0] VAR118 ;
input [1:0] VAR70 ;
input [8:1] VAR60 ;
input [8:1] VAR66 ;
inout [7:0] VAR122 ;
inout [1:0] VAR115 ;
output VAR101 ;
output VAR73 ;
input VAR58 ;
input VAR6 ;
input VAR47 ;
input VAR91 ;
input VAR2 ;
input VAR106 ;
input VAR69 ;
input VAR64 ;
input VAR119 ;
input VAR29 ;
input VAR4 ;
input VAR83 ;
input VAR46 ;
input VAR104 ;
input VAR54 ;
input VAR18 ;
input VAR25 ;
input VAR97 ;
input VAR11 ;
input VAR117 ;
input VAR26 ;
input VAR35 ;
input VAR96 ;
input VAR78 ;
input VAR111 ;
input VAR14 ;
input VAR41 ;
input VAR105 ;
input VAR3 ;
input VAR71 ;
input VAR109 ;
input VAR93 ;
input VAR24 ;
input VAR42 ;
input VAR120 ;
input VAR72 ;
input VAR30 ;
input VAR16 ;
input VAR52 ;
input VAR38 ;
input VAR43 ;
input VAR19 ;
inout VAR55 ;
inout VAR121 ;
wire VAR59 ;
wire VAR7 ;
wire VAR89 ;
wire VAR116 ;
wire VAR48 ;
wire VAR33 ;
wire VAR34 ;
wire VAR90 ;
wire VAR12 ;
wire VAR113 ;
wire VAR49 ;
wire VAR74 ;
VAR1 VAR28 (
.VAR15 ({VAR15[3:0] } ),
.VAR123 ({VAR123[3:0] } ),
.VAR124 ({VAR23 } ),
.VAR67 ({VAR67[3:0] } ),
.VAR31 ({VAR31[3:0] } ),
.VAR32 ({VAR32[3:0] } ),
.VAR8 ({VAR114 } ),
.VAR122 ({VAR122[3:0] } ),
.VAR53 ({VAR53[3:0] } ),
.VAR20 ({VAR20[3:0] } ),
.VAR13 ({VAR13[3:0] } ),
.VAR65 ({VAR70 } ),
.VAR10 ({VAR118 } ),
.VAR84 ({VAR60 } ),
.VAR94 ({VAR66 } ),
.VAR75 (VAR6 ),
.VAR125 (VAR47 ),
.VAR45 (VAR59 ),
.VAR102 (VAR120 ),
.VAR64 (VAR64 ),
.VAR38 (VAR38 ),
.VAR101 (VAR89 ),
.VAR81 (VAR119 ),
.VAR100 (VAR58 ),
.VAR36 (VAR121 ),
.VAR115 (VAR115[0] ),
.VAR98 (VAR90 ),
.VAR29 (VAR29 ),
.VAR37 (VAR42 ),
.VAR73 (VAR48 ),
.VAR19 (VAR19 ),
.VAR39 (VAR16 ),
.VAR107 (VAR30 ),
.VAR87 (VAR72 ),
.VAR68 (VAR69 ),
.VAR77 (VAR24 ),
.VAR108 (VAR93 ),
.VAR50 (VAR52 ),
.VAR5 (VAR71 ),
.VAR126 (VAR109 ),
.VAR86 (VAR41 ),
.VAR110 (VAR105 ),
.VAR17 (VAR49 ),
.VAR76 (VAR14 ) );
VAR1 VAR80 (
.VAR15 ({VAR15[7:4] } ),
.VAR123 ({VAR123[7:4] } ),
.VAR124 ({VAR92 } ),
.VAR67 ({VAR67[7:4] } ),
.VAR31 ({VAR31[7:4] } ),
.VAR32 ({VAR32[7:4] } ),
.VAR8 ({VAR22 } ),
.VAR122 ({VAR122[7:4] } ),
.VAR53 ({VAR53[7:4] } ),
.VAR20 ({VAR20[7:4] } ),
.VAR13 ({VAR13[7:4] } ),
.VAR65 ({VAR51 } ),
.VAR10 ({VAR85 } ),
.VAR84 ({VAR9 } ),
.VAR94 ({VAR82 } ),
.VAR75 (VAR91 ),
.VAR125 (VAR2 ),
.VAR45 (VAR7 ),
.VAR102 (VAR117 ),
.VAR64 (VAR113 ),
.VAR38 (VAR38 ),
.VAR101 (VAR116 ),
.VAR81 (VAR43 ),
.VAR100 (VAR106 ),
.VAR36 (VAR55 ),
.VAR115 (VAR115[1] ),
.VAR98 (VAR12 ),
.VAR29 (VAR29 ),
.VAR37 (VAR11 ),
.VAR73 (VAR73 ),
.VAR19 (VAR48 ),
.VAR39 (VAR96 ),
.VAR107 (VAR35 ),
.VAR87 (VAR26 ),
.VAR68 (VAR3 ),
.VAR77 (VAR97 ),
.VAR108 (VAR25 ),
.VAR50 (VAR78 ),
.VAR5 (VAR54 ),
.VAR126 (VAR18 ),
.VAR86 (VAR46 ),
.VAR110 (VAR104 ),
.VAR17 (VAR74 ),
.VAR76 (VAR83 ) );
VAR95 VAR27 (
.VAR57 ({VAR79 } ),
.VAR40 (VAR90 ),
.VAR21 (VAR89 ),
.VAR37 (VAR42 ),
.VAR62 (VAR33 ),
.VAR44 (VAR113 ),
.VAR88 (VAR49 ) );
VAR95 VAR56 (
.VAR57 ({VAR63 } ),
.VAR40 (VAR12 ),
.VAR21 (VAR116 ),
.VAR37 (VAR11 ),
.VAR62 (VAR34 ),
.VAR44 (VAR101 ),
.VAR88 (VAR74 ) );
VAR61 VAR99 (
.VAR103 (VAR33 ),
.clk (VAR59 ),
.VAR75 (VAR6 ),
.VAR62 (VAR111 ) );
VAR61 VAR112 (
.VAR103 (VAR34 ),
.clk (VAR7 ),
.VAR75 (VAR91 ),
.VAR62 (VAR4 ) );
endmodule
|
gpl-2.0
|
trivoldus28/pulsarch-verilog
|
design/sys/edk/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_sym_dec.v
| 17,758 |
module MODULE1
(
VAR9,
VAR34,
VAR56,
VAR64,
VAR10,
VAR21,
VAR36,
VAR26,
VAR40,
VAR62,
VAR57,
VAR29,
VAR1,
VAR3,
VAR47,
VAR14
);
parameter VAR30 = 4'hb;
parameter VAR51 = 4'hc;
parameter VAR16 = 4'h4;
parameter VAR19 = 4'ha;
parameter VAR55 = 4'h2;
parameter VAR18 = 4'hc;
parameter VAR2 = 4'hb;
parameter VAR49 = 4'h5;
parameter VAR8 = 4'hd;
parameter VAR15 = 4'h3;
parameter VAR44 = 4'h9;
parameter VAR4 = 4'hc;
parameter VAR63 = 4'h5;
parameter VAR38 = 4'hc;
parameter VAR32 = 4'hf;
parameter VAR22 = 4'hb;
parameter VAR37 = 4'hf;
parameter VAR52 = 4'hd;
parameter VAR42 = 4'hf;
parameter VAR33 = 4'he;
parameter VAR60 = 4'h7;
parameter VAR13 = 4'hc;
parameter VAR41 = 4'he;
parameter VAR24 = 4'h8;
output VAR9; output [0:15] VAR34; output VAR56; output VAR64; output VAR10;
input VAR21;
output VAR36; output VAR26; output VAR40;
output [0:1] VAR62; output VAR57;
input [15:0] VAR29; input [1:0] VAR1; input [1:0] VAR3;
input VAR47; input VAR14;
reg [0:15] VAR34;
reg VAR9;
reg VAR56;
reg VAR64;
reg VAR10;
reg VAR36;
reg VAR26;
reg VAR40;
reg [0:1] VAR62;
reg VAR57;
reg VAR31;
reg [0:7] VAR17;
reg VAR45;
reg VAR43;
reg VAR20;
reg [0:15] VAR7;
reg [0:1] VAR23;
reg [0:15] VAR48;
reg [0:1] VAR39;
reg [0:1] VAR35;
reg [0:3] VAR58;
reg [0:3] VAR6;
reg [0:3] VAR61;
reg [0:3] VAR25;
reg [0:3] VAR12;
reg [0:3] VAR65;
reg [0:1] VAR59;
reg [0:1] VAR46;
reg [0:3] VAR28;
reg VAR54;
reg [0:3] VAR53;
reg [0:3] VAR11;
reg VAR5;
wire VAR27;
always @(posedge VAR47)
if(VAR21 & !VAR5)
case({VAR3,VAR1})
4'b1010 : VAR31 <= VAR50 1'b1;
4'b0101 : VAR31 <= VAR50 1'b0;
default : VAR31 <= VAR50 VAR31;
endcase
always @(posedge VAR47)
VAR17 <= VAR50 VAR29[7:0];
always @(posedge VAR47)
VAR45 <= VAR50 VAR1[0];
always @(posedge VAR47)
VAR7[0:7] <= VAR50 VAR31? VAR29[15:8]
: VAR17;
always @(posedge VAR47)
VAR7[8:15] <= VAR50 VAR31? VAR29[7:0] : VAR29[15:8];
always @(posedge VAR47)
VAR23[0] <= VAR50 VAR31? VAR1[1]
: VAR45;
always @(posedge VAR47)
VAR23[1] <= VAR50 VAR31? VAR1[0]
: VAR1[1];
always @(posedge VAR47)
VAR48 <= VAR50 VAR7;
always @(posedge VAR47)
VAR34 <= VAR50 VAR48;
always @(posedge VAR47)
VAR39 <= VAR50 VAR23;
always @(posedge VAR47)
begin
VAR35[0] <= VAR50 (VAR7[8:11] == VAR44);
VAR35[1] <= VAR50 (VAR7[12:15] == VAR4);
end
always @(posedge VAR47)
VAR9 <= VAR50 (VAR35== 2'b11) & (VAR39 == 2'b01);
always @(posedge VAR47)
VAR56 <= VAR50 !VAR39[0];
always @(posedge VAR47)
begin
VAR58[0] <= VAR50 (VAR7[0:3] == VAR63);
VAR58[1] <= VAR50 (VAR7[4:7] == VAR38);
VAR58[2] <= VAR50 (VAR7[8:11] == VAR32);
VAR58[3] <= VAR50 (VAR7[12:15] == VAR22);
end
always @(posedge VAR47)
VAR64 <= VAR50 &{VAR39, VAR58};
always @(posedge VAR47)
begin
VAR6[0] <= VAR50 (VAR7[0:3] == VAR37);
VAR6[1] <= VAR50 (VAR7[4:7] == VAR52);
VAR6[2] <= VAR50 (VAR7[8:11] == VAR42);
VAR6[3] <= VAR50 (VAR7[12:15] == VAR33);
end
always @(posedge VAR47)
VAR10 <= VAR50 &{VAR39, VAR6};
always @(posedge VAR47)
begin
VAR61[0] <= VAR50 (VAR7[0:3] == VAR30);
VAR61[1] <= VAR50 (VAR7[4:7] == VAR51);
VAR61[2] <= VAR50 (VAR7[8:11] == VAR16)|
(VAR7[8:11] == VAR2);
VAR61[3] <= VAR50 (VAR7[12:15] == VAR19)|
(VAR7[12:15] == VAR49);
end
always @(posedge VAR47)
VAR43 <= VAR50 (VAR39 == 2'b10) &
(VAR61 == 4'b1111);
always @(posedge VAR47)
begin
VAR25[0] <= VAR50 (VAR7[0:3] == VAR30);
VAR25[1] <= VAR50 (VAR7[4:7] == VAR51);
VAR25[2] <= VAR50 (VAR7[8:11] == VAR55);
VAR25[3] <= VAR50 (VAR7[12:15] == VAR18);
end
always @(posedge VAR47)
VAR20 <= VAR50 (VAR39 == 2'b10) &
(VAR25 == 4'b1111);
always @(posedge VAR47)
begin
VAR12[0] <= VAR50 (VAR7[0:3] == VAR16)|
(VAR7[0:3] == VAR2);
VAR12[1] <= VAR50 (VAR7[4:7] == VAR19)|
(VAR7[4:7] == VAR49);
VAR12[2] <= VAR50 (VAR7[8:11] == VAR16)|
(VAR7[8:11] == VAR2);
VAR12[3] <= VAR50 (VAR7[12:15] == VAR19)|
(VAR7[12:15] == VAR49);
end
always @(posedge VAR47)
VAR36 <= VAR50 VAR43 &
(VAR39 == 2'b00) &
(VAR12 == 4'b1111);
always @(posedge VAR47)
begin
VAR65[0] <= VAR50 (VAR7[0:3] == VAR55);
VAR65[1] <= VAR50 (VAR7[4:7] == VAR18);
VAR65[2] <= VAR50 (VAR7[8:11] == VAR55);
VAR65[3] <= VAR50 (VAR7[12:15] == VAR18);
end
always @(posedge VAR47)
VAR26 <= VAR50 VAR20 &
(VAR39 == 2'b00) &
(VAR65 == 4'b1111);
always @(posedge VAR47)
begin
VAR59[0] <= VAR50 (VAR7[8:11] == VAR2);
VAR59[1] <= VAR50 (VAR7[12:15] == VAR49);
VAR46[0] <= VAR50 (VAR7[8:11] == VAR8);
VAR46[1] <= VAR50 (VAR7[12:15] == VAR15);
end
always @(posedge VAR47)
VAR40 <= VAR50 !VAR39[1] &
((VAR59 == 2'b11)|
(VAR46 == 2'b11));
always @(posedge VAR47)
begin
VAR11[0] <= VAR50 (VAR7[0:3] == VAR60);
VAR11[1] <= VAR50 (VAR7[4:7] == VAR13);
VAR11[2] <= VAR50 (VAR7[8:11] == VAR60);
VAR11[3] <= VAR50 (VAR7[12:15] == VAR13);
end
always @(posedge VAR47)
begin
VAR62[0] <= VAR50 VAR39[0] & (VAR11[0:1] == 2'b11);
VAR62[1] <= VAR50 VAR39[1] & (VAR11[2:3] == 2'b11);
end
always @(posedge VAR47)
begin
VAR28[0] <= VAR50 (VAR7[0:3] == VAR30);
VAR28[1] <= VAR50 (VAR7[4:7] == VAR51);
VAR28[2] <= VAR50 (VAR7[8:11] == VAR41);
VAR28[3] <= VAR50 (VAR7[12:15] == VAR24);
end
always @(posedge VAR47)
VAR54 <= VAR50 (VAR39 == 2'b10) &
(VAR28 == 4'b1111);
always @(posedge VAR47)
begin
VAR53[0] <= VAR50 (VAR7[0:3] == VAR41);
VAR53[1] <= VAR50 (VAR7[4:7] == VAR24);
VAR53[2] <= VAR50 (VAR7[8:11] == VAR41);
VAR53[3] <= VAR50 (VAR7[12:15] == VAR24);
end
assign VAR27 = VAR54 & (VAR39 == 2'b00) &
(VAR53 == 4'b1111);
always @(posedge VAR47)
VAR57 <= VAR50 VAR27;
|
gpl-2.0
|
TalentlessAlpaca/Automated_Vacuum_Cleaner
|
j1_soc/hdl/T_Rot/TOP_Rotation_tst.v
| 2,552 |
module MODULE1;
reg clk;
reg rst;
reg [15:0] VAR15;
reg [15:0] VAR2;
reg [15:0] VAR8;
reg [31:0] VAR1;
reg enable;
reg [7:0] VAR16;
reg VAR10;
reg VAR13;
reg [31:0] VAR6;
wire VAR7;
wire [31:0] VAR12;
wire [31:0] VAR11;
wire [31:0] VAR3;
reg [15:0] VAR9;
reg [15:0] VAR4;
reg[8:0] VAR17;
VAR5 VAR14 (
.clk(clk),
.rst(rst),
.VAR15(VAR15),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.enable(enable),
.VAR16(VAR16),
.VAR10(VAR10),
.VAR13(VAR13),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR3(VAR3)
);
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nor3/sky130_fd_sc_lp__nor3_4.v
| 2,198 |
module MODULE2 (
VAR4 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR1,
VAR7,
VAR3 ,
VAR10
);
output VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR1;
input VAR7;
input VAR3 ;
input VAR10 ;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR4,
VAR9,
VAR5,
VAR6
);
output VAR4;
input VAR9;
input VAR5;
input VAR6;
supply1 VAR1;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR10 ;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/fahcon/sky130_fd_sc_hs__fahcon.pp.symbol.v
| 1,324 |
module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR6 ,
output VAR7,
output VAR5 ,
input VAR2 ,
input VAR4
);
endmodule
|
apache-2.0
|
rkrajnc/minimig-de1
|
rtl/minimig/Copper.v
| 16,884 |
module MODULE1
(
input clk, input reset, input VAR17, output VAR22, input VAR5, input VAR23, input VAR51, input VAR43, input [7:0] VAR39, input [8:0] VAR28, input [15:0] VAR48, input [8:1] VAR15, output reg [8:1] VAR53, output reg [20:1] VAR41 );
parameter VAR14 = 9'h080;
parameter VAR19 = 9'h082;
parameter VAR9 = 9'h084;
parameter VAR3 = 9'h086;
parameter VAR55 = 9'h02e;
parameter VAR34 = 9'h08c;
parameter VAR33 = 9'h088;
parameter VAR10 = 9'h08a;
parameter VAR49 = 3'b000;
parameter VAR31 = 3'b100;
parameter VAR6 = 3'b101;
parameter VAR35 = 3'b111;
parameter VAR1 = 3'b110;
reg [20:16] VAR21; reg [15:1] VAR50; reg [20:16] VAR24; reg [15:1] VAR44; reg VAR37; reg [15:1] VAR7; reg [15:0] VAR45; reg [2:0] VAR47; reg [2:0] VAR4;
reg VAR16; reg VAR42; reg VAR13;
reg VAR27; reg VAR20; reg VAR38; reg VAR32; reg VAR8;
wire enable; reg VAR11;
wire VAR40;
wire VAR29;
reg VAR26; wire VAR46; reg VAR30;
wire VAR2; reg VAR18; reg VAR54;
assign VAR2 = VAR28[0];
always @(posedge clk)
if (reset)
VAR21[20:16] <= 0;
else if (VAR15[8:1]==VAR14[8:1])
VAR21[20:16] <= VAR48[4:0];
always @(posedge clk)
if (reset)
VAR50[15:1] <= 0;
else if (VAR15[8:1]==VAR19[8:1])
VAR50[15:1] <= VAR48[15:1];
always @(posedge clk)
if (reset)
VAR24[20:16]<=0;
else if (VAR15[8:1]==VAR9[8:1])
VAR24[20:16] <= VAR48[4:0];
always @(posedge clk)
if (reset)
VAR44[15:1] <= 0;
else if (VAR15[8:1]==VAR3[8:1])
VAR44[15:1] <= VAR48[15:1];
always @(posedge clk)
if (reset)
VAR37 <= 0;
else if (VAR15[8:1]==VAR55[8:1])
VAR37 <= VAR48[1];
always @(posedge clk)
if (VAR15[8:1]==VAR34[8:1])
begin
VAR7[15:1] <= VAR45[15:1];
VAR45[15:0] <= VAR48[15:0];
end
always @(posedge clk)
if (VAR40 && VAR16 && VAR47==VAR49) VAR41[20:1] <= {VAR21[20:16],VAR50[15:1]};
else if (VAR40 && VAR42 && VAR47==VAR49) VAR41[20:1] <= {VAR24[20:16],VAR44[15:1]};
else if (VAR40 && (VAR38 || VAR32)) VAR41[20:1] <= VAR41[20:1] + 1'b1;
always @(enable or VAR38 or VAR32 or VAR45)
if (enable & VAR38) VAR53[8:1] = VAR34[8:1];
else if (enable & VAR32) VAR53[8:1] = VAR45[8:1];
else
VAR53[8:1] = 8'hFF;
always @(VAR45 or VAR37 or VAR17)
if (VAR45[8:7]==2'b00 && !VAR37 || VAR45[8:6]==3'b000 && !VAR17) VAR27 = 1'b1;
else VAR27 = 1'b0;
reg VAR36, VAR12;
always @(posedge clk)
if (VAR15[8:1]==VAR33[8:1] || VAR51)
VAR36 = 1;
else if (VAR2)
VAR36 = 0;
always @(posedge clk)
if (VAR15[8:1]==VAR10[8:1])
VAR12 = 1;
else if (VAR2)
VAR12 = 0;
always @(posedge clk)
if (VAR36 && VAR2)
VAR16 = 1;
else if (VAR47==VAR49 && VAR40)
VAR16 = 0;
always @(posedge clk)
if (VAR12 && VAR2)
VAR42 = 1;
else if (VAR47==VAR49 && VAR40)
VAR42 = 0;
always @(posedge clk)
if (VAR2)
VAR13 = VAR36 | VAR12;
wire [8:2] VAR25;
wire [7:0] VAR52;
assign VAR25[2] = (VAR45[1]) ? VAR7[1] : VAR28[2];
assign VAR25[3] = (VAR45[2]) ? VAR7[2] : VAR28[3];
assign VAR25[4] = (VAR45[3]) ? VAR7[3] : VAR28[4];
assign VAR25[5] = (VAR45[4]) ? VAR7[4] : VAR28[5];
assign VAR25[6] = (VAR45[5]) ? VAR7[5] : VAR28[6];
assign VAR25[7] = (VAR45[6]) ? VAR7[6] : VAR28[7];
assign VAR25[8] = (VAR45[7]) ? VAR7[7] : VAR28[8];
assign VAR52[0] = (VAR45[8]) ? VAR7[8] : VAR39[0];
assign VAR52[1] = (VAR45[9]) ? VAR7[9] : VAR39[1];
assign VAR52[2] = (VAR45[10]) ? VAR7[10] : VAR39[2];
assign VAR52[3] = (VAR45[11]) ? VAR7[11] : VAR39[3];
assign VAR52[4] = (VAR45[12]) ? VAR7[12] : VAR39[4];
assign VAR52[5] = (VAR45[13]) ? VAR7[13] : VAR39[5];
assign VAR52[6] = (VAR45[14]) ? VAR7[14] : VAR39[6];
assign VAR52[7] = VAR7[15];
always @(posedge clk)
if (VAR2)
if ({VAR39[7:0],VAR28[8:2]} >= {VAR52[7:0],VAR25[8:2]})
VAR26 <= 1'b1;
else
VAR26 <= 1'b0;
assign VAR46 = VAR26 & (VAR45[15] | ~VAR43);
always @(posedge clk)
if (VAR2)
VAR30 <= VAR46;
always @(posedge clk)
if (VAR2)
if (VAR28[8:1]==8'h01)
VAR54 <= 1; else
VAR54 <= 0;
always @(posedge clk)
if (VAR2)
if (VAR54)
VAR18 <= 1; else
VAR18 <= ~VAR18;
assign enable = ~VAR54 & VAR18 & VAR2;
assign VAR22 = VAR11 & VAR18 & VAR2; assign VAR40 = VAR5 & enable; assign VAR29 = VAR23;
always @(posedge clk)
if (reset || VAR2 && VAR13) VAR47 <= VAR49;
else if (enable) VAR47 <= VAR4;
always @(posedge clk)
if (enable)
VAR20 <= VAR8;
always @(*)begin
case (VAR47)
VAR49:
begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 1; if (VAR40)
VAR4 = VAR31;
end
else
VAR4 = VAR49;
end
VAR31:
begin
VAR8 = VAR20;
VAR38 = 1;
VAR32 = 0;
VAR11 = 1;
if (VAR40)
VAR4 = VAR6;
end
else
VAR4 = VAR31;
end
VAR6:
begin
if (!VAR45[0] && VAR27) begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
VAR4 = VAR6;
end
else if (!VAR45[0] && VAR20) begin
VAR38 = 1;
VAR32 = 0;
VAR11 = 1;
if (VAR40)
begin
VAR8 = 0;
VAR4 = VAR31;
end
else
begin
VAR8 = 1;
VAR4 = VAR6;
end
end
else if (!VAR45[0]) begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 1;
VAR11 = 1;
if (VAR40)
VAR4 = VAR31;
end
else
VAR4 = VAR6;
end
else begin
VAR8 = 0;
VAR38 = 1;
VAR32 = 0;
VAR11 = 1;
if (VAR40)
VAR4 = VAR35;
end
else
VAR4 = VAR6;
end
end
VAR35:
begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
if (VAR29)
VAR4 = VAR1;
end
else
VAR4 = VAR35;
end
VAR1:
begin
if (!VAR45[0]) begin
if (VAR30) begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
if (VAR29)
VAR4 = VAR31;
end
else
VAR4 = VAR1;
end
else begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
VAR4 = VAR1;
end
end
else begin
if (VAR46) begin
VAR8 = 1;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
if (VAR29)
VAR4 = VAR31;
end
else
VAR4 = VAR1;
end
else begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
if (VAR29)
VAR4 = VAR31;
end
else
VAR4 = VAR1;
end
end
end
default:
begin
VAR8 = 0;
VAR38 = 0;
VAR32 = 0;
VAR11 = 0;
VAR4 = VAR31;
end
endcase
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/nor4b/sky130_fd_sc_ls__nor4b.blackbox.v
| 1,322 |
module MODULE1 (
VAR7 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR5;
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule
|
apache-2.0
|
hpeng2/ECE492_Group4_Project
|
ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_video_vga_controller_0.v
| 9,855 |
module MODULE1 (
clk,
reset,
VAR52,
VAR51,
VAR24,
VAR18,
valid,
ready,
VAR25,
VAR10,
VAR5,
VAR39,
VAR49,
VAR17,
VAR54,
VAR42
);
parameter VAR33 = 9;
parameter VAR27 = 29;
parameter VAR30 = 29;
parameter VAR53 = 20;
parameter VAR47 = 19;
parameter VAR28 = 10;
parameter VAR45 = 9;
parameter VAR35 = 0;
parameter VAR55 = 640;
parameter VAR26 = 16;
parameter VAR4 = 96;
parameter VAR56 = 48;
parameter VAR37 = 800;
parameter VAR15 = 480;
parameter VAR9 = 10;
parameter VAR8 = 2;
parameter VAR23 = 33;
parameter VAR48 = 525;
parameter VAR22 = 10;
parameter VAR36 = 10'h001;
parameter VAR7 = 10;
parameter VAR31 = 10'h001;
input clk;
input reset;
input [VAR27: 0] VAR52;
input VAR51;
input VAR24;
input [ 1: 0] VAR18;
input valid;
output ready;
output VAR25;
output reg VAR10;
output reg VAR5;
output reg VAR39;
output reg VAR49;
output reg [VAR33: 0] VAR17;
output reg [VAR33: 0] VAR54;
output reg [VAR33: 0] VAR42;
localparam VAR50 = 1'b0,
VAR16 = 1'b1;
wire VAR57;
wire VAR3;
wire VAR14;
wire VAR19;
wire VAR44;
wire VAR41;
wire VAR6;
wire [VAR33: 0] VAR21;
wire [VAR33: 0] VAR38;
wire [VAR33: 0] VAR40;
wire [VAR33: 0] VAR11;
reg [ 3: 0] VAR29;
reg VAR12;
reg VAR20;
always @(posedge clk) begin
if (reset == 1'b1)
VAR20 <= VAR50;
end
else
VAR20 <= VAR12;
end
always @(*)
begin
VAR12 = VAR50;
case (VAR20)
VAR50:
begin
if (valid & VAR51)
VAR12 = VAR16;
end
else
VAR12 = VAR50;
end
VAR16:
begin
if (VAR3)
VAR12 = VAR50;
end
else
VAR12 = VAR16;
end
default:
begin
VAR12 = VAR50;
end
endcase
end
always @(posedge clk)
begin
VAR10 <= VAR14;
VAR5 <= 1'b0;
VAR39 <= VAR44;
VAR49 <= VAR41;
VAR17 <= VAR21;
VAR54 <= VAR38;
VAR42 <= VAR40;
end
always @(posedge clk)
begin
if (reset)
VAR29 <= 4'h1;
end
else if (VAR20 == VAR50)
VAR29 <= 4'h1;
else if (~VAR57)
VAR29 <= {VAR29[2:0], VAR29[3]};
end
assign ready =
(VAR20 == VAR50) ?
valid & ~VAR51 :
VAR57;
assign VAR25 = ~clk;
VAR34 VAR1 (
.clk (clk),
.reset (reset),
.VAR46 (VAR52[VAR30:VAR53]),
.VAR13 (VAR52[VAR47:VAR28]),
.VAR32 (VAR52[VAR45:VAR35]),
.VAR29 (VAR29),
.VAR57 (VAR57),
.VAR3 (VAR3),
.VAR2 (),
.VAR43 (VAR14),
.VAR19 (VAR19),
.VAR44 (VAR44),
.VAR41 (VAR41),
.VAR6 (VAR6),
.VAR21 (VAR21),
.VAR38 (VAR38),
.VAR40 (VAR40),
.VAR11 (VAR11)
);
VAR1.VAR33 = VAR33,
VAR1.VAR55 = VAR55,
VAR1.VAR26 = VAR26,
VAR1.VAR4 = VAR4,
VAR1.VAR56 = VAR56,
VAR1.VAR37 = VAR37,
VAR1.VAR15 = VAR15,
VAR1.VAR9 = VAR9,
VAR1.VAR8 = VAR8,
VAR1.VAR23 = VAR23,
VAR1.VAR48 = VAR48,
VAR1.VAR22 = VAR22,
VAR1.VAR36 = VAR36,
VAR1.VAR7 = VAR7,
VAR1.VAR31 = VAR31;
endmodule
|
gpl-2.0
|
hakehuang/pycpld
|
ips/ip/ir_recieve/ir_recieve.v
| 2,431 |
module MODULE1(
clk, rst, VAR7, VAR2,VAR10
);
input clk;
input rst;
input VAR7;
output VAR2;
output [10:0] VAR10;
reg[1:0] VAR8;
wire VAR6;
wire VAR1;
reg[10:0] VAR10;
reg[7:0] VAR4;
reg[7:0] VAR5;
reg VAR2;
reg [31:0] VAR11;
reg [2:0] VAR3;
reg VAR9;
always @(posedge clk or negedge rst)begin
if(!rst)begin
VAR3 <= 'h0;
VAR5 <= 'h0;
end
else begin
if(VAR6 && VAR5 < 'd3)begin
VAR3[VAR5]<= 1'b1;
VAR5 <= VAR5 + 1'b1;
end
else begin
VAR3 <= VAR3;
VAR5 <= VAR5;
end
end
end
always @(posedge clk or negedge rst)begin
if(!rst)begin
VAR11 <= 'h0;
VAR4 <= 'h0;
VAR9 <= 'h0;
end
else begin
if(VAR3 == 3'b111 && VAR9 == 0 && VAR11 < 'd44500)
VAR11 <= VAR11 + 1'b1;
end
else if(VAR3 == 3'b111 && VAR9 == 0 && VAR11 == 'd44500)begin
VAR11 <= 'h0;
VAR9 <= 'h1;
end
else begin
if(VAR3 == 3'b111 && VAR11 < 'd89000 && VAR4 < 'd11 && VAR9 == 1)begin
VAR11 <= VAR11 + 1'b1;
end
else if(VAR3 == 3'b111 && VAR11 == 'd89000 && VAR4 < 'd11 && VAR9 == 1)begin
VAR11 <= 'h0;
VAR4 <= VAR4 + 1'b1;
end
else begin
VAR11 <= VAR11;
VAR4 <= VAR4;
VAR9 <= VAR9;
end
end
end
end
always @(posedge clk or negedge rst)begin
if(!rst)
VAR8 <= 2'b11;
end
else begin
VAR8[0] <= VAR7;
VAR8[1] <= VAR8[0];
end
end
assign VAR6 = (VAR8[1:0] == 2'b10) ? 1'b1 : 1'b0;
assign VAR1 = (VAR8[1:0] == 2'b01) ? 1'b1 : 1'b0;
always @(posedge clk or negedge rst)begin
if(!rst)begin
VAR10 <= 'h0;
end
else begin
if(VAR6 && VAR11 > 'd30000 && VAR11 < 'd60000 && VAR4 < 'd11)begin
VAR10[VAR4] <= 1'b1;
end
else if(VAR1 && VAR11 > 'd30000 && VAR11 < 'd60000 && VAR4 < 'd11)begin
VAR10[VAR4] <= 1'b0;
end
else begin
VAR10 <= VAR10;
end
end
end
always @(posedge clk or negedge rst)begin
if(!rst)
VAR2 <= 1'b0;
end
else
VAR2 <= ( VAR10 == 11'b00011110101) ? 1'b1 : 1'b0;
end
endmodule
|
mit
|
LSaldyt/qnp
|
output/vs/opt_var7_multi.v
| 3,695 |
module MODULE1(VAR4, VAR1, VAR7, VAR3, VAR5, VAR6, VAR2, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wire 023;
wire 024;
wire 025;
wire 026;
wire 027;
wire 028;
wire 029;
wire 030;
wire 031;
wire 032;
wire 033;
wire 034;
wire 035;
wire 036;
wire 037;
wire 038;
wire 039;
wire 040;
wire 041;
wire 042;
wire 043;
wire 044;
wire 045;
wire 046;
wire 047;
wire 048;
wire 049;
wire 050;
wire 051;
wire 052;
wire 053;
wire 054;
wire 055;
wire 056;
wire 057;
wire 058;
wire 059;
wire 060;
wire 061;
wire 062;
wire 063;
wire 064;
input VAR4;
input VAR1;
input VAR7;
input VAR3;
input VAR5;
input VAR6;
input VAR2;
output valid;
assign 064 = VAR4 & VAR3;
assign 000 = 064 ^ VAR1;
assign 001 = 000 ^ VAR5;
assign 002 = ~VAR6;
assign 003 = VAR4 ^ VAR3;
assign 004 = ~(003 | 002);
assign 005 = 004 ^ 001;
assign 006 = ~(005 & VAR2);
assign 007 = 000 & VAR5;
assign 008 = ~(VAR4 & VAR1);
assign 009 = ~(008 & VAR3);
assign 010 = 009 ^ 007;
assign 011 = ~((003 | 001) & VAR6);
assign 012 = ~(011 ^ 010);
assign 013 = 003 ^ VAR6;
assign 014 = 013 | VAR5;
assign 015 = ~((014 & 005) | VAR2);
assign 016 = ~((015 | 012) & 006);
assign 017 = ~VAR5;
assign 018 = VAR7 & VAR3;
assign 019 = 018 ^ VAR4;
assign 020 = VAR7 | VAR3;
assign 021 = 020 & VAR5;
assign 022 = ~(021 & 019);
assign 023 = ~(VAR4 ^ VAR1);
assign 024 = ~VAR7;
assign 025 = ~(064 | 024);
assign 026 = 025 ^ 023;
assign 027 = ~((026 | 017) & 022);
assign 028 = ~VAR4;
assign 029 = 028 & VAR1;
assign 030 = 028 | VAR1;
assign 031 = ~((030 & 024) | 029);
assign 032 = ~(064 | 018);
assign 033 = ~((032 | VAR1) & (031 | VAR3));
assign 034 = 033 ^ 017;
assign 035 = ~(034 ^ 027);
assign 036 = 021 | 019;
assign 037 = 022 & VAR5;
assign 038 = ~(037 ^ 026);
assign 039 = ~((036 & 022) | 038);
assign 040 = ~(039 & 035);
assign 041 = 018 & VAR4;
assign 042 = ~(VAR4 | VAR1);
assign 043 = ~((042 | 024) & 008);
assign 044 = ~((031 & VAR3) | 043);
assign 045 = ~((044 | 041) & (033 | 017));
assign 046 = ~((034 & 027) | 045);
assign 047 = ~(046 | 002);
assign 048 = VAR4 & VAR1;
assign 049 = ~((007 | 048) & VAR3);
assign 050 = ~((011 | 010) & 049);
assign 051 = 048 & 020;
assign 052 = ~(VAR7 & VAR3);
assign 053 = ~(020 & 052);
assign 054 = ~VAR2;
assign 055 = ~(023 & 054);
assign 056 = ~((055 | 053) & 051);
assign 057 = ~((042 | 002) & 056);
assign 058 = ~(023 | VAR2);
assign 059 = ~((058 & 053) | (008 & 052));
assign 060 = ~((059 & 057) | 041);
assign 061 = 060 & 050;
assign 062 = ~(061 & 022);
assign 063 = ~((047 & 040) | 062);
assign valid = 063 & 016;
endmodule
|
mit
|
ECE492-Team5/Platform
|
soc-platform-quartusii/soc_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
| 7,553 |
module MODULE1
parameter VAR30 = 8,
VAR38 = 8,
VAR1 = 0,
VAR26 = 0,
VAR6 = 1,
VAR7 = 0,
VAR36 = 1,
VAR18 = 2,
VAR3 = 2,
VAR45 = 1,
VAR39 = VAR30 / VAR38,
VAR43 = VAR2(VAR39)
)
(
input VAR24,
input VAR17,
input VAR29,
input VAR22,
output VAR37,
input VAR33,
input [VAR30 - 1 : 0] VAR20,
input [VAR6 - 1 : 0] VAR40,
input [VAR36 - 1 : 0] VAR11,
input VAR42,
input VAR5,
input [(VAR43 ? (VAR43 - 1) : 0) : 0] VAR12,
input VAR9,
output VAR25,
output [VAR30 - 1 : 0] VAR4,
output [VAR6 - 1 : 0] VAR21,
output [VAR36 - 1 : 0] VAR10,
output VAR28,
output VAR35,
output [(VAR43 ? (VAR43 - 1) : 0) : 0] VAR34
);
localparam VAR41 = (VAR1) ? 2 + VAR43 : 0;
localparam VAR23 = (VAR26) ? VAR6 : 0;
localparam VAR16 = (VAR7) ? VAR36 : 0;
localparam VAR31 = VAR30 +
VAR41 +
VAR23 +
VAR43 +
VAR16;
wire [VAR31 - 1: 0] VAR32;
wire [VAR31 - 1: 0] VAR14;
assign VAR32[VAR30 - 1 : 0] = VAR20;
generate
if (VAR41) begin
assign VAR32[
VAR30 + VAR41 - 1 :
VAR30
] = {VAR42, VAR5};
end
if (VAR26) begin
assign VAR32[
VAR30 + VAR41 + VAR23 - 1 :
VAR30 + VAR41
] = VAR40;
end
if (VAR43) begin
assign VAR32[
VAR30 + VAR41 + VAR23 + VAR43 - 1 :
VAR30 + VAR41 + VAR23
] = VAR12;
end
if (VAR7) begin
assign VAR32[
VAR30 + VAR41 + VAR23 + VAR43 + VAR16 - 1 :
VAR30 + VAR41 + VAR23 + VAR43
] = VAR11;
end
endgenerate
VAR8
.VAR39 (1),
.VAR38 (VAR31),
.VAR15 (VAR18),
.VAR44 (VAR3),
.VAR45 (VAR45)
) VAR27 (
.VAR24 (VAR24 ),
.VAR17 (VAR17 ),
.VAR37 (VAR37 ),
.VAR33 (VAR33 ),
.VAR20 (VAR32 ),
.VAR29 (VAR29 ),
.VAR22 (VAR22 ),
.VAR9 (VAR9 ),
.VAR25 (VAR25 ),
.VAR4 (VAR14 )
);
assign VAR4 = VAR14[VAR30 - 1 : 0];
generate
if (VAR1) begin
assign {VAR28, VAR35} =
VAR14[VAR30 + VAR41 - 1 : VAR30];
end else begin
assign {VAR28, VAR35} = 2'b0;
end
if (VAR26) begin
assign VAR21 = VAR14[
VAR30 + VAR41 + VAR23 - 1 :
VAR30 + VAR41
];
end else begin
assign VAR21 = 1'b0;
end
if (VAR43) begin
assign VAR34 = VAR14[
VAR30 + VAR41 + VAR23 + VAR43 - 1 :
VAR30 + VAR41 + VAR23
];
end else begin
assign VAR34 = 1'b0;
end
if (VAR7) begin
assign VAR10 = VAR14[
VAR30 + VAR41 + VAR23 + VAR43 + VAR16 - 1 :
VAR30 + VAR41 + VAR23 + VAR43
];
end else begin
assign VAR10 = 1'b0;
end
endgenerate
function integer VAR2;
input integer VAR19;
integer VAR13;
begin
VAR13 = 1;
VAR2 = 0;
while (VAR13 < VAR19) begin
VAR2 = VAR2 + 1;
VAR13 = VAR13 << 1;
end
end
endfunction
endmodule
|
gpl-3.0
|
Jesus89/open-fpga-verilog-tutorial
|
tutorial/ICESTICK/T06-multiples-prescalers/mpres.v
| 1,937 |
module MODULE1(input VAR12, output VAR1, output VAR19, output VAR18, output VAR14);
wire VAR12;
wire VAR1;
wire VAR19;
wire VAR18;
wire VAR14;
parameter VAR4 = 21; parameter VAR9 = 1;
parameter VAR10 = 2;
parameter VAR5 = 1;
parameter VAR16 = 2;
wire VAR17;
VAR2 #(.VAR8(VAR4))
VAR6(
.VAR12(VAR12),
.VAR13(VAR17)
);
VAR2 #(.VAR8(VAR9))
VAR3(
.VAR12(VAR17),
.VAR13(VAR1)
);
VAR2 #(.VAR8(VAR10))
VAR7(
.VAR12(VAR17),
.VAR13(VAR19)
);
VAR2 #(.VAR8(VAR5))
VAR11(
.VAR12(VAR17),
.VAR13(VAR18)
);
VAR2 #(.VAR8(VAR16))
VAR15(
.VAR12(VAR17),
.VAR13(VAR14)
);
endmodule
|
gpl-2.0
|
zYeoman/32BIT-MIPS-CPU
|
Single/Control.v
| 5,053 |
module MODULE1 (
input irq, VAR14,
input [5:0] VAR16, VAR5,
output [2:0] VAR18,
output [1:0] VAR19, VAR6, VAR22,
output VAR11, VAR35, VAR7, VAR24,
VAR33, VAR27, VAR4, VAR28, VAR29,
output reg [5:0] VAR23
);
wire VAR17; reg [5:0] VAR15;
parameter VAR8 = 6'b000000;
parameter VAR25 = 6'b000001;
parameter VAR13 = 6'b011000;
parameter VAR34 = 6'b011110;
parameter VAR21 = 6'b010110;
parameter VAR20 = 6'b010001;
parameter VAR9 = 6'b011010;
parameter VAR12 = 6'b100000;
parameter VAR30 = 6'b100001;
parameter VAR10 = 6'b100011;
parameter VAR32 = 6'b110011;
parameter VAR31 = 6'b110001;
parameter VAR3 = 6'b110101;
parameter VAR1 = 6'b111101;
parameter VAR2 = 6'b111001;
parameter VAR26 = 6'b111111;
assign VAR17 = ~( ( VAR16 <= 6'hd && VAR16 >= 6'h1 ) || (VAR16 == 6'hf || VAR16 == 6'h23 || VAR16 == 6'h2b) ||
( VAR16 == 6'h0 && (VAR5 == 6'h8 || VAR5 == 6'h9 || VAR5 == 6'h0 || VAR5 == 6'h2 || VAR5 == 6'h3 || (VAR5 >= 6'h20 && VAR5 <= 6'h27) || VAR5 == 6'h2a || VAR5 == 6'h2b ) ) );
assign VAR18 = (~VAR14&irq) ? 3'h4 : (~VAR14&VAR17) ? 3'h5 : (VAR16 == 6'h00) ? ( (VAR5 == 6'h08)|(VAR5 == 6'h09) ? 3'h3 : 3'h0 ) : (VAR16 == 6'h02 || VAR16 == 6'h03) ? 3'h2 : (VAR16 == 6'h01 || (VAR16 > 6'h03 && VAR16 < 6'h08)) ? 3'h1 : 3'h0 ; assign VAR22 = (VAR16 == 6'h00) ? ( (VAR5 == 6'h08)|(VAR5 == 6'h09) ? 2'h3 : 2'h0 ) : (VAR16 == 6'h02 || VAR16 == 6'h03) ? 2'h2 : (VAR16 == 6'h01 || (VAR16 > 6'h03 && VAR16 < 6'h08)) ? 2'h1 : 2'h0 ;
assign VAR24 = (VAR16 < 6'h08) ? 1'b1 : 1'b0;
assign VAR11 = (~VAR14&irq)|(~VAR14&VAR17) ? 1'b1 :
(VAR16 == 6'h01 || VAR16 == 6'h02 || VAR16 == 6'h04 || VAR16 == 6'h05 || VAR16 == 6'h06 || VAR16 == 6'h07 || VAR16 == 6'h2b || (VAR16==6'h00 && VAR5==6'h08)) ? 1'b0 : 1'b1;
assign VAR19 = (~VAR14&irq)|(~VAR14&VAR17) ? 2'h3 :
(VAR16 == 6'h23 || VAR16 == 6'hf || VAR16 == 6'h8 || VAR16 == 6'h9 || VAR16 == 6'hc || VAR16 == 6'hd || VAR16 == 6'ha || VAR16 == 6'hb) ? 2'h1 :
(VAR16 == 6'h03 || (VAR16 == 6'h0 && VAR5 == 6'h9) ) ? 2'h2 :
2'h0 ;
assign VAR27 = (~VAR14&irq)|(VAR16 == 6'h23) ? 1'b1 : 1'b0;
assign VAR33 = (VAR16 == 6'h2b) ? 1'b1 : 1'b0;
assign VAR6 = (~VAR14&irq)|(~VAR14&VAR17) ? 2'h2 :
(VAR16 == 6'h23) ? 2'h1 :
( VAR16 == 6'h03 || (VAR16==6'h00 && (VAR5 == 6'h08 || VAR5 == 6'h09)) ) ? 2'h2 :
2'h0 ;
assign VAR35 = (VAR16 == 6'h00) ? ( (VAR5 == 6'h0 || VAR5 == 6'h2 || VAR5 == 6'h3) ? 1'b1 : 1'b0 ) : 1'b0;
assign VAR7 = (VAR16 == 6'h00 || (VAR16 >= 6'h1 && VAR16 <= 6'h7) ) ? 1'b0 : 1'b1;
assign VAR4 = (VAR16 == 6'h0) ? ( (VAR5 == 6'h20 || VAR5 == 6'h22 || VAR5 == 6'h2a || VAR5 == 6'h8) ? 1'b1 : 1'b0 ) :
( (VAR16 == 6'h23 || VAR16 == 6'h2b || VAR16 == 6'h8 || VAR16 == 6'h1 || VAR16 == 6'ha || (VAR16 >= 6'h4 && VAR16 <= 6'h7) ) ? 1'b1 : 1'b0 );
assign VAR28 = (VAR16 == 6'h0f) ? 1'b1 : 1'b0;
assign VAR29 = VAR4;
always @
case (VAR16)
6'h00: VAR23 = VAR15;
6'h23: VAR23 = VAR8;
6'h2b: VAR23 = VAR8;
6'h0f: VAR23 = VAR8;
6'h08: VAR23 = VAR8;
6'h09: VAR23 = VAR8;
6'h0c: VAR23 = VAR13;
6'h0d: VAR23 = VAR34;
6'h0a: VAR23 = VAR3;
6'h0b: VAR23 = VAR3;
6'h04: VAR23 = VAR32;
6'h05: VAR23 = VAR31;
6'h06: VAR23 = VAR1;
6'h07: VAR23 = VAR26;
6'h01: VAR23 = VAR2;
6'h02: VAR23 = VAR8;
6'h03: VAR23 = VAR8;
default : VAR23 = VAR9; endcase
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a311oi/sky130_fd_sc_lp__a311oi.pp.symbol.v
| 1,402 |
module MODULE1 (
input VAR10 ,
input VAR4 ,
input VAR2 ,
input VAR5 ,
input VAR9 ,
output VAR6 ,
input VAR1 ,
input VAR8,
input VAR3,
input VAR7
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.functional.v
| 1,378 |
module MODULE1( VAR8, VAR3, VAR13, VAR12, VAR11 );
input VAR11, VAR12, VAR13, VAR8;
output VAR3;
wire VAR14;
not VAR4( VAR14, VAR11 );
wire VAR7;
not VAR6( VAR7, VAR12 );
wire VAR9;
not VAR5( VAR9, VAR13 );
wire VAR1;
not VAR2( VAR1, VAR8 );
and VAR10( VAR3, VAR14, VAR7, VAR9, VAR1 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2.symbol.v
| 1,322 |
module MODULE1 (
input VAR3,
output VAR5
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3.pp.symbol.v
| 1,357 |
module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR6 ,
input VAR5,
input VAR1,
input VAR4
);
endmodule
|
apache-2.0
|
Franderg/CE-4301-Arqui1
|
Processor/unsaved/synthesis/submodules/unsaved_onchip_memory2_0.v
| 3,237 |
module MODULE1 (
address,
VAR9,
VAR20,
clk,
VAR39,
VAR34,
VAR4,
reset,
VAR16,
write,
VAR22,
VAR44
)
;
output [ 31: 0] VAR44;
input [ 4: 0] address;
input [ 3: 0] VAR9;
input VAR20;
input clk;
input VAR39;
input VAR34;
input VAR4;
input reset;
input VAR16;
input write;
input [ 31: 0] VAR22;
wire VAR28;
wire [ 31: 0] VAR44;
wire VAR37;
assign VAR37 = VAR20 & write & VAR34;
assign VAR28 = VAR39 & ~VAR16;
VAR6 VAR23
(
.VAR5 (address),
.VAR40 (VAR9),
.VAR7 (clk),
.VAR28 (VAR28),
.VAR15 (VAR22),
.VAR43 (VAR44),
.VAR8 (VAR37)
);
VAR23.VAR41 = VAR10,
VAR23.VAR42 = "VAR6",
VAR23.VAR21 = 32,
VAR23.VAR12 = 32,
VAR23.VAR17 = "VAR2",
VAR23.VAR35 = "VAR14",
VAR23.VAR3 = "VAR29",
VAR23.VAR24 = "VAR13",
VAR23.VAR32 = "VAR13",
VAR23.VAR1 = 32,
VAR23.VAR27 = 4,
VAR23.VAR36 = 5;
endmodule
|
gpl-3.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/HardFloat/source/recFNToRecFN.v
| 4,789 |
module
MODULE1#(
parameter VAR21 = 3,
parameter VAR13 = 3,
parameter VAR8 = 3,
parameter VAR15 = 3
) (
input [(VAR10 - 1):0] VAR11,
input [(VAR21 + VAR13):0] in,
input [2:0] VAR5,
output [(VAR8 + VAR15):0] out,
output [4:0] VAR7
);
wire VAR23, VAR22, VAR19, VAR1;
wire signed [(VAR21 + 1):0] VAR16;
wire [VAR13:0] VAR3;
VAR24#(VAR21, VAR13)
VAR12(in, VAR23, VAR22, VAR19, VAR1, VAR16, VAR3);
wire VAR14;
VAR4#(VAR21, VAR13) VAR18(in, VAR14);
generate
if ((VAR21 == VAR8) && (VAR13 <= VAR15)) begin
wire [(VAR8 + VAR15):0] VAR2 =
in<<(VAR15 - VAR13);
assign out = VAR2 | VAR23<<(VAR15 - 2);
assign out =
VAR23
? {VAR20, 3'b111}
<<(VAR8 + VAR15 - 3)
| VAR6(VAR15)
: VAR2;
assign VAR7 = {VAR14, 4'b0000};
end else begin
VAR9#(
VAR21,
VAR13,
VAR8,
VAR15,
) VAR17(
VAR11,
VAR14,
1'b0,
VAR23,
VAR22,
VAR19,
VAR1,
VAR16,
VAR3,
VAR5,
out,
VAR7
);
end
endgenerate
endmodule
|
bsd-3-clause
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v
| 10,974 |
module MODULE1 (
VAR41,
VAR11,
VAR32);
input VAR41;
input VAR11;
output VAR32;
wire [5:0] VAR14;
wire [0:0] VAR26 = 1'h0;
wire [0:0] VAR37 = 1'h1;
wire [0:0] VAR10 = VAR14[0:0];
wire VAR32 = VAR10;
wire [5:0] VAR47 = {VAR26, VAR26, VAR26, VAR26, VAR26, VAR37};
wire VAR29 = VAR11;
wire [1:0] VAR1 = {VAR26, VAR29};
wire [3:0] VAR31 = {VAR26, VAR26, VAR26, VAR26};
VAR2 VAR17 (
.VAR45 (VAR47),
.VAR27 (VAR1),
.VAR4 (VAR31),
.VAR41 (VAR41),
.clk (VAR14)
,
.VAR28 (),
.VAR53 (),
.VAR7 (),
.VAR48 (),
.VAR5 (),
.VAR9 (),
.VAR46 (),
.VAR42 (),
.VAR22 (),
.VAR6 (),
.VAR23 (),
.VAR50 (),
.VAR39 (),
.VAR30 (),
.VAR21 (),
.VAR19 (),
.VAR33 (),
.VAR35 (),
.VAR54 (),
.VAR40 ()
);
VAR17.VAR49 = 500000,
VAR17.VAR20 = "VAR12",
VAR17.VAR13 = 5,
VAR17.VAR36 = 50,
VAR17.VAR34 = 2,
VAR17.VAR38 = "0",
VAR17.VAR16 = "VAR15",
VAR17.VAR52 = 4000,
VAR17.VAR8 = "VAR51 VAR3",
VAR17.VAR24 = "VAR2",
VAR17.VAR44 = "VAR25",
VAR17.VAR18 = "VAR43",
VAR17.VAR55 = 0;
endmodule
|
mit
|
alexforencich/xfcp
|
lib/eth/rtl/axis_eth_fcs_insert.v
| 11,227 |
module MODULE1 #
(
parameter VAR34 = 0,
parameter VAR17 = 64
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR58,
input wire VAR3,
output wire VAR55,
input wire VAR35,
input wire VAR23,
output wire [7:0] VAR46,
output wire VAR62,
input wire VAR15,
output wire VAR49,
output wire VAR38,
output wire VAR30
);
localparam [1:0]
VAR57 = 2'd0,
VAR18 = 2'd1,
VAR32 = 2'd2,
VAR51 = 2'd3;
reg [1:0] VAR59 = VAR57, VAR61;
reg VAR53;
reg VAR6;
reg [15:0] VAR45 = 16'd0, VAR20;
reg VAR28 = 1'b0;
reg VAR16 = 1'b0, VAR10;
reg [31:0] VAR7 = 32'hFFFFFFFF;
wire [31:0] VAR2;
reg [7:0] VAR1;
reg VAR36;
reg VAR56 = 1'b0;
reg VAR4;
reg VAR42;
wire VAR13;
assign VAR55 = VAR16;
assign VAR30 = VAR28;
VAR24 #(
.VAR26(32),
.VAR9(32'h4c11db7),
.VAR8("VAR39"),
.VAR21(0),
.VAR41(1),
.VAR12(8),
.VAR27("VAR43")
)
VAR11 (
.VAR19(VAR1),
.VAR29(VAR7),
.VAR14(),
.VAR31(VAR2)
);
always @* begin
VAR61 = VAR57;
VAR53 = 1'b0;
VAR6 = 1'b0;
VAR20 = VAR45;
VAR10 = 1'b0;
VAR1 = 8'd0;
VAR36 = 1'b0;
VAR4 = 1'b0;
VAR42 = 1'b0;
case (VAR59)
VAR57: begin
VAR10 = VAR13;
VAR20 = 16'd0;
VAR53 = 1'b1;
VAR1 = VAR58;
VAR36 = VAR3;
VAR4 = 1'b0;
VAR42 = 1'b0;
if (VAR55 && VAR3) begin
VAR20 = 16'd1;
VAR53 = 1'b0;
VAR6 = 1'b1;
if (VAR35) begin
if (VAR23) begin
VAR4 = 1'b1;
VAR42 = 1'b1;
VAR53 = 1'b1;
VAR20 = 16'd0;
VAR61 = VAR57;
end else begin
VAR10 = 1'b0;
if (VAR34 && VAR45 < VAR17-5) begin
VAR61 = VAR32;
end else begin
VAR20 = 16'd0;
VAR61 = VAR51;
end
end
end else begin
VAR61 = VAR18;
end
end else begin
VAR61 = VAR57;
end
end
VAR18: begin
VAR10 = VAR13;
VAR1 = VAR58;
VAR36 = VAR3;
VAR4 = 1'b0;
VAR42 = 1'b0;
if (VAR55 && VAR3) begin
VAR20 = VAR45 + 16'd1;
VAR6 = 1'b1;
if (VAR35) begin
if (VAR23) begin
VAR4 = 1'b1;
VAR42 = 1'b1;
VAR53 = 1'b1;
VAR20 = 16'd0;
VAR61 = VAR57;
end else begin
VAR10 = 1'b0;
if (VAR34 && VAR45 < VAR17-5) begin
VAR61 = VAR32;
end else begin
VAR20 = 16'd0;
VAR61 = VAR51;
end
end
end else begin
VAR61 = VAR18;
end
end else begin
VAR61 = VAR18;
end
end
VAR32: begin
VAR10 = 1'b0;
VAR1 = 8'd0;
VAR36 = 1'b1;
VAR4 = 1'b0;
VAR42 = 1'b0;
if (VAR56) begin
VAR20 = VAR45 + 16'd1;
VAR6 = 1'b1;
if (VAR45 < VAR17-5) begin
VAR61 = VAR32;
end else begin
VAR20 = 16'd0;
VAR61 = VAR51;
end
end else begin
VAR61 = VAR32;
end
end
VAR51: begin
VAR10 = 1'b0;
case (VAR45)
2'd0: VAR1 = ~VAR7[7:0];
2'd1: VAR1 = ~VAR7[15:8];
2'd2: VAR1 = ~VAR7[23:16];
2'd3: VAR1 = ~VAR7[31:24];
endcase
VAR36 = 1'b1;
VAR4 = 1'b0;
VAR42 = 1'b0;
if (VAR56) begin
VAR20 = VAR45 + 16'd1;
if (VAR45 < 16'd3) begin
VAR61 = VAR51;
end else begin
VAR53 = 1'b1;
VAR20 = 16'd0;
VAR4 = 1'b1;
VAR10 = VAR13;
VAR61 = VAR57;
end
end else begin
VAR61 = VAR51;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
VAR59 <= VAR57;
VAR45 <= 1'b0;
VAR16 <= 1'b0;
VAR28 <= 1'b0;
VAR7 <= 32'hFFFFFFFF;
end else begin
VAR59 <= VAR61;
VAR45 <= VAR20;
VAR16 <= VAR10;
VAR28 <= VAR61 != VAR57;
if (VAR53) begin
VAR7 <= 32'hFFFFFFFF;
end else if (VAR6) begin
VAR7 <= VAR2;
end
end
end
reg [7:0] VAR52 = 8'd0;
reg VAR33 = 1'b0, VAR5;
reg VAR40 = 1'b0;
reg VAR60 = 1'b0;
reg [7:0] VAR44 = 8'd0;
reg VAR50 = 1'b0, VAR47;
reg VAR22 = 1'b0;
reg VAR48 = 1'b0;
reg VAR54;
reg VAR25;
reg VAR37;
assign VAR46 = VAR52;
assign VAR62 = VAR33;
assign VAR49 = VAR40;
assign VAR38 = VAR60;
assign VAR13 = VAR15 || (!VAR50 && (!VAR33 || !VAR36));
always @* begin
VAR5 = VAR33;
VAR47 = VAR50;
VAR54 = 1'b0;
VAR25 = 1'b0;
VAR37 = 1'b0;
if (VAR56) begin
if (VAR15 || !VAR33) begin
VAR5 = VAR36;
VAR54 = 1'b1;
end else begin
VAR47 = VAR36;
VAR25 = 1'b1;
end
end else if (VAR15) begin
VAR5 = VAR50;
VAR47 = 1'b0;
VAR37 = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
VAR33 <= 1'b0;
VAR56 <= 1'b0;
VAR50 <= 1'b0;
end else begin
VAR33 <= VAR5;
VAR56 <= VAR13;
VAR50 <= VAR47;
end
if (VAR54) begin
VAR52 <= VAR1;
VAR40 <= VAR4;
VAR60 <= VAR42;
end else if (VAR37) begin
VAR52 <= VAR44;
VAR40 <= VAR22;
VAR60 <= VAR48;
end
if (VAR25) begin
VAR44 <= VAR1;
VAR22 <= VAR4;
VAR48 <= VAR42;
end
end
endmodule
|
mit
|
CalvinHsu1223/LinuxCNC-EtherCAT-HAL-Driver
|
src/hal/drivers/pluto_servo_firmware/quad.v
| 1,769 |
module MODULE1(clk, VAR8, VAR12, VAR13, VAR3, out);
parameter VAR15=14;
input clk, VAR8, VAR12, VAR13, VAR3;
reg [(VAR15-1):0] VAR9, VAR2; reg VAR10;
output [2*VAR15:0] out = { VAR10, VAR2, VAR9 };
reg [2:0] VAR1, VAR17;
reg [2:0] VAR16;
always @(posedge clk) VAR1 <= {VAR1[1:0], VAR8};
always @(posedge clk) VAR17 <= {VAR17[1:0], VAR12};
wire VAR11 = &VAR16;
wire VAR5 = ~|VAR16;
reg VAR6;
wire VAR7 = VAR11 && ! VAR6;
wire VAR14 = VAR1[1] ^ VAR1[2] ^ VAR17[1] ^ VAR17[2];
wire VAR4 = VAR1[1] ^ VAR17[2];
always @(posedge clk)
begin
if(VAR13 && !VAR11) VAR16 <= VAR16 + 2'b1;
end
else if(!VAR5) VAR16 <= VAR16 - 2'b1;
if(VAR11) VAR6 <= 1;
else if(VAR5) VAR6 <= 0;
if(VAR14)
begin
if(VAR4) VAR9 <= VAR9 + 1'd1;
end
else VAR9 <= VAR9 - 1'd1;
end
if(VAR7) begin
VAR2 <= VAR9;
VAR10 <= 1;
end else if(VAR3) begin
VAR10 <= 0;
end
end
endmodule
|
gpl-2.0
|
borti4938/n64rgb
|
advancedRGBmod/firmware/rtl/ppu/gamma_module.v
| 4,602 |
module MODULE1(
VAR30,
VAR31,
VAR18,
VAR5,
VAR19,
VAR6,
VAR15
);
input VAR30;
input VAR31;
input [ 3:0] VAR18;
input VAR5;
input [VAR11] VAR19;
output reg VAR6;
output reg [VAR11] VAR15 = {VAR3{1'b0}};
wire VAR14 = ~(VAR18 == VAR7);
wire [3:0] VAR27 = (VAR18 < VAR7) ? VAR18 :
VAR18 - 1'b1;
wire [2:0] VAR1 = VAR27[2:0];
wire [VAR8] VAR4;
reg [1:0] VAR22 = 2'b00;
reg [VAR29-1:0] VAR9 = {VAR29{1'b0}};
wire [VAR29-1:0] VAR16;
always @(posedge VAR30 or negedge VAR31)
if (!VAR31) begin
VAR22 <= 2'b00;
VAR9 <= {VAR29{1'b0}};
end else begin
if (VAR5) begin
VAR22 <= 2'b01;
VAR9 <= VAR19[VAR25];
end else begin
if (VAR22 == 2'b01)
VAR9 <= VAR19[VAR10];
if (VAR22 == 2'b10)
VAR9 <= VAR19[VAR12];
VAR22 <= VAR22 + 2'b01;
end
end
VAR28 VAR13(
.VAR30(VAR30),
.VAR31(VAR31),
.VAR23(VAR1),
.VAR17(VAR9),
.VAR2(VAR14),
.VAR26(VAR16)
);
reg VAR20[0:2];
reg [3:0] VAR21[0:2];
integer VAR24;
|
gpl-3.0
|
YuxuanLing/trunk
|
trunk/references/h265enc_v1.0/rtl/top/mem_lipo_1p_bw.v
| 12,985 |
module MODULE1 (
clk ,
VAR54 ,
VAR38 ,
VAR40 ,
VAR7 ,
VAR48 ,
VAR43 ,
VAR47 ,
VAR42 ,
VAR55 ,
VAR25 ,
VAR35
);
localparam VAR26 = 2'b00,
VAR50 = 2'b01,
VAR49 = 2'b10,
VAR9 = 2'b11;
input clk ; input VAR54 ;
input [3:0] VAR38 ; input [7:0] VAR40 ; input [VAR34*32-1:0] VAR7 ;
input VAR48 ; input VAR43 ; input [1:0] VAR47 ; input [3:0] VAR42 ; input [3:0] VAR55 ; input [4:0] VAR25 ; output [VAR34*32-1:0] VAR35 ;
reg [4:0] VAR27,
VAR16,
VAR17,
VAR56;
wire [7:0] VAR23, VAR51,
VAR45, VAR6,
VAR44, VAR37,
VAR33, VAR46;
wire VAR8,
VAR24,
VAR10,
VAR15;
reg VAR57,
VAR5,
VAR32,
VAR21;
reg [VAR34*8-1:0] VAR2,
VAR13,
VAR3,
VAR11;
wire [VAR34*8-1:0] VAR53,
VAR36,
VAR30,
VAR12;
reg [VAR34*32-1:0] VAR35;
reg [1:0] VAR52 ;
reg [3:0] VAR14;
reg [4:0] VAR31 ;
always @ begin
case (VAR47)
VAR26 ,
VAR50 : begin
case (VAR42[2:1])
2'd0: begin VAR27[1:0]=2'd0; VAR16[1:0]=2'd1; VAR17[1:0]=2'd2; VAR56[1:0]=2'd3; end
2'd1: begin VAR27[1:0]=2'd2; VAR16[1:0]=2'd3; VAR17[1:0]=2'd0; VAR56[1:0]=2'd1; end
2'd2: begin VAR27[1:0]=2'd3; VAR16[1:0]=2'd0; VAR17[1:0]=2'd1; VAR56[1:0]=2'd2; end
2'd3: begin VAR27[1:0]=2'd1; VAR16[1:0]=2'd2; VAR17[1:0]=2'd3; VAR56[1:0]=2'd0; end
endcase
end
VAR49 : begin VAR27[1:0] = {VAR25[1], VAR42[2]};
VAR16[1:0] = {VAR25[1], ~VAR42[2]};
VAR17[1:0] = {VAR25[1], VAR42[2]};
VAR56[1:0] = {VAR25[1], ~VAR42[2]};
end
VAR9 : begin VAR27[1:0] = VAR25[1:0];
VAR16[1:0] = VAR25[1:0];
VAR17[1:0] = VAR25[1:0];
VAR56[1:0] = VAR25[1:0];
end
endcase
end
always @ begin
case (VAR52)
VAR26 : if (VAR14[0]) begin
case (VAR14[2:1])
2'd0: VAR35 = {VAR53[VAR34*4-1:0], VAR53[VAR34*8-1:VAR34*4],VAR36[VAR34*4-1:0], VAR36[VAR34*8-1:VAR34*4], VAR30[VAR34*4-1:0], VAR30[VAR34*8-1:VAR34*4], VAR12[VAR34*4-1:0], VAR12[VAR34*8-1:VAR34*4]};
2'd1: VAR35 = {VAR30[VAR34*4-1:0], VAR30[VAR34*8-1:VAR34*4],VAR12[VAR34*4-1:0], VAR12[VAR34*8-1:VAR34*4], VAR53[VAR34*4-1:0], VAR53[VAR34*8-1:VAR34*4], VAR36[VAR34*4-1:0], VAR36[VAR34*8-1:VAR34*4]};
2'd2: VAR35 = {VAR36[VAR34*4-1:0], VAR36[VAR34*8-1:VAR34*4],VAR30[VAR34*4-1:0], VAR30[VAR34*8-1:VAR34*4], VAR12[VAR34*4-1:0], VAR12[VAR34*8-1:VAR34*4], VAR53[VAR34*4-1:0], VAR53[VAR34*8-1:VAR34*4]};
2'd3: VAR35 = {VAR12[VAR34*4-1:0], VAR12[VAR34*8-1:VAR34*4],VAR53[VAR34*4-1:0], VAR53[VAR34*8-1:VAR34*4], VAR36[VAR34*4-1:0], VAR36[VAR34*8-1:VAR34*4], VAR30[VAR34*4-1:0], VAR30[VAR34*8-1:VAR34*4]};
endcase
end
else begin
case (VAR14[2:1])
2'd0: VAR35 = {VAR53, VAR36, VAR30, VAR12};
2'd1: VAR35 = {VAR30, VAR12, VAR53, VAR36};
2'd2: VAR35 = {VAR36, VAR30, VAR12, VAR53};
2'd3: VAR35 = {VAR12, VAR53, VAR36, VAR30};
endcase
end
VAR50 : case (VAR14[2:1])
2'd0: VAR35 = {VAR53, VAR36, VAR30, VAR12};
2'd1: VAR35 = {VAR30, VAR12, VAR53, VAR36};
2'd2: VAR35 = {VAR36, VAR30, VAR12, VAR53};
2'd3: VAR35 = {VAR12, VAR53, VAR36, VAR30};
endcase
VAR49 : case ({VAR14[2], VAR31[1]}) 2'd0: VAR35 = {VAR53, VAR30, VAR36, VAR12};
2'd1: VAR35 = {VAR30, VAR53, VAR12, VAR36};
2'd2: VAR35 = {VAR36, VAR12, VAR30, VAR53};
2'd3: VAR35 = {VAR12, VAR36, VAR53, VAR30};
endcase
VAR9 : case (VAR31[1:0])
2'd0: VAR35 = {VAR53, VAR30, VAR36, VAR12};
2'd1: VAR35 = {VAR36, VAR12, VAR30, VAR53};
2'd2: VAR35 = {VAR30, VAR53, VAR12, VAR36};
2'd3: VAR35 = {VAR12, VAR36, VAR53, VAR30};
endcase
endcase
end
assign VAR39 = (|VAR38) & VAR48;
assign VAR8 = VAR57 | VAR48;
assign VAR24 = VAR5 | VAR48;
assign VAR10 = VAR32 | VAR48;
assign VAR15 = VAR21 | VAR48;
assign VAR51 = VAR57 ? VAR40 : VAR23;
assign VAR6 = VAR5 ? VAR40 : VAR45;
assign VAR37 = VAR32 ? VAR40 : VAR44;
assign VAR46 = VAR21 ? VAR40 : VAR33;
VAR18 VAR41(
.clk ( clk ),
.VAR29 ( VAR8 ),
.VAR4 ( VAR57 ),
.addr ( VAR51 ),
.VAR20 ( VAR2 ),
.VAR19 ( VAR53 )
);
VAR18 VAR22(
.clk ( clk ),
.VAR29 ( VAR24 ),
.VAR4 ( VAR5 ),
.addr ( VAR6 ),
.VAR20 ( VAR13 ),
.VAR19 ( VAR36 )
);
VAR18 VAR28(
.clk ( clk ),
.VAR29 ( VAR10 ),
.VAR4 ( VAR32 ),
.addr ( VAR37 ),
.VAR20 ( VAR3 ),
.VAR19 ( VAR30 )
);
VAR18 VAR1(
.clk ( clk ),
.VAR29 ( VAR15 ),
.VAR4 ( VAR21 ),
.addr ( VAR46 ),
.VAR20 ( VAR11 ),
.VAR19 ( VAR12 )
);
endmodule
|
gpl-3.0
|
mistryalok/Zedboard
|
learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_src0_data_stream_0_V.v
| 3,013 |
module MODULE2 (
clk,
VAR5,
VAR8,
VAR25,
VAR18);
parameter VAR20 = 32'd8;
parameter VAR3 = 32'd1;
parameter VAR7 = 32'd2;
input clk;
input [VAR20-1:0] VAR5;
input VAR8;
input [VAR3-1:0] VAR25;
output [VAR20-1:0] VAR18;
reg[VAR20-1:0] VAR21 [0:VAR7-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR8)
begin
for (VAR11=0;VAR11<VAR7-1;VAR11=VAR11+1)
VAR21[VAR11+1] <= VAR21[VAR11];
VAR21[0] <= VAR5;
end
end
assign VAR18 = VAR21[VAR25];
endmodule
module MODULE1 (
clk,
reset,
VAR27,
VAR19,
VAR6,
VAR13,
VAR9,
VAR22,
VAR12,
VAR15);
parameter VAR24 = "VAR10";
parameter VAR20 = 32'd8;
parameter VAR3 = 32'd1;
parameter VAR7 = 32'd2;
input clk;
input reset;
output VAR27;
input VAR19;
input VAR6;
output[VAR20 - 1:0] VAR13;
output VAR9;
input VAR22;
input VAR12;
input[VAR20 - 1:0] VAR15;
wire[VAR3 - 1:0] VAR4 ;
wire[VAR20 - 1:0] VAR2, VAR26;
reg[VAR3:0] VAR16 = {(VAR3+1){1'b1}};
reg VAR23 = 0, VAR1 = 1;
assign VAR27 = VAR23;
assign VAR9 = VAR1;
assign VAR2 = VAR15;
assign VAR13 = VAR26;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR16 <= ~{VAR3+1{1'b0}};
VAR23 <= 1'b0;
VAR1 <= 1'b1;
end
else begin
if (((VAR6 & VAR19) == 1 & VAR23 == 1) &&
((VAR12 & VAR22) == 0 | VAR1 == 0))
begin
VAR16 <= VAR16 -1;
if (VAR16 == 0)
VAR23 <= 1'b0;
VAR1 <= 1'b1;
end
else if (((VAR6 & VAR19) == 0 | VAR23 == 0) &&
((VAR12 & VAR22) == 1 & VAR1 == 1))
begin
VAR16 <= VAR16 +1;
VAR23 <= 1'b1;
if (VAR16 == VAR7-2)
VAR1 <= 1'b0;
end
end
end
assign VAR4 = VAR16[VAR3] == 1'b0 ? VAR16[VAR3-1:0]:{VAR3{1'b0}};
assign VAR14 = (VAR12 & VAR22) & VAR1;
MODULE2
.VAR20(VAR20),
.VAR3(VAR3),
.VAR7(VAR7))
VAR17 (
.clk(clk),
.VAR5(VAR2),
.VAR8(VAR14),
.VAR25(VAR4),
.VAR18(VAR26));
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/xnor2/sky130_fd_sc_ls__xnor2_4.v
| 2,132 |
module MODULE2 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR9,
VAR8,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR3 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4,
VAR1,
VAR2
);
output VAR4;
input VAR1;
input VAR2;
supply1 VAR9;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR3 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/edfxbp/sky130_fd_sc_ms__edfxbp.pp.symbol.v
| 1,447 |
module MODULE1 (
input VAR6 ,
output VAR5 ,
output VAR2 ,
input VAR7 ,
input VAR3 ,
input VAR9 ,
input VAR1,
input VAR8,
input VAR4
);
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/de/ded_cactrl.v
| 8,036 |
module MODULE1
(
input VAR53,
input VAR28,
input VAR30, input VAR20,
input VAR35,
input VAR31,
input VAR9,
input VAR36, input VAR38, input VAR7, input [9:0] VAR18, input [8:0] VAR44, input [4:0] VAR5, input [6:0] VAR42, input VAR19, input [1:0] VAR61, input [1:0] VAR1, input [1:0] VAR58, input [1:0] VAR29, input [2:0] VAR6, input VAR41, input VAR40, input VAR16, input VAR55, input VAR2, input [2:0] VAR14, input [2:0] VAR50,
input VAR48, input VAR26, input VAR46, input VAR34,
input [4:0] VAR52,
input [4:0] VAR56,
input VAR45,
input VAR12,
input [2:0] VAR17,
input [3:0] VAR47,
input [2:0] VAR4,
input [2:0] VAR25,
input [3:0] VAR59,
input [2:0] VAR3,
input VAR37,
output VAR11,
output [2:0] VAR32,
output [3:0] VAR54,
output [2:0] VAR8,
output reg VAR22,
output [9:0] VAR10, VAR57 VAR62 output reg [2:0] VAR15
);
wire [9:0] VAR60;
reg VAR49;
reg VAR24;
reg VAR39;
wire [1:0] VAR43;
wire VAR21;
reg VAR13;
always @(posedge VAR53 or negedge VAR28) begin
if(!VAR28) VAR22 <= 1'b0;
end
else if(VAR36) VAR22 <= 1'b1;
else if(VAR26) VAR22 <= 1'b0;
end
assign VAR10[9:0] = VAR60[9:0];
always @(posedge VAR35 or negedge VAR28)
begin
if(!VAR28) VAR15 <= 3'b000;
end
else if (VAR9 & VAR37) VAR15 <= 3'b000;
else if (VAR30) VAR15 <= VAR15 + 3'b001;
end
VAR27 #
(
.VAR33 (VAR33)
)
VAR23
(
.VAR28 (VAR28),
.VAR53 (VAR53),
.VAR34 (VAR34),
.VAR38 (VAR38),
.VAR7 (VAR7),
.VAR35 (VAR35),
.VAR31 (VAR31),
.VAR9 (VAR9),
.din (VAR18),
.VAR44 (VAR44),
.VAR5 (VAR5),
.VAR42 (VAR42),
.VAR61 (VAR61),
.VAR1 (VAR1),
.VAR58 (VAR58),
.VAR29 (VAR29),
.VAR41 (VAR41),
.VAR40 (VAR40),
.VAR16 (VAR16),
.VAR6 (VAR6),
.VAR19 (VAR19),
.VAR55 (VAR55),
.VAR2 (VAR2),
.VAR14 (VAR14),
.VAR50 (VAR50),
.VAR48 (VAR48),
.VAR26 (VAR26),
.VAR46 (VAR46),
.VAR52 (VAR52),
.VAR56 (VAR56),
.VAR45 (VAR45),
.VAR12 (VAR12),
.VAR17 (VAR17),
.VAR47 (VAR47),
.VAR4 (VAR4),
.VAR25 (VAR25),
.VAR59 (VAR59),
.VAR3 (VAR3),
.VAR11 (VAR11),
.VAR32 (VAR32),
.VAR54 (VAR54),
.VAR8 (VAR8),
.VAR51 (VAR60)
);
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.behavioral.v
| 1,173 |
module MODULE1( VAR2, VAR3, VAR4 );
input VAR2, VAR3;
output VAR4;
VAR5 VAR1(.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4));
VAR5 VAR6(.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4));
|
apache-2.0
|
yipenghuang0302/csee4840_14
|
software/peripheral/synthesis/submodules/ik_swift_master_0_timing_adt.v
| 1,773 |
module MODULE1 (
input clk,
input VAR3,
input VAR6,
input [ 7: 0] VAR1,
output reg VAR8,
output reg [ 7: 0] VAR9,
input VAR7
);
reg [ 7: 0] VAR4;
reg [ 7: 0] VAR5;
reg [ 0: 0] ready;
reg VAR2;
always @(negedge VAR2) begin
end
always @* begin
VAR4 = {VAR1};
{VAR9} = VAR5;
end
always @* begin
ready[0] = VAR7;
VAR8 = VAR6;
VAR5 = VAR4;
VAR2 = ready[0];
end
endmodule
|
mit
|
VerticalResearchGroup/miaow
|
src/verilog/rtl/issue/alu_issue_logic.v
| 6,708 |
module MODULE1
(
VAR41, VAR7, VAR3,
VAR23, VAR2, VAR15,
VAR19, VAR10, VAR26,
VAR35, VAR1, VAR25,
clk, rst, VAR36, VAR18, VAR6,
VAR12, VAR5, VAR40,
VAR4, VAR14, VAR11,
VAR17, VAR16, VAR24, VAR22,
VAR9, VAR21, VAR38, VAR39,
VAR33
);
input clk,rst;
input VAR36, VAR18,
VAR6,VAR12,
VAR5,VAR40,
VAR4,VAR14,
VAR11,VAR17;
input VAR16, VAR24, VAR22 ,VAR9;
input [VAR20-1:0] VAR21, VAR38, VAR39, VAR33;
output VAR41;
output VAR7, VAR3,
VAR23, VAR2,
VAR15, VAR19,
VAR10, VAR26,
VAR35, VAR1;
output [VAR20-1:0] VAR25;
reg [VAR20-1:0] VAR25;
wire [1:0] VAR37;
reg [1:0] VAR32;
VAR31 #(2) VAR13(.out(VAR37), .in(VAR32),
.VAR29(VAR41), .clk(clk), .rst(rst));
reg VAR41;
reg VAR7, VAR3,
VAR23, VAR2,
VAR15, VAR19,
VAR10, VAR26,
VAR35, VAR1;
reg [3:0] VAR27, VAR34;
reg [3:0] VAR8, VAR30;
always @(*) begin
VAR8 <= { (VAR17 | VAR11 | VAR14 |
VAR4) & VAR24,
(VAR40 | VAR5 | VAR12 |
VAR6) & VAR22,
VAR36 & VAR16,
VAR18 & VAR9 };
case( VAR37 )
2'b00 : VAR27 <= VAR8;
2'b01 : VAR27 <= {VAR8[0], VAR8[3:1]};
2'b10 : VAR27 <= {VAR8[1:0], VAR8[3:2]};
2'b11 : VAR27 <= {VAR8[2:0], VAR8[3]};
endcase
casex( VAR27 )
4'b1??? : begin
VAR34 <= VAR27 & 4'b1000;
VAR32 <= 2'h3;
end
4'b01?? : begin
VAR34 <= VAR27 & 4'b0100;
VAR32 <= 2'h2;
end
4'b001? : begin
VAR34 <= VAR27 & 4'b0010;
VAR32 <= 2'h1;
end
4'b0001 : begin
VAR34 <= VAR27 & 4'b0001;
VAR32 <= 2'h0;
end
default : begin
VAR34 <= 4'b0000;
VAR32 <= VAR37;
end
endcase
case( VAR37 )
2'b00 : VAR30 <= VAR34;
2'b01 : VAR30 <= {VAR34[2:0], VAR34[3]};
2'b10 : VAR30 <= {VAR34[1:0], VAR34[3:2]};
2'b11 : VAR30 <= {VAR34[0], VAR34[3:1]};
endcase
casex( { VAR17,VAR11,VAR14,VAR4} )
4'b1??? : begin
VAR7 <= VAR30[3];
VAR3 <= 1'b0;
VAR23 <= 1'b0;
VAR2 <= 1'b0;
end
4'b01?? : begin
VAR7 <= 1'b0;
VAR3 <= VAR30[3];
VAR23 <= 1'b0;
VAR2 <= 1'b0;
end
4'b001? : begin
VAR7 <= 1'b0;
VAR3 <= 1'b0;
VAR23 <= VAR30[3];
VAR2 <= 1'b0;
end
4'b0001 : begin
VAR7 <= 1'b0;
VAR3 <= 1'b0;
VAR23 <= 1'b0;
VAR2 <= VAR30[3];
end
default : begin
VAR7 <= 1'b0;
VAR3 <= 1'b0;
VAR23 <= 1'b0;
VAR2 <= 1'b0;
end
endcase
casex( { VAR40,VAR5,VAR12,VAR6} )
4'b1??? : begin
VAR15 <= VAR30[2];
VAR19 <= 1'b0;
VAR10 <= 1'b0;
VAR26 <= 1'b0;
end
4'b01?? : begin
VAR15 <= 1'b0;
VAR19 <= VAR30[2];
VAR10 <= 1'b0;
VAR26 <= 1'b0;
end
4'b001? : begin
VAR15 <= 1'b0;
VAR19 <= 1'b0;
VAR10 <= VAR30[2];
VAR26 <= 1'b0;
end
4'b0001 : begin
VAR15 <= 1'b0;
VAR19 <= 1'b0;
VAR10 <= 1'b0;
VAR26 <= VAR30[2];
end
default : begin
VAR15 <= 1'b0;
VAR19 <= 1'b0;
VAR10 <= 1'b0;
VAR26 <= 1'b0;
end
endcase
VAR35 <= VAR30[1];
VAR1 <= VAR30[0];
case( VAR30 )
4'b1000 : VAR25 <= VAR38;
4'b0100 : VAR25 <= VAR39;
4'b0010 : VAR25 <= VAR21;
4'b0001 : VAR25 <= VAR33;
default : VAR25 <= {VAR20{1'VAR28}};
endcase
VAR41 <= |VAR30;
end
endmodule
|
bsd-3-clause
|
olofk/oh
|
xilibs/hdl/PLLE2_ADV.v
| 5,488 |
module MODULE1 #(
parameter VAR16 = "VAR52",
parameter integer VAR40 = 5,
parameter real VAR39 = 0.000,
parameter real VAR62 = 0.000,
parameter real VAR46 = 0.000,
parameter integer VAR49 = 1,
parameter real VAR15 = 0.500,
parameter real VAR11 = 0.000,
parameter integer VAR12 = 1,
parameter real VAR47 = 0.500,
parameter real VAR59 = 0.000,
parameter integer VAR25 = 1,
parameter real VAR33 = 0.500,
parameter real VAR36 = 0.000,
parameter integer VAR54 = 1,
parameter real VAR31 = 0.500,
parameter real VAR53 = 0.000,
parameter integer VAR6 = 1,
parameter real VAR43 = 0.500,
parameter real VAR56 = 0.000,
parameter integer VAR64 = 1,
parameter real VAR21 = 0.500,
parameter real VAR22 = 0.000,
parameter VAR57 = "VAR35",
parameter integer VAR3 = 1,
parameter [0:0] VAR38 = 1'b0,
parameter [0:0] VAR42 = 1'b0,
parameter [0:0] VAR8 = 1'b0,
parameter real VAR60 = 0.010,
parameter real VAR45 = 0.010,
parameter VAR34 = "VAR37"
)(
output VAR30,
output VAR5,
output VAR51,
output VAR48,
output VAR17,
output VAR2,
output [15:0] VAR20,
output VAR32,
output VAR7,
output VAR55,
input VAR63,
input VAR19,
input VAR9,
input VAR23,
input [6:0] VAR14,
input VAR10,
input VAR27,
input [15:0] VAR29,
input VAR41,
input VAR1,
input VAR58
);
localparam real VAR44 = (VAR62 * VAR3) / VAR40;
localparam real VAR18 = VAR44 * VAR49 * (VAR11/360);
localparam real VAR50 = VAR44 * VAR12 * (VAR59/360);
localparam real VAR28 = VAR44 * VAR25 * (VAR36/360);
localparam real VAR13 = VAR44 * VAR54 * (VAR53/360);
localparam real VAR61 = VAR44 * VAR6 * (VAR56/360);
localparam real VAR4 = VAR44 * VAR64 * (VAR22/360);
localparam VAR26 = VAR40 / VAR3;
reg VAR24;
begin
begin
begin
begin
begin
|
gpl-3.0
|
rkrajnc/minimig-mist
|
rtl/minimig/denise_colortable.v
| 2,282 |
module MODULE1
(
input wire clk, input wire VAR28, input wire [ 9-1:1] VAR8, input wire [ 12-1:0] VAR23, input wire [ 8-1:0] select, input wire [ 8-1:0] VAR22, input wire [ 3-1:0] VAR24, input wire VAR4, input wire VAR3, output reg [ 24-1:0] VAR20 );
parameter VAR10 = 9'h180;
wire [ 8-1:0] VAR9 = select;
wire [ 8-1:0] VAR7 = {VAR24[2:0], VAR8[5:1]};
wire VAR21 = (VAR8[8:6] == VAR10[8:6]) && VAR28;
wire [32-1:0] VAR18 = {4'b0, VAR23[11:0], 4'b0, VAR23[11:0]};
wire [ 4-1:0] VAR2 = VAR4 ? 4'b0011 : 4'b1111;
wire [ 8-1:0] VAR15 = VAR3 ? {3'b000, VAR9[4:0]} : VAR9;
wire [32-1:0] VAR27;
reg VAR14;
VAR26 VAR5
(
.VAR6 (clk ),
.enable (1'b1 ),
.VAR16 (VAR7 ),
.VAR21 (VAR21 ),
.VAR19 (VAR2 ),
.VAR11 (VAR18 ),
.VAR12 (VAR15 ),
.VAR25 (VAR27 )
);
always @ (posedge clk) begin
VAR14 <= VAR9[5];
end
wire [12-1:0] VAR13 = VAR27[12-1+16:0+16];
wire [12-1:0] VAR17 = VAR27[12-1+ 0:0+ 0];
wire [24-1:0] VAR1 = {VAR13[11:8], VAR17[11:8], VAR13[7:4], VAR17[7:4], VAR13[3:0], VAR17[3:0]};
always @ (*) begin
if (VAR14 && VAR3) VAR20 = {1'b0,VAR1[23:17],1'b0,VAR1[15:9],1'b0,VAR1[7:1]};
end
else VAR20 = VAR1;
end
endmodule
|
gpl-3.0
|
ptracton/vscale_soc
|
rtl/wb_intercon-1.0/rtl/verilog/wb_mux.v
| 6,154 |
module MODULE1
parameter [VAR22*VAR23-1:0] VAR21 = 0)
(input VAR39,
input VAR25,
input [VAR23-1:0] VAR18,
input [VAR4-1:0] VAR28,
input [3:0] VAR24,
input VAR14,
input VAR20,
input VAR35,
input [2:0] VAR26,
input [1:0] VAR17,
output [VAR4-1:0] VAR9,
output VAR38,
output VAR2,
output VAR27,
output [VAR22*VAR23-1:0] VAR10,
output [VAR22*VAR4-1:0] VAR19,
output [VAR22*4-1:0] VAR3,
output [VAR22-1:0] VAR5,
output [VAR22-1:0] VAR29,
output [VAR22-1:0] VAR13,
output [VAR22*3-1:0] VAR1,
output [VAR22*2-1:0] VAR33,
input [VAR22*VAR4-1:0] VAR6,
input [VAR22-1:0] VAR36,
input [VAR22-1:0] VAR32,
input [VAR22-1:0] VAR30);
localparam VAR12 = VAR22 > 1 ? VAR11(VAR22) : 1;
reg VAR16;
wire [VAR12-1:0] VAR31;
wire [VAR22-1:0] VAR34;
genvar VAR8;
generate
for(VAR8=0; VAR8<VAR22 ; VAR8=VAR8+1) begin : VAR37
assign VAR34[VAR8] = (VAR18 & VAR21[VAR8*VAR23+:VAR23]) == VAR15[VAR8*VAR23+:VAR23];
end
endgenerate
assign VAR31 = VAR7(VAR34, VAR22);
always @(posedge VAR39)
VAR16 <= VAR20 & !(|VAR34);
assign VAR10 = {VAR22{VAR18}};
assign VAR19 = {VAR22{VAR28}};
assign VAR3 = {VAR22{VAR24}};
assign VAR5 = {VAR22{VAR14}};
assign VAR29 = VAR34 & (VAR20 << VAR31);
assign VAR13 = {VAR22{VAR35}};
assign VAR1 = {VAR22{VAR26}};
assign VAR33 = {VAR22{VAR17}};
assign VAR9 = VAR6[VAR31*VAR4+:VAR4];
assign VAR38 = VAR36[VAR31];
assign VAR2 = VAR32[VAR31] | VAR16;
assign VAR27 = VAR30[VAR31];
endmodule
|
mit
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N16_R2_P4_syn.v
| 4,336 |
module MODULE1 ( VAR15, VAR68, VAR21 );
input [15:0] VAR15;
input [15:0] VAR68;
output [16:0] VAR21;
wire VAR117, VAR124, VAR78, VAR44, VAR90,
VAR135, VAR88, VAR89, VAR6, VAR103, VAR139, VAR42, VAR63, VAR57, VAR82, VAR71, VAR104, VAR29, VAR111, VAR74,
VAR105, VAR128, VAR112, VAR76, VAR108, VAR49, VAR59, VAR35, VAR23, VAR43, VAR94, VAR109, VAR95, VAR86,
VAR34, VAR55, VAR142, VAR122, VAR98, VAR116, VAR28, VAR12, VAR47, VAR54, VAR141, VAR32;
VAR22 VAR121 ( .VAR132(VAR68[1]), .VAR8(VAR15[1]), .VAR13(VAR117), .VAR19(
VAR124), .VAR50(VAR21[1]) );
VAR22 VAR75 ( .VAR132(VAR68[2]), .VAR8(VAR15[2]), .VAR13(VAR124), .VAR19(
VAR78), .VAR50(VAR21[2]) );
VAR22 VAR65 ( .VAR132(VAR68[3]), .VAR8(VAR15[3]), .VAR13(VAR78), .VAR19(
VAR44), .VAR50(VAR21[3]) );
VAR22 VAR85 ( .VAR132(VAR68[4]), .VAR8(VAR15[4]), .VAR13(VAR44), .VAR19(
VAR90), .VAR50(VAR21[4]) );
VAR52 VAR101 ( .VAR92(VAR42), .VAR69(VAR139), .VAR3(VAR90), .VAR30(VAR6) );
VAR52 VAR99 ( .VAR92(VAR43), .VAR69(VAR23), .VAR3(VAR122), .VAR30(VAR55) );
VAR37 VAR33 ( .VAR132(VAR68[15]), .VAR8(VAR15[15]), .VAR136(VAR88), .VAR19(VAR21[16]), .VAR50(VAR21[15])
);
VAR96 VAR113 ( .VAR92(VAR95), .VAR69(VAR142), .VAR3(VAR109), .VAR30(VAR94) );
VAR96 VAR110 ( .VAR92(VAR59), .VAR69(VAR49), .VAR3(VAR76), .VAR30(VAR112) );
VAR96 VAR77 ( .VAR92(VAR111), .VAR69(VAR29), .VAR3(VAR104), .VAR30(VAR71) );
VAR37 VAR40 ( .VAR132(VAR68[14]), .VAR8(VAR15[14]), .VAR136(VAR89), .VAR19(VAR88), .VAR50(VAR21[14]) );
VAR96 VAR64 ( .VAR92(VAR128), .VAR69(VAR105), .VAR3(VAR43), .VAR30(VAR34) );
VAR96 VAR51 ( .VAR92(VAR82), .VAR69(VAR57), .VAR3(VAR128), .VAR30(VAR86) );
VAR107 VAR36 ( .VAR92(VAR142), .VAR69(VAR116), .VAR106(VAR98), .VAR3(VAR108), .VAR30(VAR28) );
VAR61 VAR62 ( .VAR132(VAR68[5]), .VAR8(VAR15[5]), .VAR30(VAR139) );
VAR79 VAR53 ( .VAR132(VAR68[5]), .VAR8(VAR15[5]), .VAR30(VAR42) );
VAR61 VAR130 ( .VAR132(VAR68[7]), .VAR8(VAR15[7]), .VAR30(VAR29) );
VAR79 VAR4 ( .VAR132(VAR68[7]), .VAR8(VAR15[7]), .VAR30(VAR111) );
VAR61 VAR125 ( .VAR132(VAR68[9]), .VAR8(VAR15[9]), .VAR30(VAR49) );
VAR79 VAR97 ( .VAR132(VAR68[9]), .VAR8(VAR15[9]), .VAR30(VAR59) );
VAR56 VAR114 ( .VAR132(VAR15[10]), .VAR30(VAR98) );
VAR56 VAR67 ( .VAR132(VAR68[10]), .VAR30(VAR116) );
VAR61 VAR5 ( .VAR132(VAR68[11]), .VAR8(VAR15[11]), .VAR30(VAR142) );
VAR79 VAR102 ( .VAR132(VAR68[0]), .VAR8(VAR15[0]), .VAR30(VAR117) );
VAR119 VAR80 ( .VAR92(VAR68[3]), .VAR69(VAR15[3]), .VAR3(VAR15[2]), .VAR72(VAR68[2]), .VAR30(VAR103) );
VAR56 VAR7 ( .VAR132(VAR139), .VAR30(VAR63) );
VAR56 VAR87 ( .VAR132(VAR29), .VAR30(VAR74) );
VAR56 VAR137 ( .VAR132(VAR49), .VAR30(VAR35) );
VAR10 VAR127 ( .VAR92(VAR42), .VAR69(VAR90), .VAR106(VAR139), .VAR3(VAR6), .VAR30(VAR21[5]) );
VAR10 VAR131 ( .VAR92(VAR111), .VAR69(VAR104), .VAR106(VAR29), .VAR3(VAR71), .VAR30(VAR21[7]) );
VAR10 VAR81 ( .VAR92(VAR59), .VAR69(VAR76), .VAR106(VAR49), .VAR3(VAR112), .VAR30(VAR21[9]) );
VAR10 VAR100 ( .VAR92(VAR95), .VAR69(VAR109), .VAR106(VAR142), .VAR3(VAR94), .VAR30(VAR21[11]) );
VAR38 VAR46 ( .VAR132(VAR32), .VAR8(VAR141), .VAR30(VAR21[13]) );
VAR48 VAR83 ( .VAR3(VAR47), .VAR72(VAR135), .VAR18(VAR68[13]), .VAR11(VAR15[13]), .VAR30(VAR89) );
VAR84 VAR17 ( .VAR132(VAR12), .VAR8(VAR28), .VAR30(VAR54) );
VAR91 VAR2 ( .VAR92(VAR68[12]), .VAR69(VAR15[12]), .VAR3(VAR68[12]), .VAR72(VAR28), .VAR70(
VAR15[12]), .VAR66(VAR28), .VAR30(VAR135) );
VAR56 VAR140 ( .VAR132(VAR108), .VAR30(VAR95) );
VAR14 VAR24 ( .VAR132(VAR68[13]), .VAR8(VAR15[13]), .VAR30(VAR47) );
VAR41 VAR39 ( .VAR132(VAR68[11]), .VAR8(VAR15[11]), .VAR30(VAR108) );
VAR52 VAR123 ( .VAR92(VAR68[3]), .VAR69(VAR15[3]), .VAR3(VAR103), .VAR30(VAR82) );
VAR60 VAR9 ( .VAR92(VAR68[5]), .VAR69(VAR15[5]), .VAR3(VAR68[4]), .VAR72(VAR15[4]), .VAR30(VAR57)
);
VAR25 VAR134 ( .VAR92(VAR68[4]), .VAR69(VAR15[4]), .VAR106(VAR63), .VAR3(VAR42), .VAR30(VAR128) );
VAR60 VAR126 ( .VAR92(VAR68[7]), .VAR69(VAR15[7]), .VAR3(VAR68[6]), .VAR72(VAR15[6]), .VAR30(VAR105)
);
VAR25 VAR20 ( .VAR92(VAR68[6]), .VAR69(VAR15[6]), .VAR106(VAR74), .VAR3(VAR111), .VAR30(VAR43) );
VAR60 VAR120 ( .VAR92(VAR68[9]), .VAR69(VAR15[9]), .VAR3(VAR68[8]), .VAR72(VAR15[8]), .VAR30(VAR23)
);
VAR25 VAR138 ( .VAR92(VAR68[8]), .VAR69(VAR15[8]), .VAR106(VAR35), .VAR3(VAR59), .VAR30(VAR122) );
VAR133 VAR58 ( .VAR18(VAR68[0]), .VAR11(VAR15[0]), .VAR3(VAR117), .VAR30(VAR21[0])
);
VAR22 VAR27 ( .VAR132(VAR68[6]), .VAR8(VAR15[6]), .VAR13(VAR86), .VAR19(VAR104), .VAR50(VAR21[6]) );
VAR22 VAR73 ( .VAR132(VAR68[8]), .VAR8(VAR15[8]), .VAR13(VAR34), .VAR19(VAR76), .VAR50(VAR21[8]) );
VAR22 VAR93 ( .VAR132(VAR68[10]), .VAR8(VAR15[10]), .VAR13(VAR55), .VAR19(VAR109), .VAR50(VAR21[10]) );
VAR16 VAR26 ( .VAR92(VAR116), .VAR69(VAR98), .VAR3(VAR122), .VAR70(VAR142), .VAR30(VAR12) );
VAR45 VAR118 ( .VAR92(VAR15[13]), .VAR69(VAR68[13]), .VAR3(VAR47), .VAR30(VAR32) );
VAR22 VAR129 ( .VAR132(VAR68[12]), .VAR8(VAR15[12]), .VAR13(VAR54), .VAR19(VAR141), .VAR50(VAR21[12]) );
VAR115 ("VAR31.VAR1");
endmodule
|
gpl-3.0
|
asicguy/gplgpu
|
hdl/de/ded_ca_top.v
| 4,015 |
module MODULE1
(
input VAR12,
input VAR4,
input VAR13,
input VAR11,
input [4:0] VAR9,
input [(VAR3*8)-1:0] VAR7,
output [31:0] VAR10,
output [4:0] VAR1,
output [4:0] VAR6,
output [4:0] VAR14
);
wire [2:0] VAR5;
assign VAR5 = VAR8 + 3'h1;
assign VAR10 = VAR7[VAR9[1:0]*32 +: 32];
assign VAR2[0] = VAR11 & (VAR9[1:0] == 2'd0);
assign VAR2[1] = VAR11 & (VAR9[1:0] == 2'd1);
assign VAR2[2] = VAR11 & (VAR9[1:0] == 2'd2);
assign VAR2[3] = VAR11 & (VAR9[1:0] == 2'd3);
assign VAR1 = {2'b0, VAR9[4:2]};
assign VAR6 = (VAR4) ? {2'b0, VAR15} : {2'b0, VAR8};
assign VAR14 = (VAR4) ? {2'b0, VAR15} : {2'b0, VAR5};
wire [3:0] VAR5;
assign VAR5 = VAR8 + 1;
assign VAR10 = VAR7[VAR9[0]*32 +: 32];
assign VAR2[0] = VAR11 & (VAR9[0] == 1'b0);
assign VAR2[1] = VAR11 & (VAR9[0] == 1'b1);
assign VAR1 = {1'b0, VAR9[4:1]};
assign VAR6 = (VAR4) ? {1'b0, VAR15} : {1'b0, VAR8};
assign VAR14 = (VAR4) ? {1'b0, VAR15} : {1'b0, VAR5};
wire [4:0] VAR5;
assign VAR5 = VAR8 + 1;
assign VAR10 = VAR7[31:0];
assign VAR2 = VAR11;
assign VAR1 = VAR9[4:0];
assign VAR6 = (VAR4) ? VAR15 : VAR8;
assign VAR14 = (VAR4) ? VAR15 : VAR5;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/or2b/sky130_fd_sc_hs__or2b.functional.pp.v
| 1,823 |
module MODULE1 (
VAR8,
VAR3,
VAR5 ,
VAR9 ,
VAR13
);
input VAR8;
input VAR3;
output VAR5 ;
input VAR9 ;
input VAR13 ;
wire VAR5 VAR10 ;
wire VAR1 ;
wire VAR12;
not VAR4 (VAR10 , VAR13 );
or VAR2 (VAR1 , VAR10, VAR9 );
VAR7 VAR6 (VAR12, VAR1, VAR8, VAR3);
buf VAR11 (VAR5 , VAR12 );
endmodule
|
apache-2.0
|
cpulabs/mist1032sa
|
src/core/fetch/fetch.v
| 6,862 |
module MODULE1(
input wire VAR50,
input wire VAR43,
input wire VAR10,
input wire VAR14,
input wire VAR25,
input wire [31:0] VAR40,
input wire VAR47,
input wire VAR46,
input wire VAR33,
input wire [5:0] VAR28,
input wire [31:0] VAR6,
input wire VAR35,
input wire [5:0] VAR49,
input wire [31:0] VAR18,
output wire VAR13,
output wire VAR34,
output wire [31:0] VAR30,
input wire VAR29,
output wire VAR45,
output wire [5:0] VAR19,
output wire [31:0] VAR7,
output wire VAR2,
output wire [5:0] VAR4,
output wire [31:0] VAR12,
output wire [31:0] VAR26,
input wire VAR48
);
wire VAR3;
wire [31:0] VAR16;
wire VAR20;
reg [31:0] VAR17;
reg VAR27;
reg [1:0] VAR44;
reg [31:0] VAR36;
reg VAR11;
reg [5:0] VAR38;
reg [31:0] VAR1;
reg VAR31;
reg [5:0] VAR37;
reg [31:0] VAR41;
reg VAR15;
VAR22 #(32, 8, 3) VAR42(
.VAR50(VAR50), .VAR43(VAR43),
.VAR32(VAR47),
.VAR5(),
.VAR9(!VAR14 && VAR27 && !VAR3 && !VAR29 && !VAR46),
.VAR8(VAR17),
.VAR21(VAR3),
.VAR39(VAR33 || VAR35),
.VAR23(VAR16),
.VAR24()
);
assign VAR20 = VAR48 || VAR3 || VAR29; assign VAR13 = (VAR10)? 1'b0 : VAR48;
assign VAR34 = !VAR14 && VAR27 && !VAR3 && !VAR29 && !VAR46;
assign VAR30 = VAR17[31:0];
always@(posedge VAR50 or negedge VAR43)begin
if(!VAR43)begin
VAR17 <= {32{1'b0}};
VAR27 <= 1'b0;
VAR44 <= 2'b00;
end
else if(VAR14)begin VAR27 <= 1'b0;
VAR44 <= 2'h2;
end
else begin
case(VAR44)
2'h0 : begin
VAR27 <= 1'b1;
VAR44 <= 2'h1;
VAR17 <= 32'h00000000;
end
2'h1 : begin
if(!VAR14 && !VAR3 && !VAR29 && !VAR46)begin
VAR17 <= (VAR17[2])? VAR17 + 32'h4 : VAR17 + 32'h8;
VAR27 <= 1'b1;
end
end
2'h2:
begin
if(VAR25 && VAR47)begin
VAR17 <= {VAR40[31:3], 3'h0}; VAR27 <= 1'b1;
VAR44 <= 2'h1;
end
end
default :
begin
VAR17 <= VAR17;
end
endcase
end
end
always@(posedge VAR50 or negedge VAR43)begin
if(!VAR43)begin
VAR36 <= {32{1'b0}};
VAR11 <= 1'b0;
VAR38 <= 6'h0;
VAR1 <= {32{1'b0}};
VAR31 <= 1'b0;
VAR37 <= 6'h0;
VAR41 <= {32{1'b0}};
end
else if(VAR14)begin
VAR36 <= {32{1'b0}};
VAR11 <= 1'b0;
VAR38 <= 6'h0;
VAR1 <= {32{1'b0}};
VAR31 <= 1'b0;
VAR37 <= 6'h0;
VAR41 <= {32{1'b0}};
end
else begin
if(!VAR48)begin
VAR36 <= (VAR15)? VAR18 : VAR6;
VAR11 <= !VAR10 && VAR33;
VAR38 <= (VAR15)? VAR49 : VAR28;
VAR1 <= VAR18;
VAR31 <= (VAR15)? 1'b0 : (!VAR10 && VAR35);
VAR37 <= VAR49;
VAR41 <= (VAR15)? VAR16 + 32'h8 : VAR16 + 32'h4;
end
end
end
always@(posedge VAR50 or negedge VAR43)begin
if(!VAR43)begin
VAR15 <= 1'b0;
end
else begin
if(VAR25 && VAR40[2])begin
VAR15 <= 1'b1;
end
else begin
if(!VAR48)begin
if(!VAR10 && (VAR33 || VAR35))begin
VAR15 <= 1'b0;
end
end
end
end
end
assign VAR7 = VAR36;
assign VAR45 = (!VAR48)? VAR11 : 1'b0;
assign VAR19 = VAR38;
assign VAR12 = VAR1;
assign VAR2 = (!VAR48)? VAR31 : 1'b0;
assign VAR4 = VAR37;
assign VAR26 = VAR41;
endmodule
|
bsd-2-clause
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
bin_Erosion_Operation/ip/Erosion/acl_fp_sincos_double.v
| 1,417 |
module MODULE1(VAR3, VAR10, enable, VAR15, VAR5, VAR12);
input VAR3, VAR10, enable;
input [63:0] VAR15;
output [63:0] VAR5; output [63:0] VAR12;
VAR11 VAR14(
.VAR9(1'b1),
.VAR7(8'd0),
.VAR6(VAR15),
.en(enable),
.VAR2(),
.VAR4(),
.VAR8(VAR5),
.VAR1(VAR12),
.clk(VAR3),
.VAR13(~VAR10));
endmodule
|
mit
|
BoolLi/Pollard-s-p-1-algorithm
|
exponent_finder.v
| 1,532 |
module MODULE1(
input clk,
input [63:0] VAR4,
input VAR6,
input [8:0] VAR1,
output reg [7:0] VAR8,
output reg ready
);
reg [7:0] VAR7;
reg VAR5;
reg [10:0] VAR2;
reg [10:0] VAR3;
|
mit
|
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/verilog/phsaligner.v
| 8,662 |
module MODULE1 # (
parameter VAR9 = 3, parameter VAR26 = 7, parameter VAR7 = 12 )
(
input wire rst,
input wire clk,
input wire [9:0] VAR15,
input wire [9:0] VAR25, output reg VAR1,
output reg VAR11,
output reg VAR6 );
reg VAR30, VAR20;
reg VAR22;
always @ (posedge clk) begin
VAR30 <=(VAR25 == VAR15);
VAR20 <=VAR30;
VAR22 <=!VAR20 & VAR30;
end
reg [(VAR7-1):0] VAR12;
reg VAR10;
always @ (posedge clk) begin
if (VAR10)
VAR12 <={VAR7{1'b0}};
end
else
VAR12 <=VAR12 + 1'b1;
end
reg VAR5;
always @ (posedge clk) begin
VAR5 <=(VAR12 == {VAR7{1'b1}});
end
reg [(VAR26-1):0] VAR4;
reg VAR19;
always @ (posedge clk) begin
if(VAR19)
VAR4 <={VAR26{1'b0}};
end
else
VAR4 <=VAR4 + 1'b1;
end
reg VAR21;
always @ (posedge clk) begin
VAR21 <=(VAR4 == {VAR26{1'b1}});
end
parameter VAR29 = 6'b1 << 0;
parameter VAR16 = 6'b1 << 1; parameter VAR17 = 6'b1 << 2;
parameter VAR13 = 6'b1 << 3; parameter VAR14 = 6'b1 << 4;
parameter VAR2 = 6'b1 << 5; parameter VAR8 = 6;
reg [(VAR8-1):0] VAR28 = {{(VAR8-1){1'b0}}, 1'b1}; reg [(VAR8-1):0] VAR24;
reg [8*20:1] VAR27 = "VAR29 ";
always @(VAR28) begin
if (VAR28 == VAR29 ) VAR27 <= "VAR29 ";
end
else if (VAR28 == VAR16 ) VAR27 <= "VAR16 ";
else if (VAR28 == VAR17 ) VAR27 <= "VAR17 ";
else if (VAR28 == VAR13 ) VAR27 <= "VAR13 ";
else if (VAR28 == VAR14 ) VAR27 <= "VAR14 ";
else VAR27 <= "VAR2 ";
end
always @ (posedge clk or posedge rst) begin
if (rst)
VAR28 <= VAR29;
end
else
VAR28 <=VAR24;
end
parameter VAR18 = 1;
reg [(VAR18-1):0] VAR3 = {VAR18{1'b0}};
always @ (*) begin
case (VAR28) VAR29: begin
VAR24 = (VAR5) ? VAR16 : VAR29;
end
VAR16: begin
if(VAR22)
VAR24 = VAR13;
end
else
VAR24 = (VAR5) ? VAR17 : VAR16;
end
VAR17: begin
VAR24 = VAR16;
end
VAR13: begin
if(VAR30)
VAR24 = (VAR21) ? VAR14 : VAR13;
end
else
VAR24 = VAR16;
end
VAR14: begin
VAR24 = (VAR3 == {VAR18{1'b1}}) ? VAR2 : VAR16;
end
VAR2: begin
VAR24 = VAR2; end
endcase
end
reg [2:0] VAR23;
always @ (posedge clk or posedge rst) begin
if(rst) begin
VAR6 <=1'b0; VAR11 <=1'b0;
VAR10 <=1'b1; VAR19 <=1'b1;
VAR11 <=1'b0;
VAR23 <=3'h0;
VAR1 <=1'b0;
VAR3 <={VAR18{1'b0}};
end else begin
case (VAR28) VAR29: begin
VAR10 <=1'b0;
VAR19 <=1'b1;
VAR11 <=1'b0;
VAR6 <=1'b0;
VAR11 <=1'b0;
VAR23 <=3'h0;
VAR1 <=1'b0;
VAR3 <={VAR18{1'b0}};
end
VAR16: begin
VAR10 <=1'b0;
VAR19 <=1'b1;
VAR11 <=1'b0;
VAR6 <=1'b0;
end
VAR17: begin
VAR10 <=1'b1;
VAR11 <=1'b1;
VAR23 <=VAR23 + 1'b1;
VAR1 <=VAR23[2]; end
VAR13: begin
VAR10 <=1'b0;
VAR19 <=1'b0;
end
VAR14: begin
VAR3 <=VAR3 + 1'b1;
end
VAR2: begin
VAR6 <=1'b1;
end
endcase
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/or2/sky130_fd_sc_ls__or2_2.v
| 2,075 |
module MODULE1 (
VAR2 ,
VAR1 ,
VAR7 ,
VAR8,
VAR5,
VAR3 ,
VAR9
);
output VAR2 ;
input VAR1 ;
input VAR7 ;
input VAR8;
input VAR5;
input VAR3 ;
input VAR9 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR2,
VAR1,
VAR7
);
output VAR2;
input VAR1;
input VAR7;
supply1 VAR8;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR9 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
markusC64/1541ultimate2
|
fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_rdata_path.v
| 51,917 |
module MODULE1
parameter
VAR194 = 8,
VAR89 = 2,
VAR280 = 3, VAR257 = 3,
VAR155 = 32,
VAR32 = 5,
VAR40 = 2,
VAR207 = 3,
VAR244 = 13,
VAR243 = 10,
VAR73 = 4, VAR68 = "VAR138", VAR13 = 2,
VAR241 = 3,
VAR229 = 2,
VAR251 = 1,
VAR277 = 8,
VAR74 = 3,
VAR24 = 1,
VAR131 = 1,
VAR268 = 1,
VAR183 = 5,
VAR196 = 2,
VAR118 = 9,
VAR41 = 12,
VAR108 = 3,
VAR9 = 2,
VAR215 = 1 )
(
VAR88,
VAR1,
VAR175,
VAR46,
VAR191,
VAR59,
VAR233,
VAR123,
VAR4,
VAR23,
VAR170,
VAR172,
VAR202,
VAR238,
VAR86,
VAR148,
VAR159,
VAR72,
VAR206,
VAR50,
VAR14, VAR37,
VAR216,
VAR269,
VAR189,
VAR158,
VAR106,
VAR48,
VAR232,
VAR261,
VAR223,
VAR161,
VAR130,
VAR134,
VAR110,
VAR253,
VAR79,
VAR260,
VAR193,
VAR114,
VAR100,
VAR33,
VAR15,
VAR219,
VAR218,
VAR210,
VAR28,
VAR141,
VAR177,
VAR117,
VAR98,
VAR45,
VAR91,
VAR34
);
localparam VAR136 = 0; localparam VAR64 = 1;
localparam VAR182 = 1;
localparam VAR97 = VAR40 + VAR207 + VAR244 + VAR243 + VAR257 + VAR89 + VAR280 + VAR64 + VAR182;
localparam VAR3 = VAR40 + VAR207 + VAR244 + VAR243 + VAR89 + VAR257;
localparam VAR19 = VAR89+VAR257;
localparam integer VAR57 = 2**VAR280;
localparam VAR78 = 1;
localparam VAR12 = VAR194 + VAR78;
localparam VAR122 = 2**VAR73;
localparam VAR99 = 8;
localparam VAR270 = 12;
localparam VAR227 = 2;
localparam VAR31 = 1;
localparam VAR142 = VAR243;
localparam VAR173 = VAR244;
localparam VAR90 = VAR207;
localparam VAR133 = VAR40;
localparam VAR52 = VAR190 (VAR229);
localparam VAR56 = VAR190 (VAR155);
integer VAR230,VAR127,VAR156,VAR154;
input VAR88;
input VAR1;
input [VAR74- 1:0] VAR175;
input [VAR24-1:0] VAR46;
input [VAR131-1:0] VAR191;
input [VAR268-1:0] VAR59;
input [VAR183-1:0] VAR233;
input [VAR196 - 1 : 0] VAR123;
input [VAR118 - 1 : 0] VAR4;
input [VAR41 - 1 : 0] VAR23;
input [VAR108 - 1 : 0] VAR170;
input [VAR9 - 1 : 0] VAR172;
output VAR202;
output [VAR280-1:0] VAR238;
input VAR86;
input VAR148;
input VAR159;
input VAR72;
input [VAR89-1:0] VAR206;
input [VAR257-1:0] VAR50;
output VAR14;
output [VAR194-1:0] VAR37;
output VAR216;
output [VAR257-1:0] VAR269;
input [VAR13-1:0] VAR189;
input [VAR13-1:0] VAR130;
input [VAR13-1:0] VAR134;
input [(VAR13*VAR40 ) -1:0] VAR158;
input [(VAR13*VAR207 ) -1:0] VAR106;
input [(VAR13*VAR244 ) -1:0] VAR48;
input [(VAR13*VAR243 ) -1:0] VAR232;
input [( VAR280 ) -1:0] VAR261;
input [( VAR257 ) -1:0] VAR223;
input [( VAR89 ) -1:0] VAR161;
input [VAR194-1:0] VAR110;
input VAR253;
input [VAR251 - 1 : 0] VAR79;
input [VAR251 - 1 : 0] VAR260;
input [VAR251 * VAR277 - 1 : 0] VAR193;
input VAR114;
output VAR100;
output [VAR40-1:0] VAR33;
output [VAR207-1:0] VAR15;
output [VAR244-1:0] VAR219;
output [VAR243-1:0] VAR218;
output [VAR89-1:0] VAR210;
output [VAR257-1:0] VAR28;
output [VAR155-1:0] VAR141;
output VAR177;
output VAR117;
output VAR98;
output [VAR194-1:0] VAR45;
output [VAR251 - 1 : 0] VAR91;
output [VAR251 * VAR277 - 1 : 0] VAR34;
wire VAR88;
wire VAR1;
wire [VAR74- 1:0] VAR175;
wire [VAR24-1:0] VAR46;
wire [VAR131-1:0] VAR191;
wire [VAR183-1:0] VAR233;
wire [VAR196 - 1 : 0] VAR123;
wire [VAR118 - 1 : 0] VAR4;
wire [VAR41 - 1 : 0] VAR23;
wire [VAR108 - 1 : 0] VAR170;
wire [VAR9 - 1 : 0] VAR172;
reg VAR202;
reg [VAR280-1:0] VAR238;
wire VAR86;
wire VAR148;
wire VAR159;
wire VAR72;
wire [VAR89-1:0] VAR206;
wire [VAR257-1:0] VAR50;
reg VAR14;
reg [VAR194-1:0] VAR37;
reg VAR216;
reg [VAR257-1:0] VAR269;
wire [VAR13-1:0] VAR189;
wire [VAR13-1:0] VAR130;
wire [VAR13-1:0] VAR134;
wire [(VAR13*VAR40 ) -1:0] VAR158;
wire [(VAR13*VAR207 ) -1:0] VAR106;
wire [(VAR13*VAR244 ) -1:0] VAR48;
wire [(VAR13*VAR243 ) -1:0] VAR232;
wire [( VAR280 ) -1:0] VAR261;
wire [( VAR257 ) -1:0] VAR223;
wire [( VAR89 ) -1:0] VAR161;
reg [VAR13-1:0] VAR231;
reg [VAR13-1:0] VAR42;
reg [VAR13-1:0] VAR29;
reg [VAR40 -1:0] VAR208[VAR13-1:0];
reg [VAR207 -1:0] VAR92 [VAR13-1:0];
reg [VAR244 -1:0] VAR146 [VAR13-1:0];
reg [VAR243 -1:0] VAR150 [VAR13-1:0];
reg [VAR280 -1:0] VAR36;
reg [VAR257 -1:0] VAR83;
reg [VAR89 -1:0] VAR43;
wire [VAR194-1:0] VAR110;
wire VAR253;
wire [VAR251- 1 : 0] VAR79;
wire [VAR251- 1 : 0] VAR260;
wire [VAR251 * VAR277 - 1 : 0] VAR193;
wire VAR114;
wire VAR100;
wire [VAR40-1:0] VAR33;
wire [VAR207-1:0] VAR15;
wire [VAR244-1:0] VAR219;
wire [VAR243-1:0] VAR218;
wire [VAR89-1:0] VAR210;
wire [VAR257-1:0] VAR28;
wire VAR98;
wire [VAR194-1:0] VAR45;
wire [VAR251- 1 : 0] VAR91;
wire [VAR251 * VAR277 - 1 : 0] VAR34;
reg VAR177;
reg VAR117;
wire[VAR89-1:0] VAR119;
reg [VAR56 -1 : 0] VAR188;
reg [VAR56 -1 : 0] VAR11;
reg [VAR56 -1 : 0] VAR211;
wire VAR105;
reg [VAR73-1:0] VAR152;
reg VAR167;
wire VAR169;
wire VAR178;
wire VAR143;
wire [VAR280-1:0] VAR157;
wire [VAR57-1:0]VAR192;
wire VAR8;
wire VAR5;
wire VAR30;
wire [VAR97-1:0] VAR145;
wire [VAR97-1:0] VAR120;
wire VAR94;
wire VAR164;
wire VAR168;
reg VAR263;
reg VAR96; reg VAR63; reg VAR224; reg VAR61; wire VAR27;
reg VAR16;
reg VAR82;
reg VAR18;
wire [VAR194-1:0] VAR107;
wire [VAR280-1:0] VAR278;
wire [VAR257-1:0] VAR67;
wire [VAR89-1:0] VAR137;
wire [VAR251- 1 : 0] VAR125;
wire [VAR251 * VAR277 - 1 : 0] VAR245;
reg VAR54;
reg VAR160;
reg VAR144;
reg [VAR40-1:0] VAR165;
reg [VAR207-1:0] VAR47;
reg [VAR244-1:0] VAR267;
reg [VAR243-1:0] VAR181;
reg [VAR280-1:0] VAR274;
reg [VAR257-1:0] VAR254;
reg [VAR89-1:0] VAR187;
reg VAR166 [VAR13 -1 : 0];
reg VAR103 [VAR13 -1 : 0];
reg [VAR40-1:0] VAR2 [VAR13 -1 : 0];
reg [VAR207-1:0] VAR163 [VAR13 -1 : 0];
reg [VAR244-1:0] VAR147 [VAR13 -1 : 0];
reg [VAR243-1:0] VAR184 [VAR13 -1 : 0];
wire VAR60;
wire VAR201;
wire [VAR40-1:0] VAR217;
wire [VAR207-1:0] VAR151;
wire [VAR244-1:0] VAR222;
wire [VAR243-1:0] VAR282;
wire [VAR243-1:0] VAR132;
reg [VAR40-1:0] VAR26;
reg [VAR207-1:0] VAR93;
reg [VAR244-1:0] VAR176;
reg [VAR243-1:0] VAR256;
reg [VAR243-1:0] VAR25;
wire [VAR280-1:0] VAR69;
wire [VAR257-1:0] VAR186;
wire [VAR89-1:0] VAR272;
reg [VAR155-1:0] VAR237;
wire [VAR89-1:0] VAR247;
reg [VAR89-1:0] VAR250;
wire [VAR89-1:0] VAR115;
wire [VAR89-1:0] VAR70;
reg VAR271;
reg VAR198;
wire [VAR57-1:0] VAR81;
reg [VAR57-1:0] VAR149;
reg [VAR32-1:0] VAR58 [VAR57-1:0];
reg [VAR257-1:0] VAR6 [VAR57-1:0];
wire VAR171;
reg VAR49;
wire VAR124;
wire VAR252;
wire VAR112;
reg VAR7;
wire [VAR194-1:0] VAR95;
wire VAR242;
wire [VAR280-1:0] VAR62;
wire [VAR57-1:0] VAR205;
wire [VAR257-1:0] VAR140;
reg [VAR257-1:0] VAR53;
reg [VAR89-1:0] VAR102;
reg [VAR89-1:0] VAR179;
wire [VAR89-1:0] VAR128;
wire [VAR89-1:0] VAR135;
reg [VAR57-1:0] VAR22;
wire VAR199;
wire VAR265;
wire [VAR19-1:0] VAR234;
wire [VAR19-1:0] VAR180;
wire [VAR32-1:0] VAR129;
wire [VAR89-1:0] VAR279;
wire [VAR12-1:0] VAR162;
wire [VAR32-1:0] VAR249;
wire [VAR89-1:0] VAR10;
wire [VAR12-1:0] VAR200;
wire VAR113;
wire VAR281;
wire VAR66;
reg VAR266;
wire VAR236;
wire VAR39;
wire [VAR3-1:0] VAR228;
wire [VAR3-1:0] VAR259;
reg VAR77;
reg [VAR3-1:0] VAR20;
generate
begin : VAR87
if (VAR68 == "VAR138")
begin
always @
begin
VAR14 = VAR7;
VAR37 = VAR95;
VAR216 = VAR242;
VAR269 = VAR53;
VAR202 = ~VAR167 & VAR143;
VAR238 = VAR157;
end
end
end
endgenerate
genvar VAR240;
generate
for (VAR240 = 0; VAR240 < VAR13; VAR240 = VAR240 + 1)
begin : VAR109
always @
begin
VAR36 = VAR261;
VAR83 = VAR223;
VAR43 = VAR161;
end
always @
begin
VAR166 [VAR213] = VAR166 [VAR213 - 1] | ((VAR231 [VAR213]) ? VAR42 [VAR213] : 0);
VAR103 [VAR213] = VAR103 [VAR213 - 1] | ((VAR231 [VAR213]) ? VAR29 [VAR213] : 0);
VAR2 [VAR213] = VAR2 [VAR213 - 1] | ((VAR231 [VAR213]) ? VAR208 [VAR213] : 0);
VAR163 [VAR213] = VAR163 [VAR213 - 1] | ((VAR231 [VAR213]) ? VAR92 [VAR213] : 0);
VAR147 [VAR213] = VAR147 [VAR213 - 1] | ((VAR231 [VAR213]) ? VAR146 [VAR213] : 0);
VAR184 [VAR213] = VAR184 [VAR213 - 1] | ((VAR231 [VAR213]) ? VAR150 [VAR213] : 0);
end
end
endgenerate
always @
begin
VAR224 = 0;
VAR61 = 0;
VAR82 = 0;
VAR16 = 0;
VAR18 = 0;
if (~VAR46 & ~VAR59)
begin
VAR96 = VAR253;
VAR63 = VAR96 & VAR168;
end
else
begin
VAR224 = VAR253 & VAR27;
VAR96 = VAR253 & ~VAR27;
VAR63 = VAR96 & VAR168;
VAR61 = VAR224 & VAR168;
VAR16 = VAR281;
VAR18 = VAR253 & ( VAR113 | VAR281 );
if (VAR191)
begin
VAR82 = VAR63 & (VAR271 | VAR113);
end
end
end
assign VAR98 = VAR224;
assign VAR45 = VAR107;
assign VAR91 = VAR125;
assign VAR34 = VAR245;
always @ (posedge VAR88 or negedge VAR1)
begin
if (~VAR1)
begin
VAR271 <= 0;
VAR198 <= 0;
end
else
begin
if (VAR168)
begin
VAR271 <= 0;
VAR198 <= 0;
end
else if (VAR113)
begin
VAR271 <= 1;
end
else if (VAR281)
begin
VAR198 <= 1;
end
end
end
assign VAR113 = VAR253 & (|VAR79);
assign VAR281 = VAR253 & (|VAR260);
assign VAR247 = (VAR136) ? VAR250 : VAR115;
assign VAR115 = (VAR253) ? VAR250 + 1 : VAR250;
assign VAR70 = VAR272;
always @ (posedge VAR88 or negedge VAR1)
begin
if (~VAR1)
begin
VAR250 <= 0;
end
else
begin
if (VAR168)
begin
VAR250 <= VAR115 - VAR70;
end
else
begin
VAR250 <= VAR115;
end
end
end
assign VAR39 = VAR82;
assign VAR228 = {VAR217, VAR151, VAR222, VAR132, VAR119, VAR186};
assign {VAR33, VAR15, VAR219, VAR218, VAR210, VAR28} = VAR259;
assign VAR66 = ~VAR236 & VAR39;
assign VAR119 = (VAR233 / VAR229);
assign VAR132 = (VAR175 == VAR65) ? {VAR282[(VAR243-1):3],{3{1'b0}} } : VAR282;
always @ (posedge VAR88 or negedge VAR1)
begin
if (!VAR1)
begin
VAR26 <= 0;
VAR93 <= 0;
VAR176 <= 0;
VAR256 <= 0;
VAR25 <= 0;
end
else
begin
VAR26 <= VAR217 ;
VAR93 <= VAR151 ;
VAR176 <= VAR222 ;
VAR256 <= VAR282 ;
VAR25 <= VAR132;
end
end
generate
if (VAR215 == 1)
begin
always @ (posedge VAR88 or negedge VAR1)
begin
if (!VAR1)
begin
VAR77 <= 1'b0;
VAR20 <= {VAR3{1'b0}};
end else
begin
VAR77 <= VAR39;
VAR20 <= VAR228;
end
end
end else begin
always @
begin : VAR204
VAR237 = 0;
VAR237[VAR99 - VAR52 - 1 : 0] = VAR25[VAR99 - 1 : VAR52];
for (VAR154=VAR99; VAR154<VAR142; VAR154=VAR154+1'b1) begin
if(VAR154 < VAR4) begin VAR237[VAR154 - VAR52] = VAR25[VAR154];
end
end
for (VAR230=0; VAR230<VAR270; VAR230=VAR230+1'b1) begin VAR237[VAR230 + VAR211] = VAR176[VAR230];
end
for (VAR230=VAR270; VAR230<VAR173; VAR230=VAR230+1'b1) begin
if(VAR230 < VAR23) begin VAR237[VAR230 + VAR211] = VAR176[VAR230];
end
end
for (VAR127=0; VAR127<VAR227; VAR127=VAR127+1'b1) begin VAR237[VAR127 + VAR11] = VAR93[VAR127];
end
for (VAR127=VAR227; VAR127<VAR90; VAR127=VAR127+1'b1) begin
if(VAR127 < VAR170) begin VAR237[VAR127 + VAR11] = VAR93[VAR127];
end
end
VAR156 = 0;
if (VAR172 > 1'b0) begin for (VAR156=0; VAR156<VAR31; VAR156=VAR156+1'b1) begin VAR237[VAR156 + VAR188] = VAR26[VAR156];
end
for (VAR156=VAR31; VAR156<VAR133; VAR156=VAR156+1'b1) begin
if(VAR156 < VAR172) begin VAR237[VAR156 + VAR188] = VAR26[VAR156];
end
end
end
end
always @ (posedge VAR88 or negedge VAR1)
begin
if (~VAR1)
begin
VAR188 <= 0;
VAR11 <= 0;
VAR211 <= 0;
end
else
begin
if(VAR123 == VAR258)
VAR211 <= VAR172 + VAR170 + VAR4 - VAR52;
end
else if(VAR123 == VAR246)
VAR211 <= VAR4 - VAR52;
end
else VAR211 <= VAR170 + VAR4 - VAR52;
if(VAR123 == VAR246)
VAR11 <= VAR23 + VAR4 - VAR52;
end
else VAR11 <= VAR4 - VAR52;
if(VAR123 == VAR258)
VAR188 <= VAR170 + VAR4 - VAR52;
end
else VAR188 <= VAR170 + VAR23 + VAR4 - VAR52;
end
end
generate
begin : VAR153
if (VAR68 == "VAR276")
begin
genvar VAR212;
for (VAR212 = 0; VAR212 < VAR57; VAR212 = VAR212 + 1)
begin : VAR209
assign VAR81[VAR212] = |(VAR58[VAR212]);
always @ (posedge VAR88 or negedge VAR1)
begin
if (~VAR1)
begin
VAR149[VAR212] <= 1'b0;
VAR58[VAR212] <= 0;
VAR6 [VAR212] <= 0;
end
else
begin
if (VAR105 & VAR192[VAR212])
begin
VAR58[VAR212] <= VAR206;
end
if (VAR96 & (VAR278 == VAR212))
begin
VAR149[VAR212] <= 1'b1;
VAR6[VAR212] <= VAR67;
end
if (VAR171 & VAR205[VAR212])
begin
VAR149[VAR212] <= 1'b0;
VAR58[VAR212] <= 0;
end
end
end
always @ (*)
begin
if (VAR124 & VAR205[VAR212])
begin
VAR22[VAR212] = VAR149[VAR212];
end
else
begin
VAR22[VAR212] = 1'b0;
end
end
end
assign VAR112 = |VAR22;
assign VAR178 = VAR105;
assign VAR5 = VAR178 & VAR143;
assign VAR143 = VAR30 & VAR199;
assign VAR124 = VAR252 & VAR265;
VAR71
.VAR80 (VAR280),
.VAR214 (VAR57),
.VAR55 ("VAR116"),
.VAR101 ("VAR85")
)
VAR139
(
.VAR88 (VAR88),
.VAR1 (VAR1),
.VAR76 (VAR178),
.VAR104 (VAR30),
.VAR262 (VAR157),
.VAR185 (VAR192),
.VAR17 (),
.VAR75 (VAR171),
.VAR38 (VAR62)
);
VAR71
.VAR80 (VAR280),
.VAR214 (VAR57),
.VAR55 ("VAR221"),
.VAR101 ("VAR44")
)
VAR174
(
.VAR88 (VAR88),
.VAR1 (VAR1),
.VAR76 (VAR171),
.VAR104 (VAR252),
.VAR262 (VAR62),
.VAR185 (VAR205),
.VAR17 (VAR8),
.VAR75 (VAR5),
.VAR38 (VAR157)
);
assign VAR234 = {VAR50,VAR206};
assign {VAR140,VAR135} = VAR180;
VAR264
.VAR195 (VAR19),
.VAR248 (VAR280)
)
VAR225
(
.VAR88 (VAR88),
.VAR1 (VAR1),
.VAR35 (VAR171),
.VAR84 (VAR265),
.VAR126 (VAR180),
.VAR21 (VAR199),
.VAR239 (VAR5),
.VAR51 (VAR234)
);
always @ (posedge VAR88 or negedge VAR1)
begin
if (~VAR1)
begin
VAR102 <= 0;
VAR179 <= 0;
VAR7 <= 0;
VAR49 <= 0;
VAR53 <= 0;
end
else
begin
if (VAR171)
begin
VAR102 <= 0;
VAR179 <= 1;
end
else
begin
VAR102 <= VAR128;
VAR179 <= VAR128 + 1;
end
VAR53 <= VAR140;
VAR7 <= VAR112;
VAR49 <= VAR171;
end
end
assign VAR128 = (VAR112) ? (VAR179) : VAR102;
assign VAR171 = VAR112 & (VAR179 == VAR135);
assign VAR279 = VAR250;
assign VAR129 = {VAR278,VAR279};
assign VAR162 = {VAR16,VAR107};
assign VAR10 = VAR102;
assign VAR249 = {VAR62,VAR10};
assign {VAR242,VAR95} = VAR200;
VAR255
.VAR197 (VAR32),
.VAR111 (VAR12)
)
VAR121
(
.VAR88 (VAR88),
.VAR1 (VAR1),
.VAR273 (VAR96),
.VAR220 (VAR129),
.VAR275 (VAR162),
.VAR235 (VAR112),
.VAR203 (VAR249),
.VAR37 (VAR200)
);
end
end
endgenerate
function integer VAR190;
input [31:0] VAR226;
integer VAR212;
begin
VAR190 = 0;
for(VAR212 = 0; 2**VAR212 < VAR226; VAR212 = VAR212 + 1)
VAR190 = VAR212 + 1;
end
endfunction
endmodule
|
gpl-3.0
|
GREO/GNU-Radio
|
usrp/fpga/sdr_lib/ext_fifo.v
| 3,847 |
module MODULE2 (reset,VAR1,write,VAR23,VAR10,VAR13,VAR2,VAR33,VAR15);
parameter VAR9=32;
parameter VAR18=10;
input reset; input [VAR9-1:0] VAR1;
input write;
input VAR23;
output [VAR18-1:0] VAR10;
output [VAR9-1:0] VAR13;
input VAR2;
input VAR33;
output [VAR18-1:0] VAR15;
reg [VAR18-1:0] VAR11, VAR4,
VAR34, VAR30,
VAR25, VAR22;
VAR32 #(.VAR18(10),.VAR9(VAR9),.VAR5(1024))
VAR14 (.VAR17(VAR23),.VAR7(VAR1),.VAR3(VAR4),.VAR19(write),
.VAR16(VAR33), .VAR36(VAR13),.VAR21(VAR11) );
wire [VAR18-1:0] VAR29,VAR20;
always @(posedge VAR23 or posedge reset)
if(reset) VAR4 <= 0;
else if(write) VAR4 <= VAR4 + 1;
always @(posedge VAR33 or posedge reset)
if(reset) VAR11 <= 0;
else if(VAR2) VAR11 <= VAR11 + 1;
MODULE3 #(VAR18) VAR35 (VAR4,VAR29);
MODULE3 #(VAR18) VAR27 (VAR11,VAR20);
always @(posedge VAR23 or posedge reset)
if(reset) VAR25 <= 0;
else VAR25 <= VAR29;
always @(posedge VAR33 or posedge reset)
if(reset) VAR34 <= 0;
else VAR34 <= VAR20;
always @(posedge VAR23 or posedge reset)
if(reset) VAR30 <= 0;
else VAR30 <= VAR34;
always @(posedge VAR33 or posedge reset)
if(reset) VAR22 <= 0;
else VAR22 <= VAR25;
wire [VAR18-1:0] VAR12, VAR6;
MODULE1 #(VAR18) VAR31 (VAR22, VAR12);
MODULE1 #(VAR18) VAR24 (VAR30, VAR6);
assign VAR15 = VAR12 - VAR11;
assign VAR10 = VAR4 - VAR6;
endmodule
module MODULE3(VAR8,VAR26);
parameter VAR9 = 8;
input [VAR9-1:0] VAR8;
output reg [VAR9-1:0] VAR26;
integer VAR28;
always @*
begin
VAR26[VAR9-1] = VAR8[VAR9-1];
for(VAR28=0;VAR28<VAR9-1;VAR28=VAR28+1)
VAR26[VAR28] = VAR8[VAR28] ^ VAR8[VAR28+1];
end
endmodule
module MODULE1(VAR26,VAR8);
parameter VAR9 = 8;
input [VAR9-1:0] VAR26;
output reg [VAR9-1:0] VAR8;
integer VAR28;
always @*
begin
VAR8[VAR9-1] = VAR26[VAR9-1];
for(VAR28=VAR9-2;VAR28>=0;VAR28=VAR28-1)
VAR8[VAR28] = VAR8[VAR28+1] ^ VAR26[VAR28];
end
endmodule
|
gpl-3.0
|
ultraembedded/riscv
|
top_cache_axi/src_v/dcache_core_data_ram.v
| 3,710 |
module MODULE1
(
input VAR8
,input VAR14
,input [ 10:0] VAR9
,input [ 31:0] VAR12
,input [ 3:0] VAR3
,input VAR2
,input VAR11
,input [ 10:0] VAR6
,input [ 31:0] VAR7
,input [ 3:0] VAR4
,output [ 31:0] VAR5
,output [ 31:0] VAR10
);
reg [31:0] VAR15 [2047:0] ;
reg [31:0] VAR1;
reg [31:0] VAR13;
always @ (posedge VAR8)
begin
if (VAR3[0])
VAR15[VAR9][7:0] <= VAR12[7:0];
if (VAR3[1])
VAR15[VAR9][15:8] <= VAR12[15:8];
if (VAR3[2])
VAR15[VAR9][23:16] <= VAR12[23:16];
if (VAR3[3])
VAR15[VAR9][31:24] <= VAR12[31:24];
VAR1 <= VAR15[VAR9];
end
always @ (posedge VAR2)
begin
if (VAR4[0])
VAR15[VAR6][7:0] <= VAR7[7:0];
if (VAR4[1])
VAR15[VAR6][15:8] <= VAR7[15:8];
if (VAR4[2])
VAR15[VAR6][23:16] <= VAR7[23:16];
if (VAR4[3])
VAR15[VAR6][31:24] <= VAR7[31:24];
VAR13 <= VAR15[VAR6];
end
assign VAR5 = VAR1;
assign VAR10 = VAR13;
endmodule
|
bsd-3-clause
|
GREO/GNU-Radio
|
usrp/fpga/inband_lib/chan_fifo_reader.v
| 7,796 |
module MODULE1
(reset, VAR5, VAR17, VAR28, VAR20,
VAR29, VAR23, VAR32, VAR25, VAR12, VAR1,
VAR31, VAR33, VAR30, VAR21, VAR24, VAR22) ;
input wire reset ;
input wire VAR5 ;
input wire VAR17 ; input wire [31:0] VAR28 ; input wire [3:0] VAR20 ; input wire [31:0] VAR29 ; input wire VAR23 ; output reg VAR32 ; output reg VAR25 ; output reg [15:0] VAR12 ; output reg [15:0] VAR1 ; output reg VAR31 ;
output reg VAR33 ; input wire [31:0] VAR21;
input wire [31:0] VAR24;
input wire [31:0] VAR22;
output wire [14:0] VAR30;
assign VAR30 = {7'd0, VAR32, VAR25, VAR3, VAR23, VAR17, VAR5};
parameter VAR14 = 3'd0;
parameter VAR6 = 3'd1;
parameter VAR11 = 3'd2;
parameter VAR9 = 3'd3;
parameter VAR19 = 3'd4;
parameter VAR16 = 3'd5;
reg [2:0] VAR3;
reg [6:0] VAR27;
reg [6:0] VAR15;
reg [31:0] VAR26;
reg VAR34;
reg VAR8;
reg VAR7;
reg [31:0] VAR13;
always @(posedge VAR5)
begin
if (reset)
begin
VAR3 <= VAR14;
VAR32 <= 0;
VAR25 <= 0;
VAR31 <= 0;
VAR34 <= 0;
VAR33 <= 1;
VAR12 <= 0;
VAR1 <= 0;
VAR8 <= 0;
VAR7 <= 0;
VAR13 <= 0;
end
else
begin
case (VAR3)
VAR14:
begin
VAR25 <=0;
VAR13 <= 0;
if (VAR23 == 1)
begin
VAR3 <= VAR6;
VAR32 <= 1;
VAR31 <= 0;
end
if (VAR34 == 1 && VAR23 == 0)
VAR31 <= 1;
if (VAR17 == 1)
VAR33 <= 1 ;
end
VAR6:
begin
if (VAR17 == 1)
VAR33 <= 1 ;
VAR7 <= VAR29[VAR4]&VAR29[VAR18];
if (VAR29[VAR18] == 1
&& VAR29[VAR2] == 1)
VAR34 <= 0;
end
else if (VAR29[VAR18] == 1)
VAR34 <= 1;
end
else if (VAR29[VAR2] == 1)
VAR34 <= 0;
if (VAR8 == 1 && VAR29[VAR18] == 0)
begin
VAR25 <= 1;
VAR3 <= VAR14;
VAR32 <= 0;
end
else
begin
VAR27 <= VAR29[VAR10] ;
VAR15 <= 0;
VAR32 <= 1;
VAR3 <= VAR11;
end
end
VAR11:
begin
VAR26 <= VAR29;
VAR3 <= VAR9;
if (VAR17 == 1)
VAR33 <= 1 ;
VAR32 <= 0;
end
VAR9:
begin
if (VAR17 == 1)
VAR33 <= 1 ;
VAR13 <= VAR13 + 32'd1;
if ((VAR26 < VAR28) ||
(VAR13 >= VAR22 && VAR22 != 0 && VAR7))
begin
VAR8 <= 1;
VAR3 <= VAR14;
VAR25 <= 1;
end
else if (VAR26 == VAR28
|| VAR26 == 32'hFFFFFFFF)
begin
if (VAR21 <= VAR24 || VAR7 == 0)
begin
VAR8 <= 0;
VAR3 <= VAR19;
end
else
VAR3 <= VAR9;
end
else
VAR3 <= VAR9;
end
VAR19:
begin
if (VAR15 == VAR27)
begin
VAR3 <= VAR14;
VAR25 <= 1;
if (VAR17 == 1)
VAR33 <= 1 ;
end
else if (VAR17 == 1)
begin
VAR3 <= VAR16;
VAR32 <= 1;
end
end
VAR16:
begin
VAR3 <= VAR19;
VAR15 <= VAR15 + 7'd1;
VAR33 <= 0;
VAR32 <= 0;
case(VAR20)
begin
VAR1 <= VAR29[15:0];
VAR12 <= VAR29[31:16];
end
default:
begin
VAR1 <= VAR29[15:0];
VAR12 <= VAR29[31:16];
end
endcase
end
default:
begin
VAR3 <= VAR14;
end
endcase
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/mux4/sky130_fd_sc_ls__mux4.blackbox.v
| 1,339 |
module MODULE1 (
VAR11 ,
VAR4,
VAR8,
VAR10,
VAR1,
VAR3,
VAR9
);
output VAR11 ;
input VAR4;
input VAR8;
input VAR10;
input VAR1;
input VAR3;
input VAR9;
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
curtiszimmerman/orp
|
hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/ftl_wbs.v
| 4,571 |
module MODULE1 (
input wire VAR28,
input wire VAR40,
input wire VAR27,
input wire [31:0] VAR30,
output wire [31:0] VAR37,
input wire [31:0] VAR38,
input wire [3:0] VAR35,
input wire VAR44,
input wire VAR7,
input wire VAR46,
output wire VAR5,
output wire VAR19,
output wire [15:0] VAR45,
output reg VAR33,
output reg [31:0] VAR17,
input wire [31:0] VAR1,
input wire VAR3,
output reg VAR2,
output reg VAR25,
output reg [9:0] VAR14,
input wire VAR24,
input wire VAR21
);
assign VAR19 = VAR27;
assign VAR45 = (VAR30 % VAR23) / 4;
assign VAR5 = VAR15 & VAR7;
assign VAR37 = VAR1;
reg VAR15;
reg VAR8;
reg VAR6;
wire VAR12;
wire VAR18;
wire VAR20;
wire VAR36;
VAR32 VAR11(VAR40, VAR12, VAR27);
VAR32 VAR34(VAR3, VAR18, VAR27);
VAR32 VAR16(VAR24, VAR20, VAR27);
VAR32 VAR42(VAR21, VAR36, VAR27);
wire [9:0] VAR31 = VAR30 / VAR23;
reg [9:0] VAR10;
reg [9:0] VAR43;
reg VAR39;
reg [3:0] state;
wire VAR29 = VAR30 >= 32'h200000;
parameter [3:0] VAR13 = 'd0,
VAR41 = 'd1,
VAR22 = 'd2,
VAR9 = 'd3,
VAR26 = 'd5,
VAR4 = 'd6;
always @(posedge VAR27) begin
VAR15 <= 0;
VAR8 <= VAR7;
VAR6 <= VAR36;
VAR2 <= 0;
VAR25 <= 0;
VAR33 <= 0;
case(state)
VAR13: begin
VAR43 <= -1;
VAR39 <= 0;
if(VAR18) state <= VAR41;
end
VAR41: begin
if(VAR44 & VAR7 & ~VAR8 & VAR29) begin
if(VAR46) begin
if((VAR43 == VAR31) && VAR39) begin
VAR17 <= VAR38;
VAR33 <= 1;
VAR15 <= 1;
end else begin
state <= VAR9;
VAR10 <= VAR31;
end
end else begin
if(VAR43 == VAR31) begin
state <= VAR4;
end else begin
state <= VAR22;
VAR10 <= VAR31;
end
end
end
end
VAR26: begin
VAR8 <= 0; if(~VAR20) state <= VAR41;
end
VAR9: begin
VAR39 <= 1;
VAR14 <= VAR10;
VAR25 <= 1;
if(VAR36 & ~VAR6) begin
VAR43 <= VAR10;
state <= VAR26;
end
end
VAR22: begin
VAR39 <= 0;
VAR14 <= VAR10;
VAR2 <= 1;
if(VAR36 & ~VAR6) begin
VAR43 <= VAR10;
state <= VAR26;
end
end
VAR4: begin
VAR15 <= 1;
state <= VAR41;
end
endcase
if(~VAR12) begin
state <= VAR13;
end
end
endmodule
|
apache-2.0
|
tdene/synth_opt_adders
|
src/pptrees/mappings/sky130_fd_sc_hs_map.v
| 4,263 |
module MODULE19
(
VAR1, VAR4
);
output VAR1;
input VAR4;
VAR5 MODULE19(.VAR1(VAR1), .VAR4(VAR4));
endmodule
module MODULE8
(
VAR1, VAR4
);
output VAR1;
input VAR4;
VAR10 MODULE8(.VAR20(VAR1), .VAR4(VAR4));
endmodule
module MODULE17
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR35 MODULE17(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18));
endmodule
module MODULE24
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR36 MODULE24(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18));
endmodule
module MODULE25
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR21 MODULE25(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18));
endmodule
module MODULE2
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR15 MODULE2(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18));
endmodule
module MODULE9
(
VAR1, VAR4, VAR18, VAR29
);
output VAR1;
input VAR4, VAR18, VAR29;
VAR24 MODULE9(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29));
endmodule
module MODULE22
(
VAR1, VAR4, VAR18, VAR29
);
output VAR1;
input VAR4, VAR18, VAR29;
VAR6 MODULE22(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29));
endmodule
module MODULE3
(
VAR1, VAR4, VAR18, VAR29
);
output VAR1;
input VAR4, VAR18, VAR29;
VAR26 MODULE3(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29));
endmodule
module MODULE28
(
VAR1, VAR4, VAR18, VAR29
);
output VAR1;
input VAR4, VAR18, VAR29;
VAR43 MODULE28(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29));
endmodule
module MODULE4
(
VAR1, VAR4, VAR18, VAR29, VAR39
);
output VAR1;
input VAR4, VAR18, VAR29, VAR39;
VAR38 MODULE4(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29), .VAR39(VAR39));
endmodule
module MODULE1
(
VAR1, VAR4, VAR18, VAR29, VAR39
);
output VAR1;
input VAR4, VAR18, VAR29, VAR39;
VAR30 MODULE1(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29), .VAR39(VAR39));
endmodule
module MODULE23
(
VAR1, VAR4, VAR18, VAR29, VAR39
);
output VAR1;
input VAR4, VAR18, VAR29, VAR39;
VAR8 MODULE23(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29), .VAR39(VAR39));
endmodule
module MODULE11
(
VAR1, VAR4, VAR18, VAR29, VAR39
);
output VAR1;
input VAR4, VAR18, VAR29, VAR39;
VAR3 MODULE11(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18), .VAR29(VAR29), .VAR39(VAR39));
endmodule
module MODULE12
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR25 MODULE12(.VAR1(VAR1), .VAR37(VAR4), .VAR18(VAR18));
endmodule
module MODULE27
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR9 MODULE27(.VAR1(VAR1), .VAR4(VAR18), .VAR17(VAR4));
endmodule
module MODULE13
(
VAR1, VAR28, VAR23, VAR12
);
output VAR1;
input VAR28, VAR23, VAR12;
VAR19 MODULE13(.VAR20(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12));
endmodule
module MODULE5
(
VAR1, VAR28, VAR23, VAR12
);
output VAR1;
input VAR28, VAR23, VAR12;
VAR7 MODULE5(.VAR20(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12));
endmodule
module MODULE21
(
VAR1, VAR28, VAR23, VAR12
);
output VAR1;
input VAR28, VAR23, VAR12;
VAR11 MODULE21(.VAR1(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12));
endmodule
module MODULE6
(
VAR1, VAR28, VAR23, VAR12
);
output VAR1;
input VAR28, VAR23, VAR12;
VAR40 MODULE6(.VAR1(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12));
endmodule
module MODULE10
(
VAR1, VAR28, VAR23, VAR12, VAR31
);
output VAR1;
input VAR28, VAR23, VAR12, VAR31;
VAR41 MODULE10(.VAR20(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12), .VAR34(VAR31));
endmodule
module MODULE20
(
VAR1, VAR28, VAR23, VAR12, VAR31
);
output VAR1;
input VAR28, VAR23, VAR12, VAR31;
VAR42 MODULE20(.VAR20(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12), .VAR34(VAR31));
endmodule
module MODULE14
(
VAR1, VAR28, VAR23, VAR12, VAR31
);
output VAR1;
input VAR28, VAR23, VAR12, VAR31;
VAR27 MODULE14(.VAR1(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12), .VAR34(VAR31));
endmodule
module MODULE7
(
VAR1, VAR28, VAR23, VAR12, VAR31
);
output VAR1;
input VAR28, VAR23, VAR12, VAR31;
VAR13 MODULE7(.VAR1(VAR1), .VAR23(VAR28), .VAR16(VAR23), .VAR31(VAR12), .VAR34(VAR31));
endmodule
module MODULE26
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR33 MODULE26(.VAR20(VAR1), .VAR4(VAR4), .VAR18(VAR18));
endmodule
module MODULE18
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR22 MODULE18(.VAR1(VAR1), .VAR4(VAR4), .VAR18(VAR18));
endmodule
module MODULE16
(
VAR1, VAR14, VAR4, VAR18
);
output VAR1;
input VAR14, VAR4, VAR18;
VAR32 MODULE16(.VAR20(VAR1), .VAR14(VAR14), .VAR28(VAR4), .VAR23(VAR18));
endmodule
module MODULE15
(
VAR1, VAR14, VAR4, VAR18
);
output VAR1;
input VAR14, VAR4, VAR18;
VAR2 MODULE15(.VAR1(VAR1), .VAR14(VAR14), .VAR28(VAR4), .VAR23(VAR18));
endmodule
|
apache-2.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_dram_ctrl.v
| 6,340 |
module MODULE1
import VAR21::*;
import VAR77::*;
, parameter VAR38(VAR6)
, parameter VAR38(VAR84)
, parameter VAR38(VAR85)
, localparam VAR46=(VAR84>>3)
, localparam VAR15=VAR2(VAR34)
, localparam VAR59=VAR36(VAR6)
, parameter VAR38(VAR81)
, parameter VAR5=(VAR6+VAR15)
, localparam VAR3=(VAR85/VAR81)
)
(
input VAR66
, input VAR82
, input [2:0] VAR20
, input [VAR34-1:0][VAR59-1:0] VAR68
, input [VAR34-1:0] VAR10
, output logic [VAR34-1:0] VAR18
, output logic [VAR34-1:0][VAR84-1:0] VAR80
, output logic [VAR34-1:0] VAR45
, input [VAR34-1:0] VAR60
, input [VAR34-1:0][VAR84-1:0] VAR27
, input [VAR34-1:0] VAR32
, output logic [VAR34-1:0] VAR63
, output logic VAR69
, input VAR25
, output VAR75 VAR26
, output logic [VAR5-1:0] VAR9
, output logic VAR14
, input VAR47
, output logic [VAR84-1:0] VAR67
, output logic [VAR46-1:0] VAR49
, output logic VAR71
, input VAR13
, input [VAR84-1:0] VAR40
, input VAR65
);
VAR48 VAR73;
logic VAR74;
logic [VAR15-1:0] VAR29;
logic VAR56;
VAR42 #(
.VAR17(VAR59)
,.VAR24(VAR34)
,.VAR28(0)
) VAR58 (
.VAR66(VAR66)
,.VAR82(VAR82)
,.VAR30(VAR68)
,.VAR53(VAR10)
,.VAR41(VAR18)
,.VAR33(VAR74)
,.VAR62(VAR73)
,.VAR44(VAR29)
,.VAR8(VAR56)
);
logic [VAR15-1:0] VAR43, VAR52;
logic VAR61;
logic VAR39;
VAR51 #(
.VAR34(VAR34)
,.VAR84(VAR84)
,.VAR85(VAR85)
,.VAR81(VAR81)
) VAR79 (
.VAR66(VAR66)
,.VAR82(VAR82)
,.VAR53(VAR61)
,.VAR76(VAR43)
,.VAR22(VAR39)
,.VAR80(VAR80)
,.VAR45(VAR45)
,.VAR60(VAR60)
,.VAR13(VAR13)
,.VAR40(VAR40)
,.VAR65(VAR65)
);
logic VAR86;
logic VAR64;
VAR54 #(
.VAR34(VAR34)
,.VAR84(VAR84)
,.VAR85(VAR85)
,.VAR81(VAR81)
) VAR57 (
.VAR66(VAR66)
,.VAR82(VAR82)
,.VAR53(VAR86)
,.VAR76(VAR43)
,.VAR22(VAR64)
,.VAR27(VAR27)
,.VAR32(VAR32)
,.VAR63(VAR63)
,.VAR14(VAR14)
,.VAR47(VAR47)
,.VAR67(VAR67)
,.VAR49(VAR49)
,.VAR71(VAR71)
);
typedef enum logic {
VAR37,
VAR1
} VAR78;
VAR78 VAR55, VAR12;
logic [VAR6-1:0] VAR83, VAR70;
logic VAR31, VAR72;
logic [VAR2(VAR3)-1:0] VAR16, VAR23;
VAR19 begin
VAR69 = 1'b0;
VAR26 = VAR35;
VAR56 = 1'b0;
VAR52 = VAR43;
VAR72 = VAR31;
VAR61 = 1'b0;
VAR86 = 1'b0;
VAR12 = VAR55;
VAR23 = VAR16;
VAR70 = VAR83;
case (VAR55)
VAR37: begin
if (VAR74) begin
VAR56 = 1'b1;
VAR52 = VAR29;
VAR70 = VAR73.addr;
VAR72 = VAR73.VAR11;
VAR23 = '0;
VAR12 = VAR1;
end
end
VAR1: begin
VAR69 = (VAR31
? VAR64
: VAR39);
VAR26 = VAR31
? VAR35
: VAR4;
VAR61 = ~VAR31 & VAR39 & VAR25;
VAR86 = VAR31 & VAR64 & VAR25;
VAR70 = (VAR25 & VAR69)
? VAR83 + (1 << VAR2(VAR81*VAR84/8))
: VAR83;
VAR23 = (VAR25 & VAR69)
? VAR16 + 1
: VAR16;
VAR12 = VAR25 & VAR69 & (VAR16 == VAR3-1)
? VAR37
: VAR1;
end
endcase
end
VAR19
case (VAR20)
0: VAR9 = VAR5'({VAR43, VAR83[25-VAR7(VAR34)-1:0]});
1: VAR9 = VAR5'({VAR43, VAR83[26-VAR7(VAR34)-1:0]});
2: VAR9 = VAR5'({VAR43, VAR83[27-VAR7(VAR34)-1:0]});
3: VAR9 = VAR5'({VAR43, VAR83[28-VAR7(VAR34)-1:0]});
4: VAR9 = VAR5'({VAR43, VAR83[29-VAR7(VAR34)-1:0]});
default: VAR9 = {VAR43, VAR83};
endcase
VAR50 @ (posedge VAR66) begin
if (VAR82) begin
VAR55 <= VAR37;
VAR43 <= '0;
VAR83 <= '0;
VAR16 <= '0;
VAR31 <= 1'b0;
end
else begin
VAR55 <= VAR12;
VAR43 <= VAR52;
VAR83 <= VAR70;
VAR16 <= VAR23;
VAR31 <= VAR72;
end
end
endmodule
|
bsd-3-clause
|
trivoldus28/pulsarch-verilog
|
verif/model/verilog/mem/dram/dimm.v
| 10,028 |
module MODULE1( clk, VAR28, VAR27, VAR45, VAR14, VAR1, addr, VAR6,
VAR31, VAR25, VAR21, VAR10
);
parameter VAR13=17,
VAR47=2,
VAR47=3,
VAR35=9;
input [2:0] clk;
input [1:0] VAR28;
input VAR27, VAR45, VAR14;
input [(VAR47-1):0] VAR1;
input [(VAR13-1):0] addr;
input [7:0] VAR6;
inout [63:0] VAR31;
inout [7:0] VAR25;
inout [(VAR35-1):0] VAR21, VAR10;
integer VAR32, VAR4; parameter VAR15 = 11;
parameter VAR48 = VAR47 + VAR13 + VAR15;
parameter VAR23 = (1 << VAR47);
parameter VAR5 = 31;
parameter VAR33 = 400;
wire [3:0] VAR7, VAR26, VAR16;
reg [(VAR15-1):0] VAR17;
reg [63:0] VAR39;
reg [63:0] VAR37;
reg [7:0] VAR46;
reg [7:0] VAR42;
reg [VAR5:0] VAR18;
reg [VAR5:0] VAR9;
reg [3:0] VAR38, VAR11, VAR22;
reg [(VAR48-1):0] VAR8 [VAR5:0];
reg [(VAR48-1):0] VAR41 [VAR5:0];
reg [(VAR13-1):0] VAR40 [(VAR23-1):0];
reg [5:0] VAR34;
reg VAR36;
reg VAR2;
reg VAR30;
reg [1:0] VAR19;
reg VAR29, VAR24, VAR3;
reg [(VAR47-1):0] VAR12;
reg [(VAR13-1):0] VAR44;
integer VAR20;
assign VAR31 = (VAR36 == 1'b1) ? VAR39 : {64{1'VAR43}};
assign VAR25 = (VAR36 == 1'b1) ? VAR46 : {8{1'VAR43}};
assign VAR21 = (VAR2 == 1'b1) ? {VAR35{VAR30}} : {VAR35{1'VAR43}};
assign VAR10 = (VAR2 == 1'b1) ? {VAR35{VAR30}} : {VAR35{1'VAR43}};
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
|
gpl-2.0
|
osrf/wandrr
|
firmware/motor_controller/fpga/fake_mii.v
| 4,382 |
module MODULE1
(input VAR11,
inout VAR13);
reg [15:0] VAR3[0:31];
reg [15:0] VAR12;
reg VAR15;
reg VAR1;
reg VAR8;
reg VAR6;
reg [1:0] VAR10;
reg [4:0] VAR4;
reg [4:0] VAR9;
integer VAR7;
always @(VAR13) VAR8 <= VAR13;
assign VAR13 = VAR1 ? VAR15 : 1'VAR2;
integer VAR14, VAR5;
begin
begin
|
apache-2.0
|
felixmo/Pong
|
pll108MHz_bb.v
| 10,692 |
module MODULE1 (
VAR2,
VAR1);
input VAR2;
output VAR1;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/or4/sky130_fd_sc_hd__or4.pp.blackbox.v
| 1,308 |
module MODULE1 (
VAR9 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR5 ,
VAR2,
VAR7,
VAR8 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR2;
input VAR7;
input VAR8 ;
input VAR6 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/sdfrtn/sky130_fd_sc_ms__sdfrtn.behavioral.v
| 2,952 |
module MODULE1 (
VAR5 ,
VAR23 ,
VAR25 ,
VAR16 ,
VAR24 ,
VAR17
);
output VAR5 ;
input VAR23 ;
input VAR25 ;
input VAR16 ;
input VAR24 ;
input VAR17;
supply1 VAR27;
supply0 VAR31;
supply1 VAR26 ;
supply0 VAR8 ;
wire VAR10 ;
wire VAR32 ;
wire VAR9 ;
wire VAR30 ;
reg VAR6 ;
wire VAR7 ;
wire VAR19 ;
wire VAR4 ;
wire VAR33;
wire VAR29 ;
wire VAR11 ;
wire VAR28 ;
wire VAR22 ;
wire VAR20 ;
wire VAR2 ;
wire VAR13 ;
not VAR12 (VAR32 , VAR33 );
not VAR14 (VAR9 , VAR29 );
VAR3 VAR18 (VAR30, VAR7, VAR19, VAR4 );
VAR1 VAR15 (VAR10 , VAR30, VAR9, VAR32, VAR6, VAR27, VAR31);
assign VAR11 = ( VAR27 === 1'b1 );
assign VAR28 = ( VAR11 && ( VAR33 === 1'b1 ) );
assign VAR22 = ( ( VAR4 === 1'b0 ) && VAR28 );
assign VAR20 = ( ( VAR4 === 1'b1 ) && VAR28 );
assign VAR2 = ( ( VAR7 !== VAR19 ) && VAR28 );
assign VAR13 = ( VAR11 && ( VAR17 === 1'b1 ) );
buf VAR21 (VAR5 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.blackbox.v
| 1,399 |
module MODULE1 (
VAR9 ,
VAR2,
VAR10 ,
VAR4 ,
VAR8,
VAR7
);
output VAR9 ;
input VAR2;
input VAR10 ;
input VAR4 ;
input VAR8;
input VAR7;
supply1 VAR6;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
richard42/CoCo3FPGA
|
uart_6850.v
| 7,316 |
module MODULE1(
VAR39,
VAR59,
VAR7,
VAR21,
VAR25,
VAR52,
VAR47,
VAR46,
VAR28,
VAR1,
VAR26,
VAR36,
VAR16,
VAR14,
VAR4
);
input VAR39;
input VAR59;
input VAR7;
input VAR21;
input [7:0] VAR25;
output [7:0] VAR52;
output VAR47;
input VAR46;
input VAR1;
input VAR28;
output VAR26;
input VAR36;
output VAR16;
input VAR14;
input VAR4;
reg [7:0] VAR9;
reg [7:0] VAR15;
wire [7:0] VAR35;
reg [7:0] VAR18;
wire [7:0] VAR55;
reg [7:0] VAR40;
wire VAR29;
reg VAR2;
reg VAR56;
reg VAR22;
reg VAR19;
reg VAR45;
reg [1:0] VAR30;
wire VAR27;
reg VAR43;
reg VAR38;
reg [1:0] VAR6;
reg [1:0] VAR31;
wire VAR50;
wire VAR53;
reg VAR10;
wire VAR54;
reg VAR51;
reg VAR57;
wire [1:0] VAR8;
wire VAR20;
wire [1:0] VAR23;
wire VAR11;
wire VAR37;
wire VAR42;
wire VAR5;
always @ (negedge VAR7)
VAR6 <= VAR6 +1'b1;
always @ (posedge VAR59)
VAR31 <= VAR31 +1'b1;
assign VAR50 = (VAR8 == 2'b10) ? VAR6[1]:
VAR7;
assign VAR53 = (VAR8 == 2'b10) ? VAR31[1]:
VAR59;
assign VAR11 = (VAR8 == 2'b11) ? 1'b0:
VAR39;
assign VAR55 = {!VAR47, VAR57, VAR51, VAR10, VAR14, VAR4, VAR19, VAR45};
assign VAR52 = VAR1 ? VAR18[7:0]:
VAR55;
assign VAR47 = ({VAR40[7], VAR45} == 2'b11) ? 1'b0:
({VAR40[6:5], VAR19} == 3'b011) ? 1'b0: 1'b1;
assign VAR8 = VAR40[1:0];
assign VAR20 = VAR40[4];
assign VAR23 = VAR40[6:5];
assign VAR16 = (VAR23 == 2'b10);
assign VAR37 = (VAR40[4:2] == 3'b000) ? 1'b1:
(VAR40[4:2] == 3'b001) ? 1'b1:
(VAR40[4:2] == 3'b100) ? 1'b1: 1'b0;
assign VAR5 =(VAR40[4:2] == 3'b100) ? 1'b1:
(VAR40[4:2] == 3'b101) ? 1'b1: 1'b0;
always @ (negedge VAR21 or negedge VAR39)
begin
if(!VAR39)
VAR40 <= 8'h00;
end
else
if({VAR28, VAR46, VAR1} == 3'b010) VAR40 <= VAR25;
else
if(VAR8 == 2'b11)
VAR40 <= 8'h03;
end
always @ (negedge VAR21 or negedge VAR11)
begin
if(!VAR11)
begin
VAR45 <= 1'b0;
VAR30 <= 2'b00;
VAR18 <= 8'h00;
VAR9 <= 8'h00;
VAR19 <= 1'b1;
VAR22 <= 1'b0;
VAR51 <= 1'b0;
VAR10 <= 1'b0;
VAR57 <= 1'b0;
VAR56 <= 1'b1;
VAR2 <= 1'b1;
VAR38 <= 1'b0;
VAR43 <= 1'b0;
end
else
begin
VAR56 <= VAR2; VAR2 <= VAR29;
VAR38 <= VAR43;
VAR43 <= VAR27;
case (VAR30)
2'b00:
begin
if(VAR38) begin
VAR45 <= 1'b1;
VAR30 <= 2'b01;
VAR57 <= (VAR42 & !VAR5);
VAR51 <= 1'b0;
VAR10 <= VAR54;
VAR18 <= VAR35;
end
end
2'b01: begin
if({VAR28, VAR46, VAR1} == 3'b111)
begin
VAR45 <= 1'b0;
VAR30 <= 2'b10;
end
else begin
if(~VAR38)
VAR30 <= 2'b11;
end
end
2'b10: begin
if(~VAR38)
VAR30 <= 2'b00;
end
2'b11: begin
if({VAR28, VAR46, VAR1} == 3'b111)
begin
VAR45 <= 1'b0;
VAR30 <= 2'b00;
end
else
begin
if(VAR38) begin
VAR45 <= 1'b1;
VAR30 <= 2'b01;
VAR51 <= 1'b1;
VAR57 <= (VAR42 & !VAR5);
VAR10 <= VAR54;
VAR18 <= VAR35;
end
end
end
endcase
if(~VAR19 & VAR56 & ~VAR22 & ~VAR46)
begin
VAR9 <= VAR15;
VAR19 <= 1'b1;
VAR22 <= 1'b1;
end
else
begin
if({VAR28, VAR46, VAR1} == 3'b011) begin
VAR19 <= 1'b0;
VAR15 <= VAR25;
end
if(~VAR56)
begin
VAR22 <= 1'b0;
end
end
end
end
VAR34 VAR58(
.VAR17(VAR50),
.VAR39(VAR11),
.VAR26(VAR26),
.VAR22(VAR22),
.VAR29(VAR29),
.VAR13(VAR37),
.VAR49(VAR20),
.VAR24(VAR5),
.VAR33(VAR40[2]),
.VAR9(VAR9)
);
VAR48 VAR32(
.VAR39(VAR11),
.VAR17(VAR53),
.VAR36(VAR36),
.VAR35(VAR35),
.VAR41(VAR20),
.VAR44(VAR5),
.VAR12(VAR40[2]),
.VAR42(VAR42),
.VAR10(VAR54),
.VAR3(VAR27)
);
endmodule
|
bsd-3-clause
|
javierbrito29/papiGB
|
rtl/mmu.v
| 13,246 |
module MODULE1
(
input wire VAR48,
input wire VAR11,
input wire VAR37,
input wire [15:0] VAR88,
input wire VAR84,
input wire [7:0] VAR2,
output wire [7:0] VAR62,
output wire [7:0] VAR86,
input wire VAR83,
input wire [15:0] VAR30,
output wire [3:0] VAR102,
output wire [2:0] VAR92,
output wire [7:0] VAR81,
input wire [7:0] VAR28,
input wire [7:0] VAR70,
input wire [7:0] VAR94,
input wire [7:0] VAR20,
input wire [7:0] VAR27,
input wire [7:0] VAR80,
input wire [7:0] VAR42,
input wire [7:0] VAR15,
input wire [7:0] VAR90,
input wire [7:0] VAR96,
input wire [7:0] VAR98,
input wire [7:0] VAR97,
input wire [7:0] VAR43,
input wire [7:0] VAR51,
input wire [7:0] VAR61,
input wire [7:0] VAR7
);
wire [7:0] VAR82, VAR13, VAR21, VAR29, VAR104,VAR109,VAR101,VAR78;
wire [7:0] VAR87, VAR33;
wire [15:0] VAR69, VAR55;
wire VAR72, VAR93, VAR46, VAR36, VAR34, VAR49;
wire [3:0] VAR45, VAR66;
wire [7:0] VAR47, VAR71, VAR68, VAR1;
assign VAR34 = ( VAR70[7] & VAR94[1] ) ? 1'b1 : 1'b0 ;
assign VAR69 = VAR88;
assign VAR55 = ( VAR34 ) ? VAR30[12:0] : VAR88[12:0];
assign VAR81 = VAR2;
assign VAR86 = (VAR30[15:8] == 8'hfe) ? VAR1 : VAR71;
VAR63 # (8) VAR52
(
.VAR9( VAR69[15:12] ),
.VAR26(VAR47), .VAR35(VAR47),
.VAR56(VAR47), .VAR53(VAR47),
.VAR76(VAR47), .VAR44(VAR47),
.VAR38(VAR47), .VAR74(VAR47),
.VAR19(VAR71), .VAR22(VAR71),
.VAR4(8'b0), .VAR89(8'b0),
.VAR106( VAR21 ), .VAR103( VAR21 ), .VAR17(VAR47 ),
.VAR14( VAR68 ),
.VAR95( VAR62 )
);
VAR63 # (8) VAR107
(
.VAR9( VAR69[11:8] ),
.VAR26(8'b0), .VAR35(8'b0), .VAR56(8'b0), .VAR53(8'b0), .VAR76(8'b0), .VAR44(8'b0), .VAR38(8'b0), .VAR74(8'b0), .VAR19(8'b0), .VAR22(8'b0), .VAR4(8'b0), .VAR89(8'b0), .VAR106(8'b0), .VAR103(8'b0), .VAR17( VAR1),
.VAR14( VAR29 ),
.VAR95( VAR68 )
);
wire [7:0] VAR16;
VAR6 # (8) VAR40
(
.VAR9( VAR69[7:6]),
.VAR26( VAR104 ), .VAR35( VAR104 ), .VAR56( VAR13 ), .VAR53( VAR16 ), .VAR95( VAR29 )
);
assign VAR16 =
( VAR69 == 16'hffff ) ? VAR51 : VAR13;
VAR100 # (8) VAR5
(
.VAR9( VAR69[6:4]),
.VAR26( VAR33 ), .VAR35( VAR101 ), .VAR56( VAR78 ), .VAR53( VAR87 ), .VAR76( VAR109 ), .VAR44( 8'b0 ),
.VAR38( 8'b0 ),
.VAR74( 8'b0 ),
.VAR95( VAR104 )
);
VAR59 # ( .VAR23(8), .VAR3(13), .VAR73(8192) ) VAR57
(
.VAR31( VAR48 ),
.VAR75( VAR36 ),
.VAR24( VAR55[12:0] ),
.VAR91( VAR69[12:0] ),
.VAR79( VAR2 ),
.VAR12( VAR71 )
);
VAR59 # ( .VAR23(8), .VAR3(8), .VAR73(160) ) VAR32
(
.VAR31( VAR48 ),
.VAR75( VAR36 ), .VAR24( VAR55[7:0] ),
.VAR91( VAR69[7:0] ),
.VAR79( VAR2 ),
.VAR12( VAR1 )
);
VAR59 # ( .VAR23(8), .VAR3(7), .VAR73(128) ) VAR99
(
.VAR31( VAR48 ),
.VAR75( VAR46 ),
.VAR24( VAR69[6:0] ),
.VAR91( VAR69[6:0] ),
.VAR79( VAR2 ),
.VAR12( VAR13 )
);
wire VAR18;
wire [7:0] VAR60;
assign VAR18 = (VAR84 && VAR88 == 4'hff50) ? 1'b1: 1'b0;
VAR67 # ( 8 )VAR41(
VAR48, VAR11 , VAR18, VAR2, VAR60 );
VAR59 # ( .VAR23(8), .VAR3(13), .VAR73(8191) ) VAR58
(
.VAR31( VAR48 ),
.VAR75( VAR49 ),
.VAR24( VAR69[12:0] ),
.VAR91( VAR69[12:0] ),
.VAR79( VAR2 ),
.VAR12( VAR21 )
);
assign VAR102 = ( &VAR88 ) ? 4'b0 : VAR69[3:0];
wire [7:0] VAR85;
VAR39 VAR8((VAR37 == 1'b1 && VAR69 == 16'hff44) ,VAR85);
VAR63 # (8) VAR25
(
.VAR9( VAR69[3:0]),
.VAR26( VAR70 ),
.VAR35( VAR94 ),
.VAR56( VAR20 ),
.VAR53( VAR27 ),
.VAR76( VAR85 ),
.VAR76( VAR80 ),
.VAR44( VAR42 ),
.VAR38( VAR15 ),
.VAR74( VAR90 ),
.VAR19( VAR96 ),
.VAR22( VAR98 ),
.VAR4( VAR97 ),
.VAR89( VAR43 ),
.VAR106( 8'b0 ),
.VAR103( 8'b0 ),
.VAR17( 8'b0 ),
.VAR14( 8'b0 ),
.VAR95( VAR109 )
);
VAR63 # (8) VAR10
(
.VAR9( VAR69[3:0]),
.VAR26( VAR7 ), .VAR35(8'b0 ), .VAR56(8'b0 ), .VAR53(8'b0 ), .VAR76(8'b0 ), .VAR44(8'b0 ), .VAR38(8'b0 ), .VAR74(8'b0 ), .VAR19(8'b0 ), .VAR22(8'b0 ), .VAR4(8'b0 ), .VAR89(8'b0 ), .VAR106(8'b0 ), .VAR103(8'b0 ), .VAR17(8'b0 ), .VAR14(VAR61 ), .VAR95( VAR33 )
);
VAR77 VAR50
(
.VAR48( VAR48 ),
.VAR108( VAR88[7:0] ),
.VAR105( VAR82 )
);
assign VAR46 = ( VAR84 && VAR69[15:12] == 4'hf && VAR69[11:8] == 4'hf && (VAR69[7:6] == 2'h2 || VAR69[7:6] == 2'h3) ) ? 1'b1 : 1'b0 ;
assign VAR36 = ( VAR84 && (VAR69[15:12] == 4'h8 || VAR69[15:12] == 4'h9 ) ) ? 1'b1 : 1'b0;
assign VAR92[0] = ( VAR84 && VAR69[15:4] == 12'hff4 ) ? 1'b1 : 1'b0; assign VAR92[1] = ( VAR84 && VAR69[15:4] == 12'hff0 ) ? 1'b1 : 1'b0; assign VAR92[2] = ( VAR84 & (&VAR69 | VAR69 == 16'hff0f) ) ? 1'b1 : 1'b0; assign VAR49 = ( VAR84 && VAR69[15:13] == 3'h6 ) ? 1'b1 : 1'b0;
assign VAR72 = (VAR69 & 16'hff00) ? 1'b0 : 1'b1; assign VAR93 = (VAR69 & 16'hc000) ? 1'b0 : 1'b1;
wire [7:0] VAR54;
assign VAR47 = (VAR72 & ~VAR60[0] ) ? VAR82 : VAR54;
MODULE2 VAR64
(
.VAR108( VAR69 ),
.VAR105( VAR54 )
);
endmodule
module MODULE2
(
input wire [15:0] VAR108,
output reg [7:0] VAR105
);
reg [7:0] VAR65[65534:0];
always @ (VAR108)
begin
end
begin
begin
begin
begin
|
gpl-2.0
|
onchipuis/mriscv_vivado
|
mriscv_vivado.srcs/sources_1/new/ADC_interface_AXI_XADC.v
| 7,607 |
module MODULE1 (
input VAR57,
input VAR90,
input VAR10,
output VAR7,
input [32-1:0] VAR54,
input [3-1:0] VAR42,
input VAR40,
output VAR65,
input [32-1:0] VAR36,
input [4-1:0] VAR95,
output reg VAR19,
input VAR18,
input VAR48,
output VAR84,
input [32-1:0] VAR89,
input [3-1:0] VAR3,
output reg VAR41,
input VAR37,
output reg [32-1:0] VAR46,
output [7:0] VAR51,
output VAR22,
output VAR43,
output VAR86);
wire VAR31, VAR9;
wire VAR67;
wire [4:0] VAR30;
wire VAR91;
reg [6:0] VAR35;
reg [15:0] VAR78;
wire [15:0] VAR44;
reg [1:0] VAR93;
reg [1:0] VAR11;
wire VAR15;
assign VAR15 = ~VAR90;
reg [31:0] VAR24, VAR23;
reg [31:0] VAR88;
reg [3:0] VAR64;
reg [1:0] VAR92;
reg VAR55;
assign VAR7 = 1'b1;
assign VAR84 = 1'b1;
assign VAR65 = 1'b1;
always @(posedge VAR57)
begin : VAR2
if(VAR90 == 1'b0) begin
VAR24 <= 0;
VAR23 <= 0;
VAR88 <= 0;
VAR64 <= 0;
VAR92 <= 2'b00;
VAR55 <= 1'b0;
end else begin
if(VAR19) begin VAR24 <= VAR24;
VAR92[0] <= 1'b0;
end else if(VAR10) begin
VAR24 <= VAR54;
VAR92[0] <= 1'b1;
end else begin
VAR24 <= VAR24;
VAR92[0] <= VAR92[0];
end
if(VAR19) begin VAR88 <= VAR88;
VAR64 <= VAR64;
VAR92[1] <= 1'b0;
end else if(VAR40) begin
VAR88 <= VAR36;
VAR64 <= VAR95;
VAR92[1] <= 1'b1;
end else begin
VAR88 <= VAR88;
VAR64 <= VAR64;
VAR92[1] <= VAR92[1];
end
if(VAR41) begin VAR23 <= VAR23;
VAR55 <= 1'b0;
end else if(VAR48) begin
VAR23 <= VAR89;
VAR55 <= 1'b1;
end else begin
VAR23 <= VAR23;
VAR55 <= VAR55;
end
end
end
parameter VAR20 = 8'h00,
VAR8 = 8'h01,
VAR25 = 8'h03,
VAR73 = 8'h04,
VAR47 = 8'h05,
VAR77 = 8'h06,
VAR59 = 8'h07,
VAR14 = 8'h08,
VAR52 = 8'h09,
VAR4 = 8'h0A;
reg [7:0] state;
always @(posedge VAR57)
if (VAR90 == 1'b0) begin
state <= VAR20;
VAR93 <= 2'h0;
VAR11 <= 2'h0;
VAR78 <= 16'h0000;
VAR35 <= 0;
VAR46 <= 0;
VAR19 <= 1'b0;
VAR41 <= 1'b0;
end else case (state)
VAR20 : begin
VAR35 <= 7'h40; VAR93 <= 2'h2; if (VAR67 == 0 ) state <= VAR8;
end
VAR8 :
if (VAR91 ==1) begin
VAR78 <= VAR44 & 16'h03FF; VAR35 <= 7'h40;
VAR93 <= 2'h2;
VAR11 <= 2'h2; state <= VAR25;
end else begin
VAR93 <= { 1'b0, VAR93[1] } ;
VAR11 <= { 1'b0, VAR11[1] } ;
state <= state;
end
VAR25 :
if (VAR91 ==1) begin
state <= VAR73;
end else begin
VAR93 = { 1'b0, VAR93[1] } ;
VAR11 = { 1'b0, VAR11[1] } ;
state <= state;
end
VAR73 :
if (VAR55) begin
state <= VAR47;
end else if(VAR92 == 2'b11) begin
state <= VAR59;
end else begin
state <= state;
end
VAR47 : begin
VAR35 = VAR23[8:2];
VAR93 = 2'h2; if (VAR9 == 1) state <=VAR77;
end
VAR77 :
if (VAR91 ==1) begin
VAR46 <= {15'd0, VAR44};
VAR41 <= 1'b1;
state <= VAR52;
end else begin
VAR93 = { 1'b0, VAR93[1] } ;
VAR11 = { 1'b0, VAR11[1] } ;
state <= state;
end
VAR52 :
if (VAR37 ==1) begin
VAR41 <= 1'b0;
state <= VAR73;
end else begin
state <= state;
end
VAR59 : begin
VAR78 <= VAR88[15:0];
VAR35 <= VAR24[8:2];
VAR93 <= 2'h2;
VAR11 <= 2'h2; state <= VAR14;
end
VAR14 :
if (VAR91 ==1) begin
VAR19 <= 1'b1;
state <= VAR4;
end else begin
VAR93 <= { 1'b0, VAR93[1] } ;
VAR11 <= { 1'b0, VAR11[1] } ;
state <= state;
end
VAR4 :
if (VAR18 ==1) begin
VAR19 <= 1'b0;
state <= VAR73;
end else begin
state <= state;
end
default: begin
state <= VAR20; end
endcase
wire [15:0] VAR68;
wire [15:0] VAR34;
assign VAR68 = 16'h0000; assign VAR34 = 16'h0000;
VAR53 #(
.VAR1(16'h9000), .VAR50(16'h2ef0), .VAR94(16'h0400), .VAR38(16'h4701), .VAR60(16'h000f), .VAR75(16'h0000), .VAR83(16'h0000), .VAR29(16'h0000), .VAR87(16'h0000), .VAR33(16'h0000), .VAR58(16'h0000), .VAR72(16'hb5ed), .VAR32(16'h5999), .VAR49(16'hA147), .VAR61(16'hdddd), .VAR45(16'ha93a), .VAR79(16'h5111), .VAR26(16'h91Eb), .VAR13(16'hae4e), .VAR80(16'h5999), .VAR81("VAR63.VAR5") )
VAR70 ( .VAR17(VAR15),
.VAR27(VAR57),
.VAR56 (VAR35),
.VAR28 (VAR93[0]),
.VAR12 (VAR78),
.VAR62 (VAR11[0]),
.VAR82 (VAR44),
.VAR76 (VAR91),
.VAR16 (VAR34 ),
.VAR6 (VAR68 ),
.VAR51 (VAR51),
.VAR66 (VAR67),
.VAR30(VAR30),
.VAR9 (VAR9),
.VAR31 (VAR31),
.VAR74 (), .VAR85 (), .VAR69 (), .VAR22 (VAR22),
.VAR21 (), .VAR71 (VAR71),
.VAR39 (VAR39)
);
assign VAR43 = VAR9;
assign VAR86 = VAR31;
endmodule
|
mit
|
ShepardSiegel/ocpi
|
coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_rank_timer.v
| 113,359 |
module MODULE1 #
( parameter
VAR12 = 2,
VAR24 = 4,
VAR56 = "VAR136",
VAR102 = 1,
VAR35 = 1,
VAR163 = 4,
VAR98 = 2,
VAR164 = 0,
VAR29 = 0,
VAR156 = 0,
VAR90 = 0,
VAR126 = 5,
VAR123 = 0,
VAR204 = 0,
VAR100 = 0,
VAR39 = 0,
VAR112 = 0,
VAR114 = 0,
VAR181 = 0,
VAR69 = 0,
VAR139 = 0,
VAR132 = 0,
VAR61 = 0,
VAR36 = 0
)
(
VAR217,
VAR62,
VAR157,
VAR200,
VAR161,
VAR166,
VAR14,
VAR87,
VAR127,
VAR185,
VAR197,
VAR188,
VAR146,
VAR7,
VAR67,
VAR169,
VAR31,
VAR43,
VAR81,
VAR6,
VAR172,
VAR49,
VAR174,
VAR107,
VAR38,
VAR26,
VAR18,
VAR33,
VAR221,
VAR89,
VAR124,
VAR27
);
input VAR217;
input VAR62;
input [VAR126 - 1 : 0] VAR157;
input [VAR123 - 1 : 0] VAR200;
input [VAR204 - 1 : 0] VAR161;
input [VAR100 - 1 : 0] VAR166;
input [VAR39 - 1 : 0] VAR14;
input [VAR112 - 1 : 0] VAR87;
input [VAR114 - 1 : 0] VAR127;
input [VAR181 - 1 : 0] VAR185;
input [VAR69 - 1 : 0] VAR197;
input [VAR139 - 1 : 0] VAR188;
input [VAR132 - 1 : 0] VAR146;
input [VAR61 - 1 : 0] VAR7;
input [VAR36 - 1 : 0] VAR67;
input [VAR98 - 1 : 0] VAR169;
input [VAR98 - 1 : 0] VAR31;
input [VAR98 - 1 : 0] VAR43;
input [VAR98 - 1 : 0] VAR81;
input [VAR98 - 1 : 0] VAR6;
input [VAR98 - 1 : 0] VAR172;
input [(VAR98 * VAR102) - 1 : 0] VAR49;
input [VAR163 - 1 : 0] VAR174;
input VAR107;
input [VAR35 - 1 : 0] VAR38;
input [(VAR24 * VAR35) - 1 : 0] VAR26;
input [VAR24 - 1 : 0] VAR18;
input [VAR102 - 1 : 0] VAR33;
output [VAR24 - 1 : 0] VAR221;
output [VAR24 - 1 : 0] VAR89;
output [VAR24 - 1 : 0] VAR124;
output [VAR24 - 1 : 0] VAR27;
localparam VAR141 = (VAR90) ? ((VAR156) ? 4 : 3) : ((VAR156) ? 3 : 2);
localparam VAR95 = (VAR90) ? ((VAR156) ? 2 : 1) : ((VAR156) ? 1 : 0);
localparam VAR37 = 0;
wire VAR109 = 1'b1;
wire VAR223 = 1'b0;
reg VAR115;
reg VAR93;
reg VAR219;
reg VAR94;
reg VAR193;
reg VAR212;
reg VAR2;
reg VAR66;
reg VAR144;
reg VAR186;
reg VAR59;
reg VAR122;
reg VAR32;
reg VAR48;
reg VAR88;
reg VAR13;
reg VAR167;
reg VAR154;
reg VAR76;
reg VAR60;
reg VAR40;
reg VAR152;
reg VAR153;
reg VAR143;
reg VAR20;
reg VAR196;
reg VAR220;
reg VAR191;
reg VAR133;
reg VAR120;
reg VAR130;
reg VAR41;
reg VAR77;
reg VAR99;
reg VAR72;
reg VAR17;
reg VAR97;
reg VAR211;
reg VAR142;
reg VAR53;
reg VAR129;
reg VAR19;
reg VAR192;
reg VAR187;
reg VAR121;
reg VAR149;
reg VAR63;
reg VAR64;
reg VAR42;
reg VAR222;
reg VAR91;
reg VAR147;
reg VAR202;
reg VAR201;
reg VAR194;
reg VAR105;
reg VAR209;
reg VAR51;
reg VAR84;
reg VAR28;
reg VAR213;
reg VAR82;
reg VAR1;
reg VAR58;
reg VAR184;
reg VAR108;
reg VAR177;
reg VAR57;
reg VAR207;
reg VAR173;
reg VAR92;
reg VAR4;
reg VAR165;
reg VAR22;
reg VAR215;
reg VAR189;
reg VAR15;
reg VAR214;
reg VAR16;
reg VAR180;
reg VAR199;
reg VAR145;
reg VAR151;
reg VAR52;
reg VAR68;
reg VAR160;
reg VAR171;
reg VAR103;
reg VAR86;
reg VAR101;
reg VAR9;
reg VAR131;
reg VAR5;
reg VAR128;
reg [VAR102 - 1 : 0] VAR55;
reg [VAR102 - 1 : 0] VAR73;
reg [VAR163 - 1 : 0] VAR106;
reg VAR23;
localparam VAR117 = VAR204;
localparam VAR182 = 3;
localparam VAR190 = 2 ** VAR123;
reg [VAR102 - 1 : 0] VAR138;
reg [VAR102 - 1 : 0] VAR104;
reg [VAR102 - 1 : 0] VAR137;
reg [VAR102 - 1 : 0] VAR25;
reg [VAR102 - 1 : 0] VAR8;
wire [VAR182 - 1 : 0] VAR11 [VAR102 - 1 : 0];
localparam VAR85 = 32'h49444C45;
localparam VAR205 = 32'h20205752;
localparam VAR21 = 32'h20205244;
localparam VAR96 = (VAR132 > VAR112) ? VAR132 : VAR112;
reg [VAR163 - 1 : 0] VAR208;
reg [VAR132 - 1 : 0] VAR70;
reg [VAR36 - 1 : 0] VAR162;
reg [VAR112 - 1 : 0] VAR203;
reg [VAR181 - 1 : 0] VAR119;
reg [VAR132 - 1 : 0] VAR183;
reg [VAR36 - 1 : 0] VAR54;
reg [VAR112 - 1 : 0] VAR150;
reg [VAR181 - 1 : 0] VAR3;
reg [VAR102 - 1 : 0] VAR140;
reg [VAR102 - 1 : 0] VAR110;
reg [VAR102 - 1 : 0] VAR206;
reg [VAR24 - 1 : 0] VAR175;
reg [VAR24 - 1 : 0] VAR218;
reg [VAR24 - 1 : 0] VAR159;
reg [VAR24 - 1 : 0] VAR30;
reg [VAR24 - 1 : 0] VAR221;
reg [VAR24 - 1 : 0] VAR89;
reg [VAR24 - 1 : 0] VAR124;
reg [VAR24 - 1 : 0] VAR27;
reg [VAR123 - 1 : 0] VAR155;
always @
begin
VAR101 = |VAR172;
end
always @
begin
VAR131 = |VAR81;
end
always @
begin
VAR128 = |VAR31;
end
always @
begin
VAR106 = VAR174;
end
always @
begin
if (VAR90 && VAR18 [VAR176])
begin
VAR216 = VAR38;
end
else
begin
VAR216 = VAR26 [(VAR176 + 1) * VAR35 - 1 : VAR176 * VAR35];
end
end
if (VAR90)
begin
always @
begin
VAR221 [VAR176] = VAR8 [VAR216];
end
always @
begin
VAR124 [VAR176] = VAR140 [VAR216];
end
always @
begin
if (VAR90)
begin
VAR105 = VAR93;
VAR209 = VAR13;
VAR51 = VAR167;
VAR84 = VAR154;
VAR28 = VAR76;
VAR213 = VAR60;
VAR82 = VAR40;
VAR1 = VAR152;
VAR58 = VAR153;
VAR184 = VAR143;
VAR108 = VAR20;
VAR177 = VAR219;
VAR57 = VAR196;
VAR207 = VAR220;
VAR173 = VAR191;
VAR92 = VAR133;
VAR4 = VAR120;
VAR165 = VAR130;
VAR22 = VAR41;
VAR215 = VAR77;
VAR189 = VAR99;
VAR15 = VAR72;
VAR214 = VAR94;
VAR16 = VAR17;
VAR180 = VAR97;
VAR199 = VAR211;
VAR145 = VAR142;
VAR151 = VAR53;
VAR52 = VAR129;
VAR68 = VAR19;
VAR160 = VAR192;
VAR171 = VAR187;
VAR103 = VAR121;
end
else
begin
VAR105 = VAR93;
VAR209 = VAR13;
VAR51 = VAR167;
VAR84 = VAR154;
VAR28 = VAR76;
VAR213 = VAR60;
VAR82 = VAR40;
VAR1 = VAR152;
VAR58 = VAR153;
VAR184 = VAR143;
VAR108 = VAR20;
VAR177 = VAR93;
VAR57 = VAR13;
VAR207 = VAR167;
VAR173 = VAR154;
VAR92 = VAR76;
VAR4 = VAR60;
VAR165 = VAR40;
VAR22 = VAR152;
VAR215 = VAR153;
VAR189 = VAR143;
VAR15 = VAR20;
VAR214 = VAR219;
VAR16 = VAR196;
VAR180 = VAR220;
VAR199 = VAR191;
VAR145 = VAR133;
VAR151 = VAR120;
VAR52 = VAR130;
VAR68 = VAR41;
VAR160 = VAR77;
VAR171 = VAR99;
VAR103 = VAR72;
end
end
end
else
begin
always @
begin
if (VAR193)
begin
VAR104 [VAR74] = 1'b1;
end
else
begin
if (VAR86 && VAR55 [VAR74] && VAR71 == 3'd3)
VAR104 [VAR74] = 1'b0;
end
else if (VAR71 < 3'd4)
VAR104 [VAR74] = 1'b1;
end
else
VAR104 [VAR74] = 1'b0;
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR138 [VAR74] <= 1'b0;
end
else
begin
VAR138 [VAR74] <= VAR104 [VAR74];
end
end
reg [VAR117 - 1 : 0] VAR80;
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR80 <= 0;
end
else
begin
if (VAR86 && VAR55 [VAR74])
begin
if (VAR37)
begin
VAR80 <= VAR141 - 1;
end
else
begin
VAR80 <= VAR141;
end
end
else if (VAR80 != {VAR117{1'b1}})
begin
VAR80 <= VAR80 + 1'b1;
end
end
end
always @
begin
if (!VAR90 && VAR33 [VAR74])
begin
VAR8 [VAR74] = 1'b0;
end
else
begin
if (VAR37)
begin
VAR8 [VAR74] = VAR25 [VAR74] & VAR104 [VAR74];
end
else
begin
VAR8 [VAR74] = VAR137 [VAR74] & VAR138 [VAR74];
end
end
end
end
endgenerate
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR208 <= 0;
end
else
begin
VAR208 <= VAR157 / VAR12;
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR183 <= 0;
VAR54 <= 0;
VAR150 <= 0;
VAR3 <= 0;
end
else
begin
if (VAR9)
begin
VAR183 <= VAR7;
VAR54 <= VAR67;
VAR150 <= VAR127;
VAR3 <= VAR185;
end
else if (VAR131)
begin
if (VAR146 > (VAR208 - VAR106))
VAR183 <= VAR146 - (VAR208 - VAR106);
end
else
VAR183 <= 1'b1;
if (VAR67 > (VAR208 - VAR106))
VAR54 <= VAR67 - (VAR208 - VAR106);
end
else
VAR54 <= 1'b1;
if (VAR87 > (VAR208 - VAR106))
VAR150 <= VAR87 - (VAR208 - VAR106);
end
else
VAR150 <= 1'b1;
if (VAR185 > (VAR208 - VAR106))
VAR3 <= VAR185 - (VAR208 - VAR106);
else
VAR3 <= 1'b1;
end
end
end
generate
genvar VAR135;
for (VAR135 = 0;VAR135 < VAR102;VAR135 = VAR135 + 1)
begin : VAR113
reg [31 : 0] VAR178;
reg [VAR96 - 1 : 0] VAR78;
reg [VAR96 - 1 : 0] VAR116;
reg [VAR96 - 1 : 0] VAR158;
reg [VAR96 - 1 : 0] VAR111;
reg VAR125;
reg VAR170;
reg VAR34;
reg VAR10;
reg VAR79;
reg VAR179;
reg VAR65;
reg VAR46;
always @
begin
if (VAR5)
begin
if (VAR73 [VAR135])
begin
VAR170 = 1'b1;
VAR10 = 1'b0;
end
else
begin
VAR170 = 1'b0;
VAR10 = 1'b1;
end
end
else
begin
VAR170 = 1'b0;
VAR10 = 1'b0;
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR78 <= 0;
VAR116 <= 0;
end
else
begin
if (VAR125)
VAR78 <= VAR141;
end
else if (VAR78 != {VAR96{1'b1}})
VAR78 <= VAR78 + 1'b1;
if (VAR170)
VAR116 <= VAR141;
end
else if (VAR116 != {VAR96{1'b1}})
VAR116 <= VAR116 + 1'b1;
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR158 <= 0;
VAR111 <= 0;
end
else
begin
if (VAR34)
VAR158 <= VAR141;
end
else if (VAR158 != {VAR96{1'b1}})
VAR158 <= VAR158 + 1'b1;
if (VAR10)
VAR111 <= VAR141;
end
else if (VAR111 != {VAR96{1'b1}})
VAR111 <= VAR111 + 1'b1;
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR79 <= 1'b0;
end
else
begin
if (VAR128 || VAR5)
begin
if (VAR9)
VAR79 <= 1'b1;
end
else
VAR79 <= 1'b0;
end
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR179 <= 1'b0;
end
else
begin
if (VAR128 || VAR5)
VAR179 <= 1'b0;
end
else if (VAR131)
VAR179 <= 1'b1;
end
end
reg VAR45;
reg VAR168;
reg VAR83;
reg VAR47;
reg VAR75;
reg VAR44;
reg VAR210;
reg VAR195;
reg VAR118;
reg VAR148;
reg VAR134;
reg VAR198;
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR45 <= 1'b0;
VAR168 <= 1'b0;
VAR83 <= 1'b0;
VAR47 <= 1'b0;
VAR75 <= 1'b0;
VAR44 <= 1'b0;
VAR210 <= 1'b0;
VAR195 <= 1'b0;
end
else
begin
if (VAR125)
begin
if (VAR16)
begin
VAR45 <= 1'b1;
end
else
begin
VAR45 <= 1'b0;
end
if (VAR180)
begin
VAR83 <= 1'b1;
end
else
begin
VAR83 <= 1'b0;
end
end
else
begin
if (VAR78 >= (VAR197 - 1'b1))
begin
VAR45 <= 1'b1;
end
else
begin
VAR45 <= 1'b0;
end
if (VAR78 >= (VAR146 - 1'b1))
begin
VAR83 <= 1'b1;
end
else
begin
VAR83 <= 1'b0;
end
end
if (VAR34)
begin
if (VAR68)
begin
VAR168 <= 1'b1;
end
else
begin
VAR168 <= 1'b0;
end
if (VAR160)
begin
VAR47 <= 1'b1;
end
else
begin
VAR47 <= 1'b0;
end
end
else
begin
if (VAR158 >= (VAR188 - 1'b1))
begin
VAR168 <= 1'b1;
end
else
begin
VAR168 <= 1'b0;
end
if (VAR158 >= (VAR67 - 1'b1))
begin
VAR47 <= 1'b1;
end
else
begin
VAR47 <= 1'b0;
end
end
if (VAR170)
begin
if (VAR199)
begin
VAR75 <= 1'b1;
end
else
begin
VAR75 <= 1'b0;
end
if (VAR145)
begin
VAR210 <= 1'b1;
end
else
begin
VAR210 <= 1'b0;
end
end
else
begin
if (VAR116 >= (VAR166 - 1'b1))
begin
VAR75 <= 1'b1;
end
else
begin
VAR75 <= 1'b0;
end
if (VAR116 >= (VAR87 - 1'b1))
begin
VAR210 <= 1'b1;
end
else
begin
VAR210 <= 1'b0;
end
end
if (VAR10)
begin
if (VAR171)
begin
VAR44 <= 1'b1;
end
else
begin
VAR44 <= 1'b0;
end
if (VAR103)
begin
VAR195 <= 1'b1;
end
else
begin
VAR195 <= 1'b0;
end
end
else
begin
if (VAR111 >= (VAR14 - 1'b1))
begin
VAR44 <= 1'b1;
end
else
begin
VAR44 <= 1'b0;
end
if (VAR111 >= (VAR185 - 1'b1))
begin
VAR195 <= 1'b1;
end
else
begin
VAR195 <= 1'b0;
end
end
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR118 <= 1'b0;
VAR148 <= 1'b0;
VAR134 <= 1'b0;
VAR198 <= 1'b0;
end
else
begin
if (VAR125)
begin
if (VAR146 <= VAR141)
begin
VAR118 <= 1'b1;
end
else
begin
VAR118 <= 1'b0;
end
end
else
begin
if (VAR78 >= (VAR183 - 1'b1))
begin
VAR118 <= 1'b1;
end
else
begin
VAR118 <= 1'b0;
end
end
if (VAR34)
begin
if (VAR67 <= VAR141)
begin
VAR148 <= 1'b1;
end
else
begin
VAR148 <= 1'b0;
end
end
else
begin
if (VAR158 >= (VAR54 - 1'b1))
begin
VAR148 <= 1'b1;
end
else
begin
VAR148 <= 1'b0;
end
end
if (VAR170)
begin
if (VAR87 <= VAR141)
begin
VAR134 <= 1'b1;
end
else
begin
VAR134 <= 1'b0;
end
end
else
begin
if (VAR116 >= (VAR150 - 1'b1))
begin
VAR134 <= 1'b1;
end
else
begin
VAR134 <= 1'b0;
end
end
if (VAR10)
begin
if (VAR185 <= VAR141)
begin
VAR198 <= 1'b1;
end
else
begin
VAR198 <= 1'b0;
end
end
else
begin
if (VAR111 >= (VAR3 - 1'b1))
begin
VAR198 <= 1'b1;
end
else
begin
VAR198 <= 1'b0;
end
end
end
end
always @ (posedge VAR217 or negedge VAR62)
begin
if (!VAR62)
begin
VAR178 <= VAR85;
VAR65 <= 1'b0;
VAR46 <= 1'b0;
end
else
begin
case (VAR178)
VAR85 :
begin
if (VAR170)
begin
VAR178 <= VAR205;
if (VAR9) begin
if (VAR165)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
end
else
begin
if (VAR92)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
end
if (VAR173)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
else if (VAR10)
begin
VAR178 <= VAR205;
if (VAR15)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR189)
VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else if (VAR125)
begin
VAR178 <= VAR21;
if (VAR57)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR9) begin
if (VAR4)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
else
begin
if (VAR207)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
end
else if (VAR34)
begin
VAR178 <= VAR21;
if (VAR22)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR215)
VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else
begin
VAR178 <= VAR85;
VAR65 <= 1'b1;
VAR46 <= 1'b1;
end
end
VAR205 :
begin
if (VAR170)
begin
VAR178 <= VAR205;
if (VAR9) begin
if (VAR165)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
end
else
begin
if (VAR92)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
end
if (VAR173)
VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else if (VAR10)
begin
VAR178 <= VAR205;
if (VAR15 && VAR210) VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR189 && VAR83) VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else if (VAR125)
begin
VAR178 <= VAR21;
if (VAR57)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR9) begin
if (VAR4)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
else
begin
if (VAR207)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
end
else if (VAR34)
begin
VAR178 <= VAR21;
if (VAR22 && VAR210) VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR215 && VAR83) VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else
begin
if (VAR79 || VAR179) begin
if (VAR134 && VAR45 &&
VAR198 && VAR168 )
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR75 && VAR118 &&
VAR44 && VAR148 )
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
else
begin
if (VAR210 && VAR45 &&
VAR195 && VAR168 )
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR75 && VAR83 &&
VAR44 && VAR47 )
VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
end
end
VAR21 :
begin
if (VAR170)
begin
VAR178 <= VAR205;
if (VAR9) begin
if (VAR165)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
end
else
begin
if (VAR92)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
end
if (VAR173)
VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else if (VAR10)
begin
VAR178 <= VAR205;
if (VAR15 && VAR134) VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR189 && VAR83) VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else if (VAR125)
begin
VAR178 <= VAR21;
if (VAR57)
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR9) begin
if (VAR4)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
else
begin
if (VAR207)
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
end
else if (VAR34)
begin
VAR178 <= VAR21;
if (VAR22 && VAR134) VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR215 && VAR83) VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
else
begin
if (VAR79 || VAR179) begin
if (VAR45 && VAR134 &&
VAR168 && VAR198 )
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR118 && VAR75 &&
VAR148 && VAR44 )
VAR46 <= 1'b1;
end
else
VAR46 <= 1'b0;
end
else
begin
if (VAR45 && VAR210 &&
VAR168 && VAR195 )
VAR65 <= 1'b1;
end
else
VAR65 <= 1'b0;
if (VAR83 && VAR75 &&
VAR47 && VAR44)
VAR46 <= 1'b1;
else
VAR46 <= 1'b0;
end
end
end
default :
VAR178 <= VAR85;
endcase
end
end
always @
begin
if (!VAR90 && VAR33 [VAR50])
VAR206 [VAR50] = 1'b0;
end
else
VAR206 [VAR50] = VAR109;
end
end
endgenerate
endmodule
|
lgpl-3.0
|
glennchid/font5-firmware
|
src/verilog/synthesis/timing_synch_fsm.v
| 22,772 |
module MODULE1 #(parameter VAR77 = 2.8) (
input VAR35,
input VAR36,
input VAR3, input VAR24,
input VAR27,
input [11:0] VAR64,
input [6:0] VAR46,
input [9:0] VAR2,
input [7:0] VAR44,
input VAR8,
input [6:0] VAR75,
input [6:0] VAR41,
output reg VAR82 = 1'b0,
output reg VAR10 = 1'b0,
output reg VAR53 = 1'b0,
output reg VAR29 = 1'b0,
output reg VAR30 = 1'b0,
output reg VAR63 = 1'b0,
output reg VAR5 = 1'b0,
output reg [3:0] state = 4'b0100
output reg [3:0] state = 4'b0000
);
localparam [11:0] VAR17 = (9240/VAR77);
localparam VAR45 = 1'd0;
reg VAR15=0;
reg VAR51 = 1'b0, VAR40 = 1'b0, VAR76 = 1'b0;
reg VAR59 = 1'b0, VAR61 = 1'b0;
reg [11:0] VAR32 = 12'd0, VAR70 = 12'd0;
reg [6:0] VAR72 = 7'd0, VAR16 = 7'd0;
reg [9:0] VAR19 = 10'd164, VAR6 = 10'd164;
reg [7:0] VAR55 = 8'd0, VAR71 = 8'd0;
reg VAR1 = 1'b0, VAR14 = 1'b0;
always @(posedge VAR35) begin
VAR59 <= VAR24;
VAR61 <= VAR59;
VAR32 <= VAR64;
VAR70 <= VAR32;
VAR72 <= VAR46;
VAR16 <= VAR72;
VAR15 <= VAR3;
VAR51 <= VAR15;
VAR40 <= VAR51;
VAR76 <= VAR40;
VAR19 <= VAR2;
VAR6 <= VAR19;
VAR55 <= VAR71;
VAR71 <= VAR44;
VAR1 <= VAR14;
VAR14 <= VAR8;
end
assign VAR33 = VAR61 ? (VAR40 & ~VAR76) : (~VAR40 & VAR76);
reg VAR22 = 1'b0;
reg VAR34 = 1'b0;
reg [7:0] VAR67 = 8'd0;
always @(posedge VAR35) begin
if (~VAR22 && VAR1) VAR22 <= VAR33;
end
else if (~VAR22) VAR22 <= 1'b1;
else VAR22 <= VAR22;
if (~VAR22) begin
VAR67 <= 8'd0;
VAR34 <= 1'b0;
end
else begin
if (VAR67==VAR55 || (VAR33 && VAR45)) begin
VAR67 <= 8'd0;
VAR34 <= 1'b1;
end else begin
VAR67 <= VAR67 + 1'b1;
VAR34 <= 1'b0;
end end end
reg [11:0] VAR48 = 12'd0;
reg VAR37 = 1'b1;
reg VAR20 = 1'b1;
reg VAR37 = 1'b0;
reg VAR20 = 1'b0;
reg VAR11 = 1'b0;
localparam VAR62 = 4'b0001;
localparam VAR12 = 4'b0010;
localparam VAR57 = 4'b0100;
localparam VAR23 = 4'b1000;
reg VAR4 = 1'b0, VAR42 = 1'b0;
reg VAR60 = 1'b0;
reg VAR66 = 1'b0;
reg VAR26 = 1'b0;
reg [11:0] VAR49 = 12'd0;
localparam VAR52 = 8'd192;
reg [6:0] VAR50 = 7'd0, VAR7 = 7'd0, VAR78 = 7'd0, VAR21 = 7'd0;
reg [11:0] VAR25 = 12'd0, VAR39 = 12'd0, VAR54 = 12'd0, VAR56 = 12'd0;
reg [11:0] VAR80 = 12'd0;
reg VAR38 = 1'b0, VAR79 = 1'b0;
always @(posedge VAR35) begin
VAR4 <= VAR60;
VAR42 <= VAR4;
VAR66 <= VAR20;
VAR50 <= VAR75;
VAR7 <= VAR50;
VAR78 <= VAR41;
VAR21 <= VAR78;
VAR82 <= VAR38;
VAR10 <= VAR79;
VAR80 <= VAR70 - VAR52;
VAR54 <= VAR80 + VAR7;
VAR56 <= VAR80 + VAR21;
VAR25 <= VAR54 + 2'd2;
VAR39 <= VAR56 + 2'd2;
if (~VAR37) begin
VAR48 <= 12'd0;
VAR49 <= 12'd0;
VAR37 <= VAR27;
state <= VAR62;
VAR29 <= VAR29;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
else begin
if (VAR34) VAR48 <= VAR48 + 1;
end
else VAR48 <= VAR48;
if (VAR48 == VAR54) VAR38 <= 1'b1;
end
else if (VAR48 == VAR25) VAR38 <= 1'b0;
else VAR38 <= VAR38;
if (VAR48 == VAR56) VAR79 <= 1'b1;
else if (VAR48 == VAR39) VAR79 <= 1'b0;
else VAR79 <= VAR79;
case (state)
VAR62: begin
VAR49 <= VAR49;
if (VAR48 == VAR70) begin VAR37 <= VAR37;
state <= VAR12;
VAR29 <= 1'b1;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
else begin VAR37 <= VAR37;
state <= state;
VAR29 <= VAR29;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
end
VAR12: begin
VAR49 <= VAR49 + 1'd1;
if (VAR49 == VAR17) begin VAR37 <= VAR37;
state <= VAR57;
VAR29 <= VAR29;
VAR20 <= 1'b1;
VAR11 <= VAR11;
end
else begin VAR37 <= VAR37;
state <=state;
VAR29 <= VAR29;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
end
VAR57: begin
VAR49 <= VAR49;
if (VAR26) begin VAR37 <= VAR37;
state <= VAR23;
VAR29 <= VAR29;
VAR20 <= 1'b0;
VAR11 <= 1'b1;
end
else begin VAR37 <= VAR37;
state <=state;
VAR29 <= VAR29;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
end
VAR23: begin
VAR49 <= VAR49;
if (VAR42) begin VAR37 <= 1'b0;
state <= VAR62;
VAR29 <= 1'b0;
VAR20 <= VAR20;
VAR11 <= 1'b0;
end
else begin VAR37 <= VAR37;
state <= state;
VAR29 <= VAR29;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
end
default: begin
VAR49 <= VAR49;
VAR37 <= VAR37;
state <= VAR62;
VAR29 <= VAR29;
VAR20 <= VAR20;
VAR11 <= VAR11;
end
endcase
end end
reg VAR68 = 1'b0, VAR31 = 1'b0, VAR13 = 1'b0, VAR74 = 1'b0;
reg VAR81 = 1'b0;
reg [13:0] VAR73 = 14'd0;
wire VAR9;
always @(posedge VAR36) begin
VAR68 <= VAR11;
VAR31 <= VAR68;
VAR13 <= VAR31;
VAR74 <= VAR13;
VAR60 <= (VAR73 == 14'd10000);
if (~VAR81) begin
VAR81 <= VAR9;
VAR73 <= 14'd0;
end else begin
VAR73 <= VAR73 + 14'd1;
VAR81 <= (VAR60) ? 1'd0 : VAR81;
end end
assign VAR9 = VAR13 & ~VAR74;
always @(posedge VAR35) begin VAR30 <= VAR11;
end
reg [6:0] VAR58 = 7'd0;
reg [10:0] VAR18 = 11'd163;
reg [10:0] VAR65 = 11'd0; reg VAR69 = 1'b0;
reg VAR43 = 1'b0;
always @(posedge VAR35) begin
VAR58 <= VAR16;
VAR18 <= VAR16 + VAR6;
VAR53 <= VAR43;
if (~VAR69) begin
VAR69 <= (VAR20 & ~ VAR66) ? 1 : 0;
VAR65 <= 0;
VAR43 <= VAR43;
VAR26 <= 0;
end else begin
VAR65 <= VAR65 + 1'b1;
case (VAR65)
{4'b0000, VAR58}: begin
VAR69 <= VAR69;
VAR43 <= 1'b1;
VAR26 <= VAR26;
end
VAR18: begin
VAR69 <= 1'b0;
VAR43 <= 1'b0;
VAR26 <= 1;
end
default: begin
VAR69 <= VAR69;
VAR43 <= VAR43;
VAR26 <= VAR26;
end
endcase
reg [4:0] VAR47 = 5'd0;
always @(posedge VAR35) begin
case (VAR47)
5'd0: if (VAR27) begin
VAR47 <= 5'd1;
VAR63 <= VAR63;
end else begin
VAR47 <= VAR47;
VAR63 <= VAR63;
end
5'd1: begin
VAR63 <= 1;
VAR47 <= VAR47 + 1;
end
5'd31: begin
VAR63 <= 0;
VAR47 <= 0;
end
default: begin
VAR47 <= VAR47 + 1;
VAR63 <= VAR63;
end
endcase
end
reg [4:0] VAR28 = 5'd0;
always @(posedge VAR35) begin
case (VAR28)
5'd0: if (VAR34) begin
VAR28 <= 5'd1;
VAR5 <= VAR5;
end else begin
VAR28 <= VAR28;
VAR5 <= VAR5;
end
5'd1: begin
VAR5 <= 1;
VAR28 <= VAR28 + 1;
end
5'd31: begin
VAR5 <= 0;
VAR28 <= 0;
end
default: begin
VAR28 <= VAR28 + 1;
VAR5 <= VAR5;
end
endcase
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/fill/sky130_fd_sc_hs__fill.pp.symbol.v
| 1,175 |
module MODULE1 (
input VAR4 ,
input VAR2,
input VAR1,
input VAR3
);
endmodule
|
apache-2.0
|
sh-chris110/chris
|
FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/submodules/altera_avalon_st_pipeline_base.v
| 4,579 |
module MODULE1 (
clk,
reset,
VAR7,
VAR15,
VAR2,
VAR8,
VAR1,
VAR4
);
parameter VAR14 = 1;
parameter VAR6 = 8;
parameter VAR3 = 1;
localparam VAR5 = VAR14 * VAR6;
input clk;
input reset;
output VAR7;
input VAR15;
input [VAR5-1:0] VAR2;
input VAR8;
output VAR1;
output [VAR5-1:0] VAR4;
reg VAR11;
reg VAR12;
reg [VAR5-1:0] VAR10;
reg [VAR5-1:0] VAR13;
assign VAR1 = VAR12;
assign VAR4 = VAR13;
generate if (VAR3 == 1)
begin : VAR9
assign VAR7 = !VAR11;
always @(posedge clk, posedge reset) begin
if (reset) begin
VAR10 <= {VAR5{1'b0}};
VAR13 <= {VAR5{1'b0}};
end else begin
if (~VAR11)
VAR10 <= VAR2;
if (~VAR12 || (VAR8 && VAR1)) begin
if (VAR11)
VAR13 <= VAR10;
end
else
VAR13 <= VAR2;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR11 <= 1'b0;
VAR12 <= 1'b0;
end else begin
if (~VAR11 & ~VAR12) begin
if (VAR15) begin
VAR12 <= 1'b1;
end
end
if (VAR12 & ~VAR11) begin
if (VAR15 & ~VAR8) begin
VAR11 <= 1'b1;
end
if (~VAR15 & VAR8) begin
VAR12 <= 1'b0;
end
end
if (VAR12 & VAR11) begin
if (VAR8) begin
VAR11 <= 1'b0;
end
end end
end
end
else
begin : VAR16
assign VAR7 = (~VAR12) | VAR8;
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR13 <= 'b0;
VAR12 <= 1'b0;
end
else begin
if (VAR7) begin
VAR13 <= VAR2;
VAR12 <= VAR15;
end
end
end
end
endgenerate
endmodule
|
gpl-2.0
|
mammenx/synesthesia_moksha
|
wxp/dgn/syn/limbus/synthesis/submodules/limbus_tristate_conduit_pin_sharer_0.v
| 4,868 |
module MODULE1 (
input wire VAR21, input wire VAR19, output wire request, input wire VAR17, output wire [18:0] VAR30, output wire [1:0] VAR38, output wire [0:0] VAR20, output wire [0:0] VAR15, output wire [15:0] VAR22, input wire [15:0] VAR3, output wire VAR25, output wire [0:0] VAR11, input wire VAR26, output wire VAR4, input wire [18:0] VAR34, input wire [1:0] VAR33, input wire [0:0] VAR2, input wire [0:0] VAR8, input wire [15:0] VAR29, output wire [15:0] VAR35, input wire VAR6, input wire [0:0] VAR1 );
wire [0:0] VAR23; wire VAR37; wire VAR36;
VAR24 VAR16 (
.clk (VAR21), .reset (VAR19), .request (request), .VAR17 (VAR17), .VAR30 (VAR30), .VAR38 (VAR38), .VAR20 (VAR20), .VAR15 (VAR15), .VAR22 (VAR22), .VAR3 (VAR3), .VAR25 (VAR25), .VAR11 (VAR11), .VAR26 (VAR26), .VAR4 (VAR4), .VAR9 (VAR34), .VAR13 (VAR33), .VAR7 (VAR2), .VAR27 (VAR8), .VAR39 (VAR29), .VAR28 (VAR35), .VAR18 (VAR6), .VAR5 (VAR1), .ack (VAR37), .VAR12 (VAR23), .VAR10 (VAR36) );
VAR31 VAR32 (
.clk (VAR21), .reset (VAR19), .ack (VAR37), .VAR12 (VAR23), .VAR14 (VAR36) );
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/mux2i/sky130_fd_sc_hs__mux2i_1.v
| 2,087 |
module MODULE2 (
VAR3 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR4,
VAR1
);
output VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR1;
VAR6 VAR2 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3 ,
VAR8,
VAR5,
VAR7
);
output VAR3 ;
input VAR8;
input VAR5;
input VAR7 ;
supply1 VAR4;
supply0 VAR1;
VAR6 VAR2 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
The7thPres/CFTP
|
CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/MEMWB_Stage.v
| 3,239 |
module MODULE1(
input VAR6,
input reset,
input VAR8,
input VAR2,
input VAR13,
input VAR12,
input VAR18,
input [31:0] VAR14,
input [31:0] VAR4,
input [4:0] VAR5,
input VAR1,
input VAR10,
input [31:0] VAR17,
input [31:0] VAR7,
input [4:0] VAR9,
output reg VAR11,
output reg VAR15,
output reg [31:0] VAR19,
output reg [31:0] VAR3,
output reg [4:0] VAR16
);
always @(posedge VAR6) begin
VAR11 <= (reset) ? 1'b0 : ((VAR13) ? VAR1 : ((VAR2 | VAR8) ? 1'b0 : VAR12));
VAR15 <= (reset) ? 1'b0 : ((VAR13) ? VAR10 : VAR18);
VAR19 <= (reset) ? 32'b0 : ((VAR13) ? VAR17 : VAR14);
VAR3 <= (reset) ? 32'b0 : ((VAR13) ? VAR7 : VAR4);
VAR16 <= (reset) ? 5'b0 : ((VAR13) ? VAR9 : VAR5);
end
endmodule
|
lgpl-3.0
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/vivado_cores/hls_cores/vector_add/vectoradd_prj/solution1/impl/ip/hdl/verilog/vectoradd.v
| 17,628 |
module MODULE1 (
VAR19,
VAR17,
VAR45,
VAR73,
VAR64,
VAR49,
VAR72,
VAR77,
VAR54,
VAR50,
VAR35,
VAR42,
VAR67,
VAR28,
VAR56,
VAR37,
VAR58,
VAR48,
VAR74,
VAR40,
VAR57,
VAR31,
VAR5,
VAR18,
VAR38,
VAR43,
VAR47,
VAR68,
VAR53
);
parameter VAR9 = 1'b1;
parameter VAR10 = 1'b0;
parameter VAR65 = 3'b000;
parameter VAR8 = 3'b1;
parameter VAR15 = 3'b10;
parameter VAR51 = 3'b11;
parameter VAR52 = 3'b100;
parameter VAR46 = 3'b101;
parameter VAR26 = 3'b110;
parameter VAR21 = 1'b0;
parameter VAR75 = 32'b1;
parameter VAR55 = 32'b10;
parameter VAR44 = 4'b0000;
parameter VAR66 = 4'b1111;
parameter VAR34 = 32'b00000000000000000000000000000000;
parameter VAR16 = 1'b1;
input VAR19;
input VAR17;
input [31:0] VAR45;
input VAR73;
output VAR64;
output [31:0] VAR49;
output VAR72;
input VAR77;
output [31:0] VAR54;
output VAR50;
output [3:0] VAR35;
output [31:0] VAR42;
input [31:0] VAR67;
output VAR28;
output VAR56;
output [31:0] VAR37;
output VAR58;
output [3:0] VAR48;
output [31:0] VAR74;
input [31:0] VAR40;
output VAR57;
output VAR31;
output [31:0] VAR5;
output VAR18;
output [3:0] VAR38;
output [31:0] VAR43;
input [31:0] VAR47;
output VAR68;
output VAR53;
reg VAR64;
reg VAR72;
reg VAR50;
reg VAR58;
reg VAR18;
reg[3:0] VAR38;
reg[31:0] VAR43;
reg [31:0] VAR24;
reg [2:0] VAR6 = 3'b000;
reg [31:0] VAR13;
wire [0:0] VAR4;
reg [0:0] VAR25;
wire [0:0] VAR41;
reg [0:0] VAR22;
wire [63:0] VAR2;
reg [63:0] VAR14;
wire [0:0] VAR29;
wire [0:0] VAR33;
reg VAR63;
wire [31:0] VAR32;
reg [31:0] VAR23;
wire [63:0] VAR27;
reg [63:0] VAR36;
wire [31:0] VAR61;
reg [31:0] VAR62;
reg [31:0] VAR12;
reg [31:0] VAR59;
reg VAR60 = 1'b0;
reg [31:0] VAR39;
reg [31:0] VAR76;
wire [31:0] VAR71;
wire [31:0] VAR69;
reg [31:0] VAR1;
reg [2:0] VAR78;
reg VAR3;
reg VAR7;
reg VAR30;
always @ (posedge VAR19)
begin : VAR70
if (VAR17 == 1'b0) begin
VAR6 <= VAR65;
end else begin
VAR6 <= VAR78;
end
end
always @ (posedge VAR19)
begin : VAR11
if (VAR17 == 1'b0) begin
VAR60 <= VAR10;
end else begin
if (VAR30) begin
if (~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63))) begin
VAR60 <= VAR10;
end else if ((VAR9 == VAR77)) begin
VAR60 <= VAR9;
end
end
end
end
always @(posedge VAR19)
begin
if ((~(VAR73 == VAR10) & (VAR51 == VAR6) & (VAR4 == VAR21) & ~(VAR41 == VAR21))) begin
VAR12 <= VAR45;
end else if ((VAR46 == VAR6)) begin
VAR12 <= VAR23;
end
end
always @(posedge VAR19)
begin
if ((~(VAR73 == VAR10) & (VAR51 == VAR6) & ~(VAR4 == VAR21))) begin
VAR59 <= VAR45;
end else if ((VAR26 == VAR6)) begin
VAR59 <= VAR62;
end
end
always @(posedge VAR19)
begin
if ((~(VAR73 == VAR10) & (VAR15 == VAR6))) begin
VAR13 <= VAR45;
end
end
always @(posedge VAR19)
begin
if (((VAR52 == VAR6) & ~(VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR21 == VAR29))) begin
VAR62 <= VAR61;
VAR36 <= VAR27;
end
end
always @(posedge VAR19)
begin
if (((VAR52 == VAR6) & (VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR22 == VAR21) & ~(VAR21 == VAR33))) begin
VAR23 <= VAR32;
VAR14 <= VAR2;
end
end
always @(posedge VAR19)
begin
if (((VAR8 == VAR6) & ~(VAR73 == VAR10))) begin
VAR24 <= VAR45;
end
end
always @(posedge VAR19)
begin
if ((~(VAR73 == VAR10) & (VAR51 == VAR6) & (VAR4 == VAR21))) begin
VAR22 <= VAR41;
end
end
always @(posedge VAR19)
begin
if ((~(VAR73 == VAR10) & (VAR51 == VAR6))) begin
VAR25 <= VAR4;
end
end
always @ (VAR6 or VAR2 or VAR27 or VAR3 or VAR7)
begin
if ((VAR52 == VAR6)) begin
if (VAR7) begin
VAR39 = VAR27;
end else if (VAR3) begin
VAR39 = VAR2;
end else begin
VAR39 = 'VAR20;
end
end else begin
VAR39 = 'VAR20;
end
end
always @ (VAR6 or VAR25 or VAR22 or VAR29 or VAR33 or VAR63)
begin
if ((((VAR52 == VAR6) & (VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR22 == VAR21) & ~(VAR21 == VAR33)) | ((VAR52 == VAR6) & ~(VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR21 == VAR29)))) begin
VAR50 = VAR9;
end else begin
VAR50 = VAR10;
end
end
always @ (VAR77 or VAR60)
begin
if ((VAR10 == VAR60)) begin
VAR63 = VAR77;
end else begin
VAR63 = VAR9;
end
end
always @ (VAR6 or VAR2 or VAR27 or VAR3 or VAR7)
begin
if ((VAR52 == VAR6)) begin
if (VAR7) begin
VAR76 = VAR27;
end else if (VAR3) begin
VAR76 = VAR2;
end else begin
VAR76 = 'VAR20;
end
end else begin
VAR76 = 'VAR20;
end
end
always @ (VAR6 or VAR25 or VAR22 or VAR29 or VAR33 or VAR63)
begin
if ((((VAR52 == VAR6) & (VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR22 == VAR21) & ~(VAR21 == VAR33)) | ((VAR52 == VAR6) & ~(VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR21 == VAR29)))) begin
VAR58 = VAR9;
end else begin
VAR58 = VAR10;
end
end
always @ (VAR73 or VAR6)
begin
if ((((VAR8 == VAR6) & ~(VAR73 == VAR10)) | (~(VAR73 == VAR10) & (VAR15 == VAR6)) | (~(VAR73 == VAR10) & (VAR51 == VAR6)))) begin
VAR64 = VAR9;
end else begin
VAR64 = VAR10;
end
end
always @ (VAR6 or VAR25 or VAR22 or VAR29 or VAR33 or VAR60)
begin
if (((VAR52 == VAR6) & (((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR60))) begin
VAR72 = VAR9;
end else begin
VAR72 = VAR10;
end
end
always @ (VAR6 or VAR14 or VAR36)
begin
if ((VAR26 == VAR6)) begin
VAR1 = VAR36;
end else if ((VAR46 == VAR6)) begin
VAR1 = VAR14;
end else begin
VAR1 = 'VAR20;
end
end
always @ (VAR6 or VAR71 or VAR69)
begin
if ((VAR26 == VAR6)) begin
VAR43 = VAR69;
end else if ((VAR46 == VAR6)) begin
VAR43 = VAR71;
end else begin
VAR43 = 'VAR20;
end
end
always @ (VAR6)
begin
if (((VAR46 == VAR6) | (VAR26 == VAR6))) begin
VAR18 = VAR9;
end else begin
VAR18 = VAR10;
end
end
always @ (VAR6)
begin
if (((VAR46 == VAR6) | (VAR26 == VAR6))) begin
VAR38 = VAR66;
end else begin
VAR38 = VAR44;
end
end
always @ (VAR73 or VAR6 or VAR25 or VAR22 or VAR29 or VAR33 or VAR63)
begin
case (VAR6)
VAR65 :
begin
VAR78 = VAR8;
end
VAR8 :
begin
if (~(VAR73 == VAR10)) begin
VAR78 = VAR15;
end else begin
VAR78 = VAR8;
end
end
VAR15 :
begin
if (~(VAR73 == VAR10)) begin
VAR78 = VAR51;
end else begin
VAR78 = VAR15;
end
end
VAR51 :
begin
if (~(VAR73 == VAR10)) begin
VAR78 = VAR52;
end else begin
VAR78 = VAR51;
end
end
VAR52 :
begin
if (((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)))) begin
VAR78 = VAR8;
end else if ((~(VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR21 == VAR29))) begin
VAR78 = VAR26;
end else if (((VAR25 == VAR21) & ~((((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))) & (VAR10 == VAR63)) & ~(VAR22 == VAR21) & ~(VAR21 == VAR33))) begin
VAR78 = VAR46;
end else begin
VAR78 = VAR52;
end
end
VAR46 :
begin
VAR78 = VAR52;
end
VAR26 :
begin
VAR78 = VAR52;
end
default :
begin
VAR78 = 'VAR20;
end
endcase
end
assign VAR54 = VAR39 << VAR55;
assign VAR28 = VAR19;
assign VAR42 = VAR34;
assign VAR56 = VAR17;
assign VAR35 = VAR44;
always @ (VAR25 or VAR29)
begin
VAR7 = (~(VAR25 == VAR21) & ~(VAR21 == VAR29));
end
always @ (VAR6 or VAR25 or VAR22 or VAR29 or VAR33)
begin
VAR30 = ((VAR52 == VAR6) & (((VAR25 == VAR21) & (VAR22 == VAR21)) | (~(VAR25 == VAR21) & (VAR21 == VAR29)) | ((VAR25 == VAR21) & (VAR21 == VAR33))));
end
always @ (VAR25 or VAR22 or VAR33)
begin
VAR3 = ((VAR25 == VAR21) & ~(VAR22 == VAR21) & ~(VAR21 == VAR33));
end
assign VAR37 = VAR76 << VAR55;
assign VAR57 = VAR19;
assign VAR74 = VAR34;
assign VAR31 = VAR17;
assign VAR48 = VAR44;
assign VAR61 = (VAR59 + VAR75);
assign VAR32 = (VAR12 + VAR75);
assign VAR49 = VAR75;
assign VAR5 = VAR1 << VAR55;
assign VAR68 = VAR19;
assign VAR53 = VAR17;
assign VAR41 = (VAR24 == VAR55? 1'b1: 1'b0);
assign VAR29 = ((VAR59) < (VAR13)? 1'b1: 1'b0);
assign VAR27 = (VAR59);
assign VAR69 = (VAR40 + VAR67);
assign VAR33 = ((VAR12) < (VAR13)? 1'b1: 1'b0);
assign VAR2 = (VAR12);
assign VAR71 = (VAR67 - VAR40);
assign VAR4 = (VAR24 == VAR75? 1'b1: 1'b0);
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o311a/sky130_fd_sc_lp__o311a.pp.blackbox.v
| 1,406 |
module MODULE1 (
VAR10 ,
VAR6 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR9 ,
VAR1,
VAR4,
VAR5 ,
VAR8
);
output VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR1;
input VAR4;
input VAR5 ;
input VAR8 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/and3b/sky130_fd_sc_hdll__and3b_2.v
| 2,234 |
module MODULE2 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR5 ,
VAR4,
VAR1,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR10 ;
input VAR9 ;
VAR7 VAR3 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8 ,
VAR2,
VAR6 ,
VAR5
);
output VAR8 ;
input VAR2;
input VAR6 ;
input VAR5 ;
supply1 VAR4;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR9 ;
VAR7 VAR3 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
sh-chris110/chris
|
FPGA/Math/Qsys/nios_design/synthesis/submodules/custom_math.v
| 1,685 |
module MODULE1 (
input wire [7:0] VAR6, input wire VAR2, output wire [31:0] VAR4, input wire VAR3, input wire [31:0] VAR13, output wire VAR11, input wire VAR5, input wire VAR8, output wire VAR12, output wire [7:0] VAR7, output wire VAR9, input wire VAR1, input wire [31:0] VAR10, output wire VAR15, output wire [31:0] VAR14 );
assign VAR4 = 32'b00000000000000000000000000000000;
assign VAR11 = 1'b0;
assign VAR12 = 1'b0;
assign VAR7 = 8'b00000000;
assign VAR9 = 1'b0;
assign VAR15 = 1'b0;
assign VAR14 = 32'b00000000000000000000000000000000;
endmodule
|
gpl-2.0
|
ElegantLin/My-CPU
|
Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/ctrl.v
| 3,474 |
module MODULE1(
input wire rst,
input wire[31:0] VAR3,
input wire[VAR10] VAR4,
input wire VAR5,
input wire VAR1,
input wire VAR8,
output reg[VAR10] VAR12,
output reg VAR9,
output reg[5:0] VAR13
);
always @ (*) begin
if(rst == VAR11) begin
VAR13 <= 6'b000000;
VAR9 <= 1'b0;
VAR12 <= VAR2;
end else if(VAR3 != VAR2) begin
VAR9 <= 1'b1;
VAR13 <= 6'b000000;
case (VAR3)
32'h00000001: begin VAR12 <= 32'h4;
end
32'h00000008: begin VAR12 <= 32'h4;
end
32'h0000000a: begin VAR12 <= 32'h00000040;
end
32'h0000000d: begin VAR12 <= 32'h4;
end
32'h0000000c: begin VAR12 <= 32'h4;
end
32'h0000000e: begin VAR12 <= VAR4;
end
default : begin
end
endcase
end else if(VAR1 == VAR6) begin
VAR13 <= 6'b001111;
VAR9 <= 1'b0;
end else if(VAR5 == VAR6) begin
VAR13 <= 6'b000111;
VAR9 <= 1'b0;
end else if(VAR8 == VAR7) begin
VAR13 <= 6'b000010;
VAR9 <= 1'b0;
end else begin
VAR13 <= 6'b000000;
VAR9 <= 1'b0;
VAR12 <= VAR2;
end end
endmodule
|
gpl-3.0
|
ShepardSiegel/ocpi
|
coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_ram.v
| 4,217 |
module MODULE1 (
address,
VAR34,
VAR2,
clk,
VAR10,
reset,
write,
VAR26,
VAR24
)
;
parameter VAR31 = "../MODULE1.VAR17";
output [ 31: 0] VAR24;
input [ 8: 0] address;
input [ 3: 0] VAR34;
input VAR2;
input clk;
input VAR10;
input reset;
input write;
input [ 31: 0] VAR26;
wire [ 31: 0] VAR24;
wire VAR27;
assign VAR27 = VAR2 & write;
VAR18 VAR22
(
.VAR3 (address),
.VAR30 (VAR34),
.VAR6 (clk),
.VAR29 (VAR10),
.VAR7 (VAR26),
.VAR14 (VAR24),
.VAR9 (VAR27)
);
VAR22.VAR21 = "VAR19",
VAR22.VAR4 = "VAR18",
VAR22.VAR12 = 512,
VAR22.VAR1 = 512,
VAR22.VAR28 = "VAR25",
VAR22.VAR16 = "VAR11",
VAR22.VAR15 = "VAR13",
VAR22.VAR8 = "VAR23",
VAR22.VAR32 = 32,
VAR22.VAR20 = 4,
VAR22.VAR33 = 9;
endmodule
|
lgpl-3.0
|
eda-globetrotter/MarcheProcessor
|
final/src/pipe3.v
| 1,421 |
module MODULE1(VAR12, VAR1, VAR5, VAR8,
VAR13, VAR11, VAR10, VAR2,
VAR4, VAR9, VAR6, VAR7,
VAR3, VAR14, clk, reset);
input [0:127] VAR12;
input [0:15] VAR5;
input VAR13;
input [0:4] VAR10;
input VAR4;
input [0:127] VAR6;
input [0:31] VAR3;
input clk, reset;
output [0:127] VAR1;
output [0:15] VAR8;
output VAR11;
output [0:15] VAR2;
output VAR9;
output [0:127] VAR7;
output [0:31] VAR14;
reg [0:127] VAR1;
reg [0:15] VAR8;
reg VAR11;
reg [0:4] VAR2;
reg VAR9;
reg [0:127] VAR7;
reg [0:31] VAR14;
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
VAR1<=128'b0;
VAR8<=16'b0;
VAR11<=1'b0;
VAR2<=5'b0;
VAR9<=1'b0;
VAR7<=128'b0;
VAR14<=32'b0;
end
else
begin
VAR1<=VAR12;
VAR8<=VAR5;
VAR11<=VAR13;
VAR2<=VAR10;
VAR9<=VAR4;
VAR7<=VAR6;
VAR14<=VAR3;
end
end
endmodule
|
mit
|
schmr/grlib
|
grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/mig_interface_model.v
| 4,854 |
module MODULE1
(
input [27:0] VAR21,
input [2:0] VAR34,
input VAR20,
input [511:0] VAR18,
input VAR28,
input [63:0] VAR15,
input VAR31,
output wire [511:0] VAR32,
output wire VAR11,
output wire VAR12,
output wire VAR5,
output wire VAR26,
output reg VAR25,
output reg VAR27,
output reg VAR19,
input VAR2
);
parameter VAR7 = 28 - 8;
parameter VAR30 = 512;
parameter VAR23 = (1<<VAR7);
reg VAR16;
reg VAR22;
reg VAR10;
reg VAR29;
reg VAR6;
reg VAR17;
reg VAR1;
reg [27:0] VAR3;
reg [27:0] VAR24;
reg [27:0] VAR14;
reg [27:0] VAR9;
reg [27:0] VAR13;
reg [511:0] VAR33;
reg [VAR30-1:0] VAR4 [0:VAR23];
integer VAR8;
assign VAR11 = VAR16;
assign VAR5 = VAR10;
assign VAR26 = VAR29;
assign VAR12 = VAR22;
assign VAR32 = VAR4[VAR3 >> 3];
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
gpl-2.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_axi_basic_rx_pipeline.v
| 26,674 |
module MODULE1 #(
parameter VAR66 = 128, parameter VAR16 = "VAR75", parameter VAR52 = 1,
parameter VAR67 = (VAR66 == 128) ? 2 : 1, parameter VAR31 = VAR66 / 8 ) (
output reg [VAR66-1:0] VAR7, output reg VAR64, input VAR83, output [VAR31-1:0] VAR63, output VAR72, output reg [21:0] VAR55,
input [VAR66-1:0] VAR57, input VAR61, input VAR84, input VAR65, output reg VAR70, input VAR45, input [VAR67-1:0] VAR25, input VAR43, input [6:0] VAR2, input VAR19,
input VAR3, input VAR46, input [VAR31-1:0] VAR12, input VAR39, input [4:0] VAR82,
output [2:0] VAR44, input VAR49, input VAR1 );
wire [4:0] VAR4;
wire [4:0] VAR81;
wire [4:0] VAR74;
wire [4:0] VAR18;
reg [VAR31-1:0] VAR27;
wire [VAR31-1:0] VAR6;
wire [VAR31-1:0] VAR87;
reg VAR15;
wire VAR40;
wire [VAR66-1:0] VAR21;
reg [VAR66-1:0] VAR33;
wire VAR53;
reg VAR78;
reg VAR20;
reg [VAR67-1:0] VAR59;
reg VAR69;
reg VAR32;
reg VAR28;
reg [6:0] VAR10;
reg VAR51;
reg VAR62;
reg VAR30;
reg VAR26;
wire VAR86;
wire VAR58;
reg VAR35;
reg VAR37;
assign VAR40 = VAR65 &&
(VAR26 || (VAR61 && !VAR45));
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(VAR70) begin
end
end
end
generate
if(VAR66 == 128) begin : VAR68
assign VAR21 = {VAR57[31:0],
VAR57[63:32],
VAR57[95:64],
VAR57[127:96]};
end
else if(VAR66 == 64) begin : VAR9
assign VAR21 = {VAR57[31:0], VAR57[63:32]};
end
else begin : VAR5
assign VAR21 = VAR57;
end
endgenerate
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(!VAR53) begin
if(VAR78) begin
end
else begin
end
end
end
end
assign VAR53 = (!VAR83 && VAR64);
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
end
end
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(!VAR53) begin
if(VAR30) begin
end
else if(VAR78) begin
end
else begin
end
end
end
generate
if(VAR66 == 128) begin : VAR73
assign VAR72 = 1'b0;
assign VAR63 = {VAR31{1'b1}};
end
else begin : VAR85
assign VAR72 = VAR15;
assign VAR63 = VAR27;
end
endgenerate
generate
if(VAR66 == 128) begin : VAR50
assign VAR6 = 16'h0000;
assign VAR87 = 16'h0000;
end
else if(VAR66 == 64) begin : VAR29
assign VAR6 = VAR25 ? 8'hFF : 8'h0F;
assign VAR87 = VAR59 ? 8'hFF : 8'h0F;
end
else begin : VAR54
assign VAR6 = 4'hF;
assign VAR87 = 4'hF;
end
endgenerate
generate
if(VAR66 == 128) begin : VAR36
assign VAR4 = {(VAR61 && !VAR45), (VAR61 && !VAR25[1]), 3'b000};
assign VAR81 = {(VAR28 && !VAR32), (VAR28 && !VAR59[1]), 3'b000}; end
else begin : VAR11
assign VAR4 = {(VAR61 && !VAR45), 4'b0000};
assign VAR81 = {(VAR28 && !VAR32), 4'b0000}; end
endgenerate
generate
if(VAR66 == 128) begin : VAR8
assign VAR74 = {VAR84, VAR25, 2'b11};
assign VAR18 = {VAR20, VAR59, 2'b11}; end
else if(VAR66 == 64) begin : VAR48
assign VAR74 = {VAR84, 1'b0, VAR25, 2'b11};
assign VAR18 = {VAR20, 1'b0, VAR59, 2'b11}; end
else begin : VAR14
assign VAR74 = {VAR84, 4'b0011};
assign VAR18 = {VAR20, 4'b0011}; end
endgenerate
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(VAR30 && VAR83) begin
end
else if(VAR86) begin
end
else if(VAR64) begin
end
else begin
end
end
end
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(VAR30 && VAR46 && VAR83)
begin
end
else if(VAR86 && !VAR53) begin
end
end
end
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(VAR61 && !VAR84 && VAR40 && VAR70)
begin
end
else if(VAR45) begin
end
else if(VAR84 && !VAR61 && VAR65 && VAR70) begin
end
end
end
assign VAR58 = VAR45 && !VAR37 && VAR26 &&
(!VAR61 || VAR84) && !(VAR70 && VAR84);
always @(posedge VAR49) begin
if(VAR1) begin
end
else begin
if(VAR58) begin
end
else if(VAR30) begin
end
end
end
assign VAR86 = VAR58 || VAR35;
generate
if(VAR16 == "VAR42" && VAR66 == 128) begin : VAR56
reg [2:0] VAR34;
wire VAR77 = (!(|VAR7[92:88]) && !VAR7[94]);
wire VAR23 = (VAR7[92:88] == 5'b00001);
wire VAR17 = (VAR7[92:88] == 5'b00010);
wire VAR24 = (VAR7[92:89] == 4'b0010);
wire VAR79 = ((&VAR7[91:90]) && VAR7[94]);
wire VAR22 = (VAR77 ||
VAR23 ||
VAR17 ||
VAR24 ||
VAR79) && VAR55[13];
wire VAR71 = (!(|VAR7[28:24]) && !VAR7[30]);
wire VAR13 = (VAR7[28:24] == 5'b00001);
wire VAR38 = (VAR7[28:24] == 5'b00010);
wire VAR76 = (VAR7[28:25] == 4'b0010);
wire VAR47 = ((&VAR7[27:26]) && VAR7[30]);
wire VAR80 = (VAR71 ||
VAR13 ||
VAR38 ||
VAR76 ||
VAR47) && !VAR55[13];
wire VAR60 =
VAR55[14] && VAR83 && VAR64;
always @(posedge VAR49) begin
if (VAR1) begin
end
else begin
if((VAR22 || VAR80) && VAR60)
begin
end
end
end
assign VAR44 = VAR34;
end
else begin : VAR41
assign VAR44 = 3'h0;
end
endgenerate
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.behavioral.v
| 1,674 |
module MODULE1 (
VAR6 ,
VAR1,
VAR5,
VAR13 ,
VAR4
);
output VAR6 ;
input VAR1;
input VAR5;
input VAR13 ;
input VAR4 ;
supply1 VAR7;
supply0 VAR11;
supply1 VAR14 ;
supply0 VAR10 ;
wire VAR12 ;
wire VAR8 ;
wire VAR16;
nand VAR2 (VAR12 , VAR5, VAR1 );
or VAR3 (VAR8 , VAR4, VAR13 );
nand VAR9 (VAR16, VAR12, VAR8);
buf VAR15 (VAR6 , VAR16 );
endmodule
|
apache-2.0
|
mashanz/FinalProject
|
Code/module/selesai/alu_min.v
| 7,675 |
module MODULE1( VAR2, VAR3, VAR1, VAR6, VAR5, VAR4, VAR8, VAR9);
input VAR2, VAR3, VAR1;
input [7:0]VAR9;
input [7:0]VAR6;
input [7:0]VAR5;
output [7:0]VAR4;
input [1:0]VAR8;
reg [7:0]VAR4;
reg [11:0]VAR7;
always@(posedge VAR3)begin
if(VAR2) VAR4 = 0;
end
else begin
case(VAR9)
8'b00000001: VAR4 = 0;
8'b00000010: VAR4 <= VAR6 + VAR5;
8'b00000011: VAR4 <= VAR6 - VAR5;
8'b00000011: VAR4 <= VAR6^VAR5;
8'b00000100: VAR4 <= VAR6&VAR5;
8'b00000101: VAR4 <= VAR6|VAR5;
8'b00000110: VAR4 <= VAR6&&VAR5;
8'b00000111: VAR4 <= VAR6||VAR5;
8'b00001000: VAR4 <= VAR6+1;
8'b00001001: VAR4 <= VAR6-1;
8'b00001010: VAR4 <= VAR6<<1;
8'b00001011: VAR4 <= VAR6>>1;
8'b00001100: VAR4 <= !VAR6;
8'b00001101: VAR4 <= ~VAR6;
8'b00001110: VAR4 <= VAR6+VAR6;
8'b00001111: VAR4 <= VAR6-VAR6;
8'b00010000: VAR4 <= VAR5+VAR4;
8'b00010001: VAR4 <= VAR5-VAR4;
8'b00010011: VAR4 <= VAR5^VAR4;
8'b00010100: VAR4 <= VAR5&VAR4;
8'b00010101: VAR4 <= VAR5|VAR4;
8'b00010110: VAR4 <= VAR5&&VAR4;
8'b00010111: VAR4 <= VAR5||VAR4;
8'b00111000: VAR4 <= VAR4+1;
8'b00111001: VAR4 <= VAR4-1;
8'b00111010: VAR4 <= VAR4<<1;
8'b00111011: VAR4 <= VAR4>>1;
8'b00111100: VAR4 <= !VAR4;
8'b00111101: VAR4 <= ~VAR4;
8'b00111110: VAR4 <= VAR5+VAR4;
8'b00111111: VAR4 <= VAR5-VAR4;
8'b00100000: VAR4 <= VAR6+VAR5;
8'b00100001: VAR4 <= VAR6-VAR5;
8'b00100011: VAR4 <= VAR6^VAR5;
8'b00100100: VAR4 <= VAR6&VAR5;
8'b00100101: VAR4 <= VAR6|VAR5;
8'b00100110: VAR4 <= VAR6&&VAR5;
8'b00100111: VAR4 <= VAR6||VAR5;
8'b00101000: VAR4 <= VAR6+1;
8'b00101001: VAR4 <= VAR6-1;
8'b00101010: VAR4 <= VAR6<<1;
8'b00101011: VAR4 <= VAR6>>1;
8'b00101100: VAR4 <= !VAR6;
8'b00101101: VAR4 <= ~VAR6;
8'b00101110: VAR4 <= VAR6+VAR6;
8'b00101111: VAR4 <= VAR6-VAR6;
8'b00110000: VAR4 <= VAR4+VAR6;
8'b00110001: VAR4 <= VAR4-VAR6;
8'b00111000: VAR4 <= VAR4+1;
8'b00111001: VAR4 <= VAR4-1;
8'b00111010: VAR4 <= VAR4<<1;
8'b00111011: VAR4 <= VAR4>>1;
8'b00111100: VAR4 <= !VAR4;
8'b00111101: VAR4 <= ~VAR4;
8'b00111110: VAR4 <= VAR4+VAR5;
8'b00111111: VAR4 <= VAR4-VAR5;
8'b01000000: VAR4=VAR6+VAR5;
8'b01000001: VAR4=VAR6-VAR5;
8'b01000010: VAR4=VAR5-1;
8'b01000100: VAR4=VAR6&&VAR5;
8'b01000101: VAR4=VAR6||VAR5;
8'b01000110: VAR4=!VAR6;
8'b01000111: VAR4=~VAR6;
8'b01001000: VAR4=VAR6&VAR5;
8'b01001001: VAR4=VAR6|VAR5;
8'b01001010: VAR4=VAR6^VAR5;
8'b01001011: VAR4=VAR6<<1;
8'b01001100: VAR4=VAR6>>1;
8'b01001101: VAR4=VAR6+1;
8'b01001110: VAR4=VAR6-1;
8'b01001111: VAR4=VAR6-1;
8'b01010000: VAR4=VAR6+VAR5;
8'b01010001: VAR4=VAR6-VAR5;
8'b01010010: VAR4=VAR5-1;
8'b01010011: VAR4=VAR6*VAR5;
8'b01010100: VAR4=VAR6&&VAR5;
8'b01010101: VAR4=VAR6||VAR5;
8'b01010110: VAR4=!VAR6;
8'b01010111: VAR4=~VAR6;
8'b01011000: VAR4=VAR6&VAR5;
8'b01011001: VAR4=VAR6|VAR5;
8'b01011010: VAR4=VAR6^VAR5;
8'b01011011: VAR4=VAR6<<1;
8'b01011100: VAR4=VAR6>>1;
8'b01011101: VAR4=VAR6+1;
8'b01011110: VAR4=VAR6-1;
8'b01011111: VAR4=VAR6-1;
8'b01100000: VAR4=VAR6+VAR5;
8'b01100001: VAR4=VAR6-VAR5;
8'b01100010: VAR4=VAR5-1;
8'b01100100: VAR4=VAR6&&VAR5;
8'b01100101: VAR4=VAR6||VAR5;
8'b01100110: VAR4=!VAR6;
8'b01100111: VAR4=~VAR6;
8'b01101000: VAR4=VAR6&VAR5;
8'b01101001: VAR4=VAR6|VAR5;
8'b01101010: VAR4=VAR6^VAR5;
8'b01101011: VAR4=VAR6<<1;
8'b01101100: VAR4=VAR6>>1;
8'b01101101: VAR4=VAR6+1;
8'b01101110: VAR4=VAR6-1;
8'b01101111: VAR4=VAR6-1;
8'b01110000: VAR4=VAR6+VAR5;
8'b01110001: VAR4=VAR6-VAR5;
8'b01110010: VAR4=VAR5-1;
8'b01110011: VAR4=VAR6*VAR5;
8'b01110100: VAR4=VAR6&&VAR5;
8'b01110101: VAR4=VAR6||VAR5;
8'b01110110: VAR4=!VAR6;
8'b01110111: VAR4=~VAR6;
8'b01111000: VAR4=VAR6&VAR5;
8'b01111001: VAR4=VAR6|VAR5;
8'b01111010: VAR4=VAR6^VAR5;
8'b01111011: VAR4=VAR6<<1;
8'b01111100: VAR4=VAR6>>1;
8'b01111101: VAR4=VAR6+1;
8'b01111110: VAR4=VAR6-1;
8'b01111111: VAR4=VAR6-1;
8'b10000000: VAR4=VAR6+VAR5;
8'b10000001: VAR4=VAR6-VAR5;
8'b10000010: VAR4=VAR5-1;
8'b10000100: VAR4=VAR6&&VAR5;
8'b10000101: VAR4=VAR6||VAR5;
8'b10000110: VAR4=!VAR6;
8'b10000111: VAR4=~VAR6;
8'b10001000: VAR4=VAR6&VAR5;
8'b10001001: VAR4=VAR6|VAR5;
8'b10001010: VAR4=VAR6^VAR5;
8'b10001011: VAR4=VAR6<<1;
8'b10001100: VAR4=VAR6>>1;
8'b10001101: VAR4=VAR6+1;
8'b10001110: VAR4=VAR6-1;
8'b10001111: VAR4=VAR6-1;
8'b10010000: VAR4=VAR6+VAR5;
8'b10010001: VAR4=VAR6-VAR5;
8'b10010010: VAR4=VAR5-1;
8'b10010100: VAR4=VAR6&&VAR5;
8'b10010101: VAR4=VAR6||VAR5;
8'b10010110: VAR4=!VAR6;
8'b10010111: VAR4=~VAR6;
8'b10011000: VAR4=VAR6&VAR5;
8'b10011001: VAR4=VAR6|VAR5;
8'b10011010: VAR4=VAR6^VAR5;
8'b10011011: VAR4=VAR6<<1;
8'b10011100: VAR4=VAR6>>1;
8'b10011101: VAR4=VAR6+1;
8'b10011110: VAR4=VAR6-1;
8'b10011111: VAR4=VAR6-1;
8'b10100000: VAR4=VAR6+VAR5;
8'b10100001: VAR4=VAR6-VAR5;
8'b10100010: VAR4=VAR5-1;
8'b10100011: VAR4=VAR6*VAR5;
8'b10100100: VAR4=VAR6&&VAR5;
8'b10100101: VAR4=VAR6||VAR5;
8'b10100110: VAR4=!VAR6;
8'b10100111: VAR4=~VAR6;
8'b10101000: VAR4=VAR6&VAR5;
8'b10101001: VAR4=VAR6|VAR5;
8'b10101010: VAR4=VAR6^VAR5;
8'b10101011: VAR4=VAR6<<1;
8'b10101100: VAR4=VAR6>>1;
8'b10101101: VAR4=VAR6+1;
8'b10101110: VAR4=VAR6-1;
8'b10101111: VAR4=VAR6-1;
8'b10110000: VAR4=VAR6+VAR5;
8'b10110001: VAR4=VAR6-VAR5;
8'b10110010: VAR4=VAR5-1;
8'b10110011: VAR4=VAR6*VAR5;
8'b10110100: VAR4=VAR6&&VAR5;
8'b10110101: VAR4=VAR6||VAR5;
8'b10110110: VAR4=!VAR6;
8'b10110111: VAR4=~VAR6;
8'b10111000: VAR4=VAR6&VAR5;
8'b10111001: VAR4=VAR6|VAR5;
8'b10111010: VAR4=VAR6^VAR5;
8'b10111011: VAR4=VAR6<<1;
8'b10111100: VAR4=VAR6>>1;
8'b10111101: VAR4=VAR6+1;
8'b10111110: VAR4=VAR6-1;
8'b10111111: VAR4=VAR6-1;
8'b11000000: VAR4=VAR6+VAR5;
8'b11000001: VAR4=VAR6-VAR5;
8'b11000010: VAR4=VAR5-1;
8'b11000011: VAR4=VAR6*VAR5;
8'b11000100: VAR4=VAR6&&VAR5;
8'b11000101: VAR4=VAR6||VAR5;
8'b11000110: VAR4=!VAR6;
8'b11000111: VAR4=~VAR6;
8'b11001000: VAR4=VAR6&VAR5;
8'b11001001: VAR4=VAR6|VAR5;
8'b11001010: VAR4=VAR6^VAR5;
8'b11001011: VAR4=VAR6<<1;
8'b11001100: VAR4=VAR6>>1;
8'b11001101: VAR4=VAR6+1;
8'b11001110: VAR4=VAR6-1;
8'b11001111: VAR4=VAR6-1;
8'b11010000: VAR4=VAR6+VAR5;
8'b11010001: VAR4=VAR6-VAR5;
8'b11010010: VAR4=VAR5-1;
8'b11010011: VAR4=VAR6*VAR5;
8'b11010100: VAR4=VAR6&&VAR5;
8'b11010101: VAR4=VAR6||VAR5;
8'b11010110: VAR4=!VAR6;
8'b11010111: VAR4=~VAR6;
8'b11011000: VAR4=VAR6&VAR5;
8'b11011001: VAR4=VAR6|VAR5;
8'b11011010: VAR4=VAR6^VAR5;
8'b11011011: VAR4=VAR6<<1;
8'b11011100: VAR4=VAR6>>1;
8'b11011101: VAR4=VAR6+1;
8'b11011110: VAR4=VAR6-1;
8'b11011111: VAR4=VAR6-1;
8'b11100000: VAR4=VAR6+VAR5;
8'b11100001: VAR4=VAR6-VAR5;
8'b11100010: VAR4=VAR5-1;
8'b11100011: VAR4=VAR6*VAR5;
8'b11100100: VAR4=VAR6&&VAR5;
8'b11100101: VAR4=VAR6||VAR5;
8'b11100110: VAR4=!VAR6;
8'b11100111: VAR4=~VAR6;
8'b11101000: VAR4=VAR6&VAR5;
8'b11101001: VAR4=VAR6|VAR5;
8'b11101010: VAR4=VAR6^VAR5;
8'b11101011: VAR4=VAR6<<1;
8'b11101100: VAR4=VAR6>>1;
8'b11101101: VAR4=VAR6+1;
8'b11101110: VAR4=VAR6-1;
8'b11101111: VAR4=VAR6-1;
8'b11110000: VAR4=VAR6+VAR5;
8'b11110001: VAR4=VAR6-VAR5;
8'b11110010: VAR4=VAR5-1;
8'b11110011: VAR4=VAR6*VAR5;
8'b11110100: VAR4=VAR6&&VAR5;
8'b11110101: VAR4=VAR6||VAR5;
8'b11110110: VAR4=!VAR6;
8'b11110111: VAR4=~VAR6;
8'b11111000: VAR4=VAR6&VAR5;
8'b11111001: VAR4=VAR6|VAR5;
8'b11111010: VAR4=VAR6^VAR5;
8'b11111011: VAR4=VAR6<<1;
8'b11111100: VAR4=VAR6>>1;
8'b11111101: VAR4=VAR6+1;
8'b11111110: VAR4=VAR6-1;
8'b11111111: VAR4=VAR6-1;
endcase
end
end
endmodule
|
gpl-3.0
|
CeesWolfs/ceespu
|
src/ceespu_branch_predictor.v
| 2,781 |
module MODULE1 (
input clk,
input rst,
input [31:0] VAR17,
input [13:0] VAR16,
input [13:0] VAR3,
input [1:0] VAR4,
input VAR6,
input VAR1,
output [1:0] VAR11,
output reg VAR8
);
parameter VAR10 = 6; localparam VAR7 = 0, VAR2 = 1, VAR12 = 2, VAR5 = 3;
reg [1:0] VAR15 [(2 ** VAR10) - 1:0];
reg [VAR10-1:0] VAR14 = 0;
reg [1:0] VAR9;
reg [VAR10:0] VAR13;
|
mit
|
intelligenttoasters/CPC2.0
|
FPGA/rtl/Altera/master_clock/master_clock_0002.v
| 2,145 |
module MODULE1(
input wire VAR72,
input wire rst,
output wire VAR3,
output wire VAR11,
output wire VAR67
);
VAR54 #(
.VAR43("false"),
.VAR29("50.0 VAR71"),
.VAR51("VAR5"),
.VAR59(2),
.VAR16("150.000000 VAR71"),
.VAR50("0 VAR64"),
.VAR47(50),
.VAR2("40.000000 VAR71"),
.VAR48("0 VAR64"),
.VAR20(50),
.VAR68("0 VAR71"),
.VAR8("0 VAR64"),
.VAR1(50),
.VAR15("0 VAR71"),
.VAR17("0 VAR64"),
.VAR19(50),
.VAR52("0 VAR71"),
.VAR6("0 VAR64"),
.VAR62(50),
.VAR36("0 VAR71"),
.VAR34("0 VAR64"),
.VAR14(50),
.VAR56("0 VAR71"),
.VAR35("0 VAR64"),
.VAR31(50),
.VAR63("0 VAR71"),
.VAR37("0 VAR64"),
.VAR40(50),
.VAR65("0 VAR71"),
.VAR44("0 VAR64"),
.VAR49(50),
.VAR27("0 VAR71"),
.VAR24("0 VAR64"),
.VAR58(50),
.VAR73("0 VAR71"),
.VAR22("0 VAR64"),
.VAR61(50),
.VAR42("0 VAR71"),
.VAR69("0 VAR64"),
.VAR33(50),
.VAR10("0 VAR71"),
.VAR39("0 VAR64"),
.VAR4(50),
.VAR9("0 VAR71"),
.VAR57("0 VAR64"),
.VAR53(50),
.VAR38("0 VAR71"),
.VAR41("0 VAR64"),
.VAR30(50),
.VAR18("0 VAR71"),
.VAR70("0 VAR64"),
.VAR23(50),
.VAR13("0 VAR71"),
.VAR12("0 VAR64"),
.VAR66(50),
.VAR28("0 VAR71"),
.VAR45("0 VAR64"),
.VAR26(50),
.VAR25("VAR46"),
.VAR32("VAR46")
) VAR55 (
.rst (rst),
.VAR60 ({VAR11, VAR3}),
.VAR67 (VAR67),
.VAR7 ( ),
.VAR21 (1'b0),
.VAR72 (VAR72)
);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.functional.pp.v
| 1,768 |
module MODULE1 (
VAR8 ,
VAR7 ,
VAR5,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR5;
input VAR1;
wire VAR6 ;
wire VAR9;
not VAR10 (VAR6 , VAR7 );
VAR4 VAR3 (VAR9, VAR6, VAR5, VAR1);
buf VAR2 (VAR8 , VAR9 );
endmodule
|
apache-2.0
|
carstenbru/fpga-log
|
spartanmc/hardware/uart_light/src/uart_light_clk_gen.v
| 3,201 |
module MODULE1
parameter VAR6 = 5,
parameter VAR4 = 6,
parameter VAR7 = 3
)(
output wire VAR3,
output wire VAR9,
input wire VAR8,
input wire reset
);
reg [VAR4-1:0] VAR5;
reg [VAR7-1:0] VAR1;
assign VAR9 = VAR5[VAR4-1];
assign VAR3 = VAR1[VAR7-1];
always @(posedge VAR8, posedge reset) begin
if(reset) begin
VAR5 <= {(VAR4){1'b0}};
VAR1 <= {(VAR7){1'b0}};
end
else begin
if(VAR5 == (VAR2 - 1'b1))
VAR5 <= {(VAR4){1'b0}};
end
else
VAR5 <= VAR5 + 1'b1;
if(VAR1 == (VAR6 - 1'b1))
VAR1 <= {(VAR7){1'b0}};
end
else
VAR1 <= VAR1 + 1'b1;
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.functional.pp.v
| 2,104 |
module MODULE1 (
VAR10 ,
VAR15 ,
VAR8 ,
VAR14 ,
VAR16 ,
VAR2 ,
VAR7,
VAR19,
VAR6 ,
VAR17
);
output VAR10 ;
output VAR15 ;
input VAR8 ;
input VAR14 ;
input VAR16 ;
input VAR2 ;
input VAR7;
input VAR19;
input VAR6 ;
input VAR17 ;
wire VAR5 ;
wire VAR11;
VAR4 VAR18 (VAR11, VAR14, VAR16, VAR2 );
VAR13 VAR9 VAR3 (VAR5 , VAR11, VAR8, , VAR7, VAR19);
buf VAR1 (VAR10 , VAR5 );
not VAR12 (VAR15 , VAR5 );
endmodule
|
apache-2.0
|
ankitshah009/High-Radix-Adaptive-CORDIC
|
HCORDIC_Verilog/FSM_2.v
| 106,216 |
module MODULE1(
input [31:0] VAR40, input [31:0] VAR16, input [31:0] VAR55, input [31:0] VAR50, input [31:0] VAR25,
input [31:0] VAR35,
input [31:0] VAR38,
input [1:0] VAR60, input VAR53, input VAR31,
input reset,
input VAR10,
input [1:0] VAR47, input [7:0] address,
input [3:0] VAR34, input [7:0] VAR52,
output reg [31:0] VAR46, output reg [31:0] VAR48, output reg [31:0] VAR59, output reg [31:0] VAR13, output reg [31:0] VAR61, output reg [31:0] VAR32, output reg [31:0] VAR51, output reg [1:0] VAR6,
output reg VAR27,
output reg VAR11,
output reg [7:0] VAR29
);
reg [7:0] VAR43;
reg [31:0] VAR54 [0:255];
reg [31:0] VAR58 [0:255];
reg [31:0] VAR56 [0:255];
reg [31:0] VAR57 [0:255];
reg [31:0] VAR4 [0:255];
reg [31:0] VAR36 [0:255];
reg [31:0] VAR3 [0:255];
reg [31:0] VAR30[0:255];
reg [31:0] VAR42 [0:255];
reg [31:0] VAR45 [0:255];
reg [31:0] VAR37 [0:255];
parameter VAR17 =1'b1,
VAR26 =1'b0;
parameter VAR39 =2'b01,
VAR5 =2'b00,
VAR28=2'b11;
parameter VAR1 = 4'd0,
VAR15 = 4'd1,
VAR8 = 4'd2,
VAR20 = 4'd3,
VAR41 = 4'd4,
VAR7 = 4'd5,
VAR12 = 4'd6,
VAR23 = 4'd7,
VAR2 = 4'd8,
VAR44 = 4'd9,
VAR19 = 4'd10,
VAR18= 4'd11,
VAR24 = 4'd12,
VAR21 = 4'd13,
VAR49 = 4'd14;
parameter VAR33 = 2'b00,
VAR22 = 2'b01,
VAR9 = 2'b10,
VAR14 = 2'b11;
always @ (*)
begin
case (VAR53)
VAR17 : VAR43 <= 8'b01111111 - VAR55[30:23];
VAR26 : VAR43 <= VAR16[30:23] - VAR40[30:23];
default : VAR43 <= VAR16[30:23] - VAR40[30:23];
endcase
end
always @(posedge VAR10)
begin
if(reset == 1'b1) begin
VAR54[0] <=32'h3F800000;
VAR54[1] <=32'h3F800000;
VAR54[2] <=32'h3F800000;
VAR54[3] <=32'h3F800000;
VAR54[4] <=32'h3F800000;
VAR54[5] <=32'h3F800000;
VAR54[6] <=32'h3F800000;
VAR54[7] <=32'h3F800000;
VAR54[8] <=32'h3F800000;
VAR54[9] <=32'h3F800000;
VAR54[10] <=32'h3F800000;
VAR54[11] <=32'h3F800000;
VAR54[12] <=32'h3F800000;
VAR54[13] <=32'h3F800000;
VAR54[14] <=32'h3F800000;
VAR54[15] <=32'h3F800000;
VAR54[16] <=32'h3F000000;
VAR54[17] <=32'h3F080000;
VAR54[18] <=32'h3F100000;
VAR54[19] <=32'h3F180000;
VAR54[20] <=32'h3F200000;
VAR54[21] <=32'h3F280000;
VAR54[22] <=32'h3F300000;
VAR54[23] <=32'h3F380000;
VAR54[24] <=32'h3F400000;
VAR54[25] <=32'h3F480000;
VAR54[26] <=32'h3F500000;
VAR54[27] <=32'h3F580000;
VAR54[28] <=32'h3F600000;
VAR54[29] <=32'h3F680000;
VAR54[30] <=32'h3F700000;
VAR54[31] <=32'h3F780000;
VAR54[32] <=32'h3E800000;
VAR54[33] <=32'h3E880000;
VAR54[34] <=32'h3E900000;
VAR54[35] <=32'h3E980000;
VAR54[36] <=32'h3EA00000;
VAR54[37] <=32'h3EA80000;
VAR54[38] <=32'h3EB00000;
VAR54[39] <=32'h3EB80000;
VAR54[40] <=32'h3EC00000;
VAR54[41] <=32'h3EC80000;
VAR54[42] <=32'h3ED00000;
VAR54[43] <=32'h3ED80000;
VAR54[44] <=32'h3EE00000;
VAR54[45] <=32'h3EE80000;
VAR54[46] <=32'h3EF00000;
VAR54[47] <=32'h3EF80000;
VAR54[48] <=32'h3E000000;
VAR54[49] <=32'h3E080000;
VAR54[50] <=32'h3E100000;
VAR54[51] <=32'h3E180000;
VAR54[52] <=32'h3E200000;
VAR54[53] <=32'h3E280000;
VAR54[54] <=32'h3E300000;
VAR54[55] <=32'h3E380000;
VAR54[56] <=32'h3E400000;
VAR54[57] <=32'h3E480000;
VAR54[58] <=32'h3E500000;
VAR54[59] <=32'h3E580000;
VAR54[60] <=32'h3E600000;
VAR54[61] <=32'h3E680000;
VAR54[62] <=32'h3E700000;
VAR54[63] <=32'h3E780000;
VAR54[64] <=32'h3D800000;
VAR54[65] <=32'h3D880000;
VAR54[66] <=32'h3D900000;
VAR54[67] <=32'h3D980000;
VAR54[68] <=32'h3DA00000;
VAR54[69] <=32'h3DA80000;
VAR54[70] <=32'h3DB00000;
VAR54[71] <=32'h3DB80000;
VAR54[72] <=32'h3DC00000;
VAR54[73] <=32'h3DC80000;
VAR54[74] <=32'h3DD00000;
VAR54[75] <=32'h3DD80000;
VAR54[76] <=32'h3DE00000;
VAR54[77] <=32'h3DE80000;
VAR54[78] <=32'h3DF00000;
VAR54[79] <=32'h3DF80000;
VAR54[80] <=32'h3D000000;
VAR54[81] <=32'h3D080000;
VAR54[82] <=32'h3D100000;
VAR54[83] <=32'h3D180000;
VAR54[84] <=32'h3D200000;
VAR54[85] <=32'h3D280000;
VAR54[86] <=32'h3D300000;
VAR54[87] <=32'h3D380000;
VAR54[88] <=32'h3D400000;
VAR54[89] <=32'h3D480000;
VAR54[90] <=32'h3D500000;
VAR54[91] <=32'h3D580000;
VAR54[92] <=32'h3D600000;
VAR54[93] <=32'h3D680000;
VAR54[94] <=32'h3D700000;
VAR54[95] <=32'h3D780000;
VAR54[96] <=32'h3C800000;
VAR54[97] <=32'h3C880000;
VAR54[98] <=32'h3C900000;
VAR54[99] <=32'h3C980000;
VAR54[100] <=32'h3CA00000;
VAR54[101] <=32'h3CA80000;
VAR54[102] <=32'h3CB00000;
VAR54[103] <=32'h3CB80000;
VAR54[104] <=32'h3CC00000;
VAR54[105] <=32'h3CC80000;
VAR54[106] <=32'h3CD00000;
VAR54[107] <=32'h3CD80000;
VAR54[108] <=32'h3CE00000;
VAR54[109] <=32'h3CE80000;
VAR54[110] <=32'h3CF00000;
VAR54[111] <=32'h3CF80000;
VAR54[112] <=32'h3C000000;
VAR54[113] <=32'h3C080000;
VAR54[114] <=32'h3C100000;
VAR54[115] <=32'h3C180000;
VAR54[116] <=32'h3C200000;
VAR54[117] <=32'h3C280000;
VAR54[118] <=32'h3C300000;
VAR54[119] <=32'h3C380000;
VAR54[120] <=32'h3C400000;
VAR54[121] <=32'h3C480000;
VAR54[122] <=32'h3C500000;
VAR54[123] <=32'h3C580000;
VAR54[124] <=32'h3C600000;
VAR54[125] <=32'h3C680000;
VAR54[126] <=32'h3C700000;
VAR54[127] <=32'h3C780000;
VAR54[128] <=32'h3B800000;
VAR54[129] <=32'h3B880000;
VAR54[130] <=32'h3B900000;
VAR54[131] <=32'h3B980000;
VAR54[132] <=32'h3BA00000;
VAR54[133] <=32'h3BA80000;
VAR54[134] <=32'h3BB00000;
VAR54[135] <=32'h3BB80000;
VAR54[136] <=32'h3BC00000;
VAR54[137] <=32'h3BC80000;
VAR54[138] <=32'h3BD00000;
VAR54[139] <=32'h3BD80000;
VAR54[140] <=32'h3BE00000;
VAR54[141] <=32'h3BE80000;
VAR54[142] <=32'h3BF00000;
VAR54[143] <=32'h3BF80000;
VAR54[144] <=32'h3B000000;
VAR54[145] <=32'h3B080000;
VAR54[146] <=32'h3B100000;
VAR54[147] <=32'h3B180000;
VAR54[148] <=32'h3B200000;
VAR54[149] <=32'h3B280000;
VAR54[150] <=32'h3B300000;
VAR54[151] <=32'h3B380000;
VAR54[152] <=32'h3B400000;
VAR54[153] <=32'h3B480000;
VAR54[154] <=32'h3B500000;
VAR54[155] <=32'h3B580000;
VAR54[156] <=32'h3B600000;
VAR54[157] <=32'h3B680000;
VAR54[158] <=32'h3B700000;
VAR54[159] <=32'h3B780000;
VAR54[160] <=32'h3A800000;
VAR54[161] <=32'h3A880000;
VAR54[162] <=32'h3A900000;
VAR54[163] <=32'h3A980000;
VAR54[164] <=32'h3AA00000;
VAR54[165] <=32'h3AA80000;
VAR54[166] <=32'h3AB00000;
VAR54[167] <=32'h3AB80000;
VAR54[168] <=32'h3AC00000;
VAR54[169] <=32'h3AC80000;
VAR54[170] <=32'h3AD00000;
VAR54[171] <=32'h3AD80000;
VAR54[172] <=32'h3AE00000;
VAR54[173] <=32'h3AE80000;
VAR54[174] <=32'h3AF00000;
VAR54[175] <=32'h3AF80000;
VAR54[176] <=32'h3A000000;
VAR54[177] <=32'h3A080000;
VAR54[178] <=32'h3A100000;
VAR54[179] <=32'h3A180000;
VAR54[180] <=32'h3A200000;
VAR54[181] <=32'h3A280000;
VAR54[182] <=32'h3A300000;
VAR54[183] <=32'h3A380000;
VAR54[184] <=32'h3A400000;
VAR54[185] <=32'h3A480000;
VAR54[186] <=32'h3A500000;
VAR54[187] <=32'h3A580000;
VAR54[188] <=32'h3A600000;
VAR54[189] <=32'h3A680000;
VAR54[190] <=32'h3A700000;
VAR54[191] <=32'h3A780000;
VAR54[192] <=32'h39800000;
VAR54[193] <=32'h39880000;
VAR54[194] <=32'h39900000;
VAR54[195] <=32'h39980000;
VAR54[196] <=32'h39A00000;
VAR54[197] <=32'h39A80000;
VAR54[198] <=32'h39B00000;
VAR54[199] <=32'h39B80000;
VAR54[200] <=32'h39C00000;
VAR54[201] <=32'h39C80000;
VAR54[202] <=32'h39D00000;
VAR54[203] <=32'h39D80000;
VAR54[204] <=32'h39E00000;
VAR54[205] <=32'h39E80000;
VAR54[206] <=32'h39F00000;
VAR54[207] <=32'h39F80000;
VAR54[208] <=32'h39000000;
VAR54[209] <=32'h39080000;
VAR54[210] <=32'h39100000;
VAR54[211] <=32'h39180000;
VAR54[212] <=32'h39200000;
VAR54[213] <=32'h39280000;
VAR54[214] <=32'h39300000;
VAR54[215] <=32'h39380000;
VAR54[216] <=32'h39400000;
VAR54[217] <=32'h39480000;
VAR54[218] <=32'h39500000;
VAR54[219] <=32'h39580000;
VAR54[220] <=32'h39600000;
VAR54[221] <=32'h39680000;
VAR54[222] <=32'h39700000;
VAR54[223] <=32'h39780000;
VAR54[224] <=32'h38800000;
VAR54[225] <=32'h38880000;
VAR54[226] <=32'h38900000;
VAR54[227] <=32'h38980000;
VAR54[228] <=32'h38A00000;
VAR54[229] <=32'h38A80000;
VAR54[230] <=32'h38B00000;
VAR54[231] <=32'h38B80000;
VAR54[232] <=32'h38C00000;
VAR54[233] <=32'h38C80000;
VAR54[234] <=32'h38D00000;
VAR54[235] <=32'h38D80000;
VAR54[236] <=32'h38E00000;
VAR54[237] <=32'h38E80000;
VAR54[238] <=32'h38F00000;
VAR54[239] <=32'h38F80000;
VAR54[240] <=32'h38000000;
VAR54[241] <=32'h38080000;
VAR54[242] <=32'h38100000;
VAR54[243] <=32'h38180000;
VAR54[244] <=32'h38200000;
VAR54[245] <=32'h38280000;
VAR54[246] <=32'h38300000;
VAR54[247] <=32'h38380000;
VAR54[248] <=32'h38400000;
VAR54[249] <=32'h38480000;
VAR54[250] <=32'h38500000;
VAR54[251] <=32'h38580000;
VAR54[252] <=32'h38600000;
VAR54[253] <=32'h38680000;
VAR54[254] <=32'h38700000;
VAR54[255] <=32'h38780000;
VAR58[0] <=32'h3FC75922;
VAR58[1] <=32'h3FC75922;
VAR58[2] <=32'h3FC75922;
VAR58[3] <=32'h3FC75922;
VAR58[4] <=32'h3FC75922;
VAR58[5] <=32'h3FC75922;
VAR58[6] <=32'h3FC75922;
VAR58[7] <=32'h3FC75922;
VAR58[8] <=32'h3FC75922;
VAR58[9] <=32'h3FC75922;
VAR58[10] <=32'h3FC75922;
VAR58[11] <=32'h3FC75922;
VAR58[12] <=32'h3FC75922;
VAR58[13] <=32'h3FC75922;
VAR58[14] <=32'h3FC75922;
VAR58[15] <=32'h3FC75922;
VAR58[16] <=32'h3F0BDA7A;
VAR58[17] <=32'h3F166CC7;
VAR58[18] <=32'h3F21645D;
VAR58[19] <=32'h3F2CCCD4;
VAR58[20] <=32'h3F38B334;
VAR58[21] <=32'h3F452629;
VAR58[22] <=32'h3F523659;
VAR58[23] <=32'h3F5FF6BE;
VAR58[24] <=32'h3F6E7D1B;
VAR58[25] <=32'h3F7DE288;
VAR58[26] <=32'h3F872215;
VAR58[27] <=32'h3F8FE205;
VAR58[28] <=32'h3F99451C;
VAR58[29] <=32'h3FA36319;
VAR58[30] <=32'h3FAE585F;
VAR58[31] <=32'h3FBA4729;
VAR58[32] <=32'h3E82BC2D;
VAR58[33] <=32'h3E8B4A9F;
VAR58[34] <=32'h3E93EBC5;
VAR58[35] <=32'h3E9CA0F5;
VAR58[36] <=32'h3EA56B8F;
VAR58[37] <=32'h3EAE4D00;
VAR58[38] <=32'h3EB746C2;
VAR58[39] <=32'h3EC05A5E;
VAR58[40] <=32'h3EC9896C;
VAR58[41] <=32'h3ED2D593;
VAR58[42] <=32'h3EDC408F;
VAR58[43] <=32'h3EE5CC2C;
VAR58[44] <=32'h3EEF7A4F;
VAR58[45] <=32'h3EF94CEF;
VAR58[46] <=32'h3F01A30F;
VAR58[47] <=32'h3F06B404;
VAR58[48] <=32'h3E00ABBD;
VAR58[49] <=32'h3E08CE29;
VAR58[50] <=32'h3E10F4F0;
VAR58[51] <=32'h3E192055;
VAR58[52] <=32'h3E21509E;
VAR58[53] <=32'h3E298613;
VAR58[54] <=32'h3E31C0F9;
VAR58[55] <=32'h3E3A0197;
VAR58[56] <=32'h3E424837;
VAR58[57] <=32'h3E4A9521;
VAR58[58] <=32'h3E52E89F;
VAR58[59] <=32'h3E5B42FD;
VAR58[60] <=32'h3E63A485;
VAR58[61] <=32'h3E6C0D84;
VAR58[62] <=32'h3E747E48;
VAR58[63] <=32'h3E7CF71F;
VAR58[64] <=32'h3D802ABB;
VAR58[65] <=32'h3D883344;
VAR58[66] <=32'h3D903CDE;
VAR58[67] <=32'h3D98479B;
VAR58[68] <=32'h3DA05389;
VAR58[69] <=32'h3DA860BA;
VAR58[70] <=32'h3DB06F3E;
VAR58[71] <=32'h3DB87F26;
VAR58[72] <=32'h3DC09082;
VAR58[73] <=32'h3DC8A362;
VAR58[74] <=32'h3DD0B7D7;
VAR58[75] <=32'h3DD8CDF2;
VAR58[76] <=32'h3DE0E5C4;
VAR58[77] <=32'h3DE8FF5C;
VAR58[78] <=32'h3DF11ACD;
VAR58[79] <=32'h3DF93827;
VAR58[80] <=32'h3D000AAB;
VAR58[81] <=32'h3D080CCC;
VAR58[82] <=32'h3D100F31;
VAR58[83] <=32'h3D1811DF;
VAR58[84] <=32'h3D2014D8;
VAR58[85] <=32'h3D281822;
VAR58[86] <=32'h3D301BBF;
VAR58[87] <=32'h3D381FB5;
VAR58[88] <=32'h3D402408;
VAR58[89] <=32'h3D4828BA;
VAR58[90] <=32'h3D502DD1;
VAR58[91] <=32'h3D583350;
VAR58[92] <=32'h3D60393C;
VAR58[93] <=32'h3D683F98;
VAR58[94] <=32'h3D704668;
VAR58[95] <=32'h3D784DB1;
VAR58[96] <=32'h3C8002AA;
VAR58[97] <=32'h3C880332;
VAR58[98] <=32'h3C9003CC;
VAR58[99] <=32'h3C980477;
VAR58[100] <=32'h3CA00535;
VAR58[101] <=32'h3CA80607;
VAR58[102] <=32'h3CB006EE;
VAR58[103] <=32'h3CB807EC;
VAR58[104] <=32'h3CC00900;
VAR58[105] <=32'h3CC80A2C;
VAR58[106] <=32'h3CD00B72;
VAR58[107] <=32'h3CD80CD1;
VAR58[108] <=32'h3CE00E4B;
VAR58[109] <=32'h3CE80FE2;
VAR58[110] <=32'h3CF01195;
VAR58[111] <=32'h3CF81366;
VAR58[112] <=32'h3C0000AA;
VAR58[113] <=32'h3C0800CC;
VAR58[114] <=32'h3C1000F3;
VAR58[115] <=32'h3C18011D;
VAR58[116] <=32'h3C20014D;
VAR58[117] <=32'h3C280181;
VAR58[118] <=32'h3C3001BB;
VAR58[119] <=32'h3C3801FA;
VAR58[120] <=32'h3C400240;
VAR58[121] <=32'h3C48028B;
VAR58[122] <=32'h3C5002DC;
VAR58[123] <=32'h3C580334;
VAR58[124] <=32'h3C600392;
VAR58[125] <=32'h3C6803F8;
VAR58[126] <=32'h3C700465;
VAR58[127] <=32'h3C7804D9;
VAR58[128] <=32'h3B80002A;
VAR58[129] <=32'h3B880033;
VAR58[130] <=32'h3B90003C;
VAR58[131] <=32'h3B980047;
VAR58[132] <=32'h3BA00053;
VAR58[133] <=32'h3BA80060;
VAR58[134] <=32'h3BB0006E;
VAR58[135] <=32'h3BB8007E;
VAR58[136] <=32'h3BC00090;
VAR58[137] <=32'h3BC800A2;
VAR58[138] <=32'h3BD000B7;
VAR58[139] <=32'h3BD800CD;
VAR58[140] <=32'h3BE000E4;
VAR58[141] <=32'h3BE800FE;
VAR58[142] <=32'h3BF00119;
VAR58[143] <=32'h3BF80136;
VAR58[144] <=32'h3B00000A;
VAR58[145] <=32'h3B08000C;
VAR58[146] <=32'h3B10000F;
VAR58[147] <=32'h3B180011;
VAR58[148] <=32'h3B200014;
VAR58[149] <=32'h3B280018;
VAR58[150] <=32'h3B30001B;
VAR58[151] <=32'h3B38001F;
VAR58[152] <=32'h3B400024;
VAR58[153] <=32'h3B480028;
VAR58[154] <=32'h3B50002D;
VAR58[155] <=32'h3B580033;
VAR58[156] <=32'h3B600039;
VAR58[157] <=32'h3B68003F;
VAR58[158] <=32'h3B700046;
VAR58[159] <=32'h3B78004D;
VAR58[160] <=32'h3A800002;
VAR58[161] <=32'h3A880003;
VAR58[162] <=32'h3A900003;
VAR58[163] <=32'h3A980004;
VAR58[164] <=32'h3AA00005;
VAR58[165] <=32'h3AA80006;
VAR58[166] <=32'h3AB00006;
VAR58[167] <=32'h3AB80007;
VAR58[168] <=32'h3AC00009;
VAR58[169] <=32'h3AC8000A;
VAR58[170] <=32'h3AD0000B;
VAR58[171] <=32'h3AD8000C;
VAR58[172] <=32'h3AE0000E;
VAR58[173] <=32'h3AE8000F;
VAR58[174] <=32'h3AF00011;
VAR58[175] <=32'h3AF80013;
VAR58[176] <=32'h3A000000;
VAR58[177] <=32'h3A080000;
VAR58[178] <=32'h3A100000;
VAR58[179] <=32'h3A180001;
VAR58[180] <=32'h3A200001;
VAR58[181] <=32'h3A280001;
VAR58[182] <=32'h3A300001;
VAR58[183] <=32'h3A380001;
VAR58[184] <=32'h3A400002;
VAR58[185] <=32'h3A480002;
VAR58[186] <=32'h3A500002;
VAR58[187] <=32'h3A580003;
VAR58[188] <=32'h3A600003;
VAR58[189] <=32'h3A680003;
VAR58[190] <=32'h3A700004;
VAR58[191] <=32'h3A780004;
VAR58[192] <=32'h39800000;
VAR58[193] <=32'h39880000;
VAR58[194] <=32'h39900000;
VAR58[195] <=32'h39980000;
VAR58[196] <=32'h39A00000;
VAR58[197] <=32'h39A80000;
VAR58[198] <=32'h39B00000;
VAR58[199] <=32'h39B80000;
VAR58[200] <=32'h39C00000;
VAR58[201] <=32'h39C80000;
VAR58[202] <=32'h39D00000;
VAR58[203] <=32'h39D80000;
VAR58[204] <=32'h39E00000;
VAR58[205] <=32'h39E80000;
VAR58[206] <=32'h39F00001;
VAR58[207] <=32'h39F80001;
VAR58[208] <=32'h39000000;
VAR58[209] <=32'h39080000;
VAR58[210] <=32'h39100000;
VAR58[211] <=32'h39180000;
VAR58[212] <=32'h39200000;
VAR58[213] <=32'h39280000;
VAR58[214] <=32'h39300000;
VAR58[215] <=32'h39380000;
VAR58[216] <=32'h39400000;
VAR58[217] <=32'h39480000;
VAR58[218] <=32'h39500000;
VAR58[219] <=32'h39580000;
VAR58[220] <=32'h39600000;
VAR58[221] <=32'h39680000;
VAR58[222] <=32'h39700000;
VAR58[223] <=32'h39780000;
VAR58[224] <=32'h38800000;
VAR58[225] <=32'h38880000;
VAR58[226] <=32'h38900000;
VAR58[227] <=32'h38980000;
VAR58[228] <=32'h38A00000;
VAR58[229] <=32'h38A80000;
VAR58[230] <=32'h38B00000;
VAR58[231] <=32'h38B80000;
VAR58[232] <=32'h38C00000;
VAR58[233] <=32'h38C80000;
VAR58[234] <=32'h38D00000;
VAR58[235] <=32'h38D80000;
VAR58[236] <=32'h38E00000;
VAR58[237] <=32'h38E80000;
VAR58[238] <=32'h38F00000;
VAR58[239] <=32'h38F80000;
VAR58[240] <=32'h38000000;
VAR58[241] <=32'h38080000;
VAR58[242] <=32'h38100000;
VAR58[243] <=32'h38180000;
VAR58[244] <=32'h38200000;
VAR58[245] <=32'h38280000;
VAR58[246] <=32'h38300000;
VAR58[247] <=32'h38380000;
VAR58[248] <=32'h38400000;
VAR58[249] <=32'h38480000;
VAR58[250] <=32'h38500000;
VAR58[251] <=32'h38580000;
VAR58[252] <=32'h38600000;
VAR58[253] <=32'h38680000;
VAR58[254] <=32'h38700000;
VAR58[255] <=32'h38780000;
VAR56[0] <=32'h3F42F7D5;
VAR56[1] <=32'h3F495FD9;
VAR56[2] <=32'h3F4F2E5A;
VAR56[3] <=32'h3F546DE5;
VAR56[4] <=32'h3F59291D;
VAR56[5] <=32'h3F5D6A85;
VAR56[6] <=32'h3F613C52;
VAR56[7] <=32'h3F64A851;
VAR56[8] <=32'h3F67B7CB;
VAR56[9] <=32'h3F6A737A;
VAR56[10] <=32'h3F6CE37D;
VAR56[11] <=32'h3F6F0F5A;
VAR56[12] <=32'h3F70FDFC;
VAR56[13] <=32'h3F72B5B7;
VAR56[14] <=32'h3F743C4F;
VAR56[15] <=32'h3F7596FF;
VAR56[16] <=32'h3EEC9A9E;
VAR56[17] <=32'h3EF90108;
VAR56[18] <=32'h3F028437;
VAR56[19] <=32'h3F0857A3;
VAR56[20] <=32'h3F0DFA3F;
VAR56[21] <=32'h3F136BB7;
VAR56[22] <=32'h3F18ABEF;
VAR56[23] <=32'h3F1DBAFC;
VAR56[24] <=32'h3F22991F;
VAR56[25] <=32'h3F2746C4;
VAR56[26] <=32'h3F2BC47F;
VAR56[27] <=32'h3F301304;
VAR56[28] <=32'h3F343328;
VAR56[29] <=32'h3F3825D8;
VAR56[30] <=32'h3F3BEC1C;
VAR56[31] <=32'h3F3F870D;
VAR56[32] <=32'h3E7ACBF5;
VAR56[33] <=32'h3E84E3A2;
VAR56[34] <=32'h3E8C51CC;
VAR56[35] <=32'h3E93AFBF;
VAR56[36] <=32'h3E9AFCC5;
VAR56[37] <=32'h3EA23832;
VAR56[38] <=32'h3EA96162;
VAR56[39] <=32'h3EB077B8;
VAR56[40] <=32'h3EB77A9E;
VAR56[41] <=32'h3EBE6988;
VAR56[42] <=32'h3EC543F0;
VAR56[43] <=32'h3ECC0959;
VAR56[44] <=32'h3ED2B94F;
VAR56[45] <=32'h3ED95364;
VAR56[46] <=32'h3EDFD735;
VAR56[47] <=32'h3EE64464;
VAR56[48] <=32'h3DFEACC9;
VAR56[49] <=32'h3E0734B9;
VAR56[50] <=32'h3E0F0EE8;
VAR56[51] <=32'h3E16E4B4;
VAR56[52] <=32'h3E1EB5E3;
VAR56[53] <=32'h3E26823C;
VAR56[54] <=32'h3E2E4983;
VAR56[55] <=32'h3E360B81;
VAR56[56] <=32'h3E3DC7FC;
VAR56[57] <=32'h3E457EBD;
VAR56[58] <=32'h3E4D2F8D;
VAR56[59] <=32'h3E54DA36;
VAR56[60] <=32'h3E5C7E82;
VAR56[61] <=32'h3E641C3B;
VAR56[62] <=32'h3E6BB32E;
VAR56[63] <=32'h3E734327;
VAR56[64] <=32'h3D7FAACC;
VAR56[65] <=32'h3D87CCE9;
VAR56[66] <=32'h3D8FC35E;
VAR56[67] <=32'h3D97B8B5;
VAR56[68] <=32'h3D9FACDE;
VAR56[69] <=32'h3DA79FCA;
VAR56[70] <=32'h3DAF9168;
VAR56[71] <=32'h3DB781AB;
VAR56[72] <=32'h3DBF7081;
VAR56[73] <=32'h3DC75DDB;
VAR56[74] <=32'h3DCF49AB;
VAR56[75] <=32'h3DD733E0;
VAR56[76] <=32'h3DDF1C6C;
VAR56[77] <=32'h3DE7033E;
VAR56[78] <=32'h3DEEE849;
VAR56[79] <=32'h3DF6CB7C;
VAR56[80] <=32'h3CFFEAAC;
VAR56[81] <=32'h3D07F336;
VAR56[82] <=32'h3D0FF0D1;
VAR56[83] <=32'h3D17EE25;
VAR56[84] <=32'h3D1FEB2D;
VAR56[85] <=32'h3D27E7E6;
VAR56[86] <=32'h3D2FE44A;
VAR56[87] <=32'h3D37E057;
VAR56[88] <=32'h3D3FDC08;
VAR56[89] <=32'h3D47D759;
VAR56[90] <=32'h3D4FD246;
VAR56[91] <=32'h3D57CCCC;
VAR56[92] <=32'h3D5FC6E6;
VAR56[93] <=32'h3D67C091;
VAR56[94] <=32'h3D6FB9C8;
VAR56[95] <=32'h3D77B288;
VAR56[96] <=32'h3C7FFAAA;
VAR56[97] <=32'h3C87FCCD;
VAR56[98] <=32'h3C8FFC34;
VAR56[99] <=32'h3C97FB88;
VAR56[100] <=32'h3C9FFACA;
VAR56[101] <=32'h3CA7F9F8;
VAR56[102] <=32'h3CAFF911;
VAR56[103] <=32'h3CB7F814;
VAR56[104] <=32'h3CBFF700;
VAR56[105] <=32'h3CC7F5D4;
VAR56[106] <=32'h3CCFF48F;
VAR56[107] <=32'h3CD7F330;
VAR56[108] <=32'h3CDFF1B6;
VAR56[109] <=32'h3CE7F020;
VAR56[110] <=32'h3CEFEE6D;
VAR56[111] <=32'h3CF7EC9C;
VAR56[112] <=32'h3BFFFEAA;
VAR56[113] <=32'h3C07FF33;
VAR56[114] <=32'h3C0FFF0D;
VAR56[115] <=32'h3C17FEE2;
VAR56[116] <=32'h3C1FFEB2;
VAR56[117] <=32'h3C27FE7E;
VAR56[118] <=32'h3C2FFE44;
VAR56[119] <=32'h3C37FE05;
VAR56[120] <=32'h3C3FFDC0;
VAR56[121] <=32'h3C47FD74;
VAR56[122] <=32'h3C4FFD23;
VAR56[123] <=32'h3C57FCCB;
VAR56[124] <=32'h3C5FFC6D;
VAR56[125] <=32'h3C67FC07;
VAR56[126] <=32'h3C6FFB9B;
VAR56[127] <=32'h3C77FB26;
VAR56[128] <=32'h3B7FFFAA;
VAR56[129] <=32'h3B87FFCC;
VAR56[130] <=32'h3B8FFFC3;
VAR56[131] <=32'h3B97FFB8;
VAR56[132] <=32'h3B9FFFAC;
VAR56[133] <=32'h3BA7FF9F;
VAR56[134] <=32'h3BAFFF91;
VAR56[135] <=32'h3BB7FF81;
VAR56[136] <=32'h3BBFFF70;
VAR56[137] <=32'h3BC7FF5D;
VAR56[138] <=32'h3BCFFF48;
VAR56[139] <=32'h3BD7FF32;
VAR56[140] <=32'h3BDFFF1B;
VAR56[141] <=32'h3BE7FF01;
VAR56[142] <=32'h3BEFFEE6;
VAR56[143] <=32'h3BF7FEC9;
VAR56[144] <=32'h3AFFFFEA;
VAR56[145] <=32'h3B07FFF3;
VAR56[146] <=32'h3B0FFFF0;
VAR56[147] <=32'h3B17FFEE;
VAR56[148] <=32'h3B1FFFEB;
VAR56[149] <=32'h3B27FFE7;
VAR56[150] <=32'h3B2FFFE4;
VAR56[151] <=32'h3B37FFE0;
VAR56[152] <=32'h3B3FFFDC;
VAR56[153] <=32'h3B47FFD7;
VAR56[154] <=32'h3B4FFFD2;
VAR56[155] <=32'h3B57FFCC;
VAR56[156] <=32'h3B5FFFC6;
VAR56[157] <=32'h3B67FFC0;
VAR56[158] <=32'h3B6FFFB9;
VAR56[159] <=32'h3B77FFB2;
VAR56[160] <=32'h3A7FFFFA;
VAR56[161] <=32'h3A87FFFC;
VAR56[162] <=32'h3A8FFFFC;
VAR56[163] <=32'h3A97FFFB;
VAR56[164] <=32'h3A9FFFFA;
VAR56[165] <=32'h3AA7FFF9;
VAR56[166] <=32'h3AAFFFF9;
VAR56[167] <=32'h3AB7FFF8;
VAR56[168] <=32'h3ABFFFF7;
VAR56[169] <=32'h3AC7FFF5;
VAR56[170] <=32'h3ACFFFF4;
VAR56[171] <=32'h3AD7FFF3;
VAR56[172] <=32'h3ADFFFF1;
VAR56[173] <=32'h3AE7FFF0;
VAR56[174] <=32'h3AEFFFEE;
VAR56[175] <=32'h3AF7FFEC;
VAR56[176] <=32'h39FFFFFE;
VAR56[177] <=32'h3A07FFFF;
VAR56[178] <=32'h3A0FFFFF;
VAR56[179] <=32'h3A17FFFE;
VAR56[180] <=32'h3A1FFFFE;
VAR56[181] <=32'h3A27FFFE;
VAR56[182] <=32'h3A2FFFFE;
VAR56[183] <=32'h3A37FFFE;
VAR56[184] <=32'h3A3FFFFD;
VAR56[185] <=32'h3A47FFFD;
VAR56[186] <=32'h3A4FFFFD;
VAR56[187] <=32'h3A57FFFC;
VAR56[188] <=32'h3A5FFFFC;
VAR56[189] <=32'h3A67FFFC;
VAR56[190] <=32'h3A6FFFFB;
VAR56[191] <=32'h3A77FFFB;
VAR56[192] <=32'h397FFFFF;
VAR56[193] <=32'h3987FFFF;
VAR56[194] <=32'h398FFFFF;
VAR56[195] <=32'h3997FFFF;
VAR56[196] <=32'h399FFFFF;
VAR56[197] <=32'h39A7FFFF;
VAR56[198] <=32'h39AFFFFF;
VAR56[199] <=32'h39B7FFFF;
VAR56[200] <=32'h39BFFFFF;
VAR56[201] <=32'h39C7FFFF;
VAR56[202] <=32'h39CFFFFF;
VAR56[203] <=32'h39D7FFFF;
VAR56[204] <=32'h39DFFFFF;
VAR56[205] <=32'h39E7FFFF;
VAR56[206] <=32'h39EFFFFE;
VAR56[207] <=32'h39F7FFFE;
VAR56[208] <=32'h38FFFFFF;
VAR56[209] <=32'h3907FFFF;
VAR56[210] <=32'h390FFFFF;
VAR56[211] <=32'h3917FFFF;
VAR56[212] <=32'h391FFFFF;
VAR56[213] <=32'h3927FFFF;
VAR56[214] <=32'h392FFFFF;
VAR56[215] <=32'h3937FFFF;
VAR56[216] <=32'h393FFFFF;
VAR56[217] <=32'h3947FFFF;
VAR56[218] <=32'h394FFFFF;
VAR56[219] <=32'h3957FFFF;
VAR56[220] <=32'h395FFFFF;
VAR56[221] <=32'h3967FFFF;
VAR56[222] <=32'h396FFFFF;
VAR56[223] <=32'h3977FFFF;
VAR56[224] <=32'h387FFFFF;
VAR56[225] <=32'h3887FFFF;
VAR56[226] <=32'h388FFFFF;
VAR56[227] <=32'h3897FFFF;
VAR56[228] <=32'h389FFFFF;
VAR56[229] <=32'h38A7FFFF;
VAR56[230] <=32'h38AFFFFF;
VAR56[231] <=32'h38B7FFFF;
VAR56[232] <=32'h38BFFFFF;
VAR56[233] <=32'h38C7FFFF;
VAR56[234] <=32'h38CFFFFF;
VAR56[235] <=32'h38D7FFFF;
VAR56[236] <=32'h38DFFFFF;
VAR56[237] <=32'h38E7FFFF;
VAR56[238] <=32'h38EFFFFF;
VAR56[239] <=32'h38F7FFFF;
VAR56[240] <=32'h37FFFFFF;
VAR56[241] <=32'h3807FFFF;
VAR56[242] <=32'h380FFFFF;
VAR56[243] <=32'h3817FFFF;
VAR56[244] <=32'h381FFFFF;
VAR56[245] <=32'h3827FFFF;
VAR56[246] <=32'h382FFFFF;
VAR56[247] <=32'h3837FFFF;
VAR56[248] <=32'h383FFFFF;
VAR56[249] <=32'h3847FFFF;
VAR56[250] <=32'h384FFFFF;
VAR56[251] <=32'h3857FFFF;
VAR56[252] <=32'h385FFFFF;
VAR56[253] <=32'h3867FFFF;
VAR56[254] <=32'h386FFFFF;
VAR56[255] <=32'h3877FFFF;
VAR57[0] <=32'h3F0A5142;
VAR57[1] <=32'h3F0A5142;
VAR57[2] <=32'h3F0A5142;
VAR57[3] <=32'h3F0A5142;
VAR57[4] <=32'h3F0A5142;
VAR57[5] <=32'h3F0A5142;
VAR57[6] <=32'h3F0A5142;
VAR57[7] <=32'h3F0A5142;
VAR57[8] <=32'h3F0A5142;
VAR57[9] <=32'h3F0A5142;
VAR57[10] <=32'h3F0A5142;
VAR57[11] <=32'h3F0A5142;
VAR57[12] <=32'h3F0A5142;
VAR57[13] <=32'h3F0A5142;
VAR57[14] <=32'h3F0A5142;
VAR57[15] <=32'h3F0A5142;
VAR57[16] <=32'h3F60A941;
VAR57[17] <=32'h3F5CB779;
VAR57[18] <=32'h3F588E83;
VAR57[19] <=32'h3F542F6B;
VAR57[20] <=32'h3F4F9B49;
VAR57[21] <=32'h3F4AD340;
VAR57[22] <=32'h3F45D884;
VAR57[23] <=32'h3F40AC53;
VAR57[24] <=32'h3F3B4FF7;
VAR57[25] <=32'h3F35C4C9;
VAR57[26] <=32'h3F300C2A;
VAR57[27] <=32'h3F2A278A;
VAR57[28] <=32'h3F241860;
VAR57[29] <=32'h3F1DE031;
VAR57[30] <=32'h3F17808B;
VAR57[31] <=32'h3F10FB05;
VAR57[32] <=32'h3F780AA6;
VAR57[33] <=32'h3F770591;
VAR57[34] <=32'h3F75F10C;
VAR57[35] <=32'h3F74CD27;
VAR57[36] <=32'h3F7399F6;
VAR57[37] <=32'h3F72578C;
VAR57[38] <=32'h3F7105FB;
VAR57[39] <=32'h3F6FA55B;
VAR57[40] <=32'h3F6E35C1;
VAR57[41] <=32'h3F6CB743;
VAR57[42] <=32'h3F6B29F9;
VAR57[43] <=32'h3F698DFE;
VAR57[44] <=32'h3F67E369;
VAR57[45] <=32'h3F662A56;
VAR57[46] <=32'h3F6462E1;
VAR57[47] <=32'h3F628D26;
VAR57[48] <=32'h3F7E00AC;
VAR57[49] <=32'h3F7DBEDB;
VAR57[50] <=32'h3F7D7912;
VAR57[51] <=32'h3F7D2F54;
VAR57[52] <=32'h3F7CE1A2;
VAR57[53] <=32'h3F7C8FFB;
VAR57[54] <=32'h3F7C3A63;
VAR57[55] <=32'h3F7BE0D9;
VAR57[56] <=32'h3F7B8360;
VAR57[57] <=32'h3F7B21F9;
VAR57[58] <=32'h3F7ABCA6;
VAR57[59] <=32'h3F7A5367;
VAR57[60] <=32'h3F79E63F;
VAR57[61] <=32'h3F797530;
VAR57[62] <=32'h3F79003B;
VAR57[63] <=32'h3F788761;
VAR57[64] <=32'h3F7F800C;
VAR57[65] <=32'h3F7F6F8F;
VAR57[66] <=32'h3F7F5E12;
VAR57[67] <=32'h3F7F4B96;
VAR57[68] <=32'h3F7F381B;
VAR57[69] <=32'h3F7F23A1;
VAR57[70] <=32'h3F7F0E27;
VAR57[71] <=32'h3F7EF7AF;
VAR57[72] <=32'h3F7EE037;
VAR57[73] <=32'h3F7EC7C1;
VAR57[74] <=32'h3F7EAE4C;
VAR57[75] <=32'h3F7E93D8;
VAR57[76] <=32'h3F7E7865;
VAR57[77] <=32'h3F7E5BF4;
VAR57[78] <=32'h3F7E3E85;
VAR57[79] <=32'h3F7E2017;
VAR57[80] <=32'h3F7FE002;
VAR57[81] <=32'h3F7FDBE2;
VAR57[82] <=32'h3F7FD782;
VAR57[83] <=32'h3F7FD2E3;
VAR57[84] <=32'h3F7FCE03;
VAR57[85] <=32'h3F7FC8E3;
VAR57[86] <=32'h3F7FC384;
VAR57[87] <=32'h3F7FBDE4;
VAR57[88] <=32'h3F7FB805;
VAR57[89] <=32'h3F7FB1E5;
VAR57[90] <=32'h3F7FAB86;
VAR57[91] <=32'h3F7FA4E7;
VAR57[92] <=32'h3F7F9E07;
VAR57[93] <=32'h3F7F96E8;
VAR57[94] <=32'h3F7F8F89;
VAR57[95] <=32'h3F7F87EB;
VAR57[96] <=32'h3F7FF801;
VAR57[97] <=32'h3F7FF6F9;
VAR57[98] <=32'h3F7FF5E1;
VAR57[99] <=32'h3F7FF4B9;
VAR57[100] <=32'h3F7FF381;
VAR57[101] <=32'h3F7FF239;
VAR57[102] <=32'h3F7FF0E1;
VAR57[103] <=32'h3F7FEF79;
VAR57[104] <=32'h3F7FEE01;
VAR57[105] <=32'h3F7FEC79;
VAR57[106] <=32'h3F7FEAE1;
VAR57[107] <=32'h3F7FE93A;
VAR57[108] <=32'h3F7FE782;
VAR57[109] <=32'h3F7FE5BA;
VAR57[110] <=32'h3F7FE3E2;
VAR57[111] <=32'h3F7FE1FA;
VAR57[112] <=32'h3F7FFE01;
VAR57[113] <=32'h3F7FFDBF;
VAR57[114] <=32'h3F7FFD79;
VAR57[115] <=32'h3F7FFD2F;
VAR57[116] <=32'h3F7FFCE1;
VAR57[117] <=32'h3F7FFC8F;
VAR57[118] <=32'h3F7FFC39;
VAR57[119] <=32'h3F7FFBDF;
VAR57[120] <=32'h3F7FFB81;
VAR57[121] <=32'h3F7FFB1F;
VAR57[122] <=32'h3F7FFAB9;
VAR57[123] <=32'h3F7FFA4F;
VAR57[124] <=32'h3F7FF9E1;
VAR57[125] <=32'h3F7FF96F;
VAR57[126] <=32'h3F7FF8F9;
VAR57[127] <=32'h3F7FF87F;
VAR57[128] <=32'h3F7FFF81;
VAR57[129] <=32'h3F7FFF71;
VAR57[130] <=32'h3F7FFF5F;
VAR57[131] <=32'h3F7FFF4D;
VAR57[132] <=32'h3F7FFF39;
VAR57[133] <=32'h3F7FFF25;
VAR57[134] <=32'h3F7FFF0F;
VAR57[135] <=32'h3F7FFEF9;
VAR57[136] <=32'h3F7FFEE1;
VAR57[137] <=32'h3F7FFEC9;
VAR57[138] <=32'h3F7FFEAF;
VAR57[139] <=32'h3F7FFE95;
VAR57[140] <=32'h3F7FFE79;
VAR57[141] <=32'h3F7FFE5D;
VAR57[142] <=32'h3F7FFE3F;
VAR57[143] <=32'h3F7FFE21;
VAR57[144] <=32'h3F7FFFE1;
VAR57[145] <=32'h3F7FFFDD;
VAR57[146] <=32'h3F7FFFD9;
VAR57[147] <=32'h3F7FFFD4;
VAR57[148] <=32'h3F7FFFCF;
VAR57[149] <=32'h3F7FFFCA;
VAR57[150] <=32'h3F7FFFC5;
VAR57[151] <=32'h3F7FFFBF;
VAR57[152] <=32'h3F7FFFB9;
VAR57[153] <=32'h3F7FFFB3;
VAR57[154] <=32'h3F7FFFAD;
VAR57[155] <=32'h3F7FFFA6;
VAR57[156] <=32'h3F7FFF9F;
VAR57[157] <=32'h3F7FFF98;
VAR57[158] <=32'h3F7FFF91;
VAR57[159] <=32'h3F7FFF89;
VAR57[160] <=32'h3F7FFFF9;
VAR57[161] <=32'h3F7FFFF8;
VAR57[162] <=32'h3F7FFFF7;
VAR57[163] <=32'h3F7FFFF6;
VAR57[164] <=32'h3F7FFFF5;
VAR57[165] <=32'h3F7FFFF3;
VAR57[166] <=32'h3F7FFFF2;
VAR57[167] <=32'h3F7FFFF1;
VAR57[168] <=32'h3F7FFFEF;
VAR57[169] <=32'h3F7FFFEE;
VAR57[170] <=32'h3F7FFFEC;
VAR57[171] <=32'h3F7FFFEA;
VAR57[172] <=32'h3F7FFFE9;
VAR57[173] <=32'h3F7FFFE7;
VAR57[174] <=32'h3F7FFFE5;
VAR57[175] <=32'h3F7FFFE3;
VAR57[176] <=32'h3F7FFFFF;
VAR57[177] <=32'h3F7FFFFF;
VAR57[178] <=32'h3F7FFFFF;
VAR57[179] <=32'h3F7FFFFE;
VAR57[180] <=32'h3F7FFFFE;
VAR57[181] <=32'h3F7FFFFE;
VAR57[182] <=32'h3F7FFFFD;
VAR57[183] <=32'h3F7FFFFD;
VAR57[184] <=32'h3F7FFFFD;
VAR57[185] <=32'h3F7FFFFC;
VAR57[186] <=32'h3F7FFFFC;
VAR57[187] <=32'h3F7FFFFB;
VAR57[188] <=32'h3F7FFFFB;
VAR57[189] <=32'h3F7FFFFB;
VAR57[190] <=32'h3F7FFFFA;
VAR57[191] <=32'h3F7FFFFA;
VAR57[192] <=32'h3F800000;
VAR57[193] <=32'h3F800000;
VAR57[194] <=32'h3F800000;
VAR57[195] <=32'h3F800000;
VAR57[196] <=32'h3F800000;
VAR57[197] <=32'h3F800000;
VAR57[198] <=32'h3F800000;
VAR57[199] <=32'h3F800000;
VAR57[200] <=32'h3F800000;
VAR57[201] <=32'h3F800000;
VAR57[202] <=32'h3F800000;
VAR57[203] <=32'h3F800000;
VAR57[204] <=32'h3F800000;
VAR57[205] <=32'h3F800000;
VAR57[206] <=32'h3F7FFFFF;
VAR57[207] <=32'h3F7FFFFF;
VAR57[208] <=32'h3F800000;
VAR57[209] <=32'h3F800000;
VAR57[210] <=32'h3F800000;
VAR57[211] <=32'h3F800000;
VAR57[212] <=32'h3F800000;
VAR57[213] <=32'h3F800000;
VAR57[214] <=32'h3F800000;
VAR57[215] <=32'h3F800000;
VAR57[216] <=32'h3F800000;
VAR57[217] <=32'h3F800000;
VAR57[218] <=32'h3F800000;
VAR57[219] <=32'h3F800000;
VAR57[220] <=32'h3F800000;
VAR57[221] <=32'h3F800000;
VAR57[222] <=32'h3F800000;
VAR57[223] <=32'h3F800000;
VAR57[224] <=32'h3F800000;
VAR57[225] <=32'h3F800000;
VAR57[226] <=32'h3F800000;
VAR57[227] <=32'h3F800000;
VAR57[228] <=32'h3F800000;
VAR57[229] <=32'h3F800000;
VAR57[230] <=32'h3F800000;
VAR57[231] <=32'h3F800000;
VAR57[232] <=32'h3F800000;
VAR57[233] <=32'h3F800000;
VAR57[234] <=32'h3F800000;
VAR57[235] <=32'h3F800000;
VAR57[236] <=32'h3F800000;
VAR57[237] <=32'h3F800000;
VAR57[238] <=32'h3F800000;
VAR57[239] <=32'h3F800000;
VAR57[240] <=32'h3F800000;
VAR57[241] <=32'h3F800000;
VAR57[242] <=32'h3F800000;
VAR57[243] <=32'h3F800000;
VAR57[244] <=32'h3F800000;
VAR57[245] <=32'h3F800000;
VAR57[246] <=32'h3F800000;
VAR57[247] <=32'h3F800000;
VAR57[248] <=32'h3F800000;
VAR57[249] <=32'h3F800000;
VAR57[250] <=32'h3F800000;
VAR57[251] <=32'h3F800000;
VAR57[252] <=32'h3F800000;
VAR57[253] <=32'h3F800000;
VAR57[254] <=32'h3F800000;
VAR57[255] <=32'h3F800000;
VAR4[0] <=32'h3FC583AB;
VAR4[1] <=32'h3FCF4ED6;
VAR4[2] <=32'h3FD9E961;
VAR4[3] <=32'h3FE55DE8;
VAR4[4] <=32'h3FF1B7E0;
VAR4[5] <=32'h3FFF03A4;
VAR4[6] <=32'h4006A740;
VAR4[7] <=32'h400E5361;
VAR4[8] <=32'h40168DE1;
VAR4[9] <=32'h401F5EFB;
VAR4[10] <=32'h4028CF82;
VAR4[11] <=32'h4032E8E7;
VAR4[12] <=32'h403DB543;
VAR4[13] <=32'h40493F64;
VAR4[14] <=32'h405592D5;
VAR4[15] <=32'h4062BBEB;
VAR4[16] <=32'h3F90560D;
VAR4[17] <=32'h3F927DC8;
VAR4[18] <=32'h3F94CA23;
VAR4[19] <=32'h3F973BB2;
VAR4[20] <=32'h3F99D311;
VAR4[21] <=32'h3F9C90E5;
VAR4[22] <=32'h3F9F75DE;
VAR4[23] <=32'h3FA282B6;
VAR4[24] <=32'h3FA5B82F;
VAR4[25] <=32'h3FA91717;
VAR4[26] <=32'h3FACA045;
VAR4[27] <=32'h3FB0549D;
VAR4[28] <=32'h3FB4350B;
VAR4[29] <=32'h3FB84286;
VAR4[30] <=32'h3FBC7E14;
VAR4[31] <=32'h3FC0E8C2;
VAR4[32] <=32'h3F840559;
VAR4[33] <=32'h3F848AD0;
VAR4[34] <=32'h3F851891;
VAR4[35] <=32'h3F85AEA3;
VAR4[36] <=32'h3F864D11;
VAR4[37] <=32'h3F86F3E3;
VAR4[38] <=32'h3F87A324;
VAR4[39] <=32'h3F885AE0;
VAR4[40] <=32'h3F891B21;
VAR4[41] <=32'h3F89E3F4;
VAR4[42] <=32'h3F8AB565;
VAR4[43] <=32'h3F8B8F82;
VAR4[44] <=32'h3F8C7258;
VAR4[45] <=32'h3F8D5DF5;
VAR4[46] <=32'h3F8E5267;
VAR4[47] <=32'h3F8F4FBF;
VAR4[48] <=32'h3F810056;
VAR4[49] <=32'h3F81216D;
VAR4[50] <=32'h3F814489;
VAR4[51] <=32'h3F8169AA;
VAR4[52] <=32'h3F8190D1;
VAR4[53] <=32'h3F81B9FE;
VAR4[54] <=32'h3F81E532;
VAR4[55] <=32'h3F82126D;
VAR4[56] <=32'h3F8241B1;
VAR4[57] <=32'h3F8272FE;
VAR4[58] <=32'h3F82A654;
VAR4[59] <=32'h3F82DBB5;
VAR4[60] <=32'h3F831322;
VAR4[61] <=32'h3F834C9B;
VAR4[62] <=32'h3F838821;
VAR4[63] <=32'h3F83C5B5;
VAR4[64] <=32'h3F804006;
VAR4[65] <=32'h3F804847;
VAR4[66] <=32'h3F805109;
VAR4[67] <=32'h3F805A4B;
VAR4[68] <=32'h3F80640D;
VAR4[69] <=32'h3F806E50;
VAR4[70] <=32'h3F807913;
VAR4[71] <=32'h3F808457;
VAR4[72] <=32'h3F80901B;
VAR4[73] <=32'h3F809C60;
VAR4[74] <=32'h3F80A926;
VAR4[75] <=32'h3F80B66C;
VAR4[76] <=32'h3F80C432;
VAR4[77] <=32'h3F80D27A;
VAR4[78] <=32'h3F80E142;
VAR4[79] <=32'h3F80F08C;
VAR4[80] <=32'h3F801001;
VAR4[81] <=32'h3F801211;
VAR4[82] <=32'h3F801441;
VAR4[83] <=32'h3F801691;
VAR4[84] <=32'h3F801901;
VAR4[85] <=32'h3F801B91;
VAR4[86] <=32'h3F801E42;
VAR4[87] <=32'h3F802112;
VAR4[88] <=32'h3F802402;
VAR4[89] <=32'h3F802712;
VAR4[90] <=32'h3F802A43;
VAR4[91] <=32'h3F802D93;
VAR4[92] <=32'h3F803103;
VAR4[93] <=32'h3F803494;
VAR4[94] <=32'h3F803844;
VAR4[95] <=32'h3F803C15;
VAR4[96] <=32'h3F800400;
VAR4[97] <=32'h3F800484;
VAR4[98] <=32'h3F800510;
VAR4[99] <=32'h3F8005A4;
VAR4[100] <=32'h3F800640;
VAR4[101] <=32'h3F8006E4;
VAR4[102] <=32'h3F800790;
VAR4[103] <=32'h3F800844;
VAR4[104] <=32'h3F800900;
VAR4[105] <=32'h3F8009C4;
VAR4[106] <=32'h3F800A90;
VAR4[107] <=32'h3F800B65;
VAR4[108] <=32'h3F800C41;
VAR4[109] <=32'h3F800D25;
VAR4[110] <=32'h3F800E11;
VAR4[111] <=32'h3F800F05;
VAR4[112] <=32'h3F800100;
VAR4[113] <=32'h3F800121;
VAR4[114] <=32'h3F800144;
VAR4[115] <=32'h3F800169;
VAR4[116] <=32'h3F800190;
VAR4[117] <=32'h3F8001B9;
VAR4[118] <=32'h3F8001E4;
VAR4[119] <=32'h3F800211;
VAR4[120] <=32'h3F800240;
VAR4[121] <=32'h3F800271;
VAR4[122] <=32'h3F8002A4;
VAR4[123] <=32'h3F8002D9;
VAR4[124] <=32'h3F800310;
VAR4[125] <=32'h3F800349;
VAR4[126] <=32'h3F800384;
VAR4[127] <=32'h3F8003C1;
VAR4[128] <=32'h3F800040;
VAR4[129] <=32'h3F800049;
VAR4[130] <=32'h3F800051;
VAR4[131] <=32'h3F80005B;
VAR4[132] <=32'h3F800064;
VAR4[133] <=32'h3F80006F;
VAR4[134] <=32'h3F800079;
VAR4[135] <=32'h3F800085;
VAR4[136] <=32'h3F800090;
VAR4[137] <=32'h3F80009D;
VAR4[138] <=32'h3F8000A9;
VAR4[139] <=32'h3F8000B7;
VAR4[140] <=32'h3F8000C4;
VAR4[141] <=32'h3F8000D3;
VAR4[142] <=32'h3F8000E1;
VAR4[143] <=32'h3F8000F1;
VAR4[144] <=32'h3F800010;
VAR4[145] <=32'h3F800012;
VAR4[146] <=32'h3F800015;
VAR4[147] <=32'h3F800017;
VAR4[148] <=32'h3F800019;
VAR4[149] <=32'h3F80001C;
VAR4[150] <=32'h3F80001F;
VAR4[151] <=32'h3F800021;
VAR4[152] <=32'h3F800024;
VAR4[153] <=32'h3F800027;
VAR4[154] <=32'h3F80002B;
VAR4[155] <=32'h3F80002E;
VAR4[156] <=32'h3F800031;
VAR4[157] <=32'h3F800035;
VAR4[158] <=32'h3F800039;
VAR4[159] <=32'h3F80003C;
VAR4[160] <=32'h3F800004;
VAR4[161] <=32'h3F800005;
VAR4[162] <=32'h3F800005;
VAR4[163] <=32'h3F800006;
VAR4[164] <=32'h3F800007;
VAR4[165] <=32'h3F800007;
VAR4[166] <=32'h3F800008;
VAR4[167] <=32'h3F800009;
VAR4[168] <=32'h3F800009;
VAR4[169] <=32'h3F80000A;
VAR4[170] <=32'h3F80000B;
VAR4[171] <=32'h3F80000C;
VAR4[172] <=32'h3F80000D;
VAR4[173] <=32'h3F80000D;
VAR4[174] <=32'h3F80000E;
VAR4[175] <=32'h3F80000F;
VAR4[176] <=32'h3F800001;
VAR4[177] <=32'h3F800001;
VAR4[178] <=32'h3F800002;
VAR4[179] <=32'h3F800002;
VAR4[180] <=32'h3F800002;
VAR4[181] <=32'h3F800002;
VAR4[182] <=32'h3F800002;
VAR4[183] <=32'h3F800002;
VAR4[184] <=32'h3F800003;
VAR4[185] <=32'h3F800003;
VAR4[186] <=32'h3F800003;
VAR4[187] <=32'h3F800003;
VAR4[188] <=32'h3F800003;
VAR4[189] <=32'h3F800004;
VAR4[190] <=32'h3F800004;
VAR4[191] <=32'h3F800004;
VAR4[192] <=32'h3F800001;
VAR4[193] <=32'h3F800001;
VAR4[194] <=32'h3F800001;
VAR4[195] <=32'h3F800001;
VAR4[196] <=32'h3F800001;
VAR4[197] <=32'h3F800001;
VAR4[198] <=32'h3F800001;
VAR4[199] <=32'h3F800001;
VAR4[200] <=32'h3F800001;
VAR4[201] <=32'h3F800001;
VAR4[202] <=32'h3F800001;
VAR4[203] <=32'h3F800001;
VAR4[204] <=32'h3F800001;
VAR4[205] <=32'h3F800001;
VAR4[206] <=32'h3F800001;
VAR4[207] <=32'h3F800001;
VAR4[208] <=32'h3F800000;
VAR4[209] <=32'h3F800000;
VAR4[210] <=32'h3F800000;
VAR4[211] <=32'h3F800000;
VAR4[212] <=32'h3F800000;
VAR4[213] <=32'h3F800000;
VAR4[214] <=32'h3F800000;
VAR4[215] <=32'h3F800000;
VAR4[216] <=32'h3F800000;
VAR4[217] <=32'h3F800000;
VAR4[218] <=32'h3F800001;
VAR4[219] <=32'h3F800001;
VAR4[220] <=32'h3F800001;
VAR4[221] <=32'h3F800001;
VAR4[222] <=32'h3F800001;
VAR4[223] <=32'h3F800001;
VAR4[224] <=32'h3F800000;
VAR4[225] <=32'h3F800000;
VAR4[226] <=32'h3F800000;
VAR4[227] <=32'h3F800000;
VAR4[228] <=32'h3F800000;
VAR4[229] <=32'h3F800000;
VAR4[230] <=32'h3F800000;
VAR4[231] <=32'h3F800000;
VAR4[232] <=32'h3F800000;
VAR4[233] <=32'h3F800000;
VAR4[234] <=32'h3F800000;
VAR4[235] <=32'h3F800000;
VAR4[236] <=32'h3F800000;
VAR4[237] <=32'h3F800000;
VAR4[238] <=32'h3F800000;
VAR4[239] <=32'h3F800000;
VAR4[240] <=32'h3F800000;
VAR4[241] <=32'h3F800000;
VAR4[242] <=32'h3F800000;
VAR4[243] <=32'h3F800000;
VAR4[244] <=32'h3F800000;
VAR4[245] <=32'h3F800000;
VAR4[246] <=32'h3F800000;
VAR4[247] <=32'h3F800000;
VAR4[248] <=32'h3F800000;
VAR4[249] <=32'h3F800000;
VAR4[250] <=32'h3F800000;
VAR4[251] <=32'h3F800000;
VAR4[252] <=32'h3F800000;
VAR4[253] <=32'h3F800000;
VAR4[254] <=32'h3F800000;
VAR4[255] <=32'h3F800000;
VAR30[0] <=32'h3F4CCCDE;
VAR30[1] <=32'h3F2AAABC;
VAR30[2] <=32'h3F124936;
VAR30[3] <=32'h3F000011;
VAR30[4] <=32'h3F800009;
VAR30[5] <=32'h3F555567;
VAR30[6] <=32'h3F36DB7F;
VAR30[7] <=32'h3F200011;
VAR30[8] <=32'h3F9999A2;
VAR30[9] <=32'h3F800009;
VAR30[10] <=32'h3F5B6DC8;
VAR30[11] <=32'h3F400011;
VAR30[12] <=32'h3FB3333C;
VAR30[13] <=32'h3F95555E;
VAR30[14] <=32'h3F800008;
VAR30[15] <=32'h3F600011;
VAR30[16] <=32'h3ECCCCEF;
VAR30[17] <=32'h3EAAAACD;
VAR30[18] <=32'h3E924946;
VAR30[19] <=32'h3E800022;
VAR30[20] <=32'h3F000011;
VAR30[21] <=32'h3ED55577;
VAR30[22] <=32'h3EB6DB90;
VAR30[23] <=32'h3EA00022;
VAR30[24] <=32'h3F1999AB;
VAR30[25] <=32'h3F000011;
VAR30[26] <=32'h3EDB6DD9;
VAR30[27] <=32'h3EC00022;
VAR30[28] <=32'h3F333345;
VAR30[29] <=32'h3F155566;
VAR30[30] <=32'h3F000011;
VAR30[31] <=32'h3EE00022;
VAR30[32] <=32'h3E4CCD11;
VAR30[33] <=32'h3E2AAAEE;
VAR30[34] <=32'h3E124968;
VAR30[35] <=32'h3E000043;
VAR30[36] <=32'h3E800022;
VAR30[37] <=32'h3E555599;
VAR30[38] <=32'h3E36DBB1;
VAR30[39] <=32'h3E200043;
VAR30[40] <=32'h3E9999BC;
VAR30[41] <=32'h3E800022;
VAR30[42] <=32'h3E5B6DFA;
VAR30[43] <=32'h3E400043;
VAR30[44] <=32'h3EB33355;
VAR30[45] <=32'h3E955577;
VAR30[46] <=32'h3E800022;
VAR30[47] <=32'h3E600043;
VAR30[48] <=32'h3DCCCD54;
VAR30[49] <=32'h3DAAAB31;
VAR30[50] <=32'h3D9249AB;
VAR30[51] <=32'h3D800086;
VAR30[52] <=32'h3E000043;
VAR30[53] <=32'h3DD555DC;
VAR30[54] <=32'h3DB6DBF4;
VAR30[55] <=32'h3DA00086;
VAR30[56] <=32'h3E1999DD;
VAR30[57] <=32'h3E000043;
VAR30[58] <=32'h3DDB6E3E;
VAR30[59] <=32'h3DC00086;
VAR30[60] <=32'h3E333377;
VAR30[61] <=32'h3E155599;
VAR30[62] <=32'h3E000043;
VAR30[63] <=32'h3DE00087;
VAR30[64] <=32'h3D4CCDDA;
VAR30[65] <=32'h3D2AABB7;
VAR30[66] <=32'h3D124A31;
VAR30[67] <=32'h3D00010C;
VAR30[68] <=32'h3D800087;
VAR30[69] <=32'h3D555662;
VAR30[70] <=32'h3D36DC7A;
VAR30[71] <=32'h3D20010D;
VAR30[72] <=32'h3D999A20;
VAR30[73] <=32'h3D800086;
VAR30[74] <=32'h3D5B6EC4;
VAR30[75] <=32'h3D40010D;
VAR30[76] <=32'h3DB333BA;
VAR30[77] <=32'h3D9555DC;
VAR30[78] <=32'h3D800086;
VAR30[79] <=32'h3D60010D;
VAR30[80] <=32'h3CCCCEE6;
VAR30[81] <=32'h3CAAACC4;
VAR30[82] <=32'h3C924B3E;
VAR30[83] <=32'h3C800219;
VAR30[84] <=32'h3D00010D;
VAR30[85] <=32'h3CD5576F;
VAR30[86] <=32'h3CB6DD87;
VAR30[87] <=32'h3CA00219;
VAR30[88] <=32'h3D199AA6;
VAR30[89] <=32'h3D00010D;
VAR30[90] <=32'h3CDB6FD0;
VAR30[91] <=32'h3CC00219;
VAR30[92] <=32'h3D333440;
VAR30[93] <=32'h3D155662;
VAR30[94] <=32'h3D00010D;
VAR30[95] <=32'h3CE00219;
VAR30[96] <=32'h3C4CD0FF;
VAR30[97] <=32'h3C2AAEDD;
VAR30[98] <=32'h3C124D56;
VAR30[99] <=32'h3C000432;
VAR30[100] <=32'h3C800219;
VAR30[101] <=32'h3C555988;
VAR30[102] <=32'h3C36DFA0;
VAR30[103] <=32'h3C200432;
VAR30[104] <=32'h3C999BB3;
VAR30[105] <=32'h3C800219;
VAR30[106] <=32'h3C5B71E9;
VAR30[107] <=32'h3C400432;
VAR30[108] <=32'h3CB3354D;
VAR30[109] <=32'h3C95576E;
VAR30[110] <=32'h3C800219;
VAR30[111] <=32'h3C600432;
VAR30[112] <=32'h3BCCD531;
VAR30[113] <=32'h3BAAB30F;
VAR30[114] <=32'h3B925188;
VAR30[115] <=32'h3B800863;
VAR30[116] <=32'h3C000432;
VAR30[117] <=32'h3BD55DB9;
VAR30[118] <=32'h3BB6E3D2;
VAR30[119] <=32'h3BA00864;
VAR30[120] <=32'h3C199DCC;
VAR30[121] <=32'h3C000432;
VAR30[122] <=32'h3BDB761B;
VAR30[123] <=32'h3BC00864;
VAR30[124] <=32'h3C333766;
VAR30[125] <=32'h3C155987;
VAR30[126] <=32'h3C000432;
VAR30[127] <=32'h3BE00864;
VAR30[128] <=32'h3B4CDD95;
VAR30[129] <=32'h3B2ABB72;
VAR30[130] <=32'h3B1259EC;
VAR30[131] <=32'h3B0010C7;
VAR30[132] <=32'h3B800864;
VAR30[133] <=32'h3B55661D;
VAR30[134] <=32'h3B36EC35;
VAR30[135] <=32'h3B2010C7;
VAR30[136] <=32'h3B99A1FE;
VAR30[137] <=32'h3B800864;
VAR30[138] <=32'h3B5B7E7E;
VAR30[139] <=32'h3B4010C7;
VAR30[140] <=32'h3BB33B97;
VAR30[141] <=32'h3B955DB9;
VAR30[142] <=32'h3B800864;
VAR30[143] <=32'h3B6010C7;
VAR30[144] <=32'h3ACCEE5C;
VAR30[145] <=32'h3AAACC39;
VAR30[146] <=32'h3A926AB3;
VAR30[147] <=32'h3A80218E;
VAR30[148] <=32'h3B0010C7;
VAR30[149] <=32'h3AD576E4;
VAR30[150] <=32'h3AB6FCFC;
VAR30[151] <=32'h3AA0218E;
VAR30[152] <=32'h3B19AA61;
VAR30[153] <=32'h3B0010C7;
VAR30[154] <=32'h3ADB8F45;
VAR30[155] <=32'h3AC0218E;
VAR30[156] <=32'h3B3343FB;
VAR30[157] <=32'h3B15661D;
VAR30[158] <=32'h3B0010C7;
VAR30[159] <=32'h3AE0218E;
VAR30[160] <=32'h3A4D0FE9;
VAR30[161] <=32'h3A2AEDC7;
VAR30[162] <=32'h3A128C41;
VAR30[163] <=32'h3A00431C;
VAR30[164] <=32'h3A80218E;
VAR30[165] <=32'h3A559872;
VAR30[166] <=32'h3A371E8A;
VAR30[167] <=32'h3A20431C;
VAR30[168] <=32'h3A99BB28;
VAR30[169] <=32'h3A80218E;
VAR30[170] <=32'h3A5BB0D3;
VAR30[171] <=32'h3A40431C;
VAR30[172] <=32'h3AB354C2;
VAR30[173] <=32'h3A9576E4;
VAR30[174] <=32'h3A80218E;
VAR30[175] <=32'h3A60431C;
VAR30[176] <=32'h39CD5305;
VAR30[177] <=32'h39AB30E3;
VAR30[178] <=32'h3992CF5C;
VAR30[179] <=32'h39808638;
VAR30[180] <=32'h3A00431C;
VAR30[181] <=32'h39D5DB8E;
VAR30[182] <=32'h39B761A6;
VAR30[183] <=32'h39A08638;
VAR30[184] <=32'h3A19DCB6;
VAR30[185] <=32'h3A00431C;
VAR30[186] <=32'h39DBF3EF;
VAR30[187] <=32'h39C08638;
VAR30[188] <=32'h3A337650;
VAR30[189] <=32'h3A159871;
VAR30[190] <=32'h3A00431C;
VAR30[191] <=32'h39E08638;
VAR30[192] <=32'h394DD93D;
VAR30[193] <=32'h392BB71B;
VAR30[194] <=32'h39135594;
VAR30[195] <=32'h39010C6F;
VAR30[196] <=32'h39808638;
VAR30[197] <=32'h395661C5;
VAR30[198] <=32'h3937E7DE;
VAR30[199] <=32'h39210C70;
VAR30[200] <=32'h399A1FD2;
VAR30[201] <=32'h39808638;
VAR30[202] <=32'h395C7A27;
VAR30[203] <=32'h39410C70;
VAR30[204] <=32'h39B3B96C;
VAR30[205] <=32'h3995DB8D;
VAR30[206] <=32'h39808638;
VAR30[207] <=32'h39610C70;
VAR30[208] <=32'h38CEE5AD;
VAR30[209] <=32'h38ACC38A;
VAR30[210] <=32'h38946204;
VAR30[211] <=32'h388218DF;
VAR30[212] <=32'h39010C70;
VAR30[213] <=32'h38D76E35;
VAR30[214] <=32'h38B8F44D;
VAR30[215] <=32'h38A218DF;
VAR30[216] <=32'h391AA60A;
VAR30[217] <=32'h39010C70;
VAR30[218] <=32'h38DD8696;
VAR30[219] <=32'h38C218DF;
VAR30[220] <=32'h39343FA3;
VAR30[221] <=32'h391661C5;
VAR30[222] <=32'h39010C70;
VAR30[223] <=32'h38E218DF;
VAR30[224] <=32'h3850FE8B;
VAR30[225] <=32'h382EDC69;
VAR30[226] <=32'h38167AE3;
VAR30[227] <=32'h380431BE;
VAR30[228] <=32'h388218DF;
VAR30[229] <=32'h38598714;
VAR30[230] <=32'h383B0D2C;
VAR30[231] <=32'h382431BE;
VAR30[232] <=32'h389BB279;
VAR30[233] <=32'h388218DF;
VAR30[234] <=32'h385F9F75;
VAR30[235] <=32'h384431BE;
VAR30[236] <=32'h38B54C13;
VAR30[237] <=32'h38976E35;
VAR30[238] <=32'h388218DF;
VAR30[239] <=32'h386431BE;
VAR30[240] <=32'h37D53049;
VAR30[241] <=32'h37B30E27;
VAR30[242] <=32'h379AACA1;
VAR30[243] <=32'h3788637C;
VAR30[244] <=32'h380431BE;
VAR30[245] <=32'h37DDB8D2;
VAR30[246] <=32'h37BF3EEA;
VAR30[247] <=32'h37A8637C;
VAR30[248] <=32'h381DCB58;
VAR30[249] <=32'h380431BE;
VAR30[250] <=32'h37E3D133;
VAR30[251] <=32'h37C8637C;
VAR30[252] <=32'h383764F2;
VAR30[253] <=32'h38198714;
VAR30[254] <=32'h380431BE;
VAR30[255] <=32'h37E8637C;
VAR36[0] <=32'h3F2CBBDD;
VAR36[1] <=32'h3F168762;
VAR36[2] <=32'h3F04E6CF;
VAR36[3] <=32'h3EED6353;
VAR36[4] <=32'h3F490FE3;
VAR36[5] <=32'h3F31DA68;
VAR36[6] <=32'h3F1EC8B7;
VAR36[7] <=32'h3F0F0069;
VAR36[8] <=32'h3F60455E;
VAR36[9] <=32'h3F490FE3;
VAR36[10] <=32'h3F356892;
VAR36[11] <=32'h3F24BC88;
VAR36[12] <=32'h3F735710;
VAR36[13] <=32'h3F5CB735;
VAR36[14] <=32'h3F490FE3;
VAR36[15] <=32'h3F380548;
VAR36[16] <=32'h3EC2D1D9;
VAR36[17] <=32'h3EA4BC9C;
VAR36[18] <=32'h3E8E7D6A;
VAR36[19] <=32'h3E7ADBEF;
VAR36[20] <=32'h3EED6354;
VAR36[21] <=32'h3ECA222D;
VAR36[22] <=32'h3EAFA0F3;
VAR36[23] <=32'h3E9B13D8;
VAR36[24] <=32'h3F0A58FB;
VAR36[25] <=32'h3EED6354;
VAR36[26] <=32'h3ECF4E17;
VAR36[27] <=32'h3EB7B0E8;
VAR36[28] <=32'h3F1C5895;
VAR36[29] <=32'h3F072FF0;
VAR36[30] <=32'h3EED6353;
VAR36[31] <=32'h3ED32793;
VAR36[32] <=32'h3E4A2251;
VAR36[33] <=32'h3E291CFE;
VAR36[34] <=32'h3E114DB8;
VAR36[35] <=32'h3DFEAE59;
VAR36[36] <=32'h3E7ADBF0;
VAR36[37] <=32'h3E52536C;
VAR36[38] <=32'h3E34F36C;
VAR36[39] <=32'h3E1EB7B9;
VAR36[40] <=32'h3E9539F2;
VAR36[41] <=32'h3E7ADBF0;
VAR36[42] <=32'h3E58291A;
VAR36[43] <=32'h3E3DCC1B;
VAR36[44] <=32'h3EAC60C3;
VAR36[45] <=32'h3E914D95;
VAR36[46] <=32'h3E7ADBF0;
VAR36[47] <=32'h3E5C86FB;
VAR36[48] <=32'h3DCC1F9A;
VAR36[49] <=32'h3DAA4679;
VAR36[50] <=32'h3D920A2C;
VAR36[51] <=32'h3D7FABEA;
VAR36[52] <=32'h3DFEAE5A;
VAR36[53] <=32'h3DD49199;
VAR36[54] <=32'h3DB66026;
VAR36[55] <=32'h3D9FAD7E;
VAR36[56] <=32'h3E1876DD;
VAR36[57] <=32'h3DFEAE5A;
VAR36[58] <=32'h3DDA98C1;
VAR36[59] <=32'h3DBF7146;
VAR36[60] <=32'h3E316792;
VAR36[61] <=32'h3E1449FC;
VAR36[62] <=32'h3DFEAE5A;
VAR36[63] <=32'h3DDF1D7B;
VAR36[64] <=32'h3D4CA239;
VAR36[65] <=32'h3D2A9275;
VAR36[66] <=32'h3D123A48;
VAR36[67] <=32'h3CFFECC7;
VAR36[68] <=32'h3D7FABEA;
VAR36[69] <=32'h3D552514;
VAR36[70] <=32'h3D36BD6A;
VAR36[71] <=32'h3D1FEC3C;
VAR36[72] <=32'h3D9950A5;
VAR36[73] <=32'h3D7FABEA;
VAR36[74] <=32'h3D5B391E;
VAR36[75] <=32'h3D3FDD18;
VAR36[76] <=32'h3DB2BF2E;
VAR36[77] <=32'h3D951251;
VAR36[78] <=32'h3D7FABEA;
VAR36[79] <=32'h3D5FC7FC;
VAR36[80] <=32'h3CCCC3FB;
VAR36[81] <=32'h3CAAA672;
VAR36[82] <=32'h3C924743;
VAR36[83] <=32'h3C7FFEDD;
VAR36[84] <=32'h3CFFECC7;
VAR36[85] <=32'h3CD54B17;
VAR36[86] <=32'h3CB6D5C1;
VAR36[87] <=32'h3C9FFCE4;
VAR36[88] <=32'h3D19883C;
VAR36[89] <=32'h3CFFECC7;
VAR36[90] <=32'h3CDB6262;
VAR36[91] <=32'h3CBFF91A;
VAR36[92] <=32'h3D331703;
VAR36[93] <=32'h3D154575;
VAR36[94] <=32'h3CFFECC7;
VAR36[95] <=32'h3CDFF3D0;
VAR36[96] <=32'h3C4CCE44;
VAR36[97] <=32'h3C2AAD48;
VAR36[98] <=32'h3C124C58;
VAR36[99] <=32'h3C000387;
VAR36[100] <=32'h3C7FFEDD;
VAR36[101] <=32'h3C555671;
VAR36[102] <=32'h3C36DDAE;
VAR36[103] <=32'h3C2002E4;
VAR36[104] <=32'h3C999717;
VAR36[105] <=32'h3C7FFEDD;
VAR36[106] <=32'h3C5B6E8D;
VAR36[107] <=32'h3C4001F2;
VAR36[108] <=32'h3CB32DFC;
VAR36[109] <=32'h3C955332;
VAR36[110] <=32'h3C7FFEDD;
VAR36[111] <=32'h3C60009F;
VAR36[112] <=32'h3BCCD482;
VAR36[113] <=32'h3BAAB2A9;
VAR36[114] <=32'h3B925148;
VAR36[115] <=32'h3B800839;
VAR36[116] <=32'h3C000387;
VAR36[117] <=32'h3BD55CF4;
VAR36[118] <=32'h3BB6E355;
VAR36[119] <=32'h3BA00810;
VAR36[120] <=32'h3C199CA5;
VAR36[121] <=32'h3C000387;
VAR36[122] <=32'h3BDB7544;
VAR36[123] <=32'h3BC007D4;
VAR36[124] <=32'h3C333591;
VAR36[125] <=32'h3C155878;
VAR36[126] <=32'h3C000387;
VAR36[127] <=32'h3BE0077F;
VAR36[128] <=32'h3B4CDD69;
VAR36[129] <=32'h3B2ABB59;
VAR36[130] <=32'h3B1259DC;
VAR36[131] <=32'h3B0010BC;
VAR36[132] <=32'h3B800839;
VAR36[133] <=32'h3B5565EB;
VAR36[134] <=32'h3B36EC16;
VAR36[135] <=32'h3B2010B2;
VAR36[136] <=32'h3B99A1B4;
VAR36[137] <=32'h3B800839;
VAR36[138] <=32'h3B5B7E49;
VAR36[139] <=32'h3B4010A3;
VAR36[140] <=32'h3BB33B22;
VAR36[141] <=32'h3B955D75;
VAR36[142] <=32'h3B800839;
VAR36[143] <=32'h3B60108E;
VAR36[144] <=32'h3ACCEE51;
VAR36[145] <=32'h3AAACC33;
VAR36[146] <=32'h3A926AAF;
VAR36[147] <=32'h3A80218B;
VAR36[148] <=32'h3B0010BD;
VAR36[149] <=32'h3AD576D8;
VAR36[150] <=32'h3AB6FCF4;
VAR36[151] <=32'h3AA02189;
VAR36[152] <=32'h3B19AA4F;
VAR36[153] <=32'h3B0010BC;
VAR36[154] <=32'h3ADB8F38;
VAR36[155] <=32'h3AC02185;
VAR36[156] <=32'h3B3343DD;
VAR36[157] <=32'h3B15660C;
VAR36[158] <=32'h3B0010BC;
VAR36[159] <=32'h3AE02180;
VAR36[160] <=32'h3A4D0FE7;
VAR36[161] <=32'h3A2AEDC5;
VAR36[162] <=32'h3A128C40;
VAR36[163] <=32'h3A00431B;
VAR36[164] <=32'h3A80218C;
VAR36[165] <=32'h3A55986F;
VAR36[166] <=32'h3A371E88;
VAR36[167] <=32'h3A20431B;
VAR36[168] <=32'h3A99BB23;
VAR36[169] <=32'h3A80218B;
VAR36[170] <=32'h3A5BB0D0;
VAR36[171] <=32'h3A40431A;
VAR36[172] <=32'h3AB354BA;
VAR36[173] <=32'h3A9576DF;
VAR36[174] <=32'h3A80218B;
VAR36[175] <=32'h3A604319;
VAR36[176] <=32'h39CD5305;
VAR36[177] <=32'h39AB30E2;
VAR36[178] <=32'h3992CF5C;
VAR36[179] <=32'h39808638;
VAR36[180] <=32'h3A00431B;
VAR36[181] <=32'h39D5DB8D;
VAR36[182] <=32'h39B761A5;
VAR36[183] <=32'h39A08638;
VAR36[184] <=32'h3A19DCB5;
VAR36[185] <=32'h3A00431B;
VAR36[186] <=32'h39DBF3EE;
VAR36[187] <=32'h39C08637;
VAR36[188] <=32'h3A33764E;
VAR36[189] <=32'h3A159870;
VAR36[190] <=32'h3A00431B;
VAR36[191] <=32'h39E08637;
VAR36[192] <=32'h394DD93D;
VAR36[193] <=32'h392BB71A;
VAR36[194] <=32'h39135594;
VAR36[195] <=32'h39010C6F;
VAR36[196] <=32'h39808638;
VAR36[197] <=32'h395661C5;
VAR36[198] <=32'h3937E7DD;
VAR36[199] <=32'h39210C70;
VAR36[200] <=32'h399A1FD2;
VAR36[201] <=32'h39808638;
VAR36[202] <=32'h395C7A27;
VAR36[203] <=32'h39410C70;
VAR36[204] <=32'h39B3B96B;
VAR36[205] <=32'h3995DB8D;
VAR36[206] <=32'h39808638;
VAR36[207] <=32'h39610C70;
VAR36[208] <=32'h38CEE5AC;
VAR36[209] <=32'h38ACC38A;
VAR36[210] <=32'h38946204;
VAR36[211] <=32'h388218DF;
VAR36[212] <=32'h39010C70;
VAR36[213] <=32'h38D76E35;
VAR36[214] <=32'h38B8F44D;
VAR36[215] <=32'h38A218DF;
VAR36[216] <=32'h391AA609;
VAR36[217] <=32'h39010C70;
VAR36[218] <=32'h38DD8696;
VAR36[219] <=32'h38C218DF;
VAR36[220] <=32'h39343FA3;
VAR36[221] <=32'h391661C5;
VAR36[222] <=32'h39010C70;
VAR36[223] <=32'h38E218DF;
VAR36[224] <=32'h3850FE8B;
VAR36[225] <=32'h382EDC69;
VAR36[226] <=32'h38167AE3;
VAR36[227] <=32'h380431BE;
VAR36[228] <=32'h388218DF;
VAR36[229] <=32'h38598714;
VAR36[230] <=32'h383B0D2C;
VAR36[231] <=32'h382431BE;
VAR36[232] <=32'h389BB279;
VAR36[233] <=32'h388218DF;
VAR36[234] <=32'h385F9F75;
VAR36[235] <=32'h384431BE;
VAR36[236] <=32'h38B54C13;
VAR36[237] <=32'h38976E35;
VAR36[238] <=32'h388218DF;
VAR36[239] <=32'h386431BE;
VAR36[240] <=32'h37D53049;
VAR36[241] <=32'h37B30E27;
VAR36[242] <=32'h379AACA1;
VAR36[243] <=32'h3788637C;
VAR36[244] <=32'h380431BE;
VAR36[245] <=32'h37DDB8D2;
VAR36[246] <=32'h37BF3EEA;
VAR36[247] <=32'h37A8637C;
VAR36[248] <=32'h381DCB58;
VAR36[249] <=32'h380431BE;
VAR36[250] <=32'h37E3D133;
VAR36[251] <=32'h37C8637C;
VAR36[252] <=32'h383764F2;
VAR36[253] <=32'h38198714;
VAR36[254] <=32'h380431BE;
VAR36[255] <=32'h37E8637C;
VAR3[0] <=32'h3F8C9F6C;
VAR3[1] <=32'h3F4E022F;
VAR3[2] <=32'h3F264F01;
VAR3[3] <=32'h3F0C9F6A;
VAR3[4] <=32'h40E82375;
VAR3[5] <=32'h3F99773B;
VAR3[6] <=32'h3F655883;
VAR3[7] <=32'h3F3BB10B;
VAR3[8] <=32'h40E82375;
VAR3[9] <=32'h40E82375;
VAR3[10] <=32'h3FA42842;
VAR3[11] <=32'h3F7913BD;
VAR3[12] <=32'h40E82375;
VAR3[13] <=32'h40E82375;
VAR3[14] <=32'h40E82375;
VAR3[15] <=32'h3FAD50D7;
VAR3[16] <=32'h3ED8E8AC;
VAR3[17] <=32'h3EB1723E;
VAR3[18] <=32'h3E967955;
VAR3[19] <=32'h3E82C59C;
VAR3[20] <=32'h3F0C9F6B;
VAR3[21] <=32'h3EE32677;
VAR3[22] <=32'h3EBF4998;
VAR3[23] <=32'h3EA58981;
VAR3[24] <=32'h3F317233;
VAR3[25] <=32'h3F0C9F6B;
VAR3[26] <=32'h3EEA9231;
VAR3[27] <=32'h3EC9D87F;
VAR3[28] <=32'h3F5E078B;
VAR3[29] <=32'h3F2AE16B;
VAR3[30] <=32'h3F0C9F6A;
VAR3[31] <=32'h3EF0329A;
VAR3[32] <=32'h3E4F9966;
VAR3[33] <=32'h3E2C465C;
VAR3[34] <=32'h3E134B55;
VAR3[35] <=32'h3E00AC8D;
VAR3[36] <=32'h3E82C59C;
VAR3[37] <=32'h3E5880F8;
VAR3[38] <=32'h3E38D703;
VAR3[39] <=32'h3E215292;
VAR3[40] <=32'h3E9E7980;
VAR3[41] <=32'h3E82C59C;
VAR3[42] <=32'h3E5EE249;
VAR3[43] <=32'h3E424CBD;
VAR3[44] <=32'h3EBB1B99;
VAR3[45] <=32'h3E99CC76;
VAR3[46] <=32'h3E82C59C;
VAR3[47] <=32'h3E63AE23;
VAR3[48] <=32'h3DCD7D27;
VAR3[49] <=32'h3DAB10C1;
VAR3[50] <=32'h3D92898E;
VAR3[51] <=32'h3D802B4B;
VAR3[52] <=32'h3E00AC8D;
VAR3[53] <=32'h3DD61CB1;
VAR3[54] <=32'h3DB758F3;
VAR3[55] <=32'h3DA0542B;
VAR3[56] <=32'h3E1AC4D4;
VAR3[57] <=32'h3E00AC8D;
VAR3[58] <=32'h3DDC46B1;
VAR3[59] <=32'h3DC0914B;
VAR3[60] <=32'h3E351095;
VAR3[61] <=32'h3E166820;
VAR3[62] <=32'h3E00AC8D;
VAR3[63] <=32'h3DE0E6DB;
VAR3[64] <=32'h3D4CF99C;
VAR3[65] <=32'h3D2AC507;
VAR3[66] <=32'h3D125A21;
VAR3[67] <=32'h3D000BB9;
VAR3[68] <=32'h3D802B4B;
VAR3[69] <=32'h3D5587DA;
VAR3[70] <=32'h3D36FB9E;
VAR3[71] <=32'h3D2015E7;
VAR3[72] <=32'h3D99E41B;
VAR3[73] <=32'h3D802B4B;
VAR3[74] <=32'h3D5BA499;
VAR3[75] <=32'h3D402519;
VAR3[76] <=32'h3DB3A959;
VAR3[77] <=32'h3D9599D5;
VAR3[78] <=32'h3D802B4B;
VAR3[79] <=32'h3D603A53;
VAR3[80] <=32'h3CCCD9D4;
VAR3[81] <=32'h3CAAB317;
VAR3[82] <=32'h3C924F39;
VAR3[83] <=32'h3C8004C4;
VAR3[84] <=32'h3D000BB9;
VAR3[85] <=32'h3CD563C9;
VAR3[86] <=32'h3CB6E54E;
VAR3[87] <=32'h3CA0074F;
VAR3[88] <=32'h3D19AD19;
VAR3[89] <=32'h3D000BB9;
VAR3[90] <=32'h3CDB7D41;
VAR3[91] <=32'h3CC00B1A;
VAR3[92] <=32'h3D33518E;
VAR3[93] <=32'h3D156756;
VAR3[94] <=32'h3D000BB9;
VAR3[95] <=32'h3CE01066;
VAR3[96] <=32'h3C4CD3BB;
VAR3[97] <=32'h3C2AB071;
VAR3[98] <=32'h3C124E55;
VAR3[99] <=32'h3C0004DC;
VAR3[100] <=32'h3C8004C4;
VAR3[101] <=32'h3C555C9E;
VAR3[102] <=32'h3C36E192;
VAR3[103] <=32'h3C20057F;
VAR3[104] <=32'h3C99A04F;
VAR3[105] <=32'h3C8004C4;
VAR3[106] <=32'h3C5B7545;
VAR3[107] <=32'h3C400672;
VAR3[108] <=32'h3CB33C9F;
VAR3[109] <=32'h3C955BAB;
VAR3[110] <=32'h3C8004C4;
VAR3[111] <=32'h3C6007C5;
VAR3[112] <=32'h3BCCD5E0;
VAR3[113] <=32'h3BAAB374;
VAR3[114] <=32'h3B9251C8;
VAR3[115] <=32'h3B80088E;
VAR3[116] <=32'h3C0004DD;
VAR3[117] <=32'h3BD55E7F;
VAR3[118] <=32'h3BB6E44E;
VAR3[119] <=32'h3BA008B7;
VAR3[120] <=32'h3C199EF3;
VAR3[121] <=32'h3C0004DD;
VAR3[122] <=32'h3BDB76F2;
VAR3[123] <=32'h3BC008F4;
VAR3[124] <=32'h3C33393A;
VAR3[125] <=32'h3C155A96;
VAR3[126] <=32'h3C0004DD;
VAR3[127] <=32'h3BE00949;
VAR3[128] <=32'h3B4CDDC0;
VAR3[129] <=32'h3B2ABB8B;
VAR3[130] <=32'h3B1259FC;
VAR3[131] <=32'h3B0010D2;
VAR3[132] <=32'h3B80088E;
VAR3[133] <=32'h3B55664E;
VAR3[134] <=32'h3B36EC54;
VAR3[135] <=32'h3B2010DC;
VAR3[136] <=32'h3B99A247;
VAR3[137] <=32'h3B80088E;
VAR3[138] <=32'h3B5B7EB4;
VAR3[139] <=32'h3B4010EB;
VAR3[140] <=32'h3BB33C0C;
VAR3[141] <=32'h3B955DFD;
VAR3[142] <=32'h3B80088E;
VAR3[143] <=32'h3B601101;
VAR3[144] <=32'h3ACCEE66;
VAR3[145] <=32'h3AAACC3F;
VAR3[146] <=32'h3A926AB7;
VAR3[147] <=32'h3A802191;
VAR3[148] <=32'h3B0010D2;
VAR3[149] <=32'h3AD576F0;
VAR3[150] <=32'h3AB6FD04;
VAR3[151] <=32'h3AA02193;
VAR3[152] <=32'h3B19AA73;
VAR3[153] <=32'h3B0010D2;
VAR3[154] <=32'h3ADB8F53;
VAR3[155] <=32'h3AC02197;
VAR3[156] <=32'h3B334418;
VAR3[157] <=32'h3B15662E;
VAR3[158] <=32'h3B0010D2;
VAR3[159] <=32'h3AE0219D;
VAR3[160] <=32'h3A4D0FEC;
VAR3[161] <=32'h3A2AEDC9;
VAR3[162] <=32'h3A128C42;
VAR3[163] <=32'h3A00431D;
VAR3[164] <=32'h3A802191;
VAR3[165] <=32'h3A559875;
VAR3[166] <=32'h3A371E8C;
VAR3[167] <=32'h3A20431D;
VAR3[168] <=32'h3A99BB2D;
VAR3[169] <=32'h3A802191;
VAR3[170] <=32'h3A5BB0D7;
VAR3[171] <=32'h3A40431E;
VAR3[172] <=32'h3AB354C9;
VAR3[173] <=32'h3A9576E8;
VAR3[174] <=32'h3A802191;
VAR3[175] <=32'h3A604320;
VAR3[176] <=32'h39CD5306;
VAR3[177] <=32'h39AB30E3;
VAR3[178] <=32'h3992CF5D;
VAR3[179] <=32'h39808638;
VAR3[180] <=32'h3A00431D;
VAR3[181] <=32'h39D5DB8E;
VAR3[182] <=32'h39B761A6;
VAR3[183] <=32'h39A08638;
VAR3[184] <=32'h3A19DCB7;
VAR3[185] <=32'h3A00431D;
VAR3[186] <=32'h39DBF3F0;
VAR3[187] <=32'h39C08639;
VAR3[188] <=32'h3A337652;
VAR3[189] <=32'h3A159873;
VAR3[190] <=32'h3A00431D;
VAR3[191] <=32'h39E08639;
VAR3[192] <=32'h394DD93D;
VAR3[193] <=32'h392BB71B;
VAR3[194] <=32'h39135594;
VAR3[195] <=32'h39010C70;
VAR3[196] <=32'h39808638;
VAR3[197] <=32'h395661C6;
VAR3[198] <=32'h3937E7DE;
VAR3[199] <=32'h39210C70;
VAR3[200] <=32'h399A1FD2;
VAR3[201] <=32'h39808638;
VAR3[202] <=32'h395C7A27;
VAR3[203] <=32'h39410C70;
VAR3[204] <=32'h39B3B96C;
VAR3[205] <=32'h3995DB8E;
VAR3[206] <=32'h39808638;
VAR3[207] <=32'h39610C70;
VAR3[208] <=32'h38CEE5AD;
VAR3[209] <=32'h38ACC38A;
VAR3[210] <=32'h38946204;
VAR3[211] <=32'h388218DF;
VAR3[212] <=32'h39010C70;
VAR3[213] <=32'h38D76E35;
VAR3[214] <=32'h38B8F44D;
VAR3[215] <=32'h38A218DF;
VAR3[216] <=32'h391AA60A;
VAR3[217] <=32'h39010C70;
VAR3[218] <=32'h38DD8696;
VAR3[219] <=32'h38C218DF;
VAR3[220] <=32'h39343FA3;
VAR3[221] <=32'h391661C5;
VAR3[222] <=32'h39010C70;
VAR3[223] <=32'h38E218DF;
VAR3[224] <=32'h3850FE8B;
VAR3[225] <=32'h382EDC69;
VAR3[226] <=32'h38167AE3;
VAR3[227] <=32'h380431BE;
VAR3[228] <=32'h388218DF;
VAR3[229] <=32'h38598714;
VAR3[230] <=32'h383B0D2C;
VAR3[231] <=32'h382431BE;
VAR3[232] <=32'h389BB279;
VAR3[233] <=32'h388218DF;
VAR3[234] <=32'h385F9F75;
VAR3[235] <=32'h384431BE;
VAR3[236] <=32'h38B54C13;
VAR3[237] <=32'h38976E35;
VAR3[238] <=32'h388218DF;
VAR3[239] <=32'h386431BE;
VAR3[240] <=32'h37D53049;
VAR3[241] <=32'h37B30E27;
VAR3[242] <=32'h379AACA1;
VAR3[243] <=32'h3788637C;
VAR3[244] <=32'h380431BE;
VAR3[245] <=32'h37DDB8D2;
VAR3[246] <=32'h37BF3EEA;
VAR3[247] <=32'h37A8637C;
VAR3[248] <=32'h381DCB58;
VAR3[249] <=32'h380431BE;
VAR3[250] <=32'h37E3D133;
VAR3[251] <=32'h37C8637C;
VAR3[252] <=32'h383764F2;
VAR3[253] <=32'h38198714;
VAR3[254] <=32'h380431BE;
VAR3[255] <=32'h37E8637C;
VAR45[0] <=32'h3FD5557A;
VAR45[1] <=32'h3FABBAF5;
VAR45[2] <=32'h3F9BF949;
VAR45[3] <=32'h3F93CD45;
VAR45[4] <=32'h4430C6D8;
VAR45[5] <=32'h3FE78FBB;
VAR45[6] <=32'h3FB6E544;
VAR45[7] <=32'h3FA3F8B2;
VAR45[8] <=32'h4430C6D8;
VAR45[9] <=32'h4430C6D8;
VAR45[10] <=32'h3FF881B0;
VAR45[11] <=32'h3FC184AA;
VAR45[12] <=32'h4430C6D8;
VAR45[13] <=32'h4430C6D8;
VAR45[14] <=32'h4430C6D8;
VAR45[15] <=32'h400432C9;
VAR45[16] <=32'h3F8BA8DA;
VAR45[17] <=32'h3F87C3BE;
VAR45[18] <=32'h3F859161;
VAR45[19] <=32'h3F8432AB;
VAR45[20] <=32'h3F93CD45;
VAR45[21] <=32'h3F8CCE16;
VAR45[22] <=32'h3F8909AC;
VAR45[23] <=32'h3F86BFA5;
VAR45[24] <=32'h3FA0000E;
VAR45[25] <=32'h3F93CD45;
VAR45[26] <=32'h3F8DAB90;
VAR45[27] <=32'h3F8A1385;
VAR45[28] <=32'h3FB33C76;
VAR45[29] <=32'h3F9D972A;
VAR45[30] <=32'h3F93CD45;
VAR45[31] <=32'h3F8E5892;
VAR45[32] <=32'h3F82A3B9;
VAR45[33] <=32'h3F81D0D6;
VAR45[34] <=32'h3F815398;
VAR45[35] <=32'h3F81030F;
VAR45[36] <=32'h3F8432AB;
VAR45[37] <=32'h3F82DF27;
VAR45[38] <=32'h3F82174E;
VAR45[39] <=32'h3F81977F;
VAR45[40] <=32'h3F862E39;
VAR45[41] <=32'h3F8432AB;
VAR45[42] <=32'h3F830B4A;
VAR45[43] <=32'h3F824FAB;
VAR45[44] <=32'h3F88A48F;
VAR45[45] <=32'h3F85D18B;
VAR45[46] <=32'h3F8432AB;
VAR45[47] <=32'h3F832D54;
VAR45[48] <=32'h3F80A519;
VAR45[49] <=32'h3F807264;
VAR45[50] <=32'h3F8053EE;
VAR45[51] <=32'h3F804034;
VAR45[52] <=32'h3F81030F;
VAR45[53] <=32'h3F80B341;
VAR45[54] <=32'h3F80836A;
VAR45[55] <=32'h3F80647A;
VAR45[56] <=32'h3F817700;
VAR45[57] <=32'h3F81030F;
VAR45[58] <=32'h3F80BDBC;
VAR45[59] <=32'h3F8090F9;
VAR45[60] <=32'h3F82019C;
VAR45[61] <=32'h3F81621F;
VAR45[62] <=32'h3F81030F;
VAR45[63] <=32'h3F80C5CB;
VAR45[64] <=32'h3F80290E;
VAR45[65] <=32'h3F801C7F;
VAR45[66] <=32'h3F8014EF;
VAR45[67] <=32'h3F801007;
VAR45[68] <=32'h3F804034;
VAR45[69] <=32'h3F802C8D;
VAR45[70] <=32'h3F8020B8;
VAR45[71] <=32'h3F80190B;
VAR45[72] <=32'h3F805C91;
VAR45[73] <=32'h3F804034;
VAR45[74] <=32'h3F802F23;
VAR45[75] <=32'h3F802413;
VAR45[76] <=32'h3F807E2F;
VAR45[77] <=32'h3F80577A;
VAR45[78] <=32'h3F804034;
VAR45[79] <=32'h3F803120;
VAR45[80] <=32'h3F800A43;
VAR45[81] <=32'h3F800721;
VAR45[82] <=32'h3F80053E;
VAR45[83] <=32'h3F800404;
VAR45[84] <=32'h3F801007;
VAR45[85] <=32'h3F800B22;
VAR45[86] <=32'h3F80082E;
VAR45[87] <=32'h3F800644;
VAR45[88] <=32'h3F801714;
VAR45[89] <=32'h3F801007;
VAR45[90] <=32'h3F800BC7;
VAR45[91] <=32'h3F800905;
VAR45[92] <=32'h3F801F6C;
VAR45[93] <=32'h3F8015D1;
VAR45[94] <=32'h3F801007;
VAR45[95] <=32'h3F800C46;
VAR45[96] <=32'h3F800293;
VAR45[97] <=32'h3F8001CB;
VAR45[98] <=32'h3F800152;
VAR45[99] <=32'h3F800104;
VAR45[100] <=32'h3F800404;
VAR45[101] <=32'h3F8002CB;
VAR45[102] <=32'h3F80020E;
VAR45[103] <=32'h3F800194;
VAR45[104] <=32'h3F8005C7;
VAR45[105] <=32'h3F800404;
VAR45[106] <=32'h3F8002F4;
VAR45[107] <=32'h3F800244;
VAR45[108] <=32'h3F8007DC;
VAR45[109] <=32'h3F800576;
VAR45[110] <=32'h3F800404;
VAR45[111] <=32'h3F800314;
VAR45[112] <=32'h3F8000A8;
VAR45[113] <=32'h3F800076;
VAR45[114] <=32'h3F800057;
VAR45[115] <=32'h3F800044;
VAR45[116] <=32'h3F800104;
VAR45[117] <=32'h3F8000B6;
VAR45[118] <=32'h3F800086;
VAR45[119] <=32'h3F800068;
VAR45[120] <=32'h3F800174;
VAR45[121] <=32'h3F800104;
VAR45[122] <=32'h3F8000C0;
VAR45[123] <=32'h3F800094;
VAR45[124] <=32'h3F8001FA;
VAR45[125] <=32'h3F800160;
VAR45[126] <=32'h3F800104;
VAR45[127] <=32'h3F8000C8;
VAR45[128] <=32'h3F80002D;
VAR45[129] <=32'h3F800020;
VAR45[130] <=32'h3F800019;
VAR45[131] <=32'h3F800014;
VAR45[132] <=32'h3F800044;
VAR45[133] <=32'h3F800030;
VAR45[134] <=32'h3F800024;
VAR45[135] <=32'h3F80001D;
VAR45[136] <=32'h3F800060;
VAR45[137] <=32'h3F800044;
VAR45[138] <=32'h3F800033;
VAR45[139] <=32'h3F800028;
VAR45[140] <=32'h3F800081;
VAR45[141] <=32'h3F80005B;
VAR45[142] <=32'h3F800044;
VAR45[143] <=32'h3F800035;
VAR45[144] <=32'h3F80000E;
VAR45[145] <=32'h3F80000B;
VAR45[146] <=32'h3F800009;
VAR45[147] <=32'h3F800008;
VAR45[148] <=32'h3F800014;
VAR45[149] <=32'h3F80000F;
VAR45[150] <=32'h3F80000C;
VAR45[151] <=32'h3F80000A;
VAR45[152] <=32'h3F80001B;
VAR45[153] <=32'h3F800014;
VAR45[154] <=32'h3F80000F;
VAR45[155] <=32'h3F80000D;
VAR45[156] <=32'h3F800023;
VAR45[157] <=32'h3F800019;
VAR45[158] <=32'h3F800014;
VAR45[159] <=32'h3F800010;
VAR45[160] <=32'h3F800006;
VAR45[161] <=32'h3F800005;
VAR45[162] <=32'h3F800005;
VAR45[163] <=32'h3F800005;
VAR45[164] <=32'h3F800008;
VAR45[165] <=32'h3F800006;
VAR45[166] <=32'h3F800006;
VAR45[167] <=32'h3F800005;
VAR45[168] <=32'h3F800009;
VAR45[169] <=32'h3F800008;
VAR45[170] <=32'h3F800007;
VAR45[171] <=32'h3F800006;
VAR45[172] <=32'h3F80000C;
VAR45[173] <=32'h3F800009;
VAR45[174] <=32'h3F800008;
VAR45[175] <=32'h3F800007;
VAR45[176] <=32'h3F800004;
VAR45[177] <=32'h3F800004;
VAR45[178] <=32'h3F800004;
VAR45[179] <=32'h3F800004;
VAR45[180] <=32'h3F800005;
VAR45[181] <=32'h3F800004;
VAR45[182] <=32'h3F800004;
VAR45[183] <=32'h3F800004;
VAR45[184] <=32'h3F800005;
VAR45[185] <=32'h3F800005;
VAR45[186] <=32'h3F800004;
VAR45[187] <=32'h3F800004;
VAR45[188] <=32'h3F800006;
VAR45[189] <=32'h3F800005;
VAR45[190] <=32'h3F800005;
VAR45[191] <=32'h3F800004;
VAR45[192] <=32'h3F800004;
VAR45[193] <=32'h3F800004;
VAR45[194] <=32'h3F800004;
VAR45[195] <=32'h3F800004;
VAR45[196] <=32'h3F800004;
VAR45[197] <=32'h3F800004;
VAR45[198] <=32'h3F800004;
VAR45[199] <=32'h3F800004;
VAR45[200] <=32'h3F800004;
VAR45[201] <=32'h3F800004;
VAR45[202] <=32'h3F800004;
VAR45[203] <=32'h3F800004;
VAR45[204] <=32'h3F800004;
VAR45[205] <=32'h3F800004;
VAR45[206] <=32'h3F800004;
VAR45[207] <=32'h3F800004;
VAR45[208] <=32'h3F800004;
VAR45[209] <=32'h3F800004;
VAR45[210] <=32'h3F800004;
VAR45[211] <=32'h3F800004;
VAR45[212] <=32'h3F800004;
VAR45[213] <=32'h3F800004;
VAR45[214] <=32'h3F800004;
VAR45[215] <=32'h3F800004;
VAR45[216] <=32'h3F800004;
VAR45[217] <=32'h3F800004;
VAR45[218] <=32'h3F800004;
VAR45[219] <=32'h3F800004;
VAR45[220] <=32'h3F800004;
VAR45[221] <=32'h3F800004;
VAR45[222] <=32'h3F800004;
VAR45[223] <=32'h3F800004;
VAR45[224] <=32'h3F800004;
VAR45[225] <=32'h3F800004;
VAR45[226] <=32'h3F800004;
VAR45[227] <=32'h3F800004;
VAR45[228] <=32'h3F800004;
VAR45[229] <=32'h3F800004;
VAR45[230] <=32'h3F800004;
VAR45[231] <=32'h3F800004;
VAR45[232] <=32'h3F800004;
VAR45[233] <=32'h3F800004;
VAR45[234] <=32'h3F800004;
VAR45[235] <=32'h3F800004;
VAR45[236] <=32'h3F800004;
VAR45[237] <=32'h3F800004;
VAR45[238] <=32'h3F800004;
VAR45[239] <=32'h3F800004;
VAR45[240] <=32'h3F800004;
VAR45[241] <=32'h3F800004;
VAR45[242] <=32'h3F800004;
VAR45[243] <=32'h3F800004;
VAR45[244] <=32'h3F800004;
VAR45[245] <=32'h3F800004;
VAR45[246] <=32'h3F800004;
VAR45[247] <=32'h3F800004;
VAR45[248] <=32'h3F800004;
VAR45[249] <=32'h3F800004;
VAR45[250] <=32'h3F800004;
VAR45[251] <=32'h3F800004;
VAR45[252] <=32'h3F800004;
VAR45[253] <=32'h3F800004;
VAR45[254] <=32'h3F800004;
VAR45[255] <=32'h3F800004;
VAR42[0] <=32'h3F47E706;
VAR42[1] <=32'h3F550141;
VAR42[2] <=32'h3F5E4530;
VAR42[3] <=32'h3F64F930;
VAR42[4] <=32'h3F3504F5;
VAR42[5] <=32'h3F44AA27;
VAR42[6] <=32'h3F5050D7;
VAR42[7] <=32'h3F59166C;
VAR42[8] <=32'h3F23E322;
VAR42[9] <=32'h3F3504F5;
VAR42[10] <=32'h3F425EA5;
VAR42[11] <=32'h3F4CCCCE;
VAR42[12] <=32'h3F14CC09;
VAR42[13] <=32'h3F269A45;
VAR42[14] <=32'h3F3504F5;
VAR42[15] <=32'h3F40A8DF;
VAR42[16] <=32'h3F6DB0A8;
VAR42[17] <=32'h3F72DCEC;
VAR42[18] <=32'h3F762673;
VAR42[19] <=32'h3F785B46;
VAR42[20] <=32'h3F64F930;
VAR42[21] <=32'h3F6C4EC7;
VAR42[22] <=32'h3F711602;
VAR42[23] <=32'h3F7458D0;
VAR42[24] <=32'h3F5B84A9;
VAR42[25] <=32'h3F64F930;
VAR42[26] <=32'h3F6B4D19;
VAR42[27] <=32'h3F6FB347;
VAR42[28] <=32'h3F51B930;
VAR42[29] <=32'h3F5D209E;
VAR42[30] <=32'h3F64F930;
VAR42[31] <=32'h3F6A894C;
VAR42[32] <=32'h3F7B075A;
VAR42[33] <=32'h3F7C8455;
VAR42[34] <=32'h3F7D6D5A;
VAR42[35] <=32'h3F7E05F2;
VAR42[36] <=32'h3F785B46;
VAR42[37] <=32'h3F7A9E7B;
VAR42[38] <=32'h3F7C0377;
VAR42[39] <=32'h3F7CEE61;
VAR42[40] <=32'h3F75341E;
VAR42[41] <=32'h3F785B46;
VAR42[42] <=32'h3F7A5147;
VAR42[43] <=32'h3F7B9D88;
VAR42[44] <=32'h3F71A0B6;
VAR42[45] <=32'h3F75C293;
VAR42[46] <=32'h3F785B46;
VAR42[47] <=32'h3F7A1623;
VAR42[48] <=32'h3F7EBAC8;
VAR42[49] <=32'h3F7F1DA6;
VAR42[50] <=32'h3F7F597B;
VAR42[51] <=32'h3F7F8067;
VAR42[52] <=32'h3F7E05F2;
VAR42[53] <=32'h3F7E9F56;
VAR42[54] <=32'h3F7EFC5A;
VAR42[55] <=32'h3F7F38F0;
VAR42[56] <=32'h3F7D2AF4;
VAR42[57] <=32'h3F7E05F2;
VAR42[58] <=32'h3F7E8B12;
VAR42[59] <=32'h3F7EE1E9;
VAR42[60] <=32'h3F7C2AFA;
VAR42[61] <=32'h3F7D520E;
VAR42[62] <=32'h3F7E05F2;
VAR42[63] <=32'h3F7E7B82;
VAR42[64] <=32'h3F7FAE43;
VAR42[65] <=32'h3F7FC737;
VAR42[66] <=32'h3F7FD646;
VAR42[67] <=32'h3F7FE00D;
VAR42[68] <=32'h3F7F8067;
VAR42[69] <=32'h3F7FA752;
VAR42[70] <=32'h3F7FBED2;
VAR42[71] <=32'h3F7FCE16;
VAR42[72] <=32'h3F7F487B;
VAR42[73] <=32'h3F7F8067;
VAR42[74] <=32'h3F7FA230;
VAR42[75] <=32'h3F7FB825;
VAR42[76] <=32'h3F7F0694;
VAR42[77] <=32'h3F7F527F;
VAR42[78] <=32'h3F7F8067;
VAR42[79] <=32'h3F7F9E3F;
VAR42[80] <=32'h3F7FEB8F;
VAR42[81] <=32'h3F7FF1D0;
VAR42[82] <=32'h3F7FF595;
VAR42[83] <=32'h3F7FF808;
VAR42[84] <=32'h3F7FE00D;
VAR42[85] <=32'h3F7FE9D1;
VAR42[86] <=32'h3F7FEFB5;
VAR42[87] <=32'h3F7FF388;
VAR42[88] <=32'h3F7FD1FF;
VAR42[89] <=32'h3F7FE00D;
VAR42[90] <=32'h3F7FE888;
VAR42[91] <=32'h3F7FEE09;
VAR42[92] <=32'h3F7FC166;
VAR42[93] <=32'h3F7FD484;
VAR42[94] <=32'h3F7FE00D;
VAR42[95] <=32'h3F7FE78B;
VAR42[96] <=32'h3F7FFAE9;
VAR42[97] <=32'h3F7FFC7A;
VAR42[98] <=32'h3F7FFD6B;
VAR42[99] <=32'h3F7FFE08;
VAR42[100] <=32'h3F7FF808;
VAR42[101] <=32'h3F7FFA7A;
VAR42[102] <=32'h3F7FFBF3;
VAR42[103] <=32'h3F7FFCE8;
VAR42[104] <=32'h3F7FF483;
VAR42[105] <=32'h3F7FF808;
VAR42[106] <=32'h3F7FFA27;
VAR42[107] <=32'h3F7FFB88;
VAR42[108] <=32'h3F7FF05B;
VAR42[109] <=32'h3F7FF525;
VAR42[110] <=32'h3F7FF808;
VAR42[111] <=32'h3F7FF9E8;
VAR42[112] <=32'h3F7FFEC0;
VAR42[113] <=32'h3F7FFF24;
VAR42[114] <=32'h3F7FFF61;
VAR42[115] <=32'h3F7FFF88;
VAR42[116] <=32'h3F7FFE08;
VAR42[117] <=32'h3F7FFEA4;
VAR42[118] <=32'h3F7FFF03;
VAR42[119] <=32'h3F7FFF40;
VAR42[120] <=32'h3F7FFD26;
VAR42[121] <=32'h3F7FFE08;
VAR42[122] <=32'h3F7FFE90;
VAR42[123] <=32'h3F7FFEE8;
VAR42[124] <=32'h3F7FFC1C;
VAR42[125] <=32'h3F7FFD4F;
VAR42[126] <=32'h3F7FFE08;
VAR42[127] <=32'h3F7FFE80;
VAR42[128] <=32'h3F7FFFB6;
VAR42[129] <=32'h3F7FFFCF;
VAR42[130] <=32'h3F7FFFDE;
VAR42[131] <=32'h3F7FFFE8;
VAR42[132] <=32'h3F7FFF88;
VAR42[133] <=32'h3F7FFFAF;
VAR42[134] <=32'h3F7FFFC7;
VAR42[135] <=32'h3F7FFFD6;
VAR42[136] <=32'h3F7FFF4F;
VAR42[137] <=32'h3F7FFF88;
VAR42[138] <=32'h3F7FFFAA;
VAR42[139] <=32'h3F7FFFC0;
VAR42[140] <=32'h3F7FFF0D;
VAR42[141] <=32'h3F7FFF5A;
VAR42[142] <=32'h3F7FFF88;
VAR42[143] <=32'h3F7FFFA6;
VAR42[144] <=32'h3F7FFFF3;
VAR42[145] <=32'h3F7FFFFA;
VAR42[146] <=32'h3F7FFFFD;
VAR42[147] <=32'h3F800000;
VAR42[148] <=32'h3F7FFFE8;
VAR42[149] <=32'h3F7FFFF2;
VAR42[150] <=32'h3F7FFFF8;
VAR42[151] <=32'h3F7FFFFB;
VAR42[152] <=32'h3F7FFFDA;
VAR42[153] <=32'h3F7FFFE8;
VAR42[154] <=32'h3F7FFFF0;
VAR42[155] <=32'h3F7FFFF6;
VAR42[156] <=32'h3F7FFFC9;
VAR42[157] <=32'h3F7FFFDC;
VAR42[158] <=32'h3F7FFFE8;
VAR42[159] <=32'h3F7FFFEF;
VAR42[160] <=32'h3F800001;
VAR42[161] <=32'h3F800002;
VAR42[162] <=32'h3F800002;
VAR42[163] <=32'h3F800003;
VAR42[164] <=32'h3F800000;
VAR42[165] <=32'h3F800001;
VAR42[166] <=32'h3F800002;
VAR42[167] <=32'h3F800002;
VAR42[168] <=32'h3F7FFFFC;
VAR42[169] <=32'h3F800000;
VAR42[170] <=32'h3F800001;
VAR42[171] <=32'h3F800001;
VAR42[172] <=32'h3F7FFFF8;
VAR42[173] <=32'h3F7FFFFD;
VAR42[174] <=32'h3F800000;
VAR42[175] <=32'h3F800001;
VAR42[176] <=32'h3F800003;
VAR42[177] <=32'h3F800003;
VAR42[178] <=32'h3F800003;
VAR42[179] <=32'h3F800003;
VAR42[180] <=32'h3F800003;
VAR42[181] <=32'h3F800003;
VAR42[182] <=32'h3F800003;
VAR42[183] <=32'h3F800003;
VAR42[184] <=32'h3F800002;
VAR42[185] <=32'h3F800003;
VAR42[186] <=32'h3F800003;
VAR42[187] <=32'h3F800003;
VAR42[188] <=32'h3F800002;
VAR42[189] <=32'h3F800002;
VAR42[190] <=32'h3F800003;
VAR42[191] <=32'h3F800003;
VAR42[192] <=32'h3F800004;
VAR42[193] <=32'h3F800004;
VAR42[194] <=32'h3F800004;
VAR42[195] <=32'h3F800004;
VAR42[196] <=32'h3F800003;
VAR42[197] <=32'h3F800004;
VAR42[198] <=32'h3F800004;
VAR42[199] <=32'h3F800004;
VAR42[200] <=32'h3F800003;
VAR42[201] <=32'h3F800003;
VAR42[202] <=32'h3F800004;
VAR42[203] <=32'h3F800004;
VAR42[204] <=32'h3F800003;
VAR42[205] <=32'h3F800003;
VAR42[206] <=32'h3F800003;
VAR42[207] <=32'h3F800004;
VAR42[208] <=32'h3F800004;
VAR42[209] <=32'h3F800004;
VAR42[210] <=32'h3F800004;
VAR42[211] <=32'h3F800004;
VAR42[212] <=32'h3F800004;
VAR42[213] <=32'h3F800004;
VAR42[214] <=32'h3F800004;
VAR42[215] <=32'h3F800004;
VAR42[216] <=32'h3F800004;
VAR42[217] <=32'h3F800004;
VAR42[218] <=32'h3F800004;
VAR42[219] <=32'h3F800004;
VAR42[220] <=32'h3F800004;
VAR42[221] <=32'h3F800004;
VAR42[222] <=32'h3F800004;
VAR42[223] <=32'h3F800004;
VAR42[224] <=32'h3F800004;
VAR42[225] <=32'h3F800004;
VAR42[226] <=32'h3F800004;
VAR42[227] <=32'h3F800004;
VAR42[228] <=32'h3F800004;
VAR42[229] <=32'h3F800004;
VAR42[230] <=32'h3F800004;
VAR42[231] <=32'h3F800004;
VAR42[232] <=32'h3F800004;
VAR42[233] <=32'h3F800004;
VAR42[234] <=32'h3F800004;
VAR42[235] <=32'h3F800004;
VAR42[236] <=32'h3F800004;
VAR42[237] <=32'h3F800004;
VAR42[238] <=32'h3F800004;
VAR42[239] <=32'h3F800004;
VAR42[240] <=32'h3F800004;
VAR42[241] <=32'h3F800004;
VAR42[242] <=32'h3F800004;
VAR42[243] <=32'h3F800004;
VAR42[244] <=32'h3F800004;
VAR42[245] <=32'h3F800004;
VAR42[246] <=32'h3F800004;
VAR42[247] <=32'h3F800004;
VAR42[248] <=32'h3F800004;
VAR42[249] <=32'h3F800004;
VAR42[250] <=32'h3F800004;
VAR42[251] <=32'h3F800004;
VAR42[252] <=32'h3F800004;
VAR42[253] <=32'h3F800004;
VAR42[254] <=32'h3F800004;
VAR42[255] <=32'h3F800004;
VAR37[0] <=32'h3F70F10B;
VAR37[1] <=32'h3F638E53;
VAR37[2] <=32'h3F579450;
VAR37[3] <=32'h3F4CCCE7;
VAR37[4] <=32'h3F430C4B;
VAR37[5] <=32'h3F3A2EA5;
VAR37[6] <=32'h3F32165C;
VAR37[7] <=32'h3F2AAAC4;
VAR37[8] <=32'h3F23D724;
VAR37[9] <=32'h3F1D89F2;
VAR37[10] <=32'h3F17B43F;
VAR37[11] <=32'h3F12493E;
VAR37[12] <=32'h3F0D3DE4;
VAR37[13] <=32'h3F0888A2;
VAR37[14] <=32'h3F042121;
VAR37[15] <=32'h3F000019;
VAR37[16] <=32'h3F80000D;
VAR37[17] <=32'h3F71C737;
VAR37[18] <=32'h3F650D93;
VAR37[19] <=32'h3F5999B4;
VAR37[20] <=32'h3F4F3D0E;
VAR37[21] <=32'h3F45D18E;
VAR37[22] <=32'h3F3D37C1;
VAR37[23] <=32'h3F35556F;
VAR37[24] <=32'h3F2E1494;
VAR37[25] <=32'h3F276290;
VAR37[26] <=32'h3F212F82;
VAR37[27] <=32'h3F1B6DD0;
VAR37[28] <=32'h3F1611C1;
VAR37[29] <=32'h3F11112A;
VAR37[30] <=32'h3F0C6332;
VAR37[31] <=32'h3F080019;
VAR37[32] <=32'h3F878795;
VAR37[33] <=32'h3F80000D;
VAR37[34] <=32'h3F7286D7;
VAR37[35] <=32'h3F666681;
VAR37[36] <=32'h3F5B6DD1;
VAR37[37] <=32'h3F517477;
VAR37[38] <=32'h3F485925;
VAR37[39] <=32'h3F40001A;
VAR37[40] <=32'h3F385205;
VAR37[41] <=32'h3F313B2D;
VAR37[42] <=32'h3F2AAAC4;
VAR37[43] <=32'h3F249263;
VAR37[44] <=32'h3F1EE59E;
VAR37[45] <=32'h3F1999B3;
VAR37[46] <=32'h3F14A543;
VAR37[47] <=32'h3F100019;
VAR37[48] <=32'h3F8F0F1C;
VAR37[49] <=32'h3F871C7F;
VAR37[50] <=32'h3F80000D;
VAR37[51] <=32'h3F73334D;
VAR37[52] <=32'h3F679E94;
VAR37[53] <=32'h3F5D1760;
VAR37[54] <=32'h3F537A89;
VAR37[55] <=32'h3F4AAAC4;
VAR37[56] <=32'h3F428F76;
VAR37[57] <=32'h3F3B13CB;
VAR37[58] <=32'h3F342607;
VAR37[59] <=32'h3F2DB6F5;
VAR37[60] <=32'h3F27B97A;
VAR37[61] <=32'h3F22223B;
VAR37[62] <=32'h3F1CE753;
VAR37[63] <=32'h3F180019;
VAR37[64] <=32'h3F9696A4;
VAR37[65] <=32'h3F8E38F1;
VAR37[66] <=32'h3F86BCAF;
VAR37[67] <=32'h3F80000D;
VAR37[68] <=32'h3F73CF57;
VAR37[69] <=32'h3F68BA49;
VAR37[70] <=32'h3F5E9BED;
VAR37[71] <=32'h3F55556F;
VAR37[72] <=32'h3F4CCCE6;
VAR37[73] <=32'h3F44EC68;
VAR37[74] <=32'h3F3DA149;
VAR37[75] <=32'h3F36DB87;
VAR37[76] <=32'h3F308D57;
VAR37[77] <=32'h3F2AAAC4;
VAR37[78] <=32'h3F252964;
VAR37[79] <=32'h3F200019;
VAR37[80] <=32'h3F9E1E2B;
VAR37[81] <=32'h3F955562;
VAR37[82] <=32'h3F8D7950;
VAR37[83] <=32'h3F866673;
VAR37[84] <=32'h3F80000D;
VAR37[85] <=32'h3F745D31;
VAR37[86] <=32'h3F69BD52;
VAR37[87] <=32'h3F60001A;
VAR37[88] <=32'h3F570A57;
VAR37[89] <=32'h3F4EC506;
VAR37[90] <=32'h3F471C8B;
VAR37[91] <=32'h3F40001A;
VAR37[92] <=32'h3F396134;
VAR37[93] <=32'h3F33334D;
VAR37[94] <=32'h3F2D6B74;
VAR37[95] <=32'h3F280019;
VAR37[96] <=32'h3FA5A5B3;
VAR37[97] <=32'h3F9C71D4;
VAR37[98] <=32'h3F9435F2;
VAR37[99] <=32'h3F8CCCDA;
VAR37[100] <=32'h3F86186E;
VAR37[101] <=32'h3F80000D;
VAR37[102] <=32'h3F74DEB6;
VAR37[103] <=32'h3F6AAAC5;
VAR37[104] <=32'h3F6147C8;
VAR37[105] <=32'h3F589DA4;
VAR37[106] <=32'h3F5097CE;
VAR37[107] <=32'h3F4924AC;
VAR37[108] <=32'h3F423511;
VAR37[109] <=32'h3F3BBBD5;
VAR37[110] <=32'h3F35AD85;
VAR37[111] <=32'h3F300019;
VAR37[112] <=32'h3FAD2D3B;
VAR37[113] <=32'h3FA38E46;
VAR37[114] <=32'h3F9AF294;
VAR37[115] <=32'h3F933340;
VAR37[116] <=32'h3F8C30D0;
VAR37[117] <=32'h3F85D181;
VAR37[118] <=32'h3F80000D;
VAR37[119] <=32'h3F75556F;
VAR37[120] <=32'h3F6B8539;
VAR37[121] <=32'h3F627641;
VAR37[122] <=32'h3F5A1310;
VAR37[123] <=32'h3F52493E;
VAR37[124] <=32'h3F4B08ED;
VAR37[125] <=32'h3F44445E;
VAR37[126] <=32'h3F3DEF95;
VAR37[127] <=32'h3F380019;
VAR37[128] <=32'h3FB4B4C2;
VAR37[129] <=32'h3FAAAAB8;
VAR37[130] <=32'h3FA1AF36;
VAR37[131] <=32'h3F9999A7;
VAR37[132] <=32'h3F924932;
VAR37[133] <=32'h3F8BA2F6;
VAR37[134] <=32'h3F8590BF;
VAR37[135] <=32'h3F80000D;
VAR37[136] <=32'h3F75C2A9;
VAR37[137] <=32'h3F6C4EDF;
VAR37[138] <=32'h3F638E53;
VAR37[139] <=32'h3F5B6DD1;
VAR37[140] <=32'h3F53DCCA;
VAR37[141] <=32'h3F4CCCE6;
VAR37[142] <=32'h3F4631A6;
VAR37[143] <=32'h3F400019;
VAR37[144] <=32'h3FBC3C4A;
VAR37[145] <=32'h3FB1C72A;
VAR37[146] <=32'h3FA86BD7;
VAR37[147] <=32'h3FA0000D;
VAR37[148] <=32'h3F986193;
VAR37[149] <=32'h3F91746A;
VAR37[150] <=32'h3F8B2171;
VAR37[151] <=32'h3F855562;
VAR37[152] <=32'h3F80000D;
VAR37[153] <=32'h3F76277C;
VAR37[154] <=32'h3F6D0995;
VAR37[155] <=32'h3F649263;
VAR37[156] <=32'h3F5CB0A7;
VAR37[157] <=32'h3F55556F;
VAR37[158] <=32'h3F4E73B6;
VAR37[159] <=32'h3F480019;
VAR37[160] <=32'h3FC3C3D1;
VAR37[161] <=32'h3FB8E39C;
VAR37[162] <=32'h3FAF2879;
VAR37[163] <=32'h3FA66674;
VAR37[164] <=32'h3F9E79F5;
VAR37[165] <=32'h3F9745DE;
VAR37[166] <=32'h3F90B223;
VAR37[167] <=32'h3F8AAAB7;
VAR37[168] <=32'h3F851EC5;
VAR37[169] <=32'h3F80000D;
VAR37[170] <=32'h3F7684D7;
VAR37[171] <=32'h3F6DB6F5;
VAR37[172] <=32'h3F658484;
VAR37[173] <=32'h3F5DDDF7;
VAR37[174] <=32'h3F56B5C7;
VAR37[175] <=32'h3F500019;
VAR37[176] <=32'h3FCB4B59;
VAR37[177] <=32'h3FC0000D;
VAR37[178] <=32'h3FB5E51B;
VAR37[179] <=32'h3FACCCDA;
VAR37[180] <=32'h3FA49256;
VAR37[181] <=32'h3F9D1753;
VAR37[182] <=32'h3F9642D5;
VAR37[183] <=32'h3F90000D;
VAR37[184] <=32'h3F8A3D7D;
VAR37[185] <=32'h3F84EC5B;
VAR37[186] <=32'h3F80000D;
VAR37[187] <=32'h3F76DB87;
VAR37[188] <=32'h3F6E5860;
VAR37[189] <=32'h3F666680;
VAR37[190] <=32'h3F5EF7D8;
VAR37[191] <=32'h3F58001A;
VAR37[192] <=32'h3FD2D2E0;
VAR37[193] <=32'h3FC71C7F;
VAR37[194] <=32'h3FBCA1BC;
VAR37[195] <=32'h3FB33340;
VAR37[196] <=32'h3FAAAAB8;
VAR37[197] <=32'h3FA2E8C7;
VAR37[198] <=32'h3F9BD387;
VAR37[199] <=32'h3F955562;
VAR37[200] <=32'h3F8F5C36;
VAR37[201] <=32'h3F89D8AA;
VAR37[202] <=32'h3F84BDAE;
VAR37[203] <=32'h3F80000D;
VAR37[204] <=32'h3F772C3D;
VAR37[205] <=32'h3F6EEF09;
VAR37[206] <=32'h3F6739E8;
VAR37[207] <=32'h3F60001A;
VAR37[208] <=32'h3FDA5A68;
VAR37[209] <=32'h3FCE38F1;
VAR37[210] <=32'h3FC35E5E;
VAR37[211] <=32'h3FB999A7;
VAR37[212] <=32'h3FB0C319;
VAR37[213] <=32'h3FA8BA3C;
VAR37[214] <=32'h3FA16439;
VAR37[215] <=32'h3F9AAAB8;
VAR37[216] <=32'h3F947AEE;
VAR37[217] <=32'h3F8EC4F9;
VAR37[218] <=32'h3F897B4F;
VAR37[219] <=32'h3F849256;
VAR37[220] <=32'h3F80000D;
VAR37[221] <=32'h3F777791;
VAR37[222] <=32'h3F6F7BF9;
VAR37[223] <=32'h3F68001A;
VAR37[224] <=32'h3FE1E1F0;
VAR37[225] <=32'h3FD55563;
VAR37[226] <=32'h3FCA1B00;
VAR37[227] <=32'h3FC0000D;
VAR37[228] <=32'h3FB6DB7B;
VAR37[229] <=32'h3FAE8BB0;
VAR37[230] <=32'h3FA6F4EC;
VAR37[231] <=32'h3FA0000D;
VAR37[232] <=32'h3F9999A6;
VAR37[233] <=32'h3F93B148;
VAR37[234] <=32'h3F8E38F0;
VAR37[235] <=32'h3F89249F;
VAR37[236] <=32'h3F8469FB;
VAR37[237] <=32'h3F80000D;
VAR37[238] <=32'h3F77BE09;
VAR37[239] <=32'h3F70001A;
VAR37[240] <=32'h3FE96977;
VAR37[241] <=32'h3FDC71D5;
VAR37[242] <=32'h3FD0D7A2;
VAR37[243] <=32'h3FC66674;
VAR37[244] <=32'h3FBCF3DC;
VAR37[245] <=32'h3FB45D24;
VAR37[246] <=32'h3FAC859E;
VAR37[247] <=32'h3FA55562;
VAR37[248] <=32'h3F9EB85F;
VAR37[249] <=32'h3F989D97;
VAR37[250] <=32'h3F92F692;
VAR37[251] <=32'h3F8DB6E8;
VAR37[252] <=32'h3F88D3E9;
VAR37[253] <=32'h3F844451;
VAR37[254] <=32'h3F80000D;
VAR37[255] <=32'h3F78001A;
end
else begin
VAR46 <= VAR40;
VAR48 <= VAR16;
VAR59 <= VAR55;
VAR13 <= VAR50;
VAR27 <= VAR53;
VAR6 <= VAR60;
VAR29 <= VAR52;
VAR11 <= VAR31;
case(VAR34)
VAR41:
begin
if (VAR47 == VAR22) begin
VAR61[31] <= ~VAR55[31];
VAR51[31] <= ~VAR55[31];
VAR61[30:0] <= VAR54[address][30:0];
VAR51[30:0] <= VAR58[address][30:0];
VAR32 <= VAR57[address];
end
end
VAR7:
begin
if (VAR47 == VAR22) begin
VAR61[31] <= ~VAR55[31];
VAR51[31] <= ~VAR55[31];
VAR61[30:0] <= VAR54[address][30:0];
VAR51[30:0] <= VAR56[address][30:0];
VAR32 <= VAR4[address];
end
end
VAR12:
begin
if (VAR47 == VAR14) begin
VAR51[22:0] <= VAR37[address][22:0];
VAR51[30:23] <= VAR37[address][30:23] + VAR43;
VAR51[31] <= VAR37[address][31];
VAR61[22:0] <= VAR37[address][22:0];
VAR61[30:23] <= VAR37[address][30:23] + VAR43;
VAR61[31] <= VAR37[address][31];
VAR32 <= 32'h3F800004;
end
end
VAR44:
begin
if (VAR47 == VAR14) begin
VAR51[22:0] <= VAR37[address][22:0];
VAR51[30:23] <= VAR37[address][30:23] + VAR43;
VAR51[31] <= VAR37[address][31];
VAR61[22:0] <= VAR37[address][22:0];
VAR61[30:23] <= VAR37[address][30:23] + VAR43;
VAR61[31] <= VAR37[address][31];
VAR32 <= 32'h3F800004;
end
end
VAR19:
begin
if (VAR47 == VAR9)begin
VAR61 <= VAR36[address];
VAR51 <= VAR30[address];
VAR32 <= VAR42[address];
end
end
VAR18:
begin
if (VAR47 == VAR9)begin
VAR61 <= VAR3[address];
VAR51 <= VAR30[address];
VAR32 <= VAR45[address];
end
end
VAR24:
begin
VAR32 <= VAR35;
VAR51 <= VAR38;
VAR61 <= VAR25;
end
endcase
end
end
endmodule
|
apache-2.0
|
CospanDesign/nysa-verilog
|
verilog/wishbone/slave/wb_sd_host/rtl/sd_host_stack.v
| 13,082 |
module MODULE1 #(
parameter VAR119 = 0,
parameter VAR22 = 0,
parameter VAR86 = 0,
parameter VAR78 = 11 )(
input clk,
input rst,
output VAR32,
input VAR66,
input [15:0] VAR91,
input VAR107,
output VAR6,
output VAR130,
output [7:0] VAR7,
input VAR139,
input [5:0] VAR73,
input [31:0] VAR62,
output VAR103,
input VAR99,
output [127:0] VAR120,
input VAR9,
input VAR49,
input [23:0] VAR3,
output VAR55,
input [2:0] VAR126,
input VAR149,
input [31:0] VAR132,
input [23:0] VAR75,
input [23:0] VAR34,
input [23:0] VAR111,
input [23:0] VAR110,
input [23:0] VAR50,
input [23:0] VAR114,
input [23:0] VAR101,
input [23:0] VAR138,
input [23:0] VAR64,
output [1:0] VAR14,
input [1:0] VAR131,
output [23:0] VAR68,
input VAR61,
input [31:0] VAR29,
output VAR116,
input VAR20,
output [23:0] VAR23,
input VAR81,
output [31:0] VAR84,
output VAR122,
input VAR13,
input VAR105,
output VAR2,
output VAR69,
input VAR17,
output VAR147,
output [3:0] VAR42,
output [3:0] VAR109,
output [7:0] VAR77,
output [7:0] VAR67,
output [15:0] VAR133,
output [15:0] VAR74,
output [15:0] VAR143,
output [15:0] VAR136,
output [15:0] VAR97,
output [15:0] VAR129,
output [15:0] VAR52,
output [15:0] VAR145,
output VAR108,
input [7:0] VAR134,
output [7:0] VAR11
);
wire VAR39;
wire [39:0] VAR5;
wire [7:0] VAR53;
wire [7:0] VAR71;
wire [135:0] VAR38;
wire VAR153;
wire VAR85;
wire VAR113;
wire VAR24;
wire [23:0] VAR137;
wire [31:0] VAR95;
wire [1:0] VAR118;
wire [1:0] VAR10;
wire VAR58;
wire [23:0] VAR36;
wire [31:0] VAR59;
wire VAR30;
wire VAR37;
wire VAR46;
wire VAR51;
wire VAR146;
wire [11:0] VAR45;
wire VAR82;
wire VAR60;
VAR26 VAR15(
.rst (rst || !VAR13 ),
.VAR121 (VAR139 ),
.VAR140 (VAR105 ),
.VAR70 (VAR37 )
);
VAR26 VAR106(
.rst (rst || !VAR13 ),
.VAR121 (VAR46 ),
.VAR140 (clk ),
.VAR70 (VAR103 )
);
VAR124 #(
.VAR94 (32 ),
.VAR151 (VAR78 )
)VAR150(
.reset (rst || !VAR13 ),
.VAR21 (clk ),
.VAR16 (VAR14 ),
.VAR100 (VAR131 ),
.VAR87 (VAR68 ),
.VAR125 (VAR61 ),
.VAR104 (VAR29 ),
.VAR93 (VAR1 ),
.VAR144 (VAR105 ),
.VAR142 (VAR85 ),
.VAR128 (VAR113 ),
.VAR12 (VAR24 ),
.VAR43 (VAR137 ),
.VAR96 (VAR95 )
);
VAR124 #(
.VAR94 (32 ),
.VAR151 (VAR78 )
)VAR76(
.reset (rst || !VAR13 ),
.VAR21 (VAR105 ),
.VAR16 (VAR118 ),
.VAR100 (VAR10 ),
.VAR87 (VAR36 ),
.VAR125 (VAR58 ),
.VAR104 (VAR59 ),
.VAR93 (VAR4 ),
.VAR144 (clk ),
.VAR142 (VAR116 ),
.VAR128 (VAR20 ),
.VAR12 (VAR81 ),
.VAR43 (VAR23 ),
.VAR96 (VAR84 )
);
VAR54 VAR27(
.clk (VAR105 ),
.rst (rst || !VAR13 ),
.VAR32 (VAR32 ),
.VAR66 (VAR66 ),
.VAR91 (VAR91 ),
.VAR28 (VAR107 ),
.VAR130 (VAR130 ),
.VAR7 (VAR7 ),
.VAR102 (VAR24 ),
.VAR88 (VAR58 ),
.VAR9 (VAR9 ),
.VAR49 (VAR49 ),
.VAR3 (VAR3 ),
.VAR55 (VAR55 ),
.VAR149 (VAR149 ),
.VAR126 (VAR126 ),
.VAR139 (VAR37 ),
.VAR103 (VAR46 ),
.VAR73 (VAR73 ),
.VAR62 (VAR62 ),
.VAR152 (VAR99 ),
.VAR120 (VAR120 ),
.VAR122 (VAR122 ),
.VAR132 (VAR132 ),
.VAR75 (VAR75 ),
.VAR34 (VAR34 ),
.VAR111 (VAR111 ),
.VAR110 (VAR110 ),
.VAR50 (VAR50 ),
.VAR114 (VAR114 ),
.VAR101 (VAR101 ),
.VAR138 (VAR138 ),
.VAR64 (VAR64 ),
.VAR65 (VAR39 ),
.VAR117 (VAR5 ),
.VAR92 (VAR53 ),
.VAR141(VAR153 ),
.VAR72 (VAR38 ),
.VAR79 (VAR71 ),
.VAR57 (VAR135 ),
.VAR98 (VAR51 ),
.VAR90 (VAR146 ),
.VAR33 (VAR45 ),
.VAR123 (VAR82 ),
.VAR63 (VAR60 )
);
VAR115 #(
.VAR119 (VAR119 ),
.VAR22 (VAR22 ),
.VAR86 (VAR86 )
)VAR80 (
.rst (rst || !VAR13 ),
.VAR6 (VAR6 ),
.VAR139 (VAR39 ),
.VAR73 (VAR5 ),
.VAR47 (VAR53 ),
.VAR120 (VAR38 ),
.VAR48 (VAR71 ),
.VAR44 (VAR153 ),
.VAR89 (VAR51 ),
.VAR55 (VAR146 ),
.VAR148 (VAR45 ),
.VAR49 (VAR82 ),
.VAR112 (VAR60 ),
.VAR18 (VAR85 ),
.VAR40 (VAR113 ),
.VAR56 (VAR137 ),
.VAR154 (VAR24 ),
.VAR19 (VAR95 ),
.VAR83 (VAR118 ),
.VAR35 (VAR10 ),
.VAR127 (VAR36 ),
.VAR31 (VAR58 ),
.VAR41 (VAR59 ),
.VAR2 (VAR2 ),
.VAR105 (VAR105 ),
.VAR69 (VAR69 ),
.VAR17 (VAR17 ),
.VAR147 (VAR147 ),
.VAR25 (VAR42 ),
.VAR8 (VAR109 ),
.VAR77 (VAR77 ),
.VAR67 (VAR67 ),
.VAR133 (VAR133 ),
.VAR74 (VAR74 ),
.VAR143 (VAR143 ),
.VAR136 (VAR136 ),
.VAR97 (VAR97 ),
.VAR129 (VAR129 ),
.VAR52 (VAR52 ),
.VAR145 (VAR145 ),
.VAR108 (VAR108 ),
.VAR134 (VAR134 ),
.VAR11 (VAR11 )
);
endmodule
|
mit
|
hakehuang/pycpld
|
ips/ip/pwm_capture/captuer_tx.v
| 2,234 |
module MODULE1(
clk,VAR2,VAR9,VAR6,VAR11,VAR3,VAR12,VAR4,VAR1,VAR5,VAR8
);
input clk;
input VAR2;
input VAR6;
input VAR4;
input VAR8;
input VAR1;
input[31:0] VAR11;
input[31:0] VAR3;
output VAR9;
output VAR5;
output [7:0] VAR12;
reg VAR9;
reg[15:0] VAR13;
reg[3:0] VAR10;
reg[7:0] VAR12;
reg VAR5;
always @ (posedge clk or negedge VAR2) begin
if (!VAR2)begin
VAR9 <= 1'b1;
VAR12 <= 'VAR7;
end
else if(VAR6 && (VAR13 >'d600))begin
case(VAR10)
4'b0000:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR11[7:0];
end
4'b0001:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR11[15:8];
end
4'b0010:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR11[23:16];
end
4'b0011:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR11[31:24];
end
4'b0100:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR3[7:0];
end
4'b0101:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR3[15:8];
end
4'b0110:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR3[23:16];
end
4'b0111:begin
VAR9 <= VAR9 ? 1'b0:1'b1;
VAR12 <= VAR3[31:24];
end
default:begin
VAR9 <= 1'b1;
VAR12 <= 'VAR7;
end
endcase
end
end
always @ (posedge VAR4 or negedge VAR1) begin
if (!VAR1)begin
VAR10 <= 'h0;
VAR5 <= 'h0;
end
else if(VAR4 && (VAR10<7)&&VAR6)begin
VAR10 <= VAR10 + 1'b1;
end
else begin
VAR5 <= 'h1;
end
end
always @ (posedge clk or negedge VAR2) begin
if (!VAR2)begin
VAR13 <= 'h0;
end
else if(!VAR8)begin
VAR13 <= VAR13 + 1'b1;
end
else begin
VAR13 <= 'h0;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/o21ai/sky130_fd_sc_hvl__o21ai.symbol.v
| 1,353 |
module MODULE1 (
input VAR6,
input VAR3,
input VAR1,
output VAR7
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.functional.pp.v
| 1,072 |
module MODULE1( VAR6, VAR3, VAR5, VAR9, VAR4 );
input VAR5, VAR6;
inout VAR9, VAR4;
output VAR3;
wire VAR8;
not VAR1( VAR8, VAR5 );
wire VAR7;
not VAR2( VAR7, VAR6 );
or VAR10( VAR3, VAR8, VAR7 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.v
| 2,334 |
module MODULE1 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR7 ,
VAR4,
VAR8,
VAR3 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR4;
input VAR8;
input VAR3 ;
input VAR1 ;
VAR10 VAR11 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5 ,
VAR6,
VAR2,
VAR9 ,
VAR7
);
output VAR5 ;
input VAR6;
input VAR2;
input VAR9 ;
input VAR7 ;
supply1 VAR4;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR1 ;
VAR10 VAR11 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/axi_ad9234/axi_ad9234_pnmon.v
| 10,780 |
module MODULE1 (
VAR7,
VAR3,
VAR15,
VAR5,
VAR14);
input VAR7;
input [63:0] VAR3;
output VAR15;
output VAR5;
input [ 3:0] VAR14;
reg [63:0] VAR12 = 'd0;
reg [63:0] VAR11 = 'd0;
wire [63:0] VAR1;
function [63:0] VAR13;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[22] ^ din[17];
dout[62] = din[21] ^ din[16];
dout[61] = din[20] ^ din[15];
dout[60] = din[19] ^ din[14];
dout[59] = din[18] ^ din[13];
dout[58] = din[17] ^ din[12];
dout[57] = din[16] ^ din[11];
dout[56] = din[15] ^ din[10];
dout[55] = din[14] ^ din[ 9];
dout[54] = din[13] ^ din[ 8];
dout[53] = din[12] ^ din[ 7];
dout[52] = din[11] ^ din[ 6];
dout[51] = din[10] ^ din[ 5];
dout[50] = din[ 9] ^ din[ 4];
dout[49] = din[ 8] ^ din[ 3];
dout[48] = din[ 7] ^ din[ 2];
dout[47] = din[ 6] ^ din[ 1];
dout[46] = din[ 5] ^ din[ 0];
dout[45] = din[ 4] ^ din[22] ^ din[17];
dout[44] = din[ 3] ^ din[21] ^ din[16];
dout[43] = din[ 2] ^ din[20] ^ din[15];
dout[42] = din[ 1] ^ din[19] ^ din[14];
dout[41] = din[ 0] ^ din[18] ^ din[13];
dout[40] = din[22] ^ din[12];
dout[39] = din[21] ^ din[11];
dout[38] = din[20] ^ din[10];
dout[37] = din[19] ^ din[ 9];
dout[36] = din[18] ^ din[ 8];
dout[35] = din[17] ^ din[ 7];
dout[34] = din[16] ^ din[ 6];
dout[33] = din[15] ^ din[ 5];
dout[32] = din[14] ^ din[ 4];
dout[31] = din[13] ^ din[ 3];
dout[30] = din[12] ^ din[ 2];
dout[29] = din[11] ^ din[ 1];
dout[28] = din[10] ^ din[ 0];
dout[27] = din[ 9] ^ din[22] ^ din[17];
dout[26] = din[ 8] ^ din[21] ^ din[16];
dout[25] = din[ 7] ^ din[20] ^ din[15];
dout[24] = din[ 6] ^ din[19] ^ din[14];
dout[23] = din[ 5] ^ din[18] ^ din[13];
dout[22] = din[ 4] ^ din[17] ^ din[12];
dout[21] = din[ 3] ^ din[16] ^ din[11];
dout[20] = din[ 2] ^ din[15] ^ din[10];
dout[19] = din[ 1] ^ din[14] ^ din[ 9];
dout[18] = din[ 0] ^ din[13] ^ din[ 8];
dout[17] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[16] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[15] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[14] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[13] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[12] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[11] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[10] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 9] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
dout[ 8] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
dout[ 7] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[15];
dout[ 6] = din[11] ^ din[ 1] ^ din[ 6] ^ din[19] ^ din[14];
dout[ 5] = din[10] ^ din[ 0] ^ din[ 5] ^ din[18] ^ din[13];
dout[ 4] = din[ 9] ^ din[22] ^ din[ 4] ^ din[12];
dout[ 3] = din[ 8] ^ din[21] ^ din[ 3] ^ din[11];
dout[ 2] = din[ 7] ^ din[20] ^ din[ 2] ^ din[10];
dout[ 1] = din[ 6] ^ din[19] ^ din[ 1] ^ din[ 9];
dout[ 0] = din[ 5] ^ din[18] ^ din[ 0] ^ din[ 8];
VAR13 = dout;
end
endfunction
function [63:0] VAR8;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 8] ^ din[ 4];
dout[62] = din[ 7] ^ din[ 3];
dout[61] = din[ 6] ^ din[ 2];
dout[60] = din[ 5] ^ din[ 1];
dout[59] = din[ 4] ^ din[ 0];
dout[58] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[57] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[56] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[55] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[54] = din[ 8] ^ din[ 0];
dout[53] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[52] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[51] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[50] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[49] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[48] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[47] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[46] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[45] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[44] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[43] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[42] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[41] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[40] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[39] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[38] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[37] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[36] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[35] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[34] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[33] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[32] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[31] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[27] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[26] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[25] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[24] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[23] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[22] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[21] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[20] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[18] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[17] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[12] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[11] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
dout[ 9] = din[ 3] ^ din[ 8] ^ din[ 5];
dout[ 8] = din[ 2] ^ din[ 4] ^ din[ 7];
dout[ 7] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[ 6] = din[ 0] ^ din[ 2] ^ din[ 5];
dout[ 5] = din[ 8] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 5] ^ din[ 1];
VAR8 = dout;
end
endfunction
assign VAR1 = (VAR15 == 1'b1) ? VAR12 : VAR11;
always @(posedge VAR7) begin
VAR12 <= { ~VAR3[15], VAR3[14: 0],
~VAR3[31], VAR3[30:16],
~VAR3[47], VAR3[46:32],
~VAR3[63], VAR3[62:48]};
if (VAR14 == 4'd0) begin
VAR11 <= VAR8(VAR1);
end else begin
VAR11 <= VAR13(VAR1);
end
end
VAR4 #(.VAR10(64)) VAR2 (
.VAR7 (VAR7),
.VAR6 (1'b1),
.VAR9 (VAR12),
.VAR16 (VAR11),
.VAR15 (VAR15),
.VAR5 (VAR5));
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.pp.blackbox.v
| 1,562 |
module MODULE1 (
VAR9 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR6 ,
VAR2 ,
VAR11,
VAR3 ,
VAR7 ,
VAR12 ,
VAR4
);
output VAR9 ;
output VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR11;
input VAR3 ;
input VAR7 ;
input VAR12 ;
input VAR4 ;
endmodule
|
apache-2.0
|
hoang26/processor_verilog
|
memory.v
| 2,901 |
module MODULE1(
VAR5,
VAR2,
VAR14,
VAR6,
VAR13,
VAR11,
VAR1
);
input [4*8:1] VAR5;
output [31:0] VAR2;
input [4*8:1] VAR14;
input [31:0] VAR6;
input VAR13;
input VAR11;
output [31:0] VAR1;
parameter VAR9=32'h00004000;
integer VAR7;
integer VAR8, VAR10;
reg [7:0] memory [0:VAR9-1];
reg [31:0] VAR12, VAR4;
reg [12*8:1] VAR3;
begin
begin
begin
|
gpl-2.0
|
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