repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
marco-c/leon-nexys2
|
grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_pe.v
| 36,620 |
module MODULE1( clk, rst,
VAR93, VAR12,
VAR59, VAR135, VAR108, VAR156,
VAR119, VAR116, VAR52, VAR85,
VAR96, VAR32, VAR98, VAR26,
VAR25, VAR123, VAR95, VAR133,
VAR23,
VAR143, VAR57,
VAR104, VAR86, VAR129,
VAR68, VAR5,
VAR17, VAR16,
VAR37, VAR107,
VAR64, VAR28,
VAR55, VAR34, VAR103,
VAR77, VAR126,
VAR146, VAR42,
VAR124, VAR125,
VAR43, VAR118, VAR13,
VAR145, VAR18, VAR122,
VAR76, VAR19,
VAR92, VAR83, VAR39,
VAR69, VAR9, VAR144,
VAR47,
VAR87, VAR30, VAR100
);
parameter VAR40 = 14;
input clk, rst;
input VAR93, VAR12;
input VAR59, VAR135, VAR108, VAR156;
input VAR119, VAR116, VAR52, VAR85;
input VAR96, VAR32, VAR98, VAR26;
input VAR25, VAR123, VAR95, VAR133;
input VAR23;
input VAR143; input VAR57;
input VAR104; input VAR86; input VAR129;
output VAR68;
output [1:0] VAR5;
output [1:0] VAR17;
output VAR16;
output VAR37; output VAR107; output VAR64; input VAR28; output [VAR40 + 2:0] VAR55; output [13:0] VAR34; output [13:0] VAR103; input [10:0] VAR77; output VAR126;
input VAR146; output [31:0] VAR42; input [3:0] VAR43; input VAR118; output VAR13; input VAR124, VAR125;
output VAR145; output VAR18; output VAR122; output VAR76; output VAR19; output VAR92; output VAR83; output VAR39; output VAR69; output VAR9; output VAR144; output VAR47;
input [31:0] VAR87; input [31:0] VAR30; input [31:0] VAR100;
parameter VAR75 = 0,
VAR50 = 1,
VAR73 = 2,
VAR66 = 3;
parameter [9:0]
VAR2 = 10'b0000000001,
VAR120 = 10'b0000000010,
VAR4 = 10'b0000000100,
VAR112 = 10'b0000001000,
VAR150 = 10'b0000010000,
VAR91 = 10'b0000100000,
VAR31 = 10'b0001000000,
VAR10 = 10'b0010000000,
VAR148 = 10'b0100000000,
VAR46 = 10'b1000000000;
reg [1:0] VAR5;
reg [1:0] VAR106;
reg VAR68;
reg VAR137;
reg VAR37, VAR107;
reg VAR81;
reg VAR144;
reg VAR39;
reg VAR41;
wire VAR51, VAR14, VAR152; wire VAR6, VAR151; wire VAR33, VAR11;
wire VAR45, VAR142; wire [1:0] VAR79; wire [10:0] VAR140;
wire [1:0] VAR7, VAR82;
wire VAR138;
reg VAR128, VAR3;
wire [VAR40 + 2:0] VAR131, VAR56;
wire [13:0] VAR155, VAR110;
reg [9:0] state, VAR35;
reg [1:0] VAR105;
reg [1:0] VAR60;
reg VAR63;
wire [1:0] VAR153;
wire [13:0] VAR1;
wire VAR141;
reg [VAR40 + 2:0] VAR55;
reg [13:0] VAR70;
reg [13:0] VAR61;
reg VAR99;
reg VAR149;
wire [VAR40 + 2:0] VAR80;
reg VAR102;
reg VAR8, VAR53;
wire VAR29;
reg VAR71;
reg VAR65;
reg VAR132;
reg [7:0] VAR67;
wire VAR109;
reg VAR22;
reg [7:0] VAR24;
wire [7:0] VAR38, VAR157;
reg VAR130;
wire [1:0] VAR21;
reg VAR54;
reg VAR121;
reg [31:0] VAR42;
reg VAR18, VAR122;
reg VAR76;
reg VAR19;
reg VAR27;
reg VAR145;
wire VAR134;
reg VAR94;
reg VAR117;
reg [VAR40 + 2:0] VAR154;
reg [13:0] VAR72;
reg VAR20;
reg VAR84;
reg VAR62;
wire VAR101, VAR97; reg VAR139; reg VAR147;
reg VAR136;
reg [1:0] VAR49;
reg VAR13;
reg VAR47, VAR127;
reg VAR64;
reg VAR114, VAR15;
reg VAR16;
assign VAR51 = VAR87[27:26]==2'b01;
assign VAR14 = VAR87[27:26]==2'b10;
assign VAR152 = VAR87[27:26]==2'b00;
assign VAR6 = VAR87[25:24]==2'b01;
assign VAR151 = VAR87[25:24]==2'b10;
assign VAR33 = VAR87[23:22]==2'b01;
assign VAR11 = VAR87[23:22]==2'b10;
assign VAR45 = VAR87[17];
assign VAR142 = VAR87[16];
assign VAR126 = VAR87[15] & !VAR152;
assign VAR79 = VAR87[12:11];
assign VAR140 = VAR87[10:0];
assign VAR7 = VAR87[29:28];
assign VAR82 = VAR87[31:30];
assign VAR131 = VAR30[VAR40 + 2:0];
assign VAR56 = VAR100[VAR40 + 2:0];
assign VAR155 = VAR30[30:17];
assign VAR110 = VAR100[30:17];
always @(posedge clk)
VAR128 <= VAR30[31] | ( &VAR131 );
always @(posedge clk)
VAR3 <= VAR100[31] | ( &VAR56 );
always @(posedge clk)
VAR114 <= &VAR131;
always @(posedge clk)
VAR15 <= &VAR56;
always @(posedge clk)
VAR41 <= VAR118;
always @(posedge clk)
VAR13 <= VAR143 & (VAR59 | VAR135 | VAR156) & !VAR118;
always @(posedge clk)
VAR68 <= VAR137;
always @(posedge clk)
VAR5 <= VAR106;
assign VAR153 = VAR23 ? VAR79 : 2'h0;
always @(posedge clk) casex({VAR153,VAR87[27:26],VAR87[25:24],VAR7}) 8'b0?0101??: VAR105 <= 2'b00;
8'b100101?0: VAR105 <= 2'b01; 8'b100101?1: VAR105 <= 2'b00;
8'b11010100: VAR105 <= 2'b01; 8'b11010101: VAR105 <= 2'b10; 8'b11010110: VAR105 <= 2'b00;
8'b0?1001??: VAR105 <= 2'b00;
8'b101001??: begin case({VAR85, VAR116}) 2'b10: VAR105 <= 2'b01;
2'b01: VAR105 <= 2'b00;
endcase
end
8'b11100100: begin case({VAR85, VAR52}) 2'b10: VAR105 <= 2'b01;
2'b01: VAR105 <= 2'b00;
endcase
end
8'b11100101: begin case({VAR85, VAR52}) 2'b10: VAR105 <= 2'b10;
2'b01: VAR105 <= 2'b00;
endcase
end
8'b11100110: begin case({VAR85, VAR52}) 2'b10: VAR105 <= 2'b01;
2'b01: VAR105 <= 2'b00;
endcase
end
8'VAR48??0100?0, 8'VAR48??1000?0: VAR105 <= 2'b01;
8'VAR48??0100?1, 8'VAR48??1000?1: VAR105 <= 2'b00;
8'VAR48??0110?0, 8'VAR48??1010?0: VAR105 <= 2'b01;
8'VAR48??0110?1, 8'VAR48??1010?1: VAR105 <= 2'b00;
8'VAR48??00????: casex({VAR62, VAR101, VAR97, VAR7}) 5'b1????: VAR105 <= 2'b11; 5'b0100?: VAR105 <= 2'b11; 5'b0101?: VAR105 <= 2'b01; 5'b001?0: VAR105 <= 2'b11; 5'b001?1: VAR105 <= 2'b10; endcase
endcase
always @(VAR119 or VAR116 or VAR52 or VAR85)
case({VAR119, VAR116, VAR52, VAR85} ) 4'b1000: VAR49 = 2'b00;
4'b0100: VAR49 = 2'b01;
4'b0010: VAR49 = 2'b10;
4'b0001: VAR49 = 2'b11;
endcase
always @(posedge clk) casex({VAR153,VAR87[27:26],VAR87[25:24],VAR7}) 8'b0?0101??: VAR60 <= 2'b00;
8'b100101?0: VAR60 <= 2'b01; 8'b100101?1: VAR60 <= 2'b00;
8'b11010100: VAR60 <= 2'b10; 8'b11010101: VAR60 <= 2'b01; 8'b11010110: VAR60 <= 2'b00;
8'b001001??: VAR60 <= VAR49; 8'b011001??: VAR60 <= 2'b00;
8'b101001?0: VAR60 <= 2'b11; 8'b101001?1: VAR60 <= 2'b01;
8'b11100100: VAR60 <= 2'b11; 8'b11100101: VAR60 <= 2'b11; 8'b11100110: VAR60 <= 2'b10;
8'VAR48??0100?0, 8'VAR48??1000?0: VAR60 <= 2'b00; 8'VAR48??0100?1, 8'VAR48??1000?1: VAR60 <= 2'b01;
8'VAR48??0110?0, 8'VAR48??1010?0: VAR60 <= 2'b00; 8'VAR48??0110?1, 8'VAR48??1010?1: VAR60 <= 2'b01;
8'VAR48??00????: casex({VAR62,VAR101, VAR97, VAR7}) 5'b1????: VAR60 <= 2'b00; 5'b0100?: VAR60 <= 2'b00; 5'b0101?: VAR60 <= 2'b01; 5'b001?0: VAR60 <= 2'b00; 5'b001?1: VAR60 <= 2'b01; endcase
endcase
assign VAR17 = VAR60;
always @(posedge clk)
VAR63 <= !( (VAR60==2'b00 & VAR119) |
(VAR60==2'b01 & VAR116) |
(VAR60==2'b10 & VAR52) |
(VAR60==2'b11 & VAR85) );
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) VAR20 <= 1'b0;
else
if(VAR135) VAR20 <= 1'b1;
else
if(VAR59 || VAR156) VAR20 <= 1'b0;
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) VAR84 <= 1'b0;
else
if(VAR59 || VAR156) VAR84 <= 1'b1;
else
if(VAR135) VAR84 <= 1'b0;
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) VAR62 <= 1'b0;
else
if(VAR156) VAR62 <= 1'b1;
else
if(VAR59 || VAR135) VAR62 <= 1'b0;
assign VAR101 = VAR51 | (VAR152 & VAR20);
assign VAR97 = VAR14 | (VAR152 & VAR84);
assign VAR138 = VAR126 ? 1'b0 : VAR152 ? VAR20 : ((VAR82[0] | VAR128) & !VAR3);
always @(posedge clk)
VAR55 <= VAR138 ? VAR56 : VAR131;
assign VAR103 = VAR138 ? VAR110 : VAR155;
assign VAR141 = VAR103 < {3'h0, VAR140};
assign VAR1 = VAR141 ? VAR103 : VAR140;
assign VAR34 = VAR1;
always @(posedge clk)
VAR99 <= VAR70 < {3'h0, VAR140};
always @(posedge clk)
VAR149 <= (VAR70 == 14'h0);
always @(posedge clk)
VAR102 <= VAR101 ? VAR149 : VAR99;
assign VAR134 = VAR126 &
((VAR51 & !VAR124) | (VAR14 & !VAR125));
always @(posedge clk)
VAR94 <= (VAR155 < {3'h0, VAR140});
always @(posedge clk)
VAR117 <= (VAR110 < {3'h0, VAR140});
always @(posedge clk)
VAR8 <= VAR128 | VAR134 |
(VAR138 ? VAR94 : (VAR99 & !VAR126));
always @(posedge clk)
VAR53 <= VAR3 | (VAR138 ? VAR99 : VAR117);
assign VAR29 = VAR8 & VAR53;
always @(posedge clk)
VAR61 <= (VAR97 && VAR126) ? VAR140 : (VAR101 ? VAR1 : VAR77);
always @(posedge clk)
VAR70 <= VAR103 - VAR61;
always @(posedge clk)
VAR154 <= VAR55;
always @(posedge clk)
VAR72 <= VAR1;
assign VAR80 = VAR154[VAR40 + 2:0] +
((VAR97 && VAR126) ? {{VAR40 + 2-10{1'b0}}, VAR140[10:0]} :
(VAR101 ? {{VAR40 + 2-13{1'b0}}, VAR72[13:0] } :
{ {VAR40 + 2-10{1'b0}}, VAR77[10:0]}));
always @(posedge clk)
VAR136 <= ( {3'h0, VAR77} > VAR103) & VAR104;
always @(posedge clk)
VAR127 <= VAR121 & VAR97 & VAR126 & (VAR77 != VAR140);
always @(posedge clk)
VAR47 <= VAR127;
always @(posedge clk)
VAR139 <= !VAR142 & (VAR77 < VAR140);
always @(posedge clk)
VAR147 <= !VAR45 & (VAR77 > VAR140);
assign VAR21 = VAR126 ? 2'h0 : VAR102 ? VAR82 + 2'h1 : VAR82;
always @(posedge clk)
VAR42[31:17] <= VAR127 ? {4'h0,VAR77} : {VAR102,VAR70};
always @(posedge clk)
VAR42[VAR40 + 2:4] <= VAR127 ? VAR131[VAR40 + 2:4] :
VAR80[VAR40 + 2:4];
always @(posedge clk)
if(VAR54) VAR42[3:0] <= VAR80[3:0];
else
if(VAR127) VAR42[3:0] <= VAR131[3:0];
else VAR42[3:0] <= {VAR105, VAR21};
always @(posedge clk)
VAR18 <= !VAR138 & VAR54;
always @(posedge clk)
VAR122 <= VAR138 & VAR54;
always @(posedge clk)
VAR76 <= VAR121;
always @(posedge clk)
VAR19 <= VAR121;
always @(posedge clk)
VAR145 <= VAR27;
always @(posedge clk)
VAR64 <= VAR136 | (VAR118 & (state != VAR2) ) | (VAR41 & VAR147);
always @(posedge clk)
VAR71 <= VAR93 | VAR65;
always @(posedge clk)
if(VAR71) VAR67 <= 8'h0;
else VAR67 <= VAR67 + 8'h1;
always @(posedge clk)
VAR132 <= (VAR67 == VAR38);
assign VAR38 = VAR23 ? VAR90 : VAR44;
assign VAR109 = VAR12;
always @(posedge clk)
if(VAR109) VAR24 <= 8'h0;
else VAR24 <= VAR24 + 8'h1;
always @(posedge clk)
VAR22 <= (VAR24 == VAR157);
assign VAR157 = VAR23 ? VAR111 : VAR74;
reg VAR36, VAR89, VAR113, VAR115;
assign VAR92 = !VAR138 & VAR102 & VAR130 & !VAR15;
assign VAR83 = VAR138 & VAR102 & VAR130 & !VAR114;
always @(posedge clk)
VAR36 <= VAR59;
always @(posedge clk)
VAR89 <= VAR135;
always @(posedge clk)
VAR113 <= VAR133;
always @(posedge clk)
VAR115 <= VAR156;
always @(posedge clk)
VAR39 <= VAR41 & !VAR108 & (
( VAR14 & !(VAR36 | VAR113)) |
( VAR51 & !VAR89) |
(VAR152 & !(VAR89 | VAR36 | VAR113 | VAR115))
);
assign VAR9 = ((state == VAR112) & VAR132) | ((state == VAR150) & VAR22);
assign VAR69 = VAR86 & VAR129;
always @(posedge clk)
VAR144 <= VAR81;
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) state <= VAR2;
else
if(VAR118) state <= VAR2;
else state <= VAR35;
always @(state or VAR11 or VAR128 or VAR3 or
VAR63 or VAR28 or VAR143 or VAR96 or VAR86 or
VAR22 or VAR129 or VAR33 or VAR29 or VAR23
or VAR126 or VAR132 or VAR133 or VAR6 or VAR139 or VAR147 or
VAR152 or VAR135 or VAR59 or VAR51 or VAR14 or VAR156 or VAR108
or VAR41 or VAR64 or VAR102 or VAR134 or VAR140)
begin
VAR35 = state;
VAR106 = VAR75;
VAR137 = 1'b0;
VAR37 = 1'b0;
VAR107 = 1'b0;
VAR54 = 1'b0;
VAR121 = 1'b0;
VAR27 = 1'b0;
VAR130 = 1'b0;
VAR65 = 1'b1;
VAR81 = 1'b0;
VAR16 = 1'b0;
case(state) VAR2:
begin
", );
if(rst && VAR41 && !VAR33 && !VAR108)
begin
if(VAR41 === 1'VAR58) ", );
if(VAR33 === 1'VAR58)", );
if(VAR108 === 1'VAR58) ", );
if(VAR11 === 1'VAR58) ", );
if(VAR128 === 1'VAR58) ", );
if(VAR3 === 1'VAR58) ", );
if(VAR134 === 1'VAR58)", );
if(VAR152 === 1'VAR58) ", );
if(VAR135 === 1'VAR58) ", );
if(VAR59 === 1'VAR58) ", );
if(VAR156 === 1'VAR58) ", );
if(VAR133 === 1'VAR58) ", );
if(VAR23 === 1'VAR58) ", );
if(VAR51 === 1'VAR58) ", );
if(VAR14 === 1'VAR58) ", );
end
if(VAR41 && !VAR33 && !VAR108)
begin
if(VAR11) begin
VAR106 = VAR73;
VAR137 = 1'b1;
VAR35 = VAR120;
end
else
if( (VAR128 && VAR3) || VAR134 ||
(VAR152 && VAR135 && VAR3) ||
(VAR152 && VAR59 && VAR128)
)
begin VAR106 = VAR50;
VAR137 = 1'b1;
VAR35 = VAR120;
end
else
if(VAR133 && VAR23)
begin
VAR106 = VAR75;
VAR137 = 1'b1;
VAR35 = VAR120;
end
else
if(VAR51 || (VAR152 && VAR135))
begin
if(VAR140 == 11'h0) VAR16 = 1'b1;
VAR107 = 1'b1;
VAR35 = VAR4;
end
else
if(VAR14 || (VAR152 && (VAR59 || VAR156)))
begin
VAR37 = 1'b1;
VAR35 = VAR150;
end
end
end
VAR120:
begin
", );
VAR35 = VAR2;
end
VAR4:
begin
", );
if(VAR28 === 1'VAR58) ", );
if(VAR6 === 1'VAR58) ", );
VAR65 = 1'b0;
if(VAR28)
begin
if(VAR6) VAR35 = VAR148;
end
else VAR35 = VAR112;
end
end
VAR112:
begin
", );
if(VAR132 === 1'VAR58) ", );
if(VAR143 === 1'VAR58)", );
if(VAR96 === 1'VAR58) ", );
VAR65 = 1'b0;
if(VAR132) VAR35 = VAR2;
end
else
if(VAR143 && VAR96)
begin
VAR35 = VAR148;
end
end
VAR150:
begin
", );
if(VAR22 === 1'VAR58) ", );
if(VAR129 === 1'VAR58) ", );
if(VAR64 === 1'VAR58) ", );
if(VAR86 === 1'VAR58)", );
if(VAR6 === 1'VAR58) ", );
if(VAR63 === 1'VAR58)", );
if(VAR22 || VAR129 || VAR64 )
VAR35 = VAR2;
end
else
if(VAR86)
begin if(VAR6)
begin
if(VAR63) VAR81 = 1'b1;
VAR35 = VAR10;
end
else VAR35 = VAR91;
end
end
VAR91:
begin VAR78 VAR88
", );
if(VAR64 === 1'VAR58) ", );
if(VAR64) VAR35 = VAR2;
end
else VAR35 = VAR31;
end
VAR31:
begin VAR78 VAR88
", );
if(VAR64 === 1'VAR58) ", );
if(VAR139 === 1'VAR58) ", );
if(VAR147 === 1'VAR58) ", );
if(VAR63 === 1'VAR58)", );
if(VAR23 === 1'VAR58) ", );
if(VAR29 === 1'VAR58) ", );
if(VAR64) VAR35 = VAR2;
end
else
if(VAR139 || VAR147)
begin
VAR106 = VAR50;
VAR35 = VAR2;
end
else
if(VAR63)
begin
VAR106 = VAR75;
VAR137 = 1'b1;
VAR35 = VAR2;
end
else
begin
if(VAR23 && VAR29) VAR106 = VAR66;
end
else VAR106 = VAR75;
VAR137 = 1'b1;
VAR35 = VAR148;
end
end
VAR10:
begin
", );
VAR35 = VAR148;
end
VAR148:
begin
", );
if(VAR102 === 1'VAR58) ", );
if(VAR126 === 1'VAR58) ", );
VAR130 = 1'b1;
if(VAR102 && VAR126)
begin
VAR27 = 1'b1;
end
else
begin
VAR54 = 1'b1;
end
VAR35 = VAR46;
end
VAR46: begin
", );
VAR121 = 1'b1;
VAR35 = VAR2;
end
endcase
end
endmodule
|
gpl-2.0
|
megari/sd2snes
|
verilog/sd2snes_cx4/main.v
| 21,198 |
module MODULE1(
input VAR257,
input [23:0] VAR53,
input VAR238,
input VAR165,
input VAR305,
inout [7:0] VAR194,
input VAR319,
input VAR231,
output VAR47,
output VAR196,
output VAR2,
input VAR323,
input [7:0] VAR36,
input VAR301,
input VAR174,
inout [15:0] VAR176,
output [22:0] VAR302,
output VAR77,
output VAR55,
output VAR236,
output VAR109,
output VAR132,
inout [7:0] VAR101,
output [18:0] VAR45,
output VAR24,
output VAR52,
output VAR186,
input VAR274,
inout VAR185,
input VAR192,
inout VAR199,
input VAR233,
output VAR79,
output VAR123,
output VAR17,
output VAR70,
input [3:0] VAR277,
inout VAR65,
inout VAR200,
output VAR91
);
wire VAR136;
wire [7:0] VAR33;
wire [7:0] VAR49;
wire [7:0] VAR103;
wire [7:0] VAR198;
wire [7:0] VAR171;
wire [31:0] VAR133;
wire [2:0] VAR261;
wire [23:0] VAR112;
wire [2:0] VAR128;
wire [23:0] VAR214;
wire [23:0] VAR167;
wire [7:0] VAR73;
wire [1:0] VAR298;
wire [10:0] VAR142;
wire [10:0] VAR169;
wire [10:0] VAR295;
wire [2:0] VAR260;
wire [8:0] VAR88;
wire [7:0] VAR140;
wire [7:0] VAR143;
wire [31:0] VAR326;
wire [15:0] VAR105;
wire [13:0] VAR293;
wire [13:0] VAR153;
wire [7:0] VAR304;
wire [7:0] VAR234;
wire [5:0] VAR280;
wire [5:0] VAR163;
wire [23:0] VAR296;
wire VAR18;
wire [23:0] VAR72;
wire [9:0] VAR13;
wire VAR308;
wire [8:0] VAR227;
wire [7:0] VAR203;
wire [7:0] VAR118;
reg [7:0] VAR178;
reg [7:0] VAR168;
reg [7:0] VAR201;
reg [7:0] VAR99;
reg [7:0] VAR106;
reg [23:0] VAR263 [6:0];
reg [7:0] VAR94 [6:0];
reg [7:0] VAR213 [4:0];
reg[17:0] VAR116 = 18'h00000;
reg VAR264 = 1;
reg VAR310 = 0;
reg VAR124 = 0;
wire VAR111 = ((VAR178[6:1] | VAR178[7:2]) == 6'b111110);
wire VAR110 = ((VAR168[6:1] | VAR168[7:2]) == 6'b111100);
wire VAR107 = ((VAR168[6:1] & VAR168[7:2]) == 6'b000001);
wire VAR228 = ((VAR201[6:1] & VAR201[7:2]) == 6'b000001);
wire VAR29 = ((VAR99[7:2] & VAR99[6:1]) == 6'b000011);
wire VAR120 = ((VAR99[7:2] | VAR99[6:1]) == 6'b111000);
wire VAR126 = VAR201[2] & VAR201[1];
wire VAR89 = VAR168[2] & VAR168[1];
wire VAR127 = VAR99[2] & VAR99[1];
wire VAR57 = VAR178[2] & VAR178[1];
wire VAR181 = (VAR106[5] & VAR106[4]);
wire [23:0] VAR324 = (VAR263[6] & VAR263[5]);
wire [7:0] VAR321 = (VAR94[6] & VAR94[5]);
wire [7:0] VAR266 = (VAR213[3] & VAR213[2]);
reg [7:0] VAR250;
always @(posedge VAR136) begin
if(~VAR89) VAR250 <= VAR194;
end
else if(~VAR126) VAR250 <= VAR266;
end
wire VAR173 = VAR120 | VAR124;
wire VAR267;
assign VAR245=0;
always @(posedge VAR136) begin
VAR124 <= 1'b0;
if(VAR29) VAR124 <= ~VAR267;
end
always @(posedge VAR136) begin
VAR178 <= {VAR178[6:0], VAR301};
VAR168 <= {VAR168[6:0], VAR238};
VAR201 <= {VAR201[6:0], VAR165};
VAR99 <= {VAR99[6:0], VAR319};
VAR106 <= {VAR106[6:0], VAR305};
VAR263[6] <= VAR263[5];
VAR263[5] <= VAR263[4];
VAR263[4] <= VAR263[3];
VAR263[3] <= VAR263[2];
VAR263[2] <= VAR263[1];
VAR263[1] <= VAR263[0];
VAR263[0] <= VAR53;
VAR94[6] <= VAR94[5];
VAR94[5] <= VAR94[4];
VAR94[4] <= VAR94[3];
VAR94[3] <= VAR94[2];
VAR94[2] <= VAR94[1];
VAR94[1] <= VAR94[0];
VAR94[0] <= VAR36;
VAR213[4] <= VAR213[3];
VAR213[3] <= VAR213[2];
VAR213[2] <= VAR213[1];
VAR213[1] <= VAR213[0];
VAR213[0] <= VAR194;
end
parameter VAR207 = 7'b0000001;
parameter VAR34 = 7'b0000010;
parameter VAR78 = 7'b0000100;
parameter VAR314 = 7'b0001000;
parameter VAR11 = 7'b0010000;
parameter VAR272 = 7'b0100000;
parameter VAR204 = 7'b1000000;
parameter VAR9 = 4'd6;
parameter VAR189 = 17'd80000;
reg [6:0] VAR114;
VAR96 VAR114 = VAR207;
assign VAR304 = VAR250;
assign VAR33 = VAR250;
VAR137 VAR68(
.VAR35(VAR136),
.VAR277(VAR277),
.VAR200(VAR200),
.VAR31(VAR31),
.VAR259(VAR259),
.VAR69(VAR69),
.VAR73(VAR73),
.VAR3(VAR3),
.VAR244(VAR244),
.VAR142(VAR142),
.VAR169(VAR169),
.VAR134(VAR134),
.VAR287(VAR287)
);
wire VAR14 = (VAR259 && (VAR298 == 2'b00));
VAR215 VAR230(
.VAR15(VAR136),
.VAR248(VAR323),
.VAR48(VAR123),
.VAR187(VAR17),
.VAR59(VAR70),
.VAR177(VAR298==2'b01 ? VAR69 : 1'b1),
.VAR292(VAR295),
.VAR256(VAR73),
.VAR84(VAR84),
.VAR62(VAR140),
.VAR19(VAR322),
.VAR122(VAR260),
.VAR82(VAR209),
.VAR265(VAR67),
.reset(VAR87),
.VAR129(VAR88)
);
VAR306 VAR41 (
.VAR15(VAR136),
.enable(VAR85),
.VAR292(VAR293),
.VAR256(VAR73),
.VAR100(VAR298==2'b10 ? VAR69 : 1'b1),
.VAR283(VAR324[2:0]),
.VAR255(VAR304),
.VAR242(VAR234),
.VAR247(VAR110),
.VAR148(VAR107),
.VAR223(VAR228),
.VAR4(VAR143),
.VAR150(VAR140),
.VAR86(VAR322),
.VAR146(VAR326),
.VAR138(VAR105),
.VAR312(VAR280),
.VAR235(VAR163),
.VAR158(VAR179),
.VAR37(VAR153),
.VAR241(VAR282)
);
VAR66 VAR197(
.clk(VAR136),
.VAR184(VAR274),
.VAR38(VAR185),
.VAR281(VAR192),
.VAR258(VAR199),
.VAR237(VAR251),
.VAR26(VAR218),
.VAR8(VAR103),
.VAR278(VAR198),
.VAR75(VAR95),
.VAR291(VAR104),
.VAR119(VAR171),
.VAR108(VAR133),
.VAR225(VAR261)
);
reg [7:0] VAR125;
wire [7:0] VAR262;
wire [7:0] VAR289;
wire [31:0] VAR1;
wire [7:0] VAR60;
wire [2:0] VAR145;
wire [15:0] VAR226;
wire [7:0] VAR152;
wire VAR307 = VAR289[5];
VAR205 VAR61(
.clk(VAR136),
.VAR130(VAR323),
.VAR237(VAR251),
.VAR26(VAR218),
.VAR8(VAR103),
.VAR278(VAR198),
.VAR273(VAR128),
.VAR285(VAR210),
.VAR43(VAR125),
.VAR10(VAR262),
.VAR133(VAR133),
.VAR261(VAR261),
.VAR162(VAR171),
.VAR146(VAR112),
.VAR141(VAR214),
.VAR224(VAR167),
.VAR31(VAR31),
.VAR259(VAR259),
.VAR3(VAR3),
.VAR73(VAR73),
.VAR69(VAR69),
.VAR298(VAR298),
.VAR244(VAR244),
.VAR142(VAR142),
.VAR169(VAR169),
.VAR134(VAR134),
.VAR287(VAR287),
.VAR206(VAR295),
.VAR84(VAR84),
.VAR268(VAR67),
.VAR155(VAR87),
.VAR260(VAR260),
.VAR209(VAR209),
.VAR156(VAR88),
.VAR149(VAR293),
.VAR56(VAR143),
.VAR220(VAR280),
.VAR157(VAR163),
.VAR179(VAR179),
.VAR98(VAR140),
.VAR51(VAR326),
.VAR193(VAR105),
.VAR284(VAR153),
.VAR318(VAR282),
.VAR313(VAR131),
.VAR30(VAR28),
.VAR12(VAR79),
.VAR160(VAR289),
.VAR92(VAR327),
.VAR253(VAR16),
.VAR191(VAR227),
.VAR183(VAR240),
.VAR299(VAR203),
.VAR115(VAR118),
.VAR97(VAR145),
.VAR90(VAR1),
.VAR290(VAR317),
.VAR252(VAR226)
);
wire [7:0] VAR288;
VAR300 VAR44(
.VAR257(VAR257),
.VAR32(VAR136),
.VAR211(VAR219),
.VAR315(VAR245),
.VAR316(VAR288)
);
address VAR190(
.VAR35(VAR136),
.VAR128(VAR128),
.VAR324(VAR324), .VAR321(VAR321),
.VAR302(VAR296), .VAR267(VAR267),
.VAR22(VAR22),
.VAR249(VAR249),
.VAR180(VAR180),
.VAR214(VAR214),
.VAR167(VAR167),
.VAR289(VAR289),
.VAR85(VAR85),
.VAR159(VAR159),
.VAR270(VAR270),
.VAR46(VAR46),
.VAR121(VAR121),
.VAR286(VAR286),
.VAR246(VAR246),
.VAR74(VAR74),
.VAR6(VAR6)
);
assign VAR245=0;
reg [7:0] VAR147;
wire [23:0] VAR27;
wire [2:0] VAR170;
VAR303 VAR309 (
.VAR172(VAR33),
.VAR102(VAR49),
.VAR212(VAR324[12:0]),
.VAR271(VAR159),
.VAR81(VAR270),
.VAR223(VAR228),
.VAR35(VAR136),
.VAR320(VAR147),
.VAR161(VAR27),
.VAR202(VAR117),
.VAR50(VAR54),
.VAR151(VAR151),
.VAR269(VAR170),
.VAR154(VAR226[0])
);
reg VAR5 = 0;
reg [4:0] VAR42 = 0;
reg VAR64 = 0;
VAR222 VAR25(
.clk(VAR136),
.VAR324(VAR324),
.VAR321(VAR321),
.VAR194(VAR194),
.VAR310(VAR310),
.VAR29(VAR29),
.VAR58(VAR228),
.VAR144(VAR110),
.VAR121(VAR121),
.VAR286(VAR286),
.VAR246(VAR246),
.VAR74(VAR74),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR64(VAR64),
.VAR279(VAR145),
.VAR100(VAR317),
.VAR71(VAR1),
.VAR80(VAR60),
.VAR40(VAR40),
.VAR182(VAR182)
);
wire [7:0] VAR195;
reg [7:0] VAR325;
reg VAR232;
reg [2:0] VAR254;
reg [1:0] VAR63;
VAR96 VAR325 = 8'h55;
VAR96 VAR232 = 0;
VAR96 VAR63 = 2'b01;
VAR96 VAR254 = 3'b000;
wire VAR328 = {VAR324[22], VAR324[15:0]} == 17'h04200;
wire VAR20 = {VAR324[22], VAR324[15:0]} == 17'h04016;
always @(posedge VAR136) begin
if(VAR228 & VAR328) begin
VAR64 <= VAR194[0];
end
end
always @(posedge VAR136) begin
if(VAR228 & VAR20) begin
VAR5 <= 1'b1;
VAR42 <= 5'h0;
end
if(VAR110 & VAR20) begin
VAR42 <= VAR42 + 1;
if(&VAR42[3:0]) begin
VAR5 <= 1'b0;
end
end
end
assign VAR194 = (VAR46 & ~VAR57 & ~VAR232) ? VAR325
:(~VAR89 ^ (VAR232 & VAR46 & ~VAR57))
? (VAR85 ? VAR234
:VAR159 ? VAR49
:(VAR151 & VAR270) ? VAR49
:(VAR40 & ~VAR307) ? VAR60
:(VAR182 | VAR307) & VAR121 ? VAR195
:(VAR18 ? VAR176[7:0] : VAR176[15:8])
): 8'VAR239;
reg [4:0] VAR113;
reg VAR208 = 0;
reg VAR297 = 0;
reg VAR39 = 0;
reg [23:0] VAR7;
reg [23:0] VAR175;
reg VAR139;
VAR96 VAR139 = 1'b1;
assign VAR79 = VAR139;
reg VAR243;
VAR96 VAR243 = 1'b1;
assign VAR54 = VAR243;
wire VAR221 = |(VAR114 & VAR314);
wire VAR311 = |(VAR114 & VAR34);
wire VAR21 = VAR221 | VAR311;
wire VAR166 = |(VAR114 & VAR272);
assign VAR302 = (VAR14) ? VAR112[23:1] : VAR21 ? VAR7[23:1] : VAR166 ? VAR175[23:1] : VAR296[23:1];
assign VAR18 = (VAR14) ? VAR112[0] : VAR21 ? VAR7[0] : VAR166 ? VAR175[0] : VAR296[0];
always @(posedge VAR136) begin
if(VAR151) begin
if(VAR117) begin
VAR39 <= 1'b1;
VAR243 <= 1'b0;
VAR175 <= VAR27;
end else if(VAR114 == VAR204) begin
VAR39 <= 1'b0;
VAR243 <= 1'b1;
end
end
end
always @(posedge VAR136) begin
if(VAR131) begin
VAR208 <= 1'b1;
VAR139 <= 1'b0;
VAR7 <= VAR112;
end else if(VAR28) begin
VAR297 <= 1'b1;
VAR139 <= 1'b0;
VAR7 <= VAR112;
end else if(VAR114 & (VAR78 | VAR11)) begin
VAR208 <= 1'b0;
VAR297 <= 1'b0;
VAR139 <= 1'b1;
end
end
always @(posedge VAR136) begin
if(~VAR99[1]) VAR116 <= VAR116 + 1;
end
else VAR116 <= 17'h0;
end
always @(posedge VAR136) begin
VAR310 <= 1'b0;
if(VAR99[1]) begin
VAR264 <= 1'b0;
if(VAR264) VAR310 <= 1'b1;
end
else if(VAR116 > VAR189) VAR264 <= 1'b1;
end
always @(posedge VAR136) begin
end
if(VAR264 & VAR99[1]) VAR114 <= VAR207; else
case(VAR114)
VAR207: begin
VAR114 <= VAR207;
if(VAR151) begin
if (VAR39) begin
VAR114 <= VAR272;
VAR113 <= 16;
end
end else if(VAR173 | VAR264) begin
if(VAR208) begin
VAR114 <= VAR34;
VAR113 <= VAR9;
end else if(VAR297) begin
VAR114 <= VAR314;
VAR113 <= VAR9;
end
end
end
VAR34: begin
VAR114 <= VAR34;
VAR113 <= VAR113 - 1;
if(VAR113 == 0) VAR114 <= VAR78;
VAR125 <= (VAR18 ? VAR176[7:0] : VAR176[15:8]);
end
VAR314: begin
VAR114 <= VAR314;
VAR113 <= VAR113 - 1;
if(VAR113 == 0) VAR114 <= VAR11;
end
VAR78, VAR11: begin
VAR114 <= VAR207;
end
VAR272: begin
VAR114 <= VAR272;
VAR113 <= VAR113 - 1;
if(VAR113 == 0) VAR114 <= VAR204;
VAR147 <= (VAR18 ? VAR176[7:0] : VAR176[15:8]);
end
VAR204: begin
VAR114 <= VAR207;
end
endcase
end
always @(posedge VAR136) begin
if(VAR120) VAR232 <= 1'b1;
end
else if(VAR111 & VAR46) begin
VAR232 <= 1'b0;
VAR63 <= 2'b01;
VAR325 <= {VAR194[7:5], VAR16, VAR194[3:0]};
end
end
reg VAR275;
always @(posedge VAR136) VAR275<= VAR210;
assign VAR176[7:0] = VAR18
?(VAR14 ? (!VAR275 ? VAR262 : 8'VAR239)
: (VAR267 & ~VAR126) ? VAR194
: VAR221 ? VAR262 : 8'VAR239
)
:8'VAR239;
assign VAR176[15:8] = VAR18 ? 8'VAR239
:(VAR14 ? (!VAR275 ? VAR262 : 8'VAR239)
: (VAR267 & ~VAR126) ? VAR194
: VAR221 ? VAR262
: 8'VAR239
);
assign VAR236 = VAR14
?VAR210
: (VAR267 & VAR180 & VAR127) ? VAR126
: VAR221 ? 1'b0
: 1'b1;
assign VAR55 = 1'b0;
assign VAR77 = 1'b0;
assign VAR109 = VAR18;
assign VAR132 = !VAR18;
assign VAR196 = VAR85 ? 1'b0 :
VAR159 ? 1'b0 :
(VAR151 & VAR270) ? 1'b0 :
VAR46 & !VAR57 ? 1'b0 :
VAR328 ? VAR126 :
VAR121 ? (~(VAR182 | VAR307) | (VAR89 & VAR126)) :
((VAR249 & VAR181)
|(!VAR249 & !VAR22 & !VAR180)
|(VAR89 & VAR126)
);
assign VAR2 = (~VAR89 | (~VAR57 & (VAR46)))
? 1'b1 ^ (VAR232 & VAR46 & ~VAR57)
: 1'b0;
assign VAR47 = 1'b0;
assign VAR91 = 1'b0;
VAR23 VAR135 (
.VAR216(VAR136), .VAR188(VAR228 & ((VAR182 | VAR307) & VAR121)), .VAR164(VAR324[8:0]), .VAR294(VAR194), .VAR93(VAR195), .VAR217(VAR136), .VAR83(VAR240), .VAR276(VAR227), .VAR76(VAR203), .VAR229(VAR118) );
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o22ai/sky130_fd_sc_hdll__o22ai_2.v
| 2,368 |
module MODULE1 (
VAR2 ,
VAR11 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR10,
VAR9,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR11 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR10;
input VAR9;
input VAR4 ;
input VAR1 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR2 ,
VAR11,
VAR8,
VAR6,
VAR5
);
output VAR2 ;
input VAR11;
input VAR8;
input VAR6;
input VAR5;
supply1 VAR10;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR1 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
JeremySavonet/Eurobot-2017-Moon-Village
|
software/custom_leds/fpga/soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v
| 4,885 |
module MODULE1(
VAR16,
VAR21,
VAR20,
VAR22,
VAR30,
VAR29,
VAR19,
VAR7,
VAR14,
VAR28
);
parameter VAR2 = 1;
parameter VAR5 = 8;
parameter VAR15 = 2;
parameter VAR10 = 2;
parameter VAR6 = 1;
localparam VAR26 = VAR2 * VAR5;
input VAR16;
input VAR21;
output VAR20;
input VAR22;
input [VAR26-1:0] VAR30;
input VAR29;
input VAR19;
input VAR7;
output VAR14;
output [VAR26-1:0] VAR28;
reg [VAR26-1:0] VAR27;
reg [VAR26-1:0] VAR31;
reg VAR32;
wire VAR17;
wire VAR12;
reg VAR1;
wire VAR3;
wire VAR23;
wire VAR18;
wire VAR13;
assign VAR20 = ~(VAR17 ^ VAR32);
assign VAR3 = VAR22 & VAR20;
assign VAR18 = VAR12 ^ VAR1;
assign VAR23 = VAR13 & VAR18;
always @(posedge VAR16 or posedge VAR21) begin
if (VAR21) begin
VAR27 <= {VAR26{1'b0}};
VAR32 <= 1'b0;
end else begin
if (VAR3) begin
VAR32 <= ~VAR32;
VAR27 <= VAR30;
end
end end
always @(posedge VAR29 or posedge VAR19) begin
if (VAR19) begin
VAR1 <= 1'b0;
VAR31 <= {VAR26{1'b0}};
end else begin
VAR31 <= VAR27;
if (VAR23) begin
VAR1 <= VAR12;
end
end end
VAR11 #(.VAR24(VAR15)) VAR25 (
.clk(VAR29),
.VAR4(~VAR19),
.din(VAR32),
.dout(VAR12)
);
VAR11 #(.VAR24(VAR10)) VAR8 (
.clk(VAR16),
.VAR4(~VAR21),
.din(VAR1),
.dout(VAR17)
);
generate if (VAR6 == 1) begin
VAR33
.VAR5(VAR5),
.VAR2(VAR2)
) VAR9 (
.clk(VAR29),
.reset(VAR19),
.VAR20(VAR13),
.VAR22(VAR18),
.VAR30(VAR31),
.VAR7(VAR7),
.VAR14(VAR14),
.VAR28(VAR28)
);
end else begin
assign VAR14 = VAR18;
assign VAR13 = VAR7;
assign VAR28 = VAR31;
end
endgenerate
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a2bb2o/sky130_fd_sc_hd__a2bb2o_2.v
| 2,463 |
module MODULE2 (
VAR11 ,
VAR10,
VAR4,
VAR3 ,
VAR1 ,
VAR9,
VAR8,
VAR7 ,
VAR2
);
output VAR11 ;
input VAR10;
input VAR4;
input VAR3 ;
input VAR1 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR2 ;
VAR6 VAR5 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR11 ,
VAR10,
VAR4,
VAR3 ,
VAR1
);
output VAR11 ;
input VAR10;
input VAR4;
input VAR3 ;
input VAR1 ;
supply1 VAR9;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
VAR6 VAR5 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
Monash-2015-Ultrasonic/Logs
|
Final System Code/SYSTEMV3/Source/IP/FIR/FIR.v
| 9,165 |
module MODULE1 (
input wire clk, input wire VAR8, input wire [15:0] VAR5, input wire VAR2, input wire [1:0] VAR6, output wire [29:0] VAR3, output wire VAR1, output wire [1:0] VAR4 );
VAR7 VAR9 (
.clk (clk), .VAR8 (VAR8), .VAR5 (VAR5), .VAR2 (VAR2), .VAR6 (VAR6), .VAR3 (VAR3), .VAR1 (VAR1), .VAR4 (VAR4) );
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.pp.blackbox.v
| 1,374 |
module MODULE1 (
VAR7 ,
VAR3 ,
VAR2,
VAR4 ,
VAR5 ,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR2;
input VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/rank_cntrl.v
| 16,479 |
module MODULE1 #
(
parameter VAR94 = 100,
parameter VAR78 = "8",
parameter VAR5 = 0,
parameter VAR49 = 4,
parameter VAR57 = 2,
parameter VAR33 = 5,
parameter VAR51 = 30,
parameter VAR38 = 8,
parameter VAR3 = 4,
parameter VAR71 = 4,
parameter VAR53 = 20,
parameter VAR81 = 16,
parameter VAR89 = 2,
parameter VAR29 = 4,
parameter VAR88 = "VAR70",
parameter VAR87 = 39
)
(
VAR30, VAR66, VAR92, VAR34,
VAR24,
clk, rst, VAR8, VAR62, VAR27, VAR44,
VAR68, VAR10, VAR77, VAR84,
VAR1, VAR18, VAR65, VAR37,
VAR55, VAR7, VAR56
);
input clk;
input rst;
function integer VAR74 (input integer VAR93); begin
VAR93 = VAR93 - 1;
for (VAR74=1; VAR93>1; VAR74=VAR74+1)
VAR93 = VAR93 >> 1;
end
endfunction
input [VAR49-1:0] VAR8;
input [VAR81-1:0] VAR62;
reg VAR46;
integer VAR80;
always @(VAR62 or VAR8) begin
VAR46 = 1'b0;
for (VAR80=0; VAR80<VAR49; VAR80=VAR80+1)
VAR46 =
VAR46 || (VAR8[VAR80] && VAR62[(VAR80*VAR29)+VAR5]);
end
localparam VAR21 = VAR3 - ((VAR57 == 1) ? 2 : 4);
localparam VAR14 = (VAR57 == 1)
? VAR21
: ((VAR21/2) + (VAR21%2));
localparam VAR82 = VAR74(VAR14 + 1);
reg VAR67 = 1'b0;
generate
if (VAR21 > 0) begin :VAR17
reg[VAR82-1:0] VAR52;
reg[VAR82-1:0] VAR91;
always @(VAR46 or VAR91 or rst) begin
VAR52 = VAR91;
if (rst) VAR52 = {VAR82{1'b0}};
end
else
if (VAR46)
VAR52 = VAR14[0+:VAR82];
end
else if (|VAR91) VAR52 =
VAR91 - {{VAR82-1{1'b0}}, 1'b1};
end
always @(VAR52) VAR67 = |VAR52;
end
endgenerate
localparam VAR73 = (VAR57 == 1)
? VAR51
: ((VAR51/2) + (VAR51%2));
output reg VAR30;
generate
begin : VAR47
wire VAR22;
wire [4:0] VAR61 = VAR73[4:0] - 5'd3;
VAR19 #(.VAR12(32'h00000000) ) VAR83
(.VAR4(VAR22), .VAR28(), .VAR36(VAR61), .VAR50(1'b1), .VAR32(clk), .VAR60(VAR46) );
reg [2:0] VAR6;
reg [2:0] VAR63;
reg VAR85;
always @(VAR22 or VAR46 or VAR67
or VAR63 or rst) begin
if (rst) VAR6 = 3'b0;
end
else begin
VAR6 = VAR63;
if (VAR46) VAR6 = VAR63 + 3'b1;
if (VAR22) VAR6 = VAR6 - 3'b1;
end
VAR85 = (VAR6 == 3'h4) || VAR67;
end
end endgenerate
localparam VAR25 = 1;
localparam VAR42 = ((VAR78 == "4") ? 2 : 4) + VAR71 + VAR33;
localparam VAR76 = (VAR57 == 1)
? VAR42
: ((VAR42 / 2) + (VAR42 %2));
localparam VAR69 = VAR74(VAR76 - 1);
localparam VAR16 = 2;
input [VAR49-1:0] VAR27;
input [VAR81-1:0] VAR44;
output reg VAR66;
output reg VAR92;
generate
begin : VAR2
reg VAR45;
always @(VAR27 or VAR44) begin
VAR45 = 1'b0;
for (VAR80 = 0; VAR80 < VAR49; VAR80 = VAR80 + 1)
VAR45 =
VAR45 || (VAR27[VAR80] && VAR44[(VAR80*VAR29)+VAR5]);
end
reg [VAR69-1:0] VAR35;
reg [VAR69-1:0] VAR48;
always @(rst or VAR45 or VAR35)
if (rst) VAR48 = {VAR69{1'b0}};
end
else begin
VAR48 = VAR35;
if (VAR45) VAR48 =
VAR76[VAR69-1:0] - VAR16[VAR69-1:0];
end
else if (|VAR35) VAR48 = VAR35 - VAR25[VAR69-1:0];
end
wire VAR54 = |VAR48;
wire VAR64 = VAR48 >= VAR16[VAR69-1:0];
end
endgenerate
localparam VAR90 = VAR74(VAR38 + 1);
input VAR68;
input VAR10;
input [(VAR29*VAR49)-1:0] VAR77;
input VAR84;
input VAR1;
input VAR18;
input [VAR89-1:0] VAR65;
output wire VAR34;
generate begin : VAR59
reg VAR79;
always @(VAR77) begin
VAR79 = 1'b0;
for (VAR80=0; VAR80 < VAR49; VAR80=VAR80+1)
VAR79 = VAR79 || VAR77[(VAR80*VAR29)+VAR5];
end
wire VAR31 =
VAR1 && ~VAR18 && (VAR65 == VAR5[VAR89-1:0]);
reg [VAR90-1:0] VAR43;
reg [VAR90-1:0] VAR9;
always @(VAR68 or VAR10 or VAR31
or VAR43 or VAR84)
if (~VAR10)
if (VAR87 == 0)
VAR9 = VAR38[0+:VAR90];
end
else VAR9 = {VAR90{1'b0}};
else
case ({VAR31, VAR84, VAR68})
3'b000, 3'b110, 3'b101, 3'b111 : VAR9 = VAR43;
3'b010, 3'b001, 3'b011 : VAR9 =
(|VAR43)?
VAR43 - VAR25[0+:VAR90]:
VAR43;
3'b100 : VAR9 =
VAR43 + VAR25[0+:VAR90];
VAR11: assert property (@(posedge clk)
(rst || (VAR43 <= VAR38)));
VAR72: assert property (@(posedge clk)
(rst || ~(~|VAR43 && ~VAR31 && VAR84)));
VAR13: cover property (@(posedge clk)
(rst && ~|VAR9 && (VAR43 ==
VAR25[0+:VAR90])));
VAR58: cover property (@(posedge clk)
(rst && (VAR43 ==
VAR38[0+:VAR90])));
assign VAR34 = VAR10 &&
(~|VAR43 ||
((VAR43 != VAR38[0+:VAR90]) && ~VAR79));
end
endgenerate
localparam VAR39 = VAR74(VAR53 + 1);
input VAR37;
input VAR55;
output VAR24;
input VAR7;
input [VAR81-1:0] VAR56;
generate begin : VAR75
if ( VAR88 != "VAR70" ) begin reg VAR86;
always @(VAR56 or VAR27) begin
VAR86 = 1'b0;
for (VAR80 = 0; VAR80 < VAR49; VAR80 = VAR80 + 1)
VAR86 =
VAR86 || (VAR27[VAR80] && VAR56[(VAR80*VAR29)+VAR5]);
end
reg [VAR39-1:0] VAR41;
reg [VAR39-1:0] VAR15;
always @(VAR10 or VAR55
or VAR41 or VAR86) begin
VAR15 = VAR41;
if (~VAR10)
VAR15 = {VAR39{1'b0}};
end
else if (VAR86)
VAR15 =
VAR53[0+:VAR39];
end
else if (|VAR41 && VAR55)
VAR15 =
VAR41 - VAR25[0+:VAR39];
end
wire VAR20 = VAR55 &&
(VAR41 == VAR25[0+:VAR39]);
reg VAR26;
wire VAR23 = ~rst &&
((VAR37 && VAR10) ||
((VAR53 != 0) && ~VAR10) ||
(~(VAR86 || VAR7) &&
(VAR26 || VAR20)));
always @(posedge clk) VAR26 <=
VAR40: cover property (@(posedge clk)
(rst && (VAR26 && VAR86)));
assign VAR24 = VAR10 && VAR26;
end else
assign VAR24 = 1'b0;
end
endgenerate
endmodule
|
lgpl-3.0
|
bluespec/Flute
|
builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkDM_FPR_Tap.v
| 7,716 |
module MODULE1(VAR69,
VAR59,
VAR49,
VAR34,
VAR40,
VAR64,
VAR8,
VAR53,
VAR60,
VAR23,
VAR52,
VAR31,
VAR7,
VAR22,
VAR48,
VAR44,
VAR9);
input VAR69;
input VAR59;
input VAR49;
output [69 : 0] VAR34;
output VAR40;
input [64 : 0] VAR64;
input VAR8;
output VAR53;
input [69 : 0] VAR60;
input VAR23;
output VAR52;
input VAR31;
output [64 : 0] VAR7;
output VAR22;
input VAR48;
output [426 : 0] VAR44;
output VAR9;
wire [426 : 0] VAR44;
wire [69 : 0] VAR34;
wire [64 : 0] VAR7;
wire VAR40,
VAR53,
VAR52,
VAR22,
VAR9;
wire [69 : 0] VAR39, VAR29;
wire VAR43,
VAR63,
VAR35,
VAR28,
VAR47;
wire [69 : 0] VAR57, VAR4;
wire VAR61,
VAR46,
VAR30,
VAR2,
VAR20;
wire [64 : 0] VAR58, VAR70;
wire VAR25, VAR62, VAR12, VAR32, VAR65;
wire [426 : 0] VAR6, VAR50;
wire VAR38,
VAR5,
VAR16,
VAR18,
VAR21;
wire VAR54,
VAR13,
VAR45,
VAR71,
VAR17,
VAR36,
VAR55,
VAR66,
VAR67,
VAR10,
VAR26,
VAR37;
assign VAR34 = VAR4 ;
assign VAR40 = VAR30 ;
assign VAR13 = VAR30 ;
assign VAR66 = VAR49 ;
assign VAR53 = VAR65 ;
assign VAR45 = VAR65 ;
assign VAR67 = VAR8 ;
assign VAR52 = VAR47 ;
assign VAR71 = VAR47 ;
assign VAR10 = VAR23 ;
assign VAR7 = VAR70 ;
assign VAR22 = VAR12 ;
assign VAR17 = VAR12 ;
assign VAR26 = VAR31 ;
assign VAR44 = VAR50 ;
assign VAR9 = VAR16 ;
assign VAR36 = VAR16 ;
assign VAR37 = VAR48 ;
VAR1 #(.VAR41(32'd70), .VAR51(1'd1)) VAR24(.VAR56(VAR59),
.VAR69(VAR69),
.VAR15(VAR39),
.VAR42(VAR28),
.VAR27(VAR63),
.VAR19(VAR43),
.VAR33(VAR29),
.VAR68(VAR47),
.VAR11(VAR35));
VAR1 #(.VAR41(32'd70), .VAR51(1'd1)) VAR72(.VAR56(VAR59),
.VAR69(VAR69),
.VAR15(VAR57),
.VAR42(VAR2),
.VAR27(VAR46),
.VAR19(VAR61),
.VAR33(VAR4),
.VAR68(VAR20),
.VAR11(VAR30));
VAR1 #(.VAR41(32'd65), .VAR51(1'd1)) VAR3(.VAR56(VAR59),
.VAR69(VAR69),
.VAR15(VAR58),
.VAR42(VAR32),
.VAR27(VAR62),
.VAR19(VAR25),
.VAR33(VAR70),
.VAR68(VAR65),
.VAR11(VAR12));
VAR1 #(.VAR41(32'd427), .VAR51(1'd1)) VAR14(.VAR56(VAR59),
.VAR69(VAR69),
.VAR15(VAR6),
.VAR42(VAR18),
.VAR27(VAR5),
.VAR19(VAR38),
.VAR33(VAR50),
.VAR68(VAR21),
.VAR11(VAR16));
assign VAR54 =
VAR35 && VAR20 &&
(!VAR29[69] || VAR21) ;
assign VAR55 = VAR54 ;
assign VAR39 = VAR60 ;
assign VAR28 = VAR23 ;
assign VAR63 = VAR54 ;
assign VAR43 = 1'b0 ;
assign VAR57 = VAR29 ;
assign VAR2 = VAR54 ;
assign VAR46 = VAR49 ;
assign VAR61 = 1'b0 ;
assign VAR58 = VAR64 ;
assign VAR32 = VAR8 ;
assign VAR62 = VAR31 ;
assign VAR25 = 1'b0 ;
assign VAR6 =
{ 102'h055555555555555554AAAAAAAA,
VAR29[68:64],
250'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
VAR29 } ;
assign VAR18 = VAR55 && VAR29[69] ;
assign VAR5 = VAR48 ;
assign VAR38 = 1'b0 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a21oi/sky130_fd_sc_lp__a21oi.functional.pp.v
| 2,006 |
module MODULE1 (
VAR1 ,
VAR14 ,
VAR4 ,
VAR10 ,
VAR11,
VAR3,
VAR15 ,
VAR16
);
output VAR1 ;
input VAR14 ;
input VAR4 ;
input VAR10 ;
input VAR11;
input VAR3;
input VAR15 ;
input VAR16 ;
wire VAR2 ;
wire VAR8 ;
wire VAR6;
and VAR7 (VAR2 , VAR14, VAR4 );
nor VAR5 (VAR8 , VAR10, VAR2 );
VAR9 VAR13 (VAR6, VAR8, VAR11, VAR3);
buf VAR12 (VAR1 , VAR6 );
endmodule
|
apache-2.0
|
finnball/igloo
|
infra/hdl/vga.v
| 1,433 |
module MODULE1(
input clk,
output VAR18,
output VAR4,
output VAR16,
output VAR6
);
parameter VAR19 = 640;
parameter VAR12 = 96;
parameter VAR17 = 16;
parameter VAR11 = 48;
parameter VAR5 = VAR19 + VAR12 + VAR17 + VAR11;
parameter VAR8 = 480;
parameter VAR3 = 2;
parameter VAR7 = 10;
parameter VAR1 = 33;
parameter VAR9 = VAR8 + VAR3 + VAR7 + VAR1;
localparam VAR14 = VAR10(VAR5);
localparam VAR2 = VAR10(VAR9);
reg [VAR14 - 1 : 0] VAR15 = 0;
reg [VAR2 - 1 : 0] VAR13 = 0;
always @ (posedge clk)
begin
if (VAR15 == VAR5 - 1)
begin
VAR15 <= 0;
end
else
begin
VAR15 <= VAR15 + 1;
end
end
always @ (posedge clk)
begin
if (VAR15 == VAR5 - 1)
begin
if (VAR13 == VAR9 - 1)
begin
VAR13 <= 0;
end
else
begin
VAR13 <= VAR13 + 1;
end
end
end
assign VAR16 = (VAR15 > VAR12 - 1);
assign VAR18 = (VAR13 > VAR3 - 1);
assign VAR6 = (VAR15 > VAR12 + VAR11 - 1) & (VAR15 < VAR12 + VAR11 + VAR19 - 1);
assign VAR4 = (VAR13 > VAR3 + VAR1 - 1) & (VAR13 < VAR3 + VAR1 + VAR8 - 1);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/mux2i/sky130_fd_sc_ls__mux2i_4.v
| 2,214 |
module MODULE2 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR2 ,
VAR4,
VAR8,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR5 ;
input VAR1 ;
VAR3 VAR10 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7 ,
VAR6,
VAR9,
VAR2
);
output VAR7 ;
input VAR6;
input VAR9;
input VAR2 ;
supply1 VAR4;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR1 ;
VAR3 VAR10 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
silent-observer/RCPU
|
CPU/source/TubeController.v
| 1,983 |
module MODULE2 (
input wire[3:0] VAR7,
input wire VAR10,
output reg[6:0] VAR3
);
always @ (*) begin
if (VAR10) begin
case (VAR7)
4'h0: VAR3 = 7'h00; 4'h1: VAR3 = 7'h73; 4'h2: VAR3 = 7'h78; 4'h3: VAR3 = 7'h50; 4'h4: VAR3 = 7'h1C; 4'h5: VAR3 = 7'h76; 4'h6: VAR3 = 7'h38; default: VAR3 = 7'b0;
endcase
end
else begin
case (VAR7)
4'h0: VAR3 = 7'h3F; 4'h1: VAR3 = 7'h06; 4'h2: VAR3 = 7'h5B; 4'h3: VAR3 = 7'h4F; 4'h4: VAR3 = 7'h66; 4'h5: VAR3 = 7'h6D; 4'h6: VAR3 = 7'h7D; 4'h7: VAR3 = 7'h07; 4'h8: VAR3 = 7'h7F; 4'h9: VAR3 = 7'h6F; 4'hA: VAR3 = 7'h77; 4'hB: VAR3 = 7'h7C; 4'hC: VAR3 = 7'h39; 4'hD: VAR3 = 7'h5E; 4'hE: VAR3 = 7'h79; 4'hF: VAR3 = 7'h71; default: VAR3 = 7'b0;
endcase
end
end
endmodule
module MODULE1 (
input wire[1:0] VAR5,
input wire[3:0] VAR9,
input wire[3:0] VAR4,
input wire[3:0] VAR12,
input wire[3:0] VAR11,
input wire[3:0] VAR1,
input wire[3:0] VAR13,
output wire[3:0] VAR2,
output wire[7:0] VAR6
);
wire[3:0] VAR7 = (VAR5 == 2'd0)? VAR9 :
(VAR5 == 2'd1)? VAR4 :
(VAR5 == 2'd2)? VAR12 :
VAR11;
MODULE2 MODULE1 (VAR7, VAR13[VAR5], VAR6[6:0]);
assign VAR6[7] = VAR1[VAR5];
assign VAR2 = (VAR5 == 2'd0)? 4'b0001 :
(VAR5 == 2'd1)? 4'b0010 :
(VAR5 == 2'd2)? 4'b0100 :
4'b1000;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/and4b/sky130_fd_sc_ls__and4b.functional.pp.v
| 1,988 |
module MODULE1 (
VAR13 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR11,
VAR1,
VAR14 ,
VAR16
);
output VAR13 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR11;
input VAR1;
input VAR14 ;
input VAR16 ;
wire VAR15 ;
wire VAR17 ;
wire VAR2;
not VAR8 (VAR15 , VAR4 );
and VAR9 (VAR17 , VAR15, VAR3, VAR7, VAR5 );
VAR12 VAR6 (VAR2, VAR17, VAR11, VAR1);
buf VAR10 (VAR13 , VAR2 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dfsbp/sky130_fd_sc_hd__dfsbp.functional.v
| 1,737 |
module MODULE1 (
VAR3 ,
VAR10 ,
VAR13 ,
VAR4 ,
VAR11
);
output VAR3 ;
output VAR10 ;
input VAR13 ;
input VAR4 ;
input VAR11;
wire VAR8;
wire VAR2 ;
not VAR12 (VAR2 , VAR11 );
VAR9 VAR5 VAR6 (VAR8 , VAR4, VAR13, VAR2 );
buf VAR7 (VAR3 , VAR8 );
not VAR1 (VAR10 , VAR8 );
endmodule
|
apache-2.0
|
freecores/zet86
|
impl/virtex4-ml403ep/lcd/lcd_display.v
| 3,540 |
module MODULE1 (
input [63:0] VAR8, input [63:0] VAR11, input [15:0] VAR5, input [15:0] VAR15,
input clk, input rst,
output reg VAR19,
output reg VAR4,
output reg VAR22,
output reg [7:4] VAR12
);
parameter VAR2 = 8;
parameter VAR16 = 16;
reg [VAR16+VAR2+1:0] VAR10 = 0;
reg [ 5:0] VAR13;
wire [127:0] VAR1;
wire [ 31:0] VAR18;
wire [ 4:0] VAR14;
wire [ 3:0] VAR9;
MODULE2 MODULE1 (
.in (VAR1),
.MODULE1 (VAR14),
.out (VAR9)
);
assign VAR1 = { VAR8, VAR11 };
assign VAR18 = { VAR5, VAR15 };
assign VAR14 = VAR10[VAR16+7:VAR16+3];
always @(posedge clk)
if (rst) VAR10 <= 26'hfffffff;
else begin
VAR10 <= VAR10 - 1;
casex (VAR10[VAR16+1+VAR2:VAR16+2])
8'hff: VAR13 <= 6'b000010; 8'hfe: VAR13 <= 6'b000010;
8'hfd: VAR13 <= 6'b001000;
8'hfc: VAR13 <= 6'b000000; 8'hfb: VAR13 <= 6'b001100;
8'hfa: VAR13 <= 6'b000000; 8'hf9: VAR13 <= 6'b000001;
8'hf8: VAR13 <= 6'b000000; 8'hf7: VAR13 <= 6'b000110;
8'hf6: VAR10[VAR16+1+VAR2:VAR16+2] <= 8'b10111111;
8'VAR6: VAR13 <= { 2'b10, VAR18[VAR14] ? VAR7(VAR9) : 4'h2 };
8'VAR21: VAR13 <= { 2'b10, VAR18[VAR14] ? VAR20(VAR9) : 4'h0 };
8'b10011111: VAR13 <= 6'h0c;
8'b10011110: VAR13 <= 6'h00;
8'b10011101: VAR10[VAR16+1+VAR2:VAR16+2] <= 8'b01011111;
8'VAR3: VAR13 <= { 2'b10, VAR18[VAR14] ? VAR7(VAR9) : 4'h2 };
8'VAR17: VAR13 <= { 2'b10, VAR18[VAR14] ? VAR20(VAR9) : 4'h0 };
8'b00111111: VAR13 <= 6'h08;
8'b00111110: VAR13 <= 6'h00;
8'b00111101: VAR10[VAR16+1+VAR2:VAR16+2] <= 8'b10111111;
default: VAR13 <= 6'b010000;
endcase
VAR22 <= ^VAR10[VAR16+1:VAR16+0] & ~VAR4;
{ VAR19, VAR4, VAR12 } <= VAR13;
end
function [3:0] VAR7;
input [3:0] VAR14;
begin
if (VAR14 < 8'd10) VAR7 = 4'h3;
end
else VAR7 = 4'h6;
end
endfunction
function [3:0] VAR20;
input [3:0] VAR14;
begin
if (VAR14 < 8'd10) VAR20 = VAR14 + 4'h0;
end
else VAR20 = VAR14 + 4'h7;
end
endfunction
endmodule
module MODULE2 (
input [127:0] in,
input [ 4:0] MODULE1,
output reg [ 3:0] out
);
always @(in or MODULE1)
case (MODULE1)
5'h00: out <= in[ 3: 0];
5'h01: out <= in[ 7: 4];
5'h02: out <= in[ 11: 8];
5'h03: out <= in[ 15: 12];
5'h04: out <= in[ 19: 16];
5'h05: out <= in[ 23: 20];
5'h06: out <= in[ 27: 24];
5'h07: out <= in[ 31: 28];
5'h08: out <= in[ 35: 32];
5'h09: out <= in[ 39: 36];
5'h0a: out <= in[ 43: 40];
5'h0b: out <= in[ 47: 44];
5'h0c: out <= in[ 51: 48];
5'h0d: out <= in[ 55: 52];
5'h0e: out <= in[ 59: 56];
5'h0f: out <= in[ 63: 60];
5'h10: out <= in[ 67: 64];
5'h11: out <= in[ 71: 68];
5'h12: out <= in[ 75: 72];
5'h13: out <= in[ 79: 76];
5'h14: out <= in[ 83: 80];
5'h15: out <= in[ 87: 84];
5'h16: out <= in[ 91: 88];
5'h17: out <= in[ 95: 92];
5'h18: out <= in[ 99: 96];
5'h19: out <= in[103:100];
5'h1a: out <= in[107:104];
5'h1b: out <= in[111:108];
5'h1c: out <= in[115:112];
5'h1d: out <= in[119:116];
5'h1e: out <= in[123:120];
5'h1f: out <= in[127:124];
endcase
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a311o/sky130_fd_sc_hd__a311o_1.v
| 2,437 |
module MODULE2 (
VAR10 ,
VAR8 ,
VAR9 ,
VAR11 ,
VAR7 ,
VAR4 ,
VAR12,
VAR3,
VAR1 ,
VAR6
);
output VAR10 ;
input VAR8 ;
input VAR9 ;
input VAR11 ;
input VAR7 ;
input VAR4 ;
input VAR12;
input VAR3;
input VAR1 ;
input VAR6 ;
VAR5 VAR2 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR10 ,
VAR8,
VAR9,
VAR11,
VAR7,
VAR4
);
output VAR10 ;
input VAR8;
input VAR9;
input VAR11;
input VAR7;
input VAR4;
supply1 VAR12;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
VAR5 VAR2 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor2b/sky130_fd_sc_hdll__nor2b.symbol.v
| 1,334 |
module MODULE1 (
input VAR6 ,
input VAR7,
output VAR3
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
Obijuan/open-fpga-verilog-tutorial
|
tutorial/Alhambra_II/T11-mux-2-1/mux2.v
| 1,243 |
module MODULE1(input wire clk, output reg [3:0] VAR1);
parameter VAR10 = 22; parameter VAR6 = 4'b1010; parameter VAR2 = 4'b0101;
wire [3:0] VAR8;
wire [3:0] VAR7;
wire sel;
assign VAR8 = VAR6;
assign VAR7 = VAR2;
always @(sel or VAR8 or VAR7)
if (sel==0)
VAR1 <= VAR8;
else
VAR1 <= VAR7;
VAR5 #(.VAR11(VAR10))
VAR9 (
.VAR3(clk),
.VAR4(sel)
);
endmodule
|
gpl-2.0
|
cpulabs/mist1032isa
|
src/mmu/mmu_table_load.v
| 2,880 |
module MODULE1(
input wire VAR16,
input wire VAR14,
input wire VAR19,
input wire VAR5,
input wire [31:0] VAR6,
output wire VAR20,
output wire VAR8,
input wire VAR11,
output wire [31:0] VAR17,
input wire VAR7,
input wire [63:0] VAR2,
output wire VAR13,
output wire [31:0] VAR1,
output wire [11:0] VAR18,
output wire [11:0] VAR21
);
reg [1:0] VAR9;
reg [31:0] VAR4;
localparam VAR15 = 2'h0;
localparam VAR12 = 2'h1;
localparam VAR10 = 2'h2;
wire VAR3 = VAR5 && (VAR9 == VAR15);
always@(posedge VAR16 or negedge VAR14)begin
if(!VAR14)begin
VAR4 <= 32'h0;
end
else if(VAR19)begin
VAR4 <= 32'h0;
end
else begin
if(VAR3)begin
VAR4 <= VAR6;
end
end
end
always@(posedge VAR16 or negedge VAR14)begin
if(!VAR14)begin
VAR9 <= VAR15;
end
else if(VAR19)begin
VAR9 <= VAR15;
end
else begin
case(VAR9)
VAR15:
begin
if(VAR3)begin
if(VAR11)begin
VAR9 <= VAR12;
end
else begin
VAR9 <= VAR10;
end
end
end
VAR12:
begin
if(!VAR11)begin
VAR9 <= VAR10;
end
end
VAR10:
begin
if(VAR7)begin
VAR9 <= VAR15;
end
end
default:
begin
VAR9 <= VAR15;
end
endcase
end
end
assign VAR20 = (VAR9 != VAR15);
assign VAR8 = (VAR9 == VAR12) || VAR3;
assign VAR17 = (VAR9 == VAR12)? VAR4 : VAR6;
assign VAR13 = (VAR9 == VAR10) && VAR7;
assign VAR1 = (VAR4[2])? VAR2[63:32] : VAR2[31:0];
assign VAR18 = VAR2[11:0];
assign VAR21 = VAR2[43:32];
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21bo/sky130_fd_sc_hdll__a21bo.symbol.v
| 1,396 |
module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR1,
output VAR3
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/fa/sky130_fd_sc_hd__fa.functional.pp.v
| 3,007 |
module MODULE1 (
VAR8,
VAR1 ,
VAR24 ,
VAR18 ,
VAR11 ,
VAR10,
VAR23,
VAR14 ,
VAR3
);
output VAR8;
output VAR1 ;
input VAR24 ;
input VAR18 ;
input VAR11 ;
input VAR10;
input VAR23;
input VAR14 ;
input VAR3 ;
wire VAR6 ;
wire VAR30 ;
wire VAR7 ;
wire VAR17 ;
wire VAR32 ;
wire VAR12 ;
wire VAR9 ;
wire VAR27;
wire VAR5 ;
wire VAR26 ;
or VAR2 (VAR6 , VAR11, VAR18 );
and VAR4 (VAR30 , VAR6, VAR24 );
and VAR21 (VAR7 , VAR18, VAR11 );
or VAR22 (VAR9 , VAR7, VAR30 );
VAR15 VAR25 (VAR27, VAR9, VAR10, VAR23);
buf VAR13 (VAR8 , VAR27 );
and VAR16 (VAR17 , VAR11, VAR24, VAR18 );
nor VAR20 (VAR32 , VAR24, VAR6 );
nor VAR29 (VAR12 , VAR32, VAR8 );
or VAR31 (VAR5 , VAR12, VAR17 );
VAR15 VAR19 (VAR26 , VAR5, VAR10, VAR23 );
buf VAR28 (VAR1 , VAR26 );
endmodule
|
apache-2.0
|
FAST-Switch/fast
|
projects/SDTS/example/hw-src/IPv6_LISP/parser_h.v
| 15,667 |
module MODULE1(
input VAR18,
input [130:0] VAR43,
input clk,
input reset,
input VAR26,
input VAR2,
input [138:0] VAR23,
output reg VAR15,
output reg VAR46,
output reg VAR45,
output reg [138:0] VAR13,
output reg VAR47,
output reg [138:0] VAR11,
output reg VAR19,
output reg [359:0] VAR7,
output reg [7:0] VAR9,
output reg [7:0] VAR21,
output reg [7:0] VAR5,
output reg [7:0] VAR22
);
reg [15:0] VAR38;
reg [7:0] VAR48;
reg [127:0] VAR42,VAR41;
reg [71:0] VAR29;
reg [7:0] VAR44;
reg [127:0] VAR14,VAR12,VAR6,VAR40,VAR24,VAR32,VAR3,VAR33;
reg [127:0] VAR4;
reg [3:0] VAR16;
parameter VAR37 = 4'd0,
VAR36 = 4'd1,
VAR35 = 4'd2,
VAR39 = 4'd3,
VAR27 = 4'd4,
VAR20 = 4'd5,
VAR10 = 4'd6,
VAR28 = 4'd7,
VAR30 = 4'd8,
VAR31 = 4'd9,
VAR1 = 4'd10,
VAR34 = 4'd11,
VAR17 = 4'd12,
VAR25 = 4'd13;
reg VAR8;
always @ (posedge clk or negedge reset)
if(!reset) begin
VAR15 <= 1'b1;
VAR8 <= 1'b0;
VAR46 <= 1'b0;
end
else begin
case(VAR8)
1'b0:
begin
if((VAR2 == 1'b0)&&(VAR26 == 1'b0)) begin
VAR15 <= 1'b1;
VAR8 <= 1'b1;
end
else
begin
VAR15 <= 1'b0;
end
end
1'b1:
begin
if(VAR2 == 1'b1)
begin
VAR15 <= 1'b0;
VAR8 <= 1'b0;
end
end
endcase
end
always @ (posedge clk or negedge reset)
if(!reset) begin
VAR9 <= 8'b0;
VAR21 <= 8'b0;
VAR5 <= 8'b0;
VAR22 <= 8'b0;
VAR48 <= 8'b0;
VAR42 <= 128'b0;
VAR41 <= 128'b0;
VAR29 <= 72'b0;
VAR7 <= 360'b0;
VAR19 <= 1'b0;
VAR45 <= 1'b0;
VAR13 <= 139'b0;
VAR47 <= 1'b0;
VAR11 <= 139'b0;
VAR38 <= 16'b0;
VAR4 <= 128'b0;
VAR16 <= VAR37;
end
else begin
case(VAR16)
VAR37: begin
VAR45 <= 1'b0; VAR47 <= 1'b0;
VAR19 <= 1'b0;
if(VAR2 == 1'b1)
begin
if((VAR23[138:136] == 3'b101) && (VAR23[31:16] == 16'h86dd))
begin
VAR16 <= VAR36;
VAR48 <= {4'b0,VAR23[131:128]};
VAR29[63:48] <= VAR23[15:0];
VAR45 <= 1'b1;
VAR13 <= VAR23;
end
else
begin
VAR45 <= 1'b0;
VAR16 <= VAR17;
end
end
else
begin
VAR16 <= VAR37;
VAR45 <= 1'b0;
end
end
VAR36: begin
VAR13 <= {3'b100,VAR23[135:0]};
VAR45 <= 1'b1;
VAR42[127:48] <= VAR23[79:0];
VAR29[47:0] <= VAR23[127:80];
VAR44 <= VAR23[95:88];
case(VAR48[2:0])
3'd0: VAR4 <= VAR14;
3'd1: VAR4 <= VAR12;
3'd2: VAR4 <= VAR6;
3'd3: VAR4 <= VAR40;
3'd4: VAR4 <= VAR24;
3'd5: VAR4 <= VAR32;
3'd6: VAR4 <= VAR3;
3'd7: VAR4 <= VAR33;
endcase
VAR16 <= VAR35;
end
VAR35:
begin
VAR13 <= {3'b100,VAR23[135:0]};
VAR45 <= 1'b1;
VAR42[47:0] <= VAR23[127:80];
VAR41[127:48] <= VAR23[79:0];
VAR16 <= VAR39;
end
VAR39:
begin
case(VAR48[2:0])
3'd0: begin
if({VAR41[127:48],VAR23[127:80]} != VAR14) begin VAR19 <= 1'b1;
VAR7 <= {4'b1000,356'b0};
VAR45 <= 1'b1;
if((VAR23[138:136] == 3'b110) || (VAR2 == 1'b0))
begin
VAR13 <={3'b110,VAR23[135:0]};
VAR16 <= VAR37;
end
else
begin
VAR13 <= {3'b100,VAR23[135:0]};
VAR16 <= VAR1;
end
end
else
begin
if((VAR44 == 8'd17) && (VAR23[63:48]==16'd4341)) begin
VAR16 <= VAR27;
VAR21 <= VAR21 +1'b1;
VAR45 <= 1'b1;
VAR13 <= {3'b100,VAR23[135:0]};
VAR19 <= 1'b0;
VAR29[71:64] <= {2'b11,6'b0};
end
else begin
VAR19 <= 1'b1;
VAR7 <= {4'b1000,356'b0};
VAR45 <= 1'b1;
if((VAR23[138:136] == 3'b110) || (VAR2 == 1'b0))
begin
VAR13 <={3'b110,VAR23[135:0]};
VAR16 <= VAR37;
end
else
begin
VAR13 <= {3'b100,VAR23[135:0]};
VAR16 <= VAR1;
end
end
end
end
default:
begin
if({VAR41[127:48],VAR23[127:80]} == VAR4)
begin
VAR19 <= 1'b1;
VAR7 <= {2'b01,358'b0};
VAR45 <= 1'b1;
if((VAR23[138:136] == 3'b110) || (VAR2 == 1'b0))
begin
VAR13 <={3'b110,VAR23[135:0]};
VAR16 <= VAR37;
end
else
begin
VAR13 <= {3'b100,VAR23[135:0]};
VAR16 <= VAR1;
end
end
else
begin
VAR45 <= 1'b1;
if((VAR23[138:136] == 3'b110) || (VAR2 == 1'b0))
begin
VAR13 <={3'b110,VAR23[135:0]};
VAR19 <= 1'b1;
VAR22 <= VAR22 +1'b1;
VAR7 <= {4'h1,4'b0,16'b0,VAR48,VAR42,VAR41,VAR29};
VAR16 <= VAR37;
end
else
begin
VAR13 <= {3'b110,VAR23[135:0]};
VAR9 <= 8'd1 + VAR9;
VAR16 <= VAR31;
end
end
end
endcase
end
VAR27:
begin
VAR13 <= {3'b100,VAR23[135:0]};
if(VAR23[79:72] == 8'd1) begin
if(VAR23[48] == 1'b1) begin
VAR38 <= VAR23[71:56]; VAR5 <= VAR5 +1'b1;
VAR7 <= {4'b0,4'b1100,VAR23[71:56],VAR48,VAR42,VAR41,VAR29};
end
else begin
VAR38 <= VAR23[71:56];
VAR7 <= {4'b0,4'b1000,VAR23[71:56],VAR48,VAR42,VAR41,VAR29};
end
end
else
begin
VAR7 <= {8'b0,16'b0,VAR48,VAR42,VAR41,VAR29};
end
VAR16 <= VAR20;
end
VAR20:
begin
VAR45 <= 1'b1;
VAR13 <= {3'b100,VAR23[135:0]};
VAR16 <= VAR10;
end
VAR10:
begin
VAR13 <= {3'b100,VAR23[135:0]};
VAR16 <= VAR28;
end
VAR28:
begin
VAR45 <= 1'b1;
VAR13 <= {3'b100,VAR23[135:0]};
VAR41[127:48] <= VAR23[79:0];
VAR16 <= VAR30;
end
VAR30:
begin
VAR45 <= 1'b1;
VAR19 <= 1'b1;
VAR41[47:0] <= VAR23[127:80];
if(VAR23[138:136]==3'b110)
begin
VAR13 <= {3'b110,VAR23[135:0]}; VAR16 <= VAR37;
VAR7 <= {4'h1,VAR7[355:200],VAR41[127:48],VAR23[127:80],VAR29};
end
else
begin
VAR13 <= {3'b110,VAR23[135:0]}; VAR16 <= VAR34;
VAR7 <= {4'h0,VAR7[355:200],VAR41[127:48],VAR23[127:80],VAR29};
end
end
VAR31:
begin
if(VAR29[31:16]>16'd1300) VAR7 <= {4'h2,4'b0,16'b0,VAR48,VAR42,VAR41,VAR29};
end
else VAR7 <= {8'b0,16'b0,VAR48,VAR42,VAR41,VAR29};
VAR19 <= 1'b1;
VAR45 <= 1'b0;
VAR47 <= 1'b1;
if((VAR2 == 1'b0) || (VAR23[138:136] == 3'b110))
begin
VAR16 <= VAR37;
VAR11 <= {3'b110,VAR23[135:0]};
end
else
begin
VAR16 <= VAR34;
VAR11 <= {3'b100,VAR23[135:0]};
end
end
VAR34:
begin
VAR45 <= 1'b0;
VAR19 <= 1'b0;
VAR47 <= 1'b1;
if((VAR2 == 1'b0) || (VAR23[138:136] == 3'b110))
begin
VAR16 <= VAR37;
VAR11 <= {3'b110,VAR23[135:0]};
end
else
begin
VAR16 <= VAR34;
VAR11 <= {3'b100,VAR23[135:0]};
end
end
VAR1:
begin
VAR19 <= 1'b0;
if((VAR2 == 1'b0) || (VAR23[138:136] == 3'b110))
begin
VAR16 <= VAR37;
VAR13 <= {3'b110,VAR23[135:0]};
end
else
begin
VAR16 <= VAR1;
VAR13 <= {3'b100,VAR23[135:0]};
end
end
VAR17:
begin
if(VAR23[138:136] == 3'b110) VAR16 <= VAR37;
end
default:
begin
VAR16 <= VAR37;
end
endcase
end
always @ (posedge clk or negedge reset)
if(!reset) begin
VAR12 <= 128'b0;VAR6 <= 128'b0;VAR40 <= 128'b0;
VAR24 <= 128'b0;VAR32 <= 128'b0;VAR3 <= 128'b0;VAR33 <= 128'b0;
end
else
begin
if(VAR18 == 1'b1)
begin
case(VAR43[130:128])
3'd0: VAR14 <= VAR43[127:0];
3'd1: VAR12 <= VAR43[127:0];
3'd2: VAR6 <= VAR43[127:0];
3'd3: VAR40 <= VAR43[127:0];
3'd4: VAR24 <= VAR43[127:0];
3'd5: VAR32 <= VAR43[127:0];
3'd6: VAR3 <= VAR43[127:0];
3'd7: VAR33 <= VAR43[127:0];
endcase
end
else VAR14 <= VAR14;
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/ha/sky130_fd_sc_lp__ha_lp.v
| 2,192 |
module MODULE2 (
VAR10,
VAR4 ,
VAR6 ,
VAR8 ,
VAR3,
VAR2,
VAR1 ,
VAR9
);
output VAR10;
output VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR9 ;
VAR7 VAR5 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR10,
VAR4 ,
VAR6 ,
VAR8
);
output VAR10;
output VAR4 ;
input VAR6 ;
input VAR8 ;
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR9 ;
VAR7 VAR5 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/efc/rtl/efc_lib.v
| 1,718 |
module MODULE1 (VAR3, VAR4, VAR2 );
parameter VAR10 = 1;
input [VAR10-1:0] VAR3 ; input VAR4 ;
output [VAR10-1:0] VAR2 ;
VAR7 VAR8[VAR10-1:0] (
.VAR9 (VAR2),
.VAR6 (VAR4),
.VAR1 (VAR3),
.VAR5(1'b1));
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.behavioral.v
| 3,472 |
module MODULE1 (
VAR11 ,
VAR2 ,
VAR33 ,
VAR15 ,
VAR18 ,
VAR31 ,
VAR36 ,
VAR5,
VAR19 ,
VAR23
);
output VAR11 ;
output VAR2 ;
input VAR33 ;
input VAR15 ;
input VAR18 ;
input VAR31 ;
input VAR36 ;
input VAR5;
input VAR19 ;
input VAR23 ;
wire VAR34 ;
wire VAR16 ;
wire VAR29 ;
wire VAR7 ;
reg VAR8 ;
wire VAR13 ;
wire VAR9 ;
wire VAR28 ;
wire VAR32 ;
wire VAR14 ;
wire VAR35;
wire VAR10 ;
wire VAR27 ;
wire VAR21 ;
wire VAR6 ;
wire VAR17 ;
wire VAR37 ;
wire VAR1 ;
wire VAR4 ;
not VAR38 (VAR34 , VAR35 );
not VAR20 (VAR16 , VAR14 );
not VAR12 (VAR29 , VAR32 );
VAR24 VAR26 (VAR10, VAR13, VAR9, VAR28 );
VAR30 VAR25 (VAR7 , VAR16, VAR34, VAR29, VAR10, VAR8, VAR19, VAR23);
assign VAR27 = ( VAR19 === 1'b1 );
assign VAR21 = ( VAR27 && ( VAR35 === 1'b1 ) );
assign VAR6 = ( VAR27 && ( VAR14 === 1'b1 ) );
assign VAR17 = ( VAR21 & VAR6 );
assign VAR37 = ( ( VAR28 === 1'b0 ) && VAR17 );
assign VAR1 = ( ( VAR28 === 1'b1 ) && VAR17 );
assign VAR4 = ( ( VAR13 !== VAR9 ) && VAR17 );
buf VAR22 (VAR11 , VAR7 );
not VAR3 (VAR2 , VAR7 );
endmodule
|
apache-2.0
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v
| 5,675 |
module MODULE1 #
(
parameter integer VAR39 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR39-1:0] VAR12,
output wire [1:0] VAR36,
output wire VAR50,
input wire VAR34,
input wire [1:0] VAR20,
input wire VAR51,
output wire VAR28,
input wire VAR42,
input wire [VAR39-1:0] VAR4,
input wire [7:0] VAR6,
input wire VAR31,
output wire VAR11
);
localparam [1:0] VAR45 = 2'b00;
localparam [1:0] VAR47 = 2'b01;
localparam [1:0] VAR16 = 2'b10;
localparam [1:0] VAR2 = 2'b11;
localparam VAR24 = VAR39 + 8;
localparam VAR7 = 4;
localparam VAR29 = 2;
localparam VAR27 = 2;
localparam VAR1 = 4;
localparam VAR30 = 2;
reg VAR9;
wire [VAR39-1:0] VAR46;
wire VAR33;
reg VAR40;
wire VAR26;
reg VAR38;
wire VAR15;
wire VAR44;
wire VAR23;
wire [7:0] VAR8;
reg [7:0] VAR17;
reg [1:0] VAR3;
wire [1:0] VAR21;
reg [1:0] VAR10;
wire VAR13;
wire VAR35;
assign VAR12 = VAR46;
assign VAR36 = VAR21;
assign VAR50 = VAR9;
assign VAR33 = VAR50 & VAR34;
assign VAR26 = VAR51 & VAR28;
always @(posedge clk) begin
if (reset | VAR33) begin
VAR9 <= 1'b0;
end else if (~VAR15 & ~VAR40 & ~VAR23) begin
VAR9 <= 1'b1;
end
end
always @(posedge clk) begin
VAR40 <= VAR33;
VAR38 <= VAR26;
end
VAR18 #(
.VAR43 (VAR24),
.VAR37 (VAR29),
.VAR19 (VAR7)
)
VAR25
(
.clk ( clk ) ,
.rst ( reset ) ,
.VAR32 ( VAR42 ) ,
.VAR48 ( VAR40 ) ,
.din ( {VAR4, VAR6} ) ,
.dout ( {VAR46, VAR8}) ,
.VAR14 ( ) ,
.VAR41 ( VAR11 ) ,
.VAR49 ( ) ,
.VAR22 ( VAR15 )
);
assign VAR28 = ~VAR38 & VAR23;
assign VAR13 = ( VAR20 > VAR3 );
always @( * ) begin
if ( VAR13 ) begin
VAR10 = VAR20;
end else begin
VAR10 = VAR3;
end
end
always @ (posedge clk) begin
if (reset | VAR35 ) begin
VAR3 <= VAR45;
end else if ( VAR26 ) begin
VAR3 <= VAR10;
end
end
assign VAR35 = ( VAR38 ) & (VAR17 == VAR8) & ~VAR15;
always @ (posedge clk) begin
if (reset | VAR35 ) begin
VAR17 <= 8'h00;
end else if ( VAR38 ) begin
VAR17 <= VAR17 + 1'b1;
end
end
VAR18 #(
.VAR43 (VAR27),
.VAR37 (VAR30),
.VAR19 (VAR1)
)
VAR5
(
.clk ( clk ) ,
.rst ( reset ) ,
.VAR32 ( VAR35 ) ,
.VAR48 ( VAR40 ) ,
.din ( VAR3 ) ,
.dout ( VAR21) ,
.VAR14 ( ) ,
.VAR41 ( VAR44 ) ,
.VAR49 ( ) ,
.VAR22 ( VAR23 )
);
endmodule
|
mit
|
Blunk-electronic/M-1
|
HW/ise/executor_mini/src/debouncer.v
| 4,455 |
module MODULE1 (clk, in, out, VAR6);
output reg out; input in; input clk;
input VAR6;
reg [VAR7-1:0] counter;
parameter [VAR7-1:0]
VAR5 = VAR7'h0,
VAR1 = VAR7'h1,
VAR9 = VAR7'h2,
VAR8 = VAR7'h3;
reg [VAR7-1:0] VAR4;
always @(posedge clk or negedge VAR6)
begin
if (~VAR6)
begin
counter <= #VAR3 VAR7'b0;
out <= #VAR3 1'b0;
VAR4 <= #VAR3 VAR5;
end
else
begin
case (VAR4)
VAR5:
begin
if (in)
begin
VAR4 <= #VAR3 VAR1;
end
end
VAR1:
begin
if (~in)
begin
counter <= #VAR3 VAR7'b0;
VAR4 <= #VAR3 VAR5;
end
else
begin
counter <= #VAR3 counter + 1;
if (counter == VAR2)
begin
out <= #VAR3 1'b1;
VAR4 <= #VAR3 VAR9;
end
end
end
VAR9:
begin
out <= #VAR3 1'b0;
VAR4 <= #VAR3 VAR8;
end
VAR8:
begin
if (~in)
begin
counter <= #VAR3 VAR7'b0;
VAR4 <= #VAR3 VAR5;
end
end
default:
begin
counter <= #VAR3 VAR7'b0;
VAR4 <= #VAR3 VAR5;
end
endcase
end
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.behavioral.pp.v
| 2,146 |
module MODULE1 (
VAR17,
VAR5,
VAR4 ,
VAR16,
VAR11,
VAR14 ,
VAR9
);
input VAR17;
input VAR5;
output VAR4 ;
input VAR16;
input VAR11;
input VAR14 ;
input VAR9 ;
wire VAR9 VAR12 ;
wire VAR9 VAR15 ;
wire VAR3 ;
wire VAR1;
and VAR8 (VAR12 , VAR14, VAR9 );
nor VAR6 (VAR15 , VAR16, VAR11 );
nor VAR2 (VAR3 , VAR15, VAR12 );
VAR13 VAR7 (VAR1, VAR3, VAR17, VAR5);
buf VAR10 (VAR4 , VAR1 );
endmodule
|
apache-2.0
|
ayushmaanbhav/cpu32bit
|
imemory.v
| 1,626 |
module MODULE1(output [31:0] VAR1,input [6:0] addr,input clk);
reg [31:0] VAR1;
reg [7:0] VAR2 [511:0];
begin
begin
|
mit
|
EliasLuiz/TCC
|
Leon3/lib/opencores/ge_1000baseX/ge_1000baseX.v
| 27,070 |
module MODULE1 #(
parameter VAR85 = 5'b00000,
VAR21 = 0
)(
input VAR69,
input VAR39,
input VAR78,
input VAR118,
input VAR32,
input [9:0] VAR163,
output [9:0] VAR37,
output [7:0] VAR107,
output VAR70,
output VAR128,
output VAR18,
output reg VAR146,
input [7:0] VAR71,
input VAR41,
input VAR102,
input VAR53,
input VAR132,
input VAR76,
output VAR167,
input VAR86,
output [31:0] VAR61
);
wire VAR89, VAR72, VAR109;
wire [15:0] VAR105;
wire [15:0] VAR23;
wire [4:0] VAR35;
wire VAR10;
VAR155 #(
.VAR85(VAR85)
) VAR147(
.reset(VAR132),
.VAR86(VAR86),
.VAR92(VAR89),
.VAR72(VAR72),
.VAR109(VAR109),
.VAR57(VAR35),
.VAR20(VAR23),
.VAR2(VAR105),
.VAR104(VAR10)
);
assign VAR167 = (VAR109) ? VAR72 : 1'b0;
assign VAR89 = VAR76;
wire [23:0] VAR12 = 24'ha1b2c3;
wire [7:0] VAR108 = { 4'b0000, 4'b0001 };
wire [15:0] VAR84; wire [15:0] VAR68; wire VAR36;
reg [15:0] VAR157;
wire VAR50, VAR40, VAR81, VAR14;
assign VAR50 = VAR157[15];
assign VAR40 = VAR157[14];
assign VAR14 = VAR157[12];
assign VAR81 = VAR157[9];
wire VAR6 = (VAR157[11]);
wire VAR6 = 1'b1;
reg [1:0] VAR111, VAR98, VAR5;
reg [1:0] VAR80, VAR51, VAR52;
always @(posedge VAR69, posedge VAR78)
if (VAR78) begin
VAR111 <= 2'b00; VAR98 <= 2'b00;
VAR5 <= 2'b00; VAR51 <= 2'b00;
VAR80 <= 2'b00; VAR52 <= 2'b00;
end
else begin
VAR111 <= { VAR111[0], VAR50 };
VAR98 <= { VAR98[0], VAR40 };
VAR5 <= { VAR5[0], VAR81 };
VAR51 <= { VAR51[0], VAR14 };
VAR80 <= { VAR80[0], VAR6 };
VAR52 <= { VAR52[0], VAR32 };
end
wire [1:0] VAR9 = {VAR157[6], VAR157[13]};
wire VAR66, VAR59;
wire [15:0] VAR117 = { 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
VAR59, 1'b1, VAR66, 1'b0,
1'b1, VAR80[1], 1'b0, 1'b0};
wire [15:0] VAR117 = { 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
VAR59, 1'b1, VAR66, 1'b0,
1'b1, VAR80[1], 1'b0, 1'b0};
wire [15:0] VAR136 = { VAR12[15:8], VAR12[23:16]};
wire [15:0] VAR127 = { VAR108, VAR12[7:0] };
reg [15:0] VAR141;
wire [15:0] VAR64;
assign VAR64 = VAR141;
wire [15:0] VAR73;
wire [15:0] VAR33 = VAR73;
wire [15:0] VAR153;
wire VAR100, VAR16;
assign VAR153 = { 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
VAR100, 1'b0, VAR16,1'b0};
reg [15:0] VAR148;
wire[15:0] VAR24;
assign VAR24 = VAR148;
wire [15:0] VAR42;
wire [15:0] VAR124;
assign VAR42 = VAR124;
wire [4:0] VAR156, VAR4;
wire [3:0] VAR135, VAR8;
wire [15:0] VAR115 = { 1'b1, 1'b1,
VAR8,
VAR156,
VAR4};
assign VAR23 = (VAR35 == VAR129) ? VAR157 :
(VAR35 == VAR169) ? VAR117 :
(VAR35 == VAR162) ? VAR136 :
(VAR35 == VAR95) ? VAR127 :
(VAR35 == VAR93) ? VAR141 :
(VAR35 == VAR119) ? VAR33 :
(VAR35 == VAR130) ? VAR153 :
(VAR35 == VAR46) ? VAR148 :
(VAR35 == VAR77) ? VAR42 :
(VAR35 == VAR137) ? VAR115 : 5'b00000;
always @(posedge VAR86 or posedge VAR132)
if (VAR132)
begin
VAR157 <= VAR131;
VAR141 <= VAR90;
VAR148 <= VAR7;
end
else
if (VAR10)
begin
case (VAR35)
endcase
end
else
begin
if (VAR157[9]) VAR157[9] <= 1'b0;
end
else if (VAR157[15]) VAR157[15] <= 1'b0;
end
wire [2:0] VAR26;
wire VAR97;
wire VAR99, VAR1;
always @(posedge VAR69, posedge VAR78)
if (VAR78)
VAR146 <= 1'b0;
else
if ((~VAR53 & VAR99) | VAR1) begin VAR146 <= 1'b1; end
else if ((VAR53 | ~VAR99) & ~VAR1) begin VAR146 <= 1'b0; end
reg [9:0] VAR3, VAR28, VAR144, VAR11;
always @(posedge VAR69, posedge VAR78)
begin
VAR3 <= (VAR78) ? 0 : VAR163;
VAR28 <= (VAR78) ? 0 : VAR3;
VAR144 <= (VAR78) ? 0 : VAR28;
VAR11 <= (VAR78) ? 0 : VAR144;
end
wire VAR140, VAR19, VAR152;
wire [7:0] VAR25;
VAR22 VAR63(
.VAR47(VAR69),
.reset(VAR78),
.VAR121(VAR3),
.VAR56(VAR140),
.VAR110(VAR25),
.VAR43(VAR19),
.VAR67(VAR103),
.VAR150(VAR152)
);
wire [4:0] VAR161;
wire [2:0] VAR91;
assign {VAR91, VAR161} = VAR25;
wire VAR142, VAR60;
wire [7:0] VAR49;
wire [4:0] VAR133 = VAR49[4:0];
wire [2:0] VAR112 = VAR49[7:5];
VAR125 VAR15(
.VAR94(VAR69), .reset(VAR78),
.VAR32(VAR52[1]),
.VAR120(VAR25),
.VAR170(VAR140),
.VAR166(VAR49),
.VAR116(VAR142),
.VAR59(VAR59),
.VAR106(VAR60),
.VAR19(VAR19),
.VAR152(VAR152),
.VAR101(VAR98[1]),
.VAR135(VAR135)
);
wire [5:0] VAR145; wire [3:0] VAR159;
wire VAR165, VAR62, VAR149;
wire VAR122, VAR82, VAR143;
assign VAR145[5:0] = VAR11[9:4];
assign VAR159[3:0] = VAR11[3:0];
assign VAR165 = ((VAR145 == 6'b110000) & ((VAR159 == 4'b0101) | (VAR159 == 4'b0100) | (VAR159 == 4'b0111) | (VAR159 == 4'b0001) | (VAR159==4'b1101)));
assign VAR62 = ((VAR159 == 4'b0101) & ((VAR145==6'b110001) |(VAR145==6'b110010) | (VAR145==6'b110100) | (VAR145==6'b111000) | (VAR145==6'b100000) | (VAR145==6'b010000)));
assign VAR149 = VAR165 | VAR62;
assign VAR122 = ((VAR145 == 6'b001111) & ((VAR159==4'b1010)|(VAR159==4'b1011)|(VAR159==4'b1000)|(VAR159==4'b1110)|(VAR159==4'b0010)));
assign VAR82 = ((VAR159 == 4'b1010) & ((VAR145==6'b001110)|(VAR145==6'b001101)|(VAR145==6'b001011)|(VAR145==6'b000111)|(VAR145==6'b011111)|(VAR145==6'b101111)));
assign VAR143 = VAR122 | VAR82;
assign VAR97 = VAR60 & ~VAR149 & ~VAR143;
wire [2:0] VAR158;
wire [17:0] VAR29;
wire VAR126;
assign VAR61 = { 13'b0, VAR126, VAR29 };
VAR87
.VAR21(VAR21)
)
VAR154(
.VAR94(VAR69),.reset(VAR78),
.VAR32(VAR52[1]),
.VAR26(VAR26),
.VAR13(VAR68),
.VAR58(VAR36),
.VAR138(VAR84),
.VAR158(VAR158),
.VAR45(VAR45),
.VAR79(VAR79),
.VAR113(VAR113),
.VAR48(VAR48),
.VAR59(VAR59),
.VAR50(VAR111[1]),
.VAR40(VAR98[1]),
.VAR81(VAR5[1]),
.VAR14(VAR51[1]),
.VAR66(VAR66),
.VAR64(VAR64),
.VAR73(VAR73),
.VAR100(VAR100),
.VAR16(VAR16),
.VAR24(VAR24),
.VAR124(VAR124),
.VAR8(VAR8),
.VAR29(VAR29),
.VAR126(VAR126)
);
wire VAR75, VAR134;
VAR44 VAR88(
.VAR94(VAR69), .reset(VAR78),
.VAR120(VAR49),
.VAR170(VAR142),
.VAR106(VAR60),
.VAR97(VAR97),
.VAR59(VAR59),
.VAR31(VAR31),
.VAR107(VAR107),
.VAR70(VAR70),
.VAR128(VAR128),
.VAR26(VAR26),
.VAR50(VAR111[1]),
.VAR13(VAR68),
.VAR58(VAR36),
.VAR158(VAR158),
.VAR45(VAR45),
.VAR79(VAR79),
.VAR113(VAR113),
.VAR48(VAR48),
.VAR1(VAR1),
.VAR156(VAR156)
);
reg [1:0] VAR96, VAR55, VAR30, VAR83;
always @(posedge VAR39, posedge VAR118)
if (VAR118) begin
VAR96 <= 2'b00; VAR55 <= 2'b00;
VAR30 <= 2'b00; VAR83 <= 2'b00;
end
else
begin
VAR96 <= { VAR96[0], VAR50 };
VAR55 <= { VAR55[0], VAR1 };
VAR30 <= { VAR30[0], 1'b1 };
VAR83 <= { VAR83[0], VAR32 };
end
reg [2:0] VAR160, VAR164;
always @(posedge VAR39, posedge VAR118)
begin
VAR160 <= (VAR118) ? VAR65 : VAR164;
VAR164 <= (VAR118) ? VAR65 : VAR26;
end
VAR123 VAR171(
.VAR94(VAR39),
.reset(VAR118),
.VAR37(VAR37),
.VAR75(VAR75),
.VAR17(VAR41),
.VAR54(VAR102),
.VAR139(VAR71),
.VAR18(VAR18),
.VAR1(VAR55[1]),
.VAR99(VAR99),
.VAR26(VAR160),
.VAR138(VAR84),
.VAR50(VAR96[1]),
.VAR4(VAR4)
);
reg [23:0] VAR38;
reg VAR27;
reg VAR34;
always @(posedge VAR39, posedge VAR118)
if (VAR118)
begin
VAR38 <= 0; VAR34 <= 0; VAR27 <= 1;
end
else
begin
VAR38 <= VAR38 + 1;
if (VAR34)
begin
if (~VAR38[23]) begin VAR27 <= 0;VAR34 <= 0; end
end
else if (VAR38[23] & VAR27) VAR34 <= 1;
end
else if (VAR75) VAR27 <= 1;
end
reg [23:0] VAR168;
reg VAR114;
reg VAR151;
always @(posedge VAR69, posedge VAR78)
if (VAR78)
begin
VAR168 <= 0; VAR151 <= 0; VAR114 <= 1;
end
else
begin
VAR168 <= VAR168 + 1;
if (VAR151)
begin
if (~VAR168[23]) begin VAR114 <= 0;VAR151 <= 0; end
end
else if (VAR168[23] & VAR114) VAR151 <= 1;
end
else if (VAR31) VAR114 <= 1;
end
wire VAR74 = VAR151 | VAR34;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/and4b/sky130_fd_sc_hd__and4b.pp.blackbox.v
| 1,341 |
module MODULE1 (
VAR3 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR1,
VAR9,
VAR4 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR9;
input VAR4 ;
input VAR2 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.v
| 2,218 |
module MODULE2 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR8,
VAR7
);
input VAR9 ;
input VAR1 ;
output VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR7;
VAR2 VAR4 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR9,
VAR1 ,
VAR5 ,
VAR3,
VAR6
);
input VAR9;
input VAR1 ;
output VAR5 ;
input VAR3;
input VAR6;
supply1 VAR8;
supply0 VAR7;
VAR2 VAR4 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a21bo/sky130_fd_sc_ls__a21bo_1.v
| 2,318 |
module MODULE1 (
VAR9 ,
VAR5 ,
VAR1 ,
VAR7,
VAR6,
VAR8,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR7;
input VAR6;
input VAR8;
input VAR4 ;
input VAR3 ;
VAR2 VAR10 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9 ,
VAR5 ,
VAR1 ,
VAR7
);
output VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR7;
supply1 VAR6;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR3 ;
VAR2 VAR10 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_gtx_es_wr.v
| 9,605 |
module MODULE1 (
VAR47,
VAR15,
VAR14,
VAR37,
VAR52,
VAR35,
VAR36,
VAR40,
VAR6,
VAR11,
VAR32,
VAR12,
VAR4,
VAR50,
VAR23,
VAR3,
VAR5,
VAR53,
VAR43,
VAR26,
VAR25,
VAR39,
VAR17);
input VAR47;
input VAR15;
input [31:0] VAR14;
input [15:0] VAR37;
input [15:0] VAR52;
input [15:0] VAR35;
input VAR36;
input VAR40;
input VAR6;
input [31:0] VAR11;
output VAR32;
input VAR12;
output [31: 0] VAR4;
output [31: 0] VAR50;
input VAR23;
input VAR3;
input VAR5;
output VAR53;
output VAR43;
output VAR26;
output [ 1:0] VAR25;
output [83:0] VAR39;
output [ 7:0] VAR17;
reg [ 5:0] VAR22 = 'd0;
reg VAR45 = 'd0;
reg VAR51 = 'd0;
reg VAR53 = 'd0;
reg VAR43 = 'd0;
reg [ 5:0] VAR30 = 'd0;
reg VAR31 = 'd0;
reg VAR13 = 'd0;
reg [31:0] VAR21 = 'd0;
reg VAR26 = 'd0;
reg [15:0] VAR7 = 'd0;
reg [31:0] VAR38 = 'd0;
reg [15:0] VAR1 = 'd0;
reg [15:0] VAR18 = 'd0;
reg [15:0] VAR20 = 'd0;
reg VAR32 = 'd0;
reg [31:0] VAR4 = 'd0;
reg [31:0] VAR50 = 'd0;
reg [ 1:0] VAR25 = 'd0;
reg VAR29 = 'd0;
reg [ 5:0] VAR9 = 'd0;
reg [31:0] VAR33 = 'd0;
wire [ 6:0] VAR16;
wire [31:0] VAR28;
wire VAR44;
wire [31:0] VAR49;
assign VAR17[7] = VAR43;
assign VAR17[6] = VAR53;
assign VAR17[5] = VAR26;
assign VAR17[4] = VAR13;
assign VAR17[3] = VAR32;
assign VAR17[2] = VAR12;
assign VAR17[1] = VAR23;
assign VAR17[0] = VAR3;
assign VAR39[ 83: 83] = VAR36;
assign VAR39[ 82: 82] = VAR40;
assign VAR39[ 81: 81] = VAR6;
assign VAR39[ 80: 80] = VAR32;
assign VAR39[ 79: 79] = VAR12;
assign VAR39[ 78: 78] = VAR23;
assign VAR39[ 77: 77] = VAR3;
assign VAR39[ 76: 76] = VAR5;
assign VAR39[ 75: 70] = VAR22;
assign VAR39[ 69: 69] = VAR45;
assign VAR39[ 68: 68] = VAR51;
assign VAR39[ 67: 67] = VAR53;
assign VAR39[ 66: 66] = VAR43;
assign VAR39[ 65: 60] = VAR30;
assign VAR39[ 59: 59] = VAR31;
assign VAR39[ 58: 58] = VAR13;
assign VAR39[ 57: 57] = VAR26;
assign VAR39[ 56: 41] = VAR7;
assign VAR39[ 40: 9] = VAR38;
assign VAR39[ 8: 7] = VAR25;
assign VAR39[ 6: 6] = VAR29;
assign VAR39[ 5: 0] = VAR9;
assign VAR16 = {1'b1, VAR9} - VAR30;
assign VAR28 = VAR38 + {VAR7, 2'd0};
always @(negedge VAR47 or posedge VAR15) begin
if (VAR47 == 1'b0) begin
VAR22 <= 'd0;
VAR45 <= 'd0;
VAR51 <= 'd0;
VAR53 <= 'd0;
VAR43 <= 'd0;
end else begin
VAR22 <= VAR16[5:0];
VAR45 <= (VAR22 > 60) ? 1'b1 : 1'b0;
VAR51 <= (VAR22 < 3) ? 1'b1 : 1'b0;
VAR53 <= (VAR22 < 3) ? VAR45 : 1'b0;
VAR43 <= (VAR22 > 60) ? VAR51 : 1'b0;
end
end
assign VAR44 = (VAR9 == VAR30) ? 1'b0 : ~VAR26;
always @(negedge VAR47 or posedge VAR15) begin
if (VAR47 == 1'b0) begin
VAR30 <= 'd0;
VAR31 <= 'd0;
VAR13 <= 'd0;
VAR21 <= 'd0;
end else begin
if (VAR44 == 1'b1) begin
VAR30 <= VAR30 + 1'b1;
end
VAR31 <= VAR44;
VAR13 <= VAR31;
VAR21 <= VAR49;
end
end
always @(negedge VAR47 or posedge VAR15) begin
if (VAR47 == 1'b0) begin
VAR26 <= 'd0;
VAR7 <= 'd0;
VAR38 <= 'd0;
VAR1 <= 'd0;
VAR18 <= 'd0;
VAR20 <= 'd0;
end else begin
if (VAR23 == 1'b1) begin
VAR26 <= 1'b0;
end else if (VAR44 == 1'b1) begin
VAR26 <= 1'b1;
end
if (VAR23 == 1'b1) begin
if (VAR7 >= VAR18) begin
VAR7 <= VAR1;
end else begin
VAR7 <= VAR7 + 1'b1;
end
end else if (VAR40 == 1'b1) begin
VAR7 <= VAR52;
end
if ((VAR23 == 1'b1) && (VAR7 >= VAR18)) begin
VAR38 <= VAR38 + {VAR20, 2'd0};
end else if (VAR40 == 1'b1) begin
VAR38 <= VAR14;
end
if ((VAR40 == 1'b1) || (VAR6 == 1'b1)) begin
VAR1 <= VAR52;
VAR18 <= VAR35;
VAR20 <= VAR37;
end
end
end
always @(negedge VAR47 or posedge VAR15) begin
if (VAR47 == 1'b0) begin
VAR32 <= 'd0;
VAR4 <= 'd0;
VAR50 <= 'd0;
VAR25 <= 'd0;
end else begin
if (VAR12 == 1'b1) begin
VAR32 <= 1'b0;
end else if (VAR13 == 1'b1) begin
VAR32 <= 1'b1;
end
if (VAR13 == 1'b1) begin
VAR4 <= VAR28;
VAR50 <= VAR21;
end
if (VAR23 == 1'b1) begin
VAR25 <= {VAR3, ~VAR5};
end else if (VAR13 == 1'b1) begin
VAR25 <= 2'd0;
end
end
end
always @(negedge VAR47 or posedge VAR15) begin
if (VAR47 == 1'b0) begin
VAR29 <= 'd0;
VAR9 <= 'd0;
VAR33 <= 'd0;
end else begin
VAR29 <= VAR36;
if (VAR29 == 1'b1) begin
VAR9 <= VAR9 + 1'b1;
end
VAR33 <= VAR11;
end
end
VAR27 #(.VAR2(32), .VAR24(6)) VAR10 (
.VAR46 (VAR15),
.VAR34 (VAR29),
.VAR19 (VAR9),
.VAR8 (VAR33),
.VAR42 (VAR15),
.VAR48 (VAR30),
.VAR41 (VAR49));
endmodule
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.behavioral.pp.v
| 1,311 |
module MODULE1( VAR6, VAR4, VAR3, VAR9, VAR2, VAR7 );
input VAR6, VAR4, VAR3;
inout VAR2, VAR7;
output VAR9;
VAR1 VAR8(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9),.VAR2(VAR2),.VAR7(VAR7));
VAR1 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9),.VAR2(VAR2),.VAR7(VAR7));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.blackbox.v
| 1,291 |
module MODULE1 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR1;
endmodule
|
apache-2.0
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/vfabric_fptosi.v
| 2,402 |
module MODULE1(VAR5, VAR14,
VAR8, VAR23, VAR12,
VAR1, VAR16, VAR19);
parameter VAR21 = 32;
parameter VAR18 = 3;
parameter VAR11 = 64;
input VAR5, VAR14;
input [VAR21-1:0] VAR8;
input VAR23;
output VAR12;
output [VAR21-1:0] VAR1;
input VAR16;
output VAR19;
reg [VAR18-1:0] VAR28;
wire [VAR21-1:0] VAR26;
wire VAR9;
wire VAR20;
wire VAR3;
VAR15 VAR2 ( .VAR5(VAR5), .VAR14(VAR14),
.VAR27(VAR8), .VAR25(VAR26), .VAR22(VAR23),
.VAR4( VAR9 ), .VAR29(VAR3), .VAR10(VAR12) );
VAR24 VAR6( .VAR5(VAR5), .enable(~VAR20),
.VAR14(VAR14), .VAR13(VAR26), .VAR7(VAR1));
always @(posedge VAR5 or negedge VAR14)
begin
if (~VAR14)
begin
VAR28 <= {VAR18{1'b0}};
end
else
begin
if(~VAR20)
VAR28 <= { VAR9, VAR28[VAR18-1:1] };
end
end
assign VAR20 = (VAR28[0] & VAR16);
assign VAR3 = (VAR28[0] & VAR16) | ~VAR9;
assign VAR19 = VAR28[0];
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/nor2b/sky130_fd_sc_hs__nor2b.pp.blackbox.v
| 1,269 |
module MODULE1 (
VAR3 ,
VAR4 ,
VAR5 ,
VAR2,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR1;
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/crt_sp/crt.v
| 16,631 |
module MODULE1
(
input [1:0] VAR7,
input VAR73,
input VAR91,
input VAR187,
input VAR172,
input VAR45,
input VAR98,
input VAR33,
input [3:0] VAR166,
input [31:0] VAR117,
input [7:2] VAR142,
input VAR120,
input [7:0] VAR28,
input VAR66, input [20:0] VAR188, input [31:0] VAR97,
input [39:0] VAR149,
input VAR74,
input VAR26,
input VAR110,
input [127:0] VAR131,
input VAR104,
input VAR198,
input VAR93,
input VAR121,
input [3:0] VAR31,
output [31:0] VAR193,
output [1:0] VAR173, output reg VAR139, output [15:4] VAR12,
output reg [24:4] VAR50,
output VAR180,
output [9:0] VAR128,
output [11:0] VAR135,
output [4:0] VAR5 ,
output VAR178,VAR18, VAR71,
output [23:0] VAR174, output VAR83, output [1:0] VAR124,
output [13:0] VAR161
);
parameter VAR62 = 4'b0000;
parameter VAR183 = 14'hA0,
VAR81 = 14'h140,
VAR138 = 14'h280,
VAR147 = 14'hC8,
VAR195 = 14'h190,
VAR9 = 14'h320,
VAR75 = 14'h100,
VAR6 = 14'h200,
VAR136 = 14'h400,
VAR170 = 14'h120,
VAR21 = 14'h240,
VAR94 = 14'h480,
VAR143 = 14'h140,
VAR197 = 14'h280,
VAR46 = 14'h500,
VAR122 = 14'h190,
VAR190 = 14'h320,
VAR25 = 14'h640;
wire [9:0] VAR141 = VAR149[39:30];
wire [9:0] VAR150 = VAR149[29:20];
wire [9:0] VAR82 = VAR149[19:10];
wire [9:0] VAR194 = VAR149[9:0];
reg [24:4] VAR38;
wire VAR23,
VAR154,
VAR153;
wire VAR167;
wire [11:0] VAR17;
wire VAR70;
wire [9:0] VAR119, VAR16;
wire [13:0]
VAR84,
VAR36,
VAR52;
wire [11:0] VAR186;
wire [11:0] VAR49,
VAR116,
VAR134,
VAR123;
wire [7:0] VAR53;
wire [3:0] VAR57;
wire [13:0] VAR68,
VAR159,
VAR168,
VAR189,
VAR145,
VAR101,
VAR158,
VAR63;
wire [11:0] VAR125,
VAR179,
VAR176;
wire [9:0] VAR130;
wire [24:4] VAR99;
wire [24:4] VAR35;
wire VAR56;
wire VAR113;
wire VAR95;
reg VAR105,
VAR152,
VAR112,
VAR157,
VAR169,
VAR192,
VAR76;
wire VAR55;
wire [11:0] VAR181;
reg [11:0] VAR11; reg VAR129,
VAR108,
VAR78;
wire [127:0] VAR43,
VAR148;
wire [31:0] VAR1;
wire [127:0] VAR37; wire [9:0] VAR111;
wire VAR61;
wire VAR64;
wire VAR10;
wire VAR102;
wire VAR51;
wire VAR8;
wire VAR69;
wire VAR39;
wire VAR106;
wire VAR58;
wire VAR47;
wire VAR34;
wire VAR177;
wire VAR30;
wire VAR171;
wire VAR20;
assign VAR178 = (VAR120) ? VAR104 : VAR23;
assign VAR18 = (VAR120) ? VAR198 : VAR154;
assign VAR71 = (VAR120) ? VAR93 : VAR153;
wire VAR72 = (VAR121 | (VAR31 == VAR62)) ?
VAR33 : 1'b1;
assign VAR193 = (~VAR72) ? VAR1 :
VAR97;
always @(posedge VAR187 or negedge VAR45)
if (!VAR45) begin
VAR112 <= 1'b0;
VAR105 <= 1'b0;
VAR152 <= 1'b0;
end else if (VAR91) begin
VAR105 <= VAR95;
VAR152 <= VAR105;
if(VAR56 & VAR152) begin
VAR38[24:4] <= VAR99[24:4];
VAR112 <= ~VAR112;
end
end
always @(posedge VAR172 or negedge VAR45)
if (!VAR45) begin
VAR192 <= 1'b0;
VAR169 <= 1'b0;
VAR157 <= 1'b0;
VAR139 <= 1'b0;
VAR76 <= 1'b0;
end else begin
VAR192 <= VAR169 ^ VAR157;
VAR169 <= VAR157;
VAR157 <= VAR112;
VAR139 <= VAR76;
VAR76 <= VAR167;
end
always @*
casex({VAR113,VAR17[0]})
2'VAR132: VAR50[24:4]=VAR38[24:4];
2'b10: VAR50[24:4]=VAR99[24:4];
2'b11: VAR50[24:4]=VAR35[24:4];
endcase
assign VAR135 = (VAR113)? {1'b0, VAR17[11:1]}: VAR17[11:0];
always @(posedge VAR187 or negedge VAR45)
if (!VAR45)
VAR129 <= 1'b0;
end
else if (~VAR55 && VAR91)
VAR129 <= ~VAR129;
always @(posedge VAR172 or negedge VAR45) begin
if (!VAR45) begin
VAR11 <= 12'b0;
VAR108 <= 1'b0;
VAR78 <= 1'b0;
end else begin
if (VAR108 ^ VAR78) VAR11 <= VAR181;
VAR108 <= VAR78;
VAR78 <= VAR129;
end
end
VAR164 VAR48
(
.VAR172 (VAR172),
.VAR27 (VAR45),
.VAR54 (VAR98),
.VAR86 (VAR72),
.VAR87 (VAR166),
.VAR117 (VAR117),
.VAR142 (VAR142),
.VAR196 (VAR192),
.VAR109 (VAR139),
.VAR181 (VAR11),
.VAR66 (VAR66),
.VAR188 (VAR188),
.VAR4 (VAR1),
.VAR144 (VAR53),
.VAR126 (VAR186),
.VAR140 (VAR161),
.VAR200 (VAR84),
.VAR184 (VAR36),
.VAR24 (VAR52),
.VAR199 (VAR49),
.VAR89 (VAR116),
.VAR13 (VAR134),
.VAR14 (VAR123),
.VAR41 (VAR57),
.VAR160 (VAR12[15:4]),
.VAR156 (VAR99[24:4]),
.VAR185 (VAR35[24:4]),
.VAR22 (VAR61),
.VAR2 (VAR64),
.VAR155 (VAR10),
.VAR19 (VAR102),
.VAR96 (VAR124),
.VAR107 (VAR51),
.VAR151 (VAR8),
.VAR80 (VAR69),
.VAR88 (VAR39),
.VAR83 (VAR83),
.VAR95 (VAR95),
.VAR182 (VAR130),
.VAR113 (VAR113)
);
VAR127 VAR92
(
.VAR27 (VAR45),
.VAR120 (VAR120),
.VAR3 (VAR187),
.VAR91 (VAR91),
.VAR102 (VAR102),
.VAR84 (VAR84),
.VAR36 (VAR36),
.VAR116 (VAR116),
.VAR134 (VAR134),
.VAR61 (VAR61),
.VAR64 (VAR64),
.VAR10 (VAR10),
.VAR124(VAR124),
.VAR51(VAR51),
.VAR59(VAR39),
.VAR53 (VAR53),
.VAR186 (VAR186),
.VAR68 (VAR68),
.VAR159 (VAR159),
.VAR168 (VAR168),
.VAR189 (VAR189),
.VAR145 (VAR145),
.VAR101(VAR101),
.VAR158 (VAR158),
.VAR63 (VAR63),
.VAR125 (VAR125),
.VAR179 (VAR179),
.VAR176 (VAR176),
.VAR106 (VAR106),
.VAR58 (VAR58),
.VAR100 (VAR154),
.VAR79 (VAR153),
.VAR103 (VAR23),
.VAR115 (VAR47),
.VAR40 (VAR34),
.VAR89 (VAR167),
.VAR32 (VAR177),
.VAR42 (VAR30),
.VAR65 (VAR70),
.VAR67 (VAR173), .VAR56 (VAR56),
.VAR55 (VAR55),
.VAR181 (VAR181)
);
VAR60 VAR114
(
.VAR161 (VAR161),
.VAR84 (VAR84),
.VAR36 (VAR36),
.VAR52 (VAR52),
.VAR49 (VAR49),
.VAR116 (VAR116),
.VAR134 (VAR134),
.VAR123 (VAR123),
.VAR68 (VAR68),
.VAR159 (VAR159),
.VAR168 (VAR168),
.VAR189 (VAR189),
.VAR145 (VAR145),
.VAR101(VAR101),
.VAR158 (VAR158),
.VAR63 (VAR63),
.VAR125 (VAR125),
.VAR179 (VAR179),
.VAR176 (VAR176),
.VAR106 (VAR106)
);
VAR118 VAR175
(
.VAR58 (VAR58),
.VAR27 (VAR45),
.VAR187 (VAR187),
.VAR91 (VAR91),
.VAR110 (VAR110),
.VAR65 (VAR70),
.VAR39(VAR39),
.VAR57 (VAR57),
.VAR49 (VAR49),
.VAR130 (VAR130),
.VAR74 (VAR74),
.VAR111 (VAR111),
.VAR141 (VAR141),
.VAR150 (VAR150),
.VAR82 (VAR82),
.VAR194 (VAR194),
.VAR7 (VAR7),
.VAR73 (VAR73),
.VAR8 (VAR8),
.VAR69(VAR8),
.VAR119 (VAR119),
.VAR16 (VAR16),
.VAR171 (VAR171),
.VAR180 (VAR180),
.VAR17 (VAR17),
.VAR128 (VAR128),
.VAR5 (VAR5)
);
VAR77 VAR163
(
.VAR187 (VAR187),
.VAR58 (VAR58),
.VAR27 (VAR45),
.VAR65 (VAR70),
.VAR42 (VAR30),
.VAR171 (VAR171),
.VAR119 (VAR119),
.VAR16 (VAR16),
.VAR150 (11'h0), .VAR194 (11'h0), .VAR7 (VAR7),
.VAR37 (VAR37),
.VAR28 (VAR28),
.VAR120 (VAR120),
.VAR20 (VAR20),
.VAR174 (VAR174)
);
VAR90 VAR133
(
.VAR162 (VAR131),
.VAR146 (VAR26),
.VAR44 (VAR20),
.VAR191 (VAR187),
.VAR15 (VAR110),
.VAR85 (~(VAR70 & VAR58)),
.VAR165 (VAR37),
.VAR111 (VAR111),
.VAR29 (),
.VAR137 ()
);
endmodule
|
gpl-3.0
|
HarmonInstruments/hififo
|
hdl/hififo_fpc_fifo.v
| 3,811 |
module MODULE1
(
input VAR2,
input reset,
output [31:0] VAR16,
output interrupt,
input [1:0] VAR43,
input [63:0] VAR13,
input [7:0] VAR23,
input [5:0] VAR15,
input VAR34,
input VAR25,
output reg VAR24, output [63:0] VAR21,
input VAR54,
output [2:0] VAR26,
input VAR44, input VAR35,
output [63:0] VAR42,
output VAR3
);
reg [1:0] VAR11 = 0;
reg [7:0] VAR59 = 0;
reg [8:0] VAR45;
reg [2:0] VAR22 = 0; reg [2:0] VAR49 = 0; reg VAR53, VAR29;
wire [63:0] VAR12;
wire VAR41;
wire VAR37;
wire VAR19 = VAR25;
wire VAR46 = (VAR23[5:3] == VAR43) && VAR34;
wire VAR28 = VAR34
&& (VAR23[5:3] == VAR43) && (VAR15 == 6'h3F);
wire [2:0] VAR36 = VAR49 - VAR45[8:6];
wire VAR58 = 0;
assign VAR26 = VAR49[2:0];
always @ (posedge VAR2)
begin
VAR11 <= reset ? 1'b0 :
VAR54 ? 2'd3 :
VAR11 - (VAR11 != 0);
VAR45 <= reset ? 1'b0 :
VAR45 + ((VAR45[8:6] != VAR22[2:0]) && VAR41);
VAR22 <= reset ? 1'b0 :
VAR22 + (VAR59[VAR22[2:0]]);
VAR49 <= reset ? 1'b0 :
VAR49 + (VAR54 && VAR24);
VAR53 <= ((VAR45[8:6] != VAR22[2:0]) && VAR41);
VAR29 <= VAR53;
VAR24 <= VAR37 && (VAR36 < 6) && (VAR11 == 0);
end
genvar VAR31;
generate
for (VAR31 = 0; VAR31 < 8; VAR31 = VAR31+1) begin: VAR9
always @(posedge VAR2) begin
if(reset)
VAR59[VAR31] <= 1'b0;
end
else if(VAR28 && (VAR23[2:0] == VAR31))
VAR59[VAR31] <= 1'b1;
end
else if(VAR22[2:0] == VAR31)
VAR59[VAR31] <= 1'b0;
end
end
endgenerate
VAR27 #(.VAR51(64), .VAR38(9)) VAR39
(.VAR2(VAR2),
.VAR4(VAR13),
.VAR40(VAR46),
.VAR50({VAR23[2:0],VAR15}),
.VAR52(VAR12),
.VAR33(VAR45)
);
VAR7 #(.VAR48(64)) VAR14
(
.reset(reset),
.VAR5(VAR2),
.VAR30(VAR12),
.VAR32(VAR29),
.VAR55(VAR41),
.VAR10(VAR44),
.VAR56(VAR35),
.VAR47(VAR42),
.VAR8(VAR3),
.VAR6()
);
VAR1 #(.VAR17(9)) VAR18
(
.VAR2(VAR2),
.reset(reset),
.VAR20(VAR21),
.VAR57(VAR54),
.VAR37(VAR37),
.VAR40(VAR19),
.VAR4(VAR13),
.VAR16(VAR16),
.interrupt(interrupt)
);
endmodule
|
gpl-3.0
|
The7thPres/CFTP
|
CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/SD/SD_Control.v
| 10,324 |
module MODULE1(
input VAR51, input VAR52, input [7:0] VAR16,
output reg VAR36, output VAR38, output reg [7:0] VAR40,
output VAR20,
input VAR25,
output reg [4:0] VAR45,
input VAR12,
input VAR47,
output VAR43,
input [29:0] VAR31,
input [4095:0] VAR34,
output reg [4095:0] VAR35);
wire [2:0] VAR4;
wire [8:0] VAR44;
reg [4:0] VAR42;
wire VAR5, VAR26, VAR24;
parameter VAR37 = 5'b00000;
parameter VAR23 = 5'b00001;
parameter VAR30 = 5'b00010;
parameter VAR54 = 5'b00011;
parameter VAR27 = 5'b00100;
parameter VAR8 = 5'b00101;
parameter VAR13 = 5'b00110;
parameter VAR15 = 5'b00111;
parameter VAR50 = 5'b01000;
parameter VAR10 = 5'b01001;
parameter VAR18 = 5'b01010;
parameter VAR17 = 5'b01011;
parameter VAR41 = 5'b01100;
parameter VAR3 = 5'b01101;
parameter VAR1 = 5'b01110;
parameter VAR46 = 5'b01111;
parameter VAR6 = 5'b10000;
parameter VAR39 = 5'b10001;
parameter VAR11 = 5'b10010;
parameter VAR2 = 5'b10011;
parameter VAR53 = 5'b10100;
parameter VAR29 = 5'b10101;
parameter VAR48 = 5'b10110;
parameter VAR9 = 5'b10111;
VAR28 VAR35 = 4095'd0;
VAR32 #(.VAR49(3)) VAR7(
.VAR21 (VAR51),
.VAR33 (VAR26),
.VAR19 (VAR5),
.VAR22 (VAR4));
VAR32 #(.VAR49(9)) VAR14(
.VAR21 (VAR51),
.VAR33 (VAR24),
.VAR19 (VAR5),
.VAR22 (VAR44));
assign VAR43 = (VAR45 == VAR46 || VAR45 == VAR9);
assign VAR20 = (VAR45 == VAR37);
assign VAR38 = ~(VAR45 == VAR37 || VAR45 == VAR23 || VAR45 == VAR30
|| VAR45 == VAR54 || VAR45 == VAR27 || VAR45 == VAR8
|| VAR45 == VAR13 || VAR45 == VAR15 || VAR45 == VAR50);
assign VAR26 = ~((VAR45 == VAR10) && (VAR16[0] == 1'b0)); assign VAR24 = ((VAR4==3'd7)&&~(VAR45 == VAR10 && VAR44 == 9'd1))||(VAR45 == VAR53); assign VAR5 = (VAR52) || ((VAR45 == VAR37) && (VAR44 == 9'd9) && (VAR4 == 3'd2)) ||
((VAR45 == VAR30) && (~VAR16[7])) ||
((VAR45 == VAR8) && (~VAR16[7])) ||
((VAR45 == VAR50) && (~VAR16[7])) ||
((VAR45 == VAR54) && (VAR44 == 9'd1)) ||
((VAR45 == VAR13) && (VAR44 == 9'd1)) ||
((VAR45 == VAR10) && (VAR44 == 9'd1) && ((~VAR47)||(~VAR12))) ||
((VAR45 == VAR41) && (~VAR16[0])) ||
((VAR45 == VAR39) && (~VAR16[7])) ||
(VAR45 == VAR2);
always @ (posedge VAR51)
begin
VAR36 = ((VAR45 == VAR23)||(VAR45 == VAR27)||(VAR45 == VAR15)||
(VAR45 == VAR18)||(VAR45 == VAR6)||(VAR45 == VAR2)||
(VAR45 == VAR53)||(VAR45 == VAR29));
case (VAR45)
VAR23:
case (VAR4)
3'd0 : VAR40 = 8'h40;
3'd5 : VAR40 = 8'h95;
default : VAR40 = 8'h00;
endcase
VAR27:
case (VAR4)
3'd0 : VAR40 = 8'h77;
default : VAR40 = 8'h00;
endcase
VAR15:
case (VAR4)
3'd0 : VAR40 = 8'h69;
default : VAR40 = 8'h00;
endcase
VAR18:
case (VAR4)
3'd0 : VAR40 = 8'h51;
3'd1 : VAR40 = VAR31[29:22];
3'd2 : VAR40 = VAR31[21:14];
3'd3 : VAR40 = VAR31[13:6];
3'd4 : VAR40 = {VAR31[5:0],2'b0};
default : VAR40 = 8'h00;
endcase
VAR6:
case (VAR4)
3'd0 : VAR40 = 8'h58;
3'd1 : VAR40 = VAR31[29:22];
3'd2 : VAR40 = VAR31[21:14];
3'd3 : VAR40 = VAR31[13:6];
3'd4 : VAR40 = {VAR31[5:0],2'b0};
default : VAR40 = 8'h00;
endcase
VAR2:
VAR40 = 8'hfe;
VAR53:
VAR40 = VAR34[4095-(8*VAR44)-:8];
default : VAR40 = 8'hff;
endcase
if ((VAR45 == VAR3) && (VAR4 == 3'd7)) VAR35[4095-(8*VAR44)-:8] = VAR16;
end
always @ (posedge VAR51) VAR45 = (VAR52) ? VAR37 : VAR42;
always @ (*)
case (VAR45)
VAR37 : VAR42 = (VAR44 == 9'd9 && VAR4 == 3'd2) ? VAR23 : VAR37;
VAR23 : VAR42 = (VAR4 == 3'd5) ? VAR30 : VAR23;
VAR30 : VAR42 = (~VAR16[7]) ? (VAR16 == 8'h01) ? VAR54 : VAR37 : VAR30;
VAR54 : VAR42 = (VAR44 == 9'd1) ? VAR27 : VAR54;
VAR27 : VAR42 = (VAR4 == 3'd5) ? VAR8 : VAR27;
VAR8 : VAR42 = (~VAR16[7]) ? (VAR16 == 8'h01) ? VAR13 : VAR37 : VAR8;
VAR13 : VAR42 = (VAR44 == 9'd1) ? VAR15 : VAR13;
VAR15 : VAR42 = (VAR4 == 3'd5) ? VAR50 : VAR15;
VAR50 : VAR42 = (~VAR16[7]) ? (VAR16 == 8'h00) ? VAR10 : (VAR16 == 8'b01) ? VAR27 : VAR37 : VAR50;
VAR10 : VAR42 = (VAR44 == 9'd1) ? (VAR47) ? VAR6 : (VAR12) ? VAR18 : VAR10 : VAR10;
VAR18 : VAR42 = (VAR4 == 3'd5) ? VAR17 : VAR18;
VAR17 : VAR42 = (VAR44 == 9'd20) ? VAR18 : (~VAR16[7]) ? (VAR16 == 8'h00) ? VAR41 : (VAR16 == 8'h01) ? VAR37 : VAR6 : VAR17;
VAR41 : VAR42 = (~VAR16[0]) ? VAR3 : VAR41;
VAR3 : VAR42 = ((VAR44 == 9'd511) && (VAR4 == 3'd7)) ? VAR1 : VAR3;
VAR1 : VAR42 = (VAR44 == 9'd2) ? VAR46 : VAR1;
VAR46 : VAR42 = (~VAR12) ? VAR10 : VAR46;
VAR6 : VAR42 = (VAR4 == 3'd5) ? VAR39 : VAR6;
VAR39 : VAR42 = (VAR44 == 9'd20) ? VAR6 : (~VAR16[7]) ? (VAR16 == 8'h00) ? VAR11 : (VAR16 == 8'h01) ? VAR37 : VAR6 : VAR39;
VAR11 : VAR42 = (VAR44 == 9'd1) ? VAR2 : VAR11;
VAR2 : VAR42 = VAR53;
VAR53 : VAR42 = (VAR44 == 9'd511) ? VAR29 : VAR53;
VAR29 : VAR42 = (VAR44 == 9'd2) ? VAR48 : VAR29;
VAR48 : VAR42 = (VAR16[4:0]==5'b00101) ? VAR9 : (VAR16[4:0]==5'b01011 || VAR16[4:0]==5'b01101) ? VAR10 : VAR48;
VAR9 : VAR42 = (~VAR47) ? VAR10 : VAR9;
default : VAR42 = VAR37;
endcase
endmodule
|
lgpl-3.0
|
sergev/vak-opensource
|
hardware/s3esk-openrisc/or1200/or1200_lsu.v
| 7,943 |
module MODULE1(
VAR16, VAR19, VAR11, VAR43, VAR1, VAR36, VAR33,
VAR26, VAR21, VAR23, VAR6, VAR14,
VAR20, VAR3, VAR9, VAR5, VAR12, VAR10,
VAR35, VAR7, VAR13, VAR37, VAR18
);
parameter VAR8 = VAR22;
parameter VAR45 = VAR25;
input [31:0] VAR16;
input [31:0] VAR19;
input [VAR4-1:0] VAR11;
input [VAR8-1:0] VAR43;
output [VAR8-1:0] VAR1;
output VAR36;
output VAR33;
input VAR26;
output VAR21;
output VAR23;
output VAR6;
output VAR14;
output [31:0] VAR20;
output VAR3;
output VAR9;
output [3:0] VAR5;
output [3:0] VAR12;
output [31:0] VAR10;
input [31:0] VAR35;
input VAR7;
input VAR13;
input VAR37;
input [3:0] VAR18;
reg [3:0] VAR5;
assign VAR36 = VAR13 & VAR3;
assign VAR33 = VAR7;
assign VAR21 = ((VAR11 == VAR15) | (VAR11 == VAR2) | (VAR11 == VAR28)) & VAR20[0]
| ((VAR11 == VAR32) | (VAR11 == VAR27) | (VAR11 == VAR17)) & |VAR20[1:0];
assign VAR23 = VAR37 & (VAR18 == VAR40);
assign VAR6 = VAR37 & (VAR18 == VAR29);
assign VAR14 = VAR37 & (VAR18 == VAR44);
assign VAR20 = VAR16 + VAR19;
assign VAR3 = VAR26 | VAR33 | VAR21 ? 1'b0 : |VAR11;
assign VAR9 = VAR11[3];
assign VAR12 = VAR3 ? VAR38 : VAR42;
always @(VAR11 or VAR20)
casex({VAR11, VAR20[1:0]})
{VAR30, 2'b00} : VAR5 = 4'b1000;
{VAR30, 2'b01} : VAR5 = 4'b0100;
{VAR30, 2'b10} : VAR5 = 4'b0010;
{VAR30, 2'b11} : VAR5 = 4'b0001;
{VAR15, 2'b00} : VAR5 = 4'b1100;
{VAR15, 2'b10} : VAR5 = 4'b0011;
{VAR32, 2'b00} : VAR5 = 4'b1111;
{VAR46, 2'b00}, {VAR39, 2'b00} : VAR5 = 4'b1000;
{VAR46, 2'b01}, {VAR39, 2'b01} : VAR5 = 4'b0100;
{VAR46, 2'b10}, {VAR39, 2'b10} : VAR5 = 4'b0010;
{VAR46, 2'b11}, {VAR39, 2'b11} : VAR5 = 4'b0001;
{VAR2, 2'b00}, {VAR28, 2'b00} : VAR5 = 4'b1100;
{VAR2, 2'b10}, {VAR28, 2'b10} : VAR5 = 4'b0011;
{VAR27, 2'b00}, {VAR17, 2'b00} : VAR5 = 4'b1111;
default : VAR5 = 4'b0000;
endcase
VAR41 VAR41(
.addr(VAR20[1:0]),
.VAR11(VAR11),
.VAR24(VAR35),
.VAR34(VAR1)
);
VAR31 VAR31(
.addr(VAR20[1:0]),
.VAR11(VAR11),
.VAR34(VAR43),
.VAR24(VAR10)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.functional.pp.v
| 1,935 |
module MODULE1( VAR14, VAR3, VAR26, VAR9, VAR16, VAR10, VAR4, VAR22, VAR21 );
input VAR10, VAR4, VAR9, VAR16, VAR3, VAR26;
inout VAR22, VAR21;
output VAR14;
wire VAR1;
not VAR7( VAR1, VAR10 );
wire VAR12;
not VAR17( VAR12, VAR4 );
wire VAR27;
and VAR19( VAR27, VAR1, VAR12 );
wire VAR24;
not VAR11( VAR24, VAR9 );
wire VAR13;
not VAR18( VAR13, VAR16 );
wire VAR6;
and VAR8( VAR6, VAR24, VAR13 );
wire VAR2;
not VAR25( VAR2, VAR3 );
wire VAR28;
not VAR15( VAR28, VAR26 );
wire VAR23;
and VAR20( VAR23, VAR2, VAR28 );
or VAR5( VAR14, VAR27, VAR6, VAR23 );
endmodule
|
apache-2.0
|
CospanDesign/nysa-artemis-platform
|
artemis/slave/wb_artemis_ddr3/rtl/wb_artemis_ddr3.v
| 8,897 |
module MODULE1 (
input clk,
input rst,
output VAR36,
output VAR10,
output [2:0] VAR57,
output [5:0] VAR64,
output [29:0] VAR4,
input VAR37,
input VAR44,
output VAR5,
output VAR43,
output [3:0] VAR58,
output [31:0] VAR70,
input VAR41,
input VAR25,
input [6:0] VAR15,
input VAR7,
input VAR55,
output VAR46,
output VAR32,
input [31:0] VAR13,
input VAR62,
input VAR60,
input [6:0] VAR69,
input VAR47,
input VAR52,
input VAR65,
input VAR50,
input [3:0] VAR67,
input [31:0] VAR1,
input VAR18,
output reg VAR3,
output reg [31:0] VAR40,
input [31:0] VAR23,
output reg VAR51
);
reg VAR12;
reg VAR39;
wire [27:0] VAR22;
reg VAR8;
wire [1:0] VAR2;
reg [1:0] VAR26;
wire [23:0] VAR34;
wire VAR54;
reg VAR9;
wire VAR30;
reg VAR35;
wire [23:0] VAR16;
wire [31:0] VAR14;
reg [23:0] VAR48;
reg [23:0] VAR19;
VAR6 VAR11(
.clk (clk ),
.rst (rst ),
.VAR74 (VAR23[27:0] ),
.VAR12 (VAR12 ),
.VAR68 (VAR23[27:0] ),
.VAR39 (VAR39 ),
.VAR8 (VAR8 ),
.VAR20 (VAR1 ),
.VAR2 (VAR2 ),
.VAR26 (VAR26 ),
.VAR34 (VAR34 ),
.VAR54 (VAR54 ),
.VAR9 (VAR9 ),
.VAR30 (VAR30 ),
.VAR35 (VAR35 ),
.VAR16 (VAR16 ),
.VAR14 (VAR14 ),
.VAR71 (VAR10 ),
.VAR63 (VAR57 ),
.VAR72 (VAR64 ),
.VAR56 (VAR22 ),
.VAR27 (VAR37 ),
.VAR33 (VAR44 ),
.VAR45 (VAR43 ),
.VAR31 (VAR58 ),
.VAR42 (VAR70 ),
.VAR66 (VAR41 ),
.VAR49 (VAR25 ),
.VAR29 (VAR15 ),
.VAR59 (VAR7 ),
.VAR24 (VAR55 ),
.VAR61 (VAR32 ),
.VAR53 (VAR13 ),
.VAR28 (VAR62 ),
.VAR17 (VAR60 ),
.VAR21 (VAR69 ),
.VAR73 (VAR47 ),
.VAR38 (VAR52 )
);
assign VAR36 = clk;
assign VAR5 = clk;
assign VAR46 = clk;
assign VAR4 = {VAR22, 2'b0};
always @ (posedge clk) begin
if (rst) begin
VAR40 <= 32'h0;
VAR3 <= 0;
VAR51 <= 0;
VAR12 <= 0;
VAR39 <= 0;
VAR8 <= 0;
VAR26 <= 0;
VAR9 <= 0;
VAR35 <= 0;
VAR48 <= 0;
VAR19 <= 0;
end
else begin
VAR8 <= 0;
VAR9 <= 0;
if ((VAR2 > 0) && (VAR26 == 0)) begin
VAR48 <= 0;
if (VAR2[0]) begin
VAR26[0] <= 1;
end
else begin
VAR26[1] <= 1;
end
end
if (VAR30 && !VAR35) begin
VAR19 <= 0;
VAR35 <= 1;
end
if (VAR3 && ~VAR18)begin
VAR3 <= 0;
end
if (VAR50) begin
if (VAR65) begin
VAR12 <= 1;
end
else begin
VAR39 <= 1;
end
end
else begin
VAR12 <= 0;
VAR39 <= 0;
VAR26 <= 0;
VAR35 <= 0;
end
if ((VAR26 > 0) && (VAR48 > 0)&& (VAR2 > 0)) begin
VAR26 <= 0;
end
else if (VAR18 && VAR50 && !VAR3) begin
if (VAR12) begin
if (VAR26 > 0) begin
if (VAR48 < VAR34) begin
VAR8 <= 1;
VAR3 <= 1;
VAR48 <= VAR48 + 24'h1;
end
else begin
VAR26 <= 0;
end
end
end
else begin
if (VAR35) begin
if (VAR19 < VAR16) begin
VAR19 <= VAR19 + 1;
VAR40 <= VAR14;
VAR3 <= 1;
VAR9 <= 1;
end
else begin
VAR35 <= 0;
end
end
end
end
end
end
endmodule
|
gpl-2.0
|
The7thPres/CFTP
|
CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Top.v
| 10,898 |
module MODULE1(
input VAR71,
input VAR20,
output VAR60,
output VAR42,
input VAR51,
output VAR47,
output VAR48,
output VAR80,
inout [15:0] VAR106,
input [10:0] VAR1,
input VAR65, input VAR101, input VAR67, input VAR83, output VAR33, output VAR107 );
wire VAR53, VAR28, VAR43;
wire VAR11;
reg reset;
always @(posedge VAR53) begin
reset = ~VAR11;
end
reg [31:0] VAR77;
wire [31:0] VAR23, VAR59;
wire [29:0] VAR18, VAR58;
wire [3:0] VAR32;
wire VAR97, VAR14;
reg VAR69;
wire [4:0] VAR19;
wire VAR99;
wire VAR6;
reg [3:0] VAR31;
reg VAR103;
reg [29:0] VAR63;
reg [31:0] VAR50;
wire VAR46;
wire VAR35;
wire VAR4;
wire VAR61;
wire [3:0] VAR52;
wire [31:0] VAR22;
wire VAR62;
wire [31:0] VAR100;
wire VAR24, VAR25, VAR89, VAR10;
VAR90 VAR5 (
.VAR87 (VAR71),
.VAR34 (VAR20),
.reset (1'b0),
.VAR95 (VAR53),
.VAR7 (VAR28),
.VAR36 (VAR43),
.VAR108 (VAR11)
);
VAR16 VAR76 (
.VAR53 (VAR53),
.reset (VAR38 | VAR105),
.VAR21 (VAR19),
.VAR41 (VAR99),
.VAR82 (VAR77),
.VAR55 (VAR69),
.VAR40 (VAR97),
.VAR102 (VAR32),
.VAR74 (VAR18),
.VAR3 (VAR23),
.VAR70 (VAR59),
.VAR96 (VAR58),
.VAR78 (VAR46),
.VAR45 (VAR14)
);
VAR13 VAR104 (
.VAR53 (VAR53),
.reset (reset),
.VAR64 (VAR103),
.VAR79 (VAR31),
.VAR86(VAR63),
.VAR50 (VAR50),
.VAR12 (VAR59),
.VAR17 (VAR46),
.VAR39 (VAR35),
.VAR66 (VAR4),
.VAR94 (VAR61),
.VAR85 (VAR52),
.VAR26(VAR18),
.VAR81 (VAR23),
.VAR22 (VAR22),
.VAR49 (VAR62),
.VAR9 (VAR38),
.VAR29(VAR28),
.VAR37 (VAR51),
.VAR98 (VAR42),
.VAR91 (VAR47),
.VAR88 (VAR80),
.VAR75 ()
);
assign VAR48 = 1'b0;
VAR72 VAR84(
.VAR106 (VAR106),
.VAR1 (VAR1),
.VAR65 (VAR65), .VAR101 (VAR101), .VAR67 (VAR67), .VAR83 (VAR83), .VAR33 (VAR33), .VAR107 (VAR107), .VAR27 (1'b0),
.VAR2 (VAR23),
.VAR8 (VAR100),
.VAR73 (VAR24), .VAR54 (VAR25), .VAR30 (VAR89), .VAR57 (VAR53), .VAR44 (reset), .VAR92 (VAR10) );
assign VAR6 = (VAR32 == 4'hF) ? 1 : 0;
assign VAR19[4:1] = 0;
assign VAR19[0] = VAR10;
assign VAR99 = 0;
always @ begin
case (VAR18[29])
0 : begin
VAR77 <= VAR22;
VAR69 <= VAR62;
end
1 : begin
case (VAR18[28:26])
3'b010 : begin
VAR77 <= VAR100;
VAR69 <= VAR89;
end
default: begin
VAR77 <= 32'h00000000;
VAR69 <= 0;
end
endcase
end
endcase
end
assign VAR61 = (VAR18[29]) ? 0 : VAR97;
assign VAR52 = (VAR18[29]) ? 4'h0 : VAR32;
assign VAR25 = (VAR18[29:26] == 4'b1010) ? VAR6 : 0;
assign VAR24 = (VAR18[29:26] == 4'b1010) ? VAR97 : 0;
VAR15 VAR68(
.VAR93 (VAR28),
.VAR56 (VAR60));
endmodule
|
lgpl-3.0
|
UCR-CS179-SUMMER2014/NES_FPGA
|
source/NES_FPGA/vga640x480.v
| 2,399 |
module MODULE1(
VAR4,
VAR9,
VAR2,
VAR3,
VAR7,
VAR15,
VAR5
);
input VAR4; input VAR9;
output VAR2; output VAR3;
output [9:0] VAR7; output [9:0] VAR15;
output VAR5;
localparam VAR14 = 800 , VAR12 = 521 , VAR10 = 144 , VAR11 = 784 ,
VAR1 = 31 , VAR8 = 511 ;
reg [9:0] VAR13, VAR16; reg VAR6;
assign VAR7 = VAR13;
assign VAR15 = VAR16;
assign VAR2 = (VAR13 < 128) ? 1'b0 : 1'b1; assign VAR3 = (VAR16 < 2) ? 1'b0 : 1'b1; assign VAR5 = (((VAR13 < VAR11) && (VAR13 >= VAR10)) && ((VAR16 < VAR8) && (VAR16 >= VAR1))) ? 1'b1 : 1'b0;
always @ (posedge VAR4)
begin
if(VAR9 == 1'b1)
VAR13 <= 10'b0000000000;
end
else if(VAR4 == 1'b1)
begin
if(VAR13 < (VAR14 - 1'b1) )
begin
VAR13 <= VAR13 + 1'b1;
VAR6 <= 1'b0; end
else
begin
VAR13 <= 10'b0000000000; VAR6 <= 1'b1; end
end
end
always @ (posedge VAR4)
begin
if(VAR9 == 1'b1)
VAR16 <= 10'b0000000000;
end
else if(VAR4 == 1'b1 && VAR6 == 1'b1)
begin
if( VAR16 < (VAR12 - 1'b1) )
begin
VAR16 <= VAR16 + 1'b1; end
else
begin
VAR16 <= 10'b0000000000;
end
end
end
endmodule
|
mit
|
Obijuan/open-fpga-verilog-tutorial
|
tutorial/ICESTICK/T26-rom/romleds.v
| 1,050 |
module MODULE1 (input wire clk,
output wire [3:0] VAR3);
parameter VAR5 = VAR10;
reg [3:0] addr;
reg VAR7 = 0;
wire VAR11;
VAR12
VAR6 (
.clk(clk),
.addr(addr),
.VAR2(VAR3)
);
always @(negedge clk)
if (VAR7 == 0)
addr <= 0;
else if (VAR11)
addr <= addr + 1;
VAR9 #(.VAR8(VAR5))
VAR1 ( .clk(clk),
.VAR4(VAR11)
);
always @(negedge clk)
VAR7 <= 1;
endmodule
|
gpl-2.0
|
AnAtomInTheUniverse/578_project_col_panic
|
final_verilog/src/clib/c_damq_tracker.v
| 7,792 |
module MODULE1
(clk, reset, VAR50, VAR47, VAR37, VAR26, VAR19,
VAR21, VAR6, VAR3, VAR32, VAR22, VAR36);
parameter VAR30 = 4;
parameter VAR10 = 32;
parameter VAR1 = 0;
parameter VAR13 = 0;
parameter VAR16 = 0;
parameter VAR43 = 0;
parameter VAR27 = VAR40;
localparam VAR17
= VAR43 ? (VAR10 - VAR30) : VAR10;
localparam VAR51
= VAR43 ? (1 + VAR17) : VAR10;
input clk;
input reset;
input VAR50;
input VAR47;
input [0:VAR30-1] VAR37;
input VAR26;
input [0:VAR30-1] VAR19;
output [0:VAR30-1] VAR21;
wire [0:VAR30-1] VAR21;
output [0:VAR30-1] VAR6;
wire [0:VAR30-1] VAR6;
output [0:VAR30-1] VAR3;
wire [0:VAR30-1] VAR3;
output [0:VAR30-1] VAR32;
wire [0:VAR30-1] VAR32;
output [0:VAR30-1] VAR22;
wire [0:VAR30-1] VAR22;
output [0:VAR30*2-1] VAR36;
wire [0:VAR30*2-1] VAR36;
wire VAR25;
wire VAR45;
generate
if(VAR43)
begin
wire VAR39;
VAR23
.VAR35(1))
VAR44
(.select(VAR37),
.VAR29(VAR6),
.VAR18(VAR39));
wire VAR42;
VAR23
.VAR35(1))
VAR5
(.select(VAR19),
.VAR29(VAR21),
.VAR18(VAR42));
wire VAR48;
assign VAR48 = |(VAR37 & VAR19);
assign VAR25 = VAR47 & ~VAR39 &
(~VAR26 | (VAR42 & ~VAR48));
if(VAR16)
assign VAR45 = VAR26 & ~VAR42 &
(~VAR47 | (VAR39 & ~VAR48));
end
else
assign VAR45 = VAR26 & ~VAR42 &
(~VAR47 | VAR39);
end
else
begin
assign VAR25 = VAR47 & ~VAR26;
assign VAR45 = VAR26 & ~VAR47;
end
endgenerate
wire VAR34;
wire VAR38;
wire VAR49;
wire [0:1] VAR14;
VAR9
.VAR13(VAR13),
.VAR16(0),
.VAR27(VAR27))
VAR46
(.clk(clk),
.reset(reset),
.VAR50(VAR50),
.VAR8(VAR25),
.VAR33(VAR45),
.VAR15(),
.VAR41(),
.VAR52(VAR34),
.VAR20(VAR38),
.VAR4(VAR49),
.VAR31(VAR14));
genvar VAR11;
generate
for(VAR11 = 0; VAR11 < VAR30; VAR11 = VAR11 + 1)
begin:VAR7
wire VAR12;
assign VAR12 = VAR37[VAR11];
wire VAR8;
assign VAR8 = VAR47 & VAR12;
wire VAR24;
assign VAR24 = VAR19[VAR11];
wire VAR33;
assign VAR33 = VAR26 & VAR24;
wire VAR15;
wire VAR41;
wire [0:1] VAR2;
VAR9
.VAR1(VAR1),
.VAR16(VAR16),
.VAR27(VAR27))
VAR28
(.clk(clk),
.reset(reset),
.VAR50(VAR50),
.VAR8(VAR8),
.VAR33(VAR33),
.VAR15(VAR15),
.VAR41(VAR41),
.VAR52(),
.VAR20(),
.VAR4(),
.VAR31(VAR2));
wire [0:1] VAR31;
assign VAR31[0] = VAR2[0] | (VAR33 & VAR14[0]);
assign VAR31[1] = VAR2[1] | (VAR8 & VAR14[1]);
wire VAR52;
wire VAR20;
wire VAR4;
if(VAR43)
begin
assign VAR52 = VAR41 ? VAR38 : VAR34;
assign VAR20 = ~VAR41 & VAR38;
assign VAR4 = VAR41 ? VAR34 : VAR49;
end
else
begin
assign VAR52 = VAR34;
assign VAR20 = VAR38;
assign VAR4 = VAR49;
end
assign VAR21[VAR11] = VAR15;
assign VAR6[VAR11] = VAR41;
assign VAR3[VAR11] = VAR52;
assign VAR32[VAR11] = VAR20;
assign VAR22[VAR11] = VAR4;
assign VAR36[VAR11*2:VAR11*2+1] = VAR31;
end
endgenerate
endmodule
|
gpl-2.0
|
ShepardSiegel/ocpi
|
coregen/ddr3_s4_amphy/alt_mem_ddrx_odt_gen.v
| 13,845 |
module MODULE1
VAR33 = 2,
VAR6 = 1,
VAR31 = 2, VAR44 = 2,
VAR37 = 1,
VAR43 = 4,
VAR13 = 4,
VAR5 = 3,
VAR16 = 3,
VAR9 = 4,
VAR4 = 4
)
(
VAR11,
VAR39,
VAR10,
VAR8,
VAR14,
VAR34,
VAR1,
VAR41,
VAR19,
VAR26,
VAR29,
VAR17,
VAR7,
VAR36,
VAR42
);
input VAR11;
input VAR39;
input [VAR16 -1:0] VAR10;
input [VAR13 -1:0] VAR8;
input [VAR43 -1:0] VAR14;
input [VAR5 -1:0] VAR34;
input [VAR9 -1:0] VAR1;
input [VAR4 -1:0] VAR41;
input [4:0] VAR19;
input [VAR37 -1:0] VAR26;
input VAR29;
input VAR17;
input VAR7;
input [VAR31 -1:0] VAR36;
output [(VAR44*(VAR33/2))-1:0] VAR42;
wire [VAR44-1:0] VAR24 [VAR31-1:0];
wire [VAR44-1:0] VAR28 [VAR31-1:0];
wire [VAR44-1:0] VAR40;
wire [VAR44-1:0] VAR15;
wire [VAR44-1:0] VAR32;
wire [VAR44-1:0] VAR35;
wire [VAR44-1:0] VAR38;
reg [VAR44-1:0] VAR2;
reg [VAR44-1:0] VAR20;
reg [VAR44-1:0] VAR18;
reg [VAR44-1:0] VAR21;
reg [VAR44-1:0] VAR30;
integer VAR25;
generate
genvar VAR23;
begin : VAR3
for (VAR23=0; VAR23<VAR31; VAR23=VAR23+1)
begin : VAR22
assign VAR24[VAR23] = VAR1 [(VAR23*VAR44)+VAR44-1:VAR23*VAR44];
assign VAR28[VAR23] = VAR41 [(VAR23*VAR44)+VAR44-1:VAR23*VAR44];
end
end
endgenerate
always @
begin
if (VAR10 == VAR12)
begin
VAR2 = VAR40;
VAR20 = VAR15;
VAR18 = {(VAR44){1'b0}};
end
else if (VAR10 == VAR27)
begin
VAR2 = VAR32;
VAR20 = VAR35;
VAR18 = VAR38;
end
else
begin
VAR2 = {(VAR44){1'b0}};
VAR20 = {(VAR44){1'b0}};
VAR18 = {(VAR44){1'b0}};
end
end
generate
if (VAR6 == 1)
begin
if (VAR33 == 2) assign VAR42 = VAR2;
end
else if (VAR33 == 4) assign VAR42 = {VAR20,VAR2};
else if (VAR33 == 8) assign VAR42 = {VAR20,VAR18, VAR18, VAR2};
end
else
assign VAR42 = {(VAR44 * (VAR33/2)){1'b0}};
endgenerate
endmodule
|
lgpl-3.0
|
ptracton/pmodacl2
|
behavioral/adxl362/adxl362_accelerometer.v
| 4,888 |
module MODULE1 (
VAR4, VAR17, VAR6, VAR13, VAR21, VAR25,
VAR11,
VAR20, VAR18, VAR24, VAR26
) ;
parameter VAR9 = "VAR13.VAR23";
parameter VAR1 = "VAR21.VAR23";
parameter VAR19 = "VAR25.VAR23";
parameter VAR12 = "VAR14.VAR23";
parameter VAR16 = 16;
input wire VAR20;
input wire VAR18;
input wire [1:0] VAR24;
input wire VAR26;
output wire VAR4;
output reg VAR17;
output reg [15:0] VAR6;
output wire [11:0] VAR13;
output wire [11:0] VAR21;
output wire [11:0] VAR25;
output wire [11:0] VAR11;
integer VAR3 = 0;
integer VAR7 = 0;
integer VAR10 = 0;
integer VAR15 = 0;
reg [11:0] VAR5 [VAR16-1:0];
reg [11:0] VAR2 [VAR16-1:0];
reg [11:0] VAR8 [VAR16-1:0];
reg [11:0] VAR22 [VAR16-1:0];
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/acl_fp_tanpi_s5.v
| 1,187 |
module MODULE1 (
enable,
VAR7,
VAR5,
VAR2);
input enable;
input VAR7;
input [31:0] VAR5;
output [31:0] VAR2;
wire [31:0] VAR1;
wire [31:0] VAR2 = VAR1[31:0];
VAR8 VAR9(
.en (enable),
.clk (VAR7),
.VAR3 (VAR5),
.VAR6 (VAR1),
.VAR4(1'b0));
endmodule
|
mit
|
vad-rulezz/megabot
|
fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/orpsoc_top.v
| 18,145 |
module MODULE1 #(
parameter VAR199 = 16,
parameter VAR345 = 13,
parameter VAR207 = 2,
parameter VAR205 = 6,
parameter VAR227 = 3
)(
input VAR356,
input VAR12,
input VAR7,
output VAR274,
output [12:0] VAR393,
output [2:0] VAR341,
output VAR257,
output VAR287,
output VAR68,
output VAR265,
output VAR405,
output VAR194,
output VAR330,
output VAR249,
output VAR288,
inout [15:0] VAR285,
inout VAR209,
inout VAR225,
inout VAR412,
inout VAR410,
output VAR261,
output VAR66,
inout VAR174,
inout[3:0] VAR178,
output VAR17
);
parameter VAR196=32'h14951185;
wire VAR39;
wire VAR397, VAR339;
wire VAR286, VAR19;
wire [31:0] VAR259;
wire [31:0] VAR206;
wire [3:0] VAR126;
wire VAR20;
wire VAR390;
wire VAR171;
wire [2:0] VAR302;
wire [1:0] VAR357;
wire [31:0] VAR391;
wire VAR107;
VAR166 VAR118 (
.VAR356 (VAR356),
.VAR12 (VAR12),
.VAR34 (VAR39),
.VAR296 (VAR397),
.VAR379 (VAR339),
.VAR364 (VAR286),
.VAR212 (VAR19)
);
wire VAR133;
wire VAR204;
wire VAR214;
wire VAR221;
wire VAR243;
wire VAR157;
wire VAR275;
wire VAR273;
wire VAR317;
VAR144 VAR402
(
.VAR86 (VAR273),
.VAR169 (VAR204),
.VAR220 (VAR214),
.VAR183 (VAR317),
.VAR383 (),
.VAR187 (VAR221),
.VAR352 (VAR275),
.VAR74 (VAR243),
.VAR87 (VAR157),
.VAR263 (VAR133)
);
assign VAR74 = 1'b0;
assign VAR383 = 1'b0;
wire [31:0] VAR247;
wire [31:0] VAR88;
wire [31:0] VAR22;
wire VAR101;
wire VAR282;
wire VAR159;
wire [31:0] VAR246;
wire VAR248;
wire VAR51;
wire [3:0] VAR215;
wire [1:0] VAR284;
wire [10:0] VAR377;
wire VAR348;
wire VAR49;
wire VAR32;
wire VAR47;
assign VAR47 = VAR339 | VAR49;
VAR94 #(.VAR234(32'hf0000100))
VAR2 (
.VAR13 (VAR397),
.VAR95 (VAR339),
.VAR304 (VAR386),
.VAR132 (VAR16),
.VAR186 (VAR367),
.VAR312 (VAR26),
.VAR79 (VAR228),
.VAR41 (VAR111),
.VAR414 (VAR241),
.VAR293 (VAR119),
.VAR231 (VAR71),
.VAR239 (VAR10),
.VAR193 (VAR396),
.VAR279 (VAR185),
.VAR120 (VAR397),
.VAR289 (VAR339),
.VAR116 (VAR255),
.VAR138 (VAR237),
.VAR110 (VAR347),
.VAR283 (VAR129),
.VAR253 (VAR141),
.VAR52 (VAR326),
.VAR64 (VAR298),
.VAR307 (VAR378),
.VAR103 (VAR98),
.VAR156 (VAR168),
.VAR61 (VAR175),
.VAR256 (VAR190),
.VAR336 (VAR248),
.VAR191 (1'b0),
.VAR389 (VAR215),
.VAR184 (VAR284),
.VAR75 (VAR377),
.VAR108 (VAR348),
.VAR77 (VAR22),
.VAR134 (VAR101),
.VAR268 (VAR282),
.VAR322 (VAR88),
.VAR93 (VAR246),
.VAR42 (VAR159),
.VAR142 (),
.VAR409 (),
.VAR3 (),
.VAR271 (),
.VAR375 (),
.VAR201 (),
.VAR300 (),
.VAR333 (),
.VAR81 (),
.VAR376 (VAR397),
.VAR80 (VAR47),
.VAR55 (2'b01),
.VAR56 (VAR247),
.VAR32 (VAR32),
.VAR181 (1'b0)
);
VAR355 VAR358 (
.VAR305 (VAR397),
.VAR343 (VAR49),
.VAR160 (VAR22),
.VAR365 (VAR88),
.VAR99 (VAR282),
.VAR318 (VAR101),
.VAR145 (VAR246),
.VAR232 (VAR159),
.VAR334 (VAR248),
.VAR76 (VAR348),
.VAR161 (VAR273), .VAR158 (VAR214),
.VAR319 (VAR204),
.VAR80 (VAR317), .VAR67 (VAR275),
.VAR148 (VAR221),
.VAR327 (VAR243),
.VAR369 (VAR157),
.VAR131 (VAR133),
.VAR167 (VAR339),
.VAR210 (VAR397),
.VAR219 (VAR162),
.VAR360 (VAR208),
.VAR112 (VAR349),
.VAR303 (VAR54),
.VAR72 (VAR320),
.VAR323 (VAR195),
.VAR276 (VAR172),
.VAR394 (VAR130),
.VAR43 (VAR233),
.VAR192 (VAR152),
.VAR328 (VAR277)
);
assign VAR69 = 1'b0;
assign VAR404 = 1'b0;
VAR244 #(.VAR37(VAR205))
VAR45 (
.VAR397 (VAR397),
.VAR339 (VAR339),
.VAR258 (VAR123[(VAR205 + 2) - 1 : 2]),
.VAR254 (VAR140),
.VAR188 (VAR416),
.VAR58 (VAR179),
.VAR295 (VAR115),
.VAR72 (VAR373),
.VAR278 (VAR176)
);
assign VAR78 = 0;
assign VAR82 = 0;
VAR85 VAR301 (
.VAR18 (VAR362),
.VAR14 (VAR251),
.VAR218 (VAR213),
.VAR399 (VAR313),
.VAR83 (VAR415),
.VAR308 (VAR65),
.VAR121 (VAR4),
.VAR385 (VAR398),
.VAR89 (VAR309),
.VAR403 (VAR270),
.VAR346 (VAR97),
.VAR24 (VAR104),
.VAR73 (VAR223),
.VAR368 (VAR340),
.VAR297 (VAR15),
.VAR325 (VAR371),
.VAR281 (VAR294),
.VAR338 (VAR211),
.VAR154 (VAR411),
.VAR229 (VAR170),
.VAR235 (VAR406),
.VAR224 (VAR400),
.VAR395 (VAR324),
.VAR63 (VAR135),
.VAR354 (VAR342),
.VAR1 (VAR264),
.VAR401 (VAR84),
.VAR291 (VAR128),
.VAR136 (VAR408),
.VAR90 (VAR35),
.VAR164 (VAR260),
.VAR60 (VAR92),
.VAR290 (VAR316),
.VAR417 (VAR245),
.VAR57 (VAR165),
.VAR122 (VAR200),
.VAR38 (0),
.VAR150 (0),
.VAR315 (0),
.VAR202 (0),
.VAR106 (0),
.VAR40 (0),
.VAR382 (0),
.VAR177 (0),
.VAR29 (),
.VAR124 (),
.VAR387 (),
.VAR182 (),
.VAR163 (0),
.VAR306 (0),
.VAR50 (0),
.VAR21 (0),
.VAR335 (0),
.VAR31 (0),
.VAR310 (0),
.VAR8 (0),
.VAR351 (),
.VAR44 (),
.VAR46 (),
.VAR217 (),
.VAR240 (0),
.VAR70 (0),
.VAR384 (0),
.VAR53 (0),
.VAR337 (0),
.VAR388 (0),
.VAR155 (0),
.VAR363 (0),
.VAR113 (),
.VAR350 (),
.VAR11 (),
.VAR125 (),
.VAR397 (VAR397),
.VAR339 (VAR339),
.VAR393 (VAR393[12:0]),
.VAR341 (VAR341),
.VAR257 (VAR257),
.VAR287 (VAR287),
.VAR68 (VAR68),
.VAR265 (VAR265),
.VAR330 (VAR330),
.VAR249 (VAR249),
.VAR288 (VAR288),
.VAR261 (VAR261),
.VAR66 (VAR66),
.VAR285 (VAR285),
.VAR209 (VAR209),
.VAR412 (VAR412),
.VAR286 (VAR286),
.VAR19 (VAR19)
);
wire VAR147;
VAR48 VAR96 (
.VAR210 (VAR397),
.VAR167 (VAR339),
.VAR258 (VAR366[VAR227-1:0]),
.VAR219 (VAR153),
.VAR353 (VAR143),
.VAR188 (VAR36),
.VAR254 (VAR262),
.VAR59 (4'b0), .VAR72 (VAR272),
.VAR278 (VAR329),
.VAR105 (VAR147),
.VAR372 (VAR274),
.VAR332 (),
.VAR361 (),
.VAR236 (VAR7),
.VAR100 (1'b0),
.VAR413 (1'b0),
.VAR33 (1'b0),
.VAR374 (1'b0)
);
wire VAR242;
wire VAR238;
wire VAR250;
wire [3:0] VAR267;
wire VAR252;
wire VAR9;
assign VAR174 = VAR242 ? VAR250 : 1'VAR189;
assign VAR178 = VAR238 ? VAR267 : 4'VAR380;
assign VAR314 = 0;
assign VAR392 = 0;
assign VAR5 = 0; assign VAR151 = 0;
VAR109 VAR292(
.VAR210 (VAR397),
.VAR167 (VAR339),
.VAR258 (VAR180),
.VAR219 (VAR23),
.VAR353 (VAR299),
.VAR188 (VAR344),
.VAR254 (VAR62),
.VAR59 (4'hf), .VAR72 (VAR321),
.VAR278 (VAR117),
.VAR230 (VAR331), .VAR269 (VAR198), .VAR280 (VAR222), .VAR27 (VAR114), .VAR127 (VAR311), .VAR216 (VAR102), .VAR30 (VAR370), .VAR173 (VAR197), .VAR203 (VAR25), .VAR407 (VAR91),
.VAR139 (VAR174),
.VAR137 (VAR250 ),
.VAR381 (VAR242),
.VAR146 (VAR178 ),
.VAR28 (VAR267 ) ,
.VAR149 (VAR238 ),
.VAR226 (VAR17),
.VAR359 (VAR397),
.VAR6 (VAR252),
.VAR266 (VAR9)
);
assign VAR247[0] = 0; assign VAR247[1] = 0; assign VAR247[2] = VAR147;
assign VAR247[3] = 0;
assign VAR247[4] = 0;assign VAR247[5] = 0;assign VAR247[6] = 0;assign VAR247[7] = 0;
assign VAR247[8] = 0;assign VAR247[9] = 0;
assign VAR247[10] = 0;
assign VAR247[11] = 0;
assign VAR247[12] = 0;assign VAR247[13] = 0;assign VAR247[14] = VAR252;assign VAR247[15] = VAR9;
assign VAR247[16] = 0;assign VAR247[17] = 0;
assign VAR247[18] = 0;
assign VAR247[19] = 0;
assign VAR247[20] = 0;
assign VAR247[21] = 0;
assign VAR247[22] = 0;
assign VAR247[23] = 0;
assign VAR247[24] = 0;
assign VAR247[25] = 0;
assign VAR247[26] = 0;
assign VAR247[27] = 0;
assign VAR247[28] = 0;
assign VAR247[29] = 0;
assign VAR247[30] = 0;
assign VAR247[31] = 0;
endmodule
|
gpl-2.0
|
marmolejo/zet
|
cores/wb_abrg/wb_regslice.v
| 2,059 |
module MODULE1 (
input clk,
input rst,
input [19:1] VAR18,
input [15:0] VAR11,
output reg [15:0] VAR8,
input [ 1:0] VAR7,
input VAR5,
input VAR15,
input VAR14,
input VAR19,
output reg VAR12,
output reg [19:1] VAR17,
output reg [15:0] VAR4,
input [15:0] VAR13,
output reg [ 1:0] VAR9,
output reg VAR6,
output reg VAR2,
output reg VAR1,
output reg VAR16,
input VAR3
);
wire VAR10;
assign VAR10 = VAR3 | VAR12;
always @(posedge clk)
VAR2 <= rst ? 1'b0
: (VAR10 ? 1'b0 : VAR15);
always @(posedge clk)
begin
VAR17 <= VAR18;
VAR4 <= VAR11;
VAR9 <= VAR7;
VAR6 <= VAR5;
VAR1 <= VAR14;
VAR16 <= VAR19;
end
always @(posedge clk)
begin
VAR8 <= VAR13;
VAR12 <= VAR3;
end
endmodule
|
gpl-3.0
|
orbancedric/DeepGate
|
src/core/parameterized_RAM_last.v
| 1,931 |
module MODULE1 #(
parameter VAR1 = 10,
parameter VAR4 = 2
)(
input VAR11,
input VAR12,
input VAR5,
input [7:0] VAR7,
output reg [7:0] VAR3 = 0,
output wire VAR8,
output wire VAR13
);
reg [7:0] VAR9 [VAR1*VAR4*2 - 1'b1: 0];
reg [VAR14(VAR1*VAR4*2):0] VAR6 = 0;
reg [VAR14(VAR1*VAR4*2 - 1'b1):0] VAR2 = 0;
reg [1:0] VAR10 = 0;
assign VAR13 = VAR10[0] | VAR10[1];
assign VAR8 = VAR10[0] & VAR10[1];
integer VAR15;
|
gpl-3.0
|
kielfriedt/ece472
|
lab5/HazardDetect.v
| 1,475 |
module MODULE1(clk, reset, VAR6, VAR5, VAR4, VAR1, VAR7, VAR3, VAR2);
input VAR6, clk, reset;
input [4:0] VAR5, VAR1, VAR7, VAR4;
output VAR3, VAR2;
reg VAR3, VAR2;
always @(clk or VAR4 or VAR5 or VAR7 or VAR1 )
begin
if(((VAR5 == VAR1) && (VAR5 != 0)) || ((VAR4 == VAR7) && (VAR4 != 0)))
begin
assign VAR3 = 1;
assign VAR2 = 1;
end
else
begin
assign VAR3 = 0;
assign VAR2 = 0;
end
end
|
gpl-3.0
|
CospanDesign/nysa-artemis-pcie-platform
|
artemis_pcie/slave/wb_artemis_pcie_platform/rtl/buffer_builder.v
| 5,889 |
module MODULE1 #(
parameter VAR23 = 13, parameter VAR37 = 32
)(
input VAR10,
input rst,
input [1:0] VAR2, output reg VAR13,
input VAR8,
input [VAR23 - 1: 0] VAR17,
input [VAR37 - 1: 0] VAR11,
input VAR1,
input [23:0] VAR29,
input [1:0] VAR16,
output reg [1:0] VAR34,
input [23:0] VAR22,
output reg VAR20,
output [VAR37 - 1:0] VAR28
);
localparam VAR30 = 0;
localparam VAR19 = 1;
localparam VAR24 = 2;
localparam VAR33 = 3;
localparam VAR21 = 0;
localparam VAR35 = ((2 ** VAR23) / 2);
reg [3:0] state;
reg [23:0] VAR9;
reg [VAR23 - 1: 0] VAR18;
reg [VAR23 - 1: 0] VAR5;
VAR14 #(
.VAR37 (VAR37 ),
.VAR4 (VAR23 )
) VAR26 (
.VAR31 (VAR10 ),
.VAR36 (VAR8 ),
.VAR27 (VAR17 ),
.VAR32 ( ),
.VAR15 (VAR11 ),
.VAR12 (VAR1 ),
.VAR25 (1'b0 ),
.VAR3 (VAR5 ),
.VAR6 (32'h00000000 ),
.VAR7 (VAR28 )
);
always @ (posedge VAR1) begin
VAR20 <= 0;
if (rst) begin
VAR34 <= 0;
VAR13 <= 0;
VAR9 <= 0;
VAR5 <= 0;
state <= VAR30;
end
else begin
case (state)
VAR30: begin
VAR13 <= 0;
VAR34 <= 0;
VAR5 <= 0;
VAR9 <= 0;
if (VAR2 > 0) begin
if (VAR2[0]) begin
VAR5 <= VAR21;
end
else begin
VAR5 <= VAR35;
end
state <= VAR19;
end
end
VAR19: begin
if ((VAR16 > 0) && (VAR34 == 0)) begin
if (VAR16[0]) begin
VAR34[0] <= 1;
end
else begin
VAR34[1] <= 1;
end
state <= VAR24;
end
end
VAR24: begin
if (VAR9 < VAR29) begin
VAR5 <= VAR5 + 1;
VAR20 <= 1;
VAR9 <= VAR9 + 1;
end
else begin
VAR34 <= 0;
state <= VAR33;
end
end
VAR33: begin
VAR13 <= 1;
if (VAR2 == 0) begin
VAR13 <= 0;
state <= VAR30;
end
end
default: begin
state <= VAR30;
end
endcase
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a211o/sky130_fd_sc_ms__a211o_2.v
| 2,348 |
module MODULE1 (
VAR5 ,
VAR9 ,
VAR7 ,
VAR10 ,
VAR4 ,
VAR8,
VAR11,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
input VAR8;
input VAR11;
input VAR6 ;
input VAR1 ;
VAR2 VAR3 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5 ,
VAR9,
VAR7,
VAR10,
VAR4
);
output VAR5 ;
input VAR9;
input VAR7;
input VAR10;
input VAR4;
supply1 VAR8;
supply0 VAR11;
supply1 VAR6 ;
supply0 VAR1 ;
VAR2 VAR3 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.functional.pp.v
| 1,235 |
module MODULE1( VAR8, VAR4, VAR13, VAR2, VAR1, VAR10 );
input VAR2, VAR13, VAR4;
inout VAR1, VAR10;
output VAR8;
wire VAR6;
not VAR3( VAR6, VAR2 );
wire VAR9;
not VAR12( VAR9, VAR13 );
wire VAR11;
not VAR7( VAR11, VAR4 );
and VAR5( VAR8, VAR6, VAR9, VAR11 );
endmodule
|
apache-2.0
|
yupferris/hello-everyweeks
|
hello.v
| 1,666 |
module MODULE1(
input VAR7,
input VAR14,
output VAR10);
reg [7:0] VAR15;
reg VAR2;
wire VAR6;
reg [0:VAR13 - 1] VAR12;
reg [1:0] state;
always @(posedge VAR7 or negedge VAR14)
if (VAR14 == 1'b0) begin
VAR15 <= 0;
VAR2 <= 0;
VAR12 <= VAR4;
state <= VAR11;
end else begin
case (state)
if (VAR12[0:7] != 0) begin
VAR15 <= VAR12[0:7];
VAR12 <= {VAR12[8:VAR13 - 1], 8'd0};
VAR2 <= 1;
state <= VAR8;
end else
state <= VAR5;
if (VAR6) begin
VAR2 <= 0;
state <= VAR9;
end
if (!VAR6)
state <= VAR11;
default: state <= VAR5;
endcase
end
VAR3 VAR1(
.clk(VAR7),
.reset(!VAR14),
.VAR15(VAR15),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10)
);
endmodule
|
bsd-2-clause
|
Jesus89/open-fpga-verilog-tutorial
|
tutorial/ICESTICK/T23-fsmtx/fsmtx2.v
| 4,890 |
module MODULE1 (input wire clk, output reg VAR20 );
parameter VAR10 = VAR7;
parameter VAR1 = "VAR14";
parameter VAR24 = VAR22;
reg [9:0] VAR3;
wire VAR4;
reg VAR11;
wire VAR19;
reg VAR23 = 0;
reg [3:0] VAR16;
wire VAR6; wire VAR8;
always @(posedge clk)
VAR11 <= VAR4;
always @(posedge clk)
if (VAR23 == 0)
VAR3 <= 10'b1111111111;
else if (VAR6 == 1)
VAR3 <= {VAR1,2'b01};
else if (VAR6 == 0 && VAR19 == 1)
VAR3 <= {1'b1, VAR3[9:1]};
always @(posedge clk)
if (VAR6 == 1)
VAR16 <= 0;
else if (VAR6 == 0 && VAR19 == 1)
VAR16 <= VAR16 + 1;
always @(posedge clk)
VAR20 <= VAR3[0];
VAR21 #(VAR10)
VAR17 (
.clk(clk),
.VAR12(VAR8),
.VAR13(VAR19)
);
VAR2 #(.VAR15(VAR24))
VAR5 ( .clk(clk),
.VAR13(VAR4)
);
localparam VAR9 = 0;
localparam VAR18 = 1;
localparam VAR25 = 2;
reg [1:0] state;
always @(posedge clk)
if (VAR23 == 0)
state <= VAR9;
else
case (state)
VAR9:
if (VAR11 == 1)
state <= VAR18;
else
state <= VAR9;
VAR18:
state <= VAR25;
VAR25:
if (VAR16 == 11)
state <= VAR9;
else
state <= VAR25;
default:
state <= VAR9;
endcase
assign VAR6 = (state == VAR18) ? 1 : 0;
assign VAR8 = (state == VAR9) ? 0 : 1;
always @(posedge clk)
VAR23 <= 1;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/fill/sky130_fd_sc_ls__fill.behavioral.v
| 1,110 |
module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ4_Mandelbrot/Hardware/OZ4_Mandelbrot/FIFO30x16.v
| 14,036 |
module MODULE1(
rst,
VAR219,
VAR288,
din,
VAR120,
VAR164,
dout,
VAR42,
VAR224,
VAR22,
VAR193
);
input rst;
input VAR219;
input VAR288;
input [30 : 0] din;
input VAR120;
input VAR164;
output [30 : 0] dout;
output VAR42;
output VAR224;
output VAR22;
output VAR193;
VAR206 #(
.VAR110(0),
.VAR392(0),
.VAR171(0),
.VAR118(0),
.VAR180(0),
.VAR306(0),
.VAR179(0),
.VAR363(32),
.VAR338(1),
.VAR208(1),
.VAR287(1),
.VAR320(64),
.VAR274(4),
.VAR315(1),
.VAR130(0),
.VAR105(1),
.VAR228(64),
.VAR149(4),
.VAR278(8),
.VAR281(4),
.VAR301(4),
.VAR245(4),
.VAR235(0),
.VAR128(0),
.VAR187(0),
.VAR95(10),
.VAR406("VAR332"),
.VAR47(31),
.VAR25(1),
.VAR17(32),
.VAR371(64),
.VAR103(32),
.VAR272(64),
.VAR393(2),
.VAR217("0"),
.VAR46(31),
.VAR330(0),
.VAR32(1),
.VAR335(0),
.VAR370(0),
.VAR322(0),
.VAR347(0),
.VAR161(0),
.VAR23(0),
.VAR273(0),
.VAR252("VAR378"),
.VAR196(1),
.VAR150(1),
.VAR88(1),
.VAR29(0),
.VAR236(0),
.VAR83(0),
.VAR40(0),
.VAR307(0),
.VAR55(0),
.VAR104(0),
.VAR185(0),
.VAR152(0),
.VAR215(0),
.VAR251(0),
.VAR408(0),
.VAR275(1),
.VAR116(0),
.VAR140(0),
.VAR7(0),
.VAR374(0),
.VAR8(0),
.VAR276(0),
.VAR34(0),
.VAR387(0),
.VAR151(0),
.VAR312(0),
.VAR291(0),
.VAR173(0),
.VAR199(0),
.VAR20(0),
.VAR117(0),
.VAR229(0),
.VAR367(0),
.VAR198(0),
.VAR285(0),
.VAR293(0),
.VAR182(0),
.VAR366(0),
.VAR77(1),
.VAR395(0),
.VAR11(0),
.VAR258(0),
.VAR160(0),
.VAR207(0),
.VAR344(0),
.VAR376(0),
.VAR134(2),
.VAR96(1),
.VAR396(1),
.VAR21(1),
.VAR415(1),
.VAR343(1),
.VAR289(1),
.VAR61(0),
.VAR326(0),
.VAR90(1),
.VAR270("VAR332"),
.VAR202(1),
.VAR39(0),
.VAR299(0),
.VAR133(0),
.VAR176(1),
.VAR153("1kx36"),
.VAR35(4),
.VAR59(1022),
.VAR146(1022),
.VAR220(1022),
.VAR412(1022),
.VAR214(1022),
.VAR102(1022),
.VAR232(5),
.VAR80(0),
.VAR314(5),
.VAR189(5),
.VAR416(5),
.VAR73(5),
.VAR2(5),
.VAR144(5),
.VAR74(1023),
.VAR218(1023),
.VAR111(1023),
.VAR404(1023),
.VAR45(1023),
.VAR51(1023),
.VAR162(1023),
.VAR340(1022),
.VAR304(0),
.VAR334(5),
.VAR98(5),
.VAR390(5),
.VAR316(5),
.VAR125(5),
.VAR262(5),
.VAR203(0),
.VAR14(10),
.VAR195(1024),
.VAR57(1),
.VAR391(10),
.VAR205(0),
.VAR86(0),
.VAR43(0),
.VAR194(0),
.VAR101(0),
.VAR48(0),
.VAR375(0),
.VAR67(0),
.VAR383(0),
.VAR386(0),
.VAR63(0),
.VAR54(1),
.VAR28(0),
.VAR365(0),
.VAR372(0),
.VAR177(0),
.VAR136(0),
.VAR318(0),
.VAR107(0),
.VAR225(0),
.VAR129(0),
.VAR263(0),
.VAR254(0),
.VAR142(0),
.VAR260(0),
.VAR24(0),
.VAR33(10),
.VAR388(1024),
.VAR300(1024),
.VAR242(16),
.VAR385(1024),
.VAR100(16),
.VAR58(1024),
.VAR13(16),
.VAR280(1),
.VAR238(10),
.VAR309(10),
.VAR157(4),
.VAR384(10),
.VAR147(4),
.VAR70(10),
.VAR398(4),
.VAR99(1),
.VAR381(0)
)
VAR139 (
.VAR132(rst),
.VAR38(VAR219),
.VAR244(VAR288),
.VAR361(din),
.VAR62(VAR120),
.VAR336(VAR164),
.VAR36(dout),
.VAR351(VAR42),
.VAR259(VAR224),
.VAR297(VAR22),
.VAR256(VAR193),
.VAR271(),
.VAR341(),
.VAR410(),
.VAR109(),
.VAR284(),
.VAR290(),
.VAR362(),
.VAR201(),
.VAR311(),
.VAR158(),
.VAR85(),
.VAR166(),
.VAR243(),
.VAR1(),
.VAR239(),
.VAR402(),
.VAR283(),
.VAR210(),
.VAR31(),
.VAR200(),
.VAR369(),
.VAR81(),
.VAR401(),
.VAR234(),
.VAR65(),
.VAR310(),
.VAR119(),
.VAR76(),
.VAR411(),
.VAR298(),
.VAR64(),
.VAR168(),
.VAR357(),
.VAR226(),
.VAR68(),
.VAR348(),
.VAR364(),
.VAR329(),
.VAR247(),
.VAR230(),
.VAR123(),
.VAR18(),
.VAR213(),
.VAR4(),
.VAR358(),
.VAR216(),
.VAR337(),
.VAR331(),
.VAR9(),
.VAR380(),
.VAR163(),
.VAR212(),
.VAR108(),
.VAR93(),
.VAR399(),
.VAR154(),
.VAR174(),
.VAR227(),
.VAR211(),
.VAR178(),
.VAR115(),
.VAR261(),
.VAR324(),
.VAR192(),
.VAR319(),
.VAR246(),
.VAR113(),
.VAR360(),
.VAR403(),
.VAR204(),
.VAR53(),
.VAR257(),
.VAR197(),
.VAR5(),
.VAR97(),
.VAR184(),
.VAR394(),
.VAR69(),
.VAR114(),
.VAR71(),
.VAR255(),
.VAR89(),
.VAR79(),
.VAR209(),
.VAR60(),
.VAR30(),
.VAR172(),
.VAR78(),
.VAR352(),
.VAR170(),
.VAR397(),
.VAR50(),
.VAR66(),
.VAR279(),
.VAR389(),
.VAR292(),
.VAR138(),
.VAR346(),
.VAR3(),
.VAR317(),
.VAR409(),
.VAR156(),
.VAR325(),
.VAR350(),
.VAR295(),
.VAR131(),
.VAR313(),
.VAR49(),
.VAR186(),
.VAR359(),
.VAR188(),
.VAR121(),
.VAR253(),
.VAR286(),
.VAR400(),
.VAR159(),
.VAR339(),
.VAR82(),
.VAR56(),
.VAR44(),
.VAR233(),
.VAR377(),
.VAR267(),
.VAR165(),
.VAR143(),
.VAR190(),
.VAR221(),
.VAR223(),
.VAR354(),
.VAR72(),
.VAR241(),
.VAR175(),
.VAR87(),
.VAR302(),
.VAR294(),
.VAR353(),
.VAR91(),
.VAR10(),
.VAR106(),
.VAR382(),
.VAR122(),
.VAR321(),
.VAR342(),
.VAR167(),
.VAR84(),
.VAR356(),
.VAR75(),
.VAR269(),
.VAR155(),
.VAR373(),
.VAR250(),
.VAR222(),
.VAR137(),
.VAR277(),
.VAR37(),
.VAR240(),
.VAR124(),
.VAR296(),
.VAR19(),
.VAR268(),
.VAR333(),
.VAR355(),
.VAR303(),
.VAR183(),
.VAR414(),
.VAR26(),
.VAR15(),
.VAR181(),
.VAR349(),
.VAR265(),
.VAR52(),
.VAR16(),
.VAR327(),
.VAR368(),
.VAR148(),
.VAR41(),
.VAR407(),
.VAR328(),
.VAR345(),
.VAR323(),
.VAR308(),
.VAR413(),
.VAR112(),
.VAR305(),
.VAR135(),
.VAR266(),
.VAR12(),
.VAR6(),
.VAR127(),
.VAR145(),
.VAR94(),
.VAR249(),
.VAR231(),
.VAR379(),
.VAR141(),
.VAR248(),
.VAR191(),
.VAR264(),
.VAR169(),
.VAR126(),
.VAR282(),
.VAR27(),
.VAR405(),
.VAR92(),
.VAR237()
);
endmodule
|
mit
|
open-power/snap
|
actions/hdl_helloworld/hw/hdl/fifo_axi_lcl.v
| 4,215 |
module MODULE1(
input clk ,
input VAR12,
input VAR15 ,
output reg VAR14 ,
output reg VAR22 ,
input VAR20 , output reg VAR13 , input VAR8 ,
input [511:0] din ,
input VAR4 , output VAR18, output reg VAR9 , output [511:0] dout ,
output VAR23 ,
output VAR19,
output reg VAR6
);
reg [04:00] VAR16 ;
reg [04:00] VAR26 ;
wire[04:00] VAR25 ;
wire VAR1 ;
parameter VAR7 = 5'd26,
VAR10 = 5'd16,
VAR17 = 5'd16,
VAR2 = 5'd4;
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR16 <= 5'b0;
else if(VAR15 | VAR18) VAR16 <= 5'b0;
else if(VAR8)
VAR16 <= VAR16 + 5'b1;
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR26 <= 5'b0;
else if(VAR15 | VAR18) VAR26 <= 5'b0;
else if(VAR4)
VAR26 <= VAR26 + 5'b1;
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR6 <= 1'b0;
else if(VAR15 | VAR18) VAR6 <= 1'b0;
else if(VAR20) VAR6 <= 1'b1;
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR13 <= 1'b0;
else if(VAR15)
VAR13 <= 1'b0;
else if(VAR6 | VAR20) VAR13 <= 1'b0;
else if((VAR25 < VAR10) | (VAR25 == VAR10))
VAR13 <= 1'b1;
else if((VAR25 > VAR7) | (VAR25 == VAR7))
VAR13 <= 1'b0;
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR9 <= 1'b0;
else if(VAR15)
VAR9 <= 1'b0;
else if(VAR6) begin
if(VAR18)
VAR9 <= 1'b0;
end
else
VAR9 <= 1'b1;
end
else if((VAR25 < VAR2) | (VAR25 == VAR2))
VAR9 <= 1'b0;
else if((VAR25 > VAR17) | (VAR25 == VAR17))
VAR9 <= 1'b1;
assign VAR18 = VAR4 & VAR6 & (VAR26 == VAR16 - 5'd1);
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR14 <= 1'b0;
else if(VAR15)
VAR14 <= 1'b0;
else if(VAR1 & VAR8)
VAR14 <= 1'b1;
always@(posedge clk or negedge VAR12)
if(~VAR12)
VAR22 <= 1'b0;
else if(VAR15)
VAR22 <= 1'b0;
else if(VAR19 & VAR4)
VAR22 <= 1'b1;
VAR21 VAR5 (
.clk(clk), .rst(~VAR12 | VAR15), .din(din), .VAR3(VAR8), .VAR11(VAR4), .valid(VAR23), .dout(dout), .VAR1(VAR1), .VAR19(VAR19), .VAR24(VAR25) );
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.behavioral.pp.v
| 1,179 |
module MODULE1( VAR1, VAR2, VAR4, VAR5 );
input VAR1;
inout VAR4, VAR5;
output VAR2;
VAR6 VAR3(.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5));
VAR6 VAR7(.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5));
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.behavioral.v
| 1,322 |
module MODULE1( VAR6, VAR4, VAR3, VAR8, VAR7 );
input VAR3, VAR8, VAR4, VAR6;
output VAR7;
VAR2 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7));
VAR2 VAR1(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7));
|
apache-2.0
|
svofski/mahponk
|
src/vga.v
| 6,013 |
module MODULE1(clk, VAR43, VAR76, VAR10, VAR59, VAR46, VAR28, VAR53, VAR33, VAR47, VAR2, VAR55, VAR69, VAR65, VAR7);
input clk;
output VAR43;
output VAR76;
output VAR10;
output VAR59;
output VAR46, VAR28, VAR53;
input VAR33;
output VAR47;
output VAR2;
output VAR55;
output VAR69;
input VAR65;
input VAR7;
wand VAR46;
wand VAR28;
wand VAR53;
parameter VAR14 = 10'd640;
parameter VAR18 = 10'd480;
parameter VAR12 = 10'd64;
parameter VAR19 = 8;
wire VAR54;
wire VAR67;
wire[9:0] VAR26; wire[9:0] VAR68; wire[9:0] VAR9; reg [9:0] VAR64; reg VAR38;
reg VAR66;
reg [6:0] VAR75;
always @(posedge clk) begin
if (VAR75 == 0)
VAR66 <= !VAR66;
VAR75 <= VAR75 - 1'b1;
end
reg [7:0] VAR40;
reg [6:0] VAR6;
reg VAR42;
reg VAR41;
always @(posedge VAR66) begin
VAR40 <= VAR40 - 1'b1;
VAR6 <= VAR6 - 1'b1;
if (VAR6 == 0) VAR6 <= 7'b1100000;
end
always @(posedge clk) VAR42 = VAR40 == 0;
always @(posedge clk) VAR41 = VAR6 == 0;
wire VAR35; wire VAR56; VAR63 VAR63(clk, VAR35, 1);
VAR61 #(8192) VAR16(VAR66, VAR56, VAR65);
VAR61 #(8192) VAR61(VAR66, VAR15, VAR7);
always @(posedge VAR15 or posedge VAR35) begin
if (VAR35)
VAR38 <= 1;
end
else
VAR38 <= !VAR38;
end
assign VAR76 = VAR38;
wire[9:0] VAR73; wire[9:0] VAR58; wire VAR52; wire VAR31, VAR25; VAR4 VAR4(clk, VAR59, VAR10, VAR73, VAR58, VAR52, VAR31, VAR25);
VAR5 #(VAR12, VAR18) VAR5(VAR66, VAR26, VAR68, VAR33, VAR47, VAR55, VAR2);
wire[9:0] VAR21;
VAR24 #(VAR12,VAR18) VAR34(VAR35, VAR42, VAR21, VAR9);
always @(posedge VAR66) begin
VAR64 <= VAR38 ? VAR68 : VAR9;
end
VAR32 VAR29(clk, VAR66, VAR35, VAR56, VAR59, VAR73, VAR58, VAR26, VAR64, VAR41, {VAR67, VAR54, VAR77}, VAR21, VAR69, VAR43);
wire MODULE2;
MODULE2 #(640,480) MODULE2(clk, VAR31, VAR25, VAR58, MODULE2);
reg [3:0] VAR37;
always @(posedge clk) begin
if (VAR73 == VAR14/2 && VAR58[1])
VAR37 = 4;
if (VAR37 != 0) VAR37 = VAR37 - 1'b1;
end
wire VAR60 = VAR37 != 0;
wire VAR3, VAR70, VAR22;
MODULE3 MODULE3(clk, VAR59, VAR10, VAR3, VAR70, VAR22);
reg VAR72, VAR71, VAR13;
always @(negedge clk) begin
VAR72 <= VAR52 & (VAR3 | VAR54 | MODULE2 | VAR67 | VAR77);
VAR71 <= VAR52 & (VAR70 | VAR54 | MODULE2 | VAR67 | VAR60 | VAR77);
VAR13 <= VAR52 & (VAR22 | VAR54 | MODULE2 | VAR67);
end
assign VAR46 = VAR72;
assign VAR28 = VAR71;
assign VAR53 = VAR13;
endmodule
module MODULE2(clk, VAR39, VAR8, VAR58, VAR23);
parameter VAR14 = 0;
parameter VAR18 = 0;
input clk, VAR39, VAR8;
input [9:0] VAR58;
output VAR23;
assign VAR23 = VAR39 | VAR8 | VAR58 == 0 | VAR58 == VAR18 - 1;
endmodule
module MODULE3(clk, VAR74, VAR57, VAR36, VAR51, VAR80);
input clk, VAR74, VAR57;
output VAR36, VAR51, VAR80;
reg VAR62, VAR44;
always @(negedge clk) begin
if (VAR57)
VAR62 <= ~VAR62;
end
else VAR62 <= 0;
end
always @(negedge VAR74) begin
if (VAR57)
VAR44 <= ~VAR44;
end
else VAR44 <= 0;
end
assign VAR36 = (1'b0 & ~(VAR62^VAR44));
assign VAR51 = (1'b0 & (VAR62^VAR44));
assign VAR80 = (1'b1 & (VAR62^VAR44));
endmodule
module MODULE4(VAR78, VAR11, VAR48, VAR49, VAR17, reset, VAR79);
parameter VAR45 = 0;
parameter VAR50 = 16;
input VAR78;
input [9:0]VAR11;
input [9:0]VAR48;
input [9:0]VAR49;
input [9:0]VAR17;
input reset;
output reg VAR79;
always @(posedge VAR78 or posedge reset) begin
if (VAR78) begin
VAR79 <= (VAR11 >= VAR45 && VAR11 <= (VAR45 + VAR50)) && (VAR48+4 >= VAR49 && VAR48-4 <= VAR17);
end
else begin
VAR79 <= 0;
end
end
endmodule
VAR1: MODULE1.VAR20,VAR20 1.27 2007/08/27 22:12:30 VAR30 VAR27
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/buf/sky130_fd_sc_hdll__buf_1.v
| 2,009 |
module MODULE1 (
VAR3 ,
VAR1 ,
VAR2,
VAR6,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR7 ;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
lvd2/zxevo
|
unsupported/solegstar/fpga/current/common/resetter.v
| 1,061 |
module MODULE1(
clk,
VAR1,
VAR3 );
parameter VAR6 = 4;
input clk;
input VAR1;
output VAR3; reg VAR3;
reg [VAR6:0] VAR5;
reg VAR2,VAR4;
begin
begin
begin
|
gpl-3.0
|
horia141/bachelor-thesis
|
prj/components/RegBank/RegBankP2.v
| 3,891 |
module MODULE1(VAR15,reset,VAR13,VAR17,VAR3,VAR20);
input wire VAR15;
input wire reset;
input wire [11:0] VAR13;
input wire VAR17;
output wire [7:0] VAR3;
output wire [7:0] VAR20;
reg [1:0] VAR18;
reg [7:0] VAR23;
reg [7:0] VAR7;
wire [3:0] VAR21;
wire [7:0] VAR22;
reg [256*8-1:0] VAR14;
reg [256*8-1:0] VAR24;
assign VAR3 = VAR23;
assign VAR20 = VAR7;
assign VAR21 = VAR13[11:8];
assign VAR22 = VAR13[7:0];
always @ (posedge VAR15) begin
if (reset) begin
VAR18 <= VAR6;
VAR23 <= 0;
VAR7 <= 0;
end
else begin
case (VAR18)
VAR18 <= VAR16;
VAR23 <= 0;
VAR7 <= 0;
end
if (VAR17) begin
case (VAR21)
VAR18 <= VAR16;
VAR23 <= VAR23;
VAR7 <= VAR7;
end
VAR18 <= VAR16;
VAR23 <= VAR22;
VAR7 <= VAR7;
end
VAR18 <= VAR16;
VAR23 <= VAR23;
VAR7 <= VAR22;
end
default: begin
VAR18 <= VAR4;
VAR23 <= 0;
VAR7 <= 0;
end
endcase end else begin
VAR18 <= VAR16;
VAR23 <= VAR23;
VAR7 <= VAR7;
end end
VAR18 <= VAR4;
VAR23 <= 0;
VAR7 <= 0;
end
default: begin
VAR18 <= VAR4;
VAR23 <= 0;
VAR7 <= 0;
end
endcase end end
always @ * begin
if (VAR17) begin
case (VAR21)
VAR12(VAR14,"VAR25 VAR5");
end
VAR12(VAR14,"VAR25 (VAR10 %2X)",VAR22);
end
VAR12(VAR14,"VAR25 (VAR2 %2X)",VAR22);
end
default: begin
VAR12(VAR14,"VAR25 (? %2X)",VAR22);
end
endcase end else begin
VAR12(VAR14,"VAR9");
end end
always @ * begin
case (VAR18)
VAR12(VAR24,"VAR11");
end
VAR12(VAR24,"VAR1 %2X %2X",VAR23,VAR7);
end
VAR12(VAR24,"VAR8");
end
default: begin
VAR12(VAR24,"?");
end
endcase end VAR19 endmodule
|
mit
|
hly11/CollisionDetectionFPGA
|
hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_1/synth/design_1_auto_us_1.v
| 10,494 |
module MODULE1 (
VAR30,
VAR80,
VAR79,
VAR14,
VAR31,
VAR35,
VAR17,
VAR99,
VAR93,
VAR24,
VAR2,
VAR51,
VAR68,
VAR25,
VAR64,
VAR32,
VAR82,
VAR36,
VAR86,
VAR88,
VAR55,
VAR53,
VAR5,
VAR100,
VAR50,
VAR16,
VAR23,
VAR47,
VAR34,
VAR89,
VAR44,
VAR52,
VAR18,
VAR21,
VAR39,
VAR26,
VAR91,
VAR41,
VAR98,
VAR28
);
input wire VAR30;
input wire VAR80;
input wire [31 : 0] VAR79;
input wire [7 : 0] VAR14;
input wire [2 : 0] VAR31;
input wire [1 : 0] VAR35;
input wire [0 : 0] VAR17;
input wire [3 : 0] VAR99;
input wire [2 : 0] VAR93;
input wire [3 : 0] VAR24;
input wire [3 : 0] VAR2;
input wire VAR51;
output wire VAR68;
input wire [31 : 0] VAR25;
input wire [3 : 0] VAR64;
input wire VAR32;
input wire VAR82;
output wire VAR36;
output wire [1 : 0] VAR86;
output wire VAR88;
input wire VAR55;
output wire [31 : 0] VAR53;
output wire [7 : 0] VAR5;
output wire [2 : 0] VAR100;
output wire [1 : 0] VAR50;
output wire [0 : 0] VAR16;
output wire [3 : 0] VAR23;
output wire [2 : 0] VAR47;
output wire [3 : 0] VAR34;
output wire [3 : 0] VAR89;
output wire VAR44;
input wire VAR52;
output wire [63 : 0] VAR18;
output wire [7 : 0] VAR21;
output wire VAR39;
output wire VAR26;
input wire VAR91;
input wire [1 : 0] VAR41;
input wire VAR98;
output wire VAR28;
VAR60 #(
.VAR15("VAR102"),
.VAR9(0),
.VAR66(1),
.VAR19(0),
.VAR76(32),
.VAR65(32),
.VAR7(64),
.VAR4(1),
.VAR77(0),
.VAR3(0),
.VAR10(1),
.VAR87(2),
.VAR33(0),
.VAR78(16),
.VAR74(1),
.VAR92(3)
) VAR97 (
.VAR30(VAR30),
.VAR80(VAR80),
.VAR58(1'VAR45),
.VAR79(VAR79),
.VAR14(VAR14),
.VAR31(VAR31),
.VAR35(VAR35),
.VAR17(VAR17),
.VAR99(VAR99),
.VAR93(VAR93),
.VAR24(VAR24),
.VAR2(VAR2),
.VAR51(VAR51),
.VAR68(VAR68),
.VAR25(VAR25),
.VAR64(VAR64),
.VAR32(VAR32),
.VAR82(VAR82),
.VAR36(VAR36),
.VAR49(),
.VAR86(VAR86),
.VAR88(VAR88),
.VAR55(VAR55),
.VAR43(1'VAR45),
.VAR69(32'VAR42),
.VAR57(8'VAR96),
.VAR90(3'VAR45),
.VAR73(2'VAR45),
.VAR38(1'VAR45),
.VAR11(4'VAR45),
.VAR56(3'VAR45),
.VAR70(4'VAR45),
.VAR67(4'VAR45),
.VAR62(1'VAR45),
.VAR12(),
.VAR46(),
.VAR72(),
.VAR71(),
.VAR83(),
.VAR37(),
.VAR27(1'VAR45),
.VAR6(1'VAR45),
.VAR75(1'VAR45),
.VAR53(VAR53),
.VAR5(VAR5),
.VAR100(VAR100),
.VAR50(VAR50),
.VAR16(VAR16),
.VAR23(VAR23),
.VAR47(VAR47),
.VAR34(VAR34),
.VAR89(VAR89),
.VAR44(VAR44),
.VAR52(VAR52),
.VAR18(VAR18),
.VAR21(VAR21),
.VAR39(VAR39),
.VAR26(VAR26),
.VAR91(VAR91),
.VAR41(VAR41),
.VAR98(VAR98),
.VAR28(VAR28),
.VAR85(),
.VAR101(),
.VAR13(),
.VAR81(),
.VAR1(),
.VAR94(),
.VAR22(),
.VAR48(),
.VAR20(),
.VAR54(),
.VAR84(1'VAR45),
.VAR29(64'VAR61),
.VAR40(2'VAR45),
.VAR95(1'VAR63),
.VAR8(1'VAR45),
.VAR59()
);
endmodule
|
gpl-2.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/ccx/rtl/pcx_dp0.v
| 15,897 |
module MODULE1(
VAR26, VAR14,
VAR6, VAR51, VAR24, VAR11,
VAR35, VAR46,
VAR29, VAR33, VAR40,
VAR41, VAR45, VAR32,
VAR16, VAR15, VAR31,
VAR36
);
output [7:0] VAR26;
output [VAR22-1:0] VAR14;
input [7:0] VAR33; input [7:0] VAR29; input [7:0] VAR46; input [7:0] VAR35; input [7:0] VAR11; input VAR24; input [7:0] VAR51; input VAR6;
input [VAR22-1:0] VAR40; input [VAR22-1:0] VAR41; input [VAR22-1:0] VAR45; input [VAR22-1:0] VAR32; input [VAR22-1:0] VAR16; input [VAR22-1:0] VAR15; input [VAR22-1:0] VAR31; input [VAR22-1:0] VAR36;
wire [129:0] VAR38; wire [129:0] VAR21; wire [129:0] VAR28; wire [129:0] VAR39; wire [129:0] VAR8; wire [129:0] VAR47; wire [129:0] VAR19; wire [7:1] VAR3;
wire [5:0] VAR23;
VAR4 VAR12(
.VAR44 (VAR38[129:0]), .VAR26 (VAR26[0]), .VAR3 (), .VAR17(VAR35[0]), .VAR5(VAR46[0]), .VAR18(VAR33[0]), .VAR27(VAR11[0]), .VAR30(VAR29[0]), .VAR1 ({6'b000000,VAR40[VAR22-1:0]}), .VAR24 (VAR24),
.VAR51 (VAR51[0]), .VAR6 (VAR3[1]));
VAR13 VAR50(
.VAR44 (VAR21[129:0]), .VAR26 (VAR26[1]), .VAR3 (VAR3[1]), .VAR17(VAR35[1]), .VAR5(VAR46[1]), .VAR18(VAR33[1]), .VAR27(VAR11[1]), .VAR30(VAR29[1]), .VAR1 ({6'b000000,VAR41[VAR22-1:0]}), .VAR42 (VAR38[129:0]), .VAR24 (VAR24),
.VAR51 (VAR51[1]), .VAR6 (VAR3[2])); VAR13 VAR2(
.VAR44 (VAR28[129:0]), .VAR26 (VAR26[2]), .VAR3 (VAR3[2]), .VAR17(VAR35[2]), .VAR5(VAR46[2]), .VAR18(VAR33[2]), .VAR27(VAR11[2]), .VAR30(VAR29[2]), .VAR1 ({6'b000000,VAR45[VAR22-1:0]}), .VAR42 (VAR21[129:0]), .VAR24 (VAR24),
.VAR51 (VAR51[2]), .VAR6 (VAR3[3]));
VAR25 VAR7(
.VAR44 ({VAR23[5:0],VAR14[VAR22-1:0]}), .VAR26 (VAR26[3]), .VAR3 (VAR3[3]), .VAR17(VAR35[3]), .VAR5(VAR46[3]), .VAR18(VAR33[3]), .VAR27(VAR11[3]), .VAR30(VAR29[3]), .VAR1 ({6'b000000,VAR32[VAR22-1:0]}), .VAR10 (VAR39[129:0]), .VAR20 (VAR28[129:0]), .VAR24 (VAR24),
.VAR51 (VAR51[3]), .VAR6 (VAR3[4]));
VAR9 VAR48(
.VAR44 (VAR39[129:0]), .VAR26 (VAR26[4]), .VAR3 (VAR3[4]), .VAR17(VAR35[4]), .VAR5(VAR46[4]), .VAR18(VAR33[4]), .VAR27(VAR11[4]), .VAR30(VAR29[4]), .VAR1 ({6'b000000,VAR16[VAR22-1:0]}), .VAR42 (VAR8[129:0]), .VAR24 (VAR24),
.VAR51 (VAR51[4]), .VAR6 (VAR3[5])); VAR9 VAR34(
.VAR44 (VAR8[129:0]), .VAR26 (VAR26[5]), .VAR3 (VAR3[5]), .VAR17(VAR35[5]), .VAR5(VAR46[5]), .VAR18(VAR33[5]), .VAR27(VAR11[5]), .VAR30(VAR29[5]), .VAR1 ({6'b000000,VAR15[VAR22-1:0]}), .VAR42 (VAR47[129:0]), .VAR24 (VAR24),
.VAR51 (VAR51[5]), .VAR6 (VAR3[6])); VAR9 VAR49(
.VAR44 (VAR47[129:0]), .VAR26 (VAR26[6]), .VAR3 (VAR3[6]), .VAR17(VAR35[6]), .VAR5(VAR46[6]), .VAR18(VAR33[6]), .VAR27(VAR11[6]), .VAR30(VAR29[6]), .VAR1 ({6'b000000,VAR31[VAR22-1:0]}), .VAR42 (VAR19[129:0]), .VAR24 (VAR24),
.VAR51 (VAR51[6]), .VAR6 (VAR3[7]));
VAR37 VAR43(
.VAR44 (VAR19[129:0]), .VAR26 (VAR26[7]), .VAR3 (VAR3[7]), .VAR17(VAR35[7]), .VAR5(VAR46[7]), .VAR18(VAR33[7]), .VAR27(VAR11[7]), .VAR30(VAR29[7]), .VAR1 ({6'b000000,VAR36[VAR22-1:0]}), .VAR24 (VAR24),
.VAR51 (VAR51[7]), .VAR6 (VAR6));
endmodule
|
gpl-2.0
|
agnicol88/Gaussian_Num_Gen
|
Vivado/gng/gng.srcs/sources_1/new/coeff_store.v
| 23,854 |
module MODULE1(
input clk,
input [7:0] addr,
output [17:0] VAR3,
output [17:0] VAR1,
output [20:0] VAR6
);
reg [56:0] VAR2 = 57'd0;
reg [17:0] VAR7 = 18'd0;
reg [17:0] VAR5 = 18'd0;
reg [20:0] VAR4 = 21'd0;
assign VAR3 = VAR7;
assign VAR1 = VAR5;
assign VAR6 = VAR4;
always @ (posedge clk) begin
VAR7 <= VAR2[56:39];
VAR5 <= VAR2[38:21];
VAR4 <= VAR2[20:0];
case (addr)
8'd0 : VAR2 <= 57'b000011111110100110101000000000011001000000000000000000100;
8'd1 : VAR2 <= 57'b001100101001111111101000011111010100000000101000010010000;
8'd2 : VAR2 <= 57'b010111110111100101101010000010010001000001010001100101100;
8'd3 : VAR2 <= 57'b101000111011111100101100111100000011000001111101001001100;
8'd4 : VAR2 <= 57'b001111011010110010011001000111110010000010101100101011001;
8'd5 : VAR2 <= 57'b010100110110100101011011000001110101000011000110110001011;
8'd6 : VAR2 <= 57'b011101010000010110011101100110001111000011100011000111110;
8'd7 : VAR2 <= 57'b101011011100110101100001001011010101000100000010100100111;
8'd8 : VAR2 <= 57'b001111011001000101010011011000100110000100100110011111101;
8'd9 : VAR2 <= 57'b010100001111101111010101010010100001000100111010110110011;
8'd10 : VAR2 <= 57'b011011110101110100010111110010010000000101010001011010111;
8'd11 : VAR2 <= 57'b101000110010001001011011001100011010000101101010111110010;
8'd12 : VAR2 <= 57'b001110010110010011010000001110000001000110001000101111010;
8'd13 : VAR2 <= 57'b010010110100001001010001111111101100000110011001110111010;
8'd14 : VAR2 <= 57'b011001110100101001010100010100001001000110101101000011001;
8'd15 : VAR2 <= 57'b100101110011000101010111011110011110000111000011000000010;
8'd16 : VAR2 <= 57'b001101010011010010001110001010110001000111011100110111010;
8'd17 : VAR2 <= 57'b010001011100111101001111110100001000000111101011110111110;
8'd18 : VAR2 <= 57'b010111111110100011010001111101110100000111111100110010100;
8'd19 : VAR2 <= 57'b100011001001101010010100111001101010001000010000010001110;
8'd20 : VAR2 <= 57'b001100011000110111001100101101011110001000100111011001010;
8'd21 : VAR2 <= 57'b010000010001101000001110001111100110001000110100111000111;
8'd22 : VAR2 <= 57'b010110011001010001010000001111111111001001000100001010011;
8'd23 : VAR2 <= 57'b100000111001000100010010111111011001001001010101110101011;
8'd24 : VAR2 <= 57'b001011100111001000001011100111000100001001101010111001100;
8'd25 : VAR2 <= 57'b001111010001100011001101000011000001001001110111001111100;
8'd26 : VAR2 <= 57'b010101000011000101001110111011100000001010000101010000011;
8'd27 : VAR2 <= 57'b011110111101111011010001100000010101001010010101100001011;
8'd28 : VAR2 <= 57'b001010111100101100001010101111101000001010101000111110110;
8'd29 : VAR2 <= 57'b001110011010110011001100000110010101001010110100011010101;
8'd30 : VAR2 <= 57'b010011111001010100001101111000000011001011000001011011011;
8'd31 : VAR2 <= 57'b011101010100001111010000010011110101001011010000100100010;
8'd32 : VAR2 <= 57'b001010011000001100001010000010100110001011100010101110011;
8'd33 : VAR2 <= 57'b001101101011100111001011010100110001001011101101011011000;
8'd34 : VAR2 <= 57'b010010111001100100001101000000101010001011111001100111001;
8'd35 : VAR2 <= 57'b011011111000101001001111010100101000001100000111110100101;
8'd36 : VAR2 <= 57'b001001111000011111001001011101000111001100011000111001111;
8'd37 : VAR2 <= 57'b001101000010100001001010101011010111001100100010111110111;
8'd38 : VAR2 <= 57'b010010000001111100001100010010001100001100101110011111001;
8'd39 : VAR2 <= 57'b011010101000100000001110011111010101001100111011111010100;
8'd40 : VAR2 <= 57'b001001011100101010001000111101010100001101001100000101011;
8'd41 : VAR2 <= 57'b001100011110011010001010001000000111001101010101101000111;
8'd42 : VAR2 <= 57'b010001010000111011001011101010011111001101100000100011100;
8'd43 : VAR2 <= 57'b011001100001101101001101110001101000001101101101010100010;
8'd44 : VAR2 <= 57'b001001000100000010001000100001111010001101111100101100111;
8'd45 : VAR2 <= 57'b001011111110011001001001101001101011001110000101110011011;
8'd46 : VAR2 <= 57'b010000100101011001001011001000000101001110010000001101101;
8'd47 : VAR2 <= 57'b011000100010101011001101001001111000001110011100011001001;
8'd48 : VAR2 <= 57'b001000101110000100001000001010000000001110101011000110000;
8'd49 : VAR2 <= 57'b001011100001110001001001001111000010001110110011110011010;
8'd50 : VAR2 <= 57'b001111111110011010001010101001111010001110111101110001000;
8'd51 : VAR2 <= 57'b010111101010001000001100100110111100001111001001011011111;
8'd52 : VAR2 <= 57'b001000011010010100000111110100111001001111010111100010011;
8'd53 : VAR2 <= 57'b001011001000000001001000110111011110001111011111111001010;
8'd54 : VAR2 <= 57'b001111011011010010001010001111001100001111101001011101110;
8'd55 : VAR2 <= 57'b010110110111000011001100000111111010001111110100101011110;
8'd56 : VAR2 <= 57'b001000001000011100000111100010000110010000000010001111111;
8'd57 : VAR2 <= 57'b001010110000101100001000100010011110010000001010010010111;
8'd58 : VAR2 <= 57'b001110111011011010001001110111010011010000010011100000111;
8'd59 : VAR2 <= 57'b010110001000101000001011101100000111010000011110010100111;
8'd60 : VAR2 <= 57'b000111111000001100000111010001001101010000101011011010011;
8'd61 : VAR2 <= 57'b001010011011011100001000001111100101010000110011001011011;
8'd62 : VAR2 <= 57'b001110011110010101001001100001110010010000111100000101010;
8'd63 : VAR2 <= 57'b010101011110001111001011010011000010010001000110100001111;
8'd64 : VAR2 <= 57'b000111101001010100000111000001111101010001010011001011101;
8'd65 : VAR2 <= 57'b001010000111111110000111111110011110010001011010101100100;
8'd66 : VAR2 <= 57'b001110000011101100001001001110010010010001100011010100000;
8'd67 : VAR2 <= 57'b010100110111010101001010111100010010010001101101011011011;
8'd68 : VAR2 <= 57'b000111011011101010000110110100000100010001111001101011111;
8'd69 : VAR2 <= 57'b001001110110000101000111101110111001010010000000111110000;
8'd70 : VAR2 <= 57'b001101101011001010001000111100100000010010001001010100111;
8'd71 : VAR2 <= 57'b010100010011011101001010100111011111010010010011001000111;
8'd72 : VAR2 <= 57'b000111001111000011000110100111010111010010011111000010011;
8'd73 : VAR2 <= 57'b001001100101100011000111100000101001010010100110000111000;
8'd74 : VAR2 <= 57'b001101010100011110001000101100001101010010101110001110100;
8'd75 : VAR2 <= 57'b010011110010010000001010010100011010010010110111110000111;
8'd76 : VAR2 <= 57'b000111000011010111000110011011101100010011000011010101001;
8'd77 : VAR2 <= 57'b001001010110001110000111010011100001010011001010001101011;
8'd78 : VAR2 <= 57'b001100111111011010001000011101001101010011010010000110110;
8'd79 : VAR2 <= 57'b010011010011011010001010000010110101010011011011011000110;
8'd80 : VAR2 <= 57'b000110111000100000000110010000111011010011100110101001100;
8'd81 : VAR2 <= 57'b001001000111111101000111000111011010010011101101010110010;
8'd82 : VAR2 <= 57'b001100101011110100001000001111010100010011110101000010101;
8'd83 : VAR2 <= 57'b010010110110101011001001110010100011010011111110000101100;
8'd84 : VAR2 <= 57'b000110101110010111000110000110111100010100001001000100010;
8'd85 : VAR2 <= 57'b001000111010101010000110111100001010010100001111100110011;
8'd86 : VAR2 <= 57'b001100011001100000001000000010011100010100010111000110101;
8'd87 : VAR2 <= 57'b010010011011110011001001100011011100010100011111111011100;
8'd88 : VAR2 <= 57'b000110100100111001000101111101101001010100101010101001011;
8'd89 : VAR2 <= 57'b001000101110001100000110110001101101010100110001000001101;
8'd90 : VAR2 <= 57'b001100001000010111000111110110011100010100111000010110101;
8'd91 : VAR2 <= 57'b010010000010100111001001010101010101010101000000111110011;
8'd92 : VAR2 <= 57'b000110011100000000000101110100111110010101001011011100100;
8'd93 : VAR2 <= 57'b001000100010100000000110100111111011010101010001101011100;
8'd94 : VAR2 <= 57'b001011111000010000000111101011001111010101011000110110001;
8'd95 : VAR2 <= 57'b010001101010111011001001001000001010010101100001010001101;
8'd96 : VAR2 <= 57'b000110010011101001000101101100110111010101101011100001001;
8'd97 : VAR2 <= 57'b001000010111100000000110011110110010010101110001100111100;
8'd98 : VAR2 <= 57'b001011101001000110000111100000101111010101111000101000001;
8'd99 : VAR2 <= 57'b010001010100101000001000111011110011010110000000111000010;
8'd100 : VAR2 <= 57'b000110001011110000000101100101010000010110001010111010000;
8'd101 : VAR2 <= 57'b001000001101001000000110010110001100010110010000111000010;
8'd102 : VAR2 <= 57'b001011011010110010000111010110110111010110010111101111101;
8'd103 : VAR2 <= 57'b010000111111100100001000110000001011010110011111110101000;
8'd104 : VAR2 <= 57'b000110000100010100000101011110000101010110101001101001110;
8'd105 : VAR2 <= 57'b001000000011010100000110001110000111010110101111100000011;
8'd106 : VAR2 <= 57'b001011001101010000000111001101100100010110110110001111001;
8'd107 : VAR2 <= 57'b010000101011101001001000100101001111010110111110001010010;
8'd108 : VAR2 <= 57'b000101111101010000000101010111010101010111000111110010111;
8'd109 : VAR2 <= 57'b000111111010000010000110000110011111010111001101100010010;
8'd110 : VAR2 <= 57'b001011000000011100000111000100110011010111010100001000110;
8'd111 : VAR2 <= 57'b010000011000110001001000011010111001010111011011111010011;
8'd112 : VAR2 <= 57'b000101110110100101000101010000111100010111100101010111011;
8'd113 : VAR2 <= 57'b000111110001001110000101111111010001010111101011000000000;
8'd114 : VAR2 <= 57'b001010110100010010000110111100100000010111110001011110110;
8'd115 : VAR2 <= 57'b010000000110110101001000010001000111010111111001000111010;
8'd116 : VAR2 <= 57'b000101110000001110000101001010111010011000000010011001011;
8'd117 : VAR2 <= 57'b000111101000110110000101111000011100011000000111111011100;
8'd118 : VAR2 <= 57'b001010101000101101000110110100101001011000001110010010111;
8'd119 : VAR2 <= 57'b001111110101110001001000000111110101011000010101110010110;
8'd120 : VAR2 <= 57'b000101101010001011000101000101001010011000011110111010101;
8'd121 : VAR2 <= 57'b000111100000111000000101110001111101011000100100010110101;
8'd122 : VAR2 <= 57'b001010011101101101000110101101001011011000101010100111000;
8'd123 : VAR2 <= 57'b001111100101100001000111111111000001011000110001111110110;
8'd124 : VAR2 <= 57'b000101100100011011000100111111101101011000111010111100101;
8'd125 : VAR2 <= 57'b000111011001010010000101101011110010011001000000010010111;
8'd126 : VAR2 <= 57'b001010010011001100000110100110000100011001000110011100101;
8'd127 : VAR2 <= 57'b001111010110000001000111110110101000011001001101101100101;
8'd128 : VAR2 <= 57'b000101011110111011000100111010100001011001010110100001010;
8'd129 : VAR2 <= 57'b000111010010000010000101100101111011011001011011110001111;
8'd130 : VAR2 <= 57'b001010001001001010000110011111010011011001100001110101011;
8'd131 : VAR2 <= 57'b001111000111001100000111101110101001011001101000111101111;
8'd132 : VAR2 <= 57'b000101011001101011000100110101100101011001110001101001100;
8'd133 : VAR2 <= 57'b000111001011000110000101100000010100011001110110110100111;
8'd134 : VAR2 <= 57'b001001111111100100000110011000110110011001111100110010011;
8'd135 : VAR2 <= 57'b001110111001000001000111100111000001011010000011110011111;
8'd136 : VAR2 <= 57'b000101010100101001000100110000110110011010001100010110111;
8'd137 : VAR2 <= 57'b000111000100011101000101011010111110011010010001011101010;
8'd138 : VAR2 <= 57'b001001110110011001000110010010101100011010010111010100111;
8'd139 : VAR2 <= 57'b001110101011011100000111011111101110011010011110001111101;
8'd140 : VAR2 <= 57'b000101001111110101000100101100010101011010100110101010101;
8'd141 : VAR2 <= 57'b000110111110000110000101010101110111011010101011101100010;
8'd142 : VAR2 <= 57'b001001101101100101000110001100110010011010110001011110011;
8'd143 : VAR2 <= 57'b001110011110011011000111011000110000011010111000010010101;
8'd144 : VAR2 <= 57'b000101001011001101000100101000000000011011000000100101110;
8'd145 : VAR2 <= 57'b000110110111111111000101010000111110011011000101100010110;
8'd146 : VAR2 <= 57'b001001100101001000000110000111001001011011001011001111100;
8'd147 : VAR2 <= 57'b001110010001111011000111010010000100011011010001111101101;
8'd148 : VAR2 <= 57'b000101000110110001000100100011110111011011011010001001011;
8'd149 : VAR2 <= 57'b000110110010001000000101001100010001011011011111000001111;
8'd150 : VAR2 <= 57'b001001011101000000000110000001101110011011100100101001101;
8'd151 : VAR2 <= 57'b001110000101111010000111001011101010011011101011010001110;
8'd152 : VAR2 <= 57'b000101000010100000000100011111111000011011110011010110011;
8'd153 : VAR2 <= 57'b000110101100011111000101000111110001011011111000001010101;
8'd154 : VAR2 <= 57'b001001010101001100000101111100100001011011111101101101100;
8'd155 : VAR2 <= 57'b001101111010010110000111000101100000011100000100010000000;
8'd156 : VAR2 <= 57'b000100111110011001000100011100000100011100001100001101101;
8'd157 : VAR2 <= 57'b000110100111000011000101000011011100011100010000111101110;
8'd158 : VAR2 <= 57'b001001001101101011000101110111100001011100010110011100000;
8'd159 : VAR2 <= 57'b001101101111001110000110111111100101011100011100111001000;
8'd160 : VAR2 <= 57'b000100111010011100000100011000011001011100100100110000000;
8'd161 : VAR2 <= 57'b000110100001110101000100111111010001011100101001011100010;
8'd162 : VAR2 <= 57'b001001000110011011000101110010101110011100101110110110000;
8'd163 : VAR2 <= 57'b001101100100100000000110111001111001011100110101001101110;
8'd164 : VAR2 <= 57'b000100110110101000000100010100110110011100111100111110011;
8'd165 : VAR2 <= 57'b000110011100110010000100111011010001011101000001100110111;
8'd166 : VAR2 <= 57'b001000111111011100000101101110000101011101000110111100010;
8'd167 : VAR2 <= 57'b001101011010001001000110110100011010011101001101001111000;
8'd168 : VAR2 <= 57'b000100110010111100000100010001011100011101010100111001100;
8'd169 : VAR2 <= 57'b000110010111111011000100110111011001011101011001011110010;
8'd170 : VAR2 <= 57'b001000111000101101000101101001101000011101011110101111100;
8'd171 : VAR2 <= 57'b001101010000001010000110101111000111011101100100111101010;
8'd172 : VAR2 <= 57'b000100101111011001000100001110001010011101101100100001111;
8'd173 : VAR2 <= 57'b000110010011001110000100110011101011011101110001000011010;
8'd174 : VAR2 <= 57'b001000110010001100000101100101010100011101110110010000100;
8'd175 : VAR2 <= 57'b001101000110100000000110101010000001011101111100011001100;
8'd176 : VAR2 <= 57'b000100101011111101000100001010111111011110000011111000011;
8'd177 : VAR2 <= 57'b000110001110101011000100110000000101011110001000010110011;
8'd178 : VAR2 <= 57'b001000101011111000000101100001001010011110001101011111101;
8'd179 : VAR2 <= 57'b001100111101001011000110100101000101011110010011100100001;
8'd180 : VAR2 <= 57'b000100101000101001000100000111111011011110011010111101100;
8'd181 : VAR2 <= 57'b000110001010010010000100101100100110011110011111011000001;
8'd182 : VAR2 <= 57'b001000100101110010000101011101001001011110100100011101110;
8'd183 : VAR2 <= 57'b001100110100001000000110100000010101011110101010011101111;
8'd184 : VAR2 <= 57'b000100100101011011000100000100111101011110110001110001111;
8'd185 : VAR2 <= 57'b000110000110000010000100101001001111011110110110001001011;
8'd186 : VAR2 <= 57'b001000011111111001000101011001010001011110111011001011011;
8'd187 : VAR2 <= 57'b001100101011011001000110011011101110011111000001000111001;
8'd188 : VAR2 <= 57'b000100100010010100000100000010000110011111001000010110000;
8'd189 : VAR2 <= 57'b000110000001111010000100100101111111011111001100101010100;
8'd190 : VAR2 <= 57'b001000011010001011000101010101100000011111010001101000111;
8'd191 : VAR2 <= 57'b001100100010111010000110010111010001011111010111100000101;
8'd192 : VAR2 <= 57'b000100011111010011000011111111010100011111011110101010100;
8'd193 : VAR2 <= 57'b000101111101111011000100100010110110011111100010111100000;
8'd194 : VAR2 <= 57'b001000010100101000000101010001110111011111100111110111000;
8'd195 : VAR2 <= 57'b001100011010101100000110010010111101011111101101101010110;
8'd196 : VAR2 <= 57'b000100011100010111000011111100101000011111110100101111110;
8'd197 : VAR2 <= 57'b000101111010000011000100011111110011011111111000111110011;
8'd198 : VAR2 <= 57'b001000001111010000000101001110010110011111111101110110001;
8'd199 : VAR2 <= 57'b001100010010101110000110001110110001100000000011100110000;
8'd200 : VAR2 <= 57'b000100011001100010000011111010000001100000001010100110011;
8'd201 : VAR2 <= 57'b000101110110010010000100011100110110100000001110110010001;
8'd202 : VAR2 <= 57'b001000001010000010000101001010111011100000010011100110110;
8'd203 : VAR2 <= 57'b001100001010111110000110001010101101100000011001010010111;
8'd204 : VAR2 <= 57'b000100010110110001000011110111100000100000100000001110101;
8'd205 : VAR2 <= 57'b000101110010101001000100011001111110100000100100010111110;
8'd206 : VAR2 <= 57'b001000000100111110000101000111100111100000101001001001010;
8'd207 : VAR2 <= 57'b001100000011011101000110000110110001100000101110110001101;
8'd208 : VAR2 <= 57'b000100010100000110000011110101000011100000110101101001001;
8'd209 : VAR2 <= 57'b000101101111000110000100010111001100100000111001101111101;
8'd210 : VAR2 <= 57'b001000000000000011000101000100011001100000111110011110000;
8'd211 : VAR2 <= 57'b001011111100001010000110000010111101100001000100000011000;
8'd212 : VAR2 <= 57'b000100010001011111000011110010101010100001001010110110001;
8'd213 : VAR2 <= 57'b000101101011101001000100010100011111100001001110111010001;
8'd214 : VAR2 <= 57'b000111111011010001000101000001010000100001010011100101101;
8'd215 : VAR2 <= 57'b001011110101000011000101111111001111100001011001000111001;
8'd216 : VAR2 <= 57'b000100001110111110000011110000010110100001011111110110000;
8'd217 : VAR2 <= 57'b000101101000010010000100010001110111100001100011110111100;
8'd218 : VAR2 <= 57'b000111110110100111000100111110001110100001101000100000010;
8'd219 : VAR2 <= 57'b001011101110001000000101111011101000100001101101111110011;
8'd220 : VAR2 <= 57'b000100001100100000000011101110000110100001110100101001010;
8'd221 : VAR2 <= 57'b000101100101000010000100001111010011100001111000101000011;
8'd222 : VAR2 <= 57'b000111110010000101000100111011010001100001111101001110010;
8'd223 : VAR2 <= 57'b001011100111011010000101111000001000100010000010101001010;
8'd224 : VAR2 <= 57'b000100001010000110000011101011111010100010001001010000010;
8'd225 : VAR2 <= 57'b000101100001110110000100001100110100100010001101001101000;
8'd226 : VAR2 <= 57'b000111101101101010000100111000011001100010010001110000001;
8'd227 : VAR2 <= 57'b001011100000110111000101110100101101100010010111001000000;
8'd228 : VAR2 <= 57'b000100000111110001000011101001110010100010011101101011001;
8'd229 : VAR2 <= 57'b000101011110110000000100001010011010100010100001100101101;
8'd230 : VAR2 <= 57'b000111101001010111000100110101100110100010100110000110010;
8'd231 : VAR2 <= 57'b001011011010011110000101110001011000100010101011011010111;
8'd232 : VAR2 <= 57'b000100000101011111000011100111101110100010110001111010011;
8'd233 : VAR2 <= 57'b000101011011110000000100001000000011100010110101110010101;
8'd234 : VAR2 <= 57'b000111100101001011000100110010110111100010111010010000101;
8'd235 : VAR2 <= 57'b001011010100010000000101101110001001100010111111100010011;
8'd236 : VAR2 <= 57'b000100000011010010000011100101101100100011000101111110001;
8'd237 : VAR2 <= 57'b000101011000110011000100000101110000100011001001110100010;
8'd238 : VAR2 <= 57'b000111100001000110000100110000001101100011001110001111111;
8'd239 : VAR2 <= 57'b001011001110001100000101101010111111100011010011011110101;
8'd240 : VAR2 <= 57'b000100000001000111000011100011101110100011011001110110111;
8'd241 : VAR2 <= 57'b000101010101111100000100000011100001100011011101101010111;
8'd242 : VAR2 <= 57'b000111011101000111000100101101101000100011100010000100000;
8'd243 : VAR2 <= 57'b001011001000010001000101100111111010100011100111010000000;
8'd244 : VAR2 <= 57'b000011111111000000000011100001110100100011101101100100111;
8'd245 : VAR2 <= 57'b000101010011001001000100000001010110100011110001010110110;
8'd246 : VAR2 <= 57'b000111011001001110000100101011000110100011110101101101101;
8'd247 : VAR2 <= 57'b001011000010011111000101100100111010100011111010110110110;
default: VAR2 <= 57'd0;
endcase
end
endmodule
|
gpl-3.0
|
ShepardSiegel/ocpi
|
coregen/dram_v6_mig37/mig_37/example_design/rtl/traffic_gen/afifo.v
| 6,916 |
module MODULE1 #
(
parameter VAR25 = 100,
parameter VAR32 = 32,
parameter VAR15 = 16,
parameter VAR39 = 4,
parameter VAR10 = 1 )
(
input VAR3,
input rst,
input VAR23,
input [VAR32-1:0] VAR40,
input VAR37,
input VAR16,
output [VAR32-1:0] VAR17,
output reg VAR34,
output reg VAR36,
output reg VAR33
);
reg [VAR32-1:0] VAR28 [0:VAR15-1];
reg [VAR39:0] VAR9;
reg [VAR39:0] VAR24;
reg [VAR39:0] VAR4;
reg [VAR39:0] VAR13;
reg [VAR39:0] VAR11;
reg [VAR39:0] VAR8;
reg [VAR39:0] VAR6;
reg [VAR39:0] VAR26;
reg [VAR39:0] VAR41;
reg [VAR39:0] VAR30;
wire [VAR39:0] VAR1;
wire [VAR39:0] VAR7;
wire [VAR39-1:0] VAR21, VAR31;
reg [VAR39:0] VAR38, VAR5;
integer VAR27,VAR22,VAR2;
generate
if (VAR10 == 1) begin: VAR18
always @ (VAR5)
VAR4 = VAR5;
end
endgenerate
generate
if (VAR10 == 1) begin: VAR14
always @ (VAR38)
VAR26 = VAR38;
end
endgenerate
assign VAR21 = VAR38;
assign VAR17 = VAR28[VAR31];
always @(posedge VAR3)
begin
if (VAR23 && !VAR34)
end
assign VAR31 = VAR5[VAR39-1:0];
assign VAR20 = VAR37 && !VAR36;
integer VAR19;
reg [VAR39:0] VAR12;
always @ (VAR5)
begin
VAR9[VAR39] = VAR5[VAR39];
for (VAR19=0; VAR19 < VAR39; VAR19=VAR19+1)
VAR9[VAR19] = VAR5[VAR19] ^ VAR5[VAR19+1];
end
always @(posedge VAR16)
begin
if (rst)
begin
end
else begin
if (VAR20)
end
end
assign VAR7 = VAR26 - VAR5;
always @ (posedge VAR16 )
begin
if (rst)
end
else if ((VAR7 == 0) || (VAR7 == 1 && VAR20))
else
end
reg [VAR39:0] VAR35;
wire [VAR39:0] VAR42, VAR29;
always @(posedge VAR16)
begin
if (rst)
begin
end
else begin
if (VAR23)
end
end
always @ (VAR38)
begin
VAR6[VAR39] = VAR38[VAR39];
for (VAR19=0; VAR19 < VAR39; VAR19=VAR19+1)
VAR6[VAR19] = VAR38[VAR19] ^ VAR38[VAR19+1];
end
assign VAR1 = (VAR4 + VAR15) - VAR38;
always @ (posedge VAR3 )
begin
if (rst)
end
else if ((VAR1 == 0) || (VAR1 == 1 && VAR23))
else
end
always @ (posedge VAR3 )
begin
if (rst)
end
else if ((VAR1 == VAR15 - 2 ) || ((VAR1 == VAR15 -3) && VAR23))
else
end
endmodule
|
lgpl-3.0
|
jimurai/okWishboneMaster
|
verilog/dp_ram.v
| 1,108 |
module MODULE1 #(
parameter VAR8 = 16,
parameter VAR13 = 10
) (
input wire VAR7,
input wire VAR12,
input wire [VAR13-1:0] VAR4,
input wire [VAR8-1:0] VAR1,
output reg [VAR8-1:0] VAR11,
input wire VAR3,
input wire VAR6,
input wire [VAR13-1:0] VAR2,
input wire [VAR8-1:0] VAR9,
output reg [VAR8-1:0] VAR10
);
reg [VAR8-1:0] VAR5 [(2**VAR13)-1:0];
always @(posedge VAR7) begin
VAR11 <= VAR5[VAR4];
if(VAR12) begin
VAR11 <= VAR1;
VAR5[VAR4] <= VAR1;
end
end
always @(posedge VAR3) begin
VAR10 <= VAR5[VAR2];
if(VAR6) begin
VAR10 <= VAR9;
VAR5[VAR2] <= VAR9;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/or4b/sky130_fd_sc_hdll__or4b.functional.pp.v
| 1,998 |
module MODULE1 (
VAR10 ,
VAR11 ,
VAR9 ,
VAR17 ,
VAR16 ,
VAR12,
VAR2,
VAR8 ,
VAR15
);
output VAR10 ;
input VAR11 ;
input VAR9 ;
input VAR17 ;
input VAR16 ;
input VAR12;
input VAR2;
input VAR8 ;
input VAR15 ;
wire VAR3 ;
wire VAR14 ;
wire VAR5;
not VAR1 (VAR3 , VAR16 );
or VAR7 (VAR14 , VAR3, VAR17, VAR9, VAR11 );
VAR6 VAR13 (VAR5, VAR14, VAR12, VAR2);
buf VAR4 (VAR10 , VAR5 );
endmodule
|
apache-2.0
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/imports/hdl/daala_idct4_mmap_v1_0_S00_AXI.v
| 14,666 |
module MODULE1 #
(
parameter integer VAR39 = 32,
parameter integer VAR22 = 4
)
(
input wire VAR23,
input wire VAR27,
input wire [VAR22-1 : 0] VAR16,
input wire [2 : 0] VAR26,
input wire VAR53,
output wire VAR32,
input wire [VAR39-1 : 0] VAR52,
input wire [(VAR39/8)-1 : 0] VAR10,
input wire VAR18,
output wire VAR6,
output wire [1 : 0] VAR7,
output wire VAR21,
input wire VAR57,
input wire [VAR22-1 : 0] VAR45,
input wire [2 : 0] VAR47,
input wire VAR51,
output wire VAR25,
output wire [VAR39-1 : 0] VAR9,
output wire [1 : 0] VAR31,
output wire VAR59,
input wire VAR48
);
reg [VAR22-1 : 0] VAR24;
reg VAR38;
reg VAR14;
reg [1 : 0] VAR11;
reg VAR49;
reg [VAR22-1 : 0] VAR44;
reg VAR41;
reg [VAR39-1 : 0] VAR55;
reg [1 : 0] VAR34;
reg VAR40;
localparam integer VAR20 = (VAR39/32) + 1;
localparam integer VAR13 = 1;
reg [VAR39-1:0] VAR15;
reg [VAR39-1:0] VAR46;
reg [VAR39-1:0] VAR61;
reg [VAR39-1:0] VAR2;
wire VAR56;
wire VAR30;
reg [VAR39-1:0] VAR54;
integer VAR29;
assign VAR32 = VAR38;
assign VAR6 = VAR14;
assign VAR7 = VAR11;
assign VAR21 = VAR49;
assign VAR25 = VAR41;
assign VAR9 = VAR55;
assign VAR31 = VAR34;
assign VAR59 = VAR40;
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR38 <= 1'b0;
end
else
begin
if (~VAR38 && VAR53 && VAR18)
begin
VAR38 <= 1'b1;
end
else
begin
VAR38 <= 1'b0;
end
end
end
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR24 <= 0;
end
else
begin
if (~VAR38 && VAR53 && VAR18)
begin
VAR24 <= VAR16;
end
end
end
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR14 <= 1'b0;
end
else
begin
if (~VAR14 && VAR18 && VAR53)
begin
VAR14 <= 1'b1;
end
else
begin
VAR14 <= 1'b0;
end
end
end
assign VAR30 = VAR14 && VAR18 && VAR38 && VAR53;
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR15 <= 0;
VAR46 <= 0;
VAR61 <= 0;
VAR2 <= 0;
end
else begin
if (VAR30)
begin
case ( VAR24[VAR20+VAR13:VAR20] )
2'h0:
for ( VAR29 = 0; VAR29 <= (VAR39/8)-1; VAR29 = VAR29+1 )
if ( VAR10[VAR29] == 1 ) begin
VAR15[(VAR29*8) +: 8] <= VAR52[(VAR29*8) +: 8];
end
2'h1:
for ( VAR29 = 0; VAR29 <= (VAR39/8)-1; VAR29 = VAR29+1 )
if ( VAR10[VAR29] == 1 ) begin
VAR46[(VAR29*8) +: 8] <= VAR52[(VAR29*8) +: 8];
end
default : begin
end
endcase
end
end
end
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR49 <= 0;
VAR11 <= 2'b0;
end
else
begin
if (VAR38 && VAR53 && ~VAR49 && VAR14 && VAR18)
begin
VAR49 <= 1'b1;
VAR11 <= 2'b0; end else
begin
if (VAR57 && VAR49)
begin
VAR49 <= 1'b0;
end
end
end
end
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR41 <= 1'b0;
VAR44 <= 32'b0;
end
else
begin
if (~VAR41 && VAR51)
begin
VAR41 <= 1'b1;
VAR44 <= VAR45;
end
else
begin
VAR41 <= 1'b0;
end
end
end
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR40 <= 0;
VAR34 <= 0;
end
else
begin
if (VAR41 && VAR51 && ~VAR40)
begin
VAR40 <= 1'b1;
VAR34 <= 2'b0; end
else if (VAR40 && VAR48)
begin
VAR40 <= 1'b0;
end
end
end
reg signed[15:0] VAR43, VAR58, VAR50, VAR37;
assign VAR56 = VAR41 & VAR51 & ~VAR40;
always @(*)
begin
if ( VAR27 == 1'b0 )
begin
VAR54 <= 0;
end
else
begin
case ( VAR44[VAR20+VAR13:VAR20] )
2'h0 : VAR54 <= VAR15;
2'h1 : VAR54 <= VAR46;
2'h2 : VAR54 <= {VAR43,VAR58};
2'h3 : VAR54 <= {VAR50,VAR37};
default : VAR54 <= 0;
endcase
end
end
always @( posedge VAR23 )
begin
if ( VAR27 == 1'b0 )
begin
VAR55 <= 0;
end
else
begin
if (VAR56)
begin
VAR55 <= VAR54; end
end
end
wire signed [15:0] VAR12, VAR4, VAR33, VAR60;
assign VAR12 = VAR15[31:16];
assign VAR4 = VAR15[15:0];
assign VAR33 = VAR46[31:16];
assign VAR60 = VAR46[15:0];
reg signed [31:0] VAR19;
reg signed [31:0] VAR42;
reg signed [31:0] VAR36;
reg signed [31:0] VAR3;
reg signed [31:0] VAR28;
always @(posedge VAR23)
begin
VAR19 = VAR12;
VAR42 = VAR4;
VAR36 = VAR33;
VAR28 = VAR60;
VAR28 = VAR28 + ((VAR42*16'VAR1+16'VAR8)>>>14);
VAR42 = VAR42 - ((VAR28*16'VAR5+16'VAR17)>>>15);
VAR28 = VAR28 + ((VAR42*16'VAR35+16'VAR17)>>>15);
VAR36 = VAR19 - VAR36;
VAR3 = VAR36 >>> 1;
VAR19 = VAR19 - (VAR3 - (VAR28 >>> 1));
VAR42 = VAR3 - VAR42;
VAR43 = VAR19;
VAR58 = VAR36-VAR42;
VAR50 = VAR42;
VAR37 = VAR19 - VAR28;
end
endmodule
|
bsd-2-clause
|
asicguy/gplgpu
|
hdl/altera_plls/pix_pll_bt_bb.v
| 12,245 |
module MODULE1 (
VAR3,
VAR5,
VAR1,
VAR4,
VAR2);
input VAR3;
input VAR5;
output VAR1;
output VAR4;
output VAR2;
tri0 VAR3;
endmodule
|
gpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block.v
| 2,320 |
module MODULE1
(
VAR2,
VAR8,
VAR4,
VAR10,
VAR14
);
input signed [17:0] VAR2; input signed [35:0] VAR8; input signed [17:0] VAR4; output signed [35:0] VAR10; output VAR14;
wire signed [35:0] VAR3; wire VAR6;
wire signed [35:0] VAR7; wire VAR5;
wire signed [35:0] VAR1; wire signed [35:0] VAR9; wire signed [35:0] VAR11; wire signed [35:0] VAR12; wire VAR13;
assign VAR3 = {{8{VAR2[17]}}, {VAR2, 10'b0000000000}};
assign VAR6 = (VAR8 > VAR3 ? 1'b1 :
1'b0);
assign VAR7 = {{8{VAR4[17]}}, {VAR4, 10'b0000000000}};
assign VAR5 = (VAR8 < VAR7 ? 1'b1 :
1'b0);
assign VAR1 = {{8{VAR4[17]}}, {VAR4, 10'b0000000000}};
assign VAR9 = (VAR5 == 1'b0 ? VAR8 :
VAR1);
assign VAR11 = {{8{VAR2[17]}}, {VAR2, 10'b0000000000}};
assign VAR12 = (VAR6 == 1'b0 ? VAR9 :
VAR11);
assign VAR10 = VAR12;
assign VAR13 = VAR6 | VAR5;
assign VAR14 = VAR13;
endmodule
|
gpl-3.0
|
efabless/openlane
|
designs/151/src/datapath.v
| 10,651 |
module MODULE1(
input clk, reset,
input VAR80,
input wire [1:0] VAR82,
input wire VAR28,
input wire VAR35,
input wire VAR30,
output wire [4:0] VAR99,
output wire [4:0] VAR69,
output wire [4:0] VAR75,
output wire [6:0] VAR22,
output wire [2:0] VAR65,
input wire [1:0] VAR14,
input wire [2:0] VAR45,
input wire [1:0] VAR84,
input wire VAR63,
input wire VAR9,
input wire [1:0] VAR33,
input wire VAR6,
input wire VAR26,
input wire VAR5,
output wire [4:0] VAR43,
output wire [4:0] VAR16,
output wire [4:0] VAR36,
output wire [6:0] VAR50,
output wire [2:0] VAR57,
input wire [2:0] VAR51,
input wire [1:0] VAR38,
input wire VAR32,
input wire VAR17,
output wire [4:0] VAR96,
output wire [4:0] VAR13,
output wire [4:0] VAR11,
output wire [6:0] VAR12,
output wire [2:0] VAR90,
output wire VAR46,
output [31:0] VAR24,
output [31:0] VAR34,
output reg [3:0] VAR44,
output VAR89,
output reg [31:0] VAR62,
input [31:0] VAR7,
input [31:0] VAR93,
output wire [31:0] VAR61
);
reg [VAR76-1:0] VAR27;
assign VAR61 = VAR27;
wire [4:0] VAR10;
wire [4:0] VAR3;
wire [4:0] VAR88;
wire [VAR76-1:0] VAR29;
wire [VAR76-1:0] VAR79;
reg [VAR76-1:0] VAR70;
reg [VAR76-1:0] VAR86;
VAR78 #(
.VAR1(5),
.VAR100(32)
) VAR94 (
.clk(clk),
.reset(reset),
.VAR8(VAR88),
.VAR73(VAR70),
.VAR25(VAR32),
.VAR53(VAR10),
.VAR81(VAR29),
.VAR41(VAR3),
.VAR58(VAR79)
);
wire [VAR66-1:0] VAR55;
wire [VAR66-1:0] VAR48;
wire [11:0] VAR15;
wire [19:0] VAR91;
wire [11:0] VAR40;
wire VAR71;
reg [VAR66-1:0] VAR98;
assign VAR10 = VAR99;
assign VAR3 = VAR69;
VAR37 VAR60 (
.clk(clk),
.reset(reset),
.VAR55(VAR55),
.VAR20(VAR34),
.VAR72(VAR98),
.VAR48(0), .VAR82(VAR82),
.VAR39(VAR93),
.VAR99(VAR99),
.VAR69(VAR69),
.VAR75(VAR75),
.VAR15(VAR15),
.VAR91(VAR91),
.VAR40(VAR40),
.VAR22(VAR22),
.VAR65(VAR65),
.VAR71(VAR71)
);
reg [VAR76-1:0] VAR56;
reg [VAR76-1:0] VAR47;
reg [VAR76-1:0] VAR59;
reg [11:0] VAR49;
reg [19:0] VAR64;
reg [11:0] VAR19;
reg [VAR66-1:0] VAR85;
reg [6:0] VAR67;
reg [2:0] VAR77;
reg VAR74;
reg [4:0] VAR87;
reg [4:0] VAR4;
reg [4:0] VAR68;
reg [1:0] VAR97;
reg VAR31;
reg VAR103;
reg [VAR76-1:0] VAR92;
assign VAR50 = VAR67;
assign VAR89 = VAR6;
assign VAR43 = VAR87;
assign VAR16 = VAR4;
assign VAR36 = VAR68;
always @(posedge clk) begin
if (!VAR80) begin
VAR56 <=
VAR15 == 12'h51E && VAR75 != 0 ? VAR27 : 0;
VAR47 <= VAR29;
VAR59 <= VAR79;
VAR49 <= VAR15;
VAR64 <= VAR91;
VAR19 <= VAR40;
VAR85 <= VAR55;
VAR67 <= VAR22;
VAR77 <= VAR65;
VAR74 <= VAR71;
VAR87 <= VAR99;
VAR4 <= VAR69;
VAR68 <= VAR75;
VAR31 <= VAR35;
VAR103 <= VAR30;
VAR86 <= VAR70;
end
end
wire [VAR76-1:0] VAR95;
wire VAR18;
wire [VAR76-1:0] VAR83;
wire [VAR66-1:0] VAR23;
wire [VAR76-1:0] VAR42;
wire [VAR76-1:0] VAR54;
wire [VAR76-1:0] VAR21;
assign VAR42 = VAR26 ? VAR70 :
VAR31 ? VAR86 : VAR47;
assign VAR54 = VAR5 ? VAR70 :
VAR103 ? VAR86 : VAR59;
assign VAR24 = VAR83;
assign VAR57 = VAR77;
always @ begin
case (VAR38)
default: VAR70 = VAR92;
endcase
end
parameter VAR101 = VAR76 - 5;
wire [VAR76-1:0] VAR52 =
{{VAR101{1'b0}}, VAR2};
always @(posedge clk) begin
if (!VAR80)
if (VAR28)
case (VAR17)
default: VAR27 <= VAR102;
endcase
end
endmodule
|
apache-2.0
|
CMU-SAFARI/NOCulator
|
hring/hw/buffered/src/c_decoder.v
| 2,220 |
module MODULE1
(VAR5, VAR4);
parameter VAR3 = 8;
localparam VAR2 = VAR7(VAR3);
input [0:VAR2-1] VAR5;
output [0:VAR3-1] VAR4;
wire [0:VAR3-1] VAR4;
generate
genvar VAR6;
for(VAR6 = 0; VAR6 < VAR3; VAR6 = VAR6 + 1)
begin:VAR1
assign VAR4[VAR6] = (VAR5 == VAR6);
end
endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/buf/sky130_fd_sc_hd__buf.behavioral.pp.v
| 1,746 |
module MODULE1 (
VAR8 ,
VAR9 ,
VAR5,
VAR3,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR9 ;
input VAR5;
input VAR3;
input VAR6 ;
input VAR2 ;
wire VAR12 ;
wire VAR1;
buf VAR4 (VAR12 , VAR9 );
VAR10 VAR7 (VAR1, VAR12, VAR5, VAR3);
buf VAR11 (VAR8 , VAR1 );
endmodule
|
apache-2.0
|
alexforencich/xfcp
|
lib/eth/example/DE5-Net/fpga/rtl/fpga.v
| 11,843 |
module MODULE1 (
input wire VAR168,
input wire [3:0] VAR57,
input wire [3:0] VAR1,
output wire [6:0] VAR191,
output wire VAR246,
output wire [6:0] VAR90,
output wire VAR35,
output wire [3:0] VAR67,
output wire [3:0] VAR108,
output wire VAR156,
output wire VAR128,
output wire VAR59,
input wire VAR155,
input wire VAR123,
input wire VAR169,
input wire VAR43,
input wire VAR16,
input wire VAR8,
input wire VAR77,
input wire VAR240,
inout wire VAR243,
inout wire VAR117,
input wire VAR170,
input wire VAR238,
input wire VAR70,
inout wire VAR115,
inout wire VAR159,
output wire VAR25,
output wire [1:0] VAR146,
input wire VAR69,
output wire VAR184,
input wire VAR182,
input wire VAR74,
input wire VAR65,
inout wire VAR76,
inout wire VAR100,
output wire VAR29,
output wire [1:0] VAR138,
input wire VAR167,
output wire VAR241,
input wire VAR4,
input wire VAR50,
input wire VAR116,
inout wire VAR207,
inout wire VAR165,
output wire VAR245,
output wire [1:0] VAR32,
input wire VAR214,
output wire VAR120,
input wire VAR49,
input wire VAR177,
input wire VAR93,
inout wire VAR136,
inout wire VAR83,
output wire VAR132,
output wire [1:0] VAR15,
input wire VAR86,
output wire VAR99,
input wire VAR82
);
wire VAR171 = VAR155;
wire VAR196;
VAR91 #(
.VAR58(4)
)
VAR205 (
.clk(VAR171),
.rst(~VAR168),
.out(VAR196)
);
wire VAR174;
wire VAR84;
wire VAR125;
VAR91 #(
.VAR58(4)
)
VAR209 (
.clk(VAR174),
.rst(VAR196 | ~VAR125),
.out(VAR84)
);
wire [3:0] VAR64;
wire [3:0] VAR133;
wire [3:0] VAR151;
wire [3:0] VAR226;
wire [6:0] VAR55;
wire VAR150;
wire [6:0] VAR221;
wire VAR14;
VAR172 #(
.VAR68(8),
.VAR58(4),
.VAR145(156250)
)
VAR188 (
.clk(VAR174),
.rst(VAR84),
.in({VAR57,
VAR1}),
.out({VAR64,
VAR133})
);
assign VAR67 = ~VAR151;
assign VAR108 = ~VAR226;
assign VAR191 = ~VAR55;
assign VAR246 = ~VAR150;
assign VAR90 = ~VAR221;
assign VAR35 = ~VAR14;
assign VAR59 = 1;
wire VAR239;
wire VAR216;
wire VAR129;
wire VAR52;
wire VAR210;
wire VAR54;
assign VAR52 = VAR117;
assign VAR117 = VAR54 ? 1'VAR31 : VAR210;
assign VAR239 = VAR243;
assign VAR243 = VAR129 ? 1'VAR31 : VAR216;
wire [6:0] VAR134;
wire VAR183;
wire VAR228;
wire VAR119;
wire VAR18;
wire VAR144;
wire VAR12;
wire VAR39;
wire [7:0] VAR230;
wire VAR201;
wire VAR73;
wire VAR236;
VAR5
VAR158 (
.clk(VAR171),
.rst(VAR196),
.VAR27(VAR134),
.VAR45(VAR183),
.VAR3(VAR228),
.VAR137(VAR119),
.VAR105(VAR18),
.VAR9(VAR144),
.VAR122(VAR12),
.VAR7(VAR39),
.VAR20(VAR230),
.VAR220(VAR201),
.VAR185(VAR73),
.VAR213(VAR236),
.VAR118(),
.VAR131(1)
);
VAR107
VAR40 (
.clk(VAR171),
.rst(VAR196),
.VAR27(VAR134),
.VAR45(VAR183),
.VAR3(VAR228),
.VAR137(VAR119),
.VAR105(VAR18),
.VAR9(VAR144),
.VAR122(VAR12),
.VAR7(VAR39),
.VAR85(VAR230),
.VAR33(VAR201),
.VAR190(VAR73),
.VAR19(VAR236),
.VAR20(),
.VAR220(),
.VAR185(1),
.VAR213(),
.VAR202(VAR239),
.VAR38(VAR216),
.VAR36(VAR129),
.VAR87(VAR52),
.VAR113(VAR210),
.VAR162(VAR54),
.VAR118(),
.VAR41(),
.VAR2(),
.VAR79(),
.VAR218(312),
.VAR92(1)
);
wire [71:0] VAR63;
wire [71:0] VAR197;
wire [71:0] VAR121;
wire [71:0] VAR200;
wire [71:0] VAR24;
wire [71:0] VAR229;
wire [71:0] VAR124;
wire [71:0] VAR143;
wire [367:0] VAR97;
wire [559:0] VAR217;
assign VAR115 = 1'VAR31;
assign VAR159 = 1'VAR31;
assign VAR25 = 1'b0;
assign VAR146 = 2'b00;
assign VAR76 = 1'VAR31;
assign VAR100 = 1'VAR31;
assign VAR29 = 1'b0;
assign VAR138 = 2'b00;
assign VAR207 = 1'VAR31;
assign VAR165 = 1'VAR31;
assign VAR245 = 1'b0;
assign VAR32 = 2'b00;
assign VAR136 = 1'VAR31;
assign VAR83 = 1'VAR31;
assign VAR132 = 1'b0;
assign VAR15 = 2'b00;
VAR78
VAR206 (
.VAR66(VAR82),
.VAR141(VAR125),
.VAR179(VAR184),
.VAR98(VAR69),
.VAR142(VAR241),
.VAR80(VAR167),
.VAR135(VAR120),
.VAR211(VAR214),
.VAR46(VAR99),
.VAR17(VAR86),
.VAR44(VAR63),
.VAR109(VAR197),
.VAR149(VAR121),
.VAR189(VAR200),
.VAR154(VAR24),
.VAR61(VAR229),
.VAR187(VAR124),
.VAR224(VAR143),
.VAR180(VAR174),
.VAR104(VAR174),
.VAR186(~VAR84),
.VAR153(),
.VAR114(),
.VAR219(VAR171),
.VAR11(VAR196),
.VAR106(9'd0),
.VAR176(1'b0),
.VAR227(),
.VAR103(),
.VAR157(1'b0),
.VAR72(32'd0),
.VAR71(VAR97),
.VAR47(VAR217)
);
VAR204
VAR147 (
.VAR193(),
.VAR208(VAR171),
.VAR42(VAR196),
.VAR96(7'd0),
.VAR6(1'b0),
.VAR237(),
.VAR203(),
.VAR111(1'b0),
.VAR34(32'd0),
.VAR47(VAR217),
.VAR71(VAR97)
);
wire [63:0] VAR22;
wire [7:0] VAR139;
wire [63:0] VAR212;
wire [7:0] VAR94;
wire [63:0] VAR10;
wire [7:0] VAR166;
wire [63:0] VAR173;
wire [7:0] VAR163;
wire [63:0] VAR194;
wire [7:0] VAR110;
wire [63:0] VAR222;
wire [7:0] VAR23;
wire [63:0] VAR48;
wire [7:0] VAR60;
wire [63:0] VAR127;
wire [7:0] VAR37;
VAR164
VAR199 (
.VAR62(VAR22),
.VAR88(VAR139),
.VAR234(VAR63)
);
VAR13
VAR181 (
.VAR195(VAR197),
.VAR102(VAR212),
.VAR75(VAR94)
);
VAR164
VAR95 (
.VAR62(VAR10),
.VAR88(VAR166),
.VAR234(VAR121)
);
VAR13
VAR232 (
.VAR195(VAR200),
.VAR102(VAR173),
.VAR75(VAR163)
);
VAR164
VAR148 (
.VAR62(VAR194),
.VAR88(VAR110),
.VAR234(VAR24)
);
VAR13
VAR225 (
.VAR195(VAR229),
.VAR102(VAR222),
.VAR75(VAR23)
);
VAR164
VAR175 (
.VAR62(VAR48),
.VAR88(VAR60),
.VAR234(VAR124)
);
VAR13
VAR231 (
.VAR195(VAR143),
.VAR102(VAR127),
.VAR75(VAR37)
);
VAR51
VAR215 (
.clk(VAR174),
.rst(VAR84),
.VAR53(VAR64),
.VAR244(VAR133),
.VAR140(VAR151),
.VAR178(VAR226),
.VAR89(VAR55),
.VAR235(VAR150),
.VAR101(VAR221),
.VAR152(VAR14),
.VAR28(VAR22),
.VAR112(VAR139),
.VAR160(VAR212),
.VAR81(VAR94),
.VAR26(VAR10),
.VAR21(VAR166),
.VAR161(VAR173),
.VAR130(VAR163),
.VAR223(VAR194),
.VAR242(VAR110),
.VAR30(VAR222),
.VAR192(VAR23),
.VAR126(VAR48),
.VAR198(VAR60),
.VAR233(VAR127),
.VAR56(VAR37)
);
endmodule
|
mit
|
EliasVansteenkiste/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v
| 34,524 |
module MODULE1 (
clk,
reset,
VAR22,
VAR105,
VAR23,
VAR16,
VAR181
);
parameter VAR67 = 18;
parameter VAR235 = 49;
parameter VAR285 = 25;
localparam VAR56 = 56;
input clk;
input reset;
input VAR22;
input VAR105;
input [VAR67-1:0] VAR23; output VAR16;
output [VAR67-1:0] VAR181;
localparam VAR243 = 18; localparam VAR54 = 36; localparam VAR178 = 17;
localparam VAR74 = 49;
reg [VAR67-1:0] VAR2;
reg [VAR67-1:0] VAR44;
reg [VAR67-1:0] VAR289;
reg [VAR67-1:0] VAR3;
reg [VAR67-1:0] VAR21;
reg [VAR67-1:0] VAR79;
reg [VAR67-1:0] VAR188;
reg [VAR67-1:0] VAR109;
reg [VAR67-1:0] VAR191;
reg [VAR67-1:0] VAR174;
reg [VAR67-1:0] VAR245;
reg [VAR67-1:0] VAR123;
reg [VAR67-1:0] VAR37;
reg [VAR67-1:0] VAR73;
reg [VAR67-1:0] VAR252;
reg [VAR67-1:0] VAR209;
reg [VAR67-1:0] VAR290;
reg [VAR67-1:0] VAR180;
reg [VAR67-1:0] VAR280;
reg [VAR67-1:0] VAR284;
reg [VAR67-1:0] VAR135;
reg [VAR67-1:0] VAR201;
reg [VAR67-1:0] VAR226;
reg [VAR67-1:0] VAR111;
reg [VAR67-1:0] VAR131;
always@(posedge clk) begin
VAR2 <= 18'd88;
VAR44 <= 18'd0;
VAR289 <= -18'd97;
VAR3 <= -18'd197;
VAR21 <= -18'd294;
VAR79 <= -18'd380;
VAR188 <= -18'd447;
VAR109 <= -18'd490;
VAR191 <= -18'd504;
VAR174 <= -18'd481;
VAR245 <= -18'd420;
VAR123 <= -18'd319;
VAR37 <= -18'd178;
VAR73 <= 18'd0;
VAR252 <= 18'd212;
VAR209 <= 18'd451;
VAR290 <= 18'd710;
VAR180 <= 18'd980;
VAR280 <= 18'd1252;
VAR284 <= 18'd1514;
VAR135 <= 18'd1756;
VAR201 <= 18'd1971;
VAR226 <= 18'd2147;
VAR111 <= 18'd2278;
VAR131 <= 18'd2360;
end
reg [VAR56-1:0] VAR273;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR273 <= 0;
end else begin
if(VAR22) begin
VAR273 <= {VAR273[VAR56-2:0], VAR105};
end else begin
VAR273 <= VAR273;
end
end
end
wire [VAR67-1:0] VAR222;
wire [VAR67-1:0] VAR247;
wire [VAR67-1:0] VAR278;
wire [VAR67-1:0] VAR157;
wire [VAR67-1:0] VAR236;
wire [VAR67-1:0] VAR263;
wire [VAR67-1:0] VAR165;
wire [VAR67-1:0] VAR276;
wire [VAR67-1:0] VAR256;
wire [VAR67-1:0] VAR150;
wire [VAR67-1:0] VAR212;
wire [VAR67-1:0] VAR90;
wire [VAR67-1:0] VAR229;
wire [VAR67-1:0] VAR143;
wire [VAR67-1:0] VAR133;
wire [VAR67-1:0] VAR63;
wire [VAR67-1:0] VAR199;
wire [VAR67-1:0] VAR7;
wire [VAR67-1:0] VAR281;
wire [VAR67-1:0] VAR43;
wire [VAR67-1:0] VAR267;
wire [VAR67-1:0] VAR250;
wire [VAR67-1:0] VAR218;
wire [VAR67-1:0] VAR59;
wire [VAR67-1:0] VAR108;
wire [VAR67-1:0] VAR30;
wire [VAR67-1:0] VAR32;
wire [VAR67-1:0] VAR271;
wire [VAR67-1:0] VAR152;
wire [VAR67-1:0] VAR55;
wire [VAR67-1:0] VAR127;
wire [VAR67-1:0] VAR223;
wire [VAR67-1:0] VAR46;
wire [VAR67-1:0] VAR15;
wire [VAR67-1:0] VAR18;
wire [VAR67-1:0] VAR264;
wire [VAR67-1:0] VAR266;
wire [VAR67-1:0] VAR176;
wire [VAR67-1:0] VAR272;
wire [VAR67-1:0] VAR106;
wire [VAR67-1:0] VAR89;
wire [VAR67-1:0] VAR297;
wire [VAR67-1:0] VAR78;
wire [VAR67-1:0] VAR282;
wire [VAR67-1:0] VAR205;
wire [VAR67-1:0] VAR107;
wire [VAR67-1:0] VAR116;
wire [VAR67-1:0] VAR170;
wire [VAR67-1:0] VAR261;
MODULE4 MODULE56(
.clk(clk), .VAR22(VAR22),
.VAR25(VAR23),
.VAR221(VAR222),
.VAR95(VAR247),
.VAR240(VAR278),
.VAR42(VAR157),
.VAR91(VAR236),
.VAR260(VAR263),
.VAR94(VAR165),
.VAR161(VAR276),
.VAR167(VAR256),
.VAR171(VAR150),
.VAR220(VAR212),
.VAR179(VAR90),
.VAR242(VAR229),
.VAR81(VAR143),
.VAR232(VAR133),
.VAR86(VAR63),
.VAR184(VAR199),
.VAR68(VAR7),
.VAR49(VAR281),
.VAR115(VAR43),
.VAR146(VAR267),
.VAR219(VAR250),
.VAR154(VAR218),
.VAR140(VAR59),
.VAR113(VAR108),
.VAR137(VAR30),
.VAR189(VAR32),
.VAR197(VAR271),
.VAR287(VAR152),
.VAR216(VAR55),
.VAR39(VAR127),
.VAR1(VAR223),
.VAR292(VAR46),
.VAR275(VAR15),
.VAR268(VAR18),
.VAR296(VAR264),
.VAR13(VAR266),
.VAR258(VAR176),
.VAR119(VAR272),
.VAR246(VAR106),
.VAR70(VAR89),
.VAR155(VAR297),
.VAR120(VAR78),
.VAR38(VAR282),
.VAR88(VAR205),
.VAR53(VAR107),
.VAR159(VAR116),
.VAR4(VAR170),
.VAR163(VAR261),
.reset(reset) );
wire [VAR67-1:0] VAR33;
wire [VAR67-1:0] VAR207;
wire [VAR67-1:0] VAR29;
wire [VAR67-1:0] VAR291;
wire [VAR67-1:0] VAR61;
wire [VAR67-1:0] VAR193;
wire [VAR67-1:0] VAR64;
wire [VAR67-1:0] VAR195;
wire [VAR67-1:0] VAR214;
wire [VAR67-1:0] VAR26;
wire [VAR67-1:0] VAR198;
wire [VAR67-1:0] VAR77;
wire [VAR67-1:0] VAR238;
wire [VAR67-1:0] VAR6;
wire [VAR67-1:0] VAR52;
wire [VAR67-1:0] VAR145;
wire [VAR67-1:0] VAR192;
wire [VAR67-1:0] VAR122;
wire [VAR67-1:0] VAR114;
wire [VAR67-1:0] VAR294;
wire [VAR67-1:0] VAR234;
wire [VAR67-1:0] VAR194;
wire [VAR67-1:0] VAR182;
wire [VAR67-1:0] VAR118;
wire [VAR67-1:0] VAR169;
MODULE5 VAR92(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR222),
.VAR85 (VAR261),
.VAR99(VAR33)
);
MODULE5 VAR12(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR247),
.VAR85 (VAR170),
.VAR99(VAR207)
);
MODULE5 VAR75(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR278),
.VAR85 (VAR116),
.VAR99(VAR29)
);
MODULE5 VAR11(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR157),
.VAR85 (VAR107),
.VAR99(VAR291)
);
MODULE5 VAR83(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR236),
.VAR85 (VAR205),
.VAR99(VAR61)
);
MODULE5 VAR17(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR263),
.VAR85 (VAR282),
.VAR99(VAR193)
);
MODULE5 VAR228(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR165),
.VAR85 (VAR78),
.VAR99(VAR64)
);
MODULE5 VAR142(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR276),
.VAR85 (VAR297),
.VAR99(VAR195)
);
MODULE5 VAR269(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR256),
.VAR85 (VAR89),
.VAR99(VAR214)
);
MODULE5 VAR9(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR150),
.VAR85 (VAR106),
.VAR99(VAR26)
);
MODULE5 VAR293(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR212),
.VAR85 (VAR272),
.VAR99(VAR198)
);
MODULE5 VAR48(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR90),
.VAR85 (VAR176),
.VAR99(VAR77)
);
MODULE5 VAR149(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR229),
.VAR85 (VAR266),
.VAR99(VAR238)
);
MODULE5 VAR72(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR143),
.VAR85 (VAR264),
.VAR99(VAR6)
);
MODULE5 VAR110(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR133),
.VAR85 (VAR18),
.VAR99(VAR52)
);
MODULE5 VAR202(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR63),
.VAR85 (VAR15),
.VAR99(VAR145)
);
MODULE5 VAR31(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR199),
.VAR85 (VAR46),
.VAR99(VAR192)
);
MODULE5 VAR259(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR7),
.VAR85 (VAR223),
.VAR99(VAR122)
);
MODULE5 VAR173(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR281),
.VAR85 (VAR127),
.VAR99(VAR114)
);
MODULE5 VAR211(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR43),
.VAR85 (VAR55),
.VAR99(VAR294)
);
MODULE5 VAR69(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR267),
.VAR85 (VAR152),
.VAR99(VAR234)
);
MODULE5 VAR10(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR250),
.VAR85 (VAR271),
.VAR99(VAR194)
);
MODULE5 VAR28(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR218),
.VAR85 (VAR32),
.VAR99(VAR182)
);
MODULE5 VAR60(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR59),
.VAR85 (VAR30),
.VAR99(VAR118)
);
MODULE3 VAR132(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR108),
.VAR99(VAR169)
);
wire [VAR67-1:0] VAR187;
wire [VAR67-1:0] VAR248;
wire [VAR67-1:0] VAR82;
wire [VAR67-1:0] VAR71;
wire [VAR67-1:0] VAR270;
wire [VAR67-1:0] VAR97;
wire [VAR67-1:0] VAR215;
wire [VAR67-1:0] VAR233;
wire [VAR67-1:0] VAR251;
wire [VAR67-1:0] VAR164;
wire [VAR67-1:0] VAR19;
wire [VAR67-1:0] VAR96;
wire [VAR67-1:0] VAR103;
wire [VAR67-1:0] VAR224;
wire [VAR67-1:0] VAR213;
wire [VAR67-1:0] VAR288;
wire [VAR67-1:0] VAR57;
wire [VAR67-1:0] VAR148;
wire [VAR67-1:0] VAR80;
wire [VAR67-1:0] VAR160;
wire [VAR67-1:0] VAR175;
wire [VAR67-1:0] VAR196;
wire [VAR67-1:0] VAR121;
wire [VAR67-1:0] VAR41;
wire [VAR67-1:0] VAR279;
MODULE2 VAR141(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR33),
.VAR85 (VAR2),
.VAR99(VAR187)
);
MODULE2 VAR14(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR207),
.VAR85 (VAR44),
.VAR99(VAR248)
);
MODULE2 VAR45(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR29),
.VAR85 (VAR289),
.VAR99(VAR82)
);
MODULE2 VAR36(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR291),
.VAR85 (VAR3),
.VAR99(VAR71)
);
MODULE2 VAR227(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR61),
.VAR85 (VAR21),
.VAR99(VAR270)
);
MODULE2 VAR124(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR193),
.VAR85 (VAR79),
.VAR99(VAR97)
);
MODULE2 VAR186(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR64),
.VAR85 (VAR188),
.VAR99(VAR215)
);
MODULE2 VAR76(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR195),
.VAR85 (VAR109),
.VAR99(VAR233)
);
MODULE2 VAR208(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR214),
.VAR85 (VAR191),
.VAR99(VAR251)
);
MODULE2 VAR144(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR26),
.VAR85 (VAR174),
.VAR99(VAR164)
);
MODULE2 VAR138(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR198),
.VAR85 (VAR245),
.VAR99(VAR19)
);
MODULE2 VAR8(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR77),
.VAR85 (VAR123),
.VAR99(VAR96)
);
MODULE2 VAR166(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR238),
.VAR85 (VAR37),
.VAR99(VAR103)
);
MODULE2 VAR262(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR6),
.VAR85 (VAR73),
.VAR99(VAR224)
);
MODULE2 VAR239(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR52),
.VAR85 (VAR252),
.VAR99(VAR213)
);
MODULE2 VAR104(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR145),
.VAR85 (VAR209),
.VAR99(VAR288)
);
MODULE2 VAR129(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR192),
.VAR85 (VAR290),
.VAR99(VAR57)
);
MODULE2 VAR237(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR122),
.VAR85 (VAR180),
.VAR99(VAR148)
);
MODULE2 VAR183(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR114),
.VAR85 (VAR280),
.VAR99(VAR80)
);
MODULE2 VAR128(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR294),
.VAR85 (VAR284),
.VAR99(VAR160)
);
MODULE2 VAR217(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR234),
.VAR85 (VAR135),
.VAR99(VAR175)
);
MODULE2 VAR255(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR194),
.VAR85 (VAR201),
.VAR99(VAR196)
);
MODULE2 VAR162(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR182),
.VAR85 (VAR226),
.VAR99(VAR121)
);
MODULE2 VAR50(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR118),
.VAR85 (VAR111),
.VAR99(VAR41)
);
MODULE2 VAR156(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR169),
.VAR85 (VAR131),
.VAR99(VAR279)
);
wire [VAR67-1:0] VAR134;
wire [VAR67-1:0] VAR277;
wire [VAR67-1:0] VAR65;
wire [VAR67-1:0] VAR203;
wire [VAR67-1:0] VAR58;
wire [VAR67-1:0] VAR51;
wire [VAR67-1:0] VAR147;
wire [VAR67-1:0] VAR112;
wire [VAR67-1:0] VAR102;
wire [VAR67-1:0] VAR185;
wire [VAR67-1:0] VAR206;
wire [VAR67-1:0] VAR47;
wire [VAR67-1:0] VAR158;
MODULE5 VAR230(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR187),
.VAR85 (VAR248),
.VAR99(VAR134)
);
MODULE5 VAR136(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR82),
.VAR85 (VAR71),
.VAR99(VAR277)
);
MODULE5 VAR101(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR270),
.VAR85 (VAR97),
.VAR99(VAR65)
);
MODULE5 VAR200(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR215),
.VAR85 (VAR233),
.VAR99(VAR203)
);
MODULE5 VAR87(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR251),
.VAR85 (VAR164),
.VAR99(VAR58)
);
MODULE5 VAR93(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR19),
.VAR85 (VAR96),
.VAR99(VAR51)
);
MODULE5 VAR172(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR103),
.VAR85 (VAR224),
.VAR99(VAR147)
);
MODULE5 VAR244(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR213),
.VAR85 (VAR288),
.VAR99(VAR112)
);
MODULE5 VAR295(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR57),
.VAR85 (VAR148),
.VAR99(VAR102)
);
MODULE5 VAR62(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR80),
.VAR85 (VAR160),
.VAR99(VAR185)
);
MODULE5 VAR274(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR175),
.VAR85 (VAR196),
.VAR99(VAR206)
);
MODULE5 VAR204(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR121),
.VAR85 (VAR41),
.VAR99(VAR47)
);
MODULE3 VAR24(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR279),
.VAR99(VAR158)
);
wire [VAR67-1:0] VAR34;
wire [VAR67-1:0] VAR249;
wire [VAR67-1:0] VAR257;
wire [VAR67-1:0] VAR139;
wire [VAR67-1:0] VAR254;
wire [VAR67-1:0] VAR283;
wire [VAR67-1:0] VAR190;
MODULE5 VAR5(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR134),
.VAR85 (VAR277),
.VAR99(VAR34)
);
MODULE5 VAR126(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR65),
.VAR85 (VAR203),
.VAR99(VAR249)
);
MODULE5 VAR225(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR58),
.VAR85 (VAR51),
.VAR99(VAR257)
);
MODULE5 VAR66(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR147),
.VAR85 (VAR112),
.VAR99(VAR139)
);
MODULE5 VAR168(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR102),
.VAR85 (VAR185),
.VAR99(VAR254)
);
MODULE5 VAR84(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR206),
.VAR85 (VAR47),
.VAR99(VAR283)
);
MODULE3 VAR117(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR158),
.VAR99(VAR190)
);
wire [VAR67-1:0] VAR286;
wire [VAR67-1:0] VAR130;
wire [VAR67-1:0] VAR125;
wire [VAR67-1:0] VAR153;
MODULE5 VAR27(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR34),
.VAR85 (VAR249),
.VAR99(VAR286)
);
MODULE5 VAR40(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR257),
.VAR85 (VAR139),
.VAR99(VAR130)
);
MODULE5 VAR241(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR254),
.VAR85 (VAR283),
.VAR99(VAR125)
);
MODULE3 VAR177(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR190),
.VAR99(VAR153)
);
wire [VAR67-1:0] VAR151;
wire [VAR67-1:0] VAR100;
MODULE5 VAR265(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR286),
.VAR85 (VAR130),
.VAR99(VAR151)
);
MODULE5 VAR20(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR125),
.VAR85 (VAR153),
.VAR99(VAR100)
);
wire [VAR67-1:0] VAR35;
MODULE5 VAR98(
.clk(clk), .VAR22(VAR22),
.VAR210 (VAR151),
.VAR85 (VAR100),
.VAR99(VAR35)
);
assign VAR181 = VAR35;
assign VAR16 = VAR273[VAR56-1];
endmodule
module MODULE4 (
clk,
VAR22,
VAR25,
VAR221,
VAR95,
VAR240,
VAR42,
VAR91,
VAR260,
VAR94,
VAR161,
VAR167,
VAR171,
VAR220,
VAR179,
VAR242,
VAR81,
VAR232,
VAR86,
VAR184,
VAR68,
VAR49,
VAR115,
VAR146,
VAR219,
VAR154,
VAR140,
VAR113,
VAR137,
VAR189,
VAR197,
VAR287,
VAR216,
VAR39,
VAR1,
VAR292,
VAR275,
VAR268,
VAR296,
VAR13,
VAR258,
VAR119,
VAR246,
VAR70,
VAR155,
VAR120,
VAR38,
VAR88,
VAR53,
VAR159,
VAR4,
VAR163,
reset);
parameter VAR231 = 1;
input clk;
input VAR22;
input [VAR231-1:0] VAR25;
output [VAR231-1:0] VAR221;
output [VAR231-1:0] VAR95;
output [VAR231-1:0] VAR240;
output [VAR231-1:0] VAR42;
output [VAR231-1:0] VAR91;
output [VAR231-1:0] VAR260;
output [VAR231-1:0] VAR94;
output [VAR231-1:0] VAR161;
output [VAR231-1:0] VAR167;
output [VAR231-1:0] VAR171;
output [VAR231-1:0] VAR220;
output [VAR231-1:0] VAR179;
output [VAR231-1:0] VAR242;
output [VAR231-1:0] VAR81;
output [VAR231-1:0] VAR232;
output [VAR231-1:0] VAR86;
output [VAR231-1:0] VAR184;
output [VAR231-1:0] VAR68;
output [VAR231-1:0] VAR49;
output [VAR231-1:0] VAR115;
output [VAR231-1:0] VAR146;
output [VAR231-1:0] VAR219;
output [VAR231-1:0] VAR154;
output [VAR231-1:0] VAR140;
output [VAR231-1:0] VAR113;
output [VAR231-1:0] VAR137;
output [VAR231-1:0] VAR189;
output [VAR231-1:0] VAR197;
output [VAR231-1:0] VAR287;
output [VAR231-1:0] VAR216;
output [VAR231-1:0] VAR39;
output [VAR231-1:0] VAR1;
output [VAR231-1:0] VAR292;
output [VAR231-1:0] VAR275;
output [VAR231-1:0] VAR268;
output [VAR231-1:0] VAR296;
output [VAR231-1:0] VAR13;
output [VAR231-1:0] VAR258;
output [VAR231-1:0] VAR119;
output [VAR231-1:0] VAR246;
output [VAR231-1:0] VAR70;
output [VAR231-1:0] VAR155;
output [VAR231-1:0] VAR120;
output [VAR231-1:0] VAR38;
output [VAR231-1:0] VAR88;
output [VAR231-1:0] VAR53;
output [VAR231-1:0] VAR159;
output [VAR231-1:0] VAR4;
output [VAR231-1:0] VAR163;
reg [VAR231-1:0] VAR221;
reg [VAR231-1:0] VAR95;
reg [VAR231-1:0] VAR240;
reg [VAR231-1:0] VAR42;
reg [VAR231-1:0] VAR91;
reg [VAR231-1:0] VAR260;
reg [VAR231-1:0] VAR94;
reg [VAR231-1:0] VAR161;
reg [VAR231-1:0] VAR167;
reg [VAR231-1:0] VAR171;
reg [VAR231-1:0] VAR220;
reg [VAR231-1:0] VAR179;
reg [VAR231-1:0] VAR242;
reg [VAR231-1:0] VAR81;
reg [VAR231-1:0] VAR232;
reg [VAR231-1:0] VAR86;
reg [VAR231-1:0] VAR184;
reg [VAR231-1:0] VAR68;
reg [VAR231-1:0] VAR49;
reg [VAR231-1:0] VAR115;
reg [VAR231-1:0] VAR146;
reg [VAR231-1:0] VAR219;
reg [VAR231-1:0] VAR154;
reg [VAR231-1:0] VAR140;
reg [VAR231-1:0] VAR113;
reg [VAR231-1:0] VAR137;
reg [VAR231-1:0] VAR189;
reg [VAR231-1:0] VAR197;
reg [VAR231-1:0] VAR287;
reg [VAR231-1:0] VAR216;
reg [VAR231-1:0] VAR39;
reg [VAR231-1:0] VAR1;
reg [VAR231-1:0] VAR292;
reg [VAR231-1:0] VAR275;
reg [VAR231-1:0] VAR268;
reg [VAR231-1:0] VAR296;
reg [VAR231-1:0] VAR13;
reg [VAR231-1:0] VAR258;
reg [VAR231-1:0] VAR119;
reg [VAR231-1:0] VAR246;
reg [VAR231-1:0] VAR70;
reg [VAR231-1:0] VAR155;
reg [VAR231-1:0] VAR120;
reg [VAR231-1:0] VAR38;
reg [VAR231-1:0] VAR88;
reg [VAR231-1:0] VAR53;
reg [VAR231-1:0] VAR159;
reg [VAR231-1:0] VAR4;
reg [VAR231-1:0] VAR163;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR221 <= 0;
VAR95 <= 0;
VAR240 <= 0;
VAR42 <= 0;
VAR91 <= 0;
VAR260 <= 0;
VAR94 <= 0;
VAR161 <= 0;
VAR167 <= 0;
VAR171 <= 0;
VAR220 <= 0;
VAR179 <= 0;
VAR242 <= 0;
VAR81 <= 0;
VAR232 <= 0;
VAR86 <= 0;
VAR184 <= 0;
VAR68 <= 0;
VAR49 <= 0;
VAR115 <= 0;
VAR146 <= 0;
VAR219 <= 0;
VAR154 <= 0;
VAR140 <= 0;
VAR113 <= 0;
VAR137 <= 0;
VAR189 <= 0;
VAR197 <= 0;
VAR287 <= 0;
VAR216 <= 0;
VAR39 <= 0;
VAR1 <= 0;
VAR292 <= 0;
VAR275 <= 0;
VAR268 <= 0;
VAR296 <= 0;
VAR13 <= 0;
VAR258 <= 0;
VAR119 <= 0;
VAR246 <= 0;
VAR70 <= 0;
VAR155 <= 0;
VAR120 <= 0;
VAR38 <= 0;
VAR88 <= 0;
VAR53 <= 0;
VAR159 <= 0;
VAR4 <= 0;
VAR163 <= 0;
end else begin
if(VAR22) begin
VAR221 <= VAR25;
VAR95 <= VAR221;
VAR240 <= VAR95;
VAR42 <= VAR240;
VAR91 <= VAR42;
VAR260 <= VAR91;
VAR94 <= VAR260;
VAR161 <= VAR94;
VAR167 <= VAR161;
VAR171 <= VAR167;
VAR220 <= VAR171;
VAR179 <= VAR220;
VAR242 <= VAR179;
VAR81 <= VAR242;
VAR232 <= VAR81;
VAR86 <= VAR232;
VAR184 <= VAR86;
VAR68 <= VAR184;
VAR49 <= VAR68;
VAR115 <= VAR49;
VAR146 <= VAR115;
VAR219 <= VAR146;
VAR154 <= VAR219;
VAR140 <= VAR154;
VAR113 <= VAR140;
VAR137 <= VAR113;
VAR189 <= VAR137;
VAR197 <= VAR189;
VAR287 <= VAR197;
VAR216 <= VAR287;
VAR39 <= VAR216;
VAR1 <= VAR39;
VAR292 <= VAR1;
VAR275 <= VAR292;
VAR268 <= VAR275;
VAR296 <= VAR268;
VAR13 <= VAR296;
VAR258 <= VAR13;
VAR119 <= VAR258;
VAR246 <= VAR119;
VAR70 <= VAR246;
VAR155 <= VAR70;
VAR120 <= VAR155;
VAR38 <= VAR120;
VAR88 <= VAR38;
VAR53 <= VAR88;
VAR159 <= VAR53;
VAR4 <= VAR159;
VAR163 <= VAR4;
end end
end
endmodule
module MODULE5 (
clk,
VAR22,
VAR210,
VAR85,
VAR99);
input clk;
input VAR22;
input [17:0] VAR210;
input [17:0] VAR85;
output [17:0] VAR99;
reg [17:0] VAR99;
always @(posedge clk) begin
if(VAR22) begin
VAR99 <= VAR210 + VAR85;
end
end
endmodule
module MODULE2 (
clk,
VAR22,
VAR210,
VAR85,
VAR99);
input clk;
input VAR22;
input [17:0] VAR210;
input [17:0] VAR85;
output [17:0] VAR99;
reg [17:0] VAR99;
always @(posedge clk) begin
if(VAR22) begin
VAR99 <= VAR210 * VAR85;
end
end
endmodule
module MODULE3 (
clk,
VAR22,
VAR210,
VAR99);
input clk;
input VAR22;
input [17:0] VAR210;
output [17:0] VAR99;
reg [17:0] VAR99;
always @(posedge clk) begin
if(VAR22) begin
VAR99 <= VAR210;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfxtp/sky130_fd_sc_ms__dfxtp.functional.pp.v
| 1,644 |
module MODULE1 (
VAR9 ,
VAR2 ,
VAR1 ,
VAR11,
VAR6,
VAR12 ,
VAR3
);
output VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR11;
input VAR6;
input VAR12 ;
input VAR3 ;
wire VAR10;
VAR7 VAR8 VAR5 (VAR10 , VAR1, VAR2, , VAR11, VAR6);
buf VAR4 (VAR9 , VAR10 );
endmodule
|
apache-2.0
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/vfabric_sextend.v
| 1,512 |
module MODULE1(VAR5, VAR2,
VAR3, VAR8, VAR10,
VAR1, VAR7, VAR6);
parameter VAR4 = 32;
parameter VAR9 = 64;
input VAR5, VAR2;
input [VAR4-1:0] VAR3;
input VAR8;
output VAR10;
output [VAR9-1:0] VAR1;
input VAR7;
output VAR6;
assign VAR1 = {{VAR9{VAR3[VAR4-1]}}, VAR3[VAR4-1:0]};
assign VAR10 = VAR7;
assign VAR6 = VAR8;
endmodule
|
mit
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/submidRecursiveKOA.v
| 5,160 |
module MODULE1
(
input wire clk,
input wire [VAR2-1:0] VAR18,
input wire [VAR2-1:0] VAR11,
output reg [2*VAR2-1:0] VAR1
);
wire [1:0] VAR19;
wire [3:0] VAR5;
assign VAR19 = 2'b00;
assign VAR5 = 4'b0000;
wire [VAR2/2-1:0] VAR4;
wire [VAR2/2:0] VAR20;
wire [VAR2/2-3:0] VAR21;
wire [VAR2/2-4:0] VAR13;
reg [4*(VAR2/2)+2:0] VAR15;
reg [4*(VAR2/2)-1:0] VAR12;
assign VAR4 = {(VAR2/2){1'b0}};
assign VAR20 = {(VAR2/2+1){1'b0}};
assign VAR21 = {(VAR2/2-4){1'b0}}; assign VAR13 = {(VAR2/2-5){1'b0}};
localparam VAR26 = VAR2/2;
generate
case (VAR2%2)
0:begin : VAR23
reg [VAR2/2:0] VAR27;
reg [VAR2/2:0] VAR14;
reg [VAR2-1:0] VAR30;
reg [VAR2-1:0] VAR16;
reg [VAR2+1:0] VAR17;
reg [VAR2-1:0] VAR9;
reg [VAR2-1:0] VAR33;
reg [VAR2+1:0] VAR32;
reg [2*(VAR2/2+2)-1:0] VAR7;
reg [VAR2+1:0] VAR6;
VAR22 #(.VAR2(VAR2/2)) VAR29(
.VAR18(VAR18[VAR2-1:VAR2-VAR2/2]),
.VAR11(VAR11[VAR2-1:VAR2-VAR2/2]),
.VAR1(VAR30)
);
VAR22 #(.VAR2(VAR2/2)) VAR28(
.VAR18(VAR18[VAR2-VAR2/2-1:0]),
.VAR11(VAR11[VAR2-VAR2/2-1:0]),
.VAR1(VAR16)
);
VAR22 #(.VAR2((VAR2/2)+1)) VAR24 (
.VAR18(VAR27),
.VAR11(VAR14),
.VAR1(VAR17)
);
always @(posedge clk) begin : VAR10
VAR9 = VAR30;
VAR33= VAR16;
VAR32 = VAR17;
end
always @* begin : VAR31
VAR27 <= (VAR18[((VAR2/2)-1):0] + VAR18[(VAR2-1) -: VAR2/2]);
VAR14 <= (VAR11[((VAR2/2)-1):0] + VAR11[(VAR2-1) -: VAR2/2]);
VAR6 <= (VAR32 - VAR9 - VAR33);
VAR1 <= {VAR21,VAR6,VAR4} + {VAR9,VAR33};
end
end
1:begin : VAR8
reg [VAR2/2+1:0] VAR27;
reg [VAR2/2+1:0] VAR14;
reg [2*(VAR2/2)-1:0] VAR30;
reg [2*(VAR2/2+1)-1:0] VAR16;
reg [2*(VAR2/2+2)-1:0] VAR17;
reg [2*(VAR2/2)-1:0] VAR9;
reg [2*(VAR2/2+1)-1:0] VAR33;
reg [2*(VAR2/2+2)-1:0] VAR32;
reg [2*(VAR2/2+2)-1:0] VAR7;
reg [VAR2+4-1:0] VAR6;
VAR22 #(.VAR2(VAR2/2)) VAR29(
.VAR18(VAR18[VAR2-1:VAR2-VAR2/2]),
.VAR11(VAR11[VAR2-1:VAR2-VAR2/2]),
.VAR1(VAR30)
);
VAR22 #(.VAR2((VAR2/2)+1)) VAR28(
.VAR18(VAR18[VAR2-VAR2/2-1:0]),
.VAR11(VAR11[VAR2-VAR2/2-1:0]),
.VAR1(VAR16)
);
VAR22 #(.VAR2(VAR2/2+2)) VAR24 (
.VAR18(VAR27),
.VAR11(VAR14),
.VAR1(VAR17)
);
always @(posedge clk) begin : VAR3
VAR9 = VAR30;
VAR33 = VAR16;
VAR32 = VAR17;
end
always @* begin : VAR25
VAR27 <= (VAR18[VAR2-VAR2/2-1:0] + VAR18[VAR2-1:VAR2-VAR2/2]);
VAR14 <= VAR11[VAR2-VAR2/2-1:0] + VAR11[VAR2-1:VAR2-VAR2/2];
VAR6 <= (VAR32 - VAR9 - VAR33);
VAR1 <= {VAR13,VAR6,VAR20} + {VAR9,VAR33};
end
end
endcase
endgenerate
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/nand2b/sky130_fd_sc_hd__nand2b.functional.pp.v
| 1,936 |
module MODULE1 (
VAR15 ,
VAR11 ,
VAR1 ,
VAR14,
VAR7,
VAR9 ,
VAR10
);
output VAR15 ;
input VAR11 ;
input VAR1 ;
input VAR14;
input VAR7;
input VAR9 ;
input VAR10 ;
wire VAR8 ;
wire VAR3 ;
wire VAR12;
not VAR4 (VAR8 , VAR1 );
or VAR5 (VAR3 , VAR8, VAR11 );
VAR6 VAR2 (VAR12, VAR3, VAR14, VAR7);
buf VAR13 (VAR15 , VAR12 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o2111a/sky130_fd_sc_hd__o2111a_2.v
| 2,448 |
module MODULE1 (
VAR9 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR6 ,
VAR11 ,
VAR8,
VAR4,
VAR10 ,
VAR12
);
output VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR11 ;
input VAR8;
input VAR4;
input VAR10 ;
input VAR12 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR12(VAR12)
);
endmodule
module MODULE1 (
VAR9 ,
VAR3,
VAR1,
VAR7,
VAR6,
VAR11
);
output VAR9 ;
input VAR3;
input VAR1;
input VAR7;
input VAR6;
input VAR11;
supply1 VAR8;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR12 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR11(VAR11)
);
endmodule
|
apache-2.0
|
hanw/sonic-lite
|
hw/verilog/gearbox/gearbox_66_40.v
| 5,511 |
module MODULE1 (
input clk,
input VAR3, input [65:0] din, output reg VAR4,
output reg VAR6,
output reg VAR7,
output [39:0] dout
);
reg [5:0] VAR1 = 0 ;
reg [103:0] VAR9 = 0 ;
assign dout = VAR9[39:0];
reg [65:0] VAR2 = 0;
always @(posedge clk) begin
VAR2 <= din[65:0];
VAR1 <= (VAR3 | VAR1[5]) ? 6'h0 : (VAR1 + 1'b1);
if (VAR1[5]) begin
VAR9 <= {40'h0,VAR9[103:40]}; end
else begin
case (VAR1[4:0])
5'h0 : begin VAR9[65:0] <= din[65:0]; end 5'h1 : begin VAR9[91:26] <= din[65:0]; VAR9[25:0] <= VAR9[65:40]; end 5'h2 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h3 : begin VAR9[77:12] <= din[65:0]; VAR9[11:0] <= VAR9[51:40]; end 5'h4 : begin VAR9[103:38] <= din[65:0]; VAR9[37:0] <= VAR9[77:40]; end 5'h5 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h6 : begin VAR9[89:24] <= din[65:0]; VAR9[23:0] <= VAR9[63:40]; end 5'h7 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h8 : begin VAR9[75:10] <= din[65:0]; VAR9[9:0] <= VAR9[49:40]; end 5'h9 : begin VAR9[101:36] <= din[65:0]; VAR9[35:0] <= VAR9[75:40]; end 5'ha : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'hb : begin VAR9[87:22] <= din[65:0]; VAR9[21:0] <= VAR9[61:40]; end 5'hc : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'hd : begin VAR9[73:8] <= din[65:0]; VAR9[7:0] <= VAR9[47:40]; end 5'he : begin VAR9[99:34] <= din[65:0]; VAR9[33:0] <= VAR9[73:40]; end 5'hf : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h10 : begin VAR9[85:20] <= din[65:0]; VAR9[19:0] <= VAR9[59:40]; end 5'h11 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h12 : begin VAR9[71:6] <= din[65:0]; VAR9[5:0] <= VAR9[45:40]; end 5'h13 : begin VAR9[97:32] <= din[65:0]; VAR9[31:0] <= VAR9[71:40]; end 5'h14 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h15 : begin VAR9[83:18] <= din[65:0]; VAR9[17:0] <= VAR9[57:40]; end 5'h16 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h17 : begin VAR9[69:4] <= din[65:0]; VAR9[3:0] <= VAR9[43:40]; end 5'h18 : begin VAR9[95:30] <= din[65:0]; VAR9[29:0] <= VAR9[69:40]; end 5'h19 : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h1a : begin VAR9[81:16] <= din[65:0]; VAR9[15:0] <= VAR9[55:40]; end 5'h1b : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h1c : begin VAR9[67:2] <= din[65:0]; VAR9[1:0] <= VAR9[41:40]; end 5'h1d : begin VAR9[93:28] <= din[65:0]; VAR9[27:0] <= VAR9[67:40]; end 5'h1e : begin VAR9 <= {40'h0,VAR9[103:40]}; end 5'h1f : begin VAR9[79:14] <= din[65:0]; VAR9[13:0] <= VAR9[53:40]; end endcase
end
end
wire [32:0] VAR8 = 33'b101011010110101101011010110101101;
always @(posedge clk) begin
if (VAR3) VAR4 <= 1'b0;
end
else VAR4 <= (64'h0 | VAR8) >> VAR1;
end
wire [32:0] VAR5 = 33'b110101101011010110101101011010110;
always @(posedge clk) begin
if (VAR3) VAR6 <= 1'b0;
end
else VAR6 <= (64'h0 | VAR5) >> VAR1;
end
wire [32:0] VAR10 = 33'b011010110101101011010110101101011;
always @(posedge clk) begin
if (VAR3) VAR7 <= 1'b0;
end
else VAR7 <= (64'h0 | VAR10) >> VAR1;
end
endmodule
|
mit
|
manu3193/GatoTDD
|
Controlador_Gato.v
| 4,268 |
module MODULE1(
clk,
VAR56,
VAR88,
VAR24,
VAR73,
VAR16,
VAR69,
state,
VAR92, VAR58, VAR14, VAR7, VAR62,
VAR97, VAR84,
VAR110, VAR104, VAR74,
VAR85,
VAR36,
VAR41,
VAR102,
VAR81,
VAR42,
VAR38,
VAR52,
VAR20
);
input clk, VAR56, VAR88;
output [2:0] state;
output [3:0] VAR24;
output [1:0] VAR73, VAR16, VAR69;
output VAR97, VAR84;
output VAR110, VAR104, VAR74;
wire VAR2, VAR25;
wire VAR70, VAR117, VAR9;
wire VAR61, VAR64, VAR79;
wire VAR109;
input VAR92, VAR58, VAR14, VAR7, VAR62;
wire [1:0]
VAR19,
VAR112,
VAR23,
VAR77,
VAR53,
VAR54,
VAR99,
VAR26,
VAR48;
output [1:0]
VAR85,
VAR36,
VAR41,
VAR102,
VAR81,
VAR42,
VAR38,
VAR52,
VAR20;
VAR105 VAR83 (
.clk (clk),
.reset (VAR56),
.state (state),
.VAR91 (VAR2),
.VAR51 (VAR25),
.VAR60 (VAR70),
.VAR94 (VAR117),
.VAR21 (VAR9),
.VAR57 (VAR61),
.VAR15 (VAR64),
.VAR50 (VAR79),
.VAR8 (VAR109),
.VAR71 (VAR97),
.VAR75 (VAR84),
.VAR12 (VAR110),
.VAR98 (VAR104),
.VAR30 (VAR74)
);
VAR65 VAR18 (
.clk (clk),
.VAR39 (VAR92),
.VAR108 (VAR58),
.VAR68 (VAR14),
.VAR119 (VAR7),
.VAR32 (VAR62),
.VAR71 (VAR97),
.VAR75 (VAR84),
.VAR27 (VAR19),
.VAR96 (VAR112),
.VAR37 (VAR23),
.VAR29 (VAR77),
.VAR111 (VAR53),
.VAR47 (VAR54),
.VAR90 (VAR99),
.VAR101 (VAR26),
.VAR114 (VAR48),
.VAR91 (VAR2),
.VAR51 (VAR25),
.VAR24 (VAR24)
);
VAR87 VAR93 (
.clk (clk),
.VAR116 (VAR56),
.VAR49 (VAR56),
.VAR33 (VAR56),
.VAR10 (VAR56),
.VAR115 (VAR56),
.VAR63 (VAR56),
.VAR35 (VAR56),
.VAR17 (VAR56),
.VAR3 (VAR56),
.VAR4 (VAR56),
.VAR107 (VAR19),
.VAR31 (VAR112),
.VAR118 (VAR23),
.VAR5 (VAR77),
.VAR80 (VAR53),
.VAR59 (VAR54),
.VAR6 (VAR99),
.VAR72 (VAR26),
.VAR11 (VAR48),
.VAR86 (VAR85),
.VAR45 (VAR36),
.VAR100 (VAR41),
.VAR44 (VAR102),
.VAR113 (VAR81),
.VAR95 (VAR42),
.VAR43 (VAR38),
.VAR13 (VAR52),
.VAR34 (VAR20)
);
VAR28 VAR22 (
.VAR8 (VAR109),
.VAR60 (VAR70),
.VAR94 (VAR117),
.VAR21 (VAR9),
.VAR57 (VAR61),
.VAR15 (VAR64),
.VAR50 (VAR79),
.VAR40 (VAR16),
.VAR106 (VAR73),
.VAR66 (VAR69),
.VAR82 (VAR85),
.VAR46 (VAR36),
.VAR76 (VAR41),
.VAR67 (VAR102),
.VAR55 (VAR81),
.VAR89 (VAR42),
.VAR78 (VAR38),
.VAR103 (VAR52),
.VAR1 (VAR20)
);
endmodule
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/opencores/ata/ata_device_oc.v
| 15,606 |
module MODULE1( VAR2, VAR9, VAR8, VAR16, VAR3,
VAR22, VAR18, VAR17, VAR20 );
input VAR2;
inout [15:0] VAR9;
input [2:0] VAR8;
input VAR16, VAR3;
input VAR22, VAR18;
output VAR17;
output VAR20;
integer VAR6;
integer VAR7;
reg VAR17;
reg VAR12;
reg VAR20;
integer VAR19;
reg [15:0] VAR13[32:0];
reg [15:0] dout;
reg VAR11;
wire VAR10, VAR21, VAR4, VAR15, VAR14;
wire [4:0] addr;
wire VAR1, VAR5;
begin
begin
begin
begin
begin
begin
|
mit
|
The-OpenROAD-Project/asap7
|
asap7sc7p5t_28/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020.v
| 17,248 |
module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1);
|
bsd-3-clause
|
MeshSr/onetswitch45
|
ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/core/tx_queue.v
| 10,742 |
module MODULE1
parameter VAR34 = 64,
parameter VAR45 = VAR34/8,
parameter VAR49 = 1,
parameter VAR66 = 'hff,
parameter VAR67 = 32,
parameter VAR63 = VAR67/8
)
(input [VAR34-1:0] VAR31,
input [VAR45-1:0] VAR64,
input VAR30,
output VAR28,
input VAR2,
output reg VAR38,
output [VAR67 - 1 : 0] VAR35,
output reg VAR68,
output reg [VAR63 - 1 : 0] VAR61,
input VAR41,
input VAR50,
output VAR16,
output reg VAR8,
output reg [11:0] VAR1,
output reg VAR65,
output reg [9:0] VAR11,
input reset,
input clk
);
localparam VAR23 = 1;
localparam VAR52 = 2;
localparam VAR44 = 4;
localparam VAR51 = 1;
localparam VAR48 = 2;
localparam VAR32 = 7;
wire [VAR34+VAR45 - 1 : 0] VAR12;
wire [VAR67 - 1 : 0] VAR20;
wire [VAR63 - 1 : 0] VAR57;
reg VAR14;
wire VAR59;
wire VAR54;
reg VAR60;
reg VAR40; reg [4:0] VAR17, VAR6;
reg VAR22;
reg VAR55;
reg VAR39;
reg [VAR32-1:0] VAR19;
wire VAR27;
reg [4:0] VAR47, VAR69;
reg VAR21;
reg VAR3;
assign VAR28 = ~VAR54;
reg VAR36;
always @(posedge clk) begin
if (reset) VAR36 <= 1;
end
else if (VAR60) VAR36 <= 0;
end
always @(posedge VAR2) VAR60 <= VAR36;
assign VAR12 = {VAR64[7:4], VAR31[63:32],VAR64[3:0], VAR31[31:0]};
VAR37 VAR56
(
.din (VAR12),
.VAR62 (VAR21),
.VAR15 (clk),
.dout ({VAR57,VAR20}),
.VAR4 (VAR14),
.VAR42 (VAR2),
.VAR9 (VAR59),
.VAR18 (),
.VAR7(VAR54),
.rst (reset)
);
generate
genvar VAR13;
for(VAR13=0; VAR13<VAR63; VAR13=VAR13+1) begin: VAR24
assign VAR35[8*VAR13+:8] = VAR20[VAR67-8-8*VAR13+:8];
end
endgenerate
always @begin
if(VAR6 == VAR52 || VAR6 == VAR44)begin
case (VAR57)
4'b1000: begin
VAR61 = 4'b0001;
VAR68 = 1'b1;
end
4'b0100: begin
VAR61 = 4'b0011;
VAR68 = 1'b1;
end
4'b0010: begin
VAR61 = 4'b0111;
VAR68 = 1'b1;
end
4'b0001: begin
VAR61 = 4'b1111;
VAR68 = 1'b1;
end
default: begin
VAR68 = 1'b0;
VAR61 = 4'b1111;
end
endcase
end
else begin
VAR61 = 1'b0;
VAR68 = 1'b0;
end
end
always @(posedge VAR2) begin
if (VAR60) begin
VAR6 <= VAR23;
VAR38 <= 0;
VAR3 <= 0;
end
else begin
VAR6 <= VAR17;
VAR38 <= VAR22;
if(VAR14) VAR3 <= !VAR3;
end
end
VAR25 VAR26
(.VAR5 (VAR8),
.VAR29 (clk),
.VAR46(VAR53),
.VAR58 (VAR2),
.VAR43 (reset),
.VAR33 (VAR60));
VAR25 VAR10
(.VAR5 (VAR40),
.VAR29 (VAR2),
.VAR46(VAR16),
.VAR58 (clk),
.VAR43 (VAR60),
.VAR33 (reset));
always @(posedge VAR2) begin
if (VAR60) begin
VAR19 <= 'h0;
end
else begin
case ({VAR40, VAR53})
2'b01 : VAR19 <= VAR19 + 1;
2'b10 : VAR19 <= VAR19 - 1;
default: begin end
endcase
end
end
assign VAR27 = (VAR19 != 'h0);
endmodule
|
lgpl-2.1
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/fill/sky130_fd_sc_lp__fill.pp.symbol.v
| 1,175 |
module MODULE1 (
input VAR3 ,
input VAR1,
input VAR2,
input VAR4
);
endmodule
|
apache-2.0
|
mwswartwout/EECS318
|
hw1/problem5/behavioral.v
| 1,198 |
module MODULE1(out, VAR2, VAR4, VAR3, VAR1);
output out;
reg VAR2, VAR4, VAR3, VAR1;
if (~VAR2 && ~VAR4 && ~VAR3 && ~VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b0;
out = 1'b1;
end
if (~VAR2 && ~VAR4 && ~VAR3 && VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b1;
out = 1'b1;
end
if (~VAR2 && ~VAR4 && VAR3 && ~VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b0;
out = 1'b1;
end
if (~VAR2 && ~VAR4 && VAR3 && VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b1;
end
if (~VAR2 && VAR4 && ~VAR3 && ~VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b1;
out = 1'b0;
end
if (~VAR2 && VAR4 && ~VAR3 && VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b1;
out = 1'b0;
end
if (~VAR2 && VAR4 && VAR3 && ~VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
if (~VAR2 && VAR4 && VAR3 && VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
if (VAR2 && ~VAR4 && ~VAR3 && ~VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b0;
out = 1'b0;
end
if (VAR2 && ~VAR4 && ~VAR3 && VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
if (VAR2 && ~VAR4 && VAR3 && ~VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b0;
out = 1'b0;
end
if (VAR2 && ~VAR4 && VAR3 && VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
if (VAR2 && VAR4 && ~VAR3 && ~VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b0;
out = 1'b0;
end
if (VAR2 && VAR4 && ~VAR3 && VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
if (VAR2 && VAR4 && VAR3 && ~VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
if (VAR2 && VAR4 && VAR3 && VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1'b1;
out = 1'b0;
end
endmodule
|
mit
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/xilinx_pcie_2_0_ep_v6.v
| 17,967 |
module MODULE1 # (
parameter VAR125 = "VAR129",
parameter VAR90 = 64, parameter VAR35 = VAR90 / 8 )
(
output [3:0] VAR131,
output [3:0] VAR48,
input [3:0] VAR88,
input [3:0] VAR21,
output VAR110,
output VAR16,
output VAR120,
input VAR128,
input VAR42,
input VAR71
);
wire VAR121;
wire VAR17;
wire VAR39;
wire [5:0] VAR54;
wire VAR98;
wire VAR43;
wire VAR72;
wire VAR31;
wire [3:0] VAR4;
wire [VAR90-1:0] VAR7;
wire [VAR35-1:0] VAR1;
wire VAR75;
wire VAR59;
wire [VAR90-1:0] VAR8;
wire [VAR35-1:0] VAR78;
wire VAR13;
wire VAR94;
wire VAR12;
wire [21:0] VAR30;
wire VAR55;
wire [11:0] VAR132;
wire [7:0] VAR32;
wire [11:0] VAR126;
wire [7:0] VAR20;
wire [11:0] VAR102;
wire [7:0] VAR122;
wire [2:0] VAR58;
wire [31:0] VAR3;
wire VAR6;
wire [31:0] VAR83;
wire [3:0] VAR104;
wire [9:0] VAR56;
wire VAR18;
wire VAR47;
wire VAR69;
wire VAR36;
wire VAR27;
wire VAR46;
wire VAR115;
wire VAR52;
wire VAR50;
wire VAR62;
wire [47:0] VAR41;
wire VAR37;
wire VAR60;
wire VAR33;
wire VAR103;
wire [7:0] VAR24;
wire [7:0] VAR134;
wire [2:0] VAR73;
wire VAR66;
wire VAR61;
wire VAR133;
wire VAR114;
wire VAR80;
wire VAR29;
wire VAR86;
wire [7:0] VAR49;
wire [4:0] VAR82;
wire [2:0] VAR106;
wire [15:0] VAR76;
wire [15:0] VAR9;
wire [15:0] VAR22;
wire [15:0] VAR117;
wire [15:0] VAR81;
wire [15:0] VAR11;
wire [15:0] VAR70;
wire [2:0] VAR100;
wire [63:0] VAR127;
wire [2:0] VAR99;
wire [1:0] VAR68;
wire VAR105;
wire VAR15;
wire VAR109;
wire [5:0] VAR77;
wire VAR63;
wire VAR2;
wire [1:0] VAR19;
wire VAR101;
wire [1:0] VAR123;
wire VAR84;
wire [1:0] VAR116;
wire VAR118;
wire VAR93;
wire VAR53;
VAR97 VAR10 (.VAR57(VAR93), .VAR112(), .VAR28(VAR128), .VAR40(VAR42), .VAR111(1'b0));
VAR87 VAR26 (.VAR57(VAR53), .VAR28(VAR71));
VAR91 VAR67 (.VAR57(VAR110), .VAR28(VAR53));
VAR91 VAR107 (.VAR57(VAR16), .VAR28(VAR17));
VAR91 VAR5 (.VAR57(VAR120), .VAR28(!VAR39));
VAR25 #(
.VAR14(1'b1)
) VAR51 (
.VAR95 (VAR39),
.VAR108 (VAR85),
.VAR96 (VAR121),
.VAR130 (1'b0),
.VAR23 (1'b0)
);
VAR25 #(
.VAR14(1'b1)
) VAR38 (
.VAR95 (VAR17),
.VAR108 (VAR124),
.VAR96 (VAR121),
.VAR130 (1'b0),
.VAR23 (1'b0)
);
VAR113 #(
.VAR125 ( VAR125 )
) VAR44 (
.VAR131( VAR131 ),
.VAR48( VAR48 ),
.VAR88( VAR88 ),
.VAR21( VAR21 ),
.VAR74( VAR121 ),
.VAR92( VAR124 ),
.VAR39( VAR85 ),
.VAR31( VAR31 ),
.VAR7( VAR7 ),
.VAR1( VAR1 ),
.VAR4( VAR4 ),
.VAR75( VAR75 ),
.VAR59( VAR59 ),
.VAR72( VAR72 ),
.VAR98( VAR98 ),
.VAR54( VAR54 ),
.VAR43( VAR43 ),
.VAR8( VAR8 ),
.VAR78( VAR78 ),
.VAR13( VAR13 ),
.VAR94( VAR94 ),
.VAR12( VAR12 ),
.VAR30 ( VAR30 ),
.VAR55( VAR55 ),
.VAR132( VAR132 ),
.VAR32( VAR32 ),
.VAR126( VAR126 ),
.VAR20( VAR20 ),
.VAR102( VAR102 ),
.VAR122( VAR122 ),
.VAR58( VAR58 ),
.VAR3( VAR3 ),
.VAR6( VAR6),
.VAR83( VAR83 ),
.VAR104( VAR104 ),
.VAR56( VAR56 ),
.VAR18( VAR18 ),
.VAR47( VAR47 ),
.VAR69( VAR69 ),
.VAR36( VAR36 ),
.VAR27( VAR27 ),
.VAR46( VAR46 ),
.VAR115( VAR115 ),
.VAR52( VAR52 ),
.VAR50( VAR50 ),
.VAR62( VAR62 ),
.VAR41( VAR41 ),
.VAR37( VAR37 ),
.VAR60( VAR60 ),
.VAR33( VAR33 ),
.VAR103( VAR103 ),
.VAR24( VAR24 ),
.VAR134( VAR134 ),
.VAR73( VAR73 ),
.VAR66( VAR66 ),
.VAR61( VAR61 ),
.VAR133( VAR133 ),
.VAR114( VAR114 ),
.VAR80( VAR80 ),
.VAR29( VAR29 ),
.VAR86( VAR86 ),
.VAR49( VAR49 ),
.VAR82( VAR82 ),
.VAR106( VAR106 ),
.VAR76( VAR76 ),
.VAR9( VAR9 ),
.VAR22( VAR22 ),
.VAR117( VAR117 ),
.VAR81( VAR81 ),
.VAR11( VAR11 ),
.VAR70( VAR70 ),
.VAR100( VAR100 ),
.VAR127( VAR127 ),
.VAR45( ),
.VAR89( ),
.VAR64( ),
.VAR99( VAR99 ),
.VAR68( VAR68 ),
.VAR105( VAR105 ),
.VAR15( VAR15 ),
.VAR109( VAR109 ),
.VAR77( VAR77 ),
.VAR63( VAR63 ),
.VAR2( VAR2 ),
.VAR19( VAR19 ),
.VAR101( VAR101 ),
.VAR123( VAR123 ),
.VAR84( VAR84 ),
.VAR116( VAR116 ),
.VAR118( VAR118 ),
.VAR34( VAR93 ),
.VAR65( !VAR53 )
);
VAR119 #(
.VAR90( VAR90 ),
.VAR35( VAR35 )
)VAR79 (
.VAR121( VAR121 ),
.VAR17( VAR124 ),
.VAR39( VAR85 ),
.VAR54( VAR54 ),
.VAR98( VAR98 ),
.VAR43( VAR43 ),
.VAR31( VAR31 ),
.VAR7( VAR7 ),
.VAR1( VAR1 ),
.VAR4( VAR4 ),
.VAR75( VAR75 ),
.VAR59( VAR59 ),
.VAR72( VAR72 ),
.VAR8( VAR8 ),
.VAR78( VAR78 ),
.VAR13( VAR13 ),
.VAR94( VAR94 ),
.VAR12( VAR12 ),
.VAR30 ( VAR30 ),
.VAR55( VAR55 ),
.VAR132( VAR132 ),
.VAR32( VAR32 ),
.VAR126( VAR126 ),
.VAR20( VAR20 ),
.VAR102( VAR102 ),
.VAR122( VAR122 ),
.VAR58( VAR58 ),
.VAR3( VAR3 ),
.VAR6( VAR6),
.VAR83( VAR83 ),
.VAR104( VAR104 ),
.VAR56( VAR56 ),
.VAR18( VAR18 ),
.VAR47( VAR47 ),
.VAR69( VAR69 ),
.VAR36( VAR36 ),
.VAR27( VAR27 ),
.VAR46( VAR46 ),
.VAR115( VAR115 ),
.VAR52( VAR52 ),
.VAR50( VAR50 ),
.VAR62( VAR62 ),
.VAR41( VAR41 ),
.VAR37( VAR37 ),
.VAR60( VAR60 ),
.VAR33( VAR33 ),
.VAR103( VAR103 ),
.VAR24( VAR24 ),
.VAR134( VAR134 ),
.VAR73( VAR73 ),
.VAR66( VAR66 ),
.VAR61( VAR61 ),
.VAR133( VAR133 ),
.VAR114( VAR114 ),
.VAR80( VAR80 ),
.VAR29( VAR29 ),
.VAR86( VAR86 ),
.VAR49( VAR49 ),
.VAR82( VAR82 ),
.VAR106( VAR106 ),
.VAR76( VAR76 ),
.VAR9( VAR9 ),
.VAR22( VAR22 ),
.VAR117( VAR117 ),
.VAR81( VAR81 ),
.VAR11( VAR11 ),
.VAR70( VAR70 ),
.VAR100( VAR100 ),
.VAR127( VAR127 ),
.VAR99( VAR99 ),
.VAR68( VAR68 ),
.VAR105( VAR105 ),
.VAR15( VAR15 ),
.VAR109( VAR109 ),
.VAR77( VAR77 ),
.VAR63( VAR63 ),
.VAR2( VAR2 ),
.VAR19( VAR19 ),
.VAR101( VAR101 ),
.VAR123( VAR123 ),
.VAR84( VAR84 ),
.VAR116( VAR116 ),
.VAR118( VAR118 )
);
endmodule
|
lgpl-3.0
|
DougFirErickson/parallella-hw
|
fpga/old/esaxilite/hdl/esaxilite.v
| 2,478 |
module MODULE1 (
VAR24, VAR19, VAR9,
VAR11, VAR23, VAR22, VAR12,
VAR4, VAR26, VAR1, VAR16, VAR15, VAR6,
VAR8, VAR7, VAR3,
VAR25, VAR14, VAR13,
VAR5, VAR20, VAR17, VAR10,
VAR21, VAR2
);
parameter VAR18 = 16;
input [15:0] VAR8;
input [2:0] VAR7;
output VAR24;
input VAR3;
input [15:0] VAR25;
input [2:0] VAR14;
output VAR19;
input VAR13;
input VAR5;
output [1:0] VAR9;
output VAR11;
output [31:0] VAR23;
input VAR20;
output [1:0] VAR22;
output VAR12;
input [31:0] VAR17;
output VAR4;
input [3:0] VAR10;
input VAR21;
output VAR26;
output VAR1;
output VAR16;
output [VAR18-1:0] VAR15;
output [31:0] VAR6;
input [31:0] VAR2;
endmodule
|
gpl-3.0
|
stevenokm/mor1kx
|
rtl/verilog/mor1kx_lsu_espresso.v
| 7,734 |
module MODULE1
(
VAR1, VAR3, VAR12, VAR14,
VAR18, VAR4, VAR27, VAR45, VAR15,
VAR42,
clk, rst, VAR37, VAR39, VAR20, VAR25,
VAR26, VAR31, VAR16, VAR23,
VAR7, VAR6, VAR36, VAR33,
VAR11, VAR9
);
parameter VAR2 = 32;
parameter VAR29 = "VAR41";
input clk, rst;
input VAR37;
input [VAR2-1:0] VAR39;
input [VAR2-1:0] VAR20;
input VAR25;
input VAR26;
input [1:0] VAR31;
input VAR16;
input VAR23;
input VAR7;
input VAR6;
input VAR36;
output [VAR2-1:0] VAR1;
output VAR3;
output VAR12;
output VAR14;
output [VAR2-1:0] VAR18;
output VAR4;
output [VAR2-1:0] VAR27;
output [3:0] VAR45;
output VAR15;
output VAR42;
input VAR33;
input VAR11;
input [VAR2-1:0] VAR9;
reg [VAR2-1:0] VAR13; reg [VAR2-1:0] VAR5;
reg [VAR2-1:0] VAR34;
reg [3:0] VAR24;
reg VAR8;
reg VAR10;
reg [VAR2-1:0] VAR30;
reg VAR32;
wire VAR21;
wire VAR28;
wire VAR19;
wire VAR38;
reg VAR44;
reg VAR22;
reg VAR40;
assign VAR27 = (VAR31 == 2'b00) ? {VAR20[7:0],VAR20[7:0],VAR20[7:0],VAR20[7:0]} :
(VAR31 == 2'b01) ? {VAR20[15:0],VAR20[15:0]} :
VAR20;
assign VAR21 = |VAR18[1:0];
assign VAR28 = VAR18[0];
assign VAR3 = VAR11 | VAR8| VAR10;
assign VAR12 = VAR8 | VAR22;
assign VAR19 = (VAR31 == 2'b10) & VAR21 |
(VAR31 == 2'b01) & VAR28;
assign VAR14 = VAR44;
always @(posedge clk VAR17)
if (rst)
VAR40 <= 0;
else
VAR40 <= VAR37 | (VAR6 & VAR36);
always @(posedge clk VAR17)
if (rst)
VAR10 <= 0;
else if (VAR37 | VAR7)
VAR10 <= 0;
else if (VAR11 | VAR8 | VAR14)
VAR10 <= 1;
always @(posedge clk VAR17)
if (rst)
VAR44 <= 0;
else if (VAR23)
VAR44 <= 0;
else
VAR44 <= VAR38;
always @(posedge clk VAR17)
if (rst)
VAR22 <= 0;
else if (VAR23)
VAR22 <= 0;
else if (VAR8)
VAR22 <= 1;
always @(posedge clk VAR17)
if (rst)
VAR34 <= 0;
else if (VAR40 & (VAR25 | VAR26))
VAR34 <= VAR39;
always @
case({VAR16, VAR31})
3'b100: VAR5 = {24'd0,VAR13[31:24]};
3'b101: VAR5 = {16'd0,VAR13[31:16]};
3'b000: VAR5 = {{24{VAR13[31]}},
VAR13[31:24]};
3'b001: VAR5 = {{16{VAR13[31]}},
VAR13[31:16]};
default:
VAR5 = VAR13;
endcase
always @(posedge clk)
if (VAR11 & VAR25)
VAR30 <= VAR5;
assign VAR42 = 0;
generate
if (VAR29!="VAR41")
begin : VAR43
assign VAR18 = VAR34;
always @(posedge clk)
begin
VAR8 <= VAR33;
VAR32 <= VAR25 | VAR26;
end
assign VAR4 = !VAR40 & VAR32 &
!(VAR38 | VAR44) &
!VAR10;
assign VAR38 = VAR32 & (VAR25 | VAR26) &
VAR19 & !VAR40;
end
else
begin : VAR35
assign VAR18 = VAR40 ? VAR39 : VAR34;
always @*
begin
VAR8 = VAR33;
VAR32 = VAR25 | VAR26;
end
assign VAR4 = VAR32 & !VAR38 & !VAR10;
assign VAR38 = VAR32 & VAR19;
end
endgenerate
assign VAR1 = VAR10 ? VAR30 : VAR5;
endmodule
|
mpl-2.0
|
Gum-Joe/Sora
|
FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_monitor.v
| 23,857 |
module MODULE1(
input wire clk,
input wire rst,
input wire VAR88, input wire [31:0] VAR12, input wire [31:0] VAR22, output reg VAR45, input wire VAR7,
input wire VAR86,
input wire VAR37, VAR65
output reg [4:0] VAR9,
output reg [31:0] VAR57,
output reg VAR75,
output wire [4:0] VAR109,
input [31:0] VAR72,
output reg VAR59,
input [31:0] VAR40,
input wire [63:0] VAR92,
input wire [7:0] VAR3,
input wire VAR36,
input wire VAR26,
input wire VAR87,
input wire VAR63,
input wire VAR10,
input wire [6:0] VAR98,
input wire [11:0] VAR33,
input wire [7:0] VAR34,
input wire [11:0] VAR4,
input wire [7:0] VAR94,
input wire [11:0] VAR62,
input wire [7:0] VAR48,
input wire VAR93, input wire VAR55,
input wire [2:0] VAR108, input wire VAR16, input wire VAR18, input wire [1:0] VAR70,
input wire [9:0] VAR24,
input wire [15:0] VAR8,
input wire [7:0] VAR82,
input wire [15:0] VAR71,
input wire [2:0]VAR39,
input wire VAR73,
input wire [11:0] VAR61,
input wire [63:0] VAR41,
input wire [15:0] VAR80,
input wire [7:0] VAR5,
input wire [6:0] VAR11,
input wire VAR99,
input wire VAR35,
input wire VAR104,
input wire VAR43,
input wire VAR83,
input wire VAR27,
input wire VAR67,
output reg VAR49, output wire [27:6] VAR64,
output reg [10:0] VAR50,
output wire VAR95
);
localparam VAR14 = 5'b00000;
localparam VAR32 = 5'b00001;
localparam VAR106 = 5'b00010;
localparam VAR25 = 5'b00011;
localparam VAR74 = 2'b00;
localparam VAR105 = 2'b01;
localparam VAR23 = 2'b10;
reg [63:0] VAR38;
reg [7:0] VAR1;
reg VAR96;
reg VAR44;
reg VAR20;
reg VAR31;
reg VAR66;
reg [6:0] VAR77;
reg [11:0] VAR52;
reg [7:0] VAR56;
reg [11:0] VAR47;
reg [7:0] VAR15;
reg [11:0] VAR17;
reg [7:0] VAR58;
reg [27:6] VAR81;
reg [4:0] VAR46;
reg [1:0] VAR51;
wire VAR97;
wire [27:6] VAR60;
reg VAR68;
reg VAR90, VAR30;
reg VAR101 = 0;
reg VAR13 = 0;
reg VAR69;
reg VAR28;
reg VAR84;
reg VAR78;
reg [9:0] VAR89;
reg [9:0] VAR102;
reg [9:0] VAR53;
reg [9:0] VAR100;
wire VAR107, VAR21;
reg VAR79;
wire VAR19;
reg VAR6;
always@(posedge clk) VAR6 <= rst;
wire VAR76;
reg VAR54;
VAR103 VAR29(
.clk(clk),
.rst(VAR6),
.in(VAR54),
.VAR85(VAR76)
);
always@(posedge clk)
VAR54 <= VAR88;
always @ (posedge clk)
begin
VAR38[63:0] <= VAR92[63:0] ;
VAR1[7:0] <= VAR3[7:0] ;
VAR96 <= VAR36 ;
VAR44 <= VAR26 ;
VAR20 <= VAR87 ;
VAR31 <= VAR63 ;
VAR66 <= VAR10 ;
VAR77[6:0] <= VAR98[6:0] ;
VAR52[11:0] <= VAR33[11:0] ;
VAR56[7:0] <= VAR34[7:0] ;
VAR47[11:0] <= VAR4[11:0] ;
VAR15[7:0] <= VAR94[7:0] ;
VAR17[11:0] <= VAR62[11:0];
VAR58[7:0] <= VAR48[7:0] ;
end
assign VAR109[4:0] = VAR5[4:0];
always@(posedge clk)begin
if(VAR6)begin
VAR46 <= VAR14;
VAR81[27:6] <= 0;
VAR49 <= 0; VAR9 <= 0;
VAR57 <= 0;
VAR75 <= 1'b0;
VAR59 <= 1'b0;
end else begin
case(VAR46)
VAR14:begin
VAR9[4:0] <= 5'b00000;
VAR57[31:0] <= 32'h00000000;
VAR75 <= 1'b0;
VAR59 <= 1'b0;
if(VAR97 && VAR104)begin
VAR46 <= VAR32;
VAR81[27:6] <= VAR72[21:0];
VAR49 <= VAR72[31]; end else begin
VAR46 <= VAR14;
end
end
VAR32:begin VAR46 <= VAR106;
end
VAR106:begin VAR46 <= VAR25;
VAR9[4:0] <= VAR109[4:0];
VAR57[31:0] <= {10'b0000000000, VAR60[27:6]};
VAR75 <= 1'b1;
if(VAR24[9:0] == VAR61[11:2])
VAR59 <= 1'b1;
end
else
VAR59 <= 1'b0;
end
VAR25:begin VAR46 <= VAR14;
end
default:begin
VAR81[27:6] <= 0;
VAR9 <= 0;
VAR57 <= 0;
VAR75 <= 1'b0;
VAR59 <= 1'b0;
end
endcase
end
end
VAR103 VAR42(
.clk(clk),
.rst(VAR6),
.in(VAR27),
.VAR85(VAR97)
);
assign VAR60[27:6] = (VAR24[9:0] != 10'b0000000000)
? VAR81[27:6] + VAR24[9:4]
: VAR81[27:6] + 7'b1000000;
assign VAR64[27:6] = VAR81[27:6];
always@(posedge clk)begin
if(VAR6)begin
VAR50[10:0] <= 11'b00000000000;
end else begin
if(VAR104 & VAR97)begin
VAR50[10:0] <= (VAR24[9:0] != 10'b0000000000)
? {1'b0,VAR24[9:0]}
: 11'b10000000000;
end
end
end
always@(posedge clk)begin
if(VAR6)begin
VAR68 <= 1'b0;
end else begin
VAR68 <= VAR67;
end
end
always@(posedge clk)begin
VAR90 <= VAR104;
VAR30 <= VAR90;
end
assign VAR95 = VAR68 & ~VAR67 & VAR30;
always@(posedge clk) VAR53[9:0] <= VAR22[12:3];
always@(posedge clk) begin
if (VAR97 & VAR104)
VAR102[9:0] <= VAR24[9:0];
end
always@(posedge clk)begin
if (VAR6 | (~VAR37))
if (VAR6)
VAR101 <= 1'b0;
end
else if(VAR76) VAR101 <= 1'b1;
end
else if (VAR69) VAR101 <= 1'b0;
end
always@(posedge clk)begin
if (VAR6 | (~VAR37))
if (VAR6)
VAR13 <= 1'b0;
end
else if(~VAR44 & ~VAR20 & VAR104 & ~VAR86) VAR13 <= 1'b1;
end
else if (VAR28) VAR13 <= 1'b0;
end
always@(posedge clk)begin
if(VAR6 | (~VAR37))begin
if(VAR6)begin
VAR89[9:0] <= 0;
VAR78 <= 1'b0;
VAR69 <= 1'b0;
VAR28 <= 1'b0;
VAR84 <= 1'b0;
VAR51 <= VAR74;
end else begin
case(VAR51)
VAR74: begin
VAR78 <= 1'b0;
if(VAR101)begin
VAR89[9:0] <= VAR100[9:0]
+ VAR53[9:0];
if(~VAR84)begin
VAR51 <= VAR74;
VAR69 <= 1'b0;
VAR78 <= 1'b0;
VAR84 <= 1'b1;
end else begin
VAR51 <= VAR105;
VAR69 <= 1'b1; VAR78 <= 1'b1;
VAR84 <= 1'b0;
end
end else if (VAR13)begin
VAR89[9:0] <= VAR100[9:0]
- {1'b0, VAR102[9:1]};
if(~VAR84)begin
VAR51 <= VAR74;
VAR28 <= 1'b0;
VAR78 <= 1'b0;
VAR84 <= 1'b1;
end else begin
VAR51 <= VAR105;
VAR28 <= 1'b1; VAR78 <= 1'b1;
VAR84 <= 1'b0;
end
end else begin
VAR89[9:0] <= VAR100[9:0];
VAR51 <= VAR74;
VAR28 <= 1'b0;
VAR69 <= 1'b0;
VAR84 <= 1'b0;
end
end
VAR105:begin
VAR28 <= 1'b0;
VAR69 <= 1'b0;
VAR51 <= VAR23;
VAR78 <= 1'b1;
VAR84 <= 1'b0;
end
VAR23:begin
VAR78 <= 1'b0;
VAR84 <= 1'b0;
VAR51 <= VAR74;
end
default:begin
VAR89[9:0] <= 0;
VAR78 <= 1'b0;
VAR69 <= 1'b0;
VAR28 <= 1'b0;
VAR84 <= 1'b0;
VAR51 <= VAR74;
end
endcase
end
end
always@(posedge clk)begin
if(VAR6 | (~VAR37))begin
if(VAR6)begin
VAR100[9:0] <= 0;
end else if(VAR78)begin
VAR100[9:0] <= VAR89[9:0];
end
end
always@(posedge clk)begin
VAR79 <= (VAR100[9:0] == 0) ? 1'b1 : 1'b0;
end
assign VAR107 = (VAR100[9:0] == 10'h000) ? 1'b1 : 1'b0;
VAR103 VAR2(
.clk(clk),
.rst(rst),
.in(VAR79),
.VAR85(VAR19)
);
VAR103 VAR91(
.clk(clk),
.rst(rst),
.in(VAR107),
.VAR85(VAR21)
);
always@(posedge clk)begin
if(VAR7 || VAR22[12:11] == 0)
VAR45 <= VAR19;
end
else
VAR45 <= VAR21;
end
endmodule
|
bsd-2-clause
|
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