repo_name
stringlengths 6
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| path
stringlengths 4
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| size
int64 1.02k
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| content
stringlengths 15
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| license
stringclasses 14
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|---|---|---|---|---|
davidkoltak/tawas-core
|
ip/rcn/rtl/rcn_bridge_buf.v
| 3,040 |
module MODULE1
(
input rst,
input clk,
input [68:0] VAR21,
output [68:0] VAR35,
input [68:0] VAR9,
output [68:0] VAR12
);
parameter VAR13 = 0;
parameter VAR32 = 1;
parameter VAR15 = 0;
parameter VAR18 = 1;
wire [5:0] VAR5 = VAR13;
wire [5:0] VAR22 = VAR32;
wire [23:0] VAR25 = VAR15;
wire [23:0] VAR40 = VAR18;
reg [68:0] VAR36;
reg [68:0] VAR37;
reg [68:0] VAR3;
reg [68:0] VAR1;
assign VAR35 = VAR37;
assign VAR12 = VAR1;
wire [68:0] VAR27;
wire VAR30;
wire VAR24;
wire [68:0] VAR8;
wire VAR6;
wire VAR39;
wire [68:0] VAR10;
wire VAR4;
wire VAR28;
wire [68:0] VAR31;
wire VAR14;
wire VAR41;
always @ (posedge clk or posedge rst)
if (rst)
begin
VAR36 <= 69'd0;
VAR37 <= 69'd0;
VAR3 <= 69'd0;
VAR1 <= 69'd0;
end
else
begin
VAR36 <= VAR21;
VAR37 <= (VAR6) ? VAR8 :
(VAR4) ? 69'd0 : VAR36;
VAR3 <= VAR9;
VAR1 <= (VAR14) ? VAR31 :
(VAR30) ? 69'd0 : VAR3;
end
wire VAR23 = ((VAR36[65:60] & VAR5) == VAR22);
wire VAR29 = ((VAR36[55:34] & VAR25[23:2]) == VAR40[23:2]);
assign VAR4 = !VAR28 && VAR36[68] &&
((VAR36[67] && VAR29) ||
(!VAR36[67] && VAR23));
assign VAR14 = !VAR41 && (!VAR3[68] || VAR30);
VAR19 VAR20
(
.rst(rst),
.clk(clk),
.VAR16(VAR36),
.VAR7(VAR4),
.VAR2(VAR28),
.VAR33(VAR31),
.VAR11(VAR14),
.VAR26(VAR41)
);
wire VAR17 = ((VAR3[65:60] & VAR5) == VAR22);
wire VAR38 = ((VAR3[55:34] & VAR25[23:2]) == VAR40[23:2]);
assign VAR30 = !VAR24 && VAR3[68] &&
((VAR3[67] && !VAR38) ||
(!VAR3[67] && !VAR17));
assign VAR6 = !VAR39 && (!VAR36[68] || VAR4);
VAR19 VAR34
(
.rst(rst),
.clk(clk),
.VAR16(VAR3),
.VAR7(VAR30),
.VAR2(VAR24),
.VAR33(VAR8),
.VAR11(VAR6),
.VAR26(VAR39)
);
endmodule
|
mit
|
travisg/cpu
|
rtl/sram-issi.v
| 2,622 |
module MODULE1 (VAR16, VAR14, VAR12, VAR20, VAR17, VAR1, VAR4);
parameter VAR13 = 16;
parameter VAR3 = 262143;
parameter VAR10 = 18;
parameter VAR18 = 2;
parameter VAR11 = 2;
VAR19 = 3,
VAR2 = 5;
VAR19 = 5,
VAR2 = 6;
input VAR12, VAR20, VAR17, VAR1, VAR4;
input [(VAR10 - 1) : 0] VAR16;
inout [(VAR13 - 1) : 0] VAR14;
wire [(VAR13 - 1) : 0] dout;
reg [(VAR13/2 - 1) : 0] VAR7 [0 : VAR3];
reg [(VAR13/2 - 1) : 0] VAR9 [0 : VAR3];
wire VAR5 = VAR17 & (~VAR12) & (~VAR20); wire VAR15 = (~VAR17) & (~VAR12) & ((~VAR1) | (~VAR4)); assign #(VAR5 ? VAR6 : VAR19) VAR14 = VAR5 ? dout : 16'VAR8;
begin
begin
|
mit
|
Progressive-Learning-Platform/progressive-learning-platform
|
reference/hw/verilog/mod_uart.v
| 6,300 |
module MODULE3(rst, clk, VAR23, VAR5, VAR33, VAR15, VAR2, din, VAR1, dout, VAR3, VAR26, VAR28, VAR25, VAR10);
input rst;
input clk;
input VAR23,VAR5;
input [31:0] VAR33, VAR15;
input [1:0] VAR2;
input [31:0] din;
output [31:0] VAR1, dout;
output VAR3;
input VAR26;
output VAR28;
output VAR25, VAR10;
wire [31:0] VAR13, VAR21;
assign VAR1 = VAR13;
assign dout = VAR21;
assign VAR13 = 32'h00000000;
wire VAR22,VAR16,VAR7,VAR30;
wire [7:0] VAR9;
reg [7:0] VAR12;
MODULE1 MODULE1(clk,VAR26,VAR3,VAR9,VAR12,VAR22,VAR30,VAR16,VAR7,rst);
assign VAR7 = (VAR5 && VAR2[0] && VAR15 == 32'h0) ? din[0] : 0;
assign VAR30 = (VAR5 && VAR2[0] && VAR15 == 32'h0) ? din[1] : 0;
assign VAR25 = VAR30;
assign VAR10 = VAR7;
assign VAR21 = (VAR15 == 32'h0) ? 0 :
(VAR15 == 32'h4) ? {30'h0,VAR22,VAR16} :
(VAR15 == 32'h8) ? {24'h0,VAR9} :
(VAR15 == 32'hc) ? {24'h0,VAR12} : 0;
assign VAR28 = VAR22;
always @(negedge clk) begin
if (VAR5 && VAR2[0] && VAR15 == 32'hc)
VAR12 = din[7:0];
end
endmodule
module MODULE2(clk,VAR17,VAR6,rst);
input clk,rst;
output VAR17;
output VAR6;
parameter VAR20 = 57600;
parameter VAR14 = 25000000;
parameter VAR32 = VAR14 / VAR20;
parameter VAR4 = VAR14 / (16 * VAR20);
reg [31:0] VAR8,VAR19;
assign VAR17 = (VAR8 == 0) ? 1 : 0;
assign VAR6 = (VAR19 == 0) ? 1 : 0;
always @(negedge clk) begin
VAR8 = VAR8 + 1;
VAR19 = VAR19 + 1;
if (VAR8 == VAR32)
VAR8 = 0;
if (VAR19 == VAR4)
VAR19 = 0;
if (rst) begin
VAR8 = 0;
VAR19 = 0;
end
end
endmodule
module MODULE1(clk,VAR26,VAR3,VAR9,VAR12,VAR22,VAR30,VAR16,VAR7,rst);
input clk,rst;
input VAR26;
input VAR30;
output reg [7:0] VAR9;
output reg VAR22;
output VAR16;
input [7:0] VAR12;
input VAR7;
output VAR3;
wire VAR17;
wire VAR6;
MODULE2 MODULE2(clk,VAR17,VAR6,rst);
reg [3:0] VAR11;
reg [3:0] VAR29;
wire VAR24 = (VAR29 == 0) ? 1 : 0;
always @(negedge clk) begin
if (rst) begin
VAR22 <= 0;
VAR11 <= 0;
end else if (VAR6) begin
if (VAR11 != 0)
VAR29 <= VAR29 + 1;
end
else
VAR29 <= 15;
case (VAR11)
0: if (!VAR26) VAR11 <= 1;
1: if (VAR24) VAR11 <= 2;
2: if (VAR24) begin VAR11 <= 3; VAR9[0] <= VAR26; end
3: if (VAR24) begin VAR11 <= 4; VAR9[1] <= VAR26; end
4: if (VAR24) begin VAR11 <= 5; VAR9[2] <= VAR26; end
5: if (VAR24) begin VAR11 <= 6; VAR9[3] <= VAR26; end
6: if (VAR24) begin VAR11 <= 7; VAR9[4] <= VAR26; end
7: if (VAR24) begin VAR11 <= 8; VAR9[5] <= VAR26; end
8: if (VAR24) begin VAR11 <= 9; VAR9[6] <= VAR26; end
9: if (VAR24) begin VAR11 <= 10; VAR9[7] <= VAR26; end
10: if (VAR24 & VAR26) begin VAR11 <= 0; VAR22 <= 1; end
default: if (VAR24) VAR11 <= 0;
endcase
end
if (VAR30)
VAR22 <= 0;
end
reg [3:0] VAR31;
assign VAR16 = (VAR31 == 0) ? 1 : 0;
always @(negedge clk) begin
if (VAR17) begin
case (VAR31)
1: VAR31 = 2;
2: VAR31 = 3;
3: VAR31 = 4;
4: VAR31 = 5;
5: VAR31 = 6;
6: VAR31 = 7;
7: VAR31 = 8;
8: VAR31 = 9;
9: VAR31 = 10;
10: VAR31 = 0;
default: VAR31 = 0;
endcase
end
if (VAR7)
VAR31 = 1;
end
assign VAR3 = (VAR31 == 0) ? 1 :
(VAR31 == 1) ? 1 :
(VAR31 == 2) ? 0 :
(VAR31 == 3) ? VAR12[0] :
(VAR31 == 4) ? VAR12[1] :
(VAR31 == 5) ? VAR12[2] :
(VAR31 == 6) ? VAR12[3] :
(VAR31 == 7) ? VAR12[4] :
(VAR31 == 8) ? VAR12[5] :
(VAR31 == 9) ? VAR12[6] :
(VAR31 == 10) ? VAR12[7] : 1;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.pp.blackbox.v
| 1,400 |
module MODULE1 (
VAR7 ,
VAR9,
VAR4,
VAR2 ,
VAR8 ,
VAR1,
VAR5,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR9;
input VAR4;
input VAR2 ;
input VAR8 ;
input VAR1;
input VAR5;
input VAR3 ;
input VAR6 ;
endmodule
|
apache-2.0
|
jlrandulfe/UviSpace
|
DE1-SoC/FPGA_Design/uvispace_top.v
| 27,985 |
module MODULE1(
inout VAR343,
output VAR185,
input VAR382,
output VAR32,
input VAR320,
inout VAR23,
inout VAR275,
output VAR347,
inout VAR301,
output VAR376,
input VAR9,
input VAR264,
input VAR417,
input VAR187,
output [12:0] VAR237, output [1:0] VAR96, output VAR192, output VAR348, output VAR214, output VAR217, inout [15:0] VAR19, output VAR102, output VAR219, output VAR26, output VAR160, output VAR286,
output VAR260,
inout VAR198,
inout [35:0] VAR109,
inout [35:0] VAR152,
output [6:0] VAR247,
output [6:0] VAR98,
output [6:0] VAR266,
output [6:0] VAR297,
output [6:0] VAR303,
output [6:0] VAR39,
inout VAR82,
output [14:0] VAR114,
output [2:0] VAR115,
output VAR336,
output VAR395,
output VAR119,
output VAR130,
output VAR288,
output [3:0] VAR238,
inout [31:0] VAR55,
inout [3:0] VAR261,
inout [3:0] VAR372,
output VAR154,
output VAR350,
output VAR22,
input VAR176,
output VAR11,
output VAR298,
inout VAR63,
output VAR16,
inout VAR201,
input VAR291,
input [3:0] VAR245,
input VAR374,
output [3:0] VAR213,
output VAR329,
inout [3:0] VAR123,
output VAR125,
output VAR58,
inout VAR375,
inout VAR337,
inout VAR362,
inout VAR2,
inout VAR380,
inout VAR416,
inout VAR289,
inout VAR262,
inout VAR276,
output VAR1,
inout VAR411,
inout [3:0] VAR18,
output VAR34,
input VAR317,
output VAR359,
inout VAR296,
input VAR21,
output VAR155,
input VAR13,
inout [7:0] VAR40,
input VAR404,
input VAR124,
output VAR313,
input VAR293,
output VAR44,
input [3:0] VAR233,
output [9:0] VAR67,
inout VAR99,
inout VAR391,
inout VAR377,
inout VAR146,
input [9:0] VAR361,
input VAR69,
input [7:0] VAR84,
input VAR57,
output VAR120,
input VAR251,
output [7:0] VAR142,
output VAR373,
output VAR143,
output [7:0] VAR225,
output VAR43,
output [7:0] VAR132,
output VAR141,
output VAR31
);
wire VAR104;
wire VAR318;
wire VAR50;
wire VAR93;
wire VAR271;
wire VAR381;
wire VAR116;
wire VAR101;
integer VAR164;
integer VAR255;
wire [11:0] VAR107;
wire [11:0] VAR277; wire VAR17; wire [15:0] VAR200;
wire [15:0] VAR45;
reg [11:0] VAR328; reg VAR269; reg VAR144; wire VAR181;
wire VAR419;
wire [31:0] VAR308;
wire [11:0] VAR64;
wire [11:0] VAR256;
wire [11:0] VAR334;
wire VAR363; reg [15:0] VAR227;
reg [15:0] VAR91;
wire [15:0] VAR194;
wire [15:0] VAR197;
VAR290 VAR323 (
.VAR390 ( VAR187 ),
.VAR330 ( VAR181 ),
.VAR403 ( VAR93 ),
.VAR134 ( VAR271 ),
.VAR151 ( VAR116 ),
.VAR246 ( VAR104 ),
.VAR402 ( VAR6 ),
.VAR25 ( VAR24 ),
.VAR236 ( VAR232 ),
.VAR35 ( VAR406 ),
.VAR365 ( VAR135 ),
.VAR332 ( VAR167 ),
.VAR94 ( VAR307 ),
.VAR223 ( VAR265 ),
.VAR398 ( VAR273 ),
.VAR95 ( VAR162 ),
.VAR306 ( VAR157 ),
.VAR357 ( VAR253 ),
.VAR60 ( VAR51 ),
.VAR413 ( VAR127 ),
.VAR165 ( VAR41 ),
.VAR351 ( VAR352 ),
.VAR284 ( VAR321 ),
.VAR353 ( VAR318 ),
.VAR4 ( VAR61 ),
.VAR242 ( VAR158 ),
.VAR56 ( VAR414 ),
.VAR231 ( VAR270 ),
.VAR285 ( VAR62),
.VAR385 ( VAR283 ),
.VAR136 ( VAR114 ),
.VAR206 ( VAR115 ),
.VAR113 ( VAR130 ),
.VAR191 ( VAR119 ),
.VAR418 ( VAR395 ),
.VAR48 ( VAR288 ),
.VAR59 ( VAR350 ),
.VAR83 ( VAR336 ),
.VAR70 ( VAR11 ),
.VAR356 ( VAR22) ,
.VAR409 ( VAR55 ),
.VAR388 ( VAR261 ),
.VAR140 ( VAR372 ),
.VAR86 ( VAR154 ),
.VAR54 ( VAR238 ),
.VAR106 ( VAR176 ),
.VAR203 ( VAR298 ),
.VAR354 ( VAR213[0] ),
.VAR156 ( VAR213[1] ),
.VAR234 ( VAR213[2] ),
.VAR159 ( VAR213[3] ),
.VAR129 ( VAR245[0] ),
.VAR358 ( VAR201 ),
.VAR272 ( VAR16 ),
.VAR396 ( VAR374 ),
.VAR312 ( VAR329 ),
.VAR299 ( VAR291 ),
.VAR66 ( VAR245[1] ),
.VAR407 ( VAR245[2] ),
.VAR20 ( VAR245[3] ),
.VAR8 ( VAR123[0] ),
.VAR224 ( VAR123[1] ),
.VAR302 ( VAR123[2] ),
.VAR339 ( VAR123[3] ),
.VAR177 ( VAR58 ),
.VAR386 ( VAR125 ),
.VAR186 ( VAR411 ),
.VAR244 ( VAR18[0] ),
.VAR267 ( VAR18[1] ),
.VAR282 ( VAR1 ),
.VAR105 ( VAR18[2] ),
.VAR295 ( VAR18[3] ),
.VAR226 ( VAR40[0] ),
.VAR389 ( VAR40[1] ),
.VAR14 ( VAR40[2] ),
.VAR168 ( VAR40[3] ),
.VAR310 ( VAR40[4] ),
.VAR170 ( VAR40[5] ),
.VAR173 ( VAR40[6] ),
.VAR42 ( VAR40[7] ),
.VAR81 ( VAR13 ),
.VAR393 ( VAR313 ),
.VAR397 ( VAR404 ),
.VAR47 ( VAR124 ),
.VAR304 ( VAR34 ),
.VAR205 ( VAR359 ),
.VAR182 ( VAR317 ),
.VAR368 ( VAR296 ),
.VAR401 ( VAR21 ),
.VAR324 ( VAR155 ),
.VAR210 ( VAR362 ),
.VAR412 ( VAR337 ),
.VAR327 ( VAR380 ),
.VAR249 ( VAR2 ),
.VAR74 ( VAR82 ),
.VAR150 ( VAR63 ),
.VAR333 ( VAR276 ),
.VAR153 ( VAR416 ),
.VAR147 ( VAR262 ),
.VAR76 ( VAR289 ),
.VAR355 ( VAR375 ),
.VAR314 ( ),
.VAR338 ( VAR361 ),
.VAR79 ( VAR233 )
);
VAR405 VAR85(
.VAR90 (VAR277), .VAR163 (VAR17), .VAR228 (VAR229),
.VAR342 (VAR180),
.VAR126 (VAR308), .VAR415 (VAR328), .VAR28 (VAR269), .VAR111 (VAR144), .VAR379 (VAR361[9]),
.VAR149 (VAR181),
.VAR103 (VAR104 & VAR50),
.VAR273 (VAR273[11:0]),
.VAR162 (VAR162[11:0])
);
wire [15:0] VAR273;
wire [15:0] VAR162;
wire [11:0] VAR229;
wire [11:0] VAR180;
assign VAR200 = {4'd0, VAR229};
assign VAR45 = {4'd0, VAR180};
assign VAR107[0] = VAR152[13]; assign VAR107[1] = VAR152[12]; assign VAR107[2] = VAR152[11]; assign VAR107[3] = VAR152[10]; assign VAR107[4] = VAR152[9]; assign VAR107[5] = VAR152[8]; assign VAR107[6] = VAR152[7]; assign VAR107[7] = VAR152[6]; assign VAR107[8] = VAR152[5]; assign VAR107[9] = VAR152[4]; assign VAR107[10] = VAR152[3]; assign VAR107[11] = VAR152[1]; assign VAR152[16] = VAR116; assign VAR38 = VAR152[22]; assign VAR325 = VAR152[21]; assign VAR181= VAR152[0]; assign VAR152[19] = 1'b1; assign VAR152[17] = VAR104 & VAR50;
assign VAR109[0] = VAR104 & VAR50;
assign VAR109[1] = VAR181;
always@(posedge VAR181)
begin
VAR328 <= VAR107;
VAR144 <= VAR325;
VAR269 <= VAR38;
end
VAR36 VAR73(
.VAR207 (VAR181),
.VAR274 (VAR104 & VAR50),
.VAR364 (VAR277), .VAR3 (VAR17), .VAR178 (VAR64), .VAR112 (VAR256), .VAR360 (VAR334), .VAR121 (VAR363), .VAR174 (VAR200),
.VAR108 (VAR45)
);
always @(posedge VAR181) begin
if (!VAR104 & VAR50) begin
end
else begin
if (VAR361[3]) begin
VAR227 <= {1'b0, VAR64[11:7], VAR256[11:7],
VAR334[11:7]};
VAR221 <= VAR363;
end
else begin
VAR227 <= {8'h00, VAR340[7:0]};
VAR221 <= VAR220;
end
end
end
VAR195 VAR394(
.VAR149(VAR181),
.VAR103(VAR104 & VAR50),
.VAR97(VAR64[11:4]),
.VAR345(VAR256[11:4]),
.VAR410(VAR334[11:4]),
.VAR319(VAR363),
.VAR77(1'b1),
.VAR202(1'b1),
.VAR349(VAR216),
.VAR335(VAR268),
.VAR243(VAR190),
.VAR199(VAR340),
.VAR163(VAR220),
.VAR37(),
.VAR383()
);
wire [7:0] VAR340;
wire [7:0] VAR216;
wire [7:0] VAR268;
wire [7:0] VAR190;
wire VAR220;
VAR326 VAR259 (
.clk ( VAR181 ),
.VAR103 (VAR104 & VAR50),
.VAR161( VAR216 ),
.VAR171( VAR268 ),
.VAR366( VAR190 ),
.VAR15( VAR340 ),
.VAR387( VAR269 ),
.VAR10( VAR220 ),
.VAR6( VAR6 ),
.VAR384( VAR24 ),
.VAR27( VAR232 ),
.VAR78( VAR406 ),
.VAR89( VAR135 ),
.VAR316( VAR167 ),
.VAR117( VAR307 ),
.VAR370 ( VAR265 ),
.address ( VAR61 ),
.write ( VAR158 ),
.VAR311 ( VAR414 ),
.VAR29 ( VAR270 ),
.VAR139 ( VAR62 ),
.VAR344 ( VAR283 )
);
wire VAR6; wire [15:0] VAR24; wire [15:0] VAR232; wire [31:0] VAR406; wire [31:0] VAR135; wire VAR167; wire VAR307; wire VAR265; wire [31:0]VAR61;
wire VAR158;
wire [3:0]VAR414;
wire [31:0]VAR270;
wire VAR62;
wire [6:0] VAR283;
VAR118 VAR7(
.VAR230(VAR187),
.VAR196(1'b1),
.VAR211(VAR227), .VAR53(VAR221),
.VAR322(0),
.VAR248(640*480), .VAR208(9'h80), .VAR287(!(VAR104 & VAR50)),
.VAR212(~VAR181),
.VAR133(VAR227), .VAR250(VAR221),
.VAR240(22'h100000),
.VAR80(22'h100000+640*480), .VAR209(9'h80), .VAR88(!(VAR104 & VAR50)),
.VAR128(~VAR181),
.VAR331(VAR194), .VAR138(VAR101), .VAR315(0),
.VAR408(640*480), .VAR218(9'h80), .VAR300(!(VAR104 & VAR50)),
.VAR131(~VAR93),
.VAR258(VAR197), .VAR280(VAR101), .VAR399(22'h100000),
.VAR188(22'h100000+640*480), .VAR341(9'h80), .VAR49(!(VAR104 & VAR50)),
.VAR184(~VAR93),
.VAR204(VAR237),
.VAR179(VAR96),
.VAR346(VAR217),
.VAR145(VAR348),
.VAR392(VAR219),
.VAR175(VAR192),
.VAR305(VAR160),
.VAR281(VAR19),
.VAR239({VAR26,VAR102}),
.VAR166(VAR214)
);
reg VAR221;
VAR5 VAR189(
.VAR52 ( VAR93 ),
.VAR103 ( VAR104 & VAR50 ),
.VAR46 ( VAR43 ),
.VAR122 ( VAR31 ),
.VAR65 ( VAR101 ),
.VAR378 (),
.VAR241 (),
.VAR71 ( VAR373 ),
.VAR137 ( VAR141 ),
.VAR371 ( VAR75 )
);
assign VAR132 = (!VAR101) ? 0 :
(!VAR361[3]) ? VAR194[7:0] :
(VAR361[0]) ? {VAR194[14:10], 3'd0} :
0;
assign VAR225 = (!VAR101) ? 0 :
(!VAR361[3]) ? VAR194[7:0] :
(VAR361[1]) ? {VAR194[9:5], 3'd0} :
0;
assign VAR142 = (!VAR101) ? 0 :
(!VAR361[3]) ? VAR194[7:0] :
(VAR361[2]) ? {VAR194[4:0], 3'd0} :
0;
assign VAR143 = VAR93;
VAR148 VAR87(
.VAR193 (VAR247),
.VAR222 (VAR98),
.VAR72 (VAR266),
.VAR30 (VAR297),
.VAR263 (VAR303),
.VAR92 (VAR39),
.VAR400 (),
.VAR172 (),
.VAR33 (VAR235)
);
wire [31:0] VAR235;
reg [31:0] VAR252;
reg [31:0] VAR294;
reg [31:0] VAR308;
reg VAR110;
reg pulse;
assign VAR67[0] = pulse;
assign VAR235 = (VAR361[8]) ? {16'h0, VAR127} : VAR294;
always @(posedge VAR187) begin
if (VAR252 < 50000000) begin
VAR252 = VAR252 + 1;
end
else begin
VAR252 = 0;
pulse = ~pulse;
VAR294 = VAR308 - VAR308;
VAR308 = VAR308;
end
end
VAR183 #(
.VAR279(25000000), .VAR367(20000) ) VAR369(
.VAR149(VAR181),
.VAR103(VAR104 & VAR50),
.VAR100(VAR127),
.VAR157(VAR215),
.VAR253(VAR278),
.VAR309(VAR41),
.VAR257(VAR352),
.VAR12(VAR321),
.VAR68(VAR51),
.VAR292(ready),
.VAR169(VAR152[24]),
.VAR254(VAR152[23])
);
wire ready;
wire [15:0] VAR127;
wire [15:0] VAR157;
wire [15:0] VAR253;
wire [15:0] VAR41;
wire [15:0] VAR352;
wire [15:0] VAR321;
wire [15:0] VAR51;
assign VAR50 = (VAR318 & VAR233[0]);
endmodule
|
gpl-3.0
|
toomij/DE2Labs
|
Lab2/lab2_part6.v
| 2,329 |
module MODULE2 (VAR28, VAR4, VAR5, VAR1, VAR16, VAR22, VAR26, VAR14, VAR9, VAR29, VAR2);
input [17:0] VAR28;
output [8:0] VAR5, VAR4;
output [0:6] VAR1, VAR16, VAR22, VAR26, VAR14, VAR9, VAR29, VAR2;
assign VAR5[8:0] = VAR28[8:0];
reg [4:0] VAR13, VAR19;
reg [3:0] VAR10, VAR21, VAR12, VAR27, VAR17;
reg VAR24, VAR18;
always begin
VAR19 = VAR28[3:0] + VAR28[11:8];
if (VAR19 > 9) begin
VAR21 = 10;
VAR18 = 1;
end else begin
VAR21 = 0;
VAR18 = 0;
end
VAR17 = VAR19 - VAR21;
VAR13 = VAR28[7:4] + VAR28[15:12] + VAR18;
if (VAR13 > 9) begin
VAR10 = 10;
VAR24 = 1;
end else begin
VAR10 = 0;
VAR24 = 0;
end
VAR27 = VAR13 - VAR10;
VAR12 = VAR24;
end
MODULE1 VAR23 (VAR17, VAR2);
MODULE1 VAR3 (VAR27, VAR29);
MODULE1 VAR11 (VAR12, VAR9);
assign VAR14 = 7'b1111111;
MODULE1 VAR25 (VAR28[3:0], VAR26);
MODULE1 VAR7 (VAR28[7:4], VAR22);
MODULE1 VAR6 (VAR28[11:8], VAR16);
MODULE1 VAR20 (VAR28[15:12], VAR1);
endmodule
module MODULE1 (VAR8, VAR15);
input [3:0] VAR8;
output [0:6] VAR15;
assign VAR15[0] = ((~VAR8[3] & ~VAR8[2] & ~VAR8[1] & VAR8[0]) | (~VAR8[3] & VAR8[2] & ~VAR8[1] & ~VAR8[0]));
assign VAR15[1] = ((~VAR8[3] & VAR8[2] & ~VAR8[1] & VAR8[0]) | (~VAR8[3] & VAR8[2] & VAR8[1] & ~VAR8[0]));
assign VAR15[2] = (~VAR8[3] & ~VAR8[2] & VAR8[1] & ~VAR8[0]);
assign VAR15[3] = ((~VAR8[3] & ~VAR8[2] & ~VAR8[1] & VAR8[0]) | (~VAR8[3] & VAR8[2] & ~VAR8[1] & ~VAR8[0]) | (~VAR8[3] & VAR8[2] & VAR8[1] & VAR8[0]) | (VAR8[3] & ~VAR8[2] & ~VAR8[1] & VAR8[0]));
assign VAR15[4] = ~((~VAR8[2] & ~VAR8[0]) | (VAR8[1] & ~VAR8[0]));
assign VAR15[5] = ((~VAR8[3] & ~VAR8[2] & ~VAR8[1] & VAR8[0]) | (~VAR8[3] & ~VAR8[2] & VAR8[1] & ~VAR8[0]) | (~VAR8[3] & ~VAR8[2] & VAR8[1] & VAR8[0]) | (~VAR8[3] & VAR8[2] & VAR8[1] & VAR8[0]));
assign VAR15[6] = ((~VAR8[3] & ~VAR8[2] & ~VAR8[1] & VAR8[0]) | (~VAR8[3] & ~VAR8[2] & ~VAR8[1] & ~VAR8[0]) | (~VAR8[3] & VAR8[2] & VAR8[1] & VAR8[0]));
endmodule
|
gpl-2.0
|
mosukiton/mipsprocessor
|
Mips_single_cycle.srcs/sources_1/new/alu.v
| 1,661 |
module MODULE1(
output reg [31:0] VAR10,
output reg VAR8,
input [31:0] VAR2,
input [31:0] VAR1,
input [2:0] VAR11
);
wire [31:0] VAR5, VAR7, VAR9, VAR4, VAR3, VAR6;
wire VAR12;
assign VAR5 = ~VAR1;
assign VAR7 = (VAR11[2]) ? VAR5 : VAR1;
assign {VAR12, VAR9} = VAR7 + VAR2 + VAR11[2];
assign VAR4 = VAR2 & VAR7;
assign VAR3 = VAR2 | VAR7;
assign VAR6 = {{31{1'b0}}, {VAR9[31]}};
always @ (VAR11[1:0] or VAR4 or VAR3 or VAR9 or VAR6 or VAR10) begin
case(VAR11[1:0])
2'b00: VAR10 = VAR4;
2'b01: VAR10 = VAR3;
2'b10: VAR10 = VAR9;
2'b11: VAR10 = VAR6;
endcase
if (VAR10 == 32'h00000000) begin
VAR8 <= 1;
end else begin
VAR8 <= 0;
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
models/udp_pwrgood_pp_p/sky130_fd_sc_ms__udp_pwrgood_pp_p.blackbox.v
| 1,251 |
module MODULE1 (
VAR2,
VAR1 ,
VAR3
);
output VAR2;
input VAR1 ;
input VAR3 ;
endmodule
|
apache-2.0
|
gbraad/minimig-de1
|
bench/cpu_cache_sdram/tg68_ram.v
| 1,473 |
module MODULE1 #(
parameter VAR8 = 512;
)(
input wire clk,
input wire VAR2,
input wire [ 32-1:0] VAR12,
input wire VAR5,
input wire VAR6,
input wire VAR1,
input wire [ 16-1:0] VAR7,
output wire [ 16-1:0] VAR9,
output wire VAR14
);
reg [8-1:0] VAR4 [0:VAR8-1];
reg [8-1:0] VAR10 [0:VAR8-1];
reg [16-1:0] VAR13 = 0;
reg VAR3 = 1;
reg ack = 1;
integer VAR11;
begin
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a22o/sky130_fd_sc_ms__a22o.blackbox.v
| 1,356 |
module MODULE1 (
VAR5 ,
VAR6,
VAR3,
VAR8,
VAR7
);
output VAR5 ;
input VAR6;
input VAR3;
input VAR8;
input VAR7;
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.pp.symbol.v
| 1,493 |
module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR9 ,
input VAR7 ,
input VAR2 ,
input VAR10 ,
input VAR8 ,
input VAR1,
input VAR4,
input VAR6
);
endmodule
|
apache-2.0
|
peteasa/oh
|
src/common/hdl/oh_mux8.v
| 1,280 |
module MODULE1 #(parameter VAR2 = 1 ) (
input VAR8,
input VAR1,
input VAR10,
input VAR14,
input VAR12,
input VAR17,
input VAR9,
input VAR3,
input [VAR2-1:0] VAR5,
input [VAR2-1:0] VAR13,
input [VAR2-1:0] VAR11,
input [VAR2-1:0] VAR6,
input [VAR2-1:0] VAR16,
input [VAR2-1:0] VAR15,
input [VAR2-1:0] VAR7,
input [VAR2-1:0] VAR4,
output [VAR2-1:0] out );
assign out[VAR2-1:0] = ({(VAR2){VAR3}} & VAR4[VAR2-1:0] |
{(VAR2){VAR9}} & VAR7[VAR2-1:0] |
{(VAR2){VAR17}} & VAR15[VAR2-1:0] |
{(VAR2){VAR12}} & VAR16[VAR2-1:0] |
{(VAR2){VAR14}} & VAR6[VAR2-1:0] |
{(VAR2){VAR10}} & VAR11[VAR2-1:0] |
{(VAR2){VAR1}} & VAR13[VAR2-1:0] |
{(VAR2){VAR8}} & VAR5[VAR2-1:0]);
endmodule
|
mit
|
Iuliiapl/schoolMIPS
|
src/sm_hex_display.v
| 2,556 |
module MODULE2
(
input [3:0] VAR5,
output reg [6:0] VAR1
);
always @*
case (VAR5)
'h0: VAR1 = 'b1000000; 'h1: VAR1 = 'b1111001;
'h2: VAR1 = 'b0100100; 'h3: VAR1 = 'b0110000; 'h4: VAR1 = 'b0011001; 'h5: VAR1 = 'b0010010; 'h6: VAR1 = 'b0000010; 'h7: VAR1 = 'b1111000; 'h8: VAR1 = 'b0000000; 'h9: VAR1 = 'b0011000; 'ha: VAR1 = 'b0001000; 'hb: VAR1 = 'b0000011;
'hc: VAR1 = 'b1000110;
'hd: VAR1 = 'b0100001;
'he: VAR1 = 'b0000110;
'hf: VAR1 = 'b0001110;
endcase
endmodule
module MODULE1
(
input VAR6,
input VAR2,
input [31:0] VAR4,
output reg [ 6:0] VAR1,
output reg VAR9,
output reg [ 7:0] VAR7
);
function [6:0] VAR10 (input [3:0] VAR8);
case (VAR8)
'h0: VAR10 = 'b1000000; 'h1: VAR10 = 'b1111001;
'h2: VAR10 = 'b0100100; 'h3: VAR10 = 'b0110000; 'h4: VAR10 = 'b0011001; 'h5: VAR10 = 'b0010010; 'h6: VAR10 = 'b0000010; 'h7: VAR10 = 'b1111000; 'h8: VAR10 = 'b0000000; 'h9: VAR10 = 'b0011000; 'ha: VAR10 = 'b0001000; 'hb: VAR10 = 'b0000011;
'hc: VAR10 = 'b1000110;
'hd: VAR10 = 'b0100001;
'he: VAR10 = 'b0000110;
'hf: VAR10 = 'b0001110;
endcase
endfunction
reg [2:0] VAR3;
always @ (posedge VAR6 or negedge VAR2)
begin
if (! VAR2)
begin
VAR1 <= VAR10 (0);
VAR9 <= ~ 0;
VAR7 <= ~ 8'b00000001;
VAR3 <= 0;
end
else
begin
VAR1 <= VAR10 (VAR4 [VAR3 * 4 +: 4]);
VAR9 <= ~ 0;
VAR7 <= ~ (1 << VAR3);
VAR3 <= VAR3 + 1;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlclkp/sky130_fd_sc_lp__dlclkp.symbol.v
| 1,276 |
module MODULE1 (
input VAR6 ,
input VAR7,
output VAR1
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/megafunctions/async_fifo_256x72_to_36_bb.v
| 6,420 |
module MODULE1 (
VAR4,
VAR9,
VAR2,
VAR6,
VAR7,
VAR1,
VAR3,
VAR10,
VAR5,
VAR8);
input VAR4;
input [71:0] VAR9;
input VAR2;
input VAR6;
input VAR7;
input VAR1;
output [35:0] VAR3;
output VAR10;
output [8:0] VAR5;
output VAR8;
tri0 VAR4;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/or2b/sky130_fd_sc_lp__or2b_4.v
| 2,127 |
module MODULE2 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR7,
VAR8,
VAR4 ,
VAR9
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR4 ;
input VAR9 ;
VAR6 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR5 ,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR3;
supply1 VAR7;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR9 ;
VAR6 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
lfmunoz/vhdl
|
ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_static_cmdgen.v
| 6,088 |
module MODULE1
parameter VAR19 = 32'h12A00000,
parameter VAR14 = 32 ,
parameter VAR9 = 4 , parameter VAR5 = 3,
parameter VAR7 = 0,
parameter VAR17 = 0
) (
input VAR28 ,
input VAR2 ,
input VAR6 ,
input [7:0] VAR11 ,
input [9:0] VAR30,
input [31:0] VAR15 ,
input [31:0] VAR1 ,
output [127:0] VAR21 ,
output [VAR14-1:0] VAR27 ,
output [127:0] VAR26
);
wire [2:0] VAR18;
generate if(VAR14 == 32 ) begin : VAR20
assign VAR18 = 3'b010;
end
endgenerate
generate if(VAR14 == 64 ) begin : VAR16
assign VAR18 = 3'b011;
end
endgenerate
generate if(VAR14 == 128 ) begin : VAR24
assign VAR18 = 3'b100;
end
endgenerate
generate if(VAR14 == 256 ) begin : VAR29
assign VAR18 = 3'b101;
end
endgenerate
generate if(VAR14 == 512 ) begin : VAR4
assign VAR18 = 3'b110;
end
endgenerate
wire [5:0] VAR22 = 6'h0;
wire [1:0] VAR23 = 2'b01;
reg [7:0] VAR12 = 8'h0;
always @(posedge VAR28) begin
VAR12[7:0] <= (VAR2) ? VAR11[7:0] : VAR5;
end
generate if(VAR7 == 0 &&
VAR17 == 0 ) begin : VAR25
assign VAR21 = {
32'h0,
32'h0,
VAR6,7'h0,3'b010,VAR22,VAR18,VAR23,2'b00,VAR12,
VAR19
};
assign VAR26 = {
32'h0,
32'h0,
VAR6,7'h0,3'b010,VAR22,VAR18,VAR23,2'b00,VAR12,
VAR19
};
assign VAR27[VAR14-1:0] = {
64'hCAFE5AFEC001CAFE,
64'hCAFE1AFEC001DAFE,
64'hCAFE2AFEC001EAFE,
64'hCAFE3AFEC001FAFE
};
end
endgenerate
wire VAR8;
wire VAR13;
wire VAR3;
assign VAR13 = (VAR30[VAR9] != 1'b1);
assign VAR3 = ~(&VAR15); assign VAR8 = VAR13 && VAR3;
generate if(VAR7 == 1 || VAR17 == 1 ) begin : VAR10
assign VAR21 = {
32'h0,
32'h0,
VAR8,7'h0,3'b010,VAR22,VAR18,VAR23,2'b00,8'h0,
VAR15[31:0]
};
assign VAR27[VAR14-1:0] = VAR1[31:0];
end
endgenerate
endmodule
|
mit
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v
| 4,370 |
module MODULE1 #(parameter VAR14(VAR36), parameter VAR14(VAR7), VAR4=VAR17((2**VAR7+VAR36-1)/VAR36), VAR16=VAR35(VAR36), VAR42=0)
(
input [VAR4-1:0] VAR8
, input [VAR16-1:0] VAR24
, output [VAR7-1:0] VAR19
);
if (VAR36 == 1)
begin: VAR21
assign VAR19 = VAR8;
end
else
if (VAR36 == 2)
begin: VAR28
assign VAR19 = { VAR24, VAR8 };
end
else
if (~VAR36[0])
begin: VAR33
assign VAR19[VAR7-1] = VAR24[0];
MODULE1 #(.VAR36(VAR36 >> 1),.VAR7(VAR7-1)) VAR1 ( .VAR8(VAR8[VAR4-1:0]),.VAR24(VAR24[VAR16-1:1]),.VAR19(VAR19[VAR7-2:0]));
end
else
if ((VAR36 & (VAR36+1)) == 0) begin : VAR13
if (VAR7 % VAR16)
begin : VAR43
wire VAR23;
MODULE1 #(.VAR36(VAR36),.VAR7(VAR7+1)) VAR26
( .VAR8({VAR8, 1'b0}), .VAR24(VAR24), .VAR19({VAR19[VAR7-1:0], VAR23}));
end
else
begin : VAR37
localparam VAR30 = VAR7/VAR16;
wire [VAR16-1:0][VAR30-1:0] VAR11;
wire [VAR7-1:0] VAR38 = (VAR7) ' (VAR8);
VAR18 #(.VAR7(VAR16), .VAR40(VAR30)) VAR32 (.VAR20(VAR38),.VAR19(VAR11));
genvar VAR10;
wire [VAR30-1:0] VAR15;
VAR27 #(.VAR9(VAR30),.VAR39(VAR16),.VAR25(1)) VAR34
(.VAR20(VAR38),.VAR19(VAR15));
wire [VAR30-1:0] VAR31;
VAR2 #(.VAR7(VAR30),.VAR12(1)) VAR5
(.VAR20(VAR15),.VAR19(VAR31));
wire [VAR30-1:0] VAR29;
if (VAR30 > 1)
assign VAR29 = VAR31 & ~{1'b0, VAR31[VAR30-1:1]};
end
else
assign VAR29 = VAR31;
wire [VAR16-1:0][VAR30-1:0] VAR41;
for (VAR10 = 0; VAR10 < VAR16; VAR10=VAR10+1)
begin: VAR22
assign VAR41[VAR10] = (VAR31 & ~VAR29 & VAR11[VAR10]) | (VAR29 & { VAR30 { VAR24[VAR10] }}) | ~VAR31;
end
wire [VAR7-1:0] VAR6;
VAR18 #(.VAR40(VAR16), .VAR7(VAR30)) VAR3 (.VAR20({VAR41}),.VAR19(VAR6));
assign VAR19 = VAR6[VAR7-1:0];
end
end
else
begin
end
|
bsd-3-clause
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Clock8346/Clock8346_stub.v
| 1,211 |
module MODULE1(VAR3, VAR2, VAR1)
;
input VAR3;
output VAR2;
output VAR1;
endmodule
|
gpl-3.0
|
vipinkmenon/fpgadriver
|
src/hw/fpga/source/pcie_if/reg_file.v
| 37,407 |
module MODULE1(
input VAR182, input VAR133, input [9:0] VAR19, input [31:0] VAR174, input VAR50, output VAR192, input VAR116, output reg VAR187, output reg [31:0] VAR138, output reg VAR21, output [31:0] VAR235, output VAR234, input VAR73, output VAR29, output [31:0] VAR108, output [31:0] VAR97, output VAR48, output [31:0] VAR15, output [31:0] VAR33, input VAR241, output VAR130, output VAR60,
input VAR233,
output VAR246,
output [31:0] VAR82,
output [31:0] VAR89,
output VAR101,
output [31:0] VAR2,
output [31:0] VAR242,
input VAR20,
output VAR26,
output VAR185,
input VAR172,
output VAR102,
output [31:0] VAR239,
output [31:0] VAR245,
output VAR81,
output [31:0] VAR126,
output [31:0] VAR163,
input VAR148,
output VAR35,
output VAR170,
input VAR252,
output VAR34,
output [31:0] VAR87,
output [31:0] VAR231,
output VAR14,
output [31:0] VAR69,
output [31:0] VAR117,
input VAR80,
output VAR114,
output VAR224, input VAR177, output VAR134, output [31:0] VAR184, output [31:0] VAR38, output VAR226,
input VAR158,
output VAR225,
output [31:0] VAR62, output [31:0] VAR220,
output VAR49, input VAR136, output VAR149, output [31:0] VAR165, output [31:0] VAR203, output VAR179,
input VAR40,
output VAR244,
output [31:0] VAR94, output [31:0] VAR45,
output VAR145, input VAR118, output VAR171, output [31:0] VAR115, output [31:0] VAR91, output VAR204,
input VAR68,
output VAR135,
output [31:0] VAR251, output [31:0] VAR72,
output VAR151, input VAR167, output VAR27, output [31:0] VAR120, output [31:0] VAR147, output VAR129,
input VAR25,
output VAR8,
output [31:0] VAR146, output [31:0] VAR9,
output VAR78, input VAR229, output VAR123, output [31:0] VAR212, output [31:0] VAR109, output VAR169, input VAR63, output wire [31:0] VAR65, output wire [31:0] VAR99, output wire [31:0] VAR210, output [31:0] VAR103, output reg VAR93, input VAR52, output reg VAR249, input VAR56, input wire [31:0] VAR132, output [31:0] VAR124, output reg VAR70, input VAR201, input VAR175, output VAR83, output VAR18, output VAR4, input VAR180,
input VAR200,
input VAR228,
output reg VAR58, output wire [1:0] VAR227, output VAR189, output [31:0] VAR110, input VAR240, output [6:0] VAR154, output reg VAR11, input [15:0] VAR43, input VAR202, output VAR71, output VAR104,
output [31:0] VAR195, output [31:0] VAR168, output [31:0] VAR215, output [31:0] VAR79, input [31:0] VAR173,
input [31:0] VAR248,
input VAR125,
input VAR44
);
parameter VAR74 = 32'h00000005;
localparam VAR30 = 'd0,
VAR183 = 'd1;
reg [31:0] VAR24;
reg [31:0] VAR119;
reg [31:0] VAR121;
reg [31:0] VAR153;
reg [31:0] VAR206;
reg [31:0] VAR161;
reg [31:0] VAR55;
reg [31:0] VAR193;
reg [31:0] VAR22;
reg [31:0] VAR77;
reg [31:0] VAR95;
reg [31:0] VAR54;
reg [31:0] VAR36;
reg [31:0] VAR142;
reg [31:0] VAR176;
reg [31:0] VAR64;
reg [31:0] VAR57;
reg [31:0] VAR66;
reg [31:0] VAR75;
reg [31:0] VAR90;
reg [31:0] VAR152;
reg [31:0] VAR207;
reg [31:0] VAR3;
reg [31:0] VAR250;
reg [31:0] VAR209;
reg [31:0] VAR28;
reg [31:0] VAR208;
reg [31:0] VAR211;
reg [31:0] VAR51;
reg [31:0] VAR12;
reg [31:0] VAR31;
reg [31:0] VAR162;
reg [31:0] VAR85;
reg [31:0] VAR16;
reg [31:0] VAR197;
reg [31:0] VAR181;
reg [31:0] VAR13;
reg [31:0] VAR46;
reg [31:0] VAR196;
reg [31:0] VAR219;
reg [31:0] VAR47;
reg [31:0] VAR156;
reg [31:0] VAR100;
reg [31:0] VAR127;
reg [31:0] VAR32;
reg [31:0] VAR218;
reg [31:0] VAR243;
reg [31:0] VAR222;
reg [31:0] VAR237;
reg [31:0] VAR216;
reg [15:0] VAR160;
reg [31:0] VAR37;
reg [31:0] VAR67;
reg VAR199;
reg VAR113;
reg VAR1;
reg VAR41;
reg VAR188;
reg VAR247;
reg VAR198;
reg VAR42;
reg VAR221;
reg VAR141;
reg VAR107;
reg VAR230;
reg VAR5;
reg VAR157;
reg VAR7;
reg VAR137;
reg VAR191;
reg VAR155;
reg VAR92;
reg VAR61;
reg VAR143;
reg VAR39;
reg VAR111;
reg VAR214;
reg VAR223;
reg VAR166;
reg VAR17;
reg VAR106;
reg VAR59;
reg VAR217;
reg VAR23;
reg VAR232;
reg VAR150;
reg VAR76;
reg VAR236;
reg [1:0] VAR186;
reg VAR10;
reg VAR88;
reg VAR131;
reg VAR190;
wire VAR159;
reg VAR178;
reg VAR122;
reg VAR96;
reg VAR238;
reg VAR105;
reg VAR128;
reg VAR112;
reg VAR213;
wire VAR53;
wire VAR98;
assign VAR53 = ((VAR19== VAR140)|(VAR19== VAR6)|(VAR19== VAR194)|(VAR19== VAR144)|(VAR19== VAR164)|(VAR19== VAR86)) ? 1'b1 : 1'b0;
assign VAR235 = VAR95;
assign VAR78 = VAR119[0];
assign VAR123 = VAR121[0];
assign VAR212 = VAR193;
assign VAR109 = VAR77;
assign VAR169 = VAR119[1];
assign VAR65 = VAR22;
assign VAR99 = VAR54;
assign VAR210 = VAR206;
assign VAR103 = VAR55;
assign VAR124 = VAR36;
assign VAR71 = VAR119[2];
assign VAR189 = VAR119[3];
assign VAR104 = 1'b0;
assign VAR234 = VAR119[4];
assign VAR29 = VAR121[4];
assign VAR108 = VAR75;
assign VAR97 = VAR90;
assign VAR48 = VAR119[5];
assign VAR130 = VAR121[5];
assign VAR15 = VAR152;
assign VAR33 = VAR207;
assign VAR224 = VAR119[6];
assign VAR134 = VAR121[6];
assign VAR184 = VAR209;
assign VAR38 = VAR28;
assign VAR226 = VAR119[7];
assign VAR225 = VAR121[7];
assign VAR220 = VAR250;
assign VAR62 = VAR3;
assign VAR60 = VAR119[8];
assign VAR246 = VAR121[8];
assign VAR82 = VAR208;
assign VAR89 = VAR211;
assign VAR101 = VAR119[9];
assign VAR26 = VAR121[9];
assign VAR2 = VAR51;
assign VAR242 = VAR12;
assign VAR49 = VAR119[10];
assign VAR149 = VAR121[10];
assign VAR165 = VAR31;
assign VAR203 = VAR162;
assign VAR179 = VAR119[11];
assign VAR244 = VAR121[11];
assign VAR45 = VAR16;
assign VAR94 = VAR85;
assign VAR185 = VAR119[12];
assign VAR102 = VAR121[12];
assign VAR239 = VAR197;
assign VAR245 = VAR181;
assign VAR81 = VAR119[13];
assign VAR35 = VAR121[13];
assign VAR126 = VAR13;
assign VAR163 = VAR46;
assign VAR145 = VAR119[14];
assign VAR171 = VAR121[14];
assign VAR115 = VAR196;
assign VAR91 = VAR219;
assign VAR204 = VAR119[15];
assign VAR135 = VAR121[15];
assign VAR72 = VAR156;
assign VAR251 = VAR47;
assign VAR170 = VAR119[16];
assign VAR34 = VAR121[16];
assign VAR87 = VAR100;
assign VAR231 = VAR127;
assign VAR14 = VAR119[17];
assign VAR114 = VAR121[17];
assign VAR69 = VAR32;
assign VAR117 = VAR218;
assign VAR151 = VAR119[18];
assign VAR27 = VAR121[18];
assign VAR120 = VAR243;
assign VAR147 = VAR222;
assign VAR129 = VAR119[19];
assign VAR8 = VAR121[19];
assign VAR9 = VAR216;
assign VAR146 = VAR237;
assign VAR18 = VAR153[0];
assign VAR227 = VAR153[2:1];
assign VAR195 = VAR142;
assign VAR168 = VAR176;
assign VAR215 = VAR64;
assign VAR79 = VAR57;
assign VAR110 = VAR66;
assign VAR192 = VAR1|VAR188;
assign VAR154 = VAR19[8:2];
assign VAR83 = VAR7 & VAR174[3];
assign VAR159 = |VAR121[19:0];
assign VAR98 = VAR50 & ~VAR213;
always @(posedge VAR182)
begin
VAR199 <= VAR56;
VAR113 <= VAR199;
VAR247 <= VAR63;
VAR198 <= VAR247;
VAR41 <= VAR52;
VAR188 <= VAR41;
VAR141 <= VAR202;
VAR107 <= VAR141;
VAR137 <= VAR177;
VAR191 <= VAR137;
VAR155 <= VAR158;
VAR92 <= VAR155;
VAR61 <= VAR136;
VAR143 <= VAR61;
VAR39 <= VAR40;
VAR111 <= VAR39;
VAR214 <= VAR118;
VAR223 <= VAR214;
VAR166 <= VAR68;
VAR17 <= VAR166;
VAR106 <= VAR167;
VAR59 <= VAR106;
VAR217 <= VAR25;
VAR23 <= VAR217;
VAR122 <= VAR178;
VAR178 <= VAR44 && VAR125;
VAR96 <= VAR178 & ~VAR122;
VAR238 <= VAR228;
VAR105 <= VAR238;
VAR128 <= VAR200;
VAR112 <= VAR128;
VAR213 <= VAR50;
end
always @(posedge VAR240)
begin
VAR5 <= VAR230;
VAR11 <= VAR5;
end
always @(*)
begin
case(VAR19)
VAR138 <= VAR74;
end
VAR138 <= VAR24;
end
VAR138 <= VAR119;
end
VAR138 <= VAR121;
end
VAR138 <= VAR193;
end
VAR138 <= VAR22;
end
VAR138 <= VAR77;
end
VAR138 <= VAR95;
end
VAR138 <= VAR54;
end
VAR138 <= VAR36;
end
VAR138 <= VAR206;
end
VAR138 <= VAR161;
end
VAR138 <= VAR153;
end
VAR138 <= VAR66;
end
VAR138 <= VAR37;
end
VAR138 <= VAR67;
end
default:begin
VAR138 <= VAR160;
end
endcase
end
always @(posedge VAR182)
begin
VAR1 <= 1'b0;
VAR21 <= 1'b0;
if(VAR98)
begin
VAR1 <= 1'b1;
case(VAR19)
VAR24 <= VAR174;
end
VAR153 <= VAR174;
end
VAR206 <= VAR174;
end
VAR55 <= VAR174;
VAR1 <= 1'b0;
end
VAR193 <= VAR174;
end
VAR22 <= VAR174;
end
VAR77 <= VAR174;
end
VAR95 <= VAR174;
VAR21 <= 1'b1;
end
VAR54 <= VAR174;
end
VAR36 <= VAR174;
end
VAR142 <= VAR174;
end
VAR176 <= VAR174;
end
VAR64 <= VAR174;
end
VAR57 <= VAR174;
end
VAR66 <= VAR174;
end
VAR75 <= VAR174;
end
VAR90 <= VAR174;
end
VAR152 <= VAR174;
end
VAR207 <= VAR174;
end
VAR3 <= VAR174;
end
VAR250 <= VAR174;
end
VAR209 <= VAR174;
end
VAR28 <= VAR174;
end
VAR208 <= VAR174;
end
VAR211 <= VAR174;
end
VAR51 <= VAR174;
end
VAR12 <= VAR174;
end
VAR85 <= VAR174;
end
VAR16 <= VAR174;
end
VAR31 <= VAR174;
end
VAR162 <= VAR174;
end
VAR197 <= VAR174;
end
VAR181 <= VAR174;
end
VAR13 <= VAR174;
end
VAR46 <= VAR174;
end
VAR47 <= VAR174;
end
VAR156 <= VAR174;
end
VAR196 <= VAR174;
end
VAR219 <= VAR174;
end
VAR100 <= VAR174;
end
VAR127 <= VAR174;
end
VAR32 <= VAR174;
end
VAR218 <= VAR174;
end
VAR237 <= VAR174;
end
VAR216 <= VAR174;
end
VAR243 <= VAR174;
end
VAR222 <= VAR174;
end
default:begin
VAR1 <= 1'b1;
end
endcase
end
end
always @(posedge VAR182)
begin
if(VAR116 & (VAR19 != VAR139) & ~VAR53)
VAR187 <= 1'b1;
end
else
VAR187 <= VAR113|VAR107;
end
always @(posedge VAR182)
begin
if(VAR113)
VAR249 <= 1'b0;
end
else if((VAR116 & VAR19 == VAR139))
begin
VAR249 <= 1'b1;
end
end
always @(posedge VAR182)
begin
if(VAR113)
begin
VAR161 <= VAR132;
end
end
always @(posedge VAR182)
begin
if(VAR107)
VAR230 <= 1'b0;
end
else if((VAR116 & VAR53) )
begin
VAR230 <= 1'b1;
end
end
always @(posedge VAR182)
begin
if(VAR107)
VAR160 <= VAR43;
end
always @(posedge VAR182)
begin
if(VAR188)
VAR93 <= 1'b0;
end
else if(VAR98 & (VAR19 == VAR139))
VAR93 <= 1'b1;
end
always @(posedge VAR182)
begin
if(!VAR133)
VAR119 <= 32'd0;
end
else
begin
if(VAR98 & (VAR19 == VAR205))
begin
VAR119 <= VAR119|VAR174; end
else
begin
if(VAR229)
VAR119[0] <= 1'b0;
if(VAR198)
VAR119[1] <= 1'b0;
if (!(VAR150 && VAR236)) VAR119[2] <= 1'b0;
if(VAR73)
VAR119[4] <= 1'b0;
if(VAR241)
VAR119[5] <= 1'b0;
if(VAR191)
VAR119[6] <= 1'b0;
if(VAR92)
VAR119[7] <= 1'b0;
if(VAR233)
VAR119[8] <= 1'b0;
if(VAR20)
VAR119[9] <= 1'b0;
if(VAR143)
VAR119[10] <= 1'b0;
if(VAR111)
VAR119[11] <= 1'b0;
if(VAR172)
VAR119[12] <= 1'b0;
if(VAR148)
VAR119[13] <= 1'b0;
if(VAR223)
VAR119[14] <= 1'b0;
if(VAR17)
VAR119[15] <= 1'b0;
if(VAR252)
VAR119[16] <= 1'b0;
if(VAR80)
VAR119[17] <= 1'b0;
if(VAR59)
VAR119[18] <= 1'b0;
if(VAR23)
VAR119[19] <= 1'b0;
end
end
end
always @(posedge VAR182)
begin
if(!VAR133)
begin
VAR121 <= 0;
VAR7 <= 1'b0;
end
else
begin
VAR7 <= 1'b0;
VAR121[31] <= VAR105;
VAR121[30] <= VAR112;
VAR121[29] <= VAR180;
if(VAR98 & (VAR19 == VAR84))
begin
VAR121[19:0] <= VAR121[19:0]^VAR174[19:0];
VAR7 <= 1'b1;
end
else
begin
if(VAR229)
VAR121[0] <= 1'b1; if(VAR198)
VAR121[1] <= 1'b1;
if(VAR96) VAR121[2] <= 1'b1;
if(VAR175 & ~VAR83)
VAR121[3] <= 1'b1;
if(VAR73)
VAR121[4] <= 1'b1;
if(VAR241)
VAR121[5] <= 1'b1;
if(VAR191)
VAR121[6] <= 1'b1;
if(VAR92)
VAR121[7] <= 1'b1;
if(VAR233)
VAR121[8] <= 1'b1;
if(VAR20)
VAR121[9] <= 1'b1;
if(VAR143)
VAR121[10] <= 1'b1;
if(VAR111)
VAR121[11] <= 1'b1;
if(VAR172)
VAR121[12] <= 1'b1;
if(VAR148)
VAR121[13] <= 1'b1;
if(VAR223)
VAR121[14] <= 1'b1;
if(VAR17)
VAR121[15] <= 1'b1;
if(VAR252)
VAR121[16] <= 1'b1;
if(VAR80)
VAR121[17] <= 1'b1;
if(VAR59)
VAR121[18] <= 1'b1;
if(VAR23)
VAR121[19] <= 1'b1;
end
end
end
always @(posedge VAR182)
begin
if(!VAR133)
begin
VAR157 <= VAR30;
VAR70 <= 1'b0;
end
else
begin
case(VAR157)
VAR30:begin
if(VAR159)
begin
VAR70 <= 1'b1;
VAR157 <= VAR183;
end
end
VAR183:begin
if(VAR201)
VAR70 <= 1'b0;
if(VAR7)
VAR157 <= VAR30;
end
endcase
end
end
always @(posedge VAR182)
begin
if(!VAR133)
begin
VAR232 <= 1'b1;
VAR76 <= 1'b1;
VAR150 <= 1'b1;
VAR236 <= 1'b1;
end
else begin
VAR232 <= VAR125;
VAR150 <= VAR232;
VAR76 <= VAR44;
VAR236 <= VAR76;
end
end
always @(posedge VAR182)
begin
if(!VAR133)
begin
VAR37 <= 32'd0;
VAR67 <= 32'd0;
end
else begin
if (VAR119[2] && (~VAR150))
VAR37 <= 32'd0; if (VAR119[2] && (~VAR236))
VAR67 <= 32'd0; if (VAR150)
VAR37 <= VAR173;
if (VAR236)
VAR67 <= VAR248;
end
end
always @(posedge VAR182)
begin
if(VAR186 != VAR153[2:1])
VAR88 <= 1'b1;
end
else if(VAR131)
VAR88 <= 1'b0;
VAR186 <= VAR153[2:1];
VAR190 <= VAR58;
VAR131 <= VAR190;
end
always @(posedge VAR240)
begin
VAR10 <= VAR88;
VAR58 <= VAR10;
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.pp.symbol.v
| 1,456 |
module MODULE1 (
input VAR8,
input VAR1,
input VAR4 ,
input VAR5 ,
output VAR9 ,
input VAR3 ,
input VAR2,
input VAR6,
input VAR7
);
endmodule
|
apache-2.0
|
Gilberto-Lopez/Arquitectura-Computadoras
|
Practica5/CUnit.v
| 5,751 |
module MODULE1(
input wire clk,
input wire reset,
output reg VAR1,
output reg [31:0] VAR26,
input wire [31:0] VAR34,
output reg VAR13,
output reg [9:0] VAR32,
input wire VAR21,
input wire VAR31,
input wire VAR15,
input wire [31:0] VAR25,
output reg [31:0] VAR18,
output reg [31:0] VAR37,
output reg [3:0] VAR5
);
localparam VAR6 = 5'd0;
localparam VAR36 = 5'd1;
localparam VAR33 = 5'd2;
localparam VAR14 = 5'd3;
localparam VAR12 = 5'd4;
localparam VAR2 = 5'd5;
localparam VAR7 = 5'd6;
localparam VAR11 = 5'd7;
localparam VAR8 = 5'd8;
localparam VAR28 = 5'd9;
localparam VAR27 = 5'd10;
localparam VAR9 = 5'd11;
localparam VAR30 = 5'd12;
localparam VAR24 = 5'd13;
localparam VAR23 = 5'd14;
localparam VAR19 = 5'd15;
localparam VAR22 = 5'd16;
localparam VAR10 = 4'd15;
reg [9:0] VAR29;
reg [31:0] VAR16 [15:0];
reg [31:0] VAR4;
reg [31:0] VAR20;
reg [31:0] VAR3;
reg [3:0] VAR35;
integer VAR17;
always @(posedge clk) begin
if (reset) begin
VAR29 = 10'b0;
for (VAR17 = 0; VAR17 < 16; VAR17 = VAR17 + 1) begin
VAR16[VAR17] = 32'b0;
end
VAR4 = 32'b0;
VAR20 = 32'b0;
VAR3 = 32'b0;
VAR35 = 4'b0;
VAR13 = 1;
end
else begin
case (VAR35)
4'h0: begin
VAR1 = 0; VAR32 = VAR29;
end
4'h2: begin
VAR20 = VAR34;
VAR29 = VAR29 + 1;
VAR13 = 0;
end
4'h3: VAR4 = VAR20;
endcase
case (VAR4[31:27]) VAR6: VAR35 = VAR10;
VAR36: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd0;
end
4'h6: VAR3 = VAR25;
4'h7: VAR16[VAR4[18:15]] = VAR3;
4'h8: VAR35 = VAR10;
endcase
end
VAR33: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd1;
end
4'h6: VAR3 = VAR25;
4'h7: VAR16[VAR4[18:15]] = VAR3;
4'h8: VAR35 = VAR10;
endcase
end
VAR14: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd2;
end
4'h6: VAR3 = VAR25;
4'h7: VAR16[VAR4[18:15]] = VAR3;
4'h8: VAR35 = VAR10;
endcase
end
VAR12: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd3;
end
4'h6: VAR3 = VAR25;
4'h7: VAR16[VAR4[18:15]] = VAR3;
4'h8: VAR35 = VAR10;
endcase
end
VAR2: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd7;
end
4'h6: VAR3 = VAR25;
4'h7: VAR16[VAR4[18:15]] = VAR3;
4'h8: VAR35 = VAR10;
endcase
end
VAR7: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd8;
end
4'h6: VAR3 = VAR25;
4'h7: VAR16[VAR4[18:15]] = VAR3;
4'h8: VAR35 = VAR10;
endcase
end
VAR11: begin
case (VAR35)
4'h4: begin
VAR18 = VAR16[VAR4[26:23]];
VAR5 = 4'd9;
end
4'h5: VAR3 = VAR25;
4'h6: VAR16[VAR4[22:19]] = VAR3;
4'h7: VAR35 = VAR10;
endcase
end
VAR8: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd4;
end
4'h6: if (VAR21) VAR16[VAR4[18:15]] = 32'b1;
end
else VAR16[VAR4[18:15]] = 32'b0;
4'h7: VAR35 = VAR10;
endcase
end
VAR28: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd5;
end
4'h6: if (VAR31) VAR16[VAR4[18:15]] = 32'b1;
end
else VAR16[VAR4[18:15]] = 32'b0;
4'h7: VAR35 = VAR10;
endcase
end
VAR27: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd6;
end
4'h6: if (VAR15) VAR16[VAR4[18:15]] = 32'b1;
end
else VAR16[VAR4[18:15]] = 32'b0;
4'h7: VAR35 = VAR10;
endcase
end
VAR9: begin
case (VAR35)
4'h4: begin
VAR13 = 1;
VAR1 = 0; VAR32 = VAR4[22:13];
end
4'h5: VAR20 = VAR34;
4'h7: begin
VAR16[VAR4[26:23]] = VAR20;
VAR13 = 0;
end
4'h8: VAR35 = VAR10;
endcase
end
VAR30: begin
case (VAR35)
4'h4: begin
VAR13 = 1;
VAR1 = 1; VAR32 = VAR4[22:13];
end
4'h5: VAR16[VAR4[26:23]] = VAR20;
4'h6: VAR26 = VAR20;
4'h8: begin
VAR35 = VAR10;
VAR13 = 0;
end
endcase
end
VAR24: begin
case (VAR35)
4'h4: VAR29 = VAR4[26:17];
4'h5: VAR35 = VAR10;
endcase
end
VAR23: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd5;
end
4'h6: if (VAR31) VAR29 = VAR4[18:9];
end
else VAR35 = VAR10;
4'h7: VAR35 = VAR10;
endcase
end
VAR19: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd4;
end
4'h6: if (VAR21) VAR29 = VAR4[18:9];
end
else VAR35 = VAR10;
4'h7: VAR35 = VAR10;
endcase
end
VAR22: begin
case (VAR35)
4'h4: VAR18 = VAR16[VAR4[26:23]];
4'h5: begin
VAR37 = VAR16[VAR4[22:19]];
VAR5 = 4'd6;
end
4'h6: if (VAR15) VAR29 = VAR4[18:9];
end
else VAR35 = VAR10;
4'h7: VAR35 = VAR10;
endcase
end
endcase
VAR35 = VAR35 + 1;
end end
endmodule
|
lgpl-3.0
|
dwaipayanBiswas/ECG-feature-extraction-using-DWT
|
ecg_top_stim.v
| 20,564 |
module MODULE1;
reg [15:0] VAR14;
reg clk, VAR10;
wire [15:0] VAR19,VAR3,VAR4,VAR7,
VAR12,VAR17,VAR13,VAR6,
VAR2,VAR8,VAR16,VAR9,VAR1,VAR20,VAR5,VAR15;
VAR11 VAR18 (VAR19,VAR3,VAR4,VAR7,
VAR12,VAR17,VAR13,VAR6,VAR2,VAR8,VAR16,VAR9,VAR1,VAR20,VAR5,
VAR15, VAR14,clk,VAR10);
always
begin
clk = 0;
clk = 1;
clk = 0;
end
begin
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.pp.blackbox.v
| 1,226 |
module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule
|
apache-2.0
|
alexforencich/verilog-ethernet
|
rtl/eth_phy_10g_tx.v
| 3,247 |
module MODULE1 #
(
parameter VAR10 = 64,
parameter VAR4 = (VAR10/8),
parameter VAR2 = 2,
parameter VAR5 = 0,
parameter VAR6 = 0,
parameter VAR1 = 0,
parameter VAR12 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR10-1:0] VAR7,
input wire [VAR4-1:0] VAR11,
output wire [VAR10-1:0] VAR9,
output wire [VAR2-1:0] VAR3,
output wire VAR13,
input wire VAR8
);
|
mit
|
neale/CS-program
|
474-VLSI/Lab_ADC/ADC_ROM_bb.v
| 5,039 |
module MODULE1 (
address,
VAR2,
VAR1);
input [10:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule
|
unlicense
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.v
| 2,204 |
module MODULE2 (
VAR5 ,
VAR1 ,
VAR2,
VAR4 ,
VAR3 ,
VAR8 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR2;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
VAR6 VAR9 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5 ,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR2;
supply1 VAR4;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR7 ;
VAR6 VAR9 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.v
| 2,546 |
module MODULE1 (
VAR13 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR7,
VAR2 ,
VAR10 ,
VAR12 ,
VAR4
);
output VAR13 ;
output VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR7;
input VAR2 ;
input VAR10 ;
input VAR12 ;
input VAR4 ;
VAR5 VAR11 (
.VAR13(VAR13),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR13 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR7
);
output VAR13 ;
output VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR7;
supply1 VAR2;
supply0 VAR10;
supply1 VAR12 ;
supply0 VAR4 ;
VAR5 VAR11 (
.VAR13(VAR13),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_std_synchronizer_nocut.v
| 6,568 |
module MODULE1 (
clk,
VAR2,
din,
dout
);
parameter VAR5 = 3; parameter VAR4 = 0;
input clk;
input VAR2;
input din;
output dout;
reg VAR3;
reg [VAR5-2:0] VAR1;
|
mit
|
ehliar/schematic_gui
|
mux4.v
| 1,177 |
module MODULE1 #(parameter VAR4 = 1) (input wire [1:0] VAR5,
input wire [VAR4:0] VAR1, VAR2, VAR3,VAR6,
output reg [VAR4:0] VAR7);
|
gpl-3.0
|
vad-rulezz/megabot
|
minsoc/rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
| 5,643 |
module MODULE1(
clk, rst,
VAR5, VAR12,
VAR11, VAR13, VAR10, VAR7,
VAR2, VAR6, VAR8
);
parameter VAR1 = VAR3;
input clk;
input rst;
input VAR5;
input [VAR4-1:0] VAR12;
input [VAR1-1:0] VAR11;
input [VAR1-1:0] VAR13;
input [VAR1-1:0] VAR10;
input [VAR1-1:0] VAR7;
output [VAR1-1:0] VAR2;
output [VAR1-1:0] VAR6;
output VAR8;
reg [VAR1-1:0] VAR2;
reg [VAR1-1:0] VAR6;
reg VAR8;
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR6 <= 32'd0;
VAR8 <= 1'b0;
end
else if (!VAR5) begin
VAR6 <= VAR2;
VAR8 <= VAR12[0];
end
end
always @(VAR11 or VAR13 or VAR10 or VAR7 or VAR12) begin
end
case(VAR12[VAR4-1:1]) else
case(VAR12[VAR4-1:1]) VAR9
2'b00: VAR2 = VAR11;
2'b01: begin
VAR2 = VAR13;
end
2'b10: begin
VAR2 = VAR10;
end
2'b11: begin
VAR2 = VAR7 + 32'h8;
end
endcase
end
endmodule
|
gpl-2.0
|
P3Stor/P3Stor
|
pcie/app/BMD_EP.v
| 31,548 |
module MODULE1#
(
parameter VAR155 = 128,
parameter VAR253 = 4'b0010,
parameter VAR128 = 8'h14
)
(
clk,
VAR278,
en,
VAR216,
VAR176,
VAR35,
VAR310,
VAR75,
VAR71,
VAR36,
VAR220,
VAR287,
VAR337,
VAR260,
VAR52,
VAR331,
VAR32,
VAR322,
VAR333,
VAR100,
VAR339,
VAR130,
VAR106,
VAR345,
VAR114,
VAR248,
VAR95,
VAR162,
VAR150,
VAR291,
VAR111,
VAR82,
VAR16,
VAR145,
VAR105,
VAR45,
VAR311,
VAR208,
VAR31,
VAR344,
VAR33,
VAR54,
VAR110,
VAR247,
VAR108,
VAR201,
VAR300,
VAR131,
VAR107,
VAR206,
VAR244,
VAR79,
VAR203,
VAR343,
VAR81,
VAR215,
VAR3,
VAR58,
VAR281,
VAR9,
VAR136,
VAR284,
VAR217,
VAR302,
VAR241,
VAR233,
VAR271,
VAR307,
VAR167,
VAR153,
VAR326,
VAR148,
VAR92,
VAR127,
VAR49,
VAR28,
VAR90,
VAR7,
VAR268,
VAR80,
VAR235,
VAR348,
VAR123,
VAR39,
VAR177,
VAR125,
VAR275,
VAR324,
VAR98,
VAR179,
VAR142,
VAR237,
VAR296,
VAR191,
VAR29,
VAR64,
VAR143,
VAR101 , VAR254,
VAR195,
VAR187,
VAR294,
VAR329,
VAR68,
VAR165,
VAR180
);
input VAR64;
input [31:0] VAR143;
output VAR101 ; input [31:0] VAR254;
input [31:0] VAR195;
input [31:0] VAR187;
input [31:0] VAR294;
output VAR329;
input VAR68;
input [31:0] VAR165;
input [10:0] VAR180;
input clk;
input VAR278;
input en;
output [VAR155-1:0] VAR216;
output [(VAR155/8)-1:0] VAR176;
output VAR35;
output VAR310;
output VAR75;
output VAR71;
input VAR36;
input VAR220;
input [5:0] VAR287;
output VAR337;
input [VAR155-1:0] VAR260;
input [(VAR155/8)-1:0] VAR52;
input VAR331;
input VAR32;
input VAR322;
input VAR333;
output VAR100;
input [6:0] VAR339;
output VAR130;
output VAR106;
output [6:0] VAR345;
output VAR114;
output [7:0] VAR248;
input VAR95;
input [31:0] VAR162;
output [3:0] VAR150;
output [31:0] VAR291;
input VAR111;
input [6:0] VAR82;
input [3:0] VAR16;
input [31:0] VAR145;
output VAR105;
input VAR45;
input [6:0] VAR311;
input [3:0] VAR208;
input [31:0] VAR31;
output VAR344;
input VAR33;
input [6:0] VAR54;
input [3:0] VAR110;
input [31:0] VAR247;
output VAR108;
output VAR201;
output VAR300;
output [127:0] VAR131;
input VAR107;
output VAR206;
input [127:0] VAR244;
input VAR79;
output VAR203;
output VAR343;
output VAR81;
output VAR215;
output VAR3;
output [1:0] VAR58;
input [5:0] VAR281;
output [1:0] VAR9;
output VAR136;
output VAR284;
output VAR217;
input [1:0] VAR302;
input VAR241;
input VAR233;
input VAR271;
input [2:0] VAR307;
input VAR167;
input [1:0] VAR153;
output VAR326;
output VAR148;
output VAR92;
input [31:0] VAR127;
output VAR49;
input VAR28;
output VAR90;
output [7:0] VAR7;
input [7:0] VAR268;
input [2:0] VAR80;
input VAR235;
input [15:0] VAR348;
input VAR123;
input VAR29;
input [5:0] VAR39;
input [5:0] VAR177;
input [3:0] VAR125;
input [3:0] VAR275;
input [2:0] VAR324;
input [2:0] VAR98;
input [2:0] VAR179;
input VAR142;
input VAR237;
input VAR296;
input [1:0] VAR191;
wire [3:0] VAR219;
wire [31:0] VAR317;
wire [10:0] VAR316;
wire [7:0] VAR168;
wire [31:0] VAR30;
wire VAR224;
wire VAR210;
wire VAR321;
wire VAR267;
wire [2:0] VAR231;
wire VAR202;
wire VAR104;
wire [1:0] VAR308;
wire [9:0] VAR277;
wire [15:0] VAR214;
wire [7:0] VAR226;
wire [7:0] VAR262;
wire VAR84;
wire VAR318;
wire VAR188;
wire VAR257;
wire [15:0] VAR265;
wire [7:0] VAR258;
wire [3:0] VAR91;
wire [3:0] VAR204;
wire [31:0] VAR283;
wire [31:0] VAR194;
wire [31:0] VAR198;
wire [2:0] VAR97;
wire VAR193;
wire VAR298;
wire [7:0] VAR73;
wire VAR327;
wire VAR270;
wire [7:0] VAR78;
wire VAR25;
wire VAR280;
wire VAR323;
wire [15:0] VAR115;
wire [7:0] VAR183;
wire [3:0] VAR18;
wire [3:0] VAR62;
wire [31:0] VAR43;
wire [31:0] VAR209;
wire [2:0] VAR264;
wire VAR38;
wire VAR118;
wire [7:0] VAR297;
wire VAR122;
wire VAR113;
wire [7:0] VAR11;
wire [7:0] VAR288;
wire [7:0] VAR37;
wire [31:0] VAR88;
wire VAR215;
wire VAR232;
wire VAR312;
wire VAR251;
wire VAR178;
wire VAR26;
wire [1:0] VAR295;
wire [1:0] VAR20;
wire VAR282;
wire VAR56;
reg [5:0] VAR221;
reg [1:0] VAR48;
reg VAR175;
reg VAR338;
reg VAR72;
reg [2:0] VAR261;
reg VAR109;
reg [1:0] VAR189;
wire [31:0] VAR149;
wire [31:0] VAR146;
wire [31:0] VAR161;
wire [31:0] VAR156;
wire [31:0] VAR259;
wire VAR330;
wire VAR301;
wire VAR13;
wire [6:0] VAR102;
wire [7:0] VAR336;
wire [31:0] VAR134;
wire [3:0] VAR14;
wire [31:0] VAR5;
wire VAR342;
wire [7:0] VAR184;
wire [31:0] VAR239;
wire [6:0] VAR242;
wire [3:0] VAR315;
wire [31:0] VAR325;
wire VAR12;
assign VAR343 = VAR318;
assign VAR215 = VAR25;
assign VAR81 = VAR257;
assign VAR3 = VAR323;
assign VAR300 = VAR12;
assign VAR130 = VAR251;
assign VAR337 = VAR178;
assign VAR106 = ~VAR232;
assign VAR114 = (!VAR339[0]) ? VAR224 : 1'b0;
assign VAR13 = (!VAR339[1]) ? VAR224 : 1'b0;
assign VAR345 = (!VAR339[0]) ? VAR316[6:0] : 7'b0;
assign VAR102 = (!VAR339[1]) ? VAR316[6:0] : 7'b0;
assign VAR248 = (!VAR339[0]) ? VAR168 : 8'b0;
assign VAR336 = (!VAR339[1]) ? VAR168 : 8'b0;
assign VAR161 = { VAR30[7:0] , VAR30[15:8] , VAR30[23:16] , VAR30[31:24] };
assign VAR291 = (!VAR339[0]) ? VAR161 : 32'b0;
assign VAR134 = (!VAR339[1]) ? VAR161 : 32'b0;
assign VAR210 = (!VAR339[0]) ? VAR95 : ( (!VAR339[1]) ? VAR12 : 1'b0 );
assign VAR150 = (!VAR339[0]) ? VAR219 : 4'b0;
assign VAR14 = (!VAR339[1]) ? VAR219 : 4'b0;
assign VAR317 = (!VAR339[0]) ? VAR162 : ( (!VAR339[1]) ? VAR5 : 32'b0 );
always @(posedge clk) begin
if (!VAR278) begin
VAR221 <= 6'b0;
VAR48 <= 2'b0;
VAR175 <= 1'b0;
VAR338 <= 1'b0;
VAR72 <= 1'b0;
VAR261 <= 3'b0;
VAR109 <= 1'b0;
VAR189 <= 2'b0;
end else begin
VAR221 <= VAR281;
VAR48 <= VAR302;
VAR175 <= VAR241;
VAR338 <= VAR233;
VAR72 <= VAR271;
VAR261 <= VAR307;
VAR109 <= VAR167;
VAR189 <= VAR153;
end
end
VAR96#(
.VAR253(VAR253),
.VAR128(VAR128)
)
VAR147 (
.clk(clk), .VAR278(VAR278), .en(en),
.VAR39(VAR39), .VAR177(VAR177),
.VAR125(VAR125), .VAR275(VAR275),
.VAR324(VAR324), .VAR98(VAR98), .VAR179(VAR179),
.VAR292(VAR242),
.VAR340(VAR315), .VAR230(VAR325),
.VAR192(VAR184), .VAR246(VAR239), .VAR8(VAR342), .VAR256(VAR12),
.VAR158(VAR84),
.VAR215(VAR25), .VAR207(VAR323), .VAR120(VAR43), .VAR1(VAR115), .VAR103(VAR156), .VAR264(VAR264), .VAR38(VAR38), .VAR303(VAR27), .VAR297(VAR297), .VAR63(VAR122), .VAR313(VAR113), .VAR15(VAR11), .VAR330(VAR330),
.VAR343(VAR318), .VAR124(VAR257), .VAR159(VAR283), .VAR19(VAR265), .VAR47(VAR259), .VAR97(VAR97), .VAR193(VAR193), .VAR305(VAR174), .VAR73(VAR73), .VAR346(VAR327), .VAR289(VAR270), .VAR263(VAR78), .VAR301(VAR301),
.VAR255(VAR288), .VAR306(VAR37),
.VAR58( VAR58 ),
.VAR281( VAR221 ),
.VAR9( VAR9 ),
.VAR136( VAR136 ),
.VAR284( VAR284 ),
.VAR217( VAR217 ),
.VAR302( VAR48 ),
.VAR241( VAR175 ),
.VAR233( VAR338 ),
.VAR271( VAR72 ),
.VAR307( VAR261 ),
.VAR167( VAR109 ),
.VAR153( VAR189 ),
.VAR42( VAR42 ),
.VAR152( VAR152 ),
.VAR181( VAR181 ),
.VAR332( VAR332 ),
.VAR347( VAR347 ),
.VAR186(VAR88), .VAR228(VAR127), .VAR17(VAR92), .VAR135(VAR232), .VAR61(VAR312), .VAR7(VAR7), .VAR268(VAR268), .VAR80(VAR80), .VAR235(VAR235), .VAR26(VAR26),
.VAR251(VAR251), .VAR178 ( VAR178 )
);
VAR129 VAR205 (
.VAR58(VAR58),
.VAR9(VAR9),
.VAR136(VAR136),
.VAR284(VAR284),
.VAR302(VAR48),
.VAR241(VAR175),
.VAR281( VAR221 ),
.clk(clk),
.VAR278(VAR278),
.VAR42(VAR42),
.VAR152(VAR152),
.VAR181(VAR181),
.VAR332(VAR332),
.VAR347(VAR347)
);
VAR236 VAR141 (
.clk(clk), .VAR278(VAR278),
.VAR138(VAR84),
.VAR260(VAR260),
.VAR52(VAR52),
.VAR331(VAR331), .VAR32(VAR32), .VAR322(VAR322), .VAR333(VAR333), .VAR100(VAR100), .VAR339 (VAR339),
.VAR326(VAR321), .VAR121(VAR267),
.VAR119(VAR316),
.VAR169(VAR231), .VAR249(VAR202), .VAR67(VAR104), .VAR6(VAR308), .VAR51(VAR277), .VAR85(VAR214), .VAR34(VAR226), .VAR279(VAR262),
.VAR269(VAR168), .VAR151(VAR30), .VAR238(VAR224), .VAR304(VAR210),
.VAR131(VAR131),
.VAR107(VAR107),
.VAR206(VAR206),
.VAR133(VAR288), .VAR53(VAR37),
.VAR172(VAR156),
.VAR3(),
.VAR330(VAR330),
.VAR74(VAR88), .VAR23(), .VAR92(VAR92)
);
VAR290 VAR66 (
.clk(clk), .VAR278(VAR278),
.VAR216(VAR216),
.VAR176(VAR176),
.VAR35(VAR35), .VAR310(VAR310), .VAR75(VAR75), .VAR71(VAR71), .VAR36(VAR36), .VAR220(VAR220), .VAR287(VAR287),
.VAR46(VAR321), .VAR148(VAR267),
.VAR163(VAR231), .VAR227(VAR202), .VAR154(VAR104), .VAR86(VAR308), .VAR166(VAR277), .VAR21(VAR214), .VAR77(VAR226), .VAR314(VAR262), .VAR41(VAR316),
.VAR299(), .VAR65(VAR219), .VAR234(VAR317),
.VAR138(VAR84),
.VAR112(VAR200), .VAR69(VAR43), .VAR274(VAR115), .VAR172(VAR156), .VAR320(VAR264), .VAR190(VAR38), .VAR252(1'b1 ), .VAR76(VAR297), .VAR222(4'hF),
.VAR212(4'hF),
.VAR83(8'h0),
.VAR276(VAR146),
.VAR285(VAR122), .VAR335(VAR113), .VAR319(VAR11), .VAR330(VAR330),
.VAR323(VAR323),
.VAR89(VAR293), .VAR81(VAR257), .VAR199(VAR283), .VAR243(VAR265), .VAR2(VAR259), .VAR116(VAR97), .VAR211(VAR193), .VAR94(1'b1 ), .VAR50(VAR73), .VAR229(4'hF),
.VAR197(4'hF),
.VAR132(8'h0),
.VAR223(VAR327), .VAR182(VAR270), .VAR213(VAR78), .VAR301(VAR301),
.VAR244(VAR244),
.VAR79(VAR79),
.VAR203(VAR203),
.VAR144(VAR348), .VAR117(VAR123), .VAR160(VAR29), .VAR139(VAR296), .VAR185(VAR191),
.VAR64(VAR64),
.VAR143(VAR143),
.VAR101(VAR101) , .VAR254(VAR254),
.VAR195(VAR195),
.VAR187(VAR187),
.VAR294(VAR294),
.VAR329(VAR329),
.VAR68(VAR68),
.VAR165(VAR165),
.VAR180(VAR180)
);
assign VAR326 = VAR321;
assign VAR148 = VAR267;
VAR245 VAR44(
.clk(clk),
.VAR278(VAR278),
.VAR138(VAR84),
.VAR112(VAR25),
.VAR274(VAR115),
.VAR93(VAR146),
.VAR228(VAR127),
.VAR309(),
.VAR87(VAR312),
.VAR89(VAR318),
.VAR24(VAR287),
.VAR225(VAR200),
.VAR240(VAR293)
);
VAR341 VAR140(
.VAR278(VAR278),
.VAR138(VAR84),
.VAR250(VAR13),
.VAR40(VAR102),
.VAR218(VAR336[3:0]),
.VAR171(VAR134),
.VAR60(VAR111),
.VAR286(VAR82),
.VAR70(VAR16),
.VAR173(VAR145),
.VAR10(VAR45),
.VAR157(VAR311),
.VAR196(VAR208),
.VAR328(VAR31),
.VAR164(VAR33),
.VAR266(VAR54),
.VAR55(VAR110),
.VAR57(VAR247),
.VAR137(VAR14),
.VAR334(VAR5),
.VAR238(VAR342),
.VAR119(VAR242),
.VAR269(VAR184[3:0]),
.VAR273(VAR239),
.VAR170(VAR272),
.VAR22(VAR105),
.VAR126(VAR344),
.VAR59(VAR108),
.VAR65(VAR315),
.VAR99(VAR325),
.VAR4(VAR201)
);
endmodule
|
gpl-2.0
|
vvk/sysrek
|
uart_echo/UART_loop.v
| 1,417 |
module MODULE1(
input VAR8,
output VAR4,
input VAR21,
output [7:0]VAR12
);
wire [7:0]VAR19;
reg [7:0]VAR10;
reg VAR5 = 1'b0;
reg VAR14 = 1'b0;
reg VAR1 = 1'b0;
wire VAR16;
wire VAR2;
VAR7 # (
.VAR15(100000000),
.VAR20(115200)
)VAR13 (
.VAR17(VAR21),
.VAR18(VAR19),
.VAR14(VAR14),
.VAR1(VAR1),
.VAR9(VAR8),
.VAR16(VAR16)
);
VAR22 # (
.VAR15(100000000),
.VAR20(115200)
) VAR11 (
.VAR17(VAR21),
.VAR18(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR4),
.VAR2(VAR2)
);
assign VAR12 = VAR19;
reg VAR3 = 1'b0;
reg VAR23 = 1'b0;
always @(posedge VAR21) begin
if (VAR23 == 1'b0 && VAR16 == 1'b1) begin
VAR14 <= 1'b1;
VAR10 <= VAR19;
VAR5 <= 1'b1;
VAR3 <= !VAR3;
end else begin
VAR14 <= 1'b0;
VAR5 <= 1'b0;
end
VAR23 <= VAR16;
end
endmodule
|
gpl-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.behavioral.pp.v
| 6,220 |
module MODULE1( VAR50, VAR52, VAR45, VAR47, VAR42, VAR8, VAR17 );
input VAR45, VAR50, VAR52, VAR47;
inout VAR8, VAR17;
output VAR42;
reg VAR12;
VAR61 VAR2(.VAR50(VAR50),.VAR52(VAR52),.VAR45(VAR45),.VAR47(VAR47),.VAR42(VAR42),.VAR8(VAR8),.VAR17(VAR17),.VAR12(VAR12));
VAR61 VAR60(.VAR50(VAR50),.VAR52(VAR52),.VAR45(VAR45),.VAR47(VAR47),.VAR42(VAR42),.VAR8(VAR8),.VAR17(VAR17),.VAR12(VAR12));
and VAR55(VAR11,VAR47,VAR52);
not VAR31(VAR21,VAR45);
and VAR20(VAR38,VAR52,VAR21);
and VAR51(VAR14,VAR47,VAR38);
and VAR63(VAR27,VAR52,VAR45);
and VAR24(VAR7,VAR47,VAR27);
buf VAR41(VAR37,VAR47);
not VAR13(VAR29,VAR45);
not VAR39(VAR48,VAR50);
and VAR4(VAR19,VAR48,VAR29);
and VAR9(VAR6,VAR47,VAR19);
not VAR59(VAR32,VAR50);
and VAR54(VAR28,VAR32,VAR45);
and VAR44(VAR3,VAR47,VAR28);
not VAR58(VAR16,VAR45);
not VAR46(VAR62,VAR50);
and VAR25(VAR36,VAR62,VAR16);
not VAR65(VAR49,VAR50);
and VAR33(VAR34,VAR49,VAR45);
buf VAR43(VAR64,VAR52);
not VAR22(VAR23,VAR45);
not VAR18(VAR30,VAR50);
and VAR56(VAR40,VAR30,VAR23);
and VAR57(VAR35,VAR52,VAR40);
not VAR26(VAR10,VAR50);
and VAR15(VAR5,VAR10,VAR45);
and VAR53(VAR1,VAR52,VAR5);
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a2111o/sky130_fd_sc_ls__a2111o_2.v
| 2,448 |
module MODULE2 (
VAR3 ,
VAR9 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR10,
VAR12,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR10;
input VAR12;
input VAR2 ;
input VAR6 ;
VAR11 VAR1 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3 ,
VAR9,
VAR4,
VAR5,
VAR7,
VAR8
);
output VAR3 ;
input VAR9;
input VAR4;
input VAR5;
input VAR7;
input VAR8;
supply1 VAR10;
supply0 VAR12;
supply1 VAR2 ;
supply0 VAR6 ;
VAR11 VAR1 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a2111o/sky130_fd_sc_ms__a2111o_1.v
| 2,448 |
module MODULE1 (
VAR4 ,
VAR3 ,
VAR11 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR6,
VAR12,
VAR8 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR11 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR6;
input VAR12;
input VAR8 ;
input VAR2 ;
VAR7 VAR10 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR4 ,
VAR3,
VAR11,
VAR9,
VAR1,
VAR5
);
output VAR4 ;
input VAR3;
input VAR11;
input VAR9;
input VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR12;
supply1 VAR8 ;
supply0 VAR2 ;
VAR7 VAR10 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.v
| 2,345 |
module MODULE1 (
VAR8 ,
VAR7 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR2,
VAR5,
VAR11 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR2;
input VAR5;
input VAR11 ;
input VAR6 ;
VAR4 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8 ,
VAR7,
VAR1 ,
VAR10,
VAR9
);
output VAR8 ;
input VAR7;
input VAR1 ;
input VAR10;
input VAR9;
supply1 VAR2;
supply0 VAR5;
supply1 VAR11 ;
supply0 VAR6 ;
VAR4 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
|
apache-2.0
|
monotone-RK/FACE
|
IEICE-Trans/bandwidth/PCIe/src/riffa/translation_xilinx.v
| 10,699 |
module MODULE1
parameter VAR79 = 256
)
(
input VAR31,
input VAR18,
input [VAR79-1:0] VAR86,
input [(VAR79/8)-1:0] VAR32,
input VAR26,
input VAR40,
output VAR30,
input [VAR83-1:0] VAR37,
output VAR12,
output VAR48,
output [VAR79-1:0] VAR16,
output [(VAR79/8)-1:0] VAR68,
output VAR41,
output VAR74,
input VAR66,
output [VAR1-1:0] VAR63,
output VAR58,
input [VAR87-1:0] VAR50,
input [VAR84-1:0] VAR77,
input [VAR49-1:0] VAR54,
input [VAR78-1:0] VAR56,
input [VAR78-1:0] VAR19,
input [VAR78-1:0] VAR64,
input [VAR78-1:0] VAR51,
input [VAR36-1:0] VAR67,
input [VAR82-1:0] VAR2,
output [VAR76-1:0] VAR22,
input VAR29,
input VAR46,
output VAR8,
output [VAR79-1:0] VAR43,
output VAR73,
output VAR15,
output [VAR38(VAR79/32)-1:0] VAR71,
output VAR85,
output [VAR38(VAR79/32)-1:0] VAR47,
output [VAR60-1:0] VAR23,
input VAR20,
output VAR80,
input [VAR79-1:0] VAR52,
input VAR4,
input VAR27,
input [VAR38(VAR79/32)-1:0] VAR39,
input VAR6,
input [VAR38(VAR79/32)-1:0] VAR3,
output [VAR72-1:0] VAR75,
output VAR59,
output [VAR70-1:0] VAR42,
output [VAR9-1:0] VAR10,
output [VAR61-1:0] VAR21,
output [VAR81-1:0] VAR45,
output VAR55,
output VAR17,
output [VAR36-1:0] VAR11,
output [VAR82-1:0] VAR7,
output VAR25, input VAR24 );
reg VAR14;
reg VAR33;
assign VAR43 = VAR86;
assign VAR73 = VAR40;
assign VAR30 = VAR20;
assign VAR80 = VAR66;
assign VAR16 = VAR52;
assign VAR74 = VAR4;
assign VAR41 = VAR6;
assign VAR75 = {VAR50,VAR77,VAR54};
assign VAR59 = VAR56[VAR34];
assign VAR42 = VAR64[VAR53];
assign VAR10 = VAR64[VAR44];
assign VAR21 = VAR19[VAR35];
assign VAR45 = VAR19[VAR65];
assign VAR55 = VAR29;
assign VAR17 = VAR51[VAR13];
assign VAR11 = VAR67;
assign VAR7 = VAR2;
assign VAR22 = VAR5;
assign VAR12 = 1'b1;
assign VAR48 = 1'b1;
assign VAR58 = 1'b1;
assign VAR8 = VAR24;
assign VAR25 = VAR46;
generate
if (VAR79 == 9'd32) begin : VAR57
assign VAR15 = ~VAR14 | VAR33;
assign VAR71 = {VAR38(VAR79/32){1'b0}};
assign VAR47 = 0;
assign VAR85 = VAR26;
assign VAR68 = 4'hF;
end else if (VAR79 == 9'd64) begin : VAR69
assign VAR15 = ~VAR14 | VAR33;
assign VAR71 = {VAR38(VAR79/32){1'b0}};
assign VAR47 = VAR32[4];
assign VAR85 = VAR26;
assign VAR68 = {{4{VAR3 | ~VAR6}},4'hF};
end else if (VAR79 == 9'd128) begin : VAR28
assign VAR47 = VAR37[20:19];
assign VAR85 = VAR37[21];
assign VAR15 = VAR37[14];
assign VAR71 = VAR37[13:12];
assign VAR68 = {{4{~VAR6 | (VAR3 == 2'b11)}},
{4{~VAR6 | (VAR3 >= 2'b10)}},
{4{~VAR6 | (VAR3 >= 2'b01)}},
{4{1'b1}}}; end else if (VAR79 == 9'd256) begin : VAR62
end
endgenerate
always @(posedge VAR31) begin
VAR14 <= VAR73;
VAR33 <= VAR85;
end
endmodule
|
mit
|
alexforencich/verilog-cam
|
rtl/ram_dp.v
| 2,608 |
module MODULE1 #
(
parameter VAR3 = 32,
parameter VAR11 = 10
)
(
input wire VAR12,
input wire VAR13,
input wire [VAR11-1:0] VAR10,
input wire [VAR3-1:0] VAR8,
output wire [VAR3-1:0] VAR16,
input wire VAR9,
input wire VAR6,
input wire [VAR11-1:0] VAR5,
input wire [VAR3-1:0] VAR1,
output wire [VAR3-1:0] VAR4
);
reg [VAR3-1:0] VAR17 = {VAR3{1'b0}};
reg [VAR3-1:0] VAR14 = {VAR3{1'b0}};
reg [VAR3-1:0] VAR7[(2**VAR11)-1:0];
assign VAR16 = VAR17;
assign VAR4 = VAR14;
integer VAR2, VAR15;
|
mit
|
The-OpenROAD-Project/asap7
|
asap7sc6t_26/Verilog/asap7sc6t_AO_RVT_SS_210930.v
| 231,279 |
module MODULE1 (VAR10, VAR11, VAR2, VAR5, VAR6);
output VAR10;
input VAR11, VAR2, VAR5, VAR6;
wire VAR4, VAR7, VAR9;
wire VAR1, VAR8, VAR3;
not (VAR1, VAR6);
not (VAR9, VAR5);
not (VAR7, VAR2);
and (VAR8, VAR7, VAR9);
not (VAR4, VAR11);
and (VAR3, VAR4, VAR9);
or (VAR10, VAR3, VAR8, VAR1);
|
bsd-3-clause
|
keith-epidev/VHDL-lib
|
top/lab_2/part_3/ip/clk_base/clk_base_stub.v
| 1,241 |
module MODULE1(VAR1, VAR4, VAR2, VAR3)
;
input VAR1;
output VAR4;
output VAR2;
output VAR3;
endmodule
|
gpl-2.0
|
scollinson/xc3sprog
|
bscan_spi/bscan_s3_spi_isf.v
| 1,407 |
module MODULE1
(
input VAR2
);
wire VAR10;
wire VAR33;
wire VAR1;
wire VAR4;
wire VAR18;
wire VAR31;
reg [47:0] VAR16;
reg [15:0] VAR30;
reg VAR37 = 0;
wire VAR39;
wire VAR20 = VAR4;
wire VAR27;
wire VAR7;
wire VAR22;
reg VAR38 = 0;
reg VAR44 = 0;
reg VAR42 = 0;
reg VAR14 = 0;
reg [13:0] VAR13;
reg [13:0] VAR12;
wire VAR25 = !VAR1;
wire VAR17;
wire VAR41;
reg VAR50 = 0;
VAR47 VAR11
(
.VAR51(VAR17),
.VAR5(),
.VAR34(VAR13),
.VAR43(VAR12),
.VAR8(VAR25),
.VAR9(VAR1),
.VAR3(1'b0),
.VAR32(VAR41),
.VAR45(1'b1),
.VAR40(1'b1),
.VAR36(1'b0),
.VAR24(1'b0),
.VAR23(1'b0),
.VAR35(VAR50)
);
VAR15 VAR48
(
.VAR10(VAR10),
.VAR1(VAR1),
.VAR29(),
.VAR22(VAR22),
.VAR27(VAR27),
.VAR28(),
.VAR7(VAR7),
.VAR6(),
.VAR4(VAR4),
.VAR46(),
.VAR33(VAR33),
.VAR18(VAR18),
.VAR21(1'b0)
);
VAR26
)
VAR49
(
.VAR39(VAR39),
.VAR19(VAR1),
.VAR31(VAR31),
.VAR20(VAR20)
);
endmodule
|
gpl-2.0
|
KiwiOnChip/Projet_VHDL_-_Paint
|
04_IP_Xillinx/Clk_Wizard/Clk_Wizard_stub.v
| 1,281 |
module MODULE1(VAR5, VAR4, VAR2, VAR1,
VAR3)
;
output VAR5;
output VAR4;
input VAR2;
output VAR1;
input VAR3;
endmodule
|
gpl-3.0
|
ShepardSiegel/ocpi
|
coregen/temac_axi_v5_2/example_design/fifo/ten_100_1g_eth_fifo.v
| 7,123 |
module MODULE1 #
(
parameter VAR39 = 0
)
(
input VAR37, input VAR18, input [7:0] VAR38,
input VAR13,
input VAR23,
output VAR27,
input VAR12, input VAR8, output [7:0] VAR4,
output VAR28,
output VAR2,
input VAR31,
output VAR6,
output VAR16,
output [3:0] VAR17,
input VAR5,
input VAR29,
input VAR34, input VAR36, output [7:0] VAR1,
output VAR22,
output VAR33,
input VAR7,
input VAR3, input VAR10, input [7:0] VAR24,
input VAR26,
input VAR25,
output VAR11,
input VAR14,
output [3:0] VAR30,
output VAR21
);
VAR20 #
(
.VAR39 (VAR39)
)
VAR35
(
.VAR37 (VAR37),
.VAR18 (VAR18),
.VAR38 (VAR38),
.VAR13 (VAR13),
.VAR23 (VAR23),
.VAR27 (VAR27),
.VAR12 (VAR12),
.VAR8 (VAR8),
.VAR4 (VAR4),
.VAR28 (VAR28),
.VAR2 (VAR2),
.VAR31 (VAR31),
.VAR6 (VAR6),
.VAR15 (VAR16),
.VAR32 (VAR17),
.VAR5 (VAR5),
.VAR29 (VAR29)
);
VAR19 VAR9
(
.VAR34 (VAR34),
.VAR36 (VAR36),
.VAR1 (VAR1),
.VAR22 (VAR22),
.VAR33 (VAR33),
.VAR7 (VAR7),
.VAR3 (VAR3),
.VAR10 (VAR10),
.VAR24 (VAR24),
.VAR26 (VAR26),
.VAR25 (VAR25),
.VAR11 (VAR11),
.VAR14 (VAR14),
.VAR32 (VAR30),
.VAR15 (VAR21)
);
endmodule
|
lgpl-3.0
|
csturton/wirepatch
|
system/hardware/cores/fabric/ovl_always_wrapped.v
| 2,610 |
module MODULE1(
clk,
rst,
enable,
VAR5,
VAR2,
out
);
input clk;
input rst;
input enable;
input VAR5;
input VAR2;
output out;
wire [2:0] VAR3;
wire [2:0] VAR4;
VAR6 VAR6(
.VAR1(clk),
.reset(rst),
.enable(enable),
.VAR5(VAR5),
.VAR7(VAR3),
.VAR8(VAR4)
);
assign out = VAR4[0] & ~VAR2;
endmodule
|
mit
|
rhalstea/cidr_15_fpga_join
|
probe_engine/verilog/filter_rows.v
| 2,838 |
module MODULE1 (
input clk,
input rst,
output VAR7,
input [63:0] VAR6,
input [63:0] VAR5,
input [63:0] VAR23,
input [63:0] VAR29, input [63:0] VAR14,
output VAR32,
input VAR27,
output [63:0] VAR11,
output [63:0] VAR24,
input VAR21,
output VAR19,
output [47:0] VAR15,
output VAR2,
input VAR26,
input [63:0] VAR18
);
wire VAR10;
wire VAR22;
wire [63:0] VAR17;
wire VAR31;
wire VAR30;
wire VAR28;
VAR9 VAR3 (
.clk (clk),
.rst (rst),
.VAR7 (VAR10),
.VAR6 (VAR6),
.VAR29 (VAR29), .VAR5 (VAR5),
.VAR23 (VAR23),
.VAR32 (VAR22),
.VAR27 (VAR31),
.VAR11 (VAR17),
.VAR21 (VAR21),
.VAR19 (VAR19),
.VAR15 (VAR15),
.VAR2 (VAR2),
.VAR26 (VAR26),
.VAR18 (VAR18)
);
assign VAR31 = !VAR28 && !VAR22;
VAR16 VAR4 (
.clk (clk),
.rst (rst),
.VAR7 (VAR30),
.VAR14 (VAR14),
.VAR13 (VAR28),
.VAR25 (VAR31),
.VAR20 (VAR17),
.VAR12 (VAR32),
.VAR33 (VAR27),
.VAR8 (VAR11),
.VAR1 (VAR24)
);
assign VAR7 = VAR10 && VAR30;
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr.blackbox.v
| 1,332 |
module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
SeanZarzycki/openSPARC-FPU
|
dc_compiler/iscas_benchmarks/s526.v
| 7,840 |
module MODULE2 (VAR62,VAR368,VAR102);
input VAR62,VAR102;
output VAR368;
wire VAR11,VAR93;
trireg VAR218,VAR124;
nmos VAR323 (VAR124,VAR102,VAR93);
not VAR179 (VAR11,VAR124);
nmos VAR98 (VAR218,VAR11,VAR62);
not VAR338 (VAR368,VAR218);
not VAR10 (VAR93,VAR62);
endmodule
module MODULE1(VAR381,VAR260,VAR62,VAR77,VAR331,VAR204,VAR249,VAR261,VAR256,VAR12,VAR52,VAR262);
input VAR381,VAR260,VAR62,VAR77,VAR331,VAR12;
output VAR261,VAR52,VAR204,VAR256,VAR262,VAR249;
wire VAR147,VAR336,VAR236,VAR271,VAR38,VAR75,VAR230,VAR140,VAR408,VAR380,VAR157,VAR339,VAR113,VAR393,VAR255,VAR386,VAR399,
VAR365,VAR363,VAR245,VAR42,VAR440,VAR411,VAR324,VAR207,VAR65,VAR413,VAR201,VAR44,VAR139,VAR1,VAR370,VAR53,
VAR222,VAR232,VAR174,VAR395,VAR7,VAR410,VAR184,VAR439,VAR267,VAR367,VAR350,VAR316,VAR163,VAR330,VAR378,VAR121,VAR292,
VAR389,VAR109,VAR428,VAR144,VAR415,VAR20,VAR176,VAR88,VAR285,VAR40,VAR352,VAR402,VAR101,VAR45,
VAR208,VAR322,VAR195,VAR326,VAR391,VAR270,VAR49,VAR73,VAR21,VAR405,VAR142,VAR59,VAR106,VAR274,
VAR435,VAR58,VAR110,VAR91,VAR112,VAR426,VAR24,VAR78,VAR9,VAR169,VAR349,VAR47,VAR398,VAR122,
VAR217,VAR269,VAR309,VAR333,VAR423,VAR33,VAR424,VAR94,VAR366,VAR334,VAR290,VAR430,VAR412,VAR126,VAR299,VAR55,VAR268,VAR149,
VAR188,VAR300,VAR384,VAR159,VAR376,VAR321,VAR6,VAR441,VAR382,VAR311,VAR54,VAR125,VAR197,VAR264,VAR433,VAR305,VAR343,
VAR3,VAR70,VAR205,VAR327,VAR445,VAR250,VAR287,VAR276,VAR134,VAR369,VAR240,VAR358,VAR437,VAR372,VAR359,
VAR130,VAR186,VAR34,VAR104,VAR146,VAR48,VAR15,VAR302,VAR348,VAR361,VAR403,VAR317,VAR80,VAR406,VAR341,
VAR164,VAR137,VAR69,VAR325,VAR248,VAR193,VAR246,VAR90,VAR180,VAR172,VAR394,VAR200,VAR303,VAR36,VAR216,VAR86,VAR388,VAR114,
VAR383,VAR103,VAR400,VAR74,VAR167,VAR315,VAR284,VAR105,VAR133,VAR111,VAR407,VAR429,VAR89,VAR304,VAR434,
VAR96,VAR199,VAR254,VAR258,VAR85,VAR234,VAR392,VAR353,VAR289,VAR291,VAR143,VAR203,VAR335,VAR67,VAR387,
VAR76,VAR166,VAR379;
MODULE2 VAR26(VAR62,VAR147,VAR336);
MODULE2 VAR283(VAR62,VAR236,VAR271);
MODULE2 VAR282(VAR62,VAR38,VAR75);
MODULE2 VAR14(VAR62,VAR230,VAR140);
MODULE2 VAR390(VAR62,VAR408,VAR380);
MODULE2 VAR32(VAR62,VAR157,VAR339);
MODULE2 VAR414(VAR62,VAR113,VAR393);
MODULE2 VAR416(VAR62,VAR255,VAR386);
MODULE2 VAR225(VAR62,VAR399,VAR365);
MODULE2 VAR61(VAR62,VAR363,VAR245);
MODULE2 VAR19(VAR62,VAR42,VAR440);
MODULE2 VAR209(VAR62,VAR411,VAR324);
MODULE2 VAR357(VAR62,VAR207,VAR65);
MODULE2 VAR8(VAR62,VAR413,VAR201);
MODULE2 VAR181(VAR62,VAR44,VAR139);
MODULE2 VAR83(VAR62,VAR1,VAR370);
MODULE2 VAR16(VAR62,VAR53,VAR222);
MODULE2 VAR355(VAR62,VAR232,VAR174);
MODULE2 VAR436(VAR62,VAR395,VAR7);
MODULE2 VAR135(VAR62,VAR410,VAR184);
MODULE2 VAR346(VAR62,VAR439,VAR267);
not VAR162(VAR367,VAR350);
not VAR427(VAR316,VAR38);
not VAR257(VAR163,VAR230);
not VAR173(VAR330,VAR147);
not VAR182(VAR378,VAR157);
not VAR100(VAR121,VAR408);
not VAR175(VAR292,VAR113);
not VAR107(VAR389,VAR399);
not VAR265(VAR109,VAR236);
not VAR239(VAR428,VAR363);
not VAR297(VAR144,VAR255);
not VAR263(VAR415,VAR439);
not VAR153(VAR20,VAR42);
not VAR314(VAR176,VAR367);
not VAR277(VAR88,VAR411);
not VAR185(VAR285,VAR42);
not VAR210(VAR40,VAR38);
not VAR310(VAR352,VAR411);
not VAR351(VAR402,VAR410);
not VAR425(VAR101,VAR207);
not VAR131(VAR45,VAR413);
not VAR320(VAR204,VAR45);
not VAR68(VAR208,VAR44);
not VAR259(VAR249,VAR208);
not VAR95(VAR322,VAR399);
not VAR27(VAR195,VAR42);
not VAR228(VAR326,VAR413);
not VAR81(VAR391,VAR411);
not VAR235(VAR270,VAR44);
not VAR215(VAR49,VAR230);
not VAR371(VAR73,VAR1);
not VAR298(VAR21,VAR38);
not VAR168(VAR405,VAR142);
not VAR66(VAR59,VAR395);
not VAR226(VAR106,VAR1);
not VAR56(VAR261,VAR106);
not VAR278(VAR274,VAR53);
not VAR286(VAR256,VAR274);
not VAR82(VAR435,VAR58);
not VAR154(VAR110,VAR410);
not VAR84(VAR91,VAR12);
not VAR253(VAR58,VAR91);
not VAR417(VAR112,VAR426);
not VAR115(VAR24,VAR439);
not VAR13(VAR78,VAR77);
not VAR241(VAR350,VAR78);
not VAR296(VAR9,VAR331);
not VAR161(VAR426,VAR9);
not VAR171(VAR169,VAR232);
not VAR192(VAR52,VAR169);
not VAR224(VAR349,VAR395);
not VAR87(VAR262,VAR349);
and VAR129(VAR47,VAR415,VAR398);
and VAR420(VAR122,VAR147,VAR109,VAR121,VAR157);
and VAR409(VAR217,VAR415,VAR398);
and VAR227(VAR269,VAR415,VAR398);
and VAR25(VAR309,VAR316,VAR411);
and VAR190(VAR333,VAR38,VAR88);
and VAR57(VAR423,VAR367,VAR292);
and VAR356(VAR33,VAR415,VAR367);
and VAR332(VAR424,VAR144,VAR428);
and VAR237(VAR94,VAR144,VAR399);
and VAR442(VAR366,VAR367,VAR113,VAR255);
and VAR150(VAR334,VAR367,VAR399);
and VAR63(VAR290,VAR255,VAR389);
and VAR160(VAR430,VAR144,VAR399);
and VAR30(VAR412,VAR255,VAR428);
and VAR421(VAR126,VAR367,VAR113,VAR255,VAR399);
and VAR212(VAR299,VAR367,VAR363);
and VAR141(VAR55,VAR147,VAR121,VAR157);
and VAR373(VAR268,VAR147,VAR236);
and VAR360(VAR149,VAR330,VAR109);
and VAR71(VAR188,VAR147,VAR236,VAR408);
and VAR108(VAR300,VAR330,VAR121);
and VAR213(VAR384,VAR109,VAR121);
and VAR432(VAR159,VAR378,VAR376);
and VAR165(VAR321,VAR121,VAR109,VAR147,VAR6);
and VAR50(VAR441,VAR292,VAR415,VAR398);
and VAR156(VAR382,VAR109,VAR147,VAR311,VAR54);
and VAR41(VAR125,VAR144,VAR415,VAR398);
and VAR191(VAR197,VAR399,VAR255,VAR113,VAR264);
and VAR116(VAR433,VAR389,VAR415,VAR398);
and VAR220(VAR305,VAR109,VAR147,VAR311,VAR343);
and VAR318(VAR3,VAR428,VAR415,VAR398);
and VAR354(VAR70,VAR113,VAR439,VAR343);
and VAR342(VAR205,VAR144,VAR113,VAR327,VAR264);
and VAR158(VAR445,VAR20,VAR415,VAR398);
and VAR431(VAR250,VAR20,VAR287);
and VAR206(VAR276,VAR352,VAR42,VAR402,VAR134);
and VAR211(VAR369,VAR101,VAR240);
and VAR377(VAR358,VAR352,VAR42,VAR402,VAR134);
and VAR43(VAR437,VAR101,VAR240);
and VAR396(VAR372,VAR411,VAR230,VAR53);
and VAR97(VAR359,VAR195,VAR391,VAR230);
and VAR219(VAR130,VAR230,VAR326);
and VAR221(VAR186,VAR21,VAR49);
and VAR374(VAR34,VAR391,VAR21);
and VAR345(VAR104,VAR270,VAR38);
and VAR313(VAR146,VAR49,VAR38);
and VAR35(VAR48,VAR73,VAR230,VAR411);
and VAR99(VAR15,VAR21,VAR405,VAR302);
and VAR397(VAR348,VAR405,VAR361);
and VAR198(VAR403,VAR399,VAR142);
and VAR329(VAR317,VAR59,VAR230);
and VAR123(VAR80,VAR435,VAR110);
and VAR145(VAR406,VAR58,VAR410);
and VAR127(VAR341,VAR112,VAR24);
and VAR117(VAR164,VAR426,VAR439);
or VAR307(VAR137,VAR439,VAR69);
or VAR17(VAR325,VAR163,VAR38);
or VAR404(VAR248,VAR330,VAR109,VAR121,VAR378);
or VAR132(VAR193,VAR330,VAR236,VAR408);
or VAR196(VAR246,VAR415,VAR292,VAR399,VAR428);
or VAR281(VAR90,VAR415,VAR292,VAR144);
or VAR340(VAR180,VAR113,VAR255);
or VAR214(VAR172,VAR330,VAR236,VAR408,VAR378);
or VAR275(VAR394,VAR350,VAR200,VAR303,VAR36);
or VAR138(VAR216,VAR316,VAR350,VAR86);
or VAR280(VAR388,VAR350,VAR287,VAR114,VAR36);
or VAR28(VAR383,VAR163,VAR350,VAR103);
or VAR223(VAR400,VAR350,VAR74,VAR167,VAR315);
or VAR364(VAR284,VAR88,VAR350,VAR105);
or VAR242(VAR133,VAR42,VAR411,VAR38,VAR49);
or VAR60(VAR111,VAR21,VAR1);
or VAR288(VAR407,VAR21,VAR230);
or VAR51(VAR429,VAR195,VAR411,VAR38);
or VAR155(VAR89,VAR391,VAR232);
or VAR279(VAR304,VAR21,VAR232);
or VAR128(VAR434,VAR142,VAR21,VAR49,VAR53);
or VAR18(VAR96,VAR405,VAR322);
or VAR444(VAR199,VAR21,VAR230);
or VAR72(VAR254,VAR42,VAR230);
or VAR37(VAR258,VAR411,VAR38);
or VAR306(VAR85,VAR42,VAR411,VAR38,VAR49);
or VAR120(VAR234,VAR195,VAR391,VAR230);
or VAR177(VAR392,VAR391,VAR49,VAR44);
nand VAR266(VAR353,VAR389,VAR144,VAR113,VAR289);
nand VAR29(VAR75,VAR394,VAR216);
nand VAR401(VAR200,VAR389,VAR144,VAR113);
nand VAR273(VAR303,VAR316,VAR411,VAR42,VAR363);
nand VAR294(VAR140,VAR388,VAR383);
nand VAR347(VAR114,VAR163,VAR38,VAR411,VAR42);
nand VAR443(VAR376,VAR408,VAR236,VAR147);
nand VAR418(VAR291,VAR248,VAR193,VAR367);
nand VAR194(VAR143,VAR246,VAR90,VAR180,VAR367);
nand VAR39(VAR264,VAR172,VAR415);
nand VAR5(VAR398,VAR157,VAR121,VAR109,VAR147);
nand VAR362(VAR287,VAR363,VAR389,VAR144,VAR113);
nand VAR183(VAR324,VAR400,VAR284);
nand VAR229(VAR74,VAR144,VAR113);
nand VAR136(VAR167,VAR88,VAR42,VAR363,VAR389);
nand VAR118(VAR315,VAR137,VAR325);
nand VAR231(VAR240,VAR352,VAR285,VAR410,VAR134);
nand VAR301(VAR203,VAR85,VAR234,VAR392,VAR405);
nand VAR22(VAR335,VAR133,VAR111,VAR407,VAR405);
nand VAR23(VAR67,VAR434,VAR96);
nand VAR178(VAR361,VAR429,VAR89,VAR304,VAR230);
nand VAR170(VAR387,VAR199,VAR254,VAR258,VAR405);
nor VAR31(VAR69,VAR378,VAR408,VAR236,VAR330);
nor VAR92(VAR289,VAR20,VAR428);
nor VAR247(VAR336,VAR147,VAR350);
nor VAR344(VAR271,VAR55,VAR268,VAR149,VAR350);
nor VAR238(VAR86,VAR217,VAR88,VAR20,VAR287);
nor VAR244(VAR36,VAR122,VAR439);
nor VAR438(VAR103,VAR269,VAR309,VAR333,VAR353);
nor VAR422(VAR380,VAR188,VAR300,VAR384,VAR350);
nor VAR189(VAR339,VAR159,VAR291);
nor VAR151(VAR393,VAR321,VAR441,VAR76);
nor VAR79(VAR6,VAR292,VAR378);
nor VAR312(VAR76,VAR423,VAR33);
nor VAR272(VAR386,VAR382,VAR125,VAR143);
nor VAR148(VAR54,VAR424,VAR94);
nor VAR46(VAR365,VAR197,VAR433,VAR166);
nor VAR187(VAR166,VAR366,VAR334);
nor VAR64(VAR245,VAR305,VAR3,VAR70,VAR379);
nor VAR293(VAR311,VAR292,VAR378,VAR408);
nor VAR295(VAR343,VAR290,VAR430,VAR412);
nor VAR233(VAR379,VAR126,VAR299);
nor VAR152(VAR440,VAR205,VAR445,VAR250,VAR176);
nor VAR4(VAR327,VAR20,VAR428,VAR399);
nor VAR337(VAR105,VAR47,VAR20,VAR287);
nor VAR328(VAR65,VAR276,VAR369,VAR350);
nor VAR375(VAR134,VAR230,VAR40);
nor VAR308(VAR201,VAR130,VAR186,VAR34,VAR142);
nor VAR119(VAR139,VAR104,VAR146,VAR203);
nor VAR243(VAR370,VAR48,VAR335);
nor VAR251(VAR222,VAR15,VAR67);
nor VAR319(VAR302,VAR372,VAR359);
nor VAR419(VAR174,VAR348,VAR403);
nor VAR202(VAR142,VAR358,VAR437);
nor VAR385(VAR7,VAR317,VAR387);
nor VAR2(VAR184,VAR80,VAR406,VAR350);
nor VAR252(VAR267,VAR341,VAR164,VAR350);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/tap/sky130_fd_sc_hd__tap.behavioral.pp.v
| 1,189 |
module MODULE1 (
VAR1,
VAR4,
VAR2 ,
VAR3
);
input VAR1;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule
|
apache-2.0
|
smithe0/GestureControlInterface
|
DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_rs232_0.v
| 9,593 |
module MODULE1 (
clk,
reset,
address,
VAR34,
VAR27,
read,
write,
VAR17,
VAR32,
irq,
VAR1,
VAR25
);
parameter VAR14 = 13; parameter VAR23 = 5208;
parameter VAR9 = 2604;
parameter VAR31 = 10; parameter VAR35 = 8; parameter VAR22 = 1'b0;
input clk;
input reset;
input address;
input VAR34;
input [ 3: 0] VAR27;
input read;
input write;
input [31: 0] VAR17;
input VAR32;
output reg irq;
output reg [31: 0] VAR1;
output VAR25;
wire VAR11;
wire [ 7: 0] VAR33;
wire VAR16;
wire [(VAR35-1):0] VAR1;
wire VAR7;
wire VAR30;
wire [ 7: 0] VAR37;
reg VAR4;
reg VAR21;
reg VAR29;
reg VAR20;
reg VAR12;
reg [(VAR35-1):0] VAR2;
always @(posedge clk)
begin
if (reset)
irq <= 1'b0;
end
else
irq <= VAR20 | VAR29;
end
always @(posedge clk)
begin
if (reset)
VAR1 <= 32'h00000000;
end
else if (VAR34)
begin
if (address == 1'b0)
VAR1 <=
{8'h00,
VAR33,
VAR16,
5'h00,
VAR7,
1'b0,
VAR1[(VAR35 - 1):0]};
end
else
VAR1 <=
{8'h00,
VAR37,
6'h00,
VAR20,
VAR29,
6'h00,
VAR21,
VAR4};
end
end
always @(posedge clk)
begin
if (reset)
VAR4 <= 1'b0;
end
else if ((VAR34) && (write) && (address) && (VAR27[0]))
VAR4 <= VAR17[0];
end
always @(posedge clk)
begin
if (reset)
VAR21 <= 1'b0;
end
else if ((VAR34) && (write) && (address) && (VAR27[0]))
VAR21 <= VAR17[1];
end
always @(posedge clk)
begin
if (reset)
VAR29 <= 1'b0;
end
else if (VAR4 == 1'b0)
VAR29 <= 1'b0;
else
VAR29 <= (&(VAR33[6:5]) | VAR33[7]);
end
always @(posedge clk)
begin
if (reset)
VAR20 <= 1'b0;
end
else if (VAR21 == 1'b0)
VAR20 <= 1'b0;
else
VAR20 <= (&(VAR37[6:5]) | VAR37[7]);
end
always @(posedge clk)
begin
if (reset)
VAR12 <= 1'b0;
end
else
VAR12 <=
VAR34 & write & ~address & VAR27[0];
end
always @(posedge clk)
begin
if (reset)
VAR2 <= 'h0;
end
else
VAR2 <= VAR17[(VAR35 - 1):0];
end
assign VAR7 = 1'b0;
assign VAR11 = VAR34 & read & ~address & VAR27[0];
assign VAR30 = (^(VAR2)) ^ VAR22;
VAR28 VAR26 (
.clk (clk),
.reset (reset),
.VAR15 (VAR32),
.VAR13 (VAR11),
.VAR36 (VAR33),
.VAR3 (VAR16),
.VAR5 (VAR1)
);
VAR26.VAR14 = VAR14,
VAR26.VAR23 = VAR23,
VAR26.VAR9 = VAR9,
VAR26.VAR31 = VAR31,
VAR26.VAR35 = (VAR35 - 1);
VAR10 VAR8 (
.clk (clk),
.reset (reset),
.VAR19 (VAR2),
.VAR24 (VAR12),
.VAR6 (VAR37),
.VAR18 (VAR25)
);
VAR8.VAR14 = VAR14,
VAR8.VAR23 = VAR23,
VAR8.VAR9 = VAR9,
VAR8.VAR31 = VAR31,
VAR8.VAR35 = (VAR35 - 1);
endmodule
|
apache-2.0
|
LSaldyt/qnp
|
output/vs/opt_var19_multi.v
| 30,134 |
module MODULE1(VAR10, VAR5, VAR3, VAR6, VAR4, VAR13, VAR16, VAR15, VAR8, VAR9, VAR17, VAR2, VAR14, VAR1, VAR19, VAR7, VAR18, VAR11, VAR12, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wire 0013;
wire 0014;
wire 0015;
wire 0016;
wire 0017;
wire 0018;
wire 0019;
wire 0020;
wire 0021;
wire 0022;
wire 0023;
wire 0024;
wire 0025;
wire 0026;
wire 0027;
wire 0028;
wire 0029;
wire 0030;
wire 0031;
wire 0032;
wire 0033;
wire 0034;
wire 0035;
wire 0036;
wire 0037;
wire 0038;
wire 0039;
wire 0040;
wire 0041;
wire 0042;
wire 0043;
wire 0044;
wire 0045;
wire 0046;
wire 0047;
wire 0048;
wire 0049;
wire 0050;
wire 0051;
wire 0052;
wire 0053;
wire 0054;
wire 0055;
wire 0056;
wire 0057;
wire 0058;
wire 0059;
wire 0060;
wire 0061;
wire 0062;
wire 0063;
wire 0064;
wire 0065;
wire 0066;
wire 0067;
wire 0068;
wire 0069;
wire 0070;
wire 0071;
wire 0072;
wire 0073;
wire 0074;
wire 0075;
wire 0076;
wire 0077;
wire 0078;
wire 0079;
wire 0080;
wire 0081;
wire 0082;
wire 0083;
wire 0084;
wire 0085;
wire 0086;
wire 0087;
wire 0088;
wire 0089;
wire 0090;
wire 0091;
wire 0092;
wire 0093;
wire 0094;
wire 0095;
wire 0096;
wire 0097;
wire 0098;
wire 0099;
wire 0100;
wire 0101;
wire 0102;
wire 0103;
wire 0104;
wire 0105;
wire 0106;
wire 0107;
wire 0108;
wire 0109;
wire 0110;
wire 0111;
wire 0112;
wire 0113;
wire 0114;
wire 0115;
wire 0116;
wire 0117;
wire 0118;
wire 0119;
wire 0120;
wire 0121;
wire 0122;
wire 0123;
wire 0124;
wire 0125;
wire 0126;
wire 0127;
wire 0128;
wire 0129;
wire 0130;
wire 0131;
wire 0132;
wire 0133;
wire 0134;
wire 0135;
wire 0136;
wire 0137;
wire 0138;
wire 0139;
wire 0140;
wire 0141;
wire 0142;
wire 0143;
wire 0144;
wire 0145;
wire 0146;
wire 0147;
wire 0148;
wire 0149;
wire 0150;
wire 0151;
wire 0152;
wire 0153;
wire 0154;
wire 0155;
wire 0156;
wire 0157;
wire 0158;
wire 0159;
wire 0160;
wire 0161;
wire 0162;
wire 0163;
wire 0164;
wire 0165;
wire 0166;
wire 0167;
wire 0168;
wire 0169;
wire 0170;
wire 0171;
wire 0172;
wire 0173;
wire 0174;
wire 0175;
wire 0176;
wire 0177;
wire 0178;
wire 0179;
wire 0180;
wire 0181;
wire 0182;
wire 0183;
wire 0184;
wire 0185;
wire 0186;
wire 0187;
wire 0188;
wire 0189;
wire 0190;
wire 0191;
wire 0192;
wire 0193;
wire 0194;
wire 0195;
wire 0196;
wire 0197;
wire 0198;
wire 0199;
wire 0200;
wire 0201;
wire 0202;
wire 0203;
wire 0204;
wire 0205;
wire 0206;
wire 0207;
wire 0208;
wire 0209;
wire 0210;
wire 0211;
wire 0212;
wire 0213;
wire 0214;
wire 0215;
wire 0216;
wire 0217;
wire 0218;
wire 0219;
wire 0220;
wire 0221;
wire 0222;
wire 0223;
wire 0224;
wire 0225;
wire 0226;
wire 0227;
wire 0228;
wire 0229;
wire 0230;
wire 0231;
wire 0232;
wire 0233;
wire 0234;
wire 0235;
wire 0236;
wire 0237;
wire 0238;
wire 0239;
wire 0240;
wire 0241;
wire 0242;
wire 0243;
wire 0244;
wire 0245;
wire 0246;
wire 0247;
wire 0248;
wire 0249;
wire 0250;
wire 0251;
wire 0252;
wire 0253;
wire 0254;
wire 0255;
wire 0256;
wire 0257;
wire 0258;
wire 0259;
wire 0260;
wire 0261;
wire 0262;
wire 0263;
wire 0264;
wire 0265;
wire 0266;
wire 0267;
wire 0268;
wire 0269;
wire 0270;
wire 0271;
wire 0272;
wire 0273;
wire 0274;
wire 0275;
wire 0276;
wire 0277;
wire 0278;
wire 0279;
wire 0280;
wire 0281;
wire 0282;
wire 0283;
wire 0284;
wire 0285;
wire 0286;
wire 0287;
wire 0288;
wire 0289;
wire 0290;
wire 0291;
wire 0292;
wire 0293;
wire 0294;
wire 0295;
wire 0296;
wire 0297;
wire 0298;
wire 0299;
wire 0300;
wire 0301;
wire 0302;
wire 0303;
wire 0304;
wire 0305;
wire 0306;
wire 0307;
wire 0308;
wire 0309;
wire 0310;
wire 0311;
wire 0312;
wire 0313;
wire 0314;
wire 0315;
wire 0316;
wire 0317;
wire 0318;
wire 0319;
wire 0320;
wire 0321;
wire 0322;
wire 0323;
wire 0324;
wire 0325;
wire 0326;
wire 0327;
wire 0328;
wire 0329;
wire 0330;
wire 0331;
wire 0332;
wire 0333;
wire 0334;
wire 0335;
wire 0336;
wire 0337;
wire 0338;
wire 0339;
wire 0340;
wire 0341;
wire 0342;
wire 0343;
wire 0344;
wire 0345;
wire 0346;
wire 0347;
wire 0348;
wire 0349;
wire 0350;
wire 0351;
wire 0352;
wire 0353;
wire 0354;
wire 0355;
wire 0356;
wire 0357;
wire 0358;
wire 0359;
wire 0360;
wire 0361;
wire 0362;
wire 0363;
wire 0364;
wire 0365;
wire 0366;
wire 0367;
wire 0368;
wire 0369;
wire 0370;
wire 0371;
wire 0372;
wire 0373;
wire 0374;
wire 0375;
wire 0376;
wire 0377;
wire 0378;
wire 0379;
wire 0380;
wire 0381;
wire 0382;
wire 0383;
wire 0384;
wire 0385;
wire 0386;
wire 0387;
wire 0388;
wire 0389;
wire 0390;
wire 0391;
wire 0392;
wire 0393;
wire 0394;
wire 0395;
wire 0396;
wire 0397;
wire 0398;
wire 0399;
wire 0400;
wire 0401;
wire 0402;
wire 0403;
wire 0404;
wire 0405;
wire 0406;
wire 0407;
wire 0408;
wire 0409;
wire 0410;
wire 0411;
wire 0412;
wire 0413;
wire 0414;
wire 0415;
wire 0416;
wire 0417;
wire 0418;
wire 0419;
wire 0420;
wire 0421;
wire 0422;
wire 0423;
wire 0424;
wire 0425;
wire 0426;
wire 0427;
wire 0428;
wire 0429;
wire 0430;
wire 0431;
wire 0432;
wire 0433;
wire 0434;
wire 0435;
wire 0436;
wire 0437;
wire 0438;
wire 0439;
wire 0440;
wire 0441;
wire 0442;
wire 0443;
wire 0444;
wire 0445;
wire 0446;
wire 0447;
wire 0448;
wire 0449;
wire 0450;
wire 0451;
wire 0452;
wire 0453;
wire 0454;
wire 0455;
wire 0456;
wire 0457;
wire 0458;
wire 0459;
wire 0460;
wire 0461;
wire 0462;
wire 0463;
wire 0464;
wire 0465;
wire 0466;
wire 0467;
wire 0468;
wire 0469;
wire 0470;
wire 0471;
wire 0472;
wire 0473;
wire 0474;
wire 0475;
wire 0476;
wire 0477;
wire 0478;
wire 0479;
wire 0480;
wire 0481;
wire 0482;
wire 0483;
wire 0484;
wire 0485;
wire 0486;
wire 0487;
wire 0488;
wire 0489;
wire 0490;
wire 0491;
wire 0492;
wire 0493;
wire 0494;
wire 0495;
wire 0496;
wire 0497;
wire 0498;
wire 0499;
wire 0500;
wire 0501;
wire 0502;
wire 0503;
wire 0504;
wire 0505;
wire 0506;
wire 0507;
wire 0508;
wire 0509;
wire 0510;
wire 0511;
wire 0512;
wire 0513;
wire 0514;
wire 0515;
wire 0516;
wire 0517;
wire 0518;
wire 0519;
wire 0520;
wire 0521;
wire 0522;
wire 0523;
wire 0524;
wire 0525;
wire 0526;
wire 0527;
wire 0528;
wire 0529;
wire 0530;
wire 0531;
wire 0532;
wire 0533;
wire 0534;
wire 0535;
wire 0536;
wire 0537;
wire 0538;
wire 0539;
wire 0540;
wire 0541;
wire 0542;
wire 0543;
wire 0544;
wire 0545;
wire 0546;
wire 0547;
wire 0548;
wire 0549;
wire 0550;
wire 0551;
wire 0552;
wire 0553;
wire 0554;
wire 0555;
wire 0556;
wire 0557;
wire 0558;
wire 0559;
wire 0560;
wire 0561;
wire 0562;
input VAR10;
input VAR5;
input VAR3;
input VAR6;
input VAR4;
input VAR13;
input VAR16;
input VAR15;
input VAR8;
input VAR9;
input VAR17;
input VAR2;
input VAR14;
input VAR1;
input VAR19;
input VAR7;
input VAR18;
input VAR11;
input VAR12;
output valid;
assign 0110 = ~VAR1;
assign 0121 = ~VAR8;
assign 0132 = VAR16 ^ VAR4;
assign 0143 = 0132 ^ VAR15;
assign 0154 = 0143 ^ 0121;
assign 0165 = 0154 ^ VAR9;
assign 0176 = 0165 ^ VAR17;
assign 0187 = ~(0176 | 0110);
assign 0198 = 0165 & VAR17;
assign 0209 = ~(VAR16 & VAR4);
assign 0220 = ~VAR13;
assign 0231 = VAR6 ^ VAR10;
assign 0242 = 0231 ^ 0220;
assign 0263 = 0242 ^ 0209;
assign 0264 = ~VAR15;
assign 0275 = ~(0132 | 0264);
assign 0286 = ~(0275 ^ 0263);
assign 0297 = ~(0143 | 0121);
assign 0308 = ~((0154 & VAR9) | 0297);
assign 0319 = ~(0308 ^ 0286);
assign 0340 = 0319 ^ 0198;
assign 0341 = ~0340;
assign 0352 = 0341 & 0187;
assign 0363 = ~VAR2;
assign 0374 = ~((0263 | 0143) & VAR8);
assign 0385 = ~0263;
assign 0396 = 0275 & 0385;
assign 0407 = ~(0242 | 0209);
assign 0418 = 0231 | 0220;
assign 0429 = ~VAR4;
assign 0440 = VAR6 & VAR10;
assign 0451 = 0440 ^ VAR5;
assign 0462 = 0451 ^ 0429;
assign 0473 = 0462 ^ 0418;
assign 0484 = ~(0473 ^ 0407);
assign 0495 = 0484 ^ 0396;
assign 0506 = ~(0495 ^ 0374);
assign 0517 = 0286 & 0154;
assign 0522 = 0319 & 0198;
assign 0523 = ~((0517 & VAR9) | 0522);
assign 0524 = ~(0523 ^ 0506);
assign 0525 = 0524 ^ 0363;
assign 0526 = 0525 & 0352;
assign 0527 = ~(0524 | 0363);
assign 0528 = 0506 & 0522;
assign 0529 = ~(0495 | 0374);
assign 0530 = 0132 & VAR15;
assign 0531 = ~((0263 & VAR15) | (0242 & 0530));
assign 0532 = ~((0484 | 0264) & 0531);
assign 0533 = 0473 & 0407;
assign 0534 = ~(0451 & VAR4);
assign 0535 = ~(VAR5 ^ VAR10);
assign 0536 = ~0535;
assign 0537 = VAR4 & VAR6;
assign 0538 = 0537 & 0536;
assign 0539 = ~VAR6;
assign 0540 = VAR5 & VAR10;
assign 0541 = 0540 | 0539;
assign 0542 = ~((0541 & 0534) | 0538);
assign 0543 = ~0231;
assign 0544 = ~((0462 & 0543) | 0220);
assign 0545 = 0544 ^ 0542;
assign 0546 = 0545 ^ VAR16;
assign 0547 = 0546 ^ 0533;
assign 0548 = 0547 ^ 0532;
assign 0549 = 0548 ^ 0529;
assign 0550 = ~VAR9;
assign 0551 = ~((0506 & 0517) | 0550);
assign 0552 = 0551 ^ 0549;
assign 0553 = 0552 ^ 0528;
assign 0554 = 0553 ^ 0527;
assign 0555 = 0554 ^ VAR14;
assign 0556 = 0555 ^ VAR1;
assign 0557 = 0556 ^ 0526;
assign 0558 = 0557 & VAR19;
assign 0559 = 0176 ^ 0110;
assign 0560 = 0559 & VAR19;
assign 0561 = 0560 & 0341;
assign 0562 = 0525 ^ 0352;
assign 0000 = 0562 & 0561;
assign 0001 = 0557 ^ VAR19;
assign 0002 = 0001 & 0000;
assign 0003 = 0002 | 0558;
assign 0004 = 0555 & VAR1;
assign 0005 = 0556 & 0526;
assign 0006 = 0005 | 0004;
assign 0007 = 0551 & 0549;
assign 0008 = 0545 & VAR16;
assign 0009 = 0546 & 0533;
assign 0010 = 0009 | 0008;
assign 0011 = 0540 & VAR6;
assign 0012 = 0538 | 0011;
assign 0013 = ~((0544 & 0542) | 0012);
assign 0014 = 0013 ^ 0010;
assign 0015 = ~(0547 & 0532);
assign 0016 = ~(0548 & 0529);
assign 0017 = 0016 & 0015;
assign 0018 = 0017 ^ 0014;
assign 0019 = 0018 ^ 0007;
assign 0020 = ~VAR17;
assign 0021 = 0319 & 0165;
assign 0022 = 0506 & 0021;
assign 0023 = ~0552;
assign 0024 = ~((0023 & 0022) | 0020);
assign 0025 = 0024 ^ 0019;
assign 0026 = ~(0553 & 0527);
assign 0027 = ~(0554 & VAR14);
assign 0028 = 0027 & 0026;
assign 0029 = ~(0028 ^ 0025);
assign 0030 = 0029 ^ 0006;
assign 0031 = 0030 ^ 0003;
assign 0032 = 0001 ^ 0000;
assign 0033 = ~VAR7;
assign 0034 = 0562 ^ 0561;
assign 0035 = ~0034;
assign 0036 = 0559 ^ VAR19;
assign 0037 = ~(0560 | 0187);
assign 0038 = 0037 ^ 0340;
assign 0039 = ~(0038 | 0036);
assign 0040 = ~((0039 & 0035) | 0033);
assign 0041 = 0040 ^ 0032;
assign 0042 = ~VAR18;
assign 0043 = 0036 ^ 0033;
assign 0044 = ~(0038 | VAR9);
assign 0045 = ~((0044 & 0043) | 0042);
assign 0046 = ~0045;
assign 0047 = ~(0036 | 0033);
assign 0048 = ~0047;
assign 0049 = ~(0048 | 0038);
assign 0050 = ~(0049 ^ 0034);
assign 0051 = ~(0050 | 0046);
assign 0052 = 0051 & 0041;
assign 0053 = 0052 & 0031;
assign 0054 = 0040 & 0032;
assign 0055 = 0054 & 0031;
assign 0056 = 0030 & 0003;
assign 0057 = ~(0029 & 0006);
assign 0058 = ~0025;
assign 0059 = 0058 | 0026;
assign 0060 = ~(0024 & 0019);
assign 0061 = ~0010;
assign 0062 = 0013 | 0061;
assign 0063 = 0014 | 0015;
assign 0064 = 0063 & 0062;
assign 0065 = ~((0014 | 0016) & 0064);
assign 0066 = ~((0018 & 0007) | 0065);
assign 0067 = 0066 ^ 0060;
assign 0068 = ~(0067 ^ 0059);
assign 0069 = ~0068;
assign 0070 = ~(0058 | 0027);
assign 0071 = 0070 ^ 0068;
assign 0072 = 0057 ? 0071 : 0069;
assign 0073 = 0072 ^ 0056;
assign 0074 = 0073 ^ 0055;
assign 0075 = 0050 ^ 0046;
assign 0076 = ~VAR11;
assign 0077 = VAR18 & 0550;
assign 0078 = ~((0077 & 0043) | 0047);
assign 0079 = 0078 ^ 0038;
assign 0080 = 0042 & VAR9;
assign 0081 = ~(0080 | 0077);
assign 0082 = 0081 & 0043;
assign 0083 = ~((0082 & 0079) | 0076);
assign 0084 = 0083 ^ 0075;
assign 0085 = 0084 | VAR12;
assign 0086 = 0052 | 0054;
assign 0087 = ~(0086 ^ 0031);
assign 0088 = 0083 & 0075;
assign 0089 = 0051 ^ 0041;
assign 0090 = 0089 | 0088;
assign 0091 = ~(0090 | VAR12);
assign 0092 = 0089 & 0088;
assign 0093 = ~(0092 & VAR12);
assign 0094 = ~((0093 & 0087) | 0091);
assign 0095 = 0094 & 0085;
assign 0096 = 0077 | 0043;
assign 0097 = 0043 ? 0077 : 0080;
assign 0098 = ~((0096 & VAR11) | 0097);
assign 0099 = ~((0081 | 0076) & VAR12);
assign 0100 = ~(0099 | 0098);
assign 0101 = ~VAR12;
assign 0102 = 0082 & VAR11;
assign 0103 = 0102 ^ 0079;
assign 0104 = ~(0103 | 0101);
assign 0105 = 0084 ^ 0101;
assign 0106 = ~((0104 | 0100) & 0105);
assign 0107 = 0106 | 0087;
assign 0108 = 0106 & 0087;
assign 0109 = ~((0090 & VAR12) | 0092);
assign 0111 = ~((0109 | 0108) & 0107);
assign 0112 = ~((0111 | 0095) & (0074 | 0053));
assign 0113 = ~(0073 & 0055);
assign 0114 = 0066 | 0060;
assign 0115 = 0066 & 0060;
assign 0116 = ~((0115 | 0059) & 0114);
assign 0117 = ~((0070 & 0068) | 0116);
assign 0118 = ~((0069 | 0057) & 0117);
assign 0119 = ~((0072 & 0056) | 0118);
assign 0120 = ~(0119 & 0113);
assign 0122 = ~((0074 & 0053) | 0120);
assign 0123 = 0535 ^ VAR9;
assign 0124 = 0123 ^ 0020;
assign 0125 = 0124 & VAR14;
assign 0126 = 0123 | 0020;
assign 0127 = ~(VAR5 | VAR10);
assign 0128 = VAR9 ? 0540 : 0127;
assign 0129 = 0128 ^ 0126;
assign 0130 = 0129 ^ VAR2;
assign 0131 = 0130 ^ 0125;
assign 0133 = ~VAR19;
assign 0134 = 0124 ^ VAR14;
assign 0135 = ~(0134 | 0133);
assign 0136 = 0135 ^ 0131;
assign 0137 = 0136 & VAR7;
assign 0138 = ~((0134 | 0131) & VAR19);
assign 0139 = 0130 & 0125;
assign 0140 = ~VAR3;
assign 0141 = 0540 ^ 0140;
assign 0142 = 0141 ^ 0539;
assign 0144 = 0142 ^ VAR16;
assign 0145 = 0144 ^ VAR15;
assign 0146 = 0145 ^ 0121;
assign 0147 = 0127 & VAR9;
assign 0148 = ~(0147 ^ 0146);
assign 0149 = 0148 ^ VAR17;
assign 0150 = ~(0128 | 0126);
assign 0151 = 0129 & VAR2;
assign 0152 = 0151 | 0150;
assign 0153 = 0152 ^ 0149;
assign 0155 = 0153 ^ 0139;
assign 0156 = 0155 ^ 0110;
assign 0157 = 0156 ^ 0138;
assign 0158 = 0157 & 0137;
assign 0159 = 0156 | 0138;
assign 0160 = 0155 | 0110;
assign 0161 = ~(0153 & 0139);
assign 0162 = ~VAR14;
assign 0163 = 0149 & 0151;
assign 0164 = ~((0148 & VAR17) | 0150);
assign 0166 = ~(0147 & 0146);
assign 0167 = ~(0145 | 0121);
assign 0168 = ~(0141 | 0539);
assign 0169 = ~((0540 & 0140) | 0127);
assign 0170 = 0169 ^ 0168;
assign 0171 = 0170 ^ VAR13;
assign 0172 = 0142 & VAR16;
assign 0173 = ~((0144 & VAR15) | 0172);
assign 0174 = ~(0173 ^ 0171);
assign 0175 = 0174 ^ 0167;
assign 0177 = 0175 ^ 0166;
assign 0178 = 0177 ^ 0164;
assign 0179 = 0178 ^ 0163;
assign 0180 = 0179 ^ 0162;
assign 0181 = 0180 ^ 0161;
assign 0182 = 0181 ^ 0160;
assign 0183 = 0182 ^ 0159;
assign 0184 = ~(0183 ^ 0158);
assign 0185 = 0157 ^ 0137;
assign 0186 = 0136 ^ VAR7;
assign 0188 = ~(0186 | 0042);
assign 0189 = ~(0188 ^ 0185);
assign 0190 = 0189 & 0184;
assign 0191 = 0190 | 0076;
assign 0192 = ~(0183 & 0158);
assign 0193 = ~(0182 | 0159);
assign 0194 = 0181 | 0160;
assign 0195 = ~(0179 & VAR14);
assign 0196 = ~((0180 | 0161) & 0195);
assign 0197 = 0178 & 0163;
assign 0199 = ~(0177 | 0164);
assign 0200 = 0174 | 0145;
assign 0201 = 0200 & VAR8;
assign 0202 = ~(0171 & 0172);
assign 0203 = 0170 | 0220;
assign 0204 = ~0540;
assign 0205 = VAR6 & VAR3;
assign 0206 = ~((0205 & 0204) | 0127);
assign 0207 = 0206 ^ 0203;
assign 0208 = ~(0207 ^ 0202);
assign 0210 = 0144 & VAR15;
assign 0211 = ~(0171 & 0210);
assign 0212 = ~(0211 & VAR15);
assign 0213 = 0212 ^ 0208;
assign 0214 = 0213 ^ 0201;
assign 0215 = ~0127;
assign 0216 = ~(0174 | 0215);
assign 0217 = ~((0216 & 0146) | 0550);
assign 0218 = 0217 ^ 0214;
assign 0219 = 0218 ^ 0199;
assign 0221 = 0219 ^ 0197;
assign 0222 = ~(0221 ^ 0196);
assign 0223 = 0222 ^ 0194;
assign 0224 = 0223 ^ VAR19;
assign 0225 = 0224 ^ 0193;
assign 0226 = 0225 ^ 0033;
assign 0227 = 0226 ^ 0192;
assign 0228 = ~0185;
assign 0229 = 0188 & 0228;
assign 0230 = ~(0229 & 0184);
assign 0232 = 0230 ^ 0227;
assign 0233 = 0232 | 0191;
assign 0234 = VAR4 ^ VAR3;
assign 0235 = 0234 & VAR15;
assign 0236 = VAR4 ^ VAR6;
assign 0237 = VAR3 ? 0539 : 0236;
assign 0238 = 0237 ^ VAR16;
assign 0239 = 0238 & 0235;
assign 0240 = ~VAR16;
assign 0241 = 0237 | 0240;
assign 0243 = 0205 ^ VAR10;
assign 0244 = ~((VAR6 | VAR3) & VAR4);
assign 0245 = 0244 ^ 0243;
assign 0246 = 0245 ^ VAR13;
assign 0247 = 0246 ^ 0241;
assign 0248 = 0247 ^ 0239;
assign 0249 = 0248 ^ VAR8;
assign 0250 = 0234 ^ VAR15;
assign 0251 = 0250 & VAR17;
assign 0252 = 0251 & 0238;
assign 0253 = ~(0252 | 0020);
assign 0254 = 0253 ^ 0249;
assign 0255 = 0250 ^ VAR17;
assign 0256 = 0255 & VAR2;
assign 0257 = ~(0251 | 0235);
assign 0258 = ~(0257 ^ 0238);
assign 0259 = ~(0258 & 0256);
assign 0260 = 0259 & VAR2;
assign 0261 = 0260 ^ 0254;
assign 0262 = 0258 ^ 0256;
assign 0265 = ~(0262 | 0110);
assign 0266 = 0262 ^ 0110;
assign 0267 = ~((0266 & VAR19) | 0265);
assign 0268 = 0267 ^ 0261;
assign 0269 = ~0261;
assign 0270 = ~((0266 & 0269) | 0133);
assign 0271 = ~((0249 & VAR17) | 0252);
assign 0272 = ~0237;
assign 0273 = ~((0246 & 0272) | 0240);
assign 0274 = 0245 & VAR13;
assign 0276 = ~0244;
assign 0277 = ~(0276 & 0243);
assign 0278 = ~(0440 | 0140);
assign 0279 = 0278 ^ 0535;
assign 0280 = 0279 ^ 0429;
assign 0281 = 0280 ^ 0277;
assign 0282 = ~(0281 ^ 0274);
assign 0283 = 0282 ^ 0273;
assign 0284 = 0247 & 0239;
assign 0285 = ~((0248 & VAR8) | 0284);
assign 0287 = 0285 ^ 0283;
assign 0288 = 0287 ^ 0271;
assign 0289 = 0288 ^ 0363;
assign 0290 = ~(0254 & VAR2);
assign 0291 = ~(0290 & 0259);
assign 0292 = 0291 ^ 0289;
assign 0293 = 0292 ^ VAR14;
assign 0294 = ~(0265 & 0269);
assign 0295 = 0294 ^ 0293;
assign 0296 = ~(0295 ^ 0270);
assign 0298 = ~((0296 & 0268) | 0033);
assign 0299 = ~(0292 | 0162);
assign 0300 = 0259 | 0254;
assign 0301 = ~((0288 | 0254) & VAR2);
assign 0302 = ~((0300 | 0289) & 0301);
assign 0303 = ~(0287 | 0271);
assign 0304 = 0283 & 0284;
assign 0305 = 0282 & 0273;
assign 0306 = 0281 & 0274;
assign 0307 = 0279 | 0429;
assign 0309 = 0279 & 0429;
assign 0310 = ~((0309 | 0277) & 0307);
assign 0311 = ~VAR5;
assign 0312 = ~(0311 | VAR10);
assign 0313 = ~((0311 & VAR10) | VAR3);
assign 0314 = ~((0313 | 0312) & 0539);
assign 0315 = ~((0205 | 0440) & 0311);
assign 0316 = 0315 & 0314;
assign 0317 = 0316 ^ VAR4;
assign 0318 = 0317 ^ 0310;
assign 0320 = 0318 ^ 0306;
assign 0321 = 0320 ^ 0305;
assign 0322 = ~(0321 ^ 0304);
assign 0323 = ~(0283 & 0248);
assign 0324 = 0323 & VAR8;
assign 0325 = ~(0324 ^ 0322);
assign 0326 = 0325 ^ 0303;
assign 0327 = 0326 ^ 0302;
assign 0328 = 0327 ^ 0299;
assign 0329 = ~(0262 | 0261);
assign 0330 = ~((0329 & 0293) | 0110);
assign 0331 = 0330 ^ 0328;
assign 0332 = ~((0295 & 0270) | 0133);
assign 0333 = 0332 ^ 0331;
assign 0334 = 0333 & 0298;
assign 0335 = ~((0331 & VAR19) | (0295 & 0270));
assign 0336 = 0330 & 0328;
assign 0337 = 0327 & 0299;
assign 0338 = 0326 & 0302;
assign 0339 = 0325 & 0303;
assign 0342 = ~((0323 & 0322) | 0121);
assign 0343 = 0245 | 0220;
assign 0344 = ~((0281 | 0220) & (0280 | 0343));
assign 0345 = 0318 & VAR13;
assign 0346 = 0345 | 0344;
assign 0347 = ~0277;
assign 0348 = ~(0316 & VAR4);
assign 0349 = 0348 & 0307;
assign 0350 = 0205 & VAR10;
assign 0351 = ~(0313 | 0312);
assign 0353 = 0540 | VAR3;
assign 0354 = ~((0353 & 0215) | (0351 & VAR6));
assign 0355 = 0354 | 0350;
assign 0356 = ~((0355 & 0349) | 0347);
assign 0357 = ~(0356 ^ 0346);
assign 0358 = 0320 & 0305;
assign 0359 = ~((0321 & 0304) | 0358);
assign 0360 = 0359 ^ 0357;
assign 0361 = 0360 ^ 0342;
assign 0362 = 0361 ^ 0339;
assign 0364 = 0362 ^ 0338;
assign 0365 = 0364 ^ 0337;
assign 0366 = ~(0365 ^ 0336);
assign 0367 = 0366 ^ 0335;
assign 0368 = ~(0367 & 0334);
assign 0369 = 0333 ^ 0298;
assign 0370 = 0268 ^ VAR7;
assign 0371 = 0266 ^ VAR19;
assign 0372 = 0255 ^ VAR2;
assign 0373 = ~0372;
assign 0375 = 0373 & 0371;
assign 0376 = ~((0375 & 0370) | 0042);
assign 0377 = 0268 & VAR7;
assign 0378 = ~(0377 ^ 0296);
assign 0379 = ~((0378 & 0376) | (0369 & VAR18));
assign 0380 = ~(0367 | 0334);
assign 0381 = ~((0380 | 0379) & 0368);
assign 0382 = ~(0365 & 0336);
assign 0383 = ~((0366 | 0335) & 0382);
assign 0384 = ~0358;
assign 0386 = 0357 | 0384;
assign 0387 = ~(0347 | 0350);
assign 0388 = 0356 & 0346;
assign 0389 = ~(0388 ^ 0387);
assign 0390 = ~((0321 & 0304) | 0389);
assign 0391 = 0390 & 0386;
assign 0392 = 0360 & 0342;
assign 0393 = ~((0361 & 0339) | 0392);
assign 0394 = ~(0393 ^ 0391);
assign 0395 = 0362 & 0338;
assign 0397 = ~((0364 & 0337) | 0395);
assign 0398 = 0397 ^ 0394;
assign 0399 = 0398 ^ 0383;
assign 0400 = ~(0399 ^ 0381);
assign 0401 = ~(0225 & VAR7);
assign 0402 = ~((0226 | 0192) & 0401);
assign 0403 = 0223 & VAR19;
assign 0404 = 0224 & 0193;
assign 0405 = 0404 | 0403;
assign 0406 = 0221 & 0196;
assign 0408 = ~(0219 & 0197);
assign 0409 = 0213 & 0201;
assign 0410 = ~((0208 | 0264) & 0211);
assign 0411 = ~(0207 | 0202);
assign 0412 = ~((0206 | 0170) & VAR13);
assign 0413 = ~((0205 & 0215) | 0540);
assign 0414 = 0413 ^ 0412;
assign 0415 = 0414 ^ 0411;
assign 0416 = 0415 ^ 0410;
assign 0417 = ~(0416 ^ 0409);
assign 0419 = 0217 & 0214;
assign 0420 = ~((0218 & 0199) | 0419);
assign 0421 = ~(0420 ^ 0417);
assign 0422 = 0421 ^ 0408;
assign 0423 = 0422 ^ 0406;
assign 0424 = ~(0181 | 0155);
assign 0425 = ~((0222 & 0424) | 0110);
assign 0426 = 0425 ^ 0423;
assign 0427 = 0426 ^ 0405;
assign 0428 = ~(0427 ^ 0402);
assign 0430 = ~(0228 & 0184);
assign 0431 = 0430 | 0186;
assign 0432 = ~((0431 | 0227) & VAR18);
assign 0433 = ~(0432 ^ 0428);
assign 0434 = ~((0433 | 0233) & 0400);
assign 0435 = ~(0433 ^ 0233);
assign 0436 = 0229 ^ 0184;
assign 0437 = 0189 ^ VAR11;
assign 0438 = 0437 & 0436;
assign 0439 = ~0438;
assign 0441 = 0232 ^ 0191;
assign 0442 = ~((0441 | 0439) & VAR12);
assign 0443 = ~(0442 & 0435);
assign 0444 = ~((0189 & VAR11) | VAR12);
assign 0445 = ~(0189 | VAR11);
assign 0446 = ~(0437 | 0101);
assign 0447 = 0134 ^ 0133;
assign 0448 = 0186 ^ 0042;
assign 0449 = ~((0448 & 0447) | 0446);
assign 0450 = ~((0445 | 0436) & 0449);
assign 0452 = ~((0444 & 0436) | 0450);
assign 0453 = 0438 & VAR12;
assign 0454 = 0453 ^ 0441;
assign 0455 = 0454 & 0452;
assign 0456 = 0398 & 0383;
assign 0457 = 0425 & 0423;
assign 0458 = 0422 & 0406;
assign 0459 = ~(0218 & 0199);
assign 0460 = ~((0421 | 0408) & (0417 | 0459));
assign 0461 = ~(0415 & 0410);
assign 0463 = ~(0413 | 0412);
assign 0464 = ~((0414 & 0411) | 0463);
assign 0465 = ~(0464 & 0461);
assign 0466 = ~(0217 & 0214);
assign 0467 = ~(0416 & 0409);
assign 0468 = ~((0417 | 0466) & 0467);
assign 0469 = 0468 ^ 0465;
assign 0470 = 0469 ^ 0460;
assign 0471 = 0470 & 0458;
assign 0472 = ~(0470 | 0458);
assign 0474 = ~((0468 & 0465) | (0388 & 0350));
assign 0475 = ~((0393 | 0391) & 0474);
assign 0476 = ~((0469 & 0460) | 0475);
assign 0477 = ~((0397 | 0394) & 0476);
assign 0478 = ~(0477 | 0471);
assign 0479 = ~((0472 | 0471) & 0478);
assign 0480 = 0479 | 0457;
assign 0481 = 0480 | 0456;
assign 0482 = ~((0426 & 0405) | 0481);
assign 0483 = ~((0378 & 0376) | 0042);
assign 0485 = 0483 ^ 0369;
assign 0486 = ~(0372 | 0042);
assign 0487 = 0486 ^ 0371;
assign 0488 = 0487 | 0076;
assign 0489 = 0486 & 0371;
assign 0490 = 0489 ^ 0370;
assign 0491 = 0490 | 0488;
assign 0492 = 0377 ^ 0296;
assign 0493 = 0492 ^ 0376;
assign 0494 = ~((0493 | 0076) & 0491);
assign 0496 = ~((0485 & VAR11) | 0494);
assign 0497 = 0367 ^ 0334;
assign 0498 = 0497 ^ 0379;
assign 0499 = ~((0498 | 0496) & 0482);
assign 0500 = ~(0483 ^ 0369);
assign 0501 = 0500 | 0076;
assign 0502 = 0485 ^ 0076;
assign 0503 = ~(0492 ^ 0376);
assign 0504 = 0491 & VAR11;
assign 0505 = 0487 ^ VAR11;
assign 0507 = 0486 | VAR12;
assign 0508 = ~((0372 & 0042) | 0507);
assign 0509 = ~((0508 & 0505) | (0490 & 0488));
assign 0510 = ~((0504 | 0503) & 0509);
assign 0511 = 0510 | 0494;
assign 0512 = 0511 | 0502;
assign 0513 = ~((0498 & 0501) | 0512);
assign 0514 = ~((0399 & 0381) | (0427 & 0402));
assign 0515 = ~((0432 | 0428) & 0514);
assign 0516 = 0515 | 0513;
assign 0518 = 0516 | 0499;
assign 0519 = ~((0455 & 0443) | 0518);
assign 0520 = ~((0442 | 0435) & 0519);
assign 0521 = 0520 | 0434;
assign valid = ~((0122 & 0112) | 0521);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor4bb/sky130_fd_sc_hdll__nor4bb.symbol.v
| 1,341 |
module MODULE1 (
input VAR9 ,
input VAR6 ,
input VAR5,
input VAR4,
output VAR7
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/busdriver2/sky130_fd_sc_lp__busdriver2.behavioral.v
| 1,329 |
module MODULE1 (
VAR2 ,
VAR4 ,
VAR7
);
output VAR2 ;
input VAR4 ;
input VAR7;
supply1 VAR5;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR8 ;
bufif0 VAR3 (VAR2 , VAR4, VAR7 );
endmodule
|
apache-2.0
|
kevintownsend/R3
|
verilog/pe/spmv_pe.v
| 3,454 |
module MODULE1(clk, VAR3, VAR39, VAR45, VAR13, VAR43, VAR8,
VAR6, VAR47, VAR11, VAR50, VAR24,
VAR31, VAR18, VAR17, VAR58,
VAR36, VAR2, VAR9, VAR12,
VAR30);
parameter VAR28 = 0;
localparam VAR23 = 7;
localparam VAR1 = 12;
localparam VAR44 = 16;
input clk;
input [63:0] VAR3;
output [63:0] VAR39;
input VAR45;
output VAR13;
output VAR27;
output VAR8;
output [47:0] VAR6;
output [63:0] VAR47;
input VAR11;
input VAR50;
input [32:0] VAR24;
input [63:0] VAR31;
output VAR18;
output VAR17;
output VAR58;
output [63:0] VAR36;
input VAR2;
input VAR9;
input [63:0] VAR12;
output VAR30;
reg rst, VAR42;
reg state, VAR53;
localparam VAR4 = 0;
localparam VAR38 = 1;
localparam VAR52 = 0;
localparam VAR26 = 2;
reg [47:0] VAR29 [VAR52:VAR26 - 1];
reg [47:0] VAR20 [VAR52:VAR26 - 1];
wire VAR21 = (VAR29[0] == VAR29[1]);
integer VAR41;
always @(posedge clk) begin
rst <= VAR42;
state <= VAR53;
for(VAR41 = VAR52; VAR41 < VAR26; VAR41 = VAR41 + 1)
VAR29[VAR41] = VAR20[VAR41];
end
reg [63:0] VAR54;
reg VAR32;
reg VAR55;
always @(posedge clk) begin
VAR54 <= VAR3;
VAR32 <= VAR45 | VAR55;
end
assign VAR39 = VAR54;
assign VAR13 = VAR32;
always @* begin
VAR42 = 0;
VAR53 = state;
VAR55 = VAR5;
for(VAR41 = VAR52; VAR41 < VAR26; VAR41 = VAR41 + 1)
VAR20[VAR41] = VAR29[VAR41];
if(VAR54[VAR1 - 1] || (VAR54[VAR1 - 2: VAR23] == VAR28))
case(VAR23 - 1 : 0)
VAR34: begin
VAR42 = 1;
VAR53 = VAR4;
end
VAR51: begin
VAR53 = VAR38;
end
VAR35: begin
for(VAR41 = VAR52; VAR41 < VAR26; VAR41 = VAR41 + 1)
if(VAR41 == VAR54[VAR44 - 1:VAR44])
VAR33[VAR41] = VAR54[63:VAR44];
end
endcase
case(state)
VAR38: begin
VAR55 = 1;
if(VAR21)
VAR53 = VAR4;
end
endcase
end
VAR19 decoder(clk, VAR54, VAR5, VAR14,
VAR56, VAR48, VAR10,
VAR50 && (VAR24[0] == 0), VAR24[2:1], VAR31,
VAR37, VAR17, VAR58, VAR22,
VAR36, VAR2, VAR25, VAR12,
VAR30, VAR7, VAR57, VAR49,
VAR46, VAR40, VAR15, VAR16);
endmodule;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o22ai/sky130_fd_sc_hdll__o22ai.functional.pp.v
| 2,181 |
module MODULE1 (
VAR19 ,
VAR18 ,
VAR6 ,
VAR7 ,
VAR14 ,
VAR16,
VAR3,
VAR11 ,
VAR17
);
output VAR19 ;
input VAR18 ;
input VAR6 ;
input VAR7 ;
input VAR14 ;
input VAR16;
input VAR3;
input VAR11 ;
input VAR17 ;
wire VAR15 ;
wire VAR2 ;
wire VAR8 ;
wire VAR1;
nor VAR10 (VAR15 , VAR7, VAR14 );
nor VAR5 (VAR2 , VAR18, VAR6 );
or VAR4 (VAR8 , VAR2, VAR15 );
VAR12 VAR13 (VAR1, VAR8, VAR16, VAR3);
buf VAR9 (VAR19 , VAR1 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
models/udp_dff_nr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_sn.symbol.v
| 1,532 |
module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR3 ,
input VAR5 ,
input VAR2 ,
input VAR6 ,
input VAR7,
input VAR8 ,
input VAR9
);
endmodule
|
apache-2.0
|
ymei/TMSPlane
|
Firmware/src/tms_sdm_recv.v
| 4,827 |
module MODULE1
parameter VAR3 = 19
)
(
input VAR74,
input VAR25, input VAR11, input [7:0] VAR57, input [4:0] VAR24, input VAR44, input [3:0] VAR21,
output VAR23,
output VAR35,
input VAR60,
input VAR39,
output VAR75,
input [VAR3-1:0] VAR1,
input [VAR3-1:0] VAR36,
input [VAR3-1:0] VAR2,
input [VAR3-1:0] VAR31,
output reg [VAR3*2-1:0] VAR50,
output reg VAR63
);
localparam VAR5 = "VAR46";
wire VAR27, VAR61, VAR69;
wire VAR33;
wire [VAR3*2-1:0] VAR6;
reg [VAR3*2-1:0] VAR41;
wire [VAR3*2-1:0] VAR34, VAR7;
VAR64 VAR19
(
.VAR17(), .VAR11(VAR11), .VAR9(VAR74) );
VAR49
.VAR43(VAR3*2+1),
.VAR67(1),
.VAR8("VAR58"),
.VAR77(VAR5)
)
VAR52
(
.VAR74(VAR74),
.VAR25(VAR25), .VAR57(VAR57),
.VAR24(VAR24),
.VAR44(VAR44), .VAR55({VAR33, VAR6}),
.VAR68({VAR60, VAR34}),
.VAR22({VAR39, VAR7}),
.VAR30(0),
.VAR4(),
.VAR70()
);
genvar VAR48;
generate
for (VAR48=0; VAR48<VAR3; VAR48=VAR48+1) begin
assign VAR34[VAR48*2] = VAR1[VAR48];
assign VAR34[VAR48*2+1] = VAR2[VAR48];
assign VAR7[VAR48*2] = VAR36[VAR48];
assign VAR7[VAR48*2+1] = VAR31[VAR48];
end
endgenerate
VAR42
.VAR26(32),
.VAR59(4)
)
VAR66
(
.VAR74(VAR74),
.VAR25(VAR25),
.VAR62(VAR21),
.VAR65(VAR27)
);
assign VAR61 = (VAR21==0 ? 0 : VAR27);
VAR53
.VAR32("VAR18"), .VAR28(1'b0), .VAR54("VAR20") )
VAR10
(
.VAR51(VAR69), .VAR13(VAR61), .VAR71(1), .VAR47(1), .VAR38(0), .VAR56(0), .VAR37(0) );
VAR15
.VAR29("VAR76"), .VAR12("VAR16") )
VAR73
(
.VAR14(VAR23), .VAR40(VAR35), .VAR45(VAR69) );
assign VAR75 = VAR33;
always @ (posedge VAR33 or posedge VAR74) begin
if (VAR74) begin
VAR41 <= 0;
end
else begin
VAR41 <= VAR6;
end
end
reg VAR72;
always @ (posedge VAR25 or posedge VAR74) begin
if (VAR74) begin
VAR72 <= 0;
VAR50 <= 0;
VAR63 <= 0;
end
else begin
VAR50 <= VAR41;
VAR72 <= VAR33;
VAR63 <= 0;
if (!VAR72 && VAR33) begin
VAR63 <= 1;
end
end
end
endmodule
|
bsd-3-clause
|
YoelRP/PROYECTO
|
bin/example/ram.v
| 1,190 |
module MODULE1 # ( parameter VAR13= 16, parameter VAR10=8, parameter VAR7=8 )
(
input wire VAR14,
input wire VAR12,
input wire[VAR10-1:0] VAR3,
input wire[VAR10-1:0] VAR8,
input wire[VAR10-1:0] VAR9,
input wire[VAR13-1:0] VAR5,
output reg [VAR13-1:0] VAR1,
output reg [VAR13-1:0] VAR4
);
reg [VAR13-1:0] VAR11 [VAR7:0];
always @(posedge VAR14)
begin
if (VAR12)
VAR11[VAR9] <= VAR5;
VAR1 <= VAR11[VAR3];
VAR4 <= VAR11[VAR8];
end
endmodule
module MODULE2 # ( parameter VAR13= 16, parameter VAR10=8, parameter VAR7=8 )
(
input wire VAR14,
input wire VAR12,
input wire[VAR10-1:0] VAR6,
input wire[VAR10-1:0] VAR9,
input wire[VAR13-1:0] VAR5,
output reg [VAR13-1:0] VAR2
);
reg [VAR13-1:0] VAR11 [VAR7:0];
always @(posedge VAR14)
begin
if (VAR12)
VAR11[VAR9] <= VAR5;
VAR2 <= VAR11[VAR6];
end
endmodule
|
gpl-3.0
|
cfib/bf2hw
|
lib/toplevel/bf2hw_top.v
| 1,822 |
module MODULE1(input VAR12, input VAR5, output VAR10);
wire VAR6;
wire VAR8;
wire VAR1;
wire [7:0] VAR15;
wire [7:0] VAR4;
wire VAR9;
wire VAR2; wire VAR16;
wire reset;
reg [2:0] VAR11;
assign VAR9 = ~VAR6;
VAR13 VAR3 (.VAR14(VAR12), .VAR7(VAR2), .VAR16(VAR16));
assign reset = VAR11[2];
|
gpl-3.0
|
golfit/QcmMasterController
|
QcmMasterControllerWithFCounterMain.v
| 4,139 |
module MODULE1(clk, VAR6, VAR1, VAR3, VAR4, VAR8, VAR9, VAR2);
input clk, VAR6; output wire [6:0] VAR1, VAR3; output VAR4, VAR8; output VAR9; output VAR2;
wire [13:0] VAR7; wire [6:0] state;
reg [1:0] VAR5;
|
mit
|
R4PaSs/linguist
|
samples/Verilog/t_button_debounce.v
| 1,990 |
module MODULE1();
parameter
VAR6 = 66000000,
VAR4 = 2;
reg clk, VAR2, VAR5;
wire VAR1;
VAR3
.VAR6(VAR6),
.VAR4(VAR4)
)
VAR3
(
.clk(clk),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.behavioral.v
| 1,341 |
module MODULE1( VAR2, VAR7, VAR3, VAR6, VAR4 );
input VAR4, VAR6, VAR2, VAR3;
output VAR7;
VAR8 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4));
VAR8 VAR5(.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4));
|
apache-2.0
|
open-power/snap
|
actions/hdl_helloworld/hw/hdl/action_hdl_helloworld.v
| 21,969 |
module MODULE1 # (
parameter VAR39 = 4,
parameter VAR57 = 33,
parameter VAR79 = 512,
parameter VAR38 = 1,
parameter VAR10 = 1,
parameter VAR85 = 1,
parameter VAR2 = 1,
parameter VAR31 = 1,
parameter VAR58 = 32,
parameter VAR62 = 32,
parameter VAR80 = 2,
parameter VAR16 = 64,
parameter VAR54 = 512,
parameter VAR71 = 8,
parameter VAR73 = 8,
parameter VAR21 = 1,
parameter VAR30 = 1,
parameter VAR72 = 1
)
(
input clk ,
input VAR75 ,
output [VAR80 - 1:0] VAR42 ,
output [VAR16 - 1:0] VAR64 ,
output [0007:0] VAR65 ,
output [0002:0] VAR8 ,
output [0001:0] VAR81 ,
output [0003:0] VAR48 ,
output [0001:0] VAR86 ,
output [0002:0] VAR15 ,
output [0003:0] VAR37 ,
output [0003:0] VAR14 ,
output [VAR71 - 1:0] VAR18 ,
output VAR52 ,
input VAR46 ,
output [VAR80 - 1:0] VAR7 ,
output [VAR54 - 1:0] VAR51 ,
output [(VAR54/8) -1:0] VAR77 ,
output VAR76 ,
output VAR84 ,
input VAR9 ,
output VAR83 ,
input [VAR80 - 1:0] VAR82 ,
input [0001:0] VAR35 ,
input VAR53 ,
output [VAR80 - 1:0] VAR67 ,
output [VAR16 - 1:0] VAR61 ,
output [0007:0] VAR78 ,
output [0002:0] VAR34 ,
output [0001:0] VAR60 ,
output [VAR73 - 1:0] VAR24 ,
output [0002:0] VAR43 ,
output [0001:0] VAR59 ,
output [0002:0] VAR63 ,
output [0003:0] VAR20 ,
output [0008:0] VAR33 ,
output VAR36 ,
input VAR11 ,
output VAR19 ,
input [VAR80 - 1:0] VAR47 ,
input [VAR54 - 1:0] VAR49 ,
input [0001:0] VAR69 ,
input VAR70 ,
input VAR17 ,
output VAR5 ,
input [VAR62 - 1:0] VAR3 ,
input [0002:0] VAR41 ,
input VAR27 ,
output VAR44 ,
input [VAR58 - 1:0] VAR55 ,
input [(VAR58/8) -1:0] VAR25 ,
input VAR26 ,
output [0001:0] VAR13 ,
output VAR29 ,
input VAR50 ,
output VAR45 ,
input VAR4 ,
input [VAR62 - 1:0] VAR68 ,
input [0002:0] VAR23 ,
output [VAR58 - 1:0] VAR74 ,
output [0001:0] VAR12 ,
input VAR28 ,
output VAR66 ,
input [31:0] VAR32 ,
input [31:0] VAR1
);
reg [0000:0] VAR56;
always @(posedge clk) begin
if (VAR75 == 0) begin
VAR56 <= 0;
end else begin
VAR56 <= 1;
end
end
VAR6 #(
.VAR39 (VAR39 ),
.VAR57 (VAR57 ),
.VAR79 (VAR79 ),
.VAR38(VAR38),
.VAR10(VAR10),
.VAR85 (VAR85 ),
.VAR2 (VAR2 ),
.VAR31 (VAR31 ),
.VAR58 (VAR58 ),
.VAR62 (VAR62 ),
.VAR80 (VAR80 ),
.VAR16 (VAR16 ),
.VAR54 (VAR54 ),
.VAR71 (VAR71 ),
.VAR73 (VAR73 ),
.VAR21 (VAR21 ),
.VAR30 (VAR30 ),
.VAR72 (VAR72 )
) VAR22 (
.clk (clk ),
.VAR75 (VAR75 ),
.VAR42 (VAR42 ),
.VAR64 (VAR64 ),
.VAR65 (VAR65 ),
.VAR8 (VAR8 ),
.VAR81 (VAR81 ),
.VAR48 (VAR48 ),
.VAR86 (VAR86 ),
.VAR15 (VAR15 ),
.VAR37 (VAR37 ),
.VAR14 (VAR14 ),
.VAR18 (VAR18 ),
.VAR52 (VAR52 ),
.VAR46 (VAR46 ),
.VAR7 (VAR7 ),
.VAR51 (VAR51 ),
.VAR77 (VAR77 ),
.VAR76 (VAR76 ),
.VAR84 (VAR84 ),
.VAR9 (VAR9 ),
.VAR83 (VAR83 ),
.VAR82 (VAR82 ),
.VAR35 (VAR35 ),
.VAR53 (VAR53 ),
.VAR67 (VAR67 ),
.VAR61 (VAR61 ),
.VAR78 (VAR78 ),
.VAR34 (VAR34 ),
.VAR60 (VAR60 ),
.VAR24 (VAR24 ),
.VAR43 (VAR43 ),
.VAR59 (VAR59 ),
.VAR63 (VAR63 ),
.VAR20 (VAR20 ),
.VAR33 (VAR33 ),
.VAR36 (VAR36 ),
.VAR11 (VAR11 ),
.VAR19 (VAR19 ),
.VAR47 (VAR47 ),
.VAR49 (VAR49 ),
.VAR69 (VAR69 ),
.VAR70 (VAR70 ),
.VAR17 (VAR17 ),
.VAR5 (VAR5 ),
.VAR3 (VAR3 ),
.VAR41 (VAR41 ),
.VAR27 (VAR27 ),
.VAR44 (VAR44 ),
.VAR55 (VAR55 ),
.VAR25 (VAR25 ),
.VAR26 (VAR26 ),
.VAR13 (VAR13 ),
.VAR29 (VAR29 ),
.VAR50 (VAR50 ),
.VAR45 (VAR45 ),
.VAR4 (VAR4 ),
.VAR68 (VAR68 ),
.VAR23 (VAR23 ),
.VAR74 (VAR74 ),
.VAR12 (VAR12 ),
.VAR28 (VAR28 ),
.VAR66 (VAR66 ),
.VAR40 (VAR56 ),
.VAR32 (VAR32 ),
.VAR1 (VAR1 )
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.pp.blackbox.v
| 1,256 |
module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR2
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule
|
apache-2.0
|
peteasa/parallella-fpga
|
AdiHDLLib/library/common/ad_tdd_control.v
| 23,716 |
module MODULE1(
clk,
rst,
VAR69,
VAR95,
VAR55,
VAR60,
VAR7,
VAR87,
VAR96,
VAR102,
VAR16,
VAR21,
VAR46,
VAR39,
VAR94,
VAR100,
VAR28,
VAR80,
VAR83,
VAR23,
VAR5,
VAR93,
VAR11,
VAR36,
VAR71,
VAR31,
VAR34,
VAR19,
VAR116,
VAR56,
VAR61,
VAR104,
VAR44,
VAR54,
VAR33,
VAR50,
VAR6,
VAR9);
parameter integer VAR88 = 0; parameter integer VAR10 = 0;
localparam VAR62 = 1;
localparam VAR113 = 0;
input clk;
input rst;
input VAR69;
output VAR95;
input VAR55;
input VAR60;
input VAR7;
input [ 7:0] VAR87;
input [23:0] VAR96;
input [23:0] VAR102;
input [23:0] VAR16;
input [23:0] VAR21;
input [23:0] VAR46;
input [23:0] VAR39;
input [23:0] VAR94;
input [23:0] VAR100;
input [23:0] VAR28;
input [23:0] VAR80;
input [23:0] VAR83;
input [23:0] VAR23;
input [23:0] VAR5;
input [23:0] VAR93;
input [23:0] VAR11;
input [23:0] VAR36;
input [23:0] VAR71;
input [23:0] VAR31;
input [23:0] VAR34;
input [23:0] VAR19;
input [23:0] VAR116;
input [23:0] VAR56;
input VAR61;
output VAR104;
output VAR44; output VAR54; output VAR33; output VAR50; output VAR6;
output [23:0] VAR9;
reg VAR44 = 1'b0;
reg VAR54 = 1'b0;
reg VAR33 = 1'b0;
reg VAR50 = 1'b0;
reg VAR6 = 1'b0;
reg [23:0] VAR79 = 24'h0;
reg [ 5:0] VAR17 = 6'h0;
reg VAR3 = VAR113;
reg VAR68 = VAR113;
reg VAR52 = 1'b0;
reg VAR73 = 1'b0;
reg VAR1 = 1'b0;
reg VAR105 = 1'b0;
reg VAR76 = 1'b0;
reg VAR40 = 1'b0;
reg VAR32 = 1'b0;
reg VAR111 = 1'b0;
reg VAR90 = 1'b0;
reg VAR37 = 1'b0;
reg VAR51 = 1'b0;
reg VAR13 = 1'b0;
reg VAR35 = 1'b0;
reg VAR78 = 1'b0;
reg VAR77 = 1'b0;
reg VAR58 = 1'b0;
reg VAR91 = 1'b0;
reg VAR4 = 1'b0;
reg VAR117 = 1'b0;
reg VAR108 = 1'b0;
reg VAR95 = 1'h0;
reg VAR99 = 1'b0;
reg VAR57 = 1'b0;
reg VAR48 = 1'b0;
reg VAR15 = 1'b0;
reg VAR104 = 1'b0;
wire [23:0] VAR86;
wire [23:0] VAR64;
wire [23:0] VAR114;
wire [23:0] VAR107;
wire [23:0] VAR42;
wire [23:0] VAR66;
wire [23:0] VAR29;
wire [23:0] VAR82;
wire [23:0] VAR47;
wire [23:0] VAR74;
wire [23:0] VAR24;
wire [23:0] VAR89;
wire [23:0] VAR97;
wire [23:0] VAR101;
wire [23:0] VAR110;
wire [23:0] VAR45;
wire [23:0] VAR41;
wire [23:0] VAR109;
wire [23:0] VAR92;
wire [23:0] VAR26;
wire VAR43;
wire VAR72;
wire VAR65;
assign VAR9 = VAR79;
always @(posedge clk) begin
if (rst == 1'b1) begin
VAR104 <= 1'b0;
VAR57 <= 1'b0;
VAR48 <= 1'b0;
VAR15 <= 1'b0;
end else begin
VAR104 <= VAR69;
VAR57 <= VAR61;
VAR48 <= VAR57;
VAR15 <= VAR48;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
VAR95 <= 1'b0;
end else begin
VAR95 <= ((~VAR15 & VAR48) == 1'b1) ? VAR69 : VAR95;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
VAR3 <= VAR113;
end else begin
VAR3 <= VAR68;
end
end
always @* begin
VAR68 <= VAR3;
case (VAR3)
VAR62 : begin
if ((VAR69 == 1'b0) || (VAR72 == 1'b1)) begin
VAR68 <= VAR113;
end
end
VAR113 : begin
if(VAR69 == 1'b1) begin
VAR68 <= ((~VAR15 & VAR48) == 1'b1) ? VAR62 : VAR113;
end
end
endcase
end
assign VAR43 = (VAR79 == VAR102) ? 1'b1 : 1'b0;
assign VAR72 = ((VAR99 == 1'b1) && (VAR79 == VAR102)) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (rst == 1'b1) begin
VAR79 <= VAR96;
end else begin
if (VAR3 == VAR62) begin
if ((~VAR15 & VAR48) == 1'b1) begin
VAR79 <= 24'b0;
end else begin
VAR79 <= (VAR79 < VAR102) ? VAR79 + 1 : 24'b0;
end
end else begin
VAR79 <= VAR96;
end
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
VAR17 <= VAR87;
end else begin
if (VAR3 == VAR62) begin
VAR17 <= ((VAR17 > 0) && (VAR43 == 1'b1)) ? VAR17 - 1 : VAR17;
end else begin
VAR17 <= VAR87;
end
end
end
always @(posedge clk) begin
VAR99 <= (VAR17 == 6'b1) ? 1'b1 : 1'b0;
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR52 <= 1'b0;
end else if(VAR79 == VAR86) begin
VAR52 <= 1'b1;
end else begin
VAR52 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR51 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR24)) begin
VAR51 <= 1'b1;
end else begin
VAR51 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR73 <= 1'b0;
end else if(VAR79 == VAR64) begin
VAR73 <= 1'b1;
end else begin
VAR73 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR13 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR89)) begin
VAR13 <= 1'b1;
end else begin
VAR13 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR1 <= 1'b0;
end else if(VAR79 == VAR114) begin
VAR1 <= 1'b1;
end else begin
VAR1 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR35 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR97)) begin
VAR35 <= 1'b1;
end else begin
VAR35 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR105 <= 1'b0;
end else if(VAR79 == VAR107) begin
VAR105 <= 1'b1;
end else begin
VAR105 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR78 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR101)) begin
VAR78 <= 1'b1;
end else begin
VAR78 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR76 <= 1'b0;
end else if(VAR79 == VAR42) begin
VAR76 <= 1'b1;
end else begin
VAR76 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR77 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR110)) begin
VAR77 <= 1'b1;
end else begin
VAR77 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR40 <= 1'b0;
end else if(VAR79 == VAR66) begin
VAR40 <= 1'b1;
end else begin
VAR40 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR58 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR45)) begin
VAR58 <= 1'b1;
end else begin
VAR58 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR32 <= 1'b0;
end else if(VAR79 == VAR29) begin
VAR32 <= 1'b1;
end else begin
VAR32 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR91 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR41)) begin
VAR91 <= 1'b1;
end else begin
VAR91 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR111 <= 1'b0;
end else if(VAR79 == VAR82) begin
VAR111 <= 1'b1;
end else begin
VAR111 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR4 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR109)) begin
VAR4 <= 1'b1;
end else begin
VAR4 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR90 <= 1'b0;
end else if(VAR79 == VAR47) begin
VAR90 <= 1'b1;
end else begin
VAR90 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR117 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR92)) begin
VAR117 <= 1'b1;
end else begin
VAR117 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR37 <= 1'b0;
end else if(VAR79 == VAR74) begin
VAR37 <= 1'b1;
end else begin
VAR37 <= 1'b0;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR108 <= 1'b0;
end else if((VAR55 == 1'b1) && (VAR79 == VAR26)) begin
VAR108 <= 1'b1;
end else begin
VAR108 <= 1'b0;
end
end
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR103 (
.clk(clk),
.VAR12(VAR16),
.VAR27(VAR102),
.out(VAR86),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR49 (
.clk(clk),
.VAR12(VAR21),
.VAR27(VAR102),
.out(VAR64),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR2 (
.clk(clk),
.VAR12(VAR46),
.VAR27(VAR102),
.out(VAR114),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR98 (
.clk(clk),
.VAR12(VAR39),
.VAR27(VAR102),
.out(VAR107),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR8 (
.clk(clk),
.VAR12(VAR94),
.VAR27(VAR102),
.out(VAR42),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR20 (
.clk(clk),
.VAR12(VAR100),
.VAR27(VAR102),
.out(VAR66),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR67 (
.clk(clk),
.VAR12(VAR28),
.VAR27(VAR102),
.out(VAR29),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR75 (
.clk(clk),
.VAR12(VAR80),
.VAR27(VAR102),
.out(VAR82),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR115 (
.clk(clk),
.VAR12(VAR5),
.VAR27(VAR102),
.out(VAR24),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR25 (
.clk(clk),
.VAR12(VAR93),
.VAR27(VAR102),
.out(VAR89),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR81 (
.clk(clk),
.VAR12(VAR11),
.VAR27(VAR102),
.out(VAR97),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR22 (
.clk(clk),
.VAR12(VAR36),
.VAR27(VAR102),
.out(VAR101),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR70 (
.clk(clk),
.VAR12(VAR71),
.VAR27(VAR102),
.out(VAR110),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR53 (
.clk(clk),
.VAR12(VAR31),
.VAR27(VAR102),
.out(VAR45),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR106 (
.clk(clk),
.VAR12(VAR34),
.VAR27(VAR102),
.out(VAR41),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR10),
.VAR18(0)
) VAR63 (
.clk(clk),
.VAR12(VAR19),
.VAR27(VAR102),
.out(VAR109),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR88),
.VAR18(0)
) VAR59 (
.clk(clk),
.VAR12(VAR83),
.VAR27(VAR102),
.out(VAR47),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR88),
.VAR18(0)
) VAR112 (
.clk(clk),
.VAR12(VAR116),
.VAR27(VAR102),
.out(VAR92),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR88),
.VAR18(0)
) VAR38 (
.clk(clk),
.VAR12(VAR23),
.VAR27(VAR102),
.out(VAR74),
.VAR85(1'b1)
);
VAR30 #(
.VAR118(24),
.VAR14(VAR88),
.VAR18(0)
) VAR84 (
.clk(clk),
.VAR12(VAR56),
.VAR27(VAR102),
.out(VAR26),
.VAR85(1'b1)
);
assign VAR65 = VAR60 ^ VAR7;
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR54 <= 1'b0;
end else if((VAR3 == VAR113) || (VAR73 == 1'b1) || (VAR13 == 1'b1)) begin
VAR54 <= 1'b0;
end else if((VAR3 == VAR62) && ((VAR52 == 1'b1) || (VAR51 == 1'b1))) begin
VAR54 <= 1'b1;
end else if((VAR3 == VAR62) && (VAR65 == 1'b1)) begin
VAR54 <= VAR7;
end else begin
VAR54 <= VAR54;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR33 <= 1'b0;
end else if((VAR3 == VAR113) || (VAR105 == 1'b1) || (VAR78 == 1'b1)) begin
VAR33 <= 1'b0;
end else if((VAR3 == VAR62) && ((VAR1 == 1'b1) || (VAR35 == 1'b1))) begin
VAR33 <= 1'b1;
end else if((VAR3 == VAR62) && (VAR65 == 1'b1)) begin
VAR33 <= VAR60;
end else begin
VAR33 <= VAR33;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR50 <= 1'b0;
end else if((VAR3 == VAR113) || (VAR40 == 1'b1) || (VAR58 == 1'b1)) begin
VAR50 <= 1'b0;
end else if((VAR3 == VAR62) && ((VAR76 == 1'b1) || (VAR77 == 1'b1))) begin
VAR50 <= 1'b1;
end else if((VAR3 == VAR62) && (VAR65 == 1'b1)) begin
VAR50 <= VAR7;
end else begin
VAR50 <= VAR50;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR6 <= 1'b0;
end else if((VAR3 == VAR113) || (VAR111 == 1'b1) || (VAR4 == 1'b1)) begin
VAR6 <= 1'b0;
end else if((VAR3 == VAR62) && ((VAR32 == 1'b1) || (VAR91 == 1'b1))) begin
VAR6 <= 1'b1;
end else if((VAR3 == VAR62) && (VAR65 == 1'b1)) begin
VAR6 <= VAR60;
end else begin
VAR6 <= VAR6;
end
end
always @(posedge clk) begin
if(rst == 1'b1) begin
VAR44 <= 1'b0;
end else if((VAR3 == VAR113) || (VAR37 == 1'b1) || (VAR108 == 1'b1)) begin
VAR44 <= 1'b0;
end else if((VAR3 == VAR62) && ((VAR90 == 1'b1) || (VAR117 == 1'b1))) begin
VAR44 <= 1'b1;
end else if((VAR3 == VAR62) && (VAR65 == 1'b1)) begin
VAR44 <= VAR60;
end else begin
VAR44 <= VAR44;
end
end
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a2111o/sky130_fd_sc_lp__a2111o.blackbox.v
| 1,394 |
module MODULE1 (
VAR3 ,
VAR7,
VAR10,
VAR2,
VAR9,
VAR6
);
output VAR3 ;
input VAR7;
input VAR10;
input VAR2;
input VAR9;
input VAR6;
supply1 VAR8;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o221a/sky130_fd_sc_hs__o221a.functional.v
| 2,091 |
module MODULE1 (
VAR6,
VAR3,
VAR7 ,
VAR13 ,
VAR14 ,
VAR2 ,
VAR9 ,
VAR4
);
input VAR6;
input VAR3;
output VAR7 ;
input VAR13 ;
input VAR14 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
wire VAR9 VAR1 ;
wire VAR9 VAR18 ;
wire VAR8 ;
wire VAR16;
or VAR11 (VAR1 , VAR9, VAR2 );
or VAR15 (VAR18 , VAR14, VAR13 );
and VAR5 (VAR8 , VAR1, VAR18, VAR4 );
VAR10 VAR17 (VAR16, VAR8, VAR6, VAR3);
buf VAR12 (VAR7 , VAR16 );
endmodule
|
apache-2.0
|
secworks/blake2
|
src/rtl/blake2_G.v
| 3,981 |
module MODULE1(
input wire [63 : 0] VAR25,
input wire [63 : 0] VAR4,
input wire [63 : 0] VAR1,
input wire [63 : 0] VAR14,
input wire [63 : 0] VAR19,
input wire [63 : 0] VAR2,
output wire [63 : 0] VAR8,
output wire [63 : 0] VAR6,
output wire [63 : 0] VAR15,
output wire [63 : 0] VAR5
);
reg [63 : 0] VAR21;
reg [63 : 0] VAR12;
reg [63 : 0] VAR22;
reg [63 : 0] VAR18;
assign VAR8 = VAR21;
assign VAR6 = VAR12;
assign VAR15 = VAR22;
assign VAR5 = VAR18;
always @*
begin : VAR3
reg [63 : 0] VAR16;
reg [63 : 0] VAR11;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] VAR24;
reg [63 : 0] VAR13;
reg [63 : 0] VAR9;
reg [63 : 0] VAR10;
reg [63 : 0] VAR17;
reg [63 : 0] VAR7;
reg [63 : 0] VAR20;
reg [63 : 0] VAR23;
VAR16 = VAR25 + VAR4 + VAR19;
VAR17 = VAR14 ^ VAR16;
VAR7 = {VAR17[31 : 0], VAR17[63 : 32]};
VAR9 = VAR1 + VAR7;
b0 = VAR4 ^ VAR9;
b1 = {b0[23 : 0], b0[63 : 24]};
VAR11 = VAR16 + b1 + VAR2;
VAR20 = VAR7 ^ VAR11;
VAR23 = {VAR20[15 : 0], VAR20[63 : 16]};
VAR10 = VAR9 + VAR23;
VAR24 = b1 ^ VAR10;
VAR13 = {VAR24[62 : 0], VAR24[63]};
VAR21 = VAR11;
VAR12 = VAR13;
VAR22 = VAR10;
VAR18 = VAR23;
end endmodule
|
bsd-2-clause
|
EliasVansteenkiste/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_064bits.v
| 1,917 |
module MODULE1 (
clk,
VAR20, VAR22, VAR3, VAR6, VAR26, VAR4, VAR19, VAR16,
sum,
);
input clk;
input [VAR29+0-1:0] VAR20, VAR22, VAR3, VAR6, VAR26, VAR4, VAR19, VAR16;
output [VAR29 :0] sum;
reg [VAR29 :0] sum;
wire [VAR29+3-1:0] VAR30;
wire [VAR29+2-1:0] VAR12, VAR13;
wire [VAR29+1-1:0] VAR18, VAR28, VAR5, VAR14;
reg [VAR29+0-1:0] VAR2, VAR21, VAR24, VAR15, VAR11, VAR7, VAR23, VAR9;
MODULE2 VAR34(VAR12, VAR13, VAR30 );
MODULE2 VAR27(VAR18, VAR28, VAR12 );
MODULE2 VAR17(VAR5, VAR14, VAR13 );
MODULE2 VAR10(VAR2, VAR21, VAR18);
MODULE2 VAR25(VAR24, VAR15, VAR28);
MODULE2 VAR33(VAR11, VAR7, VAR5);
MODULE2 VAR1(VAR23, VAR9, VAR14);
always @(posedge clk) begin
VAR2 <= VAR20;
VAR21 <= VAR22;
VAR24 <= VAR3;
VAR15 <= VAR6;
VAR11 <= VAR26;
VAR7 <= VAR4;
VAR23 <= VAR19;
VAR9 <= VAR16;
sum <= VAR30;
sum <= VAR12;
end
endmodule
module MODULE2(VAR31,VAR8,sum);
parameter VAR32 = 0;
input [VAR29+VAR32-1:0] VAR31;
input [VAR29+VAR32-1:0] VAR8;
output [VAR29+VAR32:0] sum;
assign sum = VAR31 + VAR8;
endmodule
|
mit
|
scalable-networks/ext
|
uhd/fpga/usrp1/sdr_lib/hb/halfband_decim.v
| 6,619 |
module MODULE1
(input VAR45, input reset, input enable, input VAR35, output wire VAR9,
input wire [15:0] VAR7, output reg [15:0] VAR39,output wire [15:0] VAR26);
reg [3:0] VAR36;
reg [3:0] VAR34;
reg [3:0] VAR10;
reg [3:0] VAR28;
wire signed [15:0] VAR18,VAR42, sum, VAR3;
wire signed [30:0] VAR22;
wire signed [33:0] VAR5;
wire VAR32;
reg VAR24;
always @(posedge VAR45)
if(reset)
VAR24 <= 1'b0;
else
if(VAR35)
VAR24 <= ~VAR24;
wire VAR37 = VAR35 & VAR24;
always @(posedge VAR45)
if(reset)
VAR28 <= 4'd0;
else if(VAR37)
VAR28 <= VAR28 + 4'd1;
always @(posedge VAR45)
if(reset)
VAR10 <= 4'd8;
else if (VAR37)
VAR10 <= 4'd0;
else if(VAR10 != 4'd8)
VAR10 <= VAR10 + 4'd1;
reg VAR8,VAR15,VAR38,VAR52,VAR27,VAR1,VAR20,VAR47,VAR13,VAR30,VAR33,VAR48,VAR31;
always @(posedge VAR45)
begin
VAR8 <= VAR37;
VAR15 <= VAR8;
VAR38 <= VAR15;
VAR52 <= VAR38;
VAR27 <= VAR52;
VAR1 <= VAR27;
VAR20 <= VAR1;
VAR47 <= VAR20;
VAR13 <= VAR47;
VAR30 <= VAR13;
VAR33 <= VAR30;
VAR48 <= VAR33;
VAR31 <= VAR48;
end
reg VAR25, VAR14;
always @(posedge VAR45)
begin
VAR14 <= VAR10!=8;
VAR25 <= VAR14;
end
assign VAR32 = VAR52; wire VAR49 = VAR52; assign VAR9 = VAR27; wire VAR16;
always @*
case(VAR10[2:0])
3'd0 : begin VAR36 = VAR28 + 4'd0; VAR34 = VAR28 + 4'd15; end
3'd1 : begin VAR36 = VAR28 + 4'd1; VAR34 = VAR28 + 4'd14; end
3'd2 : begin VAR36 = VAR28 + 4'd2; VAR34 = VAR28 + 4'd13; end
3'd3 : begin VAR36 = VAR28 + 4'd3; VAR34 = VAR28 + 4'd12; end
3'd4 : begin VAR36 = VAR28 + 4'd4; VAR34 = VAR28 + 4'd11; end
3'd5 : begin VAR36 = VAR28 + 4'd5; VAR34 = VAR28 + 4'd10; end
3'd6 : begin VAR36 = VAR28 + 4'd6; VAR34 = VAR28 + 4'd9; end
3'd7 : begin VAR36 = VAR28 + 4'd7; VAR34 = VAR28 + 4'd8; end
default: begin VAR36 = VAR28 + 4'd0; VAR34 = VAR28 + 4'd15; end
endcase
VAR21 VAR21 (.VAR45(VAR45),.addr(VAR10[2:0]-3'd1),.VAR6(VAR3));
VAR19 VAR23 (.VAR45(VAR45),.write(VAR35 & ~VAR24),
.VAR40(VAR28),.VAR2(VAR7),
.VAR36(VAR36),.VAR34(VAR34),
.sum(sum));
VAR43 VAR51 (.VAR45(VAR45),.write(VAR35 & VAR24), .VAR40(VAR28),.VAR2(VAR7),
.VAR11(VAR28+4'd6),.VAR44(VAR42));
VAR29 VAR29(.VAR45(VAR45),.VAR12(VAR3),.VAR4(sum),.VAR22(VAR22),.VAR50(VAR25),.VAR17(VAR16));
VAR46 VAR46(.VAR45(VAR45),.reset(reset),.VAR50(VAR16),.VAR17(),
.VAR32(VAR32),.VAR41(VAR22),.sum(VAR5));
wire signed [33:0] dout = VAR5 + {{4{VAR42[15]}},VAR42,14'b0};
always @(posedge VAR45)
if(reset)
VAR39 <= 16'd0;
end
else if(VAR49)
VAR39 <= dout[30:15] + (dout[33]& |dout[14:0]);
assign VAR26 = { VAR45,reset,VAR16,VAR25,VAR32,VAR49,VAR24,VAR35,VAR9,VAR10};
endmodule
|
gpl-2.0
|
Siliciumer/DOS-Mario-FPGA
|
sources/draw_mario_score.v
| 2,445 |
module MODULE1(
input wire clk,
input wire rst,
input wire [9:0] VAR4,
input wire VAR18,
input wire [9:0] VAR5,
input wire VAR13,
input wire [23:0] VAR19,
input wire VAR8,
input wire [7:0] VAR14,
output reg [9:0] VAR6,
output reg VAR3,
output reg [9:0] VAR10,
output reg VAR17,
output reg [23:0] VAR15,
output reg VAR1,
output reg [7:0] VAR20,
output reg [3:0] VAR16
);
reg [23:0] VAR9;
localparam VAR2 = 40;
localparam VAR7 = 50;
localparam VAR11 = 552;
localparam VAR12 = 16;
always @(posedge clk or posedge rst) begin
if(rst) begin
VAR6 <= 0;
VAR10 <= 0;
VAR3 <= 0;
VAR17 <= 0;
VAR15 <= 0;
VAR1 <= 0;
end
else begin
VAR6 <= VAR4;
VAR10 <= VAR5;
VAR3 <= VAR18;
VAR17 <= VAR13;
VAR15 <= VAR9;
VAR1 <= VAR8;
end
end
always @* begin
if ((VAR4 >= VAR2) && (VAR4 < VAR2 + VAR11) && (VAR5 >= VAR7) && (VAR5 < VAR7 + VAR12) && (VAR14[(VAR2 - VAR4)]))
begin
if(VAR20 == 8'h20)
VAR9 = 24'hffff00;
end
else
VAR9 = 24'hffffff;
end
else begin
VAR9 = VAR19; end
end
always @* begin
VAR20 = (VAR4 - VAR2 - 1)>>3;
end
always @* begin
VAR16 = VAR5 - VAR7;
end
endmodule
|
mit
|
gralco/FPGA-Elevator-Project
|
Mojo V3 - Xilinx Spartan 6 Project/Elevator IO Shield/source/elevator.v
| 2,622 |
module MODULE1 (
clk,
reset,
en,
VAR9,
VAR7,
VAR4,
VAR12,
VAR6,
VAR5,
VAR3,
VAR8,
VAR10
);
input clk;
input reset;
input en;
input [3:0] VAR9;
output [3:0] VAR7;
wire [3:0] VAR7;
output [3:0] VAR4;
reg [3:0] VAR4;
output VAR12;
reg VAR12;
output VAR6;
reg VAR6;
output VAR5;
reg VAR5;
output VAR3;
reg VAR3;
output [3:0] VAR8;
wire [3:0] VAR8;
output [7:0] VAR10;
wire [7:0] VAR10;
always @(en, VAR9) begin: VAR2
if (((VAR9 != 0) && en)) begin
VAR12 = ((VAR9[3] || (VAR9[1] && (!VAR9[2]))) != 0);
VAR6 = ((VAR9[2] || VAR9[3]) != 0);
end
end
always @(reset, VAR12, VAR6, en, VAR9) begin: VAR11
if (reset) begin
VAR5 = (1'b0 != 0);
VAR3 = (1'b0 != 0);
end
else if (((VAR9 != 0) && en)) begin
VAR5 = VAR12;
VAR3 = VAR6;
end
end
assign VAR7 = {((((!VAR4[3]) && (!VAR4[2]) && (!VAR4[1]) && (!VAR4[0]) && VAR3 && VAR5) || ((!VAR4[3]) && (!VAR4[2]) && VAR4[1] && (!VAR4[0]) && (!VAR3) && (!VAR5)) || (VAR4[3] && VAR4[2] && VAR4[1] && (!VAR4[0])) || ((!VAR4[3]) && (!VAR4[2]) && VAR4[1] && VAR4[0] && (!VAR3))) != 0), ((((!VAR4[3]) && (!VAR4[2]) && VAR4[1] && VAR4[0] && (!VAR3) && (!VAR5)) || ((!VAR4[3]) && (!VAR4[2]) && (!VAR4[1]) && VAR3 && VAR5) || (VAR4[3] && VAR4[2] && (!VAR4[1]) && VAR4[0]) || ((!VAR4[3]) && (!VAR4[2]) && (!VAR4[1]) && (!VAR4[0]) && VAR3)) != 0), ((((!VAR4[3]) && (!VAR4[2]) && VAR4[1] && VAR4[0] && (!VAR3)) || ((!VAR4[3]) && (!VAR4[2]) && VAR4[0] && VAR3) || (VAR4[2] && (!VAR4[1]) && VAR4[0]) || ((!VAR4[3]) && VAR4[1] && (!VAR4[0]) && VAR3) || ((!VAR4[3]) && VAR4[2] && VAR4[1] && (!VAR4[0]))) != 0), ((((!VAR4[3]) && (!VAR4[2]) && VAR4[1] && (!VAR4[0]) && (!VAR3) && (!VAR5)) || ((!VAR4[3]) && (!VAR4[2]) && (!VAR4[1]) && (!VAR3) && VAR5) || ((!VAR4[3]) && (!VAR4[2]) && VAR4[1] && VAR3 && VAR5) || ((!VAR4[3]) && (!VAR4[2]) && (!VAR4[1]) && (!VAR4[0]) && VAR3) || (VAR4[3] && VAR4[1] && (!VAR4[0])) || ((!VAR4[3]) && VAR4[2] && VAR4[1] && (!VAR4[0])) || (VAR4[1] && (!VAR4[0]) && VAR5)) != 0)};
always @(posedge clk, posedge reset) begin: VAR1
if (reset == 1) begin
VAR4 <= 0;
end
else begin
if (en) begin
VAR4 <= VAR7;
end
end
end
assign VAR8 = {((VAR4[1] && VAR4[0]) != 0), ((VAR4[1] && (!VAR4[0])) != 0), (((!VAR4[1]) && VAR4[0]) != 0), (((!VAR4[1]) && (!VAR4[0])) != 0)};
assign VAR10[0] = ~(VAR8[0] | VAR8[2] | VAR8[3]);
assign VAR10[1] = ~(VAR8[0] | VAR8[1] | VAR8[2] | VAR8[3]);
assign VAR10[2] = ~(VAR8[0] | VAR8[1] | VAR8[3]);
assign VAR10[3] = ~(VAR8[0] | VAR8[2] | VAR8[3]);
assign VAR10[4] = ~(VAR8[0] | VAR8[2]);
assign VAR10[5] = ~(VAR8[0]);
assign VAR10[6] = ~(VAR8[2] | VAR8[3]);
assign VAR10[7] = 1'b1;
endmodule
|
gpl-2.0
|
The-OpenROAD-Project/asap7
|
asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_RVT_TT_201020.v
| 210,832 |
module MODULE1 (VAR1, VAR7, VAR6, VAR4, VAR10);
output VAR1;
input VAR7, VAR6, VAR4, VAR10;
wire VAR3, VAR5, VAR11;
wire VAR9, VAR2, VAR8;
not (VAR9, VAR10);
not (VAR11, VAR4);
not (VAR5, VAR6);
and (VAR2, VAR5, VAR11);
not (VAR3, VAR7);
and (VAR8, VAR3, VAR11);
or (VAR1, VAR8, VAR2, VAR9);
|
bsd-3-clause
|
The-OpenROAD-Project/asap7
|
asap7sc6t_26/Verilog/asap7sc6t_OA_LVT_SS_210930.v
| 242,182 |
module MODULE1 (VAR13, VAR4, VAR3, VAR10, VAR8, VAR2);
output VAR13;
input VAR4, VAR3, VAR10, VAR8, VAR2;
wire VAR11, VAR1, VAR6;
wire VAR9, VAR12, VAR7;
wire VAR5;
not (VAR12, VAR2);
not (VAR9, VAR8);
not (VAR6, VAR10);
and (VAR7, VAR6, VAR9);
not (VAR1, VAR3);
not (VAR11, VAR4);
and (VAR5, VAR11, VAR1, VAR9);
or (VAR13, VAR5, VAR7, VAR12);
|
bsd-3-clause
|
ElegantLin/My-CPU
|
project_4/project_4.srcs/sources_1/imports/Chapter11/hilo_reg.v
| 2,431 |
module MODULE1(
input wire clk,
input wire rst,
input wire VAR9,
input wire[VAR1] VAR6,
input wire[VAR1] VAR3,
output reg[VAR1] VAR4,
output reg[VAR1] VAR7
);
always @ (posedge clk) begin
if (rst == VAR2) begin
VAR4 <= VAR8;
VAR7 <= VAR8;
end else if((VAR9 == VAR5)) begin
VAR4 <= VAR6;
VAR7 <= VAR3;
end
end
endmodule
|
gpl-3.0
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/jbi/jbi_mout/rtl/jbi_mout_csr.v
| 7,277 |
module MODULE1 (
VAR36, VAR2, VAR12, VAR34,
VAR11, VAR60, VAR46,
VAR58, VAR52,
VAR55, VAR22,
VAR25, VAR53, VAR1, VAR49,
VAR37, VAR54, VAR23, VAR29, VAR59,
VAR19, VAR39, VAR56, VAR18, VAR43, VAR41,
VAR42, VAR48, VAR27, VAR3,
VAR30, VAR6, VAR33,
VAR50, VAR15, clk, VAR16
);
output VAR36;
output VAR2;
input VAR37;
input [3:0] VAR54;
input VAR23;
input [3:0] VAR29;
input [31:0] VAR59;
output VAR12;
output VAR34;
output [3:0] VAR11;
input VAR19;
input VAR39;
input VAR56;
input VAR18; input VAR43; input VAR41; input [2:0] VAR42; input [2:0] VAR48; input [2:0] VAR27; input [2:0] VAR3; output VAR60; output VAR46; output [2:0] VAR58; output [2:0] VAR52; output [2:0] VAR55; output [2:0] VAR22; output [6:0] VAR25;
input VAR30; input [3:0] VAR6; input VAR33; input VAR50; input VAR15; output [3:0] VAR53; output VAR1; output VAR49;
input clk;
input VAR16;
wire VAR44;
wire VAR21;
VAR17 VAR8 (
.VAR4 (VAR37),
.VAR51 (VAR54),
.VAR26 (VAR23),
.VAR31 (VAR29),
.VAR34 (VAR34),
.VAR11 (VAR11),
.VAR19 (VAR19),
.VAR39 (VAR39),
.VAR12 (VAR12),
.VAR59 (VAR59),
.clk (clk),
.VAR16 (VAR16)
);
VAR24 VAR13 (
.VAR28 (VAR56),
.VAR18 (VAR18),
.VAR43 (VAR43),
.VAR41 (VAR41),
.VAR42 (VAR42),
.VAR48 (VAR48),
.VAR27 (VAR27),
.VAR3 (VAR3),
.VAR60 (VAR60),
.VAR46 (VAR46),
.VAR58(VAR58),
.VAR52(VAR52),
.VAR55(VAR55),
.VAR22(VAR22),
.VAR25 (VAR25),
.VAR36 (VAR36),
.VAR2 (VAR2),
.clk (clk),
.VAR16 (VAR16)
);
wire VAR14 = VAR30 && !VAR21; wire VAR62 = VAR44;
VAR7 VAR10 (.VAR45(VAR14), .VAR38(VAR62), .VAR57(VAR47), .VAR16(VAR16), .clk(clk));
wire VAR9 = VAR30;
VAR61 VAR5 (.din(VAR9), .VAR57(VAR21), .clk(clk));
wire VAR20 = (VAR33)? VAR50: VAR15;
assign VAR44 = VAR47 && VAR20;
assign VAR53[3:0] = VAR6[3:0] & {4{VAR44}};
wire VAR32 = VAR44;
VAR61 VAR40 (.din(VAR32), .VAR57(VAR35), .clk(clk));
assign VAR1 = VAR35;
assign VAR49 = VAR35;
endmodule
|
gpl-2.0
|
danbone/core
|
riscv/src/main/riscv_ex_pipe.v
| 3,477 |
module MODULE1 (
input clk,
input VAR7,
input VAR28,
output VAR25,
input [31:0] VAR5,
input [31:0] VAR9,
input [VAR24-1:0] VAR4,
input [31:0] VAR6,
input [VAR11-1:0] VAR14,
input [VAR13-1:0] VAR16,
output [31:0] VAR10,
output VAR31,
output VAR22,
input VAR15,
input [31:0] VAR1,
output [31:0] VAR20,
output [3:0] VAR30,
output VAR23,
output [31:0] VAR8
);
wire clk;
wire VAR7;
wire VAR28;
wire VAR25;
wire [31:0] VAR5;
wire [31:0] VAR9;
wire [VAR24-1:0] VAR4;
wire [31:0] VAR6;
wire [VAR11-1:0] VAR14;
wire [VAR13-1:0] VAR16;
wire VAR32;
wire VAR29;
wire VAR27;
wire [31:0] VAR17;
wire [VAR13-1:0] VAR26;
wire [VAR11-1:0] VAR12;
wire [31:0] VAR21;
wire [31:0] VAR10;
wire VAR31;
wire VAR22;
wire VAR15;
wire [31:0] VAR1;
wire [31:0] VAR20;
wire [3:0] VAR30;
wire VAR23;
wire [31:0] VAR8;
VAR3 VAR18 (
.clk (clk),
.VAR7 (VAR7),
.VAR28 (VAR28),
.VAR25 (VAR25),
.VAR5 (VAR5),
.VAR9 (VAR9),
.VAR4 (VAR4),
.VAR6 (VAR6),
.VAR14 (VAR14),
.VAR16 (VAR16),
.VAR32 (VAR32),
.VAR29 (VAR29),
.VAR27 (VAR27),
.VAR17 (VAR17),
.VAR26 (VAR26),
.VAR12 (VAR12),
.VAR21 (VAR21)
);
VAR19 VAR2 (
.clk (clk),
.VAR7 (VAR7),
.VAR32 (VAR32),
.VAR29 (VAR29),
.VAR27 (VAR27),
.VAR17 (VAR17),
.VAR26 (VAR26),
.VAR12 (VAR12),
.VAR21 (VAR21),
.VAR10 (VAR10),
.VAR31 (VAR31),
.VAR22 (VAR22),
.VAR15 (VAR15),
.VAR1 (VAR1),
.VAR20 (VAR20),
.VAR30 (VAR30),
.VAR23 (VAR23),
.VAR8 (VAR8)
);
endmodule
|
mit
|
Lan-Hekary/ARM
|
control_unit.v
| 4,488 |
module MODULE4(input [1:0] VAR50,input [5:0] VAR41,input [3:0]rd,
output reg [1:0] VAR9,output wire VAR49,output wire VAR30,
output wire VAR3,output wire VAR28,output wire VAR10,
output wire [1:0] VAR34,output wire [1:0] VAR42,output reg[1:0] VAR29 ,output wire VAR36
);
reg [9:0] VAR46;
wire VAR20;
wire VAR6;
always @*
case(VAR50)
2'b00: if(VAR41[5]) VAR46=10'b0001001001; else VAR46=10'b0000001001; 2'b01: if(VAR41[0]) VAR46=10'b0101011000; else VAR46=10'b0011010100; 2'b10: VAR46=10'b1001100010; default:VAR46=10'VAR48;
endcase
assign {VAR6,VAR28,VAR3,VAR10,VAR34,VAR30,VAR42,VAR20} = VAR46; always @*
if(VAR20)begin
case(VAR41[4:1])
4'd4 : VAR29=0; 4'd2 : VAR29=1; 4'd0 : VAR29=2; 4'd12: VAR29=3; 4'd10: VAR29=1; default:VAR29=2'VAR37;
endcase
VAR9[1]=VAR41[0]; VAR9[0] = VAR41[0] & (VAR29 == 0 | VAR29 == 1); end
else begin VAR9=0;
VAR29=0;
end
assign VAR49 =((rd == 15) & VAR30) | VAR6 ; assign VAR36 = (VAR41[4:1]==10);
endmodule
module MODULE1(input clk,input reset,input [3:0] VAR5,input [3:0]VAR27,input [1:0] VAR9 ,input VAR49,
input wire VAR4,input VAR3,input VAR36,output reg VAR17,
output wire VAR15,output wire VAR52 ,output wire VAR8);
wire [3:0] VAR35; wire VAR1,VAR33,VAR14,VAR13;
wire [1:0]VAR32;
assign VAR32= VAR9 & {2{VAR17}};
MODULE2 MODULE4 (clk,reset,VAR32[0],VAR27[1:0],VAR35[1:0]);
MODULE2 MODULE1 (clk,reset,VAR32[1],VAR27[3:2],VAR35[3:2]);
assign {VAR1,VAR33,VAR14,VAR13} = VAR35;
always@(*)
case(VAR5)
4'b0000: VAR17=VAR33; 4'b0001: VAR17=~VAR33; 4'b0010: VAR17=VAR14; 4'b0011: VAR17=~VAR14; 4'b0100: VAR17=VAR1; 4'b0101: VAR17=~VAR1; 4'b0110: VAR17=VAR13; 4'b0111: VAR17=~VAR13; 4'b1000: VAR17= ~VAR33 & VAR14; 4'b1001: VAR17= ~VAR14 | VAR33; 4'b1010: VAR17=~(VAR1^VAR13); 4'b1011: VAR17=VAR1^VAR13; 4'b1100: VAR17=~VAR33 & ~(VAR1 ^ VAR13); 4'b1101: VAR17=~VAR33 & ~(VAR1 ^ VAR13); 4'b1110: VAR17=1'b1; default: VAR17=1'VAR38;
endcase
assign VAR15 = VAR49 & VAR17;
assign VAR52 = VAR4 & VAR17 & (~ VAR36);
assign VAR8 = VAR3 & VAR17;
endmodule
module MODULE2(input clk,input reset,input en,input [1:0] VAR31,output reg [1:0] VAR39);
always @(posedge clk) begin
if(reset) VAR39<=0;
end
else begin
if(en) VAR39 <= VAR31;
end
end
endmodule
module MODULE3(input VAR26,input reset,input [3:0] VAR16,input [1:0] VAR21,input [5:0] VAR7,input [3:0] VAR19,input [3:0]VAR24,
output wire VAR15,output wire VAR45,output wire VAR8,output wire [1:0]VAR43,
output wire VAR25,output wire [1:0]VAR22,output wire VAR52,output wire [1:0]VAR47);
wire [1:0]VAR44;
wire VAR23,VAR12,VAR40;
wire VAR36;
wire VAR17;
MODULE4 MODULE2(VAR21,VAR7,VAR19,VAR44,VAR23,VAR12,VAR40,VAR45,VAR25,VAR22,VAR47,VAR43,VAR36);
MODULE1 MODULE3(VAR26,reset,VAR16,VAR24,VAR44,VAR23,VAR12,VAR40,VAR36,VAR17,VAR15,VAR52,VAR8);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nand2/sky130_fd_sc_hdll__nand2.pp.symbol.v
| 1,277 |
module MODULE1 (
input VAR4 ,
input VAR5 ,
output VAR6 ,
input VAR7 ,
input VAR1,
input VAR2,
input VAR3
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.pp.blackbox.v
| 1,309 |
module MODULE1 (
VAR1 ,
VAR4 ,
VAR5,
VAR2,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR3 ;
endmodule
|
apache-2.0
|
liuyenting/CA-Project
|
src/L1_Cache_Controller_ta.v
| 5,174 |
module MODULE1
(
input VAR21,
input VAR40,
input [256-1:0] VAR42,
input VAR38,
output [256-1:0] VAR43,
output [32-1:0] VAR28,
output VAR27,
output VAR35,
input [32-1:0] VAR47,
input [32-1:0] VAR23,
input VAR49,
input VAR15,
output [32-1:0] VAR22,
output VAR12
);
integer VAR31;
wire [4:0] VAR8;
wire VAR1;
wire [23:0] VAR50;
wire [255:0] VAR32;
wire VAR16;
wire [23:0] VAR37;
wire [255:0] VAR4;
wire VAR34;
wire VAR26;
parameter VAR36 = 3'h0,
VAR2 = 3'h1,
VAR18 = 3'h2,
VAR29 = 3'h3,
VAR11 = 3'h4;
reg [2:0] state;
reg VAR5;
reg VAR9;
reg VAR6;
wire VAR19;
reg VAR30;
wire [4:0] VAR20;
wire [4:0] VAR14;
wire [21:0] VAR3;
wire [255:0] VAR25;
wire [21:0] VAR10;
wire VAR41;
reg [255:0] VAR7;
wire VAR13;
wire VAR48;
reg [31:0] VAR44;
assign VAR48 = VAR49 | VAR15;
assign VAR20 = VAR23[4:0];
assign VAR14 = VAR23[9:5];
assign VAR3 = VAR23[31:10];
assign VAR12 = ~VAR41 & VAR48;
assign VAR22 = VAR44;
assign VAR34 = VAR37[23];
assign VAR26 = VAR37[22];
assign VAR10 = VAR37[21:0];
assign VAR8 = VAR14;
assign VAR1 = VAR48;
assign VAR16 = VAR6 | VAR13;
assign VAR50 = {1'b1, VAR19, VAR3};
assign VAR32 = (VAR41) ? VAR7 : VAR42;
assign VAR27 = VAR5;
assign VAR28 = (VAR30) ? {VAR10, VAR14, 5'b0} : {VAR3, VAR14, 5'b0};
assign VAR43 = VAR4;
assign VAR35 = VAR9;
assign VAR13 = VAR41 & VAR15;
assign VAR19 = VAR13;
assign VAR41 = ((VAR10 == VAR3) && VAR34 ) ? 1'b1 : 1'b0;
assign VAR25 = VAR4;
always @ (VAR20 or VAR25) begin
if(VAR41) begin
for(VAR31 = 0 ; VAR31 < 32 ; VAR31 = VAR31+1)
VAR44[VAR31] = VAR25[VAR31 + VAR20[4:2] * 32];
end
end
always @ (VAR20 or VAR25 or VAR47) begin
VAR7 = VAR25;
for (VAR31 = 0 ; VAR31 < 32 ; VAR31 = VAR31+1)
VAR7[VAR31 + VAR20[4:2] * 32] <= VAR47[VAR31];
end
always @ (posedge VAR21 or negedge VAR40) begin
if(~VAR40) begin
state <= VAR36;
VAR5 <= 1'b0;
VAR9 <= 1'b0;
VAR6 <= 1'b0;
VAR30 <= 1'b0;
end
else begin
case(state)
VAR36: begin
if(VAR48 && !VAR41) begin state <= VAR11;
end
else begin
state <= VAR36;
end
end
VAR11: begin
if(VAR26) begin VAR5 <= 1'b1;
VAR9 <= 1'b1;
VAR6 <= 1'b0;
VAR30 <= 1'b1;
state <= VAR29;
end
else begin VAR5 <= 1'b1;
VAR9 <= 1'b0;
VAR6 <= 1'b0;
VAR30 <= 1'b0;
state <= VAR2;
end
end
VAR2: begin
if(VAR38) begin VAR5 <= 1'b1;
VAR9 <= 1'b0;
VAR6 <= 1'b1;
VAR30 <= 1'b0;
state <= VAR18;
end
else begin
state <= VAR2;
end
end
VAR18: begin VAR5 <= 1'b0;
VAR9 <= 1'b0;
VAR6 <= 1'b0;
VAR30 <= 1'b0;
state <= VAR36;
end
VAR29: begin
if(VAR38) begin VAR5 <= 1'b1;
VAR9 <= 1'b0;
VAR6 <= 1'b0;
VAR30 <= 1'b0;
state <= VAR2;
end
else begin
state <= VAR29;
end
end
endcase
end
end
VAR39 VAR39
(
.VAR21 (VAR21),
.VAR45 (VAR8),
.VAR33 (VAR50),
.VAR17 (VAR1),
.VAR46 (VAR16),
.VAR24 (VAR37)
);
VAR51 VAR51
(
.VAR21 (VAR21),
.VAR45 (VAR8),
.VAR33 (VAR32),
.VAR17 (VAR1),
.VAR46 (VAR16),
.VAR24 (VAR4)
);
endmodule
|
gpl-3.0
|
osrf/wandrr
|
firmware/motor_controller/fpga/usb_tx_ack.v
| 1,084 |
module MODULE1
(input VAR18,
input VAR27,
output [7:0] VAR25,
output VAR21);
localparam VAR4 = 3'd0;
localparam VAR26 = 3'd1;
localparam VAR3 = 3'd2;
localparam VAR2=4, VAR12=2;
reg [VAR12+VAR2-1:0] VAR8;
wire [VAR2-1:0] state;
wire [VAR2-1:0] VAR16 = VAR8[VAR2+VAR12-1:VAR12];
VAR11 #(VAR2) VAR5
(.VAR18(VAR18), .rst(1'b0), .en(1'b1), .VAR6(VAR16), .VAR15(state));
wire VAR7;
wire [7:0] VAR20;
VAR1 #(.VAR19(8), .VAR13(1)) VAR22
(.VAR6({VAR14, 8'b10000000}), .sel(VAR7), .VAR23(VAR20));
wire [7:0] VAR24 = VAR10 ? VAR20 : 8'h0;
always @* begin
case (state)
VAR4:
if (VAR27) VAR8 = { VAR26 , 2'b01 };
end
else VAR8 = { VAR4 , 2'b00 };
VAR26: VAR8 = { VAR3 , 2'b11 };
VAR3: VAR8 = { VAR4 , 2'b00 };
default: VAR8 = { VAR4 , 2'b00 };
endcase
end
wire VAR10 = VAR8[0];
assign VAR7 = VAR8[1];
d1 #(8) VAR17 (.VAR18(VAR18), .VAR6(VAR24 ), .VAR15(VAR25 ));
d1 VAR9(.VAR18(VAR18), .VAR6(VAR10), .VAR15(VAR21));
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/altera_project/dpram_32_32x16_be/dpram_32_32x16_be.v
| 9,175 |
module MODULE1 (
VAR30,
VAR38,
VAR35,
VAR23,
VAR46,
VAR11,
VAR20,
VAR2);
input [31:0] VAR30;
input VAR38;
input [3:0] VAR35;
input [3:0] VAR23;
input [3:0] VAR46;
input VAR11;
input VAR20;
output [31:0] VAR2;
wire [31:0] VAR33;
wire [31:0] VAR2 = VAR33[31:0];
VAR45 VAR7 (
.VAR9 (VAR38),
.VAR32 (VAR11),
.VAR4 (VAR20),
.VAR46 (VAR46),
.VAR5 (VAR35),
.VAR8 (VAR23),
.VAR6 (VAR30),
.VAR3 (VAR33)
,
.VAR51 (),
.VAR54 (),
.VAR14 (),
.VAR25 (),
.VAR52 (),
.VAR47 (),
.VAR26 (),
.VAR29 (),
.VAR21 (),
.VAR1 (),
.VAR12 ()
);
VAR7.VAR40 = "VAR53 VAR50",
VAR7.VAR39 = "VAR15",
VAR7.VAR17 = 32,
VAR7.VAR48 = 4,
VAR7.VAR34 = 16,
VAR7.VAR27 = 32,
VAR7.VAR22 = 4,
VAR7.VAR42 = 16,
VAR7.VAR31 = "VAR45",
VAR7.VAR49 = 4,
VAR7.VAR36 = 8,
VAR7.VAR16 = "VAR41",
VAR7.VAR18 = "VAR10",
VAR7.VAR55 = "VAR19",
VAR7.VAR44 = "VAR28",
VAR7.VAR43 = "VAR28",
VAR7.VAR13 = "VAR28",
VAR7.VAR24 = "VAR37";
endmodule
|
gpl-3.0
|
BilkentCompGen/GateKeeper
|
FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_engine_classic.v
| 36,865 |
module MODULE4
parameter VAR94 = 128,
parameter VAR102 = 1,
parameter VAR133 = 1,
parameter VAR115 = 256,
parameter VAR114 = "VAR92"
)
(
input VAR171,
input VAR135,
input [VAR3-1:0] VAR112,
input VAR45,
output [VAR94-1:0] VAR151,
output VAR9,
output VAR119,
output [VAR39(VAR94/32)-1:0] VAR100,
output VAR116,
output [VAR39(VAR94/32)-1:0] VAR30,
input VAR139,
input [VAR94-1:0] VAR6,
input VAR63,
input [VAR39(VAR94/32)-1:0] VAR121,
input VAR168,
input [VAR39(VAR94/32)-1:0] VAR73,
output VAR32,
input VAR148,
input [VAR99-1:0] VAR130,
input [VAR65-1:0] VAR170,
input [VAR155-1:0] VAR163,
input [VAR164-1:0] VAR74,
input [VAR16-1:0] VAR123,
input [VAR75-1:0] VAR27,
input [VAR79-1:0] VAR67,
input [VAR33-1:0] VAR134,
input [VAR159-1:0] VAR98,
input [VAR167-1:0] VAR80,
input VAR41,
output VAR20,
output VAR61,
input VAR70,
input [VAR94-1:0] VAR14,
input VAR57,
input [VAR39(VAR94/32)-1:0] VAR149,
input VAR55,
input [VAR39(VAR94/32)-1:0] VAR54,
output VAR146,
input VAR152,
input [VAR99-1:0] VAR77,
input [VAR65-1:0] VAR53,
input [VAR122-1:0] VAR89,
input [VAR16-1:0] VAR56,
input [VAR79-1:0] VAR93,
input [VAR159-1:0] VAR71,
input [VAR167-1:0] VAR129,
input [VAR164-1:0] VAR62,
input VAR138,
output VAR161,
output VAR103
);
localparam VAR23 = "VAR69";
localparam VAR153 = 10;
wire [VAR94-1:0] VAR6;
wire [VAR94-1:0] VAR14;
wire [VAR94-1:0] VAR140;
wire VAR109;
wire [VAR39(VAR94/32)-1:0] VAR7;
wire VAR128;
wire VAR44;
wire [VAR39(VAR94/32)-1:0] VAR26;
wire VAR126;
wire [VAR94-1:0] VAR147;
wire VAR107;
wire [VAR39(VAR94/32)-1:0] VAR104;
wire VAR95;
wire VAR88;
wire [VAR39(VAR94/32)-1:0] VAR60;
wire VAR5;
reg VAR142;
reg [VAR157-1:0] VAR18;
reg VAR136;
reg VAR83;
reg VAR40;
assign VAR61 = VAR40;
assign VAR103 = VAR83;
always @(posedge VAR171) begin
if(VAR119) begin
VAR18 <= VAR151[VAR169];
end
VAR136 <= VAR116;
VAR142 <= VAR9 & VAR45;
VAR40 <= VAR136 & VAR142 & (VAR18 == VAR106);
VAR83 <= VAR136 & VAR142 & (VAR18 == VAR66);
end
generate
if(VAR114 == "VAR111") begin : VAR108
if(VAR94 == 128) begin : VAR90
assign VAR6 = {VAR6[103:96], VAR6[111:104], VAR6[119:112], VAR6[127:120],
VAR6[71:64], VAR6[79:72], VAR6[87:80], VAR6[95:88],
VAR6[39:32], VAR6[47:40], VAR6[55:48], VAR6[63:56],
VAR6[07:00], VAR6[15:08], VAR6[23:16], VAR6[31:24]};
assign VAR14 = {VAR14[103:96], VAR14[111:104], VAR14[119:112], VAR14[127:120],
VAR14[71:64], VAR14[79:72], VAR14[87:80], VAR14[95:88],
VAR14[39:32], VAR14[47:40], VAR14[55:48], VAR14[63:56],
VAR14[07:00], VAR14[15:08], VAR14[23:16], VAR14[31:24]};
end else if(VAR94 == 64) begin: VAR144
assign VAR6 = {VAR6[39:32], VAR6[47:40], VAR6[55:48], VAR6[63:56],
VAR6[07:00], VAR6[15:08], VAR6[23:16], VAR6[31:24]};
assign VAR14 = {VAR14[39:32], VAR14[47:40], VAR14[55:48], VAR14[63:56],
VAR14[07:00], VAR14[15:08], VAR14[23:16], VAR14[31:24]};
end else if(VAR94 == 32) begin: VAR150
assign VAR6 = {VAR6[07:00], VAR6[15:08], VAR6[23:16], VAR6[31:24]};
assign VAR14 = {VAR14[07:00], VAR14[15:08], VAR14[23:16], VAR14[31:24]};
end
end else begin : VAR110
assign VAR6 = VAR6;
assign VAR14 = VAR14;
end
endgenerate
VAR22
.VAR133 (0),
.VAR94 (VAR94),
.VAR102 (VAR102),
.VAR115 (VAR115),
.VAR153 (VAR153),
.VAR114 (VAR114))
VAR162
(
.VAR58 (VAR140[VAR94-1:0] ),
.VAR143 (VAR126),
.VAR4 (VAR44),
.VAR1 (VAR26[VAR39(VAR94/32)-1:0]),
.VAR87 (VAR109),
.VAR91 (VAR7[VAR39(VAR94/32)-1:0]),
.VAR47 (VAR128),
.VAR6 (VAR6[VAR94-1:0]),
.VAR32 (VAR32),
.VAR20 (VAR20),
.VAR171 (VAR171),
.VAR135 (VAR135),
.VAR112 (VAR112[VAR3-1:0]),
.VAR139 (VAR139),
.VAR63 (VAR63),
.VAR121 (VAR121[VAR39(VAR94/32)-1:0]),
.VAR168 (VAR168),
.VAR73 (VAR73[VAR39(VAR94/32)-1:0]),
.VAR148 (VAR148),
.VAR130 (VAR130[VAR99-1:0]),
.VAR170 (VAR170[VAR65-1:0]),
.VAR163 (VAR163[VAR155-1:0]),
.VAR74 (VAR74[VAR164-1:0]),
.VAR123 (VAR123[VAR16-1:0]),
.VAR27 (VAR27[VAR75-1:0]),
.VAR67 (VAR67[VAR79-1:0]),
.VAR134 (VAR134[VAR33-1:0]),
.VAR98 (VAR98[VAR159-1:0]),
.VAR80 (VAR80[VAR167-1:0]),
.VAR41 (VAR41));
VAR10
.VAR133 (0),
.VAR94 (VAR94),
.VAR102 (VAR102),
.VAR115 (VAR115),
.VAR153 (VAR153),
.VAR114 (VAR114))
VAR35
(
.VAR120 (VAR147[VAR94-1:0]),
.VAR37 (VAR5),
.VAR76 (VAR88),
.VAR124 (VAR60[VAR39(VAR94/32)-1:0]),
.VAR166 (VAR107),
.VAR127 (VAR104[VAR39(VAR94/32)-1:0]),
.VAR14 (VAR14[VAR94-1:0]),
.VAR125 (VAR95),
.VAR146 (VAR146),
.VAR161 (VAR161),
.VAR171 (VAR171),
.VAR135 (VAR135),
.VAR112 (VAR112[VAR3-1:0]),
.VAR70 (VAR70),
.VAR57 (VAR57),
.VAR149 (VAR149[VAR39(VAR94/32)-1:0]),
.VAR55 (VAR55),
.VAR54 (VAR54[VAR39(VAR94/32)-1:0]),
.VAR152 (VAR152),
.VAR77 (VAR77[VAR99-1:0]),
.VAR53 (VAR53[VAR65-1:0]),
.VAR89 (VAR89[VAR122-1:0]),
.VAR56 (VAR56[VAR16-1:0]),
.VAR93 (VAR93[VAR79-1:0]),
.VAR71 (VAR71[VAR159-1:0]),
.VAR129 (VAR129[VAR167-1:0]),
.VAR62 (VAR62[VAR164-1:0]),
.VAR138 (VAR138));
MODULE3
.VAR102 (0),
.VAR94 (VAR94),
.VAR133 (VAR133),
.VAR23 (VAR23),
.VAR114 (VAR114))
VAR145
(
.VAR58 (VAR140[VAR94-1:0]),
.VAR143 (VAR126),
.VAR4 (VAR44),
.VAR1 (VAR26[VAR39(VAR94/32)-1:0]),
.VAR87 (VAR109),
.VAR91 (VAR7[VAR39(VAR94/32)-1:0]),
.VAR120 (VAR147[VAR94-1:0]),
.VAR37 (VAR5),
.VAR76 (VAR88),
.VAR124 (VAR60[VAR39(VAR94/32)-1:0]),
.VAR166 (VAR107),
.VAR127 (VAR104[VAR39(VAR94/32)-1:0]),
.VAR47 (VAR128),
.VAR125 (VAR95),
.VAR151 (VAR151[VAR94-1:0]),
.VAR9 (VAR9),
.VAR119 (VAR119),
.VAR100 (VAR100[VAR39(VAR94/32)-1:0]),
.VAR116 (VAR116),
.VAR30 (VAR30[VAR39(VAR94/32)-1:0]),
.VAR171 (VAR171),
.VAR135 (VAR135),
.VAR45 (VAR45));
endmodule
module MODULE3
parameter VAR94 = 128,
parameter VAR102 = 1,
parameter VAR133 = 1,
parameter VAR23 = "VAR69",
parameter VAR114 = "VAR92"
)
(
input VAR171,
input VAR135,
input [VAR94-1:0] VAR58,
output VAR47,
input VAR143,
input VAR4,
input [VAR39(VAR94/32)-1:0] VAR1,
input VAR87,
input [VAR39(VAR94/32)-1:0] VAR91,
input [VAR94-1:0] VAR120,
input VAR37,
input VAR76,
input [VAR39(VAR94/32)-1:0] VAR124,
input VAR166,
input [VAR39(VAR94/32)-1:0] VAR127,
output VAR125,
input VAR45,
output [VAR94-1:0] VAR151,
output VAR9,
output VAR119,
output [VAR39(VAR94/32)-1:0] VAR100,
output VAR116,
output [VAR39(VAR94/32)-1:0] VAR30
);
localparam VAR21 = (VAR94 + 2 * (VAR39(VAR94/32) + 1));
localparam VAR118 = 1;
localparam VAR50 = 2;
wire [VAR94-1:0] VAR140;
wire VAR128;
wire VAR126;
wire VAR44;
wire [VAR39(VAR94/32)-1:0] VAR26;
wire VAR109;
wire [VAR39(VAR94/32)-1:0] VAR7;
wire [VAR94-1:0] VAR147;
wire VAR95;
wire VAR5;
wire VAR88;
wire [VAR39(VAR94/32)-1:0] VAR60;
wire VAR107;
wire [VAR39(VAR94/32)-1:0] VAR104;
wire [VAR94-1:0] VAR24;
wire VAR72;
wire VAR158;
wire VAR52;
wire [VAR39(VAR94/32)-1:0] VAR156;
wire VAR46;
wire [VAR39(VAR94/32)-1:0] VAR78;
VAR97
.VAR68 (VAR102?1:0),
.VAR36 (0),
.VAR21 (VAR21))
VAR38
(
.VAR84 (VAR125),
.VAR141 ({VAR147, VAR88, VAR60,
VAR107, VAR104}),
.VAR113 (VAR5),
.VAR171 (VAR171),
.VAR135 (VAR135),
.VAR160 ({VAR120,
VAR76, VAR124,
VAR166, VAR127}),
.VAR8 (VAR37),
.VAR96 (VAR95));
VAR97
.VAR68 (VAR102?1:0),
.VAR36 (0),
.VAR21 (VAR21))
VAR15
(
.VAR84 (VAR47),
.VAR141 ({VAR140, VAR44, VAR26,
VAR109, VAR7}),
.VAR113 (VAR126),
.VAR160 ({VAR58,
VAR4, VAR1,
VAR87, VAR91}),
.VAR8 (VAR143),
.VAR96 (VAR128),
.VAR171 (VAR171),
.VAR135 (VAR135));
MODULE2
.VAR118 (VAR118),
.VAR50 (VAR50))
VAR117
(
.VAR125 (VAR95),
.VAR47 (VAR128),
.VAR45 (VAR72),
.VAR143 (VAR126),
.VAR4 (VAR44),
.VAR87 (VAR109),
.VAR37 (VAR5),
.VAR76 (VAR88),
.VAR166 (VAR107),
.VAR171 (VAR171),
.VAR135 (VAR135));
MODULE1
.VAR94 (VAR94),
.VAR23 (VAR23),
.VAR21 (VAR21))
VAR105
(
.VAR47 (VAR128),
.VAR125 (VAR95),
.VAR151 (VAR24),
.VAR9 (VAR158),
.VAR119 (VAR52),
.VAR100 (VAR156),
.VAR116 (VAR46),
.VAR30 (VAR78),
.VAR58 (VAR140),
.VAR143 (VAR126),
.VAR4 (VAR44),
.VAR1 (VAR26),
.VAR87 (VAR109),
.VAR91 (VAR7),
.VAR120 (VAR147),
.VAR37 (VAR5),
.VAR76 (VAR88),
.VAR124 (VAR60),
.VAR166 (VAR107),
.VAR127 (VAR104),
.VAR171 (VAR171),
.VAR135 (VAR135));
VAR97
.VAR68 (VAR133?1:0),
.VAR36 (0),
.VAR21 (VAR21))
VAR43
(
.VAR84 (VAR72),
.VAR141 ({VAR151,
VAR119, VAR100,
VAR116, VAR30}),
.VAR113 (VAR9),
.VAR160 ({VAR24, VAR52, VAR156,
VAR46, VAR78}),
.VAR8 (VAR158),
.VAR96 (VAR45),
.VAR171 (VAR171),
.VAR135 (VAR135));
endmodule
module MODULE2
parameter VAR118 = 1,
parameter VAR50 = 1)
(
input VAR171,
input VAR135,
input VAR45,
output VAR125,
input VAR37,
input VAR76,
input VAR166,
output VAR47,
input VAR143,
input VAR4,
input VAR87
);
localparam VAR11 = 0; localparam VAR42 = 1; localparam VAR28 = 2;
localparam VAR101 = (VAR42 >= VAR28)? VAR42: VAR28;
localparam VAR64 = VAR28;
wire VAR86;
wire VAR59;
wire VAR82;
wire VAR48;
wire VAR165;
wire VAR34;
reg [VAR39(VAR64):0] VAR49,VAR49;
reg VAR25,VAR25; reg VAR85,VAR85;
reg VAR19,VAR19; reg VAR137,VAR137;
reg [VAR39(VAR118)-1:0] VAR81,VAR81; reg [VAR39(VAR50)-1:0] VAR17,VAR17;
assign VAR125 = VAR86 & VAR45; assign VAR59 = VAR76 & VAR37;
assign VAR82 = VAR166 & VAR125;
assign VAR86 = (VAR49 == VAR42);
assign VAR47 = VAR48 & VAR45; assign VAR165 = VAR4 & VAR143;
assign VAR34 = VAR87 & VAR47;
assign VAR48 = (VAR49 == VAR28);
always @ begin
VAR17 = VAR17;
VAR19 = VAR19;
VAR25 = VAR25;
if(VAR48) begin
VAR17 = 0;
end else if(VAR59 & VAR86 & ~VAR25) begin
VAR17 = VAR17 + 1;
end
if(VAR59 & VAR86) begin
VAR19 = 1;
end else if(VAR82) begin
VAR19 = 0;
end
if(VAR48 | VAR135) begin
VAR25 = 0;
end else if(VAR59 & VAR86) begin
VAR25 = (VAR17 == (VAR50 - 1));
end
end
always @(posedge VAR171) begin
if(VAR135) begin
VAR17 <= 0;
VAR19 <= 0;
VAR25 <= 0;
end else begin
VAR17 <= VAR17;
VAR19 <= VAR19;
VAR25 <= VAR25;
end
end
always @(*) begin
VAR49 = VAR49;
case(VAR49)
VAR42: begin
if((VAR25 & VAR82 & VAR165) | (~VAR19 & ~VAR59 & VAR165)) begin
VAR49 = VAR28;
end
end
VAR28: begin
if((VAR85 & VAR34 & VAR59) | (~VAR137 & ~VAR165 & VAR59)) begin
VAR49 = VAR42;
end
end
default: begin
end
endcase
end
always @(posedge VAR171) begin
if(VAR135) begin
VAR49 <= VAR101;
end else begin
VAR49 <= VAR49;
end
end
endmodule
module MODULE1
parameter VAR94 = 10'd128,
parameter VAR23 = "VAR69",
parameter VAR21 = (VAR94 + 2 * (VAR39(VAR94/32) + 1))
)
(
input VAR171,
input VAR135,
input VAR47,
input VAR125,
input [VAR94-1:0] VAR58,
input VAR143,
input VAR4,
input [VAR39(VAR94/32)-1:0] VAR1,
input VAR87,
input [VAR39(VAR94/32)-1:0] VAR91,
input [VAR94-1:0] VAR120,
input VAR37,
input VAR76,
input [VAR39(VAR94/32)-1:0] VAR124,
input VAR166,
input [VAR39(VAR94/32)-1:0] VAR127,
output [VAR94-1:0] VAR151,
output VAR9,
output VAR119,
output [VAR39(VAR94/32)-1:0] VAR100,
output VAR116,
output [VAR39(VAR94/32)-1:0] VAR30
);
localparam VAR29 = VAR94 + 3 + 2*VAR39(VAR94/32);
wire [2*VAR29-1:0] VAR132;
assign VAR132 = {{VAR120,VAR37,VAR76,
VAR124,VAR166,VAR127},
{VAR58,VAR143,VAR4,
VAR1,VAR87,VAR91}};
mux
.VAR51 (2),
.VAR31 (1),
.VAR21 (VAR29),
.VAR23 ("VAR2")
)
VAR13
(
.VAR131 ({VAR151,VAR9,VAR119,
VAR100,VAR116,
VAR30}),
.VAR154 (VAR132),
.VAR12 (VAR125)
);
endmodule
|
gpl-3.0
|
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v
| 22,799 |
module MODULE1 #
(
parameter VAR28 = 100, parameter VAR22 = "8", parameter VAR104 = 2, parameter VAR57 = 5, parameter VAR85 = 5, parameter VAR43 = 0, parameter VAR56 = 4, parameter VAR79 = 2, parameter VAR19 = 30, parameter VAR35 = 8, parameter VAR80 = 4, parameter VAR49 = 4, parameter VAR75 = 20, parameter VAR55 = 16, parameter VAR13 = 2, parameter VAR41 = 4, parameter VAR99 = 39 )
(
output VAR81,
output wire VAR95,
output reg VAR7,
output reg VAR29,
output reg VAR48,
input clk,
input rst,
input VAR21,
input VAR73,
input [VAR55-1:0] VAR58,
input VAR84,
input VAR4,
input VAR87,
input VAR77,
input VAR65,
input [VAR13-1:0] VAR96,
input VAR59,
input VAR27,
input VAR51,
input [(VAR41*VAR56)-1:0] VAR18,
input VAR91,
input [VAR56-1:0] VAR17,
input [VAR56-1:0] VAR52,
input [VAR55-1:0] VAR38,
input [VAR55-1:0] VAR47
);
localparam VAR36 = VAR80 -
(
(VAR79 == 1) ? 2 :
(VAR79 == 2) ? 4 :
8
);
localparam VAR82 =
(VAR79 == 1) ? VAR36 :
(VAR79 == 2) ? ((VAR36/2)+(VAR36%2)) :
((VAR36/4)+((VAR36%4) ? 1 : 0));
localparam VAR105 = VAR9(VAR82 + 1);
reg VAR70;
integer VAR8;
function integer VAR9 (input integer VAR6);
begin
VAR6 = VAR6 - 1;
for (VAR9 = 1; VAR6 > 1; VAR9 = VAR9 + 1)
VAR6 = VAR6 >> 1;
end
endfunction
always @(VAR58 or VAR52) begin
VAR70 = 1'b0;
for (VAR8 = 0; VAR8 < VAR56; VAR8 = VAR8 + 1)
VAR70 =
VAR70 || (VAR52[VAR8] && VAR58[(VAR8*VAR41)+VAR43]);
end
reg VAR94 = 1'b0;
generate
if (VAR36 > 0 && VAR105 > 1) begin :VAR67
reg[VAR105-1:0] VAR40;
reg[VAR105-1:0] VAR76;
always @(VAR70 or VAR76 or rst) begin
VAR40 = VAR76;
if (rst) VAR40 = {VAR105{1'b0}};
end
else
if (VAR70)
VAR40 = VAR82[0+:VAR105];
end
else if (|VAR76) VAR40 =
VAR76 - {{VAR105-1{1'b0}}, 1'b1};
end
always @(VAR40) VAR94 = |VAR40;
end else if (VAR36 > 0) begin :VAR71
reg[VAR105-1:0] VAR40;
reg[VAR105-1:0] VAR76;
always @(VAR70 or VAR76 or rst) begin
VAR40 = VAR76;
if (rst) VAR40 = {VAR105{1'b0}};
end
else
if (VAR70)
VAR40 = VAR82[0+:VAR105];
end
else if (|VAR76) VAR40 =
VAR76 - {1'b1};
end
always @(VAR40) VAR94 = |VAR40;
end endgenerate
localparam VAR68 = (VAR79 == 1)
? VAR19
: (VAR79 == 2) ? ((VAR19/2) + (VAR19%2)) :
((VAR19/4) + ((VAR19%4) ? 1 : 0));
generate
begin : VAR64
wire VAR109;
wire [4:0] VAR107 = VAR68[4:0] - 5'd3;
VAR66 #(.VAR72(32'h00000000) ) VAR30
(.VAR97(VAR109), .VAR88(), .VAR2(VAR107), .VAR11(1'b1), .VAR37(clk), .VAR69(VAR70) );
reg [2:0] VAR93;
reg [2:0] VAR1;
reg VAR63;
always @(VAR109 or VAR70 or VAR94
or VAR1 or rst) begin
if (rst) VAR93 = 3'b0;
end
else begin
VAR93 = VAR1;
if (VAR70) VAR93 = VAR1 + 3'b1;
if (VAR109) VAR93 = VAR93 - 3'b1;
end
VAR63 = (VAR93 == 3'h4) || VAR94;
end
end endgenerate
localparam VAR89 = 1;
localparam VAR42 = 2;
localparam VAR103 = VAR85 + (VAR22 == "4" ? 2 : 4) + VAR49;
localparam VAR90 = (VAR79 == 1)
? VAR103 :
(VAR79 == 2)
? ((VAR103 / 2) + (VAR103 % 2)) :
((VAR103 / 4) + ((VAR103 % 4) ? 1 :0));
localparam VAR39 = VAR9(VAR90);
generate
begin : VAR83
reg VAR46;
always @(VAR17 or VAR47) begin
VAR46 = 1'b0;
for (VAR8 = 0; VAR8 < VAR56; VAR8 = VAR8 + 1)
VAR46 =
VAR46 || (VAR17[VAR8] && VAR47[(VAR8*VAR41)+VAR43]);
end
reg [VAR39-1:0] VAR12;
reg [VAR39-1:0] VAR45;
always @(rst or VAR46 or VAR12)
if (rst) VAR45 = {VAR39{1'b0}};
end
else begin
VAR45 = VAR12;
if (VAR46) VAR45 =
VAR90[VAR39-1:0] - VAR89[VAR39-1:0];
end
else if (|VAR12) VAR45 = VAR12 - VAR89[VAR39-1:0];
end
wire VAR23 = |VAR45;
always @(VAR23) VAR29 = VAR23;
end
endgenerate
localparam VAR92 = VAR57 + (VAR22 == "4" ? 2 : 4) + VAR104 - VAR85;
localparam VAR60 = (VAR79 == 1)
? VAR92 :
(VAR79 == 2)
? ((VAR92 / 2) + (VAR92 % 2)) :
((VAR92 / 4) + ((VAR92 % 4) ? 1 :0));
localparam VAR61 = VAR9(VAR60);
generate
begin : VAR98
reg VAR14;
always @(VAR17 or VAR38) begin
VAR14 = 1'b0;
for (VAR8 = 0; VAR8 < VAR56; VAR8 = VAR8 + 1)
VAR14 =
VAR14 || (VAR17[VAR8] && VAR38[(VAR8*VAR41)+VAR43]);
end
reg [VAR61-1:0] VAR108;
reg [VAR61-1:0] VAR101;
always @(rst or VAR4 or VAR17 or VAR108)
if (rst) VAR101 = {VAR61{1'b0}};
end
else begin
VAR101 = VAR108;
if (VAR4 && |VAR17) VAR101 =
VAR60[VAR61-1:0] - VAR89[VAR61-1:0];
end
else if (|VAR108) VAR101 = VAR108 - VAR89[VAR61-1:0];
end
wire VAR53 = |VAR101;
always @(VAR53) VAR48 = VAR53;
end
endgenerate
localparam VAR102 = VAR9(VAR35 + 1);
generate begin : VAR100
reg VAR20;
always @(VAR18) begin
VAR20 = 1'b0;
for (VAR8=0; VAR8 < VAR56; VAR8=VAR8+1)
VAR20 = VAR20 || VAR18[(VAR8*VAR41)+VAR43];
end
wire VAR25 =
VAR77 && ~VAR59 && ~VAR27 && ~VAR51 &&
(VAR96 == VAR43[VAR13-1:0]);
reg [VAR102-1:0] VAR32;
reg [VAR102-1:0] VAR44;
always @(VAR73 or VAR87 or VAR25
or VAR32 or VAR91)
if (~VAR87)
if (VAR99 == 0)
VAR44 = VAR35[0+:VAR102];
end
else VAR44 = {VAR102{1'b0}};
else
case ({VAR25, VAR91, VAR73})
3'b000, 3'b110, 3'b101, 3'b111 : VAR44 = VAR32;
3'b010, 3'b001, 3'b011 : VAR44 =
(|VAR32)?
VAR32 - VAR89[0+:VAR102]:
VAR32;
3'b100 : VAR44 =
VAR32 + VAR89[0+:VAR102];
VAR50: assert property (@(posedge clk)
(rst || (VAR32 <= VAR35)));
VAR86: assert property (@(posedge clk)
(rst || ~(~|VAR32 && ~VAR25 && VAR91)));
VAR24: cover property (@(posedge clk)
(rst && ~|VAR44 && (VAR32 ==
VAR89[0+:VAR102])));
VAR10: cover property (@(posedge clk)
(rst && (VAR32 ==
VAR35[0+:VAR102])));
assign VAR95 = VAR87 &&
(~|VAR32 ||
((VAR32 != VAR35[0+:VAR102]) && ~VAR20));
end
endgenerate
localparam VAR26 = VAR9(VAR75 + 1);
generate begin : VAR78
if ( VAR75 != 0 ) begin reg VAR14;
always @(VAR38 or VAR17) begin
VAR14 = 1'b0;
for (VAR8 = 0; VAR8 < VAR56; VAR8 = VAR8 + 1)
VAR14 =
VAR14 || (VAR17[VAR8] && VAR38[(VAR8*VAR41)+VAR43]);
end
reg VAR33;
reg VAR34;
wire VAR31 = VAR14 &&
(((VAR79 == 4) && VAR33) ||
((VAR79 != 4) && VAR34));
reg VAR106;
reg VAR54;
always @(VAR84 or VAR54) begin
VAR106 = VAR54;
if (VAR84)
VAR106 = VAR54 + 1'b1;
end
always @(posedge clk) begin
end
end
reg [VAR26-1:0] VAR16;
reg [VAR26-1:0] VAR3;
wire VAR74 = VAR65 &&
(VAR16 == VAR89[0+:VAR26]);
always @(VAR87 or VAR65
or VAR16 or VAR31) begin
VAR3 = VAR16;
if (~VAR87)
VAR3 = VAR75[0+:VAR26];
end
else if (VAR31 || VAR74)
VAR3 =
VAR75[0+:VAR26];
end
else if (|VAR16 && VAR65)
VAR3 =
VAR16 - VAR89[0+:VAR26];
end
reg VAR62;
wire VAR15 = ~rst &&
((VAR21 && VAR87) ||
((VAR75 != 0) && ~VAR87) ||
(~((VAR31) || (VAR84 && VAR54)) &&
(VAR62 || VAR74)));
always @(posedge clk) VAR62 <=
VAR5: cover property (@(posedge clk)
(rst && (VAR62 && VAR14)));
assign VAR81 = VAR87 && VAR62;
end else
assign VAR81 = 1'b0;
end
endgenerate
endmodule
|
mit
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_SCC_PO_reset.v
| 4,228 |
module MODULE1
(
parameter VAR5 = 4
)
(
VAR11,
VAR14 ,
VAR12 ,
VAR10 ,
VAR9 ,
VAR15 ,
VAR4 ,
VAR17 ,
VAR2 ,
VAR16 ,
VAR8,
VAR13
);
input VAR11 ;
input VAR14 ;
input [5:0] VAR12 ;
input [4:0] VAR10 ;
input [4:0] VAR9 ;
input VAR15 ;
output VAR4 ;
output VAR17 ;
output VAR2 ;
input [7:0] VAR16 ;
input [7:0] VAR8 ;
output [7:0] VAR13 ;
wire VAR6 ;
localparam VAR18 = 3'b000;
localparam VAR20 = 3'b001;
localparam VAR7 = 3'b011;
reg [1:0] VAR3 ;
reg [1:0] VAR1 ;
wire VAR19;
always @ (posedge VAR11)
if (VAR14)
VAR3 <= VAR18;
else
VAR3 <= VAR1;
always @ (*)
case (VAR3)
VAR18:
VAR1 <= (VAR6)?VAR20:VAR18;
VAR20:
VAR1 <= (VAR16)?VAR7:VAR20;
VAR7:
VAR1 <= (VAR2)?VAR18:VAR7;
default:
VAR1 <= VAR18;
endcase
assign VAR6 = (VAR15 && VAR10 == 5'b00101 && VAR12 == 6'b110000);
assign VAR4 = (VAR3 == VAR18);
assign VAR19 = (VAR3 == VAR20);
assign VAR17 = VAR6;
assign VAR2 = (VAR3 == VAR7) & VAR8[5];
assign VAR13 = {1'b0, 1'b0, VAR19, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
endmodule
|
gpl-3.0
|
SI-RISCV/e200_opensource
|
rtl/e203/subsys/e203_subsys_clint.v
| 3,395 |
module MODULE1(
input VAR20,
output VAR7,
input [VAR24-1:0] VAR34,
input VAR37,
input [VAR14-1:0] VAR35,
input [VAR14/8-1:0] VAR13,
output VAR15,
input VAR11,
output VAR38,
output [VAR14-1:0] VAR8,
output VAR18,
output VAR28,
input VAR25,
input VAR12,
input clk,
input VAR21
);
wire VAR31;
wire VAR33;
VAR5 # (
.VAR2(VAR30),
.VAR27(1)
) VAR22(
.VAR4 (VAR25),
.dout (VAR31),
.clk (clk ),
.VAR21 (VAR21)
);
VAR16 VAR32(
.clk (clk ),
.VAR21 (VAR21 ),
.VAR29 (VAR20),
.VAR10 (VAR7),
.VAR17 (VAR34 ),
.VAR6 (VAR37 ),
.VAR3 (VAR35),
.VAR26 (VAR15),
.VAR9 (VAR11),
.VAR19 (VAR8),
.VAR1 (VAR18),
.VAR36 (VAR28),
.VAR23 (VAR33)
);
assign VAR33 = VAR31 & (~VAR12);
assign VAR38 = 1'b0;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.v
| 2,461 |
module MODULE1 (
VAR9 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR12 ,
VAR7,
VAR8,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR12 ;
input VAR7;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR9 ,
VAR6,
VAR5,
VAR2,
VAR10,
VAR12
);
output VAR9 ;
input VAR6;
input VAR5;
input VAR2;
input VAR10;
input VAR12;
supply1 VAR7;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR4 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR12(VAR12)
);
endmodule
|
apache-2.0
|
ankitshah009/High-Radix-Adaptive-CORDIC
|
HCORDIC_Verilog/PackAdderProcess.v
| 2,681 |
module MODULE1(
input [31:0] VAR21,
input [3:0] VAR20,
input VAR3,
input [31:0] VAR24,
input [27:0] VAR10,
input [7:0] VAR27,
input VAR7,
output reg [31:0] VAR6,
output reg VAR19 = 1'b0,
output reg [31:0] VAR28,
output reg [3:0] VAR9,
output reg [7:0] VAR22
);
parameter VAR25 = 1'b0,
VAR18 = 1'b1;
wire VAR2;
wire [7:0] VAR12;
assign VAR2 = VAR24[31];
assign VAR12 = VAR24[30:23];
parameter VAR17 = 4'd0,
VAR4 = 4'd1,
VAR14 = 4'd2,
VAR8 = 4'd3,
VAR13 = 4'd4,
VAR26 = 4'd5, VAR11 = 4'd6,
VAR1 = 4'd7, VAR5 = 4'd8, VAR16 = 4'd9, VAR23 = 4'd10,
VAR15 = 4'd11;
always @ (posedge VAR7)
begin
VAR22 <= VAR27;
VAR9 <= VAR20;
VAR28 <= VAR21;
VAR19 <= 1'b0;
if (VAR3 != VAR18) begin
VAR6[22:0] <= VAR10[25:3];
VAR6[30:23] <= VAR12 + 127;
VAR6[31] <= VAR2;
if ((VAR12) == -126 && VAR10[22] == 0) begin
VAR6[30 : 23] <= 0;
end
if ((VAR12) <= -126) begin
VAR6[30 : 23] <= 0;
VAR6[22:0] <= 0;
end
if ((VAR12) > 127) begin
VAR6[22 : 0] <= 0;
VAR6[30 : 23] <= 255;
VAR6[31] <= VAR2;
end
end
else begin
VAR6 <= VAR24;
end
if (VAR20 == VAR26 || VAR20 == VAR16) begin
VAR19 <= 1'b1;
end
end
endmodule
|
apache-2.0
|
shailcoolboy/Warp-Trinity
|
PlatformSupport/Deprecated/pcores/radio_controller_v1_10_a/hdl/verilog/radio_controller_TxTiming.v
| 2,985 |
module MODULE1
(
clk,
reset,
VAR4,
VAR3,
VAR1,
VAR11,
VAR15,
VAR2,
VAR10,
VAR14,
VAR7,
VAR9,
VAR17,
VAR8
);
input clk;
input reset;
input VAR4;
input [0:5] VAR3;
input [0:3] VAR1;
input [0:3] VAR11;
input [0:7] VAR15;
input [0:7] VAR2;
input [0:7] VAR10;
input [0:7] VAR14;
output VAR7;
output VAR8;
output VAR17;
output [0:5] VAR9;
reg [0:7] VAR6;
reg [0:7] VAR5;
wire [0:6] VAR13;
reg [0:6] VAR12;
wire VAR16;
assign VAR13 = ( (VAR12 + VAR1) > VAR3) ? VAR3 : (VAR12 + VAR1);
assign VAR9 = VAR12[1:6];
assign VAR7 = (VAR5 > VAR15) || VAR15 == 8'd254;
assign VAR17 = (VAR5 > VAR10) || VAR10 == 8'd254;
assign VAR8 = (VAR5 > VAR2) || VAR2 == 8'd254;
assign VAR16 = VAR5 > VAR14;
always @( posedge clk )
begin
if(reset | ~VAR4)
VAR12 <= 0;
end
else if( VAR16 & (VAR6==1))
VAR12 <= VAR13;
end
always @( posedge clk )
begin
if(reset | ~VAR4)
VAR5 <= 0;
end
else if(VAR4 & VAR5 < 254)
VAR5 <= VAR5 + 1;
end
always @( posedge clk )
begin
if(reset | VAR6 == VAR11)
VAR6 <= 0;
end
else
VAR6 <= VAR6 + 1;
end
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/maj3/sky130_fd_sc_lp__maj3_m.v
| 2,171 |
module MODULE2 (
VAR2 ,
VAR4 ,
VAR6 ,
VAR10 ,
VAR3,
VAR5,
VAR8 ,
VAR9
);
output VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR3;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR1 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR2,
VAR4,
VAR6,
VAR10
);
output VAR2;
input VAR4;
input VAR6;
input VAR10;
supply1 VAR3;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR9 ;
VAR1 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10)
);
endmodule
|
apache-2.0
|
joaocarlos/udlx-verilog
|
fpga/rtl/42s86400.v
| 39,229 |
module MODULE1 (VAR23, VAR40, VAR80, VAR67, VAR70, VAR15, VAR18, VAR29, VAR4);
parameter VAR54 = 13;
parameter VAR95 = 8;
parameter VAR44 = 10;
parameter VAR57 = 8388608;
inout [VAR95 - 1 : 0] VAR23;
input [VAR54 - 1 : 0] VAR40;
input [1 : 0] VAR80;
input VAR67;
input VAR70;
input VAR15;
input VAR18;
input VAR29;
input VAR4;
wire [1 : 0] VAR53;
assign VAR53[0]= 1'b0;
assign VAR53[1]= 1'b0;
reg [VAR95 - 1 : 0] VAR60 [0 : VAR57];
reg [VAR95 - 1 : 0] VAR66 [0 : VAR57];
reg [VAR95 - 1 : 0] VAR34 [0 : VAR57];
reg [VAR95 - 1 : 0] VAR45 [0 : VAR57];
reg [1 : 0] VAR9 [0 : 3]; reg [VAR44 - 1 : 0] VAR89 [0 : 3]; reg [3 : 0] VAR32 [0 : 3]; reg [1 : 0] VAR20, VAR90; reg [VAR54 - 1 : 0] VAR86, VAR16, VAR31, VAR48;
reg [VAR54 - 1 : 0] VAR105;
reg [VAR95 - 1 : 0] VAR74, VAR35;
reg [VAR44 - 1 : 0] VAR92, VAR10;
reg VAR103, VAR46, VAR59, VAR81; reg VAR78, VAR39, VAR76, VAR52;
reg [1 : 0] VAR62 [0 : 3]; reg VAR100 [0 : 3]; reg VAR91 [0 : 3]; reg VAR61 [0 : 3]; reg VAR19 [0 : 3]; reg VAR94 [0 : 3]; reg VAR72 [0 : 3]; reg [1 : 0] VAR99; integer VAR93 [0 : 3]; integer VAR11 [0 : 3];
reg VAR6;
reg VAR17;
reg [1 : 0] VAR64, VAR14;
reg [VAR54 - 1 : 0] VAR79;
reg [VAR44 - 1 : 0] VAR27, VAR102;
reg VAR68, VAR43;
wire VAR65 = ~VAR15 & ~VAR18 & VAR29 & VAR4;
wire VAR87 = ~VAR15 & ~VAR18 & ~VAR29 & VAR4;
wire VAR84 = ~VAR15 & VAR18 & VAR29 & ~VAR4;
wire VAR85 = ~VAR15 & ~VAR18 & ~VAR29 & ~VAR4;
wire VAR58 = ~VAR15 & ~VAR18 & VAR29 & ~VAR4;
wire VAR98 = ~VAR15 & VAR18 & ~VAR29 & VAR4;
wire VAR3 = ~VAR15 & VAR18 & ~VAR29 & ~VAR4;
wire VAR63 = ~VAR105[2] & ~VAR105[1] & ~VAR105[0];
wire VAR56 = ~VAR105[2] & ~VAR105[1] & VAR105[0];
wire VAR83 = ~VAR105[2] & VAR105[1] & ~VAR105[0];
wire VAR37 = ~VAR105[2] & VAR105[1] & VAR105[0];
wire VAR8 = VAR105[2] & VAR105[1] & VAR105[0];
wire VAR28 = ~VAR105[6] & VAR105[5] & ~VAR105[4];
wire VAR22 = ~VAR105[6] & VAR105[5] & VAR105[4];
wire VAR73 = VAR105[9];
wire VAR5 = VAR43 & VAR6;
assign VAR23 = VAR74;
parameter VAR101 = 5.5; parameter VAR71 = 5.5;
parameter VAR1 = 2.5; parameter VAR69 = 2.0; parameter VAR55 = 49.0;
parameter VAR77 = 70.0;
parameter VAR24 = 21.0;
parameter VAR38 = 21.0;
parameter VAR97 = 14.0;
parameter VAR13 = 14.0; VAR82 VAR51;
VAR82 VAR30 [0 : 3];
VAR82 VAR104, VAR88;
VAR82 VAR25, VAR47, VAR12, VAR21;
VAR82 VAR33, VAR50, VAR42, VAR75;
VAR82 VAR96, VAR41, VAR36, VAR2;
VAR82 VAR26, VAR49, VAR7, VAR106;
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
lgpl-3.0
|
Digilent/vivado-library
|
ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2.v
| 16,052 |
module MODULE1
(VAR40,
VAR77,
VAR2,
VAR63,
VAR85,
VAR144,
VAR220,
VAR1,
VAR56,
VAR229,
VAR218,
VAR94,
VAR5,
VAR96,
VAR99,
VAR136,
VAR179,
VAR27,
VAR87,
VAR13,
VAR91,
VAR67,
VAR25,
VAR83,
VAR105,
VAR157,
VAR6,
VAR184,
VAR65,
VAR163,
VAR236,
VAR215,
VAR59,
VAR177,
VAR245,
VAR137,
VAR53,
VAR19,
VAR208,
VAR156,
VAR62,
VAR71,
VAR43,
VAR106,
VAR58,
VAR11,
VAR230,
VAR17,
VAR7,
VAR175,
VAR204,
VAR128,
VAR127,
VAR41,
VAR192,
VAR123,
VAR155,
VAR80,
VAR166,
VAR198,
VAR103,
VAR118,
VAR119,
VAR203,
VAR110,
VAR210,
VAR145,
VAR151,
VAR66,
VAR207,
VAR108,
VAR52,
VAR238,
VAR20,
VAR153,
VAR172,
VAR81,
VAR197,
VAR64,
VAR130);
input [8:0]VAR40;
output VAR77;
input VAR2;
input [8:0]VAR63;
output VAR85;
input VAR144;
input VAR220;
output [1:0]VAR1;
output VAR56;
output [31:0]VAR229;
input VAR218;
output [1:0]VAR94;
output VAR5;
input [31:0]VAR96;
output VAR99;
input [3:0]VAR136;
input VAR179;
input [6:0]VAR27;
input [2:0]VAR87;
output VAR13;
input VAR91;
input [6:0]VAR67;
input [2:0]VAR25;
output VAR83;
input VAR105;
input VAR157;
output [1:0]VAR6;
output VAR184;
output [31:0]VAR65;
input VAR163;
output [1:0]VAR236;
output VAR215;
input [31:0]VAR59;
output VAR177;
input [3:0]VAR245;
input VAR137;
input [4:0]VAR53;
output VAR19;
input VAR208;
input [4:0]VAR156;
output VAR62;
input VAR71;
input VAR43;
output [1:0]VAR106;
output VAR58;
output [31:0]VAR11;
input VAR230;
output [1:0]VAR17;
output VAR7;
input [31:0]VAR175;
output VAR204;
input [3:0]VAR128;
input VAR127;
input VAR41;
output VAR192;
output VAR123;
input VAR155;
output VAR80;
output VAR166;
input VAR198;
output VAR103;
output VAR118;
input VAR119;
output VAR203;
output VAR110;
input VAR210;
output VAR145;
output VAR151;
input VAR66;
output VAR207;
output VAR108;
input VAR52;
output VAR238;
output VAR20;
input VAR153;
output VAR172;
output VAR81;
input VAR197;
input VAR64;
output VAR130;
wire [0:0]VAR93;
wire [6:0]VAR142;
wire [2:0]VAR180;
wire VAR214;
wire VAR206;
wire [6:0]VAR152;
wire [2:0]VAR45;
wire VAR176;
wire VAR74;
wire VAR68;
wire [1:0]VAR31;
wire VAR165;
wire [31:0]VAR201;
wire VAR70;
wire [1:0]VAR22;
wire VAR193;
wire [31:0]VAR30;
wire VAR154;
wire [3:0]VAR183;
wire VAR39;
wire [8:0]VAR34;
wire VAR205;
wire VAR228;
wire [8:0]VAR109;
wire VAR159;
wire VAR188;
wire VAR171;
wire [1:0]VAR88;
wire VAR178;
wire [31:0]VAR48;
wire VAR121;
wire [1:0]VAR114;
wire VAR161;
wire [31:0]VAR217;
wire VAR4;
wire [3:0]VAR51;
wire VAR57;
wire [4:0]VAR239;
wire VAR225;
wire VAR147;
wire [4:0]VAR47;
wire VAR46;
wire VAR209;
wire VAR227;
wire [1:0]VAR10;
wire VAR29;
wire [31:0]VAR117;
wire VAR190;
wire [1:0]VAR213;
wire VAR202;
wire [31:0]VAR131;
wire VAR26;
wire [3:0]VAR33;
wire VAR167;
wire [2:0]VAR132;
wire VAR195;
wire VAR140;
wire VAR194;
wire VAR196;
wire VAR73;
wire VAR173;
wire VAR89;
wire VAR199;
wire VAR143;
wire VAR116;
wire VAR8;
wire VAR15;
wire VAR104;
wire VAR170;
wire VAR232;
wire VAR32;
wire VAR186;
wire VAR36;
wire VAR164;
wire VAR12;
wire VAR182;
wire VAR224;
wire VAR169;
wire VAR237;
wire VAR55;
wire VAR97;
wire VAR234;
wire [3:0]VAR54;
wire [3:0]VAR200;
assign VAR77 = VAR205;
assign VAR85 = VAR159;
assign VAR1[1:0] = VAR88;
assign VAR56 = VAR178;
assign VAR229[31:0] = VAR48;
assign VAR94[1:0] = VAR114;
assign VAR5 = VAR161;
assign VAR99 = VAR4;
assign VAR13 = VAR214;
assign VAR83 = VAR176;
assign VAR6[1:0] = VAR31;
assign VAR184 = VAR165;
assign VAR65[31:0] = VAR201;
assign VAR236[1:0] = VAR22;
assign VAR215 = VAR193;
assign VAR177 = VAR154;
assign VAR19 = VAR225;
assign VAR62 = VAR46;
assign VAR106[1:0] = VAR10;
assign VAR58 = VAR29;
assign VAR11[31:0] = VAR117;
assign VAR17[1:0] = VAR213;
assign VAR7 = VAR202;
assign VAR204 = VAR26;
assign VAR142 = VAR27[6:0];
assign VAR180 = VAR87[2:0];
assign VAR206 = VAR91;
assign VAR152 = VAR67[6:0];
assign VAR45 = VAR25[2:0];
assign VAR74 = VAR105;
assign VAR68 = VAR157;
assign VAR70 = VAR163;
assign VAR30 = VAR59[31:0];
assign VAR183 = VAR245[3:0];
assign VAR39 = VAR137;
assign VAR192 = VAR194;
assign VAR123 = VAR196;
assign VAR80 = VAR173;
assign VAR166 = VAR89;
assign VAR103 = VAR143;
assign VAR118 = VAR116;
assign VAR203 = VAR15;
assign VAR110 = VAR104;
assign VAR145 = VAR232;
assign VAR151 = VAR32;
assign VAR207 = VAR36;
assign VAR108 = VAR164;
assign VAR238 = VAR182;
assign VAR20 = VAR224;
assign VAR172 = VAR237;
assign VAR81 = VAR55;
assign VAR34 = VAR40[8:0];
assign VAR228 = VAR2;
assign VAR109 = VAR63[8:0];
assign VAR188 = VAR144;
assign VAR171 = VAR220;
assign VAR121 = VAR218;
assign VAR217 = VAR96[31:0];
assign VAR51 = VAR136[3:0];
assign VAR57 = VAR179;
assign VAR239 = VAR53[4:0];
assign VAR147 = VAR208;
assign VAR47 = VAR156[4:0];
assign VAR209 = VAR71;
assign VAR227 = VAR43;
assign VAR190 = VAR230;
assign VAR131 = VAR175[31:0];
assign VAR33 = VAR128[3:0];
assign VAR167 = VAR127;
assign VAR140 = VAR41;
assign VAR73 = VAR155;
assign VAR199 = VAR198;
assign VAR8 = VAR119;
assign VAR170 = VAR210;
assign VAR186 = VAR66;
assign VAR12 = VAR52;
assign VAR169 = VAR153;
assign VAR97 = VAR197;
assign VAR234 = VAR64;
assign VAR130 = VAR195;
VAR38 VAR112
(.VAR187(VAR93),
.VAR241(VAR97),
.VAR141(VAR142),
.VAR107(VAR234),
.VAR75(VAR180),
.VAR243(VAR214),
.VAR50(VAR206),
.VAR211(VAR152),
.VAR216(VAR45),
.VAR226(VAR176),
.VAR69(VAR74),
.VAR247(VAR68),
.VAR79(VAR31),
.VAR125(VAR165),
.VAR44(VAR201),
.VAR148(VAR70),
.VAR233(VAR22),
.VAR16(VAR193),
.VAR3(VAR30),
.VAR113(VAR154),
.VAR219(VAR183),
.VAR115(VAR39));
VAR129 VAR146
(.VAR133(VAR132),
.VAR197(VAR97),
.VAR9(VAR34),
.VAR64(VAR234),
.VAR28(VAR205),
.VAR135(VAR228),
.VAR23(VAR109),
.VAR246(VAR159),
.VAR84(VAR188),
.VAR134(VAR171),
.VAR102(VAR88),
.VAR14(VAR178),
.VAR240(VAR48),
.VAR189(VAR121),
.VAR90(VAR114),
.VAR149(VAR161),
.VAR86(VAR217),
.VAR120(VAR4),
.VAR138(VAR51),
.VAR191(VAR57));
VAR76 VAR111
(.VAR21(1'b0),
.VAR162(1'b0),
.VAR61(1'b0),
.interrupt(VAR195),
.VAR197(VAR97),
.VAR9(VAR239),
.VAR64(VAR234),
.VAR28(VAR225),
.VAR135(VAR147),
.VAR23(VAR47),
.VAR246(VAR46),
.VAR84(VAR209),
.VAR134(VAR227),
.VAR102(VAR10),
.VAR14(VAR29),
.VAR240(VAR117),
.VAR189(VAR190),
.VAR90(VAR213),
.VAR149(VAR202),
.VAR86(VAR131),
.VAR120(VAR26),
.VAR138(VAR33),
.VAR191(VAR167));
VAR95 VAR122
(.VAR168(VAR54),
.VAR92(VAR200),
.VAR78(VAR73),
.VAR42(VAR173),
.VAR101(VAR89),
.VAR158(VAR199),
.VAR100(VAR143),
.VAR235(VAR116),
.VAR37(VAR8),
.VAR150(VAR15),
.VAR181(VAR104),
.VAR60(VAR170),
.VAR242(VAR232),
.VAR185(VAR32),
.VAR18(VAR186),
.VAR82(VAR36),
.VAR35(VAR164),
.VAR244(VAR12),
.VAR72(VAR182),
.VAR24(VAR224),
.VAR222(VAR169),
.VAR231(VAR237),
.VAR221(VAR55),
.VAR223(VAR140),
.VAR139(VAR194),
.VAR98(VAR196));
VAR49 VAR126
(.VAR174(VAR93),
.VAR160(VAR132),
.dout(VAR54));
VAR212 VAR124
(.dout(VAR200));
endmodule
|
mit
|
asicguy/gplgpu
|
hdl/altera_clk_synth/pll_config_top.v
| 1,480 |
module MODULE1
(
input VAR17,
input VAR31,
input VAR34,
input VAR5,
input VAR6,
input [2:0] VAR29,
input [3:0] VAR36,
input [8:0] VAR35,
input VAR21,
output VAR23,
output VAR33,
output VAR19
);
wire VAR7;
wire VAR11;
wire VAR8;
wire reset;
wire VAR16;
wire VAR12;
wire VAR14;
wire VAR15;
assign reset = ~VAR31;
VAR2 VAR24
(
.VAR3 (VAR17),
.reset (reset),
.VAR4 (1'b0),
.VAR29 (VAR29),
.VAR36 (VAR36),
.VAR35 (VAR35),
.VAR5 (VAR5),
.VAR6 (VAR6),
.VAR21 (VAR21),
.VAR14 (VAR14),
.VAR15 (VAR15),
.VAR23 (VAR23),
.VAR32 (),
.VAR11 (VAR11),
.VAR7 (VAR7),
.VAR8 (VAR8),
.VAR16 (VAR16),
.VAR12 (VAR12)
);
VAR30 VAR22
(
.VAR27 (VAR34),
.VAR18 (VAR11),
.VAR10 (VAR7),
.VAR13 (VAR17),
.VAR25 (VAR16),
.VAR28 (VAR12),
.VAR26 (VAR14),
.VAR9 (VAR15),
.VAR1 (VAR33),
.VAR20 (VAR19)
);
endmodule
|
gpl-3.0
|
jotego/jt12
|
hdl/alt/eg_step.v
| 1,961 |
module MODULE1(
input [2:0] VAR5,
input [5:0] VAR3,
input [2:0] VAR11,
output reg VAR7
);
localparam VAR8=3'd0, VAR9=3'd1, VAR10=3'd2, VAR6=3'd7, VAR1=3'd3;
reg [7:0] VAR4;
always @(*) begin : VAR2
if( VAR3[5:4]==2'b11 ) begin if( VAR3[5:2]==4'hf && VAR5 == VAR8)
end
VAR4 = 8'b11111111; else
case( VAR3[1:0] )
2'd0: VAR4 = 8'b00000000;
2'd1: VAR4 = 8'b10001000; 2'd2: VAR4 = 8'b10101010; 2'd3: VAR4 = 8'b11101110; endcase
end
else begin
if( VAR3[5:2]==4'd0 && VAR5 != VAR8)
end
VAR4 = 8'b11111110; else
case( VAR3[1:0] )
2'd0: VAR4 = 8'b10101010; 2'd1: VAR4 = 8'b11101010; 2'd2: VAR4 = 8'b11101110; 2'd3: VAR4 = 8'b11111110; endcase
end
VAR7 = VAR3[5:1]==5'd0 ? 1'b0 : VAR4[ VAR11 ];
end
endmodule MODULE1
|
gpl-3.0
|
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales
|
Conversor_BCD_7seg.v
| 1,167 |
module MODULE1
(
input wire [3:0] VAR1,
output reg [7:0] VAR2
);
always @*
begin
case(VAR1)
4'h0: VAR2 = 8'b00000011; 4'h1: VAR2 = 8'b10011111; 4'h2: VAR2 = 8'b00100101; 4'h3: VAR2 = 8'b00001101; 4'h4: VAR2 = 8'b10011001; 4'h5: VAR2 = 8'b01001001; 4'h6: VAR2 = 8'b01000001; 4'h7: VAR2 = 8'b00011111; 4'h8: VAR2 = 8'b00000001; 4'h9: VAR2 = 8'b00001001; default: VAR2 = 8'b11111111;
endcase
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o21ba/sky130_fd_sc_ls__o21ba_1.v
| 2,316 |
module MODULE1 (
VAR4 ,
VAR10 ,
VAR2 ,
VAR1,
VAR6,
VAR8,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR8;
input VAR3 ;
input VAR7 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4 ,
VAR10 ,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR1;
supply1 VAR6;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
ncos/Xilinx-Verilog
|
ZOLED/src/OLED/ZedboardOLED.v
| 21,451 |
module MODULE1
(
output VAR37,
output VAR42,
output VAR5,
output VAR8,
output VAR107,
output VAR3,
input wire VAR2,
input wire [127:0] VAR79,
input wire [127:0] VAR86,
input wire [127:0] VAR95,
input wire [127:0] VAR7
);
reg [143:0] VAR17;
reg [111:0] VAR11;
reg [142:0] VAR50;
reg [95:0] VAR32;
reg [39:0] VAR91;
reg [7:0] VAR94[0:3][0:15];
reg VAR60 = 1'b0;
reg VAR66 = 1'b1;
reg VAR53 = 1'b1;
reg VAR21 = 1'b1;
assign VAR5 = VAR60;
assign VAR8 = VAR66;
assign VAR107 = VAR53;
assign VAR3 = VAR21;
wire [11:0] VAR13; reg VAR55 = 1'b0; wire VAR12; assign VAR13 = (VAR11 == "VAR4") ? 12'h074 : 12'h014;
reg VAR6 = 1'b0; reg [7:0] VAR64 = 8'h00; wire VAR92;
reg [7:0] VAR80; reg [10:0] VAR49; wire [7:0] VAR40; reg [1:0] VAR70; reg [3:0] VAR100;
reg VAR36 = 1'b1; reg VAR25 = 1'b1; reg ready = 1'b0; reg VAR52 =1'b1;
reg[11:0] VAR45 =12'h000;
wire VAR63;
wire VAR54=1'b0; integer VAR62 = 0;
integer VAR89 = 0;
assign VAR63 = (VAR54 || VAR52);
reg VAR34 = 1'b0;
reg VAR22 = 1'b0;
VAR46 VAR18(
.VAR2(VAR2),
.VAR54(VAR63),
.VAR74(VAR6),
.VAR15(VAR64),
.VAR59(VAR37),
.VAR42(VAR42),
.VAR33(VAR92)
);
VAR65 VAR103(
.VAR2(VAR2),
.VAR54(VAR63),
.VAR99(VAR13),
.VAR19(VAR55),
.VAR56(VAR12)
);
VAR43 VAR96(
.VAR97(VAR2),
.VAR35(VAR49),
.VAR75(VAR40)
);
always @(posedge VAR2) begin
if(VAR63 == 1'b1) begin
VAR17 <= "VAR81";
VAR66 <= 1'b0;
end
else begin
VAR66 <= 1'b1;
case(VAR17)
"VAR81" : begin
if(VAR36 == 1'b1) begin
VAR60 <= 1'b0; VAR17 <= "VAR23";
VAR36 <= 1'b0; end
else begin
VAR17 <="VAR26";
end
end
"VAR23" : begin VAR21 <= 1'b0; VAR17 <= "VAR104";
end
"VAR104" : begin
VAR11 <= "VAR71";
VAR17 <= "VAR85";
end
"VAR71" : begin
VAR64 <= 8'hAE; VAR11 <= "VAR14";
VAR17 <= "VAR93";
end
"VAR14" : begin
VAR64 <= 8'hD5; VAR11 <= "VAR82";
VAR17 <= "VAR93";
end
"VAR82" : begin
VAR64 <= 8'h80; VAR11 <= "VAR102";
VAR17 <= "VAR93";
end
"VAR102" : begin
VAR64 <= 8'hA8; VAR11 <= "VAR69";
VAR17 <= "VAR93";
end
"VAR69" : begin
VAR64 <= 8'h1F; VAR11 <= "VAR10";
VAR17 <= "VAR93";
end
"VAR10" : begin VAR64 <= 8'h8D; VAR11 <= "VAR48";
VAR17 <= "VAR93";
end
"VAR48" : begin VAR64 <= 8'h14; VAR11 <= "VAR77";
VAR17 <= "VAR93";
end
"VAR77" : begin VAR64 <= 8'hD9; VAR11 <= "VAR20";
VAR17 <= "VAR93";
end
"VAR20" : begin VAR64 <= 8'hFF; VAR11 <= "VAR61";
VAR17 <= "VAR93";
end
"VAR61" : begin VAR64 <= 8'hDB; VAR11 <= "VAR73";
VAR17 <= "VAR93";
end
"VAR73" : begin VAR64 <= 8'h40; VAR11 <= "VAR4";
VAR17 <= "VAR93";
end
"VAR4" : begin VAR64 <= 8'h81; VAR11 <= "VAR108";
VAR17 <= "VAR93";
end
"VAR108" : begin
VAR64 <= 8'hF1; VAR11 <= "VAR24";
VAR17 <= "VAR93";
end
"VAR24" : begin
VAR64 <= 8'hA0; VAR11 <= "VAR9";
VAR17 <= "VAR93";
end
"VAR9" : begin
VAR64 <= 8'hC0; VAR11 <= "VAR83";
VAR17 <= "VAR93";
end
"VAR83" : begin
VAR64 <= 8'hDA; VAR11 <= "VAR51";
VAR17 <= "VAR93";
end
"VAR51" : begin
VAR64 <= 8'h02; VAR11 <= "VAR30";
VAR17 <= "VAR93";
end
"VAR30" : begin
VAR53 <= 1'b0;
VAR17 <= "VAR28";
end
"VAR28" : begin
VAR11 <= "VAR90";
VAR17 <= "VAR85";
end
"VAR90" : begin
VAR66 <= 1'b0;
VAR17 <= "VAR76";
end
"VAR76" : begin
VAR11 <= "VAR31";
VAR17 <= "VAR85";
end
"VAR31" : begin
VAR66 <= 1'b1;
VAR17 <= "VAR26";
end
"VAR26" : begin
if(VAR22 == 1'b1) begin
VAR17 <= "VAR47";
VAR50 <= "VAR57";
VAR70 <= 2'b00;
end
else if ((VAR34==1'b1) || (VAR25 == 1'b1)) begin
VAR17 <= "VAR47";
VAR50 <= "VAR106";
VAR70 <= 2'b00;
end
else begin
VAR17<="VAR26";
if ((VAR25 == 1'b0) && (ready ==1'b0)) begin VAR64 <= 8'hAF; VAR11 <= "VAR26";
VAR17 <= "VAR93";
VAR60<=1'b0;
ready <= 1'b1;
VAR22 <= 1'b1;
end
end
end
"VAR47" : begin
VAR60 <= 1'b0;
VAR17 <= "VAR39";
end
"VAR39" : begin
VAR64 <= 8'b00100010;
VAR11 <= "VAR41";
VAR17 <= "VAR93";
end
"VAR41" : begin
VAR64 <= {6'b000000,VAR70};
VAR11 <= "VAR98";
VAR17 <= "VAR93";
end
"VAR98" : begin
VAR64 <= 8'b00000000;
VAR11 <= "VAR87";
VAR17 <= "VAR93";
end
"VAR87" : begin
VAR64 <= 8'b00010000;
VAR11 <= "VAR16";
VAR17 <= "VAR93";
end
"VAR16" : begin
VAR60 <= 1'b1;
VAR17 <= VAR50;
end
"VAR106" : begin
for(VAR62 = 0; VAR62 <= 3 ; VAR62=VAR62+1) begin
for(VAR89 = 0; VAR89 <= 15 ; VAR89=VAR89+1) begin
VAR94[VAR62][VAR89] <= 8'h20;
end
end
VAR91 <= "VAR26";
VAR17 <= "VAR58";
end
"VAR57" : begin
VAR94[0][15]<=VAR79[7:0];
VAR94[0][14]<=VAR79[15:8];
VAR94[0][13]<=VAR79[23:16];
VAR94[0][12]<=VAR79[31:24];
VAR94[0][11]<=VAR79[39:32];
VAR94[0][10]<=VAR79[47:40];
VAR94[0][9]<=VAR79[55:48];
VAR94[0][8]<=VAR79[63:56];
VAR94[0][7]<=VAR79[71:64];
VAR94[0][6]<=VAR79[79:72];
VAR94[0][5]<=VAR79[87:80];
VAR94[0][4]<=VAR79[95:88];
VAR94[0][3]<=VAR79[103:96];
VAR94[0][2]<=VAR79[111:104];
VAR94[0][1]<=VAR79[119:112];
VAR94[0][0]<=VAR79[127:120];
VAR94[1][15]<=VAR86[7:0];
VAR94[1][14]<=VAR86[15:8];
VAR94[1][13]<=VAR86[23:16];
VAR94[1][12]<=VAR86[31:24];
VAR94[1][11]<=VAR86[39:32];
VAR94[1][10]<=VAR86[47:40];
VAR94[1][9]<=VAR86[55:48];
VAR94[1][8]<=VAR86[63:56];
VAR94[1][7]<=VAR86[71:64];
VAR94[1][6]<=VAR86[79:72];
VAR94[1][5]<=VAR86[87:80];
VAR94[1][4]<=VAR86[95:88];
VAR94[1][3]<=VAR86[103:96];
VAR94[1][2]<=VAR86[111:104];
VAR94[1][1]<=VAR86[119:112];
VAR94[1][0]<=VAR86[127:120];
VAR94[2][15]<=VAR95[7:0];
VAR94[2][14]<=VAR95[15:8];
VAR94[2][13]<=VAR95[23:16];
VAR94[2][12]<=VAR95[31:24];
VAR94[2][11]<=VAR95[39:32];
VAR94[2][10]<=VAR95[47:40];
VAR94[2][9]<=VAR95[55:48];
VAR94[2][8]<=VAR95[63:56];
VAR94[2][7]<=VAR95[71:64];
VAR94[2][6]<=VAR95[79:72];
VAR94[2][5]<=VAR95[87:80];
VAR94[2][4]<=VAR95[95:88];
VAR94[2][3]<=VAR95[103:96];
VAR94[2][2]<=VAR95[111:104];
VAR94[2][1]<=VAR95[119:112];
VAR94[2][0]<=VAR95[127:120];
VAR94[3][15]<=VAR7[7:0];
VAR94[3][14]<=VAR7[15:8];
VAR94[3][13]<=VAR7[23:16];
VAR94[3][12]<=VAR7[31:24];
VAR94[3][11]<=VAR7[39:32];
VAR94[3][10]<=VAR7[47:40];
VAR94[3][9]<=VAR7[55:48];
VAR94[3][8]<=VAR7[63:56];
VAR94[3][7]<=VAR7[71:64];
VAR94[3][6]<=VAR7[79:72];
VAR94[3][5]<=VAR7[87:80];
VAR94[3][4]<=VAR7[95:88];
VAR94[3][3]<=VAR7[103:96];
VAR94[3][2]<=VAR7[111:104];
VAR94[3][1]<=VAR7[119:112];
VAR94[3][0]<=VAR7[127:120];
VAR91 <= "VAR26";
VAR17 <= "VAR58";
end
"VAR58" : begin
VAR80 <= VAR94[VAR70][VAR100];
if(VAR100 == 'd15) begin
VAR100 <= 'd0;
VAR70 <= VAR70 + 1'b1;
VAR32 <= "VAR47";
if(VAR70 == 2'b11) begin
VAR50 <= VAR91;
VAR25<=1'b0;
end
else begin
VAR50 <= "VAR58";
end
end
else begin
VAR100 <= VAR100 + 1'b1;
VAR32 <= "VAR58";
end
VAR17 <= "VAR27";
end
"VAR27" : begin
VAR49 <= {VAR80, 3'b000};
VAR11 <= "VAR105";
VAR17 <= "VAR29";
end
"VAR105" : begin
VAR49 <= {VAR80, 3'b001};
VAR11 <= "VAR44";
VAR17 <= "VAR29";
end
"VAR44" : begin
VAR49 <= {VAR80, 3'b010};
VAR11 <= "VAR88";
VAR17 <= "VAR29";
end
"VAR88" : begin
VAR49 <= {VAR80, 3'b011};
VAR11 <= "VAR1";
VAR17 <= "VAR29";
end
"VAR1" : begin
VAR49 <= {VAR80, 3'b100};
VAR11 <= "VAR67";
VAR17 <= "VAR29";
end
"VAR67" : begin
VAR49 <= {VAR80, 3'b101};
VAR11 <= "VAR84";
VAR17 <= "VAR29";
end
"VAR84" : begin
VAR49 <= {VAR80, 3'b110};
VAR11 <= "VAR72";
VAR17 <= "VAR29";
end
"VAR72" : begin
VAR49 <= {VAR80, 3'b111};
VAR11 <= VAR32;
VAR17 <= "VAR29";
end
"VAR29" : begin
VAR17 <= "VAR38";
end
"VAR38" : begin
VAR64 <= VAR40;
VAR17 <= "VAR93";
end
"VAR93" : begin
VAR6 <= 1'b1;
VAR17 <= "VAR101";
end
"VAR101" : begin
if(VAR92 == 1'b1) begin
VAR17 <= "VAR78";
end
end
"VAR85" : begin
VAR55 <= 1'b1;
VAR17 <= "VAR68";
end
"VAR68" : begin
if(VAR12 == 1'b1) begin
VAR17 <= "VAR78";
end
end
"VAR78" : begin
VAR6 <= 1'b0;
VAR55 <= 1'b0;
VAR17 <= VAR11;
end
default : VAR17 <= "VAR81";
endcase
end
end
always @(posedge VAR2) begin
if (VAR63 == 1'b1)
VAR45<=VAR45+1'b1;
if (VAR45 == 12'hFFF) begin
VAR52 <=1'b0;
end
end
endmodule
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_jesd_regmap.v
| 15,376 |
module MODULE1 (
VAR86,
VAR62,
VAR91,
VAR74,
VAR70,
VAR38,
VAR36,
VAR2,
VAR83,
VAR51,
VAR4,
VAR81,
VAR10,
VAR92,
VAR7,
VAR59,
VAR90,
VAR25,
VAR82,
VAR58,
VAR23,
VAR17,
VAR37,
VAR77,
VAR3,
VAR85,
VAR44,
VAR15,
VAR28,
VAR87,
VAR20,
VAR71,
VAR5,
VAR48,
VAR61,
VAR34,
VAR45,
VAR54,
VAR31,
VAR14,
VAR55,
VAR53,
VAR69,
VAR22,
VAR11,
VAR78,
VAR19,
VAR21,
VAR79,
VAR33,
VAR30,
VAR57,
VAR49,
VAR39,
VAR47,
VAR13,
VAR65);
parameter VAR93 = 32'h00010061;
parameter VAR89 = 4;
parameter VAR63 = VAR89 - 1;
parameter VAR46 = (VAR89* 8) - 1;
parameter VAR32 = (VAR89*16) - 1;
parameter VAR84 = (VAR89*32) - 1;
output VAR86;
output VAR62;
output VAR91;
output VAR74;
output [ 4:0] VAR70;
output [ 7:0] VAR38;
output [12:0] VAR36;
output [ 1:0] VAR2;
output VAR83;
output VAR51;
output VAR4;
output VAR81;
output [ 4:0] VAR10;
output [ 7:0] VAR92;
output [ 7:0] VAR7;
output [ 7:0] VAR59;
output [11:0] VAR90;
output [11:0] VAR25;
output [11:0] VAR82;
output [31:0] VAR58;
output [15:0] VAR23;
output [15:0] VAR17;
output [15:0] VAR37;
input VAR77;
input VAR3;
input [ 8:0] VAR85;
input [15:0] VAR44;
output [15:0] VAR15;
output VAR28;
input VAR87;
input VAR20;
input VAR71;
input [ 1:0] VAR5;
input VAR48;
output [VAR63:0] VAR61;
output VAR34;
output [ 8:0] VAR45;
output [15:0] VAR54;
input [VAR32:0] VAR31;
input [VAR63:0] VAR14;
input VAR55;
input [VAR46:0] VAR53;
input [VAR84:0] VAR69;
input [VAR84:0] VAR22;
input [VAR84:0] VAR11;
input [VAR84:0] VAR78;
input [VAR84:0] VAR19;
input [VAR84:0] VAR21;
input [VAR84:0] VAR79;
input VAR33;
input VAR30;
input VAR57;
input VAR49;
input [ 4:0] VAR39;
input [31:0] VAR47;
output [31:0] VAR13;
output VAR65;
reg VAR86 = 'd0;
reg VAR62 = 'd0;
reg VAR91 = 'd0;
reg VAR74 = 'd0;
reg [ 4:0] VAR70 = 'd0;
reg [ 7:0] VAR38 = 'd0;
reg [12:0] VAR36 = 'd0;
reg [ 1:0] VAR2 = 'd0;
reg VAR83 = 'd0;
reg VAR51 = 'd0;
reg [ 7:0] VAR16 = 'd0;
reg VAR4 = 'd0;
reg VAR81 = 'd0;
reg [ 4:0] VAR10 = 'd0;
reg [ 7:0] VAR92 = 'd0;
reg [ 7:0] VAR7 = 'd0;
reg [ 7:0] VAR59 = 'd0;
reg [11:0] VAR90 = 'd0;
reg [11:0] VAR25 = 'd0;
reg [11:0] VAR82 = 'd0;
reg [31:0] VAR58 = 'd0;
reg [15:0] VAR23 = 'd0;
reg [15:0] VAR17 = 'd0;
reg [15:0] VAR37 = 'd0;
reg VAR42 = 'd0;
reg VAR43 = 'd0;
reg [ 1:0] VAR50 = 'd0;
reg [31:0] VAR13 = 'd0;
reg VAR29 = 'd0;
reg VAR56 = 'd0;
reg VAR65 = 'd0;
reg [VAR63:0] VAR61 = 'd0;
reg VAR34 = 'd0;
reg [ 8:0] VAR45 = 'd0;
reg [15:0] VAR54 = 'd0;
reg [15:0] VAR15 = 'd0;
reg VAR28 = 'd0;
reg VAR40 = 'd0;
reg VAR66 = 'd0;
reg [ 7:0] VAR26 = 'd0;
reg [31:0] VAR27 = 'd0;
reg [31:0] VAR76 = 'd0;
reg [31:0] VAR24 = 'd0;
reg [31:0] VAR67 = 'd0;
reg [31:0] VAR75 = 'd0;
reg [31:0] VAR12 = 'd0;
reg [31:0] VAR88 = 'd0;
wire VAR80;
wire VAR64;
wire [VAR63:0] VAR41;
wire [15:0] VAR52[0:VAR63];
wire [ 7:0] VAR68[0:VAR63];
wire [31:0] VAR72[0:VAR63];
wire [31:0] VAR18[0:VAR63];
wire [31:0] VAR35[0:VAR63];
wire [31:0] VAR60[0:VAR63];
wire [31:0] VAR6[0:VAR63];
wire [31:0] VAR9[0:VAR63];
wire [31:0] VAR8[0:VAR63];
genvar VAR73;
assign VAR80 = VAR57 & ~VAR49;
assign VAR64 = VAR29 & ~VAR56;
always @(negedge VAR33 or posedge VAR30) begin
if (VAR33 == 0) begin
VAR86 <= 'd0;
VAR62 <= 'd0;
VAR91 <= 'd0;
VAR74 <= 'd0;
VAR70 <= 'd0;
VAR38 <= 'd0;
VAR36 <= 'd0;
VAR2 <= 'd0;
VAR83 <= 'd0;
VAR51 <= 'd0;
VAR16 <= 'd0;
VAR4 <= 'd0;
VAR81 <= 'd0;
VAR10 <= 'd0;
VAR92 <= 'd0;
VAR7 <= 'd0;
VAR59 <= 'd0;
VAR90 <= 'd0;
VAR25 <= 'd0;
VAR82 <= 'd0;
VAR58 <= 'd0;
VAR23 <= 'd0;
VAR37 <= 'd0;
VAR17 <= 'd0;
VAR42 <= 'd0;
VAR43 <= 'd0;
VAR50 <= 'd0;
end else begin
if ((VAR39 == 5'h01) && (VAR80 == 1'b1)) begin
VAR86 <= VAR47[3];
VAR62 <= VAR47[2];
VAR91 <= VAR47[1];
VAR74 <= VAR47[0];
end
if ((VAR39 == 5'h03) && (VAR80 == 1'b1)) begin
VAR70 <= VAR47[12:8];
VAR38 <= VAR47[7:0];
end
if ((VAR39 == 5'h04) && (VAR80 == 1'b1)) begin
VAR36 <= VAR47[12:0];
end
if ((VAR39 == 5'h05) && (VAR80 == 1'b1)) begin
VAR83 <= VAR47[5];
VAR51 <= VAR47[4];
VAR2 <= 2'd0;
VAR16 <= {4'd0, VAR47[3:0]};
end
if ((VAR39 == 5'h10) && (VAR80 == 1'b1)) begin
VAR4 <= VAR47[1];
VAR81 <= VAR47[0];
end
if ((VAR39 == 5'h11) && (VAR80 == 1'b1)) begin
VAR10 <= VAR47[4:0];
end
if ((VAR39 == 5'h12) && (VAR80 == 1'b1)) begin
VAR92 <= VAR47[23:16];
VAR7 <= VAR47[15:8];
VAR59 <= VAR47[7:0];
end
if ((VAR39 == 5'h13) && (VAR80 == 1'b1)) begin
VAR90 <= VAR47[27:16];
VAR25 <= VAR47[11:0];
end
if ((VAR39 == 5'h14) && (VAR80 == 1'b1)) begin
VAR82 <= VAR47[11:0];
end
if ((VAR39 == 5'h15) && (VAR80 == 1'b1)) begin
VAR58 <= VAR47;
end
if ((VAR39 == 5'h16) && (VAR80 == 1'b1)) begin
VAR23 <= VAR47[15:0];
end
if ((VAR39 == 5'h17) && (VAR80 == 1'b1)) begin
VAR17 <= VAR47[31:16];
VAR37 <= VAR47[15:0];
end
if ((VAR39 == 5'h18) && (VAR80 == 1'b1)) begin
VAR42 <= VAR42 & ~VAR47[5];
VAR43 <= VAR43 & ~VAR47[4];
VAR50[1] <= VAR50[1] & ~VAR47[3];
VAR50[0] <= VAR50[0] & ~VAR47[2];
end else begin
VAR42 <= VAR42 | VAR20;
VAR43 <= VAR43 | VAR71;
VAR50[1] <= VAR50[1] | VAR5[1];
VAR50[0] <= VAR50[0] | VAR5[0];
end
end
end
always @(negedge VAR33 or posedge VAR30) begin
if (VAR33 == 0) begin
VAR13 <= 'd0;
VAR29 <= 'd0;
VAR56 <= 'd0;
VAR65 <= 'd0;
end else begin
case (VAR39)
5'h00: VAR13 <= VAR93;
5'h01: VAR13 <= {28'd0, VAR86, VAR62, VAR91, VAR74};
5'h02: VAR13 <= {31'd0, VAR66};
5'h03: VAR13 <= {19'd0, VAR70, VAR38};
5'h04: VAR13 <= {19'd0, VAR36};
5'h05: VAR13 <= {26'd0, VAR83, VAR51, VAR16[3:0]};
5'h06: VAR13 <= VAR26;
5'h07: VAR13 <= VAR27;
5'h08: VAR13 <= VAR76;
5'h09: VAR13 <= VAR24;
5'h0a: VAR13 <= VAR67;
5'h0b: VAR13 <= VAR75;
5'h0c: VAR13 <= VAR12;
5'h0d: VAR13 <= VAR88;
5'h10: VAR13 <= {30'd0, VAR4, VAR81};
5'h11: VAR13 <= {27'd0, VAR10};
5'h12: VAR13 <= {8'd0, VAR92, VAR7, VAR59};
5'h13: VAR13 <= {4'd0, VAR90, 4'd0, VAR25};
5'h14: VAR13 <= {20'd0, VAR82};
5'h15: VAR13 <= VAR58;
5'h16: VAR13 <= {16'd0, VAR23};
5'h17: VAR13 <= {VAR17, VAR37};
5'h18: VAR13 <= {26'd0, VAR42, VAR43, VAR50,
VAR48, VAR87};
default: VAR13 <= 0;
endcase
VAR29 <= VAR57;
VAR56 <= VAR29;
VAR65 <= VAR64;
end
end
always @(negedge VAR33 or posedge VAR30) begin
if (VAR33 == 0) begin
VAR61 <= 'd0;
VAR34 <= 'd0;
VAR45 <= 'd0;
VAR54 <= 'd0;
VAR15 <= 'd0;
VAR28 <= 'd0;
end else begin
VAR61 <= VAR41;
VAR34 <= VAR3;
VAR45 <= VAR85;
VAR54 <= VAR44;
VAR15 <= VAR52[VAR16];
VAR28 <= VAR14[VAR16];
end
end
always @(negedge VAR33 or posedge VAR30) begin
if (VAR33 == 0) begin
VAR40 <= 'd0;
VAR66 <= 'd0;
VAR26 <= 'd0;
VAR27 <= 'd0;
VAR76 <= 'd0;
VAR24 <= 'd0;
VAR67 <= 'd0;
VAR75 <= 'd0;
VAR12 <= 'd0;
VAR88 <= 'd0;
end else begin
VAR40 <= VAR55;
VAR66 <= VAR40;
VAR26 <= VAR68[VAR16];
VAR27 <= VAR72[VAR16];
VAR76 <= VAR18[VAR16];
VAR24 <= VAR35[VAR16];
VAR67 <= VAR60[VAR16];
VAR75 <= VAR6[VAR16];
VAR12 <= VAR9[VAR16];
VAR88 <= VAR8[VAR16];
end
end
generate
for (VAR73 = 0; VAR73 < VAR89; VAR73 = VAR73 + 1) begin : VAR1
assign VAR41[VAR73] = (VAR16 == VAR73) ? VAR77 : 1'b0;
assign VAR52[VAR73] = VAR31[((VAR73*16)+15):(VAR73*16)];
assign VAR68[VAR73] = VAR53[((VAR73*8)+7):(VAR73*8)];
assign VAR72[VAR73] = VAR69[((VAR73*32)+31):(VAR73*32)];
assign VAR18[VAR73] = VAR22[((VAR73*32)+31):(VAR73*32)];
assign VAR35[VAR73] = VAR11[((VAR73*32)+31):(VAR73*32)];
assign VAR60[VAR73] = VAR78[((VAR73*32)+31):(VAR73*32)];
assign VAR6[VAR73] = VAR19[((VAR73*32)+31):(VAR73*32)];
assign VAR9[VAR73] = VAR21[((VAR73*32)+31):(VAR73*32)];
assign VAR8[VAR73] = VAR79[((VAR73*32)+31):(VAR73*32)];
end
endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.functional.pp.v
| 1,832 |
module MODULE1 (
VAR8 ,
VAR7 ,
VAR6,
VAR4,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR6;
input VAR4;
input VAR1 ;
input VAR5 ;
wire VAR12 ;
wire VAR10;
buf VAR2 (VAR12 , VAR7 );
VAR3 VAR9 (VAR10, VAR12, VAR6, VAR4);
buf VAR11 (VAR8 , VAR10 );
endmodule
|
apache-2.0
|
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