repo_name
stringlengths 6
79
| path
stringlengths 4
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| size
int64 1.02k
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| content
stringlengths 15
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| license
stringclasses 14
values |
|---|---|---|---|---|
OrganicMonkeyMotion/fpga_experiments
|
bmax10/embedded_lab/pwm_pll_bb.v
| 11,816 |
module MODULE1 (
VAR1,
VAR2,
VAR3);
input VAR1;
output VAR2;
output VAR3;
endmodule
|
unlicense
|
hhuang25/uwaterloo_ece224
|
ANT/led_pio.v
| 2,048 |
module MODULE1 (
address,
VAR9,
clk,
VAR6,
VAR5,
VAR4,
VAR3,
VAR8
)
;
output [ 7: 0] VAR3;
output [ 7: 0] VAR8;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR6;
input VAR5;
input [ 7: 0] VAR4;
wire VAR2;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR1;
wire [ 7: 0] VAR8;
assign VAR2 = 1;
assign VAR1 = {8 {(address == 0)}} & VAR7;
always @(posedge clk or negedge VAR6)
begin
if (VAR6 == 0)
VAR7 <= 0;
end
else if (VAR9 && ~VAR5 && (address == 0))
VAR7 <= VAR4[7 : 0];
end
assign VAR8 = VAR1;
assign VAR3 = VAR7;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/dlxtn/sky130_fd_sc_hdll__dlxtn.symbol.v
| 1,349 |
module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR6
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
CospanDesign/nysa-verilog
|
verilog/wishbone/slave/wb_fpga_nes/rtl/nes_top.v
| 11,696 |
module MODULE1 (
input clk, input rst, input VAR152, input [3:0] VAR42,
output [9:0] VAR80, output [9:0] VAR10, output VAR133, output VAR101, output [2:0] VAR58, output [2:0] VAR39, output [1:0] VAR120,
input [7:0] VAR8, input [7:0] VAR70,
output VAR93,
input VAR69,
input [7:0] VAR123,
input VAR99,
output [15:0] VAR44,
output VAR76,
input [15:0] VAR72,
input [31:0] VAR61,
input VAR79,
output VAR57,
input [7:0] VAR132,
output VAR126,
input VAR128,
output [7:0] VAR82
);
wire [ 7:0] VAR106;
wire [15:0] VAR6;
wire VAR45;
wire [ 7:0] VAR119;
wire [13:0] VAR43;
wire VAR64;
wire VAR37;
wire [ 7:0] VAR41;
wire VAR49;
wire [ 7:0] VAR23;
wire [15:0] VAR35;
wire VAR142;
wire VAR146;
wire [ 3:0] VAR7;
wire [ 7:0] VAR87;
wire VAR17;
wire [ 7:0] VAR153;
VAR88 VAR140(
.VAR55 (clk ),
.VAR71 (rst ),
.VAR125 (VAR37 ),
.VAR151 (~VAR152 ),
.VAR67 (VAR49 ),
.VAR34 (VAR142 ),
.VAR18 (VAR35 ),
.din (VAR41 ),
.dout (VAR23 ),
.VAR66 (VAR146 ),
.VAR8 (VAR8 ),
.VAR70 (VAR70 ),
.VAR14 (VAR42 ),
.VAR40 (VAR93 ),
.VAR62 (VAR7 ),
.VAR30 (VAR87 ),
.VAR118 (VAR17 ),
.VAR136 (VAR153 )
);
wire VAR135;
wire [ 7:0] VAR81;
wire [ 7:0] VAR95;
wire VAR108;
wire VAR84;
wire [39:0] VAR75;
wire VAR29;
VAR97 VAR130(
.VAR55 (clk ),
.VAR90 (VAR75 ),
.VAR154 (VAR29 ),
.VAR143 (VAR135 ),
.VAR12 (VAR6[14:0] ),
.VAR19 (VAR45 ),
.VAR102 (VAR106 ),
.VAR134 (VAR81 ),
.VAR122 (VAR43 ),
.VAR148 (~VAR64 ),
.VAR31 (VAR119 ),
.VAR65 (VAR95 ),
.VAR156 (VAR108 ),
.VAR3 (VAR84 )
);
assign VAR135 = ~VAR6[15];
wire VAR116;
wire [7:0] VAR105;
VAR85 VAR91(
.VAR55 (clk ),
.VAR89 (VAR116 ),
.VAR141 (VAR45 ),
.VAR56 (VAR6[10:0] ),
.din (VAR106 ),
.dout (VAR105 )
);
assign VAR116 = (VAR6[15:13] == 0);
wire [10:0] VAR53;
wire [ 7:0] VAR2;
VAR107 VAR51(
.VAR55 (clk ),
.VAR89 (~VAR108 ),
.VAR141 (~VAR64 ),
.VAR56 (VAR53 ),
.din (VAR119 ),
.dout (VAR2 )
);
wire [ 2:0] VAR100; wire VAR92; wire VAR33; wire [ 7:0] VAR111; wire [ 7:0] VAR22;
wire [13:0] VAR20; wire VAR32; wire [ 7:0] VAR124; wire [ 7:0] VAR52;
wire VAR137;
assign VAR100 = VAR6[2:0];
assign VAR92 = (VAR6[15:13] == 3'b001) ? 1'b0 : 1'b1;
assign VAR33 = VAR45;
assign VAR111 = VAR106;
VAR121 VAR63(
.VAR55 (clk ),
.VAR71 (rst ),
.VAR115 (VAR100 ),
.VAR9 (VAR92 ),
.VAR11 (VAR33 ),
.VAR103 (VAR111 ),
.VAR80 (VAR80), .VAR10 (VAR10),
.VAR28 (VAR124 ),
.VAR46 (VAR133 ),
.VAR157 (VAR101 ),
.VAR4 (VAR58 ),
.VAR114 (VAR39 ),
.VAR139 (VAR120 ),
.VAR50 (VAR22 ),
.VAR48 (VAR137 ),
.VAR15 (VAR20 ),
.VAR2 (VAR52 ),
.VAR109 (VAR32 )
);
assign VAR53 = { VAR84, VAR43[9:0] };
wire VAR127;
wire [ 7:0] VAR26;
wire [ 7:0] VAR36;
wire [15:0] VAR150;
wire VAR47;
wire [ 7:0] VAR98;
wire [ 7:0] VAR27;
wire [15:0] VAR155;
wire VAR131;
VAR147 VAR77(
.clk (clk ),
.rst (rst ),
.VAR68 (VAR69 ),
.VAR113 (VAR123 ),
.VAR13 (VAR99 ),
.VAR24 (VAR44 ),
.VAR94 (VAR76 ),
.VAR5 (VAR72 ),
.VAR110 (VAR61 ),
.VAR59 (VAR79 ),
.VAR129 (VAR57 ),
.VAR83 (VAR132 ),
.VAR74 (VAR126 ),
.VAR144 (VAR128 ),
.VAR86 (VAR82 ),
.VAR73 (VAR146 ),
.VAR60 (VAR47 ), .VAR78 (VAR150 ),
.VAR104 (VAR26 ),
.VAR25 (VAR36 ),
.VAR149 (VAR127 ),
.VAR54 (VAR17 ),
.VAR21 (VAR7 ),
.VAR1 (VAR153 ),
.VAR117 (VAR87 ),
.VAR145 (VAR131 ),
.VAR138 (VAR155 ),
.VAR96 (VAR98 ),
.VAR38 (VAR27 ),
.VAR112 (VAR75 ),
.VAR16 (VAR29 )
);
assign VAR37 = (VAR127) ? 1'b0 : 1'b1;
assign VAR6 = (VAR127) ? VAR150 : VAR35;
assign VAR45 = (VAR127) ? VAR47 : VAR142;
assign VAR106 = (VAR127) ? VAR36 : VAR23;
assign VAR41 = VAR81 | VAR105 | VAR22;
assign VAR26 = VAR81 | VAR105 | VAR22;
assign VAR43 = (VAR127) ? VAR155[13:0] : VAR20;
assign VAR64 = (VAR127) ? VAR131 : VAR32;
assign VAR119 = (VAR127) ? VAR27 : VAR52;
assign VAR124 = VAR95 | VAR2;
assign VAR98 = VAR95 | VAR2;
assign VAR49 = VAR137;
endmodule
|
mit
|
freecores/orsoc_graphics_accelerator
|
bench/verilog/gfx/wbm_w_bench.v
| 1,750 |
module MODULE1();
reg VAR16; reg VAR13; wire VAR11; wire VAR10; wire [ 2:0] VAR8; wire [ 1:0] VAR15; wire VAR5; wire [31:0] VAR14; wire [ 3:0] VAR3; reg VAR4; reg VAR18; wire [31:0] VAR1;
wire VAR6;
reg VAR9;
wire VAR2;
reg [31:2] VAR17;
reg [3:0] VAR7;
reg [31:0] VAR12;
begin
|
gpl-3.0
|
merckhung/zet
|
cores/zet/rtl/zet.v
| 2,739 |
module MODULE1 (
input VAR29,
input VAR9,
input [15:0] VAR26,
output [15:0] VAR20,
output [19:1] VAR1,
output VAR4,
output VAR27, output [ 1:0] VAR6,
output VAR18,
output VAR21,
input VAR10,
input VAR23, output VAR30, input VAR15,
output VAR12,
output [19:0] VAR24 );
wire [15:0] VAR25;
wire VAR5;
wire [19:0] VAR14;
wire VAR31;
wire VAR2;
wire VAR17;
wire [15:0] VAR11;
wire VAR22;
wire [15:0] VAR16;
VAR13 VAR19 (
.clk (VAR29),
.rst (VAR9),
.VAR7 (VAR23),
.VAR3 (VAR30),
.VAR15 (VAR15),
.VAR12 (VAR12),
.VAR14 (VAR14),
.VAR16 (VAR16),
.VAR11 (VAR11),
.VAR25 (VAR25),
.VAR31 (VAR31),
.VAR5 (VAR5),
.VAR2 (VAR2),
.VAR17 (VAR17),
.VAR22 (VAR22),
.VAR24 (VAR24)
);
VAR8 VAR28 (
.VAR31 (VAR31),
.VAR2 (VAR2),
.VAR17 (VAR17),
.VAR14 (VAR14),
.VAR5 (VAR5),
.VAR11 (VAR11),
.VAR25 (VAR25),
.VAR22 (VAR22),
.VAR29 (VAR29),
.VAR9 (VAR9),
.VAR26 (VAR26),
.VAR20 (VAR20),
.VAR1 (VAR1),
.VAR4 (VAR4),
.VAR27 (VAR27),
.VAR6 (VAR6),
.VAR18 (VAR18),
.VAR21 (VAR21),
.VAR10 (VAR10)
);
assign VAR16 = (VAR30 | VAR12) ? VAR26 : VAR11;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/fill/sky130_fd_sc_lp__fill.symbol.v
| 1,186 |
module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
sh-chris110/chris
|
FPGA/chris/Qsys/soc_design/synthesis/submodules/soc_design_dma_0.v
| 36,119 |
module MODULE3 (
VAR32,
clk,
VAR122,
VAR133,
VAR38,
VAR7,
VAR123,
VAR2,
VAR36,
VAR114,
VAR29,
VAR42,
VAR17,
word,
VAR97
)
;
output [ 31: 0] VAR97;
input VAR32;
input clk;
input VAR122;
input [ 2: 0] VAR133;
input VAR38;
input VAR7;
input [ 14: 0] VAR123;
input VAR2;
input [ 31: 0] VAR36;
input VAR114;
input [ 10: 0] VAR29;
input [ 4: 0] VAR42;
input VAR17;
input word;
wire VAR95;
wire [ 31: 0] VAR97;
wire VAR92;
wire [ 1: 0] VAR14;
reg [ 1: 0] VAR80;
assign VAR95 = VAR38 & ~VAR7 & ((VAR133 == 6) || (VAR133 == 7));
assign VAR92 = VAR38 & ~VAR7 & (VAR133 == 3);
assign VAR14 = ((VAR95 && VAR123[3] || VAR92))? VAR29[1 : 0] :
(VAR114)? (VAR80 + VAR42) :
VAR80;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR80 <= 0;
end
else if (VAR122)
VAR80 <= VAR14[1 : 0];
end
assign VAR97[31 : 16] = VAR36[31 : 16];
assign VAR97[15 : 8] = ({8 {(VAR2 & (VAR80[1] == 0))}} & VAR36[15 : 8]) |
({8 {(VAR2 & (VAR80[1] == 1))}} & VAR36[31 : 24]) |
({8 {word}} & VAR36[15 : 8]);
assign VAR97[7 : 0] = ({8 {(VAR32 & (VAR80[1 : 0] == 0))}} & VAR36[7 : 0]) |
({8 {(VAR32 & (VAR80[1 : 0] == 1))}} & VAR36[15 : 8]) |
({8 {(VAR32 & (VAR80[1 : 0] == 2))}} & VAR36[23 : 16]) |
({8 {(VAR32 & (VAR80[1 : 0] == 3))}} & VAR36[31 : 24]) |
({8 {(VAR2 & (VAR80[1] == 0))}} & VAR36[7 : 0]) |
({8 {(VAR2 & (VAR80[1] == 1))}} & VAR36[23 : 16]) |
({8 {word}} & VAR36[7 : 0]);
endmodule
module MODULE7 (
VAR32,
VAR2,
word,
VAR26,
VAR19
)
;
output [ 3: 0] VAR19;
input VAR32;
input VAR2;
input word;
input [ 10: 0] VAR26;
wire VAR63;
wire VAR33;
wire VAR125;
wire VAR119;
wire VAR51;
wire VAR35;
wire [ 3: 0] VAR19;
assign VAR35 = VAR26[1 : 0] == 2'h3;
assign VAR51 = VAR26[1 : 0] == 2'h2;
assign VAR119 = VAR26[1 : 0] == 2'h1;
assign VAR125 = VAR26[1 : 0] == 2'h0;
assign VAR33 = VAR26[1] == 1'h1;
assign VAR63 = VAR26[1] == 1'h0;
assign VAR19 = ({4 {VAR32}} & {VAR35, VAR51, VAR119, VAR125}) |
({4 {VAR2}} & {VAR33, VAR33, VAR63, VAR63}) |
({4 {word}} & 4'b1111);
endmodule
module MODULE6 (
clk,
VAR49,
VAR138,
VAR31,
VAR17,
VAR108,
VAR100,
VAR58,
VAR46
)
;
output [ 31: 0] VAR46;
input clk;
input [ 31: 0] VAR49;
input [ 9: 0] VAR138;
input VAR31;
input VAR17;
input [ 9: 0] VAR108;
input VAR100;
input VAR58;
reg [ 31: 0] VAR16 [1023: 0];
wire [ 31: 0] VAR46;
reg [ 9: 0] VAR29;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR29 <= 0;
end
else if (VAR31)
VAR29 <= VAR138;
end
assign VAR46 = VAR16[VAR29];
always @(posedge VAR100)
begin
if (VAR58)
VAR16[VAR108] <= VAR49;
end
endmodule
module MODULE4 (
clk,
VAR122,
VAR27,
VAR97,
VAR86,
VAR9,
VAR15,
VAR17,
VAR106,
VAR57,
VAR98,
VAR104
)
;
output VAR106;
output VAR57;
output [ 31: 0] VAR98;
output VAR104;
input clk;
input VAR122;
input VAR27;
input [ 31: 0] VAR97;
input VAR86;
input VAR9;
input VAR15;
input VAR17;
wire [ 9: 0] VAR118;
reg [ 9: 0] VAR85;
wire VAR106;
wire VAR79;
reg VAR57;
reg VAR110;
wire VAR136;
wire [ 31: 0] VAR24;
wire [ 31: 0] VAR98;
reg VAR69;
reg [ 31: 0] VAR59;
wire [ 9: 0] VAR137;
wire VAR135;
wire VAR104;
wire [ 9: 0] VAR112;
wire [ 9: 0] VAR138;
reg [ 9: 0] VAR78;
reg [ 9: 0] VAR108;
wire VAR103;
assign VAR112 = (VAR86)? VAR108 - 1 :
VAR108;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR108 <= 0;
end
else if (VAR122)
if (VAR9)
VAR108 <= 0;
else
VAR108 <= VAR112;
end
assign VAR138 = VAR9 ? 0 : VAR27 ? (VAR78 - 1) : VAR78;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR78 <= 0;
end
else
VAR78 <= VAR138;
end
assign VAR106 = ~VAR57;
assign VAR136 = VAR86 & ~VAR27;
assign VAR79 = VAR27 & ~VAR86;
assign VAR118 = VAR78 - 1;
assign VAR137 = (VAR15)? VAR85 - 1 :
VAR85;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR85 <= {10 {1'b1}};
end
else if (VAR122)
if (VAR9)
VAR85 <= {10 {1'b1}};
else
VAR85 <= VAR137;
end
assign VAR135 = VAR9 | ((~VAR136 & VAR57) | (VAR79 & (VAR108 == VAR118)));
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR57 <= 1;
end
else if (VAR122)
VAR57 <= VAR135;
end
assign VAR104 = ~VAR9 & ((~VAR79 & VAR110) | (VAR15 & (VAR85 == VAR138)));
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR110 <= 0;
end
else if (VAR122)
VAR110 <= VAR104;
end
assign VAR103 = VAR86 && (VAR108 == VAR138);
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR59 <= 0;
end
else if (VAR103)
VAR59 <= VAR97;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR69 <= 0;
end
else if (VAR103)
VAR69 <= -1;
else if (VAR27)
VAR69 <= 0;
end
assign VAR98 = VAR69 ? VAR59 : VAR24;
MODULE6 MODULE2
(
.clk (clk),
.VAR49 (VAR97),
.VAR46 (VAR24),
.VAR138 (VAR138),
.VAR31 (1'b1),
.VAR17 (VAR17),
.VAR108 (VAR108),
.VAR100 (clk),
.VAR58 (VAR86)
);
endmodule
module MODULE5 (
clk,
VAR122,
VAR10,
VAR75,
VAR104,
VAR54,
VAR17,
VAR30,
VAR39
)
;
output VAR30;
output VAR39;
input clk;
input VAR122;
input VAR10;
input VAR75;
input VAR104;
input VAR54;
input VAR17;
wire VAR30;
wire VAR39;
wire VAR73;
reg VAR44;
reg VAR88;
reg VAR74;
assign VAR39 = ~VAR44;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR44 <= 0;
end
else if (VAR122)
VAR44 <= VAR73;
end
assign VAR30 = VAR44 & ~VAR54;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR74 <= 1;
end
else if (VAR122)
VAR74 <= ((VAR74 == 1) & (VAR10 == 0)) |
((VAR74 == 1) & (VAR75 == 1)) |
((VAR74 == 1) & (VAR104 == 1)) |
((VAR88 == 1) & (VAR104 == 1) & (VAR54 == 0)) |
((VAR88 == 1) & (VAR75 == 1) & (VAR54 == 0));
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR88 <= 0;
end
else if (VAR122)
VAR88 <= ((VAR74 == 1) & (VAR104 == 0) & (VAR75 == 0) & (VAR10 == 1)) |
((VAR88 == 1) & (VAR54 == 1)) |
((VAR88 == 1) & (VAR104 == 0) & (VAR75 == 0) & (VAR54 == 0));
end
assign VAR73 = ({1 {((VAR88 && (VAR54 == 1)))}} & 1) |
({1 {((VAR88 && (VAR75 == 0) && (VAR104 == 0) && (VAR54 == 0)))}} & 1) |
({1 {((VAR74 && (VAR10 == 1) && (VAR75 == 0) && (VAR104 == 0)))}} & 1);
endmodule
module MODULE1 (
VAR105,
VAR106,
VAR87,
VAR27,
VAR102,
VAR126,
VAR11
)
;
output VAR27;
output VAR102;
output VAR126;
output VAR11;
input VAR105;
input VAR106;
input VAR87;
wire VAR27;
wire VAR102;
wire VAR126;
wire VAR11;
assign VAR11 = VAR106 & ~VAR105;
assign VAR126 = ~VAR11;
assign VAR27 = VAR11 & ~VAR87;
assign VAR102 = VAR27;
endmodule
module MODULE2 (
clk,
VAR133,
VAR38,
VAR7,
VAR123,
VAR36,
VAR114,
VAR54,
VAR109,
VAR87,
VAR107,
VAR77,
VAR29,
VAR20,
VAR68,
VAR115,
VAR26,
VAR45,
VAR19,
VAR66,
VAR91,
VAR101
)
;
output VAR107;
output [ 14: 0] VAR77;
output [ 10: 0] VAR29;
output [ 6: 0] VAR20;
output VAR68;
output VAR115;
output [ 10: 0] VAR26;
output [ 6: 0] VAR45;
output [ 3: 0] VAR19;
output VAR66;
output VAR91;
output [ 31: 0] VAR101;
input clk;
input [ 2: 0] VAR133;
input VAR38;
input VAR7;
input [ 14: 0] VAR123;
input [ 31: 0] VAR36;
input VAR114;
input VAR54;
input VAR109;
input VAR87;
reg VAR12;
reg [ 6: 0] VAR6;
reg [ 6: 0] VAR1;
wire VAR132;
wire VAR32;
wire VAR122;
reg [ 12: 0] VAR64;
reg VAR5;
reg VAR105;
reg VAR52;
reg VAR76;
wire VAR107;
reg [ 14: 0] VAR77;
reg VAR50;
wire VAR21;
reg VAR18;
wire VAR22;
wire VAR25;
wire VAR106;
wire VAR57;
wire [ 31: 0] VAR98;
wire [ 31: 0] VAR56;
wire [ 31: 0] VAR82;
wire [ 31: 0] VAR65;
wire VAR27;
wire [ 31: 0] VAR97;
wire VAR86;
wire VAR89;
wire VAR9;
wire VAR10;
wire VAR2;
wire VAR117;
wire VAR30;
wire VAR102;
wire VAR43;
reg VAR124;
reg [ 14: 0] VAR70;
reg VAR60;
wire VAR55;
wire VAR39;
wire VAR126;
wire [ 12: 0] VAR130;
wire [ 14: 0] VAR40;
wire VAR75;
wire VAR48;
wire VAR104;
wire [ 14: 0] VAR34;
wire VAR81;
wire VAR99;
wire [ 10: 0] VAR127;
wire VAR41;
wire [ 10: 0] VAR53;
wire [ 14: 0] VAR28;
wire VAR3;
wire VAR93;
wire VAR134;
wire [ 10: 0] VAR29;
wire [ 6: 0] VAR20;
wire VAR68;
wire VAR120;
reg VAR94;
wire VAR115;
reg VAR131;
reg [ 10: 0] VAR29;
wire [ 4: 0] VAR42;
wire VAR62;
reg VAR116;
reg VAR17;
wire VAR67;
reg VAR47;
wire VAR83;
wire [ 4: 0] VAR61;
wire VAR8;
wire VAR111;
wire VAR37;
reg VAR96;
wire word;
wire [ 10: 0] VAR26;
wire [ 6: 0] VAR45;
wire [ 3: 0] VAR19;
wire VAR66;
wire VAR84;
reg VAR121;
wire VAR11;
wire VAR91;
wire [ 31: 0] VAR101;
reg [ 10: 0] VAR26;
wire [ 4: 0] VAR113;
reg [ 14: 0] VAR23;
reg VAR90;
assign VAR122 = 1;
MODULE3 MODULE3
(
.VAR32 (VAR32),
.clk (clk),
.VAR122 (VAR122),
.VAR133 (VAR133),
.VAR38 (VAR38),
.VAR7 (VAR7),
.VAR123 (VAR123),
.VAR97 (VAR97),
.VAR2 (VAR2),
.VAR36 (VAR36),
.VAR114 (VAR114),
.VAR29 (VAR29),
.VAR42 (VAR42),
.VAR17 (VAR17),
.word (word)
);
MODULE7 MODULE6
(
.VAR32 (VAR32),
.VAR2 (VAR2),
.word (word),
.VAR26 (VAR26),
.VAR19 (VAR19)
);
assign VAR55 = VAR38 & ~VAR7 & (VAR133 == 3);
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR1 <= 1;
end
else if (VAR55)
VAR1 <= VAR123 >> 2;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR6 <= 1;
end
else if (~VAR132)
VAR6 <= VAR1;
end
assign VAR20 = VAR6;
assign VAR45 = VAR6;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR12 <= 0;
end
else if (VAR122)
VAR12 <= ~VAR39;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR131 <= 0;
end
else if (VAR122)
VAR131 <= VAR54;
end
assign VAR115 = (~VAR131 & VAR12) || VAR39;
assign VAR8 = VAR38 & ~VAR7 & (VAR133 == 0);
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR29 <= 11'h0;
end
else if (VAR122)
VAR29 <= VAR127;
end
assign VAR127 = ((VAR38 & ~VAR7 & (VAR133 == 1)))? VAR123 :
(VAR30)? (VAR29 + VAR42) :
VAR29;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR26 <= 11'h0;
end
else if (VAR122)
VAR26 <= VAR53;
end
assign VAR53 = ((VAR38 & ~VAR7 & (VAR133 == 2)))? VAR123 :
(VAR102)? (VAR26 + VAR113) :
VAR26;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR70 <= 15'h0;
end
else if (VAR122)
VAR70 <= VAR34;
end
assign VAR34 = ((VAR38 & ~VAR7 & (VAR133 == 3)))? VAR123 :
((VAR30 && (!VAR60)))? VAR70 - VAR70 :
VAR70;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR64 <= 13'h84;
end
else if (VAR122)
VAR64 <= VAR130;
end
assign VAR130 = ((VAR38 & ~VAR7 & ((VAR133 == 6) || (VAR133 == 7))))? VAR123 :
VAR64;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR23 <= 15'h0;
end
else if (VAR122)
VAR23 <= VAR28;
end
assign VAR28 = ((VAR38 & ~VAR7 & (VAR133 == 3)))? VAR123 :
((VAR102 && (!VAR90)))? VAR23 - {1'b0,
1'b0,
word,
VAR2,
VAR32} :
VAR23;
assign VAR3 = VAR102 && (!VAR90) && ((VAR23 - {1'b0,
1'b0,
word,
VAR2,
VAR32}) == 0);
assign VAR81 = VAR30 && (!VAR60) && ((VAR70 - VAR70) == 0);
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR60 <= 1;
end
else if (VAR122)
if (VAR38 & ~VAR7 & (VAR133 == 3))
VAR60 <= 0;
else if (VAR81)
VAR60 <= -1;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR90 <= 1;
end
else if (VAR122)
if (VAR38 & ~VAR7 & (VAR133 == 3))
VAR90 <= 0;
else if (VAR3)
VAR90 <= -1;
end
assign VAR113 = (VAR111)? 0 :
(1)? 0 :
{1'b0,
1'b0,
word,
VAR2,
VAR32};
assign VAR42 = (VAR134)? 0 :
(1)? 0 :
{1'b0,
1'b0,
word,
VAR2,
VAR32};
assign VAR40 = ({15 {(VAR133 == 0)}} & VAR61) |
({15 {(VAR133 == 1)}} & VAR29) |
({15 {(VAR133 == 2)}} & VAR26) |
({15 {(VAR133 == 3)}} & VAR23) |
({15 {(VAR133 == 6)}} & VAR64);
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR77 <= 0;
end
else if (VAR122)
VAR77 <= VAR40;
end
assign VAR21 = VAR10 & VAR18;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR50 <= 0;
end
else if (VAR122)
if (VAR8)
VAR50 <= 0;
else if (VAR21 & ~VAR5)
VAR50 <= -1;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR5 <= 0;
end
else if (VAR122)
VAR5 <= VAR21;
end
assign VAR132 = VAR10 & ~VAR18;
assign VAR61[0] = VAR50;
assign VAR61[1] = VAR132;
assign VAR61[2] = VAR116;
assign VAR61[3] = VAR96;
assign VAR61[4] = VAR124;
assign VAR32 = VAR64[0];
assign VAR2 = VAR64[1];
assign word = VAR64[2];
assign VAR10 = VAR64[3];
assign VAR117 = VAR64[4];
assign VAR62 = 1'b0;
assign VAR37 = 1'b0;
assign VAR43 = VAR64[7];
assign VAR134 = VAR64[8];
assign VAR111 = VAR64[9];
assign VAR22 = VAR64[10];
assign VAR93 = VAR64[11];
assign VAR83 = VAR64[12];
assign VAR107 = VAR117 & VAR50;
assign VAR99 = ~VAR8 && (VAR94 || (VAR120 & VAR62));
assign VAR41 = ~VAR8 && (VAR121 || (VAR102 & VAR84 & VAR37));
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR94 <= 0;
end
else if (VAR122)
VAR94 <= VAR99;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR121 <= 0;
end
else if (VAR122)
VAR121 <= VAR41;
end
assign VAR9 = ~VAR5 & VAR21;
MODULE4 MODULE4
(
.clk (clk),
.VAR122 (VAR122),
.VAR106 (VAR106),
.VAR57 (VAR57),
.VAR98 (VAR98),
.VAR27 (VAR27),
.VAR97 (VAR97),
.VAR86 (VAR86),
.VAR9 (VAR9),
.VAR15 (VAR30),
.VAR104 (VAR104),
.VAR17 (VAR17)
);
MODULE5 MODULE1
(
.clk (clk),
.VAR122 (VAR122),
.VAR10 (VAR10),
.VAR30 (VAR30),
.VAR39 (VAR39),
.VAR75 (VAR75),
.VAR104 (VAR104),
.VAR54 (VAR54),
.VAR17 (VAR17)
);
assign VAR86 = VAR89;
assign VAR25 = VAR84 & VAR37;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR105 <= 0;
end
else if (VAR122)
VAR105 <= VAR25;
end
MODULE1 MODULE5
(
.VAR105 (VAR105),
.VAR106 (VAR106),
.VAR27 (VAR27),
.VAR102 (VAR102),
.VAR126 (VAR126),
.VAR11 (VAR11),
.VAR87 (VAR87)
);
assign VAR75 = (VAR43 && (VAR81 || (VAR60))) | VAR99 | VAR48;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR124 <= 0;
end
else if (VAR122)
if (VAR8)
VAR124 <= 0;
else if (~VAR5 & VAR21 && (VAR90))
VAR124 <= -1;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR116 <= 0;
end
else if (VAR122)
if (VAR8)
VAR116 <= 0;
else if (VAR57 & VAR94 & VAR52)
VAR116 <= -1;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR96 <= 0;
end
else if (VAR122)
if (VAR8)
VAR96 <= 0;
else if (VAR121)
VAR96 <= -1;
end
assign VAR48 = (VAR43 && (VAR3 || VAR90)) | VAR41 | VAR57 & VAR52;
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR52 <= 0;
end
else if (VAR122)
VAR52 <= VAR94;
end
always @(posedge clk or negedge VAR17)
begin
if (VAR17 == 0)
VAR18 <= 0;
end
else if (VAR122)
VAR18 <= VAR48;
end
assign VAR29 = VAR29;
assign VAR26 = VAR26;
assign VAR66 = VAR11;
assign VAR68 = ~VAR115;
assign VAR91 = VAR126;
assign VAR56 = {VAR98[7 : 0],
VAR98[7 : 0],
VAR98[7 : 0],
VAR98[7 : 0]};
assign VAR82 = {VAR98[15 : 0],
VAR98[15 : 0]};
assign VAR65 = VAR98[31 : 0];
assign VAR101 = ({32 {VAR32}} & VAR56) |
({32 {VAR2}} & VAR82) |
({32 {word}} & VAR65);
assign VAR89 = VAR114;
assign VAR67 = ((VAR38 & ~VAR7 & ((VAR133 == 6) || (VAR133 == 7)))) & (VAR133 != 7) & VAR123[12];
always @(posedge clk or negedge VAR109)
begin
if (VAR109 == 0)
VAR76 <= 0;
end
else if (VAR67 | VAR47)
VAR76 <= VAR83 & ~VAR47;
end
always @(posedge clk or negedge VAR109)
begin
if (VAR109 == 0)
VAR47 <= 0;
end
else if (VAR67 | VAR47)
VAR47 <= VAR76 & ~VAR47;
end
always @(posedge clk or negedge VAR109)
begin
if (VAR109 == 0)
VAR17 <= 0;
end
else
VAR17 <= ~(~VAR109 | VAR47);
end
assign VAR120 = 0;
assign VAR84 = 0;
endmodule
|
gpl-2.0
|
seyedmaysamlavasani/GorillaPP
|
apps/pageRank/build/verilog/types_float_double_grp_fu_100_ACMP_ddiv_4.v
| 1,186 |
module MODULE1(
clk,
reset,
VAR8,
VAR1,
VAR5,
VAR7,
VAR3);
input clk;
input reset;
input VAR8;
output VAR1;
input[64 - 1:0] VAR5;
input[64 - 1:0] VAR7;
output[64 - 1:0] VAR3;
MODULE2 MODULE1(
.clk(clk),
.VAR6(VAR8),
.VAR9(VAR1),
.VAR10(VAR5),
.VAR11(VAR7),
.VAR4(VAR3));
endmodule
module MODULE2(
clk,
VAR6,
VAR9,
VAR10,
VAR11,
VAR4);
input clk;
input VAR6;
output VAR9;
input[64 - 1:0] VAR10;
input[64 - 1:0] VAR11;
output[64 - 1:0] VAR4;
endmodule
|
bsd-3-clause
|
sh-chris110/chris
|
FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_smp_hps.v
| 10,056 |
module MODULE1 #(
parameter VAR2 = 0,
parameter VAR62 = 0
) (
output wire VAR18, input wire VAR11, output wire [11:0] VAR8, output wire [20:0] VAR48, output wire [3:0] VAR47, output wire [2:0] VAR56, output wire [1:0] VAR39, output wire [1:0] VAR13, output wire [3:0] VAR31, output wire [2:0] VAR52, output wire VAR16, input wire VAR30, output wire [11:0] VAR51, output wire [31:0] VAR53, output wire [3:0] VAR57, output wire VAR19, output wire VAR54, input wire VAR27, input wire [11:0] VAR25, input wire [1:0] VAR44, input wire VAR60, output wire VAR42, output wire [11:0] VAR46, output wire [20:0] VAR50, output wire [3:0] VAR6, output wire [2:0] VAR55, output wire [1:0] VAR23, output wire [1:0] VAR28, output wire [3:0] VAR7, output wire [2:0] VAR10, output wire VAR9, input wire VAR49, input wire [11:0] VAR17, input wire [31:0] VAR5, input wire [1:0] VAR20, input wire VAR15, input wire VAR38, output wire VAR45, output wire [14:0] VAR35, output wire [2:0] VAR59, output wire VAR4, output wire VAR34, output wire VAR29, output wire VAR26, output wire VAR3, output wire VAR63, output wire VAR32, output wire VAR43, inout wire [31:0] VAR41, inout wire [3:0] VAR58, inout wire [3:0] VAR22, output wire VAR40, output wire [3:0] VAR21, input wire VAR1, inout wire VAR61, inout wire VAR37, inout wire VAR24, inout wire VAR14, inout wire VAR36, inout wire VAR12, inout wire VAR33 );
generate
if (VAR2 != 0)
begin
begin
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/einvp/sky130_fd_sc_lp__einvp.pp.blackbox.v
| 1,289 |
module MODULE1 (
VAR6 ,
VAR4 ,
VAR5 ,
VAR2,
VAR1,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR7 ;
endmodule
|
apache-2.0
|
boylansr/Prop_Muse
|
P1V/P8X32A_Emulation/P8X32A_DE2_115/cog_vid.v
| 3,949 |
module MODULE1
(
input VAR26,
input VAR17,
input VAR3,
input VAR15,
input VAR24,
input [31:0] VAR25,
input [31:0] VAR10,
input [31:0] VAR30,
input [7:0] VAR28,
input VAR19,
output ack,
output [31:0] VAR16
);
reg [31:0] VAR2;
reg [31:0] VAR11;
always @(posedge VAR26 or negedge VAR3)
if (!VAR3)
VAR2 <= 32'b0;
else if (VAR15)
VAR2 <= VAR25;
always @(posedge VAR26)
if (VAR24)
VAR11 <= VAR25;
reg [7:0] VAR4;
reg [7:0] VAR23;
reg [11:0] VAR12;
reg [31:0] VAR20;
reg [31:0] VAR9;
wire enable = |VAR2[30:29];
wire VAR8 = VAR17 && enable;
wire VAR31 = VAR12 == 1'b1;
wire VAR5 = VAR23 == 1'b1;
always @(posedge VAR8)
if (VAR31)
VAR4 <= VAR11[19:12];
always @(posedge VAR8)
VAR23 <= VAR31 ? VAR11[19:12]
: VAR5 ? VAR4
: VAR23 - 1'b1;
always @(posedge VAR8)
VAR12 <= VAR31 ? VAR11[11:0]
: VAR12 - 1'b1;
always @(posedge VAR8)
if (VAR31 || VAR5)
VAR20 <= VAR31 ? VAR10
: VAR2[28] ? {VAR20[31:30], VAR20[31:2]}
: {VAR20[31], VAR20[31:1]};
always @(posedge VAR8)
if (VAR31)
VAR9 <= VAR30;
reg VAR22;
reg [1:0] VAR21;
always @(posedge VAR8 or posedge VAR21[1])
if (VAR21[1])
VAR22 <= 1'b0;
else if (VAR31)
VAR22 <= 1'b1;
always @(posedge VAR26)
if (enable)
VAR21 <= {VAR21[0], VAR22};
assign ack = VAR21[0];
reg [7:0] VAR1;
wire [31:0] VAR13 = VAR9 >> {VAR2[28] && VAR20[1], VAR20[0], 3'b000};
always @(posedge VAR8)
VAR1 <= VAR13[7:0];
reg [3:0] VAR32;
reg [3:0] VAR14;
always @(posedge VAR8)
VAR32 <= VAR32 + 1'b1;
wire [3:0] VAR33 = VAR1[7:4] + VAR32;
wire [2:0] VAR18 = VAR1[2:0] + { VAR1[3] && VAR33[3],
VAR1[3] && VAR33[3],
VAR1[3] };
always @(posedge VAR8)
VAR14 <= {VAR1[3] && VAR33[3], VAR2[26] ? VAR18 : VAR1[2:0]};
reg [2:0] VAR6;
always @(posedge VAR8)
VAR6 <= VAR2[27] ? VAR18 : VAR1[2:0];
wire [15:0][2:0] VAR7 = 48'b011100100101101110110111011011010010001001000000;
wire [3:0] VAR29 = {VAR19 ^ VAR28[VAR2[25:23]], VAR7[{VAR19, VAR6}]};
wire [7:0] VAR27 = VAR2[30] ? VAR2[29] ? {VAR14, VAR29}
: {VAR29, VAR14}
: VAR1;
assign VAR16 = enable ? {24'b0, VAR27 & VAR2[7:0]} << {VAR2[10:9], 3'b000} : 32'b0;
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.behavioral.v
| 1,027 |
module MODULE1( );
VAR3 VAR1();
VAR3 VAR2();
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dfrtp/sky130_fd_sc_hd__dfrtp.symbol.v
| 1,395 |
module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7,
input VAR8
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o2111ai/sky130_fd_sc_hd__o2111ai.behavioral.v
| 1,610 |
module MODULE1 (
VAR6 ,
VAR5,
VAR11,
VAR10,
VAR4,
VAR7
);
output VAR6 ;
input VAR5;
input VAR11;
input VAR10;
input VAR4;
input VAR7;
supply1 VAR8;
supply0 VAR15;
supply1 VAR13 ;
supply0 VAR14 ;
wire VAR2 ;
wire VAR3;
or VAR9 (VAR2 , VAR11, VAR5 );
nand VAR12 (VAR3, VAR4, VAR10, VAR7, VAR2);
buf VAR1 (VAR6 , VAR3 );
endmodule
|
apache-2.0
|
GSejas/Karatsuba_FPU
|
FPGA_FLOW/Karat/source/rtl/Round_Sgf_Dec.v
| 1,907 |
module MODULE1(
input wire [1:0] VAR4,
input wire [1:0] VAR2,
input wire VAR3,
output reg VAR1
);
always @*
case ({VAR3,VAR2,VAR4})
5'b10101: VAR1 <=1;
5'b10110: VAR1 <=1;
5'b10111: VAR1 <=1;
5'b01001: VAR1 <=1;
5'b01010: VAR1 <=1;
5'b01011: VAR1 <=1;
default: VAR1 <=0;
endcase
endmodule
|
gpl-3.0
|
combinatorylogic/soc
|
backends/small1/hw/rtl/3rdparty/arbiter.v
| 3,846 |
module MODULE1 (
clk,
rst,
VAR1,
VAR2,
VAR6,
VAR11,
VAR9,
VAR3,
VAR20,
VAR13
);
input clk;
input rst;
input VAR1;
input VAR2;
input VAR6;
input VAR11;
output VAR9;
output VAR3;
output VAR20;
output VAR13;
wire [1:0] VAR15 ;
wire VAR14 ;
wire VAR4 ;
wire [1:0] VAR16 ;
wire VAR12 ;
reg VAR10 ;
reg VAR18 ;
reg VAR21 ;
reg VAR7 ;
reg VAR5 ;
reg VAR8 ;
reg VAR17 ;
reg VAR19 ;
always @ (posedge clk)
if (rst) begin
VAR10 <= 0;
VAR18 <= 0;
VAR21 <= 0;
VAR7 <= 0;
end else begin
VAR10 <=(~VAR12 & ~VAR17 & ~VAR8 & ~VAR1 & ~VAR2 & ~VAR6 & VAR11)
| (~VAR12 & ~VAR17 & VAR8 & ~VAR1 & ~VAR2 & VAR11)
| (~VAR12 & VAR17 & ~VAR8 & ~VAR1 & VAR11)
| (~VAR12 & VAR17 & VAR8 & VAR11 )
| ( VAR12 & VAR10 );
VAR18 <=(~VAR12 & ~VAR17 & ~VAR8 & VAR6)
| (~VAR12 & ~VAR17 & VAR8 & ~VAR1 & ~VAR2 & VAR6 & ~VAR11)
| (~VAR12 & VAR17 & ~VAR8 & ~VAR1 & VAR6 & ~VAR11)
| (~VAR12 & VAR17 & VAR8 & VAR6 & ~VAR11)
| ( VAR12 & VAR18);
VAR21 <=(~VAR12 & ~VAR17 & ~VAR8 & VAR2 & ~VAR6)
| (~VAR12 & ~VAR17 & VAR8 & VAR2)
| (~VAR12 & VAR17 & ~VAR8 & ~VAR1 & VAR2 & ~VAR6 & ~VAR11)
| (~VAR12 & VAR17 & VAR8 & VAR2 & ~VAR6 & ~VAR11)
| ( VAR12 & VAR21);
VAR7 <=(~VAR12 & ~VAR17 & ~VAR8 & VAR1 & ~VAR2 & ~VAR6)
| (~VAR12 & ~VAR17 & VAR8 & VAR1 & ~VAR2)
| (~VAR12 & VAR17 & ~VAR8 & VAR1)
| (~VAR12 & VAR17 & VAR8 & VAR1 & ~VAR2 & ~VAR6 & ~VAR11)
| ( VAR12 & VAR7);
end
assign VAR4 = (VAR1 | VAR2 | VAR6 | VAR11) & ~VAR12;
always @ (posedge clk)
begin
VAR5 <= (VAR4 & ~VAR19 & ~VAR5);
VAR19 <= (VAR4 & ~VAR19 & VAR5)
| (VAR4 & VAR19 & ~VAR5);
end
assign VAR12 = ( VAR1 & VAR7 )
| ( VAR2 & VAR21 )
| ( VAR6 & VAR18 )
| ( VAR11 & VAR10 );
assign VAR16 = {(VAR7 | VAR21),(VAR7 | VAR18)};
always @ (posedge clk )
if( rst ) begin
VAR17 <= 0;
VAR8 <= 0;
end else if(VAR5) begin
VAR17 <= VAR16[1];
VAR8 <= VAR16[0];
end else begin
VAR17 <= VAR17;
VAR8 <= VAR8;
end
assign VAR14 = VAR12;
assign VAR15 = VAR16;
assign VAR9 = VAR7;
assign VAR3 = VAR21;
assign VAR20 = VAR18;
assign VAR13 = VAR10;
endmodule
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/logicblock_counter.v
| 1,779 |
module MODULE1(VAR4, VAR2, VAR7, VAR8,
VAR6, VAR3, VAR1, VAR5);
parameter VAR9 = 32;
input VAR4, VAR2;
input VAR7;
input [VAR9-1:0] VAR8;
output [VAR9-1:0] VAR6;
output VAR3;
input VAR1;
input VAR5;
reg [VAR9-1:0] counter;
always @(posedge VAR4 or negedge VAR2)
begin
if (~VAR2)
begin
counter <= 32'h00000000;
end
else
begin
if (VAR5)
begin
counter <= {VAR9{1'b0}};
end
else if (VAR7 && ~VAR1 && counter < VAR8)
begin
counter <= counter + 1;
end
end
end
assign VAR6 = counter;
assign VAR3 = VAR7 && !VAR5 && (counter < VAR8);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.symbol.v
| 1,331 |
module MODULE1 (
input VAR6,
input VAR3,
input VAR1,
input VAR7,
output VAR4 ,
input VAR2,
input VAR5
);
endmodule
|
apache-2.0
|
fallen/milkymist-mmu
|
cores/hpdmc_ddr32/rtl/hpdmc_mgmt.v
| 8,893 |
module MODULE1 #(
parameter VAR14 = 26,
parameter VAR47 = 9
) (
input VAR13,
input VAR12,
input [2:0] VAR23,
input [2:0] VAR27,
input [10:0] VAR36,
input [3:0] VAR43,
input VAR51,
input VAR11,
input [VAR14-3-1:0] address,
output reg ack,
output reg read,
output reg write,
output [3:0] VAR45,
input VAR5,
input VAR22,
input [3:0] VAR48,
output VAR40,
output VAR28,
output VAR3,
output VAR33,
output [12:0] VAR35,
output [1:0] VAR34
);
parameter VAR26 = VAR14-2-1-(VAR47+2)+1;
wire [VAR14-2-1:0] VAR20 = {address, 1'b0};
wire [VAR47-1:0] VAR29 = VAR20[VAR47-1:0];
wire [1:0] VAR24 = VAR20[VAR47+1:VAR47];
wire [VAR26-1:0] VAR16 = VAR20[VAR14-2-1:VAR47+2];
reg [3:0] VAR49;
always @ begin
VAR46 = state;
VAR6 = 1'b0;
VAR39 = 1'b0;
VAR19 = 1'b0;
VAR18 = 1'b0;
VAR25 = 1'b0;
VAR7 = 1'b0;
VAR44 = 1'b0;
VAR52 = 1'b0;
VAR17 = 1'b0;
VAR9 = 1'b0;
VAR30 = 1'b0;
VAR2 = 4'b0000;
VAR32 = 4'b0000;
read = 1'b0;
write = 1'b0;
ack = 1'b0;
case(state)
VAR53: begin
if(VAR42)
VAR46 = VAR37;
end
else begin
if(VAR51) begin
if(VAR21) begin
if(VAR11) begin
if(VAR22) begin
VAR25 = 1'b1;
VAR52 = 1'b0;
VAR44 = 1'b1;
VAR7 = 1'b1;
VAR9 = 1'b1;
write = 1'b1;
ack = 1'b1;
end
end else begin
if(VAR5) begin
VAR25 = 1'b1;
VAR52 = 1'b0;
VAR44 = 1'b1;
VAR7 = 1'b0;
VAR9 = 1'b1;
read = 1'b1;
ack = 1'b1;
end
end
end else begin
if(VAR10) begin
if(VAR41) begin
VAR25 = 1'b1;
VAR52 = 1'b1;
VAR44 = 1'b0;
VAR7 = 1'b1;
VAR2 = VAR49;
VAR6 = 1'b1;
VAR46 = VAR50;
end
end else begin
VAR25 = 1'b1;
VAR52 = 1'b1;
VAR44 = 1'b0;
VAR7 = 1'b0;
VAR17 = 1'b1;
VAR32 = VAR49;
VAR39 = 1'b1;
if(VAR11)
VAR46 = VAR1;
end
else
VAR46 = VAR54;
end
end
end
end
end
VAR50: begin
if(VAR4) begin
VAR25 = 1'b1;
VAR52 = 1'b1;
VAR44 = 1'b0;
VAR7 = 1'b0;
VAR17 = 1'b1;
VAR32 = VAR49;
VAR39 = 1'b1;
if(VAR11)
VAR46 = VAR1;
end
else
VAR46 = VAR54;
end
end
VAR54: begin
if(VAR31) begin
if(VAR5) begin
VAR25 = 1'b1;
VAR52 = 1'b0;
VAR44 = 1'b1;
VAR7 = 1'b0;
VAR9 = 1'b1;
read = 1'b1;
ack = 1'b1;
VAR46 = VAR53;
end
end
end
VAR1: begin
if(VAR31) begin
if(VAR22) begin
VAR25 = 1'b1;
VAR52 = 1'b0;
VAR44 = 1'b1;
VAR7 = 1'b1;
VAR9 = 1'b1;
write = 1'b1;
ack = 1'b1;
VAR46 = VAR53;
end
end
end
VAR37: begin
if(VAR48 == 4'b1111) begin
VAR25 = 1'b1;
VAR52 = 1'b1;
VAR44 = 1'b0;
VAR7 = 1'b1;
VAR30 = 1'b1;
VAR6 = 1'b1;
VAR2 = 4'b1111;
VAR46 = VAR8;
end
end
VAR8: begin
if(VAR4) begin
VAR25 = 1'b1;
VAR52 = 1'b1;
VAR44 = 1'b1;
VAR7 = 1'b0;
VAR19 = 1'b1;
VAR18 = 1'b1;
VAR46 = VAR38;
end
end
VAR38: begin
if(VAR15)
VAR46 = VAR53;
end
endcase
end
endmodule
|
lgpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.behavioral.v
| 1,188 |
module MODULE1( VAR6, VAR1, VAR4 );
input VAR4, VAR6;
output VAR1;
VAR3 VAR5(.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR2(.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/bufinv/sky130_fd_sc_lp__bufinv_16.v
| 2,050 |
module MODULE2 (
VAR1 ,
VAR3 ,
VAR4,
VAR8,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR2 ;
VAR5 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR4;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR2 ;
VAR5 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o32a/sky130_fd_sc_hs__o32a.functional.v
| 2,080 |
module MODULE1 (
VAR4,
VAR14,
VAR3 ,
VAR11 ,
VAR8 ,
VAR10 ,
VAR16 ,
VAR9
);
input VAR4;
input VAR14;
output VAR3 ;
input VAR11 ;
input VAR8 ;
input VAR10 ;
input VAR16 ;
input VAR9 ;
wire VAR16 VAR7 ;
wire VAR16 VAR17 ;
wire VAR1 ;
wire VAR13;
or VAR5 (VAR7 , VAR8, VAR11, VAR10 );
or VAR12 (VAR17 , VAR9, VAR16 );
and VAR6 (VAR1 , VAR7, VAR17 );
VAR15 VAR2 (VAR13, VAR1, VAR4, VAR14);
buf VAR18 (VAR3 , VAR13 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a21bo/sky130_fd_sc_ms__a21bo.blackbox.v
| 1,383 |
module MODULE1 (
VAR6 ,
VAR7 ,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR3;
supply1 VAR2;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
yipenghuang0302/csee4840_14
|
software/peripheral/synthesis/submodules/altera_avalon_st_clock_crosser.v
| 5,029 |
module MODULE1(
VAR29,
VAR15,
VAR21,
VAR8,
VAR31,
VAR7,
VAR9,
VAR27,
VAR19,
VAR13
);
parameter VAR18 = 1;
parameter VAR6 = 8;
parameter VAR23 = 2;
parameter VAR17 = 2;
parameter VAR24 = 1;
localparam VAR28 = VAR18 * VAR6;
input VAR29;
input VAR15;
output VAR21;
input VAR8;
input [VAR28-1:0] VAR31;
input VAR7;
input VAR9;
input VAR27;
output VAR19;
output [VAR28-1:0] VAR13;
reg [VAR28-1:0] VAR20;
reg [VAR28-1:0] VAR10;
reg VAR3;
wire VAR25;
wire VAR12;
reg VAR26;
wire VAR1;
wire VAR2;
wire VAR14;
wire VAR11;
assign VAR21 = ~(VAR25 ^ VAR3);
assign VAR1 = VAR8 & VAR21;
assign VAR14 = VAR12 ^ VAR26;
assign VAR2 = VAR11 & VAR14;
always @(posedge VAR29 or posedge VAR15) begin
if (VAR15) begin
VAR20 <= 'b0;
VAR3 <= 1'b0;
end else begin
if (VAR1) begin
VAR3 <= ~VAR3;
VAR20 <= VAR31;
end
end end
always @(posedge VAR7 or posedge VAR9) begin
if (VAR9) begin
VAR26 <= 1'b0;
VAR10 <= 'b0;
end else begin
VAR10 <= VAR20;
if (VAR2) begin
VAR26 <= VAR12;
end
end end
VAR5 #(.VAR22(VAR23)) VAR32 (
.clk(VAR7),
.VAR30(~VAR9),
.din(VAR3),
.dout(VAR12)
);
VAR5 #(.VAR22(VAR17)) VAR16 (
.clk(VAR29),
.VAR30(~VAR15),
.din(VAR26),
.dout(VAR25)
);
generate if (VAR24 == 1) begin
VAR33
.VAR6(VAR6),
.VAR18(VAR18)
) VAR4 (
.clk(VAR7),
.reset(VAR9),
.VAR21(VAR11),
.VAR8(VAR14),
.VAR31(VAR10),
.VAR27(VAR27),
.VAR19(VAR19),
.VAR13(VAR13)
);
end else begin
assign VAR19 = VAR14;
assign VAR11 = VAR27;
assign VAR13 = VAR10;
end
endgenerate
endmodule
|
mit
|
asicguy/gplgpu
|
hdl/lucy_tc/de3d_tc_mc_sigs.v
| 10,601 |
module MODULE1
(
input VAR22, input VAR1, input VAR35, input [3:0] VAR30, input VAR4, input VAR17, input [3:0] VAR19, input [8:0] VAR13, input [8:0] VAR27, input [8:0] VAR23, input [8:0] VAR2, input [8:0] VAR12, input [8:0] VAR34, input [8:0] VAR37, input [8:0] VAR28, input [2:0] VAR14, input [3:0] VAR15,
output reg VAR24, output reg VAR36, output reg [7:0] VAR32 );
wire VAR26 = VAR15[3];
wire VAR31 = VAR15[2];
wire VAR29 = VAR15[1];
wire VAR21 = VAR15[0];
reg VAR3;
reg VAR11;
reg VAR8;
reg VAR9;
reg [3:0] VAR5;
reg [3:0] VAR18;
reg VAR20;
reg VAR25;
reg [1:0] VAR33;
always @(posedge VAR22 or negedge VAR1)
begin
if(!VAR1) VAR5 <= 4'b0000;
end
else if(VAR35) VAR5 <= VAR30;
end
always @(posedge VAR22 or negedge VAR1)
begin
if(!VAR1)VAR3 <= 0;
end
else if(VAR35) VAR3 <= ~VAR3;
end
always @(posedge VAR4) VAR11 <= VAR3;
always @(posedge VAR4) VAR8 <= VAR11;
always @* VAR9 = VAR8 ^ VAR11;
always @(posedge VAR22) VAR20 <= VAR18[3];
always @(posedge VAR22) VAR25 <= VAR20;
always @* VAR24 = ~VAR25 & VAR20;
always @(posedge VAR4 or negedge VAR1)
begin
if(!VAR1)VAR18 <= 4'b0000;
end
else if(VAR9)VAR18 <= VAR5;
else if(VAR17)VAR18 <= VAR18 + 4'b0001;
end
always @* begin
casex({VAR19, VAR18[2:1]})
6'VAR6: VAR33 = 2'b00; 6'VAR16: VAR33 = 2'b01; 6'VAR7: VAR33 = 2'b10; 6'VAR10: VAR33 = 2'b11; 6'b001110: VAR33 = 2'b10; 6'b001111: VAR33 = 2'b11; 6'b010110: VAR33 = 2'b01; 6'b010111: VAR33 = 2'b11; 6'b011010: VAR33 = 2'b01; 6'b011011: VAR33 = 2'b10; 6'b100110: VAR33 = 2'b00; 6'b100111: VAR33 = 2'b11; 6'b101010: VAR33 = 2'b00; 6'b101011: VAR33 = 2'b10; 6'b110010: VAR33 = 2'b00; 6'b110011: VAR33 = 2'b01; 6'b011101: VAR33 = 2'b01; 6'b011110: VAR33 = 2'b10; 6'b011111: VAR33 = 2'b11; 6'b101101: VAR33 = 2'b00; 6'b101110: VAR33 = 2'b10; 6'b101111: VAR33 = 2'b11; 6'b110101: VAR33 = 2'b00; 6'b110110: VAR33 = 2'b01; 6'b110111: VAR33 = 2'b11; 6'b111001: VAR33 = 2'b00; 6'b111010: VAR33 = 2'b01; 6'b111011: VAR33 = 2'b10; 6'b111100: VAR33 = 2'b00; 6'b111101: VAR33 = 2'b01; 6'b111110: VAR33 = 2'b10; 6'b111111: VAR33 = 2'b11; default: VAR33 = 2'b00; endcase
end
always @* begin
case (VAR33)
2'b00: begin
VAR36 = VAR27[0];
case (VAR14)
3: begin VAR32 = {VAR26,VAR27[5:0],VAR13[5]};
end
5: begin VAR32 = {VAR26,VAR27[3:0],VAR13[5:3]};
end
default: begin VAR32 = {VAR26,VAR27[4:0],VAR13[5:4]};
end
endcase
end
2'b01: begin
VAR36 = VAR2[0];
case (VAR14)
3: begin VAR32 = {VAR31,VAR2[5:0],VAR23[5]};
end
5: begin VAR32 = {VAR31,VAR2[3:0],VAR13[5:3]};
end
default: begin VAR32 = {VAR31,VAR2[4:0],VAR23[5:4]};
end
endcase
end
2'b10: begin
VAR36 = VAR34[0];
case (VAR14)
3: begin VAR32 = {VAR29,VAR34[5:0],VAR12[5]};
end
5: begin VAR32 = {VAR29,VAR34[3:0],VAR12[5:3]};
end
default: begin VAR32 = {VAR29,VAR34[4:0],VAR12[5:4]};
end
endcase
end
2'b11: begin
VAR36 = VAR28[0];
case (VAR14)
3: begin VAR32 = {VAR21,VAR28[5:0],VAR37[5]};
end
5: begin VAR32 = {VAR21,VAR28[3:0],VAR37[5:3]};
end
default: begin VAR32 = {VAR21,VAR28[4:0],VAR37[5:4]};
end
endcase
end
endcase
end
endmodule
|
gpl-3.0
|
asicguy/gplgpu
|
hdl/altera_ddr3/ddr3_int_example_top_5.v
| 7,205 |
module MODULE1 (
VAR14,
VAR20,
VAR22,
VAR71,
VAR4,
VAR30,
VAR33,
VAR53,
VAR65,
VAR32,
VAR19,
VAR50,
VAR67,
VAR47,
VAR18,
VAR28,
VAR44,
VAR10,
VAR46,
VAR54,
VAR56
)
;
output [ 13: 0] VAR22;
output [ 2: 0] VAR71;
output VAR4;
output [ 0: 0] VAR30;
inout [ 0: 0] VAR33;
inout [ 0: 0] VAR53;
output [ 0: 0] VAR65;
output [ 3: 0] VAR32;
inout [ 31: 0] VAR19;
inout [ 3: 0] VAR50;
inout [ 3: 0] VAR67;
output [ 0: 0] VAR47;
output VAR18;
output VAR28;
output VAR44;
output VAR10;
output [ 15: 0] VAR46;
output VAR54;
output [ 7: 0] VAR56;
input VAR14;
input VAR20;
wire [ 0: 0] VAR51;
wire VAR7;
wire [ 5: 0] VAR12;
wire VAR15;
wire [ 13: 0] VAR22;
wire VAR26;
wire VAR55;
wire [ 2: 0] VAR71;
wire VAR4;
wire [ 0: 0] VAR30;
wire [ 0: 0] VAR33;
wire [ 0: 0] VAR53;
wire [ 0: 0] VAR65;
wire [ 3: 0] VAR32;
wire [ 31: 0] VAR19;
wire [ 3: 0] VAR50;
wire [ 3: 0] VAR67;
wire [ 24: 0] VAR40;
wire [ 15: 0] VAR48;
wire [ 9: 0] VAR13;
wire VAR38;
wire [127: 0] VAR24;
wire VAR59;
wire VAR23;
wire VAR61;
wire [ 6: 0] VAR17;
wire [127: 0] VAR3;
wire VAR11;
wire [ 0: 0] VAR47;
wire VAR18;
wire VAR28;
wire VAR44;
wire VAR2;
wire VAR10;
wire [ 15: 0] VAR46;
wire VAR21;
wire VAR54;
wire [ 7: 0] VAR56;
wire VAR39;
wire VAR72;
assign VAR65 = VAR51;
assign VAR39 = 1'b1;
assign VAR72 = 1'b0;
VAR52 VAR1
(
.VAR6 (VAR26),
.VAR34 (VAR55),
.VAR43 (VAR7),
.VAR45 (VAR12),
.VAR20 (VAR20),
.VAR8 (VAR40),
.VAR35 (VAR48),
.VAR9 (VAR15),
.VAR27 (),
.VAR49 (VAR24),
.VAR64 (VAR59),
.VAR70 (VAR23),
.VAR41 (VAR61),
.VAR42 (),
.VAR57 (VAR17),
.VAR60 (VAR3),
.VAR58 (),
.VAR5 (VAR11),
.VAR22 (VAR22[13 : 0]),
.VAR71 (VAR71),
.VAR4 (VAR4),
.VAR30 (VAR30),
.VAR33 (VAR33),
.VAR53 (VAR53),
.VAR65 (VAR51),
.VAR32 (VAR32[3 : 0]),
.VAR19 (VAR19),
.VAR50 (VAR50[3 : 0]),
.VAR67 (VAR67[3 : 0]),
.VAR47 (VAR47),
.VAR18 (VAR18),
.VAR28 (VAR28),
.VAR44 (VAR44),
.VAR2 (VAR2),
.VAR63 (VAR14),
.VAR21 (VAR21),
.VAR36 (),
.VAR68 (VAR39)
);
assign VAR40[7 : 0] = VAR13[9 : 2];
VAR16 VAR31
(
.clk (VAR2),
.VAR66 (VAR40[24 : 22]),
.VAR35 (VAR48),
.VAR9 (VAR15),
.VAR25 (VAR13),
.VAR69 (VAR38),
.VAR49 (VAR24),
.VAR64 (VAR59),
.VAR70 (VAR23),
.VAR41 (VAR61),
.VAR37 (VAR40[21 : 8]),
.VAR57 (VAR17),
.VAR60 (VAR3),
.VAR5 (VAR11),
.VAR46 (VAR46[15 : 0]),
.VAR62 (VAR10),
.VAR29 (VAR21),
.VAR54 (VAR54),
.VAR56 (VAR56)
);
endmodule
|
gpl-3.0
|
peteasa/parallella-fpga
|
AdiHDLLib/library/common/up_hdmi_rx.v
| 10,614 |
module MODULE1 (
VAR28,
VAR50,
VAR69,
VAR1,
VAR5,
VAR54,
VAR34,
VAR21,
VAR4,
VAR49,
VAR60,
VAR29,
VAR64,
VAR61,
VAR53,
VAR70,
VAR39,
VAR24,
VAR44,
VAR71,
VAR35,
VAR59,
VAR38,
VAR7,
VAR58,
VAR22,
VAR36,
VAR25);
localparam VAR62 = 32'h00040063;
parameter VAR14 = 0;
input VAR28;
output VAR50;
output VAR69;
output VAR1;
output VAR5;
output VAR54;
output [15:0] VAR34;
output [15:0] VAR21;
input VAR4;
input VAR49;
input VAR60;
input VAR29;
input VAR64;
input VAR61;
input VAR53;
input [15:0] VAR70;
input [15:0] VAR39;
input [31:0] VAR24;
input VAR44;
input VAR71;
input VAR35;
input [13:0] VAR59;
input [31:0] VAR38;
output VAR7;
input VAR58;
input [13:0] VAR22;
output [31:0] VAR36;
output VAR25;
reg VAR41 = 'd0;
reg VAR31 = 'd0;
reg VAR7 = 'd0;
reg [31:0] VAR46 = 'd0;
reg VAR52 = 'd0;
reg VAR3 = 'd0;
reg VAR26 = 'd0;
reg VAR66 = 'd0;
reg VAR42 = 'd0;
reg VAR15 = 'd0;
reg VAR75 = 'd0;
reg VAR40 = 'd0;
reg VAR74 = 'd0;
reg VAR57 = 'd0;
reg VAR11 = 'd0;
reg [15:0] VAR16 = 'd0;
reg [15:0] VAR51 = 'd0;
reg VAR25 = 'd0;
reg [31:0] VAR36 = 'd0;
wire VAR37;
wire VAR68;
wire VAR67;
wire VAR32;
wire VAR63;
wire VAR65;
wire VAR27;
wire VAR23;
wire [15:0] VAR43;
wire [15:0] VAR2;
wire [31:0] VAR30;
assign VAR37 = (VAR59[13:12] == 2'd0) ? VAR35 : 1'b0;
assign VAR68 = (VAR22[13:12] == 2'd0) ? VAR58 : 1'b0;
always @(negedge VAR44 or posedge VAR71) begin
if (VAR44 == 0) begin
VAR41 <= 1'd1;
VAR31 <= 'd0;
VAR7 <= 'd0;
VAR46 <= 'd0;
VAR52 <= 'd0;
VAR3 <= 'd0;
VAR26 <= 'd0;
VAR66 <= 'd0;
VAR42 <= 'd0;
VAR15 <= 'd0;
VAR75 <= 'd0;
VAR40 <= 'd0;
VAR74 <= 'd0;
VAR57 <= 'd0;
VAR11 <= 'd0;
VAR16 <= 'd0;
VAR51 <= 'd0;
end else begin
VAR7 <= VAR37;
VAR41 <= ~VAR31;
if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h002)) begin
VAR46 <= VAR38;
end
if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h010)) begin
VAR31 <= VAR38[0];
end
if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h011)) begin
VAR52 <= VAR38[3];
VAR3 <= VAR38[2];
VAR26 <= VAR38[1];
VAR66 <= VAR38[0];
end
if (VAR67 == 1'b1) begin
VAR42 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h018)) begin
VAR42 <= VAR42 & ~VAR38[1];
end
if (VAR32 == 1'b1) begin
VAR15 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h018)) begin
VAR15 <= VAR15 & ~VAR38[0];
end
if (VAR19 == 1'b1) begin
VAR75 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h019)) begin
VAR75 <= VAR75 & ~VAR38[1];
end
if (VAR63 == 1'b1) begin
VAR40 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h020)) begin
VAR40 <= VAR40 & ~VAR38[3];
end
if (VAR65 == 1'b1) begin
VAR74 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h020)) begin
VAR74 <= VAR74 & ~VAR38[2];
end
if (VAR27 == 1'b1) begin
VAR57 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h020)) begin
VAR57 <= VAR57 & ~VAR38[1];
end
if (VAR23 == 1'b1) begin
VAR11 <= 1'b1;
end else if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h020)) begin
VAR11 <= VAR11 & ~VAR38[0];
end
if ((VAR37 == 1'b1) && (VAR59[11:0] == 12'h100)) begin
VAR16 <= VAR38[31:16];
VAR51 <= VAR38[15:0];
end
end
end
always @(negedge VAR44 or posedge VAR71) begin
if (VAR44 == 1'b0) begin
VAR25 <= 'd0;
VAR36 <= 'd0;
end else begin
VAR25 <= VAR68;
if(VAR68 == 1'b1) begin
case (VAR22[11:0])
12'h000: VAR36 <= VAR62;
12'h001: VAR36 <= VAR14;
12'h002: VAR36 <= VAR46;
12'h010: VAR36 <= {31'h0, VAR31};
12'h011: VAR36 <= {28'h0, VAR52, VAR3, VAR26, VAR66};
12'h015: VAR36 <= VAR30;
12'h016: VAR36 <= VAR24;
12'h018: VAR36 <= {30'h0, VAR42, VAR15};
12'h019: VAR36 <= {30'h0, VAR75, 1'b0};
12'h020: VAR36 <= {28'h0, VAR40, VAR74,
VAR57, VAR11};
12'h100: VAR36 <= {VAR16, VAR51};
12'h101: VAR36 <= {VAR43, VAR2};
default: VAR36 <= 0;
endcase
end
end
end
VAR56 VAR76 (
.VAR8 (VAR41),
.clk (VAR28),
.rst (VAR50));
VAR73 #(.VAR55(36)) VAR72 (
.VAR44 (VAR44),
.VAR71 (VAR71),
.VAR18 ({ VAR52,
VAR3,
VAR26,
VAR66,
VAR16,
VAR51}),
.VAR13 (),
.VAR17 (VAR50),
.VAR20 (VAR28),
.VAR47 ({ VAR69,
VAR1,
VAR5,
VAR54,
VAR34,
VAR21}));
VAR9 #(.VAR55(39)) VAR10 (
.VAR44 (VAR44),
.VAR71 (VAR71),
.VAR45 ({ VAR67,
VAR32,
VAR19,
VAR63,
VAR65,
VAR27,
VAR23,
VAR43,
VAR2}),
.VAR17 (VAR50),
.VAR20 (VAR28),
.VAR48 ({ VAR4,
VAR49,
VAR60,
VAR29,
VAR64,
VAR61,
VAR53,
VAR70,
VAR39}));
VAR12 VAR6 (
.VAR44 (VAR44),
.VAR71 (VAR71),
.VAR33 (VAR30),
.VAR17 (VAR50),
.VAR20 (VAR28));
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.v
| 2,440 |
module MODULE1 (
VAR8,
VAR1 ,
VAR7 ,
VAR5 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR9
);
input VAR8;
input VAR1 ;
input VAR7 ;
output VAR5 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
VAR6 VAR4 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR8,
VAR1 ,
VAR7 ,
VAR5 ,
VAR10 ,
VAR2
);
input VAR8;
input VAR1 ;
input VAR7 ;
output VAR5 ;
input VAR10 ;
input VAR2 ;
supply1 VAR3;
supply0 VAR9;
VAR6 VAR4 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/nand2b/sky130_fd_sc_ls__nand2b_2.v
| 2,147 |
module MODULE2 (
VAR9 ,
VAR5 ,
VAR6 ,
VAR8,
VAR2,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR7 ;
input VAR1 ;
VAR3 VAR4 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR9 ,
VAR5,
VAR6
);
output VAR9 ;
input VAR5;
input VAR6 ;
supply1 VAR8;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR1 ;
VAR3 VAR4 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
hitomi2500/wasca
|
fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_wrapper.v
| 9,389 |
module MODULE1 (
VAR57,
VAR38,
clk,
VAR35,
VAR55,
VAR21,
VAR9,
VAR14,
VAR25,
VAR24,
VAR50,
VAR41,
VAR3,
VAR7,
VAR32,
VAR56,
VAR45,
VAR26,
VAR4,
VAR44,
VAR37,
VAR43,
VAR11,
VAR12,
VAR16,
VAR8,
VAR40,
VAR17,
VAR22,
VAR34,
VAR18,
VAR46,
VAR42
)
;
output [ 37: 0] VAR37;
output VAR43;
output VAR11;
output VAR12;
output VAR16;
output VAR8;
output VAR40;
output VAR17;
output VAR22;
output VAR34;
output VAR18;
output VAR46;
output VAR42;
input [ 31: 0] VAR57;
input [ 31: 0] VAR38;
input clk;
input VAR35;
input VAR55;
input VAR21;
input VAR9;
input VAR14;
input VAR25;
input VAR24;
input VAR50;
input VAR41;
input VAR3;
input [ 35: 0] VAR7;
input VAR32;
input [ 6: 0] VAR56;
input VAR45;
input VAR26;
input VAR4;
input VAR44;
wire [ 37: 0] VAR37;
wire VAR43;
wire [ 37: 0] VAR33;
wire VAR11;
wire VAR12;
wire VAR16;
wire VAR8;
wire VAR40;
wire VAR17;
wire VAR22;
wire VAR34;
wire VAR18;
wire VAR46;
wire VAR42;
wire VAR29;
wire [ 1: 0] VAR2;
wire [ 1: 0] VAR6;
wire VAR15;
wire VAR52;
wire VAR19;
wire VAR39;
wire VAR48;
wire VAR23;
wire VAR28;
VAR10 VAR53
(
.VAR57 (VAR57),
.VAR38 (VAR38),
.VAR35 (VAR35),
.VAR55 (VAR55),
.VAR21 (VAR21),
.VAR9 (VAR9),
.VAR14 (VAR14),
.VAR36 (VAR2),
.VAR5 (VAR6),
.VAR43 (VAR43),
.VAR13 (VAR15),
.VAR25 (VAR25),
.VAR24 (VAR24),
.VAR50 (VAR50),
.VAR41 (VAR41),
.VAR33 (VAR33),
.VAR11 (VAR11),
.VAR31 (VAR19),
.VAR51 (VAR39),
.VAR27 (VAR48),
.VAR3 (VAR3),
.VAR7 (VAR7),
.VAR32 (VAR32),
.VAR56 (VAR56),
.VAR45 (VAR45),
.VAR26 (VAR26),
.VAR4 (VAR4),
.VAR44 (VAR44),
.VAR54 (VAR29),
.VAR30 (VAR52),
.VAR20 (VAR28)
);
VAR47 VAR1
(
.clk (clk),
.VAR36 (VAR2),
.VAR37 (VAR37),
.VAR33 (VAR33),
.VAR12 (VAR12),
.VAR16 (VAR16),
.VAR8 (VAR8),
.VAR40 (VAR40),
.VAR17 (VAR17),
.VAR22 (VAR22),
.VAR34 (VAR34),
.VAR18 (VAR18),
.VAR46 (VAR46),
.VAR42 (VAR42),
.VAR49 (VAR23),
.VAR20 (VAR28)
);
assign VAR19 = 1'b0;
assign VAR39 = 1'b0;
assign VAR52 = 1'b0;
assign VAR29 = 1'b0;
assign VAR15 = 1'b0;
assign VAR28 = 1'b0;
assign VAR23 = 1'b0;
assign VAR2 = 2'b0;
endmodule
|
gpl-2.0
|
lkesteloot/alice
|
alice4/fpga/Alice4-DE0-Nano-SoC/LCD_debug.v
| 1,888 |
module MODULE1(
input wire [6:0] VAR13,
input wire [5:0] VAR7,
input wire [31:0] VAR4,
input wire [31:0] VAR12,
input wire [31:0] VAR9,
output reg [6:0] VAR3
);
reg [31:0] VAR2;
reg [3:0] VAR5;
wire [6:0] VAR6;
VAR10 VAR8(
.VAR11(VAR5),
.VAR6(VAR6)
);
reg VAR1;
always @ begin
case (VAR13)
7'd0: { VAR1, VAR5 } = { 1'b1, VAR2[31:28] };
7'd1: { VAR1, VAR5 } = { 1'b1, VAR2[27:24] };
7'd2: { VAR1, VAR5 } = { 1'b1, VAR2[23:20] };
7'd3: { VAR1, VAR5 } = { 1'b1, VAR2[19:16] };
7'd5: { VAR1, VAR5 } = { 1'b1, VAR2[15:12] };
7'd6: { VAR1, VAR5 } = { 1'b1, VAR2[11:8] };
7'd7: { VAR1, VAR5 } = { 1'b1, VAR2[7:4] };
7'd8: { VAR1, VAR5 } = { 1'b1, VAR2[3:0] };
default: { VAR1, VAR5 } = { 1'b0, 4'h0 };
endcase
end
always @(*) begin
if (VAR7 == 6'd0) begin
case (VAR13)
7'd0: VAR3 = 7'h41;
7'd1: VAR3 = 7'h6C;
7'd2: VAR3 = 7'h69;
7'd3: VAR3 = 7'h63;
7'd4: VAR3 = 7'h65;
7'd6: VAR3 = 7'h34;
7'd8: VAR3 = 7'h03;
default: VAR3 = 7'h20;
endcase
end else if (VAR7 >= 6'd2 && VAR7 <= 6'd4) begin
VAR3 = VAR1 ? VAR6 : 7'h20;
end else begin
VAR3 = 7'h20;
end
end
endmodule
|
apache-2.0
|
archlabo/Frix
|
fpga/nexys4/rtl/clock/clk_wiz_0_clk_wiz.v
| 7,238 |
module MODULE1
( input VAR43,
output VAR44,
output VAR19,
output VAR11
);
VAR37 VAR18
(.VAR78 (VAR7),
.VAR76 (VAR43));
wire [15:0] VAR65;
wire VAR10;
wire VAR79;
wire VAR74;
wire VAR50;
wire VAR33;
wire VAR32;
wire VAR2;
wire VAR53;
wire VAR81;
wire VAR45;
wire VAR39;
wire VAR42;
wire VAR16;
wire VAR12;
wire VAR83;
wire VAR58;
wire VAR63;
VAR14
.VAR72 ("VAR40"),
.VAR15 ("VAR20"),
.VAR4 ("VAR40"),
.VAR3 (1),
.VAR70 (8.000),
.VAR21 (0.000),
.VAR36 ("VAR40"),
.VAR34 (20.000),
.VAR82 (0.000),
.VAR47 (0.500),
.VAR54 ("VAR40"),
.VAR41 (40),
.VAR86 (0.000),
.VAR29 (0.500),
.VAR57 ("VAR40"),
.VAR87 (10.0),
.VAR8 (0.010))
VAR77
(
.VAR24 (VAR50),
.VAR85 (VAR32),
.VAR13 (VAR1),
.VAR5 (VAR2),
.VAR17 (VAR66),
.VAR51 (VAR53),
.VAR31 (VAR81),
.VAR64 (VAR45),
.VAR28 (VAR39),
.VAR35 (VAR42),
.VAR84 (VAR16),
.VAR27 (VAR12),
.VAR48 (VAR83),
.VAR30 (VAR33),
.VAR69 (VAR7),
.VAR62 (1'b0),
.VAR25 (1'b1),
.VAR46 (7'h0),
.VAR73 (1'b0),
.VAR61 (1'b0),
.VAR49 (16'h0),
.VAR59 (VAR65),
.VAR60 (VAR10),
.VAR9 (1'b0),
.VAR80 (1'b0),
.VAR55 (1'b0),
.VAR71 (1'b0),
.VAR26 (VAR79),
.VAR22 (VAR74),
.VAR52 (VAR63),
.VAR68 (VAR58),
.VAR75 (1'b0),
.VAR67 (1'b0));
assign VAR11 = VAR74;
VAR23 VAR56
(.VAR78 (VAR33),
.VAR76 (VAR50));
VAR23 VAR6
(.VAR78 (VAR44),
.VAR76 (VAR1));
VAR23 VAR38
(.VAR78 (VAR19),
.VAR76 (VAR66));
endmodule
|
bsd-2-clause
|
praveendath92/DDR2_Interface_Xilinx_XUPV5
|
source/mig_36_1.v
| 27,213 |
module MODULE1 #
(
parameter VAR114 = 2,
parameter VAR76 = 1,
parameter VAR117 = 2,
parameter VAR43 = 10,
parameter VAR51 = 1,
parameter VAR134 = 1,
parameter VAR66 = 0,
parameter VAR38 = 8,
parameter VAR68 = 64,
parameter VAR80 = 8,
parameter VAR75 = 8,
parameter VAR9 = 6,
parameter VAR86 = 3,
parameter VAR105 = 1,
parameter VAR60 = 13,
parameter VAR107 = 0,
parameter VAR166 = 4,
parameter VAR45 = 0,
parameter VAR14 = 4,
parameter VAR34 = 0,
parameter VAR140 = 128,
parameter VAR120 = 1,
parameter VAR160 = 1,
parameter VAR39 = 1,
parameter VAR122 = 0,
parameter VAR133 = 0,
parameter VAR58 = 7800,
parameter VAR159 = 40000,
parameter VAR82 = 15000,
parameter VAR4 = 105000,
parameter VAR108 = 15000,
parameter VAR27 = 7500,
parameter VAR6 = 15000,
parameter VAR87 = 7500,
parameter VAR153 = "VAR163",
parameter VAR138 = 0,
parameter VAR2 = 0,
parameter VAR158 = 3750,
parameter VAR81 = "VAR46",
parameter VAR36 = "VAR62",
parameter VAR59 = 0,
parameter VAR127 = 1
)
(
inout [VAR68-1:0] VAR157,
output [VAR60-1:0] VAR85,
output [VAR114-1:0] VAR72,
output VAR41,
output VAR109,
output VAR5,
output [VAR134-1:0] VAR16,
output [VAR105-1:0] VAR28,
output [VAR76-1:0] VAR18,
output [VAR38-1:0] VAR11,
input VAR123,
input VAR17,
input VAR1,
input VAR167,
input VAR49,
output VAR12,
output VAR104,
inout [VAR75-1:0] VAR101,
inout [VAR75-1:0] VAR67,
output [VAR117-1:0] VAR52,
output [VAR117-1:0] VAR164,
output wire [7:0] VAR161 );
localparam VAR132 = "VAR20";
wire VAR57;
wire VAR91;
wire VAR131;
wire VAR47;
wire VAR69;
wire VAR79;
wire VAR8;
wire VAR106;
wire VAR165;
wire VAR110;
wire VAR146;
wire VAR119;
wire VAR10;
wire VAR125;
wire VAR84;
wire VAR7;
wire VAR94;
wire [30:0] VAR156;
wire [2:0] VAR99;
wire [(VAR140)-1:0] VAR70;
wire [(VAR140)-1:0] VAR40;
wire [(VAR140/8)-1:0] VAR97;
wire [3:0] VAR129;
wire [3:0] VAR19;
wire [(6*VAR68)-1:0] VAR102;
wire [(6*VAR75)-1:0] VAR154;
wire [(6*VAR75)-1:0] VAR44;
wire [VAR75-1:0] VAR155;
wire [(5*VAR75)-1:0] VAR37;
wire [(5*VAR75)-1:0] VAR126;
wire VAR130;
wire VAR64;
wire VAR151;
wire VAR128;
wire VAR29;
wire VAR25;
wire VAR78;
wire VAR148;
wire [VAR9-1:0] VAR3;
wire VAR61;
wire [VAR86:0] VAR50;
wire VAR95;
wire [VAR86:0] VAR92;
wire VAR139;
wire [35:0] VAR103;
wire [35:0] VAR143;
wire [35:0] VAR21;
wire [35:0] VAR142;
wire [191:0] VAR118;
wire [95:0] VAR23;
wire [99:0] VAR54;
wire [31:0] VAR141;
assign VAR57 = 1'b0;
assign VAR91 = 1'b0;
VAR90 #
(
.VAR132 (VAR132)
)
VAR55
(
.VAR8 (VAR8),
.VAR146 (VAR146),
.VAR119 (VAR119)
);
VAR26 #
(
.VAR158 (VAR158),
.VAR81 (VAR81),
.VAR36 (VAR36),
.VAR59 (VAR59),
.VAR127 (VAR127)
)
VAR35
(
.VAR123 (VAR123),
.VAR17 (VAR17),
.VAR57 (VAR57),
.VAR1 (VAR1),
.VAR167 (VAR167),
.VAR91 (VAR91),
.VAR49 (VAR49),
.VAR47 (VAR47),
.VAR69 (VAR69),
.VAR79 (VAR79),
.VAR8 (VAR8),
.VAR106 (VAR106),
.VAR165 (VAR165),
.VAR110 (VAR110),
.VAR146 (VAR146),
.VAR119 (VAR119)
);
VAR31 #
(
.VAR114 (VAR114),
.VAR76 (VAR76),
.VAR117 (VAR117),
.VAR43 (VAR43),
.VAR51 (VAR51),
.VAR134 (VAR134),
.VAR66 (VAR66),
.VAR38 (VAR38),
.VAR68 (VAR68),
.VAR80 (VAR80),
.VAR75 (VAR75),
.VAR9 (VAR9),
.VAR86 (VAR86),
.VAR105 (VAR105),
.VAR60 (VAR60),
.VAR107 (VAR107),
.VAR166 (VAR166),
.VAR45 (VAR45),
.VAR14 (VAR14),
.VAR34 (VAR34),
.VAR140 (VAR140),
.VAR120 (VAR120),
.VAR160 (VAR160),
.VAR39 (VAR39),
.VAR122 (VAR122),
.VAR133 (VAR133),
.VAR58 (VAR58),
.VAR159 (VAR159),
.VAR82 (VAR82),
.VAR4 (VAR4),
.VAR108 (VAR108),
.VAR27 (VAR27),
.VAR6 (VAR6),
.VAR87 (VAR87),
.VAR153 (VAR153),
.VAR132 (VAR132),
.VAR138 (VAR138),
.VAR2 (VAR2),
.VAR116 (1),
.VAR100 (1),
.VAR158 (VAR158)
)
VAR32
(
.VAR157 (VAR157),
.VAR85 (VAR85),
.VAR72 (VAR72),
.VAR41 (VAR41),
.VAR109 (VAR109),
.VAR5 (VAR5),
.VAR16 (VAR16),
.VAR28 (VAR28),
.VAR18 (VAR18),
.VAR11 (VAR11),
.VAR12 (VAR12),
.VAR47 (VAR47),
.VAR69 (VAR69),
.VAR79 (VAR79),
.VAR106 (VAR106),
.VAR165 (VAR165),
.VAR110 (VAR110),
.VAR10 (VAR10),
.VAR125 (VAR125),
.VAR84 (VAR84),
.VAR7 (VAR7),
.VAR94 (VAR94),
.VAR156 (VAR156),
.VAR99 (VAR99),
.VAR70 (VAR70),
.VAR40 (VAR40),
.VAR97 (VAR97),
.VAR101 (VAR101),
.VAR67 (VAR67),
.VAR52 (VAR52),
.VAR71 (),
.VAR164 (VAR164),
.VAR129 (VAR129),
.VAR19 (VAR19),
.VAR102 (VAR102),
.VAR154 (VAR154),
.VAR44 (VAR44),
.VAR155 (VAR155),
.VAR37 (VAR37),
.VAR126 (VAR126),
.VAR130 (VAR130),
.VAR64 (VAR64),
.VAR151 (VAR151),
.VAR128 (VAR128),
.VAR29 (VAR29),
.VAR25 (VAR25),
.VAR78 (VAR78),
.VAR148 (VAR148),
.VAR3 (VAR3),
.VAR61 (VAR61),
.VAR50 (VAR50),
.VAR95 (VAR95),
.VAR92 (VAR92),
.VAR139 (VAR139)
);
VAR15 #
(
.VAR114 (VAR114),
.VAR43 (VAR43),
.VAR38 (VAR38),
.VAR68 (VAR68),
.VAR60 (VAR60),
.VAR166 (VAR166),
.VAR34 (VAR34),
.VAR140 (VAR140)
)
VAR30
(
.VAR12 (VAR12),
.VAR104 (VAR104),
.VAR131 (VAR131),
.VAR47 (VAR47),
.VAR106 (VAR106),
.VAR10 (VAR10),
.VAR125 (VAR125),
.VAR84 (VAR84),
.VAR7 (VAR7),
.VAR94 (VAR94),
.VAR156 (VAR156),
.VAR99 (VAR99),
.VAR70 (VAR70),
.VAR40 (VAR40),
.VAR97 (VAR97),
.VAR161 (VAR161)
);
generate
if (VAR2 == 0) begin: VAR24
assign VAR130 = 'b0;
assign VAR64 = 'b0;
assign VAR151 = 'b0;
assign VAR128 = 'b0;
assign VAR29 = 'b0;
assign VAR25 = 'b0;
assign VAR78 = 'b0;
assign VAR148 = 'b0;
assign VAR3 = 'b0;
assign VAR61 = 'b0;
assign VAR50 = 'b0;
assign VAR95 = 'b0;
assign VAR92 = 'b0;
assign VAR139 = 'b0;
end else begin: VAR22
VAR147 VAR98
(
.VAR93 (VAR103),
.VAR48 (VAR143),
.VAR33 (VAR21),
.VAR115 (VAR142)
);
VAR53 VAR89
(
.VAR65 (VAR103),
.VAR13 (VAR118)
);
VAR121 VAR56
(
.VAR65 (VAR143),
.VAR13 (VAR23)
);
VAR162 VAR152
(
.VAR65 (VAR21),
.VAR13 (VAR54)
);
VAR145 VAR112
(
.VAR65 (VAR142),
.clk (VAR110),
.VAR42 (VAR141)
);
if (VAR68 <= 32) begin: VAR83
assign VAR118[(6*VAR68)-1:0]
= VAR102[(6*VAR68)-1:0];
end else begin: VAR144
assign VAR118 = VAR102[191:0];
end
if (VAR75 <= 8) begin: VAR136
assign VAR23[(6*VAR75)-1:0]
= VAR154[(6*VAR75)-1:0];
assign VAR23[(12*VAR75)-1:(6*VAR75)]
= VAR44[(6*VAR75)-1:0];
end else begin: VAR137
assign VAR23[47:0] = VAR154[47:0];
assign VAR23[95:48] = VAR44[47:0];
end
if (VAR75 <= 8) begin: VAR88
assign VAR54[(VAR75)+7:8]
= VAR155[(VAR75)-1:0];
end else begin: VAR124
assign VAR54[15:8]
= VAR155[7:0];
end
if (VAR75 <= 8) begin: VAR150
assign VAR54[(5*VAR75)+19:20]
= VAR37[(5*VAR75)-1:0];
end else begin: VAR135
assign VAR54[59:20]
= VAR37[39:0];
end
if (VAR75 <= 8) begin: VAR63
assign VAR54[(5*VAR75)+59:60]
= VAR126[(5*VAR75)-1:0];
end else begin: VAR96
assign VAR54[99:60]
= VAR126[39:0];
end
if (VAR9 <= 5) begin: VAR73
assign VAR3[VAR9-1:0]
= VAR141[VAR9+7:8];
end else begin: VAR149
assign VAR3[4:0]
= VAR141[12:8];
end
if (VAR86 <= 3) begin: VAR111
assign VAR50[VAR86:0]
= VAR141[(VAR86+16):16];
end else begin: VAR77
assign VAR50[3:0]
= VAR141[19:16];
end
if (VAR86 <= 3) begin: VAR74
assign VAR92[VAR86:0]
= VAR141[(VAR86+21):21];
end else begin: VAR113
assign VAR92[3:0]
= VAR141[24:21];
end
assign VAR54[3:0] = VAR129;
assign VAR54[7:4] = VAR19;
assign VAR130 = VAR141[0];
assign VAR64 = VAR141[1];
assign VAR151 = VAR141[2];
assign VAR128 = VAR141[3];
assign VAR29 = VAR141[4];
assign VAR25 = VAR141[5];
assign VAR78 = VAR141[6];
assign VAR148 = VAR141[7];
assign VAR61 = VAR141[15];
assign VAR95 = VAR141[20];
assign VAR139 = VAR141[25];
end
endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlrbp/sky130_fd_sc_ms__dlrbp.symbol.v
| 1,456 |
module MODULE1 (
input VAR1 ,
output VAR5 ,
output VAR9 ,
input VAR8,
input VAR2
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule
|
apache-2.0
|
TonyBrewer/OpenHT
|
ht_lib/platform/convey/verilog/HtResetFlop1x.v
| 1,167 |
module MODULE1 (
input VAR9,
input VAR12,
input VAR7,
output VAR1
);
reg VAR3;
always @(posedge VAR9) begin
if (VAR7)
VAR3 <= 1'b1;
end
else
VAR3 <= 1'b0;
end
VAR6 rst (.VAR11(VAR9), .VAR2(VAR7), .VAR5(VAR3), .VAR10(!VAR3), .VAR8(VAR3));
reg VAR4;
always @(posedge VAR12) begin
VAR4 <= VAR3;
end
assign VAR1 = VAR4;
reg VAR4;
always @(posedge VAR12) begin
if (VAR7)
VAR4 <= 1'b1;
end
else
VAR4 <= 1'b0;
end
assign VAR1 = VAR4;
endmodule
|
bsd-3-clause
|
EliasVansteenkiste/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_068.v
| 1,532 |
module MODULE1 (
VAR2,
VAR9
);
input [31:0] VAR2;
output [31:0]
VAR9;
wire [31:0]
VAR11,
VAR6,
VAR8,
VAR10,
VAR12,
VAR1,
VAR13,
VAR4,
VAR14;
assign VAR11 = VAR2;
assign VAR10 = VAR11 << 7;
assign VAR13 = VAR1 - VAR12;
assign VAR1 = VAR11 << 14;
assign VAR14 = VAR13 + VAR4;
assign VAR12 = VAR8 - VAR10;
assign VAR6 = VAR11 << 9;
assign VAR8 = VAR11 + VAR6;
assign VAR4 = VAR12 << 4;
assign VAR9 = VAR14;
endmodule
module MODULE2(
VAR2,
VAR9,
clk
);
input [31:0] VAR2;
output [31:0] VAR9;
reg [31:0] VAR9;
input clk;
reg [31:0] VAR3;
wire [30:0] VAR5;
always @(posedge clk) begin
VAR3 <= VAR2;
VAR9 <= VAR5;
end
MODULE1 MODULE1(
.VAR2(VAR3),
.VAR9(VAR5)
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o41a/sky130_fd_sc_ms__o41a_1.v
| 2,411 |
module MODULE2 (
VAR3 ,
VAR1 ,
VAR9 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR10,
VAR11,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR10;
input VAR11;
input VAR8 ;
input VAR2 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR1,
VAR9,
VAR6,
VAR12,
VAR7
);
output VAR3 ;
input VAR1;
input VAR9;
input VAR6;
input VAR12;
input VAR7;
supply1 VAR10;
supply0 VAR11;
supply1 VAR8 ;
supply0 VAR2 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/and4b/sky130_fd_sc_hd__and4b.behavioral.pp.v
| 1,988 |
module MODULE1 (
VAR1 ,
VAR16 ,
VAR15 ,
VAR2 ,
VAR11 ,
VAR7,
VAR4,
VAR3 ,
VAR9
);
output VAR1 ;
input VAR16 ;
input VAR15 ;
input VAR2 ;
input VAR11 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR9 ;
wire VAR8 ;
wire VAR5 ;
wire VAR10;
not VAR14 (VAR8 , VAR16 );
and VAR6 (VAR5 , VAR8, VAR15, VAR2, VAR11 );
VAR17 VAR12 (VAR10, VAR5, VAR7, VAR4);
buf VAR13 (VAR1 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/einvn/sky130_fd_sc_hs__einvn.behavioral.v
| 1,766 |
module MODULE1 (
VAR1 ,
VAR6,
VAR4 ,
VAR11,
VAR8
);
input VAR1 ;
input VAR6;
output VAR4 ;
input VAR11;
input VAR8;
wire VAR3 ;
wire VAR2;
VAR10 VAR5 (VAR3 , VAR1, VAR11, VAR8 );
VAR10 VAR7 (VAR2, VAR6, VAR11, VAR8 );
notif0 VAR9 (VAR4 , VAR3, VAR2);
endmodule
|
apache-2.0
|
myriadrf/A2300
|
hdl/wca/WcaReadFifo32W8R.v
| 1,943 |
module MODULE1(
input wire reset,
input wire VAR17, input wire VAR16, input wire [31:0] in,
output wire VAR1, output wire VAR10,
input wire [11:0] VAR4, inout wire [7:0] VAR6
);
parameter VAR7 = 0;
wire [7:0] dout;
wire VAR9 = (VAR7 == VAR4[11:4]);
assign VAR6 = ( VAR9 & VAR4[3] ) ? dout : 8'VAR12;
VAR3 VAR13(
.rst(reset), .VAR15(VAR17), .VAR8(VAR4[0]), .din(in), .VAR5(VAR16), .VAR2(VAR4[1] & VAR9), .dout(dout), .VAR10(VAR10), .VAR1(VAR1), .VAR11(), .VAR14() );
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/and3/sky130_fd_sc_ms__and3_2.v
| 2,164 |
module MODULE2 (
VAR4 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR1,
VAR5,
VAR10 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR1;
input VAR5;
input VAR10 ;
input VAR3 ;
VAR6 VAR9 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4,
VAR7,
VAR2,
VAR8
);
output VAR4;
input VAR7;
input VAR2;
input VAR8;
supply1 VAR1;
supply0 VAR5;
supply1 VAR10 ;
supply0 VAR3 ;
VAR6 VAR9 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
HarmonInstruments/verilog
|
uart/uart.v
| 3,444 |
module MODULE1
(
input VAR3, input VAR21, input [1:0] VAR14, input [31:0] VAR18, output reg [31:0] rd = 0, inout VAR2 );
reg [3:0] VAR12 = 0;
reg [6:0] VAR17 = 0;
reg [6:0] VAR16 = 0;
reg [6:0] VAR9 = 100; reg VAR6 = 1;
reg VAR19 = 0;
reg VAR13 = 0;
reg [5:0] VAR7 = 0; reg [6:0] VAR1 = 0;
reg [6:0] VAR8 = 0;
reg [38:0] VAR10 = 39'h7FFFFFFFF;
assign VAR2 = VAR19 ? VAR13 : 1'VAR11;
always @ (posedge VAR3)
begin
VAR6 <= VAR2;
if(VAR12 == 0)
begin
VAR17 <= 1'b0;
if (!VAR6)
begin
VAR12 <= 1'b1;
VAR16 <= VAR9[6:1];
end
end
else
begin
VAR17 <= VAR17 + 1'b1;
if(VAR16 == VAR17)
begin
VAR16 <= VAR16 + VAR9;
VAR12 <= VAR12 == 10 ? 1'b0 : VAR12 + 1'b1;
if((VAR12 > 1) && (VAR12 < 10))
rd <= {VAR6, rd[31:1]};
end
end
VAR13 <= VAR10[0];
VAR19 <= VAR7 != 0;
if(VAR21)
begin
if((VAR14 == 0) && VAR18[31])
VAR9 <= VAR18[6:0];
VAR19 <= 1'b1;
VAR7 <= 6'd40;
VAR1 <= 1'b0;
VAR8 <= VAR9;
VAR10[38:30] <= VAR14 > 2 ? {VAR18[31:24], 1'b0} : 9'h1FF;
VAR10[29:20] <= VAR14 > 1 ? {1'b1, VAR18[23:16], 1'b0} : 10'h3FF;
VAR10[19:10] <= VAR14 > 0 ? {1'b1, VAR18[15: 8], 1'b0} : 10'h3FF;
VAR10[ 9: 0] <= (VAR14 > 0) || (VAR18[31:30] == 0) ? {1'b1, VAR18[ 7: 0], 1'b0} :
VAR18[30] == 1 ? 10'h000 : 10'h3FF;
end
else
begin
VAR1 <= VAR1 + 1'b1;
if(VAR8 == VAR1)
begin
VAR8 <= VAR8 + VAR9;
VAR10 <= {1'b1, VAR10[38:1]};
VAR7 <= VAR7 == 0 ? 1'b0 : VAR7 - 1'b1;
end
end
end
endmodule
module MODULE2 (input VAR3);
reg VAR21 = 0;
reg [2:0] VAR14 = 0;
reg [31:0] VAR18 = 0;
wand VAR2 = 1;
wire [31:0] VAR4, VAR20;
MODULE1 MODULE1 (.VAR3(VAR3), .VAR21(VAR21 & ~VAR14[2]), .VAR14(VAR14[1:0]), .VAR18(VAR18), .rd(VAR4), .VAR2(VAR2));
MODULE1 MODULE2 (.VAR3(VAR3), .VAR21(VAR21 & VAR14[2]), .VAR14(VAR14[1:0]), .VAR18(VAR18), .rd(VAR20), .VAR2(VAR2));
begin
|
gpl-3.0
|
megari/sd2snes
|
verilog/sd2snes_gsu/dcm.v
| 2,986 |
module MODULE1 (
input VAR36,
output VAR10,
output VAR32,
input VAR38,
output[7:0] VAR24
);
VAR3 #(
.VAR2("VAR14"), .VAR37(2.0), .VAR40(5), .VAR18(18), .VAR12("VAR13"), .VAR6(41.667), .VAR16("VAR21"), .VAR35("VAR21"), .VAR33("VAR22"), .VAR9("VAR7"), .VAR8("VAR7"), .VAR26("VAR17"), .VAR41(16'hFFFF), .VAR28(0), .VAR39("VAR17") ) VAR25 (
.VAR5(VAR5), .VAR27(VAR27), .VAR23(VAR23), .VAR15(VAR15), .VAR34(VAR34), .VAR20(VAR20), .VAR11(VAR11), .VAR10(VAR10), .VAR30(VAR30), .VAR32(VAR32), .VAR4(VAR4), .VAR24(VAR24), .VAR31(VAR31), .VAR36(VAR36), .VAR29(VAR29), .VAR19(VAR19), .VAR1(VAR1), .VAR38(VAR38) );
endmodule
|
gpl-2.0
|
revaldinho/opc
|
opc1/opccpu.v
| 2,615 |
module MODULE1( inout[7:0] VAR31, output[10:0] address, output VAR15, input clk, input VAR8);
parameter VAR27=0, VAR13=1, VAR28=2, VAR34=3, VAR7=4 ;
parameter VAR32=5'VAR33, VAR25=5'VAR35, VAR29=5'VAR5, VAR10=5'VAR20;
parameter VAR9=5'b01001, VAR24=5'b11000, VAR3=5'b01000;
parameter VAR22=5'b11001, VAR14=5'b11010, VAR6=5'b11011, VAR18=5'b11100;
parameter VAR12=5'b11101, VAR11=5'b11110;
reg [10:0] VAR1, VAR30;
reg [7:0] VAR23;
reg [2:0] VAR21;
reg [4:0] VAR4;
reg [2:0] VAR16; VAR2 VAR26 VAR16[0]
wire VAR17 = ((VAR21 == VAR7) && (VAR4 == VAR24 || VAR4 == VAR3)) & VAR8 ;
assign VAR15 = ~VAR17 ;
assign VAR31 = (VAR17)?VAR23:8'VAR19 ;
assign address = ( VAR17 || VAR21 == VAR28 || VAR21==VAR34)? VAR1:VAR30;
always @ (posedge clk or negedge VAR8 )
if (!VAR8)
VAR21 <= VAR27;
else
case(VAR21)
VAR27 : VAR21 <= VAR13;
VAR13 : VAR21 <= (VAR4[4])?VAR7:VAR28 ;
VAR28 : VAR21 <= (VAR4==VAR9)?VAR34:VAR7;
VAR34 : VAR21 <= VAR7;
VAR7 : VAR21 <= VAR27;
endcase
always @ (posedge clk)
begin
VAR4 <= (VAR21 == VAR27)? VAR31[7:3] : VAR4;
VAR1[10:8] <= (VAR21 == VAR27)? VAR31[2:0]: (VAR21==VAR28)?3'b0:VAR1[10:8];
VAR1[7:0] <= VAR31; if ( VAR21 == VAR7 )
casex (VAR4)
VAR18 : {VAR16,VAR23} <= VAR30 ;
VAR11 : {VAR16,VAR23} <= {VAR23[2:0], 5'b0, VAR16};
VAR32 : {VAR26, VAR23} <= {1'b0, VAR23 & VAR1[7:0]};
VAR29 : VAR23 <= ~VAR1[7:0];
VAR25 : VAR23 <= VAR1[7:0];
VAR9 : VAR23 <= VAR1[7:0];
VAR10 : {VAR26,VAR23} <= VAR23 + VAR26 + VAR1[7:0];
default: {VAR26,VAR23} <= {VAR26,VAR23};
endcase
end
always @ (posedge clk or negedge VAR8 )
if (!VAR8) VAR30 <= 11'h100;
else
if ( VAR21 == VAR27 || VAR21 == VAR13 )
VAR30 <= VAR30 + 1;
else
case (VAR4)
VAR6 : VAR30 <= VAR1;
VAR22 : VAR30 <= (VAR26)?VAR1:VAR30;
VAR14 : VAR30 <= ~(|VAR23)?VAR1:VAR30;
VAR18 : VAR30 <= VAR1;
VAR12 : VAR30 <= {VAR16, VAR23};
default: VAR30 <= VAR30;
endcase
endmodule
|
gpl-3.0
|
timtian090/Playground
|
UVM/UVMPlayground/Lab3/Lab3-Project/TF_EECS301_Lab3_TopLevel.v
| 2,513 |
module MODULE1();
localparam VAR1 = 50000000; localparam VAR3 = ((1.0 / VAR1) * 1000000000.0) / 2.0;
reg VAR2;
begin
begin
|
mit
|
nikhilghanathe/HLS-for-EMTF
|
verilog/sp_ptlut_address.v
| 14,164 |
module MODULE1 (
VAR112,
VAR91,
VAR80,
VAR27,
VAR5,
VAR6,
VAR21,
VAR45,
VAR120,
VAR22,
VAR114,
VAR105,
VAR64,
VAR116,
VAR30,
VAR24,
VAR58,
VAR46,
VAR55,
VAR15,
VAR77,
VAR40,
VAR89,
VAR79,
VAR115,
VAR121,
VAR90,
VAR73,
VAR93,
VAR109,
VAR44,
VAR100,
VAR47,
VAR48,
VAR35,
VAR11,
VAR1,
VAR28,
VAR107,
VAR74,
VAR110,
VAR61,
VAR78,
VAR63,
VAR118,
VAR102,
VAR7,
VAR2,
VAR50,
VAR111,
VAR18,
VAR83,
VAR26,
VAR84,
VAR34,
VAR94,
VAR51,
VAR9,
VAR12,
VAR16,
VAR104,
VAR113,
VAR97,
VAR53,
VAR3,
VAR60,
VAR41,
VAR68,
VAR87,
VAR10,
VAR95,
VAR66,
VAR31,
VAR19,
VAR70,
VAR8,
VAR69,
VAR101,
VAR54,
VAR75,
VAR38,
VAR59,
VAR67,
VAR103,
VAR71,
VAR17,
VAR13,
VAR37,
VAR88,
VAR52,
VAR72,
VAR33,
VAR20,
VAR76,
VAR92,
VAR42,
VAR32,
VAR81,
VAR29,
VAR117,
VAR119,
VAR65
);
input VAR112;
input VAR91;
input [11:0] VAR80;
input [11:0] VAR27;
input [11:0] VAR5;
input [6:0] VAR6;
input [6:0] VAR21;
input [6:0] VAR45;
input [3:0] VAR120;
input [3:0] VAR22;
input [3:0] VAR114;
input [3:0] VAR105;
input [3:0] VAR64;
input [3:0] VAR116;
input [3:0] VAR30;
input [3:0] VAR24;
input [3:0] VAR58;
input [3:0] VAR46;
input [3:0] VAR55;
input [3:0] VAR15;
input [11:0] VAR77;
input [11:0] VAR40;
input [11:0] VAR89;
input [11:0] VAR79;
input [11:0] VAR115;
input [11:0] VAR121;
input [11:0] VAR90;
input [11:0] VAR73;
input [11:0] VAR93;
input [11:0] VAR109;
input [11:0] VAR44;
input [11:0] VAR100;
input [11:0] VAR47;
input [11:0] VAR48;
input [11:0] VAR35;
input [11:0] VAR11;
input [11:0] VAR1;
input [11:0] VAR28;
input [6:0] VAR107;
input [6:0] VAR74;
input [6:0] VAR110;
input [6:0] VAR61;
input [6:0] VAR78;
input [6:0] VAR63;
input [6:0] VAR118;
input [6:0] VAR102;
input [6:0] VAR7;
input [6:0] VAR2;
input [6:0] VAR50;
input [6:0] VAR111;
input [6:0] VAR18;
input [6:0] VAR83;
input [6:0] VAR26;
input [6:0] VAR84;
input [6:0] VAR34;
input [6:0] VAR94;
input [5:0] VAR51;
input [5:0] VAR9;
input [5:0] VAR12;
input [5:0] VAR16;
input [5:0] VAR104;
input [5:0] VAR113;
input [6:0] VAR97;
input [6:0] VAR53;
input [6:0] VAR3;
input [1:0] VAR60;
input [1:0] VAR41;
input [1:0] VAR68;
input [3:0] VAR87;
input [3:0] VAR10;
input [3:0] VAR95;
input [3:0] VAR66;
input [3:0] VAR31;
input [3:0] VAR19;
input [3:0] VAR70;
input [3:0] VAR8;
input [3:0] VAR69;
input [3:0] VAR101;
input [3:0] VAR54;
input [3:0] VAR75;
input [3:0] VAR38;
input [3:0] VAR59;
input [3:0] VAR67;
input [2:0] VAR103;
input [0:0] VAR71;
output [2:0] VAR17;
output [2:0] VAR13;
output [31:0] VAR37;
output [31:0] VAR88;
output [31:0] VAR52;
output [7:0] VAR72;
output [7:0] VAR33;
output [7:0] VAR20;
output [3:0] VAR76;
output [3:0] VAR92;
output [3:0] VAR42;
output [29:0] VAR32;
output [29:0] VAR81;
output [29:0] VAR29;
output [8:0] VAR117;
output [8:0] VAR119;
output [8:0] VAR65;
wire [2:0] VAR56;
wire [2:0] VAR98;
wire [29:0] VAR43;
wire [29:0] VAR99;
wire [29:0] VAR86;
wire [31:0] VAR4;
wire [31:0] VAR85;
wire [31:0] VAR36;
wire [7:0] VAR57;
wire [7:0] VAR106;
wire [7:0] VAR23;
wire [8:0] VAR62;
wire [8:0] VAR25;
wire [8:0] VAR39;
wire [3:0] VAR14;
wire [3:0] VAR96;
wire [3:0] VAR82;
VAR108 VAR49(
.VAR112(VAR112),
.VAR91(VAR91),
.VAR80(VAR80),
.VAR27(VAR27),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR21(VAR21),
.VAR45(VAR45),
.VAR120(VAR120),
.VAR22(VAR22),
.VAR114(VAR114),
.VAR105(VAR105),
.VAR64(VAR64),
.VAR116(VAR116),
.VAR30(VAR30),
.VAR24(VAR24),
.VAR58(VAR58),
.VAR46(VAR46),
.VAR55(VAR55),
.VAR15(VAR15),
.VAR77(VAR77),
.VAR40(VAR40),
.VAR89(VAR89),
.VAR79(VAR79),
.VAR115(VAR115),
.VAR121(VAR121),
.VAR90(VAR90),
.VAR73(VAR73),
.VAR93(VAR93),
.VAR109(VAR109),
.VAR44(VAR44),
.VAR100(VAR100),
.VAR47(VAR47),
.VAR48(VAR48),
.VAR35(VAR35),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR28(VAR28),
.VAR107(VAR107),
.VAR74(VAR74),
.VAR110(VAR110),
.VAR61(VAR61),
.VAR78(VAR78),
.VAR63(VAR63),
.VAR118(VAR118),
.VAR102(VAR102),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR50(VAR50),
.VAR111(VAR111),
.VAR18(VAR18),
.VAR83(VAR83),
.VAR26(VAR26),
.VAR84(VAR84),
.VAR34(VAR34),
.VAR94(VAR94),
.VAR51(VAR51),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR16(VAR16),
.VAR104(VAR104),
.VAR113(VAR113),
.VAR97(VAR97),
.VAR53(VAR53),
.VAR3(VAR3),
.VAR60(VAR60),
.VAR41(VAR41),
.VAR68(VAR68),
.VAR87(VAR87),
.VAR10(VAR10),
.VAR95(VAR95),
.VAR66(VAR66),
.VAR31(VAR31),
.VAR19(VAR19),
.VAR70(VAR70),
.VAR8(VAR8),
.VAR69(VAR69),
.VAR101(VAR101),
.VAR54(VAR54),
.VAR75(VAR75),
.VAR38(VAR38),
.VAR59(VAR59),
.VAR67(VAR67),
.VAR103(VAR103),
.VAR71(VAR71),
.VAR17(VAR56),
.VAR13(VAR98),
.VAR37(VAR43),
.VAR88(VAR99),
.VAR52(VAR86),
.VAR72(VAR4),
.VAR33(VAR85),
.VAR20(VAR36),
.VAR76(VAR57),
.VAR92(VAR106),
.VAR42(VAR23),
.VAR32(VAR62),
.VAR81(VAR25),
.VAR29(VAR39),
.VAR117(VAR14),
.VAR119(VAR96),
.VAR65(VAR82)
);
assign VAR17 = VAR56;
assign VAR13 = VAR98;
assign VAR42 = VAR82;
assign VAR32 = VAR43;
assign VAR81 = VAR99;
assign VAR29 = VAR86;
assign VAR117 = VAR62;
assign VAR119 = VAR25;
assign VAR65 = VAR39;
assign VAR37 = VAR4;
assign VAR88 = VAR85;
assign VAR52 = VAR36;
assign VAR72 = VAR57;
assign VAR33 = VAR106;
assign VAR20 = VAR23;
assign VAR76 = VAR14;
assign VAR92 = VAR96;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.pp.blackbox.v
| 1,397 |
module MODULE1 (
VAR7 ,
VAR2 ,
VAR4,
VAR5 ,
VAR3 ,
VAR1 ,
VAR6
);
output VAR7 ;
input VAR2 ;
input VAR4;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
endmodule
|
apache-2.0
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_add.v
| 5,879 |
module MODULE1 (
clk,
VAR31,
VAR9,
VAR18,
VAR1,
VAR20,
VAR30,
VAR29);
parameter VAR4 = 16;
parameter VAR21 = VAR4 - 1;
input clk;
input [24:0] VAR31;
input [24:0] VAR9;
input [24:0] VAR18;
input [24:0] VAR1;
output [ 7:0] VAR20;
input [VAR21:0] VAR30;
output [VAR21:0] VAR29;
reg [VAR21:0] VAR11 = 'd0;
reg [24:0] VAR15 = 'd0;
reg [24:0] VAR24 = 'd0;
reg [24:0] VAR12 = 'd0;
reg [24:0] VAR5 = 'd0;
reg [VAR21:0] VAR13 = 'd0;
reg [24:0] VAR2 = 'd0;
reg [24:0] VAR19 = 'd0;
reg [VAR21:0] VAR6 = 'd0;
reg [24:0] VAR28 = 'd0;
reg [VAR21:0] VAR29 = 'd0;
reg [ 7:0] VAR20 = 'd0;
wire [24:0] VAR7;
wire [24:0] VAR10;
wire [24:0] VAR25;
wire [24:0] VAR22;
wire [24:0] VAR17;
wire [24:0] VAR23;
wire [24:0] VAR27;
wire [24:0] VAR8;
wire [24:0] VAR16;
wire [24:0] VAR14;
wire [24:0] VAR3;
wire [24:0] VAR26;
assign VAR7 = {1'b0, VAR31[23:0]};
assign VAR10 = ~VAR7 + 1'b1;
assign VAR25 = (VAR31[24] == 1'b1) ? VAR10 : VAR7;
assign VAR22 = {1'b0, VAR9[23:0]};
assign VAR17 = ~VAR22 + 1'b1;
assign VAR23 = (VAR9[24] == 1'b1) ? VAR17 : VAR22;
assign VAR27 = {1'b0, VAR18[23:0]};
assign VAR8 = ~VAR27 + 1'b1;
assign VAR16 = (VAR18[24] == 1'b1) ? VAR8 : VAR27;
assign VAR14 = {1'b0, VAR1[23:0]};
assign VAR3 = ~VAR14 + 1'b1;
assign VAR26 = (VAR1[24] == 1'b1) ? VAR3 : VAR14;
always @(posedge clk) begin
VAR11 <= VAR30;
VAR15 <= VAR25;
VAR24 <= VAR23;
VAR12 <= VAR16;
VAR5 <= VAR26;
end
always @(posedge clk) begin
VAR13 <= VAR11;
VAR2 <= VAR15 + VAR24;
VAR19 <= VAR12 + VAR5;
end
always @(posedge clk) begin
VAR6 <= VAR13;
VAR28 <= VAR2 + VAR19;
end
always @(posedge clk) begin
VAR29 <= VAR6;
if (VAR28[24] == 1'b1) begin
VAR20 <= 8'h00;
end else if (VAR28[23:20] == 'd0) begin
VAR20 <= VAR28[19:12];
end else begin
VAR20 <= 8'hff;
end
end
endmodule
|
mit
|
CospanDesign/nysa-sdio-device
|
rtl/sdio_device_stack.v
| 6,097 |
module MODULE1 (
input clk,
input rst,
output VAR3,
input VAR22,
inout VAR16,
inout [3:0] VAR18
);
wire [3:0] VAR30;
wire VAR2;
wire VAR12;
wire VAR19;
wire [3:0] VAR13;
wire [3:0] VAR29;
wire VAR5;
wire VAR7;
wire VAR26;
wire VAR10;
wire VAR32;
wire VAR25;
wire VAR31;
wire [5:0] VAR23;
wire [31:0] VAR33;
wire [127:0] VAR6;
wire [7:0] VAR1;
wire interrupt;
wire VAR4;
wire VAR15;
wire VAR21;
VAR17 #(
.VAR8 (1 ),
.VAR24 (0 ),
.VAR27 (0 ),
.VAR11 (24'hFFF0 )
) VAR20 (
.VAR22 (VAR22 ),
.rst (rst ),
.VAR21 (VAR21 ),
.VAR32 (VAR32 ),
.VAR25 (VAR25 ),
.VAR28 (VAR28 ),
.VAR23 (VAR23 ),
.VAR33 (VAR33 ),
.VAR15 (VAR15 ),
.VAR6 (VAR6 ),
.VAR1 (VAR1 )
);
VAR9 VAR14(
.rst (rst ),
.VAR7 (VAR7 ),
.VAR26 (VAR26 ),
.VAR10 (VAR10 ),
.VAR32 (VAR32 ),
.VAR25 (VAR25 ),
.VAR28 (VAR28 ),
.VAR23 (VAR23 ),
.VAR33 (VAR33 ),
.VAR6 (VAR6 ),
.VAR1 (VAR1 ),
.interrupt (interrupt ),
.VAR4 (VAR4 ),
.VAR3 (VAR3 ),
.VAR22 (VAR22 ),
.VAR2 (VAR2 ),
.VAR12 (VAR12 ),
.VAR19 (VAR19 ),
.VAR13 (VAR13 ),
.VAR29 (VAR29 ),
.VAR5 (VAR5 )
);
endmodule
|
mit
|
vad-rulezz/megabot
|
fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_ecc_decoder_32_syn.v
| 32,582 |
module MODULE1
(
VAR27,
VAR8) ;
input [5:0] VAR27;
output [63:0] VAR8;
tri0 [5:0] VAR27;
wire [5:0] VAR71;
wire [63:0] VAR28;
wire [63:0] VAR86;
wire [3:0] VAR111;
wire [3:0] VAR16;
wire [3:0] VAR47;
wire [3:0] VAR66;
wire [3:0] VAR113;
wire [3:0] VAR56;
wire [3:0] VAR2;
wire [3:0] VAR48;
wire [3:0] VAR78;
wire [3:0] VAR134;
wire [3:0] VAR96;
wire [3:0] VAR104;
wire [3:0] VAR124;
wire [3:0] VAR118;
wire [3:0] VAR139;
wire [3:0] VAR144;
wire [3:0] VAR103;
wire [3:0] VAR10;
wire [3:0] VAR135;
wire [3:0] VAR121;
wire [3:0] VAR74;
wire [3:0] VAR7;
wire [3:0] VAR76;
wire [3:0] VAR99;
wire [3:0] VAR84;
wire [3:0] VAR93;
wire [3:0] VAR120;
wire [3:0] VAR36;
wire [3:0] VAR61;
wire [3:0] VAR38;
wire [3:0] VAR147;
wire [3:0] VAR41;
wire [3:0] VAR89;
wire [3:0] VAR130;
wire [3:0] VAR82;
wire [3:0] VAR59;
wire [3:0] VAR110;
wire [3:0] VAR13;
wire [3:0] VAR43;
wire [3:0] VAR123;
wire [3:0] VAR88;
wire [3:0] VAR18;
wire [3:0] VAR6;
wire [3:0] VAR143;
wire [3:0] VAR26;
wire [3:0] VAR125;
wire [3:0] VAR44;
wire [3:0] VAR60;
wire [3:0] VAR141;
wire [3:0] VAR24;
wire [3:0] VAR108;
wire [3:0] VAR15;
wire [3:0] VAR31;
wire [3:0] VAR133;
wire [3:0] VAR102;
wire [3:0] VAR131;
wire [3:0] VAR65;
wire [3:0] VAR106;
wire [3:0] VAR34;
wire [3:0] VAR109;
wire [3:0] VAR14;
wire [3:0] VAR17;
wire [3:0] VAR29;
wire [3:0] VAR67;
wire [3:0] VAR21;
wire [3:0] VAR11;
wire [3:0] VAR30;
wire [3:0] VAR37;
wire [3:0] VAR128;
wire [3:0] VAR32;
wire [3:0] VAR73;
wire [3:0] VAR53;
wire [2:0] VAR57;
assign
VAR71 = VAR27,
VAR8 = VAR28,
VAR28 = VAR86[63:0],
VAR86 = {{VAR7[3], VAR74[3], VAR121[3], VAR135[3], VAR10[3], VAR103[3], VAR144[3], VAR139[3]}, {VAR124[3], VAR104[3], VAR96[3], VAR134[3], VAR78[3], VAR48[3], VAR2[3], VAR56[3]}, {VAR66[3], VAR47[3], VAR16[3], VAR111[3], VAR53[3], VAR73[3], VAR32[3], VAR128[3]}, {VAR30[3], VAR11[3], VAR21[3], VAR67[3], VAR29[3], VAR17[3], VAR14[3], VAR109[3]}, {VAR106[3], VAR65[3], VAR131[3], VAR102[3], VAR133[3], VAR31[3], VAR15[3], VAR108[3]}, {VAR141[3], VAR60[3], VAR44[3], VAR125[3], VAR26[3], VAR143[3], VAR6[3], VAR18[3]}, {VAR123[3], VAR43[3], VAR13[3], VAR110[3], VAR59[3], VAR82[3], VAR130[3], VAR89[3]}, {VAR147[3], VAR38[3], VAR61[3], VAR36[3], VAR120[3], VAR93[3], VAR84[3], VAR99[3]}},
VAR111 = {(VAR111[2] & VAR57[2]), (VAR111[1] & (~ VAR57[1])), (VAR111[0] & (~ VAR57[0])), VAR37[3]},
VAR16 = {(VAR16[2] & VAR57[2]), (VAR16[1] & (~ VAR57[1])), (VAR16[0] & VAR57[0]), VAR37[3]},
VAR47 = {(VAR47[2] & VAR57[2]), (VAR47[1] & VAR57[1]), (VAR47[0] & (~ VAR57[0])), VAR37[3]},
VAR66 = {(VAR66[2] & VAR57[2]), (VAR66[1] & VAR57[1]), (VAR66[0] & VAR57[0]), VAR37[3]},
VAR113 = {(VAR113[2] & VAR71[5]), (VAR113[1] & VAR71[4]), (VAR113[0] & (~ VAR71[3])), 1'b1},
VAR56 = {(VAR56[2] & (~ VAR57[2])), (VAR56[1] & (~ VAR57[1])), (VAR56[0] & (~ VAR57[0])), VAR113[3]},
VAR2 = {(VAR2[2] & (~ VAR57[2])), (VAR2[1] & (~ VAR57[1])), (VAR2[0] & VAR57[0]), VAR113[3]},
VAR48 = {(VAR48[2] & (~ VAR57[2])), (VAR48[1] & VAR57[1]), (VAR48[0] & (~ VAR57[0])), VAR113[3]},
VAR78 = {(VAR78[2] & (~ VAR57[2])), (VAR78[1] & VAR57[1]), (VAR78[0] & VAR57[0]), VAR113[3]},
VAR134 = {(VAR134[2] & VAR57[2]), (VAR134[1] & (~ VAR57[1])), (VAR134[0] & (~ VAR57[0])), VAR113[3]},
VAR96 = {(VAR96[2] & VAR57[2]), (VAR96[1] & (~ VAR57[1])), (VAR96[0] & VAR57[0]), VAR113[3]},
VAR104 = {(VAR104[2] & VAR57[2]), (VAR104[1] & VAR57[1]), (VAR104[0] & (~ VAR57[0])), VAR113[3]},
VAR124 = {(VAR124[2] & VAR57[2]), (VAR124[1] & VAR57[1]), (VAR124[0] & VAR57[0]), VAR113[3]},
VAR118 = {(VAR118[2] & VAR71[5]), (VAR118[1] & VAR71[4]), (VAR118[0] & VAR71[3]), 1'b1},
VAR139 = {(VAR139[2] & (~ VAR57[2])), (VAR139[1] & (~ VAR57[1])), (VAR139[0] & (~ VAR57[0])), VAR118[3]},
VAR144 = {(VAR144[2] & (~ VAR57[2])), (VAR144[1] & (~ VAR57[1])), (VAR144[0] & VAR57[0]), VAR118[3]},
VAR103 = {(VAR103[2] & (~ VAR57[2])), (VAR103[1] & VAR57[1]), (VAR103[0] & (~ VAR57[0])), VAR118[3]},
VAR10 = {(VAR10[2] & (~ VAR57[2])), (VAR10[1] & VAR57[1]), (VAR10[0] & VAR57[0]), VAR118[3]},
VAR135 = {(VAR135[2] & VAR57[2]), (VAR135[1] & (~ VAR57[1])), (VAR135[0] & (~ VAR57[0])), VAR118[3]},
VAR121 = {(VAR121[2] & VAR57[2]), (VAR121[1] & (~ VAR57[1])), (VAR121[0] & VAR57[0]), VAR118[3]},
VAR74 = {(VAR74[2] & VAR57[2]), (VAR74[1] & VAR57[1]), (VAR74[0] & (~ VAR57[0])), VAR118[3]},
VAR7 = {(VAR7[2] & VAR57[2]), (VAR7[1] & VAR57[1]), (VAR7[0] & VAR57[0]), VAR118[3]},
VAR76 = {(VAR76[2] & (~ VAR71[5])), (VAR76[1] & (~ VAR71[4])), (VAR76[0] & (~ VAR71[3])), 1'b1},
VAR99 = {(VAR99[2] & (~ VAR57[2])), (VAR99[1] & (~ VAR57[1])), (VAR99[0] & (~ VAR57[0])), VAR76[3]},
VAR84 = {(VAR84[2] & (~ VAR57[2])), (VAR84[1] & (~ VAR57[1])), (VAR84[0] & VAR57[0]), VAR76[3]},
VAR93 = {(VAR93[2] & (~ VAR57[2])), (VAR93[1] & VAR57[1]), (VAR93[0] & (~ VAR57[0])), VAR76[3]},
VAR120 = {(VAR120[2] & (~ VAR57[2])), (VAR120[1] & VAR57[1]), (VAR120[0] & VAR57[0]), VAR76[3]},
VAR36 = {(VAR36[2] & VAR57[2]), (VAR36[1] & (~ VAR57[1])), (VAR36[0] & (~ VAR57[0])), VAR76[3]},
VAR61 = {(VAR61[2] & VAR57[2]), (VAR61[1] & (~ VAR57[1])), (VAR61[0] & VAR57[0]), VAR76[3]},
VAR38 = {(VAR38[2] & VAR57[2]), (VAR38[1] & VAR57[1]), (VAR38[0] & (~ VAR57[0])), VAR76[3]},
VAR147 = {(VAR147[2] & VAR57[2]), (VAR147[1] & VAR57[1]), (VAR147[0] & VAR57[0]), VAR76[3]},
VAR41 = {(VAR41[2] & (~ VAR71[5])), (VAR41[1] & (~ VAR71[4])), (VAR41[0] & VAR71[3]), 1'b1},
VAR89 = {(VAR89[2] & (~ VAR57[2])), (VAR89[1] & (~ VAR57[1])), (VAR89[0] & (~ VAR57[0])), VAR41[3]},
VAR130 = {(VAR130[2] & (~ VAR57[2])), (VAR130[1] & (~ VAR57[1])), (VAR130[0] & VAR57[0]), VAR41[3]},
VAR82 = {(VAR82[2] & (~ VAR57[2])), (VAR82[1] & VAR57[1]), (VAR82[0] & (~ VAR57[0])), VAR41[3]},
VAR59 = {(VAR59[2] & (~ VAR57[2])), (VAR59[1] & VAR57[1]), (VAR59[0] & VAR57[0]), VAR41[3]},
VAR110 = {(VAR110[2] & VAR57[2]), (VAR110[1] & (~ VAR57[1])), (VAR110[0] & (~ VAR57[0])), VAR41[3]},
VAR13 = {(VAR13[2] & VAR57[2]), (VAR13[1] & (~ VAR57[1])), (VAR13[0] & VAR57[0]), VAR41[3]},
VAR43 = {(VAR43[2] & VAR57[2]), (VAR43[1] & VAR57[1]), (VAR43[0] & (~ VAR57[0])), VAR41[3]},
VAR123 = {(VAR123[2] & VAR57[2]), (VAR123[1] & VAR57[1]), (VAR123[0] & VAR57[0]), VAR41[3]},
VAR88 = {(VAR88[2] & (~ VAR71[5])), (VAR88[1] & VAR71[4]), (VAR88[0] & (~ VAR71[3])), 1'b1},
VAR18 = {(VAR18[2] & (~ VAR57[2])), (VAR18[1] & (~ VAR57[1])), (VAR18[0] & (~ VAR57[0])), VAR88[3]},
VAR6 = {(VAR6[2] & (~ VAR57[2])), (VAR6[1] & (~ VAR57[1])), (VAR6[0] & VAR57[0]), VAR88[3]},
VAR143 = {(VAR143[2] & (~ VAR57[2])), (VAR143[1] & VAR57[1]), (VAR143[0] & (~ VAR57[0])), VAR88[3]},
VAR26 = {(VAR26[2] & (~ VAR57[2])), (VAR26[1] & VAR57[1]), (VAR26[0] & VAR57[0]), VAR88[3]},
VAR125 = {(VAR125[2] & VAR57[2]), (VAR125[1] & (~ VAR57[1])), (VAR125[0] & (~ VAR57[0])), VAR88[3]},
VAR44 = {(VAR44[2] & VAR57[2]), (VAR44[1] & (~ VAR57[1])), (VAR44[0] & VAR57[0]), VAR88[3]},
VAR60 = {(VAR60[2] & VAR57[2]), (VAR60[1] & VAR57[1]), (VAR60[0] & (~ VAR57[0])), VAR88[3]},
VAR141 = {(VAR141[2] & VAR57[2]), (VAR141[1] & VAR57[1]), (VAR141[0] & VAR57[0]), VAR88[3]},
VAR24 = {(VAR24[2] & (~ VAR71[5])), (VAR24[1] & VAR71[4]), (VAR24[0] & VAR71[3]), 1'b1},
VAR108 = {(VAR108[2] & (~ VAR57[2])), (VAR108[1] & (~ VAR57[1])), (VAR108[0] & (~ VAR57[0])), VAR24[3]},
VAR15 = {(VAR15[2] & (~ VAR57[2])), (VAR15[1] & (~ VAR57[1])), (VAR15[0] & VAR57[0]), VAR24[3]},
VAR31 = {(VAR31[2] & (~ VAR57[2])), (VAR31[1] & VAR57[1]), (VAR31[0] & (~ VAR57[0])), VAR24[3]},
VAR133 = {(VAR133[2] & (~ VAR57[2])), (VAR133[1] & VAR57[1]), (VAR133[0] & VAR57[0]), VAR24[3]},
VAR102 = {(VAR102[2] & VAR57[2]), (VAR102[1] & (~ VAR57[1])), (VAR102[0] & (~ VAR57[0])), VAR24[3]},
VAR131 = {(VAR131[2] & VAR57[2]), (VAR131[1] & (~ VAR57[1])), (VAR131[0] & VAR57[0]), VAR24[3]},
VAR65 = {(VAR65[2] & VAR57[2]), (VAR65[1] & VAR57[1]), (VAR65[0] & (~ VAR57[0])), VAR24[3]},
VAR106 = {(VAR106[2] & VAR57[2]), (VAR106[1] & VAR57[1]), (VAR106[0] & VAR57[0]), VAR24[3]},
VAR34 = {(VAR34[2] & VAR71[5]), (VAR34[1] & (~ VAR71[4])), (VAR34[0] & (~ VAR71[3])), 1'b1},
VAR109 = {(VAR109[2] & (~ VAR57[2])), (VAR109[1] & (~ VAR57[1])), (VAR109[0] & (~ VAR57[0])), VAR34[3]},
VAR14 = {(VAR14[2] & (~ VAR57[2])), (VAR14[1] & (~ VAR57[1])), (VAR14[0] & VAR57[0]), VAR34[3]},
VAR17 = {(VAR17[2] & (~ VAR57[2])), (VAR17[1] & VAR57[1]), (VAR17[0] & (~ VAR57[0])), VAR34[3]},
VAR29 = {(VAR29[2] & (~ VAR57[2])), (VAR29[1] & VAR57[1]), (VAR29[0] & VAR57[0]), VAR34[3]},
VAR67 = {(VAR67[2] & VAR57[2]), (VAR67[1] & (~ VAR57[1])), (VAR67[0] & (~ VAR57[0])), VAR34[3]},
VAR21 = {(VAR21[2] & VAR57[2]), (VAR21[1] & (~ VAR57[1])), (VAR21[0] & VAR57[0]), VAR34[3]},
VAR11 = {(VAR11[2] & VAR57[2]), (VAR11[1] & VAR57[1]), (VAR11[0] & (~ VAR57[0])), VAR34[3]},
VAR30 = {(VAR30[2] & VAR57[2]), (VAR30[1] & VAR57[1]), (VAR30[0] & VAR57[0]), VAR34[3]},
VAR37 = {(VAR37[2] & VAR71[5]), (VAR37[1] & (~ VAR71[4])), (VAR37[0] & VAR71[3]), 1'b1},
VAR128 = {(VAR128[2] & (~ VAR57[2])), (VAR128[1] & (~ VAR57[1])), (VAR128[0] & (~ VAR57[0])), VAR37[3]},
VAR32 = {(VAR32[2] & (~ VAR57[2])), (VAR32[1] & (~ VAR57[1])), (VAR32[0] & VAR57[0]), VAR37[3]},
VAR73 = {(VAR73[2] & (~ VAR57[2])), (VAR73[1] & VAR57[1]), (VAR73[0] & (~ VAR57[0])), VAR37[3]},
VAR53 = {(VAR53[2] & (~ VAR57[2])), (VAR53[1] & VAR57[1]), (VAR53[0] & VAR57[0]), VAR37[3]},
VAR57 = VAR71[2:0];
endmodule
module MODULE3
(
clk,
VAR9,
VAR27,
VAR55,
VAR83,
VAR77,
VAR62,
VAR68) ;
parameter VAR5 = 0;
input clk;
input VAR9;
input [38:0] VAR27;
output VAR55;
output VAR83;
output VAR77;
output VAR62;
output [31:0] VAR68;
wire [63:0] VAR49;
wire VAR136;
wire VAR1;
wire VAR42;
wire VAR58;
wire VAR70;
wire VAR39;
wire VAR92;
wire VAR98;
wire VAR63;
wire VAR45;
wire VAR69;
wire VAR140;
wire VAR122;
wire VAR95;
wire VAR107;
wire VAR146;
wire VAR12;
wire VAR105;
wire VAR33;
wire VAR79;
wire VAR19;
wire VAR129;
wire VAR114;
wire VAR54;
wire VAR91;
wire VAR81;
wire VAR46;
wire VAR4;
wire VAR138;
wire VAR51;
wire VAR35;
wire VAR97;
wire VAR126;
wire [31:0] VAR132;
wire [38:0] VAR71;
wire [63:0] VAR145;
wire VAR64;
wire VAR94;
wire VAR20;
wire [18:0] VAR127;
wire [9:0] VAR116;
wire [4:0] VAR22;
wire [1:0] VAR112;
wire [0:0] VAR25;
wire [5:0] VAR72;
wire VAR80;
wire [37:0] VAR119;
wire [5:0] VAR52;
wire [31:0] VAR50;
wire VAR23;
wire VAR137;
wire [4:0] VAR117;
wire [6:0] VAR85;
reg [6:0] VAR3;
reg [38:0] VAR142;
generate
if (VAR5 == 1)
begin
always @ (posedge clk or negedge VAR9)
begin
if (!VAR9)
begin
VAR3 <= {7{1'b0}};
VAR142 <= {39{1'b0}};
end else
begin
VAR3 <= VAR85;
VAR142 <= VAR71;
end
end
end else
begin
always @ (*)
begin
VAR3 = VAR85;
VAR142 = VAR71;
end
end
endgenerate
MODULE1 MODULE1
(
.VAR27(VAR3[5:0]),
.VAR8(VAR49));
assign VAR136 = (VAR3[6] == 1'b1) ? (VAR145[3] ^ VAR142[0]) : VAR142[0];
assign VAR1 = (VAR3[6] == 1'b1) ? (VAR145[5] ^ VAR142[1]) : VAR142[1];
assign VAR42 = (VAR3[6] == 1'b1) ? (VAR145[15] ^ VAR142[10]) : VAR142[10];
assign VAR58 = (VAR3[6] == 1'b1) ? (VAR145[17] ^ VAR142[11]) : VAR142[11];
assign VAR70 = (VAR3[6] == 1'b1) ? (VAR145[18] ^ VAR142[12]) : VAR142[12];
assign VAR39 = (VAR3[6] == 1'b1) ? (VAR145[19] ^ VAR142[13]) : VAR142[13];
assign VAR92 = (VAR3[6] == 1'b1) ? (VAR145[20] ^ VAR142[14]) : VAR142[14];
assign VAR98 = (VAR3[6] == 1'b1) ? (VAR145[21] ^ VAR142[15]) : VAR142[15];
assign VAR63 = (VAR3[6] == 1'b1) ? (VAR145[22] ^ VAR142[16]) : VAR142[16];
assign VAR45 = (VAR3[6] == 1'b1) ? (VAR145[23] ^ VAR142[17]) : VAR142[17];
assign VAR69 = (VAR3[6] == 1'b1) ? (VAR145[24] ^ VAR142[18]) : VAR142[18];
assign VAR140 = (VAR3[6] == 1'b1) ? (VAR145[25] ^ VAR142[19]) : VAR142[19];
assign VAR122 = (VAR3[6] == 1'b1) ? (VAR145[6] ^ VAR142[2]) : VAR142[2];
assign VAR95 = (VAR3[6] == 1'b1) ? (VAR145[26] ^ VAR142[20]) : VAR142[20];
assign VAR107 = (VAR3[6] == 1'b1) ? (VAR145[27] ^ VAR142[21]) : VAR142[21];
assign VAR146 = (VAR3[6] == 1'b1) ? (VAR145[28] ^ VAR142[22]) : VAR142[22];
assign VAR12 = (VAR3[6] == 1'b1) ? (VAR145[29] ^ VAR142[23]) : VAR142[23];
assign VAR105 = (VAR3[6] == 1'b1) ? (VAR145[30] ^ VAR142[24]) : VAR142[24];
assign VAR33 = (VAR3[6] == 1'b1) ? (VAR145[31] ^ VAR142[25]) : VAR142[25];
assign VAR79 = (VAR3[6] == 1'b1) ? (VAR145[33] ^ VAR142[26]) : VAR142[26];
assign VAR19 = (VAR3[6] == 1'b1) ? (VAR145[34] ^ VAR142[27]) : VAR142[27];
assign VAR129 = (VAR3[6] == 1'b1) ? (VAR145[35] ^ VAR142[28]) : VAR142[28];
assign VAR114 = (VAR3[6] == 1'b1) ? (VAR145[36] ^ VAR142[29]) : VAR142[29];
assign VAR54 = (VAR3[6] == 1'b1) ? (VAR145[7] ^ VAR142[3]) : VAR142[3];
assign VAR91 = (VAR3[6] == 1'b1) ? (VAR145[37] ^ VAR142[30]) : VAR142[30];
assign VAR81 = (VAR3[6] == 1'b1) ? (VAR145[38] ^ VAR142[31]) : VAR142[31];
assign VAR46 = (VAR3[6] == 1'b1) ? (VAR145[9] ^ VAR142[4]) : VAR142[4];
assign VAR4 = (VAR3[6] == 1'b1) ? (VAR145[10] ^ VAR142[5]) : VAR142[5];
assign VAR138 = (VAR3[6] == 1'b1) ? (VAR145[11] ^ VAR142[6]) : VAR142[6];
assign VAR51 = (VAR3[6] == 1'b1) ? (VAR145[12] ^ VAR142[7]) : VAR142[7];
assign VAR35 = (VAR3[6] == 1'b1) ? (VAR145[13] ^ VAR142[8]) : VAR142[8];
assign VAR97 = (VAR3[6] == 1'b1) ? (VAR145[14] ^ VAR142[9]) : VAR142[9];
assign
VAR126 = VAR132[31],
VAR132 = {(VAR132[30] | VAR145[38]), (VAR132[29] | VAR145[37]), (VAR132[28] | VAR145[36]), (VAR132[27] | VAR145[35]), (VAR132[26] | VAR145[34]), (VAR132[25] | VAR145[33]), (VAR132[24] | VAR145[31]), (VAR132[23] | VAR145[30]), (VAR132[22] | VAR145[29]), (VAR132[21] | VAR145[28]), (VAR132[20] | VAR145[27]), (VAR132[19] | VAR145[26]), (VAR132[18] | VAR145[25]), (VAR132[17] | VAR145[24]), (VAR132[16] | VAR145[23]), (VAR132[15] | VAR145[22]), (VAR132[14] | VAR145[21]), (VAR132[13] | VAR145[20]), (VAR132[12] | VAR145[19]), (VAR132[11] | VAR145[18]), (VAR132[10] | VAR145[17]), (VAR132[9] | VAR145[15]), (VAR132[8] | VAR145[14]), (VAR132[7] | VAR145[13]), (VAR132[6] | VAR145[12]), (VAR132[5] | VAR145[11]), (VAR132[4] | VAR145[10]), (VAR132[3] | VAR145[9]), (VAR132[2] | VAR145[7]), (VAR132[1] | VAR145[6]), (VAR132[0] | VAR145[5]), VAR145[3]},
VAR71 = VAR27,
VAR145 = VAR49,
VAR55 = VAR64,
VAR64 = ((VAR23 & VAR137) & VAR126),
VAR83 = VAR94,
VAR94 = (VAR23 & (~ (VAR137 & VAR80))),
VAR77 = VAR20,
VAR62 = VAR137,
VAR20 = (VAR94 & (~ VAR64)),
VAR127 = {(VAR71[30] ^ VAR127[17]), (VAR71[28] ^ VAR127[16]), (VAR71[26] ^ VAR127[15]), (VAR71[25] ^ VAR127[14]), (VAR71[23] ^ VAR127[13]), (VAR71[21] ^ VAR127[12]), (VAR71[19] ^ VAR127[11]), (VAR71[17] ^ VAR127[10]), (VAR71[15] ^ VAR127[9]), (VAR71[13] ^ VAR127[8]), (VAR71[11] ^ VAR127[7]), (VAR71[10] ^ VAR127[6]), (VAR71[8] ^ VAR127[5]), (VAR71[6] ^ VAR127[4]), (VAR71[4] ^ VAR127[3]), (VAR71[3] ^ VAR127[2]), (VAR71[1] ^ VAR127[1]), (VAR71[0] ^ VAR127[0]), VAR71[32]},
VAR116 = {(VAR71[31] ^ VAR116[8]), ((VAR71[27] ^ VAR71[28]) ^ VAR116[7]), ((VAR71[24] ^ VAR71[25]) ^ VAR116[6]), ((VAR71[20] ^ VAR71[21]) ^ VAR116[5]), ((VAR71[16] ^ VAR71[17]) ^ VAR116[4]), ((VAR71[12] ^ VAR71[13]) ^ VAR116[3]), ((VAR71[9] ^ VAR71[10]) ^ VAR116[2]), ((VAR71[5] ^ VAR71[6]) ^ VAR116[1]), ((VAR71[2] ^ VAR71[3]) ^ VAR116[0]), (VAR71[33] ^ VAR71[0])},
VAR22 = {(((VAR71[29] ^ VAR71[30]) ^ VAR71[31]) ^ VAR22[3]), ((((VAR71[22] ^ VAR71[23]) ^ VAR71[24]) ^ VAR71[25]) ^ VAR22[2]), ((((VAR71[14] ^ VAR71[15]) ^ VAR71[16]) ^ VAR71[17]) ^ VAR22[1]), ((((VAR71[7] ^ VAR71[8]) ^ VAR71[9]) ^ VAR71[10]) ^ VAR22[0]), (((VAR71[34] ^ VAR71[1]) ^ VAR71[2]) ^ VAR71[3])},
VAR112 = {((((((((VAR71[18] ^ VAR71[19]) ^ VAR71[20]) ^ VAR71[21]) ^ VAR71[22]) ^ VAR71[23]) ^ VAR71[24]) ^ VAR71[25]) ^ VAR112[0]), (((((((VAR71[35] ^ VAR71[4]) ^ VAR71[5]) ^ VAR71[6]) ^ VAR71[7]) ^ VAR71[8]) ^ VAR71[9]) ^ VAR71[10])},
VAR25 = {(((((((((((((((VAR71[36] ^ VAR71[11]) ^ VAR71[12]) ^ VAR71[13]) ^ VAR71[14]) ^ VAR71[15]) ^ VAR71[16]) ^ VAR71[17]) ^ VAR71[18]) ^ VAR71[19]) ^ VAR71[20]) ^ VAR71[21]) ^ VAR71[22]) ^ VAR71[23]) ^ VAR71[24]) ^ VAR71[25])},
VAR72 = {(VAR71[31] ^ VAR72[4]), (VAR71[30] ^ VAR72[3]), (VAR71[29] ^ VAR72[2]), (VAR71[28] ^ VAR72[1]), (VAR71[27] ^ VAR72[0]), (VAR71[37] ^ VAR71[26])},
VAR80 = VAR52[5],
VAR119 = {(VAR71[37] ^ VAR119[36]), (VAR71[36] ^ VAR119[35]), (VAR71[35] ^ VAR119[34]), (VAR71[34] ^ VAR119[33]), (VAR71[33] ^ VAR119[32]), (VAR71[32] ^ VAR119[31]), (VAR71[31] ^ VAR119[30]), (VAR71[30] ^ VAR119[29]), (VAR71[29] ^ VAR119[28]), (VAR71[28] ^ VAR119[27]), (VAR71[27] ^ VAR119[26]), (VAR71[26] ^ VAR119[25]), (VAR71[25] ^ VAR119[24]), (VAR71[24] ^ VAR119[23]), (VAR71[23] ^ VAR119[22]), (VAR71[22] ^ VAR119[21]), (VAR71[21] ^ VAR119[20]), (VAR71[20] ^ VAR119[19]), (VAR71[19] ^ VAR119[18]), (VAR71[18] ^ VAR119[17]), (VAR71[17] ^ VAR119[16]), (VAR71[16] ^ VAR119[15]), (VAR71[15] ^ VAR119[14]), (VAR71[14] ^ VAR119[13]), (VAR71[13] ^ VAR119[12]), (VAR71[12] ^ VAR119[11]), (VAR71[11] ^ VAR119[10]), (VAR71[10] ^ VAR119[9]), (VAR71[9] ^ VAR119[8]), (VAR71[8] ^ VAR119[7]), (VAR71[7] ^ VAR119[6]), (VAR71[6] ^ VAR119[5]), (VAR71[5] ^ VAR119[4]), (VAR71[4] ^ VAR119[3]), (VAR71[3] ^ VAR119[2]), (VAR71[2] ^ VAR119[1]), (VAR71[1] ^ VAR119[0]), (VAR71[38] ^ VAR71[0])},
VAR52 = {(VAR52[4] | VAR145[32]), (VAR52[3] | VAR145[16]), (VAR52[2] | VAR145[8]), (VAR52[1] | VAR145[4]), (VAR52[0] | VAR145[2]), VAR145[1]},
VAR68 = VAR50,
VAR50 = {VAR81, VAR91, VAR114, VAR129, VAR19, VAR79, VAR33, VAR105, VAR12, VAR146, VAR107, VAR95, VAR140, VAR69, VAR45, VAR63, VAR98, VAR92, VAR39, VAR70, VAR58, VAR42, VAR97, VAR35, VAR51, VAR138, VAR4, VAR46, VAR54, VAR122, VAR1, VAR136},
VAR23 = VAR117[4],
VAR137 = VAR3[6],
VAR117 = {(VAR117[3] | VAR3[5]), (VAR117[2] | VAR3[4]), (VAR117[1] | VAR3[3]), (VAR117[0] | VAR3[2]), (VAR3[0] | VAR3[1])},
VAR85 = {VAR119[37], VAR72[5], VAR25[0], VAR112[1], VAR22[4], VAR116[9], VAR127[18]};
endmodule
module MODULE2
parameter
VAR5 = 1
)
(
clk,
VAR9,
VAR27,
VAR55,
VAR83,
VAR77,
VAR62,
VAR68);
input clk;
input VAR9;
input [38:0] VAR27;
output VAR55;
output VAR83;
output VAR77;
output VAR62;
output [31:0] VAR68;
wire VAR90;
wire VAR100;
wire VAR87;
wire VAR40;
wire [31:0] VAR115;
wire VAR83 = VAR90;
wire VAR77 = VAR100;
wire VAR55 = VAR87;
wire VAR62 = VAR40;
wire [31:0] VAR68 = VAR115[31:0];
MODULE3
.VAR5 (VAR5)
)
VAR75 (
.clk (clk),
.VAR9 (VAR9),
.VAR27 (VAR27),
.VAR83 (VAR90),
.VAR77 (VAR100),
.VAR55 (VAR87),
.VAR62 (VAR40),
.VAR68 (VAR115));
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o311a/sky130_fd_sc_ls__o311a_1.v
| 2,422 |
module MODULE2 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR12 ,
VAR11,
VAR1,
VAR8 ,
VAR2
);
output VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR12 ;
input VAR11;
input VAR1;
input VAR8 ;
input VAR2 ;
VAR10 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR9 ,
VAR6,
VAR7,
VAR5,
VAR4,
VAR12
);
output VAR9 ;
input VAR6;
input VAR7;
input VAR5;
input VAR4;
input VAR12;
supply1 VAR11;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR2 ;
VAR10 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR12(VAR12)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/or2b/sky130_fd_sc_hd__or2b.behavioral.v
| 1,442 |
module MODULE1 (
VAR5 ,
VAR10 ,
VAR9
);
output VAR5 ;
input VAR10 ;
input VAR9;
supply1 VAR8;
supply0 VAR12;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR4 ;
wire VAR7;
not VAR3 (VAR4 , VAR9 );
or VAR11 (VAR7, VAR4, VAR10 );
buf VAR1 (VAR5 , VAR7 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21o/sky130_fd_sc_hdll__a21o.symbol.v
| 1,349 |
module MODULE1 (
input VAR3,
input VAR1,
input VAR4,
output VAR5
);
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/FSM_Add_Subtract_syn.v
| 5,547 |
module MODULE1 ( clk, rst, VAR148, VAR158, VAR48,
VAR55, VAR112, VAR16, VAR22, VAR25,
VAR167, VAR128, VAR168, VAR159, VAR153, VAR69,
VAR175, VAR8, VAR81, VAR88, VAR100, VAR140,
VAR161, VAR97, VAR121, ready );
output [1:0] VAR100;
input clk, rst, VAR148, VAR158, VAR48, VAR55,
VAR112, VAR16;
output VAR22, VAR25, VAR167, VAR128, VAR168, VAR159,
VAR153, VAR69, VAR175, VAR8, VAR81, VAR88,
VAR140, VAR161, VAR97, VAR121, ready;
wire VAR147, VAR164, VAR141, VAR97, VAR172, VAR125, VAR108, VAR9, VAR76, VAR135, VAR14, VAR176, VAR7, VAR33,
VAR162, VAR173, VAR5, VAR138, VAR122, VAR143, VAR94, VAR149, VAR35, VAR32, VAR1, VAR13, VAR24, VAR174,
VAR110, VAR79, VAR152, VAR72, VAR71, VAR54, VAR36, VAR150, VAR21, VAR129, VAR130, VAR61, VAR144, VAR145,
VAR151, VAR123, VAR170, VAR11, VAR17, VAR127, VAR75, VAR115, VAR68;
wire [3:0] VAR136;
assign VAR88 = VAR97;
VAR66 VAR180 ( .VAR27(rst), .VAR82(VAR147) );
VAR91 \VAR178[2] ( .VAR117(VAR127), .VAR74(clk), .VAR3(VAR147), .VAR114(VAR136[2]),
.VAR45(VAR135) );
VAR91 \VAR178[3] ( .VAR117(VAR115), .VAR74(clk), .VAR3(VAR147), .VAR114(VAR136[3]),
.VAR45(VAR108) );
VAR91 \VAR178[1] ( .VAR117(VAR75), .VAR74(clk), .VAR3(VAR147), .VAR114(VAR136[1]),
.VAR45(VAR14) );
VAR91 \VAR178[0] ( .VAR117(VAR68), .VAR74(clk), .VAR3(VAR147), .VAR114(VAR136[0]),
.VAR45(VAR176) );
VAR60 VAR104 ( .VAR59(VAR61), .VAR92(VAR176), .VAR99(VAR136[1]), .VAR82(VAR143) );
VAR86 VAR47 ( .VAR27(VAR14), .VAR92(VAR136[3]), .VAR82(VAR11) );
VAR124 VAR40 ( .VAR27(VAR14), .VAR92(VAR108), .VAR99(VAR123), .VAR82(VAR150) );
VAR124 VAR118 ( .VAR27(VAR14), .VAR92(VAR108), .VAR99(VAR170), .VAR82(VAR24) );
VAR124 VAR96 ( .VAR27(VAR136[1]), .VAR92(VAR176), .VAR99(VAR61), .VAR82(VAR32) );
VAR124 VAR126 ( .VAR27(VAR136[1]), .VAR92(VAR123), .VAR99(VAR136[3]), .VAR82(VAR162) );
VAR98 VAR29 ( .VAR27(VAR129), .VAR92(VAR149), .VAR82(VAR175) );
VAR66 VAR102 ( .VAR27(VAR129), .VAR82(VAR161) );
VAR156 VAR120 ( .VAR157(VAR24), .VAR169(VAR7), .VAR116(VAR122), .VAR82(VAR152) );
VAR156 VAR95 ( .VAR157(VAR7), .VAR169(VAR150), .VAR116(VAR174), .VAR82(VAR128) );
VAR66 VAR106 ( .VAR27(VAR35), .VAR82(VAR97) );
VAR66 VAR15 ( .VAR27(VAR5), .VAR82(VAR9) );
VAR46 VAR89 ( .VAR27(VAR25), .VAR92(VAR22), .VAR99(VAR81), .VAR82(VAR13) );
VAR98 VAR56 ( .VAR27(VAR11), .VAR92(VAR123), .VAR82(VAR129) );
VAR98 VAR38 ( .VAR27(VAR170), .VAR92(VAR11), .VAR82(VAR149) );
VAR98 VAR109 ( .VAR27(VAR130), .VAR92(VAR32), .VAR82(VAR140) );
VAR98 VAR134 ( .VAR27(VAR24), .VAR92(VAR122), .VAR82(VAR159) );
VAR124 VAR87 ( .VAR27(VAR150), .VAR92(VAR21), .VAR99(VAR174), .VAR82(VAR167) );
VAR66 VAR37 ( .VAR27(VAR36), .VAR82(VAR25) );
VAR66 VAR163 ( .VAR27(VAR150), .VAR82(VAR141) );
VAR66 VAR93 ( .VAR27(VAR54), .VAR82(VAR121) );
VAR66 VAR155 ( .VAR27(VAR130), .VAR82(VAR8) );
VAR66 VAR50 ( .VAR27(VAR162), .VAR82(ready) );
VAR66 VAR20 ( .VAR27(VAR24), .VAR82(VAR125) );
VAR66 VAR53 ( .VAR27(VAR32), .VAR82(VAR172) );
VAR98 VAR52 ( .VAR27(VAR16), .VAR92(VAR143), .VAR82(VAR35) );
VAR77 VAR12 ( .VAR27(VAR112), .VAR92(VAR13), .VAR99(VAR144), .VAR117(VAR145), .VAR82(VAR168)
);
VAR83 VAR142 ( .VAR27(VAR151), .VAR92(VAR140), .VAR99(VAR175), .VAR117(VAR159), .VAR82(
VAR145) );
VAR31 VAR73 ( .VAR157(VAR141), .VAR169(VAR7), .VAR116(VAR170), .VAR49(VAR143), .VAR82(VAR144) );
VAR124 VAR58 ( .VAR27(VAR162), .VAR92(VAR54), .VAR99(VAR21), .VAR82(VAR151) );
VAR66 VAR28 ( .VAR27(VAR55), .VAR82(VAR7) );
VAR34 VAR160 ( .VAR59(VAR140), .VAR92(VAR112), .VAR82(VAR100[0]) );
VAR171 VAR85 ( .VAR157(VAR152), .VAR169(VAR128), .VAR116(VAR112), .VAR82(VAR69)
);
VAR154 VAR80 ( .VAR84(VAR8), .VAR51(VAR112), .VAR116(VAR32), .VAR82(
VAR100[1]) );
VAR31 VAR166 ( .VAR157(VAR150), .VAR169(VAR24), .VAR116(VAR7), .VAR49(VAR112), .VAR82(
VAR153) );
VAR67 VAR165 ( .VAR157(VAR25), .VAR169(VAR48), .VAR116(VAR81), .VAR82(VAR5) );
VAR23 VAR133 ( .VAR157(VAR158), .VAR169(VAR54), .VAR116(VAR148), .VAR2(VAR162), .VAR82(VAR94) );
VAR62 VAR131 ( .VAR59(VAR175), .VAR92(VAR174), .VAR99(VAR110), .VAR117(VAR79), .VAR82(VAR115) );
VAR67 VAR43 ( .VAR157(VAR143), .VAR169(VAR33), .VAR116(VAR172), .VAR82(VAR110) );
VAR31 VAR70 ( .VAR157(VAR136[3]), .VAR169(VAR94), .VAR116(VAR152), .VAR49(VAR9), .VAR82(VAR79)
);
VAR66 VAR132 ( .VAR27(VAR16), .VAR82(VAR33) );
VAR77 VAR146 ( .VAR27(VAR149), .VAR92(VAR35), .VAR99(VAR32), .VAR117(VAR1), .VAR82(VAR75) );
VAR30 VAR119 ( .VAR157(VAR125), .VAR169(VAR7), .VAR116(VAR136[1]), .VAR2(VAR94), .VAR49(VAR76),
.VAR82(VAR1) );
VAR66 VAR64 ( .VAR27(VAR13), .VAR82(VAR76) );
VAR4 VAR44 ( .VAR157(VAR72), .VAR169(VAR164), .VAR137(VAR71), .VAR116(VAR94), .VAR82(VAR68) );
VAR46 VAR105 ( .VAR27(VAR143), .VAR92(VAR121), .VAR99(VAR141), .VAR82(VAR71) );
VAR57 VAR41 ( .VAR84(VAR36), .VAR51(VAR48), .VAR116(VAR172), .VAR82(VAR72) );
VAR66 VAR19 ( .VAR27(VAR152), .VAR82(VAR164) );
VAR86 VAR113 ( .VAR27(VAR135), .VAR92(VAR136[0]), .VAR82(VAR123) );
VAR86 VAR18 ( .VAR27(VAR108), .VAR92(VAR136[2]), .VAR82(VAR61) );
VAR86 VAR78 ( .VAR27(VAR176), .VAR92(VAR135), .VAR82(VAR170) );
VAR46 VAR63 ( .VAR27(VAR136[2]), .VAR92(VAR136[3]), .VAR99(VAR136[1]), .VAR82(VAR17) );
VAR124 VAR181 ( .VAR27(VAR176), .VAR92(VAR14), .VAR99(VAR61), .VAR82(VAR130) );
VAR124 VAR107 ( .VAR27(VAR136[0]), .VAR92(VAR136[1]), .VAR99(VAR61), .VAR82(VAR174) );
VAR124 VAR111 ( .VAR27(VAR11), .VAR92(VAR135), .VAR99(VAR136[0]), .VAR82(VAR21) );
VAR98 VAR6 ( .VAR27(VAR17), .VAR92(VAR176), .VAR82(VAR54) );
VAR124 VAR90 ( .VAR27(VAR176), .VAR92(VAR135), .VAR99(VAR11), .VAR82(VAR36) );
VAR124 VAR103 ( .VAR27(VAR123), .VAR92(VAR14), .VAR99(VAR136[3]), .VAR82(VAR122) );
VAR101 VAR42 ( .VAR27(VAR170), .VAR92(VAR136[3]), .VAR99(VAR14), .VAR82(VAR81) );
VAR124 VAR179 ( .VAR27(VAR173), .VAR92(VAR5), .VAR99(VAR138), .VAR82(VAR127) );
VAR65 VAR26 ( .VAR59(VAR122), .VAR92(VAR167), .VAR99(VAR8), .VAR117(VAR143), .VAR82(VAR138) );
VAR177 VAR139 ( .VAR157(VAR125), .VAR169(VAR7), .VAR116(VAR136[2]), .VAR2(VAR94), .VAR82(VAR173) );
VAR10 VAR39 ( .VAR27(VAR17), .VAR92(VAR136[0]), .VAR82(VAR22) );
endmodule
|
gpl-3.0
|
ElegantLin/My-CPU
|
Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/id.v
| 30,092 |
module MODULE1(
input wire rst,
input wire[VAR40] VAR26,
input wire[VAR60] VAR15,
input wire[VAR51] VAR10,
input wire VAR52,
input wire[VAR59] VAR28,
input wire[VAR27] VAR58,
input wire VAR7,
input wire[VAR59] VAR45,
input wire[VAR27] VAR25,
input wire[VAR59] VAR24,
input wire[VAR59] VAR17,
input wire VAR5,
output reg VAR36,
output reg VAR21,
output reg[VAR27] VAR35,
output reg[VAR27] VAR61,
output reg[VAR51] VAR8,
output reg[VAR48] VAR33,
output reg[VAR59] VAR37,
output reg[VAR59] VAR19,
output reg[VAR27] VAR46,
output reg VAR53,
output wire[VAR59] VAR29,
output reg VAR11,
output reg VAR38,
output reg[VAR59] VAR9,
output reg[VAR59] VAR22,
output reg VAR57,
output wire[31:0] VAR56,
output wire[VAR59] VAR55,
output wire VAR47
);
wire[5:0] VAR49 = VAR15[31:26];
wire[4:0] VAR41 = VAR15[10:6];
wire[5:0] VAR64 = VAR15[5:0];
wire[4:0] VAR1 = VAR15[20:16];
reg[VAR59] VAR50;
reg VAR32;
wire[VAR59] VAR44;
wire[VAR59] VAR14;
wire[VAR59] VAR62;
reg VAR13;
reg VAR6;
wire VAR18;
reg VAR42;
reg VAR54;
assign VAR44 = (VAR26 > 32'h400000) ? (VAR26 + 4) : (VAR26 + 32'h400000 + 4);
assign VAR14 = VAR26 +4;
assign VAR62 = {{14{VAR15[15]}}, VAR15[15:0], 2'b00 };
assign VAR47 = VAR13 | VAR6;
assign VAR18 = ((VAR10 == VAR39) ||
(VAR10 == VAR63)||
(VAR10 == VAR16) ||
(VAR10 == VAR4)||
(VAR10 == VAR31) ||
(VAR10 == VAR12)||
(VAR10 == VAR2)||
(VAR10 == VAR65) ||
(VAR10 == VAR3)) ? 1'b1 : 1'b0;
assign VAR29 = VAR15;
assign VAR56 = {19'b0,VAR54,2'b0,
VAR32, VAR42,8'b0};
assign VAR55 = VAR26;
always @ begin
VAR13 <= VAR43;
if(rst == VAR34) begin
VAR37 <= VAR30;
end else if(VAR18 == 1'b1 && VAR58 == VAR35
&& VAR36 == 1'b1 ) begin
VAR13 <= VAR23;
end else if((VAR36 == 1'b1) && (VAR52 == 1'b1)
&& (VAR58 == VAR35) && (VAR35 != 5'b00000)) begin
VAR37 <= VAR28;
end else if((VAR36 == 1'b1) && (VAR52 == 1'b1)
&& (VAR58 == VAR35) && (VAR35 == 5'b00000)) begin
VAR37 <= VAR30;
end else if((VAR36 == 1'b1) && (VAR7 == 1'b1)
&& (VAR25 == VAR35) && (VAR35 != 5'b00000)) begin
VAR37 <= VAR45;
end else if((VAR36 == 1'b1) && (VAR52 == 1'b1)
&& (VAR25 == VAR35) && (VAR35 == 5'b00000)) begin
VAR37 <= VAR30;
end else if(VAR36 == 1'b1) begin
VAR37 <= VAR24;
end else if(VAR36 == 1'b0) begin
VAR37 <= VAR50;
end else begin
VAR37 <= VAR30;
end
end
always @ begin
if(rst == VAR34) begin
VAR57 <= VAR20;
end else begin
VAR57 <= VAR20;
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.functional.pp.v
| 1,868 |
module MODULE1 (
VAR8 ,
VAR11 ,
VAR12,
VAR2,
VAR9 ,
VAR5
);
output VAR8 ;
input VAR11 ;
input VAR12;
input VAR2;
input VAR9 ;
input VAR5 ;
wire VAR3 ;
wire VAR1;
buf VAR7 (VAR3 , VAR11 );
VAR6 VAR10 (VAR1, VAR3, VAR12, VAR2);
buf VAR4 (VAR8 , VAR1 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a211oi/sky130_fd_sc_hd__a211oi.functional.pp.v
| 2,044 |
module MODULE1 (
VAR6 ,
VAR13 ,
VAR10 ,
VAR11 ,
VAR16 ,
VAR5,
VAR14,
VAR1 ,
VAR9
);
output VAR6 ;
input VAR13 ;
input VAR10 ;
input VAR11 ;
input VAR16 ;
input VAR5;
input VAR14;
input VAR1 ;
input VAR9 ;
wire VAR2 ;
wire VAR17 ;
wire VAR4;
and VAR12 (VAR2 , VAR13, VAR10 );
nor VAR7 (VAR17 , VAR2, VAR11, VAR16 );
VAR8 VAR15 (VAR4, VAR17, VAR5, VAR14);
buf VAR3 (VAR6 , VAR4 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.blackbox.v
| 1,496 |
module MODULE1 (
VAR9 ,
VAR6 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR4
);
output VAR9 ;
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR4;
supply1 VAR10;
supply0 VAR5;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a21o/sky130_fd_sc_ms__a21o.pp.blackbox.v
| 1,351 |
module MODULE1 (
VAR7 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR8,
VAR1,
VAR4 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR8;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule
|
apache-2.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_098.v
| 1,421 |
module MODULE1 (
VAR8,
VAR7
);
input [31:0] VAR8;
output [31:0]
VAR7;
wire [31:0]
VAR11,
VAR9,
VAR1,
VAR4,
VAR12,
VAR5,
VAR2;
assign VAR11 = VAR8;
assign VAR1 = VAR9 - VAR11;
assign VAR9 = VAR11 << 2;
assign VAR12 = VAR4 - VAR1;
assign VAR4 = VAR11 << 6;
assign VAR2 = VAR5 - VAR1;
assign VAR5 = VAR12 << 7;
assign VAR7 = VAR2;
endmodule
module MODULE2(
VAR8,
VAR7,
clk
);
input [31:0] VAR8;
output [31:0] VAR7;
reg [31:0] VAR7;
input clk;
reg [31:0] VAR3;
wire [30:0] VAR6;
always @(posedge clk) begin
VAR3 <= VAR8;
VAR7 <= VAR6;
end
MODULE1 MODULE1(
.VAR8(VAR3),
.VAR7(VAR6)
);
endmodule
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_crossbar_v2_1/9368eebf/hdl/verilog/axi_crossbar_v2_1_wdata_mux.v
| 6,881 |
module MODULE1 #
(
parameter VAR37 = "none", parameter integer VAR14 = 1, parameter integer VAR43 = 1, parameter integer VAR47 = 1, parameter integer VAR8 = 0 )
(
input wire VAR4,
input wire VAR1,
input wire [VAR43*VAR14-1:0] VAR17,
input wire [VAR43-1:0] VAR19,
input wire [VAR43-1:0] VAR27,
output wire [VAR43-1:0] VAR5,
output wire [VAR14-1:0] VAR9,
output wire VAR7,
output wire VAR40,
input wire VAR25,
input wire [VAR47-1:0] VAR46, input wire VAR16,
output wire VAR33
);
localparam integer VAR39 = (VAR8 <= 5) ? VAR8 : 5;
function [VAR43-1:0] VAR6 (
input [VAR47-1:0] sel
);
integer VAR23;
begin
for (VAR23=0; VAR23<VAR43; VAR23=VAR23+1) begin
VAR6[VAR23] = (sel == VAR23);
end
end
endfunction
wire VAR31;
wire VAR12;
wire [VAR43-1:0] VAR15;
wire [VAR47-1:0] VAR28;
wire VAR22;
wire VAR20;
generate
if (VAR43>1) begin : VAR30
VAR35 #
(
.VAR37 (VAR37),
.VAR2 (VAR47),
.VAR8 (VAR39),
.VAR49 (0)
)
VAR26
(
.VAR4 (VAR4),
.VAR1 (VAR1),
.VAR38 (VAR46),
.VAR34 (VAR16),
.VAR3 (VAR33),
.VAR21 (VAR28),
.VAR11 (VAR22),
.VAR32 (VAR20)
);
assign VAR15 = VAR6(VAR28);
VAR24 #
(
.VAR37 ("VAR44"),
.VAR18 (VAR43),
.VAR42 (VAR47),
.VAR29 (VAR14)
) VAR41
(
.VAR48 (VAR28),
.VAR10 (VAR17),
.VAR36 (VAR9),
.VAR45 (1'b1)
);
assign VAR12 = |(VAR19 & VAR15);
assign VAR31 = |(VAR27 & VAR15);
assign VAR20 = VAR31 & VAR22 & VAR12 & VAR25;
assign VAR7 = VAR12;
assign VAR40 = VAR31 & VAR22;
assign VAR5 = VAR15 & {VAR43{VAR22 & VAR25}};
end else begin : VAR13
assign VAR33 = 1'b1;
assign VAR40 = VAR27;
assign VAR5 = VAR25;
assign VAR7 = VAR19;
assign VAR9 = VAR17;
end
endgenerate
endmodule
|
mit
|
jamesbowman/swapforth
|
j1a/icestorm/j4a.v
| 20,129 |
module MODULE2(
output [1:0] VAR45,
input VAR99, VAR67, VAR29,
input [10:0] VAR149,
input VAR158, VAR100, VAR121,
input [10:0] VAR147,
input [1:0] VAR75, VAR115
);
parameter VAR127 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR102 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR119 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR146 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR112 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR142 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR128 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR138 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR118 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
wire [15:0] rd;
VAR37 #(
.VAR59(3),
.VAR167(3),
.VAR127(VAR127),
.VAR102(VAR102),
.VAR119(VAR119),
.VAR146(VAR146),
.VAR11(VAR11),
.VAR112(VAR112),
.VAR142(VAR142),
.VAR55(VAR55),
.VAR48(VAR48),
.VAR128(VAR128),
.VAR36(VAR36),
.VAR2(VAR2),
.VAR138(VAR138),
.VAR118(VAR118),
.VAR1(VAR1),
.VAR65(VAR65)
) VAR83 (
.VAR45(rd),
.VAR149(VAR149),
.VAR99(VAR99), .VAR67(VAR67), .VAR29(VAR29),
.VAR158(VAR158), .VAR100(VAR100), .VAR121(VAR121),
.VAR147(VAR147),
.VAR75(16'h0000), .VAR115({4'b0, VAR115[1], 7'b0, VAR115[0], 3'b0}));
assign VAR45[0] = rd[3];
assign VAR45[1] = rd[11];
endmodule
module MODULE3(
input clk,
inout [7:0] VAR19,
input VAR64,
input [7:0] VAR26,
output [7:0] rd,
input [7:0] VAR94);
genvar VAR84;
generate
for (VAR84 = 0; VAR84 < 8; VAR84 = VAR84 + 1) begin : VAR143
VAR32 #(.VAR6(6'b100101)) VAR143 (
.VAR80(VAR19[VAR84]),
.VAR126(VAR64),
.VAR30(clk),
.VAR109(VAR26[VAR84]),
.VAR54(rd[VAR84]),
.VAR122(VAR94[VAR84]));
end
endgenerate
endmodule
module MODULE4(
input clk,
output VAR50,
input VAR64,
input VAR26,
output rd);
VAR32 #(.VAR6(6'b010101)) VAR143 (
.VAR80(VAR50),
.VAR126(VAR64),
.VAR30(clk),
.VAR109(VAR26),
.VAR54(rd));
endmodule
module MODULE5(
input clk,
input VAR50,
output rd);
VAR32 #(.VAR6(6'b000000)) VAR143 (
.VAR80(VAR50),
.VAR88(clk),
.VAR54(rd));
endmodule
module MODULE1(input VAR71,
output VAR60,
output VAR106,
output VAR154,
output VAR92,
output VAR7,
output VAR103, output VAR61, output VAR130,
output VAR117, input VAR161,
output VAR111, input VAR25, output VAR58, output VAR134,
inout VAR43, inout VAR160, inout VAR124, inout VAR90,
inout VAR107,
inout VAR14,
inout VAR35,
inout VAR153,
inout VAR27, inout VAR78, inout VAR97, inout VAR12, inout VAR114, inout VAR110, inout VAR39, inout VAR34,
inout VAR76, inout VAR136, inout VAR125, inout VAR17, inout VAR24, inout VAR116, inout VAR47, inout VAR69,
input reset
);
localparam VAR42 = 12;
wire clk;
wire VAR13;
VAR155 #(.VAR148("VAR93"),
.VAR141("VAR86"),
.VAR87(4'b0000),
.VAR104(7'd3),
.VAR77(3'b000),
.VAR81(3'b001),
) VAR73 (
.VAR38(VAR71),
.VAR133(clk),
.VAR123(VAR13),
.VAR105(reset),
.VAR108(1'b0)
);
wire VAR165, VAR46;
wire [15:0] VAR85;
wire VAR23;
wire [15:0] dout;
wire [15:0] VAR162;
wire [12:0] VAR53;
reg VAR20 = 0;
wire [1:0] VAR33;
wire [15:0] VAR89;
wire [3:0] VAR3;
VAR8 VAR8(
.clk(clk),
.VAR13(VAR13),
.VAR165(VAR165),
.VAR46(VAR46),
.VAR23(VAR23),
.dout(dout),
.VAR162(VAR162),
.VAR85(VAR85),
.VAR53(VAR53),
.VAR10(VAR10),
.VAR33(VAR33),
.VAR89(VAR89),
.VAR3(VAR3));
reg VAR46, VAR165;
reg [15:0] dout;
reg [15:0] VAR113;
reg [1:0] VAR33;
always @(posedge clk) begin
{VAR165, VAR46, dout} <= {VAR165, VAR46, dout};
VAR33 <= VAR33;
if (VAR165 | VAR46)
VAR113 <= VAR85;
end
else
VAR113 <= 0; end
reg [7:0] VAR129; wire [7:0] VAR96;
MODULE3 MODULE1 (.clk(clk),
.VAR19({VAR153, VAR35, VAR14, VAR107, VAR90, VAR124, VAR160, VAR43}),
.VAR64(VAR46 & VAR113[0]),
.VAR26(dout),
.rd(VAR96),
.VAR94(VAR129));
reg [7:0] VAR79; wire [7:0] VAR140;
MODULE3 MODULE2 (.clk(clk),
.VAR19({VAR34, VAR39, VAR110, VAR114, VAR12, VAR97, VAR78, VAR27}),
.VAR64(VAR46 & VAR113[4]),
.VAR26(dout[7:0]),
.rd(VAR140),
.VAR94(VAR79));
reg [7:0] VAR56; wire [7:0] VAR4;
MODULE3 MODULE4 (.clk(clk),
.VAR19({VAR69, VAR47, VAR116, VAR24, VAR17, VAR125, VAR136, VAR76}),
.VAR64(VAR46 & VAR113[6]),
.VAR26(dout[7:0]),
.rd(VAR4),
.VAR94(VAR56));
wire VAR95, VAR63;
wire [7:0] VAR28;
wire VAR164 = VAR46 & VAR113[12];
wire VAR70 = VAR165 & VAR113[12];
wire VAR49;
MODULE5 MODULE6(.clk(clk), .VAR50(VAR161), .rd(VAR49));
VAR91 VAR156 (
.clk(clk),
.VAR13(1'b1),
.VAR18(VAR49),
.VAR132(VAR117),
.rd(VAR70),
.wr(VAR164),
.valid(VAR95),
.VAR139(VAR63),
.VAR101(dout[7:0]),
.VAR9(VAR28));
wire [7:0] VAR62;
MODULE3 MODULE8 (.clk(clk),
.VAR19({VAR130, VAR61, VAR103, VAR7, VAR92, VAR154, VAR106, VAR60}),
.VAR64(VAR46 & VAR113[2]),
.VAR26(dout),
.rd(VAR62),
.VAR94(8'hff));
wire [2:0] VAR15;
wire VAR137 = VAR46 & VAR113[3];
MODULE4 MODULE5 (.clk(clk), .VAR64(VAR137), .VAR50(VAR134), .VAR26(dout[0]), .rd(VAR15[0]));
MODULE4 MODULE7 (.clk(clk), .VAR64(VAR137), .VAR50(VAR58), .VAR26(dout[1]), .rd(VAR15[1]));
MODULE4 MODULE3 (.clk(clk), .VAR64(VAR137), .VAR50(VAR111), .VAR26(dout[2]), .rd(VAR15[2]));
wire [1:0] VAR159, VAR41;
assign VAR159 = {VAR41[0:0], ~VAR41[1]};
VAR68 #(
.VAR66(16'd2)
) VAR166 [1:0] (
.VAR131(VAR41),
.VAR157(VAR159),
.VAR150(1'b0),
.VAR152(1'b0),
.VAR98(1'b0)
);
wire VAR16 = ~VAR41[1];
reg [15:0] VAR57;
reg [47:0] VAR135;
always @* begin
case (VAR33)
2'b00: VAR57 = 16'b0; 2'b01: VAR57 = {VAR135[15:1], 1'b0}; 2'b10: VAR57 = {VAR135[31:17], 1'b0};
2'b11: VAR57 = {VAR135[47:33], 1'b0};
endcase
end
assign VAR162 =
(VAR113[ 0] ? {8'd0, VAR96} : 16'd0)|
(VAR113[ 1] ? {8'd0, VAR129} : 16'd0)|
(VAR113[ 2] ? {8'd0, VAR62} : 16'd0)|
(VAR113[ 3] ? {13'd0, VAR15} : 16'd0)|
(VAR113[ 4] ? {8'd0, VAR140} : 16'd0)|
(VAR113[ 5] ? {8'd0, VAR79} : 16'd0)|
(VAR113[ 6] ? {8'd0, VAR4} : 16'd0)|
(VAR113[ 7] ? {8'd0, VAR56} : 16'd0)|
(VAR113[ 8] ? VAR135[15:0] : 16'd0)|
(VAR113[ 9] ? VAR135[31:16] : 16'd0)|
(VAR113[10] ? VAR135[47:32] : 16'd0)|
(VAR113[12] ? {8'd0, VAR28} : 16'd0)|
(VAR113[13] ? {11'd0, VAR16, 1'b0, VAR25, VAR95, !VAR63} : 16'd0)|
(VAR113[14] ? {VAR57} : 16'd0)|
(VAR113[15] ? {14'd0, VAR33} : 16'd0);
reg VAR22, VAR72, VAR51;
VAR52 VAR120 (
.VAR163(VAR22),
.VAR31(VAR72),
.VAR82(VAR51)
);
always@( posedge clk) begin
if (!VAR13)
end
VAR135 <= 0; else if (VAR46 ) begin if (VAR113[8]) VAR135[15:0] <= dout;
if (VAR113[9]) VAR135[31:16] <= dout;
if (VAR113[10]) VAR135[47:32] <= dout;
VAR3 <= VAR113[14] ? dout[3:0] : 4'b0;
end else case ({VAR165 , VAR113[14], VAR33}) 4'b1101: VAR135[15:0] <= VAR135[0] ? 16'b0 : VAR135[15:0];
4'b1110: VAR135[31:16] <= VAR135[16] ? 16'b0 : VAR135[31:16];
4'b1111: VAR135[47:32] <= VAR135[32] ? 16'b0 : VAR135[47:32];
endcase
if (VAR46 & VAR113[1])
VAR129 <= dout[7:0];
if (VAR46 & VAR113[5])
VAR79 <= dout[7:0];
if (VAR46 & VAR113[7])
VAR56 <= dout[7:0];
if (VAR46 & VAR113[11])
{VAR22, VAR51, VAR72} <= dout[2:0];
end
always @(negedge VAR13 or posedge clk)
if (!VAR13)
VAR20 <= 0; else
VAR20 <= VAR20 | VAR46;
endmodule
|
bsd-3-clause
|
olajep/oh
|
src/adi/hdl/library/axi_dmac/request_generator.v
| 7,507 |
module MODULE1 #(
parameter VAR10 = 3,
parameter VAR18 = 17)(
input clk,
input VAR4,
output [VAR10-1:0] VAR16,
input [VAR10-1:0] VAR9,
input VAR33,
input [VAR10+3-1:0] VAR15,
output VAR8,
output VAR35,
output reg VAR1 = 1'b0,
output VAR37,
output [1:0] VAR20,
input VAR36,
output reg VAR26,
input [VAR18-1:0] VAR13,
input VAR24,
input enable,
output VAR2
);
localparam VAR25 = 3'h0;
localparam VAR6 = 3'h1;
localparam VAR27 = 3'h2;
localparam VAR32 = 3'h3;
localparam VAR5 = 3'h4;
reg [2:0] state = VAR25;
reg [2:0] VAR11;
reg [1:0] VAR3 = 1'b0;
reg VAR19;
reg [VAR10-1:0] VAR14 = 'h0;
reg VAR34 = 1'b0;
reg VAR17;
wire VAR22;
reg VAR12;
reg [VAR18-1:0] VAR29 = 'h00;
reg [VAR18-1:0] VAR30 = 'h00;
reg [VAR10-1:0] VAR21;
wire [VAR10-1:0] VAR23 = VAR28(VAR21);
wire VAR31;
wire VAR7;
assign VAR2 = VAR29 == 'h00;
assign VAR16 = VAR21;
assign VAR31 = (VAR9 != VAR23) && (enable == 1'b1);
assign VAR7 = (state == VAR6) && (VAR31 == 1'b1);
always @(posedge clk) begin
if (state == VAR25) begin
VAR29 <= VAR13;
end else if (state == VAR27) begin
VAR29 <= VAR30;
end else if (VAR7 == 1'b1) begin
VAR29 <= VAR29 - 1'b1;
end
end
always @(posedge clk) begin
if (VAR26 == 1'b1 & VAR36 == 1'b1) begin
VAR17 <= VAR24;
VAR30 <= VAR13;
end
end
always @(posedge clk) begin
if (VAR4 == 1'b0) begin
VAR21 <= 'h0;
end else if (state == VAR27) begin
VAR21 <= VAR14;
end else if (VAR7 == 1'b1) begin
VAR21 <= VAR23;
end
end
always @(posedge clk) begin
if (VAR4 == 1'b0) begin
VAR26 <= 1'b0;
end else begin
VAR26 <= (VAR11 == VAR25 || VAR11 == VAR32);
end
end
assign VAR22 = VAR34 == VAR3[0];
always @(posedge clk) begin
if (VAR4 == 1'b0) begin
VAR34 <= 1'b0;
end else if (VAR36 == 1'b1 && VAR26 == 1'b1) begin
VAR34 <= ~VAR34;
end
end
always @(*) begin
VAR11 = state;
VAR12 = 0;
case (state)
VAR25: begin
if (VAR33 == 1'b1) begin
VAR11 = VAR27;
end else if (VAR36 == 1'b1) begin
VAR11 = VAR6;
end
end
VAR6: begin
if (VAR33 == 1'b1) begin
VAR11 = VAR27;
end else if (VAR2 == 1'b1 && VAR31 == 1'b1) begin
VAR11 = VAR25;
end
end
VAR27: begin
if (VAR22) begin
if (VAR19) begin
VAR11 = VAR25;
end else begin
VAR11 = VAR32;
end
end else begin
if (VAR19) begin
VAR11 = VAR6;
end else if (VAR17) begin
VAR11 = VAR25;
VAR12 = 1;
end else begin
VAR11 = VAR32;
VAR12 = 1;
end
end
end
VAR32: begin
if (VAR36) begin
VAR12 = 1;
VAR11 = VAR5;
end
end
VAR5:begin
if (VAR17) begin
VAR11 = VAR25;
end else begin
VAR11 = VAR32;
end
end
default: begin
VAR11 = VAR25;
end
endcase
end
always @(posedge clk) begin
if (VAR4 == 1'b0) begin
state <= VAR25;
end else begin
state <= VAR11;
end
end
always @(posedge clk) begin
if (VAR33 == 1'b1) begin
{VAR3, VAR19, VAR14} <= VAR15;
end
end
always @(posedge clk) begin
if (VAR4 == 1'b0) begin
VAR1 <= 1'b0;
end else begin
VAR1 <= VAR12;
end
end
assign VAR37 = VAR17;
assign VAR20 = VAR3;
assign VAR8 = (state == VAR27);
assign VAR35 = (state == VAR27) && !VAR19 && !VAR17;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a311o/sky130_fd_sc_ms__a311o.functional.pp.v
| 2,064 |
module MODULE1 (
VAR2 ,
VAR10 ,
VAR15 ,
VAR13 ,
VAR11 ,
VAR8 ,
VAR7,
VAR14,
VAR4 ,
VAR17
);
output VAR2 ;
input VAR10 ;
input VAR15 ;
input VAR13 ;
input VAR11 ;
input VAR8 ;
input VAR7;
input VAR14;
input VAR4 ;
input VAR17 ;
wire VAR16 ;
wire VAR9 ;
wire VAR1;
and VAR18 (VAR16 , VAR13, VAR10, VAR15 );
or VAR6 (VAR9 , VAR16, VAR8, VAR11 );
VAR3 VAR5 (VAR1, VAR9, VAR7, VAR14);
buf VAR12 (VAR2 , VAR1 );
endmodule
|
apache-2.0
|
walkthetalk/fsref
|
ip/axis_window/src/axis_window.v
| 3,658 |
module MODULE1 #
(
parameter integer VAR34 = 8,
parameter integer VAR29 = 12,
parameter integer VAR26 = 12
)
(
input wire clk,
input wire VAR16,
input wire [VAR29-1 : 0] VAR15,
input wire [VAR26-1 : 0] VAR36,
input wire [VAR29-1 : 0] VAR39,
input wire [VAR26-1 : 0] VAR11,
input wire VAR19,
input wire [VAR34-1:0] VAR13,
input wire VAR44,
input wire VAR42,
output wire VAR8,
output wire VAR6,
output wire [VAR34-1:0] VAR46,
output wire VAR2,
output wire VAR37,
input wire VAR12
);
reg VAR18;
reg VAR32;
reg VAR7;
reg [VAR34-1:0] VAR24;
reg VAR17;
reg VAR21;
wire VAR31;
wire VAR23;
assign VAR23 = VAR21 && VAR31;
assign VAR8 = (VAR7 && ~VAR17) && (~VAR21 || VAR31);
wire VAR33;
assign VAR33 = VAR6 && VAR12;
wire VAR3;
assign VAR3 = VAR19 && VAR8;
always @(posedge clk) begin
if (VAR16 == 1'b0)
VAR18 <= 0;
end
else if (~VAR7 && ~VAR18 && VAR19)
VAR18 <= 1;
else
VAR18 <= 0;
end
always @(posedge clk) begin
if (VAR16 == 1'b0)
VAR32 <= 0;
end
else
VAR32 <= VAR18;
end
always @(posedge clk) begin
if (VAR16 == 1'b0)
VAR7 <= 0;
end
else if (VAR18)
VAR7 <= 1;
else if (VAR23 && VAR17)
VAR7 <= 0;
else
VAR7 <= VAR7;
end
always @(posedge clk) begin
if (VAR16 == 1'b0 || VAR18) begin
VAR24 <= 0;
VAR17 <= 0;
end
else if (VAR3) begin
VAR24 <= VAR13;
VAR17 <= VAR42;
end
end
reg [VAR29-1 : 0] VAR30;
reg [VAR26-1 : 0] VAR14;
reg [VAR29-1 : 0] VAR40;
reg [VAR26-1 : 0] VAR38;
wire VAR4;
assign VAR4 = VAR3;
wire VAR5;
assign VAR5 = VAR32;
wire VAR1;
assign VAR1 = VAR18 && VAR44;
wire VAR43;
assign VAR43 = VAR18;
always @ (posedge clk) begin
if (VAR16 == 1'b0 || VAR43) begin
VAR30 <= 0;
VAR40 <= 1;
end
else if (VAR4) begin
VAR30 <= VAR40;
VAR40 <= VAR40 + 1;
end
else begin
VAR30 <= VAR30;
VAR40 <= VAR40;
end
end
always @ (posedge clk) begin
if (VAR16 == 1'b0 || VAR1) begin
VAR14 <= 0;
VAR38 <= 1;
end
else if (VAR5) begin
VAR14 <= VAR38;
VAR38 <= VAR38 + 1;
end
else begin
VAR14 <= VAR14;
VAR38 <= VAR38;
end
end
wire VAR41;
VAR27 # (
.VAR34(VAR34),
.VAR29(VAR29),
.VAR26(VAR26)
) VAR22 (
.clk(clk),
.VAR16(VAR16),
.VAR1(VAR1),
.VAR43(VAR43),
.VAR30(VAR30),
.VAR9(VAR40),
.VAR4(VAR4),
.VAR14(VAR14),
.VAR5(VAR5),
.VAR35(VAR15),
.VAR25(VAR36),
.VAR45(VAR39),
.VAR10(VAR11),
.VAR41(VAR41),
.VAR28(VAR2),
.VAR20(VAR37)
);
always @ (posedge clk) begin
if (VAR16 == 1'b0)
VAR21 <= 0;
end
else if (VAR3)
VAR21 <= 1;
else if (VAR33)
VAR21 <= 0;
else
VAR21 <= VAR21;
end
assign VAR31 = ~VAR41 || VAR12;
assign VAR6 = VAR41 && VAR21;
assign VAR46 = VAR24;
endmodule
|
gpl-3.0
|
seyedmaysamlavasani/GorillaPP
|
apps/multiProtocolNpu/build/synthesis/asic/FreePDK45/osu_soc/ref_design/Synthesis/cla16.v
| 2,632 |
module MODULE2(sum, VAR24, VAR12);
output [16:0] sum;
input [15:0] VAR24,VAR12;
wire [14:0] VAR29;
wire [15:0] VAR22, VAR14;
wire [4:0] VAR32, VAR34;
VAR5 VAR26(sum[0], VAR22[0], VAR14[0], VAR24[0], VAR12[0], 1'b0);
VAR5 VAR17(sum[1], VAR22[1], VAR14[1], VAR24[1], VAR12[1], VAR29[0]);
VAR5 VAR25(sum[2], VAR22[2], VAR14[2], VAR24[2], VAR12[2], VAR29[1]);
VAR5 VAR27(sum[3], VAR22[3], VAR14[3], VAR24[3], VAR12[3], VAR29[2]);
MODULE1 MODULE4(VAR29[2:0], VAR32[0], VAR34[0], VAR22[3:0], VAR14[3:0], 1'b0);
VAR5 VAR15(sum[4], VAR22[4], VAR14[4], VAR24[4], VAR12[4], VAR29[3]);
VAR5 VAR16(sum[5], VAR22[5], VAR14[5], VAR24[5], VAR12[5], VAR29[4]);
VAR5 VAR49(sum[6], VAR22[6], VAR14[6], VAR24[6], VAR12[6], VAR29[5]);
VAR5 VAR23(sum[7], VAR22[7], VAR14[7], VAR24[7], VAR12[7], VAR29[6]);
MODULE1 MODULE3(VAR29[6:4], VAR32[1], VAR34[1], VAR22[7:4], VAR14[7:4], VAR29[3]);
VAR5 VAR18(sum[8], VAR22[8], VAR14[8], VAR24[8], VAR12[8], VAR29[7]);
VAR5 VAR21(sum[9], VAR22[9], VAR14[9], VAR24[9], VAR12[9], VAR29[8]);
VAR5 VAR11(sum[10], VAR22[10], VAR14[10], VAR24[10], VAR12[10], VAR29[9]);
VAR5 VAR36(sum[11], VAR22[11], VAR14[11], VAR24[11], VAR12[11], VAR29[10]);
MODULE1 MODULE5(VAR29[10:8], VAR32[2], VAR34[2], VAR22[11:8], VAR14[11:8], VAR29[7]);
VAR5 VAR39(sum[12], VAR22[12], VAR14[12], VAR24[12], VAR12[12], VAR29[11]);
VAR5 VAR43(sum[13], VAR22[13], VAR14[13], VAR24[13], VAR12[13], VAR29[12]);
VAR5 VAR48(sum[14], VAR22[14], VAR14[14], VAR24[14], VAR12[14], VAR29[13]);
VAR5 VAR28(sum[15], VAR22[15], VAR14[15], VAR24[15], VAR12[15], VAR29[14]);
MODULE1 MODULE2(VAR29[14:12], VAR32[3], VAR34[3], VAR22[15:12], VAR14[15:12], VAR29[11]);
MODULE1 MODULE1({VAR29[11], VAR29[7], VAR29[3]}, VAR32[4], VAR34[4], {VAR32[3], VAR32[2], VAR32[1], VAR32[0]}, {VAR34[3], VAR34[2], VAR34[1], VAR34[0]}, 1'b0);
assign sum[16] = VAR32[4];
endmodule
module MODULE1 (VAR31, VAR32, VAR34, VAR22, VAR14, VAR7);
output [2:0] VAR31;
output VAR32;
output VAR34;
input [3:0] VAR22;
input [3:0] VAR14;
input VAR7;
wire VAR35, VAR41, VAR8, VAR40, VAR6, VAR42;
wire VAR33, VAR37, VAR20;
and VAR9(VAR35, VAR14[0], VAR7);
or o1(VAR31[0], VAR22[0], VAR35);
and VAR13(VAR41, VAR14[1], VAR22[0]);
and VAR50(VAR8, VAR14[1], VAR14[0], VAR7);
or o2(VAR31[1], VAR22[1], VAR41, VAR8);
and VAR4(VAR40, VAR14[2], VAR22[1]);
and VAR2(VAR6, VAR14[2], VAR14[1], VAR22[0]);
and VAR45(VAR42, VAR14[2], VAR14[1], VAR14[0], VAR7);
or o3(VAR31[2], VAR22[2], VAR40, VAR6, VAR42);
and VAR38(VAR33, VAR14[3], VAR22[2]);
and VAR46(VAR37, VAR14[3], VAR14[2], VAR22[1]);
and VAR10(VAR20, VAR14[3], VAR14[2], VAR14[1], VAR22[0]);
or o4(VAR32, VAR22[3], VAR33, VAR37, VAR20);
and VAR44(VAR34, VAR14[0], VAR14[1], VAR14[2], VAR14[3]);
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/or4/sky130_fd_sc_hd__or4.behavioral.v
| 1,382 |
module MODULE1 (
VAR6,
VAR12,
VAR4,
VAR9,
VAR2
);
output VAR6;
input VAR12;
input VAR4;
input VAR9;
input VAR2;
supply1 VAR10;
supply0 VAR11;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR1;
or VAR3 (VAR1, VAR2, VAR9, VAR4, VAR12 );
buf VAR5 (VAR6 , VAR1 );
endmodule
|
apache-2.0
|
monotone-RK/FACE
|
IEICE-Trans/16-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_poc_meta.v
| 11,937 |
module MODULE1 #
(parameter VAR9 = 0,
parameter VAR73 = 100,
parameter VAR33 = 7,
parameter VAR3 = 112)
(
VAR60, VAR39, VAR10,
rst, clk, VAR71, VAR8, VAR24, VAR66,
VAR28, VAR57, VAR43,
VAR64, VAR14, VAR16, VAR2,
VAR37, VAR52, VAR59
);
localparam VAR36 = VAR3/4;
function [VAR33-1:0] VAR45 (input [VAR33-1:0] VAR1,
input [1:0] VAR75,
input integer VAR31);
integer VAR48;
begin
VAR48 = (VAR1 + VAR75 * VAR36) < VAR31
? (VAR1 + VAR75 * VAR36)
: (VAR1 + VAR75 * VAR36 - VAR31);
VAR45 = VAR48[VAR33-1:0];
end
endfunction
function [VAR33-1:0] VAR42 (input [VAR33-1:0] VAR1,
input [VAR33-1:0] VAR75,
input integer VAR31);
begin
VAR42 = (VAR1>=VAR75) ? VAR1-VAR75 : VAR1+VAR31-VAR75;
end
endfunction
function [VAR33:0] VAR67 (input [VAR33-1:0] VAR34,
input [VAR33-1:0] VAR30,
input integer VAR31);
integer VAR54;
begin
VAR54 = ({VAR34, 1'b0} + VAR30 < VAR31 * 2)
? {VAR34, 1'b0} + VAR30 + 32'h0
: {VAR34, 1'b0} + VAR30 - VAR31 * 2;
VAR67 = VAR54[VAR33:0];
end
endfunction
input rst;
input clk;
input VAR71;
wire VAR19 = rst || ~VAR71;
input [VAR33-1:0] VAR8;
input VAR66;
reg VAR32, VAR74, VAR25, VAR5;
input VAR24;
reg VAR55, VAR69;
always @ begin
VAR12 = VAR58;
if (VAR19) VAR12 = 2'b0;
end
else case (VAR58)
2'b00 : VAR12 = VAR58 + {1'b0, VAR5 && VAR69};
2'b01, 2'b10 : VAR12 = VAR58 + {1'b0, VAR5};
endcase end
reg VAR26;
wire VAR18 = VAR71 && &VAR58;
output VAR60;
assign VAR60 = VAR26;
input [VAR33-1:0] VAR28;
input [VAR33-1:0] VAR57;
input [VAR33-1:0] VAR43;
input [VAR33-1:0] VAR64;
input [VAR33-1:0] VAR14;
input [VAR33-1:0] VAR16;
input [1:0] VAR2;
wire [1:0] VAR50 = VAR9 == 1 ? VAR2 : 2'b00 - VAR2;
wire [VAR33-1:0] VAR44 = VAR45(VAR43, VAR50, VAR3);
wire [VAR33-1:0] VAR40 = VAR45(VAR64, VAR50, VAR3);
reg [VAR33-1:0] VAR47, VAR13;
wire [VAR33-1:0] VAR6 = VAR42(VAR13, VAR47, VAR3);
reg [VAR33-1:0] VAR61;
wire [VAR33:0] VAR41 = VAR67(VAR47, VAR61, VAR3);
reg [VAR33:0] VAR72;
input VAR37;
wire [VAR33-1:0] VAR34 = VAR37 ? VAR16 : VAR57;
wire [VAR33-1:0] VAR7 = VAR37 ? VAR14 : VAR28;
wire [VAR33-1:0] VAR46 = VAR42(VAR7, VAR34, VAR3);
reg [VAR33-1:0] VAR70;
wire [VAR33:0] VAR23 = VAR67(VAR34, VAR70, VAR3);
reg [VAR33:0] VAR63;
localparam VAR20 = VAR3 * 2;
wire [VAR33+1:0] VAR62 = {1'b0, VAR9 == 1 ? VAR63 : VAR72};
wire [VAR33+1:0] VAR35 = {1'b0, VAR9 == 1 ? VAR72 : VAR63};
wire [VAR33+1:0] VAR17 = VAR35 >= VAR62
? VAR35 - VAR62
: VAR35 + VAR20[VAR33+1:0] - VAR62;
reg [VAR33+1:0] VAR65;
wire [VAR33+1:0] VAR76 = VAR65 > VAR20[VAR33+1:0]/2
? VAR20[VAR33+1:0] - VAR65
: VAR65;
reg [VAR33+1:0] VAR51, VAR4;
always @ VAR22 = VAR11 && ((VAR26 && VAR18) ? VAR38 : VAR27);
reg VAR53;
reg VAR49, VAR21;
always @(*) VAR49 = (~rst && ~VAR52 && ~VAR59 && ~VAR53) && VAR21 | VAR18;
wire VAR29 = ~rst && VAR11 && VAR18;
wire VAR68 = VAR29 && (~|VAR65 || ~VAR38 & VAR27);
reg VAR56;
wire VAR15 = VAR68 && VAR76 > VAR4;
output VAR39;
assign VAR39 = VAR56;
output VAR10;
assign VAR10 = VAR53;
endmodule
|
mit
|
cr88192/bgbtech_bjx1core
|
bjx1core32/GpReg.v
| 6,054 |
parameter[5:0] VAR4 = 6'h00;
parameter[5:0] VAR48 = 6'h0F;
parameter[5:0] VAR2 = 6'h20;
parameter[5:0] VAR25 = 6'h2F;
parameter[5:0] VAR1 = 6'h30;
parameter[5:0] VAR52 = 6'h3F;
parameter[6:0] VAR29 = 7'h00;
parameter[6:0] VAR34 = 7'h0F;
parameter[6:0] VAR23 = 7'h20;
parameter[6:0] VAR12 = 7'h2F;
parameter[6:0] VAR5 = 7'h30;
parameter[6:0] VAR7 = 7'h3F;
parameter[6:0] VAR37 = 7'h10;
parameter[6:0] VAR38 = 7'h10;
parameter[6:0] VAR33 = 7'h11;
parameter[6:0] VAR3 = 7'h12;
parameter[6:0] VAR49 = 7'h13;
parameter[6:0] VAR30 = 7'h15;
parameter[6:0] VAR42 = 7'h16;
parameter[6:0] VAR41 = 7'h1F;
parameter[6:0] VAR6 = 7'h50;
parameter[6:0] VAR9 = 7'h50;
parameter[6:0] VAR43 = 7'h51;
parameter[6:0] VAR11 = 7'h52;
parameter[6:0] VAR10 = 7'h53;
parameter[6:0] VAR40 = 7'h54;
parameter[6:0] VAR35 = 7'h57;
parameter[6:0] VAR50 = 7'h5C;
parameter[6:0] VAR45 = 7'h5D;
parameter[6:0] VAR26 = 7'h5E;
parameter[6:0] VAR31 = 7'h5F;
module MODULE1(
clk,
VAR24,
VAR17,
VAR32,
VAR13,
VAR18,
VAR21,
VAR47,
VAR8,
VAR39,
VAR20
);
input clk;
input VAR24; input VAR17; input[6:0] VAR32;
input[63:0] VAR13;
input[6:0] VAR18;
input[6:0] VAR47;
input[6:0] VAR39;
output[63:0] VAR21;
output[63:0] VAR8;
output[63:0] VAR20;
reg[31:0] VAR44[64]; reg[31:0] VAR28[64];
reg[31:0] VAR51[16]; reg[31:0] VAR16[16];
reg[31:0] VAR46; reg[31:0] VAR15; reg[31:0] VAR19;
reg[5:0] VAR14;
reg[5:0] VAR36;
reg[5:0] VAR22;
reg[5:0] VAR27;
always @ (clk) begin
VAR14 = VAR32[5:0];
VAR36 = VAR18[5:0];
VAR22 = VAR47[5:0];
VAR27 = VAR39[5:0];
if(VAR18[5:4]!=2'b01)
begin
if(VAR18[6])
begin
VAR21[31: 0] = VAR28[VAR36];
VAR21[63:32] = 32'h00000000 ;
end
else
begin
VAR21[31: 0] = VAR44[VAR36];
VAR21[63:32] = VAR28[VAR36];
end
end
else
begin
if(VAR18[6])
begin
VAR21[31: 0] = VAR51[VAR36[3:0]];
VAR21[63:32] = VAR16[VAR36[3:0]];
end
else
begin
VAR21[31: 0] = VAR44[VAR36];
VAR21[63:32] = VAR28[VAR36];
end
end
if(VAR47[5:4]!=2'b01)
begin
if(VAR47[6])
begin
VAR8[31: 0] = VAR28[VAR22];
VAR8[63:32] = 32'h00000000 ;
end
else
begin
VAR8[31: 0] = VAR44[VAR22];
VAR8[63:32] = VAR28[VAR22];
end
end
else
begin
if(VAR47[6])
begin
VAR8[31: 0] = VAR51[VAR22[3:0]];
VAR8[63:32] = VAR16[VAR22[3:0]];
end
else
begin
VAR8[31: 0] = VAR44[VAR22];
VAR8[63:32] = VAR28[VAR22];
end
end
if(VAR39[5:4]!=2'b01)
begin
if(VAR39[6])
begin
VAR20[31: 0] = VAR28[VAR27];
VAR20[63:32] = 32'h00000000 ;
end
else
begin
VAR20[31: 0] = VAR44[VAR27];
VAR20[63:32] = VAR28[VAR27];
end
end
else
begin
if(VAR39[6])
begin
VAR20[31: 0] = VAR51[VAR27[3:0]];
VAR20[63:32] = VAR16[VAR27[3:0]];
end
else
begin
VAR20[31: 0] = VAR44[VAR27];
VAR20[63:32] = VAR28[VAR27];
end
end
end
always @ (posedge clk) begin
if(VAR24==1'b1)
begin
if(VAR32[5:4]!=2'b01)
begin
if(VAR17==1'b1)
begin
VAR44[VAR14] <= VAR13[31:0];
VAR28[VAR14] <= VAR13[63:32];
end
else
begin
if(VAR32[6])
VAR28[VAR14] <= VAR13[31:0];
end
else
VAR44[VAR14] <= VAR13[31:0];
end
end
else
begin
if(VAR32[6])
begin
VAR51[VAR14[3:0]] <= VAR13[31:0];
if(VAR17==1'b1)
VAR16[VAR14[3:0]] <= VAR13[63:32];
end
else
begin
VAR44[VAR14] <= VAR13[31:0];
if(VAR17==1'b1)
VAR28[VAR14] <= VAR13[63:32];
end
end
end
end
endmodule
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_clk_wiz_0_0/zynq_1_clk_wiz_0_0.v
| 3,862 |
module MODULE1
(
input VAR4,
output VAR1
);
VAR3 VAR2
(
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
|
mit
|
masson2013/heterogeneous_hthreads
|
src/hardware/XilinxProcessorIP/pcores/opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2_reg.v
| 14,028 |
module MODULE1(
VAR46, VAR61,
VAR28, VAR42, VAR29, VAR58, VAR73, VAR51, VAR17, VAR14, VAR43, VAR16, VAR30,
VAR48, VAR62, VAR40, VAR8, VAR12, VAR66, VAR32, VAR45, VAR49, VAR13,
VAR50, VAR55
);
input VAR46; input VAR61;
input [0:7] VAR28; input [0:7] VAR42; input VAR29; input VAR58; output [0:7] VAR73; output VAR51; output VAR17; output VAR14; output VAR43; output VAR16; output VAR30;
output VAR48;
output VAR62; input VAR40; input VAR8; input VAR12; output VAR66; input VAR32; input VAR45; input VAR49;
input VAR13;
output [0:7] VAR50; input [0:7] VAR55;
wire VAR76;
wire VAR63;
wire VAR37;
wire VAR6;
wire VAR19;
wire VAR60 ;
wire VAR72 ;
wire VAR69 ;
wire VAR22;
wire VAR1;
wire VAR20;
wire VAR53;
wire VAR54;
wire VAR31;
wire VAR44;
reg VAR33;
reg VAR59;
reg VAR17;
reg VAR16;
reg VAR64;
reg [0:7] VAR11;
reg [0:7] VAR74;
wire VAR62;
wire VAR7;
wire VAR25;
wire VAR68;
wire VAR77;
wire VAR15;
wire VAR41;
wire VAR18;
wire VAR75;
wire VAR35;
wire VAR57;
wire VAR4;
wire VAR71;
assign VAR76 = VAR28[0]; assign VAR63 = VAR28[1]; assign VAR6 = VAR28[2]; assign VAR37 = VAR28[3]; assign VAR19 = VAR28[4]; assign VAR60 = VAR28[5]; assign VAR72 = VAR28[6]; assign VAR69 = VAR28[7];
assign VAR22 = VAR42[7];
assign VAR1 = VAR42[7];
assign VAR20 = VAR42[6];
assign VAR53 = VAR42[5];
assign VAR54 = VAR42[4];
assign VAR31 = VAR42[3];
assign VAR44 = VAR42[2];
assign VAR73 = (VAR76) ? {7'h0, VAR64} :
(VAR63) ? {6'h0, VAR66, VAR62} :
(VAR6) ? VAR74:
(VAR37) ? VAR11:
(VAR19 | VAR60) ? {2'h0,VAR7, VAR25,
VAR68, VAR77,
VAR15, VAR41}:
(VAR72 |VAR69) ? {2'h0,VAR18, VAR75,
VAR35, VAR57,
VAR4,VAR71}:
8'h00;
always @ (posedge VAR46)
begin
if (VAR61) begin VAR33 <= 0;
VAR59 <= 0;
end
else begin VAR33 <= VAR29;
VAR59 <= VAR58;
end
end
always @ (posedge VAR46)
begin
if (VAR61) begin VAR17 <= 0;
VAR16 <= 0;
end
else begin VAR17 <= (VAR29 & (~ VAR33) );
VAR16 <= (VAR58 & (~ VAR59) );
end
end
assign VAR51 = 1'b0;
assign VAR14 = 1'b0;
assign VAR43 = 1'b0;
always @ (posedge VAR46)
begin
if (VAR61) VAR64 <= 0;
end
else if (VAR76 && VAR58) VAR64 <= VAR22;
end
assign VAR48 = VAR64 || VAR61;
always @ (posedge VAR46)
begin
if (VAR61) VAR11 <= 0;
end
else if (VAR37 && VAR58) VAR11 <= VAR42;
end
assign VAR50 = VAR11;
VAR36 VAR10 (
.VAR39 (VAR46),
.VAR9 (VAR48 || VAR32),
.VAR47 (VAR37 && VAR58),
.VAR23 (1'b1),
.VAR56 (VAR66)
);
always @ (posedge VAR46)
begin
if (VAR61) VAR74 <= 0;
end
else if (VAR40) VAR74 <= VAR55;
else if (VAR6 && VAR58) VAR74 <= VAR42;
end
VAR36 VAR52 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR6 && VAR29)),
.VAR47 (VAR40),
.VAR23 (1'b1),
.VAR56 (VAR62)
);
VAR36 VAR27 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR60 && VAR58 && VAR44)),
.VAR47 (VAR40||(VAR19 && VAR58 && VAR44)),
.VAR23 (1'b1),
.VAR56 (VAR7)
);
VAR36 VAR3 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR60 && VAR58 && VAR31)),
.VAR47 (VAR8||(VAR19 && VAR58 && VAR31)),
.VAR23 (1'b1),
.VAR56 (VAR25)
);
VAR36 VAR65 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR60 && VAR58 && VAR54)),
.VAR47 (VAR12||(VAR19 && VAR58 && VAR54)),
.VAR23 (1'b1),
.VAR56 (VAR68)
);
VAR36 VAR67 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR60 && VAR58 && VAR53)),
.VAR47 (VAR45||(VAR19 && VAR58 && VAR53)),
.VAR23 (1'b1),
.VAR56 (VAR77)
);
VAR36 VAR2 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR60 && VAR58 && VAR20)),
.VAR47 (VAR49||(VAR19 && VAR58 && VAR20)),
.VAR23 (1'b1),
.VAR56 (VAR15)
);
VAR36 VAR34 (
.VAR39 (VAR46),
.VAR9 (VAR48 || (VAR60 && VAR58 && VAR1)),
.VAR47 (VAR13||(VAR19 && VAR58 && VAR1)),
.VAR23 (1'b1),
.VAR56 (VAR41)
);
VAR36 VAR21 (
.VAR39 (VAR46),
.VAR9 (VAR61 || (VAR69 && VAR58 && VAR44)),
.VAR47 (VAR72 && VAR58 && VAR44),
.VAR23 (1'b1),
.VAR56 (VAR18)
);
VAR36 VAR38 (
.VAR39 (VAR46),
.VAR9 (VAR61 || (VAR69 && VAR58 && VAR31)),
.VAR47 (VAR72 && VAR58 && VAR31),
.VAR23 (1'b1),
.VAR56 (VAR75)
);
VAR36 VAR5 (
.VAR39 (VAR46),
.VAR9 (VAR61 || (VAR69 && VAR58 && VAR54)),
.VAR47 (VAR72 && VAR58 && VAR54),
.VAR23 (1'b1),
.VAR56 (VAR35)
);
VAR36 VAR26 (
.VAR39 (VAR46),
.VAR9 (VAR61 || (VAR69 && VAR58 && VAR53)),
.VAR47 (VAR72 && VAR58 && VAR53),
.VAR23 (1'b1),
.VAR56 (VAR57)
);
VAR36 VAR70 (
.VAR39 (VAR46),
.VAR9 (VAR61 || (VAR69 && VAR58 && VAR20)),
.VAR47 (VAR72 && VAR58 && VAR20),
.VAR23 (1'b1),
.VAR56 (VAR4)
);
VAR36 VAR24 (
.VAR39 (VAR46),
.VAR9 (VAR61 || (VAR69 && VAR58 && VAR1)),
.VAR47 (VAR72 && VAR58 && VAR1),
.VAR23 (1'b1),
.VAR56 (VAR71)
);
assign VAR30 =
(VAR7 & VAR18 ) |
(VAR25 & VAR75 ) |
(VAR68 & VAR35 ) |
(VAR77 & VAR57 ) |
(VAR15 & VAR4 ) |
(VAR41 & VAR71 );
endmodule
|
bsd-3-clause
|
kristianpaul/milkyminer
|
boards/milkymist-one/rtl/system.v
| 5,363 |
module MODULE1(
input VAR32,
input VAR34,
output VAR47,
output VAR1,
output VAR59
);
parameter VAR38 = VAR48;
parameter VAR38 = 5;
localparam [5:0] VAR52 = (6'd1 << VAR38);
localparam [31:0] VAR35 = (32'd1 << (7 - VAR38)) + 32'd1;
reg [255:0] state = 0;
reg [511:0] VAR57 = 0;
reg [31:0] VAR20 = 32'h00000000;
wire VAR39;
wire VAR25;
VAR56 #(
.VAR22(2.0),
.VAR54(5), .VAR18(8),
.VAR66("VAR7"),
.VAR6(20.0),
.VAR55("VAR4"),
.VAR71("VAR4"),
.VAR43("VAR50"),
.VAR11("VAR73"),
.VAR36(0),
.VAR44("VAR73")
) VAR29 (
.VAR70(),
.VAR78(),
.VAR24(),
.VAR69(),
.VAR5(),
.VAR76(),
.VAR79(),
.VAR31(VAR25),
.VAR58(),
.VAR46(),
.VAR28(),
.VAR40(VAR32),
.VAR51(1'b0),
.VAR15(1'b0)
);
VAR49 b1(
.VAR13(VAR25),
.VAR45(VAR39)
);
wire [255:0] VAR27, VAR2;
reg [5:0] VAR12 = 6'd0;
reg VAR30 = 1'b0;
VAR72 #(.VAR52(VAR52)) VAR42 (
.clk(VAR39),
.VAR30(VAR30),
.VAR12(VAR12),
.VAR10(state),
.VAR61(VAR57),
.VAR68(VAR27)
);
VAR72 #(.VAR52(VAR52)) VAR63 (
.clk(VAR39),
.VAR30(VAR30),
.VAR12(VAR12),
.VAR10(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.VAR61({256'h0000010000000000000000000000000000000000000000000000000080000000, VAR27}),
.VAR68(VAR2)
);
reg [255:0] VAR21 = 0, VAR16 = 0;
wire [255:0] VAR23, VAR17;
VAR74 VAR65 (.clk(VAR39), .VAR62(VAR34), .VAR8(VAR23), .VAR75(VAR17));
reg [31:0] VAR14 = 0;
reg VAR3;
wire VAR67;
VAR37 VAR77 (.clk(VAR39), .VAR53(VAR47), .VAR26(VAR3), .VAR60(VAR67), .word(VAR14));
reg VAR9 = 1'b0;
reg VAR33 = 1'b1;
wire [5:0] VAR19;
wire [31:0] VAR41;
wire VAR64;
wire reset;
assign reset = 1'b0;
assign VAR19 = reset ? 6'd0 : (VAR52 == 1) ? 6'd0 : (VAR12 + 6'd1) & (VAR52-1);
assign VAR64 = (VAR52 == 1) ? 1'b0 : (VAR19 != {(VAR38){1'b0}});
assign VAR41 =
reset ? 32'd0 :
VAR64 ? VAR20 : (VAR20 + 32'd1);
always @ (posedge VAR39)
begin
VAR21 <= VAR23;
VAR16 <= VAR17;
VAR12 <= VAR19;
VAR30 <= VAR64;
VAR33 <= VAR30;
state <= VAR21;
VAR57 <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, VAR41, VAR16[95:0]};
VAR20 <= VAR41;
VAR9 <= (VAR2[255:224] == 32'h00000000) && !VAR33;
if(VAR9)
begin
if (VAR52 == 1)
VAR14 <= VAR20 - 32'd131;
end
else if (VAR52 == 2)
VAR14 <= VAR20 - 32'd66;
end
else
VAR14 <= VAR20 - VAR35;
if (!VAR67) VAR3 <= 1;
end else
VAR3 <= 0;
end
assign VAR1 = |VAR14;
assign VAR59 = ~VAR47;
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/mux2/sky130_fd_sc_hs__mux2.blackbox.v
| 1,233 |
module MODULE1 (
VAR2 ,
VAR6,
VAR3,
VAR5
);
output VAR2 ;
input VAR6;
input VAR3;
input VAR5 ;
supply1 VAR4;
supply0 VAR1;
endmodule
|
apache-2.0
|
devinacker/sd2snes
|
verilog/sd2snes/msu.v
| 5,243 |
module MODULE1(
input VAR30,
input enable,
input [13:0] VAR14,
input [7:0] VAR28,
input VAR12,
input [2:0] VAR44,
input [7:0] VAR19,
output [7:0] VAR5,
input VAR32,
input VAR18,
input VAR15,
output [7:0] VAR45,
output [7:0] VAR17,
output VAR39,
output [31:0] VAR23,
output [15:0] VAR13,
input [5:0] VAR7,
input [5:0] VAR20,
input VAR27,
input [13:0] VAR22,
input VAR41,
output VAR3,
output VAR42,
output VAR4,
output [13:0] VAR29,
output VAR24
);
reg [1:0] VAR31;
always @(posedge VAR30) VAR31 = {VAR31[0], VAR27};
wire VAR34 = (VAR31 == 2'b01);
reg [13:0] VAR46;
wire [13:0] VAR8 = VAR46;
VAR2 VAR46 = 13'b0;
wire [7:0] VAR16;
reg [7:0] VAR43;
reg [2:0] VAR36;
always @(posedge VAR30)
VAR36 <= {VAR36[1:0], VAR41};
wire VAR26 = (VAR36[2:1] == 2'b01);
reg [31:0] VAR33;
assign VAR23 = VAR33;
reg [15:0] VAR37;
assign VAR13 = VAR37;
reg [7:0] VAR21;
assign VAR17 = VAR21;
reg VAR25;
assign VAR39 = VAR25;
reg VAR10;
reg VAR6;
reg VAR38;
reg VAR40;
reg VAR35;
reg VAR9;
reg [2:0] VAR11;
reg [1:0] VAR1;
|
gpl-2.0
|
calee0219/Course
|
DLAB/Lab08/LCD.v
| 3,842 |
module MODULE1(
input clk,
input rst,
input [127:0] VAR6,
input [127:0] VAR2,
output VAR9,
output VAR8,
output VAR7,
output [3:0] VAR3
);
reg [23:0] VAR5 = 0;
reg VAR4;
reg [5:0] VAR1;
assign {VAR9, VAR8, VAR7, VAR3} = {VAR4, VAR1};
always@(posedge clk, posedge rst)
begin
if(rst) VAR5 <= VAR5;
end
else VAR5 <= (VAR5[23:17] < 78) ? VAR5+1 : 0;
end
always@(posedge clk, posedge rst)
begin
if(rst) VAR1 <= 6'h10;
end
else begin
case(VAR5[23:17])
0 : VAR1 <= 6'h03; 1 : VAR1 <= 6'h03;
2 : VAR1 <= 6'h03;
3 : VAR1 <= 6'h02;
4 : VAR1 <= 6'h02; 5 : VAR1 <= 6'h08;
6 : VAR1 <= 6'h00; 7 : VAR1 <= 6'h06;
8 : VAR1 <= 6'h00; 9 : VAR1 <= 6'h0C;
10: VAR1 <= 6'h00; 11: VAR1 <= 6'h01;
12: VAR1 <= {2'b10,VAR6[127:124]};
13: VAR1 <= {2'b10,VAR6[123:120]};
14: VAR1 <= {2'b10,VAR6[119:116]};
15: VAR1 <= {2'b10,VAR6[115:112]};
16: VAR1 <= {2'b10,VAR6[111:108]};
17: VAR1 <= {2'b10,VAR6[107:104]};
18: VAR1 <= {2'b10,VAR6[103:100]};
19: VAR1 <= {2'b10,VAR6[99 :96 ]};
20: VAR1 <= {2'b10,VAR6[95 :92 ]};
21: VAR1 <= {2'b10,VAR6[91 :88 ]};
22: VAR1 <= {2'b10,VAR6[87 :84 ]};
23: VAR1 <= {2'b10,VAR6[83 :80 ]};
24: VAR1 <= {2'b10,VAR6[79 :76 ]};
25: VAR1 <= {2'b10,VAR6[75 :72 ]};
26: VAR1 <= {2'b10,VAR6[71 :68 ]};
27: VAR1 <= {2'b10,VAR6[67 :64 ]};
28: VAR1 <= {2'b10,VAR6[63 :60 ]};
29: VAR1 <= {2'b10,VAR6[59 :56 ]};
30: VAR1 <= {2'b10,VAR6[55 :52 ]};
31: VAR1 <= {2'b10,VAR6[51 :48 ]};
32: VAR1 <= {2'b10,VAR6[47 :44 ]};
33: VAR1 <= {2'b10,VAR6[43 :40 ]};
34: VAR1 <= {2'b10,VAR6[39 :36 ]};
35: VAR1 <= {2'b10,VAR6[35 :32 ]};
36: VAR1 <= {2'b10,VAR6[31 :28 ]};
37: VAR1 <= {2'b10,VAR6[27 :24 ]};
38: VAR1 <= {2'b10,VAR6[23 :20 ]};
39: VAR1 <= {2'b10,VAR6[19 :16 ]};
40: VAR1 <= {2'b10,VAR6[15 :12 ]};
41: VAR1 <= {2'b10,VAR6[11 :8 ]};
42: VAR1 <= {2'b10,VAR6[7 :4 ]};
43: VAR1 <= {2'b10,VAR6[3 :0 ]};
44: VAR1 <= 6'b001100;
45: VAR1 <= 6'b000000;
46: VAR1 <= {2'b10,VAR2[127:124]};
47: VAR1 <= {2'b10,VAR2[123:120]};
48: VAR1 <= {2'b10,VAR2[119:116]};
49: VAR1 <= {2'b10,VAR2[115:112]};
50: VAR1 <= {2'b10,VAR2[111:108]};
51: VAR1 <= {2'b10,VAR2[107:104]};
52: VAR1 <= {2'b10,VAR2[103:100]};
53: VAR1 <= {2'b10,VAR2[99 :96 ]};
54: VAR1 <= {2'b10,VAR2[95 :92 ]};
55: VAR1 <= {2'b10,VAR2[91 :88 ]};
56: VAR1 <= {2'b10,VAR2[87 :84 ]};
57: VAR1 <= {2'b10,VAR2[83 :80 ]};
58: VAR1 <= {2'b10,VAR2[79 :76 ]};
59: VAR1 <= {2'b10,VAR2[75 :72 ]};
60: VAR1 <= {2'b10,VAR2[71 :68 ]};
61: VAR1 <= {2'b10,VAR2[67 :64 ]};
62: VAR1 <= {2'b10,VAR2[63 :60 ]};
63: VAR1 <= {2'b10,VAR2[59 :56 ]};
64: VAR1 <= {2'b10,VAR2[55 :52 ]};
65: VAR1 <= {2'b10,VAR2[51 :48 ]};
66: VAR1 <= {2'b10,VAR2[47 :44 ]};
67: VAR1 <= {2'b10,VAR2[43 :40 ]};
68: VAR1 <= {2'b10,VAR2[39 :36 ]};
69: VAR1 <= {2'b10,VAR2[35 :32 ]};
70: VAR1 <= {2'b10,VAR2[31 :28 ]};
71: VAR1 <= {2'b10,VAR2[27 :24 ]};
72: VAR1 <= {2'b10,VAR2[23 :20 ]};
73: VAR1 <= {2'b10,VAR2[19 :16 ]};
74: VAR1 <= {2'b10,VAR2[15 :12 ]};
75: VAR1 <= {2'b10,VAR2[11 :8 ]};
76: VAR1 <= {2'b10,VAR2[7 :4 ]};
77: VAR1 <= {2'b10,VAR2[3 :0 ]};
default: VAR1 <= 6'h10;
endcase
end
end
always@(posedge clk, posedge rst)
begin
if(rst) VAR4 <= 1;
end
else VAR4 <= VAR5[16];
end
endmodule
|
mit
|
ptracton/wb_soc_template
|
behvioral/wb_master/wb_master_model.v
| 16,209 |
module MODULE1(clk, rst, VAR2, din, dout, VAR6, VAR5, sel, VAR3, ack, VAR1, VAR4);
input clk, rst;
output [31:0] VAR2;
input [31:0] din;
output [31:0] dout;
output VAR6, VAR5;
output [3:0] sel;
output VAR3;
input ack, VAR1, VAR4;
parameter VAR7 = 4096;
reg [31:0] VAR2;
reg [31:0] dout;
reg VAR6, VAR5;
reg [3:0] sel;
reg VAR3;
reg [31:0] VAR9[VAR7:0];
integer VAR8;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
mit
|
shailcoolboy/Warp-Trinity
|
PlatformSupport/CustomPeripherals/pcores/clock_board_config_v1_04_a/hdl/verilog/clock_board_config.v
| 27,610 |
module MODULE1 (
VAR43,
VAR25,
VAR55,
VAR63,
VAR37,
VAR54,
VAR30,
VAR51,
VAR36,
VAR73,
VAR26
);
parameter VAR23 = 120000000;
parameter VAR62 = 16'h1Aff;
parameter VAR4 = 16'h1Aff;
parameter VAR12 = 16'h01ff; parameter VAR18 = 16'h1eff; parameter VAR19 = 16'h1eff; parameter VAR47 = 16'h01ff;
parameter VAR3 = 16'h0BFF;
parameter VAR31 = 16'h02ff; parameter VAR49 = 16'h02ff; parameter VAR27 = 16'h08ff; parameter VAR45 = 16'h08ff;
parameter VAR68 = 16'h1FFF;
input VAR43;
input VAR25;
output VAR55; reg VAR55 = 1'b1;
output VAR63; reg VAR63 = 1'b1;
output VAR37; reg VAR37 = 1'b1;
output VAR54; reg VAR54 = 1'b1;
output VAR30; reg VAR30 = 1'b1;
output VAR51; reg VAR51 = 1'b1;
output VAR36; reg VAR36 = 1'b1;
output VAR73; reg VAR73 = 1'b1;
output VAR26;
parameter VAR59 = 2500000;
parameter VAR20 = ((VAR23 + VAR59 - 1) / VAR59);
parameter VAR28 = (VAR20 < 2) ? 2 : VAR20;
parameter VAR35 = VAR28;
reg [3:0] VAR21 = 4'b0000; reg [7:0] VAR1 = 8'b00000000; reg VAR71 = 1'b0; reg VAR38 = 1'b0; reg VAR11 = 1'b0;
always @ (posedge VAR43)
begin
VAR21 [3:0] <= {1'b1,VAR21 [3:1]};
if (~VAR21 [0])
begin
VAR1 [7:0] <= 8'b00000000;
VAR71 <= 1'b0;
VAR38 <= 1'b0;
VAR11 <= 1'b0;
end
else
begin
if (~VAR71) VAR1 [7:0] <= VAR1 [7:0] + 1;
end
else VAR1 [7:0] <= 8'b00000000;
VAR71 <= (VAR1 [7:0] == ((VAR35 + 0) - 2));
VAR38 <= (VAR1 [7:0] == 0 );
VAR11 <= (VAR1 [7:0] == ((VAR35 + 1) / 2));
end
end
reg [3:0] VAR57 = 4'b1111;
reg [2:0] VAR5 = 3'b111;
always @ (posedge VAR43 or posedge VAR25)
begin
if (VAR25) VAR57 [3] <= 1'b1;
end
else VAR57 [3] <= 1'b0;
end
always @ (posedge VAR43 or posedge VAR57 [3])
begin
if (VAR57 [3]) VAR57 [2:0] <= 3'b111;
end
else VAR57 [2:0] <= {1'b0,VAR57 [2:1]};
end
always @ (posedge VAR43)
begin
VAR5 [2:0] <= {VAR57 [0],VAR5 [2:1]};
end
reg [9:0] VAR34 = 10'b0000000000;
reg VAR22 = 1'b1;
reg VAR48 = 1'b0;
reg VAR33 = 1'b0;
reg VAR53 = 1'b0;
reg VAR46 = 1'b1;
always @ (posedge VAR43)
begin
VAR46 <= VAR22;
end
always @ (posedge VAR43)
begin
if (~VAR11)
begin
VAR34 [9:0] <= VAR34 [9:0];
VAR22 <= VAR22;
end
else
begin
if (VAR22)
begin
VAR34 [9:0] <= 10'b0000000000;
VAR22 <= ~VAR48;
end
else
begin
VAR34 [9:0] <= VAR34 [9:0] + 1;
VAR22 <= (VAR34 [9:0] == 10'b1111111111);
end
end
VAR48 <= ~VAR48 & VAR22 & (VAR5 [1:0] == 2'b01)
| VAR48 & VAR22 & ~VAR11;
VAR33 <= ~VAR22 & VAR38;
VAR53 <= ~VAR22 & VAR11;
end
wire VAR39;
wire [63:0] VAR2;
wire [63:0] VAR58;
wire [63:0] VAR15;
wire [63:0] VAR72;
assign VAR39 = VAR33;
assign VAR2 [63:0] = {VAR58 [0],VAR58 [63:1]};
assign VAR15 [63:0] = {VAR72 [0],VAR72 [63:1]};
reg VAR26 = 1'b1;
always @(posedge VAR43)
begin
if(VAR22 & ~VAR46)
VAR26 <= 1'b0;
end
else if(VAR48)
VAR26 <= 1'b1;
end
genvar VAR7;
generate
for (VAR7 = 0 ; VAR7 < 64 ; VAR7 = VAR7 + 1)
begin : VAR14
VAR17 VAR66 (
.VAR29 (VAR58 [VAR7]),
.VAR64 (1'b1 ),
.VAR76 (1'b1 ),
.VAR13 (1'b1 ),
.VAR67 (1'b1 ),
.VAR65 (VAR39 ),
.VAR24 (VAR43 ),
.VAR8 (VAR2 [VAR7])
);
VAR17 VAR41 (
.VAR29 (VAR72 [VAR7]),
.VAR64 (1'b1 ),
.VAR76 (1'b1 ),
.VAR13 (1'b1 ),
.VAR67 (1'b1 ),
.VAR65 (VAR39 ),
.VAR24 (VAR43 ),
.VAR8 (VAR15 [VAR7])
);
end
endgenerate
reg VAR78 = 1'b0;
reg VAR40 = 1'b0;
reg VAR32 = 1'b0;
reg VAR77 = 1'b0;
reg VAR70 = 1'b0;
reg VAR16 = 1'b0;
reg VAR56 = 1'b0;
reg VAR42 = 1'b0;
always @ (posedge VAR43)
begin
if (~VAR38)
begin
VAR78 <= 1'b0;
VAR40 <= 1'b0;
VAR32 <= 1'b0;
VAR77 <= 1'b0;
VAR70 <= 1'b0;
VAR16 <= 1'b0;
VAR56 <= 1'b0;
VAR42 <= 1'b0;
end
else
begin
if (VAR22)
begin
VAR78 <= 1'b0;
VAR40 <= 1'b1;
VAR32 <= 1'b0;
VAR77 <= 1'b1;
VAR70 <= 1'b0;
VAR16 <= 1'b1;
VAR56 <= 1'b0;
VAR42 <= 1'b1;
end
else
begin
VAR78 <= VAR61;
VAR40 <= VAR6;
VAR32 <= VAR44;
VAR77 <= VAR74;
VAR70 <= VAR69;
VAR16 <= VAR50;
VAR56 <= VAR10;
VAR42 <= VAR75;
end
end
end
always @ (posedge VAR43)
begin
if (VAR39) VAR55 <= VAR58 [0];
end
else VAR55 <= VAR55;
VAR63 <= VAR63 & ~VAR78
| ~VAR63 & VAR40;
VAR37 <= VAR37 & ~VAR32
| ~VAR37 & VAR77;
VAR54 <= VAR54 & ~VAR33
| ~VAR54 & VAR53;
if (VAR39) VAR30 <= VAR72 [0];
else VAR30 <= VAR30;
VAR51 <= VAR51 & ~VAR70
| ~VAR51 & VAR16;
VAR36 <= VAR36 & ~VAR56
| ~VAR36 & VAR42;
VAR73 <= VAR73 & ~VAR33
| ~VAR73 & VAR53;
end
endmodule
|
bsd-2-clause
|
rkrajnc/minimig-mist
|
rtl/minimig/agnus_bitplanedma.v
| 18,154 |
module MODULE1 (
input wire clk, input wire VAR41, input wire reset, input wire VAR67,
input wire VAR54, input wire VAR1, input wire VAR4, input wire VAR8, input wire VAR35, input wire [ 11-1:0] VAR29, input wire [ 9-1:0] VAR34, output wire VAR47, input wire [ 9-1:1] VAR2, output reg [ 9-1:1] VAR20, input wire [ 16-1:0] VAR7, output wire [ 21-1:1] VAR39 );
localparam VAR49 = 9'h08E;
localparam VAR51 = 9'h090;
localparam VAR62 = 9'h1E4;
localparam VAR19 = 9'h0E0; localparam VAR36 = 9'h092;
localparam VAR23 = 9'h094;
localparam VAR31 = 9'h108;
localparam VAR12 = 9'h10a;
localparam VAR26 = 9'h100;
localparam VAR55 = 9'h1fc;
reg [ 8: 2] VAR15; reg [ 8: 2] VAR60; wire [ 8: 2] VAR3;
wire [ 8: 2] VAR33;
reg [15: 1] VAR40; reg [15: 1] VAR52; wire [15: 1] VAR46; wire [15: 1] VAR18;
reg [ 5: 0] VAR38; reg [ 5: 0] VAR50; reg [ 5: 0] VAR6 [1:0];
reg [15: 0] VAR27;
wire VAR10; wire VAR44; wire [ 3: 0] VAR30;
reg [20: 1] VAR5; reg [20:16] VAR32 [7:0]; reg [15: 1] VAR21 [7:0]; reg [ 4: 0] VAR37;
wire VAR48;
reg VAR58; reg VAR9; reg VAR14; reg VAR16;
reg [ 4: 0] VAR64; reg VAR43; reg VAR57;
reg [ 1: 0] VAR59;
reg [10: 0] VAR65; reg [10: 0] VAR11; reg VAR24;
wire [ 2: 0] VAR25; wire [20:16] VAR45;
wire [15: 1] VAR22;
wire VAR17;
wire VAR56; wire VAR66; wire VAR13;
reg VAR42;
reg VAR53;
reg VAR28;
reg VAR61;
wire VAR63;
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR49[8:1])
VAR65[7:0] <= VAR7[15:8];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR49[8:1])
end
VAR65[10:8] <= 3'b000; else if (VAR2[8:1]==VAR62[8:1] && VAR1) VAR65[10:8] <= VAR7[2:0];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR51[8:1])
VAR11[7:0] <= VAR7[15:8];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR51[8:1])
end
VAR11[10:8] <= {2'b00,~VAR7[15]}; else if (VAR2[8:1]==VAR62[8:1] && VAR1) VAR11[10:8] <= VAR7[10:8];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR8 && ~VAR4 || VAR29[10:0]==0 && VAR4 || VAR29[10:0]==VAR11[10:0]) VAR24 <= 1'b0;
end
else if (VAR29[10:0]==VAR65[10:0])
VAR24 <= 1'b1;
end
end
assign VAR25 = VAR47 ? VAR37[2:0] : VAR2[4:2];
assign VAR45 = VAR47 ? VAR5[20:16] : VAR7[4:0];
always @ (posedge clk) begin
if (VAR41) begin
if (VAR47 || ((VAR2[8:5]==VAR19[8:5]) && !VAR2[1])) VAR32[VAR25] <= VAR45;
end
end
assign VAR39[20:16] = VAR32[VAR37[2:0]];
assign VAR22 = VAR47 ? VAR5[15:1] : VAR7[15:1];
always @ (posedge clk) begin
if (VAR41) begin
if (VAR47 || ((VAR2[8:5]==VAR19[8:5]) && VAR2[1])) VAR21[VAR25] <= VAR22;
end
end
assign VAR39[15:1] = VAR21[VAR37[2:0]];
assign VAR17 = VAR2[8:1]==VAR36[8:1] ? 1'b1 : 1'b0;
always @ (posedge clk) begin
if (VAR41) begin
if (VAR17)
VAR15[8:2] <= VAR7[7:1];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR23[8:1])
VAR60[8:2] <= VAR7[7:1];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR31[8:1])
VAR40[15:1] <= VAR7[15:1];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR2[8:1]==VAR12[8:1])
VAR52[15:1] <= VAR7[15:1];
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (reset)
VAR38 <= 6'b000000;
end
else if (VAR2[8:1]==VAR26[8:1])
VAR38 <= {VAR7[6], VAR7[15], VAR54 & VAR7[4], VAR7[14:12]}; end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0]) begin
VAR6[0] <= VAR38;
VAR6[1] <= VAR6[0];
VAR50 <= VAR6[1];
end
end
end
assign VAR44 = VAR1 & VAR50[5];
assign VAR10 = VAR50[4];
assign VAR30 = VAR54 ? VAR50[3:0] : {1'b0, &VAR50[2:0] ? 3'd4 : VAR50[2:0]};
always @ (posedge clk) begin
if (VAR41) begin
if (reset)
VAR27 <= 16'h0000;
end
else if (VAR54 && (VAR2[8:1] == VAR55[8:1]))
VAR27 <= VAR7;
end
end
assign VAR56 = (VAR27[1:0] == 2'b00);
assign VAR66 = (VAR27[1:0] == 2'b01) || (VAR27[1:0] == 2'b10);
assign VAR13 = (VAR27[1:0] == 2'b11);
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[1:0]==2'b11)
VAR59[1:0] <= {VAR59[0], VAR35};
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0])
if (VAR34[8:1]=={VAR15[8:3], VAR15[2] & VAR1, 1'b0})
VAR42 <= 1'b1;
end
else
VAR42 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0])
if (VAR34[8:1] == {VAR60[8:3], VAR60[2] & VAR1, 1'b0})
VAR53 <= 1'b1;
end
else
VAR53 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0])
if (VAR34[8:1]==8'h18)
VAR28 <= 1'b1;
end
else
VAR28 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0])
if (VAR34[8:1]==8'hD8)
VAR61 <= 1'b1;
end
else
VAR61 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0])
if (VAR42 && (VAR1 || VAR24 && VAR35) && !VAR17) VAR9 <= 1'b1;
end
else if (VAR53 || !VAR1 && VAR61)
VAR9 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0])
if (VAR28)
VAR58 <= 1'b1;
end
else if (VAR61)
VAR58 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0]) begin
VAR16 <= (VAR58 || VAR67) && VAR9;
VAR14 <= VAR16;
end
end
end
assign VAR63 = ((!VAR10 && !VAR44 && VAR13) && (VAR64[4:0] == 5'd7)) ||
(((!VAR44 && !VAR10 && VAR66) || (VAR10 && VAR13)) && (VAR64[3:0] == 4'd7)) ||
(!(!VAR10 && !VAR44 && VAR13) && !((!VAR44 && !VAR10 && VAR66) || (VAR10 && VAR13))) && (VAR64[2:0] == 3'd7);
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0]) if (VAR14 && VAR24 && !VAR34[1] && VAR59[0]) VAR43 <= 1'b1;
end
else if ((VAR57 || !VAR24) && VAR63) VAR43 <= 1'b0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0]) if (VAR43) VAR64 <= VAR64 + 5'd1;
end
else
VAR64 <= 5'd0;
end
end
always @ (posedge clk) begin
if (VAR41) begin
if (VAR34[0] && VAR63 && VAR57)
VAR57 <= 1'b0;
end
else if (VAR34[0] && (VAR64[2:0]==7) && !VAR14)
VAR57 <= 1'b1;
end
end
assign VAR48 = (VAR44 && VAR56) ? VAR57 & VAR64[2] & VAR64[1] : ((VAR10 && VAR56) || (VAR44 && VAR66)) ? VAR57 & VAR64[2] : VAR57;
always @ begin
if (VAR48) begin
if (VAR37[0]) VAR5[20:1] = VAR39[20:1] + {{5{VAR18[15]}},VAR18[15:1]} + (VAR27[1:0] == 2'b11 ? 3'd4 : VAR27[1:0] == 2'b00 ? 3'd1 : 3'd2);
end
else VAR5[20:1] = VAR39[20:1] + {{5{VAR46[15]}},VAR46[15:1]} + (VAR27[1:0] == 2'b11 ? 3'd4 : VAR27[1:0] == 2'b00 ? 3'd1 : 3'd2);
end else begin
VAR5[20:1] = VAR39[20:1] + (VAR27[1:0] == 2'b11 ? 3'd4 : VAR27[1:0] == 2'b00 ? 3'd1 : 3'd2);
end
end
always @ (*) begin
case (VAR37[2:0])
3'b000 : VAR20[8:1] = 8'h88;
3'b001 : VAR20[8:1] = 8'h89;
3'b010 : VAR20[8:1] = 8'h8A;
3'b011 : VAR20[8:1] = 8'h8B;
3'b100 : VAR20[8:1] = 8'h8C;
3'b101 : VAR20[8:1] = 8'h8D;
3'b110 : VAR20[8:1] = 8'h8E;
3'b111 : VAR20[8:1] = 8'h8F;
endcase
end
endmodule
|
gpl-3.0
|
danbone/core
|
riscv_core_fdi.v
| 1,500 |
module MODULE2 (
clk,
VAR13,
VAR24,
VAR8,
VAR34,
VAR30,
VAR12,
VAR28,
VAR32,
VAR43,
VAR20
);
reg [31:0] VAR10;
assign VAR24 = VAR10;
always @ (*) begin
if (VAR14) begin
VAR36 = VAR10;
end
else if (VAR35) begin
VAR36 = VAR23;
end
else begin
VAR36 = VAR10 + 4;
end
end
assign VAR44 = (VAR42 == VAR40) ? VAR37 : VAR22;
assign VAR23 = VAR9 + VAR44;
case (VAR29)
VAR39 :
VAR31 :
VAR38 :
VAR26 :
VAR7 :
VAR2 :
VAR19 :
default :
module MODULE1 (
input [31:0] VAR41,
input [31:0] VAR15 ,
output VAR3 ,
output VAR4 ,
output VAR27 ,
output [1:0] VAR21 ,
output [VAR16-1:0] VAR6 ,
output VAR25 ,
output VAR5 ,
output [31:0] VAR17 ,
output [31:0] VAR33 ,
output [VAR18-1:0] VAR29 ,
output VAR1 ,
output [31:0] VAR9 ,
output [31:0] VAR22 ,
output [VAR11-1:0] VAR45
);
|
mit
|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC
|
Erosion/ip/Erosion/acl_fp_asin_s5.v
| 1,184 |
module MODULE1 (
enable,
VAR3,
VAR6,
VAR9);
input enable;
input VAR3;
input [31:0] VAR6;
output [31:0] VAR9;
wire [31:0] VAR7;
wire [31:0] VAR9 = VAR7[31:0];
VAR4 VAR1 (
.en (enable),
.VAR5(1'b0),
.clk(VAR3),
.VAR2(VAR6),
.VAR8(VAR7));
endmodule
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/megafunctions/pci2net_dma_16x32_bb.v
| 5,985 |
module MODULE1 (
VAR1,
VAR6,
VAR10,
VAR2,
VAR5,
VAR7,
VAR3,
VAR4,
VAR9,
VAR8);
input VAR1;
input VAR6;
input [31:0] VAR10;
input VAR2;
input VAR5;
output VAR7;
output VAR3;
output VAR4;
output [31:0] VAR9;
output [3:0] VAR8;
endmodule
|
mit
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/prcfg/bist/prcfg_dac.v
| 7,423 |
module MODULE1(
clk,
VAR4,
VAR17,
VAR15,
VAR2,
VAR8,
VAR11,
VAR14,
VAR1,
VAR9,
VAR19
);
localparam VAR12 = 8'hA1;
parameter VAR16 = 0;
input clk;
input [31:0] VAR4;
output [31:0] VAR17;
output VAR15;
input [31:0] VAR2;
input VAR8;
input VAR11;
input VAR14;
output [31:0] VAR1;
output VAR9;
output VAR19;
reg VAR9 = 0;
reg [31:0] VAR1 = 0;
reg VAR19 = 0;
reg VAR15 = 0;
reg [31:0] VAR6 = 32'hA2F19C;
reg [31:0] VAR17 = 0;
reg [ 2:0] counter = 0;
reg VAR7 = 0;
reg [15:0] VAR5 = 0;
reg [15:0] VAR18 = 0;
reg [ 3:0] VAR3;
wire [31:0] VAR13;
function [31:0] VAR10;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[14] ^ din[13];
dout[30] = din[13] ^ din[12];
dout[29] = din[12] ^ din[11];
dout[28] = din[11] ^ din[10];
dout[27] = din[10] ^ din[9];
dout[26] = din[9] ^ din[8];
dout[25] = din[8] ^ din[7];
dout[24] = din[7] ^ din[6];
dout[23] = din[6] ^ din[5];
dout[22] = din[5] ^ din[4];
dout[21] = din[4] ^ din[3];
dout[20] = din[3] ^ din[2];
dout[19] = din[2] ^ din[1];
dout[18] = din[1] ^ din[0];
dout[17] = din[0] ^ din[14] ^ din[13];
dout[16] = din[14] ^ din[12];
dout[15] = din[13] ^ din[11];
dout[14] = din[12] ^ din[10];
dout[13] = din[11] ^ din[9];
dout[12] = din[10] ^ din[8];
dout[11] = din[9] ^ din[7];
dout[10] = din[8] ^ din[6];
dout[9] = din[7] ^ din[5];
dout[8] = din[6] ^ din[4];
dout[7] = din[5] ^ din[3];
dout[6] = din[4] ^ din[2];
dout[5] = din[3] ^ din[1];
dout[4] = din[2] ^ din[0];
dout[3] = din[1] ^ din[14] ^ din[13];
dout[2] = din[0] ^ din[13] ^ din[12];
dout[1] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[0] = din[13] ^ din[11] ^ din[12] ^ din[10];
VAR10 = dout;
end
endfunction
always @(posedge clk) begin
VAR17 <= {24'h0, VAR12};
VAR3 <= VAR4[7:4];
end
always @(posedge clk) begin
if (VAR14 == 1'h1) begin
counter <= counter + 1;
end
end
always @(counter) begin
case(counter)
3'd0 : begin
VAR5 <= 16'h0000;
VAR18 <= 16'h7FFF;
end
3'd1 : begin
VAR5 <= 16'h5A82;
VAR18 <= 16'h5A82;
end
3'd2 : begin
VAR5 <= 16'h7FFF;
VAR18 <= 16'h0000;
end
3'd3 : begin
VAR5 <= 16'h5A82;
VAR18 <= 16'hA57E;
end
3'd4 : begin
VAR5 <= 16'h0000;
VAR18 <= 16'h8001;
end
3'd5 : begin
VAR5 <= 16'hA57E;
VAR18 <= 16'hA57E;
end
3'd6 : begin
VAR5 <= 16'h8001;
VAR18 <= 16'h0000;
end
3'd7 : begin
VAR5 <= 16'hA57E;
VAR18 <= 16'h5A82;
end
endcase
end
always @(posedge clk) begin
if(VAR14 == 1'h1) begin
VAR6 <= VAR10(VAR6);
end
end
always @(posedge clk) begin
if(VAR14 == 1'h1) begin
VAR7 <= ~VAR7;
end
end
assign VAR13 = (VAR7 == 1'h1) ?
{16'h5555, 16'hAAAA, 16'h5555, 16'hAAAA} :
{16'hAAAA, 16'h5555, 16'hAAAA, 16'h5555};
always @(posedge clk) begin
VAR15 <= (VAR3 == 0) ? VAR14 : 1'b0;
VAR19 <= (VAR3 == 0) ? VAR11 : VAR14;
VAR9 <= (VAR3 == 0) ? VAR8 : 1'b0;
end
always @(posedge clk) begin
case(VAR3)
4'h0 : begin
VAR1 <= VAR2;
end
4'h1 : begin
VAR1 <= {VAR18, VAR5};
end
4'h2 : begin
VAR1 <= VAR6;
end
4'h3 : begin
VAR1 <= VAR13;
end
default : begin
VAR1 <= VAR2;
end
endcase
end
endmodule
|
gpl-3.0
|
amrmorsey/Digital-Design-Project
|
sbox5.v
| 3,542 |
module MODULE1(
VAR2,
VAR1
);
input [6:1] VAR2;
output reg [4:1] VAR1;
wire [6:1] VAR3;
assign VAR3 = {VAR2[6], VAR2[1], VAR2[5 : 2]};
always @(VAR3)
begin
case (VAR3)
6'b000000: VAR1 <= 4'd2;
6'b000001: VAR1 <= 4'd12;
6'b000010: VAR1 <= 4'd4;
6'b000011: VAR1 <= 4'd1;
6'b000100: VAR1 <= 4'd7;
6'b000101: VAR1 <= 4'd10;
6'b000110: VAR1 <= 4'd11;
6'b000111: VAR1 <= 4'd6;
6'b001000: VAR1 <= 4'd8;
6'b001001: VAR1 <= 4'd5;
6'b001010: VAR1 <= 4'd3;
6'b001011: VAR1 <= 4'd15;
6'b001100: VAR1 <= 4'd13;
6'b001101: VAR1 <= 4'd0;
6'b001110: VAR1 <= 4'd14;
6'b001111: VAR1 <= 4'd9;
6'b010000: VAR1 <= 4'd14;
6'b010001: VAR1 <= 4'd11;
6'b010010: VAR1 <= 4'd2;
6'b010011: VAR1 <= 4'd12;
6'b010100: VAR1 <= 4'd4;
6'b010101: VAR1 <= 4'd7;
6'b010110: VAR1 <= 4'd13;
6'b010111: VAR1 <= 4'd1;
6'b011000: VAR1 <= 4'd5;
6'b011001: VAR1 <= 4'd0;
6'b011010: VAR1 <= 4'd15;
6'b011011: VAR1 <= 4'd10;
6'b011100: VAR1 <= 4'd3;
6'b011101: VAR1 <= 4'd9;
6'b011110: VAR1 <= 4'd8;
6'b011111: VAR1 <= 4'd6;
6'b100000: VAR1 <= 4'd4;
6'b100001: VAR1 <= 4'd2;
6'b100010: VAR1 <= 4'd1;
6'b100011: VAR1 <= 4'd11;
6'b100100: VAR1 <= 4'd10;
6'b100101: VAR1 <= 4'd13;
6'b100110: VAR1 <= 4'd7;
6'b100111: VAR1 <= 4'd8;
6'b101000: VAR1 <= 4'd15;
6'b101001: VAR1 <= 4'd9;
6'b101010: VAR1 <= 4'd12;
6'b101011: VAR1 <= 4'd5;
6'b101100: VAR1 <= 4'd6;
6'b101101: VAR1 <= 4'd3;
6'b101110: VAR1 <= 4'd0;
6'b101111: VAR1 <= 4'd14;
6'b110000: VAR1 <= 4'd11;
6'b110001: VAR1 <= 4'd8;
6'b110010: VAR1 <= 4'd12;
6'b110011: VAR1 <= 4'd7;
6'b110100: VAR1 <= 4'd1;
6'b110101: VAR1 <= 4'd14;
6'b110110: VAR1 <= 4'd2;
6'b110111: VAR1 <= 4'd13;
6'b111000: VAR1 <= 4'd6;
6'b111001: VAR1 <= 4'd15;
6'b111010: VAR1 <= 4'd0;
6'b111011: VAR1 <= 4'd9;
6'b111100: VAR1 <= 4'd10;
6'b111101: VAR1 <= 4'd4;
6'b111110: VAR1 <= 4'd5;
6'b111111: VAR1 <= 4'd3;
default: VAR1 <= 4'd0;
endcase
end
endmodule
|
gpl-2.0
|
chahuja/hilbert-fpga
|
fft32.v
| 2,099 |
module MODULE1( VAR19 ,VAR20 ,VAR3 ,VAR17 ,VAR23 ,VAR13 ,VAR1 ,VAR15 ,VAR4, VAR22 );
parameter VAR6 = 32;
input VAR19;
input VAR20;
input VAR3;
input VAR17;
input VAR22;
input [VAR6-1:0] VAR23;
input [VAR6-1:0] VAR13;
output reg VAR1;
output [VAR6-1:0] VAR15;
output [VAR6-1:0] VAR4;
wire [VAR6-1:0] VAR24;
wire [VAR6-1:0] VAR2;
wire [VAR6+3:0] VAR7;
wire [VAR6+3:0] VAR9;
wire [VAR6-1:0] VAR12;
wire [VAR6-1:0] VAR18;
wire [VAR6-1:0] VAR11;
wire [VAR6-1:0] VAR8;
wire VAR21,VAR5,VAR10;
wire [3:0] VAR16;
reg [5:0] VAR14;
assign VAR16 = VAR14[3:0];
|
gpl-2.0
|
khldragon/Sora
|
FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_BYTE_Alignment.v
| 9,498 |
module MODULE1(
input clk,
input enable, input [7:0] VAR8,
output reg VAR4,
output reg [7:0] VAR11
);
reg [7:0] VAR5; reg [7:0] VAR6; reg [7:0] VAR1; reg [2:0] VAR3; reg VAR10; reg [7:0] VAR7; reg [2:0] VAR12;
reg [7:0] VAR9;
reg [7:0] VAR2;
always @(negedge clk) begin
if (!enable)begin
VAR9 <= 8'h00; end
else
begin
case(VAR3) 3'h0 : VAR9 <= VAR5;
3'h1 : VAR9 <= ({VAR5[6:0],VAR8[7]});
3'h2 : VAR9 <= ({VAR5[5:0],VAR8[7:6]});
3'h3 : VAR9 <= ({VAR5[4:0],VAR8[7:5]});
3'h4 : VAR9 <= ({VAR5[3:0],VAR8[7:4]});
3'h5 : VAR9 <= ({VAR5[2:0],VAR8[7:3]});
3'h6 : VAR9 <= ({VAR5[1:0],VAR8[7:2]});
3'h7 : VAR9 <= ({VAR5[0],VAR8[7:1]});
default : VAR9 <= VAR5;
endcase
end
end
always@(negedge clk) begin
if(!enable || !VAR10) begin
VAR7 <= 0; VAR12 <= 0;
end
if(VAR10) begin
VAR7 <= VAR7 + 1; VAR12 <= VAR12+1;
end
end
always @(negedge clk) begin
if(!enable)
begin
VAR5 <= 8'h00; VAR6 <= 8'h00;
VAR1 <= 8'h00;
end
else
begin
VAR5 <= VAR8; VAR6 <= VAR5; VAR1 <= VAR6;
end
end
always @(negedge clk) begin
if(!enable) begin
VAR10 <= 0;
VAR3 <= 0;
VAR11 <= 8'h00; VAR4 <= 0;
VAR2 <= 0;
end
else begin if(!VAR10) begin
if(VAR1 === 8'hf5 & VAR6 === 8'h08) begin
VAR10 <= 1;
VAR3 <= 3'h0;
end
else if({VAR1[6:0],VAR6[7]} === 8'hf5 & {VAR6[6:0],VAR5[7]} === 8'h08 )
begin
VAR10 <= 1;
VAR3 <= 3'h1;
end
else if({VAR1[5:0],VAR6[7:6]} === 8'hf5 & {VAR6[5:0],VAR5[7:6]} === 8'h08)
begin
VAR10 <= 1;
VAR3 <= 3'h2;
end
else if({VAR1[4:0],VAR6[7:5]} === 8'hf5 & {VAR6[4:0],VAR5[7:5]} === 8'h08)
begin
VAR10 <= 1;
VAR3 <= 3'h3;
end
else if({VAR1[3:0],VAR6[7:4]} === 8'hf5 & {VAR6[3:0],VAR5[7:4]} === 8'h08)
begin
VAR10 <= 1;
VAR3 <= 3'h4;
end
else if({VAR1[2:0],VAR6[7:3]} === 8'hf5 & {VAR6[2:0],VAR5[7:3]} === 8'h08)
begin
VAR10 <= 1;
VAR3 <= 3'h5;
end
else if({VAR1[1:0],VAR6[7:2]} === 8'hf5 & {VAR6[1:0],VAR5[7:2]} === 8'h08)
begin
VAR10 <= 1;
VAR3 <= 3'h6;
end
else if({VAR1[0],VAR6[7:1]} === 8'hf5 & {VAR6[0],VAR5[7:1]} === 8'h08) begin
VAR10 <= 1;
VAR3 <= 3'h7;
end
end
else if (VAR10)
begin
if(VAR7 < 29) begin
VAR4 <= 1;
VAR11 <= VAR9;
end
else
begin
VAR4 <= 0;
VAR10 <= 0;
VAR3 <= 0;
VAR2 <= 0;
end
end
end end
endmodule
|
bsd-2-clause
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/axi_ad9144/axi_ad9144.v
| 10,664 |
module MODULE1 (
VAR20,
VAR100,
VAR105,
VAR33,
VAR107,
VAR76,
VAR72,
VAR114,
VAR7,
VAR89,
VAR62,
VAR41,
VAR91,
VAR68,
VAR78,
VAR92,
VAR25,
VAR65,
VAR51,
VAR2,
VAR35,
VAR27,
VAR56,
VAR60,
VAR70,
VAR23,
VAR73,
VAR80,
VAR111,
VAR17,
VAR40,
VAR79,
VAR84,
VAR37,
VAR6,
VAR29,
VAR28,
VAR113);
parameter VAR8 = 0;
parameter VAR53 = 1;
parameter VAR57 = 0;
input VAR20;
output [(128*VAR53)+127:0] VAR100;
output VAR105;
output VAR33;
output VAR107;
input [63:0] VAR76;
output VAR72;
output VAR114;
input [63:0] VAR7;
output VAR89;
output VAR62;
input [63:0] VAR41;
output VAR91;
output VAR68;
input [63:0] VAR78;
input VAR92;
input VAR25;
input VAR65;
input VAR51;
input VAR2;
input [ 31:0] VAR35;
input [ 2:0] VAR27;
output VAR56;
input VAR60;
input [ 31:0] VAR70;
input [ 3:0] VAR23;
output VAR73;
output VAR80;
output [ 1:0] VAR111;
input VAR17;
input VAR40;
input [ 31:0] VAR79;
input [ 2:0] VAR84;
output VAR37;
output VAR6;
output [ 31:0] VAR29;
output [ 1:0] VAR28;
input VAR113;
wire VAR39;
wire VAR87;
wire VAR109;
wire [255:0] VAR108;
wire [ 15:0] VAR66;
wire [ 15:0] VAR38;
wire [ 15:0] VAR104;
wire [ 15:0] VAR22;
wire [ 15:0] VAR67;
wire [ 15:0] VAR49;
wire [ 15:0] VAR45;
wire [ 15:0] VAR95;
wire [ 15:0] VAR77;
wire [ 15:0] VAR11;
wire [ 15:0] VAR81;
wire [ 15:0] VAR117;
wire [ 15:0] VAR19;
wire [ 15:0] VAR88;
wire [ 15:0] VAR71;
wire [ 15:0] VAR75;
wire VAR82;
wire [ 13:0] VAR102;
wire [ 31:0] VAR83;
wire VAR9;
wire VAR44;
wire [ 13:0] VAR69;
wire [ 31:0] VAR97;
wire VAR31;
assign VAR87 = VAR65;
assign VAR109 = VAR51;
assign VAR100 = (VAR53 == 1) ? VAR108 : VAR108[127:0];
VAR85 VAR74 (
.VAR20 (VAR20),
.VAR100 (VAR108),
.VAR105 (VAR105),
.VAR39 (VAR39),
.VAR90 (VAR66),
.VAR115 (VAR38),
.VAR58 (VAR104),
.VAR14 (VAR22),
.VAR46 (VAR67),
.VAR59 (VAR49),
.VAR42 (VAR45),
.VAR54 (VAR95),
.VAR16 (VAR77),
.VAR10 (VAR11),
.VAR21 (VAR81),
.VAR99 (VAR117),
.VAR55 (VAR19),
.VAR4 (VAR88),
.VAR116 (VAR71),
.VAR43 (VAR75));
VAR1 #(.VAR8(VAR8), .VAR15(VAR57)) VAR94 (
.VAR105 (VAR105),
.VAR39 (VAR39),
.VAR90 (VAR66),
.VAR115 (VAR38),
.VAR58 (VAR104),
.VAR14 (VAR22),
.VAR46 (VAR67),
.VAR59 (VAR49),
.VAR42 (VAR45),
.VAR54 (VAR95),
.VAR16 (VAR77),
.VAR10 (VAR11),
.VAR21 (VAR81),
.VAR99 (VAR117),
.VAR55 (VAR19),
.VAR4 (VAR88),
.VAR116 (VAR71),
.VAR43 (VAR75),
.VAR33 (VAR33),
.VAR107 (VAR107),
.VAR76 (VAR76),
.VAR72 (VAR72),
.VAR114 (VAR114),
.VAR7 (VAR7),
.VAR89 (VAR89),
.VAR62 (VAR62),
.VAR41 (VAR41),
.VAR91 (VAR91),
.VAR68 (VAR68),
.VAR78 (VAR78),
.VAR92 (VAR92),
.VAR25 (VAR25),
.VAR109 (VAR109),
.VAR87 (VAR87),
.VAR98 (VAR82),
.VAR93 (VAR102),
.VAR96 (VAR83),
.VAR5 (VAR9),
.VAR103 (VAR44),
.VAR48 (VAR69),
.VAR30 (VAR97),
.VAR52 (VAR31));
VAR64 VAR86 (
.VAR109 (VAR109),
.VAR87 (VAR87),
.VAR50 (VAR2),
.VAR61 (VAR35),
.VAR12 (VAR56),
.VAR24 (VAR60),
.VAR13 (VAR70),
.VAR112 (VAR23),
.VAR101 (VAR73),
.VAR26 (VAR80),
.VAR106 (VAR111),
.VAR63 (VAR17),
.VAR36 (VAR40),
.VAR110 (VAR79),
.VAR18 (VAR37),
.VAR47 (VAR6),
.VAR34 (VAR28),
.VAR3 (VAR29),
.VAR32 (VAR113),
.VAR98 (VAR82),
.VAR93 (VAR102),
.VAR96 (VAR83),
.VAR5 (VAR9),
.VAR103 (VAR44),
.VAR48 (VAR69),
.VAR30 (VAR97),
.VAR52 (VAR31));
endmodule
|
gpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.behavioral.pp.v
| 2,576 |
module MODULE1( VAR7, VAR5, VAR6, VAR9, VAR8, VAR4 );
input VAR5, VAR7, VAR6;
inout VAR8, VAR4;
output VAR9;
VAR2 VAR1(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR4(VAR4));
VAR2 VAR3(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR4(VAR4));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/and3/sky130_fd_sc_hs__and3.symbol.v
| 1,238 |
module MODULE1 (
input VAR5,
input VAR3,
input VAR4,
output VAR6
);
supply1 VAR2;
supply0 VAR1;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/and4bb/sky130_fd_sc_hs__and4bb_2.v
| 2,196 |
module MODULE2 (
VAR7 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR4,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR6;
VAR9 VAR8 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7 ,
VAR1,
VAR2,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR1;
input VAR2;
input VAR3 ;
input VAR5 ;
supply1 VAR4;
supply0 VAR6;
VAR9 VAR8 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/ebufn/sky130_fd_sc_hd__ebufn.functional.pp.v
| 1,870 |
module MODULE1 (
VAR1 ,
VAR11 ,
VAR12,
VAR3,
VAR13,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR11 ;
input VAR12;
input VAR3;
input VAR13;
input VAR6 ;
input VAR4 ;
wire VAR2 ;
wire VAR7;
VAR8 VAR5 (VAR2 , VAR11, VAR3, VAR13 );
VAR8 VAR10 (VAR7, VAR12, VAR3, VAR13 );
bufif0 VAR9 (VAR1 , VAR2, VAR7);
endmodule
|
apache-2.0
|
ThomasLee969/verilog-homework
|
exp2/sequence_detector_fsm/sequence_detector_fsm.v
| 1,237 |
module MODULE1(VAR7, state, reset, VAR1, clk);
output VAR7;
output reg [2:0] state;
input reset, VAR1, clk;
parameter VAR9 = 1'b1,
VAR3 = 1'b0;
parameter VAR11 = 3'd0,
VAR13 = 3'd1,
VAR12 = 3'd2,
VAR4 = 3'd3,
VAR2 = 3'd4,
VAR8 = 3'd5,
VAR5 = 3'd6;
reg VAR10;
reg [2:0] VAR6;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= VAR11;
VAR10 <= 1'b0;
end else begin
state <= VAR6;
VAR10 <= VAR1;
end
end
assign VAR7 = (state == VAR5 ? VAR9 : VAR3);
always @(state, VAR10) begin
case (state)
VAR11: VAR6 = (VAR10 ? VAR13 : VAR11);
VAR13: VAR6 = (VAR10 ? VAR13 : VAR12);
VAR12: VAR6 = (VAR10 ? VAR4 : VAR11);
VAR4: VAR6 = (VAR10 ? VAR13 : VAR2);
VAR2: VAR6 = (VAR10 ? VAR8 : VAR11);
VAR8: VAR6 = (VAR10 ? VAR5 : VAR2);
VAR5: VAR6 = (VAR10 ? VAR13 : VAR12);
default: VAR6 = VAR11;
endcase
end
endmodule
|
mit
|
deepakcu/maestro
|
fpga/DE4_Ethernet_0/src/store_pkt.v
| 12,019 |
module MODULE1
parameter VAR1 = 64,
parameter VAR2=VAR1/8,
parameter VAR17 = 5,
parameter VAR23 = 13,
parameter VAR19 = 11,
parameter VAR11 = VAR19-VAR4(VAR2),
parameter VAR15 = 6,
parameter VAR45 = VAR4(VAR17)
)
( VAR56,
VAR37,
VAR47,
VAR59,
VAR36,
VAR30,
VAR39,
VAR24,
VAR55,
VAR9,
VAR60,
VAR29,
VAR5,
VAR52,
VAR61,
VAR34,
VAR28,
VAR33,
VAR14,
VAR7,
VAR25,
VAR3,
VAR53,
VAR16,
VAR32,
clk,
reset
);
input VAR56;
input [VAR45-1:0] VAR37;
input [VAR19-1:0] VAR47;
input [VAR11-1:0] VAR59;
output reg VAR36;
output reg [VAR23-1:0] VAR30;
output reg VAR39;
output reg VAR24;
output reg [VAR19-1:0] VAR55;
output reg [VAR2-1:0] VAR9;
output reg [VAR11-1:0] VAR60;
output reg [VAR45-1:0] VAR29;
output reg VAR5;
input [VAR23-1:0] VAR52;
input [VAR23-1:0] VAR61;
input [VAR23-1:0] VAR34;
input [VAR17-1:0] VAR28;
output reg [VAR23-1:0] VAR33;
output reg VAR14;
input VAR7;
output reg [VAR1+VAR2-1:0] VAR25;
output reg VAR3;
input VAR53;
input [VAR1-1:0] VAR16;
input [VAR2-1:0] VAR32;
input clk;
input reset;
function integer VAR4;
input integer VAR50;
begin
VAR4=0;
while(2**VAR4<VAR50) begin
VAR4=VAR4+1;
end
end
endfunction
parameter VAR6 = 7;
parameter VAR40 = 1;
parameter VAR57 = 2;
parameter VAR35 = 4;
parameter VAR27 = 8;
parameter VAR51 = 16;
parameter VAR20 = 32;
parameter VAR21 = 64;
parameter VAR12 = 1;
parameter VAR38 = 2;
parameter VAR18 = 4;
reg [VAR6-1:0] VAR42;
reg [VAR6-1:0] VAR48;
wire [VAR23-1:0] VAR58;
reg [VAR23-1:0] VAR43;
reg [VAR1+VAR2-1:0] VAR41;
reg VAR10;
wire VAR62;
reg VAR8;
reg [VAR45-1:0] VAR22;
reg [VAR19-1:0] VAR31;
reg [VAR19-1:0] VAR54;
reg [VAR11-1:0] VAR49;
reg [VAR11-1:0] VAR46;
reg [VAR23-1:0] VAR44;
reg [VAR23-1:0] VAR13;
reg [VAR23-1:0] VAR26;
reg [VAR23-1:0] VAR63;
assign VAR58 = (VAR33 >= VAR26) ?
VAR44 : VAR33 + 1;
assign VAR62 = (VAR8 && VAR32!=0);
always @(*) begin
VAR36 = 0;
VAR5 = 0;
VAR48 = VAR42;
VAR10 = VAR14;
VAR3 = 0;
VAR24 = 0;
VAR41 = VAR25;
VAR43 = VAR33;
VAR30 = VAR58;
VAR39 = 0;
VAR22 = VAR29;
VAR54 = VAR31;
VAR46 = VAR49;
VAR13 = VAR44;
VAR63 = VAR26;
case(VAR42)
VAR40: begin
if(VAR56) begin
VAR48 = VAR57;
VAR22 = VAR37;
VAR54 = VAR47;
VAR46 = VAR59;
VAR36 = 1;
end
end
VAR57: begin
VAR48 = VAR35;
VAR5 = 1;
end
VAR35: begin
if(!VAR28[VAR29]) begin
VAR48 = VAR27;
VAR10 = 1;
VAR43 = VAR34;
VAR13 = VAR61;
VAR63 = VAR52;
VAR41 = {VAR32, VAR16};
VAR3 = 1;
end
else begin
VAR48 = VAR21;
VAR3 = !VAR53;
end
end
VAR27: begin
if(VAR7 & !VAR53) begin
VAR10 = 1;
VAR43 = VAR58;
VAR41 = {VAR32, VAR16};
VAR3 = 1;
if(VAR62) begin
VAR48 = VAR20;
end
end
else if (VAR7 & VAR53) begin
VAR48 = VAR51;
VAR10 = 0;
end
end
VAR51: begin
if(!VAR53) begin
VAR10 = 1;
VAR43 = VAR58;
VAR41 = {VAR32, VAR16};
VAR3 = 1;
if(VAR62) begin
VAR48 = VAR20;
end
else begin
VAR48 = VAR27;
end
end end
VAR20: begin
if(VAR7) begin
VAR10 = 0;
VAR39 = 1;
VAR48 = VAR40;
end end
VAR21: begin
if(VAR62) begin
VAR48 = VAR40;
VAR24 = 1;
end
VAR3 = !VAR53;
end
default: begin end
endcase
end
always @(posedge clk) begin
if(reset) begin
VAR42 <= VAR40;
VAR8 <= 0;
VAR14 <= 0;
VAR33 <= 0;
VAR25 <= 0;
VAR29 <= 0;
VAR31 <= 0;
VAR49 <= 0;
VAR44 <= 0;
VAR26 <= 0;
end
else begin
VAR42 <= VAR48;
VAR14 <= VAR10;
VAR33 <= VAR43;
VAR25 <= VAR41;
VAR29 <= VAR22;
VAR31 <= VAR54;
VAR49 <= VAR46;
VAR44 <= VAR13;
VAR26 <= VAR63;
if(VAR3) begin
VAR8 <= (VAR32==0);
end
end if(VAR48 == VAR21) begin
end
end
always @(posedge clk) begin
VAR55 <= VAR31;
VAR9 <= VAR2;
VAR60 <= VAR49 + 1;
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/and2b/sky130_fd_sc_ms__and2b.functional.v
| 1,356 |
module MODULE1 (
VAR4 ,
VAR2,
VAR3
);
output VAR4 ;
input VAR2;
input VAR3 ;
wire VAR8 ;
wire VAR1;
not VAR6 (VAR8 , VAR2 );
and VAR5 (VAR1, VAR8, VAR3 );
buf VAR7 (VAR4 , VAR1 );
endmodule
|
apache-2.0
|
justinzhf/MIPS-CPU
|
SwapUnit.v
| 1,051 |
module MODULE1(VAR1,VAR3,rd,VAR5,VAR7,VAR8,VAR6,VAR4,VAR2,rst);
input[4:0] VAR1,VAR3,rd,VAR7,VAR8;
input VAR5,VAR6;
output[1:0] VAR2,VAR4;
reg[1:0] VAR4,VAR2;
input rst;
always @(VAR1 or VAR3 or rd or VAR5 or VAR7 or VAR8 or VAR6 or VAR4 or VAR2 or rst) begin
if (rst) begin
VAR4<=0;
VAR2<=0;
end
else begin
if(VAR6 && (VAR8!=0) && !((VAR5 && (VAR7!=0)) && (VAR7==VAR1)) && (VAR8==VAR1))VAR4<=2'b01;
end
else if(VAR5 && (VAR7!=0) && (VAR7==VAR1)) VAR4<=2'b10;
end
else VAR4<=0;
if(VAR6 && (VAR8!=0) && !((VAR5 && (VAR7!=0)) && (VAR7==VAR3)) && (VAR8==VAR3))VAR2<=2'b01;
else if(VAR5 && (VAR7!=0) && (VAR7==VAR3)) VAR2<=2'b10;
else VAR2<=0;
end
end
endmodule
|
gpl-3.0
|
eda-globetrotter/MarcheProcessor
|
processor/regfile.v
| 1,845 |
module MODULE1(VAR2, VAR3, VAR7, VAR1, VAR5, clk);
parameter VAR6 = 8; parameter VAR4 = 8;
output [VAR4-1:0] VAR2;
input [VAR4-1:0] VAR3;
input clk;
input VAR5;
input [VAR6-1:0] VAR7, VAR1;
reg [VAR4-1:0] VAR2; reg [VAR6-1:0] MODULE1 [VAR4-1:0];
always @(posedge clk)
begin
if(VAR5)
begin
MODULE1[VAR7] <= VAR3;
end
else
begin
VAR2<=MODULE1[VAR1];
end
end
endmodule
|
mit
|
klaNath/synth1
|
sine.v
| 1,932 |
module MODULE1 (
VAR22,
VAR25
);
input wire [20:0] VAR22;
output wire [15:0] VAR25;
wire [8:0] VAR1;
wire [9:0] VAR7;
wire [15:0] VAR24;
wire [15:0] VAR4;
wire [25:0] VAR19;
wire [15:0] VAR11;
wire [15:0] VAR3;
function [8:0] VAR14;
input [8:0] VAR8;
input sel;
begin
case(sel)
0 : VAR14 = VAR8;
1 : VAR14 = 9'VAR20 - VAR8;
default : VAR14 = 9'VAR13;
endcase
end
endfunction
function [9:0] VAR5;
input [9:0] VAR2;
input sel;
begin
case(sel)
0 : VAR5 = VAR2;
1 : VAR5 = 10'VAR18 - VAR2;
default : VAR5 = 10'VAR12;
endcase
end
endfunction
function [15:0] VAR17;
input [15:0] VAR3;
input sel;
begin
case(sel)
0 : VAR17 = VAR3 >> 1;
1 : VAR17 = ~(VAR3 >> 1) + 1'b1;
default : VAR17 = 16'VAR16;
endcase
end
endfunction
assign VAR19 = VAR4 * VAR7;
assign VAR11 = VAR19[25:9];
assign VAR3 = VAR24[15:0] + VAR11[15:0];
assign VAR1 = VAR14(VAR22[18:10], VAR22[19]);
assign VAR7 = VAR5(VAR22[9:0], VAR22[19]);
assign VAR25 = VAR17(VAR3, VAR22[20]);
VAR23 VAR21(
.VAR9(VAR1),
.VAR15(VAR24)
);
VAR26 VAR6(
.VAR9(VAR1),
.VAR10(VAR4)
);
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.behavioral.v
| 1,163 |
module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlxbp/sky130_fd_sc_ms__dlxbp.functional.v
| 1,640 |
module MODULE1 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR9
);
output VAR2 ;
output VAR3 ;
input VAR1 ;
input VAR9;
wire VAR8;
VAR6 VAR5 VAR4 (VAR8 , VAR1, VAR9 );
buf VAR10 (VAR2 , VAR8 );
not VAR7 (VAR3 , VAR8 );
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/common/ad_csc_1.v
| 4,244 |
module MODULE1 (
clk,
sync,
VAR21,
VAR8,
VAR11,
VAR2,
VAR12,
VAR19,
VAR28);
parameter VAR4 = 16;
localparam VAR23 = VAR4 - 1;
input clk;
input [VAR23:0] sync;
input [23:0] VAR21;
input [16:0] VAR8;
input [16:0] VAR11;
input [16:0] VAR2;
input [24:0] VAR12;
output [VAR23:0] VAR19;
output [ 7:0] VAR28;
wire [24:0] VAR27;
wire [24:0] VAR15;
wire [24:0] VAR17;
wire [VAR23:0] VAR16;
VAR1 #(.VAR4(1)) VAR6 (
.clk (clk),
.VAR26 (VAR8),
.VAR22 (VAR21[23:16]),
.VAR25 (VAR27),
.VAR7 (1'd0),
.VAR9 ());
VAR1 #(.VAR4(1)) VAR18 (
.clk (clk),
.VAR26 (VAR11),
.VAR22 (VAR21[15:8]),
.VAR25 (VAR15),
.VAR7 (1'd0),
.VAR9 ());
VAR1 #(.VAR4(VAR4)) VAR10 (
.clk (clk),
.VAR26 (VAR2),
.VAR22 (VAR21[7:0]),
.VAR25 (VAR17),
.VAR7 (sync),
.VAR9 (VAR16));
VAR14 #(.VAR4(VAR4)) VAR5 (
.clk (clk),
.VAR20 (VAR27),
.VAR24 (VAR15),
.VAR13 (VAR17),
.VAR3 (VAR12),
.VAR25 (VAR28),
.VAR7 (VAR16),
.VAR9 (VAR19));
endmodule
|
gpl-3.0
|
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