repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
hanw/sonic-lite
|
hw/verilog/timestamp/xgmii_mux.v
| 4,373 |
module MODULE1 (
VAR20,
VAR5,
VAR2,
VAR6,
VAR22,
sel,
VAR13);
input VAR20;
input [65:0] VAR5;
input [65:0] VAR2;
input [65:0] VAR6;
input [65:0] VAR22;
input [1:0] sel;
output [65:0] VAR13;
wire [65:0] VAR4;
wire [65:0] VAR12 = VAR22[65:0];
wire [65:0] VAR17 = VAR6[65:0];
wire [65:0] VAR3 = VAR2[65:0];
wire [65:0] VAR13 = VAR4[65:0];
wire [65:0] VAR9 = VAR5[65:0];
wire [263:0] VAR21 = {VAR12, VAR17, VAR3, VAR9};
VAR8 VAR19 (
.VAR20 (VAR20),
.VAR1 (VAR21),
.sel (sel),
.VAR13 (VAR4)
,
.VAR11 (),
.VAR23 ()
);
VAR19.VAR18 = 1,
VAR19.VAR14 = 4,
VAR19.VAR16 = "VAR15",
VAR19.VAR10 = 66,
VAR19.VAR7 = 2;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21boi/sky130_fd_sc_hdll__a21boi.behavioral.pp.v
| 2,194 |
module MODULE1 (
VAR15 ,
VAR12 ,
VAR6 ,
VAR1,
VAR8,
VAR5,
VAR14 ,
VAR4
);
output VAR15 ;
input VAR12 ;
input VAR6 ;
input VAR1;
input VAR8;
input VAR5;
input VAR14 ;
input VAR4 ;
wire VAR11 ;
wire VAR3 ;
wire VAR10 ;
wire VAR7;
not VAR9 (VAR11 , VAR1 );
and VAR2 (VAR3 , VAR12, VAR6 );
nor VAR18 (VAR10 , VAR11, VAR3 );
VAR17 VAR16 (VAR7, VAR10, VAR8, VAR5);
buf VAR13 (VAR15 , VAR7 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nor3b/sky130_fd_sc_ms__nor3b.functional.v
| 1,417 |
module MODULE1 (
VAR1 ,
VAR6 ,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR7;
wire VAR2 ;
wire VAR8;
nor VAR5 (VAR2 , VAR6, VAR4 );
and VAR3 (VAR8, VAR7, VAR2 );
buf VAR9 (VAR1 , VAR8 );
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.behavioral.pp.v
| 2,375 |
module MODULE1( VAR5, VAR9, VAR6, VAR10, VAR3, VAR7, VAR4 );
input VAR10, VAR3, VAR9, VAR5;
inout VAR7, VAR4;
output VAR6;
VAR2 VAR1(.VAR5(VAR5),.VAR9(VAR9),.VAR6(VAR6),.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4));
VAR2 VAR8(.VAR5(VAR5),.VAR9(VAR9),.VAR6(VAR6),.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4));
|
apache-2.0
|
monotone-RK/FACE
|
IEICE-Trans/8-way_2-tree/src/riffa/sg_list_reader_128.v
| 4,700 |
module MODULE1 #(
parameter VAR13 = 9'd128
)
(
input VAR6,
input VAR3,
input [VAR13-1:0] VAR9, input VAR12, output VAR18,
output VAR4, output VAR10, input VAR17, output [63:0] VAR1, output [31:0] VAR5 );
reg VAR15=VAR2, VAR15=VAR2;
reg VAR21=VAR16, VAR21=VAR16;
reg [VAR13-1:0] VAR20={VAR13{1'd0}}, VAR20={VAR13{1'd0}};
reg [63:0] VAR22=64'd0, VAR22=64'd0;
reg [31:0] VAR11=0, VAR11=0;
reg VAR14=0, VAR14=0;
reg VAR7=0, VAR7=0;
assign VAR18 = VAR15; assign VAR4 = VAR21; assign VAR10 = (VAR12 & VAR15); assign VAR1 = VAR22;
assign VAR5 = VAR11;
always @ (posedge VAR6) begin
VAR15 <= (VAR3 ? VAR2 : VAR15);
VAR21 <= (VAR3 ? VAR16 : VAR21);
VAR20 <= VAR20;
VAR14 <= (VAR3 ? 1'd0 : VAR14);
VAR7 <= (VAR3 ? 1'd0 : VAR7);
VAR22 <= VAR22;
VAR11 <= VAR11;
end
always @ (*) begin
VAR15 = VAR15;
VAR21 = VAR21;
VAR22 = VAR22;
VAR11 = VAR11;
VAR20 = VAR9;
VAR14 = (VAR18 & !VAR12);
VAR7 = VAR14;
case (VAR21)
if (VAR7) begin
VAR22 = VAR20[63:0];
VAR11 = VAR20[95:64];
VAR21 = VAR8;
end
end
if (VAR17)
VAR21 = VAR16;
end
endcase
case (VAR15)
VAR15 = VAR19;
end
VAR15 = VAR2;
end
endcase
end
endmodule
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.functional.v
| 1,494 |
module MODULE1( VAR15, VAR16, VAR12, VAR5, VAR14 );
input VAR5, VAR14, VAR16, VAR15;
output VAR12;
wire VAR8;
not VAR17( VAR8, VAR5 );
wire VAR13;
not VAR1( VAR13, VAR14 );
wire VAR18;
and VAR10( VAR18, VAR8, VAR13 );
wire VAR2;
not VAR3( VAR2, VAR16 );
wire VAR11;
not VAR9( VAR11, VAR15 );
wire VAR4;
and VAR6( VAR4, VAR2, VAR11 );
or VAR7( VAR12, VAR18, VAR4 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o211ai/sky130_fd_sc_ls__o211ai.symbol.v
| 1,375 |
module MODULE1 (
input VAR3,
input VAR5,
input VAR9,
input VAR8,
output VAR1
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule
|
apache-2.0
|
Jawanga/ece385final
|
usb_system/synthesis/submodules/CY7C67200_IF.v
| 2,109 |
module MODULE1( VAR6,
VAR2,
VAR3, VAR8,
VAR11,
VAR18,
VAR13,
VAR16,
VAR1,
VAR15,
VAR10,
VAR5,
VAR9,
VAR12,
VAR7,
VAR14
);
input [31:0] VAR6; input [1:0] VAR3; input VAR8; input VAR11; input VAR18; input VAR13; input VAR16; output [31:0] VAR2; output VAR1;
inout [15:0] VAR15;
output [1:0] VAR10;
output VAR5;
output VAR9;
output VAR12;
output VAR7;
input VAR14;
reg [1:0] VAR10;
reg VAR5;
reg VAR9;
reg VAR12;
reg [15:0] VAR17;
reg [31:0] VAR2;
reg VAR1;
assign VAR15 = VAR9 ? 16'VAR4 : VAR17 ;
always@(posedge VAR16 or negedge VAR13)
begin
if(!VAR13)
begin
VAR17 <= 0;
VAR10 <= 0;
VAR5 <= 1;
VAR9 <= 1;
VAR12 <= 1;
VAR17 <= 0;
VAR2 <= 0;
VAR1 <= 0;
end
else
begin
VAR2 <= {16'h0000,VAR15};
VAR1 <= VAR14;
VAR17 <= VAR6[15:0];
VAR10 <= VAR3[1:0];
VAR5 <= VAR8;
VAR9 <= VAR11;
VAR12 <= VAR18;
end
end
assign VAR7 = VAR13;
endmodule
|
apache-2.0
|
eda-globetrotter/MarcheProcessor
|
processor/spare/build2/trash.v
| 55,285 |
module MODULE1 (VAR9,VAR5,VAR27,VAR17,VAR6);
output [0:127] VAR6;
input [0:127] VAR9;
input [0:127] VAR5;
input [0:1] VAR27;
input [0:4] VAR17;
integer VAR31;
reg [0:127] VAR6;
reg [0:127] VAR19;
reg [0:15] VAR29;
reg [0:15] VAR20;
reg [0:15] VAR10;
reg [0:15] VAR1;
reg [0:15] VAR18;
reg [0:15] VAR2;
reg [0:15] VAR21;
reg [0:15] VAR11;
reg [0:15] VAR8;
reg [0:15] VAR24;
reg [0:15] VAR3;
reg [0:15] VAR25;
reg [0:15] VAR13;
reg [0:15] VAR15;
reg [0:15] VAR16;
reg [0:15] VAR4;
reg [0:31] VAR7;
reg [0:31] VAR32;
reg [0:31] VAR14;
reg [0:31] VAR22;
reg [0:31] VAR12;
reg [0:31] VAR26;
reg [0:31] VAR23;
reg [0:31] VAR28;
reg [0:31] VAR30;
always @(VAR9 or VAR5 or VAR27 or VAR17)
begin
VAR19=128'd0;
VAR29=16'd0;
VAR20=16'd0;
VAR10=16'd0;
VAR1=16'd0;
VAR18=16'd0;
VAR2=16'd0;
VAR21=16'd0;
VAR11=16'd0;
VAR8=16'd0;
VAR24=16'd0;
VAR3=16'd0;
VAR25=16'd0;
VAR13=16'd0;
VAR15=16'd0;
VAR16=16'd0;
VAR4=16'd0;
VAR7=32'd0;
VAR32=32'd0;
VAR14=32'd0;
VAR22=32'd0;
VAR12=32'd0;
VAR26=32'd0;
VAR23=32'd0;
VAR28=32'd0;
VAR30=32'd0;
case(VAR17)
begin
case(VAR27)
VAR29[8:15]=VAR9[0:7];
VAR29[0:7]=8'd0;
for(VAR31=7; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[0:15]=VAR19[0:15]+(VAR29<<(7-VAR31));
end
end
VAR6[0:15]=VAR19[0:15];
VAR10[8:15]=VAR9[16:23];
VAR10[0:7]=8'd0;
for(VAR31=23; VAR31>=16; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[16:31]=VAR19[16:31]+(VAR10<<(7-(VAR31%8)));
end
end
VAR6[16:31]=VAR19[16:31];
VAR18[8:15]=VAR9[32:39];
VAR18[0:7]=8'd0;
for(VAR31=39; VAR31>=32; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[32:47]=VAR19[32:47]+(VAR18<<(7-(VAR31%8)));
end
end
VAR6[32:47]=VAR19[32:47];
VAR21[8:15]=VAR9[48:55];
VAR21[0:7]=8'd0;
for(VAR31=55; VAR31>=48; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[48:63]=VAR19[48:63]+(VAR21<<(7-(VAR31%8)));
end
end
VAR6[48:63]=VAR19[48:63];
VAR8[8:15]=VAR9[64:71];
VAR8[0:7]=8'd0;
for(VAR31=71; VAR31>=64; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[64:79]=VAR19[64:79]+(VAR8<<(7-(VAR31%8)));
end
end
VAR6[64:79]=VAR19[64:79];
VAR3[8:15]=VAR9[80:87];
VAR3[0:7]=8'd0;
for(VAR31=87; VAR31>=80; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[80:95]=VAR19[80:95]+(VAR3<<(7-(VAR31%8)));
end
end
VAR6[80:95]=VAR19[80:95];
VAR13[8:15]=VAR9[96:103];
VAR13[0:7]=8'd0;
for(VAR31=103; VAR31>=96; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[96:111]=VAR19[96:111]+(VAR13<<(7-(VAR31%8)));
end
end
VAR6[96:111]=VAR19[96:111];
VAR16[8:15]=VAR9[112:119];
VAR16[0:7]=8'd0;
for(VAR31=119; VAR31>=112; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[112:127]=VAR19[112:127]+(VAR16<<(7-(VAR31%8)));
end
end
VAR6[112:127]=VAR19[112:127];
end
VAR7[16:31]=VAR9[0:15];
VAR7[0:15]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[0:31]=VAR19[0:31]+(VAR9[0:15]<<(15-VAR31));
end
end
VAR6[0:31]=VAR19[0:31];
VAR22[16:31]=VAR9[32:47];
VAR22[0:15]=8'd0;
for(VAR31=47; VAR31>=32; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[32:63]=VAR19[32:63]+(VAR9[32:47]<<(15-(VAR31%16)));
end
end
VAR6[32:63]=VAR19[32:63];
VAR26[16:31]=VAR9[64:79];
VAR26[0:15]=8'd0;
for(VAR31=79; VAR31>=64; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[64:95]=VAR19[64:95]+(VAR9[64:79]<<(15-(VAR31%16)));
end
end
VAR6[64:95]=VAR19[64:95];
VAR28[16:31]=VAR9[96:111];
VAR28[0:15]=8'd0;
for(VAR31=111; VAR31>=96; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[96:127]=VAR19[96:127]+(VAR9[96:111]<<(15-(VAR31%16)));
end
end
VAR6[96:127]=VAR19[96:127];
end
default: begin
VAR6=128'd0;
end
endcase
end
begin
case(VAR27)
VAR29[8:15]=VAR9[8:15];
VAR29[0:7]=8'd0;
for(VAR31=15; VAR31>=8; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[0:15]=VAR19[0:15]+(VAR29<<(7-(VAR31%8)));
end
end
VAR6[0:15]=VAR19[0:15];
VAR10[8:15]=VAR9[24:31];
VAR10[0:7]=8'd0;
for(VAR31=31; VAR31>=24; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[16:31]=VAR19[16:31]+(VAR10<<(7-(VAR31%8)));
end
end
VAR6[16:31]=VAR19[16:31];
VAR18[8:15]=VAR9[40:47];
VAR18[0:7]=8'd0;
for(VAR31=39; VAR31>=33; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[32:47]=VAR19[32:47]+(VAR18<<(7-(VAR31%8)));
end
end
VAR6[32:47]=VAR19[32:47];
VAR21[8:15]=VAR9[56:63];
VAR21[0:7]=8'd0;
for(VAR31=55; VAR31>=48; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[48:63]=VAR19[48:63]+(VAR21<<(7-(VAR31%8)));
end
end
VAR6[48:63]=VAR19[48:63];
VAR8[8:15]=VAR9[72:79];
VAR8[0:7]=8'd0;
for(VAR31=79; VAR31>=72; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[64:79]=VAR19[64:79]+(VAR8<<(7-(VAR31%8)));
end
end
VAR6[64:79]=VAR19[64:79];
VAR3[8:15]=VAR9[88:95];
VAR3[0:7]=8'd0;
for(VAR31=95; VAR31>=88; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[80:95]=VAR19[80:95]+(VAR3<<(7-(VAR31%8)));
end
end
VAR6[80:95]=VAR19[80:95];
VAR13[8:15]=VAR9[104:111];
VAR13[0:7]=8'd0;
for(VAR31=111; VAR31>=104; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[96:111]=VAR19[96:111]+(VAR13<<(7-(VAR31%8)));
end
end
VAR6[96:111]=VAR19[96:111];
VAR16[8:15]=VAR9[120:127];
VAR16[0:7]=8'd0;
for(VAR31=127; VAR31>=120; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[112:127]=VAR19[112:127]+(VAR16<<(7-(VAR31%8)));
end
end
VAR6[112:127]=VAR19[112:127];
end
VAR7[16:31]=VAR9[16:31];
VAR7[0:15]=8'd0;
for(VAR31=31; VAR31>=16; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[0:31]=VAR19[0:31]+(VAR9[16:31]<<(15-(VAR31%16)));
end
end
VAR6[0:31]=VAR19[0:31];
VAR22[16:31]=VAR9[48:63];
VAR22[0:15]=8'd0;
for(VAR31=63; VAR31>=48; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[32:63]=VAR19[32:63]+(VAR9[48:63]<<(15-(VAR31%16)));
end
end
VAR6[32:63]=VAR19[32:63];
VAR26[16:31]=VAR9[80:95];
VAR26[0:15]=8'd0;
for(VAR31=95; VAR31>=80; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[64:95]=VAR19[64:95]+(VAR9[80:95]<<(15-(VAR31%16)));
end
end
VAR6[64:95]=VAR19[64:95];
VAR28[16:31]=VAR9[112:127];
VAR28[0:15]=8'd0;
for(VAR31=127; VAR31>=112; VAR31=VAR31-1)
begin
if(VAR5[VAR31]==1'b1)
begin
VAR19[96:127]=VAR19[96:127]+(VAR9[112:127]<<(15-(VAR31%16)));
end
end
VAR6[96:127]=VAR19[96:127];
end
default: begin
VAR6=128'd0;
end
endcase
end
begin
case(VAR27)
if(VAR9[8]==0)
begin
VAR29[8:15]=VAR9[8:15];
end
else
begin
VAR29[8:15]=1+~VAR9[8:15];
end
VAR10[0:7]=8'd0;
if(VAR5[8]==0)
begin
VAR20[8:15]=VAR5[8:15];
end
else
begin
VAR20[8:15]=1+~VAR5[8:15];
end
VAR1[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR20[VAR31]==1'b1)
begin
VAR19[0:15]=VAR19[0:15]+(VAR29<<(7-(VAR31%8)));
end
end
if(VAR9[8]^VAR5[8])
begin
VAR6[0:15]=1+~VAR19[0:15];
end
else
begin
VAR6[0:15]=VAR19[0:15];
end
if(VAR9[24]==0)
begin
VAR10[8:15]=VAR9[24:31];
end
else
begin
VAR10[8:15]=1+~VAR9[24:31];
end
VAR10[0:7]=8'd0;
if(VAR5[24]==0)
begin
VAR1[8:15]=VAR5[24:31];
end
else
begin
VAR1[8:15]=1+~VAR5[24:31];
end
VAR1[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR1[VAR31]==1'b1)
begin
VAR19[16:31]=VAR19[16:31]+(VAR10<<(7-(VAR31%8)));
end
end
if(VAR9[24]^VAR5[24])
begin
VAR6[16:31]=1+~VAR19[16:31];
end
else
begin
VAR6[16:31]=VAR19[16:31];
end
if(VAR9[40]==0)
begin
VAR18[8:15]=VAR9[40:47];
end
else
begin
VAR18[8:15]=1+~VAR9[40:47];
end
VAR18[0:7]=8'd0;
if(VAR5[40]==0)
begin
VAR2[8:15]=VAR5[40:47];
end
else
begin
VAR2[8:15]=1+~VAR5[40:47];
end
VAR2[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR2[VAR31]==1'b1)
begin
VAR19[32:47]=VAR19[32:47]+(VAR18<<(7-(VAR31%8)));
end
end
if(VAR9[40]^VAR5[40])
begin
VAR6[32:47]=1+~VAR19[32:47];
end
else
begin
VAR6[32:47]=VAR19[32:47];
end
if(VAR9[56]==0)
begin
VAR21[8:15]=VAR9[56:63];
end
else
begin
VAR21[8:15]=1+~VAR9[56:63];
end
VAR21[0:7]=8'd0;
if(VAR5[56]==0)
begin
VAR11[8:15]=VAR5[56:63];
end
else
begin
VAR11[8:15]=1+~VAR5[56:63];
end
VAR11[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR11[VAR31]==1'b1)
begin
VAR19[48:63]=VAR19[48:63]+(VAR21<<(7-(VAR31%8)));
end
end
if(VAR9[56]^VAR5[56])
begin
VAR6[48:63]=1+~VAR19[48:63];
end
else
begin
VAR6[48:63]=VAR19[48:63];
end
if(VAR9[72]==0)
begin
VAR8[8:15]=VAR9[72:79];
end
else
begin
VAR8[8:15]=1+~VAR9[72:79];
end
VAR8[0:7]=8'd0;
if(VAR5[72]==0)
begin
VAR24[8:15]=VAR5[72:79];
end
else
begin
VAR24[8:15]=1+~VAR5[72:79];
end
VAR24[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR24[VAR31]==1'b1)
begin
VAR19[64:79]=VAR19[64:79]+(VAR8<<(7-(VAR31%8)));
end
end
if(VAR9[72]^VAR5[72])
begin
VAR6[64:79]=1+~VAR19[64:79];
end
else
begin
VAR6[64:79]=VAR19[64:79];
end
if(VAR9[88]==0)
begin
VAR3[8:15]=VAR9[88:95];
end
else
begin
VAR3[8:15]=1+~VAR9[88:95];
end
VAR3[0:7]=8'd0;
if(VAR5[88]==0)
begin
VAR25[8:15]=VAR5[88:95];
end
else
begin
VAR25[8:15]=1+~VAR5[88:95];
end
VAR25[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR25[VAR31]==1'b1)
begin
VAR19[80:95]=VAR19[80:95]+(VAR3<<(7-(VAR31%8)));
end
end
if(VAR9[88]^VAR5[88])
begin
VAR6[80:95]=1+~VAR19[80:95];
end
else
begin
VAR6[80:95]=VAR19[80:95];
end
if(VAR9[104]==0)
begin
VAR13[8:15]=VAR9[104:111];
end
else
begin
VAR13[8:15]=1+~VAR9[104:111];
end
VAR13[0:7]=8'd0;
if(VAR5[104]==0)
begin
VAR15[8:15]=VAR5[104:111];
end
else
begin
VAR15[8:15]=1+~VAR5[104:111];
end
VAR15[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR15[VAR31]==1'b1)
begin
VAR19[96:111]=VAR19[96:111]+(VAR13<<(7-(VAR31%8)));
end
end
if(VAR9[104]^VAR5[104])
begin
VAR6[96:111]=1+~VAR19[96:111];
end
else
begin
VAR6[96:111]=VAR19[96:111];
end
if(VAR9[120]==0)
begin
VAR16[8:15]=VAR9[120:127];
end
else
begin
VAR16[8:15]=1+~VAR9[120:127];
end
VAR16[0:7]=8'd0;
if(VAR5[120]==0)
begin
VAR4[8:15]=VAR5[120:127];
end
else
begin
VAR4[8:15]=1+~VAR5[120:127];
end
VAR4[0:7]=8'd0;
for(VAR31=15; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR4[VAR31]==1'b1)
begin
VAR19[112:127]=VAR19[112:127]+(VAR16<<(7-(VAR31%8)));
end
end
if(VAR9[120]^VAR5[120])
begin
VAR6[112:127]=1+~VAR19[112:127];
end
else
begin
VAR6[112:127]=VAR19[112:127];
end
end
if(VAR9[16]==0)
begin
VAR7[16:31]=VAR9[16:31];
end
else
begin
VAR7[16:31]=1+~VAR9[16:31];
end
VAR7[0:15]=16'd0;
if(VAR5[16]==0)
begin
VAR32[16:31]=VAR5[16:31];
end
else
begin
VAR32[16:31]=1+~VAR5[16:31];
end
VAR32[0:15]=16'd0;
for(VAR31=31; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR32[VAR31]==1'b1)
begin
VAR19[0:31]=VAR19[0:31]+(VAR7<<(15-(VAR31%16)));
end
end
if(VAR9[16]^VAR5[16])
begin
VAR6[0:31]=1+~VAR19[0:31];
end
else
begin
VAR6[0:31]=VAR19[0:31];
end
if(VAR9[48]==0)
begin
VAR22[16:31]=VAR9[48:63];
end
else
begin
VAR22[16:31]=1+~VAR9[48:63];
end
VAR22[0:15]=16'd0;
if(VAR5[48]==0)
begin
VAR12[16:31]=VAR5[48:63];
end
else
begin
VAR12[16:31]=1+~VAR5[48:63];
end
VAR12[0:15]=16'd0;
for(VAR31=31; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR12[VAR31]==1'b1)
begin
VAR19[32:63]=VAR19[32:63]+(VAR22<<(15-(VAR31%16)));
end
end
if(VAR9[48]^VAR5[48])
begin
VAR6[32:63]=1+~VAR19[32:63];
end
else
begin
VAR6[32:63]=VAR19[32:63];
end
if(VAR9[80]==0)
begin
VAR26[16:31]=VAR9[80:95];
end
else
begin
VAR26[16:31]=1+~VAR9[80:95];
end
VAR26[0:15]=16'd0;
if(VAR5[80]==0)
begin
VAR23[16:31]=VAR5[80:95];
end
else
begin
VAR23[16:31]=1+~VAR5[80:95];
end
VAR23[0:15]=16'd0;
for(VAR31=31; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR23[VAR31]==1'b1)
begin
VAR19[64:95]=VAR19[64:95]+(VAR26<<(15-(VAR31%16)));
end
end
if(VAR9[80]^VAR5[80])
begin
VAR6[64:95]=1+~VAR19[64:95];
end
else
begin
VAR6[64:95]=VAR19[64:95];
end
if(VAR9[112]==0)
begin
VAR28[16:31]=VAR9[112:127];
end
else
begin
VAR28[16:31]=1+~VAR9[112:127];
end
VAR28[0:15]=16'd0;
if(VAR5[112]==0)
begin
VAR30[16:31]=VAR5[112:127];
end
else
begin
VAR30[16:31]=1+~VAR5[112:127];
end
VAR30[0:15]=16'd0;
for(VAR31=31; VAR31>=0; VAR31=VAR31-1)
begin
if(VAR30[VAR31]==1'b1)
begin
VAR19[96:127]=VAR19[96:127]+(VAR28<<(15-(VAR31%16)));
end
end
if(VAR9[112]^VAR5[112])
begin
VAR6[96:127]=1+~VAR19[96:127];
end
else
begin
VAR6[96:127]=VAR19[96:127];
end
end
default: begin
VAR6=128'd0;
end
endcase
end
begin
case(VAR27)
VAR20[8:15]=VAR5[0:7];
VAR20[0:7]=8'd0;
if(VAR9[0]==1'd1)
begin
VAR29[8:15]=1+~VAR9[0:7];
if(VAR5[0]==1'd1)
begin
VAR20[8:15]=1+~VAR5[0:7];
end
else
begin
VAR20[8:15]=VAR5[0:7];
end
end
else
begin
VAR29[8:15]=VAR9[0:7];
end
VAR29[0:7]=8'd0;
if(VAR20[15]==1'd1)
begin
VAR19[0:15]=VAR19[0:15] - VAR29[0:15];
end
else
begin
VAR19[0:15]=VAR19[0:15]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR20[VAR31]==1'b1) && (VAR20[VAR31+1]==1'b0))
begin
VAR19[0:15]=VAR19[0:15]-(VAR29<<(7-(VAR31%8)));
end
else if((VAR20[VAR31]==1'b0) && (VAR20[VAR31+1]==1'b1))
begin
VAR19[0:15]=VAR19[0:15]+(VAR29<<(7-(VAR31%8)));
end
else
begin
VAR19[0:15]=VAR19[0:15]+0;
end
end
if(VAR29[8]==1'd1)
begin
VAR6[0:15]=1+~VAR19[0:15];
end
else
begin
VAR6[0:15]=VAR19[0:15];
end
VAR1[8:15]=VAR5[16:23];
VAR1[0:7]=8'd0;
if(VAR9[16]==1'd1)
begin
VAR10[8:15]=1+~VAR9[16:23];
if(VAR5[16]==1'd1)
begin
VAR1[8:15]=1+~VAR5[16:23];
end
else
begin
VAR1[8:15]=VAR5[16:23];
end
end
else
begin
VAR10[8:15]=VAR9[16:23];
end
VAR10[0:7]=8'd0;
if(VAR1[15]==1'd1)
begin
VAR19[16:31]=VAR19[16:31] - VAR10[0:15];
end
else
begin
VAR19[16:31]=VAR19[16:31]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR1[VAR31]==1'b1) && (VAR1[VAR31+1]==1'b0))
begin
VAR19[16:31]=VAR19[16:31]-(VAR10<<(7-(VAR31%8)));
end
else if((VAR1[VAR31]==1'b0) && (VAR1[VAR31+1]==1'b1))
begin
VAR19[16:31]=VAR19[16:31]+(VAR10<<(7-(VAR31%8)));
end
else
begin
VAR19[16:31]=VAR19[16:31]+0;
end
end
if(VAR10[8]==1'd1)
begin
VAR6[16:31]=1+~VAR19[16:31];
end
else
begin
VAR6[16:31]=VAR19[16:31];
end
VAR2[8:15]=VAR5[32:39];
VAR2[0:7]=8'd0;
if(VAR9[32]==1'd1)
begin
VAR18[8:15]=1+~VAR9[32:39];
if(VAR5[32]==1'd1)
begin
VAR2[8:15]=1+~VAR5[32:39];
end
else
begin
VAR2[8:15]=VAR5[32:39];
end
end
else
begin
VAR18[8:15]=VAR9[32:39];
end
VAR18[0:7]=8'd0;
if(VAR2[15]==1'd1)
begin
VAR19[32:47]=VAR19[32:47] - VAR18[0:15];
end
else
begin
VAR19[32:47]=VAR19[32:47]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR2[VAR31]==1'b1) && (VAR2[VAR31+1]==1'b0))
begin
VAR19[32:47]=VAR19[32:47]-(VAR18<<(7-(VAR31%8)));
end
else if((VAR2[VAR31]==1'b0) && (VAR2[VAR31+1]==1'b1))
begin
VAR19[32:47]=VAR19[32:47]+(VAR18<<(7-(VAR31%8)));
end
else
begin
VAR19[32:47]=VAR19[32:47]+0;
end
end
if(VAR18[8]==1'd1)
begin
VAR6[32:47]=1+~VAR19[32:47];
end
else
begin
VAR6[32:47]=VAR19[32:47];
end
VAR11[8:15]=VAR5[48:55];
VAR11[0:7]=8'd0;
if(VAR9[48]==1'd1)
begin
VAR21[8:15]=1+~VAR9[48:55];
if(VAR5[48]==1'd1)
begin
VAR11[8:15]=1+~VAR5[48:55];
end
else
begin
VAR11[8:15]=VAR5[48:55];
end
end
else
begin
VAR21[8:15]=VAR9[48:55];
end
VAR21[0:7]=8'd0;
if(VAR11[15]==1'd1)
begin
VAR19[48:63]=VAR19[48:63] - VAR21[0:15];
end
else
begin
VAR19[48:63]=VAR19[48:63]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR11[VAR31]==1'b1) && (VAR11[VAR31+1]==1'b0))
begin
VAR19[48:63]=VAR19[48:63]-(VAR21<<(7-(VAR31%8)));
end
else if((VAR11[VAR31]==1'b0) && (VAR11[VAR31+1]==1'b1))
begin
VAR19[48:63]=VAR19[48:63]+(VAR21<<(7-(VAR31%8)));
end
else
begin
VAR19[48:63]=VAR19[48:63]+0;
end
end
if(VAR21[8]==1'd1)
begin
VAR6[48:63]=1+~VAR19[48:63];
end
else
begin
VAR6[48:63]=VAR19[48:63];
end
VAR24[8:15]=VAR5[64:71];
VAR24[0:7]=8'd0;
if(VAR9[64]==1'd1)
begin
VAR8[8:15]=1+~VAR9[64:71];
if(VAR5[64]==1'd1)
begin
VAR24[8:15]=1+~VAR5[64:71];
end
else
begin
VAR24[8:15]=VAR5[64:71];
end
end
else
begin
VAR8[8:15]=VAR9[64:71];
end
VAR8[0:7]=8'd0;
if(VAR24[15]==1'd1)
begin
VAR19[64:79]=VAR19[64:79] - VAR8[0:15];
end
else
begin
VAR19[64:79]=VAR19[64:79]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR24[VAR31]==1'b1) && (VAR24[VAR31+1]==1'b0))
begin
VAR19[64:79]=VAR19[64:79]-(VAR8<<(7-(VAR31%8)));
end
else if((VAR24[VAR31]==1'b0) && (VAR24[VAR31+1]==1'b1))
begin
VAR19[64:79]=VAR19[64:79]+(VAR8<<(7-(VAR31%8)));
end
else
begin
VAR19[64:79]=VAR19[64:79]+0;
end
end
if(VAR8[8]==1'd1)
begin
VAR6[64:79]=1+~VAR19[64:79];
end
else
begin
VAR6[64:79]=VAR19[64:79];
end
VAR25[8:15]=VAR5[80:87];
VAR25[0:7]=8'd0;
if(VAR9[80]==1'd1)
begin
VAR3[8:15]=1+~VAR9[80:87];
if(VAR5[80]==1'd1)
begin
VAR25[8:15]=1+~VAR5[80:87];
end
else
begin
VAR25[8:15]=VAR5[80:87];
end
end
else
begin
VAR3[8:15]=VAR9[80:87];
end
VAR3[0:7]=8'd0;
if(VAR25[15]==1'd1)
begin
VAR19[80:95]=VAR19[80:95] - VAR3[0:15];
end
else
begin
VAR19[80:95]=VAR19[80:95]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR25[VAR31]==1'b1) && (VAR25[VAR31+1]==1'b0))
begin
VAR19[80:95]=VAR19[80:95]-(VAR3<<(7-(VAR31%8)));
end
else if((VAR25[VAR31]==1'b0) && (VAR25[VAR31+1]==1'b1))
begin
VAR19[80:95]=VAR19[80:95]+(VAR3<<(7-(VAR31%8)));
end
else
begin
VAR19[80:95]=VAR19[80:95]+0;
end
end
if(VAR3[8]==1'd1)
begin
VAR6[80:95]=1+~VAR19[80:95];
end
else
begin
VAR6[80:95]=VAR19[80:95];
end
VAR15[8:15]=VAR5[96:103];
VAR15[0:7]=8'd0;
if(VAR9[96]==1'd1)
begin
VAR13[8:15]=1+~VAR9[96:103];
if(VAR5[96]==1'd1)
begin
VAR15[8:15]=1+~VAR5[96:103];
end
else
begin
VAR15[8:15]=VAR5[96:103];
end
end
else
begin
VAR13[8:15]=VAR9[96:103];
end
VAR13[0:7]=8'd0;
if(VAR15[15]==1'd1)
begin
VAR19[96:111]=VAR19[96:111] - VAR13[0:15];
end
else
begin
VAR19[96:111]=VAR19[96:111]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR15[VAR31]==1'b1) && (VAR15[VAR31+1]==1'b0))
begin
VAR19[96:111]=VAR19[96:111]-(VAR13<<(7-(VAR31%8)));
end
else if((VAR15[VAR31]==1'b0) && (VAR15[VAR31+1]==1'b1))
begin
VAR19[96:111]=VAR19[96:111]+(VAR13<<(7-(VAR31%8)));
end
else
begin
VAR19[96:111]=VAR19[96:111]+0;
end
end
if(VAR13[8]==1'd1)
begin
VAR6[96:111]=1+~VAR19[96:111];
end
else
begin
VAR6[96:111]=VAR19[96:111];
end
VAR4[8:15]=VAR5[112:119];
VAR4[0:7]=8'd0;
if(VAR9[112]==1'd1)
begin
VAR16[8:15]=1+~VAR9[112:119];
if(VAR5[112]==1'd1)
begin
VAR4[8:15]=1+~VAR5[112:119];
end
else
begin
VAR4[8:15]=VAR5[112:119];
end
end
else
begin
VAR16[8:15]=VAR9[112:119];
end
VAR16[0:7]=8'd0;
if(VAR4[15]==1'd1)
begin
VAR19[112:127]=VAR19[112:127] - VAR16[0:15];
end
else
begin
VAR19[112:127]=VAR19[112:127]+0;
end
for(VAR31=14; VAR31>=8; VAR31=VAR31-1)
begin
if((VAR4[VAR31]==1'b1) && (VAR4[VAR31+1]==1'b0))
begin
VAR19[112:127]=VAR19[112:127]-(VAR16<<(7-(VAR31%8)));
end
else if((VAR4[VAR31]==1'b0) && (VAR4[VAR31+1]==1'b1))
begin
VAR19[112:127]=VAR19[112:127]+(VAR16<<(7-(VAR31%8)));
end
else
begin
VAR19[112:127]=VAR19[112:127]+0;
end
end
if(VAR16[8]==1'd1)
begin
VAR6[112:127]=1+~VAR19[112:127];
end
else
begin
VAR6[112:127]=VAR19[112:127];
end
end
VAR32[16:31]=VAR5[0:15];
VAR32[0:15]=16'd0;
if(VAR9[0]==1'd1)
begin
VAR7[16:31]=1+~VAR9[0:15];
if(VAR5[0]==1'd1)
begin
VAR32[16:31]=1+~VAR5[0:15];
end
else
begin
VAR32[16:31]=VAR5[0:15];
end
end
else
begin
VAR7[16:31]=VAR9[0:15];
end
VAR7[0:15]=16'd0;
if(VAR32[31]==1'd1)
begin
VAR19[0:31]=VAR19[0:31] - VAR7[0:31];
end
else
begin
VAR19[0:31]=VAR19[0:31]+0;
end
for(VAR31=30; VAR31>=16; VAR31=VAR31-1)
begin
if((VAR32[VAR31]==1'b1) && (VAR32[VAR31+1]==1'b0))
begin
VAR19[0:31]=VAR19[0:31]-(VAR7<<(15-(VAR31%16)));
end
else if((VAR32[VAR31]==1'b0) && (VAR32[VAR31+1]==1'b1))
begin
VAR19[0:31]=VAR19[0:31]+(VAR7<<(15-(VAR31%16)));
end
else
begin
VAR19[0:31]=VAR19[0:31]+0;
end
end
if(VAR7[16]==1'd1)
begin
VAR6[0:31]=1+~VAR19[0:31];
end
else
begin
VAR6[0:31]=VAR19[0:31];
end
VAR12[16:31]=VAR5[32:47];
VAR12[0:15]=16'd0;
if(VAR9[32]==1'd1)
begin
VAR22[16:31]=1+~VAR9[32:47];
if(VAR5[32]==1'd1)
begin
VAR12[16:31]=1+~VAR5[32:47];
end
else
begin
VAR12[16:31]=VAR5[32:47];
end
end
else
begin
VAR22[16:31]=VAR9[0:15];
end
VAR22[0:15]=16'd0;
if(VAR12[31]==1'd1)
begin
VAR19[32:63]=VAR19[32:63] - VAR22[0:31];
end
else
begin
VAR19[32:63]=VAR19[32:63]+0;
end
for(VAR31=30; VAR31>=16; VAR31=VAR31-1)
begin
if((VAR12[VAR31]==1'b1) && (VAR12[VAR31+1]==1'b0))
begin
VAR19[32:63]=VAR19[32:63]-(VAR22<<(15-(VAR31%16)));
end
else if((VAR12[VAR31]==1'b0) && (VAR12[VAR31+1]==1'b1))
begin
VAR19[32:63]=VAR19[32:63]+(VAR22<<(15-(VAR31%16)));
end
else
begin
VAR19[32:63]=VAR19[32:63]+0;
end
end
if(VAR22[16]==1'd1)
begin
VAR6[32:63]=1+~VAR19[32:63];
end
else
begin
VAR6[32:63]=VAR19[32:63];
end
VAR23[16:31]=VAR5[64:79];
VAR23[0:15]=16'd0;
if(VAR9[64]==1'd1)
begin
VAR26[16:31]=1+~VAR9[64:79];
if(VAR5[64]==1'd1)
begin
VAR23[16:31]=1+~VAR5[64:79];
end
else
begin
VAR23[16:31]=VAR5[64:79];
end
end
else
begin
VAR26[16:31]=VAR9[64:79];
end
VAR26[0:15]=16'd0;
if(VAR23[31]==1'd1)
begin
VAR19[64:95]=VAR19[64:95] - VAR26[0:31];
end
else
begin
VAR19[64:95]=VAR19[64:95]+0;
end
for(VAR31=30; VAR31>=16; VAR31=VAR31-1)
begin
if((VAR23[VAR31]==1'b1) && (VAR23[VAR31+1]==1'b0))
begin
VAR19[64:95]=VAR19[64:95]-(VAR26<<(15-(VAR31%16)));
end
else if((VAR23[VAR31]==1'b0) && (VAR23[VAR31+1]==1'b1))
begin
VAR19[64:95]=VAR19[64:95]+(VAR26<<(15-(VAR31%16)));
end
else
begin
VAR19[64:95]=VAR19[64:95]+0;
end
end
if(VAR26[16]==1'd1)
begin
VAR6[64:95]=1+~VAR19[64:95];
end
else
begin
VAR6[64:95]=VAR19[64:95];
end
VAR30[16:31]=VAR5[96:111];
VAR30[0:15]=16'd0;
if(VAR9[96]==1'd1)
begin
VAR28[16:31]=1+~VAR9[96:111];
if(VAR5[96]==1'd1)
begin
VAR30[16:31]=1+~VAR5[96:111];
end
else
begin
VAR30[16:31]=VAR5[96:111];
end
end
else
begin
VAR28[16:31]=VAR9[96:111];
end
VAR28[0:15]=16'd0;
if(VAR30[31]==1'd1)
begin
VAR19[96:127]=VAR19[96:127] - VAR28[0:31];
end
else
begin
VAR19[96:127]=VAR19[96:127]+0;
end
for(VAR31=30; VAR31>=16; VAR31=VAR31-1)
begin
if((VAR30[VAR31]==1'b1) && (VAR30[VAR31+1]==1'b0))
begin
VAR19[96:127]=VAR19[96:127]-(VAR28<<(15-(VAR31%16)));
end
else if((VAR30[VAR31]==1'b0) && (VAR30[VAR31+1]==1'b1))
begin
VAR19[96:127]=VAR19[96:127]+(VAR28<<(15-(VAR31%16)));
end
else
begin
VAR19[96:127]=VAR19[96:127]+0;
end
end
if(VAR28[16]==1'd1)
begin
VAR6[96:127]=1+~VAR19[96:127];
end
else
begin
VAR6[96:127]=VAR19[96:127];
end
end
default: begin
VAR6=128'd0;
end
endcase
end
default:
begin
VAR6=128'd0;
end
endcase
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/fill/sky130_fd_sc_hvl__fill.behavioral.v
| 1,114 |
module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
zhangly/azpr_cpu
|
rtl/bus/rtl/bus_master_mux.v
| 2,683 |
module MODULE1 (
input wire [VAR17] VAR23, input wire VAR13, input wire VAR4, input wire [VAR2] VAR20, input wire VAR9, input wire [VAR17] VAR22, input wire VAR30, input wire VAR31, input wire [VAR2] VAR27, input wire VAR6, input wire [VAR17] VAR15, input wire VAR21, input wire VAR7, input wire [VAR2] VAR11, input wire VAR1, input wire [VAR17] VAR16, input wire VAR26, input wire VAR10, input wire [VAR2] VAR12, input wire VAR18,
output reg [VAR17] VAR19, output reg VAR29, output reg VAR5, output reg [VAR2] VAR8 );
always @(*) begin
if (VAR9 == VAR3) begin VAR19 = VAR23;
VAR29 = VAR13;
VAR5 = VAR4;
VAR8 = VAR20;
end else if (VAR6 == VAR3) begin VAR19 = VAR22;
VAR29 = VAR30;
VAR5 = VAR31;
VAR8 = VAR27;
end else if (VAR1 == VAR3) begin VAR19 = VAR15;
VAR29 = VAR21;
VAR5 = VAR7;
VAR8 = VAR11;
end else if (VAR18 == VAR3) begin VAR19 = VAR16;
VAR29 = VAR26;
VAR5 = VAR10;
VAR8 = VAR12;
end else begin VAR19 = VAR24'h0;
VAR29 = VAR28;
VAR5 = VAR25;
VAR8 = VAR14'h0;
end
end
endmodule
|
mit
|
leekeith/DEVBOX
|
Dev_Box_HW/soc_system/synthesis/submodules/soc_system_hps_0.v
| 29,816 |
module MODULE1 #(
parameter VAR71 = 2,
parameter VAR190 = 3
) (
output wire VAR66, input wire VAR86, input wire [7:0] VAR9, input wire [31:0] VAR73, input wire [3:0] VAR25, input wire [2:0] VAR174, input wire [1:0] VAR26, input wire [1:0] VAR153, input wire [3:0] VAR189, input wire [2:0] VAR180, input wire VAR58, output wire VAR92, input wire [4:0] VAR20, input wire [7:0] VAR81, input wire [63:0] VAR61, input wire [7:0] VAR157, input wire VAR3, input wire VAR127, output wire VAR105, output wire [7:0] VAR102, output wire [1:0] VAR36, output wire VAR42, input wire VAR75, input wire [7:0] VAR55, input wire [31:0] VAR109, input wire [3:0] VAR27, input wire [2:0] VAR83, input wire [1:0] VAR110, input wire [1:0] VAR84, input wire [3:0] VAR178, input wire [2:0] VAR15, input wire VAR181, output wire VAR133, input wire [4:0] VAR57, output wire [7:0] VAR37, output wire [63:0] VAR150, output wire [1:0] VAR187, output wire VAR94, output wire VAR80, input wire VAR184, input wire VAR74, output wire [11:0] VAR51, output wire [20:0] VAR65, output wire [3:0] VAR50, output wire [2:0] VAR68, output wire [1:0] VAR97, output wire [1:0] VAR129, output wire [3:0] VAR4, output wire [2:0] VAR128, output wire VAR67, input wire VAR114, output wire [11:0] VAR148, output wire [31:0] VAR139, output wire [3:0] VAR34, output wire VAR124, output wire VAR154, input wire VAR60, input wire [11:0] VAR119, input wire [1:0] VAR142, input wire VAR182, output wire VAR24, output wire [11:0] VAR99, output wire [20:0] VAR158, output wire [3:0] VAR166, output wire [2:0] VAR63, output wire [1:0] VAR146, output wire [1:0] VAR111, output wire [3:0] VAR145, output wire [2:0] VAR126, output wire VAR30, input wire VAR188, input wire [11:0] VAR96, input wire [31:0] VAR53, input wire [1:0] VAR159, input wire VAR132, input wire VAR168, output wire VAR56, input wire VAR64, output wire [11:0] VAR11, output wire [29:0] VAR43, output wire [3:0] VAR72, output wire [2:0] VAR5, output wire [1:0] VAR1, output wire [1:0] VAR33, output wire [3:0] VAR22, output wire [2:0] VAR112, output wire VAR45, input wire VAR87, output wire [11:0] VAR38, output wire [127:0] VAR18, output wire [15:0] VAR14, output wire VAR7, output wire VAR78, input wire VAR134, input wire [11:0] VAR44, input wire [1:0] VAR130, input wire VAR2, output wire VAR122, output wire [11:0] VAR131, output wire [29:0] VAR152, output wire [3:0] VAR100, output wire [2:0] VAR163, output wire [1:0] VAR125, output wire [1:0] VAR151, output wire [3:0] VAR177, output wire [2:0] VAR49, output wire VAR52, input wire VAR147, input wire [11:0] VAR173, input wire [127:0] VAR185, input wire [1:0] VAR160, input wire VAR123, input wire VAR144, output wire VAR186, input wire [31:0] VAR175, input wire [31:0] VAR115, output wire [14:0] VAR179, output wire [2:0] VAR19, output wire VAR70, output wire VAR69, output wire VAR106, output wire VAR8, output wire VAR32, output wire VAR149, output wire VAR165, output wire VAR172, inout wire [31:0] VAR28, inout wire [3:0] VAR118, inout wire [3:0] VAR101, output wire VAR135, output wire [3:0] VAR98, input wire VAR107, output wire VAR117, output wire VAR10, output wire VAR79, output wire VAR23, output wire VAR40, input wire VAR62, inout wire VAR90, output wire VAR170, input wire VAR12, output wire VAR113, input wire VAR76, input wire VAR85, input wire VAR104, input wire VAR16, inout wire VAR46, inout wire VAR47, inout wire VAR95, inout wire VAR93, output wire VAR48, output wire VAR88, inout wire VAR162, inout wire VAR167, inout wire VAR155, output wire VAR41, inout wire VAR39, inout wire VAR141, inout wire VAR77, inout wire VAR169, inout wire VAR120, inout wire VAR121, inout wire VAR143, inout wire VAR89, inout wire VAR156, inout wire VAR17, input wire VAR82, output wire VAR138, input wire VAR136, input wire VAR59, output wire VAR54, output wire VAR13, input wire VAR176, output wire VAR171, input wire VAR137, output wire VAR164, inout wire VAR108, inout wire VAR31, inout wire VAR116, inout wire VAR183, inout wire VAR21, inout wire VAR91, inout wire VAR161, inout wire VAR29, inout wire VAR103, inout wire VAR6, inout wire VAR35, inout wire VAR140 );
generate
if (VAR71 != 2)
begin
begin
|
gpl-2.0
|
m-labs/milkymist
|
cores/pfpu/rtl/pfpu_i2f.v
| 1,559 |
module MODULE1(
input VAR8,
input VAR11,
input [31:0] VAR20,
input VAR10,
output [31:0] VAR19,
output VAR14
);
reg VAR12;
reg VAR7;
reg [30:0] VAR5;
reg VAR18;
always @(posedge VAR8) begin
if(VAR11)
VAR12 <= 1'b0;
end
else
VAR12 <= VAR10;
VAR7 <= VAR20[31];
if(VAR20[31])
VAR5 <= 31'd0 - VAR20[30:0];
else
VAR5 <= VAR20[30:0];
VAR18 <= VAR20 == 32'd0;
end
wire [4:0] VAR9;
VAR15 VAR16(
.VAR3({VAR5, 1'VAR17}),
.VAR4(VAR9)
);
reg VAR6;
reg VAR13;
reg [7:0] VAR1;
reg [30:0] VAR2;
always @(posedge VAR8) begin
if(VAR11)
VAR6 <= 1'b0;
end
else
VAR6 <= VAR12;
VAR13 <= VAR7;
VAR2 <= VAR5 << VAR9;
if(VAR18)
VAR1 <= 8'd0;
else
VAR1 <= 8'd157 - {4'd0, VAR9};
end
assign VAR19 = {VAR13, VAR1, VAR2[29:7]};
assign VAR14 = VAR6;
endmodule
|
lgpl-3.0
|
superibk/orp
|
hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/sha256.v
| 3,521 |
module MODULE1 (
input clk,
input VAR13,
input [511:0] VAR21,
input [255:0] VAR32,
output [255:0] VAR44,
output reg VAR7
);
localparam VAR4 = 64;
reg [31:0] VAR5, VAR12, VAR40, VAR8, VAR1, VAR42, VAR26, VAR23;
reg [31:0] VAR6, VAR33, VAR2, VAR36, VAR16, VAR46, VAR28, VAR24;
reg [31:0] VAR34, VAR18;
reg [6:0] VAR45, VAR29;
reg VAR38;
wire [31:0] VAR19, VAR31;
assign VAR44 = { VAR5, VAR12, VAR40, VAR8, VAR1, VAR42, VAR26, VAR23 };
VAR22 VAR3(
.clk(clk),
.VAR21(VAR21),
.VAR13(VAR13),
.VAR27(VAR7),
.VAR47(VAR19)
);
VAR11 VAR48(
.VAR14(VAR45[5:0]),
.VAR37(VAR31)
);
always @(posedge clk)
begin
VAR7 <= VAR38;
VAR45 <= VAR29;
VAR5 <= VAR6;
VAR12 <= VAR33;
VAR40 <= VAR2;
VAR8 <= VAR36;
VAR1 <= VAR16;
VAR42 <= VAR46;
VAR26 <= VAR28;
VAR23 <= VAR24;
VAR34 <= VAR18;
end
always @*
begin
VAR29 = 0;
if(~VAR13 & VAR7)
VAR29 = VAR45 + 1;
end
always @*
begin : VAR20
reg [31:0] VAR30;
VAR30 = VAR26;
if(VAR45 == 0)
VAR30 = VAR17(7);
VAR18 = VAR30 + VAR31 + VAR19;
end
reg [31:0] VAR10, VAR25;
always @*
begin : VAR35
reg [31:0] VAR41, VAR9;
VAR41 = (VAR1 & VAR42) ^ (~VAR1 & VAR26);
VAR9 = {VAR1[5:0],VAR1[31:6]} ^ {VAR1[10:0],VAR1[31:11]} ^ {VAR1[24:0],VAR1[31:25]};
VAR10 = VAR9 + VAR41 + VAR34;
end
always @*
begin : VAR43
reg [31:0] VAR39, VAR15;
VAR39 = (VAR5 & (VAR12 ^ VAR40)) ^ (VAR12 & VAR40);
VAR15 = {VAR5[1:0],VAR5[31:2]} ^ {VAR5[12:0],VAR5[31:13]} ^ {VAR5[21:0],VAR5[31:22]};
VAR25 = VAR15 + VAR39;
end
always @*
begin
VAR38 = 0;
VAR6 = VAR5;
VAR33 = VAR12;
VAR2 = VAR40;
VAR36 = VAR8;
VAR16 = VAR1;
VAR46 = VAR42;
VAR28 = VAR26;
VAR24 = VAR23;
if(VAR13)
begin
VAR38 = 1;
VAR6 = VAR17(0);
VAR33 = VAR17(1);
VAR2 = VAR17(2);
VAR36 = VAR17(3);
VAR16 = VAR17(4);
VAR46 = VAR17(5);
VAR28 = VAR17(6);
VAR24 = VAR17(7);
end
else if(VAR7)
begin
if(VAR45 == VAR4 + 1)
begin
VAR6 = VAR5 + VAR17(0);
VAR33 = VAR12 + VAR17(1);
VAR2 = VAR40 + VAR17(2);
VAR36 = VAR8 + VAR17(3);
VAR16 = VAR1 + VAR17(4);
VAR46 = VAR42 + VAR17(5);
VAR28 = VAR26 + VAR17(6);
VAR24 = VAR23 + VAR17(7);
end
else if(VAR45 == 0)
begin
VAR38 = 1;
VAR6 = VAR5;
VAR33 = VAR12;
VAR2 = VAR40;
VAR36 = VAR8;
VAR16 = VAR1;
VAR46 = VAR42;
VAR28 = VAR26;
VAR24 = VAR23;
end
else
begin
VAR38 = 1;
VAR6 = VAR10 + VAR25;
VAR33 = VAR5;
VAR2 = VAR12;
VAR36 = VAR40;
VAR16 = VAR8 + VAR10;
VAR46 = VAR1;
VAR28 = VAR42;
VAR24 = VAR26;
end
end
end
endmodule
|
apache-2.0
|
yanhongwang/ColorImage
|
ToneReproduction/ToneReproduction.v
| 2,481 |
module MODULE2
(
input[ VAR2 - 1 : 0 ]VAR15,
input[ VAR2 - 1 : 0 ]VAR9,
input[ VAR2 - 1 : 0 ]VAR6,
input[ VAR2 - 1 : 0 ]VAR7,
output reg[ VAR2 - 1 : 0 ]VAR5,
output reg[ VAR2 - 1 : 0 ]VAR13,
output reg[ VAR2 - 1 : 0 ]VAR1
);
always@( VAR15 )
begin
if( VAR15 <= VAR11 )
begin
VAR5 = ( ( VAR9 * VAR12 ) + b1 );
VAR13 = ( ( VAR6 * VAR12 ) + b1 );
VAR1 = ( ( VAR7 * VAR12 ) + b1 );
end
else if( VAR11 < VAR15 && VAR15 <= VAR14)
begin
VAR5 = ( ( VAR9 * VAR16 ) + VAR8 );
VAR13 = ( ( VAR6 * VAR16 ) + VAR8 );
VAR1 = ( ( VAR7 * VAR16 ) + VAR8 );
end
else if( VAR14 < VAR15 && VAR15 <= VAR3)
begin
VAR5 = ( ( VAR9 * VAR10 ) + VAR19 );
VAR13 = ( ( VAR6 * VAR10 ) + VAR19 );
VAR1 = ( ( VAR7 * VAR10 ) + VAR19 );
end
else
begin
VAR5 = ( ( VAR9 * VAR4 ) + VAR17 );
VAR13 = ( ( VAR6 * VAR4 ) + VAR17 );
VAR1 = ( ( VAR7 * VAR4 ) + VAR17 );
end
end
endmodule
module MODULE1;
reg[ VAR2 - 1 : 0 ]VAR15;
reg[ VAR2 - 1 : 0 ]VAR9;
reg[ VAR2 - 1 : 0 ]VAR6;
reg[ VAR2 - 1 : 0 ]VAR7;
wire[ VAR2 - 1 : 0 ]VAR5;
wire[ VAR2 - 1 : 0 ]VAR13;
wire[ VAR2 - 1 : 0 ]VAR1;
MODULE2 VAR18( VAR15, VAR9, VAR6, VAR7, VAR5, VAR13, VAR1 );
begin
begin
|
mit
|
MarcoVogt/basil
|
firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v
| 3,146 |
module MODULE1 (
VAR27, VAR6, VAR16, VAR3, VAR26, VAR32, VAR29, VAR8, VAR17, VAR28
);
input wire VAR27;
input wire VAR6;
input wire [0 : 0] VAR16;
input wire [13 : 0] VAR3;
input wire [7 : 0] VAR26;
input wire [0 : 0] VAR32;
input wire [12 : 0] VAR29;
input wire [15 : 0] VAR8;
output wire [7 : 0] VAR17;
output wire [15 : 0] VAR28;
VAR1 VAR11 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[7]}),
.VAR33({VAR8[15], VAR8[7]}),
.VAR7({VAR17[7]}),
.VAR22({VAR28[15], VAR28[7]})
);
VAR1 VAR5 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[6]}),
.VAR33({VAR8[14], VAR8[6]}),
.VAR7({VAR17[6]}),
.VAR22({VAR28[14], VAR28[6]})
);
VAR1 VAR9 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[5]}),
.VAR33({VAR8[13], VAR8[5]}),
.VAR7({VAR17[5]}),
.VAR22({VAR28[13], VAR28[5]})
);
VAR1 VAR14 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[4]}),
.VAR33({VAR8[12], VAR8[4]}),
.VAR7({VAR17[4]}),
.VAR22({VAR28[12], VAR28[4]})
);
VAR1 VAR31 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[3]}),
.VAR33({VAR8[11], VAR8[3]}),
.VAR7({VAR17[3]}),
.VAR22({VAR28[11], VAR28[3]})
);
VAR1 VAR21 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[2]}),
.VAR33({VAR8[10], VAR8[2]}),
.VAR7({VAR17[2]}),
.VAR22({VAR28[10], VAR28[2]})
);
VAR1 VAR2 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[1]}),
.VAR33({VAR8[9], VAR8[1]}),
.VAR7({VAR17[1]}),
.VAR22({VAR28[9], VAR28[1]})
);
VAR1 VAR13 (
.VAR25(VAR27),
.VAR30(VAR6),
.VAR24(1'b1),
.VAR23(1'b0),
.VAR20(VAR16[0]),
.VAR12(VAR32[0]),
.VAR18(1'b1),
.VAR10(1'b0),
.VAR4(VAR3[13:0]),
.VAR19(VAR29[12:0]),
.VAR15({VAR26[0]}),
.VAR33({VAR8[8], VAR8[0]}),
.VAR7({VAR17[0]}),
.VAR22({VAR28[8], VAR28[0]})
);
endmodule
|
bsd-3-clause
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/projects/fmcjesdadc1/vc707/system_top.v
| 10,957 |
module MODULE1 (
VAR10,
VAR82,
VAR58,
VAR48,
VAR39,
VAR20,
VAR1,
VAR107,
VAR87,
VAR108,
VAR35,
VAR86,
VAR4,
VAR55,
VAR73,
VAR84,
VAR46,
VAR115,
VAR123,
VAR83,
VAR33,
VAR11,
VAR5,
VAR63,
VAR94,
VAR21,
VAR28,
VAR25,
VAR13,
VAR76,
VAR118,
VAR17,
VAR14,
VAR59,
VAR68,
VAR36,
VAR121,
VAR16,
VAR72,
VAR31,
VAR97,
VAR24,
VAR90,
VAR113,
VAR45,
VAR64,
VAR125,
VAR105,
VAR61,
VAR34);
input VAR10;
input VAR82;
input VAR58;
input VAR48;
output VAR39;
output [13:0] VAR20;
output [ 2:0] VAR1;
output VAR107;
output [ 0:0] VAR87;
output [ 0:0] VAR108;
output [ 0:0] VAR35;
output [ 0:0] VAR86;
output [ 7:0] VAR4;
inout [63:0] VAR55;
inout [ 7:0] VAR73;
inout [ 7:0] VAR84;
output [ 0:0] VAR46;
output VAR115;
output VAR123;
output VAR83;
input VAR33;
input VAR11;
output VAR5;
output VAR63;
output VAR94;
input VAR21;
input VAR28;
output VAR25;
inout VAR13;
output VAR76;
output [26:1] VAR118;
output VAR17;
output VAR14;
output VAR59;
output VAR68;
inout [15:0] VAR36;
inout [ 6:0] VAR121;
inout [20:0] VAR16;
output VAR72;
inout VAR31;
inout VAR97;
input VAR24;
input VAR90;
output VAR113;
output VAR45;
input [ 3:0] VAR64;
input [ 3:0] VAR125;
output VAR105;
output VAR61;
inout VAR34;
reg VAR112 = 'd0;
reg [63:0] VAR75 = 'd0;
reg VAR81 = 'd0;
reg [63:0] VAR8 = 'd0;
wire [63:0] VAR3;
wire [63:0] VAR100;
wire [63:0] VAR9;
wire [ 7:0] VAR79;
wire VAR61;
wire VAR62;
wire VAR27;
wire VAR54;
wire VAR26;
wire [127:0] VAR7;
wire VAR104;
wire [31:0] VAR91;
wire VAR50;
wire [31:0] VAR101;
wire VAR41;
wire [31:0] VAR56;
wire VAR47;
wire [31:0] VAR67;
wire [31:0] VAR49;
assign VAR98 = 2'b11;
assign VAR117 = 3'b000;
assign VAR72 = 1'b1;
assign VAR76 = 1'b1;
assign VAR105 = VAR79[0];
always @(posedge VAR26) begin
case ({VAR50, VAR104})
2'b11: begin
VAR112 <= 1'b1;
VAR75[63:48] <= VAR101[31:16];
VAR75[47:32] <= VAR91[31:16];
VAR75[31:16] <= VAR101[15: 0];
VAR75[15: 0] <= VAR91[15: 0];
end
2'b10: begin
VAR112 <= ~VAR112;
VAR75[63:48] <= VAR101[31:16];
VAR75[47:32] <= VAR101[15: 0];
VAR75[31:16] <= VAR75[63:48];
VAR75[15: 0] <= VAR75[47:32];
end
2'b01: begin
VAR112 <= ~VAR112;
VAR75[63:48] <= VAR91[31:16];
VAR75[47:32] <= VAR91[15: 0];
VAR75[31:16] <= VAR75[63:48];
VAR75[15: 0] <= VAR75[47:32];
end
default: begin
VAR112 <= 1'b0;
VAR75[63:48] <= 16'd0;
VAR75[47:32] <= 16'd0;
VAR75[31:16] <= 16'd0;
VAR75[15: 0] <= 16'd0;
end
endcase
end
always @(posedge VAR26) begin
case ({VAR47, VAR41})
2'b11: begin
VAR81 <= 1'b1;
VAR8[63:48] <= VAR67[31:16];
VAR8[47:32] <= VAR56[31:16];
VAR8[31:16] <= VAR67[15: 0];
VAR8[15: 0] <= VAR56[15: 0];
end
2'b10: begin
VAR81 <= ~VAR81;
VAR8[63:48] <= VAR67[31:16];
VAR8[47:32] <= VAR67[15: 0];
VAR8[31:16] <= VAR8[63:48];
VAR8[15: 0] <= VAR8[47:32];
end
2'b01: begin
VAR81 <= ~VAR81;
VAR8[63:48] <= VAR56[31:16];
VAR8[47:32] <= VAR56[15: 0];
VAR8[31:16] <= VAR8[63:48];
VAR8[15: 0] <= VAR8[47:32];
end
default: begin
VAR81 <= 1'b0;
VAR8[63:48] <= 16'd0;
VAR8[47:32] <= 16'd0;
VAR8[31:16] <= 16'd0;
VAR8[15: 0] <= 16'd0;
end
endcase
end
VAR109 VAR74 (
.VAR40 (1'd0),
.VAR12 (VAR24),
.VAR71 (VAR90),
.VAR92 (VAR54),
.VAR114 ());
VAR23 #(.VAR2(21)) VAR65 (
.VAR18 (VAR9[20:0]),
.VAR70 (VAR100[20:0]),
.VAR93 (VAR3[20:0]),
.VAR44 (VAR16));
VAR116 VAR53 (
.VAR79 (VAR105),
.VAR61 (VAR61),
.VAR62 (VAR62),
.VAR27 (VAR27),
.VAR34 (VAR34));
VAR99 VAR102 (
.VAR20 (VAR20),
.VAR1 (VAR1),
.VAR107 (VAR107),
.VAR87 (VAR87),
.VAR108 (VAR108),
.VAR35 (VAR35),
.VAR86 (VAR86),
.VAR4 (VAR4),
.VAR55 (VAR55),
.VAR73 (VAR73),
.VAR84 (VAR84),
.VAR46 (VAR46),
.VAR115 (VAR115),
.VAR123 (VAR123),
.VAR83 (VAR83),
.VAR118 (VAR118),
.VAR17 (VAR17),
.VAR14 (VAR14),
.VAR59 (VAR59),
.VAR68 (VAR68),
.VAR36(VAR36),
.VAR78 (VAR3[31:0]),
.VAR106 (VAR100[31:0]),
.VAR85 (VAR9[31:0]),
.VAR19 (VAR3[63:32]),
.VAR110 (VAR100[63:32]),
.VAR89 (VAR9[63:32]),
.VAR32 (VAR121),
.VAR91 (VAR91),
.VAR101 (VAR101),
.VAR104 (VAR104),
.VAR50 (VAR50),
.VAR22 (),
.VAR51 (),
.VAR56 (VAR56),
.VAR67 (VAR67),
.VAR41 (VAR41),
.VAR47 (VAR47),
.VAR52 (),
.VAR124 (),
.VAR26 (VAR26),
.VAR75 (VAR75),
.VAR69 (1'b1),
.VAR112 (VAR112),
.VAR8 (VAR8),
.VAR103 (1'b1),
.VAR81 (VAR81),
.VAR66 (VAR31),
.VAR77 (VAR97),
.VAR38 (1'b0),
.VAR57 (1'b0),
.VAR6 (1'b0),
.VAR122 (VAR49[14]),
.VAR60 (VAR49[15]),
.VAR25 (VAR25),
.VAR95 (VAR13),
.VAR15 (VAR28),
.VAR43 (VAR21),
.VAR94 (VAR94),
.VAR30 (1'b1),
.VAR11 (VAR11),
.VAR33 (VAR33),
.VAR63 (VAR63),
.VAR5 (VAR5),
.VAR58 (VAR58),
.VAR82 (VAR82),
.VAR10 (VAR10),
.VAR48 (VAR48),
.VAR39 (VAR39),
.VAR125 (VAR125),
.VAR64 (VAR64),
.VAR7 (VAR7),
.VAR111 (VAR7[63:0]),
.VAR42 (VAR7[127:64]),
.VAR54 (VAR54),
.VAR45 (VAR45),
.VAR113 (VAR113),
.VAR120 (1'b0),
.VAR96 (VAR61),
.VAR80 (8'hff),
.VAR119 (VAR79),
.VAR88 (VAR27),
.VAR37 (1'b0),
.VAR29 (VAR62));
endmodule
|
gpl-3.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/yf32/pc_next.v
| 3,927 |
module MODULE1 (clk, reset, VAR10, VAR8, VAR6,
VAR2, VAR5, VAR1, VAR9);
input clk;
input reset;
input [31:2] VAR10;
input VAR8;
input VAR6;
input [25:0] VAR2;
input [ 1:0] VAR5;
output [31:0] VAR1;
output [31:0] VAR9;
reg[31:2] MODULE1;
reg[31:2] VAR7;
wire [31:2] VAR4 = VAR7 + 1;
wire [31:0] VAR1 = {VAR7, 2'b00} ;
wire [31:0] VAR9 = {VAR4, 2'b00} ;
always @(posedge clk or posedge reset)
begin
if (reset)
VAR7 <= VAR3;
end
else
VAR7 <= MODULE1;
end
always @(VAR5 or VAR4 or VAR7 or VAR2 or
VAR8 or VAR10 or VAR6)
begin
case (VAR5)
default : begin
if (VAR8) MODULE1 = VAR10;
end
else MODULE1 = VAR4;
end
endcase
if (VAR6 == 1'b1)
begin
MODULE1 = VAR7;
end
end
endmodule
|
mit
|
BigEd/beeb816
|
pcb/l1b_mk2.v
| 10,871 |
module MODULE1();
supply0 VAR143;
supply1 VAR204;
wire VAR251, VAR127, VAR207, VAR268, VAR4, VAR14, VAR218, VAR182;
wire VAR65, VAR6, VAR7, VAR146, VAR106, VAR277, VAR30, VAR221;
wire VAR33, VAR290, VAR122, VAR47, VAR175, VAR203, VAR269, VAR194;
wire VAR107, VAR11, VAR187, VAR85, VAR181, VAR24, VAR266, VAR144;
wire VAR150, VAR78, VAR17, VAR285, VAR50, VAR224, VAR199, VAR282;
wire VAR38, VAR165, VAR283, VAR62, VAR206, VAR235, VAR239, VAR104, VAR101, VAR163,
VAR265, VAR156, VAR131, VAR98, VAR19, VAR167;
wire VAR66, VAR76, VAR112, VAR118, VAR191, VAR217, VAR152;
wire VAR186, VAR284, VAR135, VAR237 ;
wire VAR212, VAR195, VAR124, VAR120, VAR32;
wire VAR289;
wire VAR5;
wire VAR114, VAR37;
wire VAR102, VAR15, VAR74, VAR275, VAR116;
wire VAR280, VAR240, VAR271, VAR198, VAR67;
wire VAR145, VAR190;
wire VAR254, VAR51;
wire VAR20, VAR278;
wire VAR140;
wire VAR87;
wire VAR276;
VAR105 VAR56 (.VAR220(VAR143),.VAR178(VAR204));
VAR2 VAR238 (.VAR148(VAR143), .VAR270(VAR204));
VAR2 VAR3 (.VAR148(VAR204), .VAR270(VAR143));
VAR2 VAR121 (.VAR148(VAR143), .VAR270(VAR204));
VAR2 VAR25 (.VAR148(VAR204), .VAR270(VAR143));
VAR2 VAR147 (.VAR148(VAR143), .VAR270(VAR204));
VAR2 VAR244 (.VAR148(VAR143), .VAR270(VAR204));
VAR226 VAR73 (.VAR148(VAR143), .VAR270(VAR204));
VAR226 VAR232 (.VAR148(VAR143), .VAR270(VAR204));
VAR226 VAR95 (.VAR148(VAR143), .VAR270(VAR204));
VAR164 VAR126 ( .VAR148(VAR65), .VAR270(VAR33) );
VAR164 VAR39 ( .VAR148(VAR6), .VAR270(VAR290) );
VAR164 VAR43 ( .VAR148(VAR7), .VAR270(VAR122) );
VAR164 VAR287 ( .VAR148(VAR146), .VAR270(VAR47) );
VAR164 VAR119 ( .VAR148(VAR106), .VAR270(VAR175) );
VAR164 VAR228 ( .VAR148(VAR277), .VAR270(VAR203) );
VAR164 VAR242 ( .VAR148(VAR30), .VAR270(VAR269) );
VAR164 VAR42 ( .VAR148(VAR221), .VAR270(VAR194) );
VAR13 VAR258 (
.VAR57(VAR112),
.VAR114(VAR114),
.VAR179(VAR204),
.VAR217(VAR217),
.VAR128(),
.VAR152(VAR152),
.VAR272(VAR66),
.VAR53(VAR204),
.VAR257(VAR38),
.VAR91(VAR165),
.VAR250(VAR283),
.VAR193(VAR62),
.VAR208(VAR206),
.VAR21(VAR235),
.VAR201(VAR239),
.VAR267(VAR104),
.VAR155(VAR101),
.VAR125(VAR163),
.VAR158(VAR265),
.VAR177(VAR156),
.VAR172(VAR143),
.VAR97(VAR131),
.VAR227(VAR98),
.VAR80(VAR19),
.VAR243(VAR167),
.VAR22(VAR182),
.VAR205(VAR218),
.VAR245(VAR14),
.VAR261(VAR4),
.VAR149(VAR268),
.VAR230(VAR207),
.VAR273(VAR127),
.VAR1(VAR251),
.VAR184(VAR284),
.VAR94(VAR118),
.VAR180(VAR204),
.VAR141(VAR116),
.VAR129(),
.VAR209(VAR76),
.VAR130(VAR191)
);
VAR189 VAR225 (
.VAR270(VAR190),
.VAR148(VAR143)
);
VAR164 VAR281 (
.VAR148(VAR190),
.VAR270(VAR102)
);
VAR40 VAR252 (
.VAR148(VAR204),
.VAR270(VAR114)
);
VAR202 VAR160 (
.VAR142(VAR32), .VAR53(VAR204),
.VAR46(VAR124), .VAR243(VAR195),
.VAR80(VAR212), .VAR79(VAR120),
.VAR97(VAR98), .VAR48(VAR135),
.VAR267(VAR206), .VAR227(VAR38),
.VAR201(VAR239), .VAR155(VAR165),
.VAR21(VAR104), .VAR125(VAR283),
.VAR208(VAR101), .VAR177(VAR62),
.VAR193(VAR163), .VAR255(VAR237),
.VAR250(VAR265), .VAR158(VAR235),
.VAR91(VAR156), .VAR77(VAR289),
.VAR257(VAR131), .VAR22(VAR251),
.VAR1(VAR14), .VAR205(VAR127),
.VAR273(VAR218), .VAR245(VAR207),
.VAR230(VAR182), .VAR261(VAR268),
.VAR110(VAR143), .VAR149(VAR4)
);
VAR72 VAR12 (
.VAR161(VAR30),
.VAR171(VAR221),
.VAR92(VAR277),
.VAR23(VAR204),
.VAR103(VAR106),
.VAR192(VAR224),
.VAR28(VAR146),
.VAR29(VAR50),
.VAR246(VAR7),
.VAR159(VAR282)
.VAR270(VAR6),
.VAR96(VAR199),
.VAR197(VAR65),
.VAR200(VAR37),
.VAR253(VAR186),
.VAR75(VAR15),
.VAR117(VAR20),
.VAR229(VAR143),
.VAR215(VAR145),
.VAR49(VAR275),
.VAR213(VAR278),
.VAR236(VAR74),
.VAR27(VAR114),
.VAR136(VAR51),
.VAR264(VAR254),
.VAR54(VAR143),
.VAR113(),
.VAR71(VAR289),
.VAR173(VAR237),
.VAR137(VAR212),
.VAR138(VAR195),
.VAR176(VAR204),
.VAR133(VAR32),
.VAR259(VAR120),
.VAR9(VAR124),
.VAR262(VAR135),
.VAR174(VAR143),
.VAR240(VAR240),
.VAR198(VAR198),
.VAR271(VAR271),
.VAR185(VAR152),
.VAR68(VAR217),
.VAR34(VAR76),
.VAR82(VAR112),
.VAR70(VAR66),
.VAR90(VAR218),
.VAR170(VAR116),
.VAR233(VAR204),
.VAR231(VAR207),
.VAR223(VAR4),
.VAR18(VAR118),
.VAR52(VAR143),
.VAR166(VAR284),
.VAR26(VAR165),
.VAR214(VAR251),
.VAR31(VAR14),
.VAR234(VAR127),
.VAR139(VAR182),
.VAR183(VAR143),
.VAR111(VAR38),
.VAR89(VAR268),
.VAR93(VAR283),
.VAR16(VAR62),
.VAR108(VAR206),
.VAR8(VAR235),
.VAR196(VAR239),
.VAR63(VAR104),
.VAR35(VAR101),
.VAR280(VAR67),
.VAR188(VAR143),
.VAR58(VAR163),
.VAR60(VAR265),
.VAR81(VAR156),
.VAR222(VAR204),
.VAR219(VAR131),
.VAR36(VAR98),
.VAR216(VAR19),
.VAR247(VAR167),
.VAR10(VAR5),
.VAR123(VAR276),
.VAR279(VAR87),
.VAR211(VAR140),
.VAR100(VAR204),
.VAR274(VAR191),
);
VAR263 VAR109 (
.VAR270(VAR140),
.VAR96(VAR167),
.VAR197(VAR276),
.VAR200(VAR98),
.VAR215(VAR87),
.VAR49(VAR19),
.VAR236(VAR5),
.VAR41(VAR131),
.VAR83(VAR156),
.VAR229(VAR143),
.VAR213(VAR265),
.VAR61(VAR163),
.VAR27(VAR101),
.VAR136(VAR104),
.VAR240(VAR67),
.VAR198(VAR198),
.VAR271(VAR271),
.VAR71(VAR239),
.VAR173(VAR235),
.VAR137(VAR206),
.VAR233(VAR204),
.VAR99(VAR62),
.VAR54(VAR143),
.VAR259(VAR283),
.VAR9(VAR165),
.VAR262(VAR38),
.VAR168(VAR17),
.VAR134(VAR285),
.VAR286(VAR78),
.VAR280(VAR280),
.VAR174(VAR143),
.VAR241(VAR204),
.VAR34(VAR150),
.VAR82(VAR144),
.VAR70(VAR266),
.VAR90(VAR24),
.VAR170(VAR181),
.VAR162(VAR85),
.VAR274(VAR187),
.VAR92(VAR11),
.VAR100(VAR204),
.VAR171(VAR51),
.VAR166(VAR254),
.VAR26(VAR107),
);
VAR288 VAR249 (
.VAR153(VAR143),
.VAR59(VAR204),
.en(VAR204),
.clk(VAR275)
);
VAR64 VAR157 (
.VAR110(VAR143),
.VAR114(VAR114),
.VAR256(VAR15),
.VAR217(VAR217),
.VAR44(),
.VAR152(VAR152),
.sync(VAR37),
.VAR53(VAR204),
.VAR257(VAR107),
.VAR91(VAR11),
.VAR250(VAR187),
.VAR193(VAR85),
.VAR208(VAR181),
.VAR21(VAR24),
.VAR201(VAR266),
.VAR267(VAR144),
.VAR155(VAR150),
.VAR125(VAR78),
.VAR158(VAR17),
.VAR177(VAR285),
.VAR172(VAR143),
.VAR97(VAR50),
.VAR227(VAR224),
.VAR80(VAR199),
.VAR243(VAR282),
.VAR22(VAR194),
.VAR205(VAR269),
.VAR245(VAR203),
.VAR261(VAR175),
.VAR149(VAR47),
.VAR230(VAR122),
.VAR273(VAR290),
.VAR1(VAR33),
.VAR184(VAR186),
.VAR69(),
.VAR84(),
.VAR260(VAR102),
.VAR55(),
.VAR210(VAR74),
.VAR130(VAR191)
);
VAR154 VAR248(
.VAR270(VAR143), .VAR96(VAR143),
.VAR197(VAR20), .VAR200(VAR278),
.VAR253(VAR204), .VAR75(VAR204),
.VAR117(VAR204), .VAR41(VAR204),
.VAR83(VAR254), .VAR115(VAR51),
.VAR213(VAR143), .VAR61(VAR143),
);
VAR86 VAR45(
.VAR270(VAR145),
.VAR96(VAR143)
);
VAR151 VAR88 (
.VAR270(VAR190),
.VAR96(VAR145),
.VAR197(VAR102)
);
VAR169 VAR132 (
.VAR270(VAR143), .VAR96(VAR143),
.VAR197(VAR198), .VAR200(VAR240),
.VAR253(VAR280), .VAR75(VAR271),
.VAR117(VAR204), .VAR41(),
);
endmodule
|
lgpl-2.1
|
roberth188/EMU-Hearing-Assistance-Device
|
EMU_Basic_Project/DM_TLV5619_DAC_Interface_Module.v
| 1,786 |
module MODULE1(
VAR7,
VAR14,
VAR11,
VAR12,
VAR8,
VAR10,
VAR2,
VAR5,
VAR1,
VAR4,
VAR9
);
input VAR11, VAR12, VAR4;
input [9:0] VAR1;
input [11:0] VAR5;
input [8:0] VAR9;
output VAR14, VAR8, VAR10, VAR2;
output [11:0] VAR7;
reg [11:0] VAR7;
reg [14:0] VAR13;
wire VAR12, VAR14, VAR4;
wire [11:0] VAR5;
wire [8:0] VAR9;
reg [11:0] VAR6 [0:1023];
assign VAR14 = 0;
assign VAR8 = 0;
assign VAR10 = 1;
assign VAR2 = (~| VAR13[12:4]) && ( VAR13[3]);
assign VAR3 = VAR4;
always @(posedge VAR11)
begin
if (VAR3)
begin
VAR6 [ {!VAR1[9], VAR9} ] <= VAR5[11:0]; end
VAR7[11:0] <= VAR6[VAR1 + 4];
end
always @(posedge VAR11)
begin
if ( VAR12 ) begin
VAR13 <= 0;
end
else
begin
VAR13 <= VAR13 + 1;
end
end
endmodule
|
mit
|
osrf/wandrr
|
firmware/motor_controller/fpga/udp_inbound_chain.v
| 10,230 |
module MODULE1
(input VAR35, input [7:0] VAR106,
input VAR111,
input VAR45, input VAR33, input [7:0] VAR74,
input VAR83,
input VAR48,
output [1:0] VAR42,
output VAR104);
localparam VAR89 = 4, VAR24 = 3;
localparam VAR49 = 4'd0;
localparam VAR82 = 4'd1;
localparam VAR84 = 4'd2;
localparam VAR22 = 4'd3;
localparam VAR95 = 4'd4;
localparam VAR15 = 4'd5;
localparam VAR14 = 4'd6;
localparam VAR68 = 4'd7;
localparam VAR65 = 4'd8;
localparam VAR37 = 4'd9;
localparam VAR10 = 4'd10;
localparam VAR63 = 4'd11;
wire [23:0] VAR16;
VAR12 #(24) VAR17
(.VAR78(VAR33), .en(1'b1), .rst(VAR83),
.VAR100(VAR16+1'b1), .VAR103(VAR16));
wire VAR27 = VAR16 == 24'hffffff;
reg [VAR24+VAR89-1:0] VAR59;
wire [VAR89-1:0] state;
wire [VAR89-1:0] VAR107 = VAR59[VAR89+VAR24-1:VAR24];
VAR12 #(VAR89) VAR3
(.VAR78(VAR33), .rst(VAR27), .en(1'b1), .VAR100(VAR107), .VAR103(state));
wire VAR26 = state == VAR49;
wire [31:0] VAR98;
VAR12 #(32) VAR29
(.VAR78(VAR33), .en(VAR83), .rst(VAR26 & ~VAR83),
.VAR100({VAR98[23:0], VAR74}), .VAR103(VAR98));
wire [10:0] VAR72;
VAR12 #(11) VAR40
(.VAR78(VAR33), .en(VAR83), .rst(VAR59[0]), .VAR100(VAR72 + 1'b1), .VAR103(VAR72));
wire [15:0] VAR46;
VAR12 #(16) VAR11
(.VAR78(VAR33), .en(state == VAR22 & VAR72 == 11'h0), .rst(VAR26),
.VAR100(VAR98[15:0]), .VAR103(VAR46));
wire [7:0] VAR114;
VAR12 #(8) VAR75
(.VAR78(VAR33), .en(state == VAR22 & VAR72 == 11'ha), .rst(VAR26),
.VAR100(VAR98[7:0]), .VAR103(VAR114));
wire VAR117 = VAR46 == 16'h0800 & VAR114 == 8'h11;
wire [15:0] VAR102;
VAR12 #(16) VAR115
(.VAR78(VAR33), .en(state == VAR22 & VAR72 == 11'h18), .rst(VAR26),
.VAR100(VAR98[15:0]), .VAR103(VAR102));
wire [15:0] VAR6;
VAR12 #(16) VAR39
(.VAR78(VAR33), .en(state == VAR22 & VAR72 == 11'h1a), .rst(VAR26),
.VAR100(VAR98[15:0] - 16'd8), .VAR103(VAR6));
wire [15:0] VAR8;
VAR12 #(16) VAR64
(.VAR78(VAR33), .en(state == VAR15 & VAR72 == 11'h0), .rst(VAR26),
.VAR100(VAR98[15:0]), .VAR103(VAR8));
wire VAR97 = VAR117 & VAR102 == VAR112 & VAR8 == 16'h2143;
wire [7:0] VAR81; VAR12 #(8) VAR73
(.VAR78(VAR33), .en(state == VAR15 & VAR72 == 11'h1), .rst(VAR26),
.VAR100(VAR98[7:0] - 1'b1), .VAR103(VAR81));
wire [15:0] VAR58;
VAR12 #(16) VAR71
(.VAR78(VAR33), .en(1'b1), .rst(VAR59[1]),
.VAR100(VAR58+1'b1), .VAR103(VAR58));
wire [15:0] VAR5;
VAR12 #(16) VAR66
(.VAR78(VAR33), .en(state == VAR68 & VAR72 == 11'h1 & VAR83), .rst(VAR26),
.VAR100({VAR74, VAR98[7:0]}), .VAR103(VAR5));
wire [7:0] VAR18;
VAR12 #(8) VAR41
(.VAR78(VAR33), .en(1'b1), .rst(VAR59[0]), .VAR100(VAR18+1'b1), .VAR103(VAR18));
always @* begin
case (state)
VAR49:
if (VAR83) VAR59 = { VAR82 , 3'b000 };
end
else VAR59 = { VAR49 , 3'b011 };
VAR82:
if (VAR72 == 11'd11 & VAR83) VAR59 = { VAR84, 3'b001 };
else VAR59 = { VAR82 , 3'b000 };
VAR84:
if (VAR72 == 11'd1 & VAR83) VAR59 = { VAR22 , 3'b001 };
else VAR59 = { VAR84, 3'b000 };
VAR22:
if (VAR72 == 11'd27 & VAR83) VAR59 = { VAR95, 3'b001 };
else VAR59 = { VAR22 , 3'b000 };
VAR95:
if (VAR72 == 11'd1 & VAR83) VAR59 = { VAR15, 3'b001 };
else VAR59 = { VAR95, 3'b000 };
VAR15:
if (VAR72 == 11'd1 & VAR83) VAR59 = { VAR14 , 3'b001 };
else VAR59 = { VAR15 , 3'b000 };
VAR14:
if (VAR72 == 11'd1 & VAR83)
if ({VAR98[7:0], VAR74} == 16'hffff)
VAR59 = { VAR37, 3'b000 };
else VAR59 = { VAR68 , 3'b001 };
else VAR59 = { VAR14 , 3'b000 };
VAR68:
if (VAR72 == 11'd1 & VAR83) VAR59 = { VAR65 , 3'b001 };
else VAR59 = { VAR68 , 3'b000 };
VAR65:
if (VAR72 + 1'b1 == VAR5 & VAR83) VAR59 = { VAR14 , 3'b001 };
else VAR59 = { VAR65, 3'b000 };
VAR37:
if (VAR48) VAR59 = { VAR10 , 3'b101 };
else VAR59 = { VAR37, 3'b000 };
VAR10:
if (VAR18 == 8'd15) VAR59 = { VAR63 , 3'b100 };
else VAR59 = { VAR10 , 3'b000 };
VAR63:
if (VAR18 == 8'd33) VAR59 = { VAR49 , 3'b100 };
else VAR59 = { VAR63 , 3'b000 };
default: VAR59 = { VAR49 , 3'b000 };
endcase
end
VAR62 VAR105
(.VAR35(VAR35),
.VAR106(VAR106), .VAR111(VAR111), .VAR45(VAR45),
.VAR33(VAR33),
.VAR96(VAR74), .VAR119(VAR83), .VAR87(VAR48),
.VAR97(VAR97),
.VAR47(VAR81),
.VAR43(state == VAR37 & VAR97),
.VAR42(VAR42),
.VAR104(VAR104));
endmodule
module MODULE2();
wire VAR33;
VAR109 #(50) VAR50(VAR33);
wire VAR35;
VAR109 #(100) VAR86(VAR35);
wire [1:0] VAR30, VAR1;
wire VAR32, VAR21;
VAR7 #(.VAR55("VAR79.VAR4")) VAR53
(.VAR54(VAR33), .rst(1'b0),
.VAR113(2'b0), .VAR94(1'b0),
.VAR96(VAR30), .VAR119(VAR32));
VAR7 VAR51
(.VAR54(VAR33), .rst(1'b0),
.VAR113(VAR1), .VAR94(VAR21));
wire [7:0] VAR93;
wire VAR31, VAR110;
VAR23 VAR77 (.VAR78(VAR33),
.VAR100(VAR93), .VAR28(VAR31), .VAR88(VAR110),
.VAR36(VAR30), .VAR34(VAR32));
reg [7:0] VAR106;
reg VAR111, VAR45;
reg VAR52;
wire VAR25 = VAR52 ? VAR45 : 1'b0; wire [10:0] VAR69 = 11'd64;
wire [15:0] VAR91 = 16'd11300;
wire [31:0] VAR13 = 32'h12345678;
wire [31:0] VAR108 = 32'habcdef01;
wire [47:0] VAR80 = 48'ha4f3c1000011;
wire [47:0] VAR120 = 48'h01005e00007b;
wire [7:0] VAR70;
wire VAR9, VAR85;
wire [7:0] VAR90 = 8'h3;
VAR61 VAR101
(.VAR35(VAR35), .VAR56(VAR25), .VAR92(VAR69),
.VAR20(VAR91), .VAR76(VAR13), .VAR60(VAR108),
.VAR118(VAR80), .VAR44(VAR120), .VAR38(VAR90),
.VAR33(VAR33), .VAR113(VAR70), .VAR116(VAR9), .VAR99(VAR85));
wire [7:0] VAR57 = VAR52 ? VAR70 : VAR93;
wire VAR19 = VAR52 ? VAR9 : VAR31;
wire VAR67 = VAR52 ? VAR85 : VAR110;
MODULE1 MODULE1
(.VAR33(VAR33), .VAR35(VAR35),
.VAR74(VAR57), .VAR83(VAR19), .VAR48(VAR67),
.VAR106(VAR106), .VAR111(VAR111), .VAR45(VAR45),
.VAR42(VAR1), .VAR104(VAR21));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/nor2/sky130_fd_sc_hd__nor2_1.v
| 2,086 |
module MODULE1 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR4,
VAR8,
VAR1 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR7 ;
VAR3 VAR9 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR5,
VAR6,
VAR2
);
output VAR5;
input VAR6;
input VAR2;
supply1 VAR4;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR7 ;
VAR3 VAR9 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_016bits.v
| 1,917 |
module MODULE1 (
clk,
VAR4, VAR9, VAR5, VAR29, VAR25, VAR15, VAR2, VAR6,
sum,
);
input clk;
input [VAR23+0-1:0] VAR4, VAR9, VAR5, VAR29, VAR25, VAR15, VAR2, VAR6;
output [VAR23 :0] sum;
reg [VAR23 :0] sum;
wire [VAR23+3-1:0] VAR7;
wire [VAR23+2-1:0] VAR32, VAR3;
wire [VAR23+1-1:0] VAR12, VAR20, VAR8, VAR28;
reg [VAR23+0-1:0] VAR14, VAR27, VAR13, VAR18, VAR26, VAR30, VAR33, VAR21;
MODULE2 VAR17(VAR32, VAR3, VAR7 );
MODULE2 VAR31(VAR12, VAR20, VAR32 );
MODULE2 VAR22(VAR8, VAR28, VAR3 );
MODULE2 VAR1(VAR14, VAR27, VAR12);
MODULE2 VAR10(VAR13, VAR18, VAR20);
MODULE2 VAR11(VAR26, VAR30, VAR8);
MODULE2 VAR24(VAR33, VAR21, VAR28);
always @(posedge clk) begin
VAR14 <= VAR4;
VAR27 <= VAR9;
VAR13 <= VAR5;
VAR18 <= VAR29;
VAR26 <= VAR25;
VAR30 <= VAR15;
VAR33 <= VAR2;
VAR21 <= VAR6;
sum <= VAR7;
sum <= VAR32;
end
endmodule
module MODULE2(VAR19,VAR34,sum);
parameter VAR16 = 0;
input [VAR23+VAR16-1:0] VAR19;
input [VAR23+VAR16-1:0] VAR34;
output [VAR23+VAR16:0] sum;
assign sum = VAR19 + VAR34;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor2b/sky130_fd_sc_hdll__nor2b.behavioral.v
| 1,497 |
module MODULE1 (
VAR3 ,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR8 ;
input VAR2;
supply1 VAR7;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR10 ;
wire VAR4 ;
wire VAR12;
not VAR11 (VAR4 , VAR8 );
and VAR9 (VAR12, VAR4, VAR2 );
buf VAR6 (VAR3 , VAR12 );
endmodule
|
apache-2.0
|
bobnewgard/fcs
|
ver/uut_1_top.v
| 2,825 |
module MODULE1
(
output wire [31:0] VAR15,
output wire [31:0] VAR7,
output wire [31:0] VAR19,
output wire VAR18,
input wire [7:0] VAR3,
input wire VAR13,
input wire VAR8,
input wire VAR14,
input wire VAR17,
input wire VAR4
);
reg [31:0] VAR10;
reg VAR22;
reg [31:0] VAR16;
reg [31:0] VAR11;
reg [31:0] VAR9;
reg VAR1;
VAR5 VAR12
(
.VAR6(VAR10[31:0]),
.VAR21(VAR22),
.VAR3(VAR3[7:0]),
.VAR13(VAR13),
.VAR4(VAR4)
);
VAR20 VAR2
(
.VAR15(VAR16[31:0]),
.VAR7(VAR11[31:0]),
.VAR19(VAR9[31:0]),
.VAR18(VAR1),
.VAR3(VAR10[31:0]),
.VAR13(VAR22),
.VAR8(VAR8),
.VAR14(VAR14),
.VAR17(VAR17)
);
always @ (*) begin
VAR15[31:0] = VAR16[31:0];
VAR7[31:0] = VAR11[31:0];
VAR19[31:0] = VAR9[31:0];
VAR18 = VAR1;
end
endmodule
|
gpl-3.0
|
Fabeltranm/FPGA-Game-D1
|
HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba6/fifo.v
| 3,257 |
module MODULE1 # (parameter VAR6 = 5, VAR13 = 8)(
input reset, VAR19,
input rd, wr,
input [VAR13-1:0] din,
output [VAR13-1:0] dout,
output VAR16,
output VAR15
);
wire VAR4, VAR18;
reg VAR11, VAR2, VAR1, VAR12;
reg [VAR13-1:0] out;
always @ (posedge VAR19) VAR11 <= wr;
always @ (posedge VAR19) VAR2 <= VAR11;
assign VAR4 = ~VAR11 & VAR2;
always @ (posedge VAR19) VAR1 <= rd;
always @ (posedge VAR19) VAR12 <= VAR1;
assign VAR18 = ~VAR1 & VAR12;
reg [VAR13-1:0] VAR3[2**VAR6-1:0]; reg [VAR6-1:0] VAR23, VAR9, VAR10; reg [VAR6-1:0] VAR8, VAR7, VAR20; reg VAR17, VAR21, VAR22, VAR14;
assign VAR5 = VAR4 & ~VAR15;
always @ (posedge VAR19)
begin
if(VAR5)
VAR3[VAR23] <= din;
end
always @ (posedge VAR19)
begin
if(VAR18)
out <= VAR3[VAR8];
end
always @ (posedge VAR19 or posedge reset)
begin
if (reset)
begin
VAR23 <= 0;
VAR8 <= 0;
VAR17 <= 1'b0;
VAR21 <= 1'b1;
end
else
begin
VAR23 <= VAR9; VAR8 <= VAR7;
VAR17 <= VAR22;
VAR21 <= VAR14;
end
end
always @(*)
begin
VAR10 = VAR23 + 1; VAR20 = VAR8 + 1; VAR9 = VAR23; VAR7 = VAR8; VAR22 = VAR17; VAR14 = VAR21;
case({VAR4,VAR18})
2'b01: begin
if(~VAR16) begin
VAR7 = VAR20;
VAR22 = 1'b0;
if(VAR20 == VAR23) VAR14 = 1'b1; end
end
2'b10: begin
if(~VAR15) begin
VAR9 = VAR10;
VAR14 = 1'b0;
if(VAR10 == (2**VAR6-1)) VAR22 = 1'b1; end
end
2'b11: begin
VAR9 = VAR10;
VAR7 = VAR20;
end
endcase
end
assign VAR15 = VAR17;
assign VAR16 = VAR21;
assign dout = out;
endmodule
|
gpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/ip_pid_controller/hdl/ip_pid_controller_entity_declarations.v
| 21,340 |
module MODULE2 (din, clk, VAR55, VAR18, en, dout);
parameter VAR15= 16;
parameter VAR29= 4;
parameter VAR4= VAR61;
parameter VAR23= 8;
parameter VAR48= 2;
parameter VAR6= VAR61;
parameter VAR17 = 1;
parameter VAR8 = 0;
parameter VAR60 = VAR61;
parameter VAR45 = 0;
parameter VAR42 = 0;
parameter VAR16= VAR33;
parameter VAR39= VAR44;
input [VAR15-1:0] din;
input clk, VAR55, VAR18;
input [VAR17-1:0] en;
output [VAR23-1:0] dout;
wire [VAR23-1:0] VAR43;
wire VAR35;
assign VAR35 = VAR55 & en[0];
generate
if (VAR45 == 1)
begin:VAR2
assign VAR43 = din;
end
else
begin:VAR38
VAR40 #(VAR15,
VAR29,
VAR4,
VAR23,
VAR48,
VAR6,
VAR16,
VAR39)
VAR21 (.VAR24(din), .VAR25(VAR43));
end
endgenerate
generate
if (VAR42 > 0)
begin:VAR1
VAR34 # (VAR23, VAR42)
VAR10 (
.VAR32(VAR43),
.VAR55(VAR35),
.VAR18(VAR18),
.clk(clk),
.VAR7(dout));
end
else
begin:VAR27
assign dout = VAR43;
end
endgenerate
endmodule
module MODULE4 (
input [(32 - 1):0] VAR36,
output [(32 - 1):0] VAR14,
input clk,
input VAR55,
input VAR18);
wire signed [(32 - 1):0] VAR20;
localparam [(11 - 1):0] VAR50 = 11'b10010000000;
localparam [(11 - 1):0] VAR12 = 11'b11111111111;
localparam [(11 - 1):0] VAR5 = 11'b10010000000;
localparam signed [(32 - 1):0] VAR56 = 32'VAR31;
wire VAR30;
localparam [(11 - 1):0] VAR47 = 11'b11111111111;
localparam signed [(32 - 1):0] VAR37 = 32'VAR46;
wire VAR51;
reg signed [(32 - 1):0] VAR19;
localparam signed [(32 - 1):0] VAR22 = 32'VAR31;
localparam signed [(32 - 1):0] VAR58 = 32'VAR46;
assign VAR20 = VAR36;
assign VAR30 = VAR20 < VAR56;
assign VAR51 = VAR20 > VAR37;
always @(VAR30 or VAR51 or VAR20)
begin:VAR57
if (VAR30)
begin
VAR19 = VAR22;
end
else if (VAR51)
begin
VAR19 = VAR58;
end
else
begin
VAR19 = VAR20;
end
end
assign VAR14 = VAR19;
endmodule
module MODULE1 (
output [(8 - 1):0] VAR11,
input clk,
input VAR55,
input VAR18);
assign VAR11 = 8'b00000000;
endmodule
module MODULE3 #(parameter VAR52 = -1, VAR42 = -1, VAR53 = 0, reset = 0)
(input [VAR52-1:0] VAR49,
input VAR55, clk, en, rst,
output [VAR52-1:0] VAR9);
generate
if ((VAR42 == 0) || ((VAR53 == 0) && (reset == 0)))
begin:VAR41
VAR34 # (VAR52, VAR42)
VAR10 (
.VAR32(VAR49),
.VAR55(VAR55 & en),
.VAR18(1'b0),
.clk(clk),
.VAR7(VAR9));
end
if ((VAR42>=1) && ((VAR53) || (reset)))
begin:VAR54
VAR28 # (VAR52, VAR42)
VAR13 (
.VAR32(VAR49),
.VAR55(VAR55 & en),
.VAR18(rst),
.clk(clk),
.VAR7(VAR9));
end
endgenerate
endmodule
module MODULE5 (
input [(1 - 1):0] VAR59,
output [(1 - 1):0] VAR11,
input clk,
input VAR55,
input VAR18);
wire VAR26;
reg VAR3[0:(1 - 1)];
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
gpl-3.0
|
scarlso/LED_controller
|
Design01.cydsn/Design01.cydsn/STC_Datapath16_v1_0/STC_Datapath16_v1_0.v
| 8,534 |
module MODULE1 (
output VAR44,
output VAR39,
output VAR50,
input VAR9,
input VAR11
);
parameter VAR18 = 0;
parameter VAR60 = 0;
parameter VAR6 = 0;
parameter VAR41 = 0;
parameter VAR10 = 0;
parameter VAR35 = 0;
parameter VAR2 = 0;
parameter VAR14 = 0;
localparam VAR24 = 3'h0;
localparam VAR43 = 3'h1;
localparam VAR33 = 3'h2;
localparam VAR31 = 3'h3;
localparam VAR38 = 3'h4;
localparam VAR34 = 3'h5;
localparam VAR27 = 3'h6;
localparam VAR56 = 3'h7;
reg [2:0] VAR3;
assign VAR44 = VAR3[0];
assign VAR39 = VAR3[1];
assign VAR50 = VAR3[2];
always @ (posedge VAR9)
begin
if(VAR11 == 1'b1)
begin
VAR3 <= VAR44;
end
else
begin
case(VAR3)
VAR24:
begin
VAR3 <= VAR43;
end
VAR43:
begin
if (VAR18 == 16'h1)
begin
VAR3 <=VAR33;
end
else
begin
VAR3 <=VAR43;
end
end
VAR33:
begin
VAR3 <= VAR33;
end
VAR31:
begin
VAR3 <= VAR31;
end
VAR38:
begin
VAR3 <= VAR38;
end
VAR34:
begin
VAR3 <= VAR34;
end
VAR27:
begin
VAR3 <= VAR27;
end
VAR56:
begin
VAR3 <= VAR56;
end
endcase
end
end
VAR8 #(.VAR22(VAR18), .VAR16(VAR6), .VAR15(VAR10),
.VAR59(VAR2), .VAR5(VAR60), .VAR13(VAR41),
.VAR17(VAR35), .VAR45(VAR14),
.VAR19(
{
8'hFF, 8'h00,
8'hFF, 8'hFF,
1'h0, VAR29, VAR48,
10'h00, VAR61,VAR36,
}
), .VAR26(
{
8'hFF, 8'h00,
8'hFF, 8'hFF,
10'h00, VAR61,VAR36,
}
)) VAR53(
.reset(VAR11),
.clk(VAR9),
.VAR4(VAR3),
.VAR25(1'b0),
.VAR28(1'b0),
.VAR42(1'b0),
.VAR46(1'b0),
.VAR57(1'b0),
.VAR52(1'b0),
.VAR23(),
.VAR12(),
.VAR21(),
.VAR32(),
.VAR55(),
.VAR30(),
.VAR51(),
.VAR1(),
.VAR7(),
.VAR47(),
.VAR20(),
.VAR49(),
.VAR37(),
.VAR54(),
.VAR40(),
.VAR58()
);
endmodule
|
apache-2.0
|
tmatsuya/milkymist-ml401
|
cores/minimac/rtl/minimac_graycounter.v
| 1,187 |
module MODULE1
(output reg [VAR7-1:0] VAR4,
input wire VAR1, input wire VAR5,
input wire VAR6);
reg [VAR7-1:0] VAR2;
always @ (posedge VAR6)
if (VAR5) begin
VAR2 <= {VAR7{1'VAR3 0}} + 1; VAR4 <= {VAR7{1'VAR3 0}}; end
else if (VAR1) begin
VAR2 <= VAR2 + 1;
VAR4 <= {VAR2[VAR7-1],
VAR2[VAR7-2:0] ^ VAR2[VAR7-1:1]};
end
endmodule
|
lgpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/V2NFC100DDR/src/NPCG_Toggle_SCC_N_poe.v
| 4,312 |
module MODULE1
(
parameter VAR22 = 4
)
(
VAR8 ,
VAR1 ,
VAR18 ,
VAR7 ,
VAR20 ,
VAR9 ,
VAR5 ,
VAR17 ,
VAR10 ,
VAR14 ,
VAR15 ,
VAR19 ,
VAR11 ,
VAR21
);
input VAR8 ;
input VAR1 ;
input [5:0] VAR18 ;
input [4:0] VAR7 ;
input [4:0] VAR20 ;
input VAR9 ;
output VAR5 ;
output VAR17 ;
output VAR10 ;
input [7:0] VAR14 ;
input [7:0] VAR15 ;
output [7:0] VAR19 ;
output [2:0] VAR11 ;
output [15:0] VAR21 ;
wire VAR16 ;
localparam VAR6 = 3'b000;
localparam VAR12 = 3'b001;
localparam VAR2 = 3'b011;
reg [2:0] VAR4 ;
reg [2:0] VAR13 ;
wire VAR3;
always @ (posedge VAR8)
if (VAR1)
VAR4 <= VAR6;
else
VAR4 <= VAR13;
always @ (*)
case (VAR4)
VAR6:
VAR13 <= (VAR16)?VAR12:VAR6;
VAR12:
VAR13 <= (VAR14)?VAR2:VAR12;
VAR2:
VAR13 <= (VAR10)?VAR6:VAR2;
default:
VAR13 <= VAR6;
endcase
assign VAR16 = (VAR9 && VAR7[4:0] == 5'b00101 && VAR18[5:0] == 6'b111110);
assign VAR5 = (VAR4 == VAR6);
assign VAR3 = (VAR4 == VAR12);
assign VAR17 = VAR16;
assign VAR10 = (VAR4 == VAR2) & VAR15[0];
assign VAR19[7:0] = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, VAR3};
assign VAR11[2:0] = 3'b000;
assign VAR21[15:0] = 16'd11000;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.blackbox.v
| 1,367 |
module MODULE1 (
VAR7 ,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR3 ;
input VAR5;
supply1 VAR6;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
strigeus/fpganes
|
src/ppu.v
| 32,343 |
module MODULE1(input clk, input VAR11,
input VAR7,
input [2:0] VAR12, input [7:0] din, input read, input write, input VAR5, input [8:0] VAR2,
output [14:0] VAR6,
output [2:0] VAR1); reg VAR9; reg [14:0] VAR8;
reg [14:0] VAR3;
reg [2:0] VAR4;
reg VAR10;
|
gpl-3.0
|
lab1-ufba/Genius
|
pll_bb.v
| 12,986 |
module MODULE1 (
VAR2,
VAR4,
VAR1,
VAR3);
input VAR2;
output VAR4;
output VAR1;
output VAR3;
endmodule
|
gpl-3.0
|
hacktoberfest17/programming
|
computer_architecture/Day-4/rca.v
| 2,237 |
module MODULE2(VAR3,VAR28,VAR20,VAR8,VAR4,VAR1,VAR22,VAR24,b0,b1,VAR19,VAR9,VAR5,VAR25,VAR12,VAR27,VAR7,VAR2,VAR23,VAR18,VAR11,VAR21,VAR17,VAR6,VAR15,VAR10,VAR14,VAR16,VAR29,VAR26,VAR30,VAR13);
input VAR3,VAR28,VAR20,VAR8,VAR4,VAR1,VAR22,VAR24,b0,b1,VAR19,VAR9,VAR5,VAR25,VAR12,VAR27;
output VAR7,VAR2,VAR23,VAR18,VAR11,VAR21,VAR17,VAR6,VAR15,VAR10,VAR14,VAR16,VAR29,VAR26,VAR30,VAR13;
assign VAR15=VAR3^b0^0;
assign VAR7=(VAR3&b0)|(0&(VAR3^b0));
assign VAR10=VAR28^b1^VAR7;
assign VAR2=(VAR28&b1)|(VAR7&(VAR28^b1));
assign VAR14=VAR20^VAR19^VAR2;
assign VAR23=(VAR20&VAR19)|(VAR2&(VAR20^VAR19));
assign VAR16=VAR8^VAR9^VAR23;
assign VAR18=(VAR8&VAR9)|(VAR23&(VAR8^VAR9));
assign VAR29=VAR4^VAR5^VAR18;
assign VAR11=(VAR4&VAR5)|(VAR18&(VAR4^VAR5));
assign VAR26=VAR1^VAR25^VAR11;
assign VAR21=(VAR1&VAR25)|(VAR11&(VAR1^VAR25));
assign VAR30=VAR22^VAR12^VAR21;
assign VAR17=(VAR22&VAR12)|(VAR21&(VAR22^VAR12));
assign VAR13=VAR24^VAR27^VAR17;
assign VAR6=(VAR24&VAR27)|(VAR17&(VAR24^VAR27));
endmodule
module MODULE1(VAR3,VAR28,VAR20,VAR8,VAR4,VAR1,VAR22,VAR24,b0,b1,VAR19,VAR9,VAR5,VAR25,VAR12,VAR27,VAR7,VAR2,VAR23,VAR18,VAR11,VAR21,VAR17,VAR6,VAR15,VAR10,VAR14,VAR16,VAR29,VAR26,VAR30,VAR13);
output reg VAR3,VAR28,VAR20,VAR8,VAR4,VAR1,VAR22,VAR24,b0,b1,VAR19,VAR9,VAR5,VAR25,VAR12,VAR27;
input VAR7,VAR2,VAR23,VAR18,VAR11,VAR21,VAR17,VAR6,VAR15,VAR10,VAR14,VAR16,VAR29,VAR26,VAR30,VAR13;
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o21ba/sky130_fd_sc_hs__o21ba.behavioral.v
| 1,958 |
module MODULE1 (
VAR9 ,
VAR5 ,
VAR10 ,
VAR11,
VAR7,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR11;
input VAR7;
input VAR3;
wire VAR14 ;
wire VAR4 ;
wire VAR6;
nor VAR12 (VAR14 , VAR5, VAR10 );
nor VAR2 (VAR4 , VAR11, VAR14 );
VAR13 VAR1 (VAR6, VAR4, VAR7, VAR3);
buf VAR8 (VAR9 , VAR6 );
endmodule
|
apache-2.0
|
iamllama/EE2020
|
ee2020.srcs/sources_1/imports/new/seg_disp.v
| 2,689 |
module MODULE3(
input clk,
input[7:0] VAR7,
input[7:0] VAR5,
input[7:0] VAR6,
input[7:0] VAR12,
input VAR10,
output reg[6:0] VAR3,
output reg[3:0] VAR20,
output VAR25
);
wire[6:0] VAR14;
wire[6:0] VAR19;
wire[6:0] VAR18;
wire[6:0] VAR22;
reg[2:0] state = 0;
assign VAR25 = 1;
MODULE1 MODULE3(VAR7, VAR14);
MODULE1 MODULE2(VAR5, VAR19);
MODULE1 MODULE1(VAR6, VAR18);
MODULE1 MODULE4(VAR12, VAR22);
wire VAR23 = (VAR7 == 0);
wire VAR2 = (VAR5 == 0);
wire VAR4 = (VAR6 == 0);
always @(posedge clk) begin
case (state)
default: state <= 0;
0: begin
VAR3 <= VAR14;
VAR20 <= VAR23 ? 4'b1111 : 4'b0111;
state <= state + 1;
end
1: begin
VAR3 <= VAR19;
VAR20 <= VAR23 && VAR2 ? 4'b1111 : 4'b1011;
state <= state + 1;
end
2: begin
VAR3 <= VAR18;
VAR20 <= VAR23 && VAR2 && VAR4 ? 4'b1111 : 4'b1101;
state <= state + 1;
end
3: begin
VAR3 <= VAR22;
VAR20 <= 4'b1110;
state <= 0;
end
endcase
end
endmodule
module MODULE1(input[7:0] VAR9, output[6:0] VAR3);
assign VAR3 = (VAR9 == 0) ? 7'b1000000 :
(VAR9 == 1) ? 7'b1111001 :
(VAR9 == 2) ? 7'b0100100 :
(VAR9 == 3) ? 7'b0110000 :
(VAR9 == 4) ? 7'b0011001 :
(VAR9 == 5) ? 7'b0010010 :
(VAR9 == 6) ? 7'b0000010 :
(VAR9 == 7) ? 7'b1111000 :
(VAR9 == 8) ? 7'b0000000 :
(VAR9 == 9) ? 7'b0010000 : 7'b1000000;
endmodule
module MODULE4(input[11:0] VAR17, output[3:0] VAR13, output [3:0] VAR15, output [3:0] VAR1, output [3:0] VAR21);
assign VAR13 = (VAR17 % 10000) / 1000;
assign VAR15 = (VAR17 % 1000) / 100;
assign VAR1 = (VAR17 % 100) / 10;
assign VAR21 = VAR17 % 10;
endmodule
module MODULE2(input[17:0] VAR17, output[3:0] VAR13, output [3:0] VAR15, output [3:0] VAR1, output [3:0] VAR21);
assign VAR13 = (VAR17 % 10000) / 1000;
assign VAR15 = (VAR17 % 1000) / 100;
assign VAR1 = (VAR17 % 100) / 10;
assign VAR21 = VAR17 % 10;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.blackbox.v
| 1,311 |
module MODULE1 (
VAR3,
VAR1 ,
VAR2 ,
VAR4
);
output VAR3;
input VAR1 ;
input VAR2 ;
input VAR4 ;
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/common/altera/ad_lvds_clk.v
| 2,911 |
module MODULE1 (
VAR1,
VAR5,
clk);
parameter VAR2 = 0;
localparam VAR4 = 0;
localparam VAR3 = 1;
input VAR1;
input VAR5;
output clk;
assign clk = VAR1;
endmodule
|
gpl-3.0
|
f3zz3h/Embedded-Co-Design
|
ts7300_top_restored/ethernet/eth_clockgen.v
| 5,582 |
module MODULE1(VAR6, VAR1, VAR4, VAR2, VAR10, VAR7);
parameter VAR8=1;
input VAR6; input VAR1; input [7:0] VAR4;
output VAR7; output VAR2; output VAR10;
reg VAR7;
reg [7:0] VAR11;
wire VAR9;
wire [7:0] VAR3;
wire [7:0] VAR5;
assign VAR5[7:0] = (VAR4[7:0]<2)? 8'h02 : VAR4[7:0]; assign VAR3[7:0] = (VAR5[7:0]>>1) - 1'b1;
always @ (posedge VAR6 or posedge VAR1)
begin
if(VAR1)
VAR11[7:0] <= #VAR8 8'h1;
end
else
begin
if(VAR9)
begin
VAR11[7:0] <= #VAR8 VAR3[7:0];
end
else
VAR11[7:0] <= #VAR8 VAR11 - 8'h1;
end
end
always @ (posedge VAR6 or posedge VAR1)
begin
if(VAR1)
VAR7 <= #VAR8 1'b0;
end
else
begin
if(VAR9)
VAR7 <= #VAR8 ~VAR7;
end
end
assign VAR9 = VAR11 == 8'h0;
assign VAR2 = VAR9 & ~VAR7;
assign VAR10 = VAR9 & VAR7;
endmodule
|
gpl-2.0
|
ShepardSiegel/ocpi
|
coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/bank_common.v
| 17,377 |
module MODULE1 #
(
parameter VAR110 = 100,
parameter VAR103 = 2,
parameter VAR115 = 1,
parameter VAR9 = 4,
parameter VAR98 = 2,
parameter VAR11 = 0,
parameter VAR113 = 44,
parameter VAR46 = 2,
parameter VAR101 = 4,
parameter VAR20 = 5, parameter VAR28 = 64
)
(
VAR55, VAR35, VAR43, VAR75,
VAR39, VAR17, VAR21, VAR42, VAR85,
VAR31, VAR69, VAR41, VAR81, VAR58,
VAR14, VAR90, VAR30, VAR91,
VAR73,
clk, rst, VAR94, VAR56, VAR13, VAR12,
VAR36, VAR16, VAR45, VAR64, VAR80, VAR49,
VAR60, VAR4, VAR116, VAR48, VAR100,
VAR92, VAR71, VAR44, VAR111, VAR27,
VAR8, VAR96, VAR40
);
function integer VAR77 (input integer VAR7); begin
VAR7 = VAR7 - 1;
for (VAR77=1; VAR7>1; VAR77=VAR77+1)
VAR7 = VAR7 >> 1;
end
endfunction
localparam VAR37 = 0;
localparam VAR29 = 1;
localparam [VAR103-1:0] VAR104 = VAR37[0+:VAR103];
localparam [VAR103-1:0] VAR70 = VAR29[0+:VAR103];
input clk;
input rst;
input [VAR9-1:0] VAR94;
input VAR56;
wire VAR19 = VAR56 && |VAR94;
output reg VAR55;
always @(posedge clk) VAR55 <= VAR19;
wire VAR62;
wire VAR84 = VAR19 && ~VAR62;
output wire VAR35;
assign VAR35 = VAR84;
reg VAR23;
output wire VAR43;
assign VAR43 = VAR23;
property VAR89;
@(posedge clk) (VAR56 && ~|VAR16);
endproperty
VAR95: cover property (VAR89);
input VAR13;
reg VAR114;
wire VAR107 = VAR13 && ~VAR114;
output wire VAR75;
assign VAR75 = VAR107;
assign VAR62 = VAR107 && VAR19;
output wire VAR39;
assign VAR39 = VAR114;
input VAR12;
wire VAR1 = VAR114 || (VAR23 && VAR12);
output wire VAR17;
assign VAR17 = VAR1;
input [VAR9-1:0] VAR36;
output reg [VAR103-1:0] VAR21;
integer VAR25;
always @(VAR36) begin
VAR21 = VAR104;
for (VAR25 = 0; VAR25 < VAR9; VAR25 = VAR25 + 1)
if (VAR36[VAR25]) VAR21 = VAR21 + VAR70;
end
input [VAR9-1:0] VAR16;
output reg [VAR103-1:0] VAR42;
always @(VAR16) begin
VAR42 = VAR104;
for (VAR25 = 0; VAR25 < VAR9; VAR25 = VAR25 + 1)
if (VAR16[VAR25]) VAR42 = VAR42 + VAR70;
end
input [VAR9-1:0] VAR45;
output reg [VAR103-1:0] VAR85;
always @(VAR45) begin
VAR85 = VAR104;
for (VAR25 = 0; VAR25 < VAR9; VAR25 = VAR25 + 1)
if (VAR45[VAR25]) VAR85 = VAR85 + VAR70;
end
input [VAR9-1:0] VAR64;
output wire VAR31;
assign VAR31 = |VAR64;
input [VAR9-1:0] VAR80;
wire [VAR9-1:0] VAR15 = VAR16 & VAR80;
output reg[VAR103-1:0] VAR69;
always @(VAR15) begin
VAR69 = VAR104;
for (VAR25 = 0; VAR25 <= VAR9-1; VAR25 = VAR25 + 1)
if (VAR15[VAR25]) VAR69 = VAR25[VAR103-1:0];
end
input [VAR9-1:0] VAR49;
input [VAR9-1:0] VAR60;
input [VAR9-1:0] VAR4;
output wire [VAR9-1:0] VAR41;
output reg VAR81 = 1'b0;
input [VAR9-1:0] VAR116;
generate
if (VAR11 == 0) begin : VAR74
assign VAR41 = {VAR9{1'b0}};
end
else begin : VAR54
reg [VAR103:0] VAR106;
reg [VAR103:0] VAR86;
always @(VAR1 or VAR106 or VAR60
or rst or VAR116)
if (rst) VAR86 = VAR9;
end
else begin
VAR86 = VAR106 - VAR1;
for (VAR25 = 0; VAR25 <= VAR9-1; VAR25 = VAR25 + 1) begin
VAR86 = VAR86 + VAR60[VAR25];
end
VAR86 = VAR86 + |VAR116;
end
wire VAR5 = (VAR86 <= VAR115[0+:VAR103]);
wire VAR65 = |VAR49; VAR108 #
(.VAR112 (VAR9))
VAR63
(.VAR24 (VAR41[VAR9-1:0]),
.VAR32 (),
.VAR65 (VAR65),
.VAR82 (VAR49[VAR9-1:0]),
.clk (clk),
.rst (rst),
.req (VAR4[VAR9-1:0]),
.VAR10 (1'b0));
end
endgenerate
input [2:0] VAR48;
output reg VAR58;
VAR48[0] && ~(VAR13 && ~VAR114);
input VAR100;
output reg VAR14;
input VAR92;
reg VAR22;
output wire VAR90;
assign VAR90 = VAR22;
wire VAR18;
output wire VAR30;
assign VAR30 = VAR18;
input VAR71;
input [VAR9-1:0] VAR44;
input [VAR9-1:0] VAR111;
input VAR27;
input [VAR46:0] VAR8;
wire VAR97;
wire VAR109;
output wire VAR91;
generate begin : VAR52
assign VAR18 = ~(VAR92 || VAR22);
wire VAR105 =
~rst && ~VAR109 && (VAR22 || VAR92);
wire [VAR9-1:0] VAR87 = {VAR9{rst}} | VAR111;
wire [VAR9-1:0] VAR33 = {VAR9{VAR18}} &
(VAR44 | {VAR9{VAR71}}) & ~VAR94;
reg [VAR9-1:0] VAR61;
wire [VAR9-1:0] VAR93 =
~VAR87 & (VAR61 | VAR33);
wire VAR79 = VAR27 && ~VAR8[VAR46];
reg VAR2;
reg VAR26;
wire VAR68;
always @(posedge clk) begin
VAR2 <= VAR79;
VAR26 <= VAR2;
end
assign VAR68 = (VAR20 >= 7) ? VAR26:
VAR2;
wire VAR72 = ~VAR18 && ~|VAR93;
reg VAR38;
wire VAR53 =
VAR72 && VAR71 && ~VAR79 && ~VAR38;
always @(posedge clk) VAR38 <=
assign VAR91 = VAR38;
wire VAR51 = VAR72 && (~VAR71 || VAR68);
reg VAR57;
assign VAR97 = VAR51 && ~VAR57;
end endgenerate
input [7:0] VAR96;
input [7:0] VAR40;
reg VAR6;
output wire VAR73;
assign VAR73 = VAR6;
generate begin : VAR47
reg [VAR46:0] VAR50;
wire [7:0] VAR59 = VAR96 | VAR40;
always @(VAR59) begin
VAR50 = {VAR46{1'b0}};
for (VAR25=0; VAR25<8; VAR25=VAR25+1)
VAR50 = VAR50 + {{VAR46{1'b0}}, VAR59[VAR25]};
end
reg [VAR46:0] VAR67;
reg [VAR46:0] VAR83;
always @(VAR71 or VAR50 or rst or VAR83
or VAR97)
if (rst) VAR67 = 4'b0;
end
else begin
VAR67 = VAR83;
if (VAR97 && VAR71) VAR67 = VAR50;
if (|VAR67)
VAR67 = VAR67 - VAR29[VAR46-1:0];
end
wire VAR99 = VAR97 || |VAR83;
end endgenerate
localparam VAR34 = (VAR98 == 1) ? VAR113 : ((VAR113/2) + (VAR113%2));
localparam VAR3 = (VAR98 == 1) ? VAR28 : ((VAR28/2) + (VAR28%2));
localparam VAR66 = (VAR3 > VAR34)
? VAR77(VAR3 + 1)
: VAR77(VAR34 + 1);
localparam VAR76 = 3;
generate begin : VAR102
reg [VAR66-1:0] VAR78;
reg [VAR66-1:0] VAR88;
always @(VAR6 or VAR71
or VAR88 or rst) begin
VAR78 = VAR88;
if (rst) VAR78 = {VAR66{1'b0}};
end
else if (VAR6) VAR78 = VAR71
? VAR3
: VAR34;
end
else if (|VAR88) VAR78 =
VAR88 - VAR29[VAR66-1:0];
end
assign VAR109 = (VAR88 == VAR76[VAR66-1:0]);
end endgenerate
endmodule
|
lgpl-3.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v
| 25,198 |
module MODULE2 (
clk,
reset,
VAR144,
VAR45,
VAR67,
VAR168,
VAR50
);
parameter VAR173 = 18;
parameter VAR137 = 37;
parameter VAR95 = 19;
localparam VAR98 = 38;
input clk;
input reset;
input VAR144;
input VAR45;
input [VAR173-1:0] VAR67; output VAR168;
output [VAR173-1:0] VAR50;
localparam VAR107 = 18; localparam VAR62 = 36; localparam VAR205 = 17;
localparam VAR86 = 37;
reg [VAR173-1:0] VAR211;
reg [VAR173-1:0] VAR59;
reg [VAR173-1:0] VAR42;
reg [VAR173-1:0] VAR18;
reg [VAR173-1:0] VAR108;
reg [VAR173-1:0] VAR148;
reg [VAR173-1:0] VAR223;
reg [VAR173-1:0] VAR104;
reg [VAR173-1:0] VAR135;
reg [VAR173-1:0] VAR160;
reg [VAR173-1:0] VAR81;
reg [VAR173-1:0] VAR4;
reg [VAR173-1:0] VAR8;
reg [VAR173-1:0] VAR11;
reg [VAR173-1:0] VAR149;
reg [VAR173-1:0] VAR183;
reg [VAR173-1:0] VAR117;
reg [VAR173-1:0] VAR27;
reg [VAR173-1:0] VAR32;
always@(posedge clk) begin
VAR211 <= 18'd88;
VAR59 <= 18'd0;
VAR42 <= -18'd97;
VAR18 <= -18'd197;
VAR108 <= -18'd294;
VAR148 <= -18'd380;
VAR223 <= -18'd447;
VAR104 <= -18'd490;
VAR135 <= -18'd504;
VAR160 <= -18'd481;
VAR81 <= -18'd420;
VAR4 <= -18'd319;
VAR8 <= -18'd178;
VAR11 <= 18'd0;
VAR149 <= 18'd212;
VAR183 <= 18'd451;
VAR117 <= 18'd710;
VAR27 <= 18'd980;
VAR32 <= 18'd1252;
end
reg [VAR98-1:0] VAR198;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR198 <= 0;
end else begin
if(VAR144) begin
VAR198 <= {VAR198[VAR98-2:0], VAR45};
end else begin
VAR198 <= VAR198;
end
end
end
wire [VAR173-1:0] VAR72;
wire [VAR173-1:0] VAR74;
wire [VAR173-1:0] VAR39;
wire [VAR173-1:0] VAR215;
wire [VAR173-1:0] VAR21;
wire [VAR173-1:0] VAR132;
wire [VAR173-1:0] VAR60;
wire [VAR173-1:0] VAR29;
wire [VAR173-1:0] VAR123;
wire [VAR173-1:0] VAR17;
wire [VAR173-1:0] VAR33;
wire [VAR173-1:0] VAR184;
wire [VAR173-1:0] VAR203;
wire [VAR173-1:0] VAR58;
wire [VAR173-1:0] VAR47;
wire [VAR173-1:0] VAR106;
wire [VAR173-1:0] VAR34;
wire [VAR173-1:0] VAR164;
wire [VAR173-1:0] VAR70;
wire [VAR173-1:0] VAR194;
wire [VAR173-1:0] VAR13;
wire [VAR173-1:0] VAR63;
wire [VAR173-1:0] VAR94;
wire [VAR173-1:0] VAR179;
wire [VAR173-1:0] VAR201;
wire [VAR173-1:0] VAR7;
wire [VAR173-1:0] VAR124;
wire [VAR173-1:0] VAR210;
wire [VAR173-1:0] VAR140;
wire [VAR173-1:0] VAR48;
wire [VAR173-1:0] VAR14;
wire [VAR173-1:0] VAR216;
wire [VAR173-1:0] VAR114;
wire [VAR173-1:0] VAR113;
wire [VAR173-1:0] VAR41;
wire [VAR173-1:0] VAR26;
wire [VAR173-1:0] VAR10;
MODULE4 MODULE56(
.clk(clk), .VAR144(VAR144),
.VAR127(VAR67),
.VAR76(VAR72),
.VAR64(VAR74),
.VAR200(VAR39),
.VAR102(VAR215),
.VAR19(VAR21),
.VAR115(VAR132),
.VAR195(VAR60),
.VAR133(VAR29),
.VAR112(VAR123),
.VAR166(VAR17),
.VAR185(VAR33),
.VAR30(VAR184),
.VAR157(VAR203),
.VAR226(VAR58),
.VAR156(VAR47),
.VAR110(VAR106),
.VAR176(VAR34),
.VAR155(VAR164),
.VAR38(VAR70),
.VAR44(VAR194),
.VAR109(VAR13),
.VAR219(VAR63),
.VAR208(VAR94),
.VAR66(VAR179),
.VAR189(VAR201),
.VAR57(VAR7),
.VAR177(VAR124),
.VAR69(VAR210),
.VAR1(VAR140),
.VAR213(VAR48),
.VAR143(VAR14),
.VAR222(VAR216),
.VAR224(VAR114),
.VAR43(VAR113),
.VAR188(VAR41),
.VAR218(VAR26),
.VAR83(VAR10),
.reset(reset) );
wire [VAR173-1:0] VAR165;
wire [VAR173-1:0] VAR71;
wire [VAR173-1:0] VAR78;
wire [VAR173-1:0] VAR196;
wire [VAR173-1:0] VAR100;
wire [VAR173-1:0] VAR9;
wire [VAR173-1:0] VAR129;
wire [VAR173-1:0] VAR75;
wire [VAR173-1:0] VAR182;
wire [VAR173-1:0] VAR37;
wire [VAR173-1:0] VAR214;
wire [VAR173-1:0] VAR121;
wire [VAR173-1:0] VAR12;
wire [VAR173-1:0] VAR111;
wire [VAR173-1:0] VAR101;
wire [VAR173-1:0] VAR36;
wire [VAR173-1:0] VAR35;
wire [VAR173-1:0] VAR163;
wire [VAR173-1:0] VAR206;
MODULE1 VAR204(
.VAR145 (VAR72),
.VAR207 (VAR10),
.VAR125(VAR165)
);
MODULE1 VAR3(
.VAR145 (VAR74),
.VAR207 (VAR26),
.VAR125(VAR71)
);
MODULE1 VAR40(
.VAR145 (VAR39),
.VAR207 (VAR41),
.VAR125(VAR78)
);
MODULE1 VAR151(
.VAR145 (VAR215),
.VAR207 (VAR113),
.VAR125(VAR196)
);
MODULE1 VAR152(
.VAR145 (VAR21),
.VAR207 (VAR114),
.VAR125(VAR100)
);
MODULE1 VAR46(
.VAR145 (VAR132),
.VAR207 (VAR216),
.VAR125(VAR9)
);
MODULE1 VAR229(
.VAR145 (VAR60),
.VAR207 (VAR14),
.VAR125(VAR129)
);
MODULE1 VAR202(
.VAR145 (VAR29),
.VAR207 (VAR48),
.VAR125(VAR75)
);
MODULE1 VAR126(
.VAR145 (VAR123),
.VAR207 (VAR140),
.VAR125(VAR182)
);
MODULE1 VAR51(
.VAR145 (VAR17),
.VAR207 (VAR210),
.VAR125(VAR37)
);
MODULE1 VAR169(
.VAR145 (VAR33),
.VAR207 (VAR124),
.VAR125(VAR214)
);
MODULE1 VAR231(
.VAR145 (VAR184),
.VAR207 (VAR7),
.VAR125(VAR121)
);
MODULE1 VAR118(
.VAR145 (VAR203),
.VAR207 (VAR201),
.VAR125(VAR12)
);
MODULE1 VAR174(
.VAR145 (VAR58),
.VAR207 (VAR179),
.VAR125(VAR111)
);
MODULE1 VAR159(
.VAR145 (VAR47),
.VAR207 (VAR94),
.VAR125(VAR101)
);
MODULE1 VAR192(
.VAR145 (VAR106),
.VAR207 (VAR63),
.VAR125(VAR36)
);
MODULE1 VAR128(
.VAR145 (VAR34),
.VAR207 (VAR13),
.VAR125(VAR35)
);
MODULE1 VAR23(
.VAR145 (VAR164),
.VAR207 (VAR194),
.VAR125(VAR163)
);
MODULE5 VAR209(
.VAR145 (VAR70),
.VAR125(VAR206)
);
wire [VAR173-1:0] VAR55;
wire [VAR173-1:0] VAR52;
wire [VAR173-1:0] VAR105;
wire [VAR173-1:0] VAR91;
wire [VAR173-1:0] VAR180;
wire [VAR173-1:0] VAR178;
wire [VAR173-1:0] VAR56;
wire [VAR173-1:0] VAR65;
wire [VAR173-1:0] VAR130;
wire [VAR173-1:0] VAR68;
wire [VAR173-1:0] VAR199;
wire [VAR173-1:0] VAR136;
wire [VAR173-1:0] VAR20;
wire [VAR173-1:0] VAR90;
wire [VAR173-1:0] VAR227;
wire [VAR173-1:0] VAR25;
wire [VAR173-1:0] VAR147;
wire [VAR173-1:0] VAR193;
wire [VAR173-1:0] VAR217;
MODULE3 VAR220(
.VAR145 (VAR165),
.VAR207 (VAR211),
.VAR125(VAR55)
);
MODULE3 VAR190(
.VAR145 (VAR71),
.VAR207 (VAR59),
.VAR125(VAR52)
);
MODULE3 VAR212(
.VAR145 (VAR78),
.VAR207 (VAR42),
.VAR125(VAR105)
);
MODULE3 VAR186(
.VAR145 (VAR196),
.VAR207 (VAR18),
.VAR125(VAR91)
);
MODULE3 VAR225(
.VAR145 (VAR100),
.VAR207 (VAR108),
.VAR125(VAR180)
);
MODULE3 VAR22(
.VAR145 (VAR9),
.VAR207 (VAR148),
.VAR125(VAR178)
);
MODULE3 VAR77(
.VAR145 (VAR129),
.VAR207 (VAR223),
.VAR125(VAR56)
);
MODULE3 VAR31(
.VAR145 (VAR75),
.VAR207 (VAR104),
.VAR125(VAR65)
);
MODULE3 VAR89(
.VAR145 (VAR182),
.VAR207 (VAR135),
.VAR125(VAR130)
);
MODULE3 VAR170(
.VAR145 (VAR37),
.VAR207 (VAR160),
.VAR125(VAR68)
);
MODULE3 VAR103(
.VAR145 (VAR214),
.VAR207 (VAR81),
.VAR125(VAR199)
);
MODULE3 VAR167(
.VAR145 (VAR121),
.VAR207 (VAR4),
.VAR125(VAR136)
);
MODULE3 VAR54(
.VAR145 (VAR12),
.VAR207 (VAR8),
.VAR125(VAR20)
);
MODULE3 VAR181(
.VAR145 (VAR111),
.VAR207 (VAR11),
.VAR125(VAR90)
);
MODULE3 VAR6(
.VAR145 (VAR101),
.VAR207 (VAR149),
.VAR125(VAR227)
);
MODULE3 VAR79(
.VAR145 (VAR36),
.VAR207 (VAR183),
.VAR125(VAR25)
);
MODULE3 VAR15(
.VAR145 (VAR35),
.VAR207 (VAR117),
.VAR125(VAR147)
);
MODULE3 VAR92(
.VAR145 (VAR163),
.VAR207 (VAR27),
.VAR125(VAR193)
);
MODULE3 VAR158(
.VAR145 (VAR206),
.VAR207 (VAR32),
.VAR125(VAR217)
);
wire [VAR173-1:0] VAR88;
wire [VAR173-1:0] VAR24;
wire [VAR173-1:0] VAR73;
wire [VAR173-1:0] VAR82;
wire [VAR173-1:0] VAR171;
wire [VAR173-1:0] VAR119;
wire [VAR173-1:0] VAR150;
wire [VAR173-1:0] VAR139;
wire [VAR173-1:0] VAR122;
wire [VAR173-1:0] VAR99;
MODULE1 VAR154(
.VAR145 (VAR55),
.VAR207 (VAR52),
.VAR125(VAR88)
);
MODULE1 VAR161(
.VAR145 (VAR105),
.VAR207 (VAR91),
.VAR125(VAR24)
);
MODULE1 VAR97(
.VAR145 (VAR180),
.VAR207 (VAR178),
.VAR125(VAR73)
);
MODULE1 VAR80(
.VAR145 (VAR56),
.VAR207 (VAR65),
.VAR125(VAR82)
);
MODULE1 VAR138(
.VAR145 (VAR130),
.VAR207 (VAR68),
.VAR125(VAR171)
);
MODULE1 VAR120(
.VAR145 (VAR199),
.VAR207 (VAR136),
.VAR125(VAR119)
);
MODULE1 VAR49(
.VAR145 (VAR20),
.VAR207 (VAR90),
.VAR125(VAR150)
);
MODULE1 VAR85(
.VAR145 (VAR227),
.VAR207 (VAR25),
.VAR125(VAR139)
);
MODULE1 VAR153(
.VAR145 (VAR147),
.VAR207 (VAR193),
.VAR125(VAR122)
);
MODULE5 VAR2(
.VAR145 (VAR217),
.VAR125(VAR99)
);
wire [VAR173-1:0] VAR228;
wire [VAR173-1:0] VAR87;
wire [VAR173-1:0] VAR221;
wire [VAR173-1:0] VAR96;
wire [VAR173-1:0] VAR141;
MODULE1 VAR172(
.VAR145 (VAR88),
.VAR207 (VAR24),
.VAR125(VAR228)
);
MODULE1 VAR146(
.VAR145 (VAR73),
.VAR207 (VAR82),
.VAR125(VAR87)
);
MODULE1 VAR134(
.VAR145 (VAR171),
.VAR207 (VAR119),
.VAR125(VAR221)
);
MODULE1 VAR84(
.VAR145 (VAR150),
.VAR207 (VAR139),
.VAR125(VAR96)
);
MODULE1 VAR175(
.VAR145 (VAR122),
.VAR207 (VAR99),
.VAR125(VAR141)
);
wire [VAR173-1:0] VAR28;
wire [VAR173-1:0] VAR53;
wire [VAR173-1:0] VAR162;
MODULE1 VAR197(
.VAR145 (VAR228),
.VAR207 (VAR87),
.VAR125(VAR28)
);
MODULE1 VAR116(
.VAR145 (VAR221),
.VAR207 (VAR96),
.VAR125(VAR53)
);
MODULE5 VAR187(
.VAR145 (VAR141),
.VAR125(VAR162)
);
wire [VAR173-1:0] VAR93;
wire [VAR173-1:0] VAR131;
MODULE1 VAR191(
.VAR145 (VAR28),
.VAR207 (VAR53),
.VAR125(VAR93)
);
MODULE5 VAR142(
.VAR145 (VAR162),
.VAR125(VAR131)
);
wire [VAR173-1:0] VAR230;
MODULE1 VAR5(
.VAR145 (VAR93),
.VAR207 (VAR131),
.VAR125(VAR230)
);
reg [17:0] VAR50;
always @(posedge clk) begin
if(VAR144) begin
VAR50 <= VAR230;
end
end
assign VAR168 = VAR198[VAR98-1];
endmodule
module MODULE4 (
clk,
VAR144,
VAR127,
VAR76,
VAR64,
VAR200,
VAR102,
VAR19,
VAR115,
VAR195,
VAR133,
VAR112,
VAR166,
VAR185,
VAR30,
VAR157,
VAR226,
VAR156,
VAR110,
VAR176,
VAR155,
VAR38,
VAR44,
VAR109,
VAR219,
VAR208,
VAR66,
VAR189,
VAR57,
VAR177,
VAR69,
VAR1,
VAR213,
VAR143,
VAR222,
VAR224,
VAR43,
VAR188,
VAR218,
VAR83,
reset);
parameter VAR61 = 1;
input clk;
input VAR144;
input [VAR61-1:0] VAR127;
output [VAR61-1:0] VAR76;
output [VAR61-1:0] VAR64;
output [VAR61-1:0] VAR200;
output [VAR61-1:0] VAR102;
output [VAR61-1:0] VAR19;
output [VAR61-1:0] VAR115;
output [VAR61-1:0] VAR195;
output [VAR61-1:0] VAR133;
output [VAR61-1:0] VAR112;
output [VAR61-1:0] VAR166;
output [VAR61-1:0] VAR185;
output [VAR61-1:0] VAR30;
output [VAR61-1:0] VAR157;
output [VAR61-1:0] VAR226;
output [VAR61-1:0] VAR156;
output [VAR61-1:0] VAR110;
output [VAR61-1:0] VAR176;
output [VAR61-1:0] VAR155;
output [VAR61-1:0] VAR38;
output [VAR61-1:0] VAR44;
output [VAR61-1:0] VAR109;
output [VAR61-1:0] VAR219;
output [VAR61-1:0] VAR208;
output [VAR61-1:0] VAR66;
output [VAR61-1:0] VAR189;
output [VAR61-1:0] VAR57;
output [VAR61-1:0] VAR177;
output [VAR61-1:0] VAR69;
output [VAR61-1:0] VAR1;
output [VAR61-1:0] VAR213;
output [VAR61-1:0] VAR143;
output [VAR61-1:0] VAR222;
output [VAR61-1:0] VAR224;
output [VAR61-1:0] VAR43;
output [VAR61-1:0] VAR188;
output [VAR61-1:0] VAR218;
output [VAR61-1:0] VAR83;
reg [VAR61-1:0] VAR76;
reg [VAR61-1:0] VAR64;
reg [VAR61-1:0] VAR200;
reg [VAR61-1:0] VAR102;
reg [VAR61-1:0] VAR19;
reg [VAR61-1:0] VAR115;
reg [VAR61-1:0] VAR195;
reg [VAR61-1:0] VAR133;
reg [VAR61-1:0] VAR112;
reg [VAR61-1:0] VAR166;
reg [VAR61-1:0] VAR185;
reg [VAR61-1:0] VAR30;
reg [VAR61-1:0] VAR157;
reg [VAR61-1:0] VAR226;
reg [VAR61-1:0] VAR156;
reg [VAR61-1:0] VAR110;
reg [VAR61-1:0] VAR176;
reg [VAR61-1:0] VAR155;
reg [VAR61-1:0] VAR38;
reg [VAR61-1:0] VAR44;
reg [VAR61-1:0] VAR109;
reg [VAR61-1:0] VAR219;
reg [VAR61-1:0] VAR208;
reg [VAR61-1:0] VAR66;
reg [VAR61-1:0] VAR189;
reg [VAR61-1:0] VAR57;
reg [VAR61-1:0] VAR177;
reg [VAR61-1:0] VAR69;
reg [VAR61-1:0] VAR1;
reg [VAR61-1:0] VAR213;
reg [VAR61-1:0] VAR143;
reg [VAR61-1:0] VAR222;
reg [VAR61-1:0] VAR224;
reg [VAR61-1:0] VAR43;
reg [VAR61-1:0] VAR188;
reg [VAR61-1:0] VAR218;
reg [VAR61-1:0] VAR83;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR76 <= 0;
VAR64 <= 0;
VAR200 <= 0;
VAR102 <= 0;
VAR19 <= 0;
VAR115 <= 0;
VAR195 <= 0;
VAR133 <= 0;
VAR112 <= 0;
VAR166 <= 0;
VAR185 <= 0;
VAR30 <= 0;
VAR157 <= 0;
VAR226 <= 0;
VAR156 <= 0;
VAR110 <= 0;
VAR176 <= 0;
VAR155 <= 0;
VAR38 <= 0;
VAR44 <= 0;
VAR109 <= 0;
VAR219 <= 0;
VAR208 <= 0;
VAR66 <= 0;
VAR189 <= 0;
VAR57 <= 0;
VAR177 <= 0;
VAR69 <= 0;
VAR1 <= 0;
VAR213 <= 0;
VAR143 <= 0;
VAR222 <= 0;
VAR224 <= 0;
VAR43 <= 0;
VAR188 <= 0;
VAR218 <= 0;
VAR83 <= 0;
end else begin
if(VAR144) begin
VAR76 <= VAR127;
VAR64 <= VAR76;
VAR200 <= VAR64;
VAR102 <= VAR200;
VAR19 <= VAR102;
VAR115 <= VAR19;
VAR195 <= VAR115;
VAR133 <= VAR195;
VAR112 <= VAR133;
VAR166 <= VAR112;
VAR185 <= VAR166;
VAR30 <= VAR185;
VAR157 <= VAR30;
VAR226 <= VAR157;
VAR156 <= VAR226;
VAR110 <= VAR156;
VAR176 <= VAR110;
VAR155 <= VAR176;
VAR38 <= VAR155;
VAR44 <= VAR38;
VAR109 <= VAR44;
VAR219 <= VAR109;
VAR208 <= VAR219;
VAR66 <= VAR208;
VAR189 <= VAR66;
VAR57 <= VAR189;
VAR177 <= VAR57;
VAR69 <= VAR177;
VAR1 <= VAR69;
VAR213 <= VAR1;
VAR143 <= VAR213;
VAR222 <= VAR143;
VAR224 <= VAR222;
VAR43 <= VAR224;
VAR188 <= VAR43;
VAR218 <= VAR188;
VAR83 <= VAR218;
end end
end
endmodule
module MODULE1 (
VAR145,
VAR207,
VAR125);
input clk;
input VAR144;
input [17:0] VAR145;
input [17:0] VAR207;
output [17:0] VAR125;
assign VAR125 = VAR145 + VAR207;
endmodule
module MODULE3 (
VAR145,
VAR207,
VAR125);
input clk;
input VAR144;
input [17:0] VAR145;
input [17:0] VAR207;
output [17:0] VAR125;
assign VAR125 = VAR145 * VAR207;
endmodule
module MODULE5 (
VAR145,
VAR125);
input clk;
input VAR144;
input [17:0] VAR145;
output [17:0] VAR125;
assign VAR125 = VAR145;
endmodule
|
mit
|
MIPSfpga/schoolMIPS
|
board/de4_230/de4_230.v
| 1,576 |
module MODULE1
(
input VAR24,
output VAR3,
input VAR30,
input VAR29,
input VAR8,
input VAR15,
input VAR7,
input VAR23,
input VAR11,
output [7:0] VAR10,
input [3:0] VAR9,
input VAR16, inout VAR5,
input [7:0] VAR1, input [3:0] VAR6, output [6:0] VAR18,
output VAR26,
output [6:0] VAR12,
output VAR4
);
wire clk;
wire VAR20 = VAR30;
wire VAR2 = VAR16;
wire VAR22 = VAR1 [7] | ~VAR9[0];
wire [ 3:0 ] VAR28 = VAR1 [3:0];
wire [ 4:0 ] VAR21 = { ~VAR9[1], VAR6 };
wire [ 31:0 ] VAR17;
VAR27 VAR27
(
.VAR20 ( VAR20 ),
.VAR2 ( VAR2 ),
.VAR28 ( VAR28 ),
.VAR22 ( VAR22 ),
.clk ( clk ),
.VAR21 ( VAR21 ),
.VAR17 ( VAR17 )
);
assign VAR10[0] = clk;
assign VAR10[7:1] = VAR17[6:0];
wire [ 31:0 ] VAR19 = VAR17;
assign VAR26 = 1'b1;
assign VAR4 = 1'b1;
VAR13 VAR25 ( VAR19 [ 7: 4] , VAR12 );
VAR13 VAR14 ( VAR19 [ 3: 0] , VAR18 );
endmodule
|
mit
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_fcmp_32ns_32ns_1_1.v
| 2,372 |
module MODULE1
VAR40 = 5,
VAR5 = 1,
VAR37 = 32,
VAR15 = 32,
VAR41 = 1
)(
input wire [VAR37-1:0] VAR33,
input wire [VAR15-1:0] VAR38,
input wire [4:0] VAR31,
output wire [VAR41-1:0] dout
);
localparam [4:0]
VAR16 = 5'b00001,
VAR26 = 5'b00010,
VAR17 = 5'b00011,
VAR25 = 5'b00100,
VAR7 = 5'b00101,
VAR35 = 5'b00110,
VAR22 = 5'b01000;
localparam [7:0]
VAR34 = 8'b00010100,
VAR21 = 8'b00100100,
VAR23 = 8'b00110100,
VAR29 = 8'b00001100,
VAR2 = 8'b00011100,
VAR8 = 8'b00101100,
VAR18 = 8'b00000100;
wire VAR12;
wire [31:0] VAR3;
wire VAR14;
wire [31:0] VAR4;
wire VAR9;
reg [7:0] VAR13;
wire VAR10;
wire [7:0] VAR28;
VAR20 VAR30 (
.VAR19 ( VAR12 ),
.VAR27 ( VAR3 ),
.VAR32 ( VAR14 ),
.VAR1 ( VAR4 ),
.VAR11 ( VAR9 ),
.VAR39 ( VAR13 ),
.VAR36 ( VAR10 ),
.VAR24 ( VAR28 )
);
assign VAR12 = 1'b1;
assign VAR3 = VAR33==='VAR6 ? 'b0 : VAR33;
assign VAR14 = 1'b1;
assign VAR4 = VAR38==='VAR6 ? 'b0 : VAR38;
assign VAR9 = 1'b1;
assign dout = VAR28[0];
always @(*) begin
case (VAR31)
VAR16 : VAR13 = VAR34;
VAR26 : VAR13 = VAR21;
VAR17 : VAR13 = VAR23;
VAR25 : VAR13 = VAR29;
VAR7 : VAR13 = VAR2;
VAR35 : VAR13 = VAR8;
VAR22 : VAR13 = VAR18;
default : VAR13 = VAR34;
endcase
end
endmodule
|
gpl-3.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_xlconcat_0/system_microblaze_0_xlconcat_0_stub.v
| 1,461 |
module MODULE1(VAR2, VAR7, VAR1, VAR4, VAR3, VAR5, VAR6, dout)
;
input [0:0]VAR2;
input [0:0]VAR7;
input [0:0]VAR1;
input [0:0]VAR4;
input [0:0]VAR3;
input [0:0]VAR5;
input [0:0]VAR6;
output [6:0]dout;
endmodule
|
apache-2.0
|
vipinkmenon/scas
|
hw/fpga/source/enet_if/v6_emac_v2_2_block.v
| 21,826 |
module MODULE1 (
input VAR38,
output [27:0] VAR122,
output VAR58,
output VAR14,
output VAR76,
output [7:0] VAR44,
output VAR90,
output VAR21,
output VAR87,
input [7:0] VAR96,
output [31:0] VAR52,
output VAR128,
output VAR91,
output VAR18,
input [7:0] VAR26,
input VAR105,
input VAR9,
input VAR124,
output VAR72,
output VAR85,
output VAR31,
input VAR104,
input [15:0] VAR29,
input VAR17,
input VAR77,
output [7:0] VAR93,
output VAR50,
output VAR103,
output VAR56,
input [7:0] VAR11,
input VAR70,
input VAR8,
input VAR22,
input VAR27,
input VAR94,
input VAR15,
output VAR16,
input VAR19,
output VAR46,
output VAR114,
input VAR82,
input VAR131,
input VAR49
);
wire VAR79; reg [3:0] VAR118; reg VAR32;
wire VAR130; wire VAR55; wire [7:0] VAR60; wire VAR48; wire VAR5; wire [7:0] VAR68; wire VAR63; wire VAR89;
wire VAR54;
wire VAR101;
wire VAR20;
wire VAR84;
wire VAR100; wire VAR4;
wire [27:0] VAR113;
wire VAR64;
wire [31:0] VAR34;
wire VAR108;
wire [31:0] VAR13;
wire VAR97;
wire VAR7;
wire [31:0] VAR95;
wire VAR98;
wire VAR81;
wire [1:0] VAR73;
wire VAR109;
wire VAR121;
wire [31:0] VAR24;
wire VAR30;
wire VAR47;
wire [31:0] VAR133;
wire [1:0] VAR71;
wire VAR126;
wire VAR59;
wire VAR10;
wire VAR1;
wire [31:0] VAR23;
wire VAR45;
wire VAR80;
wire VAR62;
wire [31:0] VAR123;
wire [31:0] VAR83;
wire VAR42;
wire VAR43;
wire VAR6;
reg VAR41,VAR119;
assign VAR84 = VAR82;
assign VAR40 = VAR82;
assign VAR76 = VAR4;
assign VAR18 = VAR100;
assign VAR91 = VAR20;
assign VAR14 = VAR101;
assign VAR78 = VAR38;
always @ (posedge VAR78)
begin
if(~VAR82) begin
VAR41 <= 1'b0;
VAR119 <= 1'b0;
end
else begin
VAR41 <= 1'b0;
if (VAR119 != VAR77)
VAR41 <= 1'b1;
VAR119 <= VAR77;
end
end
VAR115 VAR125 (
.VAR65 (),
.VAR12 (VAR17),
.VAR75 (VAR32)
);
VAR2 VAR86 (
.clk (VAR17),
.enable (1'b1),
.VAR120 (!VAR82),
.VAR28 (VAR79)
);
always @(posedge VAR17)
begin
if (VAR79) begin
VAR118 <= 4'b0000;
VAR32 <= 1'b1;
end
else begin
case (VAR118)
4'b0000 : VAR118 <= 4'b0001;
4'b0001 : VAR118 <= 4'b0010;
4'b0010 : VAR118 <= 4'b0011;
4'b0011 : VAR118 <= 4'b0100;
4'b0100 : VAR118 <= 4'b0101;
4'b0101 : VAR118 <= 4'b0110;
4'b0110 : VAR118 <= 4'b0111;
4'b0111 : VAR118 <= 4'b1000;
4'b1000 : VAR118 <= 4'b1001;
4'b1001 : VAR118 <= 4'b1010;
4'b1010 : VAR118 <= 4'b1011;
4'b1011 : VAR118 <= 4'b1100;
default : VAR118 <= 4'b1100;
endcase
if (VAR118 === 4'b1100) begin
VAR32 <= 1'b0;
end
else begin
VAR32 <= 1'b1;
end
end
end
assign VAR20 = VAR38;
VAR66 VAR102(
.VAR18 (VAR100),
.VAR76 (VAR4),
.VAR110 (VAR54),
.VAR93 (VAR93),
.VAR50 (VAR50),
.VAR103 (VAR103),
.VAR56 (VAR56),
.VAR27 (VAR27),
.VAR94 (VAR94),
.VAR11 (VAR11),
.VAR70 (VAR70),
.VAR8 (VAR8),
.VAR22 (VAR22),
.VAR57 (VAR60),
.VAR3 (VAR130),
.VAR67 (VAR55),
.VAR99 (VAR20),
.VAR36 (VAR63),
.VAR129 (VAR89),
.VAR39 (VAR68),
.VAR88 (VAR48),
.VAR116 (VAR5),
.VAR74 (VAR101)
);
assign VAR122 = VAR113;
assign VAR58 = VAR64;
assign VAR52 = VAR34;
assign VAR128 = VAR108;
VAR127 VAR61(
.VAR38 (VAR38),
.VAR25 (VAR101),
.VAR35 (VAR4),
.VAR44 (VAR44),
.VAR90 (VAR90),
.VAR21 (VAR21),
.VAR87 (VAR87),
.VAR122 (VAR113),
.VAR58 (VAR64),
.VAR117 (VAR20),
.VAR107 (VAR100),
.VAR26 (VAR26),
.VAR105 (VAR105),
.VAR9 (VAR9),
.VAR124 (VAR124),
.VAR72 (VAR72),
.VAR31 (VAR31),
.VAR85 (VAR85),
.VAR96 (VAR96),
.VAR52 (VAR34),
.VAR128 (VAR108),
.VAR104 (VAR104),
.VAR29 (VAR29),
.VAR110 (VAR54),
.VAR93 (VAR60),
.VAR50 (VAR130),
.VAR103 (VAR55),
.VAR11 (VAR68),
.VAR70 (VAR48),
.VAR8 (VAR5),
.VAR46(VAR46), .VAR19(VAR19), .VAR16(VAR16), .VAR51(VAR114), .VAR10(VAR10), .VAR1(VAR1), .VAR23(VAR23), .VAR45(VAR45), .VAR80(VAR80), .VAR62(VAR62), .VAR123(VAR123), .VAR83(VAR83), .VAR42(VAR42), .VAR43(VAR43), .VAR6(VAR6),
.VAR82 (VAR84),
.VAR131 (VAR131),
.VAR49 (VAR49)
);
VAR33 #(
.VAR92 (32'h0)
) VAR106 (
.VAR78 (VAR78),
.VAR40 (VAR40),
.VAR69 (VAR119),
.VAR111 (VAR41),
.VAR13 (VAR13),
.VAR97 (VAR97),
.VAR7 (VAR7),
.VAR95 (VAR95),
.VAR98 (VAR98),
.VAR81 (VAR81),
.VAR73 (VAR73),
.VAR109 (VAR109),
.VAR121 (VAR121),
.VAR24 (VAR24),
.VAR30 (VAR30),
.VAR47 (VAR47),
.VAR133 (VAR133),
.VAR71 (VAR71),
.VAR126 (VAR126),
.VAR59 (VAR59)
);
VAR132 #(
.VAR53 (32'd0)
) VAR37 (
.VAR78 (VAR78),
.VAR112 (VAR40),
.VAR13 (VAR13),
.VAR97 (VAR97),
.VAR7 (VAR7),
.VAR95 (VAR95),
.VAR98 (VAR98),
.VAR81 (VAR81),
.VAR73 (VAR73),
.VAR109 (VAR109),
.VAR121 (VAR121),
.VAR24 (VAR24),
.VAR30 (VAR30),
.VAR47 (VAR47),
.VAR133 (VAR133),
.VAR71 (VAR71),
.VAR126 (VAR126),
.VAR59 (VAR59),
.VAR10 (VAR10),
.VAR1 (VAR1),
.VAR23 (VAR23),
.VAR45 (VAR45),
.VAR80 (VAR80),
.VAR62 (VAR62),
.VAR123 (VAR123),
.VAR83 (VAR83),
.VAR42 (VAR42),
.VAR43 (VAR43),
.VAR6 (VAR6)
);
endmodule
|
mit
|
alexforencich/xfcp
|
lib/eth/rtl/eth_axis_rx.v
| 15,360 |
module MODULE1 #
(
parameter VAR21 = 8,
parameter VAR16 = (VAR21>8),
parameter VAR25 = (VAR21/8)
)
(
input wire clk,
input wire rst,
input wire [VAR21-1:0] VAR10,
input wire [VAR25-1:0] VAR13,
input wire VAR8,
output wire VAR26,
input wire VAR11,
input wire VAR9,
output wire VAR3,
input wire VAR22,
output wire [47:0] VAR18,
output wire [47:0] VAR6,
output wire [15:0] VAR7,
output wire [VAR21-1:0] VAR20,
output wire [VAR25-1:0] VAR23,
output wire VAR1,
input wire VAR14,
output wire VAR2,
output wire VAR12,
output wire VAR15,
output wire VAR19
);
parameter VAR4 = (14+VAR25-1)/VAR25;
parameter VAR5 = VAR17(VAR4);
parameter VAR24 = 14 % VAR25;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dlrbn/sky130_fd_sc_ls__dlrbn.functional.v
| 1,942 |
module MODULE1 (
VAR5 ,
VAR13 ,
VAR12,
VAR10 ,
VAR6
);
output VAR5 ;
output VAR13 ;
input VAR12;
input VAR10 ;
input VAR6 ;
wire VAR1 ;
wire VAR4;
wire VAR11 ;
not VAR15 (VAR1 , VAR12 );
not VAR3 (VAR4, VAR6 );
VAR2 VAR9 VAR8 (VAR11 , VAR10, VAR4, VAR1);
buf VAR7 (VAR5 , VAR11 );
not VAR14 (VAR13 , VAR11 );
endmodule
|
apache-2.0
|
CospanDesign/nysa-artemis-pcie-platform
|
artemis_pcie/slave/wb_artemis_pcie_platform/rtl/ingress_buffer_manager.v
| 18,400 |
module MODULE1 #(
parameter VAR21 = 12, parameter VAR39 = 9
)(
input clk,
input rst,
input VAR52, input [1:0] VAR18, output reg VAR101, output reg [1:0] VAR59,
input VAR65, input VAR26, input VAR28, output reg VAR31, output [7:0] VAR85, output [9:0] VAR64, output [11:0] VAR48, output reg VAR46, output VAR17,
input VAR63, input [9:0] VAR33, input [7:0] VAR23, input [6:0] VAR92,
output [12:0] VAR7, output reg [1:0] VAR57, input VAR12,
output [15:0] VAR68,
output [15:0] VAR27,
output reg VAR13, output reg VAR97 );
localparam VAR66 = 4'h0;
localparam VAR38 = 4'h1;
localparam VAR44 = 4'h2;
localparam VAR81 = 4'h1;
localparam VAR19 = 4'h2;
localparam VAR99 = 4'h3;
localparam VAR96 = 4'h1;
localparam VAR67 = 4'h2;
localparam VAR62 = 2 ** VAR39;
localparam VAR93 = 2 ** VAR21;
localparam VAR34 = 2 ** (VAR21 - VAR39);
localparam VAR36 = VAR62 / 4;
localparam VAR73 = (VAR93 / VAR62) * 2;
localparam VAR22 = 0;
localparam VAR74 = (VAR73 / 2);
localparam VAR10 = (2 ** VAR74) - 1;
localparam VAR69 = VAR10 << (VAR74);
reg [3:0] VAR75;
reg [3:0] VAR14;
reg VAR56;
reg VAR100;
reg [1:0] VAR50;
reg [1:0] VAR15;
reg [3:0] VAR88;
reg [VAR73 - 1:0] VAR40;
wire [1:0] VAR25;
reg [VAR73 - 1:0] VAR6;
wire [7:0] VAR98[1:0];
wire [7:0] VAR11[1:0];
wire [VAR73 - 1:0] VAR30[1:0];
wire [1:0] VAR71;
wire [15:0] VAR84 = VAR34;
wire [15:0] VAR79 = VAR62;
wire [15:0] VAR102 = VAR93;
wire [7:0] VAR78 = VAR73;
wire [7:0] VAR32;
wire [7:0] VAR37;
wire [VAR73 - 1:0] VAR77;
wire [VAR73 - 1:0] VAR70;
reg [3:0] VAR43[0:VAR73];
reg [11:0] VAR41[0:VAR73];
wire [11:0] VAR8;
wire [11:0] VAR90;
wire [11:0] VAR20;
wire [11:0] VAR42;
wire [11:0] VAR49;
wire [11:0] VAR76;
wire [11:0] VAR86;
wire [11:0] VAR54;
wire [11:0] VAR60;
wire [11:0] VAR9;
wire [11:0] VAR29;
wire [11:0] VAR5;
wire [11:0] VAR72;
wire [11:0] VAR45;
wire [11:0] VAR35;
wire [11:0] VAR53;
wire [3:0] VAR16;
wire [3:0] VAR55;
wire [3:0] VAR80;
wire [3:0] VAR61;
wire [3:0] VAR89;
wire [3:0] VAR2;
wire [3:0] VAR83;
wire [3:0] VAR51;
wire [3:0] VAR58;
wire [3:0] VAR47;
wire [3:0] VAR3;
wire [3:0] VAR24;
wire [3:0] VAR87;
wire [3:0] VAR91;
wire [3:0] VAR95;
wire [3:0] VAR4;
assign VAR85 = VAR88;
assign VAR32 = VAR98[0];
assign VAR37 = VAR98[1];
assign VAR98[0] = VAR22;
assign VAR98[1] = VAR74;
assign VAR11[0] = VAR22 + ((VAR73 / 2) - 1);
assign VAR11[1] = VAR74 + ((VAR73 / 2) - 1);
assign VAR48 = VAR85 << VAR39;
assign VAR30[0] = VAR10;
assign VAR30[1] = VAR69;
assign VAR77 = VAR30[0];
assign VAR70 = VAR30[1];
assign VAR25[0] = ((VAR40 & VAR30[0]) == 0);
assign VAR25[1] = ((VAR40 & VAR30[1]) == 0);
assign VAR71[0] = VAR28 ? ((VAR6 & VAR30[0]) == (VAR40 & VAR30[0]) &&
((VAR40 & VAR30[0]) > 0)):
((VAR6 & VAR30[0]) == (VAR40 & VAR30[0]) &&
((VAR40 & VAR30[0]) == VAR30[0]));
assign VAR71[1] = VAR28 ? ((VAR6 & VAR30[1]) == (VAR40 & VAR30[1]) &&
((VAR40 & VAR30[1]) > 0)):
((VAR6 & VAR30[1]) == (VAR40 & VAR30[1]) &&
((VAR40 & VAR30[1]) == VAR30[1]));
assign VAR7 = (VAR23 << (VAR39 - 2)) + VAR41[VAR23][11:2];
assign VAR64 = VAR36;
assign VAR17 = (VAR40 == 0);
assign VAR16 = VAR43[0];
assign VAR55 = VAR43[1];
assign VAR80 = VAR43[2];
assign VAR61 = VAR43[3];
assign VAR89 = VAR43[4];
assign VAR2 = VAR43[5];
assign VAR83 = VAR43[6];
assign VAR51 = VAR43[7];
assign VAR58 = VAR43[8];
assign VAR47 = VAR43[9];
assign VAR3 = VAR43[10];
assign VAR24 = VAR43[11];
assign VAR87 = VAR43[12];
assign VAR91 = VAR43[13];
assign VAR95 = VAR43[14];
assign VAR4 = VAR43[15];
assign VAR8 = VAR41[0];
assign VAR90 = VAR41[1];
assign VAR20 = VAR41[2];
assign VAR42 = VAR41[3];
assign VAR49 = VAR41[4];
assign VAR76 = VAR41[5];
assign VAR86 = VAR41[6];
assign VAR54 = VAR41[7];
assign VAR60 = VAR41[8];
assign VAR9 = VAR41[9];
assign VAR29 = VAR41[10];
assign VAR5 = VAR41[11];
assign VAR72 = VAR41[12];
assign VAR45 = VAR41[13];
assign VAR35 = VAR41[14];
assign VAR53 = VAR41[15];
assign VAR68 = VAR40;
assign VAR27 = VAR6;
integer VAR94;
always @ (posedge clk) begin
VAR101 <= 0;
VAR57 <= 0;
VAR59 <= 2'b00;
VAR56 <= 0;
VAR13 <= 0;
VAR97 <= 0;
if (rst || !VAR65) begin
VAR88 <= 0;
VAR40 <= 0;
VAR46 <= 0;
VAR31 <= 0;
VAR15 <= 0;
VAR50 <= 0;
VAR75 <= VAR66;
VAR14 <= VAR66;
VAR100 <= 0;
end
else begin
case (VAR75)
VAR66: begin
VAR101 <= 1;
VAR100 <= 0; VAR75 <= VAR81;
end
VAR81: begin
if (!VAR52 && !VAR56 && (VAR15 > 0)) begin
VAR46 <= VAR50[0];
VAR50[0] <= VAR50[1];
VAR88 <= VAR98[VAR50[0]];
VAR15 <= VAR15 - 1;
VAR75 <= VAR19;
end
end
VAR19: begin
VAR31 <= 1;
if (VAR26) begin
if (VAR40[VAR88]) begin
VAR13 <= 1;
if (VAR41[VAR88] > 0) begin
VAR97 <= 1;
end
end
VAR40[VAR88] <= 1;
if (VAR88 < VAR11[VAR46]) begin
VAR88 <= VAR88 + 1;
end
else begin
VAR75 <= VAR99;
VAR31 <= 0;
end
end
end
VAR99: begin
if (VAR101) begin
VAR75 <= VAR81;
end
end
default: begin
VAR75 <= VAR66;
end
endcase
case (VAR14)
VAR66: begin
if (VAR71[0]) begin
VAR14 <= VAR96;
end
else if (VAR71[1]) begin
VAR14 <= VAR67;
end
end
VAR96: begin
VAR57[0] <= 1;
if (VAR12) begin
VAR59[0] <= 1;
VAR101 <= 1;
VAR40 <= VAR40 & ~VAR10;
VAR14 <= VAR66;
end
end
VAR67: begin
VAR57[1] <= 1;
if (VAR12) begin
VAR59[1] <= 1;
VAR101 <= 1;
VAR40 <= VAR40 & ~VAR69;
VAR14 <= VAR66;
end
end
default: begin
VAR14 <= VAR66;
end
endcase
if (VAR52 && (VAR18 > 0)) begin
VAR50[VAR15] <= VAR18[1];
VAR15 <= VAR15 + 1;
VAR56 <= 1;
end
end
end
genvar VAR1;
generate
for (VAR1 = 0; VAR1 < VAR73; VAR1 = VAR1 + 1) begin : VAR82
always @ (posedge clk) begin
VAR6[VAR1] <= 0;
if (rst || !VAR65) begin
VAR43[VAR1] <= VAR66;
VAR6[VAR1] <= 0;
VAR41[VAR1] <= 0;
end
else begin
case (VAR43[VAR1])
VAR66: begin
VAR41[VAR1] <= 0;
if (VAR40[VAR1]) begin
VAR43[VAR1] <= VAR38;
end
end
VAR38: begin
if (VAR63 && (VAR23 == VAR1)) begin
VAR41[VAR1] <= VAR41[VAR1] + {VAR33, 2'b00};
end
if (VAR41[VAR1] >= VAR62) begin
VAR43[VAR1] <= VAR44;
end
end
VAR44: begin
VAR6[VAR1] <= 1;
if (!VAR40[VAR1]) begin
VAR43[VAR1] <= VAR66;
end
end
endcase
end
end
end
endgenerate
endmodule
|
mit
|
mammenx/synesthesia_moksha
|
wxp/dgn/syn/limbus/synthesis/submodules/limbus_uart.v
| 26,742 |
module MODULE1 (
VAR30,
VAR15,
clk,
VAR92,
VAR88,
VAR97,
VAR83,
VAR101,
VAR19,
VAR40,
VAR80,
VAR2,
VAR44
)
;
output VAR40;
output VAR80;
output VAR2;
output VAR44;
input [ 9: 0] VAR30;
input VAR15;
input clk;
input VAR92;
input VAR88;
input VAR97;
input VAR83;
input [ 7: 0] VAR101;
input VAR19;
reg VAR20;
reg [ 9: 0] VAR17;
wire VAR34;
reg VAR42;
wire VAR69;
reg VAR78;
wire VAR103;
wire [ 9: 0] VAR57;
reg VAR40;
reg VAR80;
reg VAR2;
wire VAR32;
wire [ 9: 0] VAR35;
wire VAR18;
reg VAR44;
wire [ 9: 0] VAR9;
reg [ 9: 0] VAR46;
assign VAR18 = VAR19 && VAR15;
assign VAR57 = {{1 {1'b1}},
VAR101,
1'b0};
assign VAR103 = ~(|VAR35);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR42 <= 0;
end
else if (VAR92)
VAR42 <= (~VAR80) && VAR103;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR80 <= 1'b1;
end
else if (VAR92)
if (VAR18)
VAR80 <= 0;
else if (VAR42)
VAR80 <= -1;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR40 <= 0;
end
else if (VAR92)
if (VAR83)
VAR40 <= 0;
else if (~VAR80 && VAR18)
VAR40 <= -1;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR2 <= 1'b1;
end
else if (VAR92)
VAR2 <= VAR80 && VAR103;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR17 <= 0;
end
else if (VAR92)
if (VAR34 || VAR42)
VAR17 <= VAR30;
else
VAR17 <= VAR17 - 1;
end
assign VAR34 = VAR17 == 0;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR20 <= 0;
end
else if (VAR92)
VAR20 <= VAR34;
end
assign VAR69 = VAR20 &&
(~VAR103) &&
(~VAR42);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR78 <= 1;
end
else if (~VAR103)
VAR78 <= VAR32;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR44 <= 1;
end
else if (VAR92)
VAR44 <= VAR78 & ~VAR88;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR46 <= 0;
end
else if (VAR92)
VAR46 <= VAR9;
end
assign VAR9 = (VAR42)? VAR57 :
(VAR69)? {1'b0,
VAR46[9 : 1]} :
VAR46;
assign VAR35 = VAR46;
assign VAR32 = VAR46[0];
endmodule
module MODULE4 (
VAR30,
clk,
VAR92,
VAR97,
VAR73,
VAR75,
VAR29
)
;
output VAR29;
input [ 9: 0] VAR30;
input clk;
input VAR92;
input VAR97;
input VAR73;
input VAR75;
reg [ 7: 0] VAR74;
reg VAR96;
wire VAR61;
wire VAR55;
wire VAR29;
wire [ 7: 0] VAR102;
wire VAR67;
wire VAR22;
wire VAR87;
MODULE1 MODULE3
(
.VAR30 (VAR30),
.VAR15 (VAR61),
.clk (clk),
.VAR92 (VAR92),
.VAR88 (1'b0),
.VAR97 (VAR97),
.VAR83 (1'b0),
.VAR101 (VAR74),
.VAR40 (VAR22),
.VAR80 (VAR87),
.VAR2 (VAR67),
.VAR19 (1'b1),
.VAR44 (VAR29)
);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR74 <= 0;
end
else if (VAR61)
VAR74 <= VAR102;
end
assign VAR102 = 8'b0;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR96 <= 0;
end
else if (VAR92)
VAR96 <= VAR73;
end
assign VAR55 = ~(VAR73) & (VAR96);
assign VAR61 = (VAR55 || 1'b0) && 1'b0;
endmodule
module MODULE3 (
VAR30,
VAR15,
clk,
VAR92,
VAR97,
VAR5,
VAR75,
VAR83,
VAR7,
VAR60,
VAR76,
VAR73,
VAR25,
VAR28
)
;
output VAR7;
output VAR60;
output VAR76;
output VAR73;
output [ 7: 0] VAR25;
output VAR28;
input [ 9: 0] VAR30;
input VAR15;
input clk;
input VAR92;
input VAR97;
input VAR5;
input VAR75;
input VAR83;
reg VAR20;
wire [ 9: 0] VAR93;
reg [ 9: 0] VAR17;
wire VAR34;
reg VAR7;
reg VAR59;
reg VAR6;
reg VAR63;
reg VAR39;
reg VAR60;
wire VAR1;
wire [ 8: 0] VAR77;
wire VAR23;
wire VAR62;
wire VAR76;
wire [ 7: 0] VAR84;
reg VAR73;
reg [ 7: 0] VAR25;
wire VAR79;
reg VAR28;
wire VAR3;
wire VAR14;
wire VAR82;
wire [ 9: 0] VAR91;
wire VAR58;
wire VAR50;
wire VAR29;
wire VAR90;
wire VAR33;
wire VAR4;
wire [ 9: 0] VAR99;
reg [ 9: 0] VAR94;
MODULE4 MODULE1
(
.VAR30 (VAR30),
.clk (clk),
.VAR92 (VAR92),
.VAR97 (VAR97),
.VAR73 (VAR73),
.VAR75 (VAR75),
.VAR29 (VAR29)
);
VAR16 VAR41
(
.clk (clk),
.din (VAR29),
.dout (VAR33),
.VAR97 (VAR97)
);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR6 <= 0;
end
else if (VAR92)
VAR6 <= VAR33;
end
assign VAR82 = ~(VAR33) & (VAR6);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR63 <= 0;
end
else if (VAR92)
VAR63 <= VAR33;
end
assign VAR14 = (VAR33) ^ (VAR63);
assign VAR3 = VAR5 && VAR15;
assign VAR77 = VAR30[9 : 1];
assign VAR93 = (VAR14)? VAR77 :
VAR30;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR17 <= 0;
end
else if (VAR92)
if (VAR34 || VAR14)
VAR17 <= VAR93;
else
VAR17 <= VAR17 - 1;
end
assign VAR34 = VAR17 == 0;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR20 <= 0;
end
else if (VAR92)
if (VAR14)
VAR20 <= 0;
else
VAR20 <= VAR34;
end
assign VAR58 = VAR20 && VAR79;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR39 <= 0;
end
else if (VAR92)
if (~VAR79 && VAR82)
VAR39 <= 1;
else
VAR39 <= 0;
end
assign VAR79 = VAR50;
assign {VAR90,
VAR84,
VAR4} = VAR91;
assign VAR23 = ~(|VAR91);
assign VAR62 = ~VAR90 && ~VAR23;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR59 <= 0;
end
else if (VAR92)
VAR59 <= VAR79;
end
assign VAR1 = ~(VAR79) & (VAR59);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR25 <= 0;
end
else if (VAR1)
VAR25 <= VAR84;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR60 <= 0;
end
else if (VAR92)
if (VAR83)
VAR60 <= 0;
else if (VAR1 && VAR62)
VAR60 <= -1;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR7 <= 0;
end
else if (VAR92)
if (VAR83)
VAR7 <= 0;
else if (VAR1 && VAR23)
VAR7 <= -1;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR28 <= 0;
end
else if (VAR92)
if (VAR83)
VAR28 <= 0;
else if (VAR1 && VAR73)
VAR28 <= -1;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR73 <= 0;
end
else if (VAR92)
if (VAR3)
VAR73 <= 0;
else if (VAR1)
VAR73 <= -1;
end
assign VAR76 = 0;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR94 <= 0;
end
else if (VAR92)
VAR94 <= VAR99;
end
assign VAR99 = (VAR39)? {10{1'b1}} :
(VAR58)? {VAR33,
VAR94[9 : 1]} :
VAR94;
assign VAR91 = VAR94;
assign VAR50 = VAR94[0];
endmodule
module MODULE2 (
address,
VAR7,
VAR53,
clk,
VAR92,
VAR60,
VAR76,
VAR26,
VAR97,
VAR73,
VAR25,
VAR28,
VAR40,
VAR80,
VAR2,
VAR51,
VAR65,
VAR30,
VAR98,
VAR88,
irq,
VAR21,
VAR86,
VAR5,
VAR83,
VAR101,
VAR19
)
;
output [ 9: 0] VAR30;
output VAR98;
output VAR88;
output irq;
output [ 15: 0] VAR21;
output VAR86;
output VAR5;
output VAR83;
output [ 7: 0] VAR101;
output VAR19;
input [ 2: 0] address;
input VAR7;
input VAR53;
input clk;
input VAR92;
input VAR60;
input VAR76;
input VAR26;
input VAR97;
input VAR73;
input [ 7: 0] VAR25;
input VAR28;
input VAR40;
input VAR80;
input VAR2;
input VAR51;
input [ 15: 0] VAR65;
wire VAR49;
wire [ 9: 0] VAR30;
reg [ 9: 0] VAR68;
wire VAR89;
wire VAR70;
reg VAR72;
reg VAR52;
wire VAR98;
wire VAR31;
reg VAR47;
wire [ 9: 0] VAR56;
wire VAR88;
wire VAR81;
wire VAR8;
wire VAR24;
wire VAR64;
wire VAR48;
wire VAR71;
wire VAR45;
wire VAR100;
wire VAR95;
wire VAR85;
wire VAR13;
reg irq;
wire VAR27;
reg [ 15: 0] VAR21;
wire VAR86;
wire VAR5;
wire [ 15: 0] VAR54;
wire [ 12: 0] VAR38;
wire VAR83;
reg [ 7: 0] VAR101;
wire VAR19;
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR21 <= 0;
end
else if (VAR92)
VAR21 <= VAR54;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
irq <= 0;
end
else if (VAR92)
irq <= VAR27;
end
assign VAR5 = VAR53 && ~VAR26 && (address == 3'd0);
assign VAR19 = VAR53 && ~VAR51 && (address == 3'd1);
assign VAR83 = VAR53 && ~VAR51 && (address == 3'd2);
assign VAR89 = VAR53 && ~VAR51 && (address == 3'd3);
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR101 <= 0;
end
else if (VAR19)
VAR101 <= VAR65[7 : 0];
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR68 <= 0;
end
else if (VAR89)
VAR68 <= VAR65[9 : 0];
end
assign VAR30 = VAR56;
assign VAR70 = 0;
assign VAR31 = 0;
assign {VAR88,
VAR24,
VAR45,
VAR85,
VAR13,
VAR95,
VAR100,
VAR64,
VAR48,
VAR71} = VAR68;
assign VAR49 = VAR40 ||
VAR28 ||
VAR76 ||
VAR60 ||
VAR7;
assign VAR38 = {VAR8,
VAR70,
VAR31,
1'b0,
VAR49,
VAR73,
VAR80,
VAR2,
VAR40,
VAR28,
VAR7,
VAR60,
VAR76};
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR72 <= 0;
end
else if (VAR92)
VAR72 <= VAR73;
end
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR52 <= 0;
end
else if (VAR92)
VAR52 <= VAR80;
end
assign VAR98 = VAR72;
assign VAR86 = VAR52;
assign VAR8 = 1'b0;
assign VAR54 = ({16 {(address == 3'd0)}} & VAR25) |
({16 {(address == 3'd1)}} & VAR101) |
({16 {(address == 3'd2)}} & VAR38) |
({16 {(address == 3'd3)}} & VAR68);
assign VAR27 = (VAR24 && VAR49 ) ||
(VAR13 && VAR2 ) ||
(VAR95 && VAR40 ) ||
(VAR100 && VAR28 ) ||
(VAR64 && VAR7 ) ||
(VAR48 && VAR60 ) ||
(VAR71 && VAR76 ) ||
(VAR45 && VAR73 ) ||
(VAR85 && VAR80 );
always @(posedge clk or negedge VAR97)
begin
if (VAR97 == 0)
VAR47 <= 0;
end
else if (VAR92)
VAR47 <= VAR80;
end
assign VAR81 = (VAR80) & ~(VAR47);
always @(posedge clk)
begin
if (VAR81)
("%VAR10", VAR101);
end
assign VAR56 = 4;
endmodule
module MODULE5 (
address,
VAR15,
VAR53,
clk,
VAR26,
VAR97,
VAR75,
VAR51,
VAR65,
VAR98,
irq,
VAR21,
VAR86,
VAR44
)
;
output VAR98;
output irq;
output [ 15: 0] VAR21;
output VAR86;
output VAR44;
input [ 2: 0] address;
input VAR15;
input VAR53;
input clk;
input VAR26;
input VAR97;
input VAR75;
input VAR51;
input [ 15: 0] VAR65;
wire [ 9: 0] VAR30;
wire VAR7;
wire VAR92;
wire VAR98;
wire VAR88;
wire VAR60;
wire irq;
wire VAR76;
wire [ 15: 0] VAR21;
wire VAR86;
wire VAR73;
wire [ 7: 0] VAR25;
wire VAR28;
wire VAR5;
wire VAR83;
wire [ 7: 0] VAR101;
wire VAR40;
wire VAR80;
wire VAR2;
wire VAR19;
wire VAR44;
assign VAR92 = 1;
MODULE1 MODULE2
(
.VAR30 (VAR30),
.VAR15 (VAR15),
.clk (clk),
.VAR92 (VAR92),
.VAR88 (VAR88),
.VAR97 (VAR97),
.VAR83 (VAR83),
.VAR101 (VAR101),
.VAR40 (VAR40),
.VAR80 (VAR80),
.VAR2 (VAR2),
.VAR19 (VAR19),
.VAR44 (VAR44)
);
MODULE3 MODULE5
(
.VAR30 (VAR30),
.VAR15 (VAR15),
.VAR7 (VAR7),
.clk (clk),
.VAR92 (VAR92),
.VAR60 (VAR60),
.VAR76 (VAR76),
.VAR97 (VAR97),
.VAR73 (VAR73),
.VAR25 (VAR25),
.VAR28 (VAR28),
.VAR5 (VAR5),
.VAR75 (VAR75),
.VAR83 (VAR83)
);
MODULE2 MODULE4
(
.address (address),
.VAR30 (VAR30),
.VAR7 (VAR7),
.VAR53 (VAR53),
.clk (clk),
.VAR92 (VAR92),
.VAR98 (VAR98),
.VAR88 (VAR88),
.VAR60 (VAR60),
.irq (irq),
.VAR76 (VAR76),
.VAR26 (VAR26),
.VAR21 (VAR21),
.VAR86 (VAR86),
.VAR97 (VAR97),
.VAR73 (VAR73),
.VAR25 (VAR25),
.VAR28 (VAR28),
.VAR5 (VAR5),
.VAR83 (VAR83),
.VAR101 (VAR101),
.VAR40 (VAR40),
.VAR80 (VAR80),
.VAR2 (VAR2),
.VAR19 (VAR19),
.VAR51 (VAR51),
.VAR65 (VAR65)
);
endmodule
|
gpl-3.0
|
cpulabs/mist1032isa
|
src/core/execute/execute_debugger.v
| 2,567 |
module MODULE1(
input wire VAR15,
input wire VAR9,
input wire VAR4,
input wire VAR6,
input wire VAR2,
input wire VAR17,
output wire VAR16,
output wire [31:0] VAR3,
output wire VAR11,
input wire [4:0] VAR7,
input wire VAR14
);
localparam VAR5 = 2'h0;
localparam VAR13 = 2'h1;
localparam VAR8 = 2'h2;
reg [1:0] VAR12;
reg VAR1;
reg VAR10;
always@(posedge VAR15 or negedge VAR9)begin
if(!VAR9)begin
VAR12 <= VAR5;
VAR1 <= 1'b0;
VAR10 <= 1'b0;
end
else if(VAR4)begin
VAR12 <= VAR5;
VAR1 <= 1'b0;
VAR10 <= 1'b0;
end
else begin
case(VAR12)
VAR5:
begin
VAR10 <= 1'b0;
if(VAR6 && VAR2)begin
VAR12 <= VAR13;
end
else if(VAR6 && VAR17)begin
VAR12 <= VAR8;
end
end
VAR13:
begin
VAR1 <= 1'b0;
VAR10 <= 1'b1;
VAR12 <= VAR5;
end
VAR8:
begin
if(!VAR14)begin
VAR1 <= 1'b1;
VAR10 <= 1'b1;
VAR12 <= VAR5;
end
end
endcase
end
end
always@(posedge VAR15 or negedge VAR9)begin
if(!VAR9)begin
VAR12 <= VAR5;
VAR1 <= 1'b0;
VAR10 <= 1'b0;
end
else if(VAR4)begin
VAR12 <= VAR5;
VAR1 <= 1'b0;
VAR10 <= 1'b0;
end
else begin
VAR12 <= VAR12;
VAR1 <= VAR1;
VAR10 <= VAR10;
end
end
assign VAR16 = VAR10;
assign VAR3 = {27'h0, VAR7};
assign VAR16 = 32'h0;
assign VAR3 = 32'h0;
assign VAR11 = VAR1;
endmodule
|
bsd-2-clause
|
eda-globetrotter/PicenoDecoders
|
extra_credit/encoder.v
| 1,237 |
module MODULE1 (VAR2,VAR3);
output reg [14:0] VAR3;
input [10:0] VAR2;
reg [3:0] VAR1;
always @(*)
begin
VAR1[0]=VAR2[0]^VAR2[1]^VAR2[3]^VAR2[4]^VAR2[6]^VAR2[8]^VAR2[10];
VAR1[1]=((VAR2[0]^VAR2[2])^(VAR2[3]^VAR2[5]))^((VAR2[6]^VAR2[9])^VAR2[10]);
VAR1[2]=((VAR2[1]^VAR2[2])^(VAR2[3]^VAR2[7]))^((VAR2[8]^VAR2[9])^VAR2[10]);
VAR1[3]=((VAR2[4]^VAR2[5])^(VAR2[6]^VAR2[7]))^((VAR2[8]^VAR2[9])^VAR2[10]);
VAR3[2]=VAR2[0];
VAR3[4]=VAR2[1];
VAR3[5]=VAR2[2];
VAR3[6]=VAR2[3];
VAR3[8]=VAR2[4];
VAR3[9]=VAR2[5];
VAR3[10]=VAR2[6];
VAR3[11]=VAR2[7];
VAR3[12]=VAR2[8];
VAR3[13]=VAR2[9];
VAR3[14]=VAR2[10];
VAR3[0]=VAR1[0];
VAR3[1]=VAR1[1];
VAR3[3]=VAR1[2];
VAR3[7]=VAR1[3];
end
endmodule
|
mit
|
antmicro/yosys
|
techlibs/ice40/arith_map.v
| 2,172 |
module MODULE1(
module 80ice40alu (VAR11, VAR23, VAR9, VAR31, VAR10, VAR1, VAR6);
parameter VAR19 = 0;
parameter VAR14 = 0;
parameter VAR12 = 1;
parameter VAR29 = 1;
parameter VAR2 = 1;
input [VAR12-1:0] VAR11;
input [VAR29-1:0] VAR23;
output [VAR2-1:0] VAR10, VAR1;
input VAR9, VAR31;
output [VAR2-1:0] VAR6;
wire VAR8 = VAR2 <= 2;
wire [VAR2-1:0] VAR5, VAR30;
\pos #(.VAR19(VAR19), .VAR12(VAR12), .VAR2(VAR2)) VAR26 (.VAR11(VAR11), .VAR1(VAR5));
\pos #(.VAR19(VAR14), .VAR12(VAR29), .VAR2(VAR2)) VAR22 (.VAR11(VAR23), .VAR1(VAR30));
wire [VAR2-1:0] VAR4 = VAR5;
wire [VAR2-1:0] VAR18 = VAR31 ? ~VAR30 : VAR30;
wire [VAR2-1:0] VAR17 = {VAR6, VAR9};
genvar VAR25;
generate for (VAR25 = 0; VAR25 < VAR2; VAR25 = VAR25 + 1) begin:VAR21
\VAR13 #(
.VAR27(16'VAR20 0110100110010110),
.VAR24(1'b1)
) VAR28 (
.VAR11(VAR4[VAR25]),
.VAR23(VAR18[VAR25]),
.VAR9(VAR17[VAR25]),
.VAR3(1'b0),
.VAR15(1'VAR16),
.VAR6(VAR6[VAR25]),
.VAR7(VAR1[VAR25])
);
end endgenerate
assign VAR10 = VAR4 ^ VAR18;
endmodule
|
isc
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/o21ai/sky130_fd_sc_hd__o21ai_1.v
| 2,261 |
module MODULE1 (
VAR10 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR8,
VAR9,
VAR2 ,
VAR1
);
output VAR10 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR8;
input VAR9;
input VAR2 ;
input VAR1 ;
VAR5 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR10 ,
VAR6,
VAR4,
VAR7
);
output VAR10 ;
input VAR6;
input VAR4;
input VAR7;
supply1 VAR8;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR1 ;
VAR5 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
|
apache-2.0
|
vipinkmenon/fpgadriver
|
src/hw/fpga/source/pcie_if/pcie_7x_v1_8_pipe_clock.v
| 21,021 |
module MODULE1 #
(
parameter VAR8 = "VAR15", parameter VAR12 = "VAR15", parameter VAR95 = 1, parameter VAR90 = 3, parameter VAR25 = 0, parameter VAR87 = 2, parameter VAR143 = 2, parameter VAR114 = 1, parameter VAR46 = 0
)
(
input VAR121,
input VAR110,
input [VAR95-1:0] VAR122,
input VAR91,
input [VAR95-1:0] VAR39,
input VAR88,
output VAR78,
output VAR86,
output [VAR95-1:0] VAR68,
output VAR61,
output VAR109,
output VAR28,
output VAR29,
output VAR118
);
localparam VAR133 = (VAR25 == 2) ? 1 :
(VAR25 == 1) ? 1 : 1;
localparam VAR113 = (VAR25 == 2) ? 4 :
(VAR25 == 1) ? 8 : 10;
localparam VAR2 = (VAR25 == 2) ? 4 :
(VAR25 == 1) ? 8 : 10;
localparam VAR76 = 8;
localparam VAR83 = 4;
localparam VAR119 = (VAR87 == 5) ? 2 :
(VAR87 == 4) ? 4 :
(VAR87 == 3) ? 8 :
(VAR87 == 1) ? 32 : 16;
localparam VAR97 = (VAR143 == 5) ? 2 :
(VAR143 == 4) ? 4 :
(VAR143 == 3) ? 8 :
(VAR143 == 1) ? 32 : 16;
localparam VAR74 = 20;
localparam VAR34 = ((VAR12 == "VAR55") && (VAR90 != 3)) ? 1'd1 : 1'd0;
reg [VAR95-1:0] VAR127 = {VAR95{1'd0}};
reg VAR13 = 1'd0;
reg [VAR95-1:0] VAR93 = {VAR95{1'd0}};
reg VAR89 = 1'd0;
wire VAR69;
wire VAR42;
wire VAR66;
wire VAR147;
wire VAR41;
wire VAR99;
wire VAR117;
wire VAR94;
reg VAR32 = 1'd0;
wire VAR36;
wire VAR137;
wire VAR128;
wire VAR21;
wire VAR146;
genvar VAR37;
always @ (posedge VAR137)
begin
if (!VAR91)
begin
VAR127 <= {VAR95{1'd0}};
VAR13 <= 1'd0;
VAR93 <= {VAR95{1'd0}};
VAR89 <= 1'd0;
end
else
begin
VAR127 <= VAR39;
VAR13 <= VAR88;
VAR93 <= VAR127;
VAR89 <= VAR13;
end
end
generate if ((VAR12 == "VAR55") && (VAR90 != 3))
begin : VAR101
VAR77 VAR101
(
.VAR40 (VAR121),
.VAR54 (VAR69)
);
end
else
begin : VAR49
VAR77 VAR49
(
.VAR40 (VAR110),
.VAR54 (VAR69)
);
end
endgenerate
VAR139 #
(
.VAR111 ("VAR45"),
.VAR43 ("VAR15"),
.VAR35 ("VAR142"),
.VAR115 ("VAR15"),
.VAR133 (VAR133),
.VAR113 (VAR113),
.VAR85 (0.000),
.VAR67 ("VAR15"),
.VAR76 (VAR76),
.VAR44 (0.000),
.VAR112 (0.500),
.VAR51 ("VAR15"),
.VAR83 (VAR83),
.VAR23 (0.000),
.VAR116 (0.500),
.VAR20 ("VAR15"),
.VAR119 (VAR119),
.VAR150 (0.000),
.VAR131 (0.500),
.VAR1 ("VAR15"),
.VAR97 (VAR97),
.VAR24 (0.000),
.VAR48 (0.500),
.VAR134 ("VAR15"),
.VAR74 (VAR74),
.VAR59 (0.000),
.VAR138 (0.500),
.VAR19 ("VAR15"),
.VAR2 (VAR2),
.VAR71 (0.010)
)
VAR70
(
.VAR60 (VAR69),
.VAR79 (1'd1),
.VAR108 (VAR42),
.VAR82 (!VAR91),
.VAR72 (1'd0),
.VAR31 (VAR42),
.VAR130 (),
.VAR3 (VAR66),
.VAR38 (),
.VAR126 (VAR41),
.VAR33 (),
.VAR73 (VAR99),
.VAR7 (),
.VAR124 (VAR117),
.VAR129 (),
.VAR140 (VAR94),
.VAR106 (),
.VAR11 (),
.VAR102 (VAR146),
.VAR103 ( 1'd0),
.VAR120 ( 7'd0),
.VAR22 ( 1'd0),
.VAR92 ( 1'd0),
.VAR123 (16'd0),
.VAR57 (),
.VAR65 (),
.VAR27 (1'd0),
.VAR149 (1'd0),
.VAR17 (1'd0),
.VAR98 (),
.VAR16 (),
.VAR63 ()
);
generate if (VAR90 != 1)
begin : VAR30
VAR50 VAR148
(
.VAR104 (1'd1),
.VAR132 (1'd1),
.VAR4 (VAR66),
.VAR47 (VAR41),
.VAR6 (1'd0),
.VAR151 (1'd0),
.VAR145 (~VAR32),
.VAR52 ( VAR32),
.VAR54 (VAR36)
);
end
else
begin : VAR53
VAR77 VAR148
(
.VAR40 (VAR66),
.VAR54 (VAR147)
);
assign VAR36 = VAR147;
end
endgenerate
generate if ((VAR46 == 1) || (VAR8 == "VAR55"))
begin : VAR96
for (VAR37=0; VAR37<VAR95; VAR37=VAR37+1)
begin : VAR100
VAR77 VAR100
(
.VAR40 (VAR122[VAR37]),
.VAR54 (VAR68[VAR37])
);
end
end
else
begin : VAR105
assign VAR68 = {VAR95{1'd0}};
end
endgenerate
generate if (VAR90 != 1)
begin : VAR141
VAR77 VAR56
(
.VAR40 (VAR66),
.VAR54 (VAR61)
);
end
else
begin : VAR56
assign VAR61 = VAR147; end
endgenerate
generate if (VAR87 != 0)
begin : VAR80
VAR77 VAR107
(
.VAR40 (VAR99),
.VAR54 (VAR128)
);
end
else
begin : VAR81
assign VAR128 = 1'd0;
end
endgenerate
generate if (VAR143 != 0)
begin : VAR10
VAR77 VAR125
(
.VAR40 (VAR117),
.VAR54 (VAR21)
);
end
else
begin : VAR14
assign VAR21 = 1'd0;
end
endgenerate
generate if (VAR114 == 2)
begin : VAR135
VAR77 VAR135
(
.VAR40 (VAR94),
.VAR54 (VAR109)
);
end
else
begin : VAR64
assign VAR109 = VAR137;
end
endgenerate
generate if ((VAR90 == 3) && (VAR8 == "VAR55"))
begin : VAR136
VAR77 VAR26
(
.VAR40 (VAR36),
.VAR54 (VAR137)
);
VAR50 VAR144
(
.VAR104 (1'b1),
.VAR132 (1'b1),
.VAR4 (VAR36),
.VAR47 (VAR122[0]),
.VAR6 (1'b0),
.VAR151 (1'b0),
.VAR145 (~VAR89),
.VAR52 ( VAR89),
.VAR54 (VAR86)
);
if (VAR87 != 0)
begin : VAR75
VAR77 VAR58
(
.VAR40 (VAR128),
.VAR54 (VAR28)
);
end
else
begin : VAR62
assign VAR28 = VAR128;
end
if (VAR143 != 0)
begin : VAR18
VAR77 VAR9
(
.VAR40 (VAR21),
.VAR54 (VAR29)
);
end
else
begin : VAR5
assign VAR29 = VAR21;
end
end
else
begin : VAR84
assign VAR137 = VAR36;
assign VAR86 = VAR36;
assign VAR28 = VAR128;
assign VAR29 = VAR21;
end
endgenerate
always @ (posedge VAR137)
begin
if (!VAR91)
VAR32 <= 1'd0;
end
else
begin
if (&VAR93)
VAR32 <= 1'd1;
end
else if (&(~VAR93))
VAR32 <= 1'd0;
else
VAR32 <= VAR32;
end
end
assign VAR78 = VAR137;
assign VAR118 = VAR146;
endmodule
|
mit
|
FAST-Switch/fast
|
lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_rgmii_in1.v
| 5,071 |
module MODULE1 (
VAR10,
VAR14,
VAR7,
VAR9,
VAR5);
input VAR10;
input VAR14;
input VAR7;
output VAR9;
output VAR5;
wire [0:0] VAR6;
wire [0:0] VAR8;
wire [0:0] VAR18 = VAR6[0:0];
wire VAR9 = VAR18;
wire [0:0] VAR13 = VAR8[0:0];
wire VAR5 = VAR13;
wire VAR21 = VAR14;
wire VAR12 = VAR21;
VAR22 VAR3 (
.VAR14 (VAR12),
.VAR7 (VAR7),
.VAR10 (VAR10),
.VAR9 (VAR6),
.VAR5 (VAR8),
.VAR16 (1'b0),
.VAR11 (1'b1));
VAR3.VAR20 = "VAR1 VAR15",
VAR3.VAR17 = "VAR2",
VAR3.VAR19 = "VAR22",
VAR3.VAR4 = 1;
endmodule
|
apache-2.0
|
FAST-Switch/fast
|
lib/hardware/pipeline/IPE_PPS_OPENFLOW/DISPATHER/DISPATHER_OUTPUT_zyl.v
| 6,483 |
module MODULE1(
input clk,
input reset,
input VAR38,input [133:0] VAR9,input VAR40,input VAR46,output VAR18,
input VAR49,input [133:0] VAR23,input VAR12,input VAR6,output VAR20,
output reg VAR26,output reg [133:0] VAR3,output reg VAR19,output reg VAR30,input VAR39
);
wire VAR27;
wire VAR22;
reg VAR31;
wire [7:0] VAR37;
assign VAR18 = VAR37[7];
reg VAR24;
wire [133:0]VAR43;
wire VAR28;
wire VAR2;
reg VAR42;
wire VAR45;
wire [7:0] VAR35;
assign VAR20 = VAR35[7];
reg VAR34;
wire [133:0]VAR32;
reg VAR44;reg [2:0] VAR17;
parameter VAR10 = 3'd0,
VAR25 = 3'd1,
VAR7 = 3'd2,
VAR13=3'd3,
VAR48=3'd4;
always@(posedge clk or negedge reset) begin
if(!reset) begin
VAR26<= 1'b0;
VAR3<= 134'b0;
VAR19<= 1'b0;
VAR30<=1'b0;
VAR44<=1'b0;
VAR31<=1'b0;
VAR24<=1'b0;
VAR42<=1'b0;
VAR34<=1'b0;
VAR17<=VAR10;
end
else begin
case(VAR17)
VAR10: begin
VAR26<= 1'b0;
VAR19<= 1'b0;
VAR30<=1'b0;
if(VAR39==1'b0) begin
case({VAR22,VAR2})
2'b00: begin if(VAR44==1'b0) begin VAR31<=1'b0;
VAR24<=1'b0;
VAR42<=1'b1;
VAR34<=1'b1;
VAR17<=VAR25;
end
else begin
VAR31<=1'b1;
VAR24<=1'b1;
VAR42<=1'b0;
VAR34<=1'b0;
VAR17<=VAR7;
end
end
2'b01: begin VAR31<=1'b1;
VAR24<=1'b1;
VAR42<=1'b0;
VAR34<=1'b0;
VAR17<=VAR7;
end
2'b10: begin VAR31<=1'b0;
VAR24<=1'b0;
VAR42<=1'b1;
VAR34<=1'b1;
VAR17<=VAR25;
end
default: begin
VAR31<=1'b0;
VAR24<=1'b0;
VAR42<=1'b0;
VAR34<=1'b0;
VAR17<=VAR10;
end
endcase
end
else begin
VAR31<=1'b0;
VAR24<=1'b0;
VAR42<=1'b0;
VAR34<=1'b0;
VAR17<=VAR10;
end
end
VAR7:begin
VAR31<=1'b0;
VAR26<=1'b1;
VAR3<=VAR43;
VAR44<=1'b0; if(VAR43[133:132]==2'b10) begin
VAR24<=1'b0;
VAR19<=1'b1;
VAR30<=1'b1;
VAR17<=VAR10;
end
else begin
VAR24<=1'b1;
VAR19<=1'b0;
VAR17<=VAR7;
end
end
VAR25:begin
VAR42<=1'b0;
VAR26<=1'b1;
VAR3<=VAR32;
VAR44<=1'b1; if(VAR32[133:132]==2'b10) begin
VAR34<=1'b0;
VAR19<=1'b1;
VAR17<=VAR10;
end
else begin
VAR34<=1'b1;
VAR19<=1'b0;
VAR17<=VAR25;
end
end
VAR13:begin
VAR31<=1'b0;
if(VAR32[133:132]==2'b10) begin
VAR24<=1'b0;
VAR17<=VAR10;
end
else begin
VAR24<=1'b1;
VAR17<=VAR13;
end
end
VAR48:begin
VAR42<=1'b0;
if(VAR32[133:132]==2'b10) begin
VAR42<=1'b0;
VAR17<=VAR10;
end
else begin
VAR34<=1'b1;
VAR17<=VAR48;
end
end
default: begin
VAR26<= 1'b0;
VAR19<= 1'b0;
VAR30<=1'b0;
VAR31<=1'b0;
VAR24<=1'b0;
VAR42<=1'b0;
VAR34<=1'b0;
VAR17<=VAR10;
end
endcase
end
end
VAR21 VAR5 (
.VAR36(!reset),
.VAR41(VAR46),
.VAR33(clk),
.VAR15(VAR31),
.VAR8(VAR40),
.VAR4(VAR27),
.VAR14(VAR22)
);
VAR1 VAR16 (
.VAR36(!reset),
.VAR41(VAR9),
.VAR33(clk),
.VAR15(VAR24),
.VAR8(VAR38),
.VAR4(VAR43),
.VAR47(VAR37)
);
VAR21 VAR29 (
.VAR36(!reset),
.VAR41(VAR6),
.VAR33(clk),
.VAR15(VAR42),
.VAR8(VAR12),
.VAR4(VAR28),
.VAR14(VAR2)
);
VAR1 VAR11 (
.VAR36(!reset),
.VAR41(VAR23),
.VAR33(clk),
.VAR15(VAR34),
.VAR8(VAR49),
.VAR4(VAR32),
.VAR47(VAR35),
.VAR14(VAR45)
);
endmodule
|
apache-2.0
|
bargei/NoC264
|
NoC264_3x3/mkRouterInputArbitersRoundRobin.v
| 37,229 |
module MODULE1(VAR215,
VAR2,
VAR157,
VAR91,
VAR4,
VAR57,
VAR78,
VAR19,
VAR118,
VAR115,
VAR40,
VAR3,
VAR205,
VAR13,
VAR117,
VAR64,
VAR81);
input VAR215;
input VAR2;
input [4 : 0] VAR157;
output [4 : 0] VAR91;
input VAR4;
input [4 : 0] VAR57;
output [4 : 0] VAR78;
input VAR19;
input [4 : 0] VAR118;
output [4 : 0] VAR115;
input VAR40;
input [4 : 0] VAR3;
output [4 : 0] VAR205;
input VAR13;
input [4 : 0] VAR117;
output [4 : 0] VAR64;
input VAR81;
wire [4 : 0] VAR91,
VAR78,
VAR115,
VAR205,
VAR64;
reg [4 : 0] VAR37;
wire [4 : 0] VAR62;
wire VAR216;
reg [4 : 0] VAR87;
wire [4 : 0] VAR191;
wire VAR94;
reg [4 : 0] VAR208;
wire [4 : 0] VAR72;
wire VAR168;
reg [4 : 0] VAR179;
wire [4 : 0] VAR148;
wire VAR228;
reg [4 : 0] VAR38;
wire [4 : 0] VAR219;
wire VAR177;
wire [1 : 0] VAR226,
VAR30,
VAR138,
VAR172,
VAR126,
VAR131,
VAR140,
VAR60,
VAR171,
VAR199,
VAR158,
VAR175,
VAR209,
VAR122,
VAR35,
VAR44,
VAR24,
VAR100,
VAR193,
VAR192,
VAR210,
VAR196,
VAR189,
VAR84,
VAR15,
VAR48,
VAR47,
VAR221,
VAR1,
VAR121,
VAR107,
VAR123,
VAR224,
VAR137,
VAR105,
VAR71,
VAR112,
VAR166,
VAR119,
VAR142,
VAR227,
VAR55,
VAR188,
VAR176,
VAR195,
VAR190,
VAR21,
VAR214,
VAR147,
VAR90;
wire VAR149,
VAR218,
VAR180,
VAR79,
VAR143,
VAR132,
VAR54,
VAR225,
VAR223,
VAR98,
VAR43,
VAR56,
VAR68,
VAR16,
VAR197,
VAR102,
VAR162,
VAR86,
VAR25,
VAR152,
VAR8,
VAR88,
VAR127,
VAR27,
VAR124,
VAR167,
VAR32,
VAR207,
VAR85,
VAR165,
VAR36,
VAR156,
VAR61,
VAR63,
VAR59,
VAR213,
VAR186,
VAR46,
VAR134,
VAR181,
VAR66,
VAR185,
VAR80,
VAR201,
VAR129,
VAR133,
VAR212,
VAR106,
VAR93,
VAR110,
VAR31,
VAR51,
VAR204,
VAR187,
VAR155,
VAR174,
VAR159,
VAR108,
VAR12,
VAR49,
VAR75,
VAR26,
VAR136,
VAR17,
VAR70,
VAR141,
VAR206,
VAR116,
VAR111,
VAR211,
VAR217,
VAR151,
VAR144,
VAR113,
VAR128,
VAR39,
VAR50,
VAR67,
VAR220,
VAR83,
VAR120,
VAR52,
VAR198,
VAR9,
VAR58,
VAR184,
VAR11,
VAR23,
VAR41,
VAR7;
assign VAR91 =
{ VAR227[1] || VAR190[1],
!VAR227[1] && !VAR190[1] &&
(VAR55[1] || VAR21[1]),
VAR143,
!VAR227[1] && !VAR190[1] &&
VAR86,
VAR132 } ;
assign VAR78 =
{ VAR226[1] || VAR131[1],
!VAR226[1] && !VAR131[1] &&
(VAR30[1] || VAR140[1]),
VAR180,
!VAR226[1] && !VAR131[1] &&
VAR162,
VAR79 } ;
assign VAR115 =
{ VAR158[1] || VAR44[1],
!VAR158[1] && !VAR44[1] &&
(VAR175[1] || VAR24[1]),
VAR197,
!VAR158[1] && !VAR44[1] &&
VAR16,
VAR102 } ;
assign VAR205 =
{ VAR210[1] || VAR48[1],
!VAR210[1] && !VAR48[1] &&
(VAR196[1] || VAR47[1]),
VAR43,
!VAR210[1] && !VAR48[1] &&
VAR225,
VAR56 } ;
assign VAR64 =
{ VAR107[1] || VAR71[1],
!VAR107[1] && !VAR71[1] &&
(VAR123[1] || VAR112[1]),
VAR149,
!VAR107[1] && !VAR71[1] &&
VAR152,
VAR218 } ;
assign VAR62 = { VAR37[0], VAR37[4:1] } ;
assign VAR216 = VAR4 ;
assign VAR191 = { VAR87[0], VAR87[4:1] } ;
assign VAR94 = VAR19 ;
assign VAR72 = { VAR208[0], VAR208[4:1] } ;
assign VAR168 = VAR40 ;
assign VAR148 = { VAR179[0], VAR179[4:1] } ;
assign VAR228 = VAR13 ;
assign VAR219 = { VAR38[0], VAR38[4:1] } ;
assign VAR177 = VAR81 ;
VAR34 VAR95(.VAR139(1'd0),
.VAR109(VAR157[0]),
.VAR178(VAR141),
.VAR99(VAR195));
VAR34 VAR222(.VAR139(VAR159),
.VAR109(VAR157[1]),
.VAR178(VAR206),
.VAR99(VAR176));
VAR34 VAR160(.VAR139(VAR108),
.VAR109(VAR157[2]),
.VAR178(VAR116),
.VAR99(VAR188));
VAR34 VAR163(.VAR139(VAR12),
.VAR109(VAR157[3]),
.VAR178(VAR111),
.VAR99(VAR55));
VAR34 VAR89(.VAR139(VAR49),
.VAR109(VAR157[4]),
.VAR178(VAR211),
.VAR99(VAR227));
VAR34 VAR153(.VAR139(VAR75),
.VAR109(VAR157[0]),
.VAR178(VAR141),
.VAR99(VAR90));
VAR34 VAR161(.VAR139(VAR70),
.VAR109(VAR157[1]),
.VAR178(VAR206),
.VAR99(VAR147));
VAR34 VAR170(.VAR139(VAR17),
.VAR109(VAR157[2]),
.VAR178(VAR116),
.VAR99(VAR214));
VAR34 VAR96(.VAR139(VAR136),
.VAR109(VAR157[3]),
.VAR178(VAR111),
.VAR99(VAR21));
VAR34 VAR45(.VAR139(VAR26),
.VAR109(VAR157[4]),
.VAR178(VAR211),
.VAR99(VAR190));
VAR34 VAR150(.VAR139(1'd0),
.VAR109(VAR57[0]),
.VAR178(VAR217),
.VAR99(VAR126));
VAR34 VAR183(.VAR139(VAR8),
.VAR109(VAR57[1]),
.VAR178(VAR151),
.VAR99(VAR172));
VAR34 VAR73(.VAR139(VAR88),
.VAR109(VAR57[2]),
.VAR178(VAR144),
.VAR99(VAR138));
VAR34 VAR42(.VAR139(VAR127),
.VAR109(VAR57[3]),
.VAR178(VAR113),
.VAR99(VAR30));
VAR34 VAR114(.VAR139(VAR27),
.VAR109(VAR57[4]),
.VAR178(VAR128),
.VAR99(VAR226));
VAR34 VAR125(.VAR139(VAR124),
.VAR109(VAR57[0]),
.VAR178(VAR217),
.VAR99(VAR199));
VAR34 VAR74(.VAR139(VAR85),
.VAR109(VAR57[1]),
.VAR178(VAR151),
.VAR99(VAR171));
VAR34 VAR20(.VAR139(VAR207),
.VAR109(VAR57[2]),
.VAR178(VAR144),
.VAR99(VAR60));
VAR34 VAR76(.VAR139(VAR32),
.VAR109(VAR57[3]),
.VAR178(VAR113),
.VAR99(VAR140));
VAR34 VAR28(.VAR139(VAR167),
.VAR109(VAR57[4]),
.VAR178(VAR128),
.VAR99(VAR131));
VAR34 VAR203(.VAR139(1'd0),
.VAR109(VAR118[0]),
.VAR178(VAR39),
.VAR99(VAR35));
VAR34 VAR169(.VAR139(VAR165),
.VAR109(VAR118[1]),
.VAR178(VAR50),
.VAR99(VAR122));
VAR34 VAR97(.VAR139(VAR36),
.VAR109(VAR118[2]),
.VAR178(VAR67),
.VAR99(VAR209));
VAR34 VAR164(.VAR139(VAR156),
.VAR109(VAR118[3]),
.VAR178(VAR220),
.VAR99(VAR175));
VAR34 VAR18(.VAR139(VAR61),
.VAR109(VAR118[4]),
.VAR178(VAR83),
.VAR99(VAR158));
VAR34 VAR145(.VAR139(VAR63),
.VAR109(VAR118[0]),
.VAR178(VAR39),
.VAR99(VAR192));
VAR34 VAR146(.VAR139(VAR46),
.VAR109(VAR118[1]),
.VAR178(VAR50),
.VAR99(VAR193));
VAR34 VAR173(.VAR139(VAR186),
.VAR109(VAR118[2]),
.VAR178(VAR67),
.VAR99(VAR100));
VAR34 VAR10(.VAR139(VAR213),
.VAR109(VAR118[3]),
.VAR178(VAR220),
.VAR99(VAR24));
VAR34 VAR65(.VAR139(VAR59),
.VAR109(VAR118[4]),
.VAR178(VAR83),
.VAR99(VAR44));
VAR34 VAR101(.VAR139(1'd0),
.VAR109(VAR3[0]),
.VAR178(VAR120),
.VAR99(VAR15));
VAR34 VAR82(.VAR139(VAR134),
.VAR109(VAR3[1]),
.VAR178(VAR52),
.VAR99(VAR84));
VAR34 VAR104(.VAR139(VAR181),
.VAR109(VAR3[2]),
.VAR178(VAR198),
.VAR99(VAR189));
VAR34 VAR103(.VAR139(VAR66),
.VAR109(VAR3[3]),
.VAR178(VAR9),
.VAR99(VAR196));
VAR34 VAR194(.VAR139(VAR185),
.VAR109(VAR3[4]),
.VAR178(VAR58),
.VAR99(VAR210));
VAR34 VAR22(.VAR139(VAR80),
.VAR109(VAR3[0]),
.VAR178(VAR120),
.VAR99(VAR121));
VAR34 VAR200(.VAR139(VAR212),
.VAR109(VAR3[1]),
.VAR178(VAR52),
.VAR99(VAR1));
VAR34 VAR6(.VAR139(VAR133),
.VAR109(VAR3[2]),
.VAR178(VAR198),
.VAR99(VAR221));
VAR34 VAR69(.VAR139(VAR129),
.VAR109(VAR3[3]),
.VAR178(VAR9),
.VAR99(VAR47));
VAR34 VAR92(.VAR139(VAR201),
.VAR109(VAR3[4]),
.VAR178(VAR58),
.VAR99(VAR48));
VAR34 VAR202(.VAR139(1'd0),
.VAR109(VAR117[0]),
.VAR178(VAR184),
.VAR99(VAR105));
VAR34 VAR29(.VAR139(VAR106),
.VAR109(VAR117[1]),
.VAR178(VAR11),
.VAR99(VAR137));
VAR34 VAR130(.VAR139(VAR93),
.VAR109(VAR117[2]),
.VAR178(VAR23),
.VAR99(VAR224));
VAR34 VAR5(.VAR139(VAR110),
.VAR109(VAR117[3]),
.VAR178(VAR41),
.VAR99(VAR123));
VAR34 VAR135(.VAR139(VAR31),
.VAR109(VAR117[4]),
.VAR178(VAR7),
.VAR99(VAR107));
VAR34 VAR53(.VAR139(VAR51),
.VAR109(VAR117[0]),
.VAR178(VAR184),
.VAR99(VAR142));
VAR34 VAR14(.VAR139(VAR174),
.VAR109(VAR117[1]),
.VAR178(VAR11),
.VAR99(VAR119));
VAR34 VAR154(.VAR139(VAR155),
.VAR109(VAR117[2]),
.VAR178(VAR23),
.VAR99(VAR166));
VAR34 VAR77(.VAR139(VAR187),
.VAR109(VAR117[3]),
.VAR178(VAR41),
.VAR99(VAR112));
VAR34 VAR182(.VAR139(VAR204),
.VAR109(VAR117[4]),
.VAR178(VAR7),
.VAR99(VAR71));
assign VAR149 =
!VAR107[1] && !VAR71[1] && !VAR123[1] &&
!VAR112[1] &&
(VAR224[1] || VAR166[1]) ;
assign VAR218 =
!VAR107[1] && !VAR71[1] && !VAR123[1] &&
!VAR112[1] &&
VAR25 ;
assign VAR180 =
!VAR226[1] && !VAR131[1] && !VAR30[1] &&
!VAR140[1] &&
(VAR138[1] || VAR60[1]) ;
assign VAR79 =
!VAR226[1] && !VAR131[1] && !VAR30[1] &&
!VAR140[1] &&
VAR223 ;
assign VAR143 =
!VAR227[1] && !VAR190[1] && !VAR55[1] &&
!VAR21[1] &&
(VAR188[1] || VAR214[1]) ;
assign VAR132 =
!VAR227[1] && !VAR190[1] && !VAR55[1] &&
!VAR21[1] &&
VAR98 ;
assign VAR54 =
!VAR189[1] && !VAR221[1] && !VAR84[1] &&
!VAR1[1] &&
(VAR15[1] || VAR121[1]) ;
assign VAR225 =
!VAR196[1] && !VAR47[1] && !VAR189[1] &&
!VAR221[1] &&
(VAR84[1] || VAR1[1]) ;
assign VAR223 =
!VAR138[1] && !VAR60[1] && !VAR172[1] &&
!VAR171[1] &&
(VAR126[1] || VAR199[1]) ;
assign VAR98 =
!VAR188[1] && !VAR214[1] && !VAR176[1] &&
!VAR147[1] &&
(VAR195[1] || VAR90[1]) ;
assign VAR43 =
!VAR210[1] && !VAR48[1] && !VAR196[1] &&
!VAR47[1] &&
(VAR189[1] || VAR221[1]) ;
assign VAR56 =
!VAR210[1] && !VAR48[1] && !VAR196[1] &&
!VAR47[1] &&
VAR54 ;
assign VAR68 =
!VAR209[1] && !VAR100[1] && !VAR122[1] &&
!VAR193[1] &&
(VAR35[1] || VAR192[1]) ;
assign VAR16 =
!VAR175[1] && !VAR24[1] && !VAR209[1] &&
!VAR100[1] &&
(VAR122[1] || VAR193[1]) ;
assign VAR197 =
!VAR158[1] && !VAR44[1] && !VAR175[1] &&
!VAR24[1] &&
(VAR209[1] || VAR100[1]) ;
assign VAR102 =
!VAR158[1] && !VAR44[1] && !VAR175[1] &&
!VAR24[1] &&
VAR68 ;
assign VAR162 =
!VAR30[1] && !VAR140[1] && !VAR138[1] &&
!VAR60[1] &&
(VAR172[1] || VAR171[1]) ;
assign VAR86 =
!VAR55[1] && !VAR21[1] && !VAR188[1] &&
!VAR214[1] &&
(VAR176[1] || VAR147[1]) ;
assign VAR25 =
!VAR224[1] && !VAR166[1] && !VAR137[1] &&
!VAR119[1] &&
(VAR105[1] || VAR142[1]) ;
assign VAR152 =
!VAR123[1] && !VAR112[1] && !VAR224[1] &&
!VAR166[1] &&
(VAR137[1] || VAR119[1]) ;
assign VAR8 = VAR126[0] ;
assign VAR88 = VAR172[0] ;
assign VAR127 = VAR138[0] ;
assign VAR27 = VAR30[0] ;
assign VAR124 = VAR226[0] ;
assign VAR167 = VAR140[0] ;
assign VAR32 = VAR60[0] ;
assign VAR207 = VAR171[0] ;
assign VAR85 = VAR199[0] ;
assign VAR165 = VAR35[0] ;
assign VAR36 = VAR122[0] ;
assign VAR156 = VAR209[0] ;
assign VAR61 = VAR175[0] ;
assign VAR63 = VAR158[0] ;
assign VAR59 = VAR24[0] ;
assign VAR213 = VAR100[0] ;
assign VAR186 = VAR193[0] ;
assign VAR46 = VAR192[0] ;
assign VAR134 = VAR15[0] ;
assign VAR181 = VAR84[0] ;
assign VAR66 = VAR189[0] ;
assign VAR185 = VAR196[0] ;
assign VAR80 = VAR210[0] ;
assign VAR201 = VAR47[0] ;
assign VAR129 = VAR221[0] ;
assign VAR133 = VAR1[0] ;
assign VAR212 = VAR121[0] ;
assign VAR106 = VAR105[0] ;
assign VAR93 = VAR137[0] ;
assign VAR110 = VAR224[0] ;
assign VAR31 = VAR123[0] ;
assign VAR51 = VAR107[0] ;
assign VAR204 = VAR112[0] ;
assign VAR187 = VAR166[0] ;
assign VAR155 = VAR119[0] ;
assign VAR174 = VAR142[0] ;
assign VAR159 = VAR195[0] ;
assign VAR108 = VAR176[0] ;
assign VAR12 = VAR188[0] ;
assign VAR49 = VAR55[0] ;
assign VAR75 = VAR227[0] ;
assign VAR26 = VAR21[0] ;
assign VAR136 = VAR214[0] ;
assign VAR17 = VAR147[0] ;
assign VAR70 = VAR90[0] ;
assign VAR141 = VAR37[0] ;
assign VAR206 = VAR37[1] ;
assign VAR116 = VAR37[2] ;
assign VAR111 = VAR37[3] ;
assign VAR211 = VAR37[4] ;
assign VAR217 = VAR87[0] ;
assign VAR151 = VAR87[1] ;
assign VAR144 = VAR87[2] ;
assign VAR113 = VAR87[3] ;
assign VAR128 = VAR87[4] ;
assign VAR39 = VAR208[0] ;
assign VAR50 = VAR208[1] ;
assign VAR67 = VAR208[2] ;
assign VAR220 = VAR208[3] ;
assign VAR83 = VAR208[4] ;
assign VAR120 = VAR179[0] ;
assign VAR52 = VAR179[1] ;
assign VAR198 = VAR179[2] ;
assign VAR9 = VAR179[3] ;
assign VAR58 = VAR179[4] ;
assign VAR184 = VAR38[0] ;
assign VAR11 = VAR38[1] ;
assign VAR23 = VAR38[2] ;
assign VAR41 = VAR38[3] ;
assign VAR7 = VAR38[4] ;
always@(posedge VAR215)
begin
if (!VAR2)
begin
VAR37 <= VAR33 5'd1;
VAR87 <= VAR33 5'd2;
VAR208 <= VAR33 5'd4;
VAR179 <= VAR33 5'd8;
VAR38 <= VAR33 5'd16;
end
else
begin
if (VAR216)
VAR37 <= VAR33 VAR62;
if (VAR94)
VAR87 <= VAR33 VAR191;
if (VAR168)
VAR208 <= VAR33 VAR72;
if (VAR228)
VAR179 <= VAR33 VAR148;
if (VAR177)
VAR38 <= VAR33 VAR219;
end
end
begin
VAR37 = 5'h0A;
VAR87 = 5'h0A;
VAR208 = 5'h0A;
VAR179 = 5'h0A;
VAR38 = 5'h0A;
end
|
mit
|
alexforencich/verilog-axis
|
rtl/axis_demux.v
| 10,715 |
module MODULE1 #
(
parameter VAR11 = 4,
parameter VAR19 = 8,
parameter VAR13 = (VAR19>8),
parameter VAR15 = ((VAR19+7)/8),
parameter VAR21 = 0,
parameter VAR6 = 8,
parameter VAR25 = 0,
parameter VAR30 = 8,
parameter VAR31 = VAR30+VAR22(VAR11),
parameter VAR8 = 1,
parameter VAR10 = 1,
parameter VAR17 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR19-1:0] VAR14,
input wire [VAR15-1:0] VAR28,
input wire VAR2,
output wire VAR3,
input wire VAR16,
input wire [VAR6-1:0] VAR27,
input wire [VAR31-1:0] VAR4,
input wire [VAR10-1:0] VAR29,
output wire [VAR11*VAR19-1:0] VAR32,
output wire [VAR11*VAR15-1:0] VAR7,
output wire [VAR11-1:0] VAR26,
input wire [VAR11-1:0] VAR1,
output wire [VAR11-1:0] VAR9,
output wire [VAR11*VAR6-1:0] VAR24,
output wire [VAR11*VAR30-1:0] VAR18,
output wire [VAR11*VAR10-1:0] VAR23,
input wire enable,
input wire VAR5,
input wire [VAR22(VAR11)-1:0] select
);
parameter VAR12 = VAR22(VAR11);
parameter VAR20 = VAR30 > 0 ? VAR30 : 1;
|
mit
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.behavioral.v
| 1,170 |
module MODULE1( VAR3, VAR5, VAR4 );
input VAR3, VAR5;
output VAR4;
VAR1 VAR2(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR6(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4));
|
apache-2.0
|
ipburbank/Raster-Laser-Projector
|
src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_scaler_multiply_width.v
| 6,273 |
module MODULE1 (
clk,
reset,
VAR12,
VAR3,
VAR8,
VAR5,
VAR16,
VAR6,
VAR9,
VAR4,
VAR1,
VAR13,
VAR10,
VAR18
);
parameter VAR20 = 15; parameter VAR15 = 15;
parameter VAR7 = 0;
input clk;
input reset;
input [VAR20: 0] VAR12;
input [VAR15: 0] VAR3;
input VAR8;
input VAR5;
input VAR16;
input VAR6;
output VAR9;
output reg [VAR20: 0] VAR4;
output reg [VAR15: 0] VAR1;
output reg VAR13;
output reg VAR10;
output reg VAR18;
reg [VAR20: 0] VAR17;
reg [VAR15: 0] VAR14;
reg VAR11;
reg VAR2;
reg valid;
reg [VAR7:0] VAR19;
always @(posedge clk)
begin
if (reset)
begin
VAR4 <= 'h0;
VAR1 <= 'h0;
VAR13 <= 1'b0;
VAR10 <= 1'b0;
VAR18 <= 1'b0;
end
else if (VAR6 | ~VAR18)
begin
VAR4 <= {VAR17, VAR19};
VAR1 <= VAR14;
if (|(VAR19))
VAR13 <= 1'b0;
end
else
VAR13 <= VAR11;
if (&(VAR19))
VAR10 <= VAR2;
end
else
VAR10 <= 1'b0;
VAR18 <= valid;
end
end
always @(posedge clk)
begin
if (reset)
begin
VAR17 <= 'h0;
VAR14 <= 'h0;
VAR11 <= 1'b0;
VAR2 <= 1'b0;
valid <= 1'b0;
end
else if (VAR9)
begin
VAR17 <= VAR12;
VAR14 <= VAR3;
VAR11 <= VAR8;
VAR2 <= VAR5;
valid <= VAR16;
end
end
always @(posedge clk)
begin
if (reset)
VAR19 <= 'h0;
end
else if ((VAR6 | ~VAR18) & valid)
VAR19 <= VAR19 + 1;
end
assign VAR9 = (~valid) |
((&(VAR19)) & (VAR6 | ~VAR18));
endmodule
|
gpl-3.0
|
Nrpickle/ECE272
|
Lab3_7SegDisplayDriver/section3_schematic_tf.v
| 1,543 |
module MODULE1();
reg VAR2;
reg VAR10;
reg VAR3;
reg VAR8;
wire VAR11;
wire VAR4;
wire VAR6;
wire VAR12;
wire VAR13;
wire VAR9;
wire VAR1;
VAR7 VAR5 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR13(VAR13),
.VAR9(VAR9),
.VAR1(VAR1)
);
|
mit
|
ssabogal/nocturnal
|
noc_dev/noc_dev.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v
| 5,685 |
module MODULE1 #
(
parameter integer VAR27 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR27-1:0] VAR46,
output wire [1:0] VAR17,
output wire VAR23,
input wire VAR51,
input wire [1:0] VAR8,
input wire VAR11,
output wire VAR44,
input wire VAR47,
input wire [VAR27-1:0] VAR26,
input wire [7:0] VAR33,
input wire VAR5,
output wire VAR28
);
localparam [1:0] VAR42 = 2'b00;
localparam [1:0] VAR21 = 2'b01;
localparam [1:0] VAR38 = 2'b10;
localparam [1:0] VAR41 = 2'b11;
localparam VAR14 = VAR27 + 8;
localparam VAR35 = 4;
localparam VAR49 = 2;
localparam VAR32 = 2;
localparam VAR39 = 4;
localparam VAR19 = 2;
reg VAR25;
wire [VAR27-1:0] VAR9;
wire VAR37;
reg VAR1;
wire VAR10;
reg VAR31;
wire VAR30;
wire VAR43;
wire VAR48;
wire [7:0] VAR4;
reg [7:0] VAR20;
reg [1:0] VAR12;
wire [1:0] VAR2;
reg [1:0] VAR40;
wire VAR50;
wire VAR3;
assign VAR46 = VAR9;
assign VAR17 = VAR2;
assign VAR23 = VAR25;
assign VAR37 = VAR23 & VAR51;
assign VAR10 = VAR11 & VAR44;
always @(posedge clk) begin
if (reset | VAR37) begin
VAR25 <= 1'b0;
end else if (~VAR30 & ~VAR1 & ~VAR48) begin
VAR25 <= 1'b1;
end
end
always @(posedge clk) begin
VAR1 <= VAR37;
VAR31 <= VAR10;
end
VAR13 #(
.VAR16 (VAR14),
.VAR6 (VAR49),
.VAR36 (VAR35)
)
VAR22
(
.clk ( clk ) ,
.rst ( reset ) ,
.VAR18 ( VAR47 ) ,
.VAR24 ( VAR1 ) ,
.din ( {VAR26, VAR33} ) ,
.dout ( {VAR9, VAR4}) ,
.VAR45 ( ) ,
.VAR7 ( VAR28 ) ,
.VAR29 ( ) ,
.VAR34 ( VAR30 )
);
assign VAR44 = ~VAR31 & VAR48;
assign VAR50 = ( VAR8 > VAR12 );
always @( * ) begin
if ( VAR50 ) begin
VAR40 = VAR8;
end else begin
VAR40 = VAR12;
end
end
always @ (posedge clk) begin
if (reset | VAR3 ) begin
VAR12 <= VAR42;
end else if ( VAR10 ) begin
VAR12 <= VAR40;
end
end
assign VAR3 = ( VAR31 ) & (VAR20 == VAR4) & ~VAR30;
always @ (posedge clk) begin
if (reset | VAR3 ) begin
VAR20 <= 8'h00;
end else if ( VAR31 ) begin
VAR20 <= VAR20 + 1'b1;
end
end
VAR13 #(
.VAR16 (VAR32),
.VAR6 (VAR19),
.VAR36 (VAR39)
)
VAR15
(
.clk ( clk ) ,
.rst ( reset ) ,
.VAR18 ( VAR3 ) ,
.VAR24 ( VAR1 ) ,
.din ( VAR12 ) ,
.dout ( VAR2) ,
.VAR45 ( ) ,
.VAR7 ( VAR43 ) ,
.VAR29 ( ) ,
.VAR34 ( VAR48 )
);
endmodule
|
mit
|
pradeep9676/pradeep_9676
|
LZD_16bit.v
| 1,549 |
module MODULE1( in, out, valid
);
input [15:0]in;
output reg [3:0]out;
output reg valid;
wire VAR2,VAR3;
wire [2:0]VAR1, VAR4;
begin
begin
begin
end
begin
begin
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a32o/sky130_fd_sc_hs__a32o_4.v
| 2,342 |
module MODULE2 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR10,
VAR2
);
output VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR10;
input VAR2;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7,
VAR9,
VAR1,
VAR5,
VAR4
);
output VAR6 ;
input VAR7;
input VAR9;
input VAR1;
input VAR5;
input VAR4;
supply1 VAR10;
supply0 VAR2;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o2111a/sky130_fd_sc_hs__o2111a.symbol.v
| 1,357 |
module MODULE1 (
input VAR1,
input VAR2,
input VAR4,
input VAR5,
input VAR6,
output VAR3
);
supply1 VAR7;
supply0 VAR8;
endmodule
|
apache-2.0
|
jefg89/proyecto_final_prototipado
|
ProyectoFinal/db/altera_mult_add_opt2.v
| 15,361 |
module MODULE1
(
VAR209,
VAR120,
VAR210,
VAR237,
VAR91) ;
input VAR209;
input VAR120;
input [15:0] VAR210;
input [15:0] VAR237;
output [15:0] VAR91;
tri0 VAR209;
tri1 VAR120;
tri0 [15:0] VAR210;
tri0 [15:0] VAR237;
wire [15:0] VAR274;
VAR28 VAR284
(
.VAR209(VAR209),
.VAR107(),
.VAR120(VAR120),
.VAR210(VAR210),
.VAR237(VAR237),
.VAR70(),
.VAR10(),
.VAR222(),
.VAR140(),
.VAR259(),
.VAR91(VAR274),
.VAR227(),
.VAR12(),
.VAR248(1'b0),
.VAR47(1'b0),
.VAR54(1'b0),
.VAR186(1'b0),
.VAR41(1'b1),
.VAR87(1'b0),
.VAR152(1'b1),
.VAR53(1'b0),
.VAR117({1{1'b0}}),
.VAR196(1'b0),
.VAR79(1'b0),
.VAR142(1'b1),
.VAR92(1'b1),
.VAR268(1'b1),
.VAR215({3{1'b0}}),
.VAR168({3{1'b0}}),
.VAR81({3{1'b0}}),
.VAR180({3{1'b0}}),
.VAR138({22{1'b0}}),
.VAR33(1'b1),
.VAR118(1'b1),
.VAR278(1'b1),
.VAR263(1'b1),
.VAR1(1'b0),
.VAR134(1'b0),
.VAR267(1'b0),
.VAR25(1'b0),
.VAR179(1'b0),
.VAR288(1'b0),
.VAR102(1'b0),
.VAR126({16{1'b0}}),
.VAR245({16{1'b0}}),
.VAR71(1'b0),
.VAR192(1'b0),
.VAR250(1'b0),
.VAR154(1'b0),
.VAR143({1{1'b0}}),
.VAR223({1{1'b0}}),
.VAR211(1'b0),
.VAR276(1'b0)
);
VAR284.VAR219 = "VAR144",
VAR284.VAR270 = "VAR177",
VAR284.VAR277 = "VAR177",
VAR284.VAR153 = "VAR104",
VAR284.VAR255 = "VAR104",
VAR284.VAR145 = "VAR149",
VAR284.VAR121 = "VAR149",
VAR284.VAR216 = "VAR149",
VAR284.VAR229 = "VAR177",
VAR284.VAR233 = "VAR177",
VAR284.VAR285 = "VAR104",
VAR284.VAR172 = "VAR104",
VAR284.VAR20 = "VAR177",
VAR284.VAR163 = "VAR177",
VAR284.VAR256 = "VAR104",
VAR284.VAR67 = "VAR104",
VAR284.VAR249 = "VAR177",
VAR284.VAR51 = "VAR177",
VAR284.VAR221 = "VAR269",
VAR284.VAR189 = "VAR177",
VAR284.VAR57 = "VAR247",
VAR284.VAR15 = "VAR104",
VAR284.VAR198 = "VAR104",
VAR284.VAR217 = "VAR104",
VAR284.VAR169 = "VAR177",
VAR284.VAR60 = "VAR149",
VAR284.VAR78 = "VAR104",
VAR284.VAR108 = "VAR177",
VAR284.VAR4 = "VAR177",
VAR284.VAR27 = "VAR104",
VAR284.VAR208 = "VAR177",
VAR284.VAR7 = "VAR104",
VAR284.VAR241 = "VAR104",
VAR284.VAR214 = "VAR149",
VAR284.VAR74 = "VAR177",
VAR284.VAR88 = "VAR177",
VAR284.VAR55 = "VAR104",
VAR284.VAR109 = "VAR177",
VAR284.VAR32 = "VAR104",
VAR284.VAR159 = "VAR104",
VAR284.VAR101 = "VAR149",
VAR284.VAR252 = 0,
VAR284.VAR175 = 0,
VAR284.VAR45 = 0,
VAR284.VAR181 = 0,
VAR284.VAR18 = 0,
VAR284.VAR150 = 0,
VAR284.VAR135 = 0,
VAR284.VAR116 = 0,
VAR284.VAR43 = 0,
VAR284.VAR24 = 0,
VAR284.VAR93 = 0,
VAR284.VAR62 = 0,
VAR284.VAR3 = 0,
VAR284.VAR236 = 0,
VAR284.VAR119 = 0,
VAR284.VAR170 = 0,
VAR284.VAR89 = 0,
VAR284.VAR190 = 0,
VAR284.VAR96 = 0,
VAR284.VAR197 = 0,
VAR284.VAR193 = 0,
VAR284.VAR5 = 0,
VAR284.VAR199 = 0,
VAR284.VAR99 = 0,
VAR284.VAR26 = 0,
VAR284.VAR147 = 0,
VAR284.VAR36 = 0,
VAR284.VAR130 = 0,
VAR284.VAR30 = 0,
VAR284.VAR139 = 0,
VAR284.VAR115 = 0,
VAR284.VAR56 = 0,
VAR284.VAR195 = "VAR177",
VAR284.VAR141 = "VAR104",
VAR284.VAR232 = "VAR177",
VAR284.VAR156 = "VAR104",
VAR284.VAR243 = "VAR177",
VAR284.VAR64 = "VAR104",
VAR284.VAR157 = "VAR177",
VAR284.VAR123 = "VAR104",
VAR284.VAR94 = "VAR205",
VAR284.VAR112 = "VAR149",
VAR284.VAR235 = "VAR279",
VAR284.VAR148 = 0,
VAR284.VAR194 = "VAR177",
VAR284.VAR85 = "VAR177",
VAR284.VAR61 = "VAR177",
VAR284.VAR133 = "VAR177",
VAR284.VAR50 = "VAR177",
VAR284.VAR283 = "VAR177",
VAR284.VAR42 = "VAR177",
VAR284.VAR162 = "VAR177",
VAR284.VAR239 = "VAR177",
VAR284.VAR225 = "VAR177",
VAR284.VAR82 = "VAR177",
VAR284.VAR146 = "VAR177",
VAR284.VAR176 = "VAR104",
VAR284.VAR165 = "VAR104",
VAR284.VAR261 = "VAR104",
VAR284.VAR125 = "VAR104",
VAR284.VAR183 = "VAR104",
VAR284.VAR110 = "VAR104",
VAR284.VAR31 = "VAR104",
VAR284.VAR38 = "VAR104",
VAR284.VAR151 = "VAR104",
VAR284.VAR191 = "VAR104",
VAR284.VAR17 = "VAR104",
VAR284.VAR2 = "VAR104",
VAR284.VAR76 = "VAR63",
VAR284.VAR136 = "VAR63",
VAR284.VAR72 = "VAR63",
VAR284.VAR240 = "VAR63",
VAR284.VAR203 = "VAR226",
VAR284.VAR287 = "VAR226",
VAR284.VAR35 = "VAR226",
VAR284.VAR65 = "VAR226",
VAR284.VAR37 = "VAR177",
VAR284.VAR58 = "VAR104",
VAR284.VAR75 = 64,
VAR284.VAR129 = "VAR177",
VAR284.VAR228 = "VAR104",
VAR284.VAR220 = "VAR269",
VAR284.VAR16 = "VAR104",
VAR284.VAR289 = "VAR177",
VAR284.VAR238 = "VAR104",
VAR284.VAR84 = "VAR177",
VAR284.VAR66 = "VAR104",
VAR284.VAR212 = "VAR149",
VAR284.VAR201 = "VAR149",
VAR284.VAR202 = "VAR144",
VAR284.VAR19 = "VAR149",
VAR284.VAR9 = "VAR149",
VAR284.VAR242 = "VAR144",
VAR284.VAR207 = "VAR269",
VAR284.VAR281 = "VAR177",
VAR284.VAR106 = "VAR177",
VAR284.VAR171 = "VAR177",
VAR284.VAR262 = "VAR247",
VAR284.VAR251 = "VAR104",
VAR284.VAR90 = "VAR104",
VAR284.VAR8 = "VAR104",
VAR284.VAR286 = 1,
VAR284.VAR173 = "VAR177",
VAR284.VAR29 = "VAR104",
VAR284.VAR254 = "VAR177",
VAR284.VAR155 = "VAR177",
VAR284.VAR48 = "VAR104",
VAR284.VAR187 = "VAR104",
VAR284.VAR137 = "VAR40",
VAR284.VAR52 = "VAR149",
VAR284.VAR275 = "VAR177",
VAR284.VAR178 = "VAR177",
VAR284.VAR204 = "VAR104",
VAR284.VAR246 = "VAR104",
VAR284.VAR188 = "VAR80",
VAR284.VAR182 = "VAR149",
VAR284.VAR158 = "VAR86",
VAR284.VAR128 = "VAR86",
VAR284.VAR13 = "VAR86",
VAR284.VAR83 = "VAR86",
VAR284.VAR266 = "VAR86",
VAR284.VAR131 = "VAR86",
VAR284.VAR23 = "VAR144",
VAR284.VAR46 = "VAR144",
VAR284.VAR59 = "VAR144",
VAR284.VAR231 = "VAR144",
VAR284.VAR95 = "VAR132",
VAR284.VAR167 = "VAR244",
VAR284.VAR22 = "VAR244",
VAR284.VAR272 = "VAR177",
VAR284.VAR271 = "VAR177",
VAR284.VAR49 = "VAR104",
VAR284.VAR111 = "VAR177",
VAR284.VAR124 = "VAR104",
VAR284.VAR103 = "VAR104",
VAR284.VAR258 = "VAR177",
VAR284.VAR265 = "VAR104",
VAR284.VAR273 = "VAR206 VAR77",
VAR284.VAR264 = "VAR149",
VAR284.VAR257 = "VAR177",
VAR284.VAR200 = "VAR177",
VAR284.VAR164 = "VAR104",
VAR284.VAR34 = "VAR177",
VAR284.VAR14 = "VAR104",
VAR284.VAR166 = "VAR104",
VAR284.VAR174 = "VAR177",
VAR284.VAR224 = "VAR177",
VAR284.VAR280 = "VAR269",
VAR284.VAR21 = "VAR269",
VAR284.VAR105 = "VAR247",
VAR284.VAR97 = "VAR247",
VAR284.VAR260 = "VAR104",
VAR284.VAR114 = "VAR104",
VAR284.VAR122 = "VAR177",
VAR284.VAR218 = "VAR177",
VAR284.VAR73 = "VAR104",
VAR284.VAR160 = "VAR104",
VAR284.VAR69 = "VAR149",
VAR284.VAR68 = 16,
VAR284.VAR230 = 16,
VAR284.VAR100 = 22,
VAR284.VAR113 = 1,
VAR284.VAR282 = 18,
VAR284.VAR11 = 17,
VAR284.VAR253 = 16,
VAR284.VAR185 = 1,
VAR284.VAR39 = "VAR177",
VAR284.VAR98 = "VAR104",
VAR284.VAR6 = "VAR177",
VAR284.VAR213 = "VAR177",
VAR284.VAR127 = "VAR104",
VAR284.VAR44 = "VAR177",
VAR284.VAR161 = "VAR104",
VAR284.VAR234 = "VAR104",
VAR284.VAR184 = "VAR28";
assign
VAR91 = VAR274;
endmodule
|
gpl-2.0
|
alexforencich/verilog-ethernet
|
rtl/ptp_ts_extract.v
| 2,028 |
module MODULE1 #
(
parameter VAR1 = 96,
parameter VAR9 = 1,
parameter VAR4 = VAR1+VAR9
)
(
input wire clk,
input wire rst,
input wire VAR3,
input wire VAR2,
input wire [VAR4-1:0] VAR8,
output wire [VAR1-1:0] VAR5,
output wire VAR6
);
reg VAR7 = 1'b0;
assign VAR5 = VAR8 >> VAR9;
assign VAR6 = VAR3 && !VAR7;
always @(posedge clk) begin
if (VAR3) begin
VAR7 <= !VAR2;
end
if (rst) begin
VAR7 <= 1'b0;
end
end
endmodule
|
mit
|
bpervan/zedboard
|
LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_trace_buffer.v
| 8,668 |
module MODULE1 #
(
parameter integer VAR28 = 128,
parameter integer VAR30 = 0,
parameter integer VAR1 = 12
)
(
input wire VAR29,
input wire VAR16,
input wire VAR13,
input wire [3:0] VAR6,
input wire [31:0] VAR24,
output wire VAR7,
output wire [3:0] VAR9,
output wire [31:0] VAR12
);
function integer VAR4 (input integer VAR19);
integer VAR14;
integer VAR5;
begin
VAR5 = 0;
for(VAR14=VAR19; VAR14 > 0; VAR14 = VAR14>>1)
VAR4 = VAR5;
VAR5=VAR5+1;
end
endfunction
localparam VAR23 = VAR4(VAR28-1);
wire [31:0] VAR18;
reg [31:0] VAR25; reg [31:0] VAR3;
reg [31:0] VAR26;
reg [3:0] VAR22;
reg [31:0] VAR27 [VAR28-1:0];
reg [4:0] VAR17;
reg [VAR23-1:0] VAR20;
reg [VAR23-1:0] VAR21;
reg VAR15;
wire VAR31;
wire VAR10;
reg VAR11;
assign VAR18 = 32'h0;
always @(posedge VAR29) begin
if((VAR16 == 1'b1)) begin
VAR22 <= VAR18;
end
else begin
VAR22 <= VAR6;
end
end
assign VAR9 = VAR22;
generate
if (VAR30 == 0) begin : VAR2
always @(posedge VAR29) begin
if (VAR13 == 1'b1 && VAR11 != 1'b1) begin
VAR27[VAR20] <= VAR24;
end
end
always @(posedge VAR29) begin
if(VAR16 == 1'b1) begin
VAR20 <= {VAR23{1'b0}};
end
else if(VAR13 ) begin
if(VAR20 == (VAR28 - 1)) begin
if (VAR31) begin
VAR20 <= {VAR23{1'b0}};
end
end
else begin
VAR20 <= VAR20 + 1;
end
end
end
end else begin : VAR8
always @(posedge VAR29) begin
if((VAR16 == 1'b1)) begin
VAR3 <= VAR18;
VAR25 <= VAR18;
end
else begin
VAR3 <= VAR24;
VAR25 <= (~VAR3 & VAR24);
end
end
always @(posedge VAR29) begin
if(|(VAR25) == 1'b1 && VAR11 != 1'b1) begin
VAR27[VAR20] <= VAR25;
end
end
always @(posedge VAR29) begin
if(VAR16 == 1'b1) begin
VAR20 <= {VAR23{1'b0}};
end
else if(|(VAR25) == 1'b1) begin
if(VAR20 == (VAR28 - 1)) begin
if (VAR31) begin
VAR20 <= {VAR23{1'b0}};
end
end
else begin
VAR20 <= VAR20 + 1;
end
end
end
end
endgenerate
always @(posedge VAR29) begin
VAR26 <= VAR27[VAR21] ;
end
always @(posedge VAR29) begin
if(VAR16 == 1'b1) begin
VAR21 <= {VAR23{1'b0}};
VAR15 <= 1'b0;
end
else if(VAR31 != 1'b1 && VAR17 == 5'b00000 && VAR15 == 1'b0) begin
VAR15 <= 1'b1;
if(VAR21 == (VAR28 - 1)) begin
VAR21 <= {VAR23{1'b0}};
end
else begin
VAR21 <= VAR21 + 1;
end
end
else begin
VAR15 <= 1'b0;
end
end
always @(posedge VAR29) begin
if(VAR16 == 1'b1) begin
VAR17 <= 5'h0;
end
else if (VAR15 == 1'b1) begin
VAR17 <= VAR1-1;
end
else if(VAR17 != 5'h0) begin
VAR17 <= VAR17 - 1;
end
end
assign VAR31 = (VAR20 == VAR21) ? 1'b1 : 1'b0;
assign VAR10 = (VAR20 == VAR28-1)? 1'b1 : 1'b0;
always @(posedge VAR29) begin
if(VAR16 == 1'b1) begin
VAR11 <= 1'b0;
end
else if (VAR31) begin
VAR11 <= 1'b0;
end else begin
VAR11 <= VAR10;
end
end
assign VAR12 = VAR26;
assign VAR7 = VAR15;
endmodule
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/sparc/tlu/rtl/tlu_mmu_dp.v
| 54,613 |
module MODULE1 (
VAR12, VAR30, VAR189,
VAR102, VAR26,
VAR49, VAR191, VAR48,
VAR23, VAR14, VAR188,
VAR94, VAR43, VAR9, VAR61,
VAR157, VAR224, VAR74,
VAR34, VAR171, VAR164, VAR110,
VAR47, VAR190, VAR28,
VAR96, VAR98, VAR123,
VAR145, VAR59,
VAR92, VAR50,VAR244, VAR84,
VAR71,
VAR142, VAR218, VAR52,
VAR172, VAR87, VAR22,
VAR68, VAR42,
VAR216, VAR141, VAR36,
VAR101, VAR7, VAR4, VAR25, VAR63,
VAR174, VAR198, VAR117,
VAR170, VAR183, VAR134, VAR19
) ;
input VAR34 ; input VAR171 ;
input [3:0] VAR164 ;
input [3:0] VAR110 ;
input VAR47 ;
input [3:0] VAR190 ;
input [12:0] VAR96 ;
input [12:0] VAR98 ;
input [2:0] VAR123 ;
input [63:59] VAR145 ;
input [47:0] VAR59 ;
input [47:0] VAR92 ;
input [47:0] VAR50 ;
input [47:13] VAR244 ;
input [47:13] VAR84 ;
input [3:0] VAR71 ;
input [2:0] VAR142 ;
input [4:0] VAR218 ;
input VAR19 ;
input VAR52 ;
input [2:0] VAR172 ;
input [155:6] VAR87 ;
input VAR22 ;
input [23:0] VAR68 ;
input [23:0] VAR42 ;
input [2:0] VAR216 ; input VAR141 ;
input [3:0] VAR36 ; input [3:0] VAR101 ; input [2:0] VAR7 ; input VAR174 ; input VAR198 ; input VAR117 ;
input VAR28 ;
input VAR170 ;
input VAR4 ;
input VAR63 ;
input VAR25 ;
input VAR183 ;
input VAR134 ;
output VAR224 ;
output VAR12 ;
output [3:0] VAR30 ;
output [47:13] VAR189 ; output VAR102 ;
output [3:0] VAR26 ;
output [58:0] VAR49 ;
output [42:0] VAR191 ;
output [58:0] VAR48 ;
output [42:0] VAR23 ;
output [5:0] VAR9 ; output [40:0] VAR14 ;
output [3:0] VAR188 ;
output [3:0] VAR94 ;
output [12:0] VAR61 ;
output [63:0] VAR157 ;
output [47:13] VAR74 ;
output [155:0] VAR43 ;
wire [47:0] VAR8,VAR219 ;
wire [63:59] VAR54 ;
wire [39:8] VAR231 ;
wire [6:1] VAR212 ;
wire [63:0] VAR150 ;
wire [47:13] VAR10 ;
wire [23:0] VAR138,VAR122 ;
wire [23:0] VAR143,VAR194 ;
wire [23:0] VAR192,VAR228 ;
wire [23:0] VAR5,VAR169 ;
wire [23:0] VAR158,VAR6 ;
wire [47:0] VAR35 ;
wire [47:0] VAR11,VAR106 ;
wire [47:0] VAR18,VAR105 ;
wire [23:0] VAR51 ;
wire [23:0] VAR173 ;
wire [40:0] VAR136 ;
wire [47:0] VAR64 ;
wire [41:0] VAR195 ;
wire VAR161, VAR120 ;
wire [40:0] VAR115 ;
wire [47:0] VAR90 ;
wire [12:0] VAR27,VAR144 ;
wire [58:55] VAR168 ;
wire [53:0] VAR70 ;
wire [58:55] VAR186 ;
wire [53:0] VAR233 ;
wire [41:0] VAR135 ;
wire [47:13] VAR91 ;
wire [47:0] VAR2 ;
wire [47:0] VAR237 ;
wire clk;
assign clk = VAR4;
wire VAR31;
VAR21 VAR131(.din (VAR25),
.VAR208 (VAR31),
.clk (clk), .VAR134(VAR134), .VAR183(), .VAR224(),
.VAR31 (VAR63));
wire [47:13] VAR153 ;
VAR108 #(35) VAR220 (
.din (VAR84[47:13]),
.VAR208 (VAR153[47:13]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(48) VAR55 (
.din (VAR92[47:0]),
.VAR208 (VAR8[47:0]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(48) VAR180 (
.din (VAR8[47:0]),
.VAR208 (VAR219[47:0]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(35) VAR236 (
.din (VAR244[47:13]),
.VAR208 (VAR91[47:13]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire [4:0] VAR73 ;
wire [47:13] VAR107 ;
VAR108 #(40) VAR88 (
.din ({VAR91[47:13],VAR218[4:0]}),
.VAR208 ({VAR107[47:13],VAR73[4:0]}),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire [2:0] VAR53,VAR226 ;
wire VAR82,VAR222 ;
wire [47:13] VAR197 ;
wire [5:0] VAR45 ;
VAR56 #(41) VAR225 (
.VAR163 ({VAR107[47:13],VAR73[4:0],VAR82}),
.VAR167 ({VAR64[47:13],1'b1,VAR53[2:0],VAR82,VAR82}),
.sel (VAR22),
.dout ({VAR197[47:13],VAR45[5:0]})
);
assign VAR136[40:0] =
{
VAR197[47:28], VAR45[5], VAR197[27:22], VAR45[4], VAR197[21:16], VAR45[3], VAR197[15:13], VAR45[2], VAR45[1], VAR45[0] } ;
wire VAR118 ;
VAR184 VAR3 (
.VAR4 (clk),
.VAR60 (VAR19),
.VAR182 (~VAR134),
.clk (VAR118)
) ;
VAR13 #(41) VAR112 (
.din (VAR136[40:0]),
.VAR208 (VAR115[40:0]),
.VAR31 (VAR52),
.en (~(VAR19)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(41) VAR112 (
.din (VAR136[40:0]),
.VAR208 (VAR115[40:0]),
.VAR31 (VAR52),
.en (~(VAR19)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(41) VAR112 (
.din (VAR136[40:0]),
.VAR208 (VAR115[40:0]),
.VAR31 (VAR52),
.clk (VAR118),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR14[40:0] = VAR115[40:0] ;
VAR24 #(13) VAR99(
.VAR163 (VAR98[12:0]), .VAR167 (13'd0), .VAR176 (VAR96[12:0]), .VAR159 (VAR123[0]),
.VAR177 (VAR123[1]),
.VAR155 (VAR123[2]),
.dout (VAR27[12:0])
);
VAR108 #(13) VAR116 (
.din (VAR27[12:0]),
.VAR208 (VAR144[12:0]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire [15:0] VAR203 ;
assign VAR203[15:0] = VAR219[47:32] & {16{~VAR34}} ;
VAR24 #(48) VAR193(
.VAR163 ({VAR203[15:0],VAR219[31:13],VAR144[12:0]}), .VAR167 ({VAR153[47:13],VAR144[12:0]}), .VAR176 (VAR59[47:0]), .VAR159 (VAR172[0]),
.VAR177 (VAR172[1]),
.VAR155 (VAR172[2]),
.dout (VAR90[47:0])
);
assign VAR61[12:0] = VAR144[12:0] ;
wire [47:0] VAR86 ;
VAR56 #(48) VAR103(
.VAR163 ({VAR203[15:0],VAR219[31:0]}), .VAR167 (VAR59[47:0]), .sel (VAR171),
.dout (VAR86[47:0])
);
assign VAR43[155:0] =
{VAR59[47:12],8'd0,
VAR59[3:0], VAR59[47:12],8'd0,
VAR59[3:0], VAR90[47:0], VAR59[10:8], VAR59[2:0], 6'd0};
assign VAR10[47:13] = VAR87[VAR185:VAR40+13] ;
assign VAR189[47:13] = VAR10[47:13] ;
assign VAR150[63:0] =
{3'b000,
VAR237[12:0], 6'b000000,
{16{VAR237[47]}}, VAR237[47:22]};
wire [47:0] VAR213, VAR78 ;
assign VAR213[47:0] = VAR87[VAR201:VAR202] ;
assign VAR78[47:0] = VAR87[VAR178:VAR156] ;
assign VAR12 = VAR213[12] ;
assign VAR30[3:0] = VAR213[3:0] ;
wire [5:0] VAR206 ;
assign VAR9[5:0] = VAR87[VAR44:VAR97] ;
VAR108 #(6) VAR121 (
.din (VAR87[VAR44:VAR97]),
.VAR208 (VAR206[5:0]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR102 = VAR78[12] ;
assign VAR26[3:0] = VAR78[3:0] ;
wire [47:13] VAR39 ;
assign VAR39[47:13] =
VAR170 ? VAR213[47:13] : VAR78[47:13] ;
VAR108 #(35) VAR240 (
.din (VAR39[47:13]),
.VAR208 (VAR74[47:13]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR54[63:59] = VAR145[63:59] ;
assign VAR231[39:8] = VAR59[39:8] ;
assign VAR212[6:1] = VAR59[6:1] ;
assign VAR64[47:0] = VAR87[VAR185:VAR40] ;
wire VAR67,VAR119 ;
assign VAR67 =
VAR54[63] ;
wire VAR69,VAR80 ;
assign VAR69 =
VAR117 ? VAR212[6] : VAR54[61] ;
VAR184 VAR243 (
.VAR4 (clk),
.VAR60 (VAR28),
.VAR182 (~VAR134),
.clk (VAR179)
) ;
VAR151 #(10) VAR38 (
.din ({VAR67,VAR69,VAR142[2:0],
VAR216[2:0],VAR141,VAR174}),
.VAR208 ({VAR119,VAR80,VAR53[2:0],
VAR226[2:0],VAR82,VAR222}),
.en (~(VAR28)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(10) VAR38 (
.din ({VAR67,VAR69,VAR142[2:0],
VAR216[2:0],VAR141,VAR174}),
.VAR208 ({VAR119,VAR80,VAR53[2:0],
VAR226[2:0],VAR82,VAR222}),
.en (~(VAR28)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(10) VAR38 (
.din ({VAR67,VAR69,VAR142[2:0],
VAR216[2:0],VAR141,VAR174}),
.VAR208 ({VAR119,VAR80,VAR53[2:0],
VAR226[2:0],VAR82,VAR222}),
.clk (VAR179),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR70[53:0] =
{VAR64[47:22], VAR53[2], VAR119, VAR80, 1'b1, VAR64[21:16], VAR53[1], VAR64[15:13], VAR53[0], VAR64[12:0] };
assign VAR168[58:55] = {VAR226[2:0],VAR82};
wire [41:0] VAR227 ;
assign VAR227[41:0] =
{VAR231[39:22], ~VAR142[2], VAR231[21:16], ~VAR142[1], VAR231[15:13], ~VAR142[0], VAR54[63], VAR54[60], VAR54[59], VAR212[6], VAR212[5:4], VAR212[3], VAR212[2], VAR212[1], 3'b000}; wire [41:0] VAR162 ;
assign VAR162[41:0] =
{VAR231[39:22], ~VAR142[2], VAR231[21:16], ~VAR142[1], VAR231[15:13], ~VAR142[0], VAR54[63], VAR54[62], VAR231[12], VAR54[61], VAR231[10:9], VAR231[11], VAR231[8], VAR212[6], 3'b000}; assign VAR135[41:0] =
VAR117 ? VAR227[41:0] : VAR162[41:0];
VAR184 VAR221 (
.VAR4 (clk),
.VAR60 (VAR19),
.VAR182 (~VAR134),
.clk (VAR161)
) ;
VAR151 #(58) VAR148 (
.din ({VAR168[58:55],VAR70[53:0]}),
.VAR208 ({VAR186[58:55],VAR233[53:0]}),
.en (~(VAR19)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(58) VAR148 (
.din ({VAR168[58:55],VAR70[53:0]}),
.VAR208 ({VAR186[58:55],VAR233[53:0]}),
.en (~(VAR19)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(58) VAR148 (
.din ({VAR168[58:55],VAR70[53:0]}),
.VAR208 ({VAR186[58:55],VAR233[53:0]}),
.clk (VAR161),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR184 VAR100 (
.VAR4 (clk),
.VAR60 (VAR28),
.VAR182 (~VAR134),
.clk (VAR120)
) ;
VAR151 #(42) VAR127 (
.din (VAR135[41:0]),
.VAR208 (VAR195[41:0]),
.en (~(VAR28)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(42) VAR127 (
.din (VAR135[41:0]),
.VAR208 (VAR195[41:0]),
.en (~(VAR28)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(42) VAR127 (
.din (VAR135[41:0]),
.VAR208 (VAR195[41:0]),
.clk (VAR120),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire VAR242,VAR104 ;
wire VAR137,VAR210 ;
assign VAR48[58:0] = {VAR186[58:55],VAR137,VAR233[53:0]} ;
assign VAR49[58:0] = {VAR186[58:55],VAR137,VAR233[53:0]} ;
assign VAR23[42:0] = {VAR210,VAR195[41:0]} ;
assign VAR191[42:0] = {VAR210,VAR195[41:0]} ;
wire VAR154,VAR75 ;
VAR151 #(1) VAR1 (
.din (VAR222),
.VAR208 (VAR154),
.en (~(VAR19)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(1) VAR1 (
.din (VAR222),
.VAR208 (VAR154),
.en (~(VAR19)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(1) VAR1 (
.din (VAR222),
.VAR208 (VAR154),
.clk (VAR161),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(1) VAR95 (
.din (VAR198),
.VAR208 (VAR75),
.en (~(VAR28)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(1) VAR95 (
.din (VAR198),
.VAR208 (VAR75),
.en (~(VAR28)), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(1) VAR95 (
.din (VAR198),
.VAR208 (VAR75),
.clk (VAR120),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR242 =
VAR154^(^{VAR186[58:55],
VAR233[53:27],VAR233[25],VAR233[23:0]}) ;
assign VAR104 = VAR75^(^VAR195[41:0]) ;
VAR108 #(2) VAR72 (
.din ({VAR242,VAR104}),
.VAR208 ({VAR137,VAR210}),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire [47:0] VAR132 ;
assign VAR132[47:0] = VAR86[47:0] ;
wire VAR79 ;
VAR184 VAR147 (
.VAR4 (clk),
.VAR60 (VAR110[0]),
.VAR182 (~VAR134),
.clk (VAR79)
) ;
VAR151 #(48) VAR128 (
.din (VAR132[47:0]),
.VAR208 (VAR11[47:0]),
.en (~(VAR110[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(48) VAR128 (
.din (VAR132[47:0]),
.VAR208 (VAR11[47:0]),
.en (~(VAR110[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(48) VAR128 (
.din (VAR132[47:0]),
.VAR208 (VAR11[47:0]),
.clk (VAR79),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire VAR230 ;
VAR184 VAR126 (
.VAR4 (clk),
.VAR60 (VAR110[1]),
.VAR182 (~VAR134),
.clk (VAR230)
) ;
VAR151 #(48) VAR109 (
.din (VAR132[47:0]),
.VAR208 (VAR106[47:0]),
.en (~(VAR110[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(48) VAR109 (
.din (VAR132[47:0]),
.VAR208 (VAR106[47:0]),
.en (~(VAR110[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(48) VAR109 (
.din (VAR132[47:0]),
.VAR208 (VAR106[47:0]),
.clk (VAR230),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire VAR62 ;
VAR184 VAR114 (
.VAR4 (clk),
.VAR60 (VAR110[2]),
.VAR182 (~VAR134),
.clk (VAR62)
) ;
VAR151 #(48) VAR199 (
.din (VAR132[47:0]),
.VAR208 (VAR18[47:0]),
.en (~(VAR110[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(48) VAR199 (
.din (VAR132[47:0]),
.VAR208 (VAR18[47:0]),
.en (~(VAR110[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(48) VAR199 (
.din (VAR132[47:0]),
.VAR208 (VAR18[47:0]),
.clk (VAR62),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire VAR215 ;
VAR184 VAR223 (
.VAR4 (clk),
.VAR60 (VAR110[3]),
.VAR182 (~VAR134),
.clk (VAR215)
) ;
VAR151 #(48) VAR83 (
.din (VAR132[47:0]),
.VAR208 (VAR105[47:0]),
.en (~(VAR110[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(48) VAR83 (
.din (VAR132[47:0]),
.VAR208 (VAR105[47:0]),
.en (~(VAR110[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(48) VAR83 (
.din (VAR132[47:0]),
.VAR208 (VAR105[47:0]),
.clk (VAR215),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR205 #(48) VAR16(
.VAR163(VAR11[47:0]),
.VAR167(VAR106[47:0]),
.VAR176(VAR18[47:0]),
.VAR81(VAR105[47:0]),
.VAR159 (VAR71[0]),
.VAR177 (VAR71[1]),
.VAR155 (VAR71[2]),
.VAR111 (VAR71[3]),
.dout(VAR35[47:0])
);
VAR56 #(24) VAR149(
.VAR163 (VAR42[23:0]),
.VAR167 ({VAR59[23:16], 2'b00,VAR59[13:0]}),
.sel (VAR171),
.dout (VAR51[23:0])
);
wire VAR85 ;
VAR184 VAR66 (
.VAR4 (clk),
.VAR60 (VAR164[0]),
.VAR182 (~VAR134),
.clk (VAR85)
) ;
VAR151 #(23) VAR196 (
.din (VAR51[23:1]),
.VAR208 (VAR143[23:1]),
.en (~(VAR164[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR196 (
.din (VAR51[23:1]),
.VAR208 (VAR143[23:1]),
.en (~(VAR164[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR196 (
.din (VAR51[23:1]),
.VAR208 (VAR143[23:1]),
.clk (VAR85),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR20 (
.din (VAR51[0]),
.VAR208 (VAR143[0]),
.VAR31 (VAR31),
.en (~(VAR164[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR20 (
.din (VAR51[0]),
.VAR208 (VAR143[0]),
.VAR31 (VAR31),
.en (~(VAR164[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR20 (
.din (VAR51[0]),
.VAR208 (VAR143[0]),
.VAR31 (VAR31),
.clk (VAR85),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR188[0] = VAR143[0] ;
wire VAR165 ;
VAR184 VAR239 (
.VAR4 (clk),
.VAR60 (VAR164[1]),
.VAR182 (~VAR134),
.clk (VAR165)
) ;
VAR151 #(23) VAR200 (
.din (VAR51[23:1]),
.VAR208 (VAR192[23:1]),
.en (~(VAR164[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR200 (
.din (VAR51[23:1]),
.VAR208 (VAR192[23:1]),
.en (~(VAR164[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR200 (
.din (VAR51[23:1]),
.VAR208 (VAR192[23:1]),
.clk (VAR165),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR124 (
.din (VAR51[0]),
.VAR208 (VAR192[0]),
.VAR31 (VAR31),
.en (~(VAR164[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR124 (
.din (VAR51[0]),
.VAR208 (VAR192[0]),
.VAR31 (VAR31),
.en (~(VAR164[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR124 (
.din (VAR51[0]),
.VAR208 (VAR192[0]),
.VAR31 (VAR31),
.clk (VAR165),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR188[1] = VAR192[0] ;
wire VAR209 ;
VAR184 VAR129 (
.VAR4 (clk),
.VAR60 (VAR164[2]),
.VAR182 (~VAR134),
.clk (VAR209)
) ;
VAR151 #(23) VAR175 (
.din (VAR51[23:1]),
.VAR208 (VAR5[23:1]),
.en (~(VAR164[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR175 (
.din (VAR51[23:1]),
.VAR208 (VAR5[23:1]),
.en (~(VAR164[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR175 (
.din (VAR51[23:1]),
.VAR208 (VAR5[23:1]),
.clk (VAR209),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR166 (
.din (VAR51[0]),
.VAR208 (VAR5[0]),
.VAR31 (VAR31),
.en (~(VAR164[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR166 (
.din (VAR51[0]),
.VAR208 (VAR5[0]),
.VAR31 (VAR31),
.en (~(VAR164[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR166 (
.din (VAR51[0]),
.VAR208 (VAR5[0]),
.VAR31 (VAR31),
.clk (VAR209),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR188[2] = VAR5[0] ;
wire VAR133 ;
VAR184 VAR58 (
.VAR4 (clk),
.VAR60 (VAR164[3]),
.VAR182 (~VAR134),
.clk (VAR133)
) ;
VAR151 #(23) VAR234 (
.din (VAR51[23:1]),
.VAR208 (VAR158[23:1]),
.en (~(VAR164[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR234 (
.din (VAR51[23:1]),
.VAR208 (VAR158[23:1]),
.en (~(VAR164[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR234 (
.din (VAR51[23:1]),
.VAR208 (VAR158[23:1]),
.clk (VAR133),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR139 (
.din (VAR51[0]),
.VAR208 (VAR158[0]),
.VAR31 (VAR31),
.en (~(VAR164[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR139 (
.din (VAR51[0]),
.VAR208 (VAR158[0]),
.VAR31 (VAR31),
.en (~(VAR164[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR139 (
.din (VAR51[0]),
.VAR208 (VAR158[0]),
.VAR31 (VAR31),
.clk (VAR133),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR188[3] = VAR158[0] ;
VAR204 #(24) VAR37(
.VAR163 (VAR143[23:0]),
.VAR167 (VAR192[23:0]),
.VAR176 (VAR5[23:0]),
.VAR81 (VAR158[23:0]),
.VAR29 (~VAR71[0]),
.VAR130 (~VAR71[1]),
.VAR207 (~VAR71[2]),
.VAR15 (~VAR71[3]),
.dout (VAR138[23:0])
);
VAR56 #(24) VAR77(
.VAR163 (VAR68[23:0]),
.VAR167 ({VAR59[23:16], 2'b00,VAR59[13:0]}),
.sel (VAR47),
.dout (VAR173[23:0])
);
wire VAR113 ;
VAR184 VAR211 (
.VAR4 (clk),
.VAR60 (VAR190[0]),
.VAR182 (~VAR134),
.clk (VAR113)
) ;
VAR151 #(23) VAR160 (
.din (VAR173[23:1]),
.VAR208 (VAR194[23:1]),
.en (~(VAR190[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR160 (
.din (VAR173[23:1]),
.VAR208 (VAR194[23:1]),
.en (~(VAR190[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR160 (
.din (VAR173[23:1]),
.VAR208 (VAR194[23:1]),
.clk (VAR113),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR93 (
.din (VAR173[0]),
.VAR208 (VAR194[0]),
.VAR31 (VAR31), .en (~(VAR190[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR93 (
.din (VAR173[0]),
.VAR208 (VAR194[0]),
.VAR31 (VAR31), .en (~(VAR190[0])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR93 (
.din (VAR173[0]),
.VAR208 (VAR194[0]),
.VAR31 (VAR31), .clk (VAR113),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR94[0] = VAR194[0] ;
wire VAR217 ;
VAR184 VAR187 (
.VAR4 (clk),
.VAR60 (VAR190[1]),
.VAR182 (~VAR134),
.clk (VAR217)
) ;
VAR151 #(23) VAR41 (
.din (VAR173[23:1]),
.VAR208 (VAR228[23:1]),
.en (~(VAR190[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR41 (
.din (VAR173[23:1]),
.VAR208 (VAR228[23:1]),
.en (~(VAR190[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR41 (
.din (VAR173[23:1]),
.VAR208 (VAR228[23:1]),
.clk (VAR217),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR125 (
.din (VAR173[0]),
.VAR208 (VAR228[0]),
.VAR31 (VAR31), .en (~(VAR190[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR125 (
.din (VAR173[0]),
.VAR208 (VAR228[0]),
.VAR31 (VAR31), .en (~(VAR190[1])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR125 (
.din (VAR173[0]),
.VAR208 (VAR228[0]),
.VAR31 (VAR31), .clk (VAR217),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR94[1] = VAR228[0] ;
wire VAR32 ;
VAR184 VAR17 (
.VAR4 (clk),
.VAR60 (VAR190[2]),
.VAR182 (~VAR134),
.clk (VAR32)
) ;
VAR151 #(23) VAR152 (
.din (VAR173[23:1]),
.VAR208 (VAR169[23:1]),
.en (~(VAR190[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR152 (
.din (VAR173[23:1]),
.VAR208 (VAR169[23:1]),
.en (~(VAR190[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR152 (
.din (VAR173[23:1]),
.VAR208 (VAR169[23:1]),
.clk (VAR32),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR140 (
.din (VAR173[0]),
.VAR208 (VAR169[0]),
.VAR31 (VAR31), .en (~(VAR190[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR140 (
.din (VAR173[0]),
.VAR208 (VAR169[0]),
.VAR31 (VAR31), .en (~(VAR190[2])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR140 (
.din (VAR173[0]),
.VAR208 (VAR169[0]),
.VAR31 (VAR31), .clk (VAR32),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR94[2] = VAR169[0] ;
wire VAR46 ;
VAR184 VAR76 (
.VAR4 (clk),
.VAR60 (VAR190[3]),
.VAR182 (~VAR134),
.clk (VAR46)
) ;
VAR151 #(23) VAR235 (
.din (VAR173[23:1]),
.VAR208 (VAR6[23:1]),
.en (~(VAR190[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR151 #(23) VAR235 (
.din (VAR173[23:1]),
.VAR208 (VAR6[23:1]),
.en (~(VAR190[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR108 #(23) VAR235 (
.din (VAR173[23:1]),
.VAR208 (VAR6[23:1]),
.clk (VAR46),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR146 (
.din (VAR173[0]),
.VAR208 (VAR6[0]),
.VAR31 (VAR31), .en (~(VAR190[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR13 #(1) VAR146 (
.din (VAR173[0]),
.VAR208 (VAR6[0]),
.VAR31 (VAR31), .en (~(VAR190[3])), .clk(clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
VAR238 #(1) VAR146 (
.din (VAR173[0]),
.VAR208 (VAR6[0]),
.VAR31 (VAR31), .clk (VAR46),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
assign VAR94[3] = VAR6[0] ;
VAR204 #(24) VAR57(
.VAR163 (VAR194[23:0]),
.VAR167 (VAR228[23:0]),
.VAR176 (VAR169[23:0]),
.VAR81 (VAR6[23:0]),
.VAR29 (~VAR71[0]),
.VAR130 (~VAR71[1]),
.VAR207 (~VAR71[2]),
.VAR15 (~VAR71[3]),
.dout (VAR122[23:0])
);
VAR24 #(48) VAR89(
.VAR163(VAR213[47:0]), .VAR167(VAR78[47:0]), .VAR176(VAR64[47:0]),
.VAR159(VAR36[1]),
.VAR177(VAR36[2]),
.VAR155(VAR36[3]),
.dout(VAR2[47:0])
);
VAR108 #(48) VAR65 (
.din (VAR2[47:0]),
.VAR208 (VAR237[47:0]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
wire [63:0] VAR181 ;
assign VAR181[63:0] =
VAR36[0] ?
VAR150[63:0] : {{16{VAR237[47]}},VAR237[47:0]} ;
wire [47:0] VAR214 ;
VAR205 #(48) VAR232(
.VAR163({24'd0,VAR138[23:0]}),
.VAR167(VAR35[47:0]),
.VAR176({24'd0,VAR122[23:0]}),
.VAR81({37'd0,VAR206[5:3],5'd0,VAR206[2:0]}),
.VAR159(VAR101[0]),
.VAR177(VAR101[1]),
.VAR155(VAR101[2]),
.VAR111(VAR101[3]),
.dout(VAR214[47:0])
);
wire [63:0] VAR241 ;
VAR24 #(64) VAR33 (
.VAR163 (VAR181[63:0]),
.VAR167 ({{16{VAR214[47]}},VAR214[47:0]}),
.VAR176 ({{16{VAR50[47]}},VAR50[47:0]}),
.VAR159 (VAR7[0]),
.VAR177 (VAR7[1]),
.VAR155 (VAR7[2]),
.dout (VAR241[63:0])
);
VAR108 #(64) VAR229 (
.din (VAR241[63:0]),
.VAR208 (VAR157[63:0]),
.clk (clk),
.VAR134 (1'b0), .VAR183 (), .VAR224 ()
);
endmodule
|
gpl-2.0
|
freecores/zet86
|
soc/vga/rtl/ram2k_b16.v
| 3,246 |
module MODULE1 (clk, rst, VAR11, VAR1, addr, VAR5, VAR13);
input clk;
input rst;
input VAR11;
input VAR1;
input [10:0] addr;
output [7:0] VAR5;
input [7:0] VAR13;
wire VAR4;
VAR7 VAR3 (.VAR8(VAR5),
.VAR2 (VAR4),
.VAR14 (addr),
.VAR6 (clk),
.VAR16 (VAR13),
.VAR10 (VAR4),
.VAR17 (VAR11),
.VAR9 (rst),
.VAR15 (VAR1));
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/bufinv/sky130_fd_sc_hs__bufinv.pp.blackbox.v
| 1,206 |
module MODULE1 (
VAR3 ,
VAR4 ,
VAR2,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2;
input VAR1;
endmodule
|
apache-2.0
|
MarcoVogt/basil
|
firmware/modules/utils/cdc_reset_sync.v
| 1,127 |
module MODULE1 (
input wire VAR10,
input wire VAR7,
input wire VAR3,
output wire VAR8
);
wire VAR9;
reg [1:0] VAR2;
always@(posedge VAR10) begin
VAR2[0] <= VAR7;
VAR2[1] <= VAR2[0];
end
reg VAR5;
VAR4 VAR5 = 0; always@(posedge VAR10) begin
if (VAR2[1])
VAR5 <= 1;
end
else if (VAR9)
VAR5 <= 0;
end
reg [2:0] VAR1;
always@(posedge VAR3) begin
VAR1[0] <= VAR5;
VAR1[1] <= VAR1[0];
VAR1[2] <= VAR1[1];
end
assign VAR8 = VAR1[2];
reg [1:0] VAR6;
always@(posedge VAR10) begin
VAR6[0] <= VAR1[2];
VAR6[1] <= VAR6[0];
end
assign VAR9 = VAR6[1];
endmodule
|
bsd-3-clause
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_fsb_node_level_shift_fsb_domain.v
| 3,332 |
module MODULE1 #(parameter VAR27(VAR28 ))
(
input VAR10,
input VAR25,
input VAR13,
output VAR24,
output VAR16,
output VAR15,
output [VAR28-1:0] VAR4,
input VAR19,
input VAR1,
input [VAR28-1:0] VAR14,
output VAR9,
output VAR33,
output [VAR28-1:0] VAR29,
input VAR11,
input VAR12,
input [VAR28-1:0] VAR22,
output VAR20
);
VAR21 #(.VAR17(1)) VAR32
(
.VAR23(1'b1),
.VAR30(VAR25),
.VAR6(VAR24)
);
VAR21 #(.VAR17(1)) VAR7
(
.VAR23(1'b1),
.VAR30(VAR13),
.VAR6(VAR16)
);
VAR8 #(.VAR17(1)) VAR26
(
.VAR3(VAR10),
.VAR30(VAR12),
.VAR6(VAR15)
);
VAR8 #(.VAR17(VAR28)) VAR18
(
.VAR3(VAR10),
.VAR30(VAR22),
.VAR6(VAR4)
);
VAR21 #(.VAR17(1)) VAR31
(
.VAR23(VAR10),
.VAR30(VAR19),
.VAR6(VAR20)
);
VAR21 #(.VAR17(1)) VAR34
(
.VAR23(VAR10),
.VAR30(VAR1),
.VAR6(VAR33)
);
VAR21 #(.VAR17(VAR28)) VAR2
(
.VAR23(VAR10),
.VAR30(VAR14),
.VAR6(VAR29)
);
VAR8 #(.VAR17(1)) VAR5
(
.VAR3(VAR10),
.VAR30(VAR11),
.VAR6(VAR9)
);
endmodule
|
bsd-3-clause
|
f3zz3h/Embedded-Co-Design
|
ts7300_top_restored/wb32_blockram.v
| 4,912 |
module MODULE1(
VAR23,
VAR24,
VAR15,
VAR21,
VAR40,
VAR6,
VAR10,
VAR18,
VAR26,
VAR13,
VAR2,
VAR27,
VAR39,
VAR5,
VAR20,
VAR30,
VAR4,
VAR37
);
input VAR23, VAR24;
input [10:0] VAR15, VAR2;
input [31:0] VAR21, VAR27;
input VAR6, VAR5, VAR10, VAR20, VAR26, VAR4;
input [3:0] VAR13, VAR37;
output [31:0] VAR40, VAR39;
output reg VAR18, VAR30;
parameter VAR17 = 1'b0;
reg [31:0] VAR34;
reg [10:0] VAR25, VAR19;
wire [31:0] VAR28;
reg [3:0] VAR11;
VAR3 VAR33(
.VAR22(VAR23),
.VAR35(VAR34[7:0]),
.VAR31(VAR25),
.VAR14(VAR19),
.VAR41(VAR11[0]),
.VAR36(VAR28[7:0])
);
VAR3 VAR8(
.VAR22(VAR23),
.VAR35(VAR34[15:8]),
.VAR31(VAR25),
.VAR14(VAR19),
.VAR41(VAR11[1]),
.VAR36(VAR28[15:8])
);
VAR3 VAR16(
.VAR22(VAR23),
.VAR35(VAR34[23:16]),
.VAR31(VAR25),
.VAR14(VAR19),
.VAR41(VAR11[2]),
.VAR36(VAR28[23:16])
);
VAR3 VAR38(
.VAR22(VAR23),
.VAR35(VAR34[31:24]),
.VAR31(VAR25),
.VAR14(VAR19),
.VAR41(VAR11[3]),
.VAR36(VAR28[31:24])
);
reg VAR12 = 1'b0;
reg VAR32 = 1'b0;
reg VAR1, VAR7, VAR29, VAR9;
always @(VAR12 or VAR32 or VAR15 or VAR2 or VAR21 or
VAR27 or VAR13 or VAR37 or VAR12 or VAR32 or
VAR9 or VAR29 or VAR17) begin
if (VAR12) VAR25 = VAR2;
end
else VAR25 = VAR15;
VAR11 = 4'b0000;
if (VAR32) begin
VAR19 = VAR2;
if (VAR17) begin
VAR34 = {VAR27[7:0], VAR27[15:8], VAR27[23:16],
VAR27[31:24]};
if (VAR9) VAR11 = {VAR37[0], VAR37[1], VAR37[2],
VAR37[3]};
end else begin
VAR34 = VAR27;
if (VAR9) VAR11 = VAR37;
end
end else begin
VAR19 = VAR15;
VAR34 = VAR21;
if (VAR29) VAR11 = VAR13;
end
end
assign VAR40 = VAR28;
assign VAR39 = VAR17 ? {VAR28[7:0],
VAR28[15:8], VAR28[23:16], VAR28[31:24]} :
VAR28;
always @(VAR6 or VAR10 or VAR26 or VAR24 or
VAR5 or VAR20 or VAR4 or VAR12 or VAR32 or
VAR18 or VAR30) begin
VAR1 = VAR6 && VAR10 && !VAR26 && !VAR18;
VAR7 = VAR5 && VAR20 && !VAR4 && !VAR30;
VAR29 = VAR6 && VAR10 && VAR26 && !VAR18;
VAR9 = VAR5 && VAR20 && VAR4 && !VAR30;
if (VAR12) begin
if (VAR1 && !VAR7) VAR12 = 1'b0;
end
else VAR12 = 1'b1;
end else begin
if (!VAR1 && VAR7) VAR12 = 1'b1;
end
else VAR12 = 1'b0;
end
if (VAR32) begin
if (VAR29 && !VAR9) VAR32 = 1'b0;
end
else VAR32 = 1'b1;
end else begin
if (!VAR29 && VAR9) VAR32 = 1'b1;
end
else VAR32 = 1'b0;
end
if (VAR24) begin
VAR12 = 1'b0;
VAR32 = 1'b0;
end
end
always @(posedge VAR23) begin
VAR18 <= 1'b0;
VAR30 <= 1'b0;
if (VAR1 && !VAR12 && !VAR18) begin
VAR18 <= 1'b1;
end else if (VAR7 && VAR12 && !VAR30) begin
VAR30 <= 1'b1;
end
if (VAR29 && !VAR32 && !VAR18) begin
VAR18 <= 1'b1;
end else if (VAR9 && VAR32 && !VAR30) begin
VAR30 <= 1'b1;
end
end
endmodule
|
gpl-2.0
|
parallella/oh
|
enoc/hdl/emesh_readback.v
| 3,185 |
module MODULE1 (
VAR17, VAR14, VAR5,
VAR2, clk, VAR18, VAR26, VAR21, VAR12
);
parameter VAR15 = 32; parameter VAR25 = 104;
input VAR2; input clk;
input VAR18; input [VAR25-1:0] VAR26; output VAR17;
input [63:0] VAR21;
output VAR14; output [VAR25-1:0] VAR5; input VAR12;
wire [12:0] VAR20; wire [VAR15-1:0] VAR24; wire [1:0] VAR8; wire [VAR15-1:0] VAR6; wire [VAR15-1:0] VAR10; wire VAR23;
reg [1:0] VAR3;
reg [4:0] VAR13;
reg [VAR15-1:0] VAR16;
wire [VAR15-1:0] VAR19;
wire [VAR15-1:0] VAR11;
reg VAR14;
VAR22 #(.VAR15(VAR15),
.VAR25(VAR25))
VAR1 (
.VAR23 (VAR23),
.VAR8 (VAR8[1:0]),
.VAR20 (VAR20[12:0]),
.VAR6 (VAR6[VAR15-1:0]),
.VAR10 (VAR10[VAR15-1:0]),
.VAR24 (VAR24[VAR15-1:0]),
.VAR26 (VAR26[VAR25-1:0]));
always @ (posedge clk or negedge VAR2)
if(!VAR2)
VAR14 <= 1'b0;
else if(VAR12)
VAR14 <= VAR18 & ~VAR23;
always @ (posedge clk)
if(VAR12 & VAR18 & ~VAR23)
begin
VAR3[1:0] <= VAR8[1:0];
VAR13[4:0] <= VAR20[4:0];
VAR16[VAR15-1:0] <= VAR10[VAR15-1:0];
end
assign VAR19[VAR15-1:0] = VAR21[31:0];
assign VAR11[VAR15-1:0] = VAR21[63:32];
assign VAR17 = VAR12;
VAR9 #(.VAR15(VAR15),
.VAR25(VAR25))
VAR4 (.VAR7 (1'b1),
.VAR5 (VAR5[VAR25-1:0]),
.VAR3 (VAR3[1:0]),
.VAR13 (VAR13[12:0]),
.VAR16 (VAR16[VAR15-1:0]),
.VAR19 (VAR19[VAR15-1:0]),
.VAR11 (VAR11[VAR15-1:0]));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/decaphe/sky130_fd_sc_ls__decaphe_8.v
| 1,899 |
module MODULE2 (
VAR4,
VAR6,
VAR1 ,
VAR3
);
input VAR4;
input VAR6;
input VAR1 ;
input VAR3 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR4;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR3 ;
VAR2 VAR5 ();
endmodule
|
apache-2.0
|
eda-globetrotter/PicenoDecoders
|
extra_credit/syn/netlist/spare/decoder.v
| 1,923 |
module MODULE1 (VAR5,VAR3);
output reg [10:0] VAR3;
input [14:0] VAR5;
reg [3:0] VAR2;
reg [3:0] VAR6;
reg [3:0] VAR4;
reg [14:0] VAR1;
always @(*)
begin
VAR2[0]=VAR5[2]^VAR5[4]^VAR5[6]^VAR5[8]^VAR5[10]^VAR5[12]^VAR5[14];
VAR2[1]=VAR5[2]^VAR5[5]^VAR5[6]^VAR5[9]^VAR5[10]^VAR5[13]^VAR5[14];
VAR2[2]=VAR5[4]^VAR5[5]^VAR5[6]^VAR5[11]^VAR5[12]^VAR5[13]^VAR5[14];
VAR2[3]=VAR5[8]^VAR5[9]^VAR5[10]^VAR5[11]^VAR5[12]^VAR5[13]^VAR5[14];
VAR6[0] = VAR5[0]^VAR2[0];
VAR6[1] = VAR5[1]^VAR2[1];
VAR6[2] = VAR5[3]^VAR2[2];
VAR6[3] = VAR5[7]^VAR2[3];
VAR1=VAR5;
VAR4=VAR6[0]*1;
VAR4=VAR4+VAR6[1]*2;
VAR4=VAR4+VAR6[2]*4;
VAR4=VAR4+VAR6[3]*8-1;
VAR1[VAR4]=VAR5[VAR4]^1;
VAR3[0]=VAR1[2];
VAR3[1]=VAR1[4];
VAR3[2]=VAR1[5];
VAR3[3]=VAR1[6];
VAR3[4]=VAR1[8];
VAR3[5]=VAR1[9];
VAR3[6]=VAR1[10];
VAR3[7]=VAR1[11];
VAR3[8]=VAR1[12];
VAR3[9]=VAR1[13];
VAR3[10]=VAR1[14];
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a311oi/sky130_fd_sc_ls__a311oi.pp.blackbox.v
| 1,429 |
module MODULE1 (
VAR3 ,
VAR10 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR9 ,
VAR4,
VAR1,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR9 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR7 ;
endmodule
|
apache-2.0
|
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_1_0/mig_wrap_proc_sys_reset_1_0_stub.v
| 1,811 |
module MODULE1(VAR2, VAR4, VAR10,
VAR7, VAR3, VAR9, VAR8, VAR6,
VAR1, VAR5)
;
input VAR2;
input VAR4;
input VAR10;
input VAR7;
input VAR3;
output VAR9;
output [0:0]VAR8;
output [0:0]VAR6;
output [0:0]VAR1;
output [0:0]VAR5;
endmodule
|
mit
|
rkrajnc/minimig-mist
|
rtl/minimig/userio.v
| 18,836 |
module MODULE1 (
input wire clk, input wire reset, input wire VAR111,
input wire VAR47,
input wire VAR66,
input wire VAR84,
input wire VAR115, input wire VAR101, input wire VAR109,
input wire [ 9-1:1] VAR36, input wire [ 16-1:0] VAR16, output reg [ 16-1:0] VAR32, inout wire VAR108, inout wire VAR85, output wire VAR87, output wire VAR19, input wire VAR18,
input wire VAR55,
input wire [ 8-1:0] VAR34, input wire [ 8-1:0] VAR23, input wire VAR83, input wire [ 3-1:0] VAR14,
input wire VAR40,
input wire VAR88,
input wire [ 6-1:0] VAR21,
input wire VAR57,
input wire VAR112,
input wire [ 2-1:0] VAR102,
input wire [ 8-1:0] VAR62,
input wire [ 8-1:0] VAR68, output reg VAR13, input wire VAR2, input wire VAR89, output wire VAR46, input wire VAR78, output wire VAR58, output wire VAR53, output wire [ 2-1:0] VAR4,
output wire [ 2-1:0] VAR60,
output wire [ 7-1:0] VAR38,
output wire [ 5-1:0] VAR12,
output wire [ 4-1:0] VAR10,
output wire [ 2-1:0] VAR74,
output wire [ 2-1:0] VAR92,
output wire [ 3-1:0] VAR28,
output wire [ 4-1:0] VAR73,
output VAR93, output VAR52,
output VAR37,
output wire VAR49,
output wire VAR80,
output wire [ 24-1:0] VAR107,
output wire VAR77,
output wire [ 2-1:0] VAR27,
output wire [ 16-1:0] VAR63,
input wire [ 16-1:0] VAR95,
input wire VAR24
);
parameter VAR90 = 9'h00a;
parameter VAR8 = 9'h00c;
parameter VAR106 = 9'h1f0;
parameter VAR41 = 9'h016;
parameter VAR26 = 9'h034;
parameter VAR39 = 9'h036;
parameter VAR6 = 8'h69;
parameter VAR9 = 8'h45;
parameter VAR76 = 8'h44;
parameter VAR33 = 8'h4C;
parameter VAR31 = 8'h4D;
parameter VAR75 = 8'h4F;
parameter VAR17 = 8'h4E;
parameter VAR44 = 8'h6c;
parameter VAR30 = 8'h6d;
reg [7:0] VAR56; reg [7:0] VAR99; reg [5:0] VAR86; reg [7:0] VAR51; reg [7:0] VAR59; wire [5:0] VAR22; reg [15:0] VAR7; wire [15:0] VAR45; wire [7:0] VAR79; reg [15:0] VAR67; reg [15:0] VAR71; wire VAR91; wire VAR103; wire VAR3; reg VAR69; reg VAR72; wire VAR54; wire VAR61; reg [7:0] VAR42; wire VAR113; wire [15:0] VAR15; wire [1:0] VAR64;
reg [1:0] VAR65;
wire VAR104;
reg VAR29;
reg VAR50;
always @ (posedge clk) begin
if (VAR111) begin
if (reset)
VAR7 <= 0;
end
else if (VAR36[8:1]==VAR26[8:1])
VAR7[15:0] <= VAR16[15:0];
end
end
reg [4-1:0] VAR105;
always @ (posedge clk) begin
if (VAR111) begin
if (reset)
VAR105 <= 4'h0;
end
else begin
if (VAR104 && (VAR7[15] && !VAR7[14])) begin
VAR105[3] <= VAR116[7];
end else begin
if (!VAR22[5]) VAR105[3] <= 1'b0;
end
else if (VAR7[15] & VAR7[14]) VAR105[3] <= 1'b1;
end
if (VAR7[13]) VAR105[2] <= VAR7[12];
if (VAR104 && (VAR7[11] && !VAR7[10])) begin
VAR105[1] <= VAR110[7];
end else begin
if (!(VAR3&VAR99[5]&VAR88)) VAR105[1] <= 1'b0;
end
else if (VAR7[11] & VAR7[10]) VAR105[1] <= 1'b1;
end
if (!VAR103) VAR105[0] <= 1'b0;
end
else if (VAR7[ 9] & VAR7[ 8]) VAR105[0] <= 1'b1;
end
end
end
reg VAR35;
always @ (posedge clk) begin
if (VAR111) begin
if (reset)
VAR35 <= 1'b1;
end
else
VAR35 <= VAR18;
end
end
wire VAR100 = !(VAR7[9] && !VAR7[8]);
wire VAR114 = VAR18 && !VAR35;
reg [8-1:0] VAR110;
always @ (posedge clk) begin
if (VAR111) begin
if (reset)
VAR110 <= 8'hff;
end
else if (VAR100)
VAR110 <= {VAR99[5], VAR99[4], VAR99[6], VAR99[7], 3'b111, 1'b1};
end
else if (VAR114)
VAR110 <= {VAR110[6:0], 1'b0};
end
end
reg VAR5;
always @ (posedge clk) begin
if (VAR111) begin
if (reset)
VAR5 <= 1'b1;
end
else
VAR5 <= VAR55;
end
end
wire VAR70 = !(VAR7[13] && !VAR7[12]);
wire VAR97 = VAR55 && !VAR5;
reg [8-1:0] VAR116;
always @ (posedge clk) begin
if (VAR111) begin
if (reset)
VAR116 <= 8'hff;
end
else if (VAR70)
VAR116 <= {VAR59[5], VAR59[4], VAR59[6], VAR59[7], 3'b111, 1'b1};
end
else if (VAR97)
VAR116 <= {VAR116[6:0], 1'b0};
end
end
always @ (posedge clk) begin
if (VAR111) begin
if (VAR101)
if (VAR65 == 1)
VAR65 <= VAR64;
end
else
VAR65 <= VAR65 - 2'd1;
end
end
always @ (posedge clk) begin
if (VAR111) begin
if (VAR101)
if (VAR64 == 2'd0)
VAR29 <= 1'b0;
end
else if (VAR65 == 2'd1)
VAR29 <= ~VAR29;
end
end
always @ (posedge clk) begin
if (VAR111) begin
VAR50 <= (~VAR83 ^ VAR86[4]) ? VAR29 : 1'b0;
end
end
always @ begin
if (~VAR72)
if (~VAR86[5] || (~VAR86[3] && ~VAR86[2]))
VAR42 = VAR6;
end
else if (~VAR86[4])
VAR42 = VAR76;
else if (~VAR86[3])
VAR42 = VAR33;
else if (~VAR86[2])
VAR42 = VAR31;
else if (~VAR86[1])
VAR42 = VAR75;
else if (~VAR86[0])
VAR42 = VAR17;
else if (~VAR86[1] && ~VAR86[3])
VAR42 = VAR44;
else if (~VAR86[0] && ~VAR86[2])
VAR42 = VAR30;
else
VAR42 = VAR68;
else
VAR42 = VAR68;
end
always @ (posedge clk) begin
if (VAR111) begin
if (!VAR91 || reset) VAR69 = 0;
end
else if (!VAR56[4]) VAR69 = 1;
end
end
always @ (posedge clk) begin
if (VAR111) begin
if (VAR113)
VAR67[7:0] <= 8'h00;
end
else if ((!VAR99[0] && VAR56[0] && VAR56[2]) || (VAR99[0] && !VAR56[0] && !VAR56[2]) || (!VAR99[2] && VAR56[2] && !VAR56[0]) || (VAR99[2] && !VAR56[2] && VAR56[0]))
VAR67[7:0] <= VAR67[7:0] + 1;
end
else if ((!VAR99[0] && VAR56[0] && !VAR56[2]) || (VAR99[0] && !VAR56[0] && VAR56[2]) || (!VAR99[2] && VAR56[2] && VAR56[0]) || (VAR99[2] && !VAR56[2] && !VAR56[0]))
VAR67[7:0] <= VAR67[7:0] - 1;
else
VAR67[1:0] <= {!VAR99[0], VAR99[0] ^ VAR99[2]};
end
end
always @ (posedge clk) begin
if (VAR111) begin
if (VAR113)
VAR67[15:8] <= 8'h00;
end
else if ((!VAR99[1] && VAR56[1] && VAR56[3]) || (VAR99[1] && !VAR56[1] && !VAR56[3]) || (!VAR99[3] && VAR56[3] && !VAR56[1]) || (VAR99[3] && !VAR56[3] && VAR56[1]))
VAR67[15:8] <= VAR67[15:8] + 1;
end
else if ((!VAR99[1] && VAR56[1] && !VAR56[3]) || (VAR99[1] && !VAR56[1] && VAR56[3]) || (!VAR99[3] && VAR56[3] && VAR56[1]) || (VAR99[3] && !VAR56[3] && !VAR56[1]))
VAR67[15:8] <= VAR67[15:8] - 1;
else
VAR67[9:8] <= {!VAR99[1], VAR99[1] ^ VAR99[3]};
end
end
always @ (posedge clk) begin
if (VAR111) begin
if (VAR113)
VAR71[7:2] <= VAR15[7:2];
end
else if ((!VAR59[0] && VAR51[0] && VAR51[2]) || (VAR59[0] && !VAR51[0] && !VAR51[2]) || (!VAR59[2] && VAR51[2] && !VAR51[0]) || (VAR59[2] && !VAR51[2] && VAR51[0]))
VAR71[7:0] <= VAR71[7:0] + 1;
end
else if ((!VAR59[0] && VAR51[0] && !VAR51[2]) || (VAR59[0] && !VAR51[0] && VAR51[2]) || (!VAR59[2] && VAR51[2] && VAR51[0]) || (VAR59[2] && !VAR51[2] && !VAR51[0]))
VAR71[7:0] <= VAR71[7:0] - 1;
else
VAR71[1:0] <= {!VAR59[0], VAR59[0] ^ VAR59[2]};
end
end
always @ (posedge clk) begin
if (VAR111) begin
if (VAR113)
VAR71[15:10] <= VAR15[15:10];
end
else if ((!VAR59[1] && VAR51[1] && VAR51[3]) || (VAR59[1] && !VAR51[1] && !VAR51[3]) || (!VAR59[3] && VAR51[3] && !VAR51[1]) || (VAR59[3] && !VAR51[3] && VAR51[1]))
VAR71[15:8] <= VAR71[15:8] + 1;
end
else if ((!VAR59[1] && VAR51[1] && !VAR51[3]) || (VAR59[1] && !VAR51[1] && VAR51[3]) || (!VAR59[3] && VAR51[3] && VAR51[1]) || (VAR59[3] && !VAR51[3] && !VAR51[1]))
VAR71[15:8] <= VAR71[15:8] - 1;
else
VAR71[9:8] <= {!VAR59[1], VAR59[1] ^ VAR59[3]};
end
end
always @(*) begin
if ((VAR36[8:1]==VAR90[8:1]) && VAR69) VAR32[15:0] = {VAR45[15:10] + VAR67[15:10],VAR67[9:8],VAR45[7:2] + VAR67[7:2],VAR67[1:0]};
end
else if (VAR36[8:1]==VAR90[8:1]) VAR32[15:0] = {VAR45[15:8] + VAR67[15:8],VAR45[7:0] + VAR67[7:0]};
else if (VAR36[8:1]==VAR8[8:1]) VAR32[15:0] = VAR71;
else if (VAR36[8:1]==VAR41[8:1]) VAR32[15:0] = {1'b0, VAR105[3],
1'b0, VAR105[2],
1'b0, VAR105[1],
1'b0, VAR105[0],
8'h00};
else if (VAR36[8:1]==VAR106[8:1]) VAR32[15:0] = {8'h00,VAR79};
else
VAR32[15:0] = 16'h0000;
end
assign VAR87 = VAR104 && !VAR100 ? VAR35 : VAR56[4] & VAR91 & VAR40;
assign VAR19 = VAR104 && !VAR70 ? VAR5 : VAR22[4];
assign VAR113 = VAR36[8:1]==VAR39[8:1] ? 1'b1 : 1'b0;
assign VAR15 = VAR16[15:0];
VAR98 VAR81
(
.clk (clk),
.VAR111 (VAR111),
.reset (reset),
.VAR108 (VAR108),
.VAR85 (VAR85),
.VAR21 (VAR21),
.VAR101 (VAR101),
.VAR1 (VAR79),
.VAR94 (VAR45[15:8]),
.VAR25 (VAR45[7:0]),
.VAR91 (VAR91),
.VAR103 (VAR103),
.VAR3 (VAR3),
.VAR113 (VAR113),
.VAR15 (VAR15)
);
reg [ 2:0] VAR20;
wire VAR11;
reg [ 7:0] VAR96[0:1];
reg [ 1:0] VAR82[0:1];
reg [ 7:0] VAR25;
reg [ 7:0] VAR94;
always @ (posedge clk) begin
VAR20 <= {VAR20[1:0], VAR112};
end
assign VAR11 = VAR20[2] ^ VAR20[1];
always @ (posedge clk) begin
VAR96[0] <= VAR62;
VAR96[1] <= VAR96[0];
VAR82[0] <= VAR102;
VAR82[1] <= VAR82[0];
end
always @(posedge clk) begin
if(reset) begin
VAR25 <= 8'd0;
VAR94 <= 8'd0;
end else if (VAR113 && VAR111) begin
VAR94[7:2] <= VAR15[15:10];
VAR25[7:2] <= VAR15[7:2];
end else if (VAR11) begin
if(VAR82[1] == 0)
VAR25[7:0] <= VAR25[7:0] + VAR96[1];
end
else if(VAR82[1] == 1)
VAR94[7:0] <= VAR94[7:0] + VAR96[1];
end
end
assign VAR45 = {VAR94, VAR25};
assign VAR91 = ~VAR14[0];
assign VAR3 = ~VAR14[1];
assign VAR103 = ~VAR14[2];
VAR48 VAR43
(
.clk (clk),
.VAR111 (VAR111),
.VAR47 (VAR47),
.reset (reset),
.VAR66 (VAR66),
.VAR84 (VAR84),
.VAR115 (VAR115),
.VAR101 (VAR101),
.VAR109 (VAR109),
.VAR68 (VAR42),
.VAR2 (VAR2),
.VAR89 (VAR89),
.VAR46 (VAR46),
.VAR78 (VAR78),
.VAR58 (VAR58),
.VAR53 (VAR53),
.VAR54 (VAR54),
.VAR61 (VAR61),
.VAR4 (VAR4),
.VAR60 (VAR60),
.VAR38 (VAR38),
.VAR12 (VAR12),
.VAR10 (VAR10),
.VAR74 (VAR74),
.VAR92 (VAR92),
.VAR28 (VAR28),
.VAR73 (VAR73),
.VAR64 (VAR64),
.VAR104 (VAR104),
.VAR93 (VAR93),
.VAR52 (VAR52),
.VAR37 (VAR37),
.VAR49 (VAR49),
.VAR80 (VAR80),
.VAR107 (VAR107),
.VAR77 (VAR77),
.VAR27 (VAR27),
.VAR63 (VAR63),
.VAR95 (VAR95),
.VAR24 (VAR24)
);
endmodule
|
gpl-3.0
|
cfangmeier/VFPIX-telescope-Code
|
DAQ_Firmware/src/ram/ram_controller_phy_alt_mem_phy_pll.v
| 22,785 |
module MODULE1 (
VAR118,
VAR127,
VAR38,
VAR82,
VAR90,
VAR137,
VAR98,
VAR42,
VAR85,
VAR110,
VAR64,
VAR71,
VAR35);
input VAR118;
input VAR127;
input [2:0] VAR38;
input VAR82;
input VAR90;
input VAR137;
output VAR98;
output VAR42;
output VAR85;
output VAR110;
output VAR64;
output VAR71;
output VAR35;
tri0 VAR118;
tri0 [2:0] VAR38;
tri0 VAR82;
tri0 VAR90;
wire [4:0] VAR13;
wire VAR122;
wire VAR91;
wire [0:0] VAR23 = 1'h0;
wire [4:4] VAR81 = VAR13[4:4];
wire [3:3] VAR32 = VAR13[3:3];
wire [2:2] VAR21 = VAR13[2:2];
wire [1:1] VAR65 = VAR13[1:1];
wire [0:0] VAR30 = VAR13[0:0];
wire VAR98 = VAR30;
wire VAR42 = VAR65;
wire VAR85 = VAR21;
wire VAR110 = VAR32;
wire VAR64 = VAR81;
wire VAR71 = VAR122;
wire VAR35 = VAR91;
wire VAR128 = VAR127;
wire [1:0] VAR114 = {VAR23, VAR128};
VAR52 VAR89 (
.VAR118 (VAR118),
.VAR113 (VAR114),
.VAR38 (VAR38),
.VAR82 (VAR82),
.VAR90 (VAR90),
.VAR137 (VAR137),
.clk (VAR13),
.VAR71 (VAR122),
.VAR35 (VAR91),
.VAR41 (),
.VAR58 (),
.VAR43 ({6{1'b1}}),
.VAR97 (),
.VAR63 (1'b0),
.VAR50 (1'b0),
.VAR8 (),
.VAR67 (),
.VAR18 (),
.VAR57 ({4{1'b1}}),
.VAR87 (1'b1),
.VAR47 (),
.VAR7 (),
.VAR33 (),
.VAR77 (),
.VAR45 (1'b1),
.VAR79 (1'b1),
.VAR10 (1'b0),
.VAR24 (1'b1),
.VAR14 (1'b0),
.VAR9 (),
.VAR126 (),
.VAR6 (1'b0),
.VAR51 (1'b0),
.VAR62 (),
.VAR106 (),
.VAR36 (),
.VAR49 ());
VAR89.VAR112 = "VAR125",
VAR89.VAR48 = 100,
VAR89.VAR56 = 50,
VAR89.VAR134 = 133,
VAR89.VAR72 = "0",
VAR89.VAR124 = 50,
VAR89.VAR53 = 50,
VAR89.VAR130 = 133,
VAR89.VAR2 = "0",
VAR89.VAR101 = 50,
VAR89.VAR70 = 50,
VAR89.VAR95 = 133,
VAR89.VAR135 = "-1880",
VAR89.VAR107 = 50,
VAR89.VAR26 = 50,
VAR89.VAR46 = 133,
VAR89.VAR5 = "0",
VAR89.VAR15 = 50,
VAR89.VAR133 = 50,
VAR89.VAR68 = 133,
VAR89.VAR120 = "0",
VAR89.VAR94 = "VAR34",
VAR89.VAR105 = 20000,
VAR89.VAR19 = "VAR17 VAR61 VAR132",
VAR89.VAR131 = "VAR52",
VAR89.VAR59 = "VAR22",
VAR89.VAR29 = "VAR125",
VAR89.VAR39 = "VAR96",
VAR89.VAR25 = "VAR93",
VAR89.VAR116 = "VAR96",
VAR89.VAR75 = "VAR96",
VAR89.VAR102 = "VAR96",
VAR89.VAR138 = "VAR96",
VAR89.VAR31 = "VAR96",
VAR89.VAR103 = "VAR96",
VAR89.VAR99 = "VAR93",
VAR89.VAR84 = "VAR96",
VAR89.VAR40 = "VAR93",
VAR89.VAR66 = "VAR96",
VAR89.VAR108 = "VAR93",
VAR89.VAR123 = "VAR93",
VAR89.VAR129 = "VAR93",
VAR89.VAR115 = "VAR93",
VAR89.VAR88 = "VAR96",
VAR89.VAR100 = "VAR96",
VAR89.VAR16 = "VAR93",
VAR89.VAR1 = "VAR96",
VAR89.VAR76 = "VAR96",
VAR89.VAR3 = "VAR96",
VAR89.VAR28 = "VAR96",
VAR89.VAR121 = "VAR96",
VAR89.VAR119 = "VAR96",
VAR89.VAR4 = "VAR93",
VAR89.VAR109 = "VAR93",
VAR89.VAR80 = "VAR93",
VAR89.VAR78 = "VAR93",
VAR89.VAR69 = "VAR93",
VAR89.VAR104 = "VAR96",
VAR89.VAR27 = "VAR96",
VAR89.VAR136 = "VAR96",
VAR89.VAR11 = "VAR96",
VAR89.VAR83 = "VAR96",
VAR89.VAR20 = "VAR96",
VAR89.VAR73 = "VAR96",
VAR89.VAR111 = "VAR96",
VAR89.VAR12 = "VAR96",
VAR89.VAR44 = "VAR96",
VAR89.VAR117 = "VAR96",
VAR89.VAR37 = "VAR55",
VAR89.VAR74 = "VAR92",
VAR89.VAR54 = 117,
VAR89.VAR86 = 5,
VAR89.VAR60 = 3;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/sregsbp/sky130_fd_sc_lp__sregsbp.behavioral.pp.v
| 2,875 |
module MODULE1 (
VAR16 ,
VAR26 ,
VAR13 ,
VAR29 ,
VAR23 ,
VAR7 ,
VAR4,
VAR31 ,
VAR28 ,
VAR21 ,
VAR24
);
output VAR16 ;
output VAR26 ;
input VAR13 ;
input VAR29 ;
input VAR23 ;
input VAR7 ;
input VAR4;
input VAR31 ;
input VAR28 ;
input VAR21 ;
input VAR24 ;
wire VAR5 ;
wire VAR30 ;
wire VAR25 ;
reg VAR11 ;
wire VAR2 ;
wire VAR19 ;
wire VAR22 ;
wire VAR9;
wire VAR1 ;
wire VAR18 ;
wire VAR27 ;
wire VAR12 ;
wire VAR14 ;
wire VAR15 ;
wire VAR8 ;
not VAR3 (VAR30 , VAR9 );
VAR10 VAR17 (VAR25, VAR2, VAR19, VAR22 );
VAR6 VAR33 (VAR5 , VAR25, VAR1, VAR30, VAR11, VAR31, VAR28);
assign VAR18 = ( VAR31 === 1'b1 );
assign VAR27 = ( ( VAR9 === 1'b1 ) && VAR18 );
assign VAR12 = ( ( VAR22 === 1'b0 ) && VAR27 );
assign VAR14 = ( ( VAR22 === 1'b1 ) && VAR27 );
assign VAR15 = ( ( VAR2 !== VAR19 ) && VAR27 );
assign VAR8 = ( ( VAR4 === 1'b1 ) && VAR18 );
buf VAR20 (VAR16 , VAR5 );
not VAR32 (VAR26 , VAR5 );
endmodule
|
apache-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/aemb/aeMB_xecu.v
| 12,765 |
module MODULE1 (
VAR78, VAR66, VAR76, VAR64, VAR58, VAR29,
VAR27, VAR52,
VAR21, VAR46, VAR25, VAR7, VAR38, VAR17, VAR47, VAR1, VAR60, VAR12,
VAR54, VAR10, VAR8, VAR74, VAR55, VAR37, VAR20, VAR24, VAR3, VAR11
);
parameter VAR30=32;
parameter VAR35=0;
parameter VAR5=0;
output [VAR30-1:2] VAR78;
output [3:0] VAR66;
output [6:2] VAR76;
output [1:0] VAR64;
output [31:0] VAR58;
output [3:0] VAR29;
output VAR27;
output VAR52;
input [31:0] VAR21, VAR46;
input [1:0] VAR25, VAR7;
input [4:0] VAR38, VAR17;
input [2:0] VAR47;
input VAR1, VAR60;
input [10:0] VAR12;
input VAR54;
input [31:0] VAR10;
input [15:0] VAR8;
input [5:0] VAR74;
input [4:0] VAR55;
input [31:0] VAR37;
input [31:2] VAR20;
input VAR24, VAR3, VAR11;
reg VAR44, VAR63;
reg VAR27, VAR75;
reg VAR73, VAR67;
reg VAR52, VAR45;
wire VAR65 = VAR1 & !VAR60;
reg [31:0] VAR50, VAR2;
always @(VAR37 or VAR25 or VAR20 or VAR21 or VAR58)
case (VAR25)
2'o0: VAR50 <= VAR21;
2'o1: VAR50 <= VAR58;
2'o2: VAR50 <= VAR37;
2'o3: VAR50 <= {VAR20, 2'o0};
endcase
always @(VAR37 or VAR7 or VAR46 or VAR58 or VAR10)
case (VAR7)
2'o0: VAR2 <= VAR46;
2'o1: VAR2 <= VAR58;
2'o2: VAR2 <= VAR37;
2'o3: VAR2 <= VAR10;
endcase
reg VAR28;
reg [31:0] VAR15;
wire [31:0] VAR61;
wire VAR72;
wire VAR56 = !VAR74[5] & VAR74[1]; wire VAR4 = !VAR74[5] & VAR74[0]; wire VAR69 = !VAR74[3] & VAR8[1]; wire VAR34 = (VAR69) ? !VAR72 : VAR61[31];
wire [31:0] VAR36 = (VAR4) ? ~VAR50 : VAR50;
wire VAR9 = (VAR56) ? VAR44 : VAR4;
assign {VAR72, VAR61} = (VAR2 + VAR36) + VAR9;
always @(VAR72 or VAR61 or VAR34) begin
{VAR28, VAR15} <= {VAR72, VAR34, VAR61[30:0]}; end
reg [31:0] VAR68;
always @(VAR50 or VAR2 or VAR74)
case (VAR74[1:0])
2'o0: VAR68 <= VAR50 | VAR2;
2'o1: VAR68 <= VAR50 & VAR2;
2'o2: VAR68 <= VAR50 ^ VAR2;
2'o3: VAR68 <= VAR50 & ~VAR2;
endcase
reg [31:0] VAR41;
reg VAR26;
always @(VAR8 or VAR44 or VAR50)
case (VAR8[6:5])
2'o0: {VAR41, VAR26} <= {VAR50[31],VAR50[31:0]};
2'o1: {VAR41, VAR26} <= {VAR44,VAR50[31:0]};
2'o2: {VAR41, VAR26} <= {1'b0,VAR50[31:0]};
2'o3: {VAR41, VAR26} <= (VAR8[0]) ? { {(16){VAR50[15]}}, VAR50[15:0], VAR44} :
{ {(24){VAR50[7]}}, VAR50[7:0], VAR44};
endcase
wire [31:0] VAR53 = {VAR44, 3'o0,
20'h0ED32,
4'h0, VAR52, VAR44, VAR27, VAR73};
wire VAR22 = (VAR74 == 6'o45) & !VAR8[14] & VAR8[0];
wire VAR6 = (VAR74 == 6'o45) & !VAR8[14] & !VAR8[0];
reg [31:0] VAR57;
always @(VAR6 or VAR22 or VAR50 or VAR2 or VAR20 or VAR38
or VAR53)
VAR57 <= (VAR22) ? VAR53 :
(VAR6) ? VAR20 :
(VAR38[3]) ? VAR2 :
VAR50;
reg [31:0] VAR71, VAR48, VAR70;
always @(VAR50 or VAR2) begin
VAR70 <= (VAR50 * VAR2);
end
always @(posedge VAR24)
if (VAR3) begin
VAR71 <= 32'h0;
end else if (VAR54) begin
VAR71 <= VAR70;
end
reg [31:0] VAR42;
reg [31:0] VAR77, VAR62, VAR39;
always @(VAR50 or VAR2)
VAR39 <= VAR50 << VAR2[4:0];
always @(VAR50 or VAR2)
VAR77 <= VAR50 >> VAR2[4:0];
always @(VAR50 or VAR2)
case (VAR2[4:0])
5'd00: VAR62 <= VAR50;
5'd01: VAR62 <= {{(1){VAR50[31]}}, VAR50[31:1]};
5'd02: VAR62 <= {{(2){VAR50[31]}}, VAR50[31:2]};
5'd03: VAR62 <= {{(3){VAR50[31]}}, VAR50[31:3]};
5'd04: VAR62 <= {{(4){VAR50[31]}}, VAR50[31:4]};
5'd05: VAR62 <= {{(5){VAR50[31]}}, VAR50[31:5]};
5'd06: VAR62 <= {{(6){VAR50[31]}}, VAR50[31:6]};
5'd07: VAR62 <= {{(7){VAR50[31]}}, VAR50[31:7]};
5'd08: VAR62 <= {{(8){VAR50[31]}}, VAR50[31:8]};
5'd09: VAR62 <= {{(9){VAR50[31]}}, VAR50[31:9]};
5'd10: VAR62 <= {{(10){VAR50[31]}}, VAR50[31:10]};
5'd11: VAR62 <= {{(11){VAR50[31]}}, VAR50[31:11]};
5'd12: VAR62 <= {{(12){VAR50[31]}}, VAR50[31:12]};
5'd13: VAR62 <= {{(13){VAR50[31]}}, VAR50[31:13]};
5'd14: VAR62 <= {{(14){VAR50[31]}}, VAR50[31:14]};
5'd15: VAR62 <= {{(15){VAR50[31]}}, VAR50[31:15]};
5'd16: VAR62 <= {{(16){VAR50[31]}}, VAR50[31:16]};
5'd17: VAR62 <= {{(17){VAR50[31]}}, VAR50[31:17]};
5'd18: VAR62 <= {{(18){VAR50[31]}}, VAR50[31:18]};
5'd19: VAR62 <= {{(19){VAR50[31]}}, VAR50[31:19]};
5'd20: VAR62 <= {{(20){VAR50[31]}}, VAR50[31:20]};
5'd21: VAR62 <= {{(21){VAR50[31]}}, VAR50[31:21]};
5'd22: VAR62 <= {{(22){VAR50[31]}}, VAR50[31:22]};
5'd23: VAR62 <= {{(23){VAR50[31]}}, VAR50[31:23]};
5'd24: VAR62 <= {{(24){VAR50[31]}}, VAR50[31:24]};
5'd25: VAR62 <= {{(25){VAR50[31]}}, VAR50[31:25]};
5'd26: VAR62 <= {{(26){VAR50[31]}}, VAR50[31:26]};
5'd27: VAR62 <= {{(27){VAR50[31]}}, VAR50[31:27]};
5'd28: VAR62 <= {{(28){VAR50[31]}}, VAR50[31:28]};
5'd29: VAR62 <= {{(29){VAR50[31]}}, VAR50[31:29]};
5'd30: VAR62 <= {{(30){VAR50[31]}}, VAR50[31:30]};
5'd31: VAR62 <= {{(31){VAR50[31]}}, VAR50[31]};
endcase
reg [31:0] VAR32, VAR49, VAR16;
always @(posedge VAR24)
if (VAR3) begin
VAR16 <= 32'h0;
VAR49 <= 32'h0;
VAR32 <= 32'h0;
end else if (VAR54) begin
VAR32 <= VAR77;
VAR49 <= VAR62;
VAR16 <= VAR39;
end
always @(VAR12 or VAR16 or VAR49 or VAR32)
case (VAR12[10:9])
2'd0: VAR42 <= VAR32;
2'd1: VAR42 <= VAR49;
2'd2: VAR42 <= VAR16;
default: VAR42 <= 32'VAR31;
endcase
wire VAR40 = (VAR74 == 6'o45) & VAR8[14] & !VAR65;
wire VAR13 = ({VAR74[5:4], VAR74[2]} == 3'o0);
always @(VAR13 or VAR40 or VAR65 or VAR44 or VAR47
or VAR50 or VAR28 or VAR26)
if (VAR65) begin
VAR63 <= VAR44;
end else
case (VAR47)
3'o0: VAR63 <= (VAR13) ? VAR28 : VAR44;
3'o1: VAR63 <= VAR44; 3'o2: VAR63 <= VAR26; 3'o3: VAR63 <= (VAR40) ? VAR50[2] : VAR44;
3'o4: VAR63 <= VAR44;
3'o5: VAR63 <= VAR44;
default: VAR63 <= 1'VAR31;
endcase
wire VAR14 = (VAR74 == 6'o55) & VAR55[0] & !VAR65;
wire VAR33 = (VAR74 == 6'o55) & VAR55[1] & !VAR65;
wire VAR23 = ((VAR74 == 6'o56) | (VAR74 == 6'o66)) & (VAR38 == 5'hC);
wire VAR19 = ((VAR74 == 6'o56) | (VAR74 == 6'o66)) & (VAR38 == 5'hE);
always @(VAR19 or VAR40 or VAR14 or VAR27 or VAR50)
VAR75 <= (VAR19) ? 1'b0 :
(VAR14) ? 1'b1 :
(VAR40) ? VAR50[1] :
VAR27;
always @(VAR23 or VAR40 or VAR33 or VAR52 or VAR50)
VAR45 <= (VAR23) ? 1'b1 :
(VAR33) ? 1'b0 :
(VAR40) ? VAR50[3] :
VAR52;
always @(VAR40 or VAR73 or VAR50)
VAR67 <= (VAR40) ? VAR50[0] : VAR73;
reg [31:0] VAR58, VAR51;
always @(VAR65 or VAR47 or VAR15 or VAR42
or VAR68 or VAR57 or VAR71 or VAR41)
if (VAR65)
VAR51 <= 32'h0;
end
else
case (VAR47)
3'o0: VAR51 <= VAR15;
3'o1: VAR51 <= VAR68;
3'o2: VAR51 <= VAR41;
3'o3: VAR51 <= VAR57;
3'o4: VAR51 <= (VAR35) ? VAR71 : 32'VAR31;
3'o5: VAR51 <= (VAR5) ? VAR42 : 32'VAR31;
default: VAR51 <= 32'VAR31;
endcase
reg [3:0] VAR29, VAR18;
assign VAR78 = VAR58[VAR30-1:2];
assign VAR66 = VAR29;
always @(VAR74 or VAR61)
case (VAR74[1:0])
2'o0: case (VAR61[1:0]) 2'o0: VAR18 <= 4'h8;
2'o1: VAR18 <= 4'h4;
2'o2: VAR18 <= 4'h2;
2'o3: VAR18 <= 4'h1;
endcase 2'o1: VAR18 <= (VAR61[1]) ? 4'h3 : 4'hC; 2'o2: VAR18 <= 4'hF; 2'o3: VAR18 <= 4'h0; endcase
reg [14:2] VAR59, VAR43;
assign {VAR76, VAR64} = VAR59[8:2];
always @(VAR12 or VAR17) begin
VAR43 <= {VAR12, VAR17[3:2]};
end
always @(posedge VAR24)
if (VAR3) begin
VAR29 <= 4'h0;
VAR59 <= 13'h0;
VAR73 <= 1'h0;
VAR52 <= 1'h0;
VAR44 <= 1'h0;
VAR27 <= 1'h0;
VAR58 <= 32'h0;
end else if (VAR11) begin VAR58 <= VAR51;
VAR29 <= VAR18;
VAR44 <= VAR63;
VAR27 <= VAR75;
VAR73 <= VAR67;
VAR52 <= VAR45;
VAR59 <= VAR43;
end
endmodule
|
mit
|
iafnan/es2-hardwaresecurity
|
or1200/rtl/verilog/or1200/or1200_operandmuxes.v
| 6,581 |
module MODULE1(
clk, rst,
VAR2, VAR5, VAR16, VAR18, VAR6, VAR11,
VAR17, VAR8, VAR15, VAR19, VAR3, VAR4
);
parameter VAR9 = VAR1;
input clk;
input rst;
input VAR2;
input VAR5;
input [VAR9-1:0] VAR16;
input [VAR9-1:0] VAR18;
input [VAR9-1:0] VAR6;
input [VAR9-1:0] VAR11;
input [VAR9-1:0] VAR17;
input [VAR12-1:0] VAR8;
input [VAR12-1:0] VAR15;
output [VAR9-1:0] VAR19;
output [VAR9-1:0] VAR3;
output [VAR9-1:0] VAR4;
reg [VAR9-1:0] VAR19;
reg [VAR9-1:0] VAR3;
reg [VAR9-1:0] VAR7;
reg [VAR9-1:0] VAR4;
reg VAR10;
reg VAR13;
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR19 <= 32'd0;
VAR10 <= 1'b0;
end else if (!VAR5 && VAR2 && !VAR10) begin
VAR19 <= VAR7;
VAR10 <= 1'b1;
end else if (!VAR5 && !VAR10) begin
VAR19 <= VAR7;
end else if (!VAR5 && !VAR2)
VAR10 <= 1'b0;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR3 <= 32'd0;
VAR13 <= 1'b0;
end else if (!VAR5 && VAR2 && !VAR13) begin
VAR3 <= VAR4;
VAR13 <= 1'b1;
end else if (!VAR5 && !VAR13) begin
VAR3 <= VAR4;
end else if (!VAR5 && !VAR2)
VAR13 <= 1'b0;
end
always @(VAR6 or VAR11 or VAR16 or VAR8) begin
end
casex (VAR8) else
casex (VAR8) VAR14
VAR7 = VAR6;
VAR7 = VAR11;
default:
VAR7 = VAR16;
endcase
end
always @(VAR17 or VAR6 or VAR11 or VAR18 or VAR15) begin
end
casex (VAR15) else
casex (VAR15) VAR14
VAR4 = VAR17;
VAR4 = VAR6;
VAR4 = VAR11;
default:
VAR4 = VAR18;
endcase
end
endmodule
|
gpl-3.0
|
tuura/fantasi
|
dependencies/Altera_DE4/niosII/synthesis/submodules/system1_nios2_gen2_0.v
| 5,783 |
module MODULE1 (
input wire clk, input wire VAR24, input wire VAR6, output wire [20:0] VAR16, output wire [3:0] VAR3, output wire VAR18, input wire [31:0] VAR9, input wire VAR14, output wire VAR8, output wire [31:0] VAR21, output wire VAR12, output wire [20:0] VAR13, output wire VAR19, input wire [31:0] VAR5, input wire VAR26, input wire [31:0] irq, output wire VAR17, input wire [8:0] VAR22, input wire [3:0] VAR10, input wire VAR15, input wire VAR11, output wire [31:0] VAR4, output wire VAR23, input wire VAR7, input wire [31:0] VAR1, output wire VAR2 );
VAR20 VAR25 (
.clk (clk), .VAR24 (VAR24), .VAR6 (VAR6), .VAR16 (VAR16), .VAR3 (VAR3), .VAR18 (VAR18), .VAR9 (VAR9), .VAR14 (VAR14), .VAR8 (VAR8), .VAR21 (VAR21), .VAR12 (VAR12), .VAR13 (VAR13), .VAR19 (VAR19), .VAR5 (VAR5), .VAR26 (VAR26), .irq (irq), .VAR17 (VAR17), .VAR22 (VAR22), .VAR10 (VAR10), .VAR15 (VAR15), .VAR11 (VAR11), .VAR4 (VAR4), .VAR23 (VAR23), .VAR7 (VAR7), .VAR1 (VAR1), .VAR2 (VAR2) );
endmodule
|
mit
|
scalable-networks/ext
|
uhd/fpga/usrp2/sdr_lib/halfband_ideal.v
| 3,312 |
module MODULE1 (
input VAR2,
input reset,
input enable,
input VAR6,
input wire signed [17:0] VAR9,
output reg VAR8,
output reg signed [17:0] VAR1
) ;
parameter VAR4 = 1 ;
parameter VAR5 = 2 ;
reg signed [40:0] VAR3 ;
reg signed [17:0] delay[30:0] ;
reg signed [17:0] VAR7[30:0] ;
reg [7:0] VAR11 ;
integer VAR10 ;
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.functional.pp.v
| 1,867 |
module MODULE1 (
VAR9 ,
VAR11 ,
VAR1,
VAR3,
VAR2 ,
VAR4
);
output VAR9 ;
input VAR11 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
wire VAR12 ;
wire VAR5;
not VAR6 (VAR12 , VAR11 );
VAR7 VAR10 (VAR5, VAR12, VAR1, VAR3);
buf VAR8 (VAR9 , VAR5 );
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/ddr3_s4_amphy/alt_mem_ddrx_rdwr_data_tmg.v
| 127,864 |
module MODULE1
VAR124 = 2,
VAR61 = 8,
VAR16 = 1,
VAR121 = 1,
VAR104 = 6,
VAR89 = 1,
VAR188 = 10,
VAR187 = 0,
VAR131 = 0,
VAR138 = 2,
VAR2 = 1,
VAR67 = 1
)
(
VAR27,
VAR132,
VAR151,
VAR147,
VAR15,
VAR63,
VAR40,
VAR48, VAR184,
VAR102,
VAR133,
VAR19,
VAR100,
VAR56,
VAR144, VAR47,
VAR64,
VAR91,
VAR154,
VAR38,
VAR66,
VAR62,
VAR125,
VAR162,
VAR58,
VAR161,
VAR92,
VAR87,
VAR97,
VAR83,
VAR52,
VAR70,
VAR155,
VAR175,
VAR23,
VAR122
);
localparam integer VAR179 = 2**(VAR104/VAR89);
localparam integer VAR93 = 2**VAR188;
integer VAR109;
input VAR27;
input VAR132;
input [VAR2-1:0] VAR151;
input [VAR67-1:0] VAR147;
output [VAR67-1:0] VAR15;
input VAR63;
input VAR40;
input VAR48;
input [VAR188-1:0] VAR184;
input [VAR138-1:0] VAR102;
input [VAR138-1:0] VAR133;
input [VAR61*VAR124-1:0] VAR19;
input [(VAR61*VAR124)/(VAR61/VAR16)-1:0] VAR100;
input [VAR104-1:0] VAR56;
output [VAR16*(VAR124/2)-1:0] VAR144;
output [VAR16*(VAR124/2)-1:0] VAR47;
output [VAR89-1:0] VAR64;
output [VAR89*VAR188-1:0] VAR91;
output [VAR89*VAR93-1:0] VAR154;
output [VAR89-1:0] VAR38;
output [VAR89-1:0] VAR66;
output VAR62;
output [VAR188-1:0] VAR125;
output [VAR93-1:0] VAR162;
output VAR58;
output VAR161;
output [VAR89-1:0] VAR92;
output VAR87;
output [VAR188-1:0] VAR97;
output [VAR93-1:0] VAR83;
output VAR52;
output VAR70;
output [VAR16*(VAR124/2)-1:0] VAR155;
output [VAR16*(VAR124/2)-1:0] VAR175;
output [VAR61*VAR124-1:0] VAR23;
output [VAR121*VAR124-1:0] VAR122;
wire VAR63;
wire VAR40;
wire VAR48;
wire [VAR188-1:0] VAR184;
wire [VAR138-1:0] VAR102;
wire [VAR138-1:0] VAR133;
wire [VAR16*(VAR124/2)-1:0] VAR144;
wire [VAR16*(VAR124/2)-1:0] VAR47;
wire [VAR89-1:0] VAR64;
reg [VAR89-1:0] VAR21;
wire [VAR89*VAR188-1:0] VAR91;
wire [VAR89*VAR93-1:0] VAR154;
wire [VAR89-1:0] VAR38;
wire [VAR89-1:0] VAR66;
wire VAR62;
wire [VAR188-1:0] VAR125;
wire [VAR93-1:0] VAR162;
wire VAR58;
wire VAR161;
reg [VAR89-1:0] VAR92;
wire VAR87;
wire [VAR188-1:0] VAR97;
wire [VAR93-1:0] VAR83;
wire VAR52;
wire VAR70;
wire [VAR16*(VAR124/2)-1:0] VAR155;
wire [VAR16*(VAR124/2)-1:0] VAR175;
wire [VAR61*VAR124-1:0] VAR23;
wire [VAR121*VAR124-1:0] VAR122;
reg [VAR67-1:0] VAR173 [VAR89-1:0];
reg [VAR67-1:0] VAR28 [VAR89-1:0];
reg [VAR67-1:0] VAR3 [VAR89-1:0];
reg [VAR67-1:0] VAR152 [VAR89-1:0];
reg [VAR67-1:0] VAR15;
reg [VAR67-1:0] VAR137;
reg VAR158;
reg VAR57;
reg VAR43;
reg VAR6;
reg [VAR179-1:0] VAR69;
reg [VAR179-1:0] VAR39;
reg [VAR179-1:0] VAR156;
reg [VAR179-1:0] VAR17;
reg [VAR188-1:0] VAR145 [VAR179-1:0];
reg [VAR93-1:0] VAR32 [VAR179-1:0];
reg [VAR93-1:0] VAR170;
reg VAR35;
reg VAR183;
reg VAR163;
reg VAR53;
reg VAR24;
reg [VAR89-1:0] VAR126;
reg [VAR89-1:0] VAR72;
reg [VAR188-1:0] VAR10 [VAR89-1:0];
reg [VAR188-1:0] VAR112 [VAR89-1:0];
reg [VAR93-1:0] VAR105 [VAR89-1:0];
reg [VAR93-1:0] VAR130 [VAR89-1:0];
reg [VAR89-1:0] VAR168;
reg [VAR89-1:0] VAR50;
reg [VAR89-1:0] VAR20;
reg [VAR89-1:0] VAR96;
wire VAR78;
wire VAR12;
reg VAR141;
reg VAR4;
reg [VAR89-1:0] VAR139;
reg [VAR89-1:0] VAR74;
reg [VAR104/VAR89-1:0] VAR41 [VAR89-1:0];
reg [VAR104/VAR89-1:0] VAR86 [VAR89-1:0];
reg VAR60;
reg [VAR104/VAR89-1:0] VAR99;
reg [VAR104/VAR89-1:0] VAR176;
reg [VAR104/VAR89-1:0] VAR174;
reg VAR136;
reg VAR82;
reg VAR36;
reg VAR127;
reg VAR5;
reg [VAR188-1:0] VAR8;
reg [VAR188-1:0] VAR25;
reg [VAR93-1:0] VAR42;
reg [VAR93-1:0] VAR164;
reg VAR116;
reg VAR119;
reg VAR81;
reg VAR54;
reg VAR13;
reg VAR111;
reg [VAR188-1:0] VAR135;
reg [VAR93-1:0] VAR33;
reg VAR9;
reg VAR51;
reg VAR46;
reg [VAR104/VAR89-1:0] VAR98;
reg [VAR104/VAR89-1:0] VAR103;
reg [VAR104/VAR89-1:0] VAR71;
reg VAR59;
reg VAR106;
reg VAR44;
reg VAR177;
reg VAR172;
reg [VAR188-1:0] VAR84;
reg [VAR188-1:0] VAR95;
reg [VAR93-1:0] VAR115;
reg [VAR93-1:0] VAR49;
reg VAR159;
reg VAR14;
reg VAR171;
reg VAR108;
reg VAR160;
reg VAR22;
reg [VAR188-1:0] VAR120;
reg [VAR93-1:0] VAR29;
reg VAR7;
reg VAR45;
reg VAR85 [VAR89-1:0];
reg [VAR104/VAR89-1:0] VAR18 [VAR89-1:0];
reg [VAR104/VAR89-1:0] VAR140 [VAR89-1:0];
reg [VAR104/VAR89-1:0] VAR114 [VAR89-1:0];
reg VAR123 [VAR89-1:0];
reg VAR55 [VAR89-1:0];
reg VAR76 [VAR89-1:0];
reg VAR117 [VAR89-1:0];
reg VAR150 [VAR89-1:0];
reg [VAR188-1:0] VAR113 [VAR89-1:0];
reg [VAR188-1:0] VAR26 [VAR89-1:0];
reg [VAR93-1:0] VAR165 [VAR89-1:0];
reg [VAR93-1:0] VAR178 [VAR89-1:0];
reg VAR80 [VAR89-1:0];
reg VAR143 [VAR89-1:0];
reg VAR65 [VAR89-1:0];
reg VAR94 [VAR89-1:0];
reg VAR180 [VAR89-1:0];
reg VAR129 [VAR89-1:0];
reg [VAR188-1:0] VAR167 [VAR89-1:0];
reg [VAR93-1:0] VAR142 [VAR89-1:0];
reg VAR75 [VAR89-1:0];
reg VAR149 [VAR89-1:0];
generate
genvar VAR182;
for (VAR182 = 0;VAR182 < VAR89;VAR182 = VAR182 + 1)
begin : VAR148
always @
begin
VAR3 [VAR182] = VAR173 [VAR182] | VAR3 [VAR182-1];
VAR152 [VAR182] = VAR28 [VAR182] | VAR152 [VAR182-1];
end
end
endgenerate
always @
begin
if (VAR63 && VAR48)
begin
VAR158 = 1'b1;
end
else
begin
VAR158 = 1'b0;
end
VAR57 = VAR63;
end
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR43 <= 1'b0;
VAR6 <= 1'b0;
end
else
begin
VAR43 <= VAR158;
VAR6 <= VAR57;
end
end
generate
genvar VAR186;
for (VAR186 = 0; VAR186 < VAR16*(VAR124/2); VAR186 = VAR186 + 1)
begin : VAR110
assign VAR144 [VAR186] = (VAR15) ? VAR43 : VAR158;
assign VAR47 [VAR186] = (VAR15) ? VAR6 : VAR57;
end
endgenerate
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR69 <= 0;
end
else
begin
VAR69 <= {VAR69[VAR179 -2 :0],VAR40};
end
end
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR39 <= 0;
end
else
begin
VAR39 <= {VAR39[VAR179 - 2:0],VAR48};
end
end
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
for (VAR109=0; VAR109<VAR179; VAR109=VAR109+1)
begin
VAR145 [VAR109] <= 0;
end
end
else
begin
VAR145 [0] <= VAR184;
for (VAR109=1; VAR109<VAR179; VAR109=VAR109+1)
begin
VAR145 [VAR109] <= VAR145[VAR109-1];
end
end
end
always @
begin
if (VAR187 || VAR131)
begin
VAR180 [VAR185] = VAR76 [VAR185];
VAR129 [VAR185] = VAR150 [VAR185];
VAR167 [VAR185] = VAR26 [VAR185];
VAR142 [VAR185] = VAR178 [VAR185];
VAR75 [VAR185] = VAR143 [VAR185];
VAR149 [VAR185] = VAR94 [VAR185];
end
else
begin
VAR180 [VAR185] = VAR55 [VAR185];
VAR129 [VAR185] = VAR117 [VAR185];
VAR167 [VAR185] = VAR113 [VAR185];
VAR142 [VAR185] = VAR165 [VAR185];
VAR75 [VAR185] = VAR80 [VAR185];
VAR149 [VAR185] = VAR65 [VAR185];
end
end
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR92 [VAR185] <= 1'b0;
end
else
begin
if (VAR118 == VAR41 [VAR89 - 1])
begin
VAR92 [VAR185] <= 1'b1;
end
else
begin
VAR92 [VAR185] <= 1'b0;
end
end
end
end
for (VAR185 = 1;VAR185 < VAR89;VAR185 = VAR185 + 1)
begin : VAR166
wire [(VAR104 / VAR89) - 1 : 0] VAR118 = VAR56 [(VAR185 + 1) * (VAR104 / VAR89) - 1 : VAR185 * (VAR104 / VAR89)];
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR41 [VAR185] <= 0;
VAR86 [VAR185] <= 0;
end
else
begin
if (VAR118 < VAR41 [VAR185-1])
begin
VAR41 [VAR185] <= VAR118;
end
else
begin
VAR41 [VAR185] <= VAR41 [VAR185-1];
end
if (VAR118 > VAR86 [VAR185-1])
begin
VAR86 [VAR185] <= VAR118;
end
else
begin
VAR86 [VAR185] <= VAR86 [VAR185-1];
end
end
end
end
endgenerate
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR41 [0] <= 0;
VAR86 [0] <= 0;
end
else
begin
VAR41 [0] <= VAR56 [(VAR104 / VAR89) - 1 : 0];
VAR86 [0] <= VAR56 [(VAR104 / VAR89) - 1 : 0];
end
end
generate
if (VAR89 == 1) begin
always @
begin
if (VAR187 || VAR131)
begin
VAR13 = VAR36 ;
VAR111 = VAR5;
VAR135 = VAR25 ;
VAR33 = VAR164 ;
VAR9 = VAR119 ;
VAR51 = VAR54 ;
end
else
begin
VAR13 = VAR82 ;
VAR111 = VAR127;
VAR135 = VAR8 ;
VAR33 = VAR42 ;
VAR9 = VAR116 ;
VAR51 = VAR81 ;
end
end
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR46 <= 1'b0;
VAR98 <= {(VAR104 / VAR89){1'b0}};
VAR103 <= {(VAR104 / VAR89){1'b0}};
VAR71 <= {(VAR104 / VAR89){1'b0}};
end
else
begin
if (VAR86 [VAR89-1] == 0)
begin
VAR46 <= 1'b1;
end
else
begin
VAR46 <= 1'b0;
end
VAR98 <= VAR86 [VAR89-1] - 1;
VAR103 <= VAR86 [VAR89-1] - 2;
VAR71 <= VAR86 [VAR89-1] - 3;
end
end
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR59 <= 1'b0;
VAR106 <= 1'b0;
VAR44 <= 1'b0;
end
else
begin
if (VAR86 [VAR89-1] == 0)
begin
VAR59 <= 1'b0;
VAR106 <= 1'b0;
VAR44 <= 1'b0;
end
else if (VAR86 [VAR89-1] == 1)
begin
if (VAR69[0])
begin
VAR59 <= 1'b1;
end
else
begin
VAR59 <= 1'b0;
end
if (VAR40)
begin
VAR106 <= 1'b1;
end
else
begin
VAR106 <= 1'b0;
end
if (VAR40) begin
VAR44 <= 1'b1;
end
else
begin
VAR44 <= 1'b0;
end
end
else if (VAR86 [VAR89-1] == 2)
begin
if (VAR69[1])
begin
VAR59 <= 1'b1;
end
else
begin
VAR59 <= 1'b0;
end
if (VAR69[0])
begin
VAR106 <= 1'b1;
end
else
begin
VAR106 <= 1'b0;
end
if (VAR40)
begin
VAR44 <= 1'b1;
end
else
begin
VAR44 <= 1'b0;
end
end
else
begin
if (VAR69[VAR98])
begin
VAR59 <= 1'b1;
end
else
begin
VAR59 <= 1'b0;
end
if (VAR69[VAR103])
begin
VAR106 <= 1'b1;
end
else
begin
VAR106 <= 1'b0;
end
if (VAR69[VAR71])
begin
VAR44 <= 1'b1;
end
else
begin
VAR44 <= 1'b0;
end
end
end
end
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR177 <= 1'b0;
VAR172 <= 1'b0;
end
else
begin
if (VAR86 [VAR89-1] == 0)
begin
VAR177 <= 1'b0;
VAR172 <= 1'b0;
end
else if (VAR86 [VAR89-1] == 1)
begin
if (VAR48)
begin
VAR177 <= 1'b1;
end
else
begin
VAR177 <= 1'b0;
end
if (VAR48) begin
VAR172 <= 1'b1;
end
else
begin
VAR172 <= 1'b0;
end
end
else if (VAR86 [VAR89-1] == 2)
begin
if (VAR39[0])
begin
VAR177 <= 1'b1;
end
else
begin
VAR177 <= 1'b0;
end
if (VAR48)
begin
VAR172 <= 1'b1;
end
else
begin
VAR172 <= 1'b0;
end
end
else
begin
if (VAR39[VAR103])
begin
VAR177 <= 1'b1;
end
else
begin
VAR177 <= 1'b0;
end
if (VAR39[VAR71])
begin
VAR172 <= 1'b1;
end
else
begin
VAR172 <= 1'b0;
end
end
end
end
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR84 <= 0;
VAR95 <= 0;
VAR115 <= 0;
VAR49 <= 0;
end
else
begin
if (VAR86 [VAR89-1] == 0)
begin
VAR84 <= 0;
VAR95 <= 0;
VAR115 <= 0;
VAR49 <= 0;
end
else if (VAR86 [VAR89-1] == 1)
begin
VAR84 <= VAR184;
VAR95 <= VAR184; VAR115 <= VAR170;
VAR49 <= VAR170; end
else if (VAR86 [VAR89-1] == 2)
begin
VAR84 <= VAR145 [0];
VAR95 <= VAR184;
VAR115 <= VAR32[0];
VAR49 <= VAR170;
end
else
begin
VAR84 <= VAR145 [VAR103];
VAR95 <= VAR145 [VAR71];
VAR115 <= VAR32[VAR103];
VAR49 <= VAR32[VAR71];
end
end
end
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR159 <= 1'b0;
VAR14 <= 1'b0;
VAR171 <= 1'b0;
VAR108 <= 1'b0;
end
else
begin
if (VAR86 [VAR89-1] == 0)
begin
VAR159 <= 1'b0;
VAR14 <= 1'b0;
VAR171 <= 1'b0;
VAR108 <= 1'b0;
end
else if (VAR86 [VAR89-1] == 1)
begin
if (VAR78)
begin
VAR159 <= 1'b1;
end
else
begin
VAR159 <= 1'b0;
end
if (VAR12)
begin
VAR171 <= 1'b1;
end
else
begin
VAR171 <= 1'b0;
end
if (VAR78) begin
VAR14 <= 1'b1;
end
else
begin
VAR14 <= 1'b0;
end
if (VAR12) begin
VAR108 <= 1'b1;
end
else
begin
VAR108 <= 1'b0;
end
end
else if (VAR86 [VAR89-1] == 2)
begin
if (VAR156[0])
begin
VAR159 <= 1'b1;
end
else
begin
VAR159 <= 1'b0;
end
if (VAR17[0])
begin
VAR171 <= 1'b1;
end
else
begin
VAR171 <= 1'b0;
end
if (VAR78)
begin
VAR14 <= 1'b1;
end
else
begin
VAR14 <= 1'b0;
end
if (VAR12)
begin
VAR108 <= 1'b1;
end
else
begin
VAR108 <= 1'b0;
end
end
else
begin
if (VAR156[VAR103])
begin
VAR159 <= 1'b1;
end
else
begin
VAR159 <= 1'b0;
end
if (VAR17[VAR103])
begin
VAR171 <= 1'b1;
end
else
begin
VAR171 <= 1'b0;
end
if (VAR156[VAR71])
begin
VAR14 <= 1'b1;
end
else
begin
VAR14 <= 1'b0;
end
if (VAR17[VAR71])
begin
VAR108 <= 1'b1;
end
else
begin
VAR108 <= 1'b0;
end
end
end
end
always @
begin
if (VAR60)
begin
if (VAR40 || VAR69[0])
begin
VAR35 = 1'b1;
end
else
begin
VAR35 = 1'b0;
end
end
else
begin
if (VAR82 || VAR136)
begin
VAR35 = 1'b1;
end
else
begin
VAR35 = 1'b0;
end
end
end
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR183 <= 1'b0;
end
else
begin
VAR183 <= VAR35;
end
end
always @
begin
if (VAR60)
begin
if (VAR69[0])
begin
VAR163 = 1'b1;
end
else
begin
VAR163 = 1'b0;
end
end
else
begin
if (VAR136)
begin
VAR163 = 1'b1;
end
else
begin
VAR163 = 1'b0;
end
end
end
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR53 <= 1'b0;
end
else
begin
VAR53 <= VAR163;
end
end
generate
genvar VAR88;
for (VAR88 = 0; VAR88 < VAR16*(VAR124/2); VAR88 = VAR88 + 1)
begin : VAR146
assign VAR175[VAR88] = (VAR15) ? VAR53 : VAR163;
end
endgenerate
generate
genvar VAR77;
for (VAR77 = 0;VAR77 < VAR89;VAR77 = VAR77 + 1) begin : VAR153
always @
begin
if (VAR85 [VAR77])
begin
if (VAR48 && VAR40)
begin
VAR10 [VAR77] = VAR184;
VAR105 [VAR77] = VAR170;
end
else
begin
VAR10 [VAR77] = {(VAR188){1'b0}};
VAR105 [VAR77] = {(VAR93){1'b0}};
end
end
else
begin
if (VAR129 [VAR77] && VAR180 [VAR77])
begin
VAR10 [VAR77] = VAR167 [VAR77];
VAR105 [VAR77] = VAR142 [VAR77];
end
else
begin
VAR10 [VAR77] = {(VAR188){1'b0}};
VAR105 [VAR77] = {(VAR93){1'b0}};
end
end
end
always @ (posedge VAR27, negedge VAR132)
begin
if (~VAR132)
begin
VAR112 [VAR77] <= 0;
VAR130 [VAR77] <= 0;
end
else
begin
VAR112 [VAR77] <= VAR10 [VAR77];
VAR130 [VAR77] <= VAR105 [VAR77];
end
end
assign VAR91 [(VAR77 + 1) * VAR188 - 1 : VAR77 * VAR188 ] = (VAR137) ? VAR112 [VAR77] : VAR10 [VAR77];
assign VAR154 [(VAR77 + 1) * VAR93 - 1 : VAR77 * VAR93] = (VAR137) ? VAR130 [VAR77] : VAR105 [VAR77];
always @
begin
if (VAR60)
begin
if (VAR48 && VAR40)
begin
VAR169 = 1'b1;
end
else
begin
VAR169 = 1'b0;
end
end
else
begin
if (VAR111 && VAR13)
begin
VAR169 = 1'b1;
end
else
begin
VAR169 = 1'b0;
end
end
end
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR31 <= 1'b0;
end
else
begin
VAR31 <= VAR169;
end
end
assign VAR62 = (VAR137) ? VAR31 : VAR169;
always @ (posedge VAR27 or negedge VAR132)
begin
if (!VAR132)
begin
VAR157 <= 1'b0;
end
else
begin
VAR157 <= VAR62;
end
end
always @
begin
if (VAR60)
begin
if (VAR48 && VAR40)
begin
VAR68 = VAR78;
VAR101 = VAR12;
end
else
begin
VAR68 = 1'b0;
VAR101 = 1'b0;
end
end
else
begin
if (VAR111 && VAR13)
begin
VAR68 = VAR9;
VAR101 = VAR51;
end
else
begin
VAR68 = 1'b0;
VAR101 = 1'b0;
end
end
end
always @ (posedge VAR27, negedge VAR132)
begin
if (~VAR132)
begin
VAR1 <= 0;
VAR90 <= 0;
end
else
begin
VAR1 <= VAR68;
VAR90 <= VAR101;
end
end
assign VAR58 = (VAR137) ? VAR1 : VAR68;
assign VAR161 = (VAR137) ? VAR90 : VAR101;
always @
begin
if (VAR46)
begin
if (VAR48 && VAR40)
begin
VAR34 = VAR184;
VAR11 = VAR170;
end
else
begin
VAR34 = {(VAR188){1'b0}};
VAR11 = {(VAR93){1'b0}};
end
end
else
begin
if (VAR22 && VAR160)
begin
VAR34 = VAR120 ;
VAR11 = VAR29;
end
else
begin
VAR34 = {(VAR188){1'b0}};
VAR11 = {(VAR93){1'b0}};
end
end
end
always @ (posedge VAR27, negedge VAR132)
begin
if (~VAR132)
begin
VAR134 <= 0;
VAR37 <= 0;
end
else
begin
VAR134 <= VAR34 ;
VAR37 <= VAR11;
end
end
assign VAR97 = (VAR137) ? VAR134 : VAR34 ;
assign VAR83 = (VAR137) ? VAR37 : VAR11;
always @(*)
begin
if (VAR46)
begin
if (VAR48 && VAR40)
begin
VAR73 = VAR78;
VAR107 = VAR12;
end
else
begin
VAR73 = 1'b0;
VAR107 = 1'b0;
end
end
else
begin
if (VAR22 && VAR160)
begin
VAR73 = VAR7;
VAR107 = VAR45;
end
else
begin
VAR73 = 1'b0;
VAR107 = 1'b0;
end
end
end
always @ (posedge VAR27, negedge VAR132)
begin
if (~VAR132)
begin
VAR128 <= 0;
VAR181 <= 0;
end
else
begin
VAR128 <= VAR73;
VAR181 <= VAR107;
end
end
assign VAR52 = (VAR137) ? VAR128 : VAR73;
assign VAR70 = (VAR137) ? VAR181 : VAR107;
end
endgenerate
assign VAR23 = VAR19;
always @(posedge VAR27, negedge VAR132)
begin
if (!VAR132)
begin
VAR24 <= 1'b0;
end
else
begin
if (VAR187 || VAR131)
begin
VAR24 <= VAR21;
end
else
begin
VAR24 <= VAR64;
end
end
end
generate
genvar VAR30;
for (VAR30 = 0; VAR30 < VAR121*VAR124; VAR30 = VAR30 + 1)
begin : VAR79
assign VAR122[VAR30] = ~VAR100[VAR30] | ~VAR24;
end
endgenerate
endmodule
|
lgpl-3.0
|
fallen/milkymist-mmu
|
cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v
| 3,300 |
module MODULE1 #(
parameter VAR7 = 4'h0
) (
input VAR12,
input VAR15,
input [13:0] VAR10,
input VAR17,
input [31:0] VAR6,
output reg [31:0] VAR25,
output reg VAR8,
output reg VAR22,
output reg VAR11,
output reg VAR9,
output reg VAR13,
output reg VAR19,
output reg VAR5,
output reg [12:0] VAR1,
output reg [1:0] VAR2,
output reg [2:0] VAR20,
output reg [2:0] VAR24,
output reg VAR26,
output reg [10:0] VAR16,
output reg [3:0] VAR4,
output reg [1:0] VAR27,
output reg VAR3,
output reg VAR23,
output reg VAR18,
output reg VAR14
);
wire VAR21 = VAR10[13:10] == VAR7;
always @(posedge VAR12) begin
if(VAR15) begin
VAR25 <= 32'd0;
VAR8 <= 1'b1;
VAR22 <= 1'b1;
VAR11 <= 1'b0;
VAR1 <= 13'd0;
VAR2 <= 2'd0;
VAR20 <= 3'd2;
VAR24 <= 3'd2;
VAR26 <= 1'b0;
VAR16 <= 11'd620;
VAR4 <= 4'd6;
VAR27 <= 2'd2;
end else begin
VAR9 <= 1'b1;
VAR13 <= 1'b1;
VAR19 <= 1'b1;
VAR5 <= 1'b1;
VAR3 <= 1'b0;
VAR23 <= 1'b0;
VAR18 <= 1'b0;
VAR25 <= 32'd0;
if(VAR21) begin
if(VAR17) begin
case(VAR10[1:0])
2'b00: begin
VAR8 <= VAR6[0];
VAR22 <= VAR6[1];
VAR11 <= VAR6[2];
end
2'b01: begin
VAR9 <= ~VAR6[0];
VAR13 <= ~VAR6[1];
VAR19 <= ~VAR6[2];
VAR5 <= ~VAR6[3];
VAR1 <= VAR6[16:4];
VAR2 <= VAR6[18:17];
end
2'b10: begin
VAR20 <= VAR6[2:0];
VAR24 <= VAR6[5:3];
VAR26 <= VAR6[6];
VAR16 <= VAR6[17:7];
VAR4 <= VAR6[21:18];
VAR27 <= VAR6[23:22];
end
2'b11: begin
VAR3 <= VAR6[0];
VAR23 <= VAR6[1];
VAR18 <= VAR6[2];
VAR14 <= VAR6[3];
end
endcase
end
case(VAR10[1:0])
2'b00: VAR25 <= {VAR11, VAR22, VAR8};
2'b01: VAR25 <= {VAR2, VAR1, 4'h0};
2'b10: VAR25 <= {VAR27, VAR4, VAR16, VAR26, VAR24, VAR20};
2'b11: VAR25 <= 4'd0;
endcase
end
end
end
endmodule
|
lgpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry.v
| 4,336 |
module MODULE1 #
(
parameter VAR8 = "VAR11"
)
(
input wire VAR4,
input wire VAR3,
input wire VAR2,
output wire VAR6
);
generate
if ( VAR8 == "VAR1" ) begin : VAR13
assign VAR6 = (VAR4 & VAR3) | (VAR2 & ~VAR3);
end else begin : VAR5
VAR10 VAR7
(
.VAR9 (VAR6),
.VAR12 (VAR4),
.VAR2 (VAR2),
.VAR3 (VAR3)
);
end
endgenerate
endmodule
|
gpl-3.0
|
vad-rulezz/megabot
|
minsoc/rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
| 8,651 |
module MODULE1 (VAR37, VAR7, VAR22, VAR30, VAR27, VAR36,
VAR5, VAR21, VAR3, VAR15, VAR9, VAR28,
VAR12, VAR29, VAR4, VAR38, VAR13, VAR6, VAR1, VAR31,
VAR11, VAR34, VAR10, VAR24, VAR17, VAR25,
VAR14, VAR19, VAR23, VAR32, VAR26, VAR16
);
input VAR38; input VAR13; input VAR37; input VAR7; input [1:0] VAR22; input VAR30; input VAR27; input VAR36; input VAR5; input VAR21; input VAR3; input VAR24; input VAR15; input VAR9; input VAR28; input VAR12; input VAR29; input VAR4; input [15:0] VAR6; input [15:0] VAR1; input VAR31; input VAR11; input VAR34;
input VAR10;
output [15:0] VAR17; output [15:0] VAR25; output VAR14; output VAR19; output VAR23; output VAR32; output VAR26; output [2:0] VAR16;
wire VAR20;
wire VAR2;
wire VAR18;
wire VAR33;
wire VAR8;
wire VAR35;
reg [15:0] VAR25;
reg [15:0] VAR17;
reg [2:0] VAR16;
assign VAR18 = VAR7 | VAR37 | (|VAR22) | VAR30
| VAR27 | VAR36 | VAR5 | VAR21 & ~VAR14 & VAR4;
assign VAR2 = VAR21 & VAR14 & ~VAR4 | VAR37 & VAR23
| VAR36 & VAR19 | VAR3 | VAR15 | VAR9 | VAR28 | VAR12;
always @ (posedge VAR38 or posedge VAR13)
begin
if(VAR13)
VAR25 <= 16'h0;
end
else
begin
if(VAR2)
VAR25 <= 16'h0;
end
else
if(VAR18)
VAR25 <= VAR25 + 16'd1;
end
end
assign VAR19 = &VAR25[2:0];
assign VAR23 = &VAR25[3:0];
assign VAR26 = VAR25 >= (((VAR6-16'd4)<<1) -1);
assign VAR20 = VAR25[13:0] == 14'h17b7;
assign VAR14 = VAR25[13:0] == 14'h17b7 & ~VAR11;
assign VAR8 = VAR22[1] & ~VAR35
| VAR5 & (&VAR25[6:0])
| (VAR30 | VAR27) & VAR25[0] & ~VAR35;
assign VAR33 = VAR29 | VAR3 & VAR4 | VAR34;
always @ (posedge VAR38 or posedge VAR13)
begin
if(VAR13)
VAR17[15:0] <= 16'h0;
end
else
begin
if(VAR33)
VAR17[15:0] <= 16'h0;
end
else
if(VAR8)
VAR17[15:0] <= VAR17[15:0] + 16'd1;
end
end
assign VAR32 = VAR17[15:0] == VAR1[15:0] & ~VAR31;
assign VAR35 = &VAR17[15:0];
always @ (posedge VAR38 or posedge VAR13)
begin
if(VAR13)
VAR16 <= 3'h0;
end
else
begin
if(VAR22[1] & VAR16 == 3'h4 | VAR12 | VAR34)
VAR16 <= 3'h0;
end
else
if(VAR10 & (VAR24 | VAR22[1] & (|VAR16[2:0])))
VAR16 <= VAR16 + 3'd1;
end
end
endmodule
|
gpl-2.0
|
chriz2600/DreamcastHDMI
|
Core/source/dc_video_reconfig.v
| 2,423 |
module MODULE1(
input VAR2,
input [7:0] VAR5,
output VAR8 VAR6,
output VAR1
);
reg [7:0] VAR7 = 0;
reg VAR4;
VAR8 VAR3;
|
mit
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPM_Toggle_PIR.v
| 6,309 |
module MODULE1
(
VAR21 ,
VAR10 ,
VAR20 ,
VAR9 ,
VAR19 ,
VAR18 ,
VAR12
);
input VAR21 ;
input VAR10 ;
output VAR20 ;
output VAR9 ;
input VAR19 ;
output VAR18 ;
input VAR12 ;
parameter VAR16 = 6;
parameter VAR14 = 6'b000001;
parameter VAR8 = 6'b000010;
parameter VAR4 = 6'b000100; parameter VAR1 = 6'b001000; parameter VAR7 = 6'b010000; parameter VAR17 = 6'b100000;
reg [VAR16-1:0] VAR2 ;
reg [VAR16-1:0] VAR11 ;
reg VAR15 ;
reg [9:0] VAR3 ;
wire VAR5 ;
wire VAR13 ;
reg VAR6 ;
assign VAR5 = (10'b0000001001 == VAR3[9:0]); assign VAR13 = (10'b0110001111 == VAR3[9:0]);
always @ (posedge VAR21, posedge VAR10) begin
if (VAR10) begin
VAR2 <= VAR14;
end else begin
VAR2 <= VAR11;
end
end
always @ ( * ) begin
case (VAR2)
VAR14: begin
VAR11 <= VAR8;
end
VAR8: begin
VAR11 <= (VAR19)? VAR4:VAR8;
end
VAR4: begin
VAR11 <= VAR1;
end
VAR1: begin
VAR11 <= (VAR5)? VAR7:VAR1;
end
VAR7: begin
VAR11 <= VAR17;
end
VAR17: begin
VAR11 <= (VAR13)? ((VAR19)? VAR4:VAR8):VAR17;
end
default:
VAR11 <= VAR8;
endcase
end
always @ (posedge VAR21, posedge VAR10) begin
if (VAR10) begin
VAR15 <= 0;
VAR3[9:0] <= 0;
VAR6 <= 0;
end else begin
case (VAR11)
VAR14: begin
VAR15 <= 0;
VAR3[9:0] <= 0;
VAR6 <= 0;
end
VAR8: begin
VAR15 <= 1;
VAR3[9:0] <= 0;
VAR6 <= 0;
end
VAR4: begin
VAR15 <= 0;
VAR3[9:0] <= 10'b0000000000;
VAR6 <= 1;
end
VAR1: begin
VAR15 <= 0;
VAR3[9:0] <= VAR3[9:0] + 1'b1;
VAR6 <= 1;
end
VAR7: begin
VAR15 <= 0;
VAR3[9:0] <= 10'b0000000000;
VAR6 <= 0;
end
VAR17: begin
VAR15 <= 0;
VAR3[9:0] <= VAR3[9:0] + 1'b1;
VAR6 <= 0;
end
endcase
end
end
assign VAR20 = VAR15 | VAR13 ;
assign VAR9 = VAR13 ;
assign VAR18 = VAR6 ;
endmodule
|
gpl-3.0
|
eda-globetrotter/MarcheProcessor
|
processor/spare/build1/regfile.v
| 1,844 |
module MODULE1(VAR3, VAR4, VAR7, VAR2, VAR5, clk);
parameter VAR6 = 8; parameter VAR1 = 8;
output [VAR1-1:0] VAR3;
input [VAR1-1:0] VAR4;
input clk;
input VAR5;
input [VAR6-1:0] VAR7, VAR2;
reg [VAR1-1:0] VAR3; reg [VAR6-1:0] MODULE1 [VAR1-1:0];
always @(posedge clk)
begin
if(VAR5)
begin
MODULE1[VAR7] <= VAR4;
end
else
begin
VAR3<=MODULE1[VAR2];
end
end
endmodule
|
mit
|
ychaim/FPGA-Litecoin-Miner
|
ICARUS-LX150/pbkdfengine.v
| 20,275 |
module MODULE1
(VAR31, VAR77, VAR58, VAR25, VAR23, VAR90, VAR108, VAR44, VAR7, VAR103, VAR24,
VAR40, VAR57, VAR35, VAR48, VAR45, VAR94, VAR88);
input VAR31; input VAR77;
input [255:0] VAR58;
input [255:0] VAR25;
input [127:0] VAR23;
input [31:0] VAR90;
input [3:0] VAR108;
output [31:0] VAR44;
output [31:0] VAR7;
output VAR103; input VAR24;
parameter VAR41 = 8; input [VAR41-1:0] VAR57;
output [VAR41-1:0] VAR40;
input VAR35, VAR48; output VAR45;
output VAR94;
output reg VAR88 = 1'b0;
reg [4:0]VAR71 = 4'd0;
reg reset = 1'b0;
assign VAR45 = reset;
reg [23:0]VAR30 = 24'd0;
always @ (posedge VAR77)
begin
VAR71 <= VAR71 + 1'd1;
if (VAR71 == 0)
reset <= 1'b1;
if (VAR71 == 31)
begin
reset <= 1'b0;
VAR71 <= 31;
end
VAR30 <= VAR30 + 1'd1;
if (VAR30 == 2500000) begin
VAR30 <= 24'd0;
VAR71 <= 5'd0;
end
if (VAR24)
VAR71 <= 5'd0;
end
reg [31:0] VAR69 = 32'hffffffff; VAR16
reg [27:0] VAR27 = 28'h318f; else
reg [27:0] VAR27 = 28'd0; VAR16
wire [31:0] VAR62;
assign VAR62 = { VAR108, VAR27 };
reg [31:0] VAR62 = 32'd0; VAR16
assign VAR44 = VAR62;
reg [31:0] VAR82 = 32'd0; reg [31:0] VAR72 = 32'd0;
assign VAR7 = VAR72;
reg VAR103 = 1'b0;
reg [2:0] VAR5 = 3'd0;
reg [255:0] VAR96;
reg [511:0] VAR97;
wire [255:0] VAR61;
reg [255:0] VAR2 = 256'd0; reg [255:0] VAR9 = 256'd0; reg [255:0] VAR100 = 256'd0; VAR1 VAR106
reg [255:0] VAR8 = 256'd0; VAR16
reg [2:0] VAR21 = 3'd0; reg [1023:0] VAR101 = 1024'd0; reg [5:0] VAR89 = 6'd0;
wire VAR11;
assign VAR11 = (VAR89 != 6'b0);
assign VAR40 = VAR101[1023:1024-VAR41];
wire [1023:0] VAR84;
genvar VAR12;
generate
for (VAR12 = 0; VAR12 < 32; VAR12 = VAR12 + 1) begin : VAR95
wire [31:0] VAR67;
assign VAR67 = VAR101[VAR3(VAR12)]; assign VAR84[VAR3(VAR12)] = { VAR67[7:0], VAR67[15:8], VAR67[23:16], VAR67[31:24] };
end
endgenerate
reg VAR26 = 1'b0; reg VAR66 = 1'b0; wire VAR14;
wire VAR36;
reg VAR104 = 1'b0;
reg VAR75 = 1'b0;
wire VAR56;
wire VAR13;
reg [4:0]VAR80 = 0; reg [4:0]VAR85 = 0;
always @ (posedge VAR31)
begin
VAR80[0] <= VAR35;
if (VAR35 & ~ VAR80[0])
VAR80[1] <= ~ VAR80[1];
VAR85[0] <= VAR48;
if (VAR48 & ~ VAR85[0])
VAR85[1] <= ~ VAR85[1]; end
always @ (posedge VAR77)
begin
VAR80[4:2] <= VAR80[3:1];
VAR85[4:2] <= VAR85[3:1];
if (VAR104)
VAR26 <= 1'b1;
if (VAR56)
VAR26 <= 1'b0; if (VAR13)
VAR66 <= 1'b1;
if (VAR75)
VAR66 <= 1'b0;
if (reset)
begin VAR26 <= 1'b0;
VAR66 <= 1'b0;
end
end
assign VAR56 = VAR26 & (VAR80[3] ^ VAR80[4]);
assign VAR13 = ~VAR66 & (VAR85[3] ^ VAR85[4]);
assign VAR14 = VAR56 ? 1'b0 : VAR104 ? 1'b1 : VAR26;
assign VAR36 = VAR75 ? 1'b0 : VAR13 ? 1'b1 : VAR66;
assign VAR94 = VAR14;
reg [3:0]VAR78 = 1'b0;
reg [3:0]VAR79 = 1'b0;
reg [3:0]VAR46 = 1'b0;
parameter VAR52=0,
VAR43= 1, VAR29= 2, VAR70= 3, VAR74= 4, VAR91= 5, VAR42= 6, VAR39= 7, VAR87= 8, VAR22= 9, VAR93=10, VAR37=11, VAR73=12, VAR38=13, VAR92=14, VAR107=15, VAR55=16, VAR81=17, VAR47=18, VAR32=19, VAR28=20, VAR99=21, VAR98=22, VAR4=41, VAR59=42, VAR34=23, VAR86=24, VAR63=25, VAR19=26, VAR51=27, VAR65=28, VAR17=29, VAR33=30, VAR76=31, VAR53=32, VAR50=33, VAR68=34,
VAR49=35, VAR64=36, VAR6=37, VAR54=38, VAR60=39, VAR105=40;
reg [5:0] state = VAR52;
reg VAR83 = 0; reg VAR18 = 0;
always @ (posedge VAR77)
begin
VAR104 <= 1'b0; VAR75 <= 1'b0;
VAR103 <= 1'b0;
VAR46[3:1] <= VAR46[2:0];
end
if (VAR24) else
if (VAR24 || (VAR69 != VAR23[127:96]))
begin
end
VAR62 <= VAR23[127:96]; else
VAR27 <= VAR23[123:96]; VAR16
VAR69 <= VAR23[127:96];
end
if (reset == 1'b1)
begin
state <= VAR52;
VAR18 <= 1'b0;
end
else
begin
case (state)
VAR52: begin
if (VAR36 & ~VAR18)
begin
VAR79[0] <= ~VAR79[0]; state <= VAR59;
end
else
begin
if (VAR18 || !VAR14) begin
VAR18 <= 1'b0;
VAR83 <= 1'b0;
VAR96 <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
VAR97 <= { VAR25, VAR58 }; VAR21 <= 3'd1;
VAR89 <= 6'd0;
if (VAR36) VAR83 <= 1'b1;
state <= VAR43;
end
end
end
VAR43: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR29;
end
end
VAR29: begin state <= VAR70;
end
VAR70: begin VAR96 <= VAR61;
VAR97 <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
VAR83 ? VAR82 : VAR62, VAR23[95:0] };
state <= VAR74;
end
VAR74: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR91;
end
end
VAR91: begin state <= VAR42;
end
VAR42: begin VAR2 <= VAR61; VAR96 <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
VAR97 <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
VAR61 ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
VAR89 <= 6'd0;
if (VAR83)
state <= VAR34;
end
else
state <= VAR39;
end
VAR39: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR87;
end
end
VAR87: begin state <= VAR22;
end
VAR22: begin VAR96 <= VAR61;
VAR97 <= { VAR25, VAR58 }; state <= VAR93;
end
VAR93: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR37;
end
end
VAR37: begin state <= VAR73;
end
VAR73: begin VAR9 <= VAR61; VAR96 <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
VAR97 <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
VAR2 ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
VAR89 <= 6'd0;
state <= VAR38;
end
VAR38: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR92;
end
end
VAR92: begin state <= VAR107;
end
VAR107: begin VAR100 <= VAR61; VAR96 <= VAR9;
VAR97 <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, VAR21, VAR62, VAR23[95:0] }; VAR21 <= VAR21 + 1'd1; VAR89 <= 6'd0;
state <= VAR55;
end
VAR55: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR81;
end
end
VAR81: begin state <= VAR47;
end
VAR47: begin VAR96 <= VAR100;
VAR97 <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, VAR61 };
state <= VAR32;
end
VAR32: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR28;
end
end
VAR28: begin state <= VAR99;
end
VAR99: begin
VAR2 <= VAR61;
VAR78[0] <= ~VAR78[0];
if (VAR21 == 3'd5)
begin
VAR5 <= 3'd7;
state <= VAR98;
end
else begin
VAR96 <= VAR9;
VAR97 <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, VAR21, VAR62, VAR23[95:0] }; VAR21 <= VAR21 + 1'd1; VAR89 <= 6'd0;
state <= VAR55;
end
end
VAR98: begin
VAR5 <= VAR5 - 1'd1;
if (VAR5 == 0)
begin
VAR27 <= VAR27 + 1'd1;
VAR62 <= VAR62 + 1'd1;
VAR79[0] <= ~VAR79[0];
state <= VAR4;
end
end
VAR4: begin if (VAR46[3] != VAR46[2])
begin
VAR104 <= 1'd1; state <= VAR52;
end
end
VAR59: begin if (VAR46[3] != VAR46[2])
begin
VAR18 <= 1'd1; state <= VAR52;
end
end
VAR34: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR86;
end
end
VAR86: begin state <= VAR63;
end
VAR63: begin VAR96 <= VAR61;
VAR97 <= VAR84[511:0]; state <= VAR19;
end
VAR19: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR51;
end
end
VAR51: begin state <= VAR65;
end
VAR65: begin VAR96 <= VAR61;
VAR97 <= VAR84[1023:512]; state <= VAR17;
end
VAR17: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR33;
end
end
VAR33: begin state <= VAR76;
end
VAR76: begin VAR96 <= VAR61;
VAR97 <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= VAR53;
end
VAR53: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR50;
end
end
VAR50: begin state <= VAR68;
end
VAR68: begin VAR9 <= VAR61; VAR96 <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
VAR97 <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
VAR2 ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
VAR89 <= 6'd0;
state <= VAR49;
end
VAR49: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR64;
end
end
VAR64: begin state <= VAR6;
end
VAR6: begin VAR96 <= VAR61;
VAR97 <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, VAR9 };
state <= VAR54;
end
VAR54: begin VAR89 <= VAR89 + 6'd1;
if (VAR89 == 6'd63)
begin
VAR89 <= 6'd0;
state <= VAR60;
end
end
VAR60: begin state <= VAR105;
end
VAR105: begin VAR1 VAR106
VAR8 <= VAR61; VAR16
if ( { VAR61[231:224], VAR61[239:232], VAR61[247:240], VAR61[255:248] } < VAR90)
begin
VAR72 <= VAR82;
VAR103 <= 1'b1; end
state <= VAR52;
VAR83 <= 1'b0;
VAR75 <= 1'b1; end
endcase
end
end
reg [10:0]VAR10 = 11'd0;
always @ (posedge VAR31)
begin
if (reset)
begin
VAR88 <= 1'b0;
VAR10 <= 11'd0;
end
VAR78[3:1] <= VAR78[2:0];
if (VAR78[3] != VAR78[2])
begin
VAR101[255:0] <= VAR101[511:256];
VAR101[511:256] <= VAR101[767:512];
VAR101[767:512] <= VAR101[1023:768];
VAR101[1023:768] <= VAR2;
VAR82 <= VAR62; end
VAR79[3:1] <= VAR79[2:0];
if (VAR79[3] != VAR79[2])
begin
VAR88 <= 1'b1;
end
if (VAR88)
begin
VAR10 <= VAR10 + 1'b1;
VAR101 <= { VAR101[1023-VAR41:0], VAR82[31:32-VAR41] };
VAR82 <= { VAR82[31-VAR41:0], VAR57 };
end
if (VAR10 == (1024+32)/VAR41-1)
begin
VAR46[0] = ~VAR46[0];
VAR10 <= 0;
VAR88 <= 0;
end
end
VAR102 # (.VAR15(64)) VAR20 (
.clk(VAR77),
.VAR11(VAR11),
.VAR89(VAR89),
.VAR96(VAR96),
.VAR97(VAR97),
.VAR61(VAR61)
);
endmodule
|
gpl-3.0
|
fpgaminer/Open-Source-FPGA-Bitcoin-Miner
|
projects/DE2_115_makomk_serial/sha256_transform.v
| 7,740 |
module MODULE3 #(
parameter VAR12 = 6'd4
) (
input clk,
input VAR29,
input [5:0] VAR74,
input [255:0] VAR18,
input [511:0] VAR67,
output reg [255:0] VAR4
);
localparam VAR62 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
reg [31:0] VAR60 = 32'd0;
reg [255:0] VAR65 = 0;
reg [511:0] VAR75 = 0;
genvar VAR33;
generate
for (VAR33 = 0; VAR33 < 64/VAR12; VAR33 = VAR33 + 1) begin : VAR23
wire [31:0] VAR19;
wire [255:0] state;
wire [31:0] VAR53;
wire [31:0] VAR27, VAR40, VAR47, VAR48;
reg [479:0] VAR50;
wire [31:0] VAR46 = VAR62[32*(63-VAR12*VAR33-VAR74-1) +: 32];
if (VAR33 == 0)
assign VAR48 = VAR75[479:448];
end
else if (VAR33 == 1)
MODULE4 #(.VAR8(1)) VAR43 (clk, VAR75[511:480], VAR48);
else
MODULE4 #(.VAR8(1)) VAR43 (clk, VAR23[VAR33-2].VAR19, VAR48);
if (VAR33 == 0)
assign VAR47 = VAR75[319:288];
else if (VAR33 < 5)
MODULE4 # (.VAR8(VAR33)) VAR72 (clk, VAR75[VAR26(9+VAR33)], VAR47);
else
MODULE4 # (.VAR8(5)) VAR72 (clk, VAR23[VAR33-5].VAR48, VAR47);
if (VAR33 == 0)
assign VAR40 = VAR75[63:32];
else if(VAR33 < 8)
MODULE4 #(.VAR8(VAR33)) VAR13 (clk, VAR75[VAR26(1+VAR33)], VAR40);
else
MODULE4 #(.VAR8(8)) VAR13 (clk, VAR23[VAR33-8].VAR47, VAR40);
if (VAR33 == 0)
assign VAR27 = VAR75[31:0];
else
MODULE4 # (.VAR8(1)) VAR56 (clk, VAR23[VAR33-1].VAR40, VAR27);
if(VAR33 == 0)
MODULE2 VAR1 (
.clk(clk),
.VAR45(VAR46),
.VAR18(VAR29 ? state : VAR65),
.VAR69(VAR60),
.VAR58(VAR40),
.VAR54(state),
.VAR3(VAR53)
);
else
MODULE2 VAR1 (
.clk(clk),
.VAR45(VAR46),
.VAR18(VAR23[VAR33-1].state),
.VAR69(VAR23[VAR33-1].VAR53),
.VAR58(VAR40),
.VAR54(state),
.VAR3(VAR53)
);
MODULE1 MODULE2 (
.clk(clk),
.VAR17(VAR27),
.VAR58(VAR40),
.VAR34(VAR47),
.VAR68(VAR48),
.VAR20(VAR19)
);
end
endgenerate
always @ (posedge clk)
begin
VAR65 <= VAR18;
VAR75 <= VAR67;
VAR60 <= VAR18[VAR26(7)] + VAR67[31:0] + 32'h428a2f98;
if (!VAR29)
begin
VAR4[VAR26(0)] <= VAR18[VAR26(0)] + VAR23[64/VAR12-6'd1].state[VAR26(0)];
VAR4[VAR26(1)] <= VAR18[VAR26(1)] + VAR23[64/VAR12-6'd1].state[VAR26(1)];
VAR4[VAR26(2)] <= VAR18[VAR26(2)] + VAR23[64/VAR12-6'd1].state[VAR26(2)];
VAR4[VAR26(3)] <= VAR18[VAR26(3)] + VAR23[64/VAR12-6'd1].state[VAR26(3)];
VAR4[VAR26(4)] <= VAR18[VAR26(4)] + VAR23[64/VAR12-6'd1].state[VAR26(4)];
VAR4[VAR26(5)] <= VAR18[VAR26(5)] + VAR23[64/VAR12-6'd1].state[VAR26(5)];
VAR4[VAR26(6)] <= VAR18[VAR26(6)] + VAR23[64/VAR12-6'd1].state[VAR26(6)];
VAR4[VAR26(7)] <= VAR18[VAR26(7)] + VAR23[64/VAR12-6'd1].state[VAR26(7)];
end
end
endmodule
module MODULE1 (clk, VAR17, VAR58, VAR34, VAR68, VAR20);
input clk;
input [31:0] VAR17, VAR58, VAR34, VAR68;
output reg [31:0] VAR20;
wire [31:0] VAR22, VAR25;
VAR55 VAR73 (VAR58, VAR22);
VAR30 VAR61 (VAR68, VAR25);
wire [31:0] VAR49 = VAR25 + VAR34 + VAR22 + VAR17;
always @ (posedge clk)
VAR20 <= VAR49;
endmodule
module MODULE2 (clk, VAR45, VAR18, VAR69, VAR58, VAR54, VAR3);
input clk;
input [31:0] VAR45, VAR69, VAR58;
input [255:0] VAR18;
output reg [255:0] VAR54;
output reg [31:0] VAR3;
wire [31:0] VAR9, VAR35, VAR41, VAR51;
VAR66 VAR11 (VAR18[VAR26(0)], VAR9);
VAR71 VAR31 (VAR18[VAR26(4)], VAR35);
VAR7 VAR5 (VAR18[VAR26(4)], VAR18[VAR26(5)], VAR18[VAR26(6)], VAR41);
VAR16 VAR42 (VAR18[VAR26(0)], VAR18[VAR26(1)], VAR18[VAR26(2)], VAR51);
wire [31:0] VAR39 = VAR69 + VAR35 + VAR41;
wire [31:0] VAR38 = VAR9 + VAR51;
wire [31:0] VAR2 = VAR18[VAR26(6)] + VAR58 + VAR45;
always @ (posedge clk)
begin
VAR3 <= VAR2;
VAR54[VAR26(7)] <= VAR18[VAR26(6)];
VAR54[VAR26(6)] <= VAR18[VAR26(5)];
VAR54[VAR26(5)] <= VAR18[VAR26(4)];
VAR54[VAR26(4)] <= VAR18[VAR26(3)] + VAR39;
VAR54[VAR26(3)] <= VAR18[VAR26(2)];
VAR54[VAR26(2)] <= VAR18[VAR26(1)];
VAR54[VAR26(1)] <= VAR18[VAR26(0)];
VAR54[VAR26(0)] <= VAR39 + VAR38;
end
endmodule
module MODULE4 # (
parameter VAR8 = 1
) (
input clk,
input [31:0] VAR21,
output [31:0] VAR44
);
genvar VAR33;
generate
if (VAR8 >= 4)
begin
VAR59 # (.VAR37(1), .VAR70(VAR8), .VAR6(32)) VAR28
(.VAR15(1'b1), .VAR52(1'b0), .VAR64(clk), .VAR10(VAR21), .VAR63(), .VAR32(VAR44) );
end
else
begin
for (VAR33 = 0; VAR33 < VAR8; VAR33 = VAR33 + 1) begin : VAR36
reg [31:0] VAR24;
wire [31:0] VAR14;
if (VAR33 == 0)
assign VAR14 = VAR21;
end
else
assign VAR14 = VAR36[VAR33-1].VAR24;
always @ (posedge clk)
VAR24 <= VAR14;
end
assign VAR44 = VAR36[VAR8-1].VAR24;
end
endgenerate
endmodule
|
gpl-3.0
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_source_sync_output.v
| 12,731 |
module MODULE1
parameter VAR8 = 5
, parameter VAR56 = 3 , parameter VAR68 = 8
, parameter VAR22 = {VAR68 { 2'b01 } }
)
(
input VAR6
, input VAR18
, input [VAR68-1:0] VAR47
, input VAR59
, output VAR5
, input VAR64
, input VAR50 , input VAR19
, input VAR13
, input [VAR68:0] VAR43
, output VAR63
, output logic VAR66 , output logic [VAR68-1:0] VAR39 , output logic VAR37
, input VAR40
, input VAR65
, input VAR30 );
wire VAR52, VAR16;
wire [VAR68-1:0] VAR26;
VAR58 #(.VAR49(VAR68)) VAR62
(.VAR35(VAR6)
,.VAR33(VAR18)
,.VAR10(VAR5)
,.VAR24 (VAR47)
,.VAR14 (VAR59)
,.VAR57 (VAR52)
,.VAR31(VAR26)
,.VAR2(VAR16)
);
logic VAR70;
logic [VAR68-1:0] VAR61;
logic VAR48;
logic VAR54;
always @(posedge VAR64)
begin
VAR54 <= VAR50;
if (VAR13)
{ VAR37, VAR39 } <= VAR43;
end
else
begin
VAR37 <= VAR48;
if (VAR48)
VAR39 <= VAR61;
end
else
VAR39 <= VAR22 [0+:VAR68];
end
end
logic VAR3, VAR20;
always @(negedge VAR64)
begin
VAR66 <= VAR19 ? 1'b0 : VAR3;
end
always @(posedge VAR64)
begin
if (VAR19 === 1)
end
assign VAR3 = ~VAR66;
VAR38 @(posedge VAR64)
VAR20 <= VAR3;
assign VAR63 = ~VAR20;
wire VAR17;
assign VAR16 = VAR52 & ~VAR17;
VAR41 #(.VAR60(3)
,.VAR49(VAR68)
) VAR27
(
.VAR42(VAR6)
,.VAR67(VAR18)
,.VAR69(VAR16)
,.VAR21(VAR26)
,.VAR28(VAR17)
,.VAR36(VAR64)
,.VAR15(VAR50)
,.VAR72(VAR48)
,.VAR51(VAR61)
,.VAR46(VAR70)
);
logic [VAR56+1-1:0] VAR73;
always @(posedge VAR64)
begin
if (VAR50)
VAR73 <= 0;
end
else
if (VAR48)
VAR73 <= VAR73 + 1;
end
wire VAR44 = VAR73[VAR56];
logic VAR1, VAR53;
wire VAR7 = VAR44
? VAR1
: VAR53;
assign VAR48 = VAR7 & VAR70;
wire VAR12 = VAR48 & VAR44;
wire VAR71 = VAR48 & ~VAR44;
VAR25
,.VAR56(VAR56)
,.VAR32(1'b0)
,.VAR45(2)
,.VAR9(1)
) VAR23
(
.VAR42 (VAR65 )
,.VAR55(1'b1)
,.VAR67(VAR30)
,.VAR36 (VAR64)
,.VAR15(VAR50 )
,.VAR34 (VAR71)
,.VAR11(VAR40)
,.VAR4 (VAR53)
);
VAR25
,.VAR56(VAR56)
,.VAR32(1'b1)
,.VAR45(2)
,.VAR9(1)
) VAR29
(
.VAR42 (VAR65)
,.VAR55(1'b1)
,.VAR67(VAR30)
,.VAR36 (VAR64 )
,.VAR15 (VAR50 )
,.VAR34 (VAR12)
,.VAR11(VAR40)
,.VAR4(VAR1)
);
endmodule
|
bsd-3-clause
|
firedom/combin-for-FPGA
|
src/decoders38.v
| 2,278 |
module MODULE1(in, out, en);
input [0:2]in;
input [0:2]en;
output [0:7]out;
wire VAR2;
and
VAR3(VAR2, en[0], ~en[1], ~en[2]);
nand
VAR1(out[0], ~in[2], ~in[1], ~in[0], VAR2),
VAR10(out[1], ~in[2], ~in[1], in[0], VAR2),
VAR6(out[2], ~in[2], in[1], ~in[0], VAR2),
VAR5(out[3], ~in[2], in[1], in[0], VAR2),
VAR8(out[4], in[2], ~in[1], ~in[0], VAR2),
VAR4(out[5], in[2], ~in[1], in[0], VAR2),
VAR7(out[6], in[2], in[1], ~in[0], VAR2),
VAR9(out[7], in[2], in[1], in[0], VAR2);
endmodule
|
gpl-3.0
|
ckdur/mriscv_vivado_arty
|
mriscv_vivado.srcs/sources_1/ip/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_0_data_prbs_gen.v
| 4,725 |
module MODULE1 #
(
parameter VAR4 = 100,
parameter VAR14 = "VAR9",
parameter VAR2 = 32, parameter VAR10 = 32
)
(
input VAR12,
input VAR1,
input VAR7,
input VAR6, input [VAR2 - 1:0] VAR3,
output [VAR2 - 1:0] VAR11 );
reg [VAR2 - 1 :0] VAR8;
reg [VAR2 :1] VAR13;
integer VAR5;
always @ (posedge VAR12)
begin
if (VAR6 && VAR14 == "VAR9" || VAR7 )
begin
end
else if (VAR1) begin
end
end
always @ (VAR13[VAR2:1]) begin
VAR8 = VAR13[VAR2:1];
end
assign VAR11 = VAR8;
endmodule
|
mit
|
ShepardSiegel/ocpi
|
coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/controller/col_mach.v
| 18,166 |
module MODULE1 #
(
parameter VAR14 = 100,
parameter VAR38 = 3,
parameter VAR92 = "8",
parameter VAR12 = 12,
parameter VAR21 = 4,
parameter VAR43 = 8,
parameter VAR32 = 1,
parameter VAR13 = 0,
parameter VAR22 = 8,
parameter VAR89 = "VAR50",
parameter VAR49 = "VAR53",
parameter VAR59 = "VAR53",
parameter VAR106 = 31,
parameter VAR102 = 2,
parameter VAR24 = 0,
parameter VAR74 = 6,
parameter VAR11 = 4,
parameter VAR29 = 4,
parameter VAR83 = 2,
parameter VAR63 = 16
)
(
VAR121, VAR90, VAR15, VAR75,
VAR26, VAR7, VAR39, VAR52,
VAR65, VAR131, VAR27, VAR95, VAR117,
VAR82, VAR99, VAR130,
clk, rst, VAR86, VAR36, VAR25, VAR61,
VAR85, VAR81, VAR8, VAR66,
VAR78, VAR125, VAR100, VAR19
);
input clk;
input rst;
input VAR86;
output reg VAR121 = 1'b0;
generate
if ((VAR102 == 1) && ((VAR92 == "8") || (VAR89 == "VAR50")))
begin : VAR2
reg [1:0] VAR118;
wire [1:0] VAR5 = {VAR86, VAR118[1]};
always @(VAR118 or VAR86)
VAR121 = VAR86 || |VAR118;
end
if (((VAR102 == 2) && ((VAR92 == "8") || (VAR89 == "VAR50")))
|| ((VAR102 == 1) && ((VAR92 == "4") || (VAR89 == "VAR76"))))
begin : VAR104
always @(VAR86) VAR121 = VAR86;
end
endgenerate
reg [1:0] VAR80 = 2'b0;
reg [1:0] VAR4 = 2'b0;
input VAR36;
wire VAR45;
generate
if (VAR32 == 2) begin : VAR58
always @(VAR36 or VAR80 or rst or VAR86) begin
if (rst) VAR4 = 2'b0;
end
else begin
VAR4 = VAR80;
if (VAR86) VAR4 = 2'b1;
end
else if (|VAR80 && (VAR80 != {VAR36, 1'b1}))
VAR4 = VAR80 + 2'b1;
end
else VAR4 = 2'b0;
end
end
assign VAR45 = VAR36 ? (VAR80 == 2'b11) : VAR80[0];
end
else begin : VAR132
always @(VAR36 or rst or VAR86)
VAR4[0] = rst ? 1'b0 : VAR86 && VAR36;
assign VAR45 = VAR36 ? VAR80[0] : 1'b1;
end
endgenerate
reg [VAR32-1:0] VAR67 = {VAR32{1'b0}};
generate
if ((VAR24 == 1) || (VAR13 == 1)) begin : VAR112
always @(posedge clk) VAR67 <=
end
endgenerate
output wire [VAR32-1:0] VAR90;
assign VAR90 = (VAR13 == 1)
? VAR67[VAR32-1:0]
: (VAR49 == "VAR53")
? VAR80[VAR32-1:0]
: VAR4[VAR32-1:0];
input [VAR83:0] VAR25;
reg VAR87;
wire VAR75 = (VAR24 == 0)
? ((VAR86 || |VAR80) && VAR25[VAR83])
: ((VAR87 || |VAR67) && VAR25[VAR83]);
output wire [VAR22-1:0] VAR15;
assign VAR15 = {VAR22{VAR75}};
output wire VAR75;
assign VAR75 = (VAR13 == 1)
? ((VAR87 || |VAR67) && VAR25[VAR83])
: ((VAR86 || |VAR80) && VAR25[VAR83]);
input [VAR43-1:0] VAR61;
output wire [VAR43-1:0] VAR26;
generate
if (VAR13 == 1) begin : VAR54
reg [VAR43-1:0] VAR73;
always @(posedge clk) VAR73 <=
assign VAR26 = VAR73;
end
else begin : VAR129
assign VAR26 = VAR61;
end
endgenerate
wire VAR3 = (VAR86 || |VAR80) && ~VAR25[VAR83];
output wire [VAR22-1:0] VAR7;
assign VAR7 = {VAR22{VAR3}};
function integer VAR34 (input integer VAR109); begin
VAR109 = VAR109 - 1;
for (VAR34=1; VAR109>1; VAR34=VAR34+1)
VAR109 = VAR109 >> 1;
end
endfunction
localparam VAR17 = 1;
localparam VAR77 = VAR74 - 2;
localparam VAR47 = VAR29 - 2;
localparam VAR44 = VAR34(VAR77 + 1);
reg [VAR44-1:0] VAR70;
reg [VAR44-1:0] VAR110;
always @(VAR70 or VAR3 or rst or VAR75) begin
if (rst) VAR110 = {VAR44{1'b0}};
end
else begin
VAR110 = VAR70;
if (VAR75)
VAR110 = VAR47[VAR44-1:0];
end
else
if (VAR3)
VAR110 = VAR77[VAR44-1:0];
else
if (|VAR70)
VAR110 = VAR70 - VAR17[VAR44-1:0];
end end
localparam VAR33 = VAR11 - 2;
localparam VAR72 = VAR34(VAR33 + 1);
reg [VAR72-1:0] VAR108;
reg [VAR72-1:0] VAR107;
always @(VAR108 or rst or VAR75) begin
if (rst) VAR107 = {VAR72{1'b0}};
end
else begin
VAR107 = VAR108;
if (VAR75)
VAR107 = VAR33[VAR72-1:0];
end
else
if (|VAR108)
VAR107 = VAR108 - VAR17[VAR72-1:0];
end
end
wire VAR127 = (VAR110 != {VAR44{1'b0}});
reg VAR96;
output wire VAR39;
assign VAR39 = VAR86 || VAR75 || VAR96;
wire VAR115 = (VAR107 != {VAR72{1'b0}});
reg VAR6;
output wire VAR52;
assign VAR52 = VAR86 || VAR75 || VAR6;
input VAR85;
output wire VAR65;
output reg [VAR106-1:0] VAR131;
output reg VAR27;
output reg VAR95;
output reg VAR117;
output reg [VAR43-1:0] VAR82;
output reg [VAR32-1:0] VAR99;
output reg VAR130;
input VAR81;
input [VAR43-1:0] VAR8;
input VAR66;
input [VAR83-1:0] VAR78;
input [VAR38-1:0] VAR125;
input [VAR63-1:0] VAR100;
input [VAR63-1:0] VAR19;
wire [11:0] VAR1;
assign VAR1[10:0] = {VAR19[11], VAR19[9:0]};
assign VAR1[11] = VAR63 >= 14 ? VAR19[13] : 0;
wire [VAR12-1:0] VAR119 = VAR1[VAR12-1:0];
localparam VAR93 = VAR106-VAR32;
localparam VAR9 = 1 +
1 +
VAR43 +
VAR32 +
((VAR59 == "VAR53") ? 0 : 1+VAR93);
localparam VAR20 = (VAR9/6);
localparam VAR55 = VAR9 % 6;
localparam VAR35 = VAR20 + ((VAR55 == 0 ) ? 0 : 1);
localparam VAR123 = (VAR35*6);
generate
begin : VAR103
wire [VAR93:0] VAR79;
if (VAR21 == 1)
assign VAR79 = {VAR66, VAR125, VAR100, VAR119};
end
else
assign VAR79 = {VAR66,
VAR78,
VAR125,
VAR100,
VAR119};
wire [VAR9-1:0] VAR98;
if (VAR59 == "VAR53")
assign VAR98 = {VAR45,
VAR81,
VAR8,
VAR80[VAR32-1:0]};
else
assign VAR98 = {VAR45,
VAR81,
VAR8,
VAR80[VAR32-1:0],
VAR79};
wire [VAR123-1:0] VAR126;
reg [VAR123-1:0] VAR48;
if (VAR55 == 0)
assign VAR126 = VAR98;
else
assign VAR126 = {{6-VAR55{1'b0}}, VAR98};
wire [VAR123-1:0] VAR40;
reg [4:0] VAR101;
reg [4:0] VAR16;
wire [4:0] VAR114 = rst ? 5'b0 : VAR3
? (VAR101 + 5'b1)
: VAR101;
reg [4:0] VAR31;
wire [4:0] VAR18 = rst ? 5'b0 : VAR85
? (VAR31 + 5'b1)
: VAR31;
genvar VAR51;
for (VAR51=0; VAR51<VAR35; VAR51=VAR51+1) begin : VAR116
VAR62
.VAR105(64'h0000000000000000),
.VAR10(64'h0000000000000000),
.VAR30(64'h0000000000000000)
) VAR68 (
.VAR120(VAR40[((VAR51*6)+4)+:2]),
.VAR84(VAR40[((VAR51*6)+2)+:2]),
.VAR56(VAR40[((VAR51*6)+0)+:2]),
.VAR128(),
.VAR111(VAR48[((VAR51*6)+4)+:2]),
.VAR97(VAR48[((VAR51*6)+2)+:2]),
.VAR94(VAR48[((VAR51*6)+0)+:2]),
.VAR64(2'b0),
.VAR42(VAR18),
.VAR113(VAR18),
.VAR46(VAR18),
.VAR88(VAR16),
.VAR57(1'b1),
.VAR60(clk)
);
end
reg [VAR123-1:0] VAR41;
if (VAR59 == "VAR53") begin
reg VAR71;
always @(VAR85 or VAR41) begin
{VAR117,
VAR71,
VAR82,
VAR99} = VAR41[VAR9-1:0];
VAR131 = {VAR106{1'b0}};
VAR130 = VAR85 && ~VAR71;
VAR27 = 1'b0;
VAR95 = 1'b0;
end
assign VAR65 = 1'b0;
end
else begin
wire VAR124;
wire VAR71;
wire [VAR43-1:0] VAR28;
wire [VAR32-1:0] VAR23;
wire [VAR106-1:0] VAR37;
assign {VAR124,
VAR71,
VAR28,
VAR23,
VAR65,
VAR37[VAR32+:VAR93]} =
{VAR41[VAR9-1:0]};
assign VAR37[0+:VAR32] = VAR23;
wire VAR91 = VAR85 && ~(VAR71 || VAR65);
always @(posedge clk) VAR130 <= VAR91;
wire VAR69 = VAR85 && ~VAR71;
wire VAR122 = VAR85 && ~VAR71 && VAR65;
end
end
endgenerate
endmodule
|
lgpl-3.0
|
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