repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
wsoltys/AtomFpga
|
mist/sd_card.v
| 13,986 |
module MODULE1 (
output [31:0] VAR31,
output reg VAR33,
output reg VAR29,
input VAR1,
output VAR4,
output VAR61,
input [7:0] VAR21,
input VAR56,
output [7:0] VAR26,
input VAR38,
input VAR48,
input VAR12,
input VAR17,
input VAR6,
output reg VAR54
);
reg VAR30 = 1'b0; always @(posedge VAR30 or posedge VAR1) begin
if(VAR1) VAR33 <= 1'b0;
end
else VAR33 <= 1'b1;
end
reg VAR40 = 1'b0; always @(posedge VAR40 or posedge VAR1) begin
if(VAR1) VAR29 <= 1'b0;
end
else VAR29 <= 1'b1;
end
wire [31:0] VAR35 = { 1'b0, VAR61, 30'h0 }; wire [7:0] VAR42 = 8'hfe;
localparam VAR59=4;
localparam VAR46 = 2'd0;
localparam VAR22 = 2'd1;
localparam VAR11 = 2'd2;
localparam VAR8 = 2'd3;
reg [1:0] VAR34 = VAR46;
localparam VAR5 = 3'd0;
localparam VAR71 = 3'd1;
localparam VAR69 = 3'd2;
localparam VAR2 = 3'd3;
localparam VAR24 = 3'd4;
localparam VAR64 = 3'd5;
localparam VAR28 = 3'd6;
reg [2:0] VAR67 = VAR5;
reg VAR13 = 1'b0; reg [6:0] VAR70;
reg VAR65;
reg VAR36;
reg [7:0] VAR14 = 8'h00;
reg [2:0] VAR18; reg [3:0] VAR45= 4'd15;
reg [31:0] VAR7;
assign VAR31 = VAR61?VAR7:{9'd0, VAR7[31:9]};
reg [7:0] VAR16;
reg [7:0] VAR49, VAR58, VAR39, VAR44;
reg [3:0] VAR53;
wire VAR15 = (VAR34 != VAR46);
reg VAR47 = 1'b0;
always @(negedge VAR1 or negedge VAR15) begin
if(!VAR15) VAR47 <= 1'b0;
end
else VAR47 <= 1'b1;
end
wire VAR25 = (VAR67 == VAR28);
reg VAR51 = 1'b0;
always @(negedge VAR1 or negedge VAR25) begin
if(!VAR25) VAR51 <= 1'b0;
end
else VAR51 <= 1'b1;
end
reg VAR52;
reg VAR43;
always @(posedge VAR17) begin
VAR43 <= VAR47;
VAR52 <= VAR51;
end
reg [7:0] buffer [511:0];
reg [8:0] VAR63;
reg VAR60;
wire VAR55 = VAR60 || VAR38;
reg [7:0] VAR3;
assign VAR26 = VAR3;
reg VAR37;
reg VAR41;
always @(posedge VAR55 or posedge VAR36) begin
if(VAR36 == 1) begin
VAR63 <= 9'd0;
VAR37 <= 1'b0;
VAR41 <= 1'b0;
end else begin
VAR3 <= buffer[VAR63];
VAR63 <= VAR63 + 9'd1;
if(VAR63 == 511) VAR37 <= 1'b1;
if(VAR63 == 15) VAR41 <= 1'b1;
end
end
reg [8:0] VAR66;
reg VAR62;
wire VAR23 = VAR56 || VAR62;
wire [7:0] VAR72 = (VAR14 == 8'h51)?VAR21:{VAR70, VAR6};
always @(posedge VAR23 or posedge VAR36) begin
if(VAR36 == 1)
VAR66 <= 9'd0;
end
else begin
buffer[VAR66] <= VAR72;
VAR66 <= VAR66 + 9'd1;
end
end
wire [7:0] VAR10 = 8'h05;
assign VAR4 = (VAR57 == 0);
reg [7:0] VAR32 [15:0];
reg [7:0] VAR50 [15:0];
reg [7:0] VAR9;
reg [7:0] VAR19;
reg [7:0] VAR27;
reg [5:0] VAR57 = 6'd0;
wire VAR68 = VAR9[0];
assign VAR61 = VAR48 && VAR68;
always @(posedge VAR56) begin
if(!VAR1 && (VAR57 <= 32)) begin
if(VAR57 < 16) VAR32[VAR57[3:0]] <= VAR21;
if((VAR57 >= 16) && (VAR57 < 32)) VAR50[VAR57[3:0]] <= VAR21;
if(VAR57 == 32) VAR9 <= VAR21;
VAR57 <= VAR57 + 6'd1;
end
end
always @(posedge VAR55) begin
VAR19 <= VAR32[VAR63[3:0]];
VAR27 <= VAR50[VAR63[3:0]];
end
always@(negedge VAR17) begin
if(VAR12 == 0) begin
VAR60 <= 1'b0;
VAR54 <= 1'b1; VAR30 <= 1'b0;
if(VAR45 == 5+VAR59) begin
VAR54 <= VAR16[~VAR18];
if(VAR18 == 7) begin
if((VAR14 == 8'h49)||(VAR14 == 8'h4a))
VAR34 <= VAR11;
if(VAR14 == 8'h51) begin
VAR34 <= VAR22; VAR30 <= 1'b1; end
end
end
else if((VAR53 > 0) && (VAR45 == 5+VAR59+1))
VAR54 <= VAR49[~VAR18];
end
else if((VAR53 > 1) && (VAR45 == 5+VAR59+2))
VAR54 <= VAR58[~VAR18];
end
else if((VAR53 > 2) && (VAR45 == 5+VAR59+3))
VAR54 <= VAR39[~VAR18];
else if((VAR53 > 3) && (VAR45 == 5+VAR59+4))
VAR54 <= VAR44[~VAR18];
else
VAR54 <= 1'b1;
case(VAR34)
VAR46: ;
VAR22: begin
if(VAR43 && (VAR18 == 7))
VAR34 <= VAR11;
end
VAR11: begin
VAR54 <= VAR42[~VAR18];
if(VAR18 == 7) begin
VAR34 <= VAR8; VAR60 <= 1'b1; end
end
VAR8: begin
if(VAR14 == 8'h51) VAR54 <= VAR3[~VAR18];
end
else if(VAR14 == 8'h49) VAR54 <= VAR27[~VAR18];
else if(VAR14 == 8'h4a) VAR54 <= VAR19[~VAR18];
else
VAR54 <= 1'b1;
if(VAR18 == 7) begin
if((VAR14 == 8'h51) && VAR37) VAR34 <= VAR46;
end
else if(((VAR14 == 8'h49)||(VAR14 == 8'h4a)) && VAR41) VAR34 <= VAR46;
else
VAR60 <= 1'b1; end
end
endcase
if(VAR67 == VAR64)
VAR54 <= VAR10[~VAR18];
if(VAR67 == VAR28)
VAR54 <= 1'b0;
end
end
reg VAR20 ;
always @(posedge VAR17 or posedge VAR12) begin
if(VAR12 == 1) begin
VAR18 <= 3'd0;
end else begin
VAR20 <= 1'b0;
VAR36 <= 1'b0;
VAR62 <= 1'b0;
VAR40 <= 1'b0;
VAR18 <= VAR18 + 3'd1;
if(VAR18 != 7)
VAR70[6:0] <= { VAR70[5:0], VAR6 };
end
else begin
if(VAR45 != 15)
VAR45 <= VAR45 + 4'd1;
if((VAR45 > 5) && (VAR67 == VAR5) &&
(VAR34 == VAR46) && VAR70[6:5] == 2'b01) begin
VAR45 <= 4'd0;
VAR14 <= { VAR70, VAR6};
VAR36 <= 1'b1;
VAR65 <= (VAR14 == 8'h77);
end
if(VAR45 == 0) VAR7[31:24] <= { VAR70, VAR6};
if(VAR45 == 1) VAR7[23:16] <= { VAR70, VAR6};
if(VAR45 == 2) VAR7[15:8] <= { VAR70, VAR6};
if(VAR45 == 3) VAR7[7:0] <= { VAR70, VAR6};
if(VAR45 == 4) begin
VAR16 <= 8'h04; VAR53 <= 4'd0;
if(VAR14 == 8'h40) begin
VAR13 <= 1'b1;
VAR16 <= 8'h01; end
else if(VAR13) begin
if(VAR14 == 8'h41)
VAR16 <= 8'h00;
end
else if(VAR14 == 8'h48) begin
VAR16 <= 8'h01; VAR49 <= 8'h00;
VAR58 <= 8'h00;
VAR39 <= 8'h01;
VAR44 <= 8'hAA;
VAR53 <= 4'd4;
end
else if(VAR14 == 8'h49)
VAR16 <= 8'h00;
end
else if(VAR14 == 8'h4a)
VAR16 <= 8'h00;
end
else if(VAR14 == 8'h50) begin
if(VAR7 == 32'd512)
end
VAR16 <= 8'h00; else
VAR16 <= 8'h40; end
else if(VAR14 == 8'h51)
VAR16 <= 8'h00;
end
else if(VAR14 == 8'h58) begin
VAR16 <= 8'h00; VAR67 <= VAR71; end
else if(VAR65 && (VAR14 == 8'h69))
VAR16 <= 8'h00;
else if(VAR14 == 8'h77)
VAR16 <= 8'h01;
else if(VAR14 == 8'h7a) begin
VAR16 <= 8'h00;
VAR49 <= VAR35[31:24]; VAR58 <= VAR35[23:16];
VAR39 <= VAR35[15:8];
VAR44 <= VAR35[7:0];
VAR53 <= 4'd4;
end
end
end
case(VAR67)
VAR5: ;
VAR71:
if({ VAR70, VAR6} == 8'hfe )
VAR67 <= VAR69;
VAR69: begin
VAR62 <= 1'b1;
if(VAR66 == 511)
VAR67 <= VAR2;
end
VAR2:
VAR67 <= VAR24;
VAR24:
VAR67 <= VAR64;
VAR64: begin
VAR67 <= VAR28;
VAR40 <= 1'b1; end
VAR28:
if(VAR52)
VAR67 <= VAR5;
default:
VAR20 <= 1'b1;
endcase
end
end
end
endmodule
|
apache-2.0
|
LSaldyt/qnp
|
output/vs/opt_var14_multi.v
| 18,150 |
module MODULE1(VAR14, VAR13, VAR2, VAR9, VAR11, VAR1, VAR3, VAR10, VAR7, VAR12, VAR15, VAR6, VAR4, VAR5, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wire 023;
wire 024;
wire 025;
wire 026;
wire 027;
wire 028;
wire 029;
wire 030;
wire 031;
wire 032;
wire 033;
wire 034;
wire 035;
wire 036;
wire 037;
wire 038;
wire 039;
wire 040;
wire 041;
wire 042;
wire 043;
wire 044;
wire 045;
wire 046;
wire 047;
wire 048;
wire 049;
wire 050;
wire 051;
wire 052;
wire 053;
wire 054;
wire 055;
wire 056;
wire 057;
wire 058;
wire 059;
wire 060;
wire 061;
wire 062;
wire 063;
wire 064;
wire 065;
wire 066;
wire 067;
wire 068;
wire 069;
wire 070;
wire 071;
wire 072;
wire 073;
wire 074;
wire 075;
wire 076;
wire 077;
wire 078;
wire 079;
wire 080;
wire 081;
wire 082;
wire 083;
wire 084;
wire 085;
wire 086;
wire 087;
wire 088;
wire 089;
wire 090;
wire 091;
wire 092;
wire 093;
wire 094;
wire 095;
wire 096;
wire 097;
wire 098;
wire 099;
wire 100;
wire 101;
wire 102;
wire 103;
wire 104;
wire 105;
wire 106;
wire 107;
wire 108;
wire 109;
wire 110;
wire 111;
wire 112;
wire 113;
wire 114;
wire 115;
wire 116;
wire 117;
wire 118;
wire 119;
wire 120;
wire 121;
wire 122;
wire 123;
wire 124;
wire 125;
wire 126;
wire 127;
wire 128;
wire 129;
wire 130;
wire 131;
wire 132;
wire 133;
wire 134;
wire 135;
wire 136;
wire 137;
wire 138;
wire 139;
wire 140;
wire 141;
wire 142;
wire 143;
wire 144;
wire 145;
wire 146;
wire 147;
wire 148;
wire 149;
wire 150;
wire 151;
wire 152;
wire 153;
wire 154;
wire 155;
wire 156;
wire 157;
wire 158;
wire 159;
wire 160;
wire 161;
wire 162;
wire 163;
wire 164;
wire 165;
wire 166;
wire 167;
wire 168;
wire 169;
wire 170;
wire 171;
wire 172;
wire 173;
wire 174;
wire 175;
wire 176;
wire 177;
wire 178;
wire 179;
wire 180;
wire 181;
wire 182;
wire 183;
wire 184;
wire 185;
wire 186;
wire 187;
wire 188;
wire 189;
wire 190;
wire 191;
wire 192;
wire 193;
wire 194;
wire 195;
wire 196;
wire 197;
wire 198;
wire 199;
wire 200;
wire 201;
wire 202;
wire 203;
wire 204;
wire 205;
wire 206;
wire 207;
wire 208;
wire 209;
wire 210;
wire 211;
wire 212;
wire 213;
wire 214;
wire 215;
wire 216;
wire 217;
wire 218;
wire 219;
wire 220;
wire 221;
wire 222;
wire 223;
wire 224;
wire 225;
wire 226;
wire 227;
wire 228;
wire 229;
wire 230;
wire 231;
wire 232;
wire 233;
wire 234;
wire 235;
wire 236;
wire 237;
wire 238;
wire 239;
wire 240;
wire 241;
wire 242;
wire 243;
wire 244;
wire 245;
wire 246;
wire 247;
wire 248;
wire 249;
wire 250;
wire 251;
wire 252;
wire 253;
wire 254;
wire 255;
wire 256;
wire 257;
wire 258;
wire 259;
wire 260;
wire 261;
wire 262;
wire 263;
wire 264;
wire 265;
wire 266;
wire 267;
wire 268;
wire 269;
wire 270;
wire 271;
wire 272;
wire 273;
wire 274;
wire 275;
wire 276;
wire 277;
wire 278;
wire 279;
wire 280;
wire 281;
wire 282;
wire 283;
wire 284;
wire 285;
wire 286;
wire 287;
wire 288;
wire 289;
wire 290;
wire 291;
wire 292;
wire 293;
wire 294;
wire 295;
wire 296;
wire 297;
wire 298;
wire 299;
wire 300;
wire 301;
wire 302;
wire 303;
wire 304;
wire 305;
wire 306;
wire 307;
wire 308;
wire 309;
wire 310;
wire 311;
wire 312;
wire 313;
wire 314;
wire 315;
wire 316;
wire 317;
wire 318;
wire 319;
wire 320;
wire 321;
wire 322;
wire 323;
wire 324;
wire 325;
wire 326;
wire 327;
wire 328;
wire 329;
wire 330;
wire 331;
wire 332;
wire 333;
wire 334;
wire 335;
wire 336;
wire 337;
wire 338;
wire 339;
wire 340;
wire 341;
wire 342;
wire 343;
wire 344;
wire 345;
wire 346;
wire 347;
wire 348;
wire 349;
wire 350;
wire 351;
wire 352;
wire 353;
wire 354;
wire 355;
wire 356;
wire 357;
wire 358;
wire 359;
wire 360;
wire 361;
input VAR14;
input VAR13;
input VAR2;
input VAR9;
input VAR11;
input VAR1;
input VAR3;
input VAR10;
input VAR7;
input VAR12;
input VAR15;
input VAR6;
input VAR4;
input VAR5;
wire [7:0] VAR8;
output valid;
assign 060 = ~VAR5;
assign 071 = ~VAR12;
assign 082 = ~(VAR13 ^ VAR14);
assign 093 = 082 ^ 071;
assign 104 = ~(093 & VAR15);
assign 115 = VAR13 & VAR14;
assign 126 = ~(VAR13 | VAR14);
assign 137 = VAR12 ? 115 : 126;
assign 148 = 137 ^ 104;
assign 159 = 148 & VAR6;
assign 170 = 115 ^ VAR2;
assign 181 = 170 ^ VAR9;
assign 192 = 181 ^ VAR3;
assign 203 = 192 ^ VAR10;
assign 214 = 203 ^ VAR7;
assign 235 = 126 & VAR12;
assign 236 = 235 ^ 214;
assign 247 = 236 ^ VAR15;
assign 258 = 247 & 159;
assign 269 = ~(137 | 104);
assign 280 = 236 & VAR15;
assign 299 = 280 | 269;
assign 300 = ~126;
assign 301 = ~((214 | 300) & VAR12);
assign 302 = ~VAR7;
assign 303 = 203 | 302;
assign 304 = ~(170 & VAR9);
assign 305 = VAR13 ^ VAR14;
assign 306 = VAR9 & VAR2;
assign 307 = 306 & 305;
assign 308 = ~(115 & VAR2);
assign 309 = 308 & 082;
assign 310 = ~((309 & 304) | 307);
assign 311 = 310 ^ VAR1;
assign 312 = 181 & VAR3;
assign 313 = ~((192 & VAR10) | 312);
assign 314 = ~(313 ^ 311);
assign 315 = 314 ^ VAR12;
assign 316 = 315 ^ 303;
assign 317 = 316 ^ 301;
assign 318 = 317 ^ 299;
assign 319 = 318 ^ 258;
assign 320 = 319 & VAR4;
assign 321 = 319 ^ VAR4;
assign 322 = 148 ^ VAR6;
assign 323 = 093 ^ VAR15;
assign 324 = 323 & VAR4;
assign 325 = 324 & 322;
assign 326 = ~(159 | 269);
assign 327 = ~(326 ^ 247);
assign 328 = 327 & 325;
assign 329 = 328 & 321;
assign 330 = 329 | 320;
assign 331 = 318 & 258;
assign 332 = 317 & 299;
assign 333 = 126 | 071;
assign 334 = 214 | 333;
assign 335 = ~((314 | 214) & VAR12);
assign 336 = ~((334 | 316) & 335);
assign 337 = 314 | 203;
assign 338 = 337 & VAR7;
assign 339 = ~(311 & 312);
assign 340 = ~VAR1;
assign 341 = ~(310 | 340);
assign 342 = ~VAR2;
assign 343 = ~VAR9;
assign 344 = 115 | 343;
assign 345 = ~((344 | 342) & 300);
assign 346 = 345 ^ 341;
assign 347 = ~(346 ^ 339);
assign 348 = 192 & VAR10;
assign 349 = ~(311 & 348);
assign 350 = ~(349 & VAR10);
assign 351 = 350 ^ 347;
assign 352 = 351 ^ 338;
assign 353 = 352 ^ 336;
assign 354 = 353 ^ 332;
assign 355 = 354 ^ 331;
assign 356 = ~(355 ^ 330);
assign 357 = ~(323 | VAR4);
assign 358 = 322 ? 324 : 357;
assign 359 = ~358;
assign 360 = 359 & 327;
assign 361 = ~(360 & 321);
assign 000 = 361 | 356;
assign 001 = 328 ^ 321;
assign 002 = ~(327 | 325);
assign 003 = ~((002 | 328) & 358);
assign 004 = ~(003 | 001);
assign 005 = ~((004 & 356) | (000 & 060));
assign 006 = ~(354 & 331);
assign 007 = 351 & 338;
assign 008 = ~VAR10;
assign 009 = ~((347 | 008) & 349);
assign 010 = ~(346 | 339);
assign 011 = 307 | 115;
assign 012 = 309 & 304;
assign 013 = 012 | 307;
assign 014 = ~((345 & 013) | 340);
assign 015 = 014 ^ 011;
assign 016 = 015 ^ 010;
assign 017 = 016 ^ 009;
assign 018 = ~(017 ^ 007);
assign 019 = 352 & 336;
assign 020 = ~((353 & 332) | 019);
assign 021 = ~(020 ^ 018);
assign 022 = 355 & 330;
assign 023 = ~(021 ^ 022);
assign 024 = 006 ? 023 : 021;
assign 025 = ~021;
assign 026 = 025 & 022;
assign 027 = VAR11 ^ VAR9;
assign 028 = VAR2 ? 343 : 027;
assign 029 = 306 ^ VAR14;
assign 030 = ~VAR11;
assign 031 = ~((343 & 342) | 030);
assign 032 = 031 ^ 029;
assign 033 = 032 ^ VAR1;
assign 034 = ~((033 | 028) & VAR3);
assign 035 = ~(032 | 340);
assign 036 = VAR14 & VAR9;
assign 037 = ~(036 | 342);
assign 038 = 037 ^ 082;
assign 039 = ~(031 & 029);
assign 040 = 039 & VAR11;
assign 041 = 040 ^ 038;
assign 042 = 041 ^ 035;
assign 043 = ~(042 | 034);
assign 044 = 041 & 035;
assign 045 = ~((038 | 030) & 039);
assign 046 = ~VAR13;
assign 047 = 046 | VAR14;
assign 048 = ~VAR14;
assign 049 = ~((VAR13 | 048) & 342);
assign 050 = ~((049 & 047) | VAR9);
assign 051 = VAR13 | 048;
assign 052 = ~((046 | VAR14) & VAR2);
assign 053 = ~((052 & 051) | 343);
assign 054 = ~((053 & 308) | 050);
assign 055 = 054 ^ VAR11;
assign 056 = 055 ^ 045;
assign 057 = 056 ^ 044;
assign 058 = ~(057 & 043);
assign 059 = 055 & 045;
assign 061 = 054 & VAR11;
assign 062 = 306 & VAR14;
assign 063 = ~(049 & 047);
assign 064 = 063 | 343;
assign 065 = ~((115 | VAR2) & 300);
assign 066 = ~((065 & 064) | 062);
assign 067 = 066 | 061;
assign 068 = ~((067 | 059) & 039);
assign 069 = ~(040 ^ 038);
assign 070 = ~(069 | 032);
assign 072 = ~(055 ^ 045);
assign 073 = ~((072 & 070) | 340);
assign 074 = 073 ^ 068;
assign 075 = 028 ^ VAR3;
assign 076 = VAR11 ^ VAR2;
assign 077 = 076 & VAR10;
assign 078 = 077 & 075;
assign 079 = ~VAR3;
assign 080 = ~(028 | 079);
assign 081 = 080 ^ 033;
assign 083 = ~(081 & 078);
assign 084 = ~(042 ^ 034);
assign 085 = 084 | 083;
assign 086 = ~(057 ^ 043);
assign 087 = ~((086 | 085) & (074 | 058));
assign 088 = ~((074 & 058) | 087);
assign 089 = ~(086 ^ 085);
assign 090 = 042 ^ 034;
assign 091 = 081 ^ 078;
assign 092 = ~(091 & 090);
assign 094 = ~((092 & 089) | 302);
assign 095 = ~(094 ^ 088);
assign 096 = ~VAR15;
assign 097 = 076 ^ VAR10;
assign 098 = 097 & VAR15;
assign 099 = ~(098 & 075);
assign 100 = 091 ^ 302;
assign 101 = ~((100 | 096) & 099);
assign 102 = ~(091 & VAR7);
assign 103 = 102 & 083;
assign 105 = 103 ^ 084;
assign 106 = 105 & 101;
assign 107 = 092 & VAR7;
assign 108 = ~(107 ^ 089);
assign 109 = ~(108 & 106);
assign 110 = 108 ^ 106;
assign 111 = 105 ^ 101;
assign 112 = 111 & VAR6;
assign 113 = 099 & VAR15;
assign 114 = ~(113 ^ 100);
assign 116 = 097 ^ VAR15;
assign 117 = 116 & VAR6;
assign 118 = ~(098 | 077);
assign 119 = ~(118 ^ 075);
assign 120 = 119 & 117;
assign 121 = 120 | 114;
assign 122 = 121 & VAR6;
assign 123 = ~((122 | 112) & 110);
assign 124 = 123 & 109;
assign 125 = ~(124 ^ 095);
assign 127 = ~VAR6;
assign 128 = ~(121 | 127);
assign 129 = 128 ^ 111;
assign 130 = 129 & VAR4;
assign 131 = 122 | 112;
assign 132 = 131 ^ 110;
assign 133 = 132 ^ 130;
assign 134 = ~(120 | 127);
assign 135 = ~(134 ^ 114);
assign 136 = 129 ^ VAR4;
assign 138 = 119 ^ 117;
assign 139 = ~(138 | 136);
assign 140 = ~((139 & 135) | 060);
assign 141 = ~(140 & 133);
assign 142 = ~(132 & 130);
assign 143 = 142 | 125;
assign 144 = 021 | 006;
assign 145 = VAR3 ^ VAR11;
assign 146 = 145 ^ VAR10;
assign 147 = ~(VAR3 & VAR11);
assign 149 = VAR14 ^ VAR9;
assign 150 = 149 ^ 340;
assign 151 = 150 ^ 147;
assign 152 = ~((151 | 146) & VAR7);
assign 153 = ~(150 | 147);
assign 154 = 149 | 340;
assign 155 = 036 ^ VAR13;
assign 156 = 155 ^ 030;
assign 157 = 156 ^ 154;
assign 158 = 157 ^ 153;
assign 160 = 145 & VAR10;
assign 161 = 150 & 160;
assign 162 = 161 | 008;
assign 163 = 162 | 151;
assign 164 = 163 ^ 158;
assign 165 = ~(164 | 152);
assign 166 = ~161;
assign 167 = ~(158 | 151);
assign 168 = ~((167 | 008) & 166);
assign 169 = 157 & 153;
assign 171 = ~(155 & VAR11);
assign 172 = VAR11 & VAR9;
assign 173 = 172 & 305;
assign 174 = ~((171 & 344) | 173);
assign 175 = ~149;
assign 176 = ~((156 & 175) | 340);
assign 177 = 176 ^ 174;
assign 178 = 177 ^ VAR3;
assign 179 = 178 ^ 169;
assign 180 = 179 ^ 168;
assign 182 = 180 ^ 165;
assign 183 = ~(164 ^ 152);
assign 184 = ~(145 | 008);
assign 185 = 184 ^ 151;
assign 186 = ~185;
assign 187 = 146 ^ 302;
assign 188 = 187 & 186;
assign 189 = ~((188 & 183) | 071);
assign 190 = 189 ^ 182;
assign 191 = 187 & VAR12;
assign 193 = ~(187 | VAR12);
assign 194 = ~(193 | 191);
assign 195 = ~194;
assign 196 = ~(146 | 302);
assign 197 = 196 ^ 185;
assign 198 = 191 ? 186 : 197;
assign 199 = 198 | 195;
assign 200 = ~199;
assign 201 = 200 & 183;
assign 202 = ~201;
assign 204 = 202 | 190;
assign 205 = 204 & VAR15;
assign 206 = 189 & 182;
assign 207 = 177 & VAR3;
assign 208 = 178 & 169;
assign 209 = 208 | 207;
assign 210 = ~(176 & 174);
assign 211 = ~((115 & VAR9) | 173);
assign 212 = 211 & 210;
assign 213 = 212 ^ 209;
assign 215 = 179 & 168;
assign 216 = ~((180 & 165) | 215);
assign 217 = ~(216 ^ 213);
assign 218 = ~(217 ^ 206);
assign 219 = ~(218 & 205);
assign 220 = ~206;
assign 221 = 217 | 220;
assign 222 = ~212;
assign 223 = 222 & 209;
assign 224 = 222 | 209;
assign 225 = ~((223 | 215) & 224);
assign 226 = ~(180 & 165);
assign 227 = 213 | 226;
assign 228 = 227 & 225;
assign 229 = 228 & 221;
assign 230 = ~(353 & 332);
assign 231 = 072 & 070;
assign 232 = 231 | 340;
assign 233 = ~((031 & 029) | 062);
assign 234 = ~((232 | 068) & 233);
assign 237 = 234 | 087;
assign 238 = ~((094 & 088) | 237);
assign 239 = ~((018 | 230) & 238);
assign 240 = ~(016 & 009);
assign 241 = 115 & VAR1;
assign 242 = ~((015 & 010) | 241);
assign 243 = 242 & 240;
assign 244 = 017 & 007;
assign 245 = 017 | 007;
assign 246 = ~((245 & 019) | 244);
assign 248 = ~((246 | 243) & (109 | 095));
assign 249 = 248 | 239;
assign 250 = ~(246 ^ 243);
assign 251 = ~((123 | 095) & 250);
assign 252 = 251 | 249;
assign 253 = ~((229 & 219) | 252);
assign 254 = 253 & 144;
assign 255 = 254 & 143;
assign 256 = ~((141 | 125) & 255);
assign 257 = 256 | 026;
assign 259 = ~(199 | 096);
assign 260 = 191 & 186;
assign 261 = 260 ^ 183;
assign 262 = 261 & 259;
assign 263 = 262 ^ 190;
assign 264 = ~(263 | VAR4);
assign 265 = 218 ^ 205;
assign 266 = 261 ^ 259;
assign 267 = 266 & 127;
assign 268 = ~267;
assign 270 = ~((268 | VAR5) & 265);
assign 271 = ~(266 | 127);
assign 272 = ~(198 | VAR15);
assign 273 = ~272;
assign 274 = ~((195 & VAR15) | 060);
assign 275 = ~274;
assign 276 = ~((197 & 194) | 275);
assign 277 = 276 & 273;
assign 278 = ~((277 | 265) & 271);
assign 279 = ~((278 & 270) | 264);
assign 281 = ~(267 | 060);
assign 282 = 281 | 277;
assign 283 = ~(282 | 265);
assign 284 = ~((282 & 265) | (263 & VAR4));
assign 285 = ~((284 | 283) & (229 | 219));
assign 286 = 138 | 060;
assign 287 = 135 ? 139 : 286;
assign 288 = 116 ^ VAR6;
assign 289 = ~((138 & 060) | 288);
assign 290 = ~((135 & VAR5) | 136);
assign 291 = ~((289 & 286) | 290);
assign 292 = 291 & 287;
assign 293 = ~(292 & 141);
assign 294 = 142 & 125;
assign 295 = ~((140 | 133) & 143);
assign 296 = 295 | 294;
assign 297 = ~((296 | 293) & (285 | 279));
assign 298 = 297 | 257;
assign valid = ~((024 & 005) | 298);
assign VAR8[0] = VAR12;
endmodule
|
mit
|
zhangry868/MultiCycleCPU
|
Multiple_Cycles_CPU/ALU.v
| 2,399 |
module MODULE5(VAR7,VAR17);
input [3:0] VAR7;
output [2:0] VAR17;
assign VAR17[2] = ((!VAR7[3])&(!VAR7[1]))|(!VAR7[3]& VAR7[2]& VAR7[0])|(VAR7[3]&VAR7[1]);
assign VAR17[1] = (!VAR7[3]&!VAR7[2]&!VAR7[1])|(VAR7[3]&!VAR7[2]&!VAR7[0])|(VAR7[2]&VAR7[1]&!VAR7[0])|(VAR7[3]&VAR7[1]);
assign VAR17[0] = (!VAR7[2]&!VAR7[1])|(!VAR7[3]&VAR7[2]&VAR7[0])|(VAR7[3]&VAR7[2]&VAR7[1]);
endmodule
module MODULE2(VAR13,VAR20,VAR30,VAR19,VAR33,VAR1,VAR3,VAR11);
input [31:0] VAR13,VAR20;
output [31:0] VAR11;
input VAR30;
output VAR19,VAR33,VAR1,VAR3;
assign {VAR33,VAR11} = VAR13 + VAR20 + VAR30;
assign VAR19 = (VAR11 == 32'b0)? 1'b1 : 1'b0;
assign VAR1 = (!(VAR13[31]^VAR20[31])&(VAR20[31]^VAR11[31]));
assign VAR3 = VAR11[31];
endmodule
module MODULE4(VAR12,VAR35,VAR14,VAR23,VAR18,VAR6,VAR37,VAR5,VAR36,VAR9);
input [2:0] VAR12;
input [31:0] VAR35,VAR14,VAR23,VAR18,VAR6,VAR37,VAR5,VAR36;
output [31:0]VAR9;
assign VAR9 = (VAR12[2])? (VAR12[1]?(VAR12[0]?VAR36:VAR5) : (VAR12[0]?VAR37:VAR6)) : (VAR12[1]?(VAR12[0]?VAR18:VAR23) : (VAR12[0]?VAR14:VAR35));
endmodule
module MODULE3(VAR21,VAR10);
input [31:0] VAR21;
output reg[31:0] VAR10;
integer VAR27 = 0;
always@(VAR21)begin
VAR10 = 32;
for(VAR27 = 31;VAR27 >= 0;VAR27 = VAR27-1)
if(VAR21[VAR27] == 1'b1 && VAR10 == 32)
VAR10 = 31 - VAR27;
end
endmodule
module MODULE1(
input [31:0] VAR13,VAR20,
input [3:0] VAR7,
output VAR19,VAR32,VAR8,
output [31:0] VAR9
);
wire [31:0] VAR31,VAR16,VAR34,VAR26;
wire [31:0] VAR4;
wire [31:0] VAR24;
wire VAR33,VAR1,VAR3;
wire [31:0] VAR11,VAR2;
wire [31:0] VAR25;
wire VAR30;
wire [2:0] VAR17;
MODULE5 VAR15(VAR7,VAR17);
MODULE4 VAR28(VAR17,VAR25,VAR34,VAR16,VAR26,VAR31,VAR2,VAR4,VAR11,VAR9);
MODULE3 VAR22(VAR24,VAR25);
MODULE2 MODULE2(VAR13,VAR20^{32{VAR7[0]}},VAR30,VAR19,VAR33,VAR1,VAR3,VAR11);
assign VAR30 = VAR7[0];
assign VAR31 = VAR13 & VAR20;
assign VAR16 = VAR13 | VAR20;
assign VAR34 = VAR13 ^ VAR20;
assign VAR26 = !VAR16;
assign VAR4 = (VAR7[0])?({{16{VAR20[7]}},VAR20[15:0]}):({{24{VAR20[7]}},VAR20[7:0]});
assign VAR24 = {32{VAR7[0]}}^VAR13[31:0];
assign VAR2 = VAR32 ? 32'hffffffff : 32'b0;
assign VAR32 = ((!VAR7[3])&VAR7[2]&VAR7[1]&VAR7[0])?(!VAR33):(VAR1^VAR3);
assign VAR8 = (VAR7[1]&VAR7[2]&VAR7[3])? VAR1:1'b0;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfbbp/sky130_fd_sc_ms__dfbbp.blackbox.v
| 1,435 |
module MODULE1 (
VAR1 ,
VAR2 ,
VAR9 ,
VAR6 ,
VAR5 ,
VAR8
);
output VAR1 ;
output VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR8;
supply1 VAR10;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule
|
apache-2.0
|
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/GC_fifo.v
| 13,416 |
module MODULE1(
clk,
rst,
din,
VAR163,
VAR128,
dout,
VAR107,
VAR120,
VAR289
);
input clk;
input rst;
input [31 : 0] din;
input VAR163;
input VAR128;
output [31 : 0] dout;
output VAR107;
output VAR120;
output [12 : 0] VAR289;
VAR226 #(
.VAR18(0),
.VAR237(0),
.VAR360(0),
.VAR270(0),
.VAR138(0),
.VAR274(0),
.VAR264(0),
.VAR334(32),
.VAR1(1),
.VAR17(1),
.VAR170(1),
.VAR94(64),
.VAR375(4),
.VAR302(1),
.VAR22(0),
.VAR402(1),
.VAR178(64),
.VAR348(4),
.VAR241(8),
.VAR110(4),
.VAR61(4),
.VAR254(4),
.VAR376(0),
.VAR196(1),
.VAR349(0),
.VAR117(13),
.VAR322("VAR67"),
.VAR157(32),
.VAR207(1),
.VAR176(32),
.VAR271(64),
.VAR40(32),
.VAR218(64),
.VAR123(2),
.VAR363("0"),
.VAR70(32),
.VAR152(0),
.VAR122(1),
.VAR367(0),
.VAR372(0),
.VAR369(0),
.VAR116(0),
.VAR80(0),
.VAR309(0),
.VAR240(0),
.VAR378("VAR146"),
.VAR143(1),
.VAR98(0),
.VAR74(0),
.VAR312(0),
.VAR86(0),
.VAR366(0),
.VAR127(0),
.VAR245(0),
.VAR171(0),
.VAR332(0),
.VAR103(0),
.VAR387(0),
.VAR51(0),
.VAR361(0),
.VAR248(0),
.VAR91(1),
.VAR403(0),
.VAR131(0),
.VAR65(0),
.VAR135(1),
.VAR108(0),
.VAR68(0),
.VAR183(0),
.VAR220(0),
.VAR411(0),
.VAR355(0),
.VAR216(0),
.VAR379(0),
.VAR48(0),
.VAR358(0),
.VAR130(0),
.VAR88(0),
.VAR195(0),
.VAR162(0),
.VAR265(0),
.VAR83(0),
.VAR413(0),
.VAR300(0),
.VAR346(1),
.VAR259(0),
.VAR156(0),
.VAR299(0),
.VAR344(0),
.VAR160(0),
.VAR187(0),
.VAR290(0),
.VAR255(0),
.VAR282(1),
.VAR119(1),
.VAR129(1),
.VAR141(1),
.VAR389(1),
.VAR190(1),
.VAR283(0),
.VAR125(0),
.VAR57(1),
.VAR6("VAR67"),
.VAR47(1),
.VAR258(0),
.VAR52(0),
.VAR357(0),
.VAR233(1),
.VAR89("4kx9"),
.VAR30(4),
.VAR202(1022),
.VAR266(1022),
.VAR4(1022),
.VAR5(1022),
.VAR252(1022),
.VAR9(1022),
.VAR405(5),
.VAR221(0),
.VAR180(5),
.VAR132(5),
.VAR13(5),
.VAR412(5),
.VAR268(5),
.VAR33(5),
.VAR139(4095),
.VAR8(1023),
.VAR273(1023),
.VAR341(1023),
.VAR38(1023),
.VAR7(1023),
.VAR244(1023),
.VAR155(4094),
.VAR161(0),
.VAR326(5),
.VAR230(5),
.VAR228(5),
.VAR147(5),
.VAR318(5),
.VAR154(5),
.VAR277(0),
.VAR206(13),
.VAR328(4096),
.VAR87(1),
.VAR114(12),
.VAR72(0),
.VAR148(0),
.VAR55(0),
.VAR408(0),
.VAR323(0),
.VAR338(0),
.VAR111(0),
.VAR224(2),
.VAR124(0),
.VAR58(0),
.VAR249(0),
.VAR260(0),
.VAR121(1),
.VAR227(0),
.VAR330(0),
.VAR24(0),
.VAR173(0),
.VAR27(0),
.VAR267(0),
.VAR211(0),
.VAR219(0),
.VAR407(0),
.VAR79(1),
.VAR380(0),
.VAR329(0),
.VAR71(0),
.VAR359(0),
.VAR247(13),
.VAR151(4096),
.VAR325(1024),
.VAR316(16),
.VAR371(1024),
.VAR31(16),
.VAR164(1024),
.VAR54(16),
.VAR169(1),
.VAR314(12),
.VAR3(10),
.VAR215(4),
.VAR327(10),
.VAR294(4),
.VAR396(10),
.VAR21(4),
.VAR12(1),
.VAR142(0)
)
VAR193 (
.VAR25(clk),
.VAR64(rst),
.VAR362(din),
.VAR203(VAR163),
.VAR15(VAR128),
.VAR281(dout),
.VAR343(VAR107),
.VAR253(VAR120),
.VAR242(VAR289),
.VAR263(),
.VAR144(),
.VAR374(),
.VAR229(),
.VAR399(),
.VAR93(),
.VAR11(),
.VAR62(),
.VAR353(),
.VAR307(),
.VAR39(),
.VAR331(),
.VAR286(),
.VAR205(),
.VAR238(),
.VAR214(),
.VAR168(),
.VAR136(),
.VAR373(),
.VAR350(),
.VAR276(),
.VAR321(),
.VAR280(),
.VAR409(),
.VAR209(),
.VAR34(),
.VAR297(),
.VAR257(),
.VAR287(),
.VAR388(),
.VAR29(),
.VAR200(),
.VAR153(),
.VAR356(),
.VAR370(),
.VAR319(),
.VAR246(),
.VAR298(),
.VAR212(),
.VAR217(),
.VAR347(),
.VAR208(),
.VAR234(),
.VAR383(),
.VAR351(),
.VAR43(),
.VAR16(),
.VAR398(),
.VAR56(),
.VAR82(),
.VAR44(),
.VAR414(),
.VAR175(),
.VAR20(),
.VAR295(),
.VAR150(),
.VAR345(),
.VAR291(),
.VAR184(),
.VAR42(),
.VAR112(),
.VAR337(),
.VAR317(),
.VAR394(),
.VAR166(),
.VAR410(),
.VAR250(),
.VAR275(),
.VAR46(),
.VAR49(),
.VAR284(),
.VAR159(),
.VAR262(),
.VAR174(),
.VAR140(),
.VAR104(),
.VAR19(),
.VAR213(),
.VAR393(),
.VAR364(),
.VAR189(),
.VAR352(),
.VAR165(),
.VAR73(),
.VAR75(),
.VAR306(),
.VAR342(),
.VAR28(),
.VAR236(),
.VAR32(),
.VAR109(),
.VAR53(),
.VAR63(),
.VAR279(),
.VAR223(),
.VAR235(),
.VAR210(),
.VAR304(),
.VAR158(),
.VAR96(),
.VAR288(),
.VAR81(),
.VAR10(),
.VAR251(),
.VAR69(),
.VAR101(),
.VAR401(),
.VAR391(),
.VAR167(),
.VAR382(),
.VAR386(),
.VAR115(),
.VAR23(),
.VAR392(),
.VAR365(),
.VAR377(),
.VAR188(),
.VAR243(),
.VAR179(),
.VAR225(),
.VAR78(),
.VAR192(),
.VAR134(),
.VAR113(),
.VAR336(),
.VAR37(),
.VAR305(),
.VAR256(),
.VAR406(),
.VAR100(),
.VAR340(),
.VAR105(),
.VAR231(),
.VAR311(),
.VAR59(),
.VAR313(),
.VAR222(),
.VAR385(),
.VAR118(),
.VAR36(),
.VAR99(),
.VAR292(),
.VAR102(),
.VAR145(),
.VAR77(),
.VAR354(),
.VAR232(),
.VAR85(),
.VAR185(),
.VAR198(),
.VAR368(),
.VAR303(),
.VAR126(),
.VAR285(),
.VAR204(),
.VAR404(),
.VAR395(),
.VAR384(),
.VAR172(),
.VAR177(),
.VAR191(),
.VAR201(),
.VAR41(),
.VAR181(),
.VAR45(),
.VAR133(),
.VAR261(),
.VAR296(),
.VAR66(),
.VAR390(),
.VAR97(),
.VAR197(),
.VAR50(),
.VAR315(),
.VAR106(),
.VAR182(),
.VAR26(),
.VAR381(),
.VAR2(),
.VAR92(),
.VAR308(),
.VAR95(),
.VAR293(),
.VAR320(),
.VAR194(),
.VAR272(),
.VAR324(),
.VAR90(),
.VAR239(),
.VAR310(),
.VAR335(),
.VAR400(),
.VAR60(),
.VAR199(),
.VAR76(),
.VAR269(),
.VAR149(),
.VAR186(),
.VAR137(),
.VAR333(),
.VAR84(),
.VAR35(),
.VAR397(),
.VAR301(),
.VAR14(),
.VAR339(),
.VAR278()
);
endmodule
|
gpl-2.0
|
aj-michael/Digital-Systems
|
MultiplicationUnit/Controller.v
| 2,355 |
module MODULE1(VAR6, VAR15, VAR13, VAR2, VAR16, VAR18);
input VAR6, VAR15, VAR13;
output reg [2:0] VAR16;
output reg [2:0] VAR2;
output reg VAR18;
parameter VAR7 = 4'b0000;
parameter VAR20 = 4'b0001;
parameter VAR11 = 4'b0010;
parameter VAR12 = 4'b0011;
parameter VAR14 = 4'b0100;
parameter VAR8 = 4'b0101;
parameter VAR17 = 4'b0110;
parameter VAR9 = 4'b0111;
parameter VAR3 = 4'b1000;
parameter VAR4 = 4'b1001;
parameter VAR5 = 4'b1010;
parameter VAR19 = 4'b1011;
reg [3:0] VAR10;
reg [3:0] VAR1;
always @ VAR10
case (VAR10)
VAR7: {VAR18, VAR2, VAR16} <= 7'b1000000; VAR20: {VAR18, VAR2, VAR16} <= 7'b0000000; VAR11: {VAR18, VAR2, VAR16} <= 7'b1101101; VAR12: {VAR18, VAR2, VAR16} <= 7'b1010010; VAR14: {VAR18, VAR2, VAR16} <= 7'b1111000; VAR8: {VAR18, VAR2, VAR16} <= 7'b1010010; VAR17: {VAR18, VAR2, VAR16} <= 7'b1111000;
VAR9: {VAR18, VAR2, VAR16} <= 7'b1010010;
VAR3: {VAR18, VAR2, VAR16} <= 7'b1111000;
VAR4: {VAR18, VAR2, VAR16} <= 7'b1010010;
VAR5: {VAR18, VAR2, VAR16} <= 7'b1111000;
VAR19: {VAR18, VAR2, VAR16} <= 7'b1000000; endcase
always @ (posedge VAR6 or negedge VAR15)
if (VAR15 == 0) begin VAR10 <= VAR7; VAR1 <= VAR7; end
else VAR10 <= VAR1;
always @ (VAR10 or VAR13 or VAR1)
case (VAR10)
VAR7: if (VAR13 == 1) VAR1 <= VAR20;
VAR20: VAR1 <= VAR11;
VAR11: VAR1 <= VAR12;
VAR12: VAR1 <= VAR14;
VAR14: VAR1 <= VAR8;
VAR8: VAR1 <= VAR17;
VAR17: VAR1 <= VAR9;
VAR9: VAR1 <= VAR3;
VAR3: VAR1 <= VAR4;
VAR4: VAR1 <= VAR5;
VAR5: VAR1 <= VAR19;
endcase
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/o22ai/sky130_fd_sc_lp__o22ai.blackbox.v
| 1,364 |
module MODULE1 (
VAR4 ,
VAR3,
VAR8,
VAR9,
VAR7
);
output VAR4 ;
input VAR3;
input VAR8;
input VAR9;
input VAR7;
supply1 VAR6;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
EliasVansteenkiste/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v
| 19,500 |
module MODULE3 (
clk,
reset,
VAR134,
VAR27,
VAR166,
VAR78,
VAR158
);
parameter VAR61 = 18;
parameter VAR4 = 28;
parameter VAR56 = 14;
localparam VAR112 = 29;
input clk;
input reset;
input VAR134;
input VAR27;
input [VAR61-1:0] VAR166; output VAR78;
output [VAR61-1:0] VAR158;
localparam VAR1 = 18; localparam VAR142 = 36; localparam VAR94 = 17;
localparam VAR163 = 28;
reg [VAR61-1:0] VAR80;
reg [VAR61-1:0] VAR59;
reg [VAR61-1:0] VAR19;
reg [VAR61-1:0] VAR172;
reg [VAR61-1:0] VAR155;
reg [VAR61-1:0] VAR12;
reg [VAR61-1:0] VAR14;
reg [VAR61-1:0] VAR18;
reg [VAR61-1:0] VAR119;
reg [VAR61-1:0] VAR53;
reg [VAR61-1:0] VAR29;
reg [VAR61-1:0] VAR136;
reg [VAR61-1:0] VAR62;
reg [VAR61-1:0] VAR143;
always@(posedge clk) begin
VAR80 <= 18'd88;
VAR59 <= 18'd0;
VAR19 <= -18'd97;
VAR172 <= -18'd197;
VAR155 <= -18'd294;
VAR12 <= -18'd380;
VAR14 <= -18'd447;
VAR18 <= -18'd490;
VAR119 <= -18'd504;
VAR53 <= -18'd481;
VAR29 <= -18'd420;
VAR136 <= -18'd319;
VAR62 <= -18'd178;
VAR143 <= 18'd0;
end
reg [VAR112-1:0] VAR40;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR40 <= 0;
end else begin
if(VAR134) begin
VAR40 <= {VAR40[VAR112-2:0], VAR27};
end else begin
VAR40 <= VAR40;
end
end
end
wire [VAR61-1:0] VAR105;
wire [VAR61-1:0] VAR44;
wire [VAR61-1:0] VAR157;
wire [VAR61-1:0] VAR128;
wire [VAR61-1:0] VAR160;
wire [VAR61-1:0] VAR5;
wire [VAR61-1:0] VAR32;
wire [VAR61-1:0] VAR170;
wire [VAR61-1:0] VAR148;
wire [VAR61-1:0] VAR137;
wire [VAR61-1:0] VAR123;
wire [VAR61-1:0] VAR124;
wire [VAR61-1:0] VAR47;
wire [VAR61-1:0] VAR60;
wire [VAR61-1:0] VAR49;
wire [VAR61-1:0] VAR67;
wire [VAR61-1:0] VAR58;
wire [VAR61-1:0] VAR43;
wire [VAR61-1:0] VAR95;
wire [VAR61-1:0] VAR98;
wire [VAR61-1:0] VAR15;
wire [VAR61-1:0] VAR51;
wire [VAR61-1:0] VAR20;
wire [VAR61-1:0] VAR125;
wire [VAR61-1:0] VAR99;
wire [VAR61-1:0] VAR45;
wire [VAR61-1:0] VAR107;
wire [VAR61-1:0] VAR100;
MODULE2 MODULE31(
.clk(clk), .VAR134(VAR134),
.VAR25(VAR166),
.VAR17(VAR105),
.VAR13(VAR44),
.VAR3(VAR157),
.VAR90(VAR128),
.VAR88(VAR160),
.VAR108(VAR5),
.VAR39(VAR32),
.VAR55(VAR170),
.VAR103(VAR148),
.VAR69(VAR137),
.VAR139(VAR123),
.VAR50(VAR124),
.VAR33(VAR47),
.VAR89(VAR60),
.VAR171(VAR49),
.VAR42(VAR67),
.VAR121(VAR58),
.VAR31(VAR43),
.VAR152(VAR95),
.VAR87(VAR98),
.VAR145(VAR15),
.VAR151(VAR51),
.VAR167(VAR20),
.VAR153(VAR125),
.VAR75(VAR99),
.VAR8(VAR45),
.VAR130(VAR107),
.VAR96(VAR100),
.reset(reset) );
wire [VAR61-1:0] VAR104;
wire [VAR61-1:0] VAR149;
wire [VAR61-1:0] VAR77;
wire [VAR61-1:0] VAR82;
wire [VAR61-1:0] VAR41;
wire [VAR61-1:0] VAR173;
wire [VAR61-1:0] VAR140;
wire [VAR61-1:0] VAR129;
wire [VAR61-1:0] VAR168;
wire [VAR61-1:0] VAR141;
wire [VAR61-1:0] VAR48;
wire [VAR61-1:0] VAR131;
wire [VAR61-1:0] VAR91;
wire [VAR61-1:0] VAR159;
MODULE1 VAR161(
.VAR120 (VAR105),
.VAR81 (VAR100),
.VAR132(VAR104)
);
MODULE1 VAR101(
.VAR120 (VAR44),
.VAR81 (VAR107),
.VAR132(VAR149)
);
MODULE1 VAR144(
.VAR120 (VAR157),
.VAR81 (VAR45),
.VAR132(VAR77)
);
MODULE1 VAR36(
.VAR120 (VAR128),
.VAR81 (VAR99),
.VAR132(VAR82)
);
MODULE1 VAR23(
.VAR120 (VAR160),
.VAR81 (VAR125),
.VAR132(VAR41)
);
MODULE1 VAR46(
.VAR120 (VAR5),
.VAR81 (VAR20),
.VAR132(VAR173)
);
MODULE1 VAR102(
.VAR120 (VAR32),
.VAR81 (VAR51),
.VAR132(VAR140)
);
MODULE1 VAR68(
.VAR120 (VAR170),
.VAR81 (VAR15),
.VAR132(VAR129)
);
MODULE1 VAR146(
.VAR120 (VAR148),
.VAR81 (VAR98),
.VAR132(VAR168)
);
MODULE1 VAR26(
.VAR120 (VAR137),
.VAR81 (VAR95),
.VAR132(VAR141)
);
MODULE1 VAR28(
.VAR120 (VAR123),
.VAR81 (VAR43),
.VAR132(VAR48)
);
MODULE1 VAR122(
.VAR120 (VAR124),
.VAR81 (VAR58),
.VAR132(VAR131)
);
MODULE1 VAR97(
.VAR120 (VAR47),
.VAR81 (VAR67),
.VAR132(VAR91)
);
MODULE1 VAR79(
.VAR120 (VAR60),
.VAR81 (VAR49),
.VAR132(VAR159)
);
wire [VAR61-1:0] VAR11;
wire [VAR61-1:0] VAR76;
wire [VAR61-1:0] VAR111;
wire [VAR61-1:0] VAR52;
wire [VAR61-1:0] VAR74;
wire [VAR61-1:0] VAR57;
wire [VAR61-1:0] VAR73;
wire [VAR61-1:0] VAR110;
wire [VAR61-1:0] VAR7;
wire [VAR61-1:0] VAR154;
wire [VAR61-1:0] VAR72;
wire [VAR61-1:0] VAR92;
wire [VAR61-1:0] VAR10;
wire [VAR61-1:0] VAR114;
MODULE5 VAR2(
.VAR120 (VAR104),
.VAR81 (VAR80),
.VAR132(VAR11)
);
MODULE5 VAR24(
.VAR120 (VAR149),
.VAR81 (VAR59),
.VAR132(VAR76)
);
MODULE5 VAR30(
.VAR120 (VAR77),
.VAR81 (VAR19),
.VAR132(VAR111)
);
MODULE5 VAR174(
.VAR120 (VAR82),
.VAR81 (VAR172),
.VAR132(VAR52)
);
MODULE5 VAR83(
.VAR120 (VAR41),
.VAR81 (VAR155),
.VAR132(VAR74)
);
MODULE5 VAR109(
.VAR120 (VAR173),
.VAR81 (VAR12),
.VAR132(VAR57)
);
MODULE5 VAR16(
.VAR120 (VAR140),
.VAR81 (VAR14),
.VAR132(VAR73)
);
MODULE5 VAR138(
.VAR120 (VAR129),
.VAR81 (VAR18),
.VAR132(VAR110)
);
MODULE5 VAR162(
.VAR120 (VAR168),
.VAR81 (VAR119),
.VAR132(VAR7)
);
MODULE5 VAR9(
.VAR120 (VAR141),
.VAR81 (VAR53),
.VAR132(VAR154)
);
MODULE5 VAR116(
.VAR120 (VAR48),
.VAR81 (VAR29),
.VAR132(VAR72)
);
MODULE5 VAR126(
.VAR120 (VAR131),
.VAR81 (VAR136),
.VAR132(VAR92)
);
MODULE5 VAR63(
.VAR120 (VAR91),
.VAR81 (VAR62),
.VAR132(VAR10)
);
MODULE5 VAR164(
.VAR120 (VAR159),
.VAR81 (VAR143),
.VAR132(VAR114)
);
wire [VAR61-1:0] VAR65;
wire [VAR61-1:0] VAR34;
wire [VAR61-1:0] VAR22;
wire [VAR61-1:0] VAR106;
wire [VAR61-1:0] VAR66;
wire [VAR61-1:0] VAR21;
wire [VAR61-1:0] VAR85;
MODULE1 VAR135(
.VAR120 (VAR11),
.VAR81 (VAR76),
.VAR132(VAR65)
);
MODULE1 VAR64(
.VAR120 (VAR111),
.VAR81 (VAR52),
.VAR132(VAR34)
);
MODULE1 VAR150(
.VAR120 (VAR74),
.VAR81 (VAR57),
.VAR132(VAR22)
);
MODULE1 VAR127(
.VAR120 (VAR73),
.VAR81 (VAR110),
.VAR132(VAR106)
);
MODULE1 VAR118(
.VAR120 (VAR7),
.VAR81 (VAR154),
.VAR132(VAR66)
);
MODULE1 VAR165(
.VAR120 (VAR72),
.VAR81 (VAR92),
.VAR132(VAR21)
);
MODULE1 VAR156(
.VAR120 (VAR10),
.VAR81 (VAR114),
.VAR132(VAR85)
);
wire [VAR61-1:0] VAR147;
wire [VAR61-1:0] VAR54;
wire [VAR61-1:0] VAR6;
wire [VAR61-1:0] VAR86;
MODULE1 VAR84(
.VAR120 (VAR65),
.VAR81 (VAR34),
.VAR132(VAR147)
);
MODULE1 VAR169(
.VAR120 (VAR22),
.VAR81 (VAR106),
.VAR132(VAR54)
);
MODULE1 VAR35(
.VAR120 (VAR66),
.VAR81 (VAR21),
.VAR132(VAR6)
);
MODULE4 VAR133(
.VAR120 (VAR85),
.VAR132(VAR86)
);
wire [VAR61-1:0] VAR70;
wire [VAR61-1:0] VAR71;
MODULE1 VAR117(
.VAR120 (VAR147),
.VAR81 (VAR54),
.VAR132(VAR70)
);
MODULE1 VAR93(
.VAR120 (VAR6),
.VAR81 (VAR86),
.VAR132(VAR71)
);
wire [VAR61-1:0] VAR115;
MODULE1 VAR37(
.VAR120 (VAR70),
.VAR81 (VAR71),
.VAR132(VAR115)
);
reg [17:0] VAR158;
always @(posedge clk) begin
if(VAR134) begin
VAR158 <= VAR115;
end
end
assign VAR78 = VAR40[VAR112-1];
endmodule
module MODULE2 (
clk,
VAR134,
VAR25,
VAR17,
VAR13,
VAR3,
VAR90,
VAR88,
VAR108,
VAR39,
VAR55,
VAR103,
VAR69,
VAR139,
VAR50,
VAR33,
VAR89,
VAR171,
VAR42,
VAR121,
VAR31,
VAR152,
VAR87,
VAR145,
VAR151,
VAR167,
VAR153,
VAR75,
VAR8,
VAR130,
VAR96,
reset);
parameter VAR38 = 1;
input clk;
input VAR134;
input [VAR38-1:0] VAR25;
output [VAR38-1:0] VAR17;
output [VAR38-1:0] VAR13;
output [VAR38-1:0] VAR3;
output [VAR38-1:0] VAR90;
output [VAR38-1:0] VAR88;
output [VAR38-1:0] VAR108;
output [VAR38-1:0] VAR39;
output [VAR38-1:0] VAR55;
output [VAR38-1:0] VAR103;
output [VAR38-1:0] VAR69;
output [VAR38-1:0] VAR139;
output [VAR38-1:0] VAR50;
output [VAR38-1:0] VAR33;
output [VAR38-1:0] VAR89;
output [VAR38-1:0] VAR171;
output [VAR38-1:0] VAR42;
output [VAR38-1:0] VAR121;
output [VAR38-1:0] VAR31;
output [VAR38-1:0] VAR152;
output [VAR38-1:0] VAR87;
output [VAR38-1:0] VAR145;
output [VAR38-1:0] VAR151;
output [VAR38-1:0] VAR167;
output [VAR38-1:0] VAR153;
output [VAR38-1:0] VAR75;
output [VAR38-1:0] VAR8;
output [VAR38-1:0] VAR130;
output [VAR38-1:0] VAR96;
reg [VAR38-1:0] VAR17;
reg [VAR38-1:0] VAR13;
reg [VAR38-1:0] VAR3;
reg [VAR38-1:0] VAR90;
reg [VAR38-1:0] VAR88;
reg [VAR38-1:0] VAR108;
reg [VAR38-1:0] VAR39;
reg [VAR38-1:0] VAR55;
reg [VAR38-1:0] VAR103;
reg [VAR38-1:0] VAR69;
reg [VAR38-1:0] VAR139;
reg [VAR38-1:0] VAR50;
reg [VAR38-1:0] VAR33;
reg [VAR38-1:0] VAR89;
reg [VAR38-1:0] VAR171;
reg [VAR38-1:0] VAR42;
reg [VAR38-1:0] VAR121;
reg [VAR38-1:0] VAR31;
reg [VAR38-1:0] VAR152;
reg [VAR38-1:0] VAR87;
reg [VAR38-1:0] VAR145;
reg [VAR38-1:0] VAR151;
reg [VAR38-1:0] VAR167;
reg [VAR38-1:0] VAR153;
reg [VAR38-1:0] VAR75;
reg [VAR38-1:0] VAR8;
reg [VAR38-1:0] VAR130;
reg [VAR38-1:0] VAR96;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR17 <= 0;
VAR13 <= 0;
VAR3 <= 0;
VAR90 <= 0;
VAR88 <= 0;
VAR108 <= 0;
VAR39 <= 0;
VAR55 <= 0;
VAR103 <= 0;
VAR69 <= 0;
VAR139 <= 0;
VAR50 <= 0;
VAR33 <= 0;
VAR89 <= 0;
VAR171 <= 0;
VAR42 <= 0;
VAR121 <= 0;
VAR31 <= 0;
VAR152 <= 0;
VAR87 <= 0;
VAR145 <= 0;
VAR151 <= 0;
VAR167 <= 0;
VAR153 <= 0;
VAR75 <= 0;
VAR8 <= 0;
VAR130 <= 0;
VAR96 <= 0;
end else begin
if(VAR134) begin
VAR17 <= VAR25;
VAR13 <= VAR17;
VAR3 <= VAR13;
VAR90 <= VAR3;
VAR88 <= VAR90;
VAR108 <= VAR88;
VAR39 <= VAR108;
VAR55 <= VAR39;
VAR103 <= VAR55;
VAR69 <= VAR103;
VAR139 <= VAR69;
VAR50 <= VAR139;
VAR33 <= VAR50;
VAR89 <= VAR33;
VAR171 <= VAR89;
VAR42 <= VAR171;
VAR121 <= VAR42;
VAR31 <= VAR121;
VAR152 <= VAR31;
VAR87 <= VAR152;
VAR145 <= VAR87;
VAR151 <= VAR145;
VAR167 <= VAR151;
VAR153 <= VAR167;
VAR75 <= VAR153;
VAR8 <= VAR75;
VAR130 <= VAR8;
VAR96 <= VAR130;
end end
end
endmodule
module MODULE1 (
VAR120,
VAR81,
VAR132);
input clk;
input VAR134;
input [17:0] VAR120;
input [17:0] VAR81;
output [17:0] VAR132;
assign VAR132 = VAR120 + VAR81;
endmodule
module MODULE5 (
VAR120,
VAR81,
VAR132);
input clk;
input VAR134;
input [17:0] VAR120;
input [17:0] VAR81;
output [17:0] VAR132;
assign VAR132 = VAR120 * VAR81;
endmodule
module MODULE4 (
VAR120,
VAR132);
input clk;
input VAR134;
input [17:0] VAR120;
output [17:0] VAR132;
assign VAR132 = VAR120;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a31oi/sky130_fd_sc_hd__a31oi.functional.pp.v
| 2,038 |
module MODULE1 (
VAR16 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR11 ,
VAR5,
VAR3,
VAR15 ,
VAR13
);
output VAR16 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR11 ;
input VAR5;
input VAR3;
input VAR15 ;
input VAR13 ;
wire VAR6 ;
wire VAR12 ;
wire VAR9;
and VAR2 (VAR6 , VAR7, VAR4, VAR8 );
nor VAR14 (VAR12 , VAR11, VAR6 );
VAR17 VAR10 (VAR9, VAR12, VAR5, VAR3);
buf VAR1 (VAR16 , VAR9 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/o31ai/sky130_fd_sc_hdll__o31ai.blackbox.v
| 1,355 |
module MODULE1 (
VAR9 ,
VAR7,
VAR4,
VAR6,
VAR2
);
output VAR9 ;
input VAR7;
input VAR4;
input VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule
|
apache-2.0
|
olajep/oh
|
src/adi/hdl/library/axi_dmac/src_axi_mm.v
| 6,489 |
module MODULE1 #(
parameter VAR29 = 3,
parameter VAR52 = 64,
parameter VAR32 = 32,
parameter VAR5 = 3,
parameter VAR35 = 4,
parameter VAR36 = 8)(
input VAR2,
input VAR23,
input VAR45,
output VAR3,
input [VAR32-1:VAR5] VAR60,
input [VAR35-1:0] VAR7,
input enable,
output reg VAR28 = 1'b0,
output VAR54,
input VAR44,
output [VAR35-1:0] VAR59,
input [VAR29-1:0] VAR61,
output [VAR29-1:0] VAR33,
output [VAR29-1:0] VAR40,
output [VAR29-1:0] VAR48,
input VAR17,
output VAR55,
output [VAR52-1:0] VAR14,
output VAR13,
input VAR38,
output VAR4,
output [VAR32-1:0] VAR49,
output [VAR36-1:0] VAR20,
output [ 2:0] VAR16,
output [ 1:0] VAR9,
output [ 2:0] VAR24,
output [ 3:0] VAR25,
input [VAR52-1:0] VAR62,
output VAR31,
input VAR11,
input VAR21,
input [ 1:0] VAR26
);
reg [VAR29-1:0] VAR39 = 'h00;
wire VAR43;
wire VAR53;
wire VAR15;
wire VAR50;
wire VAR8;
assign VAR40 = VAR39;
assign VAR33 = VAR39;
assign VAR59 = VAR7;
VAR1 #(
.VAR63(3)
) VAR41 (
.clk(VAR2),
.VAR18(VAR23),
.VAR34(VAR45),
.VAR47(VAR3),
.VAR57({
VAR54,
VAR8,
VAR15
}),
.VAR51({
VAR44,
VAR50,
VAR53
})
);
VAR22 #(
.VAR29(VAR29),
.VAR35(VAR35),
.VAR5(VAR5),
.VAR52(VAR52),
.VAR10(VAR36),
.VAR32(VAR32)
) VAR37 (
.clk(VAR2),
.VAR18(VAR23),
.enable(enable),
.VAR28(VAR43),
.VAR61(VAR61),
.VAR39(VAR48),
.VAR45(VAR15),
.VAR3(VAR53),
.VAR60(VAR60),
.VAR54(VAR8),
.VAR44(VAR50),
.VAR59(VAR7),
.VAR19(VAR17),
.VAR27(VAR38),
.VAR56(VAR4),
.addr(VAR49),
.VAR12(VAR20),
.VAR30(VAR16),
.VAR58(VAR9),
.VAR42(VAR24),
.VAR46(VAR25)
);
assign VAR55 = VAR11;
assign VAR14 = VAR62;
assign VAR13 = VAR21;
always @(posedge VAR2) begin
if (VAR23 == 1'b0) begin
VAR39 <= 'h00;
end else if (VAR11 == 1'b1 && VAR21 == 1'b1) begin
VAR39 <= VAR6(VAR39);
end
end
assign VAR31 = 1'b1;
always @(posedge VAR2) begin
if (VAR23 == 1'b0) begin
VAR28 <= 1'b0;
end else if (VAR43 == 1'b1) begin
VAR28 <= 1'b1;
end else if (VAR39 == VAR48) begin
VAR28 <= 1'b0;
end
end
endmodule
|
mit
|
set-soft/collection-kefir_i
|
blocks/Varios/Comunicación/Templates/ft245_sync_if_m.v
| 1,055 |
module MODULE1
parameter VAR15=0, parameter VAR9=0, parameter VAR7=0, parameter VAR14=0) (
inout [7:0] VAR5,
input VAR8,
input VAR2,
output VAR18,
output VAR1,
input VAR11,
output VAR13,
output VAR19,
input VAR3,
input [7:0] VAR10,
input VAR6,
output VAR17,
output [7:0] VAR4,
output VAR12,
input VAR16);
endmodule
|
gpl-2.0
|
mbuesch/pyprofibus
|
phy_fpga/uart_mod.v
| 17,446 |
module MODULE1 (
input clk,
input VAR7,
input [23:0] VAR6,
output reg VAR8,
output reg VAR4,
output reg VAR5,
);
localparam VAR1 = 4;
reg [23:0] VAR9;
wire [23:0] VAR3;
wire [23:0] VAR2;
assign VAR3 = (VAR6 >= VAR1) ? VAR6 : VAR1;
assign VAR2 = VAR3 >> 1;
|
gpl-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/pc_next.v
| 4,064 |
module MODULE1 (clk, reset, VAR6, VAR2, VAR10,
VAR9, VAR3, VAR7, VAR5);
input clk;
input reset;
input [31:2] VAR6;
input VAR2;
input VAR10;
input [25:0] VAR9;
input [ 1:0] VAR3;
output [31:0] VAR7;
output [31:0] VAR5;
reg[31:2] MODULE1;
reg[31:2] VAR4;
wire [31:2] VAR1 = VAR4 + 1;
wire [31:0] VAR7 = {VAR4, 2'b00} ;
wire [31:0] VAR5 = {VAR1, 2'b00} ;
always @(posedge clk or posedge reset)
begin
if (reset)
VAR4 <= VAR8;
end
else
VAR4 <= MODULE1;
end
always @(VAR3 or VAR1 or VAR4 or VAR9 or
VAR2 or VAR6 or VAR10)
begin
case (VAR3)
default : begin
if (VAR2) MODULE1 = VAR6;
end
else MODULE1 = VAR1;
end
endcase
if (VAR10 == 1'b1)
begin
MODULE1 = VAR4;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a2111o/sky130_fd_sc_hd__a2111o_4.v
| 2,448 |
module MODULE1 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR12 ,
VAR3 ,
VAR5 ,
VAR8,
VAR11,
VAR10 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR12 ;
input VAR3 ;
input VAR5 ;
input VAR8;
input VAR11;
input VAR10 ;
input VAR4 ;
VAR1 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR7,
VAR2,
VAR12,
VAR3,
VAR5
);
output VAR6 ;
input VAR7;
input VAR2;
input VAR12;
input VAR3;
input VAR5;
supply1 VAR8;
supply0 VAR11;
supply1 VAR10 ;
supply0 VAR4 ;
VAR1 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/ramdac_sp/crcx.v
| 4,342 |
module MODULE1
(
input VAR2,
input VAR6,
input VAR7,
input VAR8,
input [7:0] VAR3,
input [7:0] VAR11,
input [7:0] VAR10,
output [7:0] VAR9,
output [7:0] VAR12,
output [7:0] VAR1
);
reg[23:0] VAR4;
wire[23:0] VAR5 ;
assign VAR5[23:16] = VAR3[7:0] ;
assign VAR5[15: 8] = VAR11[7:0] ;
assign VAR5[ 7: 0] = VAR10[7:0] ;
always @(posedge VAR2 or negedge VAR6)
if (!VAR6)
begin VAR4[23:0] <= 24'hFFFFFF; end
else begin
if (VAR8)
VAR4[23:0] <= 24'hFFFFFF;
end
else if (VAR7)
begin
VAR4[0] <= VAR4[1] ^ VAR5[1];
VAR4[1] <= VAR4[2] ^ VAR5[2];
VAR4[2] <= VAR4[3] ^ VAR5[3];
VAR4[3] <= VAR4[4] ^ VAR5[4];
VAR4[4] <= VAR4[5] ^ VAR5[5];
VAR4[5] <= VAR4[6] ^ VAR5[6];
VAR4[6] <= VAR4[7] ^ VAR5[7];
VAR4[7] <= VAR4[8] ^ VAR5[8];
VAR4[8] <= VAR4[9] ^ VAR5[9];
VAR4[9] <= VAR4[10] ^ VAR5[10];
VAR4[10] <= VAR4[11] ^ VAR5[11];
VAR4[11] <= VAR4[12] ^ VAR5[12];
VAR4[12] <= VAR4[13] ^ VAR5[13];
VAR4[13] <= VAR4[14] ^ VAR5[14];
VAR4[14] <= VAR4[15] ^ VAR5[15];
VAR4[15] <= VAR4[16] ^ VAR5[16];
VAR4[16] <= VAR4[17] ^ VAR5[17] ^ VAR4[0] ^VAR5[0];
VAR4[17] <= VAR4[18] ^ VAR5[18];
VAR4[18] <= VAR4[19] ^ VAR5[19];
VAR4[19] <= VAR4[20] ^ VAR5[20];
VAR4[20] <= VAR4[21] ^ VAR5[21];
VAR4[21] <= VAR4[22] ^ VAR5[22] ^ VAR4[0] ^ VAR5[0];
VAR4[22] <= VAR4[23] ^ VAR5[23] ^ VAR4[0] ^ VAR5[0];
VAR4[23] <= VAR4[0] ^ VAR5[0];
end
end
assign VAR9[7:0] = VAR4[23:16];
assign VAR12[7:0] = VAR4[15:8];
assign VAR1[7:0] = VAR4[7:0];
endmodule
|
gpl-3.0
|
SI-RISCV/e200_opensource
|
rtl/e203/perips/sirv_ResetCatchAndSync.v
| 2,261 |
module MODULE1(
input VAR5,
input reset,
input VAR14,
output VAR17
);
wire VAR15;
wire VAR10;
wire [2:0] VAR4;
wire [2:0] VAR12;
wire VAR16;
wire [1:0] VAR13;
wire [2:0] VAR8;
wire VAR2;
wire VAR3;
VAR1 VAR7 (
.VAR5(VAR15),
.reset(VAR10),
.VAR9(VAR4),
.VAR6(VAR12),
.VAR11(VAR16)
);
assign VAR17 = VAR14 ? reset : VAR3;
assign VAR15 = VAR5;
assign VAR10 = reset;
assign VAR4 = VAR8;
assign VAR16 = 1'h1;
assign VAR13 = VAR12[2:1];
assign VAR8 = {1'h1,VAR13};
assign VAR2 = VAR12[0];
assign VAR3 = ~ VAR2;
endmodule
|
apache-2.0
|
phase4ground/DVB-receiver
|
modem/hdl/library/lookup_table_behavioural/lookup_table_behavioural.v
| 3,464 |
module MODULE1 #
(
parameter integer VAR21 = 32,
parameter integer VAR7 = 8
)
(
input wire VAR4,
input wire VAR8,
output wire VAR16,
input wire [VAR7-1:0] VAR23,
input wire VAR19,
input wire VAR11,
output wire VAR22,
output wire VAR17,
input wire VAR10,
output reg [VAR21-1:0] VAR18,
output reg VAR5,
output reg VAR13,
input wire VAR1,
input wire VAR14,
output wire VAR3,
input wire [VAR21-1:0] VAR6,
input wire VAR2,
input wire VAR20
);
reg [VAR21-1:0] VAR24[2**VAR7-1:0];
integer VAR15;
always @(posedge VAR1) begin
if(!VAR14) begin
for (VAR15 = 0; VAR15 < VAR7; VAR15=VAR15+1) begin
VAR24[VAR15] <= 0;
end
end
else begin
if (VAR20 & VAR3) begin
VAR24[VAR9] <= VAR6;
end
end
end
always @(posedge VAR22) begin
if(!VAR17) begin
VAR18 <= 0;
end
else begin
VAR18 <= VAR24[VAR23];
end
end
assign VAR16 = VAR10;
always @(posedge VAR4) begin
if(!VAR8) begin
VAR13 <= 0;
VAR5 <= 0;
end
else begin
VAR13 <= VAR11;
VAR5 <= VAR19;
end
end
assign VAR12 = VAR20 & VAR3;
reg [VAR7-1:0] VAR9;
assign VAR3 = 1;
always @(posedge VAR1) begin
if(!VAR14) begin
VAR9 <= 0;
end
else begin
if (VAR2) begin
VAR9 <= 0;
end
else if (VAR12) begin
VAR9 <= VAR9 + 1;
end
end
end
|
gpl-3.0
|
scalable-networks/ext
|
uhd/fpga/usrp2/opencores/wb_zbt/wb_zbt.v
| 4,340 |
module MODULE1(
input clk,
input rst,
input [31:0] VAR37,
input [31:0] VAR14,
output [31:0] VAR20,
input [ 3:0] VAR10,
input VAR6,
input VAR30,
output VAR21,
input VAR9,
input [31:0] VAR5,
input [31:0] VAR28,
output [31:0] VAR33,
input [ 3:0] VAR29,
input VAR7,
input VAR41,
output VAR27,
input VAR24,
output VAR4,
output [17:0] VAR13,
inout [31:0] VAR19,
output VAR36,
output [ 3:0] VAR18,
output VAR1,
output VAR11,
output VAR35,
output VAR39,
output VAR3
);
assign VAR4 = clk;
assign VAR35 = 1'b0;
assign VAR11 = 1'b0;
assign VAR1 = 1'b0;
assign VAR39 = 1'b0;
assign VAR3 = 1'b0;
wire VAR2;
wire VAR34;
assign VAR2 = VAR6 & VAR30;
assign VAR34 = VAR7 & VAR41;
wire [18:0] VAR23;
reg [18:0] VAR8;
reg [18:0] VAR32;
always @(posedge clk or posedge rst) begin
if(rst) begin
VAR8 <= 0;
VAR32 <= 0;
end else begin
VAR8 <= VAR23;
VAR32 <= VAR8;
end
end
wire VAR15;
wire VAR17;
assign VAR15 = (VAR8[18:1] == VAR37[19:2]) & (VAR8[0] == VAR9);
assign VAR17 = (VAR8[18:1] == VAR5[19:2]) & (VAR8[0] == VAR24);
wire VAR22;
wire VAR40;
assign VAR22 = (VAR32[18:1] == VAR37[19:2]) & (VAR32[0] == VAR9);
assign VAR40 = (VAR32[18:1] == VAR5[19:2]) & (VAR32[0] == VAR24);
wire [1:0] VAR25;
assign VAR25[0] = VAR2 & ~VAR15 & ~VAR22;
assign VAR25[1] = VAR34 & ~VAR17 & ~VAR40;
wire VAR26;
reg [17:0] VAR31;
assign VAR26 = ~VAR25[0] & ~VAR25[1];
always @(posedge clk) begin
if(VAR26)
VAR31 <= VAR37[19:2] + 2;
end
else
VAR31 <= VAR37[19:2] + 1;
end
wire [1:0] VAR12;
assign VAR12[0] = VAR25[0];
assign VAR12[1] = VAR25[1] & ~VAR25[0];
assign VAR23[18:1] = ({18{VAR12[0]}} & VAR37[19:2])
| ({18{VAR12[1]}} & VAR5[19:2])
| ({18{VAR26}} & VAR31);
assign VAR23[0] = (VAR12[0] & VAR9)|(VAR12[1] & VAR24);
assign VAR13 = VAR23[18:1];
assign VAR18 = ~(({4{VAR12[0]}} & VAR10)|({4{VAR12[1]}} & VAR29));
assign VAR36 = ~VAR23[0];
wire [31:0] VAR16;
assign VAR21 = VAR2 & VAR22;
assign VAR27 = VAR34 & VAR40;
assign VAR16 = ({32{VAR22}} & VAR14)|({32{VAR40}} & VAR28);
assign VAR19 = VAR32[0] ? VAR16 : 32'VAR38;
assign VAR20 = VAR19;
assign VAR33 = VAR19;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o21a/sky130_fd_sc_ms__o21a_4.v
| 2,248 |
module MODULE2 (
VAR4 ,
VAR6 ,
VAR10 ,
VAR8 ,
VAR1,
VAR7,
VAR5 ,
VAR9
);
output VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR5 ;
input VAR9 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR4 ,
VAR6,
VAR10,
VAR8
);
output VAR4 ;
input VAR6;
input VAR10;
input VAR8;
supply1 VAR1;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.blackbox.v
| 1,219 |
module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.behavioral.v
| 1,098 |
module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR2 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR4(.VAR1(VAR1),.VAR3(VAR3));
|
apache-2.0
|
hoangt/NOCulator
|
hring/hw/buffered/src/vcr_comb_alloc_mac.v
| 7,251 |
module MODULE1
(clk, reset, VAR1, VAR27, VAR10, VAR9,
VAR30, VAR22, VAR7, VAR17,
VAR13, VAR28, VAR11, VAR14);
parameter VAR19 = 2;
parameter VAR15 = 2;
localparam VAR25 = VAR19 * VAR15;
parameter VAR29 = 1;
localparam VAR5 = VAR25 * VAR29;
parameter VAR16 = 5;
localparam VAR3 = VAR23(VAR16);
parameter VAR24 = VAR21;
localparam VAR8 = VAR24-VAR12;
parameter VAR4 = VAR18;
parameter VAR2 = VAR6;
input clk;
input reset;
input [0:VAR16*VAR5*VAR3-1] VAR1;
input [0:VAR16*VAR5-1] VAR27;
input [0:VAR16*VAR5-1] VAR10;
input [0:VAR16*VAR5-1] VAR9;
output [0:VAR16*VAR5*VAR5-1] VAR22;
wire [0:VAR16*VAR5*VAR5-1] VAR22;
output [0:VAR16*VAR5-1] VAR30;
wire [0:VAR16*VAR5-1] VAR30;
output [0:VAR16*VAR5-1] VAR7;
wire [0:VAR16*VAR5-1] VAR7;
output [0:VAR16*VAR5*VAR16-1] VAR17;
wire [0:VAR16*VAR5*VAR16-1] VAR17;
output [0:VAR16*VAR5*VAR5-1] VAR13;
wire [0:VAR16*VAR5*VAR5-1] VAR13;
input [0:VAR16*VAR5-1] VAR28;
output [0:VAR16*VAR5-1] VAR11;
wire [0:VAR16*VAR5-1] VAR11;
output [0:VAR16*VAR16-1] VAR14;
wire [0:VAR16*VAR16-1] VAR14;
generate
case(VAR24)
begin
VAR26
.VAR15(VAR15),
.VAR29(VAR29),
.VAR16(VAR16),
.VAR4(VAR4),
.VAR2(VAR2))
VAR20
(.clk(clk),
.reset(reset),
.VAR1(VAR1),
.VAR27(VAR27),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR30(VAR30),
.VAR22(VAR22),
.VAR7(VAR7),
.VAR17(VAR17),
.VAR13(VAR13),
.VAR28(VAR28),
.VAR11(VAR11),
.VAR14(VAR14));
end
endcase
endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nor4bb/sky130_fd_sc_lp__nor4bb.behavioral.pp.v
| 1,998 |
module MODULE1 (
VAR11 ,
VAR2 ,
VAR5 ,
VAR14 ,
VAR4 ,
VAR6,
VAR1,
VAR12 ,
VAR8
);
output VAR11 ;
input VAR2 ;
input VAR5 ;
input VAR14 ;
input VAR4 ;
input VAR6;
input VAR1;
input VAR12 ;
input VAR8 ;
wire VAR15 ;
wire VAR17 ;
wire VAR9;
nor VAR10 (VAR15 , VAR2, VAR5 );
and VAR7 (VAR17 , VAR15, VAR14, VAR4 );
VAR13 VAR3 (VAR9, VAR17, VAR6, VAR1);
buf VAR16 (VAR11 , VAR9 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nor3b/sky130_fd_sc_ms__nor3b_4.v
| 2,254 |
module MODULE2 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR3,
VAR5,
VAR10 ,
VAR6
);
output VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR10 ;
input VAR6 ;
VAR2 VAR8 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR4;
supply1 VAR3;
supply0 VAR5;
supply1 VAR10 ;
supply0 VAR6 ;
VAR2 VAR8 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
qiuzou/nysa_saya
|
rtl/link/sata_link_layer.v
| 11,199 |
module MODULE1 (
input rst, input clk,
output VAR20,
input VAR16,
output VAR70,
input VAR18,
input VAR38,
output VAR56,
input VAR88,
output [31:0] VAR44,
output VAR83,
input [31:0] VAR69,
input [3:0] VAR86,
input VAR43,
output VAR78,
input [31:0] VAR63,
input [31:0] VAR52,
input VAR22,
output VAR35,
input VAR9,
output VAR28,
output VAR15,
output [31:0] VAR47,
input VAR81,
output VAR66,
output VAR33,
output VAR11,
output VAR72,
output VAR49,
input VAR31,
input VAR2,
input VAR14,
output [3:0] VAR84,
output [3:0] VAR40,
output [3:0] VAR46,
output [3:0] VAR89,
output VAR58,
output VAR74,
output VAR32,
output VAR60,
output VAR51,
output VAR73,
output VAR1,
output VAR64,
output VAR57,
output VAR82,
output VAR30,
output VAR71,
output VAR68,
output VAR76,
output VAR19,
output VAR41,
output VAR42,
output VAR91,
output [23:0] VAR34,
output [12:0] VAR36,
output [12:0] VAR17,
output [3:0] VAR26
);
parameter VAR3 = 4'h0;
parameter VAR6 = 4'h1;
parameter VAR48 = 4'h2;
reg [3:0] state;
reg VAR8;
reg VAR21;
reg VAR45;
wire VAR80;
wire [31:0] VAR94;
wire VAR10;
reg VAR7;
wire VAR4;
wire [31:0] VAR53;
wire VAR87;
reg VAR62;
wire VAR85;
wire [31:0] VAR61;
wire VAR24;
wire [31:0] VAR39;
wire VAR77;
wire VAR29;
VAR54 VAR12 (
.rst (rst ),
.clk (clk ),
.VAR38 (VAR38 ),
.VAR92 (VAR31 ),
.VAR29 (VAR29 ),
.VAR69 (VAR69 ),
.VAR86 (VAR86 ),
.VAR59 (VAR39 ),
.VAR77 (VAR77 ),
.VAR27 (VAR44 ),
.VAR5 (VAR83 ),
.VAR58 (VAR58 ),
.VAR74 (VAR74 ),
.VAR32 (VAR32 ),
.VAR51 (VAR51 ),
.VAR60 (VAR60 ),
.VAR73 (VAR73 ),
.VAR1 (VAR1 ),
.VAR64 (VAR64 ),
.VAR57 (VAR57 ),
.VAR82 (VAR82 ),
.VAR30 (VAR30 ),
.VAR71 (VAR71 ),
.VAR76 (VAR76 ),
.VAR19 (VAR19 ),
.VAR68 (VAR68 ),
.VAR41 (VAR41 )
);
VAR55 VAR75 (
.rst (rst ),
.clk (clk ),
.en (VAR7 ),
.VAR79 (VAR4 ),
.VAR38 (VAR38 ),
.VAR56 (VAR56 ),
.VAR65 (VAR16 ),
.VAR73 (VAR73 ),
.VAR74 (VAR74 ),
.VAR32 (VAR32 ),
.VAR51 (VAR51 ),
.VAR60 (VAR60 ),
.VAR82 (VAR82 ),
.VAR30 (VAR30 ),
.VAR71 (VAR71 ),
.VAR58 (VAR58 ),
.VAR68 (VAR68 ),
.VAR50 (VAR91 ),
.VAR43 (VAR43 ),
.VAR78 (VAR78 ),
.VAR63 (VAR63 ),
.VAR52 (VAR52 ),
.VAR22 (VAR22 ),
.VAR35 (VAR35 ),
.VAR9 (VAR9 ),
.VAR29 (VAR29 ),
.VAR42 (VAR42 ),
.VAR70 (VAR70 ),
.VAR44 (VAR53 ),
.VAR83 (VAR87 ),
.VAR69 (VAR69 ),
.VAR86 (VAR86 ),
.VAR72 (VAR72 ),
.VAR49 (VAR49 ),
.VAR2 (VAR2 ),
.VAR14 (VAR14 ),
.state (VAR46 ),
.VAR37 (VAR89 ),
.VAR34 (VAR34 ),
.VAR17 (VAR17 ),
.VAR36 (VAR36 ),
.VAR26 (VAR26 )
);
VAR25 VAR23 (
.rst (rst ),
.clk (clk ),
.en (VAR62 ),
.VAR79 (VAR85 ),
.VAR16 (VAR16 ),
.VAR38 (VAR38 ),
.VAR67 (VAR18 ),
.VAR68 (VAR68 ),
.VAR58 (VAR58 ),
.VAR73 (VAR73 ),
.VAR1 (VAR1 ),
.VAR64 (VAR64 ),
.VAR57 (VAR57 ),
.VAR82 (VAR82 ),
.VAR71 (VAR71 ),
.VAR30 (VAR30 ),
.VAR41 (VAR41 ),
.VAR44 (VAR61 ),
.VAR83 (VAR24 ),
.VAR69 (VAR69 ),
.VAR86 (VAR86 ),
.VAR81 (VAR81 ),
.VAR15 (VAR15 ),
.VAR47 (VAR47 ),
.VAR28 (VAR28 ),
.VAR66 (VAR66 ),
.VAR11 (VAR11 ),
.VAR93 (VAR33 ),
.VAR2 (VAR2 ),
.VAR14 (VAR14 ),
.VAR40 (VAR40 )
);
assign VAR39 = (!VAR85) ? VAR61 : (!VAR4) ? VAR53 : VAR94;
assign VAR77 = (!VAR85) ? VAR24 : (!VAR4) ? VAR87 : VAR10;
assign VAR94 = (VAR45) ? VAR13 :
(VAR21) ? VAR90 :
assign VAR10 = 1;
assign VAR20 = (state == VAR6) && VAR85 && VAR4;
assign VAR84 = state;
always @ (posedge clk) begin
if (rst) begin
state <= VAR3;
VAR45 <= 0;
VAR21 <= 0;
VAR7 <= 0;
VAR62 <= 0;
end
else begin
VAR45 <= 0;
VAR21 <= 0;
VAR7 <= 0;
VAR62 <= 0;
if (!VAR88) begin
state <= VAR3;
end
if (VAR38) begin
case (state)
VAR3: begin
if (VAR88) begin
state <= VAR6;
end
end
VAR6: begin
VAR7 <= 1;
VAR62 <= 1;
if (VAR76 || VAR19) begin
VAR45 <= 1;
state <= VAR48;
end
end
VAR48: begin
if (VAR76 || VAR19) begin
VAR45 <= 1;
end
else begin
state <= VAR6;
end
end
default: begin
state <= VAR3;
end
endcase
end
end
end
endmodule
|
mit
|
ShepardSiegel/ocpi
|
coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/phy_init.v
| 136,321 |
module MODULE1 #
(
parameter VAR290 = 100,
parameter VAR102 = 4, parameter VAR103 = 3000, parameter VAR243 = 64, parameter VAR37 = 2,
parameter VAR42 = 10,
parameter VAR56 = 1, parameter VAR170 = 64,
parameter VAR43 = 8,
parameter VAR55 = 3, parameter VAR100 = 14,
parameter VAR247 = 1,
parameter VAR146 = 1, parameter VAR15 = 1, parameter VAR92 = "VAR30",
parameter VAR87 = "VAR31",
parameter VAR22 = 16'h0000, parameter VAR242 = 12'h000, parameter VAR112 = 3'h0,
parameter VAR10 = "0", parameter VAR131 = "8", parameter VAR17 = "VAR210", parameter VAR139 = 5, parameter VAR224 = 5, parameter VAR50 = 110000, parameter VAR127 = "VAR163", parameter VAR73 = "60", parameter VAR110 = "60", parameter VAR234 = "VAR31", parameter VAR292 = "VAR288", parameter VAR77 = 1, parameter VAR296 = "VAR226", parameter VAR213 = "VAR226" )
(
input clk,
input rst,
input [VAR243-1:0] VAR159,
input VAR251,
input VAR256,
input VAR272,
output VAR197,
input VAR196,
input VAR41,
input VAR153,
input VAR62,
input VAR245,
input [5:0] VAR228,
input [6*VAR146-1:0] VAR248,
input VAR268,
input VAR23,
input VAR258,
input [7:0] VAR222,
input [7:0] VAR67,
output reg VAR71,
output reg VAR173,
output reg VAR134,
input VAR225,
input VAR175,
output reg VAR216,
output reg VAR281,
output reg VAR262,
input VAR141,
input VAR172,
output reg VAR32,
output reg VAR180,
output reg [VAR102*VAR100-1:0] VAR88,
output reg [VAR102*VAR37-1:0]VAR294,
output reg [VAR102-1:0] VAR164,
output reg [VAR102-1:0] VAR182,
output reg [VAR102-1:0] VAR219,
output reg VAR79,
output [VAR247*VAR56*VAR102-1:0] VAR254,
input VAR217,
input VAR27,
input VAR246,
input VAR229,
output reg VAR66,
output reg VAR231,
output reg [1:0] VAR91,
output reg VAR3,
output reg VAR205,
output reg [2:0] VAR284,
output reg [3:0] VAR293,
output reg [3:0] VAR16,
output [1:0] VAR160,
output reg [5:0] VAR6,
output reg VAR221,
output reg [2*VAR102*VAR170-1:0] VAR240,
output VAR218,
output VAR165
);
localparam VAR241 = (VAR131 == "8") ? 128 :
(VAR131 == "4") ? 256 : 128;
localparam VAR273 = (VAR131 == "8") ? 8 :
(VAR131 == "4") ? 4 : 8;
localparam VAR33 = "40";
localparam VAR138 = "40";
localparam VAR152 = (VAR92 == "VAR30")? 1'b0 :
(VAR131 == "8") ? 1'b0 :
((VAR131 == "4") ? 1'b1 : 1'b0);
localparam VAR151 = VAR103 / VAR102;
localparam VAR4 = 200000;
localparam VAR84 = 500000 + VAR4;
localparam VAR7 = 200000;
localparam VAR276 =
((VAR4+VAR103-1)/VAR103);
localparam VAR46 = (VAR92 == "VAR30") ?
(((VAR84+VAR103-1)/VAR103)) :
(((VAR7+VAR103-1)/VAR103));
localparam VAR178 = 400000;
localparam VAR116 =
((VAR178+VAR103-1)/VAR103)-1;
localparam VAR28 =
(5*VAR151 > VAR50+10000) ?
(((5+VAR102-1)/VAR102)-1)+11 :
(((VAR50+10000+VAR103-1)/VAR103)-1)+11;
localparam VAR132 = 255;
localparam VAR133 = ((15000) % VAR151) ?
(15000/VAR151) + 1 : 15000/VAR151;
localparam VAR58 = (VAR102 == 4) ? 7'b1100110 : 7'b1111111;
localparam VAR26 = 2'b00;
localparam VAR104 = 2'b01;
localparam VAR274 = 2'b10;
localparam VAR266 = 2'b11;
localparam VAR44 = 2'b11;
localparam VAR215 = 8'b00000000;
localparam VAR95 = (VAR146 <= 2) ? 8'b00110001 : 8'b00000001;
localparam VAR283 = 8'b00000010;
localparam VAR187 = 8'b00000011;
localparam VAR90 = 8'b00000100;
localparam VAR5 = 8'b00000101;
localparam VAR277 = (VAR10 == "VAR69-1") ? VAR139 - 1 : 0;
localparam VAR86 = (VAR87 == "VAR31") ? VAR224 + VAR277 + 1 : VAR224 + VAR277;
localparam VAR13 = 6'b000000; localparam VAR261 = 6'b000001; localparam VAR244 = 6'b000010; localparam VAR264 = 6'b000011; localparam VAR233 = 6'b000100; localparam VAR167 = 6'b000101; localparam VAR108 = 6'b000110; localparam VAR19 = 6'b000111; localparam VAR269 = 6'b001000; localparam VAR14 = 6'b001001; localparam VAR129 = 6'b001010; localparam VAR128 = 6'b001011; localparam VAR239 = 6'b001100; localparam VAR289 = 6'b001101; localparam VAR238 = 6'b001110; localparam VAR193 = 6'b001111; localparam VAR275 = 6'b010000; localparam VAR94 = 6'b010001; localparam VAR63 = 6'b010010; localparam VAR278 = 6'b010011; localparam VAR40 = 6'b010100; localparam VAR155 = 6'b010101; localparam VAR101 = 6'b010110; localparam VAR161 = 6'b010111; localparam VAR21 = 6'b011000; localparam VAR158 = 6'b011001; localparam VAR287 = 6'b011010; localparam VAR157 = 6'b011011; localparam VAR38 = 6'b011100; localparam VAR282 = 6'b011101; localparam VAR150 = 6'b011110; localparam VAR117 = 6'b011111; localparam VAR267 = 6'b100000; localparam VAR122 = 6'b100001; localparam VAR39 = 6'b100010; localparam VAR115 = 6'b100011; localparam VAR120 = 6'b100100; localparam VAR202 = 6'b100101;
integer VAR236, VAR169, VAR137, VAR20, VAR223, VAR220, VAR89;
reg VAR8;
reg VAR34;
reg VAR2;
reg VAR188;
reg VAR194;
reg VAR29;
reg VAR35;
reg VAR130;
reg [1:0] VAR75;
reg [6:0] VAR147;
reg VAR136;
reg [7:0] VAR195;
reg VAR250;
reg VAR279;
reg [1:0] VAR45;
reg [1:0] VAR186;
reg [1:0] VAR190;
reg VAR184;
reg VAR49;
reg [7:0] VAR68;
reg [9:0] VAR54;
reg VAR211;
reg VAR214;
reg [8:0] VAR124;
reg VAR156;
reg VAR126;
reg [7:0] VAR232;
reg VAR199;
reg VAR12;
reg VAR174;
reg [4:0] VAR235;
reg VAR154;
reg VAR36;
reg VAR106;
reg [5:0] VAR70;
reg [5:0] VAR118;
reg [5:0] VAR61;
wire [15:0] VAR177;
wire [15:0] VAR260;
wire [15:0] VAR80;
wire [15:0] VAR18;
reg VAR286;
reg [1:0] VAR144 [0:3];
reg [2:0] VAR271 [0:3];
reg VAR142;
reg [15:0] VAR11;
wire VAR255;
reg [VAR102-1:0] VAR81;
reg [VAR102-1:0] VAR25;
reg [VAR247*VAR56-1:0] VAR291;
reg [VAR247*VAR56*VAR102-1:0] VAR99;
wire VAR52;
reg [15:0] VAR201;
reg VAR145;
reg VAR83;
reg VAR78;
reg VAR203;
reg VAR60;
reg VAR208;
reg VAR280;
reg VAR111;
reg [VAR100-1:0] VAR252;
reg [VAR37-1:0] VAR259;
reg VAR209;
reg [15:0] VAR148;
wire VAR207;
wire VAR72;
wire VAR237;
reg VAR263;
wire VAR191;
reg [2:0] VAR253;
reg [1:0] VAR179 [0:3];
reg [2:0] VAR105 [0:3];
reg VAR183;
reg VAR64;
reg VAR212;
reg VAR143;
reg VAR123;
reg [2:0] VAR48;
reg VAR85;
reg VAR24;
reg VAR200;
reg [1:0] VAR149;
reg [8:0] VAR257;
reg VAR59;
reg VAR114;
reg [1:0] VAR198;
reg [VAR243-1:0] VAR168;
reg [VAR243-1:0] VAR121;
reg [VAR243-1:0] VAR230;
reg [VAR243-1:0] VAR107;
reg [VAR243-1:0] VAR166;
reg [VAR243-1:0] VAR204;
reg [VAR243-1:0] VAR265;
always @(posedge VAR286) begin
if (!rst)
end
always @(posedge VAR153) begin
if (!rst && (VAR234 == "VAR31"))
end
always @(posedge VAR225) begin
if (!rst)
end
always @(posedge VAR35) begin
if (!rst)
end
always @(posedge VAR272) begin
if (!rst)
end
always @(posedge VAR23) begin
if (!rst && (VAR234 == "VAR31"))
end
assign VAR197 = VAR35;
always @(posedge clk)
if (rst) begin
end else begin
if (VAR118 == VAR101)
end
generate
if(VAR92 == "VAR30") begin: VAR93
assign VAR177[1:0] = (VAR131 == "8") ? 2'b00 :
(VAR131 == "VAR249") ? 2'b01 :
(VAR131 == "4") ? 2'b10 : 2'b11;
assign VAR177[2] = (VAR139 >= 12) ? 1'b1 : 1'b0; assign VAR177[3] = (VAR17 == "VAR210") ? 1'b0 : 1'b1;
assign VAR177[6:4] = ((VAR139 == 5) || (VAR139 == 13)) ? 3'b001 :
((VAR139 == 6) || (VAR139 == 14)) ? 3'b010 :
(VAR139 == 7) ? 3'b011 :
(VAR139 == 8) ? 3'b100 :
(VAR139 == 9) ? 3'b101 :
(VAR139 == 10) ? 3'b110 :
(VAR139 == 11) ? 3'b111 :
(VAR139 == 12) ? 3'b000 : 3'b111;
assign VAR177[7] = 1'b0;
assign VAR177[8] = 1'b1; assign VAR177[11:9] = (VAR133 == 5) ? 3'b001 :
(VAR133 == 6) ? 3'b010 :
(VAR133 == 7) ? 3'b011 :
(VAR133 == 8) ? 3'b100 :
(VAR133 == 9) ? 3'b101 :
(VAR133 == 10) ? 3'b101 :
(VAR133 == 11) ? 3'b110 :
(VAR133 == 12) ? 3'b110 :
(VAR133 == 13) ? 3'b111 :
(VAR133 == 14) ? 3'b111 :
(VAR133 == 15) ? 3'b000 :
(VAR133 == 16) ? 3'b000 : 3'b010;
assign VAR177[12] = 1'b0; assign VAR177[15:13] = 3'b000;
end else if (VAR92 == "VAR65") begin: VAR206 assign VAR177[2:0] = (VAR131 == "8") ? 3'b011 :
(VAR131 == "4") ? 3'b010 : 3'b111;
assign VAR177[3] = (VAR17 == "VAR210") ? 1'b0 : 1'b1;
assign VAR177[6:4] = (VAR139 == 3) ? 3'b011 :
(VAR139 == 4) ? 3'b100 :
(VAR139 == 5) ? 3'b101 :
(VAR139 == 6) ? 3'b110 : 3'b111;
assign VAR177[7] = 1'b0;
assign VAR177[8] = 1'b1; assign VAR177[11:9] = (VAR133 == 2) ? 3'b001 :
(VAR133 == 3) ? 3'b010 :
(VAR133 == 4) ? 3'b011 :
(VAR133 == 5) ? 3'b100 :
(VAR133 == 6) ? 3'b101 : 3'b010;
assign VAR177[15:12]= 4'b0000; end
endgenerate
generate
if(VAR92 == "VAR30") begin: VAR270
assign VAR260[0] = 1'b0; assign VAR260[1] = (VAR127 == "VAR135") ? 1'b0 : 1'b1;
assign VAR260[2] = ((VAR73 == "30") || (VAR73 == "40") ||
(VAR73 == "60")) ? 1'b1 : 1'b0;
assign VAR260[4:3] = (VAR10 == "0") ? 2'b00 :
(VAR10 == "VAR69-1") ? 2'b01 :
(VAR10 == "VAR69-2") ? 2'b10 : 2'b11;
assign VAR260[5] = 1'b0;
assign VAR260[6] = ((VAR73 == "40") || (VAR73 == "120")) ?
1'b1 : 1'b0;
assign VAR260[7] = 1'b0; assign VAR260[8] = 1'b0;
assign VAR260[9] = ((VAR73 == "20") || (VAR73 == "30")) ?
1'b1 : 1'b0;
assign VAR260[10] = 1'b0;
assign VAR260[15:11] = 5'b00000;
end else if (VAR92 == "VAR65") begin: VAR125
assign VAR260[0] = 1'b0; assign VAR260[1] = (VAR127 == "VAR135") ? 1'b1 : 1'b0;
assign VAR260[2] = ((VAR73 == "75") || (VAR73 == "50")) ?
1'b1 : 1'b0;
assign VAR260[5:3] = (VAR10 == "0") ? 3'b000 :
(VAR10 == "1") ? 3'b001 :
(VAR10 == "2") ? 3'b010 :
(VAR10 == "3") ? 3'b011 :
(VAR10 == "4") ? 3'b100 : 3'b111;
assign VAR260[6] = ((VAR73 == "50") ||
(VAR73 == "150")) ? 1'b1 : 1'b0;
assign VAR260[9:7] = 3'b000;
assign VAR260[10] = (VAR292 == "VAR288") ? 1'b0 : 1'b1;
assign VAR260[15:11] = 5'b00000;
end
endgenerate
generate
if(VAR92 == "VAR30") begin: VAR51
assign VAR80[2:0] = 3'b000;
assign VAR80[5:3] = (VAR224 == 5) ? 3'b000 :
(VAR224 == 6) ? 3'b001 :
(VAR224 == 7) ? 3'b010 :
(VAR224 == 8) ? 3'b011 :
(VAR224 == 9) ? 3'b100 :
(VAR224 == 10) ? 3'b101 :
(VAR224 == 11) ? 3'b110 : 3'b111;
assign VAR80[6] = 1'b0;
assign VAR80[7] = 1'b0;
assign VAR80[8] = 1'b0;
assign VAR80[10:9] = 2'b00;
assign VAR80[15:11] = 5'b00000;
end else begin: VAR109
assign VAR80[15:0] = 16'd0;
end
endgenerate
assign VAR18[1:0] = 2'b00;
assign VAR18[2] = 1'b0;
assign VAR18[15:3] = 13'b0000000000000;
assign VAR160 = VAR75;
assign VAR255 = (VAR118 == VAR115);
assign VAR52 = (((VAR118 == VAR275) ||
(VAR118 == VAR94) ||
(VAR118 == VAR115)) &&
VAR145 &&
!VAR83);
always @(posedge clk) begin
VAR255};
VAR52};
end
always @(posedge clk)
always @(posedge clk)
if (rst) begin
end else begin
if (!VAR272 && VAR118 == VAR94)
if (VAR272 && VAR136 &&
(VAR118 == VAR289))
if (VAR272 &&
(VAR118 == VAR275))
if (VAR11[5])
end
always @(posedge clk)
if (rst)
end
else if (VAR272)
generate
if (VAR102 == 4) begin: VAR57
always @ (posedge clk)
if (rst || VAR62)
end
else if ((VAR118 == VAR108) ||
(VAR85 && (VAR235 == 5'd0)))
end
else if ((VAR235 > 5'd0) && ~(VAR27 || VAR246))
always @(posedge clk)
if (rst || VAR62 || VAR245)
end
else if (VAR235 == 5'd1)
end else begin: VAR9
always @ (posedge clk)
if (rst)
end
else if ((VAR118 == VAR108) ||
(VAR85 && (VAR235 == 5'd0)))
end
else if ((VAR235 > 5'd0) && ~(VAR27 || VAR246))
always @(posedge clk)
if (rst || VAR62 || VAR245)
end
else if (VAR235 == 5'd1)
end
endgenerate
always @(posedge clk)
if (rst || VAR62 || VAR245)
else if ((VAR235 == 5'd1) && VAR85 && !VAR24)
always @(posedge clk)begin
if(rst || (VAR235 != 5'd1)) begin
end else if ((VAR235 == 5'd1) && (VAR200)) begin
end
end
always @ (posedge clk) begin
if (rst)
end
else if (VAR59 && VAR198 != 2'd3)
end
always @ (posedge clk) begin
if (rst || ~VAR24)
end
else if (VAR198 == 2'd3)
end
always @(posedge clk) begin
if (rst)
end
else
end
always @(posedge clk) begin
end
always @ (posedge clk) begin
if (rst)
end
else if (VAR62)
end
assign VAR1 = VAR141 | VAR258;
always @(posedge clk)
if (rst) begin
end else begin
if (VAR83)
end
else if (VAR52)
end
always @(posedge clk) begin
case (VAR118)
VAR264,
VAR14,
VAR128,
VAR289,
VAR193,
VAR63,
VAR267,
VAR39,
VAR120,
VAR278,
VAR155,
VAR21,
VAR38,
VAR287: begin
if (VAR27 || VAR246)
end
else
end
VAR19:
default:
endcase
end
always @(posedge clk)
always @(posedge clk) begin
if (rst)
end
else if ((VAR147 == VAR58) &&
(VAR118 == VAR63))
else
end
always @(posedge clk)
if (rst) begin
end else begin
end
always @(posedge clk)
if (rst)
end
else if (VAR203)
always @(posedge clk)
if (rst || ~VAR217) begin
end else begin
if ((VAR296 == "VAR53") ||
(VAR296 == "VAR176")) begin
end else begin
if (VAR92 == "VAR30") begin
if (!VAR156)
VAR156
if (!VAR211)
VAR211
VAR211
end
end
end
always @(posedge clk)
always @(posedge clk) begin
end
always @(posedge clk)
if (!VAR211) begin
end else begin
if (!VAR126)
end
always @(posedge clk)
if (!VAR211) begin
end else begin
if (!VAR49)
VAR49
end
always @(posedge clk)
if (VAR118 == VAR233) begin
end else if (~(VAR27 || VAR246)) begin
if (!VAR250)
VAR250
end
always @(posedge clk)
if ((VAR118 == VAR13)||
((VAR118 == VAR158)
&& (~VAR286))) begin
end else if (VAR118 == VAR244) begin
end
always @(posedge clk)
if (VAR118 == VAR13)
end
else if (VAR118 == VAR244)
end
else if ((VAR12) &&
(VAR118 == VAR264)&&
(VAR136) && (VAR184))
always @(posedge clk)
if (VAR118 == VAR13)
end
else if ((VAR118 == VAR158) && (~VAR286))
end
else if ((VAR12) &&
(VAR118 == VAR264)&&
(VAR136) && (VAR184))
always @(posedge clk)
if (VAR118 == VAR13) begin
end else if ((VAR118 == VAR158) && (~VAR286))begin
end
always @(posedge clk)
if (VAR118 == VAR13)
end
else if (VAR118 == VAR157)
always @(posedge clk)
if (VAR118 == VAR13)
end
else if (VAR118 == VAR193)
always @(posedge clk)
if (rst)begin
end else begin
end
always @(VAR130 or VAR75 or VAR136
or VAR250 or VAR279
or VAR184 or VAR217 or VAR27
or VAR246 or VAR149 or VAR41 or VAR8
or VAR49 or VAR211
or VAR126 or VAR199
or VAR12 or VAR174
or VAR118 or VAR286
or VAR83 or VAR23 or VAR172
or VAR225 or VAR175 or VAR209
or VAR257 or VAR194 or VAR29 or VAR35
or VAR272 or VAR268 or VAR281
or VAR253 or VAR64 or VAR123) begin
VAR70 = VAR118;
case (VAR118)
VAR13:
if (VAR211 && VAR217
&& ~(VAR27 || VAR246) && VAR41) begin
if (VAR296 == "VAR176")
if (VAR234 == "VAR31")
VAR70 = VAR108;
end
else VAR70 = VAR239;
end
else
VAR70 = VAR261;
end
VAR261:
if ((VAR126) && (VAR92 == "VAR30")
&& ~(VAR27 || VAR246)) begin
if((VAR87 == "VAR31") && ((VAR56 > 1) ||
(VAR146 > 1)))
VAR70 = VAR157;
end
else
VAR70 = VAR244;
end else if ((VAR49) && (VAR92 == "VAR65")
&& ~(VAR27 || VAR246))
VAR70 = VAR161;
VAR157:
VAR70 = VAR38;
VAR38:
if (VAR136 && ~(VAR27 || VAR246)) begin
if(VAR253 == 3'd5)
VAR70 = VAR244;
end
else
VAR70 = VAR157;
end
VAR244:
VAR70 = VAR264;
VAR264:
if (VAR136 && ~(VAR27 || VAR246)) begin
if(VAR225 && VAR272)
VAR70 = VAR40;
end
else if (VAR184)begin
if(VAR92 == "VAR30")
VAR70 = VAR233;
end
else begin if(VAR12)begin
if (!VAR286 && (VAR75 <= VAR146-1))
VAR70 = VAR282;
end
else
VAR70 = VAR239;
end else
VAR70 = VAR161;
end
end else
VAR70 = VAR244;
end
VAR282:
VAR70 = VAR150;
VAR150:
VAR70 = VAR161;
VAR233:
VAR70 = VAR167;
VAR167:
if (VAR250 && ~(VAR27 || VAR246))
if (!VAR286 && (VAR75 <= VAR146-1))
VAR70 = VAR244;
else if (VAR234 == "VAR31")
VAR70 = VAR108;
else
VAR70 = VAR239;
VAR161:
VAR70 = VAR21;
VAR21:
if (VAR136 && ~(VAR27 || VAR246)) begin
if(VAR199)
VAR70 = VAR158;
end
else VAR70 = VAR244;
end
VAR158:
VAR70 = VAR287;
VAR287:
if (VAR136 && ~(VAR27 || VAR246))begin
if(VAR279 && (~VAR286))
VAR70 = VAR244;
end
else if (((VAR225 && VAR272) && (VAR234 == "VAR31"))
&& VAR286)
VAR70 = VAR117;
else if (VAR286)
VAR70 = VAR239;
else VAR70 = VAR158;
end
VAR108:
VAR70 = VAR19;
VAR19:
if (VAR123 && ~(VAR27 || VAR246))
VAR70 = VAR269;
VAR269:
VAR70 = VAR14;
VAR14:
if (VAR136 && ~(VAR27 || VAR246))
VAR70 = VAR129;
VAR129:
VAR70 = VAR128;
VAR128:
if (VAR136 && ~(VAR27 || VAR246)) begin
if (~VAR64)
VAR70 = VAR108;
end
else if (VAR213 == "VAR47")
VAR70 = VAR101;
else
VAR70 = VAR239;
end
VAR239:
VAR70 = VAR289;
VAR289:
if (VAR136 && ~(VAR27 || VAR246)) begin
if (VAR194 && !VAR29)
VAR70 = VAR202;
end
else if (!VAR272)
VAR70 = VAR94;
else if (!VAR225 && ~VAR8)
VAR70 = VAR238;
else if (!VAR225 && VAR209)
VAR70 = VAR275;
else
VAR70 = VAR278;
end
VAR202:
if (VAR35)
VAR70 = VAR278;
VAR238:
if (VAR257 == 9'd1)
VAR70 = VAR193;
VAR193:
if (VAR136 && ~(VAR27 || VAR246))
VAR70 = VAR275;
VAR275:
if (VAR175 || VAR225 || VAR83)
VAR70 = VAR278;
VAR94:
if (VAR149 == 'b1)
VAR70 = VAR63;
VAR63:
if (~(VAR27 || VAR246)) begin
if (VAR268 ||
VAR272 || VAR83)
VAR70 = VAR278;
end
else if (VAR136)
VAR70 = VAR94;
end
VAR117:
VAR70 = VAR267;
VAR267:
if (VAR136)
VAR70 = VAR122;
VAR122:
if (VAR130 == 1'b1)
VAR70 = VAR39;
VAR39:
if (VAR136 && ~(VAR27 || VAR246))
VAR70 = VAR115;
VAR115:
if (VAR130 == 1'b1)
VAR70 = VAR120;
VAR120:
if (~(VAR27 || VAR246)) begin
if (VAR172)
VAR70 = VAR122;
end
else if (VAR23 || VAR83)
VAR70 = VAR278;
end
VAR278:
if (VAR136 && ~(VAR27 || VAR246))
VAR70 = VAR40;
VAR40:
VAR70 = VAR155;
VAR155:
if (VAR136 && ~(VAR27 || VAR246)) begin
if ((VAR23 || (VAR234 == "VAR76")) && VAR225 &&
VAR272 && ((VAR174) || (VAR92 == "VAR65")))
VAR70 = VAR101;
end
else if ((VAR23 || (VAR234 == "VAR76")) && VAR225
&& VAR272)
VAR70 = VAR244;
else if (VAR225 && VAR272 && (VAR234 == "VAR31"))
VAR70 = VAR158;
else
VAR70 = VAR158;
end
VAR101:
VAR70 = VAR101;
endcase
end
always @(posedge clk)
if (rst)
else if ((!VAR250 &&
(VAR195 == VAR132) &&
(VAR75 == VAR146-1) && (VAR92 == "VAR30"))
|| ( (VAR118 == VAR264) &&
(VAR12) && (VAR75 == VAR146-1)
&& (VAR184) && (VAR92 == "VAR65")))
always @(posedge clk) begin
if (rst || VAR245)
end
else if (VAR200)
end
always @(posedge clk) begin
if (rst || VAR35)
end
else if (~VAR35 && (VAR118 == VAR289) &&
(VAR147 == VAR58))
end
always @(posedge clk)
always @(posedge clk) begin
if (rst || VAR35)
end
else if (~VAR35 && (VAR118 == VAR202))
end
always @(posedge clk)
if (rst)
else if (VAR256)
always @(posedge clk)
if (rst)
else if ((VAR118 == VAR264) &&
(VAR75 == VAR146-1) && VAR23)
always @(posedge clk)
always @(posedge clk)
if (rst || (VAR183 &&
(VAR118==VAR128)))begin
end else if ((((VAR118 == VAR167) &&
(VAR195 == VAR132)) ||
((VAR118!=VAR128) &&
(VAR70==VAR128)) &&
(VAR92 == "VAR30")) ||
VAR175 ||
(VAR268 && ~VAR2) ||
((VAR118 == VAR264)&& VAR136
&& VAR23) ||
((VAR118 == VAR282)
&& (VAR92 == "VAR65"))) begin
if ((~VAR286 || ~VAR225 || ~VAR272 ||
VAR23)
&& (VAR75 != VAR146-1))
end
else
end
generate
if (VAR92 == "VAR30") begin: VAR30
always @(posedge clk)
if (rst)
end
else if (VAR146 == 1)
else begin
case (VAR75)
2'b00:begin
for (VAR220 = 0; VAR220 < VAR56*VAR102*2; VAR220 = VAR220 + (VAR56*2)) begin
end
end
2'b01:begin
for (VAR89 = VAR56; VAR89 < VAR56*VAR102*2; VAR89 = VAR89 + (VAR56*2)) begin
end
end
endcase
end
end else begin: VAR65
always @(posedge clk)
if (rst) begin
end else begin
if (VAR118 == VAR157) begin
end else if ((VAR85) ||
(VAR118 == VAR244) ||
(VAR118 == VAR233) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR239) ||
(VAR118 == VAR202) ||
(VAR118 == VAR238) ||
(VAR118 == VAR275) ||
(VAR118 == VAR40) ||
(VAR118 == VAR94) ||
(VAR118 == VAR117) ||
(VAR118 == VAR115) ||
(VAR118 == VAR122) ||
(VAR118 == VAR161) ||
(VAR118 == VAR158)) begin
end
end end endgenerate
assign VAR254 = VAR99;
assign VAR237 = (VAR118 == VAR238) ||
(VAR118 == VAR122);
assign VAR72 = (VAR118 == VAR202) ||
(VAR118 == VAR275) ||
(VAR118 == VAR94) ||
(VAR118 == VAR115);
assign VAR191 = VAR237 | VAR72;
generate
if (VAR102 == 4) begin:VAR295
always @(posedge clk)
if (rst || VAR23)
end
else if ((VAR118 == VAR267) ||
(VAR118 == VAR122) ||
(VAR118 == VAR39) ||
(VAR118 == VAR115) ||
(VAR118 == VAR120))
end
else if (VAR191)
end
else
end else begin: VAR97
always @(posedge clk)
if (VAR191)
end
else
end
endgenerate
always @(posedge clk)
if (rst || (VAR118 == VAR193) ||
VAR225 || (VAR257==9'd0))
always @(posedge clk)
if (rst || (VAR118 == VAR63))
else if ((VAR149 > 2'b00) && ~(VAR27 || VAR246))
else if ((VAR118 == VAR94) || VAR27 || VAR246)
always @(posedge clk)
if (VAR191) begin
end
always @(posedge clk) begin
end
generate
if ((VAR102 == 4) || (VAR131 == "4")) begin: VAR185
always @(rst or VAR229 or VAR118) begin
if (rst)
VAR60 = 1'b0;
end
else if (~VAR229 && ((VAR118 == VAR238) ||
(VAR118 == VAR122)))
VAR60 = 1'b1;
end
else
VAR60 = 1'b0;
end
end else begin: VAR227
always @(VAR237 or VAR263)
VAR60 = VAR237 | VAR263;
end
endgenerate
assign VAR218 = ~VAR196;
assign VAR165 = (VAR36) ? VAR218 : 1'b0;
always @(posedge clk)
if ((VAR118 == VAR13) ||
(VAR118 == VAR238))
else if (VAR60)
else if (VAR118 == VAR122)
always @(posedge clk) begin
end
generate
if (VAR102 == 4) begin: VAR285
always @(posedge clk)
VAR121[VAR170-1:0],VAR230[VAR170-1:0],
VAR107[VAR170-1:0],VAR166[VAR170-1:0],
VAR204[VAR170-1:0],VAR265[VAR170-1:0]};
end
{VAR170/4{4'hA}},{VAR170/4{4'h5}},
{VAR170/4{4'h5}},{VAR170/4{4'hA}},
{VAR170/4{4'h0}},{VAR170/4{4'hF}}};
end else begin: VAR192
always @(posedge clk)
case (VAR186)
2'b00:
VAR121[VAR170-1:0],VAR230[VAR170-1:0]};
2'b01:
VAR204[VAR170-1:0],VAR265[VAR170-1:0]};
2'b10:
{VAR170/4{4'h0}},{VAR170/4{4'hF}}};
2'b11:
{VAR170/4{4'hA}},{VAR170/4{4'h5}}};
endcase
end
endgenerate
generate
if (VAR102 == 4) begin: VAR82
if (!(VAR86 % 2)) begin: VAR98
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR239) ||
(VAR118 == VAR117) ||
(VAR118 == VAR40) ||
(VAR118 == VAR161) ||
(VAR118 == VAR158))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR158) ||
(VAR191 && VAR142))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR233) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR40) ||
(VAR118 == VAR161)||
(VAR237 && VAR142))begin
end else begin
end
end end else begin: VAR119
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR239) ||
(VAR118 == VAR117) ||
(VAR118 == VAR40) ||
(VAR118 == VAR161) ||
(VAR118 == VAR158))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR158) ||
(VAR191 && VAR142))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR233) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR40) ||
(VAR118 == VAR161)||
(VAR237 && VAR142))begin
end else begin
end
end
end end else begin: VAR96
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR239) ||
(VAR118 == VAR117) ||
(VAR118 == VAR40) ||
(VAR118 == VAR161) ||
(VAR118 == VAR158))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR158) ||
(VAR191 && VAR142))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR118 == VAR244) ||
(VAR118 == VAR157) ||
(VAR118 == VAR233) ||
(VAR118 == VAR108) ||
(VAR118 == VAR269) ||
(VAR118 == VAR129) ||
(VAR118 == VAR40) ||
(VAR118 == VAR161)||
(VAR237 && VAR142))begin
end else begin
end
end
end
endgenerate
always @(posedge clk) begin
if (VAR59) begin
end
end else if (VAR237 && VAR142) begin
end
end else if (VAR72 && VAR142) begin
if (~VAR35)
end
else if (~VAR34)
end
else
end else begin
end
end
always @(posedge clk) begin
if (rst) begin
end else if (VAR211 && VAR217
&& ~(VAR27 || VAR246)) begin
end else begin
end
end
generate
genvar VAR162;
for (VAR162 = 0; VAR162 < 4; VAR162 = VAR162 + 1) begin: VAR113
always @(posedge clk) begin
if (rst) begin
end else begin
end
end
end
endgenerate
generate
if (VAR77 == 1) begin: VAR74
always @(posedge clk) begin
case ({VAR222[0],VAR222[1],
VAR222[2],VAR222[3]})
4'b1111: begin
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
VAR291[((VAR75*VAR56)
end
4'b1000: begin
if ((VAR87 == "VAR31") && (VAR56 > 1)) begin
end else begin
end
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153)) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1100: begin
VAR291[((VAR75*VAR56)
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
default: begin
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153)) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
endcase end
end else if (VAR77 == 2) begin: VAR140
always @ (posedge clk) begin
case ({VAR222[0],VAR222[1],
VAR67[0],VAR67[1]})
4'b1000: begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
end
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153)) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b0010: begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
end
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153)) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b0011: begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
VAR81
end
VAR291[(VAR75*VAR56) +: VAR56]
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1100: begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
end
VAR291[(VAR75*VAR56) +: VAR56]
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1010: begin
if(VAR92 == "VAR65")begin
if(VAR75 == 2'b00)begin
VAR81
VAR81
end else begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
VAR81
(VAR118 == VAR275) ||
(VAR118 == VAR94) ||
(VAR118 == VAR115)) begin
if (VAR75 == 2'b00) begin
VAR81
end else if (VAR75 == 2'b01) begin
VAR81
end
end
end
VAR291[(VAR75*VAR56) +: VAR56]
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR73 == "120") ? 3'b010 :
(VAR73 == "20") ? 3'b100 :
(VAR73 == "30") ? 3'b101 :
3'b011;
2'b10;
(VAR73 == "120") ? 3'b010 :
(VAR73 == "20") ? 3'b100 :
(VAR73 == "30") ? 3'b101 :
3'b011;
end
end
4'b1011: begin
(VAR138 == "120") ? 3'b010 :
(VAR138 == "20") ? 3'b100 :
(VAR138 == "30") ? 3'b101 :
3'b011;
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR73 == "120") ? 3'b010 :
(VAR73 == "20") ? 3'b100 :
(VAR73 == "30") ? 3'b101 :
3'b011;
2'b10;
end
if(VAR92 == "VAR65")begin
if(VAR75 == 2'b00)begin
VAR81
end else begin
VAR81
end
end else begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
if (VAR75[0] == 1'b1) begin
VAR81
end else begin
VAR81
end else if ((VAR118 == VAR275)
|| (VAR118 == VAR202) ||
(VAR118 == VAR94) ||
(VAR118 == VAR115))begin
if (VAR75 == 2'b00) begin
VAR81
end else begin
VAR81
end
end
end
VAR291[(VAR75*VAR56) +: VAR56]
end
4'b1110: begin
(VAR33 == "120") ? 3'b010 :
(VAR33 == "20") ? 3'b100 :
(VAR33 == "30") ? 3'b101 :
3'b011;
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR73 == "120") ? 3'b010 :
(VAR73 == "20") ? 3'b100 :
(VAR73 == "30") ? 3'b101 :
3'b011;
2'b10;
end
if(VAR92 == "VAR65")begin
if(VAR75[1] == 1'b1)begin
VAR81 <=
end else begin
VAR81
end else begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
if (VAR75[1] == 1'b1) begin
VAR81
end else begin
VAR81 <=
end
end else if ((VAR118 == VAR275)
|| (VAR118 == VAR202) ||
(VAR118 == VAR94) ||
(VAR118 == VAR115)) begin
if (VAR75[1] == 1'b1) begin
VAR81[(1*VAR56) +: VAR56]
end else begin
VAR81
end
end end
VAR291[(VAR75*VAR56) +: VAR56]
end
4'b1111: begin
(VAR33 == "120") ? 3'b010 :
(VAR33 == "20") ? 3'b100 :
(VAR33 == "30") ? 3'b101 :
3'b011;
(VAR138 == "120") ? 3'b010 :
(VAR138 == "20") ? 3'b100 :
(VAR138 == "30") ? 3'b101 :
3'b011;
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153 &&
(VAR48==3'd0))) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
2'b10;
end
if(VAR92 == "VAR65")begin
if(VAR75[1] == 1'b1)begin
VAR81
end else begin
VAR81
end
end else begin
if ( (VAR118 == VAR238) ||
(VAR118 == VAR122)) begin
if (VAR75[0] == 1'b1) begin
VAR81
end else begin
VAR81
end
end else if ((VAR118 == VAR275)
|| (VAR118 == VAR202) ||
(VAR118 == VAR94) ||
(VAR118 == VAR115))begin
if (VAR75[0] == 1'b1) begin
VAR81
end else begin
VAR81
end
end end
VAR291[(VAR75*VAR56) +: VAR56]
end
default: begin
VAR291[(VAR75*VAR56) +: VAR56]
if ((VAR110 == "VAR76") ||
((VAR234=="VAR31") && ~VAR153)) begin
(VAR73 == "60") ? 3'b001 :
3'b010;
(VAR73 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR73 == "120") ? 3'b010 :
(VAR73 == "20") ? 3'b100 :
(VAR73 == "30") ? 3'b101 :
3'b011;
2'b10;
(VAR73 == "120") ? 3'b010 :
(VAR73 == "20") ? 3'b100 :
(VAR73 == "30") ? 3'b101 :
3'b011;
end
end
endcase
end
end
endgenerate
generate
if ((VAR77 == 1) && (VAR146 > 2)) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR211 && ~VAR214)
end
else
if ((((VAR73 == "VAR189") && (VAR110 == "VAR76")) ||
VAR62 || VAR212 ||
(VAR153 && !VAR183)) && (VAR92 == "VAR30"))
end
else if (((VAR92 == "VAR30")
||((VAR73 != "VAR189") && (VAR92 == "VAR65")))
&& (((VAR118 == VAR19) && VAR85) ||
(VAR118 == VAR238) ||
(VAR118 == VAR122)))
end
else
end
end else if ((VAR77 == 1) && (VAR146 <= 2)) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR211 && ~VAR214)begin
end else begin
end
if ((((VAR73 == "VAR189") && (VAR110 == "VAR76")) ||
VAR62 || VAR212 ||
(VAR153 && !VAR183)) && (VAR92 == "VAR30")) begin
end else if (((VAR92 == "VAR30")
||((VAR73 != "VAR189") && (VAR92 == "VAR65")))
&& (((VAR118 == VAR19) && VAR85) ||
(VAR118 == VAR238) ||
(VAR118 == VAR122))) begin
end else begin
end
end
end else if ((VAR77 == 2) && (VAR146 > 2)) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR211 && ~VAR214)
end
else
if ((((VAR73 == "VAR189") && (VAR110 == "VAR76")) ||
VAR62 || VAR212 ||
(VAR153 && !VAR183)) && (VAR92 == "VAR30"))
end
else if (((VAR92 == "VAR30")
||((VAR73 != "VAR189") && (VAR92 == "VAR65")))
&& (((VAR118 == VAR19) && VAR85) ||
(VAR118 == VAR238) ||
(VAR118 == VAR122)))
end
else
end
end else if ((VAR77 == 2) && (VAR146 <= 2)) begin
always @(posedge clk)
if (rst) begin
end else begin
if (VAR211 && ~VAR214)begin
end else begin
end
if ((((VAR73 == "VAR189") && (VAR110 == "VAR76")) ||
VAR62 || VAR212 ||
(VAR153 && !VAR183)) && (VAR92 == "VAR30")) begin
end else if (((VAR92 == "VAR30")
||((VAR73 != "VAR189") && (VAR92 == "VAR65")))
&& (((VAR118 == VAR19) && VAR85) ||
(VAR118 == VAR238) ||
(VAR118 == VAR122))) begin
end else begin
end
end
end
endgenerate
always @(VAR130 or VAR190 or VAR75
or VAR12 or VAR118 or VAR177
or VAR260 or VAR80 or VAR18 or VAR271[VAR75][0]
or VAR271[VAR75][1] or VAR271[VAR75][2] or VAR144[VAR75]
or VAR225 or VAR272 or VAR191
or VAR253)begin
VAR252 = 'b0;
VAR259 = 'b0;
if ((VAR118 == VAR40) ||
(VAR118 == VAR233) ||
(VAR118 == VAR161)) begin
VAR252 = 'b0;
VAR252[10] = 1'b1;
VAR259 = 'b0;
end else if (VAR118 == VAR108) begin
VAR259[1:0] = 2'b01;
VAR252 = VAR260[VAR100-1:0];
VAR252[7] = 1'b1;
end else if (VAR118 == VAR269) begin
VAR259[1:0] = 2'b01;
VAR252 = VAR260[VAR100-1:0];
VAR252[2] = VAR271[VAR75][0];
VAR252[6] = VAR271[VAR75][1];
VAR252[9] = VAR271[VAR75][2];
end else if (VAR118 == VAR129) begin
VAR259[1:0] = 2'b10;
VAR252 = VAR80[VAR100-1:0];
VAR252[10:9] = VAR144[VAR75];
end else if ((VAR118 == VAR157)&
(VAR92 == "VAR30"))begin
VAR259 = 'b0;
VAR252 = 'b0;
case (VAR253)
VAR215[2:0]: VAR252[4:0] = VAR215[4:0];
VAR95[2:0]:begin
VAR252[4:0] = VAR95[4:0];
VAR259 = VAR95[7:5];
end
VAR283[2:0]: VAR252[4:0] = VAR283[4:0];
VAR187[2:0]: VAR252[4:0] = VAR187[4:0];
VAR90[2:0]: VAR252[4:0] = VAR90[4:0];
VAR5[2:0]: VAR252[4:0] = VAR5[4:0];
endcase
end else if (VAR118 == VAR244) begin
VAR252 = 'b0;
VAR259 = 'b0;
if(VAR92 == "VAR30")begin
if(VAR225 && VAR272)begin
VAR259[1:0] = 2'b00;
VAR252 = VAR177[VAR100-1:0];
VAR252[8]= 1'b0; end else begin
case (VAR190)
VAR26: begin
VAR259[1:0] = 2'b10;
VAR252 = VAR80[VAR100-1:0];
VAR252[10:9] = VAR144[VAR75];
end
VAR104: begin
VAR259[1:0] = 2'b11;
VAR252 = VAR18[VAR100-1:0];
end
VAR274: begin
VAR259[1:0] = 2'b01;
VAR252 = VAR260[VAR100-1:0];
VAR252[2] = VAR271[VAR75][0];
VAR252[6] = VAR271[VAR75][1];
VAR252[9] = VAR271[VAR75][2];
end
VAR266: begin
VAR259[1:0] = 2'b00;
VAR252 = VAR177[VAR100-1:0];
VAR252[1:0] = 2'b00;
end
default: begin
VAR259 = {VAR37{1'VAR181}};
VAR252 = {VAR100{1'VAR181}};
end
endcase end end else begin case (VAR190)
VAR26: begin
if(~VAR12)begin
VAR259[1:0] = 2'b10;
VAR252 = VAR80[VAR100-1:0];
end else begin VAR259[1:0] = 2'b00;
VAR252 = VAR177[VAR100-1:0];
VAR252[8]= 1'b0;
end
end
VAR104: begin
if(~VAR12)begin
VAR259[1:0] = 2'b11;
VAR252 = VAR18[VAR100-1:0];
end else begin VAR259[1:0] = 2'b00;
VAR252 = VAR177[VAR100-1:0];
VAR252[8]= 1'b0;
end
end
VAR274: begin
VAR259[1:0] = 2'b01;
if(~VAR12)begin
VAR252 = VAR260[VAR100-1:0];
end else begin VAR252 = VAR260[VAR100-1:0];
VAR252[9:7] = 3'b111;
end
end
VAR266: begin
if(~VAR12)begin
VAR259[1:0] = 2'b00;
VAR252 = VAR177[VAR100-1:0];
end else begin VAR259[1:0] = 2'b01;
VAR252 = VAR260[VAR100-1:0];
if((VAR75 == 2'd1) || (VAR75 == 2'd3))begin
VAR252[2] = 'b0;
VAR252[6] = 'b0;
end
end
end
default: begin
VAR259 = {VAR37{1'VAR181}};
VAR252 = {VAR100{1'VAR181}};
end
endcase end
end else if ((VAR118 == VAR202) ||
(VAR118 == VAR238) ||
(VAR118 == VAR275)) begin
VAR259 = VAR112[VAR37-1:0];
VAR252[VAR100-1:VAR42] = {VAR100-VAR42{1'b0}};
if (VAR257 == VAR241)
VAR252[VAR42-1:0] = {VAR42{1'b0}};
end
else if (VAR257 >= 9'd0)
VAR252[VAR42-1:0] = VAR88[VAR42-1:0] + VAR273;
end else if ((VAR118 == VAR122) ||
(VAR118 == VAR115) ||
(VAR118 == VAR94)) begin
VAR259 = VAR112[VAR37-1:0];
VAR252[VAR100-1:VAR42] = {VAR100-VAR42{1'b0}};
VAR252[VAR42-1:0] =
{VAR242[VAR42-1:3],VAR130, 3'b000};
VAR252[12] = 1'b1;
end else if ((VAR118 == VAR239) ||
(VAR118 == VAR117)) begin
VAR259 = VAR112[VAR37-1:0];
VAR252 = VAR22[VAR100-1:0];
end else begin
VAR259 = {VAR37{1'VAR181}};
VAR252 = {VAR100{1'VAR181}};
end
end
always @(posedge clk) begin
for (VAR236 = 0; VAR236 < VAR102; VAR236 = VAR236 + 1) begin: VAR171
end
end
endmodule
|
lgpl-3.0
|
GSejas/Aproximate-Arithmetic-Operators
|
src_lib/multlib/KOA_2c_approx.v
| 6,257 |
module MODULE1
(
input wire clk,
input wire rst,
input wire VAR44,
input wire [VAR39-1:0] VAR40,
input wire [VAR39-1:0] VAR11,
output wire [2*VAR39-1:0] VAR26
);
wire [1:0] VAR28;
wire [3:0] VAR7;
assign VAR28 = 2'b00;
assign VAR7 = 4'b0000;
wire [VAR39/2-1:0] VAR18;
wire [VAR39/2:0] VAR33;
wire [VAR39/2-3:0] VAR32;
wire [VAR39/2-4:0] VAR1;
reg [4*(VAR39/2)+2:0] VAR23;
reg [4*(VAR39/2)-1:0] VAR21;
assign VAR18 = {(VAR39/2){1'b0}};
assign VAR33 = {(VAR39/2+1){1'b0}};
assign VAR32 = {(VAR39/2-4){1'b0}}; assign VAR1 = {(VAR39/2-5){1'b0}};
localparam VAR35 = VAR39/2;
generate
case (VAR39%2)
0:begin : VAR8
wire [VAR39/2:0] VAR3;
wire [VAR39/2:0] VAR36;
wire [VAR39-1:0] VAR15;
wire [VAR39-1:0] VAR43;
wire [VAR39+1:0] VAR12;
reg [2*(VAR39/2+2)-1:0] VAR41;
reg [VAR39+1:0] VAR10;
VAR2 #(.VAR39(VAR39/2)) VAR25(
.clk(clk),
.VAR9(VAR40[VAR39-1:VAR39-VAR39/2]),
.VAR34(VAR11[VAR39-1:VAR39-VAR39/2]),
.VAR16(VAR15)
);
VAR2 #(.VAR39(VAR39/2)) VAR45(
.clk(clk),
.VAR9(VAR40[VAR39-VAR39/2-1:0]),
.VAR34(VAR11[VAR39-VAR39/2-1:0]),
.VAR16(VAR43)
);
VAR2 #(.VAR39((VAR39/2)+1)) VAR37 (
.clk(clk),
.VAR9(VAR3),
.VAR34(VAR36),
.VAR16(VAR12)
);
VAR38 #(.VAR20(VAR39/2))
VAR4 (
.VAR24 (1'b0),
.VAR19 (VAR40[((VAR39/2)-1):0] ),
.VAR6 (VAR40[(VAR39-1) -: VAR39/2]),
.VAR31 (VAR3));
VAR38 #(.VAR20(VAR39/2))
VAR5(
.VAR24 (1'b0),
.VAR19 (VAR11[((VAR39/2)-1):0]),
.VAR6 (VAR11[(VAR39-1) -: VAR39/2]),
.VAR31 (VAR36));
always @* begin : VAR30
VAR10 <= (VAR12 - VAR15 - VAR43);
VAR23[4*(VAR39/2):0] <= {VAR32,VAR10,VAR18} + {VAR15,VAR43};
end
VAR13 #(.VAR20(4*(VAR39/2))) VAR29 ( .clk(clk),
.rst(rst),
.VAR27(VAR44),
.VAR17(VAR23[4*(VAR39/2)-1:0]),
.VAR42({VAR26})
);
end
1:begin : VAR22
wire [VAR39/2+1:0] VAR3;
wire [VAR39/2+1:0] VAR36;
wire [2*(VAR39/2)-1:0] VAR15;
wire [2*(VAR39/2+1)-1:0] VAR43;
wire [2*(VAR39/2+2)-1:0] VAR12;
reg [2*(VAR39/2+2)-1:0] VAR41;
reg [VAR39+4-1:0] VAR10;
VAR2 #(.VAR39(VAR39/2)) VAR25(
.clk(clk),
.VAR9(VAR40[VAR39-1:VAR39-VAR39/2]),
.VAR34(VAR11[VAR39-1:VAR39-VAR39/2]),
.VAR16(VAR15)
);
VAR2 #(.VAR39((VAR39/2)+1)) VAR45(
.clk(clk),
.VAR9(VAR40[VAR39-VAR39/2-1:0]),
.VAR34(VAR11[VAR39-VAR39/2-1:0]),
.VAR16(VAR43)
);
VAR2 #(.VAR39(VAR39/2+2)) VAR37 (
.clk(clk),
.VAR9(VAR3),
.VAR34(VAR36),
.VAR16(VAR12)
);
VAR38 #(.VAR20(VAR39/2+1))
VAR4(
.VAR24 (1'b0),
.VAR19 (VAR40[((VAR39/2)-1):0] ),
.VAR6 (VAR40[(VAR39-1) -: VAR39/2]),
.VAR31 (VAR3));
VAR38 #(.VAR20(VAR39/2+1))
VAR5(
.VAR24 (1'b0),
.VAR19 (VAR11[((VAR39/2)-1):0]),
.VAR6 (VAR11[(VAR39-1) -: VAR39/2]),
.VAR31 (VAR36));
always @* begin : VAR14
VAR10 <= (VAR12 - VAR15 - VAR43);
VAR23[4*(VAR39/2)+2:0]<= {VAR1,VAR10,VAR33} + {VAR15,VAR43};
end
VAR13 #(.VAR20(4*(VAR39/2)+2)) VAR29 ( .clk(clk),
.rst(rst),
.VAR27(VAR44),
.VAR17(VAR23[2*VAR39-1:0]),
.VAR42({VAR26})
);
end
endcase
endgenerate
endmodule
|
apache-2.0
|
bangonkali/quartus-sockit
|
soc_system/synthesis/submodules/alt_vipvfr131_prc_core.v
| 11,116 |
module MODULE1
(
VAR23,
reset,
VAR34,
VAR39,
read,
VAR5,
VAR8,
VAR36,
VAR25,
VAR32,
VAR10,
VAR4,
VAR14,
VAR2,
VAR11,
enable,
VAR15,
VAR6,
VAR31,
VAR12,
VAR26,
VAR21,
VAR20
);
parameter VAR13 = 8;
parameter VAR42 = 3;
parameter VAR43 = 7;
parameter VAR18 = 32;
localparam VAR29 = 32; localparam VAR30 = 3;
input VAR23;
input reset;
output VAR34;
input VAR39;
output reg read;
input [VAR13 * VAR42 - 1:0] VAR5;
output reg VAR8;
output reg VAR25; output reg [VAR43-1:0] VAR36;
output reg [VAR29-1:0] VAR32;
input VAR10;
output VAR4;
output [VAR13 * VAR42 - 1:0] VAR14;
output VAR2;
output VAR11;
input enable; output reg VAR15; output VAR6; output reg VAR31; input [VAR29-1:0] VAR12;
input [3:0] VAR26;
input [VAR18-1:0] VAR21;
input [VAR43-1:0] VAR20;
reg [VAR30-1:0] VAR41;
reg [VAR13 * VAR42 - 1 : 0] VAR7;
reg VAR22;
reg VAR27;
reg [VAR13 * VAR42 - 1:0] VAR17;
reg VAR24;
reg VAR28;
reg VAR16;
reg [VAR18-1:0] VAR37;
reg [VAR18-1:0] VAR38;
wire VAR3;
assign VAR3 = (VAR38 == VAR37-1);
localparam VAR40 = 0;
localparam VAR1 = 1;
localparam VAR35 = 2;
localparam VAR19 = 3;
reg [1:0] state;
reg VAR33;
integer VAR9;
always @(posedge VAR23 or posedge reset)
if (reset) begin
state <= VAR40;
VAR33 <= 1'b0;
VAR15 <= 1'b1;
VAR25 <= 1'b0;
VAR24 <= 1'b0;
VAR28 <= 1'b0;
VAR16 <= 1'b0;
VAR31 <= 1'b0;
VAR41 <= {VAR30{1'b0}};
VAR8 <= 1'b0;
read <= 1'b0;
VAR38 <= {VAR18{1'b0}};
end
else begin
VAR38 <= read & VAR39 & ~VAR3 ? VAR38 + 1'b1 : VAR38;
if(VAR39) begin
VAR41[VAR30-1] <= (read);
for(VAR9=0;VAR9<VAR30-1;VAR9=VAR9+1) begin
VAR41[VAR9] <= VAR41[VAR9+1];
end
end
case (state)
VAR40 : begin
VAR38 <= {VAR18{1'b0}};
if( VAR39 & VAR8) begin
VAR8 <= 0;
end
VAR15 <= 1'b0;
if (VAR16 & VAR39) begin
VAR16 <= 1'b0;
end
VAR31 <= 1'b0;
if (enable & !VAR8) begin
VAR15 <= 1'b1;
VAR33 <= 1'b1;
VAR25 <= 1'b1;
VAR32 <= VAR12;
VAR36 <= VAR20;
VAR37 <= VAR21;
VAR24 <= 1'b1;
VAR28 <= 1'b1;
VAR17 <= VAR26;
state <= VAR1;
end else begin
VAR33 <= 1'b0;
state <= VAR40;
VAR25 <= 1'b0;
VAR24 <= 1'b0;
VAR28 <= 1'b0;
end
end
VAR1 : begin
VAR15 <= 1'b0;
if (VAR25 & VAR39) begin
VAR25 <= 1'b0;
end
if(VAR39) begin
VAR24 <= 1'b0;
VAR28 <= 1'b0;
state <= VAR35;
end
end
VAR35 : begin
if(VAR39) begin
VAR24 <= VAR41[0];
end
if ((VAR25 & VAR39) | !VAR25 & !VAR3) begin
VAR25 <= 1'b0;
read <= 1'b1;
end
if (VAR3 & VAR39) begin
read <= 1'b0;
end
VAR17 <= VAR39 ? VAR5 : VAR17;
if(VAR41==1 & VAR3 & VAR39) begin
VAR8 <= 1;
VAR16 <= 1'b1;
state <= VAR19;
end else begin
state <= VAR35;
VAR16 <= 1'b0;
end
end
VAR19 : begin VAR24 <= 1'b1;
if( VAR39 & VAR8) begin
VAR8 <= 0;
end
if(VAR39) begin
VAR33 <= 1'b0;
VAR31 <= 1'b1;
VAR16 <= 1'b0;
state <= VAR40;
VAR24 <= 1'b0;
end
end
endcase
end
assign VAR6 = ~VAR33;
assign VAR34 = !VAR10;
assign VAR4 = VAR24 & VAR39;
assign VAR14 = VAR4 ? VAR17 : VAR7;
assign VAR11 = VAR4 ? VAR16 : VAR27;
assign VAR2 = VAR4 ? VAR28 : VAR22;
always @(posedge VAR23 or posedge reset)
if (reset) begin
VAR7 <= {(VAR13 * VAR42){1'b0}};
VAR22 <= 1'b0;
VAR27 <= 1'b0;
end
else begin
VAR7 <= VAR14;
VAR22 <= VAR2;
VAR27 <= VAR11;
end
endmodule
|
mit
|
walkthetalk/fsref
|
ip/fsa/src/include/fsa_detect_edge.v
| 12,488 |
module MODULE1 #(
parameter integer VAR103 = 8,
parameter integer VAR100 = 12,
parameter integer VAR46 = 12,
parameter integer VAR67 = 4,
parameter integer VAR68 = 12 )(
input clk,
input VAR93,
input wire VAR79 ,
input wire VAR56 ,
input wire VAR57 ,
input wire VAR66 ,
input wire VAR99 ,
input wire VAR62 ,
input wire VAR50 ,
input wire VAR88 ,
input wire [VAR68-1:0] VAR94 ,
input wire VAR101,
input wire [VAR100-1:0] VAR78,
input wire [VAR100-1:0] VAR41,
input wire VAR14,
input wire [VAR100-1:0] VAR32,
input wire [VAR100-1:0] VAR21,
output wire VAR3,
output reg VAR38 ,
output reg [VAR46-1:0] VAR6 ,
output reg VAR96,
output reg [VAR46-1:0] VAR72 ,
output reg [VAR46-1:0] VAR95 ,
output reg VAR25,
output reg [VAR46-1:0] VAR109,
output reg [VAR100-1:0] VAR24,
output reg [VAR46-1:0] VAR1,
output reg [VAR100-1:0] VAR34,
output reg VAR18 ,
output reg [VAR46-1:0] VAR98 ,
output reg VAR82 ,
output reg [VAR46-1:0] VAR105 ,
output reg [VAR46-1:0] VAR40 ,
output reg VAR13 ,
output reg [VAR46-1:0] VAR76 ,
output reg [VAR100-1:0] VAR23 ,
output reg [VAR46-1:0] VAR8 ,
output reg [VAR100-1:0] VAR51 ,
output reg VAR85,
output reg [VAR46-1:0] VAR74 ,
output reg [VAR46-1:0] VAR73 ,
output reg VAR10 ,
output reg [VAR46-1:0] VAR70 ,
output reg [VAR46-1:0] VAR112
);
reg VAR15;
always @ (posedge clk) begin
if (VAR93 == 1'b0)
VAR15 <= 0;
end
else
VAR15 <= VAR79;
end
reg VAR16;
reg VAR75;
reg VAR58;
reg VAR91;
reg VAR27;
reg VAR107;
reg [VAR46-1:0] VAR19;
always @ (posedge clk) begin
if (VAR93 == 1'b0) begin
VAR16 <= 1'b0;
VAR75 <= 1'b0;
VAR58 <= 1'b0;
VAR91 <= 1'b0;
VAR27 <= 1'b0;
VAR107 <= 1'b0;
VAR19 <= 0;
end
else begin
VAR16 <= VAR56;
VAR75 <= VAR57;
VAR58 <= VAR66;
VAR91 <= VAR62;
VAR27 <= VAR50;
VAR107 <= VAR88;
VAR19 <= VAR94;
end
end
reg VAR53;
reg VAR5;
reg[VAR46-1:0] VAR28;
reg VAR52;
reg VAR63;
reg[VAR46-1:0] VAR35;
always @ (posedge clk) begin
if (VAR93 == 1'b0 || VAR99 == 1'b1) begin
VAR53 <= 0;
VAR5 <= 0;
VAR28 <= 0;
end
else if (VAR56 && VAR66) begin
if (~VAR53 && VAR101)
VAR28 <= VAR94;
if (~VAR101)
VAR53 <= 1;
if (VAR50 && VAR101)
VAR5 <= 1;
end
end
always @ (posedge clk) begin
if (VAR93 == 1'b0 || VAR99 == 1'b1) begin
VAR52 <= 0;
VAR63 <= 0;
VAR35 <= 0;
end
else if (VAR56 && VAR66) begin
VAR52 <= VAR101;
if (~VAR52)
VAR35 <= VAR94;
if (VAR88 && VAR101)
VAR63 <= 1'b1;
end
end
wire VAR7;
wire [VAR100-1:0] VAR43;
wire [VAR100-1:0] VAR11;
wire VAR90;
wire [VAR46-1:0] VAR97;
wire [VAR46-1:0] VAR29;
wire VAR31;
wire [VAR46-1:0] VAR55;
wire [VAR46-1:0] VAR71;
VAR69 # (
.VAR100(VAR100),
.VAR46(VAR46)
) VAR22 (
.clk(clk),
.VAR93(VAR93),
.VAR56 (VAR56 ),
.VAR66 (VAR66 ),
.VAR50 (VAR50 ),
.VAR88 (VAR88 ),
.VAR16 (VAR16 ),
.VAR89 (VAR91 ),
.VAR75 (VAR75 ),
.VAR58 (VAR58 ),
.VAR19 (VAR19 ),
.VAR28 (VAR28 ),
.VAR35 (VAR35 ),
.VAR20 (VAR101 ),
.VAR80 (VAR78 ),
.VAR12 (VAR41 ),
.VAR102 (VAR7 ),
.VAR59 (VAR43 ),
.VAR83 (VAR11 ),
.VAR4(VAR90),
.VAR33 (VAR97 ),
.VAR30 (VAR29 ),
.VAR92 (VAR31 ),
.VAR65 (VAR55 ),
.VAR37 (VAR71 )
);
wire VAR87;
wire [VAR46-1:0] VAR2;
wire [VAR46-1:0] VAR48;
wire VAR9;
wire [VAR46-1:0] VAR108;
wire [VAR46-1:0] VAR49;
VAR69 # (
.VAR100(VAR100),
.VAR46(VAR46)
) VAR26 (
.clk(clk),
.VAR93(VAR93),
.VAR56 (VAR56 ),
.VAR66 (VAR66 ),
.VAR50 (VAR50 ),
.VAR88 (VAR88 ),
.VAR16 (VAR16 ),
.VAR89 (VAR91 ),
.VAR75 (VAR75 ),
.VAR58 (VAR58 ),
.VAR19 (VAR19 ),
.VAR28 (VAR28 ),
.VAR35 (VAR35 ),
.VAR20 (VAR14 ),
.VAR80 (VAR32 ),
.VAR12 (VAR21 ),
.VAR102 (),
.VAR59 (),
.VAR83 (),
.VAR4(VAR87),
.VAR33 (VAR2 ),
.VAR30 (VAR48 ),
.VAR92 (VAR9 ),
.VAR65 (VAR108 ),
.VAR37 (VAR49 )
);
reg VAR81 ;
reg VAR39 ;
reg VAR47;
reg [VAR100-1:0] VAR36;
reg [VAR46-1:0] VAR84;
reg [VAR100-1:0] VAR44;
reg [VAR46-1:0] VAR64;
always @ (posedge clk) begin
if (VAR93 == 1'b0 || VAR75 == 1'b1) begin
VAR81 <= 0;
VAR39 <= 0;
VAR47 <= 1'b0;
VAR36 <= 0;
VAR44 <= 0;
VAR84 <= 0;
VAR64 <= 0;
end
else if (VAR16 && VAR91) begin
VAR81 <= (VAR19 + 1 == VAR97);
if (VAR81)
VAR39 <= 1'b1;
if (~VAR7) begin
VAR47 <= VAR90;
end
if (~VAR47 && VAR7) begin
if (VAR81) begin
VAR84 <= VAR19;
VAR36 <= VAR43;
VAR64 <= VAR19;
VAR44 <= VAR11;
end
else if (VAR39) begin
if (VAR43 <= VAR36) begin
VAR84 <= VAR19;
VAR36 <= VAR43;
end
if (VAR11 >= VAR44) begin
VAR64 <= VAR19;
VAR44 <= VAR11;
end
end
end
end
end
reg VAR17 ;
reg VAR45;
reg [VAR100-1:0] VAR42;
reg [VAR46-1:0] VAR77;
reg [VAR100-1:0] VAR54;
reg [VAR46-1:0] VAR86;
always @ (posedge clk) begin
if (VAR93 == 1'b0 || VAR91 == 1'b0) begin
VAR17 <= 1'b0;
VAR45 <= 1'b0;
VAR42 <= 0;
VAR54 <= 0;
VAR77 <= 0;
VAR86 <= 0;
end
else if (VAR16) begin
if (VAR19 == VAR55)
VAR17 <= 1'b1;
VAR45 <= VAR7 && VAR31;
if (~VAR45) begin
VAR77 <= VAR19;
VAR42 <= VAR43;
VAR86 <= VAR19;
VAR54 <= VAR11;
end
else if (~VAR17) begin
if (VAR43 < VAR42) begin
VAR77 <= VAR19;
VAR42 <= VAR43;
end
if (VAR11 > VAR54) begin
VAR86 <= VAR19;
VAR54 <= VAR11;
end
end
end
end
reg VAR61;
always @ (posedge clk) begin
if (VAR93 == 1'b0)
VAR61 <= 0;
end
else
VAR61 <= VAR15;
end
reg VAR110;
reg[VAR46-1:0] VAR60;
reg VAR106;
reg[VAR46-1:0] VAR104;
always @ (posedge clk) begin
if (VAR93 == 1'b0) begin
VAR110 <= 0;
VAR60 <= 0;
VAR106 <= 0;
VAR104 <= 0;
end
else begin
VAR110 <= VAR5 ;
VAR60 <= VAR28 ;
VAR106 <= VAR63 ;
VAR104 <= VAR35 ;
end
end
reg VAR111;
always @ (posedge clk) begin
if (VAR93 == 1'b0)
VAR111 <= 0;
end
else
VAR111 <= VAR61;
end
assign VAR3 = VAR111;
always @ (posedge clk) begin
if (VAR93 == 1'b0) begin
VAR6 <= 0;
VAR38 <= 0;
VAR98 <= 0;
VAR18 <= 0;
VAR109 <= 0;
VAR24 <= 0;
VAR1 <= 0;
VAR34 <= 0;
VAR76 <= 0;
VAR23 <= 0;
VAR8 <= 0;
VAR51 <= 0;
VAR96 <= 0;
VAR72 <= 0;
VAR95 <= 0;
VAR82 <= 0;
VAR105 <= 0;
VAR40 <= 0;
VAR85 <= 0;
VAR74 <= 0;
VAR73 <= 0;
VAR10 <= 0;
VAR70 <= 0;
VAR112 <= 0;
end
else if (VAR61) begin
VAR6 <= VAR60 ;
VAR38 <= VAR110;
VAR98 <= VAR104 ;
VAR18 <= VAR106 ;
VAR96 <= VAR90 ;
VAR72 <= VAR97 ;
VAR95 <= VAR29 ;
VAR25 <= VAR47 ;
VAR109 <= VAR84 ;
VAR24 <= VAR36 ;
VAR1 <= VAR64 ;
VAR34 <= VAR44 ;
VAR82 <= VAR31 ;
VAR105 <= VAR55 ;
VAR40 <= VAR71 ;
VAR13 <= VAR45 ;
VAR76 <= VAR77 ;
VAR23 <= VAR42 ;
VAR8 <= VAR86 ;
VAR51 <= VAR54 ;
VAR85 <= VAR87 ;
VAR74 <= VAR2 ;
VAR73 <= VAR48 ;
VAR10 <= VAR9 ;
VAR70 <= VAR108 ;
VAR112 <= VAR49 ;
end
end
endmodule
|
gpl-3.0
|
mda-ut/AquaTux
|
fpga/fpga_hw/top_level/RS232/Altera_UP_RS232_In_Deserializer.v
| 4,788 |
module MODULE1 (
clk,
reset,
VAR9,
VAR31,
VAR16,
VAR4
);
parameter VAR17 = 9;
parameter VAR22 = 9'd1;
parameter VAR18 = 9'd433;
parameter VAR15 = 9'd216;
parameter VAR14 = 11;
parameter VAR12 = 9;
input clk;
input reset;
input VAR9;
input VAR31;
output reg [7:0] VAR16;
output [(VAR12 - 1):0] VAR4;
wire VAR1;
wire VAR8;
wire VAR23;
wire VAR13;
wire [6:0] VAR5;
reg VAR25;
reg [(VAR14 - 1):0] VAR20;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR16 <= 8'h00;
end
else
VAR16 <= {VAR13, VAR5};
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR25 <= 1'b0;
end
else if (VAR8 == 1'b1)
VAR25 <= 1'b0;
else if (VAR9 == 1'b0)
VAR25 <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR20 <= {VAR14{1'b0}};
end
else if (VAR1)
VAR20 <=
{VAR9, VAR20[(VAR14 - 1):1]};
end
VAR2 VAR24 (
.clk (clk),
.reset (reset),
.VAR28 (~VAR25),
.VAR26 (),
.VAR30 (VAR1),
.VAR29 (VAR8)
);
VAR24.VAR17 = VAR17,
VAR24.VAR22 = VAR22,
VAR24.VAR18 = VAR18,
VAR24.VAR15 = VAR15,
VAR24.VAR14 = VAR14;
VAR10 VAR3 (
.clk (clk),
.reset (reset),
.VAR7 (VAR8 & ~VAR13),
.VAR19 (VAR20[(VAR12 + 1):1]),
.VAR11 (VAR31 & ~VAR23),
.VAR23 (VAR23),
.VAR13 (VAR13),
.VAR27 (VAR5),
.VAR21 (VAR4)
);
VAR3.VAR12 = VAR12,
VAR3.VAR32 = 128,
VAR3.VAR6 = 7;
endmodule
|
gpl-2.0
|
kyflores/ice-mc
|
rtl/spi_comm_top.v
| 1,174 |
module MODULE1(VAR12, reset, VAR21, VAR29, VAR30, VAR26, VAR7,
VAR4, VAR2, VAR11, VAR8, VAR16, VAR25, VAR5, VAR20);
input VAR12;
input reset;
output VAR21;
output VAR4, VAR2, VAR11, VAR8, VAR16, VAR25, VAR5, VAR20;
input VAR29;
output VAR30;
output VAR26;
output VAR7;
wire VAR24, VAR28, VAR15;
wire[7:0] VAR18, VAR1;
VAR27 #(.VAR10(16)) VAR23(
.clk(VAR12),
.rst(reset),
.VAR29(VAR29),
.VAR30(VAR30),
.VAR26(VAR26),
.VAR22(VAR24),
.VAR19(VAR18),
.VAR3(VAR1),
.VAR28(VAR28),
.VAR15(VAR15)
);
VAR17 #(.VAR14(2)) VAR13(
.clk(VAR12),
.rst(reset),
.VAR22(VAR22),
.VAR28(VAR28),
.VAR15(VAR15),
.VAR9(VAR18),
.VAR6(VAR1),
.VAR24(VAR24),
.VAR21(VAR21),
.VAR7(VAR7)
);
assign VAR4 = VAR1[0];
assign VAR2 = VAR1[1];
assign VAR11 = VAR1[2];
assign VAR8 = VAR1[3];
assign VAR16 = VAR1[4];
assign VAR25 = VAR1[5];
assign VAR5 = VAR1[6];
assign VAR20 = VAR1[7];
endmodule
|
mit
|
litex-hub/pythondata-cpu-blackparrot
|
pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
| 2,859 |
module MODULE1
, parameter VAR12(VAR14)
, parameter VAR16=0
, parameter VAR36=VAR28(VAR14)
)
(input VAR3
, input VAR33
, input [VAR5(VAR15, 1):0] VAR26
, input [VAR36-1:0] VAR25
, input VAR21
, input [VAR5(VAR15, 1):0] VAR11
, input VAR8
, output logic [VAR5(VAR15, 1):0] VAR29
);
wire VAR2 = VAR33;
if (VAR15 == 0)
begin: VAR35
wire VAR20 = &{VAR3, VAR26, VAR25, VAR21, VAR11, VAR8};
assign VAR29 = '0;
end
else
begin: VAR4
logic [VAR36-1:0] VAR34;
logic [VAR15-1:0] VAR10 [VAR14-1:0];
logic VAR1;
assign VAR1 = VAR21 & ~VAR8;
VAR30 @(posedge VAR3)
if (VAR1)
VAR34 <= VAR25;
end
else
VAR34 <= 'VAR6;
logic [VAR15-1:0] VAR24;
assign VAR24 = VAR10[VAR34];
if (VAR16)
begin: VAR18
logic VAR27;
VAR17 #(
.VAR15(1)
) VAR19 (
.VAR3(VAR3)
,.VAR26(VAR1)
,.VAR29(VAR27)
);
VAR9 #(
.VAR15(VAR15)
) VAR13 (
.VAR3(VAR3)
,.VAR7(VAR27)
,.VAR26(VAR24)
,.VAR29(VAR29)
);
end
else
begin: VAR22
assign VAR29 = VAR24;
end
logic [VAR15-1:0] VAR31;
for (genvar VAR32 = 0; VAR32 < VAR15; VAR32++)
begin : VAR23
assign VAR31[VAR32] = VAR11[VAR32] ? VAR26[VAR32] : VAR10[VAR25][VAR32];
end
VAR30 @(posedge VAR3)
if (VAR21 & VAR8)
VAR10[VAR25] <= VAR31;
VAR30 @(posedge VAR3)
if (VAR21 & VAR8)
for (integer VAR32 = 0; VAR32 < VAR15; VAR32=VAR32+1)
if (VAR11[VAR32])
VAR10[VAR25][VAR32] <= VAR26[VAR32];
end
endmodule
|
bsd-3-clause
|
parallella/oh
|
common/dv/dut_clockdiv.v
| 1,182 |
module MODULE1(
VAR13, VAR4, VAR1, VAR6, VAR17,
VAR10, VAR11, VAR7, VAR9, VAR3, VAR14, VAR8, VAR12
);
parameter VAR2 = 1;
parameter VAR16 = 104;
input VAR10;
input VAR11;
input VAR7;
input [VAR2*VAR2-1:0] VAR9;
input VAR3;
output VAR13;
output VAR4;
input [VAR2-1:0] VAR14;
input [VAR2*VAR16-1:0] VAR8;
output [VAR2-1:0] VAR1;
output [VAR2-1:0] VAR6;
output [VAR2*VAR16-1:0] VAR17;
input [VAR2-1:0] VAR12;
assign VAR13 = 1'b1;
assign VAR1 = 1'b0;
assign clk = VAR10;
VAR5 VAR5 (.VAR4 (VAR4),
.VAR18 (VAR18),
.clk (clk),
.VAR7 (VAR7),
.en (1'b1),
.VAR15 (VAR8[11:8])
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.pp.blackbox.v
| 1,474 |
module MODULE1 (
VAR8 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR6,
VAR3 ,
VAR9 ,
VAR2 ,
VAR5
);
output VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR6;
input VAR3 ;
input VAR9 ;
input VAR2 ;
input VAR5 ;
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.functional.v
| 1,557 |
module MODULE1( VAR1, VAR15, VAR16, VAR17 );
input VAR15, VAR1, VAR16;
output VAR17;
wire VAR3;
and VAR11( VAR3, VAR15, VAR1, VAR16 );
wire VAR12;
not VAR14( VAR12, VAR1 );
wire VAR7;
not VAR10( VAR7, VAR16 );
wire VAR13;
and VAR9( VAR13, VAR12, VAR7, VAR15 );
wire VAR19;
not VAR18( VAR19, VAR15 );
wire VAR6;
and VAR5( VAR6, VAR19, VAR7, VAR1 );
wire VAR2;
and VAR4( VAR2, VAR19, VAR12, VAR16 );
or VAR8( VAR17, VAR3, VAR13, VAR6, VAR2 );
endmodule
|
apache-2.0
|
vipinkmenon/scas
|
hw/fpga/source/enet_if/v7_ethernet_top.v
| 4,668 |
module MODULE1
(
input VAR7,
input VAR58,
output VAR48,
input VAR52, input VAR50, output VAR55, output VAR1, input VAR37, input VAR24,
output VAR44,
output VAR35,
input VAR62,
output VAR61,
output VAR18,
output VAR40,
input VAR14, input VAR10, input [31:0] VAR32, input [31:0] VAR57, input [31:0] VAR28, input [31:0] VAR9, output [31:0] VAR20, output [31:0] VAR26, output VAR21, output VAR46,
output VAR15,
output VAR33,
output [255:0] VAR25,
output [31:0] VAR31,
output [31:0] VAR30,
output [31:0] VAR53,
input [255:0] VAR16,
input VAR11,
input VAR42,
input VAR34
);
wire [63:0] VAR2;
wire [63:0] VAR45;
VAR29 VAR56
(
.VAR7(VAR7),
.VAR49(VAR58),
.VAR48(VAR48),
.VAR52(VAR52),
.VAR50(VAR50),
.VAR55(VAR55),
.VAR1(VAR1),
.VAR37(VAR37),
.VAR24(VAR24),
.VAR44(VAR44),
.VAR35(VAR35),
.VAR62(VAR62),
.VAR18(VAR18),
.VAR61(VAR61),
.VAR40(VAR40),
.VAR39(VAR10),
.VAR47(VAR58),
.VAR51(VAR51),
.VAR2(VAR2),
.VAR43(VAR43),
.VAR63(VAR58),
.VAR12(VAR12),
.VAR45(VAR45),
.VAR38(VAR38),
.VAR23(VAR22),
.VAR59(VAR54)
);
VAR6 VAR8 (
.VAR5(VAR58),
.VAR27(VAR7),
.VAR14(VAR14),
.VAR32(VAR32),
.VAR57(VAR57),
.VAR28(VAR28),
.VAR9(VAR9),
.VAR19(VAR22),
.VAR3(VAR38),
.VAR20(VAR20),
.VAR26(VAR26),
.VAR21(VAR21),
.VAR46(VAR46),
.VAR13(VAR12),
.VAR41(VAR45),
.VAR36(VAR2),
.VAR60(VAR51),
.VAR4(VAR43),
.VAR15(VAR15),
.VAR33(VAR33),
.VAR25(VAR25),
.VAR31(VAR31),
.VAR30(VAR30),
.VAR53(VAR53),
.VAR16(VAR16),
.VAR11(VAR11),
.VAR42(VAR42),
.VAR34(VAR34),
.VAR17(VAR54)
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/nor4b/sky130_fd_sc_hd__nor4b.symbol.v
| 1,323 |
module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR7 ,
input VAR6,
output VAR4
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR3 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a2111o/sky130_fd_sc_lp__a2111o_4.v
| 2,448 |
module MODULE2 (
VAR11 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR12 ,
VAR5 ,
VAR1,
VAR7,
VAR10 ,
VAR2
);
output VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR12 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR10 ;
input VAR2 ;
VAR3 VAR6 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR11 ,
VAR9,
VAR8,
VAR4,
VAR12,
VAR5
);
output VAR11 ;
input VAR9;
input VAR8;
input VAR4;
input VAR12;
input VAR5;
supply1 VAR1;
supply0 VAR7;
supply1 VAR10 ;
supply0 VAR2 ;
VAR3 VAR6 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlxtn/sky130_fd_sc_lp__dlxtn.functional.v
| 1,697 |
module MODULE1 (
VAR7 ,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR3 ;
input VAR2;
wire VAR10 ;
wire VAR12 ;
wire VAR8;
wire VAR9 ;
VAR5 VAR1 VAR11 (VAR12 , VAR3, VAR10 );
not VAR6 (VAR10 , VAR2 );
buf VAR4 (VAR7 , VAR12 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/einvn/sky130_fd_sc_lp__einvn_1.v
| 2,150 |
module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR3,
VAR9,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR9;
input VAR7 ;
input VAR4 ;
VAR5 VAR6 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR2 ,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR8 ;
input VAR1;
supply1 VAR3;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR4 ;
VAR5 VAR6 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dlrbn/sky130_fd_sc_hd__dlrbn_1.v
| 2,480 |
module MODULE2 (
VAR11 ,
VAR3 ,
VAR9,
VAR10 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR8
);
output VAR11 ;
output VAR3 ;
input VAR9;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR8 ;
VAR5 VAR1 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR11 ,
VAR3 ,
VAR9,
VAR10 ,
VAR6
);
output VAR11 ;
output VAR3 ;
input VAR9;
input VAR10 ;
input VAR6 ;
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR8 ;
VAR5 VAR1 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
tmatsuya/milkymist-ml401
|
cores/vgafb/rtl/vgafb.v
| 4,963 |
module MODULE1 #(
parameter VAR68 = 4'h0,
parameter VAR10 = 26
) (
input VAR19,
input VAR12,
input [13:0] VAR5,
input VAR13,
input [31:0] VAR7,
output [31:0] VAR15,
output [VAR10-1:0] VAR20,
output VAR33,
input VAR66,
input [63:0] VAR14,
output VAR23,
output [VAR10-1:0] VAR8,
input [63:0] VAR41,
input VAR26,
input VAR61,
output VAR60,
output reg VAR16,
output reg VAR46,
output VAR37,
output VAR3,
output reg [7:0] VAR59,
output reg [7:0] VAR54,
output reg [7:0] VAR36,
output [1:0] VAR67
);
wire VAR27;
wire [10:0] VAR1;
wire [10:0] VAR45;
wire [10:0] VAR56;
wire [10:0] VAR48;
wire [10:0] VAR39;
wire [10:0] VAR50;
wire [10:0] VAR32;
wire [10:0] VAR69;
wire [VAR10-1:0] VAR52;
wire VAR42;
wire [17:0] VAR65;
VAR35 #(
.VAR68(VAR68),
.VAR10(VAR10)
) VAR29 (
.VAR19(VAR19),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR13(VAR13),
.VAR7(VAR7),
.VAR15(VAR15),
.VAR27(VAR27),
.VAR1(VAR1),
.VAR45(VAR45),
.VAR56(VAR56),
.VAR48(VAR48),
.VAR39(VAR39),
.VAR50(VAR50),
.VAR32(VAR32),
.VAR69(VAR69),
.VAR52(VAR52),
.VAR42(VAR42),
.VAR65(VAR65),
.VAR67(VAR67)
);
reg VAR22;
reg VAR47;
wire VAR34;
wire [15:0] VAR2;
wire VAR38;
wire [15:0] VAR63;
wire VAR51;
reg VAR49;
reg VAR57;
wire VAR44 = VAR49 & VAR57;
assign VAR63 = VAR44 ? VAR2 : 16'h0000;
wire VAR24;
reg [10:0] VAR4;
reg [10:0] VAR28;
always @(posedge VAR19) begin
if(VAR27) begin
VAR4 <= 10'd0;
VAR28 <= 10'd0;
VAR49 <= 1'b0;
VAR22 <= 1'b1;
VAR57 <= 1'b0;
VAR47 <= 1'b1;
end else begin
if(VAR24) begin
VAR4 <= VAR4 + 10'd1;
if(VAR4 == 10'd0) VAR49 <= 1'b1;
if(VAR4 == VAR1) VAR49 <= 1'b0;
if(VAR4 == VAR45) VAR22 <= 1'b0;
if(VAR4 == VAR56) VAR22 <= 1'b1;
if(VAR4 == VAR48) begin
VAR4 <= 10'd0;
if(VAR28 == VAR69)
VAR28 <= 10'd0;
end
else
VAR28 <= VAR28 + 10'd1;
end
if(VAR28 == 10'd0) VAR57 <= 1'b1;
if(VAR28 == VAR39) VAR57 <= 1'b0;
if(VAR28 == VAR50) VAR47 <= 1'b0;
if(VAR28 == VAR32) VAR47 <= 1'b1;
end
end
end
assign VAR24 = ~VAR51 & (~VAR44 | VAR34);
assign VAR38 = ~VAR51 & VAR44 & VAR34;
VAR21 #(
.VAR10(VAR10)
) VAR30 (
.VAR19(VAR19),
.VAR12(VAR12),
.VAR27(VAR27),
.VAR65(VAR65),
.VAR52(VAR52),
.VAR42(VAR42),
.VAR20(VAR20),
.VAR33(VAR33),
.VAR66(VAR66),
.VAR14(VAR14),
.VAR23(VAR23),
.VAR8(VAR8),
.VAR41(VAR41),
.VAR26(VAR26),
.VAR34(VAR34),
.VAR63(VAR2),
.VAR38(VAR38)
);
wire [17:0] VAR25;
VAR55 #(
.VAR40(18),
.VAR58(6)
) VAR6 (
.VAR11(VAR25),
.VAR18(),
.VAR9(1'b1),
.VAR43(VAR61),
.VAR62({VAR47, VAR22, VAR63}),
.VAR17(VAR51),
.VAR64(VAR24),
.VAR31(VAR19),
.VAR53(VAR27)
);
assign VAR37 = 1'b0;
assign VAR60 = 1'b1;
assign VAR3 = 1'b1;
always @(posedge VAR61) begin
VAR46 <= VAR25[17];
VAR16 <= VAR25[16];
VAR59 <= {VAR25[15:11], VAR25[15:13]};
VAR54 <= {VAR25[10:5], VAR25[10:9]};
VAR36 <= {VAR25[4:0], VAR25[4:2]};
end
endmodule
|
lgpl-3.0
|
vipinkmenon/fpgadriver
|
src/hw/fpga/source/memory_if/mig_7series_v1_8_memc_ui_top_std.v
| 36,324 |
module MODULE1 #
(
parameter VAR245 = 100,
parameter VAR130 = 64,
parameter VAR186 = "VAR227",
parameter VAR260 = "0", parameter VAR6 = 3, parameter VAR149 = 2, parameter VAR135 = "8", parameter VAR99 = "VAR156", parameter VAR175 = "VAR185", parameter VAR268 = 1, parameter VAR67 = 5,
parameter VAR205 = 12, parameter VAR32 = "VAR119", parameter VAR154 = 1, parameter VAR207 = 1, parameter VAR152 = 5,
parameter VAR174 = 64,
parameter VAR122 = 5,
parameter VAR60 = 1,
parameter VAR153 = "VAR281", parameter VAR226 = 8, parameter VAR17 = 6, parameter VAR204 = 64, parameter VAR177 = 3, parameter VAR145 = 8, parameter VAR61 = "VAR229",
parameter VAR88 = 8, parameter VAR101 = "VAR185",
parameter VAR34 = 8,
parameter VAR89 = "VAR185",
parameter VAR139 = 31,
parameter VAR80 = 0, parameter VAR300 = 0, parameter VAR158 = 4,
parameter VAR146 = 2, parameter VAR157 = 1, parameter VAR184 = "VAR138",
parameter VAR12 = "VAR185",
parameter VAR265 = "VAR119",
parameter VAR303 = "VAR242", parameter VAR36 = "VAR110", parameter VAR108 = "VAR119", parameter VAR160 = "VAR15",
parameter VAR213 = "VAR155",
parameter VAR72 = "VAR185",
parameter VAR248 = "60",
parameter VAR124 = "120",
parameter VAR287 = 2,
parameter VAR275 = 2500, parameter VAR10 = 10000, parameter VAR296 = 40000, parameter VAR257 = 1000000, parameter VAR136 = 37500, parameter VAR294 = 12500, parameter VAR273 = 7800000, parameter VAR116 = 110000, parameter VAR220 = 12500, parameter VAR91 = 10000, parameter VAR42 = 7500, parameter VAR270 = 7500, parameter VAR295 = 128000000, parameter VAR200 = 64, parameter VAR256 = "VAR185", parameter VAR297 = "VAR119", parameter VAR13 = "VAR185",
parameter VAR173 = "VAR185",
parameter VAR26 = "VAR202",
parameter VAR68 = 1,
parameter VAR3 = 4,
parameter VAR280 = 1,
parameter VAR239 = 16, parameter VAR9 = 32,
parameter VAR7 = 8,
parameter VAR147 = 64,
parameter [3:0] VAR289 = 4'hF,
parameter [3:0] VAR236 = 4'hF,
parameter [3:0] VAR143 = 4'hF,
parameter [3:0] VAR292 = 4'hF,
parameter [3:0] VAR5 = 4'hF,
parameter [3:0] VAR82 = 4'hc,
parameter [3:0] VAR123 = 4'hf,
parameter [3:0] VAR71 = 4'hf,
parameter [3:0] VAR44 = 4'h0,
parameter [3:0] VAR183 = 4'h0,
parameter [47:0] VAR165 = 48'h000000000000,
parameter [47:0] VAR194 = 48'h000000000000,
parameter [47:0] VAR70 = 48'h000000000000,
parameter [143:0] VAR269
= 144'h000000000000000000000000000000000000,
parameter [191:0] VAR262
= 192'h000000000000000000000000000000000000000000000000,
parameter [35:0] VAR237 = 36'h000000000,
parameter [11:0] VAR73 = 12'h000,
parameter [7:0] VAR223 = 8'h00,
parameter [95:0] VAR35 = 96'h000000000000000000000000,
parameter [95:0] VAR258 = 96'h000000000000000000000000,
parameter VAR197 = "VAR278",
parameter [119:0] VAR151 = 120'h000000000000000000000000000000,
parameter [11:0] VAR77 = 12'h000,
parameter [11:0] VAR190 = 12'h000,
parameter [11:0] VAR84 = 12'h000,
parameter [143:0] VAR29
= 144'h000000000000000000000000000000000000,
parameter [95:0] VAR304 = 96'h000000000000000000000000,
parameter [95:0] VAR148 = 96'h000000000000000000000000,
parameter [95:0] VAR16 = 96'h000000000000000000000000,
parameter [95:0] VAR38 = 96'h000000000000000000000000,
parameter [95:0] VAR46 = 96'h000000000000000000000000,
parameter [95:0] VAR234 = 96'h000000000000000000000000,
parameter [95:0] VAR246 = 96'h000000000000000000000000,
parameter [95:0] VAR168 = 96'h000000000000000000000000,
parameter [95:0] VAR96 = 96'h000000000000000000000000,
parameter [95:0] VAR8 = 96'h000000000000000000000000,
parameter [95:0] VAR52 = 96'h000000000000000000000000,
parameter [95:0] VAR279 = 96'h000000000000000000000000,
parameter [95:0] VAR27 = 96'h000000000000000000000000,
parameter [95:0] VAR120 = 96'h000000000000000000000000,
parameter [95:0] VAR79 = 96'h000000000000000000000000,
parameter [95:0] VAR11 = 96'h000000000000000000000000,
parameter [95:0] VAR14 = 96'h000000000000000000000000,
parameter [95:0] VAR133 = 96'h000000000000000000000000,
parameter [107:0] VAR111 = 108'h000000000000000000000000000,
parameter [107:0] VAR241 = 108'h000000000000000000000000000,
parameter [7:0] VAR85 = 8'b00000001,
parameter [7:0] VAR180 = 8'b00000000,
parameter VAR63 = "VAR230",
parameter [15:0] VAR251 = 16'h0000, parameter [11:0] VAR150 = 12'h000, parameter [2:0] VAR272 = 3'h0, parameter VAR252 = "VAR185",
parameter VAR50 = 300.0,
parameter VAR128 = 1, parameter VAR144 = 1, parameter VAR298 = 1 )
(
input clk,
input VAR102,
input VAR140 ,
input VAR276 ,
input VAR176,
input VAR225 ,
input rst,
inout [VAR204-1:0] VAR109,
inout [VAR145-1:0] VAR20,
inout [VAR145-1:0] VAR250,
output [VAR239-1:0] VAR172,
output [VAR6-1:0] VAR19,
output VAR203,
output [VAR268-1:0] VAR198,
output [VAR268-1:0] VAR291,
output [VAR207-1:0] VAR191,
output [VAR154*VAR157-1:0] VAR193,
output [VAR226-1:0] VAR112,
output [VAR280-1:0] VAR263,
output VAR238,
output VAR115,
output VAR90,
output VAR210,
output [VAR149-1:0] VAR76,
input [VAR9-1:0] VAR211,
input [2:0] VAR286,
input VAR2,
input VAR301,
input [VAR147-1:0] VAR117,
input VAR305,
input [VAR7-1:0] VAR282,
input VAR142,
input VAR83,
input [2*VAR146-1:0] VAR126,
output [2*VAR146-1:0] VAR100,
output [VAR147-1:0] VAR118,
output VAR302,
output VAR293,
output VAR181,
output VAR127,
input VAR216,
output VAR105,
input VAR164,
output VAR33,
input VAR178,
output VAR277,
input [11:0] VAR40,
input VAR187,
input VAR267,
input VAR48,
input VAR299,
input VAR23,
input [VAR177-1:0] VAR189,
output [6*VAR145*VAR3-1:0] VAR1,
output [6*VAR145*VAR3-1:0] VAR131,
output [VAR145-1:0] VAR97,
output [2*VAR146*VAR204-1:0] VAR274,
output [1:0] VAR37,
output [1:0] VAR255,
output [1:0] VAR221,
output [5:0] VAR170,
output VAR41,
output VAR214,
output VAR285,
output VAR259,
output [6*VAR145-1:0] VAR163,
output [3*VAR145-1:0] VAR98,
output VAR25,
input VAR106,
input VAR195,
input [VAR177:0] VAR47,
input VAR235,
input VAR218,
input VAR65,
input VAR54,
input VAR121,
output [6*VAR145*VAR3-1:0] VAR254,
output [5*VAR145*VAR3-1:0] VAR125,
output VAR94,
output [6*VAR145-1:0] VAR132,
output [3*VAR145-1:0] VAR232,
output VAR129,
input VAR4,
output [6*VAR3-1:0] VAR75,
output [255:0] VAR103,
output [255:0] VAR290,
output [255:0] VAR166,
output [99:0] VAR199,
output [255:0] VAR215,
output [255:0] VAR59,
output [255:0] VAR31,
output [5:0] VAR201,
output [8:0] VAR39,
output VAR92,
output VAR249,
output VAR162,
output VAR66,
output VAR55,
output VAR244,
output VAR284,
output VAR167,
output VAR171,
output [11:0] VAR264,
output [11:0] VAR161,
output [6*VAR3-1:0] VAR49,
output [6*VAR3-1:0] VAR95,
output [5:0] VAR217,
output [5:0] VAR21,
output [5:0] VAR58,
output VAR288,
output VAR113,
output [255:0] VAR159,
output [VAR88*16 -1:0] VAR93
);
wire VAR212;
wire [2*VAR146-1:0] VAR266;
wire [2*VAR146-1:0] VAR87;
wire [2*VAR146-1:0] VAR141;
wire [VAR139-1:0] VAR192;
wire [VAR60-1:0] VAR45;
wire VAR78;
wire [VAR122-1:0] VAR222;
wire [VAR60-1:0] VAR188;
wire VAR179;
wire [VAR122-1:0] VAR104;
wire VAR107;
wire VAR169;
wire [2*VAR146*VAR130-1:0] VAR206;
wire VAR233;
wire VAR18;
wire VAR253;
wire [VAR239-1:0] VAR69;
wire [VAR68-1:0] VAR28;
wire VAR57;
wire [VAR122-1:0] VAR56;
wire [VAR205-1:0] VAR64;
wire [2:0] VAR81;
wire [VAR6-1:0] VAR283;
wire [2*VAR146*VAR130-1:0] VAR261;
wire [2*VAR146*VAR174/8-1:0] VAR228;
wire VAR224;
wire VAR62;
wire VAR74;
wire VAR240;
wire VAR196;
wire VAR247;
wire VAR182;
wire VAR137;
wire VAR219;
reg reset;
always @(posedge clk)
VAR271 #
(
.VAR245 (VAR245),
.VAR130 (VAR130),
.VAR186 (VAR186),
.VAR260 (VAR260),
.VAR6 (VAR6),
.VAR149 (VAR149),
.VAR135 (VAR135),
.VAR99 (VAR99),
.VAR175 (VAR175),
.VAR268 (VAR268),
.VAR205 (VAR205),
.VAR32 (VAR32),
.VAR154 (VAR154),
.VAR157 (VAR157),
.VAR207 (VAR207),
.VAR174 (VAR174),
.VAR122 (VAR122),
.VAR80 (VAR80),
.VAR60 (VAR60),
.VAR153 (VAR153),
.VAR226 (VAR226),
.VAR17 (VAR17),
.VAR204 (VAR204),
.VAR177 (VAR177),
.VAR145 (VAR145),
.VAR61 (VAR61),
.VAR88 (VAR88),
.VAR101 (VAR101),
.VAR34 (VAR34),
.VAR139 (VAR139),
.VAR50 (VAR50),
.VAR300 (VAR300),
.VAR158 (VAR158),
.VAR146 (VAR146),
.VAR184 (VAR184),
.VAR213 (VAR213),
.VAR12 (VAR12),
.VAR265 (VAR265),
.VAR303 (VAR303),
.VAR36 (VAR36),
.VAR108 (VAR108),
.VAR160 (VAR160),
.VAR72 (VAR72),
.VAR248 (VAR248),
.VAR124 (VAR124),
.VAR67 (VAR67),
.VAR152 (VAR152),
.VAR275 (VAR275),
.VAR10 (VAR10),
.VAR296 (VAR296),
.VAR257 (VAR257),
.VAR136 (VAR136),
.VAR294 (VAR294),
.VAR273 (VAR273),
.VAR116 (VAR116),
.VAR220 (VAR220),
.VAR91 (VAR91),
.VAR42 (VAR42),
.VAR270 (VAR270),
.VAR295 (VAR295),
.VAR200 (VAR200),
.VAR256 (VAR256),
.VAR297 (VAR297),
.VAR13 (VAR13),
.VAR173 (VAR173),
.VAR26 (VAR26),
.VAR68 (VAR68),
.VAR3 (VAR3),
.VAR280 (VAR280),
.VAR239 (VAR239),
.VAR252 (VAR252),
.VAR289 (VAR289),
.VAR236 (VAR236),
.VAR143 (VAR143),
.VAR292 (VAR292),
.VAR5 (VAR5),
.VAR82 (VAR82),
.VAR123 (VAR123),
.VAR71 (VAR71),
.VAR44 (VAR44),
.VAR183 (VAR183),
.VAR165 (VAR165),
.VAR194 (VAR194),
.VAR70 (VAR70),
.VAR269 (VAR269),
.VAR262 (VAR262),
.VAR237 (VAR237),
.VAR73 (VAR73),
.VAR223 (VAR223),
.VAR35 (VAR35),
.VAR258 (VAR258),
.VAR197 (VAR197),
.VAR151 (VAR151),
.VAR77 (VAR77),
.VAR190 (VAR190),
.VAR84 (VAR84),
.VAR29 (VAR29),
.VAR304 (VAR304),
.VAR148 (VAR148),
.VAR16 (VAR16),
.VAR38 (VAR38),
.VAR46 (VAR46),
.VAR234 (VAR234),
.VAR246 (VAR246),
.VAR168 (VAR168),
.VAR96 (VAR96),
.VAR8 (VAR8),
.VAR52 (VAR52),
.VAR279 (VAR279),
.VAR27 (VAR27),
.VAR120 (VAR120),
.VAR79 (VAR79),
.VAR11 (VAR11),
.VAR14 (VAR14),
.VAR133 (VAR133),
.VAR111 (VAR111),
.VAR241 (VAR241),
.VAR85 (VAR85),
.VAR180 (VAR180),
.VAR251 (VAR251),
.VAR150 (VAR150),
.VAR272 (VAR272),
.VAR287 (VAR287),
.VAR128 (VAR128),
.VAR144 (VAR144),
.VAR298 (VAR298)
)
VAR51
(
.clk (clk),
.VAR102 (VAR102),
.VAR140 (VAR140), .VAR276 (VAR276),
.VAR176 (VAR176),
.VAR225 (VAR225),
.rst (rst),
.VAR137 (VAR137),
.reset (reset),
.VAR182 (VAR182),
.VAR109 (VAR109),
.VAR20 (VAR20),
.VAR250 (VAR250),
.VAR172 (VAR172),
.VAR19 (VAR19),
.VAR203 (VAR203),
.VAR198 (VAR198),
.VAR291 (VAR291),
.VAR191 (VAR191),
.VAR193 (VAR193),
.VAR112 (VAR112),
.VAR263 (VAR263),
.VAR238 (VAR238),
.VAR115 (VAR115),
.VAR90 (VAR90),
.VAR210 (VAR210),
.VAR231 (VAR85),
.VAR53 (VAR180),
.VAR212 (VAR212),
.VAR283 (VAR283),
.VAR81 (VAR81),
.VAR64 (VAR64),
.VAR56 (VAR56),
.VAR261 (VAR261),
.VAR228 (VAR228),
.VAR28 (VAR28),
.VAR266 (VAR266),
.VAR69 (VAR69),
.VAR57 (VAR57),
.VAR253 (VAR253),
.VAR18 (VAR18),
.VAR107 (VAR107),
.VAR169 (VAR169),
.VAR87 (VAR87),
.VAR141 (VAR141),
.VAR192 (VAR192),
.VAR206 (VAR206),
.VAR104 (VAR104),
.VAR179 (VAR179),
.VAR233 (VAR233),
.VAR188 (VAR188),
.VAR222 (VAR222),
.VAR78 (VAR78),
.VAR45 (VAR45),
.VAR76 (VAR76),
.VAR25 (VAR25),
.VAR219 (VAR219),
.VAR216 (VAR224),
.VAR105 (VAR62),
.VAR164 (VAR74),
.VAR33 (VAR240),
.VAR178 (VAR196),
.VAR277 (VAR247),
.VAR40 (VAR40),
.VAR48 (VAR48),
.VAR187 (VAR187),
.VAR299 (VAR299),
.VAR267 (VAR267),
.VAR189 (VAR189),
.VAR23 (VAR23),
.VAR103 (VAR103),
.VAR1 (VAR1),
.VAR131 (VAR131),
.VAR166 (VAR166),
.VAR199 (VAR199),
.VAR163 (VAR163),
.VAR98 (VAR98),
.VAR97 (VAR97),
.VAR274 (VAR274),
.VAR37 (VAR37),
.VAR255 (VAR255),
.VAR221 (VAR221),
.VAR170 (VAR170),
.VAR41 (VAR41),
.VAR214 (VAR214),
.VAR285 (VAR285),
.VAR259 (VAR259),
.VAR106 (VAR106),
.VAR195 (VAR195),
.VAR47 (VAR47),
.VAR235 (VAR235),
.VAR218 (VAR218),
.VAR65 (VAR65),
.VAR54 (VAR54),
.VAR121 (VAR121),
.VAR254 (VAR254),
.VAR125 (VAR125),
.VAR94 (VAR94),
.VAR132 (VAR132),
.VAR232 (VAR232),
.VAR290 (VAR290),
.VAR201 (VAR201),
.VAR39 (VAR39),
.VAR129 (VAR129),
.VAR4 (VAR4),
.VAR75 (VAR75),
.VAR215 (VAR215),
.VAR59 (VAR59),
.VAR31 (VAR31),
.VAR92 (VAR92),
.VAR249 (VAR249),
.VAR162 (VAR162),
.VAR66 (VAR66),
.VAR55 (VAR55),
.VAR244 (VAR244),
.VAR284 (VAR284),
.VAR167 (VAR167),
.VAR171 (VAR171),
.VAR264 (VAR264),
.VAR161 (VAR161),
.VAR49 (VAR49),
.VAR95 (VAR95),
.VAR217 (VAR217),
.VAR21 (VAR21),
.VAR58 (VAR58),
.VAR159 (VAR159),
.VAR93 (VAR93),
.VAR288 (VAR288),
.VAR113 (VAR113)
);
VAR22 #
(
.VAR245 (VAR245),
.VAR147 (VAR147),
.VAR7 (VAR7),
.VAR6 (VAR6),
.VAR205 (VAR205),
.VAR152 (VAR152),
.VAR122 (VAR122),
.VAR101 (VAR101),
.VAR89 (VAR89),
.VAR146 (VAR146),
.VAR184 (VAR184),
.VAR3 (VAR3),
.VAR68 (VAR68),
.VAR239 (VAR239),
.VAR63 (VAR63)
)
VAR209
(
.VAR228 (VAR228[VAR7-1:0]),
.VAR261 (VAR261[VAR147-1:0]),
.VAR18 (VAR18),
.VAR253 (VAR253),
.VAR69 (VAR69),
.VAR266 (VAR266),
.VAR28 (VAR28),
.VAR57 (VAR57),
.VAR56 (VAR56),
.VAR64 (VAR64),
.VAR81 (VAR81),
.VAR283 (VAR283),
.VAR127 (VAR127),
.VAR181 (VAR181),
.VAR293 (VAR293),
.VAR302 (VAR302),
.VAR118 (VAR118),
.VAR100 (VAR100),
.VAR212 (VAR212),
.VAR45 (VAR45),
.VAR78 (VAR78),
.VAR222 (VAR222),
.rst (reset),
.VAR188 (VAR188),
.VAR233 (VAR233),
.VAR179 (VAR179),
.VAR104 (VAR104),
.VAR206 (VAR206[VAR147-1:0]),
.VAR141 (VAR141),
.clk (clk),
.VAR142 (VAR142),
.VAR282 (VAR282),
.VAR305 (VAR305),
.VAR117 (VAR117),
.VAR30 (1'b1),
.VAR126 (VAR126),
.VAR301 (VAR301),
.VAR2 (VAR2),
.VAR286 (VAR286),
.VAR211 (VAR211),
.VAR169 (VAR169),
.VAR107 (VAR107),
.VAR114 (VAR83),
.VAR216 (VAR216),
.VAR208 (VAR224),
.VAR43 (VAR62),
.VAR105 (VAR105),
.VAR164 (VAR164),
.VAR243 (VAR74),
.VAR24 (VAR240),
.VAR33 (VAR33),
.VAR178 (VAR178),
.VAR86 (VAR196),
.VAR134 (VAR247),
.VAR277 (VAR277)
);
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25.pp.blackbox.v
| 1,343 |
module MODULE1 (
VAR1 ,
VAR3 ,
VAR5,
VAR4,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR2 ;
endmodule
|
apache-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/yacc/ram_module_altera.v
| 5,353 |
module MODULE1(VAR24,VAR58,VAR1,VAR46,VAR38,VAR47,VAR53,VAR21,VAR12,VAR28,
VAR9,VAR13);
input VAR24,VAR58;
input VAR53;
input [31:0] VAR21;
input VAR28;
input [7:0] VAR9;
input VAR13;VAR5 VAR30
input [14:0] VAR38,VAR47; reg [14:0] VAR61;
input [13:0] VAR38,VAR47; reg [13:0] VAR61;
input [11:0] VAR38,VAR47; reg [11:0] VAR61;
output [31:0] VAR1; output [31:0] VAR46; input [1:0] VAR12;
reg [31:0] VAR1;
reg [31:0] VAR46;
reg [1:0] VAR44;
wire [7:0] VAR32,VAR26,VAR60,VAR63;
wire [7:0] b0,b1,VAR36,VAR31;
wire [7:0] VAR64,VAR15,VAR55,VAR6;
wire VAR48,VAR14,VAR40,VAR51;
wire VAR62=VAR8==VAR47;
reg VAR35;
assign VAR64=VAR21[7:0] ;
assign VAR15=VAR12 !=VAR27 ? VAR21[15:8] : VAR21[7:0];
assign VAR55=VAR12==VAR7 ? VAR21[23:16] : VAR21[7:0];
assign VAR6=VAR12==VAR7 ? VAR21[31:24] :
VAR12==VAR43 ? VAR21[15:8] : VAR21[7:0];
VAR57 VAR19(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[14:2]),
.VAR39(VAR64),.VAR56(VAR47[14:2]),.VAR50(VAR48),.VAR24(VAR24),
.VAR34(VAR32),.VAR4(b0));
VAR18 VAR11(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[14:2]),
.VAR39(VAR15),.VAR56(VAR47[14:2]),.VAR50(VAR14),.VAR24(VAR24),
.VAR34(VAR26),.VAR4(b1));
VAR54 VAR22(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[14:2]),
.VAR39(VAR55),.VAR56(VAR47[14:2]),.VAR50(VAR40),.VAR24(VAR24),
.VAR34(VAR60),.VAR4(VAR36));
VAR17 VAR52(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[14:2]),
.VAR39(VAR6),.VAR56(VAR47[14:2]),.VAR50(VAR51),.VAR24(VAR24),
.VAR34(VAR63),.VAR4(VAR31));
VAR45 VAR19(.VAR33(VAR38[13:2]),
.VAR16(VAR64),.VAR65(VAR47[13:2]),.VAR42(VAR48),.VAR49(VAR24),.VAR37(VAR24),
.VAR29(VAR32),.VAR59(b0));
VAR41 VAR11(.VAR33(VAR38[13:2]),
.VAR16(VAR15),.VAR65(VAR47[13:2]),.VAR42(VAR14),.VAR49(VAR24),.VAR37(VAR24),
.VAR29(VAR26),.VAR59(b1));
VAR10 VAR22(.VAR33(VAR38[13:2]),
.VAR16(VAR55),.VAR65(VAR47[13:2]),.VAR42(VAR40),.VAR49(VAR24),.VAR37(VAR24),
.VAR29(VAR60),.VAR59(VAR36));
VAR3 VAR52(.VAR33(VAR38[13:2]),
.VAR16(VAR6),.VAR65(VAR47[13:2]),.VAR42(VAR51),.VAR49(VAR24),.VAR37(VAR24),
.VAR29(VAR63),.VAR59(VAR31));
VAR45 VAR19(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[11:2]),
.VAR39(VAR64),.VAR56(VAR47[11:2]),.VAR50(VAR48),.VAR24(VAR24),
.VAR34(VAR32),.VAR4(b0));
VAR41 VAR11(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[11:2]),
.VAR39(VAR15),.VAR56(VAR47[11:2]),.VAR50(VAR14),.VAR24(VAR24),
.VAR34(VAR26),.VAR4(b1));
VAR10 VAR22(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[11:2]),
.VAR39(VAR55),.VAR56(VAR47[11:2]),.VAR50(VAR40),.VAR24(VAR24),
.VAR34(VAR60),.VAR4(VAR36));
VAR3 VAR52(.VAR20(8'h00),.VAR25(1'b0),.VAR23(VAR38[11:2]),
.VAR39(VAR6),.VAR56(VAR47[11:2]),.VAR50(VAR51),.VAR24(VAR24),
.VAR34(VAR63),.VAR4(VAR31));
wire VAR2=( VAR12==VAR27 && VAR47[1:0]==2'b00);
assign VAR51= VAR53 &&
( VAR12==VAR7 ||
( VAR12==VAR43 && !VAR47[1] ) ||
( VAR12==VAR27 && VAR47[1:0]==2'b00));
assign VAR40= VAR53 &&
( VAR12==VAR7 ||
( VAR12==VAR43 && !VAR47[1]) ||
( VAR47[1:0]==2'b01));
assign VAR14= VAR53 &&
( VAR12==VAR7 ||
( VAR12==VAR43 && VAR47[1]) ||
( VAR47[1:0]==2'b10));
assign VAR48= VAR53 &&
( VAR12==VAR7 ||
( VAR12==VAR43 && VAR47[1]) ||
( VAR47[1:0]==2'b11));
always @(*) VAR1={VAR63,VAR60,VAR26,VAR32};
always @(posedge VAR24) begin
if (VAR58) VAR1 <=0;
end
else VAR1 <={VAR63,VAR60,VAR26,VAR32};
end
always @(posedge VAR24) begin
if (VAR44==VAR7) begin
if(VAR35) begin
VAR46 <={23'h000000,VAR13,VAR9};
end else
VAR46 <={VAR31,VAR36,b1,b0};
end else if (VAR44==VAR43) begin
case (VAR61[1])
end
1'b0: if(VAR28) VAR46 <={{16{VAR31[7]}},VAR31,VAR36}; else VAR46 <={16'h0000,VAR31,VAR36};
end
1'b1: if(VAR28) VAR46 <={{16{b1[7]}},b1,b0}; else VAR46 <={16'h0000,b1,b0};
endcase
end else begin case (VAR61[1:0])
2'b00:if(VAR28) VAR46 <={{24{VAR31[7]}},VAR31};
end
else VAR46 <={16'h0000,8'h00,VAR31};
2'b01:if(VAR28) VAR46 <={{24{VAR36[7]}},VAR36};
end
else VAR46 <={16'h0000,8'h00,VAR36};
2'b10:if(VAR28) VAR46 <={{24{b1[7]}},b1};
else VAR46 <={16'h0000,8'h00,b1};
2'b11:if(VAR28) VAR46 <={{24{b0[7]}},b0};
else VAR46 <={16'h0000,8'h00,b0};
endcase
end
end
always @(posedge VAR24) begin
VAR44<=VAR12;
VAR61<=VAR47;
VAR35<=VAR62; end
endmodule
|
mit
|
keith-epidev/VHDL-lib
|
top/lab_5/part_1/ip/clk_108MHz/clk_108MHz_stub.v
| 1,182 |
module MODULE1(VAR1, MODULE1, VAR2)
;
input VAR1;
output MODULE1;
output VAR2;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/a211o/sky130_fd_sc_lp__a211o.functional.v
| 1,443 |
module MODULE1 (
VAR7 ,
VAR6,
VAR1,
VAR10,
VAR4
);
output VAR7 ;
input VAR6;
input VAR1;
input VAR10;
input VAR4;
wire VAR3 ;
wire VAR2;
and VAR8 (VAR3 , VAR6, VAR1 );
or VAR5 (VAR2, VAR3, VAR4, VAR10);
buf VAR9 (VAR7 , VAR2 );
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.behavioral.pp.v
| 1,187 |
module MODULE1( VAR4, VAR3, VAR7, VAR6 );
input VAR4;
inout VAR7, VAR6;
output VAR3;
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR6(VAR6));
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR6(VAR6));
|
apache-2.0
|
Monash-2015-Ultrasonic/Logs
|
Final System Code/SYSTEMV3/Source/IP/MULT_sumXsq/MULT_sumXsq.v
| 4,400 |
module MODULE1 (
VAR4,
VAR14,
VAR1);
input [25:0] VAR4;
input [23:0] VAR14;
output [49:0] VAR1;
wire [49:0] VAR11;
wire [49:0] VAR1 = VAR11[49:0];
VAR8 VAR15 (
.VAR4 (VAR4),
.VAR14 (VAR14),
.VAR1 (VAR11),
.VAR10 (1'b0),
.VAR16 (1'b1),
.VAR12 (1'b0),
.sum (1'b0));
VAR15.VAR7 = "VAR19=VAR9,VAR13=9",
VAR15.VAR17 = "VAR18",
VAR15.VAR5 = "VAR20",
VAR15.VAR3 = 26,
VAR15.VAR6 = 24,
VAR15.VAR2 = 50;
endmodule
|
gpl-2.0
|
GREO/GNU-Radio
|
usrp/fpga/models/fifo_1c_2k.v
| 1,551 |
module MODULE1 ( VAR12, VAR18, VAR19, VAR10, VAR14, VAR4, VAR3,
VAR2, VAR1, VAR7, VAR17, VAR15, VAR6);
parameter VAR16 = 32;
parameter VAR5 = 2048;
input [31:0] VAR12;
input VAR18;
input VAR19;
input VAR10;
input VAR14;
input VAR4;
output [31:0] VAR3;
output VAR2;
output VAR1;
output [10:0] VAR7;
output VAR17;
output VAR15;
output [10:0] VAR6;
reg [VAR16-1:0] VAR9 [0:VAR5-1];
reg [7:0] VAR11;
reg [7:0] VAR13;
reg [VAR16-1:0] VAR3;
wire [VAR16-1:0] VAR3;
reg [10:0] VAR7;
reg [10:0] VAR6;
integer VAR8;
always @( VAR4)
begin
VAR13 <= 0;
VAR11 <= 0;
for(VAR8=0;VAR8<VAR5;VAR8=VAR8+1)
VAR9[VAR8] <= 0;
end
always @(posedge VAR14)
if(VAR18)
begin
VAR13 <= VAR13+1;
VAR9[VAR13] <= VAR12;
end
always @(posedge VAR10)
if(VAR19)
begin
VAR11 <= VAR11+1;
VAR3 <= VAR9[VAR11];
end
assign VAR3 = VAR9[VAR11];
always @(posedge VAR14)
VAR6 <= VAR13 - VAR11;
always @(posedge VAR10)
VAR7 <= VAR13 - VAR11;
assign VAR15 = (VAR6 == 0);
assign VAR17 = (VAR6 == VAR5-1);
assign VAR1 = (VAR7 == 0);
assign VAR2 = (VAR7 == VAR5-1);
endmodule
|
gpl-3.0
|
valptek/v586
|
core_rtl/realign.v
| 6,659 |
module MODULE1 (
clk,
VAR24,
VAR21,VAR10,
VAR25,VAR15,
VAR26,VAR1,
VAR18,VAR7,
VAR20,
VAR2,
VAR19,
VAR4,
VAR23,
VAR22,
VAR3,
VAR28
);
input [31:0] VAR23 ,VAR19 ,VAR20;
output [31:0] VAR22,VAR4,VAR2;
input VAR24,clk;
input VAR21,VAR10,VAR26,VAR1;
input [1:0] VAR3;
output [3:0] VAR28;
output VAR15,VAR25,VAR18,VAR7;
reg VAR8, VAR17, VAR27, VAR5;
reg [31:0] VAR16;
reg VAR14;
reg [31:0] VAR13;
reg [31:0] VAR12,VAR11;
reg [3:0] VAR9;
wire VAR6 = ((VAR20[1] == 1'b1) || (VAR20[0] == 1'b1)) ? 1'b1 : 1'b0;
assign VAR25 = VAR6 ? VAR27 : VAR21;
assign VAR18 = VAR6 ? VAR5 : VAR26;
assign VAR15 = ((VAR6 == 1'b1) && (VAR3 !=2'b00)) ? VAR8 : VAR10;
assign VAR7 = ((VAR6 == 1'b1) && (VAR3 !=2'b00)) ? VAR17 : VAR1;
assign VAR28 = ((VAR6 == 1'b1) && (VAR3 != 2'b00)) ? VAR9 :
((VAR20[1:0] == 2'b00) && (VAR3 == 2'b00)) ? 4'b0001 :
((VAR20[1:0] == 2'b01) && (VAR3 == 2'b00)) ? 4'b0010 :
((VAR20[1:0] == 2'b10) && (VAR3 == 2'b00)) ? 4'b0100 :
((VAR20[1:0] == 2'b11) && (VAR3 == 2'b00)) ? 4'b1000 :
(VAR3 == 2'b01) ? 4'b0011 :
4'b1111 ;
assign VAR22 = ((VAR6 == 1'b1) && (VAR3 != 2'b00)) ? VAR11 :
((VAR20[1:0] == 2'b01) && (VAR3 == 2'b00)) ? {16'h5555,VAR23[7:0],8'h55} :
((VAR20[1:0] == 2'b10) && (VAR3 == 2'b00)) ? { 8'h55,VAR23[7:0],16'h5555} :
((VAR20[1:0] == 2'b11) && (VAR3 == 2'b00)) ? { VAR23[7:0],24'h555555} :
VAR23;
assign VAR4 = VAR6 ? VAR12 : VAR19;
assign VAR2 = ((VAR6 == 1'b1) && ( VAR21 == 1'b1)) ? VAR16 :
((VAR6 == 1'b1) && (VAR10 == 1'b1) && (VAR3 !=2'b00)) ? VAR16 :
{VAR20[31:2],2'b00};
always @(posedge clk or negedge VAR24)
if (~VAR24)
begin
VAR8 <= 1'b0;
VAR17 <= 1'b0;
VAR27 <= 1'b0;
VAR5 <= 1'b0;
VAR14 <= 1'b0;
VAR9 <= 4'b1111;
VAR12 <= 32'h0;
VAR11 <= 32'h0;
end
else
begin
if (VAR17 == 1'b1)
begin
VAR8 <= 1'b0;
VAR17 <= 1'b0;
VAR14 <= 1'b0;
VAR9 <= 4'b0000;
end
else if (VAR5 == 1'b1)
begin
VAR27 <= 1'b0;
VAR5 <= 1'b0;
VAR14 <= 1'b0;
end
else
if ((VAR6 == 1'b1) && (VAR27 == 1'b0) && (VAR21 == 1'b1) && (VAR14 == 1'b0))
begin
VAR27 <= 1'b1;
VAR16 <= {VAR20[31:2],2'b00};
VAR14 <= 1'b1;
end
else
if ((VAR6 == 1'b1) && (VAR27 == 1'b1) && (VAR26 == 1'b1) && (VAR14 == 1'b1))
begin
VAR16 <= {VAR20[31:2],2'b00} + 3'b100;
VAR13<= VAR19;
VAR14 <= 1'b0;
end
else
if ((VAR6 == 1'b1) && (VAR27 == 1'b1) && (VAR26 == 1'b1) && (VAR14 == 1'b0))
begin
VAR14 <= 1'b0;
VAR5 <= 1'b1;
VAR27 <= 1'b0;
case(VAR20[1:0])
2'b00: VAR12 <= VAR13;
2'b01: VAR12 <= {VAR19[ 7:0],VAR13[31: 8]};
2'b10: VAR12 <= {VAR19[15:0],VAR13[31:16]};
2'b11: VAR12 <= {VAR19[23:0],VAR13[31:24]};
endcase
end
else
if ((VAR6 == 1'b1) && (VAR8 == 1'b0) && (VAR10 == 1'b1) && (VAR14 == 1'b0) && (VAR3 != 2'b00))
begin
VAR16 <= {VAR20[31:2],2'b00};
VAR14 <= 1'b1;
VAR8 <= 1'b1;
if ((VAR20[1:0] == 2'b01) && (VAR3 ==2'b01)) begin VAR9 <= 4'b0110; VAR11 <= {VAR23[23:0], 8'b0}; end else
if ((VAR20[1:0] == 2'b01) && (VAR3 ==2'b10)) begin VAR9 <= 4'b1110; VAR11 <= {VAR23[23:0], 8'b0}; end else
if ((VAR20[1:0] == 2'b10) && (VAR3 ==2'b01)) begin VAR9 <= 4'b1100; VAR11 <= {VAR23[15:0],16'b0}; end else
if ((VAR20[1:0] == 2'b10) && (VAR3 ==2'b10)) begin VAR9 <= 4'b1100; VAR11 <= {VAR23[15:0],16'b0}; end else
if ((VAR20[1:0] == 2'b11) && (VAR3 ==2'b01)) begin VAR9 <= 4'b1000; VAR11 <= {VAR23[ 7:0],24'b0}; end else
if ((VAR20[1:0] == 2'b11) && (VAR3 ==2'b10)) begin VAR9 <= 4'b1000; VAR11 <= {VAR23[ 7:0],24'b0}; end
end
else
if ((VAR6 == 1'b1) && (VAR8 == 1'b1) && (VAR1 == 1'b1) && (VAR14 == 1'b1))
begin
VAR16 <= {VAR20[31:2],2'b00} + 3'b100;
VAR14 <= 1'b0;
if ((VAR20[1:0] == 2'b01) && (VAR3 ==2'b10)) begin VAR9 <= 4'b0001; VAR11 <= {24'b0,VAR23[31:24]}; end else
if ((VAR20[1:0] == 2'b10) && (VAR3 ==2'b10)) begin VAR9 <= 4'b0011; VAR11 <= {16'b0,VAR23[31:16]}; end else
if ((VAR20[1:0] == 2'b11) && (VAR3 ==2'b01)) begin VAR9 <= 4'b0001; VAR11 <= { 8'b0,VAR23[31: 8]}; end else
if ((VAR20[1:0] == 2'b11) && (VAR3 ==2'b10)) begin VAR9 <= 4'b0111; VAR11 <= { 8'b0,VAR23[31: 8]}; end else
begin VAR9 <= 4'b0000; end
end
else
if ((VAR6 == 1'b1) && (VAR8 == 1'b1) && (VAR1 == 1'b1) && (VAR14 == 1'b0))
begin
VAR14 <= 1'b0;
VAR17 <= 1'b1;
VAR8 <= 1'b0;
end
end
endmodule
|
apache-2.0
|
bbrown1867/ObjectTracking
|
hw/common/video_input/yuv422_to_yuv444.v
| 1,055 |
module MODULE1
(
input wire VAR2,
input wire VAR10,
input wire [15:0] VAR6,
input wire VAR12,
output wire [7:0] VAR3,
output wire [7:0] VAR4,
output wire [7:0] VAR9,
output wire VAR7
);
reg VAR1;
reg [7:0] VAR11;
reg [7:0] VAR5;
reg [7:0] VAR13;
reg VAR8;
assign VAR3 = VAR11;
assign VAR4 = VAR5;
assign VAR9 = VAR13;
assign VAR7 = VAR8;
always@(posedge VAR2 or negedge VAR10)
begin
if(!VAR10)
begin
VAR1 <= 0;
VAR11 <= 0;
VAR5 <= 0;
VAR13 <= 0;
VAR8 <= 0;
end
else
begin
VAR1 <= ~VAR1;
VAR8 <= VAR12;
if(VAR1)
{VAR11,VAR13} <= VAR6;
end
else
{VAR11,VAR5} <= VAR6;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o211a/sky130_fd_sc_ms__o211a.behavioral.v
| 1,542 |
module MODULE1 (
VAR2 ,
VAR3,
VAR7,
VAR9,
VAR6
);
output VAR2 ;
input VAR3;
input VAR7;
input VAR9;
input VAR6;
supply1 VAR12;
supply0 VAR1;
supply1 VAR14 ;
supply0 VAR10 ;
wire VAR8 ;
wire VAR13;
or VAR5 (VAR8 , VAR7, VAR3 );
and VAR11 (VAR13, VAR8, VAR9, VAR6);
buf VAR4 (VAR2 , VAR13 );
endmodule
|
apache-2.0
|
manu3193/GatoTDD
|
Gato_Top.v
| 3,452 |
module MODULE1(
input clk , VAR88, input VAR90, input VAR94, input VAR92,
input VAR56,
input VAR24,
input VAR8,
output VAR20,VAR22, output [2:0] VAR19, output [3:0] VAR34
);
wire VAR41;
wire [3:0] VAR34;
wire [1:0] VAR26;
wire [1:0] VAR78;
wire [1:0] VAR37;
wire [2:0] state;
wire VAR79;
wire VAR53;
wire VAR97;
wire VAR77;
wire VAR21;
wire [1:0]
VAR40,
VAR82,
VAR18,
VAR5,
VAR81,
VAR49,
VAR14,
VAR7,
VAR73;
wire VAR45;
wire VAR35;
wire VAR12;
wire VAR1;
wire VAR83;
wire[10:0] VAR96, VAR72;
wire VAR44;
wire VAR39;
wire VAR89;
wire VAR63;
assign VAR20 = ~VAR89;
assign VAR22 = ~VAR63;
VAR71 VAR57 (
.clk(VAR41),
.VAR9(VAR94),
.VAR33(VAR92),
.VAR46(VAR56),
.VAR27(VAR24),
.VAR36(VAR8),
.VAR85(VAR45),
.VAR3(VAR35),
.VAR61(VAR12),
.VAR15(VAR1),
.VAR50(VAR83)
);
VAR38 VAR29 (
.clk(VAR41),
.VAR88(VAR88),
.VAR90(VAR90),
.VAR34(VAR34),
.VAR26(VAR26),
.VAR78(VAR78),
.VAR37(VAR37),
.state(state),
.VAR76(VAR40),
.VAR93(VAR82),
.VAR13(VAR18),
.VAR47(VAR5),
.VAR75(VAR81),
.VAR25(VAR49),
.VAR80(VAR14),
.VAR43(VAR7),
.VAR4(VAR73),
.VAR52(VAR45),
.VAR60(VAR35),
.VAR30(VAR12),
.VAR66(VAR1),
.VAR31(VAR83),
.VAR79(VAR79),
.VAR53(VAR53),
.VAR51(VAR97),
.VAR28(VAR77),
.VAR67(VAR21)
);
VAR55 VAR95 (
.clk(VAR39),
.reset(reset),
.VAR20(VAR89),
.VAR22(VAR63),
.VAR42(VAR96),
.VAR6(VAR72),
.VAR54(VAR44));
VAR65 VAR10(
.VAR87(VAR44),
.VAR32(VAR34),
.VAR69(VAR40),
.VAR91(VAR82),
.VAR62(VAR18),
.VAR84(VAR5),
.VAR23(VAR81),
.VAR11(VAR49),
.VAR86(VAR7),
.VAR16(VAR14),
.VAR70(VAR73),
.VAR17(VAR96),
.VAR48(VAR72),
.VAR58(VAR19)
);
VAR74 VAR2 (.VAR68(clk), .VAR64(VAR39), .VAR59(VAR41));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.v
| 2,128 |
module MODULE1 (
VAR6 ,
VAR2 ,
VAR9 ,
VAR5,
VAR1,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR5;
input VAR1;
input VAR4 ;
input VAR3 ;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6 ,
VAR2,
VAR9
);
output VAR6 ;
input VAR2;
input VAR9 ;
supply1 VAR5;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR3 ;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.v
| 2,345 |
module MODULE2 (
VAR4 ,
VAR1 ,
VAR10 ,
VAR11 ,
VAR8 ,
VAR5,
VAR9,
VAR3 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR11 ;
input VAR8 ;
input VAR5;
input VAR9;
input VAR3 ;
input VAR2 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4 ,
VAR1,
VAR10 ,
VAR11,
VAR8
);
output VAR4 ;
input VAR1;
input VAR10 ;
input VAR11;
input VAR8;
supply1 VAR5;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR2 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/bbcpu
|
cpu.v
| 8,687 |
module MODULE1(
input clk,
output VAR16);
localparam VAR1 = 4;
localparam VAR73 = 8;
localparam VAR40 = VAR73 - VAR1;
localparam VAR55 = 4'b0000; localparam VAR39 = 4'b0001; localparam VAR79 = 4'b0010; localparam VAR30 = 4'b0011; localparam VAR52 = 4'b0100; localparam VAR50 = 4'b0101; localparam VAR42 = 4'b0110; localparam VAR45 = 4'b0111; localparam VAR11 = 4'b1000; localparam VAR63= 4'b1001; localparam VAR58= 4'b1010; localparam VAR6 = 4'b1111;
localparam VAR21 = 0; localparam VAR35 = 1; localparam VAR67 = 2; localparam VAR64 = 3; localparam VAR5 = 4; localparam VAR18 = 5; localparam VAR72 = 6; localparam VAR32 = 7; localparam VAR53 = 8; localparam VAR57 = 9; localparam VAR59 = 10; localparam VAR22 = 11; localparam VAR20 = VAR22 + 1;
localparam VAR74 = 0;
localparam VAR10 = 1;
localparam VAR65 = 2;
localparam VAR14 = 3;
localparam VAR26 = 4;
localparam VAR34 = VAR26 + 1;
localparam VAR13 = VAR9(VAR34);
localparam VAR47 = 5;
localparam VAR19 = (1 << 5) - 1;
reg [VAR47 : 0] VAR48 = 0;
reg VAR7 = 0;
reg [VAR73-1 : 0] VAR75; reg [VAR20-1 : 0] VAR41; reg [VAR13-1 : 0] VAR76; reg [VAR73-1 : 0] VAR17; reg [VAR73-1 : 0] VAR46; reg VAR66;
wire [VAR73-1 : 0] VAR61; wire VAR56; wire [VAR40-1 : 0] VAR43; wire [VAR40-1 : 0] VAR38; wire [VAR73-1 : 0] VAR78; wire [VAR73-1 : 0] VAR77; wire [VAR73-1 : 0] VAR51; wire VAR31;
VAR71 #(.VAR40(VAR40)) VAR33(
.rst(!VAR7),
.clk(clk),
.enable(VAR41[VAR67]),
.VAR4(VAR41[VAR21]),
.VAR44(VAR41[VAR35]),
.VAR8(VAR43),
.VAR28(VAR38));
alu #(.VAR73(VAR73)) alu(
.VAR25(VAR17),
.VAR27(VAR46),
.VAR24(VAR41[VAR22]),
.VAR69(VAR41[VAR5]),
.VAR54(VAR41[VAR59]),
.VAR70(VAR75[2 : 0]),
.VAR2(VAR61),
.VAR3(VAR56));
VAR15 #(.VAR73(VAR73),.VAR40(VAR40)) memory(
.clk(clk),
.enable(VAR41[VAR32]),
.VAR62(VAR41[VAR53]),
.addr(VAR51),
.VAR68(VAR78),
.VAR12(VAR77));
VAR23 VAR36(
.rst(!VAR7),
.clk(clk),
.VAR60(VAR41[VAR64]),
.VAR49(VAR17),
.VAR37(VAR16),
.VAR29(VAR31));
assign VAR43 = (VAR41[VAR21] && VAR41[VAR72]) ? VAR75[VAR40-1 : 0] : 0;
assign VAR51 = (VAR41[VAR57] && VAR41[VAR72]) ? VAR75[VAR40-1 : 0] :
(VAR41[VAR57] && VAR41[VAR35]) ? VAR38 : 0;
assign VAR78 = (VAR41[VAR53] && VAR41[VAR18]) ? VAR17 : 0;
always @(posedge clk) begin
if (VAR48 != VAR19) begin
VAR48 <= VAR48 + 1;
end else begin
VAR7 <= 1;
end
end
always @(posedge clk) begin
if (VAR7) begin
case (VAR76)
VAR74: begin
VAR41 <= (1 << VAR32) | (1 << VAR57) | (1 << VAR35);
VAR76 <= VAR10;
end
VAR10: begin
VAR41 <= 1 << VAR67;
VAR75 <= VAR77;
VAR76 <= VAR65;
end
VAR65: begin
case (VAR75[VAR73-1 : VAR40])
VAR58: begin
VAR41 <= (1 << VAR22);
VAR76 <= VAR14;
end
VAR63: begin
VAR41 <= (1 << VAR59);
VAR76 <= VAR14;
end
VAR39: begin
VAR41 <= (1 << VAR32) | (1 << VAR57) | (1 << VAR72);
VAR76 <= VAR14;
end
VAR52: begin
VAR41 <= (1 << VAR53) | (1 << VAR18) | (1 << VAR57) | (1 << VAR72);
VAR76 <= VAR74;
end
VAR79: begin
VAR41 <= (1 << VAR32) | (1 << VAR57) | (1 << VAR72);
VAR76 <= VAR14;
end
VAR30: begin
VAR41 <= (1 << VAR32) | (1 << VAR57) | (1 << VAR72);
VAR76 <= VAR14;
end
VAR50: begin
VAR41 <= 1 << VAR64;
VAR76 <= VAR14;
end
VAR42: begin
VAR41 <= (1 << VAR21) | (1 << VAR72);
VAR76 <= VAR74;
end
VAR11: begin
if (VAR66) begin
VAR41 <= (1 << VAR21) | (1 << VAR72);
end else begin
VAR41 <= 0;
end
VAR76 <= VAR74;
end
VAR45: begin
VAR41 <= 0;
VAR17 <= {4'b0, VAR75[3 : 0]};
VAR76 <= VAR74;
end
VAR55: begin
VAR41 <= 0;
VAR76 <= VAR74;
end
VAR6: begin
VAR41 <= 0;
VAR76 <= VAR34;
end
default: begin
VAR76 <= VAR34;
end
endcase
end
VAR14: begin
case (VAR75[VAR73-1 : VAR40])
VAR58: begin
VAR17 <= VAR61;
VAR66 <= VAR56;
VAR76 <= VAR74;
end
VAR63: begin
VAR17 <= VAR61;
VAR66 <= VAR56;
VAR76 <= VAR74;
end
VAR39: begin
VAR17 <= VAR77;
VAR76 <= VAR74;
end
VAR79: begin
VAR41 <= 0;
VAR46 <= VAR77;
VAR76 <= VAR26;
end
VAR30: begin
VAR41 <= 1 << VAR5;
VAR46 <= VAR77;
VAR76 <= VAR26;
end
VAR50: begin
VAR41 <= 0;
if (VAR31) begin
VAR76 <= VAR74;
end else begin
VAR76 <= VAR14;
end
end
default: begin
VAR76 <= VAR34;
end
endcase
end
VAR26: begin
case (VAR75[VAR73-1 : VAR40])
VAR79: begin
VAR17 <= VAR61;
VAR66 <= VAR56;
VAR76 <= VAR74;
end
VAR30: begin
VAR17 <= VAR61;
VAR76 <= VAR74;
end
default: begin
VAR76 <= VAR34;
end
endcase
end
default: begin
VAR76 <= VAR34;
end
endcase
end else begin
VAR75 <= 0;
VAR66 <= 0;
VAR41 <= 0;
VAR17 <= 0;
VAR46 <= 0;
VAR76 <= VAR74;
end
end
endmodule
|
apache-2.0
|
davidkoltak/tawas-core
|
ip/debug_ip/rtl/spdr_fifo.v
| 2,245 |
module MODULE1
(
input VAR2,
input VAR10,
input VAR3,
input [7:0] din,
input VAR14,
output VAR5,
output [7:0] dout,
input VAR8,
output VAR7
);
reg [1:0] VAR15;
reg [3:0] VAR4;
reg [3:0] VAR1;
reg [3:0] VAR9;
reg [1:0] VAR18;
reg [3:0] VAR6;
reg [3:0] VAR17;
reg [3:0] VAR19;
always @ (posedge VAR10)
VAR15 <= VAR18;
always @ (posedge VAR3 or posedge VAR2)
if (VAR2)
VAR18 <= 2'b00;
else
case (VAR15)
2'b00: VAR18 <= 2'b01;
2'b01: VAR18 <= 2'b11;
2'b11: VAR18 <= 2'b10;
default: VAR18 <= 2'b00;
endcase
wire [3:0] VAR12 = VAR4 + 4'd1;
wire VAR16 = (VAR12 == VAR9);
always @ (posedge VAR10 or posedge VAR2)
if (VAR2)
begin
VAR4 <= 4'd0;
VAR1 <= 4'd0;
VAR9 <= 4'd0;
end
else
begin
if (VAR14 && !VAR16)
VAR4 <= VAR12;
case (VAR15)
2'b01: VAR1 <= VAR4;
2'b10: VAR9 <= VAR19;
endcase
end
wire [3:0] VAR20 = VAR17 + 4'd1;
wire VAR13 = (VAR17 == VAR6);
always @ (posedge VAR3 or posedge VAR2)
if (VAR2)
begin
VAR6 <= 4'd0;
VAR17 <= 4'd0;
VAR19 <= 4'd0;
end
else
begin
if (VAR8 && !VAR13)
VAR17 <= VAR20;
case (VAR18)
2'b01: VAR19 <= VAR17;
2'b10: VAR6 <= VAR1;
endcase
end
reg [7:0] VAR11[15:0];
always @ (posedge VAR10)
if (VAR14)
VAR11[VAR4] <= din[7:0];
assign VAR5 = VAR16;
assign VAR7 = VAR13;
assign dout = VAR11[VAR17];
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15.behavioral.pp.v
| 1,866 |
module MODULE1 (
VAR8 ,
VAR2 ,
VAR1,
VAR11,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR7 ;
input VAR6 ;
wire VAR5 ;
wire VAR10;
buf VAR3 (VAR5 , VAR2 );
VAR12 VAR4 (VAR10, VAR5, VAR1, VAR11);
buf VAR9 (VAR8 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nand3b/sky130_fd_sc_ms__nand3b.pp.symbol.v
| 1,313 |
module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR7 ,
output VAR4 ,
input VAR8 ,
input VAR3,
input VAR5,
input VAR6
);
endmodule
|
apache-2.0
|
markusC64/1541ultimate2
|
fpga/nios_c5/nios/synthesis/submodules/rw_manager_lfsr36.v
| 2,025 |
module MODULE1(
clk,
VAR1,
VAR2,
word
);
input clk;
input VAR1;
input VAR2;
output reg [35:0] word;
always @(posedge clk or negedge VAR1) begin
if(~VAR1) begin
word <= 36'hF0F0AA55;
end
else if(VAR2) begin
word[35] <= word[0];
word[34] <= word[35];
word[33] <= word[34];
word[32] <= word[33];
word[31] <= word[32];
word[30] <= word[31];
word[29] <= word[30];
word[28] <= word[29];
word[27] <= word[28];
word[26] <= word[27];
word[25] <= word[26];
word[24] <= word[25] ^ word[0];
word[23] <= word[24];
word[22] <= word[23];
word[21] <= word[22];
word[20] <= word[21];
word[19] <= word[20];
word[18] <= word[19];
word[17] <= word[18];
word[16] <= word[17];
word[15] <= word[16];
word[14] <= word[15];
word[13] <= word[14];
word[12] <= word[13];
word[11] <= word[12];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6];
word[4] <= word[5];
word[3] <= word[4];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1];
end
end
endmodule
|
gpl-3.0
|
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_stub.v
| 1,296 |
module MODULE1(VAR2, VAR1, VAR3, VAR5, VAR4)
;
output VAR2;
output VAR1;
output VAR3;
input VAR5;
input VAR4;
endmodule
|
mit
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_084.v
| 1,519 |
module MODULE2 (
VAR5,
VAR12
);
input [31:0] VAR5;
output [31:0]
VAR12;
wire [31:0]
VAR11,
VAR7,
VAR13,
VAR8,
VAR4,
VAR2,
VAR10,
VAR6,
VAR1;
assign VAR11 = VAR5;
assign VAR8 = VAR11 << 4;
assign VAR10 = VAR2 - VAR4;
assign VAR2 = VAR13 << 8;
assign VAR1 = VAR10 + VAR6;
assign VAR4 = VAR13 - VAR8;
assign VAR6 = VAR4 << 7;
assign VAR7 = VAR11 << 6;
assign VAR13 = VAR11 + VAR7;
assign VAR12 = VAR1;
endmodule
module MODULE1(
VAR5,
VAR12,
clk
);
input [31:0] VAR5;
output [31:0] VAR12;
reg [31:0] VAR12;
input clk;
reg [31:0] VAR3;
wire [30:0] VAR14;
always @(posedge clk) begin
VAR3 <= VAR5;
VAR12 <= VAR14;
end
MODULE2 MODULE1(
.VAR5(VAR3),
.VAR12(VAR14)
);
endmodule
|
mit
|
jmahler/mips-cpu
|
im.v
| 1,164 |
module MODULE1(
input wire clk,
input wire [31:0] addr,
output wire [31:0] VAR1);
parameter VAR4 = 128; parameter VAR6 = "VAR2.VAR5";
reg [31:0] VAR3 [0:127];
|
gpl-3.0
|
chiragsakhuja/gpu
|
fb_block.v
| 7,041 |
module MODULE1 (
address,
VAR44,
VAR31,
VAR37,
VAR15);
input [7:0] address;
input VAR44;
input [7:0] VAR31;
input VAR37;
output [7:0] VAR15;
tri1 VAR44;
wire [7:0] VAR25;
wire [7:0] VAR15 = VAR25[7:0];
VAR7 VAR20 (
.VAR18 (address),
.VAR24 (VAR44),
.VAR6 (VAR31),
.VAR12 (VAR37),
.VAR52 (VAR25),
.VAR29 (1'b0),
.VAR5 (1'b0),
.VAR16 (1'b1),
.VAR40 (1'b0),
.VAR38 (1'b0),
.VAR36 (1'b1),
.VAR14 (1'b1),
.VAR49 (1'b1),
.VAR13 (1'b1),
.VAR11 (1'b1),
.VAR23 (1'b1),
.VAR9 (1'b1),
.VAR43 (1'b1),
.VAR42 (),
.VAR35 (),
.VAR46 (1'b1),
.VAR50 (1'b1),
.VAR41 (1'b0));
VAR20.VAR32 = "VAR28",
VAR20.VAR3 = "VAR28",
VAR20.VAR34 = "VAR22 VAR53",
VAR20.VAR51 = "VAR1=VAR21",
VAR20.VAR2 = "VAR7",
VAR20.VAR48 = 256,
VAR20.VAR8 = "VAR26",
VAR20.VAR39 = "VAR33",
VAR20.VAR45 = "VAR4",
VAR20.VAR54 = "VAR47",
VAR20.VAR17 = "VAR10",
VAR20.VAR30 = 8,
VAR20.VAR27 = 8,
VAR20.VAR19 = 1;
endmodule
|
gpl-2.0
|
efabless/openlane
|
designs/aes_cipher/src/aes_cipher.v
| 10,245 |
module MODULE1(clk, rst, VAR111, VAR3, VAR77, VAR86, VAR27, VAR41, VAR94, VAR99 );
input clk, rst;
input VAR111, VAR41, VAR94;
output VAR3, VAR99;
input [127:0] VAR77;
input [127:0] VAR86;
output [127:0] VAR27;
wire [31:0] VAR51, VAR85, VAR5, VAR89;
reg [127:0] VAR127;
reg [127:0] VAR27;
reg [7:0] VAR73, VAR39, VAR82, VAR84;
reg [7:0] VAR58, VAR76, VAR113, VAR16;
reg [7:0] VAR35, VAR1, VAR116, VAR108;
reg [7:0] VAR50, VAR22, VAR48, VAR92;
wire [7:0] VAR125, VAR37, VAR129, VAR12;
wire [7:0] VAR117, VAR97, VAR47, VAR98;
wire [7:0] VAR78, VAR7, VAR101, VAR44;
wire [7:0] VAR79, VAR70, VAR114, VAR128;
wire [7:0] VAR52, VAR104, VAR14, VAR132;
wire [7:0] VAR120, VAR112, VAR29, VAR88;
wire [7:0] VAR131, VAR46, VAR119, VAR61;
wire [7:0] VAR64, VAR66, VAR26, VAR34;
wire [7:0] VAR2, VAR126, VAR53, VAR123;
wire [7:0] VAR105, VAR96, VAR28, VAR95;
wire [7:0] VAR74, VAR21, VAR33, VAR103;
wire [7:0] VAR65, VAR55, VAR100, VAR23;
wire [7:0] VAR45, VAR43, VAR38, VAR80;
wire [7:0] VAR68, VAR102, VAR24, VAR130;
wire [7:0] VAR42, VAR11, VAR115, VAR91;
wire [7:0] VAR59, VAR83, VAR72, VAR54;
reg VAR3, VAR18;
reg [3:0] VAR75;
always @(posedge clk)
if(!rst) VAR75 <= 4'h0;
else
if(VAR111) VAR75 <= 4'hb;
else
if(|VAR75) VAR75 <= VAR75 - 4'h1;
always @(posedge clk) VAR3 <= !(|VAR75[3:1]) & VAR75[0] & !VAR111;
always @(posedge clk) if(VAR111) VAR127 <= VAR86;
always @(posedge clk) VAR18 <= VAR111;
always @(posedge clk) VAR92 <= VAR18 ? VAR127[007:000] ^ VAR89[07:00] : VAR128;
always @(posedge clk) VAR108 <= VAR18 ? VAR127[015:008] ^ VAR89[15:08] : VAR44;
always @(posedge clk) VAR16 <= VAR18 ? VAR127[023:016] ^ VAR89[23:16] : VAR98;
always @(posedge clk) VAR84 <= VAR18 ? VAR127[031:024] ^ VAR89[31:24] : VAR12;
always @(posedge clk) VAR48 <= VAR18 ? VAR127[039:032] ^ VAR5[07:00] : VAR114;
always @(posedge clk) VAR116 <= VAR18 ? VAR127[047:040] ^ VAR5[15:08] : VAR101;
always @(posedge clk) VAR113 <= VAR18 ? VAR127[055:048] ^ VAR5[23:16] : VAR47;
always @(posedge clk) VAR82 <= VAR18 ? VAR127[063:056] ^ VAR5[31:24] : VAR129;
always @(posedge clk) VAR22 <= VAR18 ? VAR127[071:064] ^ VAR85[07:00] : VAR70;
always @(posedge clk) VAR1 <= VAR18 ? VAR127[079:072] ^ VAR85[15:08] : VAR7;
always @(posedge clk) VAR76 <= VAR18 ? VAR127[087:080] ^ VAR85[23:16] : VAR97;
always @(posedge clk) VAR39 <= VAR18 ? VAR127[095:088] ^ VAR85[31:24] : VAR37;
always @(posedge clk) VAR50 <= VAR18 ? VAR127[103:096] ^ VAR51[07:00] : VAR79;
always @(posedge clk) VAR35 <= VAR18 ? VAR127[111:104] ^ VAR51[15:08] : VAR78;
always @(posedge clk) VAR58 <= VAR18 ? VAR127[119:112] ^ VAR51[23:16] : VAR117;
always @(posedge clk) VAR73 <= VAR18 ? VAR127[127:120] ^ VAR51[31:24] : VAR125;
assign VAR2 = VAR52;
assign VAR126 = VAR104;
assign VAR53 = VAR14;
assign VAR123 = VAR132;
assign VAR105 = VAR112;
assign VAR96 = VAR29;
assign VAR28 = VAR88;
assign VAR95 = VAR120;
assign VAR74 = VAR119;
assign VAR21 = VAR61;
assign VAR33 = VAR131;
assign VAR103 = VAR46;
assign VAR65 = VAR34;
assign VAR55 = VAR64;
assign VAR100 = VAR66;
assign VAR23 = VAR26;
assign {VAR45, VAR68, VAR42, VAR59} = VAR40(VAR2,VAR105,VAR74,VAR65);
assign {VAR43, VAR102, VAR11, VAR83} = VAR40(VAR126,VAR96,VAR21,VAR55);
assign {VAR38, VAR24, VAR115, VAR72} = VAR40(VAR53,VAR28,VAR33,VAR100);
assign {VAR80, VAR130, VAR91, VAR54} = VAR40(VAR123,VAR95,VAR103,VAR23);
assign VAR125 = VAR45 ^ VAR51[31:24];
assign VAR37 = VAR43 ^ VAR85[31:24];
assign VAR129 = VAR38 ^ VAR5[31:24];
assign VAR12 = VAR80 ^ VAR89[31:24];
assign VAR117 = VAR68 ^ VAR51[23:16];
assign VAR97 = VAR102 ^ VAR85[23:16];
assign VAR47 = VAR24 ^ VAR5[23:16];
assign VAR98 = VAR130 ^ VAR89[23:16];
assign VAR78 = VAR42 ^ VAR51[15:08];
assign VAR7 = VAR11 ^ VAR85[15:08];
assign VAR101 = VAR115 ^ VAR5[15:08];
assign VAR44 = VAR91 ^ VAR89[15:08];
assign VAR79 = VAR59 ^ VAR51[07:00];
assign VAR70 = VAR83 ^ VAR85[07:00];
assign VAR114 = VAR72 ^ VAR5[07:00];
assign VAR128 = VAR54 ^ VAR89[07:00];
always @(posedge clk) VAR27[127:120] <= VAR2 ^ VAR51[31:24];
always @(posedge clk) VAR27[095:088] <= VAR126 ^ VAR85[31:24];
always @(posedge clk) VAR27[063:056] <= VAR53 ^ VAR5[31:24];
always @(posedge clk) VAR27[031:024] <= VAR123 ^ VAR89[31:24];
always @(posedge clk) VAR27[119:112] <= VAR105 ^ VAR51[23:16];
always @(posedge clk) VAR27[087:080] <= VAR96 ^ VAR85[23:16];
always @(posedge clk) VAR27[055:048] <= VAR28 ^ VAR5[23:16];
always @(posedge clk) VAR27[023:016] <= VAR95 ^ VAR89[23:16];
always @(posedge clk) VAR27[111:104] <= VAR74 ^ VAR51[15:08];
always @(posedge clk) VAR27[079:072] <= VAR21 ^ VAR85[15:08];
always @(posedge clk) VAR27[047:040] <= VAR33 ^ VAR5[15:08];
always @(posedge clk) VAR27[015:008] <= VAR103 ^ VAR89[15:08];
always @(posedge clk) VAR27[103:096] <= VAR65 ^ VAR51[07:00];
always @(posedge clk) VAR27[071:064] <= VAR55 ^ VAR85[07:00];
always @(posedge clk) VAR27[039:032] <= VAR100 ^ VAR5[07:00];
always @(posedge clk) VAR27[007:000] <= VAR23 ^ VAR89[07:00];
function [31:0] VAR40;
input [7:0] VAR31,VAR106,VAR62,VAR69;
reg [7:0] VAR17,VAR81,VAR56,VAR49;
begin
VAR40[31:24]=VAR4(VAR31)^VAR4(VAR106)^VAR106^VAR62^VAR69;
VAR40[23:16]=VAR31^VAR4(VAR106)^VAR4(VAR62)^VAR62^VAR69;
VAR40[15:08]=VAR31^VAR106^VAR4(VAR62)^VAR4(VAR69)^VAR69;
VAR40[07:00]=VAR4(VAR31)^VAR31^VAR106^VAR62^VAR4(VAR69);
end
endfunction
function [7:0] VAR4;
input [7:0] VAR30; VAR4={VAR30[6:0],1'b0}^(8'h1b&{8{VAR30[7]}});
endfunction
VAR87 VAR107(
.clk( clk ),
.VAR121( VAR111 ),
.VAR77( VAR77 ),
.VAR9( VAR51 ),
.VAR57( VAR85 ),
.VAR13( VAR5 ),
.VAR8( VAR89 ));
VAR109 VAR63( .VAR6( VAR73 ), .VAR25( VAR52 ));
VAR109 VAR71( .VAR6( VAR39 ), .VAR25( VAR104 ));
VAR109 VAR90( .VAR6( VAR82 ), .VAR25( VAR14 ));
VAR109 VAR10( .VAR6( VAR84 ), .VAR25( VAR132 ));
VAR109 VAR122( .VAR6( VAR58 ), .VAR25( VAR120 ));
VAR109 VAR19( .VAR6( VAR76 ), .VAR25( VAR112 ));
VAR109 VAR118( .VAR6( VAR113 ), .VAR25( VAR29 ));
VAR109 VAR60( .VAR6( VAR16 ), .VAR25( VAR88 ));
VAR109 VAR67( .VAR6( VAR35 ), .VAR25( VAR131 ));
VAR109 VAR15( .VAR6( VAR1 ), .VAR25( VAR46 ));
VAR109 VAR124( .VAR6( VAR116 ), .VAR25( VAR119 ));
VAR109 VAR110( .VAR6( VAR108 ), .VAR25( VAR61 ));
VAR109 VAR36( .VAR6( VAR50 ), .VAR25( VAR64 ));
VAR109 VAR20( .VAR6( VAR22 ), .VAR25( VAR66 ));
VAR109 VAR32( .VAR6( VAR48 ), .VAR25( VAR26 ));
VAR109 VAR93( .VAR6( VAR92 ), .VAR25( VAR34 ));
endmodule
|
apache-2.0
|
Siliciumer/DOS-Mario-FPGA
|
sources/keyboard.v
| 17,139 |
module MODULE1(
input wire VAR16, input wire VAR28, input wire VAR4,
input wire rst,
output reg VAR7,
output reg VAR26,
output reg VAR44,
output reg VAR25,
output reg VAR35,
output reg VAR10,
output reg VAR31,
output reg VAR23,
output reg VAR12,
output reg VAR34,
output reg VAR33
);
localparam reg [7:0] VAR40 = 8'h11;
localparam reg [7:0] VAR15 = 8'h14;
localparam reg [7:0] VAR6 = 8'h29;
localparam reg [7:0] VAR39 = 8'h12;
localparam reg [7:0] VAR46 = 8'h59;
localparam reg [7:0] VAR3 = 8'h76;
localparam reg [7:0] VAR2 = 8'h72;
localparam reg [7:0] VAR18 = 8'h6B;
localparam reg [7:0] VAR38 = 8'h74;
localparam reg [7:0] VAR22 = 8'hF0;
localparam reg [7:0] VAR11 = 8'hE0;
localparam reg [7:0] VAR47 = 8'h1F;
localparam reg [7:0] VAR1 = 8'h27;
localparam reg [7:0] VAR49 = 8'h2F;
reg VAR9;
reg VAR37;
reg VAR19;
reg VAR36;
reg VAR5;
reg VAR27;
reg VAR20;
reg VAR42;
reg VAR29;
reg VAR13;
reg VAR21;
reg VAR32;
reg VAR43;
reg read; reg [11:0] VAR8; reg VAR14; reg [10:0] VAR48; reg VAR17; reg [7:0] VAR41; reg VAR30; reg [3:0]VAR50; reg VAR45;
reg VAR24;
always @(posedge VAR16 or posedge rst) begin
if(rst) begin
VAR8 <= 0;
end
else begin
end
if (read) VAR8 <= VAR8 + 1; else VAR8 <= 0; end
end
always @(posedge VAR16 or posedge rst) begin
if(rst) begin
VAR14 <= 1;
read <= 0;
VAR17 <= 0;
VAR48 <= 11'b00000000000;
VAR50 <= 0;
VAR30 <= 0;
end
else begin
if (VAR28 != VAR14) begin if (!VAR28) begin read <= 1; VAR17 <= 0; VAR48[10:0] <= {VAR4, VAR48[10:1]}; VAR50 <= VAR50 + 1; end
end
else if (VAR50 == 11) begin VAR50 <= 0;
read <= 0; VAR30 <= 1; if (!VAR48[10] || VAR48[0] || !(VAR48[1]^VAR48[2]^VAR48[3]^VAR48[4]
^VAR48[5]^VAR48[6]^VAR48[7]^VAR48[8]
^VAR48[9]))
VAR17 <= 1;
end
else
VAR17 <= 0;
end
else begin VAR30 <= 0; if (VAR50 < 11 && VAR8 >= 4000) begin VAR50 <= 0; read <= 0; end
end
VAR14 <= VAR28; end
end
always @(posedge VAR16 or posedge rst) begin
if(rst) begin
VAR41 <= 8'd0;
end
else begin
if (VAR30) begin if (VAR17) begin VAR41 <= 8'd0; end
else begin
VAR41 <= VAR48[8:1]; end end else VAR41 <= 8'd0; end
end
always @(posedge VAR16 or posedge rst) begin
if(rst) begin
VAR45<= 0;
VAR24 <= 0;
VAR7 <= 0;
VAR26 <= 0;
VAR44 <= 0;
VAR25 <= 0;
VAR10 <= 0;
VAR31 <= 0;
VAR35 <= 0;
VAR23 <= 0;
VAR12 <= 0;
VAR34 <= 0;
VAR33 <= 0;
end
else begin
VAR45<= VAR9;
VAR24 <= VAR37;
VAR7 <= VAR19;
VAR26 <= VAR36;
VAR44 <= VAR5;
VAR25 <= VAR27;
VAR10 <= VAR42;
VAR31 <= VAR29;
VAR35 <= VAR20;
VAR23 <= VAR13;
VAR12 <= VAR21;
VAR34 <= VAR32;
VAR33 <= VAR43;
end
end
always @* begin
if(VAR17 == 0) begin
if(VAR41 == VAR11) begin
VAR9= 1;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR22) begin
VAR9= VAR45;
VAR37 = 1;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR45) begin
if(VAR41 == VAR38) begin
if(VAR24) begin
VAR43 = 0;
end
else begin
VAR43 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR36 = VAR26;
VAR27 = VAR25;
end
else if(VAR41 == VAR40) begin
if(VAR24) begin
VAR36 = 0;
end
else begin
VAR36 = 1;
end
VAR37 = 0;
VAR9= 0;
VAR27 = VAR25;
VAR43 = VAR33;
end
else if(VAR41 == VAR15) begin
if(VAR24) begin
VAR27 = 0;
end
else begin
VAR27 = 1;
end
VAR37 = 0;
VAR9= 0;
VAR36 = VAR26;
VAR43 = VAR33;
end
else begin
VAR9= VAR45;
VAR37 = VAR24;
VAR36 = VAR26;
VAR27 = VAR25;
VAR43 = VAR33;
end
VAR19 = VAR7;
VAR5 = VAR44;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
end
else if(VAR41 == VAR2) begin
if(VAR24) begin
VAR21 = 0;
end
else begin
VAR21 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR18) begin
if(VAR24) begin
VAR32 = 0;
end
else begin
VAR32 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR43 = VAR33;
end
else if(VAR41 == VAR40) begin
if(VAR24) begin
VAR19 = 0;
end
else begin
VAR19 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR15) begin
if(VAR24) begin
VAR5 = 0;
end
else begin
VAR5 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR39) begin
if(VAR24) begin
VAR42 = 0;
end
else begin
VAR42 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR46) begin
if(VAR24) begin
VAR29 = 0;
end
else begin
VAR29 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR6) begin
if(VAR24) begin
VAR20 = 0;
end
else begin
VAR20 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else if(VAR41 == VAR3) begin
if(VAR24) begin
VAR13 = 0;
end
else begin
VAR13 = 1;
end
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
else begin
VAR9= VAR45;
VAR37 = VAR24;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
end
else begin
VAR9= 0;
VAR37 = 0;
VAR19 = VAR7;
VAR36 = VAR26;
VAR5 = VAR44;
VAR27 = VAR25;
VAR42 = VAR10;
VAR29 = VAR31;
VAR20 = VAR35;
VAR13 = VAR23;
VAR21 = VAR12;
VAR32 = VAR34;
VAR43 = VAR33;
end
end
endmodule
|
mit
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/KOA_1c.v
| 5,688 |
module MODULE1
(
input wire clk,
input wire rst,
input wire VAR6,
input wire [VAR3-1:0] VAR19,
input wire [VAR3-1:0] VAR11,
output wire [2*VAR3-1:0] VAR25
);
wire [1:0] VAR30;
wire [3:0] VAR7;
assign VAR30 = 2'b00;
assign VAR7 = 4'b0000;
wire [VAR3/2-1:0] VAR28;
wire [VAR3/2:0] VAR34;
wire [VAR3/2-3:0] VAR31;
wire [VAR3/2-4:0] VAR32;
reg [4*(VAR3/2)+2:0] VAR12;
reg [4*(VAR3/2)-1:0] VAR21;
assign VAR28 = {(VAR3/2){1'b0}};
assign VAR34 = {(VAR3/2+1){1'b0}};
assign VAR31 = {(VAR3/2-4){1'b0}}; assign VAR32 = {(VAR3/2-5){1'b0}};
localparam VAR8 = VAR3/2;
generate
case (VAR3%2)
0:begin : VAR13
reg [VAR3/2:0] VAR1;
reg [VAR3/2:0] VAR27;
wire [VAR3-1:0] VAR35;
wire [VAR3-1:0] VAR16;
wire [VAR3+1:0] VAR22;
reg [2*(VAR3/2+2)-1:0] VAR15;
reg [VAR3+1:0] VAR24;
VAR33 #(.VAR3(VAR3/2)) VAR10(
.VAR19(VAR19[VAR3-1:VAR3-VAR3/2]),
.VAR11(VAR11[VAR3-1:VAR3-VAR3/2]),
.VAR4(VAR35)
);
VAR33 #(.VAR3(VAR3/2)) VAR20(
.VAR19(VAR19[VAR3-VAR3/2-1:0]),
.VAR11(VAR11[VAR3-VAR3/2-1:0]),
.VAR4(VAR16)
);
VAR33 #(.VAR3((VAR3/2)+1)) VAR18 (
.VAR19(VAR1),
.VAR11(VAR27),
.VAR4(VAR22)
);
always @* begin : VAR14
VAR1 <= (VAR19[((VAR3/2)-1):0] + VAR19[(VAR3-1) -: VAR3/2]);
VAR27 <= (VAR11[((VAR3/2)-1):0] + VAR11[(VAR3-1) -: VAR3/2]);
VAR24 <= (VAR22 - VAR35 - VAR16);
VAR12[4*(VAR3/2):0] <= {VAR31,VAR24,VAR28} + {VAR35,VAR16};
end
VAR2 #(.VAR26(4*(VAR3/2))) VAR29 ( .clk(clk),
.rst(rst),
.VAR36(VAR6),
.VAR5(VAR12[4*(VAR3/2)-1:0]),
.VAR17({VAR25})
);
end
1:begin : VAR23
reg [VAR3/2+1:0] VAR1;
reg [VAR3/2+1:0] VAR27;
wire [2*(VAR3/2)-1:0] VAR35;
wire [2*(VAR3/2+1)-1:0] VAR16;
wire [2*(VAR3/2+2)-1:0] VAR22;
reg [2*(VAR3/2+2)-1:0] VAR15;
reg [VAR3+4-1:0] VAR24;
VAR33 #(.VAR3(VAR3/2)) VAR10(
.clk(clk),
.VAR19(VAR19[VAR3-1:VAR3-VAR3/2]),
.VAR11(VAR11[VAR3-1:VAR3-VAR3/2]),
.VAR4(VAR35)
);
VAR33 #(.VAR3(VAR3/2+1)) VAR20(
.clk(clk),
.VAR19(VAR19[VAR3-VAR3/2-1:0]),
.VAR11(VAR11[VAR3-VAR3/2-1:0]),
.VAR4(VAR16)
);
VAR33 #(.VAR3(VAR3/2+2)) VAR18 (
.clk(clk),
.VAR19(VAR1),
.VAR11(VAR27),
.VAR4(VAR22)
);
always @* begin : VAR9
VAR1 <= (VAR19[VAR3-VAR3/2-1:0] + VAR19[VAR3-1:VAR3-VAR3/2]);
VAR27 <= VAR11[VAR3-VAR3/2-1:0] + VAR11[VAR3-1:VAR3-VAR3/2];
VAR24 <= (VAR22 - VAR35 - VAR16);
VAR12[4*(VAR3/2)+2:0]<= {VAR32,VAR24,VAR34} + {VAR35,VAR16};
end
VAR2 #(.VAR26(4*(VAR3/2)+2)) VAR29 ( .clk(clk),
.rst(rst),
.VAR36(VAR6),
.VAR5(VAR12[2*VAR3-1:0]),
.VAR17({VAR25})
);
end
endcase
endgenerate
endmodule
|
gpl-3.0
|
hakehuang/pycpld
|
ips/ip/spi_slave_cpha0/spi_slave_cpha0.v
| 2,925 |
module MODULE1(
clk,VAR2,VAR9,VAR12,VAR11,VAR8
);
input clk;
input VAR8;
input VAR2,VAR9,VAR11;
output VAR12;
reg VAR10;
reg[2:0] VAR17;
reg[2:0] VAR16;
reg[1:0] VAR4;
reg[2:0] VAR1;
reg[7:0] VAR3;
reg VAR15; reg [7:0] VAR14;
wire VAR7;
wire VAR6;
wire VAR13;
wire VAR5;
always @(posedge clk or negedge VAR8)begin
if(!VAR8)
VAR17 <= 3'h0;
end
else
VAR17 <= {VAR17[1:0],VAR2};
end
assign VAR6 = (VAR17[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign VAR13 = (VAR17[2:1] == 2'b10) ? 1'b1 : 1'b0;
always @(posedge clk or negedge VAR8)begin
if(!VAR8)
VAR16 <= 3'h0;
end
else
VAR16 <= {VAR16[1:0],VAR11};
end
assign VAR7 = (~VAR16[1]) ? 1'b1 : 1'b0;
always @(posedge clk or negedge VAR8)begin
if(!VAR8)
VAR4 <= 2'h0;
end
else
VAR4 <={VAR4[0],VAR9};
end
assign VAR5 = VAR4[1];
always @(posedge clk or negedge VAR8)begin
if(!VAR8)begin
VAR1 <= 3'b000;
VAR14 <= 8'h0;
end
else begin
if(~VAR7)
VAR1 <= 3'b000;
end
else begin
if(VAR6)begin
VAR1 <= VAR1 + 3'b001;
VAR14 <= {VAR14[6:0], VAR5};
end
else begin
VAR1 <= VAR1;
VAR14 <= VAR14;
end
end
end
end
always @(posedge clk or negedge VAR8) begin
if(!VAR8)
VAR15 <= 1'b0;
end
else
VAR15 <= VAR7 && VAR6 && (VAR1==3'b111);
end
assign VAR12 = VAR5;
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor2/sky130_fd_sc_hdll__nor2.blackbox.v
| 1,241 |
module MODULE1 (
VAR2,
VAR4,
VAR6
);
output VAR2;
input VAR4;
input VAR6;
supply1 VAR5;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Transform_dq_to_ABC.v
| 3,451 |
module MODULE1
(
VAR8,
VAR19,
VAR23,
VAR6,
VAR1,
VAR3,
VAR12
);
input signed [17:0] VAR8; input signed [17:0] VAR19; input signed [17:0] VAR23; input signed [17:0] VAR6; output signed [17:0] VAR1; output signed [17:0] VAR3; output signed [17:0] VAR12;
wire signed [17:0] VAR7; wire signed [17:0] VAR4; wire signed [17:0] VAR10; wire signed [17:0] VAR14; wire signed [17:0] VAR15;
VAR2 VAR16 (.VAR5(VAR8), .VAR22(VAR19), .VAR11(VAR23), .VAR9(VAR6), .VAR24(VAR7), .VAR13(VAR4) );
VAR18 VAR17 (.VAR24(VAR7), .VAR13(VAR4), .VAR21(VAR10), .VAR20(VAR14), .VAR25(VAR15) );
assign VAR1 = VAR10;
assign VAR3 = VAR14;
assign VAR12 = VAR15;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/probec_p/sky130_fd_sc_hd__probec_p.symbol.v
| 1,282 |
module MODULE1 (
input VAR1,
output VAR3
);
supply0 VAR4;
supply0 VAR2 ;
supply1 VAR6 ;
supply1 VAR5;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nor4/sky130_fd_sc_lp__nor4_2.v
| 2,275 |
module MODULE1 (
VAR1 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR4,
VAR3,
VAR2 ,
VAR8
);
output VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR8 ;
VAR10 VAR11 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR1,
VAR9,
VAR5,
VAR7,
VAR6
);
output VAR1;
input VAR9;
input VAR5;
input VAR7;
input VAR6;
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR8 ;
VAR10 VAR11 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
1995parham/AlteraDE2-RS232
|
src/async-trasmitter.v
| 1,820 |
module MODULE1(
input clk,
input VAR2,
input [7:0] VAR13,
output VAR17,
output VAR16
);
parameter VAR15 = 50000000; parameter VAR6 = 9600;
generate
if(VAR15<VAR6*8 && (VAR15 % VAR6!=0)) VAR1 VAR4("VAR10 VAR9 with VAR19 VAR6 VAR8");
endgenerate
wire VAR18 = 1'b1;
wire VAR18;
VAR3 #(VAR15, VAR6) VAR11(.clk(clk), .enable(VAR16), .VAR12(VAR18));
reg [3:0] VAR7 = 0;
wire VAR5 = (VAR7==0);
assign VAR16 = ~VAR5;
reg [7:0] VAR14 = 0;
always @(posedge clk)
begin
if(VAR5 & VAR2)
VAR14 <= VAR13;
end
else
if(VAR7[3] & VAR18)
VAR14 <= (VAR14 >> 1);
case(VAR7)
4'b0000: if(VAR2) VAR7 <= 4'b0100;
4'b0100: if(VAR18) VAR7 <= 4'b1000; 4'b1000: if(VAR18) VAR7 <= 4'b1001; 4'b1001: if(VAR18) VAR7 <= 4'b1010; 4'b1010: if(VAR18) VAR7 <= 4'b1011; 4'b1011: if(VAR18) VAR7 <= 4'b1100; 4'b1100: if(VAR18) VAR7 <= 4'b1101; 4'b1101: if(VAR18) VAR7 <= 4'b1110; 4'b1110: if(VAR18) VAR7 <= 4'b1111; 4'b1111: if(VAR18) VAR7 <= 4'b0010; 4'b0010: if(VAR18) VAR7 <= 4'b0011; 4'b0011: if(VAR18) VAR7 <= 4'b0000; default: if(VAR18) VAR7 <= 4'b0000;
endcase
end
assign VAR17 = (VAR7 < 4) | (VAR7[3] & VAR14[0]);
endmodule
|
gpl-2.0
|
LordRafa/Sobel-FPGA
|
SISSources/V/SIS.v
| 6,964 |
module MODULE1 (
input clk,
input rst,
output wire[VAR52-1:0] VAR71,
input VAR39,
output wire[VAR59-1:0] VAR9,
output wire VAR10,
output wire[VAR18-1:0] VAR51,
output wire[VAR54-1:0] VAR83,
output wire[VAR52-1:0] VAR74,
input VAR88,
input VAR61,
output wire[VAR59-1:0] VAR87,
output wire VAR55,
input wire[VAR18-1:0] VAR65,
output wire[VAR56-1:0] VAR29,
input [23:0] VAR20,
input VAR4,
output wire VAR6,
input wire VAR21,
input wire VAR32,
input VAR46,
input VAR17,
input VAR41,
input VAR45,
output wire VAR80,
input[VAR18-1:0] VAR60,
input[VAR18-1:0] VAR25,
output wire[VAR18-1:0] VAR3,
input [1:0] VAR42
);
parameter VAR18 = 32;
parameter VAR52 = 32;
parameter VAR54 = 5;
parameter VAR56 = 6;
parameter VAR59 = 4; parameter VAR34 = 8;
wire [VAR18-1:0] VAR70;
wire VAR38;
wire VAR76;
wire [VAR52-1:0] VAR63;
wire [VAR18-1:0] VAR57;
wire VAR82;
wire VAR1;
wire [VAR34:0] VAR50;
wire [VAR18-1:0] VAR48;
wire VAR35;
wire VAR22;
wire [VAR52-1:0] VAR26;
wire [VAR18-1:0] VAR36;
wire VAR73;
wire VAR49;
wire [VAR34:0] VAR47;
wire [VAR18-1:0] VAR2;
wire VAR23;
wire [VAR18-1:0] VAR86;
wire VAR66;
wire [VAR18-1:0] VAR7;
wire VAR19;
wire VAR79;
wire VAR84;
wire VAR68;
reg [1:0] VAR43;
reg VAR72;
reg valid;
reg [VAR18-1:0] VAR62;
wire VAR75;
wire VAR24;
wire VAR30;
wire VAR15;
wire VAR40;
wire VAR31;
wire[VAR52-1:0] VAR11;
wire[VAR59-1:0] VAR27;
wire VAR12;
wire[VAR56-1:0] VAR33;
wire[VAR52-1:0] VAR13;
wire[VAR59-1:0] VAR8;
wire VAR5;
wire[VAR56-1:0] VAR16;
VAR58 VAR44 (
.clk(clk),
.rst(rst),
.VAR74(VAR11),
.VAR88(VAR88),
.VAR61(VAR61),
.VAR87(VAR27),
.VAR55(VAR12),
.VAR65(VAR65),
.VAR29(VAR33),
.VAR70(VAR70),
.VAR38(VAR38),
.VAR76(VAR76),
.VAR63(VAR63),
.VAR57(VAR57),
.VAR82(VAR82),
.VAR1(VAR1),
.VAR50(VAR50)
);
VAR28 VAR14 (
.clk(clk),
.rst(rst),
.VAR71(VAR71),
.VAR39(VAR39),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR51(VAR51),
.VAR83(VAR83),
.VAR48(VAR48),
.VAR35(VAR35),
.VAR22(VAR22),
.VAR26(VAR26),
.VAR36(VAR36),
.VAR73(VAR73),
.VAR49(VAR49),
.VAR47(VAR47)
);
VAR81 VAR77 (
.clk(clk),
.rst(rst),
.VAR20(VAR20),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR21(VAR21),
.VAR32(VAR32),
.VAR48(VAR2),
.VAR35(VAR23),
.VAR47(VAR47),
.VAR78(VAR15),
.VAR53(VAR75)
);
VAR37 VAR85 (
.clk(clk),
.rst(rst),
.VAR48(VAR86),
.VAR35(VAR66),
.VAR47(VAR47),
.VAR70(VAR70),
.VAR38(VAR79),
.VAR50(VAR50),
.VAR78(VAR40),
.VAR53(VAR24)
);
VAR69 VAR64 (
.clk(clk),
.rst(rst),
.VAR48(VAR7),
.VAR35(VAR19),
.VAR47(VAR47),
.VAR74(VAR13),
.VAR88(VAR88),
.VAR61(VAR61),
.VAR87(VAR8),
.VAR55(VAR5),
.VAR65(VAR65),
.VAR29(VAR16),
.VAR78(VAR31),
.VAR53(VAR30),
.VAR67(VAR60)
);
always @(negedge VAR46 or posedge VAR17) begin
if (VAR17 == 1) begin
VAR43 <= 2'd0;
end else begin
if ((VAR41 == 1) && (VAR45 == 1)) begin
VAR43 <= 2'd1;
end else begin
if ((VAR73 == 0) && (VAR72 == 1'd1)) begin
VAR43 <= 2'd2;
end else begin
if ((VAR43 == 2'd2) && (VAR72 == 1'd0)) begin
VAR43 <= 2'd3;
end else begin
if (VAR80 == 1) begin
VAR43 <= 2'd0;
end
end
end
end
end
end
always @(posedge clk) begin
if (VAR68 == 1) begin
VAR72 <= 1;
end else begin
if (VAR43 == 2'd2) begin
VAR72 <= 0;
end
end
end
assign VAR48 = (VAR42 == 0)? VAR2 : ((VAR42 == 1)? VAR86 : VAR7);
assign VAR35 = (VAR42 == 0)? VAR23 : ((VAR42 == 1)? VAR66 : VAR19);
assign VAR22 = VAR68;
assign VAR26 = VAR25;
assign VAR36 = 12000;
assign VAR38 = (VAR42 == 0)? 0 : ((VAR42 == 1)? VAR79 : VAR84);
assign VAR76 = VAR68;
assign VAR63 = VAR60;
assign VAR57 = (VAR42 != 1)? 0 : 12000;
assign VAR74 = (VAR42 == 1)? VAR11 : VAR13;
assign VAR87 = (VAR42 == 1)? VAR27 : VAR8;
assign VAR55 = (VAR42 == 1)? VAR12 : VAR5;
assign VAR29 = (VAR42 == 1)? VAR33 : VAR16;
assign VAR15 = (VAR68 == 1) & (VAR42 == 0);
assign VAR40 = (VAR68 == 1) & (VAR42 == 1);
assign VAR31 = (VAR68 == 1) & (VAR42 == 2);
assign VAR68 = ((VAR43 == 1) & (VAR72 == 0));
assign VAR80 = (VAR43 == 2'd3);
assign VAR3 = 0;
endmodule
|
gpl-2.0
|
scalable-networks/ext
|
uhd/fpga/usrp1/toplevel/mrfm/mrfm.v
| 6,841 |
module MODULE1
(output VAR40,
input VAR132,
input VAR65,
input VAR8,
inout VAR104,
input VAR1,
input VAR125,
output VAR98,
output VAR28,
input wire [11:0] VAR6,
input wire [11:0] VAR64,
input wire [11:0] VAR24,
input wire [11:0] VAR15,
output wire [13:0] VAR29,
output wire [13:0] VAR53,
output wire VAR113,
output wire VAR142,
input VAR96,
input wire [2:0] VAR83,
output wire [1:0] VAR50,
inout [15:0] VAR48,
inout wire [15:0] VAR18,
inout wire [15:0] VAR115,
inout wire [15:0] VAR129,
inout wire [15:0] VAR99
);
wire [15:0] VAR3,VAR19;
assign VAR40 = 1'b0;
wire VAR131;
wire VAR51 = VAR83[0];
wire VAR14 = VAR83[1];
wire VAR20 = VAR83[2];
wire VAR79, VAR109;
assign VAR50[0] = VAR79;
assign VAR50[1] = VAR109;
wire VAR134, VAR26;
wire VAR93 = VAR125;
assign VAR98 = VAR26;
assign VAR28 = VAR134;
wire [15:0] VAR141;
wire [3:0] VAR7,VAR90,VAR45,VAR77;
wire VAR111;
wire [3:0] VAR12;
wire [15:0] VAR78, VAR139;
wire VAR43, VAR105;
wire VAR25, VAR41, VAR116, VAR74;
wire [7:0] VAR128;
VAR92 VAR92( .VAR27(VAR141),.VAR80(VAR20),.VAR71(VAR48) );
assign VAR131 = VAR132;
wire [15:0] VAR32,VAR100,VAR34,VAR85;
wire [15:0] VAR54,VAR106,VAR137,VAR110,VAR81,VAR112,VAR36,VAR23;
wire VAR39;
wire [6:0] VAR103;
wire [31:0] VAR37;
VAR58 #(VAR86)
VAR136(.VAR72(VAR131),.reset(VAR25),.VAR22(VAR39),.addr(VAR103),.in(VAR37),
.out({VAR77,VAR45,VAR90,VAR7,VAR111,VAR101}));
reg [15:0] VAR120;
wire [15:0] VAR42;
wire [15:0] VAR126,VAR117,VAR55,VAR4;
wire VAR9;
wire VAR108;
always @(posedge VAR131)
VAR120 <= {VAR6[11],VAR6[11:0],3'b0};
wire [15:0] VAR135;
VAR70 #(0)VAR95(.VAR72(VAR131),.enable(1'b1),.reset(reset),.VAR88(VAR120),.VAR102(VAR135),
.VAR103(7'd0),.VAR37(32'd0),.VAR39(1'b0));
VAR38 VAR38(.VAR72(VAR131),.reset(VAR41),.enable(VAR105),
.VAR103(VAR103),.VAR37(VAR37),.VAR39(VAR39),
.VAR16(VAR135),.VAR118(VAR42),.VAR108(VAR108),
.VAR126(VAR126),.VAR117(VAR117),.VAR55(VAR55),.VAR4(VAR4),.VAR9(VAR9),
.VAR114( ));
wire VAR87 = 1'b0;
assign VAR113 = VAR87;
assign VAR142 = VAR87;
assign VAR29 = VAR42[15:2];
assign VAR12[0] = 1'b0;
VAR58 #(VAR10) VAR11(.VAR72(VAR131),.reset(VAR41),.VAR22(VAR39),.addr(VAR103),
.in(VAR37),.out(VAR12[3:1]));
VAR76 VAR76
( .VAR96(VAR96),.VAR119(VAR74),.reset(VAR41),
.VAR48(VAR141),.VAR14(VAR14),.VAR109(VAR109),.VAR26(VAR26),
.VAR57(VAR12),
.VAR47(VAR126),.VAR61(VAR117),
.VAR56(VAR55),.VAR133(VAR4),
.VAR67(16'd0),.VAR84(16'd0),
.VAR66(16'd0),.VAR33(16'd0),
.VAR52(VAR131),.VAR97(VAR9),
.VAR93(VAR93),
.VAR103(VAR103),.VAR37(VAR37),.VAR39(VAR39),
.VAR114(VAR139) );
wire [31:0] VAR60 = 32'd2;
VAR107 VAR107
( .VAR132(VAR131),.VAR63(VAR65),.VAR46(VAR8),
.enable(VAR1),.reset(1'b0),.VAR21(VAR104),
.VAR103(VAR103),.VAR37(VAR37),.VAR39(VAR39),
.VAR17({VAR129,VAR18}),.VAR82({VAR99,VAR115}),.VAR31(VAR60),.VAR5(32'hf0f0931a) );
wire [15:0] VAR73,VAR127,VAR123,VAR68;
VAR121 VAR121
( .VAR132(VAR131),.VAR96(VAR96),
.VAR103(VAR103),.VAR37(VAR37),.VAR39(VAR39),
.VAR116(VAR116),.VAR74(VAR74),
.VAR25(VAR25),.VAR41(VAR41),
.VAR43(VAR43),.VAR105(VAR105),
.VAR124(VAR124),.VAR13(VAR13),
.VAR94(VAR94),.VAR62(VAR62),
.VAR30(VAR30),.VAR140(VAR140),
.VAR2(VAR2),
.VAR44({15'd0,VAR108}), .VAR75({15'd0,VAR108}), .VAR89({15'd0,VAR108}), .VAR122({15'd0,VAR108}), .VAR73(VAR73),.VAR127(VAR127),.VAR123(VAR123),.VAR68(VAR68) );
VAR138 VAR138
(.VAR69(VAR18),.VAR91(VAR129),.VAR130(VAR115),.VAR35(VAR99),
.VAR73(VAR73),.VAR127(VAR127),.VAR123(VAR123),.VAR68(VAR68),
.VAR72(VAR131),.VAR59(VAR41),.VAR49(VAR25),
.VAR103(VAR103),.VAR37(VAR37),.VAR39(VAR39));
endmodule
|
gpl-2.0
|
chriz2600/DreamcastHDMI
|
Core/source/char_rom/char_rom.v
| 24,748 |
module MODULE1 (
input [11:0] address,
input VAR2,
output [7:0] VAR3
);
reg[7:0] VAR4;
reg[7:0] VAR1;
assign VAR3 = VAR1;
always @(posedge VAR2) begin
case (address)
endcase
VAR1 <= VAR4;
end
endmodule
|
mit
|
gtaylormb/fpga_nes
|
hw/zybo_vivado/zybo_vivado.runs/synth_1/nes_top_X99.v
| 3,823 |
module MODULE1(VAR1,VAR2);
input[5:0] VAR1;
output reg[7:0] VAR2;
always @(VAR1)
begin
case(VAR1)
6'b000000: VAR2 = 8'b01101101;
6'b000001: VAR2 = 8'b00100010;
6'b000010: VAR2 = 8'b00000010;
6'b000011: VAR2 = 8'b01000010;
6'b000100: VAR2 = 8'b10000001;
6'b000101: VAR2 = 8'b10100000;
6'b000110: VAR2 = 8'b10100000;
6'b000111: VAR2 = 8'b01100000;
6'b001000: VAR2 = 8'b01000100;
6'b001001: VAR2 = 8'b00001000;
6'b001010: VAR2 = 8'b00001000;
6'b001011: VAR2 = 8'b00000100;
6'b001100: VAR2 = 8'b00000101;
6'b001101: VAR2 = 8'b00000000;
6'b001110: VAR2 = 8'b00000000;
6'b001111: VAR2 = 8'b00000000;
6'b010000: VAR2 = 8'b10110110;
6'b010001: VAR2 = 8'b00001111;
6'b010010: VAR2 = 8'b00100111;
6'b010011: VAR2 = 8'b10000011;
6'b010100: VAR2 = 8'b10100010;
6'b010101: VAR2 = 8'b11100001;
6'b010110: VAR2 = 8'b11000100;
6'b010111: VAR2 = 8'b11001000;
6'b011000: VAR2 = 8'b10001100;
6'b011001: VAR2 = 8'b00010000;
6'b011010: VAR2 = 8'b00010100;
6'b011011: VAR2 = 8'b00010000;
6'b011100: VAR2 = 8'b00010010;
6'b011101: VAR2 = 8'b00000000;
6'b011110: VAR2 = 8'b00000000;
6'b011111: VAR2 = 8'b00000000;
6'b100000: VAR2 = 8'b11111111;
6'b100001: VAR2 = 8'b00110111;
6'b100010: VAR2 = 8'b01010011;
6'b100011: VAR2 = 8'b10110011;
6'b100100: VAR2 = 8'b11101111;
6'b100101: VAR2 = 8'b11101110;
6'b100110: VAR2 = 8'b11101101;
6'b100111: VAR2 = 8'b11110000;
6'b101000: VAR2 = 8'b11110100;
6'b101001: VAR2 = 8'b10011000;
6'b101010: VAR2 = 8'b01011001;
6'b101011: VAR2 = 8'b01011110;
6'b101100: VAR2 = 8'b00011111;
6'b101101: VAR2 = 8'b00000000;
6'b101110: VAR2 = 8'b00000000;
6'b101111: VAR2 = 8'b00000000;
6'b110000: VAR2 = 8'b11111111;
6'b110001: VAR2 = 8'b10111111;
6'b110010: VAR2 = 8'b11011011;
6'b110011: VAR2 = 8'b11011011;
6'b110100: VAR2 = 8'b11111011;
6'b110101: VAR2 = 8'b11111011;
6'b110110: VAR2 = 8'b11110110;
6'b110111: VAR2 = 8'b11111010;
6'b111000: VAR2 = 8'b11111110;
6'b111001: VAR2 = 8'b11111110;
6'b111010: VAR2 = 8'b10111110;
6'b111011: VAR2 = 8'b10111111;
6'b111100: VAR2 = 8'b10011111;
6'b111101: VAR2 = 8'b00000000;
6'b111110: VAR2 = 8'b00000000;
6'b111111: VAR2 = 8'b00000000;
endcase
end
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a211o/sky130_fd_sc_hdll__a211o.pp.blackbox.v
| 1,397 |
module MODULE1 (
VAR7 ,
VAR3 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR8,
VAR2,
VAR4 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR8;
input VAR2;
input VAR4 ;
input VAR9 ;
endmodule
|
apache-2.0
|
subailong/miaow
|
src/verilog/rtl/lsu/PS_flops_issue_lsu.v
| 2,589 |
module MODULE1 (
VAR7,
VAR37,
VAR36,
VAR5,
VAR23,
VAR21,
VAR11,
VAR38,
VAR33,
VAR26,
VAR17,
VAR4,
VAR31,
VAR32,
VAR18,
VAR19,
VAR10,
VAR34,
VAR40,
VAR1,
VAR24,
VAR35,
VAR15,
VAR9,
clk,
rst
);
input VAR7;
input [5:0] VAR37;
input [15:0] VAR36;
input [11:0] VAR5;
input [11:0] VAR23;
input [11:0] VAR21;
input [11:0] VAR11;
input [15:0] VAR38;
input [31:0] VAR33;
input [11:0] VAR26;
input [31:0] VAR17;
input [31:0] VAR4;
input clk;
input rst;
output VAR31;
output [5:0] VAR32;
output [15:0] VAR18;
output [11:0] VAR19;
output [11:0] VAR10;
output [11:0] VAR34;
output [11:0] VAR40;
output [15:0] VAR1;
output [31:0] VAR24;
output [11:0] VAR35;
output [31:0] VAR15;
output [31:0] VAR9;
VAR2 VAR20(
.VAR22(VAR31),
.VAR16(VAR7),
.clk(clk),
.rst(rst)
);
VAR30 VAR6[5:0](
.VAR22(VAR32),
.VAR16(VAR37),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR29[15:0](
.VAR22(VAR18),
.VAR16(VAR36),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR12[11:0](
.VAR22(VAR19),
.VAR16(VAR5),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR14[11:0](
.VAR22(VAR10),
.VAR16(VAR23),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR27[11:0](
.VAR22(VAR34),
.VAR16(VAR21),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR8[11:0](
.VAR22(VAR40),
.VAR16(VAR11),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR3[15:0](
.VAR22(VAR1),
.VAR16(VAR38),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR39[31:0](
.VAR22(VAR24),
.VAR16(VAR33),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR13[11:0](
.VAR22(VAR35),
.VAR16(VAR26),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR25[31:0](
.VAR22(VAR15),
.VAR16(VAR17),
.clk(clk),
.rst(rst),
.en(VAR7)
);
VAR30 VAR28[31:0](
.VAR22(VAR9),
.VAR16(VAR4),
.clk(clk),
.rst(rst),
.en(VAR7)
);
endmodule
|
bsd-3-clause
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_2xcmp.v
| 1,937 |
module MODULE1(VAR2 ,VAR1 );
output VAR2 ;
input VAR1 ;
assign VAR2 = VAR1;
endmodule
|
gpl-2.0
|
adbrant/zuma-fpga
|
verilog/platforms/altera/init_config.v
| 6,505 |
module MODULE1 (
address,
VAR27,
VAR38);
input [12:0] address;
input VAR27;
output [31:0] VAR38;
tri1 VAR27;
wire [31:0] VAR16;
wire [31:0] VAR38 = VAR16[31:0];
VAR3 VAR32 (
.VAR43 (address),
.VAR37 (VAR27),
.VAR13 (VAR16),
.VAR39 (1'b0),
.VAR41 (1'b0),
.VAR53 (1'b1),
.VAR7 (1'b0),
.VAR24 (1'b0),
.VAR34 (1'b1),
.VAR9 (1'b1),
.VAR19 (1'b1),
.VAR4 (1'b1),
.VAR31 (1'b1),
.VAR51 (1'b1),
.VAR25 (1'b1),
.VAR14 ({32{1'b1}}),
.VAR23 (1'b1),
.VAR42 (),
.VAR45 (),
.VAR26 (1'b1),
.VAR46 (1'b1),
.VAR36 (1'b0),
.VAR18 (1'b0));
VAR32.VAR22 = "VAR11",
VAR32.VAR1 = "VAR20",
VAR32.VAR17 = "VAR20",
VAR32.VAR29 = "../output.VAR47"
VAR32.VAR29 = "../output.VAR33"
,
VAR32.VAR40 = "VAR52 VAR15",
VAR32.VAR28 = "VAR50=VAR5,VAR48=VAR11",
VAR32.VAR30 = "VAR3",
VAR32.VAR44 = 8192,
VAR32.VAR21 = "VAR10",
VAR32.VAR49 = "VAR11",
VAR32.VAR8 = "VAR2",
VAR32.VAR6 = 13,
VAR32.VAR35 = 32,
VAR32.VAR12 = 1;
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a21boi/sky130_fd_sc_ls__a21boi.pp.symbol.v
| 1,394 |
module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR8,
output VAR1 ,
input VAR6 ,
input VAR5,
input VAR3,
input VAR2
);
endmodule
|
apache-2.0
|
chriz2600/DreamcastHDMI
|
Core/source/configuration.v
| 1,041 |
module MODULE1(
input VAR6,
input VAR10 VAR5,
inout 480pactiven,
input VAR9,
input VAR8,
output reg VAR4,
output reg [3:0] VAR12,
output reg VAR3
);
reg VAR1 = 1'b0;
reg VAR13 = 1'b0;
reg 480pactivenreg = 1'VAR7;
assign 480pactiven = 480pactivenreg;
always @(posedge VAR6) begin
if (VAR1 != VAR13) begin
VAR3 <= 1'b1;
end else begin
VAR3 <= 1'b0;
end
if (VAR8 || VAR9 || ~480pactiven) begin
VAR12 <= VAR5.VAR2;
VAR4 <= 1'b0;
VAR13 <= 1'b1;
end else begin
VAR12 <= VAR5.VAR11;
VAR4 <= 1'b1;
VAR13 <= 1'b0;
end
480pactivenreg <= VAR9 ? 1'b0 : 1'VAR7;
VAR1 <= VAR13;
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/buf/sky130_fd_sc_ls__buf_1.v
| 1,993 |
module MODULE1 (
VAR7 ,
VAR2 ,
VAR4,
VAR6,
VAR5 ,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR4;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/mux2/sky130_fd_sc_ms__mux2.behavioral.v
| 1,604 |
module MODULE1 (
VAR11 ,
VAR12,
VAR9,
VAR6
);
output VAR11 ;
input VAR12;
input VAR9;
input VAR6 ;
supply1 VAR10;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
wire VAR4;
VAR8 VAR1 (VAR4, VAR12, VAR9, VAR6 );
buf VAR3 (VAR11 , VAR4);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/conb/sky130_fd_sc_ls__conb_1.v
| 2,042 |
module MODULE1 (
VAR3 ,
VAR5 ,
VAR4,
VAR8,
VAR7 ,
VAR6
);
output VAR3 ;
output VAR5 ;
input VAR4;
input VAR8;
input VAR7 ;
input VAR6 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
output VAR5;
supply1 VAR4;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR6 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
secworks/sha512
|
src/rtl/sha512_core.v
| 17,408 |
module MODULE1(
input wire clk,
input wire VAR28,
input wire VAR93,
input wire VAR99,
input wire [1 : 0] VAR48,
input wire VAR19,
input wire [31 : 0] VAR109,
input wire [1023 : 0] VAR12,
output wire ready,
output wire [511 : 0] VAR23,
output wire VAR1
);
localparam VAR62 = 79;
localparam VAR41 = 2'h0;
localparam VAR105 = 2'h1;
localparam VAR30 = 2'h2;
reg [63 : 0] VAR85;
reg [63 : 0] VAR52;
reg [63 : 0] VAR87;
reg [63 : 0] VAR96;
reg [63 : 0] VAR67;
reg [63 : 0] VAR35;
reg [63 : 0] VAR40;
reg [63 : 0] VAR43;
reg [63 : 0] VAR13;
reg [63 : 0] VAR54;
reg [63 : 0] VAR38;
reg [63 : 0] VAR74;
reg [63 : 0] VAR89;
reg [63 : 0] VAR33;
reg [63 : 0] VAR106;
reg [63 : 0] VAR76;
reg VAR70;
reg [63 : 0] VAR22;
reg [63 : 0] VAR65;
reg [63 : 0] VAR49;
reg [63 : 0] VAR92;
reg [63 : 0] VAR77;
reg [63 : 0] VAR79;
reg [63 : 0] VAR53;
reg [63 : 0] VAR110;
reg [63 : 0] VAR24;
reg [63 : 0] VAR31;
reg [63 : 0] VAR100;
reg [63 : 0] VAR88;
reg [63 : 0] VAR55;
reg [63 : 0] VAR5;
reg [63 : 0] VAR3;
reg [63 : 0] VAR37;
reg VAR34;
reg [6 : 0] VAR101;
reg [6 : 0] VAR15;
reg VAR50;
reg VAR17;
reg VAR51;
reg [31 : 0] VAR73;
reg [31 : 0] VAR113;
reg VAR103;
reg VAR14;
reg VAR29;
reg VAR98;
reg VAR10;
reg VAR78;
reg VAR81;
reg VAR42;
reg VAR97;
reg [1 : 0] VAR27;
reg [1 : 0] VAR69;
reg VAR95;
reg VAR45;
reg VAR36;
reg VAR102;
reg VAR111;
reg VAR107;
reg [63 : 0] VAR44;
reg [63 : 0] VAR68;
wire [63 : 0] VAR4;
reg VAR108;
reg VAR82;
wire [63 : 0] VAR16;
wire [63 : 0] VAR60;
wire [63 : 0] VAR26;
wire [63 : 0] VAR8;
wire [63 : 0] VAR66;
wire [63 : 0] VAR11;
wire [63 : 0] VAR46;
wire [63 : 0] VAR112;
wire [63 : 0] VAR64;
VAR7 VAR47(
.addr(VAR101),
.VAR32(VAR4)
);
VAR58 VAR57(
.VAR48(VAR48),
.VAR2(VAR60),
.VAR18(VAR26),
.VAR59(VAR8),
.VAR84(VAR66),
.VAR71(VAR11),
.VAR83(VAR46),
.VAR104(VAR112),
.VAR20(VAR64)
);
VAR86 VAR21(
.clk(clk),
.VAR28(VAR28),
.VAR12(VAR12),
.VAR93(VAR108),
.VAR99(VAR82),
.VAR90(VAR16)
);
assign ready = VAR98;
assign VAR23 = {VAR22, VAR49, VAR77, VAR53,
VAR24, VAR100, VAR55, VAR3};
assign VAR1 = VAR81;
always @ (posedge clk or negedge VAR28)
begin : VAR61
if (!VAR28)
begin
VAR85 <= 64'h0;
VAR87 <= 64'h0;
VAR67 <= 64'h0;
VAR40 <= 64'h0;
VAR13 <= 64'h0;
VAR38 <= 64'h0;
VAR89 <= 64'h0;
VAR106 <= 64'h0;
VAR22 <= 64'h0;
VAR49 <= 64'h0;
VAR77 <= 64'h0;
VAR53 <= 64'h0;
VAR24 <= 64'h0;
VAR100 <= 64'h0;
VAR55 <= 64'h0;
VAR3 <= 64'h0;
VAR73 <= 32'h0;
VAR98 <= 1'b1;
VAR81 <= 1'b0;
VAR101 <= 7'h0;
VAR27 <= VAR41;
end
else
begin
if (VAR70)
begin
VAR85 <= VAR52;
VAR87 <= VAR96;
VAR67 <= VAR35;
VAR40 <= VAR43;
VAR13 <= VAR54;
VAR38 <= VAR74;
VAR89 <= VAR33;
VAR106 <= VAR76;
end
if (VAR34)
begin
VAR22 <= VAR65;
VAR49 <= VAR92;
VAR77 <= VAR79;
VAR53 <= VAR110;
VAR24 <= VAR31;
VAR100 <= VAR88;
VAR55 <= VAR5;
VAR3 <= VAR37;
end
if (VAR50)
VAR101 <= VAR15;
if (VAR29)
VAR73 <= VAR113;
if (VAR78)
VAR98 <= VAR10;
if (VAR97)
VAR81 <= VAR42;
if (VAR95)
VAR27 <= VAR69;
end
end
always @*
begin : VAR25
VAR65 = 64'h0;
VAR92 = 64'h0;
VAR79 = 64'h0;
VAR110 = 64'h0;
VAR31 = 64'h0;
VAR88 = 64'h0;
VAR5 = 64'h0;
VAR37 = 64'h0;
VAR34 = 0;
if (VAR45)
begin
VAR65 = VAR60;
VAR92 = VAR26;
VAR79 = VAR8;
VAR110 = VAR66;
VAR31 = VAR11;
VAR88 = VAR46;
VAR5 = VAR112;
VAR37 = VAR64;
VAR34 = 1;
end
if (VAR36)
begin
VAR65 = VAR22 + VAR85;
VAR92 = VAR49 + VAR87;
VAR79 = VAR77 + VAR67;
VAR110 = VAR53 + VAR40;
VAR31 = VAR24 + VAR13;
VAR88 = VAR100 + VAR38;
VAR5 = VAR55 + VAR89;
VAR37 = VAR3 + VAR106;
VAR34 = 1;
end
end
always @*
begin : VAR80
reg [63 : 0] VAR63;
reg [63 : 0] VAR91;
VAR63 = {VAR13[13 : 0], VAR13[63 : 14]} ^
{VAR13[17 : 0], VAR13[63 : 18]} ^
{VAR13[40 : 0], VAR13[63 : 41]};
VAR91 = (VAR13 & VAR38) ^ ((~VAR13) & VAR89);
VAR44 = VAR106 + VAR63 + VAR91 + VAR4 + VAR16;
end
always @*
begin : VAR6
reg [63 : 0] VAR39;
reg [63 : 0] VAR56;
VAR39 = {VAR85[27 : 0], VAR85[63 : 28]} ^
{VAR85[33 : 0], VAR85[63 : 34]} ^
{VAR85[38 : 0], VAR85[63 : 39]};
VAR56 = (VAR85 & VAR87) ^ (VAR85 & VAR67) ^ (VAR87 & VAR67);
VAR68 = VAR39 + VAR56;
end
always @*
begin : VAR72
VAR52 = 64'h0;
VAR96 = 64'h0;
VAR35 = 64'h0;
VAR43 = 64'h0;
VAR54 = 64'h0;
VAR74 = 64'h0;
VAR33 = 64'h0;
VAR76 = 64'h0;
VAR70 = 0;
if (VAR102)
begin
if (VAR107)
begin
VAR52 = VAR60;
VAR96 = VAR26;
VAR35 = VAR8;
VAR43 = VAR66;
VAR54 = VAR11;
VAR74 = VAR46;
VAR33 = VAR112;
VAR76 = VAR64;
VAR70 = 1;
end
else
begin
VAR52 = VAR22;
VAR96 = VAR49;
VAR35 = VAR77;
VAR43 = VAR53;
VAR54 = VAR24;
VAR74 = VAR100;
VAR33 = VAR55;
VAR76 = VAR3;
VAR70 = 1;
end
end
if (VAR111)
begin
VAR52 = VAR44 + VAR68;
VAR96 = VAR85;
VAR35 = VAR87;
VAR43 = VAR67;
VAR54 = VAR40 + VAR44;
VAR74 = VAR13;
VAR33 = VAR38;
VAR76 = VAR89;
VAR70 = 1;
end
end
always @*
begin : VAR75
VAR15 = 7'h00;
VAR50 = 0;
if (VAR51)
begin
VAR15 = 7'h00;
VAR50 = 1;
end
if (VAR17)
begin
VAR15 = VAR101 + 1'b1;
VAR50 = 1;
end
end
always @*
begin : VAR9
VAR113 = 32'h0;
VAR29 = 0;
if (VAR103)
begin
VAR113 = 32'h0;
VAR29 = 1;
end
if (VAR14)
begin
VAR113 = VAR73 + 1'b1;
VAR29 = 1;
end
end
always @*
begin : VAR94
VAR45 = 1'b0;
VAR36 = 1'b0;
VAR102 = 1'b0;
VAR111 = 1'b0;
VAR107 = 1'b0;
VAR108 = 1'b0;
VAR82 = 1'b0;
VAR17 = 1'b0;
VAR51 = 1'b0;
VAR42 = 1'b0;
VAR97 = 1'b0;
VAR103 = 1'b0;
VAR14 = 1'b0;
VAR10 = 1'b0;
VAR78 = 1'b0;
VAR69 = VAR41;
VAR95 = 1'b0;
case (VAR27)
VAR41:
begin
if (VAR93)
begin
VAR10 = 1'b0;
VAR78 = 1'b1;
VAR103 = 1;
VAR45 = 1;
VAR108 = 1;
VAR102 = 1;
VAR107 = 1;
VAR51 = 1;
VAR42 = 0;
VAR97 = 1;
VAR69 = VAR105;
VAR95 = 1;
end
if (VAR99)
begin
VAR10 = 1'b0;
VAR78 = 1'b1;
VAR103 = 1;
VAR108 = 1;
VAR102 = 1;
VAR51 = 1;
VAR42 = 0;
VAR97 = 1;
VAR69 = VAR105;
VAR95 = 1;
end
end
VAR105:
begin
VAR82 = 1;
VAR111 = 1;
VAR17 = 1;
if (VAR101 == VAR62)
begin
VAR14 = 1;
VAR69 = VAR30;
VAR95 = 1;
end
end
VAR30:
begin
if (VAR19)
begin
if (VAR73 < VAR109)
begin
VAR108 = 1'b1;
VAR102 = 1'b1;
VAR51 = 1'b1;
VAR69 = VAR105;
VAR95 = 1'b1;
end
else
begin
VAR10 = 1'b1;
VAR78 = 1'b1;
VAR36 = 1'b1;
VAR42 = 1'b1;
VAR97 = 1'b1;
VAR69 = VAR41;
VAR95 = 1'b1;
end
end
else
begin
VAR10 = 1'b1;
VAR78 = 1'b1;
VAR36 = 1'b1;
VAR42 = 1'b1;
VAR97 = 1'b1;
VAR69 = VAR41;
VAR95 = 1'b1;
end
end
default:
begin
end
endcase end
endmodule
|
bsd-2-clause
|
SiLab-Bonn/basil
|
basil/firmware/modules/utils/bus_to_ip.v
| 1,114 |
module MODULE1
parameter VAR8 = 0,
parameter VAR6 = 0,
parameter VAR5 = 16,
parameter VAR11 = 8
)
(
input wire VAR10,
input wire VAR1,
input wire [VAR5-1:0] VAR14,
inout wire [VAR11-1:0] VAR9,
output wire VAR15,
output wire VAR2,
output wire [VAR5-1:0] VAR3,
output wire [VAR11-1:0] VAR12,
input wire [VAR11-1:0] VAR4
);
wire VAR7;
assign VAR7 = (VAR14 >= VAR8 && VAR14 <= VAR6);
assign VAR3 = VAR7 ? VAR14 - VAR8 : {VAR5{1'b0}};
assign VAR15 = VAR7 ? VAR10 : 1'b0;
assign VAR2 = VAR7 ? VAR1: 1'b0;
assign VAR12 = VAR9;
assign VAR9 = (VAR7 && VAR1) ? {VAR11{1'VAR13}} : (VAR7 ? VAR4 : {VAR11{1'VAR13}});
endmodule
|
bsd-3-clause
|
Obijuan/open-fpga-verilog-tutorial
|
tutorial/Alhambra_II/T24-uart-tx/scicad2.v
| 4,723 |
module MODULE1 (input wire clk, output wire VAR19 );
parameter VAR5 = VAR10;
parameter VAR15 = VAR14;
reg VAR8 = 0;
wire ready;
reg [7:0] VAR1;
reg [7:0] VAR12;
reg VAR26;
wire VAR13;
reg VAR11; reg VAR18;
always @(posedge clk)
VAR8 <= 1;
VAR4 #(.VAR5(VAR5))
VAR6 (
.clk(clk),
.VAR8(VAR8),
.VAR1(VAR12),
.VAR18(VAR18),
.ready(ready),
.VAR19(VAR19)
);
always @*
case (VAR25)
8'd0: VAR1 <= "VAR20";
8'd1: VAR1 <= "VAR2";
8'd2: VAR1 <= "VAR3";
8'd3: VAR1 <= "VAR27";
8'd4: VAR1 <= "!";
8'd5: VAR1 <= ".";
8'd6: VAR1 <= ".";
8'd7: VAR1 <= ".";
default: VAR1 <= ".";
endcase
always @*
VAR12 <= VAR1;
reg [2:0] VAR25;
always @(posedge clk)
if (VAR8 == 0)
VAR25 = 0;
else if (VAR11)
VAR25 = VAR25 + 1;
always @(posedge clk)
VAR26 <= VAR13;
VAR24 #(.VAR21(VAR15))
VAR22 ( .clk(clk),
.VAR9(VAR13)
);
localparam VAR16 = 0; localparam VAR23 = 2'd1; localparam VAR7 = 2'd2; localparam VAR17 = 3;
reg [1:0] state;
always @(posedge clk)
if (VAR8 == 0)
state <= VAR16;
else
case (state)
VAR16:
if (VAR26 == 1) state <= VAR23;
else state <= VAR16;
VAR23:
if (ready == 1) state <= VAR7;
else state <= VAR23;
VAR7:
if (VAR25 == 7) state <= VAR17;
else state <= VAR23;
VAR17:
if (ready == 1) state <= VAR16;
else state <= VAR17;
default:
state <= VAR16;
endcase
always @*
case (state)
VAR16: begin
VAR18 <= 0;
VAR11 <= 0;
end
VAR23: begin
VAR18 <= 1;
VAR11 <= 0;
end
VAR7: begin
VAR18 <= 0;
VAR11 <= 1;
end
VAR17: begin
VAR18 <= 0;
VAR11 <= 0;
end
default: begin
VAR18 <= 0;
VAR11 <= 0;
end
endcase
endmodule
|
gpl-2.0
|
MeshSr/onetswitch30
|
ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v
| 7,255 |
module MODULE1
parameter VAR1 = VAR9/8
)
( input [VAR9-1:0] VAR31,
input [VAR1-1:0] VAR16,
input VAR37,
output VAR14,
output reg [VAR9-1:0] VAR24,
output reg [VAR1-1:0] VAR21,
output reg VAR12,
input VAR30,
input reset,
input clk
);
localparam VAR44 = 5;
localparam VAR13 = 0,
VAR4 = 1,
VAR18 = 2,
VAR29 = 3,
VAR40 = 4;
wire [VAR9-1:0] VAR5;
wire [VAR1-1:0] VAR45;
reg [15:0] VAR28, VAR27;
reg [31:0] VAR34, VAR20;
reg [7:0] VAR19, VAR11;
reg [VAR44-1:0] VAR15, VAR10;
reg VAR23;
reg VAR22;
reg [VAR9-1:0] VAR35;
reg [VAR1-1:0] VAR46;
VAR7
VAR33
(.din ({VAR16, VAR31}), .VAR36 (VAR37), .VAR41 (VAR23), .dout ({VAR45, VAR5}),
.VAR43 (),
.VAR6 (),
.VAR3 (VAR38),
.VAR32 (VAR2),
.reset (reset),
.clk (clk)
);
assign VAR14 = !VAR38;
always @(*) begin
VAR15 = VAR10;
VAR23 = 0;
VAR22 = 0;
VAR35 = VAR5;
VAR46 = VAR45;
VAR28 = VAR27;
VAR34 = VAR20;
VAR19 = VAR11;
case (VAR10)
VAR13: begin
if (VAR30 && !VAR2) begin
VAR23 = 1;
if (VAR45 == VAR8 && VAR5[31]==0) begin
VAR22 = 0;
VAR28 = VAR5[15:0];
VAR15 = VAR4;
end
else if(VAR45 == VAR8 && VAR5[31]==1) begin
VAR22 = 0;
VAR28 = 0;
end
else begin
VAR22 = 1;
end
end
end
VAR4: begin
if (VAR30 && !VAR2) begin
VAR23 = 1;
VAR22 = 1;
if (VAR45 == VAR39) begin
VAR35[VAR26+15:VAR26]
= VAR5[VAR26+15:VAR26] + 4;
VAR35[VAR25+15:VAR25]
= VAR42((VAR5[VAR26+15:VAR26] + 4), 8);
end
else if (VAR45 == 0) begin
VAR15 = VAR18;
end
end
end
VAR18: begin
if (VAR30 && !VAR2) begin
VAR23 = 1;
VAR22 = 1;
if (VAR45 == 0) begin
VAR35 = {VAR5[63:32], VAR17, VAR27};
VAR34 = VAR5[31:0];
VAR19 = VAR45;
VAR15 = VAR29;
end
else begin
VAR15 = VAR13;
end
end
end
VAR29: begin
if (VAR30 && !VAR2) begin
VAR23 = 1;
VAR22 = 1;
VAR35 = {VAR20, VAR5[63:32]};
VAR34 = VAR5[31:0];
VAR19 = VAR45;
if (VAR45[7:4] != 0) begin
VAR46 = (VAR45 >> 4);
VAR15 = VAR13;
end
else if (VAR45[3:0] != 0) begin
VAR46 = 0;
VAR15 = VAR40;
end
end
end
VAR40: begin
if (VAR30) begin
VAR22 = 1;
VAR35 = {VAR20, 32'h0};
VAR46 = VAR11 << 4;
VAR15 = VAR13;
end
end default:VAR15=VAR13;
endcase end
always @(posedge clk) begin
if(reset) begin
VAR10 <= VAR13;
VAR12 <= 0;
VAR24 <= 0;
VAR21 <= 1;
VAR20 <= 0;
VAR11 <= 0;
VAR27 <= 0;
end
else begin
VAR10 <= VAR15;
VAR12 <= VAR22;
VAR24 <= VAR35;
VAR21 <= VAR46;
VAR20 <= VAR34;
VAR11 <= VAR19;
VAR27 <= VAR28;
end end
endmodule
|
lgpl-2.1
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.v
| 2,814 |
module MODULE1 (
VAR9 ,
VAR7 ,
VAR12 ,
VAR4 ,
VAR3 ,
VAR6,
VAR1,
VAR8 ,
VAR10 ,
VAR2 ,
VAR13 ,
VAR14
);
output VAR9 ;
input VAR7 ;
input VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR1;
input VAR8 ;
input VAR10 ;
input VAR2 ;
input VAR13 ;
input VAR14 ;
VAR5 VAR11 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR13(VAR13),
.VAR14(VAR14)
);
endmodule
module MODULE1 (
VAR9 ,
VAR7 ,
VAR12 ,
VAR4 ,
VAR3 ,
VAR6,
VAR1
);
output VAR9 ;
input VAR7 ;
input VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR1;
supply1 VAR8;
supply1 VAR10 ;
supply0 VAR2 ;
supply1 VAR13 ;
supply0 VAR14 ;
VAR5 VAR11 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
|
apache-2.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_hcmd_table_prp.v
| 3,777 |
module MODULE1 # (
parameter VAR26 = 45,
parameter VAR24 = 8
)
(
input clk,
input VAR14,
input [VAR24-1:0] VAR33,
input [VAR26-1:0] VAR12,
input [VAR24-1:0] VAR34,
output [VAR26-1:0] VAR17
);
localparam VAR32 = "7SERIES";
localparam VAR1 = "36Kb";
localparam VAR6 = 0;
localparam VAR21 = VAR26;
localparam VAR23 = VAR26;
localparam VAR8 = "VAR7";
localparam VAR19 = 8;
localparam VAR15 = 9;
localparam VAR11 = VAR15 - VAR24;
generate
wire [VAR15-1:0] VAR34;
wire [VAR15-1:0] VAR33;
wire [VAR11-1:0] VAR36 = 0;
if(VAR11 == 0) begin : VAR18
assign VAR34 = VAR34[VAR24-1:0];
assign VAR33 = VAR33[VAR24-1:0];
end
else begin
wire [VAR11-1:0] VAR36 = 0;
assign VAR34 = {VAR36, VAR34[VAR24-1:0]};
assign VAR33 = {VAR36, VAR33[VAR24-1:0]};
end
endgenerate
VAR13 #(
.VAR22 (VAR32),
.VAR29 (VAR1),
.VAR16 (VAR6),
.VAR9 (VAR21),
.VAR5 (VAR23),
.VAR2 (VAR8)
)
VAR38(
.VAR30 (VAR17),
.VAR20 (VAR12),
.VAR3 (VAR34),
.VAR25 (clk),
.VAR31 (1'b1),
.VAR28 (1'b1),
.VAR35 (1'b0),
.VAR4 ({VAR19{1'b1}}),
.VAR27 (VAR33),
.VAR37 (clk),
.VAR10 (VAR14)
);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/dlrbp/sky130_fd_sc_hd__dlrbp.functional.pp.v
| 2,072 |
module MODULE1 (
VAR2 ,
VAR14 ,
VAR10,
VAR6 ,
VAR8 ,
VAR7 ,
VAR9 ,
VAR12 ,
VAR11
);
output VAR2 ;
output VAR14 ;
input VAR10;
input VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR12 ;
input VAR11 ;
wire VAR17;
wire VAR5;
not VAR1 (VAR17 , VAR10 );
VAR15 VAR16 VAR3 (VAR5 , VAR6, VAR8, VAR17, , VAR7, VAR9);
buf VAR13 (VAR2 , VAR5 );
not VAR4 (VAR14 , VAR5 );
endmodule
|
apache-2.0
|
MeshSr/onetswitch20
|
ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/axis_control_if.v
| 3,729 |
module MODULE1
parameter VAR34 = 32,
parameter VAR9 = 32,
parameter VAR15 = 32,
parameter VAR32 = 32,
parameter VAR37 = 32,
parameter VAR7 = 32,
parameter VAR27 = 1
)
(
input VAR16,
input VAR43,
input VAR1,
input [11:0] VAR40,
input VAR26,
input VAR25,
input VAR29,
output VAR44,
input [VAR32-1 : 0] VAR22,
input [(VAR32/8)-1 : 0] VAR47,
input VAR8,
input VAR12,
input VAR19,
input VAR4,
output reg VAR30,
output reg [VAR37-1 : 0] VAR21,
output reg [(VAR37/8)-1 : 0] VAR17,
output reg VAR38,
input VAR3
);
reg [2:0] VAR48;
localparam VAR39 = 1,
VAR36 = 2,
VAR41 = 4;
reg [7:0] VAR18;
localparam VAR28 = 1,
VAR24 = 2,
VAR20 = 4,
VAR2 = 8,
VAR33 = 16,
VAR11 = 32;
assign VAR44 = 1'b1;
reg VAR5;
wire [11:0] VAR13;
generate
if(VAR27)begin
VAR42
.VAR31(5))
VAR14
(
.clk(VAR19),
.reset(!VAR4),
.din(VAR40),
.VAR10(VAR26),
.VAR23(VAR5),
.dout(VAR13),
.VAR6( ),
.VAR46(),
.VAR35(),
.VAR45( )
);
end
else begin
assign VAR13 = 12'hFFF;
end
endgenerate
always@(posedge VAR19)
if(!VAR4)
VAR5 <= 1'b0;
else if(VAR26)
VAR5 <= 1'b1;
else VAR5<=0;
always @(posedge VAR19)
if(!VAR4)begin
VAR48 <= VAR39;
VAR18 <= VAR28;
VAR30 <= 1'b0;
VAR21 <= 32'hFFFFFFFF;
VAR17 <= 4'hF;
VAR38 <= 1'b0;
end
else begin
VAR30 <= 1'b0;
VAR21 <= {24'h50000,VAR13};
VAR17 <= 4'hF;
VAR38 <= 1'b0;
case (VAR48)
VAR39: begin
if(VAR16) begin
VAR30 <= 1'b1;
VAR48 <= VAR36;
end
end
VAR36: begin
VAR30 <= 1'b1;
if(VAR3) begin
case (VAR18)
VAR28: VAR18 <= VAR24;
VAR24: VAR18 <= VAR20;
VAR20: VAR18 <= VAR2;
VAR2: VAR18 <= VAR33;
VAR33: begin
VAR18 <= VAR28;
VAR38 <= 1'b1;
VAR48 <= VAR41;
end
endcase
end
end
VAR41: begin
if(VAR1 && VAR43)VAR48 <= VAR39;
end
default:
VAR48<=VAR39;
endcase
end
endmodule
|
lgpl-2.1
|
alan4186/16bit-Processor
|
alu16.v
| 1,233 |
module MODULE1(
input clk,rst,
input [2:0] VAR2, input [15:0] VAR5,VAR1,
output reg [15:0] out, VAR3
);
always@(*) begin
if(rst == 1'b0) begin
out <= VAR4'd0;
end else begin
case(VAR2)
default: out <= VAR4'd0;
endcase
end
end
always@(posedge clk or negedge rst) begin
if(rst == 1'b0) begin
VAR3 = VAR4'd0;
end else begin
VAR3 <= out;
end
end
endmodule
|
mit
|
zeruniverse/pipelined_CPU
|
ISE project/control_unit.v
| 3,657 |
module MODULE1(VAR13,VAR29,VAR25,VAR7,VAR3,VAR11,VAR33,VAR1,VAR21,VAR10,VAR42,VAR45,VAR32,VAR35,VAR17,VAR40,VAR39,VAR15,VAR5,VAR37,VAR38,VAR34,VAR19,VAR36);
input wire [5:0] VAR25,VAR7;
input wire [4:0] VAR3,VAR11,VAR33,VAR10;
input wire VAR1,VAR21,VAR42,VAR45,VAR37;
output wire VAR29,VAR32,VAR35,VAR17,VAR40,VAR15,VAR5,VAR38,VAR34;
output wire [3:0] VAR39;
output wire [1:0] VAR13,VAR36,VAR19;
wire VAR20,VAR2,VAR16,VAR46,VAR4,VAR8,VAR44,VAR47,VAR28,VAR30,VAR18,VAR12,VAR23,VAR9,VAR14,VAR24,VAR6,VAR41,VAR26,VAR27,VAR43,VAR31,VAR22;
assign VAR20=~VAR25[5]&~VAR25[4]&~VAR25[3]&~VAR25[2]&~VAR25[1]&~VAR25[0];
assign VAR2=VAR20&VAR7[5]&~VAR7[4]&~VAR7[3]&VAR7[2]&~VAR7[1]&~VAR7[0];
assign VAR16=VAR20&VAR7[5]&~VAR7[4]&~VAR7[3]&VAR7[2]&~VAR7[1]&VAR7[0];
assign VAR46=VAR20&VAR7[5]&~VAR7[4]&~VAR7[3]&VAR7[2]&VAR7[1]&~VAR7[0];
assign VAR4=VAR20&VAR7[5]&~VAR7[4]&~VAR7[3]&~VAR7[2]&~VAR7[1]&~VAR7[0];
assign VAR8=VAR20&VAR7[5]&~VAR7[4]&~VAR7[3]&~VAR7[2]&VAR7[1]&~VAR7[0];
assign VAR14=VAR20&~VAR7[5]&~VAR7[4]&~VAR7[3]&~VAR7[2]&~VAR7[1]&~VAR7[0];
assign VAR24=VAR20&~VAR7[5]&~VAR7[4]&~VAR7[3]&~VAR7[2]&VAR7[1]&~VAR7[0];
assign VAR6=VAR20&~VAR7[5]&~VAR7[4]&~VAR7[3]&~VAR7[2]&VAR7[1]&VAR7[0];
assign VAR41=VAR20&~VAR7[5]&~VAR7[4]&VAR7[3]&~VAR7[2]&~VAR7[1]&~VAR7[0];
assign VAR26=~VAR25[5]&~VAR25[4]&~VAR25[3]&~VAR25[2]&VAR25[1]&~VAR25[0];
assign VAR27=~VAR25[5]&~VAR25[4]&~VAR25[3]&~VAR25[2]&VAR25[1]&VAR25[0];
assign VAR44=~VAR25[5]&~VAR25[4]&VAR25[3]&~VAR25[2]&~VAR25[1]&~VAR25[0];
assign VAR47=~VAR25[5]&~VAR25[4]&VAR25[3]&VAR25[2]&~VAR25[1]&~VAR25[0];
assign VAR28=~VAR25[5]&~VAR25[4]&VAR25[3]&VAR25[2]&~VAR25[1]&VAR25[0];
assign VAR30=~VAR25[5]&~VAR25[4]&VAR25[3]&VAR25[2]&VAR25[1]&~VAR25[0];
assign VAR18=VAR25[5]&~VAR25[4]&~VAR25[3]&~VAR25[2]&VAR25[1]&VAR25[0];
assign VAR12=VAR25[5]&~VAR25[4]&VAR25[3]&~VAR25[2]&VAR25[1]&VAR25[0];
assign VAR23=~VAR25[5]&~VAR25[4]&~VAR25[3]&VAR25[2]&~VAR25[1]&~VAR25[0];
assign VAR9=~VAR25[5]&~VAR25[4]&~VAR25[3]&VAR25[2]&~VAR25[1]&VAR25[0];
assign VAR43=~VAR25[5]&~VAR25[4]&VAR25[3]&VAR25[2]&VAR25[1]&VAR25[0];
assign VAR31=VAR4|VAR8|VAR2|VAR16|VAR46|VAR41|VAR44|VAR47|VAR28|VAR30|VAR18|VAR12|VAR23|VAR9;
assign VAR22=VAR4|VAR8|VAR2|VAR16|VAR46|VAR14|VAR24|VAR6|VAR12|VAR23|VAR9;
assign VAR39[3]=VAR6;
assign VAR39[2]=VAR8|VAR23|VAR9|VAR16|VAR28|VAR43|VAR24|VAR6;
assign VAR39[1]=VAR46|VAR30|VAR43|VAR14|VAR24|VAR6;
assign VAR39[0]=VAR2|VAR47|VAR16|VAR28|VAR14|VAR24|VAR6;
assign VAR29=~(VAR45&VAR42&(VAR10!=0)&(VAR31&(VAR10==VAR3)|VAR22&(VAR10==VAR11)));
assign VAR32=(VAR4|VAR8|VAR2|VAR16|VAR46|VAR14|VAR24|VAR6|VAR44|VAR47|VAR28|VAR30|VAR18|VAR43|VAR27)&VAR29;
assign VAR17=VAR12&VAR29;
assign VAR35=VAR18;
assign VAR40=VAR27;
assign VAR15=VAR44|VAR47|VAR28|VAR30|VAR43|VAR12|VAR18;
assign VAR5=VAR14|VAR24|VAR6;
assign VAR38=VAR43|VAR44|VAR47|VAR28|VAR30|VAR18;
assign VAR34=VAR43|VAR44|VAR18|VAR12|VAR23|VAR9;
assign VAR36=(VAR45&(VAR10!=0)&(VAR10==VAR3)&~VAR42)?2'b01:((VAR21&(VAR33!=0)&(VAR33==VAR3)&~VAR1)?2'b10:((VAR21&(VAR33!=0)&(VAR33==VAR3)&VAR1)?2'b11:2'b00));
assign VAR19=(VAR45&(VAR10!=0)&(VAR10==VAR11)&~VAR42)?2'b01:((VAR21&(VAR33!=0)&(VAR33==VAR11)&~VAR1)?2'b10:((VAR21&(VAR33!=0)&(VAR33==VAR11)&VAR1)?2'b11:2'b00));
assign VAR13[1]=VAR26|VAR41|VAR27;
assign VAR13[0]=(VAR23&VAR37)|(VAR9&~VAR37)|VAR26|VAR27;
endmodule
|
gpl-3.0
|
intelligenttoasters/CPC2.0
|
FPGA/Quartus/DE10-old/HAL.v
| 5,184 |
module MODULE1(
input VAR5,
input VAR17,
input VAR7,
inout VAR42,
inout VAR9,
inout VAR52,
inout VAR3,
inout VAR40,
inout VAR47,
output VAR20,
output VAR48,
output [23:0] VAR46,
output VAR2,
input VAR37,
output VAR83,
output [14: 0] VAR8,
output [ 2: 0] VAR1,
output VAR77,
output VAR50,
output VAR22,
output VAR57,
output VAR6,
output [ 3: 0] VAR25,
inout [31: 0] VAR15,
inout [ 3: 0] VAR38,
inout [ 3: 0] VAR51,
output VAR14,
output VAR43,
output VAR76,
input VAR12,
output VAR41,
input [1:0] VAR69,
output [7:0] VAR63,
input [3:0] VAR49
);
wire VAR21;
wire [7:0] VAR80;
wire [7:0] VAR61,VAR67,VAR55;
wire [79:0] VAR60;
wire VAR29, VAR18, VAR11;
assign VAR63 = {7'd0,VAR21};
assign VAR46 = {VAR61,VAR67,VAR55};
VAR4 VAR72(
.VAR13(VAR5),
.VAR27(),
.VAR39(),
.VAR56(),
.VAR16(),
.VAR65(), .VAR79(), .VAR66(VAR11),
.VAR53(VAR42),
.VAR44(VAR9),
.VAR63(VAR21),
.VAR26(VAR83),
.VAR73(VAR2),
.VAR33(VAR48),
.VAR71(VAR20),
.VAR61(VAR61),
.VAR67(VAR67),
.VAR55(VAR55),
.VAR64(VAR18), .VAR82(VAR29), .VAR75(VAR60)
);
VAR81 VAR68 (
.VAR62 (VAR5), .VAR74 (VAR8), .VAR30 (VAR1), .VAR35 (VAR22), .VAR36 (VAR50), .VAR28 (VAR57), .VAR32 (VAR6), .VAR19 (VAR43), .VAR10 (VAR77), .VAR58 (VAR41), .VAR24 (VAR76), .VAR23 (VAR15), .VAR84 (VAR51), .VAR45 (VAR38), .VAR70 (VAR14), .VAR78 (VAR25), .VAR59 (VAR12), .VAR64 (VAR29), .VAR82 (VAR18), .VAR34 (VAR5),
.VAR31 (VAR11),
.VAR54 (VAR60) );
endmodule
|
gpl-3.0
|
tommythorn/yari
|
shared/rtl/yari-core/stage_I.v
| 14,757 |
module MODULE1(input wire VAR27
,input wire VAR33 ,input wire VAR61 ,input wire [31:0] VAR47
,input wire VAR91
,input wire [31:0] VAR59
,input VAR71
,output reg [29:0] VAR80
,output reg VAR5 = 0
,input [31:0] VAR79
,input VAR8
,output reg VAR39 = 0 ,output wire [31:0] VAR102
,output reg VAR60 = 0
,output wire [31:0] VAR18
,output reg VAR19 = 0 ,output reg [31:0] VAR64 = 0 ,output reg [31:0] VAR65 = 0 ,output reg [31:0] VAR87
,output reg [31:0] VAR42 = 0
);
parameter VAR105 = 0;
parameter VAR52 = VAR53 + 2;
parameter VAR70 = VAR54 + VAR52;
parameter VAR51 = VAR48 + VAR70; parameter VAR56 = VAR75 - VAR70;
wire [31:0] VAR12 = VAR61 ? VAR47 : VAR65;
assign VAR102 = VAR12;
assign VAR18 = VAR64;
wire [VAR56-1:0] VAR57, VAR44, VAR35, VAR58;
wire [31:0] VAR34, VAR21, VAR20, VAR10;
wire [(1 << VAR48)-1:0]
VAR15 = {VAR58 == VAR82, VAR35 == VAR82,
VAR44 == VAR82, VAR57 == VAR82};
reg [VAR48-1:0] VAR24;
always @* casex (VAR15)
'b0001: VAR24 = 0;
'b0010: VAR24 = 1;
'b0100: VAR24 = 2;
'b1000: VAR24 = 3;
default:VAR24 = 2'VAR100;
endcase
always @* VAR87 = ((VAR15[0] ? VAR34 : 0) |
(VAR15[1] ? VAR21 : 0) |
(VAR15[2] ? VAR20 : 0) |
(VAR15[3] ? VAR10 : 0));
always @* casex (VAR15)
'b0001: VAR19 = VAR60;
'b0010: VAR19 = VAR60;
'b0100: VAR19 = VAR60;
'b1000: VAR19 = VAR60;
default:VAR19 = 0;
endcase
parameter VAR31 = 0;
parameter VAR11 = 1;
parameter VAR104 = 2;
parameter VAR89 = 3;
parameter VAR6 = 4;
reg [VAR48-1:0] VAR67 = 0;
reg [31:0] state = VAR31;
reg [VAR53-1:0] VAR103;
reg [VAR54-1:0] VAR49;
reg [VAR56-1:0] VAR96;
reg [3:0] VAR74 = 0;
wire [VAR56-1:0] VAR25 = 1'd0;
wire [VAR56-1:0] VAR13 = ~VAR25;
VAR76 #(VAR56,VAR54,"VAR4")
VAR7(.VAR27(VAR27), .VAR22(VAR83), .VAR40(VAR57),
.VAR81(VAR49), .VAR95(VAR96),
.VAR85(VAR74[0]));
VAR76 #(VAR56,VAR54,"VAR73")
VAR1(.VAR27(VAR27), .VAR22(VAR83), .VAR40(VAR44),
.VAR81(VAR49), .VAR95(VAR96),
.VAR85(VAR74[1]));
VAR76 #(VAR56,VAR54,"VAR93")
VAR62(.VAR27(VAR27), .VAR22(VAR83), .VAR40(VAR35),
.VAR81(VAR49), .VAR95(VAR96),
.VAR85(VAR74[2]));
VAR76 #(VAR56,VAR54,"VAR50")
VAR17(.VAR27(VAR27), .VAR22(VAR83), .VAR40(VAR58),
.VAR81(VAR49), .VAR95(VAR96),
.VAR85(VAR74[3]));
VAR76 #(32,VAR51 - 4,"VAR41")
VAR41(.VAR27(VAR27),
.VAR22({VAR83,VAR32}), .VAR40(VAR34),
.VAR81({VAR86,VAR103}),
.VAR95(VAR79),
.VAR85(VAR67 == 0 && state == VAR11 && VAR8));
VAR76 #(32,VAR51 - 4,"VAR88")
VAR88(.VAR27(VAR27),
.VAR22({VAR83,VAR32}), .VAR40(VAR21),
.VAR81({VAR86,VAR103}),
.VAR95(VAR79),
.VAR85(VAR67 == 1 && state == VAR11 && VAR8));
VAR76 #(32,VAR51 - 4,"VAR101")
VAR101(.VAR27(VAR27),
.VAR22({VAR83,VAR32}), .VAR40(VAR20),
.VAR81({VAR86,VAR103}),
.VAR95(VAR79),
.VAR85(VAR67 == 2 && state == VAR11 && VAR8));
VAR76 #(32,VAR51 - 4,"VAR45")
VAR45(.VAR27(VAR27),
.VAR22({VAR83,VAR32}), .VAR40(VAR10),
.VAR81({VAR86,VAR103}),
.VAR95(VAR79),
.VAR85(VAR67 == 3 && state == VAR11 && VAR8));
reg [32:0] VAR37 = 0;
reg VAR16 = 0;
reg [31:0] VAR97 = 0;
reg [31:0] VAR38 = 0;
always @(posedge VAR27) begin
VAR37 <= {VAR37[31:0], ~VAR37[32] ^ VAR37[19]};
VAR74 <= 0;
if (VAR91) begin
VAR16 <= 1;
VAR97 <= VAR59;
VAR38 <= VAR47; end
if (~VAR71 & VAR5) begin
VAR5 <= 0;
end
case (state)
VAR31:
if (VAR91 | VAR16) begin
", ,
VAR91 ? VAR59 : VAR97,
VAR91 ? VAR98 : VAR69);
VAR65 <= VAR91 ? VAR59 : VAR97;
VAR39 <= 0;
VAR60 <= 0;
state <= VAR89;
end else if (|VAR15 | ~VAR60) begin
if (VAR105)
VAR64 <= VAR12;
VAR65 <= VAR12 + 4;
VAR60 <= VAR39 | VAR61;
if (VAR61)
VAR39 <= 1;
if (VAR105 & VAR61)
end else begin
VAR42 <= VAR42 + 1;
VAR65 <= VAR61 ? VAR47 : VAR64;
VAR60 <= 0;
VAR103 <= 0;
VAR80 <= {VAR64[VAR75-1:VAR52],
{(VAR52 - 2){1'd0}}};
VAR5 <= 1;
VAR23("%05d VAR29 begin VAR28 VAR92 %8x", ,
{VAR64[VAR75-1:VAR52],{(VAR52){1'd0}}});
if (VAR105 & VAR61)
state <= VAR11;
end
VAR89: begin
VAR64 <= VAR65;
state <= VAR6;
end
VAR6: begin
if (|VAR15) begin
VAR2 VAR9 VAR63 VAR66 VAR92 VAR36 %VAR77 (VAR43 %VAR26), VAR78 %VAR77 VAR14 %VAR26 %VAR26 %VAR26 %VAR26",
,
VAR12, VAR99, VAR24, VAR15, VAR83,
VAR57, VAR44, VAR35, VAR58);
end else
VAR2 VAR94 (VAR43 %VAR26), VAR78 %VAR77 VAR14 %VAR26 %VAR26 %VAR26 %VAR26",
,
VAR12, VAR99, VAR15, VAR83,
VAR57, VAR44, VAR35, VAR58);
VAR49 <= VAR69;
VAR96 <= VAR13;
VAR74 <= VAR15;
VAR65 <= VAR38;
VAR39 <= 1;
VAR16 <= 0;
state <= VAR104; end
VAR11: begin
if (VAR61) begin
if (VAR105)
VAR65 <= VAR47;
end
if (VAR8) begin
VAR23("%05d VAR29 {%1d,%1d,%1d} <- %8x", ,
VAR67, VAR86, VAR103, VAR79);
VAR103 <= VAR103 + 1'd1;
if (&VAR103) begin
VAR23("%05d VAR90 VAR46%VAR77[%VAR77] <- %VAR26", ,
VAR67, VAR86, VAR82);
VAR49 <= VAR86;
VAR96 <= VAR82;
VAR74 <= 4'd1 << VAR67;
VAR67 <= VAR37[1:0];
state <= VAR104;
end
end else
if (VAR105)
end
VAR104: begin
if (VAR61) begin
if (VAR105)
VAR65 <= VAR47;
end
state <= VAR31;
end
endcase
if (!VAR91 & !VAR16 & VAR33 & ~VAR61) begin
if (VAR105)
VAR39 <= 0;
VAR60 <= 0;
end
if (VAR105) begin
if (state == VAR31)
VAR23(
"%05d VAR29 VAR68: VAR55 %VAR26 (valid %VAR77) <%VAR26;%VAR26;%VAR26> -- VAR55 %VAR26 (valid %VAR77) VAR3 %VAR26 -- VAR55 %VAR26 VAR72 %VAR26 VAR30 %VAR77 | %VAR77: %VAR26 %VAR26 %VAR26 %VAR26",
,
VAR12, VAR39, VAR24, VAR83, VAR84,
VAR64, VAR19, VAR15,
VAR64, VAR87, VAR19,
VAR24, VAR34, VAR21, VAR20, VAR10);
end
end
endmodule
|
gpl-2.0
|
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