repo_name
stringlengths 6
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stringlengths 4
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| size
int64 1.02k
768k
| content
stringlengths 15
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| license
stringclasses 14
values |
|---|---|---|---|---|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_bCMD_manager.v
| 7,984 |
module MODULE1
(
parameter VAR32 = 4
)
(
VAR4 ,
VAR21 ,
VAR13 ,
VAR24 ,
VAR16 ,
VAR20 ,
VAR33 ,
VAR30 ,
VAR17 ,
VAR14 ,
VAR6 ,
VAR23 ,
VAR10 ,
VAR2 ,
VAR15 ,
VAR19 ,
VAR5 ,
VAR22 ,
VAR25 ,
VAR28
);
input VAR4 ;
input VAR21 ;
input [VAR32 - 1:0] VAR13 ;
input VAR24 ;
input VAR16 ;
input VAR20 ;
input VAR33 ;
input VAR30 ;
input [5:0] VAR17 ;
input [4:0] VAR14 ;
input [4:0] VAR6 ;
output [5:0] VAR23 ;
output [4:0] VAR10 ;
output [4:0] VAR2 ;
input VAR15 ;
output VAR19 ;
output VAR5 ;
output VAR22 ;
input VAR25 ;
output [VAR32 - 1:0] VAR28 ;
parameter VAR26 = 5; parameter VAR27 = 5'b00001;
parameter VAR29 = 5'b00010; parameter VAR9 = 5'b00100; parameter VAR8 = 5'b01000; parameter VAR18 = 5'b10000;
reg [VAR26-1:0] VAR11 ;
reg [VAR26-1:0] VAR31 ;
reg [3:0] VAR3 ;
wire VAR1 ;
reg [VAR32 - 1:0] VAR7 ;
reg VAR12 ;
assign VAR1 = (VAR3[3:0] == 4'b0100);
always @ (posedge VAR4, posedge VAR21) begin
if (VAR21) begin
VAR11 <= VAR27;
end else begin
VAR11 <= VAR31;
end
end
always @ ( * ) begin
case (VAR11)
VAR27: begin
VAR31 <= VAR29;
end
VAR29: begin
VAR31 <= (VAR24)? VAR9:VAR29;
end
VAR9: begin
VAR31 <= (VAR16)? ((VAR20)? VAR29:VAR18):VAR8;
end
VAR8: begin
VAR31 <= (VAR16)? ((VAR20)? VAR29:VAR18):VAR8;
end
VAR18: begin
VAR31 <= (VAR1)? VAR29:VAR18;
end
default:
VAR31 <= VAR29;
endcase
end
always @ (posedge VAR4, posedge VAR21) begin
if (VAR21) begin
VAR7[VAR32 - 1:0] <= 0;
VAR12 <= 0;
VAR3[3:0] <= 0;
end else begin
case (VAR31)
VAR27: begin
VAR7[VAR32 - 1:0] <= 0;
VAR12 <= 0;
VAR3[3:0] <= 0;
end
VAR29: begin
VAR7[VAR32 - 1:0] <= 0;
VAR12 <= 0;
VAR3[3:0] <= 0;
end
VAR9: begin
VAR7[VAR32 - 1:0] <= VAR13[VAR32 - 1:0];
VAR12 <= 1'b1;
VAR3[3:0] <= 4'b0000;
end
VAR8: begin
VAR7[VAR32 - 1:0] <= VAR7[VAR32 - 1:0];
VAR12 <= 1'b1;
VAR3[3:0] <= 4'b0000;
end
VAR18: begin
VAR7[VAR32 - 1:0] <= VAR7[VAR32 - 1:0];
VAR12 <= 1'b1;
VAR3[3:0] <= VAR3[3:0] + 1'b1;
end
endcase
end
end
assign VAR19 = (~VAR12) & (VAR33 | (VAR15 & (~VAR33)));
assign VAR5 = (~VAR12) & (~VAR30) & (VAR15) & (~VAR33);
assign VAR22 = (~VAR12) & (~VAR30) & (VAR25) & (~VAR33);
assign VAR23[5:0] = (VAR33)? (6'b111110):(VAR17[5:0]);
assign VAR10[4:0] = (VAR33)? (5'b00101):(VAR14[4:0]);
assign VAR2[4:0] = (VAR33)? (5'b00101):(VAR6[4:0]);
assign VAR28[VAR32 - 1:0] = VAR7[VAR32 - 1:0];
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o41ai/sky130_fd_sc_ls__o41ai.blackbox.v
| 1,375 |
module MODULE1 (
VAR2 ,
VAR10,
VAR7,
VAR6,
VAR1,
VAR9
);
output VAR2 ;
input VAR10;
input VAR7;
input VAR6;
input VAR1;
input VAR9;
supply1 VAR4;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule
|
apache-2.0
|
freecores/zet86
|
rtl-model/regfile.v
| 3,125 |
module MODULE1 (
output [15:0] VAR25,
output [15:0] VAR6,
output [15:0] VAR12,
output [15:0] VAR30,
output [15:0] VAR20,
output [15:0] VAR15,
output [15:0] VAR11,
output [15:0] VAR4,
output [15:0] VAR18,
output [15:0] VAR24,
input [31:0] VAR21,
output [15:0] VAR27,
output reg [8:0] VAR7,
input wr,
input VAR26,
input VAR1,
input clk,
input rst,
input [ 3:0] VAR2,
input [ 3:0] VAR23,
input [ 3:0] VAR13,
input [ 3:0] VAR3,
input [ 1:0] VAR5,
input [ 8:0] VAR29,
input VAR8,
input VAR16,
input VAR17,
input VAR14,
output VAR31,
input VAR22
);
reg [15:0] VAR28[15:0];
wire [7:0] VAR19, VAR9, VAR10;
assign VAR25 = VAR28[0];
assign VAR6 = VAR28[2];
assign VAR12 = VAR28[5];
assign VAR30 = VAR28[6];
assign VAR20 = VAR28[8];
assign VAR15 = (VAR16 & ~VAR2[3]) ? { {8{VAR19[7]}}, VAR19} : VAR28[VAR2];
assign VAR19 = VAR2[2] ? VAR28[VAR2[1:0]][15:8] : VAR28[VAR2][7:0];
assign VAR11 = (VAR17 & ~VAR23[3]) ? { {8{VAR9[7]}}, VAR9} : VAR28[VAR23];
assign VAR9 = VAR23[2] ? VAR28[VAR23[1:0]][15:8] : VAR28[VAR23][7:0];
assign VAR4 = (VAR14 & ~VAR13[3]) ? { {8{VAR10[7]}}, VAR10} : VAR28[VAR13];
assign VAR10 = VAR13[2] ? VAR28[VAR13[1:0]][15:8] : VAR28[VAR13][7:0];
assign VAR27 = VAR28[{2'b10,VAR5}];
assign VAR18 = VAR28[9];
assign VAR31 = (VAR3==4'd1) ? (VAR21==16'd0) : (VAR28[1]==16'd0);
assign VAR24 = VAR28[15];
always @(posedge clk)
if (rst) begin
VAR28[0] <= 16'd0; VAR28[1] <= 16'd0;
VAR28[2] <= 16'd0; VAR28[3] <= 16'd0;
VAR28[4] <= 16'd0; VAR28[5] <= 16'd0;
VAR28[6] <= 16'd0; VAR28[7] <= 16'd0;
VAR28[8] <= 16'd0; VAR28[9] <= 16'hf000;
VAR28[10] <= 16'd0; VAR28[11] <= 16'd0;
VAR28[12] <= 16'd0; VAR28[13] <= 16'd0;
VAR28[14] <= 16'd0; VAR28[15] <= 16'hfff0;
VAR7 <= 9'd0;
end else
begin
if (wr) begin
if (VAR8 | VAR3[3:2]==2'b10)
VAR28[VAR3] <= VAR8 ? VAR21[15:0] : {{8{VAR21[7]}},VAR21[7:0]};
end
else if (VAR3[3]~^VAR3[2]) VAR28[VAR3][7:0] <= VAR21[7:0];
end
else VAR28[{2'b0,VAR3[1:0]}][15:8] <= VAR21[7:0];
end
if (VAR26) VAR7 <= VAR29;
if (VAR1) VAR28[4'd2] <= VAR21[31:16];
if (VAR22) VAR28[14] <= VAR24;
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/bufbuf/sky130_fd_sc_hd__bufbuf.behavioral.pp.v
| 1,768 |
module MODULE1 (
VAR3 ,
VAR11 ,
VAR7,
VAR12,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR11 ;
input VAR7;
input VAR12;
input VAR2 ;
input VAR8 ;
wire VAR4 ;
wire VAR6;
buf VAR1 (VAR4 , VAR11 );
VAR10 VAR5 (VAR6, VAR4, VAR7, VAR12);
buf VAR9 (VAR3 , VAR6 );
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_fast_cfg_init_cntr.v
| 3,209 |
module MODULE1 #(
parameter VAR4 = 8,
parameter VAR2 = 8'hA5,
parameter VAR1 = 1
) (
input clk,
input rst,
output reg [VAR4-1:0] VAR3
);
always @(posedge clk) begin
if(rst) begin
end else begin
if(VAR3 != VAR2) begin
end
end
end
endmodule
|
lgpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature_KOA/Design-of-various-multiplier-Array-Booth-Wallace--master/Booth multiplier/Booth multiplier.v
| 5,499 |
module MODULE1(VAR72,VAR24,VAR81);
input [7:0] VAR72,VAR24;
output [15:0] VAR81;
wire [7:0] VAR47,VAR86,VAR120,VAR28,VAR124,VAR79,VAR39,VAR63;
wire [9:0] VAR84,VAR71,VAR94;
wire [7:0] VAR51;
wire [3:0] VAR42,VAR25,VAR69;
wire [10:0] VAR85,VAR96;
wire [8:0] VAR110,VAR103;
wire [9:0] VAR83;
wire [11:0] VAR60;
wire [3:0] VAR15,VAR44;
xor VAR111(VAR44[0],VAR42[0],VAR25[0]);
and VAR99(VAR15[0],VAR44[0],VAR69[0]);
xor VAR5(VAR44[1],VAR42[1],VAR25[1]);
and VAR56(VAR15[1],VAR44[1],VAR69[1]);
xor VAR76(VAR44[2],VAR42[2],VAR25[2]);
and VAR61(VAR15[2],VAR44[2],VAR69[2]);
xor VAR36(VAR44[3],VAR42[3],VAR25[3]);
and VAR52(VAR15[3],VAR44[3],VAR69[3]);
MODULE4 MODULE31(VAR42[0],VAR25[0],VAR69[0],VAR24[1],VAR24[0],1'b0);
MODULE4 MODULE37(VAR42[1],VAR25[1],VAR69[1],VAR24[3],VAR24[2],VAR24[1]);
MODULE4 MODULE4(VAR42[2],VAR25[2],VAR69[2],VAR24[5],VAR24[4],VAR24[3]);
MODULE4 MODULE9(VAR42[3],VAR25[3],VAR69[3],VAR24[7],VAR24[6],VAR24[5]);
MODULE2 MODULE59(VAR72[0],VAR69[0],VAR15[0],VAR42[0],VAR25[0],VAR69[0],VAR81[0],VAR47[0],VAR124[0]);
MODULE2 MODULE61(VAR72[1],VAR47[0],VAR124[0],VAR42[0],VAR25[0],VAR69[0],VAR81[1],VAR47[1],VAR124[1]);
MODULE2 MODULE3(VAR72[2],VAR47[1],VAR124[1],VAR42[0],VAR25[0],VAR69[0],VAR51[0],VAR47[2],VAR124[2]);
MODULE2 MODULE29(VAR72[3],VAR47[2],VAR124[2],VAR42[0],VAR25[0],VAR69[0],VAR51[1],VAR47[3],VAR124[3]);
MODULE2 MODULE13(VAR72[4],VAR47[3],VAR124[3],VAR42[0],VAR25[0],VAR69[0],VAR51[2],VAR47[4],VAR124[4]);
MODULE2 MODULE49(VAR72[5],VAR47[4],VAR124[4],VAR42[0],VAR25[0],VAR69[0],VAR51[3],VAR47[5],VAR124[5]);
MODULE2 MODULE23(VAR72[6],VAR47[5],VAR124[5],VAR42[0],VAR25[0],VAR69[0],VAR51[4],VAR47[6],VAR124[6]);
MODULE2 MODULE52(VAR72[7],VAR47[6],VAR124[6],VAR42[0],VAR25[0],VAR69[0],VAR51[5],VAR47[7],VAR124[7]);
xor VAR6(VAR60[0],VAR47[7],VAR124[7]);
and VAR40(VAR60[1],VAR25[0],VAR47[7]);
and VAR14(VAR60[2],VAR42[0],VAR60[0]);
or o1(VAR51[6],VAR60[1],VAR60[2]);
not VAR16(VAR51[7],VAR51[6]);
MODULE2 MODULE25(VAR72[0],VAR69[1],VAR15[1],VAR42[1],VAR25[1],VAR69[1],VAR84[0],VAR86[0],VAR79[0]);
MODULE2 MODULE62(VAR72[1],VAR86[0],VAR79[0],VAR42[1],VAR25[1],VAR69[1],VAR84[1],VAR86[1],VAR79[1]);
MODULE2 MODULE14(VAR72[2],VAR86[1],VAR79[1],VAR42[1],VAR25[1],VAR69[1],VAR84[2],VAR86[2],VAR79[2]);
MODULE2 MODULE56(VAR72[3],VAR86[2],VAR79[2],VAR42[1],VAR25[1],VAR69[1],VAR84[3],VAR86[3],VAR79[3]);
MODULE2 MODULE8(VAR72[4],VAR86[3],VAR79[3],VAR42[1],VAR25[1],VAR69[1],VAR84[4],VAR86[4],VAR79[4]);
MODULE2 MODULE68(VAR72[5],VAR86[4],VAR79[4],VAR42[1],VAR25[1],VAR69[1],VAR84[5],VAR86[5],VAR79[5]);
MODULE2 MODULE55(VAR72[6],VAR86[5],VAR79[5],VAR42[1],VAR25[1],VAR69[1],VAR84[6],VAR86[6],VAR79[6]);
MODULE2 MODULE45(VAR72[7],VAR86[6],VAR79[6],VAR42[1],VAR25[1],VAR69[1],VAR84[7],VAR86[7],VAR79[7]);
xor VAR12(VAR60[3],VAR86[7],VAR79[7]);
and VAR43(VAR60[4],VAR25[1],VAR86[7]);
and VAR53(VAR60[5],VAR42[1],VAR60[3]);
or o2(VAR84[8],VAR60[4],VAR60[5]);
not VAR70(VAR84[9],VAR84[8]);
MODULE2 MODULE41(VAR72[0],VAR69[2],VAR15[2],VAR42[2],VAR25[2],VAR69[2],VAR71[0],VAR120[0],VAR39[0]);
MODULE2 MODULE67(VAR72[1],VAR120[0],VAR39[0],VAR42[2],VAR25[2],VAR69[2],VAR71[1],VAR120[1],VAR39[1]);
MODULE2 MODULE22(VAR72[2],VAR120[1],VAR39[1],VAR42[2],VAR25[2],VAR69[2],VAR71[2],VAR120[2],VAR39[2]);
MODULE2 MODULE26(VAR72[3],VAR120[2],VAR39[2],VAR42[2],VAR25[2],VAR69[2],VAR71[3],VAR120[3],VAR39[3]);
MODULE2 MODULE54(VAR72[4],VAR120[3],VAR39[3],VAR42[2],VAR25[2],VAR69[2],VAR71[4],VAR120[4],VAR39[4]);
MODULE2 MODULE30(VAR72[5],VAR120[4],VAR39[4],VAR42[2],VAR25[2],VAR69[2],VAR71[5],VAR120[5],VAR39[5]);
MODULE2 MODULE18(VAR72[6],VAR120[5],VAR39[5],VAR42[2],VAR25[2],VAR69[2],VAR71[6],VAR120[6],VAR39[6]);
MODULE2 MODULE6(VAR72[7],VAR120[6],VAR39[6],VAR42[2],VAR25[2],VAR69[2],VAR71[7],VAR120[7],VAR39[7]);
xor VAR107(VAR60[6],VAR120[7],VAR39[7]);
and VAR104(VAR60[7],VAR25[2],VAR120[7]);
and VAR115(VAR60[8],VAR42[2],VAR60[6]);
or o3(VAR71[8],VAR60[7],VAR60[8]);
not VAR130(VAR71[9],VAR71[8]);
MODULE2 MODULE33(VAR72[0],VAR69[3],VAR15[3],VAR42[3],VAR25[3],VAR69[3],VAR94[0],VAR28[0],VAR63[0]);
MODULE2 MODULE65(VAR72[1],VAR28[0],VAR63[0],VAR42[3],VAR25[3],VAR69[3],VAR94[1],VAR28[1],VAR63[1]);
MODULE2 MODULE27(VAR72[2],VAR28[1],VAR63[1],VAR42[3],VAR25[3],VAR69[3],VAR94[2],VAR28[2],VAR63[2]);
MODULE2 MODULE38(VAR72[3],VAR28[2],VAR63[2],VAR42[3],VAR25[3],VAR69[3],VAR94[3],VAR28[3],VAR63[3]);
MODULE2 MODULE12(VAR72[4],VAR28[3],VAR63[3],VAR42[3],VAR25[3],VAR69[3],VAR94[4],VAR28[4],VAR63[4]);
MODULE2 MODULE17(VAR72[5],VAR28[4],VAR63[4],VAR42[3],VAR25[3],VAR69[3],VAR94[5],VAR28[5],VAR63[5]);
MODULE2 MODULE21(VAR72[6],VAR28[5],VAR63[5],VAR42[3],VAR25[3],VAR69[3],VAR94[6],VAR28[6],VAR63[6]);
MODULE2 MODULE50(VAR72[7],VAR28[6],VAR63[6],VAR42[3],VAR25[3],VAR69[3],VAR94[7],VAR28[7],VAR63[7]);
xor VAR95(VAR60[9],VAR28[7],VAR63[7]);
and VAR58(VAR60[10],VAR25[3],VAR28[7]);
and VAR128(VAR60[11],VAR42[3],VAR60[9]);
or o4(VAR94[8],VAR60[10],VAR60[11]);
not VAR34(VAR94[9],VAR94[8]);
MODULE3 MODULE57(VAR84[0],VAR51[0],VAR85[0],VAR81[2]);
MODULE5 MODULE1(VAR84[1],VAR51[1],VAR85[0],VAR85[1],VAR81[3]);
MODULE5 MODULE53(VAR84[2],VAR51[2],VAR85[1],VAR85[2],VAR110[0]);
MODULE5 MODULE47(VAR84[3],VAR51[3],VAR85[2],VAR85[3],VAR110[1]);
MODULE5 MODULE28(VAR84[4],VAR51[4],VAR85[3],VAR85[4],VAR110[2]);
MODULE5 MODULE43(VAR84[5],VAR51[5],VAR85[4],VAR85[5],VAR110[3]);
MODULE5 MODULE51(VAR84[6],VAR51[6],VAR85[5],VAR85[6],VAR110[4]);
MODULE5 MODULE70(VAR84[7],VAR51[6],VAR85[6],VAR85[7],VAR110[5]);
MODULE5 MODULE32(VAR84[8],VAR51[6],VAR85[7],VAR85[8],VAR110[6]);
MODULE5 MODULE69(VAR84[9],VAR51[7],VAR85[8],VAR85[9],VAR110[7]);
MODULE3 MODULE7(VAR85[9],1'b1,VAR85[10],VAR110[8]);
MODULE3 MODULE16(VAR71[0],VAR110[0],VAR96[0],VAR81[4]);
MODULE5 MODULE39(VAR71[1],VAR110[1],VAR96[0],VAR96[1],VAR81[5]);
MODULE5 MODULE24(VAR71[2],VAR110[2],VAR96[1],VAR96[2],VAR103[0]);
MODULE5 MODULE44(VAR71[3],VAR110[3],VAR96[2],VAR96[3],VAR103[1]);
MODULE5 MODULE42(VAR71[4],VAR110[4],VAR96[3],VAR96[4],VAR103[2]);
MODULE5 MODULE35(VAR71[5],VAR110[5],VAR96[4],VAR96[5],VAR103[3]);
MODULE5 MODULE36(VAR71[6],VAR110[6],VAR96[5],VAR96[6],VAR103[4]);
MODULE5 MODULE5(VAR71[7],VAR110[7],VAR96[6],VAR96[7],VAR103[5]);
MODULE5 MODULE11(VAR71[8],VAR110[8],VAR96[7],VAR96[8],VAR103[6]);
MODULE5 MODULE19(VAR71[9],VAR85[10],VAR96[8],VAR96[9],VAR103[7]);
MODULE3 MODULE46(VAR96[9],1'b1,VAR96[10],VAR103[8]);
MODULE3 MODULE10(VAR94[0],VAR103[0],VAR83[0],VAR81[6]);
MODULE5 MODULE48(VAR94[1],VAR103[1],VAR83[0],VAR83[1],VAR81[7]);
MODULE5 MODULE2(VAR94[2],VAR103[2],VAR83[1],VAR83[2],VAR81[8]);
MODULE5 MODULE66(VAR94[3],VAR103[3],VAR83[2],VAR83[3],VAR81[9]);
MODULE5 MODULE40(VAR94[4],VAR103[4],VAR83[3],VAR83[4],VAR81[10]);
MODULE5 MODULE63(VAR94[5],VAR103[5],VAR83[4],VAR83[5],VAR81[11]);
MODULE5 MODULE64(VAR94[6],VAR103[6],VAR83[5],VAR83[6],VAR81[12]);
MODULE5 MODULE20(VAR94[7],VAR103[7],VAR83[6],VAR83[7],VAR81[13]);
MODULE5 MODULE15(VAR94[8],VAR103[8],VAR83[7],VAR83[8],VAR81[14]);
MODULE5 MODULE34(VAR94[9],VAR96[10],VAR83[8],VAR83[9],VAR81[15]);
endmodule
module MODULE4(VAR42,VAR25,VAR69,VAR4,VAR102,VAR75);
input VAR4,VAR102,VAR75;
output VAR42,VAR25,VAR69;
wire [1:0]VAR120;
xor VAR6(VAR42,VAR75,VAR102);
xor VAR12(VAR120[1],VAR4,VAR102);
not VAR16(VAR120[0],VAR42);
and VAR40(VAR25,VAR120[0],VAR120[1]);
assign VAR69=VAR4;
endmodule
module MODULE2(VAR6,VAR33,VAR12,VAR42,VAR25,VAR69,VAR81,VAR47,VAR117);
input VAR6,VAR33,VAR12,VAR69,VAR42,VAR25;
output VAR81,VAR47,VAR117;
wire [2:0] VAR120;
xor VAR132(VAR47,VAR6,VAR69);
and VAR40(VAR120[1],VAR47,VAR42);
and VAR20(VAR120[0],VAR33,VAR25);
or o0(VAR120[2],VAR120[1],VAR120[0]);
xor VAR108(VAR81,VAR120[2],VAR12);
and VAR14(VAR117,VAR120[2],VAR12);
endmodule
module MODULE3(VAR98,VAR73,VAR91,VAR46);
input VAR98,VAR73;
output VAR91,VAR46;
xor VAR6(VAR46,VAR98,VAR73);
and VAR40(VAR91,VAR98,VAR73);
endmodule
module MODULE5(VAR98,VAR73,VAR91,VAR100,VAR50);
input VAR98,VAR73,VAR91;
output VAR100,VAR50;
wire VAR72,VAR24,VAR44;
MODULE3 MODULE60(VAR98,VAR73,VAR72,VAR44);
MODULE3 MODULE58(VAR44,VAR91,VAR24,VAR50);
or o1(VAR100,VAR72,VAR24);
endmodule
|
gpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v
| 6,293 |
module MODULE1
parameter VAR48 = 100,
parameter VAR27 = 64,
parameter VAR28 = 4,
parameter VAR4 = 1,
parameter VAR32 = 64,
parameter VAR1 = 4
)
(
VAR6,
clk, rst, VAR40, VAR10, VAR17,
VAR11, VAR43, VAR8
);
input clk;
input rst;
input [VAR28-1:0] VAR40;
input [VAR4-1:0] VAR10;
wire [4:0] VAR23;
input [VAR28-1:0] VAR17;
input [VAR4-1:0] VAR11;
reg [4:0] VAR42;
generate
if (VAR28 >= 4) begin : VAR18
always @(posedge clk)
assign VAR23 = {VAR40[3:0], VAR10};
end
else begin : VAR31
always @(posedge clk)
VAR17[VAR28-1:0],
VAR11};
assign VAR23 = {{4-VAR28{1'b0}},
VAR40[VAR28-1:0],
VAR10};
end
endgenerate
input [2*VAR1*VAR27-1:0] VAR43;
reg [2*VAR1*VAR32-1:0] VAR13;
integer VAR16;
always @(VAR43)
for (VAR16=0; VAR16<2*VAR1; VAR16=VAR16+1)
VAR13[VAR16*VAR32+:VAR32] =
VAR43[VAR16*VAR27+:VAR32];
input VAR8;
localparam VAR37 = 2*VAR1*VAR32;
localparam VAR19 = (VAR37/6);
localparam VAR26 = VAR37 % 6;
localparam VAR30 = VAR19 + ((VAR26 == 0 ) ? 0 : 1);
localparam VAR24 = (VAR30*6);
wire [VAR24-1:0] VAR15;
generate
begin : VAR33
wire [VAR24-1:0] VAR20;
if (VAR26 == 0)
assign VAR20 = VAR13;
end
else
assign VAR20 = {{6-VAR26{1'b0}}, VAR13};
genvar VAR29;
for (VAR29=0; VAR29<VAR30; VAR29=VAR29+1) begin : VAR34
VAR35
.VAR39(64'h0000000000000000),
.VAR38(64'h0000000000000000),
.VAR9(64'h0000000000000000)
) VAR47 (
.VAR2(VAR15[((VAR29*6)+4)+:2]),
.VAR46(VAR15[((VAR29*6)+2)+:2]),
.VAR36(VAR15[((VAR29*6)+0)+:2]),
.VAR14(),
.VAR3(VAR20[((VAR29*6)+4)+:2]),
.VAR41(VAR20[((VAR29*6)+2)+:2]),
.VAR25(VAR20[((VAR29*6)+0)+:2]),
.VAR22(2'b0),
.VAR21(VAR42),
.VAR45(VAR42),
.VAR7(VAR42),
.VAR44(VAR23),
.VAR5(VAR8),
.VAR12(clk)
);
end end
endgenerate
output wire [2*VAR1*VAR32-1:0] VAR6;
assign VAR6 = VAR15[2*VAR1*VAR32-1:0];
endmodule
|
lgpl-3.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.behavioral.pp.v
| 1,383 |
module MODULE1( VAR2, VAR7, VAR1, VAR3, VAR5, VAR8, VAR9 );
input VAR3, VAR1, VAR7, VAR2;
inout VAR8, VAR9;
output VAR5;
VAR6 VAR10(.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR9(VAR9));
VAR6 VAR4(.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR9(VAR9));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.v
| 2,312 |
module MODULE2 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR5,
VAR2 ,
VAR1 ,
VAR4 ,
VAR10
);
output VAR9 ;
output VAR6 ;
input VAR7 ;
input VAR5;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR10 ;
VAR8 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR5
);
output VAR9 ;
output VAR6 ;
input VAR7 ;
input VAR5;
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR10 ;
VAR8 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
|
apache-2.0
|
fallen/milkymist-mmu
|
cores/tmu2/rtl/tmu2_vdiv.v
| 3,459 |
module MODULE1(
input VAR24,
input VAR11,
output VAR41,
input VAR19,
output reg VAR43,
input signed [17:0] VAR38,
input signed [17:0] VAR39,
input signed [17:0] VAR20,
input signed [17:0] VAR52,
input VAR17,
input [16:0] VAR35,
input VAR8,
input [16:0] VAR44,
input VAR22,
input [16:0] VAR16,
input VAR3,
input [16:0] VAR45,
input signed [11:0] VAR4,
input signed [11:0] VAR40,
input [10:0] VAR5,
output reg VAR29,
input VAR30,
output reg signed [17:0] VAR51,
output reg signed [17:0] VAR18,
output reg signed [17:0] VAR1,
output reg signed [17:0] VAR50,
output reg VAR9,
output [16:0] VAR14,
output [16:0] VAR7,
output reg VAR33,
output [16:0] VAR46,
output [16:0] VAR21,
output reg VAR47,
output [16:0] VAR2,
output [16:0] VAR26,
output reg VAR23,
output [16:0] VAR12,
output [16:0] VAR15,
output reg signed [11:0] VAR37,
output reg signed [11:0] VAR36
);
reg VAR28;
wire ready;
VAR10 VAR13(
.VAR24(VAR24),
.VAR11(VAR11),
.VAR28(VAR28),
.VAR42(VAR35),
.VAR32({6'd0, VAR5}),
.ready(ready),
.VAR48(VAR14),
.VAR31(VAR7)
);
VAR10 VAR25(
.VAR24(VAR24),
.VAR11(VAR11),
.VAR28(VAR28),
.VAR42(VAR44),
.VAR32({6'd0, VAR5}),
.ready(),
.VAR48(VAR46),
.VAR31(VAR21)
);
VAR10 VAR34(
.VAR24(VAR24),
.VAR11(VAR11),
.VAR28(VAR28),
.VAR42(VAR16),
.VAR32({6'd0, VAR5}),
.ready(),
.VAR48(VAR2),
.VAR31(VAR26)
);
VAR10 VAR6(
.VAR24(VAR24),
.VAR11(VAR11),
.VAR28(VAR28),
.VAR42(VAR45),
.VAR32({6'd0, VAR5}),
.ready(),
.VAR48(VAR12),
.VAR31(VAR15)
);
always @(posedge VAR24) begin
if(VAR28) begin
VAR51 <= VAR38;
VAR18 <= VAR39;
VAR1 <= VAR20;
VAR50 <= VAR52;
VAR9 <= VAR17;
VAR33 <= VAR8;
VAR47 <= VAR22;
VAR23 <= VAR3;
VAR37 <= VAR4;
VAR36 <= VAR40;
end
end
reg state;
reg VAR53;
parameter VAR49 = 1'b0;
parameter VAR27 = 1'b1;
always @(posedge VAR24) begin
if(VAR11)
state = VAR49;
end
else
state = VAR53;
end
assign VAR41 = state;
always @(*) begin
VAR53 = state;
VAR28 = 1'b0;
VAR29 = 1'b0;
VAR43 = 1'b0;
case(state)
VAR49: begin
VAR43 = 1'b1;
if(VAR19) begin
VAR28 = 1'b1;
VAR53 = VAR27;
end
end
VAR27: begin
if(ready) begin
VAR29 = 1'b1;
if(VAR30)
VAR53 = VAR49;
end
end
endcase
end
endmodule
|
lgpl-3.0
|
TalentlessAlpaca/Automated_Vacuum_Cleaner
|
j1_soc/hdl/crc_7/crc_7.v
| 2,871 |
module MODULE1(VAR7, clk, rst, VAR9, VAR6, VAR16);
input VAR7;
input clk;
input rst;
input [VAR4-1:0] VAR9;
output [VAR13:0] VAR6;
output VAR16;
localparam VAR4 = 32, VAR13 = 7;
localparam VAR5 = 8'b10001001 ;
reg VAR17; reg [VAR4-1:0] VAR10; reg [VAR13:0] VAR11; VAR1 VAR17 = 1'b0;
localparam VAR3 = 3'd0, VAR8 = 3'd1, VAR14 = 3'd2, VAR12 = 3'd3, VAR18 = 3'd4, VAR2 = 3'd5;
reg[2:0] state;
VAR1 state = VAR3;
reg[6:0] VAR15;
assign VAR6 = VAR11; assign VAR16 = VAR17;
always @(posedge clk or negedge clk) begin
if(rst)begin
VAR17 <= 0;
VAR15 <= 0;
VAR11 <= 0;
state = VAR3;
end
else begin
case(state)
VAR3 : begin VAR15 <= 6'd0; VAR17 <= 1'b0; if (VAR7) begin
VAR10 <= VAR9; state = VAR8; end
end
VAR8 : begin VAR11 <= VAR10[(VAR4-1):(VAR4-1)-(VAR13)]; state = VAR14; end
VAR14 : begin
end
VAR15 <= VAR15 + 1'b1; if(VAR11[VAR13]) state = VAR12; else
state = VAR18; end
VAR12 : begin VAR11 <= VAR11 ^ VAR5; state = VAR18; end
VAR18 : begin VAR10 <= {VAR11[VAR13:0], VAR10[(VAR4-1)-VAR13-1:0], 1'b0};
if (VAR15 == VAR4)
end
state = VAR2; else
state = VAR8; end
VAR2 : begin VAR17 <= 1'b1; state = VAR3; end
endcase
end
end
endmodule
|
mit
|
nyaxt/dmix
|
ringbuf.v
| 1,030 |
module MODULE1
parameter VAR11 = 16,
parameter VAR2 = 4,
parameter VAR5 = VAR11/2
)(
input wire clk,
input wire rst,
input wire [23:0] VAR10,
input wire VAR7,
input wire VAR4,
input wire [(VAR2-1):0] VAR1,
output wire [23:0] VAR13);
reg [23:0] VAR3 [(VAR11-1):0];
reg [(VAR2-1):0] VAR8;
always @(posedge clk) begin
if(rst) begin
VAR8 <= 0;
end else begin
if(VAR7) begin
VAR3[VAR8] <= VAR10;
VAR8 <= VAR8 + 1;
end
end
end
reg [(VAR2-1):0] VAR9;
wire [(VAR2-1):0] VAR6 = VAR9 - VAR1;
reg [23:0] VAR12;
assign VAR13 = VAR12;
always @(posedge clk) begin
if(rst)
VAR9 <= VAR5;
end
else begin
if(VAR4)
VAR9 <= VAR9 + 1;
VAR12 <= VAR3[VAR6];
end
end
endmodule
|
mit
|
intelligenttoasters/CPC2.0
|
FPGA/Quartus/DE10/cpc_clks/cpc_clks_0002.v
| 2,269 |
module MODULE1(
input wire VAR72,
input wire rst,
output wire VAR3,
output wire VAR52,
output wire VAR48,
output wire VAR59,
output wire VAR42
);
VAR43 #(
.VAR19("true"),
.VAR30("50.0 VAR65"),
.VAR70("VAR44"),
.VAR4(4),
.VAR14("48.000000 VAR65"),
.VAR64("0 VAR25"),
.VAR17(50),
.VAR69("16.000000 VAR65"),
.VAR8("0 VAR25"),
.VAR16(50),
.VAR60("4.000000 VAR65"),
.VAR63("0 VAR25"),
.VAR5(50),
.VAR13("1.000000 VAR65"),
.VAR39("0 VAR25"),
.VAR38(50),
.VAR51("0 VAR65"),
.VAR46("0 VAR25"),
.VAR61(50),
.VAR53("0 VAR65"),
.VAR7("0 VAR25"),
.VAR56(50),
.VAR67("0 VAR65"),
.VAR6("0 VAR25"),
.VAR34(50),
.VAR26("0 VAR65"),
.VAR9("0 VAR25"),
.VAR2(50),
.VAR28("0 VAR65"),
.VAR10("0 VAR25"),
.VAR32(50),
.VAR66("0 VAR65"),
.VAR33("0 VAR25"),
.VAR35(50),
.VAR49("0 VAR65"),
.VAR73("0 VAR25"),
.VAR20(50),
.VAR62("0 VAR65"),
.VAR41("0 VAR25"),
.VAR24(50),
.VAR11("0 VAR65"),
.VAR74("0 VAR25"),
.VAR23(50),
.VAR37("0 VAR65"),
.VAR75("0 VAR25"),
.VAR50(50),
.VAR68("0 VAR65"),
.VAR1("0 VAR25"),
.VAR54(50),
.VAR36("0 VAR65"),
.VAR31("0 VAR25"),
.VAR18(50),
.VAR12("0 VAR65"),
.VAR45("0 VAR25"),
.VAR15(50),
.VAR22("0 VAR65"),
.VAR58("0 VAR25"),
.VAR29(50),
.VAR27("VAR47"),
.VAR55("VAR47")
) VAR21 (
.rst (rst),
.VAR40 ({VAR59, VAR48, VAR52, VAR3}),
.VAR42 (VAR42),
.VAR57 ( ),
.VAR71 (1'b0),
.VAR72 (VAR72)
);
endmodule
|
gpl-3.0
|
cfelton/minnesota
|
mn/cores/usbext/fpgalink/comm_fpga_fx2_v1_stub.v
| 1,721 |
module MODULE1 (
VAR10,
VAR17,
VAR15,
VAR19,
VAR18,
VAR13,
VAR4,
VAR1,
VAR12,
VAR8,
VAR7,
VAR11,
VAR5,
VAR14,
VAR9,
VAR6,
VAR2,
VAR16
);
input VAR10;
input VAR17;
output VAR15;
reg VAR15;
input [7:0] VAR19;
output [7:0] VAR18;
reg [7:0] VAR18;
output VAR13;
reg VAR13;
output VAR4;
reg VAR4;
input VAR1;
output VAR12;
reg VAR12;
input VAR8;
output VAR7;
reg VAR7;
output [6:0] VAR11;
reg [6:0] VAR11;
output [7:0] VAR5;
reg [7:0] VAR5;
output VAR14;
reg VAR14;
input VAR9;
input [7:0] VAR6;
input VAR2;
output VAR16;
reg VAR16;
always @(posedge VAR10, negedge VAR17) begin: VAR3
if ((VAR1 || VAR8 || VAR9 || VAR2 || (VAR19 == 0) || (VAR6 == 0))) begin
VAR18 <= 2;
VAR13 <= 1'b0;
VAR15 <= 1'b1;
VAR4 <= 1'b1;
VAR12 <= 1'b1;
VAR7 <= 1'b1;
VAR11 <= 1'b1;
VAR5 <= 3;
VAR14 <= 1'b1;
VAR16 <= 1'b1;
end
end
endmodule
|
gpl-3.0
|
antmicro/yosys
|
techlibs/greenpak4/cells_map.v
| 5,298 |
module MODULE1(input VAR35, VAR47, VAR40, output reg VAR42);
parameter [0:0] VAR21 = 1'VAR41;
VAR4 #(
.VAR21(VAR21),
.VAR36(1'b1),
) VAR12 (
.VAR35(VAR35),
.VAR47(VAR47),
.VAR15(VAR40),
.VAR42(VAR42)
);
endmodule
module MODULE7(input VAR35, VAR47, VAR30, output reg VAR42);
parameter [0:0] VAR21 = 1'VAR41;
VAR4 #(
.VAR21(VAR21),
.VAR36(1'b0),
) VAR12 (
.VAR35(VAR35),
.VAR47(VAR47),
.VAR15(VAR30),
.VAR42(VAR42)
);
endmodule
module MODULE8(input VAR35, VAR47, VAR40, output reg VAR33);
parameter [0:0] VAR21 = 1'VAR41;
VAR14 #(
.VAR21(VAR21),
.VAR36(1'b1),
) VAR12 (
.VAR35(VAR35),
.VAR47(VAR47),
.VAR15(VAR40),
.VAR33(VAR33)
);
endmodule
module MODULE6(input VAR35, VAR47, VAR30, output reg VAR33);
parameter [0:0] VAR21 = 1'VAR41;
VAR14 #(
.VAR21(VAR21),
.VAR36(1'b0),
) VAR12 (
.VAR35(VAR35),
.VAR47(VAR47),
.VAR15(VAR30),
.VAR33(VAR33)
);
endmodule
module MODULE9(input VAR35, VAR2, VAR40, output reg VAR42);
parameter [0:0] VAR21 = 1'VAR41;
VAR28 #(
.VAR21(VAR21),
.VAR36(1'b1),
) VAR12 (
.VAR35(VAR35),
.VAR2(VAR2),
.VAR15(VAR40),
.VAR42(VAR42)
);
endmodule
module MODULE5(input VAR35, VAR2, VAR30, output reg VAR42);
parameter [0:0] VAR21 = 1'VAR41;
VAR28 #(
.VAR21(VAR21),
.VAR36(1'b0),
) VAR12 (
.VAR35(VAR35),
.VAR2(VAR2),
.VAR15(VAR30),
.VAR42(VAR42)
);
endmodule
module MODULE10(input VAR35, VAR2, VAR40, output reg VAR33);
parameter [0:0] VAR21 = 1'VAR41;
VAR43 #(
.VAR21(VAR21),
.VAR36(1'b1),
) VAR12 (
.VAR35(VAR35),
.VAR2(VAR2),
.VAR15(VAR40),
.VAR33(VAR33)
);
endmodule
module MODULE4(input VAR35, VAR2, VAR30, output reg VAR33);
parameter [0:0] VAR21 = 1'VAR41;
VAR43 #(
.VAR21(VAR21),
.VAR36(1'b0),
) VAR12 (
.VAR35(VAR35),
.VAR2(VAR2),
.VAR15(VAR30),
.VAR33(VAR33)
);
endmodule
module MODULE3(input VAR44, input VAR20, output VAR39);
VAR31 VAR12 (
.VAR44(VAR44),
.VAR20(VAR20),
.VAR17(VAR39),
.VAR39()
);
endmodule
module MODULE11 (VAR5, VAR45);
parameter VAR3 = 0;
parameter VAR6 = 0;
input [VAR3-1:0] VAR5;
output VAR45;
generate
if (VAR3 == 1) begin
if(VAR6 == 2'b01) begin
VAR19 VAR12 (.VAR39(VAR45), .VAR44(VAR5[0]) );
end
else begin
VAR11 #(.VAR21({2'b00, VAR6})) VAR12 (.VAR39(VAR45),
.VAR23(VAR5[0]), .VAR26(1'b0));
end
end else
if (VAR3 == 2) begin
VAR11 #(.VAR21(VAR6)) VAR12 (.VAR39(VAR45),
.VAR23(VAR5[0]), .VAR26(VAR5[1]));
end else
if (VAR3 == 3) begin
VAR9 #(.VAR21(VAR6)) VAR12 (.VAR39(VAR45),
.VAR23(VAR5[0]), .VAR26(VAR5[1]), .VAR38(VAR5[2]));
end else
if (VAR3 == 4) begin
VAR46 #(.VAR21(VAR6)) VAR12 (.VAR39(VAR45),
.VAR23(VAR5[0]), .VAR26(VAR5[1]), .VAR38(VAR5[2]), .VAR37(VAR5[3]));
end else begin
wire VAR13 = 1;
end
endgenerate
endmodule
module \VAR25 (VAR22, VAR47, VAR39, VAR10, VAR27, VAR29);
input wire VAR22;
input wire VAR47;
output reg VAR39;
output reg[VAR3-1:0] VAR10;
input wire VAR27;
input wire VAR29;
parameter VAR8 = 1;
parameter VAR1 = "VAR34";
parameter VAR32 = 0;
parameter VAR18 = 0;
parameter VAR16 = 0;
parameter VAR3 = 8;
parameter VAR7 = "VAR24";
if(VAR7 != "VAR24") begin
|
isc
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_switches.v
| 1,839 |
module MODULE1 (
address,
clk,
VAR6,
VAR4,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR6;
input VAR4;
wire VAR1;
wire [ 7: 0] VAR5;
wire [ 7: 0] VAR3;
reg [ 31: 0] VAR2;
assign VAR1 = 1;
assign VAR3 = {8 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (VAR4 == 0)
VAR2 <= 0;
end
else if (VAR1)
VAR2 <= {32'b0 | VAR3};
end
assign VAR5 = VAR6;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.symbol.v
| 1,283 |
module MODULE1 (
input VAR5,
output VAR1
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
freecores/tiny_tate_bilinear_pairing
|
group_size_is_151_bits/rtl/ram.v
| 1,654 |
module MODULE1 #(
parameter VAR11 = 198,
parameter VAR2 = 6
) (
input clk,
input wire VAR4,
input wire [VAR2-1:0] VAR14,
input wire [VAR11-1:0] VAR10,
output reg [VAR11-1:0] VAR7,
input wire VAR13,
input wire [VAR2-1:0] VAR8,
input wire [VAR11-1:0] VAR6,
output reg [VAR11-1:0] VAR9
);
reg [VAR11-1:0] VAR5 [(2**VAR2)-1:0];
VAR12 begin : VAR1
integer VAR3;
for(VAR3 = 0; VAR3 < (2**VAR2); VAR3 = VAR3 + 1)
VAR5[VAR3] = 0;
end
always @(posedge clk) begin
VAR7 <= VAR5[VAR14];
if(VAR4) begin
VAR7 <= VAR10;
VAR5[VAR14] <= VAR10;
end
end
always @(posedge clk) begin
VAR9 <= VAR5[VAR8];
if(VAR13) begin
VAR9 <= VAR6;
VAR5[VAR8] <= VAR6;
end
end
endmodule
|
apache-2.0
|
alanachtenberg/CSCE-350
|
Lab 7/lab7_5.v
| 5,260 |
module MODULE2(VAR29, VAR22, VAR59, VAR23, VAR2, VAR47, VAR38);
input VAR23, VAR59, VAR2, VAR47, VAR38;
output VAR29, VAR22;
wire VAR17;
wire VAR53, VAR12;
wire VAR8, VAR10;
wire VAR52, VAR57;
wire VAR51, VAR42;
and (VAR17, VAR38, VAR59);
not (VAR53, VAR23);
not (VAR12, VAR17);
nand VAR13(VAR8,VAR17, VAR23);
nand VAR24(VAR10,VAR17, VAR53);
nand VAR1(VAR42,VAR10,VAR51, VAR47); nand VAR36(VAR51,VAR8,VAR42, VAR2); nand VAR26(VAR52,VAR12, VAR51);
nand VAR32(VAR57,VAR12, VAR42);
nand VAR15(VAR22,VAR57,VAR29, VAR47);
nand VAR20(VAR29,VAR52,VAR22,VAR2);
endmodule
module MODULE1(VAR29, VAR22, VAR59, VAR23, VAR2, VAR47, VAR38);
input [31:0] VAR23;
input VAR59, VAR2, VAR47, VAR38;
output [31:0] VAR29, VAR22;
MODULE2 MODULE16(VAR29[0],VAR22[0],VAR59,VAR23[0],VAR2,VAR47,VAR38);
MODULE2 MODULE10(VAR29[1],VAR22[1],VAR59,VAR23[1],VAR2,VAR47,VAR38);
MODULE2 MODULE6(VAR29[2],VAR22[2],VAR59,VAR23[2],VAR2,VAR47,VAR38);
MODULE2 MODULE27(VAR29[3],VAR22[3],VAR59,VAR23[3],VAR2,VAR47,VAR38);
MODULE2 MODULE29(VAR29[4],VAR22[4],VAR59,VAR23[4],VAR2,VAR47,VAR38);
MODULE2 MODULE19(VAR29[5],VAR22[5],VAR59,VAR23[5],VAR2,VAR47,VAR38);
MODULE2 MODULE22(VAR29[6],VAR22[6],VAR59,VAR23[6],VAR2,VAR47,VAR38);
MODULE2 MODULE28(VAR29[7],VAR22[7],VAR59,VAR23[7],VAR2,VAR47,VAR38);
MODULE2 MODULE21(VAR29[8],VAR22[8],VAR59,VAR23[8],VAR2,VAR47,VAR38);
MODULE2 MODULE2(VAR29[9],VAR22[9],VAR59,VAR23[9],VAR2,VAR47,VAR38);
MODULE2 MODULE18(VAR29[10],VAR22[10],VAR59,VAR23[10],VAR2,VAR47,VAR38);
MODULE2 MODULE5(VAR29[11],VAR22[11],VAR59,VAR23[11],VAR2,VAR47,VAR38);
MODULE2 MODULE1(VAR29[12],VAR22[12],VAR59,VAR23[12],VAR2,VAR47,VAR38);
MODULE2 MODULE7(VAR29[13],VAR22[13],VAR59,VAR23[13],VAR2,VAR47,VAR38);
MODULE2 MODULE17(VAR29[14],VAR22[14],VAR59,VAR23[14],VAR2,VAR47,VAR38);
MODULE2 MODULE25(VAR29[15],VAR22[15],VAR59,VAR23[15],VAR2,VAR47,VAR38);
MODULE2 MODULE20(VAR29[16],VAR22[16],VAR59,VAR23[16],VAR2,VAR47,VAR38);
MODULE2 MODULE30(VAR29[17],VAR22[17],VAR59,VAR23[17],VAR2,VAR47,VAR38);
MODULE2 MODULE24(VAR29[18],VAR22[18],VAR59,VAR23[18],VAR2,VAR47,VAR38);
MODULE2 MODULE3(VAR29[19],VAR22[19],VAR59,VAR23[19],VAR2,VAR47,VAR38);
MODULE2 MODULE8(VAR29[20],VAR22[20],VAR59,VAR23[20],VAR2,VAR47,VAR38);
MODULE2 MODULE14(VAR29[21],VAR22[21],VAR59,VAR23[21],VAR2,VAR47,VAR38);
MODULE2 MODULE11(VAR29[22],VAR22[22],VAR59,VAR23[22],VAR2,VAR47,VAR38);
MODULE2 MODULE26(VAR29[23],VAR22[23],VAR59,VAR23[23],VAR2,VAR47,VAR38);
MODULE2 MODULE31(VAR29[24],VAR22[24],VAR59,VAR23[24],VAR2,VAR47,VAR38);
MODULE2 MODULE23(VAR29[25],VAR22[25],VAR59,VAR23[25],VAR2,VAR47,VAR38);
MODULE2 MODULE9(VAR29[26],VAR22[26],VAR59,VAR23[26],VAR2,VAR47,VAR38);
MODULE2 MODULE4(VAR29[27],VAR22[27],VAR59,VAR23[27],VAR2,VAR47,VAR38);
MODULE2 MODULE12(VAR29[28],VAR22[28],VAR59,VAR23[28],VAR2,VAR47,VAR38);
MODULE2 MODULE15(VAR29[29],VAR22[29],VAR59,VAR23[29],VAR2,VAR47,VAR38);
MODULE2 MODULE32(VAR29[30],VAR22[30],VAR59,VAR23[30],VAR2,VAR47,VAR38);
MODULE2 MODULE13(VAR29[31],VAR22[31],VAR59,VAR23[31],VAR2,VAR47,VAR38);
endmodule
module MODULE3(VAR17);
parameter VAR35 = 10, VAR5 = 50, VAR7 = 50;
output VAR17;
reg VAR17;
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21o/sky130_fd_sc_hdll__a21o.pp.symbol.v
| 1,352 |
module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR3 ,
output VAR1 ,
input VAR4 ,
input VAR7,
input VAR2,
input VAR8
);
endmodule
|
apache-2.0
|
eda-globetrotter/MarcheProcessor
|
processor/spare/build3/umult8.v
| 1,138 |
module MODULE1(VAR3, VAR2, VAR7);
input [0:7] VAR3, VAR2;
output [0:15] VAR7;
reg [0:15] VAR5;
reg [0:15] VAR6;
reg [0:15] VAR1;
reg [0:15] VAR7;
integer VAR4;
always @ (VAR3 or VAR2)
begin
VAR5=16'b0;
VAR6=16'b0;
VAR1=16'b0;
VAR6={{8{1'b0}},VAR2[0:7]};
VAR5={{8{1'b0}},VAR3[0:7]};
for (VAR4=15; VAR4>7; VAR4=VAR4-1)
begin
VAR1=VAR1+(VAR5[VAR4]?(VAR6<<(8'd15-VAR4)):16'b0);
end
VAR7<=VAR1;
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.behavioral.v
| 1,375 |
module MODULE1 (
VAR7 ,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR6;
supply1 VAR5;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR3 ;
or VAR2 (VAR7 , VAR4, VAR6 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.functional.pp.v
| 2,245 |
module MODULE1 (
VAR4 ,
VAR7,
VAR3,
VAR11 ,
VAR2 ,
VAR15,
VAR13,
VAR8 ,
VAR9
);
output VAR4 ;
input VAR7;
input VAR3;
input VAR11 ;
input VAR2 ;
input VAR15;
input VAR13;
input VAR8 ;
input VAR9 ;
wire VAR12 ;
wire VAR14 ;
wire VAR16 ;
wire VAR6;
and VAR1 (VAR12 , VAR11, VAR2 );
nor VAR5 (VAR14 , VAR7, VAR3 );
nor VAR10 (VAR16 , VAR14, VAR12 );
VAR18 VAR17 (VAR6, VAR16, VAR15, VAR13);
buf VAR19 (VAR4 , VAR6 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nand2b/sky130_fd_sc_ms__nand2b_4.v
| 2,147 |
module MODULE1 (
VAR1 ,
VAR5 ,
VAR9 ,
VAR8,
VAR7,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR3 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1 ,
VAR5,
VAR9
);
output VAR1 ;
input VAR5;
input VAR9 ;
supply1 VAR8;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
|
apache-2.0
|
sabertazimi/open-hust-verilog
|
regfile.v
| 1,624 |
module MODULE1
(
input clk,
input rst,
input VAR6,
input [4:0] VAR12,
input [4:0] VAR1,
input [4:0] VAR13,
input [VAR8-1:0] VAR2,
output [VAR8-1:0] VAR7,
output [VAR8-1:0] VAR5,
output [VAR8-1:0] VAR10,
output [VAR8-1:0] VAR3
);
reg [4:0] VAR9;
reg [VAR8-1:0] MODULE1 [0:31];
always @ (posedge clk) begin
if (rst) begin
for (VAR9 = 0; VAR9 < 31; VAR9 = VAR9 + 1)
begin
MODULE1[VAR9] <= 0;
end
end else if (VAR6 && VAR13 != 0) begin
MODULE1[VAR13] <= VAR2;
end
end
assign VAR7 = (VAR6 && VAR13 == VAR12) ? VAR2
: (VAR12 != 0) ? MODULE1[VAR12]
: 0;
assign VAR5 = (VAR6 && VAR13 == VAR1) ? VAR2
: (VAR1 != 0) ? MODULE1[VAR1]
: 0;
assign VAR10 = MODULE1[VAR4];
assign VAR3 = MODULE1[VAR11];
endmodule
|
mit
|
travisg/cpu
|
rtl/cpu/alu.v
| 1,902 |
module MODULE1(
input [3:0] VAR3,
input [31:0] VAR5,
input [31:0] VAR2,
output reg [31:0] VAR1
);
always @(VAR3 or VAR5 or VAR2)
begin
case (VAR3)
default: VAR1 = 32'VAR4;
endcase
end
endmodule
|
mit
|
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v
| 20,180 |
module MODULE1 #
(
parameter VAR41 = 100,
parameter VAR23 = 256,
parameter VAR19 = 5,
parameter VAR34 = "VAR57",
parameter VAR11 = 2 ,
parameter VAR59 = "VAR35"
)
(
VAR20, VAR2, VAR9, VAR65,
VAR52, VAR80, VAR81, VAR63,
VAR84,
rst, clk, VAR88, VAR16, VAR17, VAR50,
VAR86, VAR101, VAR103, VAR43
);
input rst;
input clk;
output wire VAR20;
output wire [3:0] VAR2;
reg [5:0] VAR74;
reg VAR97 ;
assign VAR20 = VAR97;
wire VAR31;
wire VAR27;
reg [5:0] VAR6;
generate begin : VAR32
wire VAR75 = ~VAR97 || VAR31;
wire VAR69 =
~rst && (VAR97 || (VAR74[4:0] == 5'h1f));
always @(VAR74 or rst or VAR27
or VAR75) begin
VAR6 = VAR74;
if (rst) VAR6 = 6'b0;
end
else if (VAR75) VAR6 =
VAR74 + 6'h1 + (VAR19 == 5 ? 0 : VAR27);
end
end
endgenerate
assign VAR2 = VAR74[3:0];
input VAR88;
input [VAR19-1:0] VAR16;
input VAR17;
input VAR50;
input [VAR23-1:0] VAR86;
output reg VAR9 ;
output reg VAR65;
output reg [VAR23-1:0] VAR52;
input [(2*VAR11)-1:0] VAR101;
input [(2*VAR11)-1:0] VAR103;
reg [2*VAR11-1:0] VAR100 = 'b0;
reg [2*VAR11-1:0] VAR58 = 'b0;
output wire [2*VAR11-1:0] VAR80;
output wire [2*VAR11-1:0] VAR84;
assign VAR80 = VAR100;
assign VAR84 = VAR58;
input VAR43;
output wire VAR81;
output wire [VAR19-1:0] VAR63;
localparam VAR14 = VAR23 + (VAR34 == "VAR57" ? 0 : 2*2*VAR11);
localparam VAR42 = (VAR14/6);
localparam VAR8 = VAR14 % 6;
localparam VAR3 = VAR42 + ((VAR8 == 0 ) ? 0 : 1);
localparam VAR21 = (VAR3*6);
generate
if (VAR59 == "VAR15") begin : VAR46
assign VAR31 = 1'b0;
assign VAR27 = 1'b0;
assign VAR81 = 1'b0;
reg [VAR19-1:0] VAR70;
wire [VAR19-1:0] VAR10 =
rst
? 0
: VAR70 + VAR43;
always @(posedge clk) VAR70 <=
assign VAR63 = VAR10;
if (VAR34 == "VAR57") begin : VAR62
always @(VAR86) VAR52 = VAR86;
always @(VAR88) VAR9 = VAR88;
always @(VAR50) VAR65 = VAR50;
end
else begin : VAR53
end
end
else begin : VAR28
wire VAR1 = ~VAR97 || VAR88 ;
wire [4:0] VAR71 = VAR19 == 5 ?
VAR16 :
{VAR16, VAR17};
wire [1:0] VAR92;
begin : VAR36
wire [4:0] VAR68 = VAR97
? VAR71
: VAR74[4:0];
reg [4:0] VAR96;
always @(posedge clk) VAR96 <=
wire [1:0] VAR95;
reg VAR37;
wire [1:0] VAR89 =
VAR97
? {VAR50, ~(VAR17
? VAR37
: VAR95[0])}
: 2'b0;
reg [1:0] VAR102;
always @(posedge clk) VAR102 <=
reg VAR79;
VAR56
.VAR33(64'h0000000000000000),
.VAR22(64'h0000000000000000),
.VAR12(64'h0000000000000000)
) VAR29 (
.VAR60(VAR92),
.VAR67(),
.VAR24(VAR95),
.VAR25(),
.VAR38(VAR102),
.VAR18(2'b0),
.VAR98(VAR102),
.VAR91(VAR102),
.VAR82(VAR74[4:0]),
.VAR83(5'b0),
.VAR61(VAR68),
.VAR87(VAR96),
.VAR49(VAR79),
.VAR72(clk)
);
end
wire [VAR21-1:0] VAR7;
begin : VAR90
wire [VAR21-1:0] VAR4;
if (VAR8 == 0)
if (VAR34 == "VAR57")
assign VAR4 = VAR86;
end
else
assign VAR4 = {VAR103, VAR101, VAR86};
end
else
if (VAR34 == "VAR57")
assign VAR4 = {{6-VAR8{1'b0}}, VAR86};
else
assign VAR4 =
{{6-VAR8{1'b0}}, VAR103, VAR101, VAR86};
reg [4:0] VAR54 ;
genvar VAR40;
for (VAR40=0; VAR40<VAR3; VAR40=VAR40+1) begin : VAR77
VAR56
.VAR33(64'h0000000000000000),
.VAR22(64'h0000000000000000),
.VAR12(64'h0000000000000000)
) VAR29 (
.VAR60(VAR7[((VAR40*6)+4)+:2]),
.VAR67(VAR7[((VAR40*6)+2)+:2]),
.VAR24(VAR7[((VAR40*6)+0)+:2]),
.VAR25(),
.VAR38(VAR4[((VAR40*6)+4)+:2]),
.VAR18(VAR4[((VAR40*6)+2)+:2]),
.VAR98(VAR4[((VAR40*6)+0)+:2]),
.VAR91(2'b0),
.VAR82(VAR54[4:0]),
.VAR83(VAR54[4:0]),
.VAR61(VAR54[4:0]),
.VAR87(VAR71),
.VAR49(VAR1),
.VAR72(clk)
);
end end
wire VAR78 = (VAR92[0] == VAR74[5]);
wire VAR64 = VAR88 && (VAR71[4:0] == VAR74[4:0]) ;
assign VAR31 =
VAR97 && (VAR64 || VAR78);
wire VAR66 = VAR64 ? VAR50 : VAR92[1];
assign VAR27 =
VAR31 && VAR66 && ~VAR74[0];
wire [VAR23-1:0] VAR99 =
VAR64
? VAR86
: VAR7[VAR23-1:0];
if (VAR34 != "VAR57") begin : VAR26
wire [(2*VAR11)-1:0] VAR76 =
VAR64
? VAR101
: VAR7[VAR23+:(2*VAR11)];
always @(posedge clk) VAR100 <=
end
if (VAR34 != "VAR57") begin : VAR47
wire [(2*VAR11)-1:0] VAR5 =
VAR64
? VAR103
: VAR7[(VAR23+(2*VAR11))+:(2*VAR11)];
always @(posedge clk) VAR58 <=
end
reg VAR13;
wire VAR85 = VAR13 && VAR65; reg [VAR19:0] VAR55;
wire [VAR19:0] VAR93 = VAR55 - 1;
wire [VAR19:0] VAR39 = VAR55 + 1;
begin : VAR73
reg [VAR19:0] VAR30;
always @(VAR85 or VAR55 or VAR43 or rst or VAR93 or VAR39) begin
VAR30 = VAR55;
if (rst) VAR30 = 0;
end
else case ({VAR43, VAR85})
2'b01 : VAR30 = VAR93;
2'b10 : VAR30 = VAR39;
endcase end
assign VAR81 = VAR30[VAR19];
VAR51: cover property (@(posedge clk) (~rst && VAR81));
VAR45: cover property (@(posedge clk)
(~rst && VAR43 && VAR85 && (VAR55 == 'hf)));
VAR94: assert property (@(posedge clk)
(rst || !((VAR55 == 'b0) && (VAR30 == 'h1f))));
VAR44: assert property (@(posedge clk)
(rst || !((VAR55 == 'h10) && (VAR30 == 'h11))));
end
reg [VAR19-1:0] VAR70;
assign VAR63 = VAR70;
begin : VAR48
reg [VAR19-1:0] VAR10;
always @(VAR43 or VAR70 or rst) begin
VAR10 = VAR70;
if (rst) VAR10 = 0;
end
else if (VAR43) VAR10 =
VAR70 + 1;
end
always @(posedge clk) VAR70 <=
end end endgenerate
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a221o/sky130_fd_sc_ls__a221o.pp.symbol.v
| 1,401 |
module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR10 ,
input VAR3 ,
input VAR4 ,
output VAR6 ,
input VAR7 ,
input VAR1,
input VAR9,
input VAR5
);
endmodule
|
apache-2.0
|
donnaware/TabX1
|
rtl/tabx1/lcd1.v
| 24,686 |
module MODULE1 (
input VAR66, input VAR59, input reset,
input [ 7:0] VAR82, output reg [ 7:0] VAR25,
input [19:0] VAR33, input VAR52, input VAR40, output VAR92,
inout reg [ 7:0] VAR42, output reg [11:0] VAR86, output reg VAR36, output reg VAR28, output reg VAR93,
output [ 5:0] VAR60, output [ 5:0] VAR65, output [ 5:0] VAR50, output VAR37, output VAR45 );
wire clk = VAR66; wire VAR54 = VAR59; wire VAR27 = VAR52; wire VAR58 = VAR24 & ~VAR11;
assign VAR92 = (VAR96 | VAR58);
reg VAR24;
reg VAR11;
always @(VAR27 or VAR11 or reset) begin
if(reset) begin VAR24 <= 1'b0; end
else begin if(VAR27 & !VAR11) VAR24 <= 1'b1; else VAR24 <= 1'b0; end
end
wire [11:0] VAR56 = {1'b0, VAR39};
wire [11:0] VAR16 = {3'b0, VAR4[8:0]};
wire [19:0] VAR4;
wire [10:0] VAR39;
VAR64 VAR77(.VAR10(11'd1280),.VAR81(VAR33),.VAR53(VAR4),.VAR5(VAR39));
wire [27:0] VAR83 = {VAR33, VAR82};
wire VAR62;
wire [11:0] VAR14;
wire VAR96 = (VAR14 > 12'hFFA) & VAR40;
wire VAR67 = ~VAR40; wire VAR17 = 1'b1;
wire [27:0] VAR98;
wire VAR70;
reg VAR26;
VAR8 VAR29(
.VAR100 ( VAR83 ),
.VAR76 ( VAR62 ),
.VAR35 ( VAR14 ),
.VAR78 ( VAR67 ),
.VAR94 ( VAR17 ),
.VAR55 ( VAR66 ),
.VAR22 ( VAR26 ),
.VAR51 ( VAR98 ),
.VAR90 ( VAR70 )
);
wire [ 7:0] VAR19 = VAR98[ 7: 0]; wire [11:0] VAR44 = {1'b0, VAR85};
wire [11:0] VAR79 = {3'b0, VAR21[8:0]};
wire [19:0] VAR21;
wire [10:0] VAR85;
VAR64 VAR2(.VAR10(11'd1280),.VAR81(VAR98[27: 8]),.VAR53(VAR21),.VAR5(VAR85));
parameter VAR95 = 2'b00; parameter VAR87 = 2'b01; parameter VAR97 = 2'b10;
parameter VAR88 = 640; parameter VAR99 = 480;
parameter VAR71 = VAR88*2; parameter VAR61 = 480;
parameter VAR41 = 800; parameter VAR69 = 525;
parameter VAR57 = VAR88-1; parameter VAR34 = VAR41-1; parameter VAR30 = VAR99-1; parameter VAR43 = VAR69-1;
wire VAR32= (VAR7 == VAR41-1); wire VAR3= (VAR80 == VAR69-1); wire VAR63 = (VAR7 < VAR88); wire VAR13 = (VAR80 < VAR99); assign VAR45 = VAR63 & VAR13; assign VAR37 = VAR12;
reg [9:0] VAR7; reg [9:0] VAR80;
reg [1:0] VAR75; wire VAR12 = VAR75[1]; always @(posedge VAR54) VAR75 <= VAR75 + 2'b1;
always @(posedge VAR12) begin
end
if(VAR32) VAR7 <= 10'd0; else VAR7 <= VAR7 + 10'd1; end
always @(posedge VAR12) begin if(VAR32) begin
end
if(VAR3) VAR80 <= 10'd0; else VAR80 <= VAR80 + 10'd1; end
end
wire VAR46 = VAR45; wire VAR55 = VAR12 & VAR46; wire VAR48 = VAR13; wire VAR20 = (VAR7 > VAR41-128); wire VAR23 = VAR20 & VAR48; wire VAR72 = (VAR86 == VAR71-1);
wire [9:0] VAR89 = VAR7[9:0]; reg VAR9; reg [10:0] VAR18; wire [15:0] VAR49;
VAR91 VAR47(.VAR38(VAR89),.VAR84(VAR55),.VAR51(VAR49),.VAR74(VAR18),.VAR68(clk),.VAR73(VAR9),.VAR100(VAR42));
assign VAR60 = {VAR49[ 4: 0], VAR49[ 0]}; assign VAR65 = VAR49[10: 5]; assign VAR50 = {VAR49[15:11], VAR49[11]};
reg [ 4:0] VAR6; reg [ 4:0] VAR31; reg [10:0] VAR1; always @(negedge clk) begin
end
if(reset) VAR6 <= 5'd00; else VAR6 <= VAR31;
end
always @(posedge clk)
if(reset) begin VAR42 <= 8'VAR15; VAR93 <= 1'b1; VAR36 <= 1'b1; VAR28 <= 1'b1; VAR86 <= 12'd0; VAR26 <= 1'b0; VAR11 <= 1'b0; end
else begin case(VAR6) 5'd00: begin if(VAR23) VAR31 <= 5'd01; else VAR31 <= 5'd06; end 5'd01: begin VAR86 <= {2'b00,VAR80}; VAR31 <= 5'd02; end 5'd02: begin VAR28 <= 1'b0; VAR31 <= 5'd03; end 5'd03: begin VAR86 <= 12'd0; VAR18 <= 10'b1; VAR9 <= 1'b1; VAR31 <= 5'd04; end 5'd04: begin VAR36 <= 1'b0; VAR31 <= 5'd05; end 5'd05: begin VAR36 <= 1'b1; VAR18 <= VAR18 + 10'd1; VAR86 <= VAR86 + 12'd1; if(VAR72) VAR31 <= 5'd06; else VAR31 <= 5'd04; end
5'd06: begin VAR9 <= 1'b0; VAR28 <= 1'b1; if(VAR70) VAR31 <= 5'd16; else begin VAR26 <= 1'b1; VAR31 <= 5'd07; end end 5'd07: begin VAR26 <= 1'b0; VAR86 <= VAR79; VAR31 <= 5'd08; end 5'd08: begin VAR28 <= 1'b0; VAR31 <= 5'd09; end 5'd09: begin VAR86 <= VAR44; VAR93 <= 1'b0; VAR31 <= 5'd11; end 5'd11: begin VAR42 <= VAR19; VAR36 <= 1'b0; VAR31 <= 5'd12; end 5'd12: begin VAR36 <= 1'b1; VAR31 <= 5'd13; end 5'd13: begin VAR28 <= 1'b1; VAR93 <= 1'b1; VAR31 <= 5'd14; end 5'd14: begin VAR42 <= 8'VAR15; VAR31 <= 5'd31; end
5'd16: begin if(VAR24) begin VAR86 <= VAR16; VAR31 <= 5'd17; end else VAR31 <= 5'd31; end 5'd17: begin VAR28 <= 1'b0; VAR31 <= 5'd18; end 5'd18: begin VAR86 <= VAR56; VAR31 <= 5'd19; end 5'd19: begin VAR36 <= 1'b0; VAR31 <= 5'd20; end 5'd20: begin VAR25 <= VAR42; VAR36 <= 1'b1; VAR31 <= 5'd21; end 5'd21: begin VAR28 <= 1'b1; VAR93 <= 1'b1; VAR11 <= 1'b1; VAR31 <= 5'd31; end
5'd31: begin case(VAR1) 11'h5: VAR36 <= 1'b0; 11'h6: ; 11'h7: VAR28 <= 1'b0; 11'h8: ; 11'h9: ; 11'hA: VAR36 <= 1'b1; 11'hB: ; 11'hC: VAR28 <= 1'b1; default: VAR31 <= 5'd00; endcase VAR1 <= VAR1 + 11'h1; end default: VAR31 <= 5'd00; endcase
if(!VAR24) VAR11 <= 1'b0;
end
endmodule
|
gpl-3.0
|
parallella/oh
|
common/hdl/oh_iobuf.v
| 1,446 |
module MODULE1 #(parameter VAR3 = 1, parameter VAR7 = "VAR5" )
(
inout VAR13, inout VAR15, inout VAR16, input VAR10, input VAR17, input VAR4, input [3:0] VAR8, input [VAR3-1:0] VAR2, input [VAR3-1:0] VAR6, output [VAR3-1:0] out, input [VAR3-1:0] in, inout [VAR3-1:0] VAR11
);
genvar VAR18;
for (VAR18 = 0; VAR18 < VAR3; VAR18 = VAR18 + 1) begin : VAR9
if(VAR7=="VAR5") begin : VAR14
assign VAR11[VAR18] = VAR6[VAR18] ? in[VAR18] : 1'VAR12;
assign out[VAR18] = VAR2[VAR18] ? VAR11[VAR18] : 1'b0;
end
else begin : VAR1
end
end
endmodule
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/acl_fp_fabs.v
| 4,748 |
module MODULE1
(
VAR2,
VAR4,
VAR5,
VAR8) ;
input VAR2;
input VAR4;
input [31:0] VAR5;
output [31:0] VAR8;
tri1 VAR2;
tri0 VAR4;
reg [30:0] VAR7;
wire VAR6;
wire [31:0] VAR3;
wire VAR1;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.v
| 2,358 |
module MODULE1 (
VAR10 ,
VAR6,
VAR8 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR1
);
output VAR10 ;
input VAR6;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
VAR4 VAR2 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR10 ,
VAR6,
VAR8 ,
VAR3
);
output VAR10 ;
input VAR6;
input VAR8 ;
input VAR3 ;
supply1 VAR5;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR1 ;
VAR4 VAR2 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
qeedquan/fpga
|
de2-115/vgadla/vgadla.v
| 6,458 |
module MODULE1
(
input wire VAR38,
input wire [3:0] VAR20,
input wire [17:0] VAR32,
inout wire [15:0] VAR5,
output wire [19:0] VAR12,
output wire VAR21,
output wire VAR57,
output wire VAR16,
output wire VAR15,
output wire VAR35,
output wire VAR26,
output wire VAR56,
output wire VAR52,
output wire VAR24,
output wire VAR43,
output wire [7:0] VAR29,
output wire [7:0] VAR14,
output wire [7:0] VAR2,
output wire [8:0] VAR25,
output wire [17:0] VAR28
);
localparam VAR27 = 0;
localparam VAR18 = 1;
localparam VAR31 = 2;
localparam VAR51 = 3;
localparam VAR3 = 4;
localparam VAR45 = 5;
localparam VAR42 = 6;
localparam VAR6 = 7;
localparam VAR34 = 8;
localparam VAR33 = 9;
localparam VAR49 = 16'hffff;
wire VAR19;
wire rst;
wire VAR50;
wire [7:0] VAR37, VAR13, VAR54;
wire [9:0] VAR39, VAR44;
wire VAR48, VAR7;
reg [9:0] VAR41, VAR10;
reg [30:0] VAR36;
reg [28:0] VAR53;
reg [19:0] addr;
reg [15:0] VAR22;
reg [3:0] state;
reg [3:0] sum;
reg [8:0] VAR25;
reg [17:0] VAR28;
reg VAR46;
reg VAR9;
assign VAR12 = addr;
assign VAR21 = 0;
assign VAR57 = 0;
assign VAR15 = 0;
assign VAR35 = 0;
assign VAR16 = VAR9;
assign VAR5 = (VAR9) ? 16'VAR23 : VAR22;
assign VAR37 = {VAR5[15:12], 4'b0};
assign VAR13 = {VAR5[11:8], 4'b0};
assign VAR54 = {VAR5[7:4], 4'b0};
assign VAR48 = VAR36[27] ^ VAR36[30];
assign VAR7 = VAR53[26] ^ VAR53[28];
assign VAR19 = ~VAR20[0];
assign VAR25 = VAR25;
assign VAR28 = VAR28;
always @ (posedge VAR50) begin
if (VAR19) begin
addr <= {VAR39, VAR44};
VAR9 <= 1'b0;
VAR22 <= 16'b0;
VAR36 <= 31'h55555555;
VAR53 <= 29'h55555555;
VAR41 <= 10'd155;
VAR10 <= 10'd120;
state <= VAR27;
end
else if ((~VAR52 | ~VAR56) & VAR20[1]) begin
case (state)
VAR27: begin
addr <= {10'd160,10'd120};
VAR9 <= 1'b0;
VAR22 <= VAR49;
state <= VAR18;
end
VAR18: begin
VAR46 <= 1'b1;
sum <= 0;
VAR9 <= 1'b1;
addr <= {VAR41 - 10'd1, VAR10};
state <= VAR31;
end
VAR31: begin
VAR9 <= 1'b1;
sum <= sum + {3'b0, VAR5[15]};
addr <= {VAR41 + 10'd1, VAR10};
state <= VAR51;
end
VAR51: begin
VAR9 <= 1'b1;
sum <= sum + {3'b0, VAR5[15]};
addr <= {VAR41, VAR10 - 10'd1};
state <= VAR3;
end
VAR3: begin
VAR9 <= 1'b1;
sum <= sum + {3'b0, VAR5[15]};
addr <= {VAR41, VAR10 + 10'd1};
state <= VAR45;
end
VAR45: begin
VAR9 <= 1'b1;
sum <= sum + {3'b0, VAR5[15]};
state <= VAR42;
end
VAR42: begin
if (VAR46 & sum > 0) begin
VAR28 <= {4'b0, VAR41[9:0], sum[3:0]};
VAR25 <= {VAR10[8:0]};
state <= VAR6;
end
else begin
VAR28 <= 18'b0;
VAR25 <= 9'b0;
state <= VAR34;
end
end
VAR6: begin
VAR9 <= 1'b0;
addr <= {VAR41, VAR10};
VAR22 <= VAR49;
state <= VAR33;
end
VAR34: begin
VAR9 <= 1'b1;
if (VAR41 < 10'd318 & VAR36[30] == 1)
VAR41 <= VAR41 + 1;
end
else if (VAR41 > 10'd2 & VAR36[30] == 0)
VAR41 <= VAR41 - 1;
if (VAR10 < 10'd237 & VAR53[28] == 1)
VAR10 <= VAR10 + 1;
end
else if (VAR10 > 10'd2 & VAR53[28] == 0)
VAR10 <= VAR10 - 1;
VAR36 <= {VAR36[29:0], VAR48} ;
VAR53 <= {VAR53[27:0], VAR7} ;
state <= VAR18;
end
VAR33: begin
VAR9 <= 1'b1;
if (VAR36[30])
VAR41 <= 10'd318;
end
else
VAR41 <= 10'd2;
if (VAR53[28])
VAR10 <= 10'd238;
else
VAR10 <= 10'd2;
VAR36 <= {VAR36[29:0], VAR48} ;
VAR53 <= {VAR53[27:0], VAR7} ;
state <= VAR18;
end
endcase
end
else begin
VAR46 <= 1'b0;
addr <= {VAR39, VAR44};
VAR9 <= 1'b1;
end
end
VAR47 VAR8(
.clk(VAR38),
.rst(rst)
);
VAR17 VAR55(
.VAR4(~rst),
.VAR58(VAR38),
.VAR1(VAR50),
.VAR11(VAR26)
);
VAR40 VAR30(
.clk(VAR50),
.rst(rst),
.VAR37(VAR37),
.VAR13(VAR13),
.VAR54(VAR54),
.VAR39(VAR39),
.VAR44(VAR44),
.VAR56(VAR56),
.VAR52(VAR52),
.VAR24(VAR24),
.VAR43(VAR43),
.VAR29(VAR29),
.VAR14(VAR14),
.VAR2(VAR2)
);
endmodule
module MODULE2();
reg VAR38;
reg [3:0] VAR20;
reg [17:0] VAR32;
wire [15:0] VAR5;
wire [19:0] VAR12;
wire VAR21;
wire VAR57;
wire VAR16;
wire VAR15;
wire VAR35;
wire VAR26;
wire VAR56;
wire VAR52;
wire VAR24;
wire VAR43;
wire [7:0] VAR29;
wire [7:0] VAR14;
wire [7:0] VAR2;
wire [8:0] VAR25;
wire [17:0] VAR28;
|
mit
|
chriswynnyk/american-put-verilog
|
american_put_stratix/src/mem_1k.v
| 9,473 |
module MODULE1 (
VAR46,
VAR2,
VAR30,
VAR21,
VAR6,
VAR37,
VAR20);
input [63:0] VAR46;
input [9:0] VAR2;
input VAR30;
input [9:0] VAR21;
input VAR6;
input VAR37;
output [63:0] VAR20;
tri1 VAR37;
wire [63:0] VAR44;
wire [63:0] VAR20 = VAR44[63:0];
VAR10 VAR28 (
.VAR57 (VAR37),
.VAR35 (VAR6),
.VAR43 (VAR30),
.VAR18 (VAR21),
.VAR33 (VAR2),
.VAR13 (VAR46),
.VAR55 (VAR44),
.VAR41 (1'b0),
.VAR52 (1'b0),
.VAR17 (1'b0),
.VAR4 (1'b0),
.VAR24 (1'b1),
.VAR36 (1'b1),
.VAR58 (1'b1),
.VAR15 (1'b1),
.VAR50 (1'b1),
.VAR31 (1'b1),
.VAR40 ({64{1'b1}}),
.VAR39 (),
.VAR27 (),
.VAR23 (1'b1),
.VAR11 (1'b1),
.VAR45 (1'b0));
VAR28.VAR16 = "VAR34",
VAR28.VAR42 = "VAR5",
VAR28.VAR14 = "VAR3",
VAR28.VAR53 = "VAR3",
VAR28.VAR12 = "VAR3",
VAR28.VAR51 = "VAR8 VAR1",
VAR28.VAR54 = "VAR10",
VAR28.VAR26 = 1024,
VAR28.VAR25 = 1024,
VAR28.VAR7 = "VAR38",
VAR28.VAR22 = "VAR34",
VAR28.VAR48 = "VAR5",
VAR28.VAR49 = "VAR9",
VAR28.VAR29 = 10,
VAR28.VAR19 = 10,
VAR28.VAR32 = 64,
VAR28.VAR47 = 64,
VAR28.VAR56 = 1;
endmodule
|
apache-2.0
|
olajep/oh
|
src/adi/hdl/library/common/ad_xcvr_rx_if.v
| 3,062 |
module MODULE1 (
input VAR6,
input [ 3:0] VAR8,
input [31:0] VAR7,
output reg VAR2,
output reg [31:0] VAR4);
reg [31:0] VAR3 = 'd0;
reg [ 3:0] VAR5 = 'd0;
reg [ 3:0] VAR1 = 'd0;
always @(posedge VAR6) begin
VAR3 <= VAR7;
VAR1 <= VAR8;
if (VAR8 != 4'h0) begin
VAR5 <= VAR8;
end
VAR2 <= |VAR1;
if (VAR5[0] == 1'b1) begin
VAR4 <= VAR7;
end else if (VAR5[1] == 1'b1) begin
VAR4 <= {VAR7[ 7:0], VAR3[31: 8]};
end else if (VAR5[2] == 1'b1) begin
VAR4 <= {VAR7[15:0], VAR3[31:16]};
end else if (VAR5[3] == 1'b1) begin
VAR4 <= {VAR7[23:0], VAR3[31:24]};
end else begin
VAR4 <= 32'd0;
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/or4b/sky130_fd_sc_hs__or4b.pp.blackbox.v
| 1,282 |
module MODULE1 (
VAR2 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR1,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR6;
endmodule
|
apache-2.0
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution4/syn/verilog/array_io.v
| 66,193 |
module MODULE1 (
VAR19,
VAR61,
VAR266,
VAR311,
VAR59,
VAR44,
VAR262,
VAR228,
VAR247,
VAR98,
VAR110,
VAR249,
VAR123,
VAR196,
VAR195,
VAR36,
VAR52,
VAR317,
VAR126,
VAR67,
VAR182,
VAR50,
VAR269,
VAR112,
VAR45,
VAR326,
VAR82,
VAR205,
VAR117,
VAR261,
VAR179,
VAR216,
VAR193,
VAR4,
VAR174,
VAR162,
VAR103,
VAR288,
VAR135,
VAR282,
VAR28,
VAR76,
VAR194,
VAR272,
VAR268,
VAR254,
VAR323,
VAR72,
VAR273,
VAR265,
VAR229,
VAR271,
VAR30,
VAR257,
VAR212,
VAR93,
VAR232,
VAR278,
VAR244,
VAR227,
VAR280,
VAR309,
VAR158,
VAR222,
VAR185,
VAR27,
VAR243,
VAR154,
VAR295,
VAR87,
VAR310,
VAR258,
VAR79,
VAR23,
VAR147,
VAR11,
VAR113,
VAR284,
VAR304,
VAR242,
VAR119,
VAR322,
VAR34,
VAR180,
VAR99,
VAR318,
VAR60,
VAR210,
VAR101,
VAR35,
VAR17,
VAR231,
VAR156,
VAR100,
VAR307,
VAR106,
VAR255,
VAR270,
VAR281,
VAR122,
VAR161,
VAR181,
VAR302,
VAR313,
VAR172,
VAR12,
VAR145,
VAR230,
VAR186,
VAR191,
VAR14,
VAR140,
VAR134,
VAR264,
VAR188,
VAR215,
VAR316,
VAR130,
VAR306,
VAR207,
VAR40,
VAR286,
VAR49,
VAR144,
VAR153,
VAR160,
VAR75,
VAR150,
VAR235,
VAR64,
VAR277,
VAR173,
VAR202,
VAR56
);
parameter VAR94 = 3'd1;
parameter VAR31 = 3'd2;
parameter VAR209 = 3'd4;
input VAR19;
input VAR61;
input VAR266;
output VAR311;
output VAR59;
output VAR44;
output [15:0] VAR262;
input VAR228;
output VAR247;
output [15:0] VAR98;
input VAR110;
output VAR249;
output [15:0] VAR123;
input VAR196;
output VAR195;
output [15:0] VAR36;
input VAR52;
output VAR317;
output [15:0] VAR126;
input VAR67;
output VAR182;
output [15:0] VAR50;
input VAR269;
output VAR112;
output [15:0] VAR45;
input VAR326;
output VAR82;
output [15:0] VAR205;
input VAR117;
output VAR261;
output [15:0] VAR179;
input VAR216;
output VAR193;
output [15:0] VAR4;
input VAR174;
output VAR162;
output [15:0] VAR103;
input VAR288;
output VAR135;
output [15:0] VAR282;
input VAR28;
output VAR76;
output [15:0] VAR194;
input VAR272;
output VAR268;
output [15:0] VAR254;
input VAR323;
output VAR72;
output [15:0] VAR273;
input VAR265;
output VAR229;
output [15:0] VAR271;
input VAR30;
output VAR257;
output [15:0] VAR212;
input VAR93;
output VAR232;
output [15:0] VAR278;
input VAR244;
output VAR227;
output [15:0] VAR280;
input VAR309;
output VAR158;
output [15:0] VAR222;
input VAR185;
output VAR27;
output [15:0] VAR243;
input VAR154;
output VAR295;
output [15:0] VAR87;
input VAR310;
output VAR258;
output [15:0] VAR79;
input VAR23;
output VAR147;
output [15:0] VAR11;
input VAR113;
output VAR284;
output [15:0] VAR304;
input VAR242;
output VAR119;
output [15:0] VAR322;
input VAR34;
output VAR180;
output [15:0] VAR99;
input VAR318;
output VAR60;
output [15:0] VAR210;
input VAR101;
output VAR35;
output [15:0] VAR17;
input VAR231;
output VAR156;
output [15:0] VAR100;
input VAR307;
output VAR106;
output [15:0] VAR255;
input VAR270;
output VAR281;
output [15:0] VAR122;
input VAR161;
output VAR181;
input [15:0] VAR302;
input [15:0] VAR313;
input [15:0] VAR172;
input [15:0] VAR12;
input [15:0] VAR145;
input [15:0] VAR230;
input [15:0] VAR186;
input [15:0] VAR191;
input [15:0] VAR14;
input [15:0] VAR140;
input [15:0] VAR134;
input [15:0] VAR264;
input [15:0] VAR188;
input [15:0] VAR215;
input [15:0] VAR316;
input [15:0] VAR130;
input [15:0] VAR306;
input [15:0] VAR207;
input [15:0] VAR40;
input [15:0] VAR286;
input [15:0] VAR49;
input [15:0] VAR144;
input [15:0] VAR153;
input [15:0] VAR160;
input [15:0] VAR75;
input [15:0] VAR150;
input [15:0] VAR235;
input [15:0] VAR64;
input [15:0] VAR277;
input [15:0] VAR173;
input [15:0] VAR202;
input [15:0] VAR56;
reg VAR311;
reg VAR59;
reg VAR44;
reg VAR247;
reg VAR249;
reg VAR195;
reg VAR317;
reg VAR182;
reg VAR112;
reg VAR82;
reg VAR261;
reg VAR193;
reg VAR162;
reg VAR135;
reg VAR76;
reg VAR268;
reg VAR72;
reg VAR229;
reg VAR257;
reg VAR232;
reg VAR227;
reg VAR158;
reg VAR27;
reg VAR295;
reg VAR258;
reg VAR147;
reg VAR284;
reg VAR119;
reg VAR180;
reg VAR60;
reg VAR35;
reg VAR156;
reg VAR106;
reg VAR281;
reg VAR181;
reg [2:0] VAR291;
wire VAR236;
reg [31:0] VAR167;
reg [31:0] VAR267;
reg [31:0] VAR83;
reg [31:0] VAR239;
reg [31:0] VAR21;
reg [31:0] VAR129;
reg [31:0] VAR253;
reg [31:0] VAR24;
reg VAR251;
wire VAR142;
reg VAR224;
reg VAR275;
reg VAR46;
reg VAR104;
reg VAR168;
reg VAR95;
reg VAR22;
reg VAR163;
reg VAR42;
reg VAR8;
reg VAR220;
reg VAR77;
reg VAR29;
reg VAR139;
reg VAR189;
reg VAR164;
reg VAR97;
reg VAR47;
reg VAR218;
reg VAR204;
reg VAR131;
reg VAR148;
reg VAR303;
reg VAR226;
reg VAR246;
reg VAR111;
reg VAR92;
reg VAR63;
reg VAR300;
reg VAR208;
reg VAR136;
wire [15:0] VAR198;
reg [15:0] VAR32;
wire [15:0] VAR259;
reg [15:0] VAR319;
wire [15:0] VAR38;
reg [15:0] VAR184;
wire [15:0] VAR2;
reg [15:0] VAR13;
wire [15:0] VAR71;
reg [15:0] VAR221;
wire [15:0] VAR102;
reg [15:0] VAR285;
wire [15:0] VAR149;
reg [15:0] VAR51;
wire [15:0] VAR9;
reg [15:0] VAR73;
wire [16:0] VAR203;
reg [16:0] VAR53;
wire [16:0] VAR69;
reg [16:0] VAR274;
wire [16:0] VAR299;
reg [16:0] VAR70;
wire [16:0] VAR16;
reg [16:0] VAR155;
wire [16:0] VAR297;
reg [16:0] VAR10;
wire [16:0] VAR201;
reg [16:0] VAR141;
wire [16:0] VAR263;
reg [16:0] VAR241;
wire [16:0] VAR314;
reg [16:0] VAR294;
wire [15:0] VAR192;
reg [15:0] VAR320;
wire VAR124;
wire [15:0] VAR125;
reg [15:0] VAR177;
wire [15:0] VAR84;
reg [15:0] VAR233;
wire [15:0] VAR128;
reg [15:0] VAR88;
wire [15:0] VAR5;
reg [15:0] VAR171;
wire [15:0] VAR85;
reg [15:0] VAR96;
wire [15:0] VAR217;
reg [15:0] VAR152;
wire [15:0] VAR245;
reg [15:0] VAR116;
wire [15:0] VAR55;
reg [15:0] VAR223;
wire [15:0] VAR250;
reg [15:0] VAR159;
wire [15:0] VAR240;
reg [15:0] VAR54;
wire [15:0] VAR325;
reg [15:0] VAR283;
wire [15:0] VAR298;
reg [15:0] VAR57;
wire [15:0] VAR48;
reg [15:0] VAR143;
wire [15:0] VAR200;
reg [15:0] VAR214;
wire [15:0] VAR301;
reg [15:0] VAR6;
reg VAR18;
wire [31:0] VAR176;
wire [31:0] VAR256;
wire [31:0] VAR248;
wire [31:0] VAR109;
wire [31:0] VAR225;
wire [31:0] VAR199;
wire [31:0] VAR105;
wire [31:0] VAR219;
wire [15:0] VAR37;
wire [15:0] VAR33;
wire [15:0] VAR118;
wire [15:0] VAR211;
wire [15:0] VAR289;
wire [15:0] VAR3;
wire [15:0] VAR234;
wire [15:0] VAR86;
wire signed [16:0] VAR138;
wire signed [16:0] VAR65;
wire signed [16:0] VAR165;
wire signed [16:0] VAR133;
wire signed [16:0] VAR237;
wire signed [16:0] VAR292;
wire signed [16:0] VAR308;
wire signed [16:0] VAR146;
wire signed [16:0] VAR290;
wire signed [16:0] VAR114;
wire signed [16:0] VAR260;
wire signed [16:0] VAR41;
wire signed [16:0] VAR81;
wire signed [16:0] VAR7;
wire signed [16:0] VAR175;
wire signed [16:0] VAR121;
wire signed [31:0] VAR190;
wire signed [17:0] VAR90;
wire signed [17:0] VAR321;
wire [17:0] VAR178;
wire signed [31:0] VAR238;
wire [31:0] VAR20;
wire signed [31:0] VAR187;
wire signed [17:0] VAR170;
wire signed [17:0] VAR293;
wire [17:0] VAR132;
wire signed [31:0] VAR296;
wire [31:0] VAR327;
wire signed [31:0] VAR107;
wire signed [17:0] VAR166;
wire signed [17:0] VAR252;
wire [17:0] VAR91;
wire signed [31:0] VAR287;
wire [31:0] VAR127;
wire signed [31:0] VAR137;
wire signed [17:0] VAR108;
wire signed [17:0] VAR68;
wire [17:0] VAR115;
wire signed [31:0] VAR305;
wire [31:0] VAR151;
wire signed [31:0] VAR206;
wire signed [17:0] VAR120;
wire signed [17:0] VAR74;
wire [17:0] VAR183;
wire signed [31:0] VAR43;
wire [31:0] VAR1;
wire signed [31:0] VAR25;
wire signed [17:0] VAR157;
wire signed [17:0] VAR80;
wire [17:0] VAR197;
wire signed [31:0] VAR169;
wire [31:0] VAR324;
wire signed [31:0] VAR312;
wire signed [17:0] VAR39;
wire signed [17:0] VAR276;
wire [17:0] VAR66;
wire signed [31:0] VAR62;
wire [31:0] VAR78;
wire signed [31:0] VAR58;
wire signed [17:0] VAR279;
wire signed [17:0] VAR15;
wire [17:0] VAR26;
wire signed [31:0] VAR315;
wire [31:0] VAR89;
reg [2:0] VAR213;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/nand3/sky130_fd_sc_hs__nand3_1.v
| 2,048 |
module MODULE2 (
VAR5 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR3,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR1;
VAR7 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR4,
VAR2,
VAR6
);
output VAR5;
input VAR4;
input VAR2;
input VAR6;
supply1 VAR3;
supply0 VAR1;
VAR7 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
skarpenko/ultiparc
|
rtl/src/intr_controller.v
| 4,508 |
module MODULE1(
clk,
VAR11,
VAR14,
VAR1,
VAR20,
VAR10,
VAR19,
VAR5,
VAR12,
VAR8,
VAR2
);
localparam [VAR15-1:0] VAR18 = 32'h000;
localparam [VAR15-1:0] VAR6 = 32'h004;
localparam [VAR15-1:0] VAR13 = 32'h008;
input wire clk;
input wire VAR11;
input wire [31:0] VAR14;
output wire VAR1;
input wire [VAR15-1:0] VAR20;
input wire [2:0] VAR10;
input wire [VAR4-1:0] VAR19;
input wire [VAR7-1:0] VAR5;
output wire VAR12;
output reg [VAR4-1:0] VAR8;
output reg [1:0] VAR2;
reg [31:0] VAR9;
reg [31:0] VAR16;
reg VAR17;
reg [31:0] VAR3;
assign VAR12 = 1'b1;
always @(*)
begin
case(VAR10)
VAR8 = {(VAR4){1'b0}};
VAR2 = VAR21;
end
if(VAR20 == VAR18)
begin
VAR8 = { {(VAR4-32){1'b0}},
VAR9 & VAR16 };
end
else if(VAR20 == VAR6)
begin
VAR8 = { {(VAR4-32){1'b0}}, VAR9 };
end
else if(VAR20 == VAR13)
begin
VAR8 = { {(VAR4-32){1'b0}}, VAR16 };
end
else
VAR8 = 32'hDEADDEAD;
VAR2 = VAR21;
end
default: begin
VAR8 = {(VAR4){1'b0}};
VAR2 = VAR22;
end
endcase
end
always @(posedge clk or negedge VAR11)
begin
if(!VAR11)
begin
VAR9 <= 32'b0;
VAR17 <= 1'b0;
VAR3 <= 32'b0;
end
else if(VAR10 == VAR23)
begin
VAR17 <= VAR20 == VAR18 ? 1'b1 : 1'b0;
if(VAR20 == VAR18)
begin
VAR3 <= VAR19[31:0];
end
if(VAR20 == VAR6)
begin
VAR9 <= VAR19[31:0];
end
end else
VAR17 <= 1'b0;
end
assign VAR1 = |(VAR9 & VAR16);
always @(posedge clk or negedge VAR11)
begin
if(!VAR11)
begin
VAR16 <= 32'b0;
end
else
begin
VAR16 <= (VAR17 ? VAR16 & ~VAR3 : VAR16) | VAR14;
end
end
endmodule
|
bsd-2-clause
|
chriz2600/DreamcastHDMI
|
Core/source/filter/output_data.v
| 2,267 |
module MODULE1(
input VAR19,
input VAR11,
input VAR1,
input VAR4,
input VAR10,
input VAR17,
input [8:0] VAR14,
input [23:0] VAR6,
output reg [23:0] VAR16
);
localparam VAR7 = 9'd256;
localparam VAR13 = VAR13;
localparam VAR13 = 9'd64;
reg [23:0] VAR2;
reg [8:0] VAR22;
wire [23:0] VAR15;
VAR3 VAR18 (
.VAR19(VAR19),
.VAR6(VAR2),
.VAR26(VAR22),
.VAR16(VAR15)
);
function [8:0] VAR25(
input[16:0] VAR23
);
VAR25 = VAR23[16:8];
endfunction
reg [8:0] VAR5;
reg VAR24, VAR12, VAR20, VAR8, VAR9;
reg [23:0] VAR21;
always @(posedge VAR19) begin
VAR21 <= VAR6;
VAR5 <= VAR13 * VAR14;
{ VAR24, VAR12, VAR20, VAR8, VAR9 } <= { VAR4, VAR1, VAR10, VAR11, VAR17 };
case ({ VAR12, VAR20, VAR8 })
3'b001: begin
VAR2 <= VAR21;
VAR22 <= (VAR9 ? VAR14 : VAR7);
end
3'b011: begin
VAR2 <= VAR21;
VAR22 <= (VAR9 ? VAR25(VAR5) : VAR13);
end
3'b111: begin
if (VAR24) begin
VAR2 <= 24'hFFFFFF;
VAR22 <= VAR7;
end else begin
VAR2 <= VAR21;
VAR22 <= (VAR9 ? VAR25(VAR5) : VAR13);
end
end
default: begin
VAR2 <= 24'h00;
VAR22 <= VAR7;
end
endcase
VAR16 <= VAR15;
end
endmodule
|
mit
|
merckhung/zet
|
cores/gpio/rtl/sw_leds.v
| 2,337 |
module MODULE1 (
input VAR1,
input VAR14,
input VAR9,
output [15:0] VAR7,
input [15:0] VAR4,
input [ 1:0] VAR13,
input VAR18,
input VAR15,
input VAR2,
output VAR16,
output reg [13:0] VAR5,
input [ 7:0] VAR19,
input VAR17,
input VAR20,
output reg VAR8
);
wire VAR3;
reg VAR10;
reg VAR6;
reg VAR11;
reg [2:0] VAR12;
assign VAR3 = VAR2 & VAR15;
assign VAR16 = VAR3;
assign VAR7 = VAR9 ? { 2'b00, VAR5 }
: { 8'h00, VAR19 };
always @(posedge VAR1)
VAR5 <= VAR14 ? 14'h0
: ((VAR3 & VAR18 & VAR9) ? VAR4[13:0] : VAR5);
always @(posedge VAR1)
begin
VAR10 <= VAR20;
VAR6 <= VAR20 & ~VAR10;
end
always @(posedge VAR1)
VAR11 <= !VAR17;
always @(posedge VAR1)
begin
if (VAR14)
begin
VAR8 <= 1'b0;
VAR12 <= 3'b111;
end
else
begin
if (VAR12 == 3'b111)
begin
if (VAR11 != VAR8)
begin
VAR8 <= VAR11;
VAR12 <= VAR12 + 3'b001; end
end
else if (VAR6)
VAR12 <= VAR12 + 3'b001;
end
end
endmodule
|
gpl-3.0
|
intelligenttoasters/CPC2.0
|
FPGA/Quartus/custom/usb/buffers/RxFifoBI.v
| 5,448 |
module MODULE1 (
address,
VAR9,
VAR15,
VAR1,
VAR17,
VAR6,
VAR7,
VAR19,
VAR11,
VAR5,
VAR12,
VAR3,
VAR14,
VAR4
);
input [2:0] address;
input VAR9;
input VAR15;
input VAR1;
input VAR17;
input VAR6;
input [7:0] VAR19;
input [7:0] VAR11;
output [7:0] VAR5;
output VAR12;
output VAR3;
output VAR14;
input [15:0] VAR4;
input VAR7;
wire [2:0] address;
wire VAR9;
wire VAR15;
wire VAR1;
wire VAR17;
wire VAR6;
wire [7:0] VAR19;
wire [7:0] VAR11;
reg [7:0] VAR5;
reg VAR12;
wire VAR3;
wire VAR14;
wire [15:0] VAR4;
wire VAR7;
reg VAR13;
reg VAR18;
reg VAR16;
reg [2:0] VAR10;
always @(posedge VAR1)
begin
if (VAR9 == 1'b1 && VAR7 == 1'b1 &&
address == VAR2 && VAR15 == 1'b1 && VAR11[0] == 1'b1)
VAR18 <= 1'b1;
end
else
VAR18 <= 1'b0;
end
always @(posedge VAR1) begin
if (VAR6 == 1'b1) begin
VAR13 <= 1'b0;
VAR16 <= 1'b0;
end
else begin
if (VAR18 == 1'b1)
VAR13 <= 1'b1;
end
else
VAR13 <= 1'b0;
if (VAR18 == 1'b1 && VAR13 == 1'b0)
VAR16 <= ~VAR16;
end
end
assign VAR14 = (VAR18 == 1'b1 && VAR13 == 1'b0) ? 1'b1 : 1'b0;
always @(posedge VAR17) begin
VAR10 <= {VAR10[1:0], VAR16};
end
assign VAR3 = VAR10[2] ^ VAR10[1];
always @(address or VAR19 or VAR4)
begin
case (address)
default: VAR5 <= 8'h00;
endcase
end
always @(address or VAR9 or VAR15 or VAR7) begin
if (address == VAR8 && VAR9 == 1'b0 &&
VAR15 == 1'b1 && VAR7 == 1'b1)
VAR12 <= 1'b1;
end
else
VAR12 <= 1'b0;
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/a22oi/sky130_fd_sc_hvl__a22oi.functional.pp.v
| 2,175 |
module MODULE1 (
VAR2 ,
VAR9 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR11,
VAR17,
VAR15 ,
VAR10
);
output VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR11;
input VAR17;
input VAR15 ;
input VAR10 ;
wire VAR6 ;
wire VAR18 ;
wire VAR19 ;
wire VAR13;
nand VAR16 (VAR6 , VAR7, VAR9 );
nand VAR14 (VAR18 , VAR1, VAR8 );
and VAR5 (VAR19 , VAR6, VAR18 );
VAR3 VAR12 (VAR13, VAR19, VAR11, VAR17);
buf VAR4 (VAR2 , VAR13 );
endmodule
|
apache-2.0
|
asicguy/gplgpu
|
hdl/vga/crt_reg_dec.v
| 8,210 |
module MODULE1
(
input VAR29,
input VAR47,
input VAR31,
input VAR16,
input VAR42,
input VAR17,
input VAR7, input VAR23,
input VAR35,
input VAR19,
input VAR40,
input VAR36,
input [15:0] VAR25,
input [15:0] VAR11,
output [7:0] VAR43, output reg [7:0] VAR39, output VAR6, output VAR45,
output [3:0] VAR24,
output VAR37,
output VAR2,
output VAR32,
output VAR12, output VAR30,
output VAR10,
output VAR27,
output VAR8,
output VAR15
);
reg [7:0] VAR26;
reg [5:0] VAR48;
reg VAR34;
reg VAR22;
wire VAR46, VAR9; wire VAR1, VAR38;
wire VAR18;
wire VAR5;
wire VAR28;
wire VAR49;
wire VAR14;
wire VAR3;
wire VAR4;
wire VAR20;
wire VAR44;
wire VAR21;
wire VAR41;
wire VAR33;
wire VAR13 = VAR7;
always @(posedge VAR16 or negedge VAR29)
if (!VAR29) begin
VAR48 <= 6'h0;
VAR39 <= 8'h0;
end else if (VAR31) begin
if (VAR18) VAR48 <= VAR11[5:0];
if (VAR5) VAR39 <= {4'b0, VAR11[3:0]};
end
assign VAR43 = {2'b0, VAR48};
assign VAR24[3:0] = VAR39[3:0];
assign VAR45 = 1'b1;
always @(posedge VAR16 or negedge VAR29)
if (!VAR29) VAR22 <= 1'b0;
end
else VAR22 <= VAR31;
assign VAR6 = VAR31 & VAR22;
assign VAR18 = VAR13 ? (VAR25 == 16'h3d4) :
(VAR25 == 16'h3b4);
assign VAR28 = VAR13 ? (VAR25 == 16'h3d5) :
(VAR25 == 16'h3b5);
assign VAR49 = VAR18 & VAR31;
assign VAR3 = VAR18 & VAR47;
assign VAR14 = ( (VAR18 & VAR42) | VAR28 );
assign VAR10 = (VAR43 == 36) & VAR47;
assign VAR27 = (VAR43 == 38) & VAR47;
assign VAR5 = (VAR25 == 16'h3ce) ;
assign VAR12 = VAR36 & VAR31;
assign VAR30 = VAR40 & VAR31;
assign VAR20 = VAR23 | VAR19;
assign VAR44 = VAR14
& ( ((VAR43 >= 8'h00) & (VAR43 <= 8'h0b))
| ((VAR43 >= 8'h10) & (VAR43 <= 8'h18) &
(VAR43 != 8'h13)) );
assign VAR21 = VAR44;
assign VAR8 = VAR13 ? (VAR25 == 16'h03da) :
(VAR25 == 16'h03ba);
assign VAR9 = VAR8 & VAR31;
assign VAR46 = (VAR25 == 16'h03ca) & VAR47;
assign VAR1 = (VAR25 == 16'h03c2) & VAR47;
assign VAR38 = VAR8 & VAR47;
assign VAR41 = (VAR25 == 16'h3cc & VAR47) |
(VAR25 == 16'h3c2 & VAR31) |
VAR1 | VAR38 |
VAR46 | VAR9 |
(VAR5 & (VAR42 | VAR17)) |
(VAR18 & (VAR42 | VAR17));
assign VAR4 = VAR31 | VAR47;
always @(posedge VAR16 or negedge VAR29)
if (!VAR29) VAR34 <= 1'b0;
else VAR34 <= VAR4;
assign VAR32 = (~(VAR34 & (VAR21 |
VAR41)));
assign VAR37 = VAR21 & VAR47;
assign VAR2 = (VAR41 |
(VAR33 & VAR42)) & VAR47;
assign VAR15 = VAR14 & ( ((VAR43 >= 8'h0c) &
(VAR43 <= 8'h0f))
| (VAR43 == 19)
| (VAR43 == 34));
assign VAR33 = VAR15 |
VAR10 | VAR27 ;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/dlclkp/sky130_fd_sc_hs__dlclkp.functional.v
| 1,645 |
module MODULE1 (
VAR11,
VAR6,
VAR4,
VAR3,
VAR2
);
input VAR11;
input VAR6;
output VAR4;
input VAR3;
input VAR2 ;
wire VAR9 ;
wire VAR8 ;
wire VAR5 ;
wire VAR12;
not VAR13 (VAR8 , VAR2 );
VAR7 VAR10 (VAR9 , VAR3, VAR8, VAR11, VAR6);
and VAR1 (VAR4 , VAR9, VAR2 );
endmodule
|
apache-2.0
|
Triple-Z/COExperiment_Repo
|
Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.v
| 5,353 |
module MODULE1(
input clk,
input VAR27,
input VAR17,
output VAR10,
output VAR3,
output VAR37,
output VAR39,
output VAR26,
inout[15:0] VAR8,
output VAR40,
inout VAR41,
inout VAR28,
output VAR35,
output VAR23
);
wire VAR18; reg VAR11;
reg VAR5;
always @(posedge clk)
begin
if (!VAR27)
begin
VAR11<= 1'b0;
end
else
begin
VAR11 <= ~VAR17;
end
VAR5 <= VAR11;
end
wire VAR21;
assign VAR21 = !VAR27 || (!VAR11 && VAR5);
VAR42 VAR19(.VAR4(clk),.VAR6(VAR21),.VAR36(VAR18));
wire [31:0] VAR24; wire [31:0] VAR25; wire [ 4:0] VAR12; wire [31:0] VAR34; reg [31:0] VAR30; wire [31:0] VAR29; VAR32 VAR13(
.clk (VAR18 ),
.VAR27 (VAR27 ),
.VAR12 (VAR12 ),
.VAR30(VAR30),
.VAR34 (VAR34 ),
.VAR29(VAR29),
.VAR24 (VAR24 ),
.VAR25(VAR25)
);
reg VAR31;
reg [39:0] VAR2;
reg [31:0] VAR9;
wire [5 :0] VAR16;
wire VAR38;
wire [31:0] VAR7;
VAR1 VAR1(
.clk (clk ), .VAR27 (VAR27 ),
.VAR31 (VAR31 ),
.VAR2 (VAR2 ),
.VAR9 (VAR9 ),
.VAR16 (VAR16),
.VAR38 (VAR38 ),
.VAR7 (VAR7 ),
.VAR10 (VAR10 ),
.VAR3 (VAR3 ),
.VAR37 (VAR37 ),
.VAR39 (VAR39 ),
.VAR26 (VAR26 ),
.VAR8 (VAR8 ),
.VAR40 (VAR40 ),
.VAR41 (VAR41 ),
.VAR28 (VAR28 ),
.VAR35 (VAR35 ),
.VAR23 (VAR23 )
);
always @(posedge clk)
begin
if (!VAR27)
begin
VAR30 <= 32'd0;
end
else if (VAR38)
begin
VAR30 <= VAR7;
end
end
assign VAR12 = VAR16-6'd5;
always @(posedge clk)
begin
if (VAR16 >6'd4 && VAR16 <6'd37 )
begin VAR31 <= 1'b1;
VAR2[39:16] <= "VAR33";
VAR2[15: 8] <= {4'b0011,3'b000,VAR12[4]};
VAR2[7 : 0] <= {4'b0011,VAR12[3:0]};
VAR9 <= VAR34;
end
else
begin
case(VAR16)
6'd1 : begin
VAR31 <= 1'b1;
VAR2 <= " VAR20";
VAR9 <= VAR24;
end
6'd2 : begin
VAR31 <= 1'b1;
VAR2 <= " VAR14";
VAR9 <= VAR25;
end
6'd3 : begin
VAR31 <= 1'b1;
VAR2 <= "VAR15";
VAR9 <= VAR30;
end
6'd4 : begin
VAR31 <= 1'b1;
VAR2 <= "VAR22";
VAR9 <= VAR29;
end
default :
begin
VAR31 <= 1'b0;
end
endcase
end
end
endmodule
|
mit
|
hanw/sonic-lite
|
hw/verilog/si570/clock_divider.v
| 2,231 |
module MODULE1(
VAR4,
VAR2,
VAR1,
);
input VAR4;
input VAR2;
output VAR1;
reg [VAR5-1:0] VAR3;
always@(posedge VAR4 or negedge VAR2)
begin
if (!VAR2)
VAR3 <= 0;
end
else
VAR3 <= VAR3 + 1;
end
assign VAR1 = VAR3[VAR5-1];
endmodule
|
mit
|
jas0n1ee/THU-DSD
|
FB/epcs_flash_controller.v
| 17,705 |
module MODULE3 (
VAR1,
clk,
VAR76,
VAR94,
VAR49,
VAR40,
VAR64,
VAR44,
VAR60,
VAR27,
VAR6,
VAR73,
VAR25,
VAR18,
irq,
VAR31
)
;
output VAR60;
output VAR27;
output VAR6;
output [ 15: 0] VAR73;
output VAR25;
output VAR18;
output irq;
output VAR31;
input VAR1;
input clk;
input [ 15: 0] VAR76;
input VAR94;
input [ 2: 0] VAR49;
input VAR40;
input VAR64;
input VAR44;
wire VAR70;
reg VAR13;
reg VAR52;
wire VAR60;
reg VAR16;
reg VAR17;
wire VAR27;
reg VAR56;
reg VAR65;
wire VAR6;
wire VAR10;
reg VAR90;
wire VAR8;
wire VAR14;
reg VAR93;
reg [ 15: 0] VAR73;
reg VAR81;
wire VAR25;
wire VAR11;
wire VAR75;
wire VAR18;
reg [ 15: 0] VAR34;
wire VAR69;
wire [ 10: 0] VAR28;
reg [ 15: 0] VAR63;
reg [ 15: 0] VAR33;
wire [ 10: 0] VAR51;
reg VAR59;
reg VAR67;
reg VAR54;
reg VAR2;
reg VAR62;
reg VAR21;
reg VAR5;
wire irq;
reg VAR57;
wire VAR39;
wire [ 15: 0] VAR66;
wire VAR85;
wire VAR87;
wire [ 1: 0] VAR89;
wire VAR15;
reg VAR22;
wire VAR31;
reg [ 7: 0] VAR58;
reg [ 7: 0] VAR26;
wire VAR12;
wire VAR91;
reg [ 1: 0] VAR30;
reg [ 4: 0] state;
reg VAR82;
wire VAR80;
reg VAR46;
reg VAR19;
reg [ 7: 0] VAR45;
reg VAR23;
wire VAR29;
wire VAR77;
assign VAR87 = ~VAR22 & VAR94 & ~VAR40;
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR22 <= 0;
end
else
VAR22 <= VAR87;
end
assign VAR39 = VAR87 & (VAR49 == 0);
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR93 <= 0;
end
else
VAR93 <= VAR39;
end
assign VAR15 = ~VAR23 & VAR94 & ~VAR44;
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR23 <= 0;
end
else
VAR23 <= VAR15;
end
assign VAR85 = VAR15 & (VAR49 == 1);
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR81 <= 0;
end
else
VAR81 <= VAR85;
end
assign VAR14 = VAR23 & (VAR49 == 3);
assign VAR80 = VAR23 & (VAR49 == 2);
assign VAR12 = VAR23 & (VAR49 == 5);
assign VAR69 = VAR23 & (VAR49 == 6);
assign VAR10 = ~VAR46 & ~VAR19;
assign VAR70 = VAR16 | VAR90;
assign VAR51 = {VAR13, VAR70, VAR17, VAR8, VAR10, VAR90, VAR16, 3'b0};
assign VAR25 = VAR17;
assign VAR31 = VAR8;
assign VAR18 = VAR13;
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
begin
VAR59 <= 0;
VAR67 <= 0;
VAR2 <= 0;
VAR5 <= 0;
VAR62 <= 0;
VAR21 <= 0;
VAR54 <= 0;
VAR65 <= 0;
end
else if (VAR14)
begin
VAR59 <= VAR76[9];
VAR67 <= VAR76[8];
VAR2 <= VAR76[7];
VAR5 <= VAR76[6];
VAR62 <= VAR76[5];
VAR21 <= VAR76[4];
VAR54 <= VAR76[3];
VAR65 <= VAR76[10];
end
end
assign VAR28 = {VAR65, VAR59, VAR67, VAR2, VAR5, 1'b0, VAR21, VAR54, 3'b0};
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR57 <= 0;
end
else
VAR57 <= (VAR13 & VAR59) | ((VAR90 | VAR16) & VAR67) | (VAR17 & VAR2) | (VAR8 & VAR5) | (VAR90 & VAR21) | (VAR16 & VAR54);
end
assign irq = VAR57;
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR33 <= 1;
end
else if (VAR29 || VAR14 & VAR76[10] & ~VAR65)
VAR33 <= VAR63;
end
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR63 <= 1;
end
else if (VAR12)
VAR63 <= VAR76;
end
assign VAR91 = VAR30 == 2'h1;
assign VAR89 = ({2 {(VAR46 && !VAR91)}} & (VAR30 + 1)) |
({2 {(~((VAR46 && !VAR91)))}} & 0);
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR30 <= 0;
end
else
VAR30 <= VAR89;
end
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR34 <= 0;
end
else if (VAR69)
VAR34 <= VAR76;
end
assign VAR66 = ((VAR49 == 2))? VAR51 :
((VAR49 == 3))? VAR28 :
((VAR49 == 6))? VAR34 :
((VAR49 == 5))? VAR33 :
VAR58;
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
VAR73 <= 0;
end
else
VAR73 <= VAR66;
end
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
begin
state <= 0;
VAR82 <= 1;
end
else if (VAR46 & VAR91)
begin
VAR82 <= state == 17;
if (state == 17)
state <= 0;
end
else
state <= state + 1;
end
end
assign VAR75 = VAR46 & ~VAR82;
assign VAR60 = VAR26[7];
assign VAR6 = (VAR75 | VAR65) ? ~VAR33 : {1 {1'b1} };
assign VAR27 = VAR56;
assign VAR8 = ~(VAR46 & VAR19);
assign VAR77 = VAR81 & VAR8;
assign VAR29 = VAR19 & ~VAR46;
always @(posedge clk or negedge VAR64)
begin
if (VAR64 == 0)
begin
VAR26 <= 0;
VAR58 <= 0;
VAR13 <= 0;
VAR17 <= 0;
VAR16 <= 0;
VAR90 <= 0;
VAR45 <= 0;
VAR19 <= 0;
VAR46 <= 0;
VAR56 <= 0;
VAR52 <= 0;
end
else
begin
if (VAR77)
begin
VAR45 <= VAR76;
VAR19 <= 1;
end
if (VAR81 & ~VAR8)
VAR90 <= 1;
if ((VAR39 && (VAR58 == VAR34)) || (VAR85 && (VAR76[7 : 0] == VAR34)))
VAR13 <= 1;
if (VAR29)
begin
VAR26 <= VAR45;
VAR46 <= 1;
end
if (VAR29 & ~VAR77)
VAR19 <= 0;
if (VAR93)
VAR17 <= 0;
if (VAR80)
begin
VAR13 <= 0;
VAR17 <= 0;
VAR16 <= 0;
VAR90 <= 0;
end
if (VAR91)
begin
if (state == 17)
begin
VAR46 <= 0;
VAR17 <= 1;
VAR58 <= VAR26;
VAR56 <= 0;
if (VAR17)
VAR16 <= 1;
end
else if (state != 0)
if (VAR46)
VAR56 <= ~VAR56;
if (VAR56 ^ 0 ^ 0)
begin
if (1)
VAR26 <= {VAR26[6 : 0], VAR52};
end
else
VAR52 <= VAR11;
end
end
end
assign VAR11 = VAR1;
endmodule
module MODULE1 (
VAR32,
VAR55,
VAR72,
VAR3,
VAR35
)
;
output VAR35;
input VAR32;
input VAR55;
input VAR72;
input VAR3;
wire VAR35;
assign VAR35 = VAR3 | VAR72 | VAR32 | VAR55;
endmodule
module MODULE2 (
address,
VAR48,
clk,
VAR40,
VAR64,
VAR44,
VAR24,
VAR25,
VAR18,
irq,
VAR83,
VAR31
)
;
parameter VAR47 = "VAR36.VAR4";
output VAR25;
output VAR18;
output irq;
output [ 31: 0] VAR83;
output VAR31;
input [ 8: 0] address;
input VAR48;
input clk;
input VAR40;
input VAR64;
input VAR44;
input [ 31: 0] VAR24;
wire VAR1;
wire VAR60;
wire VAR27;
wire VAR6;
wire [ 15: 0] VAR76;
wire [ 15: 0] VAR73;
wire VAR25;
wire VAR18;
wire VAR94;
wire irq;
wire [ 2: 0] VAR49;
wire [ 31: 0] VAR83;
wire VAR31;
wire [ 31: 0] VAR20;
MODULE3 MODULE1
(
.VAR1 (VAR1),
.VAR60 (VAR60),
.VAR27 (VAR27),
.VAR6 (VAR6),
.clk (clk),
.VAR76 (VAR76),
.VAR73 (VAR73),
.VAR25 (VAR25),
.VAR18 (VAR18),
.VAR94 (VAR94),
.irq (irq),
.VAR49 (VAR49),
.VAR40 (VAR40),
.VAR31 (VAR31),
.VAR64 (VAR64),
.VAR44 (VAR44)
);
MODULE1 MODULE2
(
.VAR35 (VAR1),
.VAR32 (VAR27),
.VAR55 (1'b0),
.VAR72 (VAR6),
.VAR3 (VAR60)
);
assign VAR94 = VAR48 && (address[7] );
assign VAR49 = address;
assign VAR76 = VAR24;
assign VAR83 = VAR94 ? VAR73 : VAR20;
VAR7 VAR53
(
.VAR78 (address[6 : 0]),
.VAR71 (clk),
.VAR38 (VAR20)
);
VAR53.VAR41 = VAR47,
VAR53.VAR9 = "VAR7",
VAR53.VAR68 = 128,
VAR53.VAR42 = "VAR61",
VAR53.VAR79 = "VAR50",
VAR53.VAR92 = "VAR84",
VAR53.VAR74 = 32,
VAR53.VAR43 = 7;
endmodule
|
mit
|
theHawke/real-dcpu
|
ALU/shift16.v
| 3,948 |
module MODULE1 (
VAR12,
VAR17,
VAR6,
VAR1);
input [31:0] VAR12;
input VAR17;
input [3:0] VAR6;
output [31:0] VAR1;
wire [31:0] VAR18;
wire [31:0] VAR1 = VAR18[31:0];
VAR4 VAR5 (
.VAR12 (VAR12),
.VAR17 (VAR17),
.VAR6 (VAR6),
.VAR1 (VAR18)
,
.VAR7 (),
.VAR8 (),
.VAR3 (),
.VAR9 (),
.VAR14 ()
);
VAR5.VAR2 = "VAR10",
VAR5.VAR15 = "VAR11",
VAR5.VAR16 = 32,
VAR5.VAR13 = 4;
endmodule
|
gpl-2.0
|
cpulabs/mist1032isa
|
src/lib/mist1032isa_async_fifo.v
| 3,801 |
module MODULE1
parameter VAR25 = 16,
parameter VAR13 = 4,
parameter VAR3 = 2
)
(
input wire VAR23,
input wire VAR11,
input wire VAR16,
input wire VAR2,
input wire [VAR25-1:0] VAR12,
output wire VAR33,
input wire VAR22,
input wire VAR9,
output wire [VAR25-1:0] VAR14,
output wire VAR15
);
wire [VAR3:0] VAR18;
wire VAR26;
wire [VAR3:0] VAR10;
wire VAR5;
reg [VAR25-1:0] VAR1[0:VAR13-1];
reg [VAR3:0] VAR35; reg [VAR3:0] VAR34; wire [VAR3:0] VAR24;
wire [VAR3:0] VAR31;
wire [VAR3:0] VAR21;
wire [VAR3:0] VAR17;
assign VAR18 = VAR35 - VAR31;
assign VAR26 = VAR18[VAR3] || (VAR18[VAR3-1:0] == {VAR3{1'b1}})? 1'b1 : 1'b0;
assign VAR10 = VAR17 - (VAR34);
assign VAR5 = (VAR10 == {VAR3+1{1'b0}})? 1'b1 : 1'b0;
always@(posedge VAR16 or negedge VAR23)begin
if(!VAR23)begin
VAR35 <= {VAR3{1'b0}};
end
else if(VAR11)begin
VAR35 <= {VAR3{1'b0}};
end
else begin
if(VAR2 && !VAR26)begin
VAR1[VAR35[VAR3-1:0]] <= VAR12;
VAR35 <= VAR35 + {{VAR3-1{1'b0}}, 1'b1};
end
end
end
always@(posedge VAR22 or negedge VAR23)begin
if(!VAR23)begin
VAR34 <= {VAR3{1'b0}};
end
else if(VAR11)begin
VAR34 <= {VAR3{1'b0}};
end
else begin
if(VAR9 && !VAR5)begin
VAR34 <= VAR34 + {{VAR3-1{1'b0}}, 1'b1};
end
end
end
VAR30 #(VAR3+1) VAR19(
.VAR27(VAR16),
.VAR23(VAR23),
.VAR7(VAR32(VAR34)),
.VAR28(VAR24)
);
assign VAR31 = VAR8(VAR24);
VAR30 #(VAR3+1) VAR4(
.VAR27(VAR22),
.VAR23(VAR23),
.VAR7(VAR32(VAR35)),
.VAR28(VAR21)
);
assign VAR17 = VAR8(VAR21);
function [VAR3:0] VAR32;
input [VAR3:0] VAR6;
begin
VAR32 = VAR6 ^ (VAR6 >> 1'b1);
end
endfunction
function[VAR3:0] VAR8(input[VAR3:0] VAR29);
integer VAR20;
for(VAR20=VAR3; VAR20>=0; VAR20=VAR20-1)begin
if(VAR20==VAR3)begin
VAR8[VAR20] = VAR29[VAR20];
end
else begin
VAR8[VAR20] = VAR29[VAR20] ^ VAR8[VAR20+1];
end
end
endfunction
assign VAR33 = VAR26;
assign VAR15 = VAR5;
assign VAR14 = VAR1[VAR34[VAR3-1:0]];
endmodule
|
bsd-2-clause
|
olajep/oh
|
src/adi/hdl/library/common/up_dac_common.v
| 15,322 |
module MODULE1 #(
parameter VAR6 = 0,
parameter VAR24 = 0,
parameter VAR72 = 1'b0,
parameter VAR47 = 6'h10,
parameter VAR13 = 0,
parameter VAR69 = 0,
parameter VAR111 = 0) (
output VAR25,
input VAR105,
output VAR65,
output VAR40,
output VAR103,
output VAR95,
output VAR56,
output VAR109,
output VAR38,
output VAR90,
output [15:0] VAR106,
input VAR77,
input VAR107,
input [31:0] VAR32,
output VAR34,
input [31:0] VAR63,
input VAR15,
output reg VAR66,
output VAR8,
output VAR70,
output [11:0] VAR89,
output [31:0] VAR11,
input [31:0] VAR83,
input VAR91,
input VAR19,
output [ 7:0] VAR86,
input [ 7:0] VAR60,
input [31:0] VAR18,
output [31:0] VAR96,
input VAR101,
input VAR20,
input VAR104,
input [13:0] VAR36,
input [31:0] VAR30,
output VAR58,
input VAR110,
input [13:0] VAR16,
output [31:0] VAR99,
output VAR64);
localparam VAR88 = 32'h00090062;
reg VAR108 = 'd1;
reg VAR7 = 'd1;
reg VAR76 = 'd0;
reg [31:0] VAR53 = 'd0;
reg VAR75 = 'd0;
reg VAR57 = 'd0;
reg VAR44 = 'd0;
reg VAR100 = 'd0;
reg VAR73 = 'd0;
reg VAR5 = 'd0;
reg VAR80 = 'd0;
reg VAR52 = 'd0;
reg VAR39 = 'd0;
reg [15:0] VAR33 = 'd0;
reg VAR78 = 'd0;
reg VAR112 = VAR72;
reg VAR61 = 'd0;
reg [ 7:0] VAR62 = 'd0;
reg [31:0] VAR31 = 'd0;
reg [31:0] VAR59 = 'd0;
reg VAR84 = 'd0;
reg [31:0] VAR85 = 'd0;
reg VAR92 = 'd0;
reg VAR43 = 'd0;
reg [ 5:0] VAR98 = 'd0;
reg VAR51 = 'd0;
reg VAR94 = 'd0;
reg VAR10 = 'd0;
reg VAR74 = 'd0;
wire VAR46;
wire VAR12;
wire VAR3;
wire VAR113;
wire VAR97;
wire VAR68;
wire VAR67;
wire [31:0] VAR37;
wire VAR71;
wire VAR2;
wire [31:0] VAR22;
assign VAR46 = (VAR36[13:8] == VAR47) ? VAR104 : 1'b0;
assign VAR12 = (VAR16[13:8] == VAR47) ? VAR110 : 1'b0;
assign VAR34 = VAR75;
assign VAR58 = VAR76;
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR108 <= 1'd1;
VAR7 <= 1'd1;
VAR76 <= 'd0;
VAR53 <= 'd0;
VAR75 <= 'd1;
VAR57 <= 'd0;
VAR44 <= 'd0;
VAR100 <= 'd0;
VAR73 <= 'd0;
VAR5 <= 'd0;
VAR80 <= 'd0;
VAR52 <= 'd0;
VAR39 <= 'd0;
VAR33 <= 'd0;
VAR78 <= 'd0;
VAR112 <= VAR72;
VAR66 <= 1'b1;
end else begin
VAR75 <= ~VAR57;
VAR108 <= ~VAR100;
VAR7 <= ~VAR44;
VAR76 <= VAR46;
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h02)) begin
VAR53 <= VAR30;
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h04)) begin
VAR66 <= VAR30[0];
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h10)) begin
VAR57 <= VAR30[2];
VAR44 <= VAR30[1];
VAR100 <= VAR30[0];
end
if (VAR73 == 1'b1) begin
if (VAR3 == 1'b1) begin
VAR73 <= 1'b0;
end
end else if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h11)) begin
VAR73 <= VAR30[0];
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h12)) begin
VAR5 <= VAR30[7];
VAR80 <= VAR30[6];
VAR52 <= VAR30[5];
VAR39 <= VAR30[4];
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h13)) begin
VAR33 <= VAR30[15:0];
end
if (VAR78 == 1'b1) begin
if (VAR3 == 1'b1) begin
VAR78 <= 1'b0;
end
end else if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h14)) begin
VAR78 <= VAR30[0];
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h18)) begin
VAR112 <= VAR30[0];
end
end
end
generate
if (VAR13 == 1) begin
assign VAR8 = 'd0;
assign VAR70 = 'd0;
assign VAR71 = 'd0;
assign VAR2 = 'd0;
assign VAR89 = 'd0;
assign VAR11 = 'd0;
assign VAR22 = 'd0;
end else begin
reg VAR102 = 'd0;
reg VAR42 = 'd0;
reg VAR81 = 'd0;
reg VAR9 = 'd0;
reg [11:0] VAR87 = 'd0;
reg [31:0] VAR4 = 'd0;
reg [31:0] VAR50 = 'd0;
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR102 <= 'd0;
VAR42 <= 'd0;
VAR81 <= 'd0;
VAR9 <= 'd0;
VAR87 <= 'd0;
VAR4 <= 'd0;
VAR50 <= 'd0;
end else begin
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h1c)) begin
VAR102 <= 1'b1;
VAR42 <= ~VAR30[28];
end else begin
VAR102 <= 1'b0;
VAR42 <= 1'b0;
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h1c)) begin
VAR81 <= 1'b1;
end else if (VAR91 == 1'b1) begin
VAR81 <= 1'b0;
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h1c)) begin
VAR9 <= VAR30[28];
VAR87 <= VAR30[27:16];
end
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h1e)) begin
VAR4 <= VAR30;
end
if (VAR91 == 1'b1) begin
VAR50 <= VAR83;
end
end
end
assign VAR8 = VAR102;
assign VAR70 = VAR42;
assign VAR71 = VAR81;
assign VAR2 = VAR9;
assign VAR89 = VAR87;
assign VAR11 = VAR4;
assign VAR22 = VAR50;
end
endgenerate
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR61 <= 'd0;
end else begin
if (VAR97 == 1'b1) begin
VAR61 <= 1'b1;
end else if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h22)) begin
VAR61 <= VAR61 & ~VAR30[0];
end
end
end
assign VAR86 = VAR62;
generate
if (VAR69 == 1) begin
always @(posedge VAR20) begin
VAR62 <= 'd0;
end
end else begin
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR62 <= 'd0;
end else begin
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h28)) begin
VAR62 <= VAR30[7:0];
end
end
end
end
endgenerate
assign VAR96 = VAR31;
generate
if (VAR111 == 1) begin
always @(posedge VAR20) begin
VAR31 <= 'd0;
end
end else begin
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR31 <= 'd0;
end else begin
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h2f)) begin
VAR31 <= VAR30;
end
end
end
end
endgenerate
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR59 <= 32'd0;
end else begin
if ((VAR46 == 1'b1) && (VAR36[7:0] == 8'h40)) begin
VAR59 <= VAR30;
end else if (VAR59 > 0) begin
VAR59 <= VAR59 - 1'b1;
end
end
end
assign VAR64 = VAR84;
assign VAR99 = VAR85;
always @(negedge VAR101 or posedge VAR20) begin
if (VAR101 == 0) begin
VAR84 <= 'd0;
VAR85 <= 'd0;
end else begin
VAR84 <= VAR12;
if (VAR12 == 1'b1) begin
case (VAR16[7:0])
8'h00: VAR85 <= VAR88;
8'h01: VAR85 <= VAR6;
8'h02: VAR85 <= VAR53;
8'h03: VAR85 <= VAR24;
8'h10: VAR85 <= {29'd0, VAR57, VAR44, VAR100};
8'h11: VAR85 <= {31'd0, VAR73};
8'h12: VAR85 <= {24'd0, VAR5, VAR80, VAR52,
VAR39, 4'd0};
8'h13: VAR85 <= {16'd0, VAR33};
8'h14: VAR85 <= {31'd0, VAR78};
8'h15: VAR85 <= VAR37;
8'h16: VAR85 <= VAR32;
8'h17: VAR85 <= {31'd0, VAR113};
8'h18: VAR85 <= {31'd0, VAR112};
8'h1c: VAR85 <= {3'd0, VAR2, VAR89, 16'b0};
8'h1d: VAR85 <= {14'd0, VAR19, VAR71, 16'b0};
8'h1e: VAR85 <= VAR11;
8'h1f: VAR85 <= VAR22;
8'h22: VAR85 <= {31'd0, VAR61};
8'h28: VAR85 <= {24'd0, VAR60};
8'h2e: VAR85 <= VAR18;
8'h2f: VAR85 <= VAR31;
8'h30: VAR85 <= VAR63;
8'h31: VAR85 <= VAR15;
8'h40: VAR85 <= VAR59;
default: VAR85 <= 0;
endcase
end else begin
VAR85 <= 32'd0;
end
end
end
VAR55 VAR41 (.VAR26(VAR7), .clk(VAR20), .VAR1(), .rst(VAR25));
VAR55 VAR45 (.VAR26(VAR108), .clk(VAR105), .VAR1(), .rst(VAR65));
VAR114 #(.VAR29(23)) VAR48 (
.VAR101 (VAR101),
.VAR20 (VAR20),
.VAR35 ({ VAR73,
VAR112,
VAR78,
VAR5,
VAR80,
VAR52,
VAR39,
VAR33}),
.VAR93 (VAR3),
.VAR54 (VAR65),
.VAR49 (VAR105),
.VAR79 ({ VAR68,
VAR95,
VAR67,
VAR56,
VAR109,
VAR38,
VAR90,
VAR106}));
VAR14 #(.VAR29(2)) VAR28 (
.VAR101 (VAR101),
.VAR20 (VAR20),
.VAR21 ({VAR113,
VAR97}),
.VAR54 (VAR65),
.VAR49 (VAR105),
.VAR27 ({ VAR77,
VAR107}));
assign VAR40 = VAR51;
assign VAR103 = VAR74;
always @(posedge VAR105) begin
VAR92 <= VAR68;
VAR43 <= VAR92;
if (VAR98[5] == 1'b1) begin
VAR98 <= VAR98 + 1'b1;
end else if ((VAR92 == 1'b1) && (VAR43 == 1'b0)) begin
VAR98 <= 6'h20;
end
VAR51 <= VAR98[5];
VAR94 <= VAR67;
VAR10 <= VAR94;
VAR74 <= VAR94 & ~VAR10;
end
VAR23 VAR17 (
.VAR101 (VAR101),
.VAR20 (VAR20),
.VAR82 (VAR37),
.VAR54 (VAR65),
.VAR49 (VAR105));
endmodule
|
mit
|
gbraad/minimig-de1
|
rtl/ctrl/ctrl_boot.v
| 6,711 |
module MODULE1 (
address,
VAR33,
VAR17);
input [10:0] address;
input VAR33;
output [31:0] VAR17;
tri1 VAR33;
wire [31:0] VAR9;
wire [31:0] VAR17 = VAR9[31:0];
VAR52 VAR8 (
.VAR22 (address),
.VAR49 (VAR33),
.VAR55 (VAR9),
.VAR37 (1'b0),
.VAR21 (1'b0),
.VAR51 (1'b1),
.VAR18 (1'b0),
.VAR4 (1'b0),
.VAR5 (1'b1),
.VAR27 (1'b1),
.VAR40 (1'b1),
.VAR14 (1'b1),
.VAR12 (1'b1),
.VAR19 (1'b1),
.VAR50 (1'b1),
.VAR35 ({32{1'b1}}),
.VAR1 (1'b1),
.VAR54 (),
.VAR48 (),
.VAR45 (1'b1),
.VAR16 (1'b1),
.VAR7 (1'b0),
.VAR39 (1'b0));
VAR8.VAR11 = "VAR46",
VAR8.VAR20 = "VAR46",
VAR8.VAR41 = "../../VAR29/MODULE1/VAR47/MODULE1.VAR36",
VAR8.VAR3 = "VAR15 VAR25",
VAR8.VAR34 = "VAR13=VAR42",
VAR8.VAR53 = "VAR52",
VAR8.VAR24 = 512,
VAR8.VAR23 = 1280,
VAR8.VAR43 = "VAR10",
VAR8.VAR28 = "VAR30",
VAR8.VAR32 = "VAR2",
VAR8.VAR31 = "VAR44",
VAR8.VAR38 = 11,
VAR8.VAR6 = 32,
VAR8.VAR26 = 1;
endmodule
|
gpl-3.0
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/bd/system/ip/system_auto_us_0/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v
| 4,336 |
module MODULE1 #
(
parameter VAR4 = "VAR3"
)
(
input wire VAR9,
input wire VAR8,
output wire VAR10
);
generate
if ( VAR4 == "VAR1" ) begin : VAR2
assign VAR10 = VAR9 & VAR8;
end else begin : VAR7
VAR5 VAR6
(
.VAR12 (VAR10),
.VAR13 (VAR9),
.VAR11 (1'b0),
.VAR8 (VAR8)
);
end
endgenerate
endmodule
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_6/synth/bd_350b_slot_0_r_0.v
| 4,558 |
module MODULE1 (
VAR39,
VAR42,
dout
);
input wire [0 : 0] VAR39;
input wire [0 : 0] VAR42;
output wire [1 : 0] dout;
VAR57 #(
.VAR69(1),
.VAR36(1),
.VAR67(1),
.VAR15(1),
.VAR24(1),
.VAR2(1),
.VAR18(1),
.VAR38(1),
.VAR26(1),
.VAR62(1),
.VAR66(1),
.VAR11(1),
.VAR14(1),
.VAR10(1),
.VAR6(1),
.VAR13(1),
.VAR19(1),
.VAR51(1),
.VAR3(1),
.VAR23(1),
.VAR52(1),
.VAR31(1),
.VAR61(1),
.VAR56(1),
.VAR50(1),
.VAR4(1),
.VAR7(1),
.VAR27(1),
.VAR54(1),
.VAR37(1),
.VAR33(1),
.VAR47(1),
.VAR17(2),
.VAR8(2)
) VAR32 (
.VAR39(VAR39),
.VAR42(VAR42),
.VAR28(1'VAR60),
.VAR25(1'VAR60),
.VAR29(1'VAR60),
.VAR30(1'VAR60),
.VAR49(1'VAR60),
.VAR40(1'VAR60),
.VAR46(1'VAR60),
.VAR9(1'VAR60),
.VAR45(1'VAR60),
.VAR53(1'VAR60),
.VAR63(1'VAR60),
.VAR22(1'VAR60),
.VAR12(1'VAR60),
.VAR41(1'VAR60),
.VAR5(1'VAR60),
.VAR64(1'VAR60),
.VAR21(1'VAR60),
.VAR55(1'VAR60),
.VAR20(1'VAR60),
.VAR16(1'VAR60),
.VAR68(1'VAR60),
.VAR59(1'VAR60),
.VAR34(1'VAR60),
.VAR43(1'VAR60),
.VAR1(1'VAR60),
.VAR35(1'VAR60),
.VAR58(1'VAR60),
.VAR48(1'VAR60),
.VAR65(1'VAR60),
.VAR44(1'VAR60),
.dout(dout)
);
endmodule
|
mit
|
tugrulyatagan/RISC-processor
|
xilinx_processor/control_unit.v
| 8,853 |
module MODULE1(
input [15:0] VAR13,
output reg [2:0] VAR10,
output reg [2:0] VAR19,
output reg [2:0] VAR6,
output reg VAR5,
output reg VAR7,
output reg [7:0] VAR2,
output reg [15:0] VAR1,
output reg VAR11,
output reg VAR17,
output reg VAR18,
output reg [3:0] VAR16,
output reg VAR4,
output reg VAR8,
output reg VAR12
);
always @(*) begin
casex (VAR13[15:12])
4'b0000: begin
VAR10 = 3'h0;
VAR19 = 3'h0;
VAR6 = 3'h0;
VAR5 = 0;
VAR7 = 0;
VAR2 = 8'h00;
VAR1 = 16'h0000;
VAR11 = 0;
VAR17 = 0;
VAR18 = 0;
VAR16 = 4'h0;
case (VAR13[2:0])
3'b001: begin
VAR4 = 1;
VAR8 = 0;
VAR12 = 0;
end
3'b010: begin
VAR8 = 1;
VAR4 = 0;
VAR12 = 0;
end
3'b011: begin
VAR12 = 1;
VAR4 = 0;
VAR8 = 0;
end
endcase
end
4'b0001: begin
VAR10 = VAR13[5:3];
VAR19 = 3'h0;
VAR6 = VAR13[2:0];
VAR5 = 1;
VAR7 = 1;
VAR1 = {12'h000, VAR13[9:6]};
VAR11 = 0;
VAR17 = 0;
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
case (VAR13[11:10])
2'b00: VAR2 = 8'he3;
2'b01: VAR2 = 8'he4;
2'b10: VAR2 = 8'he5;
2'b11: VAR2 = 8'he6;
endcase
end
4'VAR9: begin
VAR10 = VAR13[5:3];
VAR19 = 3'h0;
VAR6 = VAR13[2:0];
VAR5 = 1;
VAR7 = 1;
VAR1 = {10'h000, VAR13[11:6]};
VAR11 = 0;
VAR17 = 0;
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
case (VAR13[12])
0: VAR2 = 8'hf7;
1: VAR2 = 8'hf8;
endcase
end
4'VAR21: begin
VAR19 = 3'h0;
VAR7 = 1;
VAR1 = {8'h00, VAR13[7:0]};
VAR11 = 0;
VAR17 = 0;
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
case (VAR13[12:11])
2'b00: begin
VAR10 = 3'h0;
VAR2 = 8'hcf;
VAR6 = VAR13[10:8];
VAR5 = 1;
end
2'b01: begin
VAR10 = VAR13[10:8];
VAR2 = 8'hf8;
VAR6 = 3'h0;
VAR5 = 0;
end
2'b10: begin
VAR10 = VAR13[10:8];
VAR2 = 8'hf7;
VAR6 = VAR13[10:8];
VAR5 = 1;
end
2'b11: begin
VAR10 = VAR13[10:8];
VAR2 = 8'hf8;
VAR6 = VAR13[10:8];
VAR5 = 1;
end
endcase
end
4'VAR20: begin
VAR10 = 3'h0;
VAR19 = 3'h0;
VAR7 = 0;
VAR1 = 16'h0000;
VAR11 = 0;
VAR17 = 0;
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
case (VAR13[12:9])
4'h0: begin
VAR2 = 8'hc0;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h1: begin
VAR2 = 8'hc1;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h2: begin
VAR2 = 8'hc2;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h3: begin
VAR2 = 8'he3;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h4: begin
VAR2 = 8'he4;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h5: begin
VAR2 = 8'he5;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h6: begin
VAR2 = 8'he6;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h7: begin
VAR2 = 8'hf7;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h8: begin
VAR2 = 8'hf8;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'h9: begin
VAR2 = 8'hc9;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'ha: begin
VAR2 = 8'hca;
VAR6 = VAR13[2:0];
VAR5 = 1;
end
4'hb: begin
VAR2 = 8'hf8;
VAR6 = 3'h0;
VAR5 = 0;
end
4'hc: begin
VAR2 = 8'hf0;
VAR6 = 3'h0;
VAR5 = 0;
end
endcase
end
4'VAR15: begin
VAR10 = VAR13[5:3];
VAR19 = VAR13[8:6];
VAR6 = VAR13[2:0];
VAR5 = 1;
VAR7 = 0;
VAR2 = 8'h07;
VAR1 = 16'h0000;
VAR11 = 0;
VAR17 = 1;
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
end
4'VAR14: begin
VAR10 = VAR13[5:3];
VAR7 = 1;
VAR2 = 8'h07;
VAR1 = {10'h000, VAR13[11:6]};
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
case (VAR13[12])
0: begin
VAR19 = 3'h0;
VAR6 = VAR13[2:0];
VAR5 = 1;
VAR11 = 0;
VAR17 = 1;
end
1: begin
VAR19 = VAR13[2:0];
VAR6 = 3'h0;
VAR5 = 0;
VAR11 = 1;
VAR17 = 0;
end
endcase
end
4'VAR3: begin
VAR10 = 3'h0;
VAR19 = 3'h0;
VAR6 = 3'h0;
VAR5 = 0;
VAR7 = 1;
VAR2 = 8'h0f;
VAR1 = {7'h00, VAR13[8:0]};
VAR11 = 0;
VAR17 = 0;
VAR18 = 1;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
case (VAR13[12:9])
4'h0: VAR16 = 4'h0;
4'h1: VAR16 = 4'h1;
4'h2: VAR16 = 4'h2;
4'h3: VAR16 = 4'h3;
4'h4: VAR16 = 4'h4;
4'h5: VAR16 = 4'h5;
4'h6: VAR16 = 4'h6;
4'h7: VAR16 = 4'h7;
4'h8: VAR16 = 4'h8;
4'h9: VAR16 = 4'h9;
4'ha: VAR16 = 4'ha;
4'hb: VAR16 = 4'hb;
4'hc: VAR16 = 4'hc;
4'hd: VAR16 = 4'hd;
endcase
end
4'b1110: begin
VAR10 = 3'h0;
VAR19 = 3'h0;
VAR6 = 3'h0;
VAR5 = 0;
VAR7 = 1;
VAR2 = 8'h0f;
VAR1 = {4'h0, VAR13[11:0]};
VAR11 = 0;
VAR17 = 0;
VAR18 = 1;
VAR16 = 4'hf;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
end
4'b1111: begin
VAR10 = 3'h0;
VAR19 = 3'h0;
VAR6 = 3'h0;
VAR5 = 1;
VAR7 = 1;
VAR2 = 8'h0f;
VAR1 = {4'h0, VAR13[11:0]};
VAR11 = 0;
VAR17 = 0;
VAR18 = 0;
VAR16 = 4'h0;
VAR4 = 0;
VAR8 = 0;
VAR12 = 0;
end
endcase
end
endmodule
|
gpl-2.0
|
skalldri/mips-verilog
|
fetch-decode/fetch.v
| 1,114 |
module MODULE1 (clk, VAR11, VAR13, VAR5, VAR12, VAR4, enable, VAR6, VAR2, VAR9, VAR10);
parameter VAR3 = 32'h80020000;
input clk;
input VAR11;
input VAR13;
input [31:0] VAR6;
input VAR2;
input [31:0] VAR9;
input VAR10;
output [31:0] VAR5;
output [2:0] VAR4;
output VAR12; output enable;
reg [31:0] VAR8 = 32'h8001FFFC; reg [2:0] VAR7 = 3'b000;
reg VAR14 = 1'b0;
reg VAR1 = 1'b1;
assign VAR5 = VAR8;
assign VAR4 = VAR7;
assign VAR12 = VAR14;
assign enable = VAR1;
always @(posedge clk)
begin
if(VAR11 != 1 & VAR13 != 1)
begin
if(VAR2 != 1 & VAR10 != 1)
begin
VAR8 = VAR8 + 32'h00000004;
end
else if (VAR10 == 1)
begin
VAR8 = VAR9;
end
else if(VAR2 == 1)
begin
VAR8 = VAR6;
end
end
else if (VAR10 == 1)
begin
VAR8 = VAR9;
end
else if(VAR2 == 1)
begin
VAR8 = VAR6;
end
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/edfxtp/sky130_fd_sc_hs__edfxtp.behavioral.v
| 1,921 |
module MODULE1 (
VAR5 ,
VAR13 ,
VAR1 ,
VAR9 ,
VAR15,
VAR14
);
output VAR5 ;
input VAR13 ;
input VAR1 ;
input VAR9 ;
input VAR15;
input VAR14;
wire VAR6 ;
reg VAR3 ;
wire VAR11 ;
wire VAR16 ;
wire VAR7;
wire VAR10 ;
wire VAR4 ;
VAR8 VAR2 (VAR6 , VAR11, VAR7, VAR16, VAR3, VAR15, VAR14);
assign VAR10 = ( VAR15 === 1'b1 );
assign VAR4 = ( VAR10 && ( VAR16 === 1'b1 ) );
buf VAR12 (VAR5 , VAR6 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nand3b/sky130_fd_sc_lp__nand3b_lp.v
| 2,237 |
module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR7,
VAR10,
VAR5 ,
VAR6
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR7;
input VAR10;
input VAR5 ;
input VAR6 ;
VAR1 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR4 ,
VAR9,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR9;
input VAR3 ;
input VAR8 ;
supply1 VAR7;
supply0 VAR10;
supply1 VAR5 ;
supply0 VAR6 ;
VAR1 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
YuxuanLing/trunk
|
trunk/references/h265enc_v1.0/rtl/tq/mcm00.v
| 3,125 |
module MODULE1(
clk,
rst,
VAR2,
VAR11,
VAR14,
VAR15,
VAR10,
o0,
o1,
o2,
o3
);
input clk;
input rst;
input VAR2;
input signed [19:0] VAR11;
input signed [19:0] VAR14;
input signed [19:0] VAR15;
input signed [19:0] VAR10;
output reg signed [19+7+1:0] o0;
output reg signed [19+7+1:0] o1;
output reg signed [19+7+1:0] o2;
output reg signed [19+7+1:0] o3;
wire signed [19+7:0] VAR6;
wire signed [19+7:0] VAR1;
wire signed [19+7:0] VAR19;
wire signed [19+7:0] VAR13;
wire signed [19+7:0] VAR3;
wire signed [19+7:0] VAR21;
wire signed [19+8:0] VAR19;
wire signed [19+8:0] VAR13;
wire signed [19+8:0] VAR3;
wire signed [19+8:0] VAR21;
wire signed [19+8:0] VAR4;
wire signed [19+8:0] VAR8;
wire signed [19+8:0] VAR17;
wire signed [19+8:0] VAR7;
assign VAR6=64*VAR11;
assign VAR1=64*VAR14;
assign VAR4 =VAR6+VAR1;
assign VAR8 =VAR6-VAR1;
assign VAR19 =VAR19+VAR21;
assign VAR13 =VAR19-VAR21;
assign VAR17=VAR2?VAR13:VAR19;
assign VAR3 =-VAR13+VAR3;
assign VAR21 =VAR13+VAR3;
assign VAR7=VAR2?VAR21:VAR3;
always @(posedge clk or negedge rst)
if(!rst)
begin
o0<=28'b0;
o1<=28'b0;
o2<=28'b0;
o3<=28'b0;
end
else
begin
o0<=VAR4;
o1<=VAR8;
o2<=VAR17;
o3<=VAR7;
end
VAR18 VAR9(
.VAR12(VAR15),
.VAR20(VAR19),
.VAR5(VAR13)
);
VAR18 VAR16(
.VAR12(VAR10),
.VAR20(VAR3),
.VAR5(VAR21)
);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/tapmet1/sky130_fd_sc_hs__tapmet1.symbol.v
| 1,207 |
module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
endmodule
|
apache-2.0
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/yacc/mul_div_module5.v
| 8,683 |
module MODULE1(VAR17,VAR20,VAR38,VAR4,VAR18,VAR47,VAR41,VAR16,state,VAR5,VAR31,VAR3);
parameter VAR6=16; parameter VAR34=2;
parameter VAR6=1; parameter VAR34=32; VAR2
parameter VAR6=16; parameter VAR34=2;
parameter VAR6=16; parameter VAR34=2; else
parameter VAR6=1; parameter VAR34=32; VAR2
input VAR17,VAR20;
input [31:0] VAR38,VAR4;
input [7:0] state;
input VAR3;
input VAR31,VAR47,VAR41,VAR16;
output VAR5;
output [31:0] VAR18;
reg [31:0] VAR28;
reg [31:0] VAR21;
reg [31:0] VAR7;
reg VAR1; reg [5:0] counter;
reg VAR22,VAR27;
reg VAR11,VAR32;
reg VAR12;
wire [63:0] VAR13={1'b0,VAR28[31]*VAR12,62'h0}; wire [63:0] VAR44=VAR22 ? ~{2'b0,VAR28[30:0],31'h0}+1'b1: {2'b0,VAR28[30:0],31'h0} ; wire [63:0] VAR10=VAR22 ? ~{2'b0,VAR21[30:0],31'h0}+1'b1: {2'b0,VAR21[30:0],31'h0};
wire [30:0] VAR24 =VAR12*VAR44[30:0] +VAR28[31]*VAR10[30:0]+VAR13[30:0]; wire [63:31] VAR36=VAR12*VAR44[63:31]+VAR28[31]*VAR10[63:31]+VAR13[63:31]; wire [63:0] VAR37={VAR36,VAR24};
wire [VAR6+30 :0] VAR23=VAR28[30:0]*VAR21[VAR6-1:0]; wire [VAR6+31 :0] VAR14={1'b0,VAR23};
reg [63:0] VAR48;
reg [31:0] VAR26;
wire [63:0] VAR42;
wire [63:0] VAR8=VAR28* VAR21;
reg [VAR6+31-1+1 :0] VAR40;
wire VAR25;
wire VAR39;
wire [32:0] sum;
wire [31:0] VAR43;
wire [31:0] VAR45=-VAR38;
wire [31:0] VAR46,VAR9;
wire VAR19;
reg VAR30;
reg VAR33;
assign VAR19=VAR39 ? VAR16: VAR27;
assign VAR18=!VAR3 ? !VAR27 ? VAR42[31:0] : VAR46 :
!VAR27 ? VAR42[63:32] : VAR46;
assign VAR9=!VAR3 ? VAR7: {VAR33,VAR26[31:1]};
assign VAR46= (!VAR3 && (VAR11 ^ VAR32) && VAR22) ||
(VAR3 && VAR22 && VAR11) ? ~VAR9+1'b1 : VAR9;
reg [31:0] VAR35,VAR15;
assign VAR18=!VAR3 ? !VAR27 ? VAR42[31:0] : VAR15 :
!VAR27 ? VAR42[63:32] : VAR35;
always @(posedge VAR17) begin
if ( (VAR11 ^ VAR32) && VAR22)
VAR15<=~VAR7+1'b1;
end
else VAR15<= VAR7;
if ( VAR22 && VAR11)
VAR35<=~{VAR33,VAR26[31:1]}+1'b1;
else VAR35<={VAR33,VAR26[31:1]};
end
always @(posedge VAR17) begin
VAR12<=VAR4[31];
end
always @(posedge VAR17) begin
VAR40<=VAR14;
end
always @(posedge VAR17) begin
if (VAR20) VAR30<=0;
end
else if (VAR39 && VAR19==VAR29 ) VAR30<=1;
else if (VAR25) VAR30<=0;
end
always @(posedge VAR17) begin
if (VAR30 && counter==0 )begin
VAR48<=VAR37; end
else
if (VAR30) begin
{VAR48,VAR26[31:31-VAR6+1]}<={{VAR6 {1'b0}},VAR48+VAR40};
VAR26[31-VAR6:0] <=VAR26[31:VAR6];
end else if (VAR39 && counter==0 ) VAR26<=0; else if (VAR27 && VAR1 ) begin
if (sum[32]==1'b0) begin if (VAR25) VAR33<=sum[31];
VAR26<={sum,VAR28[31]};
end else begin
if (VAR25) VAR33<=VAR26[31];
VAR26[0]<=VAR28[31];
VAR26[31:1] <=VAR26[30:0];
end
end
end
assign VAR42={VAR48[31:0],VAR26[31:0]};
always @(posedge VAR17) begin
if (VAR20) begin
VAR22<=0;
VAR27<=0;
end else if (VAR39) begin
VAR22<=VAR47;
VAR11<=VAR38[31];
VAR32<=VAR4[31];
VAR27<=VAR16;
end
end
assign VAR39=VAR31 ;
assign VAR25=(VAR27 && counter==32) || (VAR30 && counter==VAR34) ;
always @(posedge VAR17) begin
if (VAR20) VAR1 <=0;
end
else if (VAR39 && !VAR1 ) VAR1<=1;
end
else if (VAR1 && VAR25) VAR1<=0;
end
assign VAR5=VAR1;
always @(posedge VAR17) begin
if (VAR20) counter <=0;
end
else if (!VAR1) counter <=0;
end
else if (VAR1 ) counter <=counter+1;
end
always @(posedge VAR17) begin
end
if(VAR19==VAR29 && VAR39) VAR28 <=VAR38; else if(VAR19 !=VAR29 )begin if (!VAR1 && !VAR39) VAR28 <=VAR28; else if (VAR39 && counter==0 ) begin if (VAR47) begin if (VAR38[31]) VAR28 <=VAR45; else VAR28 <=VAR38;
end else VAR28 <=VAR38; end else begin VAR28 <={VAR28[30:0],1'b0}; end
end
end
always @(posedge VAR17) begin
if (VAR39 && VAR19==VAR29 ) VAR21<={1'b0,VAR4[30:0]};
end
else if ( VAR30) VAR21<=VAR21[31:VAR6];
else if( VAR19 !=VAR29) begin if (!VAR1 && !VAR39 ) VAR21 <=VAR21; else if (VAR39 && counter==0 ) begin if (VAR47) begin if ( VAR4[31]) VAR21 <=-VAR4[31:0]; else VAR21 <=VAR4[31:0]; end else begin
VAR21 <=VAR4[31:0]; end
end else begin VAR21 <=VAR21; end
end
end
always @(posedge VAR17) begin
end
if (VAR19 !=VAR29) begin if (!VAR1 && !VAR39) VAR7 <=VAR7; else if (VAR39 && counter==0 ) VAR7<=0; else begin if ( !sum[32] ) begin if (VAR25) VAR7 <=VAR43;
else VAR7 <={VAR43[30:0],1'b0}; end else begin
if (VAR25 ) begin
VAR7 <=VAR7;
end else VAR7 <={VAR7[30:0],1'b0}; end
end
end
end
assign sum={1'b0,VAR26}+~{1'b0,VAR21}+1'b1; assign VAR43=VAR7+1'b1;
endmodule
|
mit
|
markusC64/1541ultimate2
|
fpga/nios_c5/nios/synthesis/submodules/nios_mm_interconnect_0_avalon_st_adapter.v
| 6,146 |
module MODULE1 #(
parameter VAR13 = 34,
parameter VAR21 = 0,
parameter VAR3 = 34,
parameter VAR2 = 0,
parameter VAR16 = 0,
parameter VAR23 = 0,
parameter VAR24 = 1,
parameter VAR8 = 1,
parameter VAR5 = 0,
parameter VAR19 = 34,
parameter VAR17 = 0,
parameter VAR25 = 1,
parameter VAR9 = 0,
parameter VAR10 = 1,
parameter VAR12 = 1,
parameter VAR7 = 0
) (
input wire VAR1, input wire VAR14, input wire [33:0] VAR4, input wire VAR20, output wire VAR11, output wire [33:0] VAR6, output wire VAR22, input wire VAR15, output wire [0:0] VAR18 );
generate
if (VAR13 != 34)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/inv/sky130_fd_sc_hd__inv_6.v
| 1,995 |
module MODULE1 (
VAR5 ,
VAR3 ,
VAR6,
VAR1,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR4 ;
VAR2 VAR8 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR6;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR4 ;
VAR2 VAR8 (
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/dfrbp/sky130_fd_sc_hvl__dfrbp.pp.symbol.v
| 1,434 |
module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR8 ,
input VAR5,
input VAR9 ,
input VAR1 ,
input VAR2 ,
input VAR6 ,
input VAR7
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.functional.v
| 1,909 |
module MODULE1( VAR2, VAR9, VAR3, VAR13, VAR20, VAR10, VAR17 );
input VAR10, VAR17, VAR13, VAR20, VAR9, VAR3;
output VAR2;
wire VAR14;
not VAR5( VAR14, VAR10 );
wire VAR16;
not VAR23( VAR16, VAR17 );
wire VAR25;
and VAR7( VAR25, VAR14, VAR16 );
wire VAR15;
not VAR18( VAR15, VAR13 );
wire VAR22;
not VAR24( VAR22, VAR20 );
wire VAR12;
and VAR8( VAR12, VAR15, VAR22 );
wire VAR6;
not VAR4( VAR6, VAR9 );
wire VAR19;
not VAR1( VAR19, VAR3 );
wire VAR26;
and VAR21( VAR26, VAR6, VAR19 );
or VAR11( VAR2, VAR25, VAR12, VAR26 );
endmodule
|
apache-2.0
|
siamumar/TinyGarbled
|
circuit_synthesis/aes/KeyExpansionSeq.v
| 1,309 |
module MODULE1
(
VAR18,
counter,
VAR16
);
localparam VAR5 = 10;
input [127:0] VAR18;
input [3:0] counter;
output [127:0] VAR16;
wire [31:0] VAR10[3:0];
wire [31:0] VAR9[3:0];
wire [31:0] VAR12;
wire [7:0] VAR6[VAR5:0];
wire [31:0] VAR17;
wire [31:0] VAR2;
wire [95:0] VAR13;
assign VAR6[0] = 8'h01;
assign VAR6[1] = 8'h02;
assign VAR6[2] = 8'h04;
assign VAR6[3] = 8'h08;
assign VAR6[4] = 8'h10;
assign VAR6[5] = 8'h20;
assign VAR6[6] = 8'h40;
assign VAR6[7] = 8'h80;
assign VAR6[8] = 8'h1b;
assign VAR6[9] = 8'h36;
assign VAR6[10] = 8'h00;
genvar VAR14;
generate
for(VAR14=0;VAR14<4;VAR14=VAR14+1) begin:VAR4
assign VAR10[VAR14] = (counter<10)?VAR18[32*(VAR14+1)-1:32*VAR14]:32'b0;
assign VAR16[32*(VAR14+1)-1:32*VAR14] = VAR9[VAR14];
end
endgenerate
generate
for(VAR14=0;VAR14<4;VAR14=VAR14+1) begin:VAR19
if(VAR14==0) begin:VAR11
assign VAR9[VAR14] = VAR10[VAR14] ^ VAR12;
end else begin:VAR3
assign VAR9[VAR14] = VAR10[VAR14] ^ VAR9[VAR14-1];
end
end
endgenerate
assign VAR17 = {VAR10[3][7:0], VAR10[3][31:8]};
VAR8 VAR15(.VAR7({VAR17, 96'b0}), .VAR1({VAR2, VAR13}));
assign VAR12 = {VAR2[31:8], VAR6[counter] ^ VAR2[7:0]};
endmodule
|
gpl-3.0
|
ElegantLin/My-CPU
|
Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/div.v
| 4,942 |
module MODULE1(
input wire clk,
input wire rst,
input wire VAR1,
input wire[31:0] VAR19,
input wire[31:0] VAR8,
input wire VAR4,
input wire VAR18,
output reg[63:0] VAR15,
output reg VAR22
);
wire[32:0] VAR5;
reg[5:0] VAR13;
reg[64:0] VAR21;
reg[1:0] state;
reg[31:0] VAR7;
reg[31:0] VAR9;
reg[31:0] VAR6;
assign VAR5 = {1'b0,VAR21[63:32]} - {1'b0,VAR7};
always @ (posedge clk) begin
if (rst == VAR3) begin
state <= VAR10;
VAR22 <= VAR16;
VAR15 <= {VAR2,VAR2};
end else begin
case (state)
if(VAR8 == VAR2) begin
state <= VAR17;
end else begin
state <= VAR12;
VAR13 <= 6'b000000;
if(VAR1 == 1'b1 && VAR19[31] == 1'b1 ) begin
VAR9 = ~VAR19 + 1;
end else begin
VAR9 = VAR19;
end
if(VAR1 == 1'b1 && VAR8[31] == 1'b1 ) begin
VAR6 = ~VAR8 + 1;
end else begin
VAR6 = VAR8;
end
VAR21 <= {VAR2,VAR2};
VAR21[32:1] <= VAR9;
VAR7 <= VAR6;
end
end else begin
VAR22 <= VAR16;
VAR15 <= {VAR2,VAR2};
end
end
state <= VAR11;
end
if(VAR13 != 6'b100000) begin
if(VAR5[32] == 1'b1) begin
VAR21 <= {VAR21[63:0] , 1'b0};
end else begin
VAR21 <= {VAR5[31:0] , VAR21[31:0] , 1'b1};
end
VAR13 <= VAR13 + 1;
end else begin
if((VAR1 == 1'b1) && ((VAR19[31] ^ VAR8[31]) == 1'b1)) begin
VAR21[31:0] <= (~VAR21[31:0] + 1);
end
if((VAR1 == 1'b1) && ((VAR19[31] ^ VAR21[64]) == 1'b1)) begin
VAR21[64:33] <= (~VAR21[64:33] + 1);
end
state <= VAR11;
VAR13 <= 6'b000000;
end
end else begin
state <= VAR10;
end
end
VAR22 <= VAR20;
if(VAR4 == VAR14) begin
state <= VAR10;
VAR22 <= VAR16;
VAR15 <= {VAR2,VAR2};
end
end
endcase
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_4.v
| 2,345 |
module MODULE1 (
VAR8 ,
VAR4 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR10,
VAR2,
VAR5 ,
VAR6
);
output VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR10;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR11 VAR7 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8 ,
VAR4,
VAR1 ,
VAR9,
VAR3
);
output VAR8 ;
input VAR4;
input VAR1 ;
input VAR9;
input VAR3;
supply1 VAR10;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
VAR11 VAR7 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
kernelpanics/Grad
|
CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/Barrel_shifter.v
| 1,323 |
module MODULE1#(parameter VAR7=26, parameter VAR15=5)(
input wire clk,
input wire rst,
input wire VAR11,
input wire [VAR15-1:0] VAR4,
input wire [VAR7-1:0] VAR5,
input wire VAR14,
input wire VAR3,
output wire [VAR7-1:0] VAR10
);
wire [VAR7-1:0] VAR9;
VAR17 #(.VAR7(VAR7),.VAR15(VAR15)) VAR17(
.clk(clk),
.rst(rst),
.VAR11(VAR11),
.VAR12(VAR5),
.VAR13(VAR14),
.VAR4(VAR4),
.VAR8(VAR3),
.VAR20(VAR9)
);
VAR19 #(.VAR6(VAR7)) VAR18(
.clk(clk),
.rst(rst),
.VAR16(VAR11),
.VAR1(VAR9),
.VAR2(VAR10)
);
endmodule
|
gpl-3.0
|
lvd2/zxevo
|
unsupported/solegstar/fpga/current/vg93/fapch_counter.v
| 1,697 |
module MODULE1
(
input wire VAR2,
input wire VAR6,
output reg VAR4,
output reg VAR8
);
reg [4:0] VAR5;
reg VAR10, VAR3;
wire VAR11;
wire VAR9;
reg [3:0] VAR7;
wire VAR12;
reg [5:0] VAR1;
always @(posedge VAR2)
VAR5[4:0] <= { VAR5[3:0], (~VAR6) };
always @(posedge VAR2)
begin
if( VAR5[4:1]==4'b1111 ) VAR10 <= 1'b1;
end
else if( VAR12 ) VAR10 <= 1'b0;
VAR3 <= VAR10;
end
assign VAR11 = VAR10 & (~VAR3);
always @(posedge VAR2)
if( VAR9 )
begin
if( VAR11 )
VAR7 <= 4'd0;
end
else
VAR7 <= VAR7 + 4'd1;
end
assign VAR9 = VAR11 | (~VAR7[2]);
always @(posedge VAR2)
VAR8 <= VAR7[2];
assign VAR12 = (VAR1==6'd0);
always @(posedge VAR2)
begin
if( VAR11 )
end
VAR1 <= 6'd29; else if( VAR12 )
VAR1 <= 6'd55; else
VAR1 <= VAR1 - 6'd1;
end
always @(posedge VAR2)
if( VAR12 )
VAR4 <= ~VAR4;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/fah/sky130_fd_sc_hd__fah.symbol.v
| 1,296 |
module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
output VAR8,
output VAR7
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/or3/sky130_fd_sc_lp__or3.behavioral.v
| 1,361 |
module MODULE1 (
VAR11,
VAR3,
VAR8,
VAR1
);
output VAR11;
input VAR3;
input VAR8;
input VAR1;
supply1 VAR6;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR5 ;
wire VAR10;
or VAR7 (VAR10, VAR8, VAR3, VAR1 );
buf VAR2 (VAR11 , VAR10 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a41oi/sky130_fd_sc_ms__a41oi.functional.pp.v
| 2,070 |
module MODULE1 (
VAR1 ,
VAR10 ,
VAR9 ,
VAR14 ,
VAR3 ,
VAR13 ,
VAR8,
VAR15,
VAR16 ,
VAR2
);
output VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR14 ;
input VAR3 ;
input VAR13 ;
input VAR8;
input VAR15;
input VAR16 ;
input VAR2 ;
wire VAR18 ;
wire VAR17 ;
wire VAR5;
and VAR11 (VAR18 , VAR10, VAR9, VAR14, VAR3 );
nor VAR6 (VAR17 , VAR13, VAR18 );
VAR7 VAR12 (VAR5, VAR17, VAR8, VAR15);
buf VAR4 (VAR1 , VAR5 );
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_trn_v5_gtp_x8_125/source/cmm_errman_ram8x26.v
| 4,629 |
module MODULE1 (
VAR2,
VAR4, VAR6,
VAR7,
VAR8,
rst,
clk
);
output [49:0] VAR2;
input [49:0] VAR4;
input [2:0] VAR6;
input [2:0] VAR7;
input VAR8;
input rst;
input clk;
reg [49:0] VAR5 [0:7];
always @(posedge clk) begin
if (VAR8)
VAR5[VAR6] <= #VAR3 VAR4;
end
reg [49:0] VAR1;
always @(posedge clk or posedge rst)
begin
if (rst) VAR1 <= #VAR3 50'h000000000000;
end
else VAR1 <= #VAR3 VAR5[VAR7];
end
assign VAR2 = VAR1;
endmodule
|
lgpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a22oi/sky130_fd_sc_ms__a22oi.functional.v
| 1,545 |
module MODULE1 (
VAR1 ,
VAR10,
VAR7,
VAR9,
VAR3
);
output VAR1 ;
input VAR10;
input VAR7;
input VAR9;
input VAR3;
wire VAR6 ;
wire VAR12 ;
wire VAR5;
nand VAR2 (VAR6 , VAR7, VAR10 );
nand VAR11 (VAR12 , VAR3, VAR9 );
and VAR4 (VAR5, VAR6, VAR12);
buf VAR8 (VAR1 , VAR5 );
endmodule
|
apache-2.0
|
Mw1993/5CPipelinedCPU
|
data_mem.v
| 1,037 |
module MODULE1(clk,addr,VAR5,VAR2,VAR4,VAR3);
input clk;
input [15:0] addr;
input VAR5; input VAR2; input [15:0] VAR4;
output reg [15:0] VAR3;
reg [15:0]VAR1[0:65535];
always @(addr,VAR5,clk)
if (~clk && VAR5 && ~VAR2)
VAR3 <= VAR1[addr];
always @(addr,VAR2,clk)
if (~clk && VAR2 && ~VAR5)
VAR1[addr] <= VAR4;
endmodule
|
gpl-2.0
|
osrf/wandrr
|
firmware/motor_controller/fpga/spi_slave_rxq.v
| 2,717 |
module MODULE1
(input VAR16,
input VAR56, input VAR36, input VAR43,
output [7:0] VAR62, output VAR7, output VAR67);
wire [7:0] VAR21;
wire VAR63, VAR14;
VAR61 VAR51
(.clk(VAR16), .VAR56(VAR56), .VAR36(VAR36), .VAR43(VAR43),
.VAR62(VAR21), .VAR7(VAR63), .VAR67(VAR14));
wire VAR2, VAR68;
wire [7:0] VAR26;
wire [7:0] VAR33;
VAR57 #(.VAR65(8),
.VAR9(256),
.VAR22(8),
.VAR37("VAR41"),
.VAR64("VAR41"),
.VAR4("VAR42 VAR13")) VAR60
(.VAR30(VAR16),
.VAR10(VAR63), .VAR34(VAR21),
.VAR31(VAR2), .VAR48(VAR26),
.VAR15(VAR68), .VAR44(VAR33), .VAR66(1'b0), .VAR27(1'b0));
localparam VAR5 = 3;
localparam VAR32 = 3'd0;
localparam VAR58 = 3'd1;
localparam VAR25 = 3'd2;
localparam VAR46 = 3'd3;
localparam VAR55 = 4;
reg [VAR5+VAR55-1:0] VAR54;
wire [VAR5-1:0] state;
wire [VAR5-1:0] VAR12 = VAR54[VAR5+VAR55-1:VAR55];
VAR45 #(VAR5) VAR11
(.VAR16(VAR16), .VAR49(VAR12), .rst(1'b0), .en(1'b1), .VAR48(state));
assign VAR7 = VAR54[0];
assign VAR62 = state == VAR58 ? 8'h99 : VAR26;
assign VAR67 = VAR7 & VAR33 == 8'h1;
assign VAR2 = VAR54[1];
always @* begin
case (state)
VAR32:
if (VAR14) VAR54 = { VAR58 , 4'b0000 };
end
else VAR54 = { VAR32 , 4'b0000 };
VAR58: VAR54 = { VAR25, 4'b0001 };
VAR25:
if (VAR33 == 8'h1) VAR54 = { VAR32 , 4'b0011 };
else VAR54 = { VAR25, 4'b0011 };
default: VAR54 = { VAR32 , 4'b0000 };
endcase
end
endmodule
module MODULE2();
wire VAR16;
VAR19 #(100) VAR59(VAR16);
localparam VAR1 = 8;
reg [VAR1-1:0] VAR38;
wire [VAR1-1:0] VAR29;
reg VAR28;
wire VAR40;
wire VAR39, VAR47;
wire VAR36, VAR43, VAR6, VAR56;
VAR52 #(.VAR53(50), .VAR1(8)) VAR50
(.VAR16(VAR16), .VAR8(VAR47), .VAR20(VAR39),
.VAR35(VAR38), .VAR23(VAR28),
.VAR62(VAR29), .VAR7(VAR40),
.VAR36(VAR36), .VAR43(VAR43), .VAR6(VAR6), .VAR56(VAR56));
wire [7:0] VAR18;
wire VAR3, VAR17;
MODULE1 MODULE1
(.VAR16(VAR16), .VAR56(VAR56), .VAR36(VAR36), .VAR43(VAR43),
.VAR62(VAR18), .VAR7(VAR3), .VAR67(VAR17));
|
apache-2.0
|
kramble/FPGA-Litecoin-Miner
|
ICARUS-LX150/ltcminer_icarus.v
| 11,847 |
module MODULE1 (VAR43, VAR76, VAR31, VAR112, VAR13, VAR15, VAR95, VAR32, VAR16, VAR2);
function integer VAR34; input integer VAR70;
begin
VAR70 = VAR70-1;
for (VAR34=0; VAR70>0; VAR34=VAR34+1)
VAR70 = VAR70>>1;
end
endfunction
parameter VAR10 = VAR10;
parameter VAR10 = 25; VAR77
parameter VAR104 = VAR104; else
parameter VAR104 = 100; VAR77
parameter VAR106 = VAR106; else
parameter VAR106 = 10;
parameter VAR4 = VAR101;
parameter VAR4 = 12500000; VAR77
parameter VAR6 = VAR6;
parameter VAR6 = 115200;
parameter VAR18 = VAR18;
parameter VAR18 = 2; VAR77
parameter VAR68 = VAR68; else
parameter VAR68 = 12 - VAR34(VAR18); VAR77
parameter VAR53 = VAR53;
parameter VAR53 = 1;
localparam VAR30 = VAR18 + VAR53;
input VAR43;
wire VAR46, VAR52, VAR50;
wire VAR65, VAR20, VAR23, VAR64, VAR88, VAR67, VAR54;
wire [2:1] VAR56;
VAR84 # (.VAR10(VAR10)) VAR60
(VAR43,
VAR50,
VAR46,
VAR52,
VAR65,
VAR20,
VAR23,
VAR64,
VAR88,
VAR67,
VAR54,
VAR56);
VAR37 # (.VAR10(VAR10)) VAR71 (.VAR99(VAR43), .VAR24(VAR46), .VAR11(VAR52));
assign VAR50 = VAR52;
assign VAR46 = VAR43;
assign VAR52 = VAR43;
assign VAR50 = VAR43;
assign VAR65 = 1'b1;
assign VAR67 = 1'b1;
assign VAR54 = 1'b1;
assign VAR56 = 0;
reg [7:0] VAR93 = VAR10;
reg VAR28 = 0;
parameter VAR47 = 100; VAR82 # (.VAR10(VAR10), .VAR104(VAR104), .VAR106(VAR106), .VAR47(VAR47)) VAR25
(VAR52, VAR65, VAR93,
VAR28,
VAR20,
VAR23,
VAR64,
VAR88,
VAR54,
VAR56);
input VAR32, VAR16, VAR2;
input [3:0]VAR95;
wire reset, VAR110;
assign reset = VAR95[0]; assign VAR110 = VAR95[1];
input VAR76;
output VAR31;
wire [VAR30*32-1:0] VAR98;
wire [VAR30*32-1:0] VAR69;
wire [VAR30-1:0] VAR111;
wire VAR103;
wire VAR86;
wire [31:0] VAR8;
VAR38 #(.VAR4(VAR4), .VAR58(VAR6)) VAR41 (.clk(VAR52), .VAR31(VAR31), .VAR35(VAR103), .VAR74(VAR86), .word(VAR8));
VAR36 #(.VAR30(VAR30)) hc (.VAR52(VAR52), .VAR111(VAR111), .VAR8(VAR8), .VAR103(VAR103), .VAR86(VAR86), .VAR98(VAR98));
wire [255:0] VAR83, VAR57;
wire [127:0] VAR85;
wire [31:0] VAR90;
reg [31:0] VAR27 = 32'h000007ff; wire VAR100;
reg VAR109 = 1'b0; always @ (posedge VAR52)
VAR109 <= VAR109 ^ VAR100;
reg VAR66 = 1'b0; reg VAR45 = 1'b0;
reg VAR79 = 1'b0;
wire VAR51;
assign VAR51 = VAR79 ^ VAR45;
always @ (posedge VAR50)
begin
VAR66 <= VAR109;
VAR45 <= VAR66;
VAR79 <= VAR45;
if (VAR51)
VAR27 <= VAR90;
end
wire [31:0] VAR17;
always @ (posedge VAR52)
begin
VAR28 <= 0;
if (VAR100 && VAR90[31:24] != VAR93 && VAR90[31:24] != 0 && VAR90[23:16] != 0 && VAR90[31:24] == ~VAR90[23:16])
begin
VAR93 <= VAR90[31:24];
VAR28 <= 1;
end
end
assign VAR17 = { 16'd0, VAR27[15:0] }; else
assign VAR17 = { 16'd0, VAR27[15:0] }; VAR77
VAR78 #(.VAR4(VAR4), .VAR58(VAR6)) VAR42 (.clk(VAR52), .VAR76(VAR76), .VAR83(VAR83),
.VAR57(VAR57), .VAR85(VAR85), .VAR90(VAR90), .VAR100(VAR100));
parameter VAR89 = 8;
generate
genvar VAR12;
for (VAR12 = 0; VAR12 < VAR18; VAR12 = VAR12 + 1)
begin: VAR21
wire [31:0] VAR102; wire [2:0] VAR29 = VAR12;
wire VAR73;
wire VAR61, VAR1, VAR92, VAR9, VAR80;
wire [VAR89-1:0] VAR96;
wire [VAR89-1:0] VAR39;
wire [3:0] VAR72;
VAR40 #(.VAR89(VAR89)) VAR107
(.VAR46(VAR46), .VAR50(VAR50), .VAR83(VAR83), .VAR57(VAR57), .VAR85(VAR85), .VAR90(VAR17),
.VAR33({VAR110, VAR29}), .VAR102(VAR102), .VAR59(VAR98[VAR12*32+31:VAR12*32]),
.VAR19(VAR73), .VAR51(VAR51),
.VAR96(VAR96), .VAR39(VAR39), .VAR61(VAR61), .VAR1(VAR1),
.VAR92(VAR92), .VAR9(VAR9), .VAR80(VAR80));
VAR94 #(.VAR68(VAR68), .VAR89(VAR89)) VAR81
(.VAR46(VAR46), .reset(VAR92), .din(VAR96), .dout(VAR39),
.VAR105(VAR80), .VAR108(VAR9), .VAR74(VAR61), .VAR97(VAR1) );
reg VAR14 = 1'b0; always @ (posedge VAR50)
VAR14 <= VAR14 ^ VAR73;
reg VAR7 = 1'b0; reg VAR49 = 1'b0;
reg VAR87 = 1'b0;
assign VAR111[VAR12] = VAR87 ^ VAR49;
always @ (posedge VAR52)
begin
VAR7 <= VAR14;
VAR49 <= VAR7;
VAR87 <= VAR49;
end
end endgenerate
output [VAR53-1:0] VAR15;
input [VAR53-1:0] VAR13;
assign VAR15 = {VAR53{VAR76}};
generate
genvar VAR5;
for (VAR5 = VAR18; VAR5 < VAR30; VAR5 = VAR5 + 1)
begin: VAR44
VAR75 #(.VAR4(VAR4), .VAR58(VAR6)) VAR48 (.clk(VAR52), .VAR76(VAR13[VAR5-VAR18]), .VAR22(VAR98[VAR5*32+31:VAR5*32]), .VAR113(VAR111[VAR5]));
end
endgenerate
output [3:0] VAR112;
assign VAR112[1] = ~VAR76;
assign VAR112[3] = ~VAR65 | ~VAR54 | VAR56[2] | ~(VAR32 | VAR16 | VAR2);
reg [26:0] VAR91 = 0;
reg [3:0] VAR3 = 0;
always @ (posedge VAR52)
if (VAR100)
VAR3[0] <= ~VAR3[0];
always @ (posedge VAR46)
begin
VAR3[3:1] <= VAR3[2:0];
VAR91 <= VAR91 + 1'b1;
if (VAR3[3] != VAR3[2])
VAR91 <= 0;
end
assign VAR112[2] = VAR91[26];
assign VAR112[2] = ~VAR31;
VAR55 VAR63 (.clk(VAR52), .VAR62(|VAR111[VAR18-1:0]), .VAR26(VAR112[0]));
endmodule
|
gpl-3.0
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/ip/ip_2/synth/bd_c3fe_slot_0_aw_0.v
| 4,561 |
module MODULE1 (
VAR35,
VAR55,
dout
);
input wire [0 : 0] VAR35;
input wire [0 : 0] VAR55;
output wire [1 : 0] dout;
VAR23 #(
.VAR14(1),
.VAR68(1),
.VAR26(1),
.VAR7(1),
.VAR39(1),
.VAR47(1),
.VAR64(1),
.VAR5(1),
.VAR51(1),
.VAR4(1),
.VAR52(1),
.VAR66(1),
.VAR69(1),
.VAR6(1),
.VAR3(1),
.VAR8(1),
.VAR58(1),
.VAR15(1),
.VAR59(1),
.VAR17(1),
.VAR29(1),
.VAR43(1),
.VAR50(1),
.VAR45(1),
.VAR22(1),
.VAR38(1),
.VAR32(1),
.VAR62(1),
.VAR21(1),
.VAR31(1),
.VAR16(1),
.VAR67(1),
.VAR19(2),
.VAR9(2)
) VAR57 (
.VAR35(VAR35),
.VAR55(VAR55),
.VAR36(1'VAR40),
.VAR61(1'VAR40),
.VAR27(1'VAR40),
.VAR37(1'VAR40),
.VAR28(1'VAR40),
.VAR65(1'VAR40),
.VAR10(1'VAR40),
.VAR20(1'VAR40),
.VAR60(1'VAR40),
.VAR33(1'VAR40),
.VAR11(1'VAR40),
.VAR53(1'VAR40),
.VAR12(1'VAR40),
.VAR56(1'VAR40),
.VAR54(1'VAR40),
.VAR30(1'VAR40),
.VAR48(1'VAR40),
.VAR42(1'VAR40),
.VAR18(1'VAR40),
.VAR34(1'VAR40),
.VAR44(1'VAR40),
.VAR24(1'VAR40),
.VAR41(1'VAR40),
.VAR25(1'VAR40),
.VAR2(1'VAR40),
.VAR13(1'VAR40),
.VAR46(1'VAR40),
.VAR63(1'VAR40),
.VAR49(1'VAR40),
.VAR1(1'VAR40),
.dout(dout)
);
endmodule
|
mit
|
camsoupa/cc3000
|
cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/bfm_apbtoapb.v
| 6,187 |
module MODULE1 ( VAR25, VAR16, VAR4, VAR21, VAR27, VAR12, VAR39, VAR37, VAR8,
VAR33, VAR19, VAR29, VAR28, VAR34, VAR40, VAR13, VAR3, VAR24);
parameter[9:0] VAR36 = 1;
localparam VAR5 = VAR36 * 1;
input VAR25;
input VAR16;
input[31:0] VAR4;
input VAR21;
input VAR27;
input[31:0] VAR12;
output[31:0] VAR39;
reg[31:0] VAR39;
output VAR37;
reg VAR37;
output VAR8;
reg VAR8;
input VAR33;
output[15:0] VAR19;
wire[15:0] #VAR5 VAR19;
output[31:0] VAR29;
wire[31:0] #VAR5 VAR29;
output VAR28;
wire #VAR5 VAR28;
output VAR34;
wire #VAR5 VAR34;
output[31:0] VAR40;
wire[31:0] #VAR5 VAR40;
input[31:0] VAR13;
input VAR3;
input VAR24;
parameter[0:0] VAR18 = 0;
parameter[0:0] VAR7 = 1;
reg[0:0] VAR35;
parameter[1:0] VAR22 = 0;
parameter[1:0] VAR14 = 1;
parameter[1:0] VAR30 = 2;
reg[1:0] VAR38;
reg[15:0] VAR11;
reg[31:0] VAR20;
reg VAR10;
reg VAR2;
reg[31:0] VAR23;
reg VAR6;
reg[31:0] VAR1;
reg VAR32;
reg VAR31;
reg VAR15;
reg VAR26;
always @(posedge VAR25 or negedge VAR16)
begin
if (VAR16 == 1'b0)
begin
VAR35 <= VAR18 ;
VAR15 <= 1'b0 ;
VAR37 <= 1'b0 ;
VAR8 <= 1'b0 ;
VAR39 <= {32{1'b0}} ;
VAR31 <= 1'b0 ;
end
else
begin
VAR37 <= 1'b0 ;
VAR31 <= VAR27 ;
case (VAR35)
VAR18 :
begin
if (VAR27 == 1'b1 & VAR31 == 1'b0)
begin
VAR15 <= 1'b1 ;
VAR35 <= VAR7 ;
end
end
VAR7 :
begin
if (VAR26 == 1'b1)
begin
VAR35 <= VAR18 ;
VAR15 <= 1'b0 ;
VAR37 <= 1'b1 ;
VAR8 <= VAR32 ;
VAR39 <= VAR1 ;
end
end
endcase
end
end
always @(posedge VAR33 or negedge VAR15)
begin
if (VAR15 == 1'b0)
begin
VAR38 <= VAR22 ;
VAR26 <= 1'b0 ;
VAR1 <= {32{1'b0}} ;
VAR32 <= 1'b0 ;
VAR6 <= 1'b0 ;
VAR2 <= 1'b0 ;
VAR20 <= {32{1'b0}} ;
VAR23 <= {32{1'b0}} ;
VAR10 <= 1'b0 ;
end
else
begin
case (VAR38)
VAR22 :
begin
VAR38 <= VAR14 ;
VAR20 <= VAR4 ;
VAR23 <= VAR12 ;
VAR10 <= VAR21 ;
VAR6 <= 1'b1 ;
VAR2 <= 1'b0 ;
VAR26 <= 1'b0 ;
end
VAR14 :
begin
VAR38 <= VAR30 ;
VAR2 <= 1'b1 ;
end
VAR30 :
begin
if (VAR3 == 1'b1)
begin
VAR26 <= 1'b1 ;
VAR1 <= VAR13 ;
VAR32 <= VAR24 ;
VAR6 <= 1'b0 ;
VAR2 <= 1'b0 ;
VAR20 <= {32{1'b0}} ;
VAR23 <= {32{1'b0}} ;
VAR10 <= 1'b0 ;
end
end
endcase
end
end
always @(VAR20 or VAR6)
begin
VAR11 <= {16{1'b0}} ;
if (VAR6 == 1'b1)
begin
begin : VAR9
integer VAR17;
for(VAR17 = 0; VAR17 <= 15; VAR17 = VAR17 + 1)
begin
VAR11[VAR17] <= (VAR20[27:24] == VAR17);
end
end
end
end
assign VAR19 = VAR11 ;
assign VAR29 = VAR20 ;
assign VAR28 = VAR10 ;
assign VAR34 = VAR2 ;
assign VAR40 = VAR23 ;
endmodule
|
mit
|
mbus/mbus
|
mbus/verilog/no_pwr_gating_ben/mbus_wire_ctrl_Ben.v
| 1,781 |
module MODULE1(
input VAR4,
input VAR9,
input VAR11,
input VAR5,
input VAR7,
input VAR10,
output reg VAR8,
output reg VAR2,
input VAR6,
input VAR3
);
always @ *
begin
if( !VAR4 )
VAR2 <= 1'b1;
end
else if (VAR10==VAR1)
begin
if (VAR3==1'b1)
VAR2 <= 1'b1;
end
else
VAR2 <= VAR11;
end
else
VAR2 <= VAR7;
if ( !VAR4 )
VAR8 <= 1'b1;
else if (VAR6)
begin
VAR8 <= 0;
end
else
begin
if (VAR10==VAR1)
begin
if (VAR3==1'b1)
VAR8 <= 1'b1;
end
else
VAR8 <= VAR9;
end
else
begin
VAR8 <= VAR5;
end
end
end
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/nand4b/sky130_fd_sc_lp__nand4b.symbol.v
| 1,329 |
module MODULE1 (
input VAR8,
input VAR9 ,
input VAR6 ,
input VAR2 ,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule
|
apache-2.0
|
AngelTerrones/MUSB
|
Boards/xilinx_diligent_s3e/rtl/verilog/memory/memory.v
| 4,375 |
module MODULE1#(
parameter VAR18 = 8 )(
input clk,
input rst,
input [VAR18-1:0] VAR23, input [31:0] VAR19, input [3:0] VAR20, input VAR4, output reg [31:0] VAR10, output reg VAR11, input [VAR18-1:0] VAR21, input [31:0] VAR7, input [3:0] VAR12, input VAR14, output reg [31:0] VAR5, output reg VAR17 );
wire [31:0] VAR6;
wire [31:0] VAR22;
always @(posedge clk) begin
VAR11 <= (rst) ? 1'b0 : VAR4;
VAR17 <= (rst) ? 1'b0 : VAR14;
end
always @(*) begin
VAR10 <= (VAR11) ? VAR6 : 32'VAR8;
VAR5 <= (VAR17) ? VAR22 : 32'VAR8;
end
VAR3 #(8, VAR18) VAR2(
.VAR1 ( clk ),
.VAR20 ( VAR20[0] & VAR4 ),
.VAR23 ( VAR23 ),
.VAR19 ( VAR19[7:0] ),
.VAR10 ( VAR6[7:0] ),
.VAR9 ( clk ),
.VAR12 ( VAR12[0] & VAR14 ),
.VAR21 ( VAR21 ),
.VAR7 ( VAR7[7:0] ),
.VAR5 ( VAR22[7:0] )
);
VAR3 #(8, VAR18) VAR13(
.VAR1 ( clk ),
.VAR20 ( VAR20[1] & VAR4 ),
.VAR23 ( VAR23 ),
.VAR19 ( VAR19[15:8] ),
.VAR10 ( VAR6[15:8] ),
.VAR9 ( clk ),
.VAR12 ( VAR12[1] & VAR14 ),
.VAR21 ( VAR21 ),
.VAR7 ( VAR7[15:8] ),
.VAR5 ( VAR22[15:8] )
);
VAR3 #(8, VAR18) VAR15(
.VAR1 ( clk ),
.VAR20 ( VAR20[2] & VAR4 ),
.VAR23 ( VAR23 ),
.VAR19 ( VAR19[23:16] ),
.VAR10 ( VAR6[23:16] ),
.VAR9 ( clk ),
.VAR12 ( VAR12[2] & VAR14 ),
.VAR21 ( VAR21 ),
.VAR7 ( VAR7[23:16] ),
.VAR5 ( VAR22[23:16] )
);
VAR3 #(8, VAR18) VAR16(
.VAR1 ( clk ),
.VAR20 ( VAR20[3] & VAR4 ),
.VAR23 ( VAR23 ),
.VAR19 ( VAR19[31:24] ),
.VAR10 ( VAR6[31:24] ),
.VAR9 ( clk ),
.VAR12 ( VAR12[3] & VAR14 ),
.VAR21 ( VAR21 ),
.VAR7 ( VAR7[31:24] ),
.VAR5 ( VAR22[31:24] )
);
endmodule
|
mit
|
asicguy/gplgpu
|
hdl/vga/ram_9x32_2p.v
| 2,281 |
module MODULE1
(
input VAR1,
input VAR2,
input [4:0] VAR7,
input [4:0] VAR5,
input [8:0] VAR6,
output reg [8:0] VAR3
);
reg [8:0] VAR4 [0:31];
always @(posedge VAR1) if(VAR2) VAR4[VAR7] <= VAR6;
always @(posedge VAR1) VAR3 <= VAR4[VAR5];
endmodule
|
gpl-3.0
|
qmn/riscv-invicta
|
hardware/src/top.v
| 2,605 |
module MODULE1 (
input clk,
input reset
);
wire VAR23;
wire [31:0] VAR12;
wire VAR18;
wire VAR24;
wire [31:0] VAR21;
wire [31:0] VAR4;
wire [3:0] VAR6;
wire VAR2;
wire VAR15;
wire VAR7;
wire[31:0] VAR9;
wire [31:0] VAR1;
wire VAR14;
VAR10 VAR20(.clk(clk), .reset(reset), .VAR23(VAR23),
.VAR12(VAR12), .VAR18(VAR18), .VAR24(VAR24),
.VAR17(VAR21), .VAR11(VAR4), .VAR5(VAR6),
.VAR16(VAR2), .VAR19(VAR15), .VAR13(VAR7),
.VAR9(VAR9), .VAR14(VAR14), .VAR1(VAR1), .VAR22(VAR22));
VAR8 VAR3(.clk(clk), .reset(reset), .VAR23(VAR23),
.VAR9(VAR9),
.VAR14(VAR14), .VAR1(VAR1), .VAR22(VAR22),
.VAR12(VAR12), .VAR18(VAR18), .VAR24(VAR24),
.VAR17(VAR21), .VAR11(VAR4), .VAR5(VAR6),
.VAR16(VAR2), .VAR19(VAR15), .VAR13(VAR7));
endmodule
|
bsd-2-clause
|
FAST-Switch/fast
|
lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_wait_generate.v
| 2,054 |
module MODULE1
(
input wire rst,
input wire clk,
input wire VAR8,
output wire VAR10
);
reg VAR4 = 0;
reg VAR1 = 0;
always @ (posedge clk, posedge rst) begin
if(rst) VAR4 <= 1'b0;
end
else VAR4 <= VAR8;
end
always @ (posedge clk, posedge rst) begin
if(rst) VAR1 <= 1'b0;
end
else VAR1 <= VAR8 & VAR4 & (! VAR1 & !VAR10);
end
wire VAR3;
VAR9 #(.VAR7 (1)) VAR2 (.clk(clk),.reset(rst),.VAR5(1'b0),.VAR6(VAR3));
assign VAR10 = VAR3 | (VAR8 & ~VAR4) | (VAR1 & VAR8 ) ;
endmodule
|
apache-2.0
|
mindrobots/P8X32A_Emulation
|
P8X32A_Pipistrello/src/cog_vid.v
| 5,135 |
module MODULE1
(
input VAR17,
input VAR14,
input VAR13,
input VAR27,
input VAR24,
input [31:0] VAR6,
input [31:0] VAR3,
input [31:0] VAR21,
input [7:0] VAR5,
input VAR32,
output ack,
output [31:0] VAR10
);
reg [31:0] VAR25;
reg [31:0] VAR23;
always @(posedge VAR17 or negedge VAR13)
if (!VAR13)
VAR25 <= 32'b0;
else if (VAR27)
VAR25 <= VAR6;
always @(posedge VAR17)
if (VAR24)
VAR23 <= VAR6;
reg [7:0] VAR1;
reg [7:0] VAR29;
reg [11:0] VAR7;
reg [31:0] VAR16;
reg [31:0] VAR11;
wire enable = |VAR25[30:29];
wire VAR9 = VAR14 && enable;
wire VAR26 = VAR7 == 1'b1;
wire VAR19 = VAR29 == 1'b1;
always @(posedge VAR9)
if (VAR26)
VAR1 <= VAR23[19:12];
always @(posedge VAR9)
VAR29 <= VAR26 ? VAR23[19:12]
: VAR19 ? VAR1
: VAR29 - 1'b1;
always @(posedge VAR9)
VAR7 <= VAR26 ? VAR23[11:0]
: VAR7 - 1'b1;
always @(posedge VAR9)
if (VAR26 || VAR19)
VAR16 <= VAR26 ? VAR3
: VAR25[28] ? {VAR16[31:30], VAR16[31:2]}
: {VAR16[31], VAR16[31:1]};
always @(posedge VAR9)
if (VAR26)
VAR11 <= VAR21;
reg VAR2;
reg [1:0] VAR8;
always @(posedge VAR9 or posedge VAR8[1])
if (VAR8[1])
VAR2 <= 1'b0;
else if (VAR26)
VAR2 <= 1'b1;
always @(posedge VAR17)
if (enable)
VAR8 <= {VAR8[0], VAR2};
assign ack = VAR8[0];
reg [7:0] VAR4;
wire [31:0] VAR22 = VAR11 >> {VAR25[28] && VAR16[1], VAR16[0], 3'b000};
always @(posedge VAR9)
VAR4 <= VAR22[7:0];
reg [3:0] VAR30;
reg [3:0] VAR15;
always @(posedge VAR9)
VAR30 <= VAR30 + 1'b1;
wire [3:0] VAR31 = VAR4[7:4] + VAR30;
wire [2:0] VAR33 = VAR4[2:0] + { VAR4[3] && VAR31[3],
VAR4[3] && VAR31[3],
VAR4[3] };
always @(posedge VAR9)
VAR15 <= {VAR4[3] && VAR31[3], VAR25[26] ? VAR33 : VAR4[2:0]};
reg [2:0] VAR18;
always @(posedge VAR9)
VAR18 <= VAR25[27] ? VAR33 : VAR4[2:0];
wire [63:0] VAR20 = 64'b0011010001000101010101100110011100110011001000100001000100000000;
wire [3:0] VAR12 = {VAR32 ^ VAR5[VAR25[25:23]], VAR20[{VAR32, VAR18}*4 +: 3]};
wire [7:0] VAR28 = VAR25[30] ? VAR25[29] ? {VAR15, VAR12}
: {VAR12, VAR15}
: VAR4;
assign VAR10 = enable ? {24'b0, VAR28 & VAR25[7:0]} << {VAR25[10:9], 3'b000} : 32'b0;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nor4b/sky130_fd_sc_ms__nor4b_2.v
| 2,302 |
module MODULE1 (
VAR8 ,
VAR1 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR3,
VAR9,
VAR5 ,
VAR7
);
output VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR3;
input VAR9;
input VAR5 ;
input VAR7 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR8 ,
VAR1 ,
VAR4 ,
VAR11 ,
VAR10
);
output VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR11 ;
input VAR10;
supply1 VAR3;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR7 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10)
);
endmodule
|
apache-2.0
|
tmatsuya/milkymist-ml401
|
cores/tmu2/rtl/tmu2_geninterp18.v
| 1,602 |
module MODULE1(
input VAR2,
input VAR13,
input VAR15,
input signed [17:0] VAR3,
input VAR10,
input [16:0] VAR6,
input [16:0] VAR4,
input [16:0] VAR12,
output signed [17:0] VAR14
);
reg VAR11;
reg [16:0] VAR7;
reg [16:0] VAR1;
reg [16:0] VAR8;
always @(posedge VAR2) begin
if(VAR13) begin
VAR11 <= VAR10;
VAR7 <= VAR6;
VAR1 <= VAR4;
VAR8 <= VAR12;
end
end
reg [17:0] VAR5;
reg VAR9;
reg signed [17:0] or;
assign VAR14 = or;
always @(posedge VAR2) begin
if(VAR13) begin
VAR5 = 18'd0;
or = VAR3;
end else if(VAR15) begin
VAR5 = VAR5 + VAR1;
VAR9 = (VAR5[16:0] > {1'b0, VAR8[16:1]}) & ~VAR5[17];
if(VAR11) begin
or = or + {1'b0, VAR7};
if(VAR9)
or = or + 18'd1;
end else begin
or = or - {1'b0, VAR7};
if(VAR9)
or = or - 18'd1;
end
if(VAR9)
VAR5 = VAR5 - {1'b0, VAR8};
end
end
endmodule
|
lgpl-3.0
|
ludisu13/Estructuras2
|
tarea45/decodificador.v
| 6,621 |
module MODULE1(
input wire VAR9,
input wire[15:0] VAR10,
input wire VAR5, VAR12, VAR1, VAR11, VAR13, VAR8,
output reg VAR3,
output reg VAR2,
output reg[9:0] VAR7,
output reg[7:0] VAR6,
output reg VAR4,
output reg VAR14
);
always @( posedge VAR9)
begin
case(VAR10[15:10])
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=1;
VAR14<=0;
VAR3<=0;
VAR7<=10'd1;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=1;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=1;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=1;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=1;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=1;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=1;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=1;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=1;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR2<=0;
VAR4<=1;
VAR14<=0;
VAR3<=0;
VAR7<=10'b0;
VAR6=VAR10[7:0];
end
begin
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR2<=1;
VAR7<=VAR10[9:0];
VAR6<=8'b0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR5==1)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR5==0)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR1==1)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR1==0)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR13==1)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR13==0)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR12==1)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR12==0)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR11==1)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR11==0)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR8==1)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR6<=8'b0;
if(VAR8==0)
begin
VAR3<=1;
VAR7<=VAR10[6:0];
end
else
VAR3<=0;
end
default:
begin
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR2<=0;
VAR7<=10'b0;
VAR6=8'b0;
end
endcase
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o311a/sky130_fd_sc_ls__o311a.functional.v
| 1,459 |
module MODULE1 (
VAR7 ,
VAR4,
VAR3,
VAR2,
VAR9,
VAR10
);
output VAR7 ;
input VAR4;
input VAR3;
input VAR2;
input VAR9;
input VAR10;
wire VAR11 ;
wire VAR6;
or VAR1 (VAR11 , VAR3, VAR4, VAR2 );
and VAR5 (VAR6, VAR11, VAR9, VAR10);
buf VAR8 (VAR7 , VAR6 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/sdfstp/sky130_fd_sc_hd__sdfstp.blackbox.v
| 1,418 |
module MODULE1 (
VAR9 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR4;
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR10 ;
endmodule
|
apache-2.0
|
scalable-networks/ext
|
uhd/fpga/usrp2/models/PLL_ADV.v
| 82,459 |
module MODULE1 (
VAR32,
VAR200,
VAR163,
VAR256,
VAR166,
VAR164,
VAR68,
VAR179,
VAR285,
VAR299,
VAR314,
VAR49,
VAR199,
VAR112,
VAR26,
VAR229,
VAR140,
VAR324,
VAR259,
VAR203,
VAR296,
VAR57,
VAR42,
VAR223,
VAR107,
VAR48,
VAR78,
VAR197
);
parameter VAR242 = "VAR198";
parameter VAR250 = "VAR327";
parameter VAR136 = "VAR327";
parameter VAR325 = "VAR327";
parameter VAR116 = "VAR327";
parameter VAR7 = "VAR327";
parameter VAR137 = "VAR327";
parameter VAR307 = "VAR327";
parameter integer VAR308 = 1;
parameter real VAR126 = 0.0;
parameter real VAR276 = 0.000;
parameter real VAR34 = 0.000;
parameter integer VAR157 = 1;
parameter real VAR309 = 0.5;
parameter real VAR334 = 0.0;
parameter integer VAR83 = 1;
parameter real VAR11 = 0.5;
parameter real VAR317 = 0.0;
parameter integer VAR195 = 1;
parameter real VAR100 = 0.5;
parameter real VAR153 = 0.0;
parameter integer VAR8 = 1;
parameter real VAR279 = 0.5;
parameter real VAR13 = 0.0;
parameter integer VAR97 = 1;
parameter real VAR24 = 0.5;
parameter real VAR209 = 0.0;
parameter integer VAR205 = 1;
parameter real VAR55 = 0.5;
parameter real VAR322 = 0.0;
parameter VAR292 = "VAR288";
parameter integer VAR61 = 1;
parameter VAR27 = "VAR266";
parameter VAR130 = "VAR266";
parameter real VAR30 = 0.100;
parameter VAR56 = "VAR266";
parameter VAR319 = "VAR259";
localparam VAR330 = 1100;
localparam VAR124 = 400;
output VAR32;
output VAR200;
output VAR163;
output VAR256;
output VAR166;
output VAR164;
output VAR68;
output VAR179;
output VAR285;
output VAR299;
output VAR314;
output VAR49;
output VAR199;
output VAR112;
output VAR229;
output VAR140;
output [15:0] VAR26;
input VAR324;
input VAR259;
input VAR203;
input VAR296;
input VAR42;
input VAR223;
input VAR48;
input VAR78;
input VAR197;
input [15:0] VAR107;
input [4:0] VAR57;
localparam VAR323 = 800;
localparam VAR290 = 1000;
localparam VAR89 = 1; localparam VAR191 = 550;
localparam VAR95 = 1; localparam VAR232 = 1;
localparam VAR54 = 74;
localparam VAR329 = 1;
localparam VAR21 = 52;
localparam VAR96 = 1;
localparam VAR226 = 128;
localparam VAR286 = 64;
localparam VAR115 = 350;
localparam VAR149 = 0.1;
localparam VAR138 = 10.0;
localparam VAR117 = 1.0;
tri0 VAR303 = VAR94.VAR303;
reg [4:0] VAR118;
reg VAR202;
reg VAR230;
reg VAR29, VAR302;
reg [15:0] VAR217 [31:0];
reg [160:0] VAR272;
wire VAR324, VAR259, VAR203, VAR296 ;
wire VAR210, VAR197, VAR64 ;
wire VAR318;
wire VAR282;
reg VAR169, VAR241, VAR253, VAR258, VAR219, VAR51;
reg VAR237, VAR243;
reg VAR33, VAR10, VAR50, VAR66;
integer VAR235, VAR180, VAR234;
integer VAR111, VAR84, VAR300;
reg VAR3, VAR240, VAR181;
reg VAR260;
reg VAR14, VAR206, VAR47;
VAR91 VAR144, VAR227;
reg VAR277, VAR60;
reg VAR275;
real VAR283;
VAR91 VAR246, VAR161, VAR88, VAR75, VAR15;
VAR91 VAR123, VAR20;
real VAR175;
integer VAR76 [4:0];
integer VAR9, VAR141, VAR152, VAR127;
integer VAR99, VAR254, VAR73, VAR189;
integer VAR160, VAR233, VAR65;
integer VAR72, VAR264;
integer VAR174, VAR278;
real VAR119, VAR101;
real VAR212;
integer VAR44, VAR80, VAR63, VAR311;
integer VAR261, VAR294, VAR186, VAR121;
VAR91 VAR125, VAR35, VAR315;
reg VAR332, VAR36;
wire VAR156;
reg VAR208, VAR37;
reg VAR145;
reg VAR132, VAR310;
reg VAR113, VAR122;
reg VAR263, VAR158;
wire VAR216, VAR19;
reg VAR188;
integer VAR150, VAR4, VAR40, VAR62;
integer VAR225, VAR173;
wire VAR78, VAR48, VAR223, VAR42, VAR213, VAR178, VAR31;
wire VAR326, VAR90, VAR236, VAR248, VAR289, VAR159, VAR69, VAR22, VAR244;
wire VAR204, VAR252;
reg VAR82;
reg VAR228;
reg VAR239;
reg VAR335;
reg VAR262;
reg VAR215;
reg VAR131, VAR305, VAR70, VAR165, VAR297;
reg VAR134, VAR86, VAR336, VAR110, VAR109;
reg VAR1;
reg VAR313;
wire VAR114, VAR74;
wire VAR18, VAR176, VAR177, VAR273, VAR46, VAR333;
reg [7:0] VAR321;
reg [2:0] VAR105, VAR6, VAR135, VAR184, VAR245, VAR67;
reg [2:0] VAR287;
reg VAR104, VAR271, VAR128, VAR281, VAR187, VAR331;
reg VAR41, VAR108;
reg VAR218, VAR274, VAR106, VAR298, VAR16, VAR120;
reg VAR53, VAR59;
reg VAR103, VAR268;
reg [5:0] VAR316, VAR280;
reg [5:0] VAR255, VAR146;
reg [5:0] VAR214, VAR12;
reg [5:0] VAR43, VAR265;
reg [5:0] VAR52, VAR185;
reg [5:0] VAR221, VAR257;
reg [6:0] VAR133, VAR129;
reg [6:0] VAR201, VAR291;
reg [6:0] VAR207, VAR247;
reg [6:0] VAR168, VAR249;
reg [6:0] VAR23, VAR93;
reg [6:0] VAR81, VAR284;
reg [5:0] VAR171, VAR162;
reg [6:0] VAR167, VAR183;
reg [7:0] VAR77, VAR194;
reg [7:0] VAR304, VAR154;
reg [7:0] VAR39, VAR38, VAR5, VAR192;
reg [7:0] VAR170, VAR102, VAR147, VAR85;
reg [7:0] VAR148, VAR190, VAR58, VAR155;
reg [7:0] VAR142, VAR320, VAR151, VAR79;
reg [7:0] VAR92, VAR45, VAR28, VAR87;
reg [7:0] VAR25, VAR269, VAR328, VAR172;
reg [7:0] VAR251, VAR17, VAR193, VAR295;
reg [7:0] VAR306;
reg [3:0] VAR139, VAR98;
reg [1:0] VAR220;
reg [1:0] VAR301 = 2'b01;
reg VAR182;
wire [15:0] VAR211, VAR196;
wire VAR293, VAR270, VAR231, VAR2, VAR143, VAR312, VAR224;
wire [4:0] VAR222;
wire VAR267, VAR238, VAR71;
assign VAR140 = VAR318;
assign VAR229 = VAR230;
assign VAR26 = VAR211;
assign VAR293 = VAR259;
assign VAR270 = VAR203;
assign VAR231 = VAR324;
assign VAR2 = VAR296;
assign VAR71 = VAR197;
assign VAR222 = VAR57;
assign VAR196 = VAR107;
assign VAR143 = VAR48;
assign VAR312 = VAR223;
assign VAR224 = VAR42;
assign VAR267 = VAR78;
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
|
gpl-2.0
|
YuxuanLing/trunk
|
trunk/references/h265enc_v1.0/rtl/tq/butterfly.v
| 27,048 |
module MODULE1(
clk,
rst,
VAR193,
VAR54,
VAR28,
VAR48,
VAR245,
VAR243,
VAR196,
VAR136,
VAR249,
VAR261,
VAR224,
VAR101,
VAR148,
VAR31,
VAR67,
VAR238,
VAR173,
VAR84,
VAR229,
VAR227,
VAR62,
VAR24,
VAR195,
VAR127,
VAR128,
VAR130,
VAR83,
VAR167,
VAR47,
VAR129,
VAR121,
VAR60,
VAR234,
VAR185,
VAR228,
VAR6,
o0 ,
o1 ,
o2 ,
o3 ,
o4 ,
o5 ,
o6 ,
o7 ,
VAR50 ,
VAR202 ,
o10,
o11,
o12,
o13,
o14,
o15,
o16,
o17,
VAR203,
VAR177,
o20,
o21,
o22,
o23,
o24,
o25,
o26,
o27,
VAR210,
VAR178,
o30,
o31
);
input clk;
input rst;
input VAR193;
input [1:0] VAR28;
input VAR54;
input signed [26:0] VAR48;
input signed [26:0] VAR245;
input signed [26:0] VAR243;
input signed [26:0] VAR196;
input signed [26:0] VAR136;
input signed [26:0] VAR249;
input signed [26:0] VAR261;
input signed [26:0] VAR224;
input signed [26:0] VAR101;
input signed [26:0] VAR148;
input signed [26:0] VAR31;
input signed [26:0] VAR67;
input signed [26:0] VAR238;
input signed [26:0] VAR173;
input signed [26:0] VAR84;
input signed [26:0] VAR229;
input signed [26:0] VAR227;
input signed [26:0] VAR62;
input signed [26:0] VAR24;
input signed [26:0] VAR195;
input signed [26:0] VAR127;
input signed [26:0] VAR128;
input signed [26:0] VAR130;
input signed [26:0] VAR83;
input signed [26:0] VAR167;
input signed [26:0] VAR47;
input signed [26:0] VAR129;
input signed [26:0] VAR121;
input signed [26:0] VAR60;
input signed [26:0] VAR234;
input signed [26:0] VAR185;
input signed [26:0] VAR228;
output reg VAR6;
output reg signed [27:0] o0 ;
output reg signed [27:0] o1 ;
output reg signed [27:0] o2 ;
output reg signed [27:0] o3 ;
output reg signed [27:0] o4 ;
output reg signed [27:0] o5 ;
output reg signed [27:0] o6 ;
output reg signed [27:0] o7 ;
output reg signed [27:0] VAR50 ;
output reg signed [27:0] VAR202 ;
output reg signed [27:0] o10;
output reg signed [27:0] o11;
output reg signed [27:0] o12;
output reg signed [27:0] o13;
output reg signed [27:0] o14;
output reg signed [27:0] o15;
output reg signed [27:0] o16;
output reg signed [27:0] o17;
output reg signed [27:0] VAR203;
output reg signed [27:0] VAR177;
output reg signed [27:0] o20;
output reg signed [27:0] o21;
output reg signed [27:0] o22;
output reg signed [27:0] o23;
output reg signed [27:0] o24;
output reg signed [27:0] o25;
output reg signed [27:0] o26;
output reg signed [27:0] o27;
output reg signed [27:0] VAR210;
output reg signed [27:0] VAR178;
output reg signed [27:0] o30;
output reg signed [27:0] o31;
wire VAR3;
wire VAR226;
wire VAR12;
wire VAR137;
wire VAR175;
wire VAR125;
wire signed [26:0] VAR208;
wire signed [26:0] VAR78;
wire signed [26:0] VAR240;
wire signed [26:0] VAR233;
wire signed [26:0] VAR154;
wire signed [26:0] VAR250;
wire signed [26:0] VAR110;
wire signed [26:0] VAR81;
wire signed [26:0] VAR255;
wire signed [26:0] VAR242;
wire signed [26:0] VAR123;
wire signed [26:0] VAR77;
wire signed [26:0] VAR133;
wire signed [26:0] VAR216;
wire signed [26:0] VAR146;
wire signed [26:0] VAR257;
wire signed [26:0] VAR191;
wire signed [26:0] VAR181;
wire signed [26:0] VAR179;
wire signed [26:0] VAR256;
wire signed [26:0] VAR138;
wire signed [26:0] VAR96;
wire signed [26:0] VAR253;
wire signed [26:0] VAR74;
wire signed [26:0] VAR15;
wire signed [26:0] VAR25;
wire signed [26:0] VAR132;
wire signed [26:0] VAR94;
wire signed [26:0] VAR56;
wire signed [26:0] VAR70;
wire signed [26:0] VAR97;
wire signed [26:0] VAR144;
wire signed [24:0] VAR32;
wire signed [24:0] VAR27;
wire signed [24:0] VAR95;
wire signed [24:0] VAR150;
wire signed [24:0] VAR239;
wire signed [24:0] VAR190;
wire signed [24:0] VAR207;
wire signed [24:0] VAR230;
wire signed [24:0] VAR172;
wire signed [24:0] VAR217;
wire signed [24:0] VAR157;
wire signed [24:0] VAR225;
wire signed [24:0] VAR13;
wire signed [24:0] VAR34;
wire signed [24:0] VAR222;
wire signed [24:0] VAR49;
wire signed [24:0] VAR21;
wire signed [24:0] VAR23;
wire signed [24:0] VAR248;
wire signed [24:0] VAR206;
wire signed [24:0] VAR201;
wire signed [24:0] VAR112;
wire signed [24:0] VAR160;
wire signed [24:0] VAR7;
wire signed [24:0] VAR51;
wire signed [24:0] VAR4;
wire signed [24:0] VAR147;
wire signed [24:0] VAR20;
wire signed [24:0] VAR104;
wire signed [24:0] VAR180;
wire signed [24:0] VAR111;
wire signed [24:0] VAR182;
wire signed [25:0] VAR174;
wire signed [25:0] VAR251;
wire signed [25:0] VAR35;
wire signed [25:0] VAR2;
wire signed [25:0] VAR82;
wire signed [25:0] VAR114;
wire signed [25:0] VAR92;
wire signed [25:0] VAR205;
wire signed [25:0] VAR235;
wire signed [25:0] VAR152;
wire signed [25:0] VAR142;
wire signed [25:0] VAR107;
wire signed [25:0] VAR247;
wire signed [25:0] VAR109;
wire signed [25:0] VAR244;
wire signed [25:0] VAR124;
wire signed [25:0] VAR241;
wire signed [25:0] VAR260;
wire signed [25:0] VAR163;
wire signed [25:0] VAR71;
wire signed [25:0] VAR68;
wire signed [25:0] VAR140;
wire signed [25:0] VAR170;
wire signed [25:0] VAR209;
wire signed [25:0] VAR38;
wire signed [25:0] VAR169;
wire signed [25:0] VAR72;
wire signed [25:0] VAR145;
wire signed [25:0] VAR131;
wire signed [25:0] VAR89;
wire signed [25:0] VAR187;
wire signed [25:0] VAR232;
wire signed [25:0] VAR52;
wire signed [25:0] VAR29;
wire signed [25:0] VAR91;
wire signed [25:0] VAR37;
wire signed [25:0] VAR55;
wire signed [25:0] VAR115;
wire signed [25:0] VAR11;
wire signed [25:0] VAR220;
wire signed [25:0] VAR231;
wire signed [25:0] VAR33;
wire signed [25:0] VAR254;
wire signed [25:0] VAR100;
wire signed [25:0] VAR166;
wire signed [25:0] VAR57;
wire signed [25:0] VAR85;
wire signed [25:0] VAR99;
wire signed [25:0] VAR139;
wire signed [25:0] VAR158;
wire signed [25:0] VAR161;
wire signed [25:0] VAR73;
wire signed [25:0] VAR171;
wire signed [25:0] VAR194;
wire signed [25:0] VAR200;
wire signed [25:0] VAR162;
wire signed [25:0] VAR116;
wire signed [25:0] VAR63;
wire signed [25:0] VAR211;
wire signed [25:0] VAR66;
wire signed [25:0] VAR18;
wire signed [25:0] VAR105;
wire signed [25:0] VAR120;
wire signed [25:0] VAR223;
wire signed [26:0] o160;
wire signed [26:0] o161;
wire signed [26:0] o162;
wire signed [26:0] o163;
wire signed [26:0] o164;
wire signed [26:0] o165;
wire signed [26:0] o166;
wire signed [26:0] o167;
wire signed [26:0] VAR141;
wire signed [26:0] VAR108;
wire signed [26:0] o1610;
wire signed [26:0] o1611;
wire signed [26:0] o1612;
wire signed [26:0] o1613;
wire signed [26:0] o1614;
wire signed [26:0] o1615;
wire signed [26:0] o1616;
wire signed [26:0] o1617;
wire signed [26:0] VAR165;
wire signed [26:0] VAR176;
wire signed [26:0] o1620;
wire signed [26:0] o1621;
wire signed [26:0] o1622;
wire signed [26:0] o1623;
wire signed [26:0] o1624;
wire signed [26:0] o1625;
wire signed [26:0] o1626;
wire signed [26:0] o1627;
wire signed [26:0] VAR119;
wire signed [26:0] VAR90;
wire signed [26:0] o1630;
wire signed [26:0] o1631;
wire signed [26:0] VAR164;
wire signed [26:0] VAR262;
wire signed [26:0] VAR218;
wire signed [26:0] VAR16;
wire signed [26:0] VAR36;
wire signed [26:0] VAR9;
wire signed [26:0] VAR117;
wire signed [26:0] VAR212;
wire signed [26:0] VAR236;
wire signed [26:0] VAR17;
wire signed [26:0] VAR46;
wire signed [26:0] VAR237;
wire signed [26:0] VAR14;
wire signed [26:0] VAR58;
wire signed [26:0] VAR113;
wire signed [26:0] VAR69;
wire signed [26:0] VAR80;
wire signed [26:0] VAR106;
wire signed [26:0] VAR184;
wire signed [26:0] VAR213;
wire signed [26:0] VAR118;
wire signed [26:0] VAR64;
wire signed [26:0] VAR155;
wire signed [26:0] VAR98;
wire signed [26:0] VAR204;
wire signed [26:0] VAR41;
wire signed [26:0] VAR65;
wire signed [26:0] VAR93;
wire signed [26:0] VAR122;
wire signed [26:0] VAR215;
wire signed [26:0] VAR19;
wire signed [26:0] VAR53;
wire signed [27:0] o320;
wire signed [27:0] o321;
wire signed [27:0] o322;
wire signed [27:0] o323;
wire signed [27:0] o324;
wire signed [27:0] o325;
wire signed [27:0] o326;
wire signed [27:0] o327;
wire signed [27:0] VAR258;
wire signed [27:0] VAR1;
wire signed [27:0] o3210;
wire signed [27:0] o3211;
wire signed [27:0] o3212;
wire signed [27:0] o3213;
wire signed [27:0] o3214;
wire signed [27:0] o3215;
wire signed [27:0] o3216;
wire signed [27:0] o3217;
wire signed [27:0] VAR5;
wire signed [27:0] VAR214;
wire signed [27:0] o3220;
wire signed [27:0] o3221;
wire signed [27:0] o3222;
wire signed [27:0] o3223;
wire signed [27:0] o3224;
wire signed [27:0] o3225;
wire signed [27:0] o3226;
wire signed [27:0] o3227;
wire signed [27:0] VAR103;
wire signed [27:0] VAR143;
wire signed [27:0] o3230;
wire signed [27:0] o3231;
wire signed [27:0] VAR159 ;
wire signed [27:0] VAR246 ;
wire signed [27:0] VAR153 ;
wire signed [27:0] VAR198 ;
wire signed [27:0] VAR134 ;
wire signed [27:0] VAR79 ;
wire signed [27:0] VAR8 ;
wire signed [27:0] VAR151 ;
wire signed [27:0] VAR199 ;
wire signed [27:0] VAR59 ;
wire signed [27:0] VAR102;
wire signed [27:0] VAR30;
wire signed [27:0] VAR40;
wire signed [27:0] VAR126;
wire signed [27:0] VAR259;
wire signed [27:0] VAR168;
wire signed [27:0] VAR42;
wire signed [27:0] VAR76;
wire signed [27:0] VAR43;
wire signed [27:0] VAR88;
wire signed [27:0] VAR39;
wire signed [27:0] VAR149;
wire signed [27:0] VAR189;
wire signed [27:0] VAR86;
wire signed [27:0] VAR252;
wire signed [27:0] VAR186;
wire signed [27:0] VAR61;
wire signed [27:0] VAR188;
wire signed [27:0] VAR221;
wire signed [27:0] VAR183;
wire signed [27:0] VAR135;
wire signed [27:0] VAR87;
assign VAR3=(VAR28[1]||VAR28[0]);
assign VAR226=((~VAR28[1])&VAR28[0]);
assign VAR12=(VAR226||VAR175);
assign VAR137=VAR28[1];
assign VAR175=((~VAR28[0])&VAR28[1]);
assign VAR125=(VAR28[1]&VAR28[0]);
assign VAR208=VAR193?VAR48:VAR208;
assign VAR78=VAR193?VAR245:VAR78;
assign VAR240=VAR193?VAR243:VAR240;
assign VAR233=VAR193?VAR196:VAR233;
assign VAR154=VAR193?VAR136:VAR154;
assign VAR250=VAR193?VAR249:VAR250;
assign VAR110=VAR193?VAR261:VAR110;
assign VAR81=VAR193?VAR224:VAR81;
assign VAR255=VAR193?VAR101:VAR255;
assign VAR242=VAR193?VAR148:VAR242;
assign VAR123=VAR193?VAR31:VAR123;
assign VAR77=VAR193?VAR67:VAR77;
assign VAR133=VAR193?VAR238:VAR133;
assign VAR216=VAR193?VAR173:VAR216;
assign VAR146=VAR193?VAR84:VAR146;
assign VAR257=VAR193?VAR229:VAR257;
assign VAR191=VAR193?VAR227:VAR191;
assign VAR181=VAR193?VAR62:VAR181;
assign VAR179=VAR193?VAR24:VAR179;
assign VAR256=VAR193?VAR195:VAR256;
assign VAR138=VAR193?VAR127:VAR138;
assign VAR96=VAR193?VAR128:VAR96;
assign VAR253=VAR193?VAR130:VAR253;
assign VAR74=VAR193?VAR83:VAR74;
assign VAR15=VAR193?VAR167:VAR15;
assign VAR25=VAR193?VAR47:VAR25;
assign VAR132=VAR193?VAR129:VAR132;
assign VAR94=VAR193?VAR121:VAR94;
assign VAR56=VAR193?VAR60:VAR56;
assign VAR70=VAR193?VAR234:VAR70;
assign VAR97=VAR193?VAR185:VAR97;
assign VAR144=VAR193?VAR228:VAR144;
assign VAR32 =VAR54?VAR208 :o160 ;
assign VAR27 =VAR54?VAR78 :o161 ;
assign VAR95 =VAR54?VAR240 :o162 ;
assign VAR150 =VAR54?VAR233 :o163 ;
assign VAR239 =VAR54?VAR154 :o164 ;
assign VAR190 =VAR54?VAR250 :o165 ;
assign VAR207 =VAR54?VAR110 :o166 ;
assign VAR230 =VAR54?VAR81 :o167 ;
assign VAR172 =VAR54?VAR255 :VAR141 ;
assign VAR217 =VAR54?VAR242 :VAR108 ;
assign VAR157=VAR54?VAR123:o1610;
assign VAR225=VAR54?VAR77:o1611;
assign VAR13=VAR54?VAR133:o1612;
assign VAR34=VAR54?VAR216:o1613;
assign VAR222=VAR54?VAR146:o1614;
assign VAR49=VAR54?VAR257:o1615;
assign VAR21=VAR54?VAR191:o1616;
assign VAR23=VAR54?VAR181:o1617;
assign VAR248=VAR54?VAR179:VAR165;
assign VAR206=VAR54?VAR256:VAR176;
assign VAR201=VAR54?VAR138:o1620;
assign VAR112=VAR54?VAR96:o1621;
assign VAR160=VAR54?VAR253:o1622;
assign VAR7=VAR54?VAR74:o1623;
assign VAR51=VAR54?VAR15:o1624;
assign VAR4=VAR54?VAR25:o1625;
assign VAR147=VAR54?VAR132:o1626;
assign VAR20=VAR54?VAR94:o1627;
assign VAR104=VAR54?VAR56:VAR119;
assign VAR180=VAR54?VAR70:VAR90;
assign VAR111=VAR54?VAR97:o1630;
assign VAR182=VAR54?VAR144:o1631;
assign VAR52 =VAR54?VAR174 :o320 ;
assign VAR29 =VAR54?VAR251 :o321 ;
assign VAR91 =VAR54?VAR35 :o322 ;
assign VAR37 =VAR54?VAR2 :o323 ;
assign VAR55 =VAR54?VAR82 :o324 ;
assign VAR115 =VAR54?VAR114 :o325 ;
assign VAR11 =VAR54?VAR92 :o326 ;
assign VAR220 =VAR54?VAR205 :o327 ;
assign VAR231 =VAR54?VAR235 :VAR258 ;
assign VAR33 =VAR54?VAR152 :VAR1 ;
assign VAR254=VAR54?VAR142:o3210;
assign VAR100=VAR54?VAR107:o3211;
assign VAR166=VAR54?VAR247:o3212;
assign VAR57=VAR54?VAR109:o3213;
assign VAR85=VAR54?VAR244:o3214;
assign VAR99=VAR54?VAR124:o3215;
assign VAR139=VAR54?VAR241:o3216;
assign VAR158=VAR54?VAR260:o3217;
assign VAR161=VAR54?VAR163:VAR5;
assign VAR73=VAR54?VAR71:VAR214;
assign VAR171=VAR54?VAR68:o3220;
assign VAR194=VAR54?VAR140:o3221;
assign VAR200=VAR54?VAR170:o3222;
assign VAR162=VAR54?VAR209:o3223;
assign VAR116=VAR54?VAR38:o3224;
assign VAR63=VAR54?VAR169:o3225;
assign VAR211=VAR54?VAR72:o3226;
assign VAR66=VAR54?VAR145:o3227;
assign VAR18=VAR54?VAR131:VAR103;
assign VAR105=VAR54?VAR89:VAR143;
assign VAR120=VAR54?VAR187:o3230;
assign VAR223=VAR54?VAR232:o3231;
assign VAR164 =VAR54?o160 :VAR208 ;
assign VAR262 =VAR54?o161 :VAR78 ;
assign VAR218 =VAR54?o162 :VAR240 ;
assign VAR16 =VAR54?o163 :VAR233 ;
assign VAR36 =VAR54?o164 :VAR154 ;
assign VAR9 =VAR54?o165 :VAR250 ;
assign VAR117 =VAR54?o166 :VAR110 ;
assign VAR212 =VAR54?o167 :VAR81 ;
assign VAR236 =VAR54?VAR141 :VAR255 ;
assign VAR17 =VAR54?VAR108 :VAR242 ;
assign VAR46=VAR54?o1610:VAR123;
assign VAR237=VAR54?o1611:VAR77;
assign VAR14=VAR54?o1612:VAR133;
assign VAR58=VAR54?o1613:VAR216;
assign VAR113=VAR54?o1614:VAR146;
assign VAR69=VAR54?o1615:VAR257;
assign VAR80=VAR54?o1616:VAR191;
assign VAR106=VAR54?o1617:VAR181;
assign VAR184=VAR54?VAR165:VAR179;
assign VAR213=VAR54?VAR176:VAR256;
assign VAR118=VAR54?o1620:VAR138;
assign VAR64=VAR54?o1621:VAR96;
assign VAR155=VAR54?o1622:VAR253;
assign VAR98=VAR54?o1623:VAR74;
assign VAR204=VAR54?o1624:VAR15;
assign VAR41=VAR54?o1625:VAR25;
assign VAR65=VAR54?o1626:VAR132;
assign VAR93=VAR54?o1627:VAR94;
assign VAR122=VAR54?VAR119:VAR56;
assign VAR215=VAR54?VAR90:VAR70;
assign VAR19=VAR54?o1630:VAR97;
assign VAR53=VAR54?o1631:VAR144;
assign VAR159 =VAR54?o320 :VAR174 ;
assign VAR246 =VAR54?o321 :VAR251 ;
assign VAR153 =VAR54?o322 :VAR35 ;
assign VAR198 =VAR54?o323 :VAR2 ;
assign VAR134 =VAR54?o324 :VAR82 ;
assign VAR79 =VAR54?o325 :VAR114 ;
assign VAR8 =VAR54?o326 :VAR92 ;
assign VAR151 =VAR54?o327 :VAR205 ;
assign VAR199 =VAR54?VAR258 :VAR235 ;
assign VAR59 =VAR54?VAR1 :VAR152 ;
assign VAR102=VAR54?o3210:VAR142;
assign VAR30=VAR54?o3211:VAR107;
assign VAR40=VAR54?o3212:VAR247;
assign VAR126=VAR54?o3213:VAR109;
assign VAR259=VAR54?o3214:VAR244;
assign VAR168=VAR54?o3215:VAR124;
assign VAR42=VAR54?o3216:VAR241;
assign VAR76=VAR54?o3217:VAR260;
assign VAR43=VAR54?VAR5:VAR163;
assign VAR88=VAR54?VAR214:VAR71;
assign VAR39=VAR54?o3220:VAR68;
assign VAR149=VAR54?o3221:VAR140;
assign VAR189=VAR54?o3222:VAR170;
assign VAR86=VAR54?o3223:VAR209;
assign VAR252=VAR54?o3224:VAR38;
assign VAR186=VAR54?o3225:VAR169;
assign VAR61=VAR54?o3226:VAR72;
assign VAR188=VAR54?o3227:VAR145;
assign VAR221=VAR54?VAR103:VAR131;
assign VAR183=VAR54?VAR143:VAR89;
assign VAR135=VAR54?o3230:VAR187;
assign VAR87=VAR54?o3231:VAR232;
always@(posedge clk or negedge rst)
if(!rst)
VAR6<=1'b0;
else
VAR6<=VAR193;
always@(posedge clk or negedge rst)
if(!rst)
begin
o0 <=28'b0;
o1 <=28'b0;
o2 <=28'b0;
o3 <=28'b0;
o4 <=28'b0;
o5 <=28'b0;
o6 <=28'b0;
o7 <=28'b0;
VAR50 <=28'b0;
VAR202 <=28'b0;
o10<=28'b0;
o11<=28'b0;
o12<=28'b0;
o13<=28'b0;
o14<=28'b0;
o15<=28'b0;
o16<=28'b0;
o17<=28'b0;
VAR203<=28'b0;
VAR177<=28'b0;
o20<=28'b0;
o21<=28'b0;
o22<=28'b0;
o23<=28'b0;
o24<=28'b0;
o25<=28'b0;
o26<=28'b0;
o27<=28'b0;
VAR210<=28'b0;
VAR178<=28'b0;
o30<=28'b0;
o31<=28'b0;
end
else
begin
o0 <=VAR159 ;
o1 <=VAR246 ;
o2 <=VAR153 ;
o3 <=VAR198 ;
o4 <=VAR134 ;
o5 <=VAR79 ;
o6 <=VAR8 ;
o7 <=VAR151 ;
VAR50 <=VAR199 ;
VAR202 <=VAR59 ;
o10<=VAR102;
o11<=VAR30;
o12<=VAR40;
o13<=VAR126;
o14<=VAR259;
o15<=VAR168;
o16<=VAR42;
o17<=VAR76;
VAR203<=VAR43;
VAR177<=VAR88;
o20<=VAR39;
o21<=VAR149;
o22<=VAR189;
o23<=VAR86;
o24<=VAR252;
o25<=VAR186;
o26<=VAR61;
o27<=VAR188;
VAR210<=VAR221;
VAR178<=VAR183;
o30<=VAR135;
o31<=VAR87;
end
VAR75 VAR197(
VAR3,
VAR32,
VAR27,
VAR95,
VAR150,
VAR239,
VAR190,
VAR207,
VAR230,
VAR174,
VAR251,
VAR35,
VAR2,
VAR82,
VAR114,
VAR92,
VAR205
);
VAR75 VAR10(
VAR226,
VAR172 ,
VAR217 ,
VAR157,
VAR225,
VAR13,
VAR34,
VAR222,
VAR49,
VAR235 ,
VAR152 ,
VAR142,
VAR107,
VAR247,
VAR109,
VAR244,
VAR124
);
VAR75 VAR44(
VAR12,
VAR21,
VAR23,
VAR248,
VAR206,
VAR201,
VAR112,
VAR160,
VAR7,
VAR241,
VAR260,
VAR163,
VAR71,
VAR68,
VAR140,
VAR170,
VAR209
);
VAR75 VAR26(
VAR226,
VAR51,
VAR4,
VAR147,
VAR20,
VAR104,
VAR180,
VAR111,
VAR182,
VAR38,
VAR169,
VAR72,
VAR145,
VAR131,
VAR89,
VAR187,
VAR232
);
VAR192 VAR156(
VAR137,
VAR52,
VAR29,
VAR91,
VAR37,
VAR55,
VAR115,
VAR11,
VAR220,
VAR231,
VAR33,
VAR254,
VAR100,
VAR166,
VAR57,
VAR85,
VAR99,
o160,
o161,
o162,
o163,
o164,
o165,
o166,
o167,
VAR141,
VAR108,
o1610,
o1611,
o1612,
o1613,
o1614,
o1615
);
VAR192 VAR219(
VAR175,
VAR139,
VAR158,
VAR161,
VAR73,
VAR171,
VAR194,
VAR200,
VAR162,
VAR116,
VAR63,
VAR211,
VAR66,
VAR18,
VAR105,
VAR120,
VAR223,
o1616,
o1617,
VAR165,
VAR176,
o1620,
o1621,
o1622,
o1623,
o1624,
o1625,
o1626,
o1627,
VAR119,
VAR90,
o1630,
o1631
);
VAR45 VAR22(
VAR125,
VAR164,
VAR262,
VAR218,
VAR16,
VAR36,
VAR9,
VAR117,
VAR212,
VAR236,
VAR17,
VAR46,
VAR237,
VAR14,
VAR58,
VAR113,
VAR69,
VAR80,
VAR106,
VAR184,
VAR213,
VAR118,
VAR64,
VAR155,
VAR98,
VAR204,
VAR41,
VAR65,
VAR93,
VAR122,
VAR215,
VAR19,
VAR53,
o320,
o321,
o322,
o323,
o324,
o325,
o326,
o327,
VAR258,
VAR1,
o3210,
o3211,
o3212,
o3213,
o3214,
o3215,
o3216,
o3217,
VAR5,
VAR214,
o3220,
o3221,
o3222,
o3223,
o3224,
o3225,
o3226,
o3227,
VAR103,
VAR143,
o3230,
o3231
);
endmodule
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/bashkiria-2m/src/k580wi53.v
| 4,593 |
module MODULE1(input clk,
input VAR21, input VAR41, input VAR22,
input VAR33, input VAR17, input VAR25,
output VAR14, output VAR32, output VAR40,
input[1:0] addr, input rd, input VAR9, input[7:0] VAR38, output reg[7:0] VAR31);
wire[7:0] VAR36;
wire[7:0] VAR27;
wire[7:0] VAR7;
always @
case ({VAR15,VAR6})
2'b00: VAR31 = counter[7:0];
2'b01: VAR31 = counter[15:8];
2'b10: VAR31 = VAR18[7:0];
2'b11: VAR31 = VAR18[15:8];
endcase
always @
casex ({VAR8[0],|counter[15:12],|counter[11:8],|counter[7:4],|counter[3:1]})
5'b10000: VAR23 = 16'h9998;
5'b11000: VAR23 = 16'hF998;
5'VAR34: VAR23 = 16'hFF98;
5'VAR39: VAR23 = 16'hFFF8;
default: VAR23 = 16'hFFFE;
endcase
wire[15:0] VAR37 = counter + (VAR1|~&VAR8[2:1]?VAR10:VAR23);
wire[15:0] VAR20 = {VAR37[15:1],VAR37[0]&~&VAR8[2:1]};
always @(posedge clk)
begin
VAR12 <= VAR11; VAR16 <= VAR29; VAR42 <= rd; VAR4 <= VAR9;
if (VAR19 & VAR11 & ~VAR12) begin
if (VAR26) begin
if (VAR8[2]==1'b1 && VAR20==0) begin
counter <= VAR24;
VAR1 <= VAR24[0]&~VAR35;
end else begin
counter <= VAR20;
VAR1 <= 0;
end
if (VAR20[15:1]==0 && ~VAR2) begin
casex ({VAR8[3:1],VAR20[0]})
4'b0000: {VAR35,VAR2} <= 2'b11;
4'b0010: {VAR35,VAR2} <= 2'b11;
4'VAR3: VAR35 <= 1'b1;
4'VAR13: VAR35 <= 0;
4'VAR30: VAR35 <= ~VAR35;
4'b1000: {VAR35,VAR2} <= 2'b11;
4'b1001: VAR35 <= 0;
4'b1010: {VAR35,VAR2} <= 2'b11;
4'b1011: VAR35 <= 0;
endcase
end
end else begin
counter <= VAR24; VAR26 <= 1'b1; VAR1 <= 1'b1; VAR2 <= 0;
if (VAR8[3:2]==0) VAR35 <= 0;
end
end
if (VAR16 ^ VAR29) begin
if (VAR8[2:1]!=2'b01) VAR19 <= VAR29;
end
else if (VAR29) begin VAR26 <= 0; VAR19 <= 1; end
end
if (VAR42 & ~rd) begin
if (VAR8[5:4]==2'b11) VAR6 <= ~VAR6;
if (VAR8[5:4]!=2'b11 || VAR6) VAR15 <= 0;
end else
if (VAR4 & ~VAR9) begin
if (addr) begin
if (VAR38[5:4]==0) begin
VAR18 <= counter; VAR15 <= 1;
end else begin
VAR8 <= VAR38[5:0]; VAR19 <= 0; VAR26 <= 0; VAR2 <= 1'b1;
VAR15 <= 0; VAR35 <= VAR38[3:1]!=0;
end
VAR6 <= VAR38[5:4]==2'b10;
end else begin
casex ({VAR8[5:4],VAR6})
3'VAR28: begin VAR24 <= {8'h00,VAR38}; VAR19 <= VAR29; VAR6 <= 0; end
3'VAR5: begin VAR24 <= {VAR38,8'h00}; VAR19 <= VAR29; VAR6 <= 1; end
3'b110: begin VAR24[7:0] <= VAR38; VAR19 <= 0; VAR6 <= 1; end
3'b111: begin VAR24[15:8] <= VAR38; VAR19 <= VAR29; VAR6 <= 0; end
endcase
VAR26 <= VAR8[2:1]!=0 & ~VAR2;
VAR35 <= VAR8[3:1]!=0||(VAR8[5:4]==2'b01&&VAR38==8'b1);
end
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a2111o/sky130_fd_sc_ms__a2111o.functional.v
| 1,489 |
module MODULE1 (
VAR11 ,
VAR6,
VAR7,
VAR2,
VAR10,
VAR1
);
output VAR11 ;
input VAR6;
input VAR7;
input VAR2;
input VAR10;
input VAR1;
wire VAR3 ;
wire VAR8;
and VAR9 (VAR3 , VAR6, VAR7 );
or VAR5 (VAR8, VAR10, VAR2, VAR3, VAR1);
buf VAR4 (VAR11 , VAR8 );
endmodule
|
apache-2.0
|
rqou/openfpga
|
hdl/xc2c-model/XC2CZIA.v
| 9,145 |
module MODULE1(
VAR3, VAR1, VAR6,
VAR5,
VAR2);
parameter VAR4 = 32;
|
lgpl-2.1
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nor4/sky130_fd_sc_ms__nor4_4.v
| 2,275 |
module MODULE2 (
VAR7 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR5,
VAR11,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR5;
input VAR11;
input VAR4 ;
input VAR8 ;
VAR10 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7,
VAR2,
VAR9,
VAR1,
VAR6
);
output VAR7;
input VAR2;
input VAR9;
input VAR1;
input VAR6;
supply1 VAR5;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR8 ;
VAR10 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/a22o/sky130_fd_sc_hs__a22o.behavioral.v
| 2,045 |
module MODULE1 (
VAR6 ,
VAR9 ,
VAR7 ,
VAR11 ,
VAR14 ,
VAR12,
VAR15
);
output VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR11 ;
input VAR14 ;
input VAR12;
input VAR15;
wire VAR14 VAR16 ;
wire VAR14 VAR10 ;
wire VAR5 ;
wire VAR17;
and VAR4 (VAR16 , VAR11, VAR14 );
and VAR2 (VAR10 , VAR9, VAR7 );
or VAR8 (VAR5 , VAR10, VAR16 );
VAR3 VAR13 (VAR17, VAR5, VAR12, VAR15);
buf VAR1 (VAR6 , VAR17 );
endmodule
|
apache-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_altpll_0.v
| 10,973 |
module MODULE1
(
VAR1,
VAR4,
VAR6,
VAR8) ;
input VAR1;
input VAR4;
input [0:0] VAR6;
output [0:0] VAR8;
tri0 VAR1;
tri1 VAR4;
reg [0:0] VAR9;
reg [0:0] VAR2;
reg [0:0] VAR5;
wire VAR10;
wire VAR7;
wire VAR3;
|
gpl-2.0
|
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